Motorola MPC 555 Microcontroller USER’S MANUAL

MPC555
USER’S MANUAL
Revised 1 March 1999
 Copyright 1999 MOTOROLA; All Rights Reserved
MPC555
USER’S MANUAL
Revised 1 March 1999
 Copyright 1999 MOTOROLA; All Rights Reserved
Paragraph
Number
TABLE OF CONTENTS
Page
Number
PREFACE
Section 1
OVERVIEW
1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 MPC555 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.1 RISC MCU Central Processing Unit (RCPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.2 Four-Bank Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.3 U-Bus System Interface Unit (USIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.4 Flexible Memory Protection Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.5 448 Kbytes of CDR MoneT Flash EEPROM Memory (CMF) . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.6 26 Kbytes of Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.7 General-Purpose I/O Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.8 Two Time Processor Units (TPU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.9 18-Channel Modular I/O System (MIOS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.10 Two Queued Analog-to-Digital Converter Modules (QADC) . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.11 Two CAN 2.0B Controller Modules (TouCANs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.12 Queued Serial Multi-Channel Module (QSMCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3 MPC555 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Section 2
SIGNAL DESCRIPTIONS
2.1 Packaging and Pinout Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Pin Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.1 USIU Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.1.1 ADDR[8:31]/SGPIOA[8:31]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.1.2 DATA[0:31]/SGPIOD[0:31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.1.3 IRQ[0]/SGPIOC[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.1.4 IRQ[1]/RSV_B/SGPIOC[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.1.5 IRQ[2]/CR_B/SGPIOC[2]/MTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.1.6 IRQ[3]/KR/RETRY/SGPIOC[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.1.7 IRQ[4]/AT[2]/SGPIOC[4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.1.8 IRQ[5]/SGPIOC[5]/MODCK[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.1.9 IRQ[6:7]/MODCK[2:3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.1.10 TSIZ[0:1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.1.11 RD/WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.1.12 BURST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.1.13 BDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.1.14 TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.1.15 TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
MPC555
TABLE OF CONTENTS
MOTOROLA
USER’S MANUAL
Revised 1 March 1999
iii
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2.3.1.16 TEA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.1.17 RSTCONF/TEXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.1.18 OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.1.19 BI/STS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.1.20 CS[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.1.21 WE[0:3]/AT[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.1.22 PORESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.1.23 HRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.1.24 SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.1.25 SGPIOC[6]/FRZ/PTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.1.26 SGPIOC[7]/IRQOUT/LWP[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.1.27 BG/VF[0]/LWP[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.1.28 BR/VF[1]/IWP[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.1.29 BB/VF[2]/IWP[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3.1.30 IWP[0:1]/VFLS[0:1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3.1.31 TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3.1.32 TDI/DSDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3.1.33 TCK/DSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3.1.34 TDO/DSDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.1.35 TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.1.36 XTAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.1.37 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.1.38 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.1.39 CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.1.40 EXTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.1.41 VDDSYN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.1.42 VSSSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.1.43 ENGCLK/BUCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.2 QSMCM PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.2.1 PCS0/SS/QGPIO[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.2.2 PCS(1:3)/QGPIO[1:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.2.3 MISO/QGPIO[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.2.4 MOSI/QGPIO[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.2.5 SCK/QGPIO[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.2.6 TXD[1:2]/QGPO[1:2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.2.7 RXD[1:2]/QGPI[1:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.2.8 ECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.3 MIOS PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.3.3.1 MDA[11], [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.3.3.2 MDA[12], [14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.3.3.3 MDA[15], [27:31]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.3.3.4 MPWM[0:3], [16:19] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.3.3.5 VF[0:2]/MPIO32B[0:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
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MPC555
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2.3.3.6 VFLS[0:1]/MPIO32B[3:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.3.3.7 MPIO32B[5:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.4 TPU_A/TPU_B PADS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.4.1 TPUCH[0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.4.2 T2CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.5 QADC_A/QADC_B PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.5.1 ETRIG[1:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.5.2 AN[0]/ANW/PQB[0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.5.3 AN[1]/ANX/PQB[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.3.5.4 AN[2]/ANY/PQB[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.3.5.5 AN[3]/ANZ/PQB[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.3.5.6 AN[48:51]/PQB[4:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.3.5.7 AN[52:54]/MA[0:2]/PQA[0:2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.5.8 AN[55:59]/PQA[3:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.5.9 VRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.5.10 VRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.5.11 VDDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.5.12 VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.6 TOUCAN_A/TOUCAN_B PADS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.6.1 CNTX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.3.6.2 CNRX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.3.7 CMF PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.3.7.1 EPEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.3.7.2 VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.3.7.3 VDDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.3.7.4 VSSF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.3.8 GLOBAL POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.3.8.1 VDDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.3.8.2 VDDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.3.8.3 VDDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.3.8.4 VSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.3.8.5 KAPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.3.8.6 VDDSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.3.8.7 VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.4 Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.4.1 Pin Functionality out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.4.2 Pad Module Configuration Register (PDMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.4.3 Pin State During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.4.4 Power-On Reset and Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.4.5 Pull-Up and Pull-Down Enable and Disable for 5-V Only Pins . . . . . . . . . . . . . . . . . . . . 2-31
2.4.6 Pull-Up and Pull-Down Enable and Disable for 3-V / 5-V Multiplexed Pins . . . . . . . . . . 2-31
2.4.6.1 PRDS Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.4.6.2 Encoded 3-V / 5-V Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
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2.4.6.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.4.7 Special Pull Resistor Disable Control (SPRDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.4.8 Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.5 Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.5.1 Pad Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.5.2 Three-Volt Output Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
2.5.2.1 Type A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
2.5.2.2 Type B Interface (Clock Pad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
2.5.3 Three-Volt Input Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
2.5.3.1 Type C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
2.5.3.2 Type CH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.5.3.3 Type CNH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.5.3.4 Type D Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.5.4 Three-Volt Input/Output Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
2.5.4.1 Type E Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
2.5.4.2 Type EOH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
2.5.4.3 Type F Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
2.5.4.4 Type G Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2.5.5 Five-Volt Input/Output Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2.5.5.1 Type H Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2.5.5.2 Type I Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
2.5.5.3 Type IH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
2.5.5.4 Type J Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
2.5.5.5 Type JD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
2.5.6 Type K Interface (EPEE Pad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
2.5.7 Analog Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52
2.5.7.1 Type L Interface (QADC Port A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52
2.5.7.2 Type M Interface (QADC Port B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
2.5.7.3 Type N Interface (ETRIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
2.5.8 Pads with Fast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
2.5.8.1 Type O Interface (QSMCM Pads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
2.5.8.2 Type P Interface (TPU and MIOS Pads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
2.5.9 5V Input, 5V Output Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56
2.5.9.1 5V Output (Type Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56
2.5.9.2 Type R Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
2.5.9.3 5V Output for Clock Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
2.6 Pad Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
2.7 Pin Names and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
Section 3
CENTRAL PROCESSING UNIT
3.1 RCPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 RCPU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
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3.3 Instruction Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4 Independent Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.1 Branch Processing Unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.4.2 Integer Unit (IU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.4.3 Load/Store Unit (LSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4.4 Floating-Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5 Levels of the PowerPC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.6 RCPU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.7 PowerPC UISA Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7.1 General-Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.7.2 Floating-Point Registers (FPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.7.3 Floating-Point Status and Control Register (FPSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.7.4 Condition Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.7.4.1 Condition Register CR0 Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.7.4.2 Condition Register CR1 Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.7.4.3 Condition Register CRn Field — Compare Instruction . . . . . . . . . . . . . . . . . . . . . . 3-17
3.7.5 Integer Exception Register (XER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.7.6 Link Register (LR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.7.7 Count Register (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.8 PowerPC VEA Register Set — Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.9 PowerPC OEA Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.9.1 Machine State Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.9.2 DAE/Source Instruction Service Register (DSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.9.3 Data Address Register (DAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.9.4 Time Base Facility (TB) — OEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.9.5 Decrementer Register (DEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.9.6 Machine Status Save/Restore Register 0 (SRR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.9.7 Machine Status Save/Restore Register 1 (SRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.9.8 General SPRs (SPRG0–SPRG3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.9.9 Processor Version Register (PVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.9.10 Implementation-Specific SPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.9.10.1 EIE, EID, and NRI Special-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.9.10.2 Floating-Point Exception Cause Register (FPECR) . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.9.10.3 Additional Implementation-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.10 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.10.1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.10.2 Recommended Simplified Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.10.3 Calculating Effective Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.11 Exception Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
3.11.1 Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
3.11.2 Ordered Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
3.11.3 Unordered Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
3.11.4 Precise Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
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USER’S MANUAL
Revised 1 March 1999
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3.11.5 Exception Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3.12 Instruction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
3.13 PowerPC User Instruction Set Architecture (UISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.13.1 Computation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.13.2 Reserved Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.13.3 Classes of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.13.4 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.13.5 The Branch Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.13.6 Instruction Fetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.13.7 Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.13.7.1 Invalid Branch Instruction Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.13.7.2 Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.13.8 The Fixed-Point Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.13.8.1 Fixed-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.13.9 Floating-Point Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.13.9.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.13.9.2 Optional instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.13.10 Load/Store Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.13.10.1 Fixed-Point Load With Update and Store With Update Instructions. . . . . . . . . . 3-41
3.13.10.2 Fixed-Point Load and Store Multiple Instructions . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.13.10.3 Fixed-Point Load String Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.13.10.4 Storage Synchronization Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.13.10.5 Floating-Point Load and Store With Update Instructions . . . . . . . . . . . . . . . . . . 3-41
3.13.10.6 Floating-Point Load Single Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.13.10.7 Floating-Point Store Single Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.13.10.8 Optional Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.13.10.9 Little-Endian Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.14 PowerPC Virtual Environment Architecture (VEA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.14.1 Atomic Update Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.14.2 Effect of Operand Placement on Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.14.3 Storage Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.14.4 Instruction Synchronize (isync) Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.14.4.1 Enforce In-Order Execution of I/O (eieio) Instruction . . . . . . . . . . . . . . . . . . . . . . 3-43
3.14.5 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.15 POWERPC Operating Environment Architecture (OEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.15.1 Branch Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.15.1.1 Machine State Register (MSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.15.1.2 Branch Processors Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.15.2 Fixed-Point Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
3.15.2.1 Special Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
3.15.3 Storage Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
3.15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
3.15.4.1 System Reset Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
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3.15.4.2 Machine Check Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
3.15.4.3 Data Storage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
3.15.4.4 Instruction Storage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
3.15.4.5 Alignment Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3.15.4.6 Floating-Point Enabled Exception Type Program Interrupt . . . . . . . . . . . . . . . . . 3-47
3.15.4.7 Illegal Instruction Type Program Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3.15.4.8 Privileged Instruction Type Program interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3.15.4.9 Floating-Point Unavailable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3.15.4.10 Trace Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3.15.4.11 Floating-Point Assist Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
3.15.4.12 Implementation-Dependent Software Emulation Interrupt . . . . . . . . . . . . . . . . . 3-49
3.15.4.13 Implementation-Specific Instruction Storage Protection Error Interrupt . . . . . . . 3-50
3.15.4.14 Implementation-Specific Data Storage Protection Error Interrupt . . . . . . . . . . . 3-51
3.15.4.15 Implementation-Specific Debug Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
3.15.4.16 Partially Executed Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
3.15.5 Timer Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
3.15.6 Optional Facilities and Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
Section 4
BURST BUFFER
4.1 Burst Buffer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Burst Buffer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.3 Little-Endian Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.4 Modes Of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.4.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.4.2 Slave Operation.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4.4 Debug Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4.5 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4.6 Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.4.7 Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.5 Exception Table Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.5.1 Exception Table Relocation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.6 Burst Buffer Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.6.1 Region Base Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.6.2 Region Attribute Registers MI_RA[0:3] Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.6.3 Global Region Attribute Register Description (MI_GRA) . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.6.4 BBC Module Configuration Register (BBCMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Section 5
UNIFIED SYSTEM INTERFACE UNIT
5.1 Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 SIU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 USIU Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
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5.4 USIU PowerPC Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Section 6
SYSTEM CONFIGURATION AND PROTECTION
6.1 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.1.1 USIU Pins Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.1.2 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.1.3 Arbitration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.2 External Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.2.1 Operation of External Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.2 Address Decoding for External Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.3 USIU General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.4 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.4.1 SIU Interrupt Sources Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.5 Hardware Bus Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.6 MPC555 Decrementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.7 MPC555 Time Base (TB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.8 Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.9 Periodic Interrupt Timer (PIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.10 Software Watchdog Timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.11 Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.12 Low Power Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.13 System Configuration and Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.13.1 System Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.13.1.1 SIU Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.13.1.2 Internal Memory Map Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.13.1.3 External Master Control Register (EMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.13.2 SIU Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.13.2.1 SIPEND Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.13.2.2 SIU Interrupt Mask Register (SIMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
6.13.2.3 SIU Interrupt Edge Level Register (SIEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.13.2.4 SIU Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.13.3 System Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
6.13.3.1 System Protection Control Register (SYPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
6.13.3.2 Software Service Register (SWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
6.13.3.3 Transfer Error Status Register (TESR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
6.13.4 System Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
6.13.4.1 Decrementer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
6.13.4.2 Time Base SPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
6.13.4.3 Time Base Reference Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6.13.4.4 Time Base Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6.13.4.5 Real-Time Clock Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
6.13.4.6 Real-Time Clock Register (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
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6.13.4.7 Real-Time Clock Alarm Register (RTCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
6.13.4.8 Periodic Interrupt Status and Control Register (PISCR). . . . . . . . . . . . . . . . . . . . 6-33
6.13.4.9 Periodic Interrupt Timer Count Register (PITC) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
6.13.4.10 Periodic Interrupt Timer Register (PITR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
6.13.5 General-Purpose I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.13.5.1 SGPIO Data Register 1 (SGPIODT1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.13.5.2 SGPIO Data Register 2 (SGPIODT2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.13.5.3 SGPIO Control Register (SGPIOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
Section 7
RESET
7.1 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.2 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.1.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.1.4 Loss of Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.1.5 On-Chip Clock Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.6 Software Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.7 Checkstop Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.8 Debug Port Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.9 Debug Port Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.10 JTAG Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2 Reset Actions Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.3 Data Coherency During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.4 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.5 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.5.1 Hard Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.5.2 Hard Reset Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.5.3 Soft Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Section 8
CLOCKS AND POWER CONTROL
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 System Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3.1 Frequency Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3.2 Skew Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3.3 Pre-Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3.4 PLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3.5 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.4 System Clock During PLL Loss of Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.5 Low-Power Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.6 MPC555 Internal Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.6.1 General System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
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8.6.2 CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.6.3 Engineering Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.7 Clock Source Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.8.1 Entering a Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.8.2 Power Mode Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.8.3 Exiting from Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.8.3.1 Exiting from Normal-Low Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.8.3.2 Exiting from Doze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.8.3.3 Exiting from Deep-Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.8.3.4 Exiting from Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.8.3.5 Low-Power Modes Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.9 Basic Power Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.9.1 Clock Unit Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.9.2 Chip Power Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.9.2.1 VDDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.9.2.2 VDDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.9.2.3 VDDSYN, VSSSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.9.2.4 KAPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.9.2.5 VDDA, VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.9.2.6 VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.9.2.7 VDDF, VSSF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.9.2.8 VDDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.9.2.9 VDDSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.9.2.10 VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.9.3 Keep Alive Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
8.9.3.1 Keep Alive Power Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
8.9.3.2 Keep Alive Power Registers Lock Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
8.10 VDDSRAM Supply Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
8.11 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
8.12 Clocks Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
8.12.1 System Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
8.12.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) . . . . . . . . . . . . . . . . . . . . . . 8-31
8.12.3 Change of Lock Interrupt Register (COLIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
8.12.4 VDDSRAM Control Register (VSRMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
Section 9
EXTERNAL BUS INTERFACE
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 Bus Transfer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.3 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.4 Bus Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.5 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
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9.5.1 Basic Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.5.2 Single Beat Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.5.2.1 Single Beat Read Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.5.2.2 Single Beat Write Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.5.2.3 Single Beat Flow with Small Port Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.5.3 Burst Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.5.4 Burst Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.5.5 Alignment and Packaging of Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9.5.6 Arbitration Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9.5.6.1 Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9.5.6.2 Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9.5.6.3 Bus Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
9.5.6.4 Internal Bus Arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
9.5.7 Address Transfer Phase Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9.5.7.1 Transfer Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9.5.7.2 Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9.5.7.3 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9.5.7.4 Burst Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
9.5.7.5 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9.5.7.6 Address Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9.5.7.7 Burst Data in Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38
9.5.8 Termination Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38
9.5.8.1 Transfer Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38
9.5.8.2 Burst Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39
9.5.8.3 Transfer Error Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39
9.5.8.4 Termination Signals Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39
9.5.9 Storage Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
9.5.10 Bus Exception Control Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43
9.5.10.1 Retrying a Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43
9.5.10.2 Termination Signals Protocol Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47
9.5.11 Bus Operation in External Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47
9.5.12 Contention Resolution on External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-52
9.5.13 Show Cycle Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54
Section 10
MEMORY CONTROLLER
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 Memory Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.1 Associated Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.2 Port Size Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.3 Write-Protect Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.4 Address and Address Space Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.5 Burst Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
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10.3 Chip-Select Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3.1 Memory Devices Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.2 Peripheral Devices Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.3.3 Relaxed Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.3.4 Extended Hold Time on Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.3.5 Summary of GPCM Timing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.4 Global (Boot) Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.5 Write and Byte Enable Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.6 Dual Mapping of the Internal Flash EEPROM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.7 Memory Controller External Master Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.8 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.8.1 General Memory Controller Programming Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.8.2 Memory Controller Status Registers (MSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28
10.8.3 Memory Controller Base Registers (BR0 – BR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28
10.8.4 Memory Controller Option Registers (OR0 – OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10.8.5 Dual Mapping Base Register (DMBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.8.6 Dual-Mapping Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
Section 11
L-BUS TO U-BUS INTERFACE (L2U)
11.1 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 DMPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.3 L2U Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.4 Modes Of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.4.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.4.2 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.4.3 Factory Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.4.4 Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.5 Data Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.5.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.5.2 Associated Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.5.3 L-bus Memory Access Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.6 Reservation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.6.1 The Reservation Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.6.2 L2U Reservation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.6.3 Reserved Location (Bus) and Possible Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.7 L-Bus Show Cycle Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.7.1 Programming Show Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.7.2 Performance Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.7.3 Show Cycle Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.7.4 L-Bus Write Show Cycle Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.7.5 L-Bus Read Show Cycle Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.7.6 Show Cycle Support Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
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11.8 L2U Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.8.1 U-bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.8.2 Transaction Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.8.3 L2U Module Configuration Register (L2U_MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.8.4 Region Base Address Registers (L2U_RBAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.8.5 Region Attribute Registers (L2U_RAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.8.6 Global Region Attribute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Section 12
U-BUS TO IMB3 BUS INTERFACE (UIMB)
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 UIMB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3 Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.4 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4.1 Interrupt Sources and Levels on IMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4.2 IMB Interrupt Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.3 ILBS Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.4 Interrupt Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.5 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.5.1 UIMB Module Configuration Register (UMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.5.2 Test control register (UTSTCREG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.5.3 Pending Interrupt Request Register (UIPEND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Section 13
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3 QADC64 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3.1 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3.1.1 Port A Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3.1.2 Port A Digital Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3.2 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.2.1 Port B Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.2.2 Port B Digital Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.3 External Trigger Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.4 Multiplexed Address Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.5 Multiplexed Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.3.6 Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.3.7 Dedicated Analog Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.3.8 External Digital Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.3.9 Digital Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.4 QADC64 Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.5 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.5.1 Low-Power Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
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13.5.2 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.5.3 Supervisor/Unrestricted Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.6 General-Purpose I/O Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.6.1 Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.6.2 Port Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.7 External Multiplexing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.8 Analog Input Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.9 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.9.1 Conversion Cycle Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.9.1.1 Amplifier Bypass Mode Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.9.2 Front-End Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.9.3 Digital-to-Analog Converter Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.9.4 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.9.5 Successive Approximation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.10 Digital Control Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.10.1 Queue Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.10.2 Queue Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.10.3.1 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.10.3.2 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.10.3.3 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.10.3.4 Continuous-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
13.10.4 QADC64 Clock (QCLK) Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24
13.10.5 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
13.11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
13.11.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
13.11.2 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
13.11.3 Interrupt Levels and Time Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
13.12 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
13.12.1 QADC64 Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32
13.12.2 QADC64 Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32
13.12.3 QADC64 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32
13.12.4 Port A/B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33
13.12.5 Port Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34
13.12.6 QADC64 Control Register 0 (QACR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34
13.12.7 QADC64 Control Register 1 (QACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35
13.12.8 QADC64 Control Register 2 (QACR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-38
13.12.9 QADC64 Status Register 0 (QASR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39
13.12.10 QADC64 Status Register 1 (QASR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-41
13.12.11 Conversion Command Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-42
13.12.12 Result Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-48
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Section 14
QUEUED SERIAL MULTI-CHANNEL MODULE
14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.5 QSMCM Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.5.1 Low-Power Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.5.2 Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.5.3 Access Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.5.4 QSMCM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.5.5 QSMCM Configuration Register (QSMCMMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.5.6 QSMCM Test Register (QTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.5.7 QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL) . . . . . . . . . . . . . . . . . . . . . . 14-8
14.6 QSMCM Pin Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.6.1 Port QS Data Register (PORTQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
14.6.2 PORTQS Pin Assignment Register (PQSPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
14.6.3 PORTQS Data Direction Register (DDRQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.7 Queued Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.7.1 QSPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.7.1.1 QSPI Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.7.1.2 QSPI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.7.1.3 QSPI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
14.7.1.4 QSPI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
14.7.1.5 QSPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20
14.7.2 QSPI RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
14.7.2.1 Receive RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.7.2.2 Transmit RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.7.2.3 Command RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22
14.7.3 QSPI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23
14.7.4 QSPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24
14.7.4.1 Enabling, Disabling, and Halting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
14.7.4.2 QSPI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
14.7.4.3 QSPI Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
14.7.5 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
14.7.5.1 Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34
14.7.5.2 Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34
14.7.5.3 Delay Before Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
14.7.5.4 Delay After Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35
14.7.5.5 Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
14.7.5.6 Peripheral Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
14.7.5.7 Master Wraparound Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37
14.7.6 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37
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Revised 1 March 1999
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14.7.6.1 Description of Slave Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
14.7.7 Slave Wraparound Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
14.7.8 Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-41
14.8 Serial Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-41
14.8.1 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-44
14.8.2 SCI Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45
14.8.3 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45
14.8.4 SCI Status Register (SCxSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-47
14.8.5 SCI Data Register (SCxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-49
14.8.6 SCI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50
14.8.7 SCI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50
14.8.7.1 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50
14.8.7.2 Serial Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
14.8.7.3 Baud Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51
14.8.7.4 Parity Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-53
14.8.7.5 Transmitter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-53
14.8.7.6 Receiver Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-55
14.8.7.7 Idle-Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-56
14.8.7.8 Receiver Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-57
14.8.7.9 Internal Loop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-58
14.9 SCI Queue Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-58
14.9.1 Queue Operation of SCI1 for Transmit and Receive . . . . . . . . . . . . . . . . . . . . . . . . . 14-58
14.9.2 Queued SCI1 Status and Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-58
14.9.2.1 QSCI1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-58
14.9.2.2 QSCI1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-60
14.9.3 QSCI1 Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-60
14.9.4 QSCI1 Additional Transmit Operation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-61
14.9.5 QSCI1 Transmit Flow Chart Implementing the Queue . . . . . . . . . . . . . . . . . . . . . . . . 14-63
14.9.6 Example QSCI1 Transmit for 17 Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-65
14.9.7 Example SCI Transmit for 25 Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-66
14.9.8 QSCI1 Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-67
14.9.9 QSCI1 Additional Receive Operation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-67
14.9.10 QSCI1 Receive Flow Chart Implementing The Queue . . . . . . . . . . . . . . . . . . . . . . . 14-70
14.9.11 QSCI1 Receive Queue Software Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-71
14.9.12 Example QSCI1 Receive Operation of 17 Data Frames . . . . . . . . . . . . . . . . . . . . . 14-72
Section 15
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
15.1 MIOS1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2 Submodule Numbering, Naming and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.3 MIOS1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.5 MIOS1 Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
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15.5.1 Read/Write and Control Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.5.2 Request Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.5.3 Counter Bus Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.6 MIOS1 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.7 MIOS1 I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.8 MIOS Bus Interface Submodule (MBISM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.8.1 MIOS Bus Interface (MBISM) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.8.1.1 MIOS1 Test and Pin Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.8.1.2 MIOS1 Vector Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.8.1.3 MIOS1 Module and Version Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.8.1.4 MIOS1 Module Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.8.2 MBISM Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.8.2.1 MIOS1 Interrupt Level Register 0 (MIOS1LVL0) . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.8.2.2 MIOS1 Interrupt Level Register 1 (MIOS1LVL1) . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.8.3 Interrupt Control Section (ICS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.9 MIOS Counter Prescaler Submodule (MCPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.9.1 MIOS Counter Prescaler Submodule (MCPSM) Registers . . . . . . . . . . . . . . . . . . . . 15-12
15.9.1.1 MCPSM Status/Control Register (MCPSMCSCR) . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.10 MIOS Modulus Counter Submodule (MMCSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.10.1 MIOS Modulus Counter Submodule (MMCSM) Registers . . . . . . . . . . . . . . . . . . . . 15-15
15.10.1.1 MMCSM Up-Counter Register (MMCSMCNT). . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.10.1.2 MMCSM Modulus Latch Register (MMCSMML) . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.10.1.3 MMCSM Status/Control Register (Duplicated) . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.10.1.4 MMCSM Status/Control Register (MMCSMSCR) . . . . . . . . . . . . . . . . . . . . . . 15-17
15.11 MIOS Double Action Submodule (MDASM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
15.11.1 MIOS Double Action Submodule (MDASM) Registers . . . . . . . . . . . . . . . . . . . . . . . 15-19
15.11.1.1 MDASM Data A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
15.11.1.2 MDASM Data B Register (MDASMBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
15.11.1.3 MDASM Status/Control Register (Duplicated) . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
15.11.1.4 MDASM Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
15.12 MIOS Pulse Width Modulation Submodule (MPWMSM) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27
15.12.1 MIOS Pulse Width Modulation Submodule (MPWMSM) Registers . . . . . . . . . . . . . 15-28
15.12.1.1 MPWMSM Period Register (MPWMSMPERR) . . . . . . . . . . . . . . . . . . . . . . . . 15-29
15.12.1.2 MPWMSM Pulse Width Register (MPWMSMPULR) . . . . . . . . . . . . . . . . . . . . 15-29
15.12.1.3 MPWMSM Counter Register (MPWMSMCNTR) . . . . . . . . . . . . . . . . . . . . . . . 15-30
15.12.1.4 MPWMSM Status/Control Register(MPWMSMCR) . . . . . . . . . . . . . . . . . . . . . 15-30
15.13 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-32
15.13.1 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM) Registers. . . . . . . . . . . . . . . . 15-32
15.13.1.1 MPIOSM Data Register (MPIOSMDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-32
15.13.1.2 MPIOSM Data Direction Register (MPIOSMDDR) . . . . . . . . . . . . . . . . . . . . . . 15-33
15.14 MIOS1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33
15.14.1 MIOS Interrupt Request Submodule (MIRSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34
15.14.2 MIOS Interrupt Request Submodule 0 (MIRSM0) Registers . . . . . . . . . . . . . . . . . . 15-35
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15.14.2.1 MIRSM0 Interrupt Status Register (MIOS1SR0) . . . . . . . . . . . . . . . . . . . . . . . 15-36
15.14.2.2 MIRSM0 Interrupt Enable Register (MIOS1ER0) . . . . . . . . . . . . . . . . . . . . . . . 15-37
15.14.2.3 MIRSM0 Request Pending Register (MIOS1RPR0) . . . . . . . . . . . . . . . . . . . . 15-37
15.14.3 MIOS Interrupt Request Submodule 1 (MIRSM1) Registers . . . . . . . . . . . . . . . . . . 15-38
15.14.3.1 MIRSM1 Interrupt Status Register (MIOS1SR1) . . . . . . . . . . . . . . . . . . . . . . . 15-38
15.14.3.2 MIRSM1 Interrupt Enable Register (MIOS1ER1) . . . . . . . . . . . . . . . . . . . . . . . 15-39
15.14.3.3 MIRSM1 Request Pending Register (MIOS1RPR1) . . . . . . . . . . . . . . . . . . . . 15-40
15.15 MIOS1 Function Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40
15.15.1 MIOS1 Input Double Edge Pulse Width Measurement . . . . . . . . . . . . . . . . . . . . . . 15-40
15.15.2 MIOS1 Input Double Edge Period Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-42
15.15.3 MIOS1 Double Edge Single Output Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . 15-43
15.15.4 MIOS1 Output Pulse Width Modulation With MDASM . . . . . . . . . . . . . . . . . . . . . . . 15-44
15.15.5 MIOS1 Input Pulse Accumulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-45
15.16 MIOS1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-45
Section 16
CAN 2.0B CONTROLLER MODULE
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.3 TouCAN Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3.1 TX/RX Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3.1.1 Common Fields for Extended and Standard Format Frames. . . . . . . . . . . . . . . . 16-4
16.3.1.2 Fields for Extended Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.1.3 Fields for Standard Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.1.4 Serial Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.1.5 Message Buffer Activation/Deactivation Mechanism . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.1.6 Message Buffer Lock/Release/Busy Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.2 Receive Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.3.3 Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
16.3.3.1 Configuring the TouCAN Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.3.4 Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.3.5 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.4 TouCAN Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.4.1 TouCAN Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.4.2 TouCAN Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.4.3 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
16.4.3.1 Transmit Message Buffer Deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.4.3.2 Reception of Transmitted Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.4.4 Receive Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.4.4.1 Receive Message Buffer Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.4.4.2 Locking and Releasing Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.4.5 Remote Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.4.6 Overload Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
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16.5 Special Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.5.1 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.5.2 Low-Power Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.5.3 Auto Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.7 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19
16.7.1 TouCAN Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.7.2 TouCAN Test Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24
16.7.3 TouCAN Interrupt Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24
16.7.4 Control Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
16.7.5 Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26
16.7.6 Prescaler Divide Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27
16.7.7 Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28
16.7.8 Free Running Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28
16.7.9 Receive Global Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29
16.7.10 Receive Buffer 14 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29
16.7.11 Receive Buffer 15 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29
16.7.12 Error and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30
16.7.13 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32
16.7.14 Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32
16.7.15 Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33
Section 17
TIME PROCESSOR UNIT 3
17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.2 TPU3 Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.1 Time Bases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.2 Timer Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.3 Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.4 Microengine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.5 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.6 Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3 TPU Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3.1 Event Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3.2 Channel Orthogonality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3.3 Interchannel Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.3.4 Programmable Channel Service Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.3.5 Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.3.6 Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.3.7 TPU3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.3.8 Prescaler Control for TCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.3.9 Prescaler Control for TCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
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17.4.1 TPU Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.4.2 TPU3 Test Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.4.3 Development Support Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.4.4 Development Support Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
17.4.5 TPU3 Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
17.4.6 Channel Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
17.4.7 Channel Function Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
17.4.8 Host Sequence Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.4.9 Host Service Request Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
17.4.10 Channel Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.4.11 Channel Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.12 Link Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.13 Service Grant Latch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.14 Decoded Channel Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.15 TPU3 Module Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
17.4.16 TPU Module Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
17.4.17 TPU3 Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
17.4.18 TPU3 Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
17.5 Time Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
Section 18
DUAL-PORT TPU RAM (DPTRAM)
18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.2 DPTRAM Configuration and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.3.1 DPTRAM Module Configuration Register (DPTMCR) . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3.2 DPTRAM Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.3.3 Ram Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.3.4 MISR High (MISRH) and MISR Low (MISRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.5 MISC Counter (MISCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
18.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
18.4.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
18.4.2 Standby Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
18.4.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
18.4.4 Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.4.5 Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.4.6 TPU3 Emulation Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
18.5 Multiple Input Signature Calculator (MISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
Section 19
CDR MoneT FLASH EEPROM
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.1 MPC555 CMF Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.1.2 Glossary of Terms for the CMF EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
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19.2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.2.1 CMF EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.2.1.1 CMF EEPROM Configuration Register (CMFMCR) . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.2.1.2 CMF EEPROM Test Register (CMFTST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.2.1.3 CMF EEPROM High Voltage Control Register (CMFCTL). . . . . . . . . . . . . . . . . . 19-8
19.2.2 CMF EEPROM Array Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10
19.2.2.1 Read Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
19.2.2.2 Program Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12
19.2.2.3 Array Configuration for CMF Module A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13
19.2.2.4 Array Configuration for CMF Module B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
19.3 Shadow Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
19.3.1 Address Range of Shadow Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.3.2 Reset Configuration Word (CMFCFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.4 Array Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
19.5 Programming the CMF Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.5.1 Program Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.5.2 Program Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21
19.5.3 Over-Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21
19.6 Erasing CMF Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22
19.6.1 Erase Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22
19.6.2 Erase Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24
19.6.3 Erasing Shadow Information Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.7 Voltage Control for Programming and Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.7.1 Pulse Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.7.2 Pulse Width Timing Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.7.3 System Clock Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26
19.7.4 Exponential Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27
19.7.5 Linear Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27
19.7.6 A Technique to Determine SCLKR, CLKPE, and CLKPM . . . . . . . . . . . . . . . . . . . . . 19-27
19.7.7 Starting and Ending a Program or Erase Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.7.8 Controlling the Program/Erase Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.8 Censored and Non-Censored Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29
19.8.1 Uncensored Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29
19.8.2 Censored Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29
19.8.3 Device Modes and Censorship Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
19.8.4 Setting and Clearing Censor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32
19.8.5 Switching the CMF EEPROM Censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33
19.9 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34
19.9.1 EPEE Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34
19.9.2 FLASH Program/Erase Voltage Conditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35
19.10 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37
19.10.1 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37
19.10.2 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37
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19.10.3 Emulation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-38
19.11 Disabling the CMF Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-38
Section 20
STATIC RANDOM ACCESS MEMORY (SRAM)
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
20.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
20.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
20.3.1 SRAM Module Configuration Register (SRAMMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
20.3.2 SRAM Test Register (SRAMTST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Section 21
DEVELOPMENT SUPPORT
21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.2 Program Flow Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.2.1 Program Trace Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.2.1.1 Instruction Queue Status Pins — VF [0:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.2.1.2 History Buffer Flushes Status Pins— VFLS [0..1] . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.2.1.3 Queue Flush Information Special Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.2.2 Program Trace when in Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.2.3 Sequential Instructions Marked as Indirect Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.2.4 The External Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.2.4.1 Synchronizing the Trace Window to the CPU Internal Events . . . . . . . . . . . . . . . 21-5
21.2.4.2 Detecting the Trace Window Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.2.4.3 Detecting the Assertion/Negation of VSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.2.4.4 Detecting the Trace Window End Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.2.4.5 Compress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.2.5 Instruction Fetch Show Cycle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.3 Watchpoints and Breakpoints Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.3.1 Internal Watchpoints and Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.3.1.1 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
21.3.1.2 Byte and Half-Word Working Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
21.3.1.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14
21.3.1.4 Context Dependent Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15
21.3.1.5 Ignore First Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15
21.3.1.6 Generating Six Compare Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16
21.3.2 Instruction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16
21.3.2.1 Load/Store Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17
21.3.3 Watchpoint Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.3.3.1 Trap Enable Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.4 Development System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.4.1 Debug Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24
21.4.1.1 Debug Mode Enable vs. Debug Mode Disable. . . . . . . . . . . . . . . . . . . . . . . . . . 21-26
21.4.1.2 Entering Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26
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21.4.1.3 The Check Stop State and Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29
21.4.1.4 Saving Machine State upon Entering Debug Mode . . . . . . . . . . . . . . . . . . . . . . 21-29
21.4.1.5 Running in Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30
21.4.1.6 Exiting Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30
21.5 Development Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31
21.5.1 Development Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31
21.5.2 Development Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31
21.5.3 Development Serial Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31
21.5.4 Development Serial Data Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32
21.5.5 Freeze Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32
21.5.5.1 SGPIO6/FRZ/PTR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32
21.5.5.2 IWP[0:1]/VFLS[0:1] Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32
21.5.5.3 VFLS[0:1]_MPIO32B[3:4] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32
21.5.6 Development Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32
21.5.6.1 Development Port Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33
21.5.6.2 Trap Enable Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33
21.5.6.3 Development Port Registers Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33
21.5.6.4 Development Port Serial Communications — Clock Mode Selection . . . . . . . . 21-34
21.5.6.5 Development Port Serial Communications — Trap Enable Mode . . . . . . . . . . . 21-38
21.5.6.6 Serial Data into Development Port — Trap Enable Mode . . . . . . . . . . . . . . . . . 21-38
21.5.6.7 Serial Data Out of Development Port — Trap Enable Mode . . . . . . . . . . . . . . . 21-39
21.5.6.8 Development Port Serial Communications — Debug Mode. . . . . . . . . . . . . . . . 21-39
21.5.6.9 Serial Data Into Development Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-40
21.5.6.10 Serial Data Out of Development Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-41
21.5.6.11 Fast Download Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-41
21.6 Software Monitor Debugger Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43
21.6.1 Freeze Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43
21.7 Development Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43
21.7.1 Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44
21.7.2 Comparator A–D Value Registers (CMPA–CMPD) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-45
21.7.3 Comparator E–F Value Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46
21.7.4 Breakpoint Address Register (BAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46
21.7.5 Comparator G–H Value Registers (CMPG–CMPH) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47
21.7.6 I-Bus Support Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47
21.7.7 L-Bus Support Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-49
21.7.8 L-Bus Support Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-50
21.7.9 Breakpoint Counter A Value and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-52
21.7.10 Breakpoint Counter B Value and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 21-53
21.7.11 Exception Cause Register (ECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-53
21.7.12 Debug Enable Register (DER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-55
21.7.13 Development Port Data Register (DPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-57
MPC555
TABLE OF CONTENTS
MOTOROLA
USER’S MANUAL
Revised 1 March 1999
xxv
Page
Number
Paragraph
Number
Section 22
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
22.1 JTAG Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.2 JTAG Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.3 Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.4 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.5 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.5.1 EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.5.2 SAMPLE/PRELOAD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.5.3 BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.5.4 CLAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.5.5 HI-Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.6 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.7 Low-Power Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.8 Non-IEEE 1149.1-1990 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.9 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
Appendix A
MPC555 INTERNAL MEMORY MAP
Appendix B
REGISTER GENERAL INDEX
Appendix C
REGISTER DIAGRAM INDEX
Appendix D
TPU ROM FUNCTIONS
D.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
D.2 Programmable Time Accumulator (PTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
D.3 Queued Output Match TPU Function (QOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5
D.4 Table Stepper Motor (TSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
D.5 Frequency Measurement (FQM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-10
D.6 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-12
D.7 New Input Capture/Transition Counter (NITC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-15
D.8 Multiphase Motor Commutation (COMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-17
D.9 Hall Effect Decode (HALLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-19
D.10 Multichannel Pulse-Width Modulation (MCPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-21
D.11 Fast Quadrature Decode TPU Function (FQD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-28
D.12 Period/Pulse-Width Accumulator (PPWA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-31
D.13 Output Compare (OC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-33
D.14 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-35
D.15 Discrete Input/Output (DIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-37
D.16 Synchronized Pulse-Width Modulation (SPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-39
D.17 Serial Input/Output Port (SIOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-42
D.17.1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-43
D.17.1.1 CHAN_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44
D.17.1.2 BIT_D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44
MOTOROLA
TABLE OF CONTENTS
MPC555
xxvi
Revised 1 March 1999
USER’S MANUAL
Page
Number
Paragraph
Number
D.17.1.3 HALF_PERIOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.1.4 BIT_COUNT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.1.5 XFER_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.1.6 SIOP_DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.2 Host CPU Initialization of the SIOP Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.3 SIOP Function Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.3.1 XFER_SIZE Greater than 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.3.2 Data Positioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.3.3 Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-44
D-44
D-44
D-44
D-45
D-45
D-46
D-46
D-46
Appendix E
CLOCK AND BOARD GUIDELINES
E.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.2 MPC555 Power distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.3 PLL and Crystal Oscillator External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.3.1 Crystal Oscillator External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.3.2 KAPWR filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.3.3 PLL External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.3.4 PLL Off-Chip Capacitor CXFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.4 Clock Oscillator and PLL External Components Layout Requirements. . . . . . . . . . . . . . . . . . .
E.4.1 Traces and Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.4.2 Grounding/Guarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E-1
E-2
E-4
E-4
E-5
E-6
E-7
E-7
E-7
E-8
INDEX
Online publishing by JABIS, http://www.jabis.com
MPC555
TABLE OF CONTENTS
MOTOROLA
USER’S MANUAL
Revised 1 March 1999
xxvii
MOTOROLA
TABLE OF CONTENTS
MPC555
xxviii
Revised 1 March 1999
USER’S MANUAL
Paragraph
Number
LIST OF FIGURES
Page
Number
1-1
1-2
1-3
MPC555 Block Diagram ................................................................................. 1-2
MPC555 Memory Map .................................................................................... 1-6
MPC555 Internal Memory Map ....................................................................... 1-7
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
MPC555 Case Dimensions and Packaging .................................................... 2-2
MPC555 Pinout Data ...................................................................................... 2-3
Type A Interface ........................................................................................... 2-40
Type B Interface ........................................................................................... 2-41
Type C Interface ........................................................................................... 2-41
Type CH Interface ........................................................................................ 2-42
Type CNH Interface ...................................................................................... 2-42
Type D Interface ........................................................................................... 2-43
Type E Interface ........................................................................................... 2-44
3-V Type EOH Interface ............................................................................... 2-45
Type F Interface ........................................................................................... 2-45
Type G Interface ........................................................................................... 2-46
Type H Interface ........................................................................................... 2-47
Type I Interface ............................................................................................. 2-48
Type IH Interface .......................................................................................... 2-49
Type J Interface ............................................................................................ 2-50
Type JD Interface ......................................................................................... 2-51
EPEE Pad (Type K) ...................................................................................... 2-52
Type L Interface ............................................................................................ 2-53
Type M Interface ........................................................................................... 2-53
Type N Interface ........................................................................................... 2-54
Type O Interface ........................................................................................... 2-55
Type P Interface ........................................................................................... 2-56
Type Q Interface ........................................................................................... 2-57
Type R Interface ........................................................................................... 2-57
Type S Interface ........................................................................................... 2-58
3-1
3-2
3-3
3-4
RCPU Block Diagram ..................................................................................... 3-2
Sequencer Data Path ..................................................................................... 3-4
RCPU Programming Model ............................................................................ 3-8
Basic Instruction Pipeline ............................................................................. 3-37
4-1
4-2
Burst Buffer Block Diagram ............................................................................ 4-2
Exception Table Entries Mapping ................................................................... 4-7
5-1
MPC555 USIU Block Diagram ........................................................................ 5-2
6-1
6-2
System Configuration and Protection Logic ................................................... 6-3
MPC555 Memory Map .................................................................................... 6-5
MPC555
USER’S MANUAL
LIST OF FIGURES
Revised 1 March 1999
MOTOROLA
xxix
Page
Number
Paragraph
Number
6-3
6-4
6-5
6-6
6-7
6-8
SGPIO Cell ..................................................................................................... 6-9
MPC555 Interrupt Structure .......................................................................... 6-10
MPC555 Interrupt Configuration ................................................................... 6-12
RTC Block Diagram ...................................................................................... 6-15
PIT Block Diagram ........................................................................................ 6-16
SWT Block Diagram ..................................................................................... 6-18
7-1
7-2
7-5
Reset Configuration Basic Scheme ................................................................ 7-7
Reset Configuration Sampling Scheme
For “Short” PORESET Assertion, Limp Mode Disabled .............................. 7-8
Reset Configuration Timing for
“Short” PORESET Assertion, Limp Mode Enabled ..................................... 7-9
Reset Configuration Timing for
“Long” PORESET Assertion, Limp Mode Disabled ..................................... 7-9
Reset Configuration Sampling Timing Requirements ................................... 7-10
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
Clock Unit Block Diagram ............................................................................... 8-2
Main System Oscillator (OSCM) ..................................................................... 8-3
System PLL Block Diagram ............................................................................ 8-5
MPC555 Clocks .............................................................................................. 8-7
General System Clocks Select ..................................................................... 8-10
Divided System Clocks Timing Diagram ...................................................... 8-11
Clocks Timing For DFNH = 1 (or DFNL = 0) ................................................ 8-12
Clock Source Flow Chart .............................................................................. 8-14
MPC555 Low-Power Modes Flow Diagram .................................................. 8-19
Basic Power Supply Configuration ............................................................... 8-22
External Power Supply Scheme ................................................................... 8-23
Keep Alive Register Key State Diagram ....................................................... 8-25
No Standby, No KAPWR, All System Power On/Off .................................... 8-26
Standby and KAPWR, Other Power On/Off ................................................. 8-27
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
Input Sample Window ..................................................................................... 9-2
MPC555 Bus Signals ...................................................................................... 9-3
Basic Transfer Protocol .................................................................................. 9-8
Basic Flow Diagram of a Single Beat Read Cycle .......................................... 9-9
Single Beat Read Cycle–Basic Timing–Zero Wait States ............................ 9-10
Single Beat Read Cycle–Basic Timing–One Wait State ............................... 9-11
Basic Flow Diagram of a Single Beat Write Cycle ........................................ 9-12
Single Beat Basic Write Cycle Timing, Zero Wait States ............................. 9-13
Single Beat Basic Write Cycle Timing, One Wait State ................................ 9-14
Single Beat 32-Bit Data
Write Cycle Timing, 16 Bit-Port Size ......................................................... 9-15
Basic Flow Diagram Of A Burst Read Cycle ................................................ 9-18
Burst-Read Cycle–32-Bit Port Size–Zero Wait State ................................... 9-19
Burst-Read Cycle–32-Bit Port Size–One Wait State .................................... 9-20
Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats ................. 9-21
7-3
7-4
9-11
9-12
9-13
9-14
MOTOROLA
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LIST OF FIGURES
Revised 1 March 1999
MPC555
USER’S MANUAL
Page
Number
Paragraph
Number
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
9-38
9-39
9-40
9-41
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
Burst-Read Cycle, 16-Bit Port Size .............................................................. 9-22
Basic Flow Diagram of a Burst Write Cycle .................................................. 9-23
Burst-Write Cycle, 32-Bit Port Size, Zero Wait States .................................. 9-24
Burst-Inhibit Cycle, 32-Bit Port Size (Emulated Burst) ................................. 9-25
Non-Wrap Burst with Three Beats ................................................................ 9-26
Non-Wrap Burst with One Data Beat ............................................................ 9-27
Internal Operand Representation ................................................................. 9-28
Interface To Different Port Size Devices ...................................................... 9-29
Bus Arbitration Flowchart ............................................................................. 9-31
Masters Signals Basic Connection ............................................................... 9-32
Bus Arbitration Timing Diagram .................................................................... 9-33
Internal Bus Arbitration State Machine ......................................................... 9-35
Termination Signals Protocol Basic Connection ........................................... 9-39
Termination Signals Protocol Timing Diagram ............................................. 9-40
Reservation On Local Bus ............................................................................ 9-41
Reservation On Multilevel Bus Hierarchy ..................................................... 9-42
Retry Transfer Timing–Internal Arbiter ......................................................... 9-44
Retry Transfer Timing–External Arbiter ........................................................ 9-45
Retry On Burst Cycle .................................................................................... 9-46
Basic Flow of an External Master Read Access ........................................... 9-48
Basic Flow of an External Master Write Access ........................................... 9-49
Peripheral Mode: External Master Reads
from MPC555 — Two Wait States ............................................................ 9-50
Peripheral Mode: External Master Writes to MPC555;
Two Wait States ........................................................................................ 9-51
Flow of Retry of External Master Read Access ............................................ 9-53
Retry of External Master Access (Internal Arbiter) ....................................... 9-54
Instruction Show Cycle Transaction ............................................................. 9-55
Data Show Cycle Transaction ...................................................................... 9-56
Memory Controller Function within the USIU ............................................... 10-1
Memory Controller Block Diagram ................................................................ 10-2
MPC555 Simple System Configuration ........................................................ 10-3
Bank Base Address and Match Structure ..................................................... 10-4
MPC555 GPCM–Memory Devices Interface ................................................ 10-7
Memory Devices Interface Basic Timing
(ACS = 00,TRLX = 0) ................................................................................ 10-8
Peripheral Devices Interface ........................................................................ 10-9
Peripheral Devices Basic Timing
(ACS = 11,TRLX = 0) ................................................................................ 10-9
Relaxed Timing–Read Access
(ACS = 11, SCY = 1, TRLX = 1) ............................................................. 10-11
Relaxed Timing–Write Access
(ACS = 10, SCY = 0, CSNT = 0, TRLX = 1) ........................................... 10-12
Relaxed Timing–Write Access
(ACS = 11, SCY = 0, CSNT = 1, TRLX = 1) ........................................... 10-13
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Paragraph
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10-12
10-19
Relaxed Timing–Write Access
(ACS = 00, SCY = 0, CSNT = 1, TRLX = 1 ............................................. 10-14
Consecutive Accesses (Write After Read, EHTR = 0) ................................ 10-15
Consecutive Accesses (Write After Read, EHTR = 1) ................................ 10-16
Consecutive Accesses
(Read After Read From Different Banks, EHTR = 1) .............................. 10-17
Consecutive Accesses
(Read After Read From Same Bank, EHTR = 1) .................................... 10-18
Aliasing Phenomena Illustration ................................................................. 10-23
Synchronous External Master
Configuration For GPCM–Handled Memory Devices ............................. 10-25
Synchronous External Master Basic Access (GPCM controlled) ............... 10-26
11-1
11-2
11-3
L2U Bus Interface Block Diagram ................................................................ 11-2
DMP Basic Functional Diagram .................................................................... 11-4
Region Base Address Example .................................................................... 11-6
12-1
12-2
12-3
12-4
12-5
12-6
UIMB Interface Module Block Diagram ........................................................ 12-2
IMB Clock – Full-Speed IMB Bus ................................................................. 12-2
IMB Clock – Half-Speed IMB Bus ................................................................. 12-3
Interrupt Synchronizer Signal Flow ............................................................... 12-4
Time-Multiplexing Protocol for IRQ pins ....................................................... 12-5
Interrupt Synchronizer Block diagram .......................................................... 12-6
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
QADC64 Block Diagram ............................................................................... 13-1
QADC64 Input and Output Signals ............................................................... 13-3
Example of External Multiplexing ............................................................... 13-10
QADC64 Module Block Diagram ................................................................ 13-11
Conversion Timing ...................................................................................... 13-12
Bypass Mode Conversion Timing ............................................................... 13-13
QADC64 Queue Operation with Pause ...................................................... 13-15
QADC64 Clock Subsystem Functions ........................................................ 13-25
QADC64 Clock Programmability Examples ............................................... 13-27
QADC64 Interrupt Flow Diagram ................................................................ 13-29
Interrupt levels on IRQ with ILBS ............................................................... 13-30
QADC64 Conversion Queue Operation ..................................................... 13-43
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
QSMCM Block Diagram ............................................................................... 14-2
QSMCM Interrupt Levels .............................................................................. 14-6
QSPI Interrupt Generation ............................................................................ 14-7
QSPI Block Diagram ................................................................................... 14-14
QSPI RAM .................................................................................................. 14-22
Flowchart of QSPI Initialization Operation .................................................. 14-27
Flowchart of QSPI Master Operation (Part 1) ............................................. 14-28
Flowchart of QSPI Master Operation (Part 2) ............................................. 14-29
Flowchart of QSPI Master Operation (Part 3) ............................................. 14-30
10-13
10-14
10-15
10-16
10-17
10-18
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Paragraph
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14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
14-21
14-22
Flowchart of QSPI Slave Operation (Part 1) ............................................... 14-31
Flowchart of QSPI Slave Operation (Part 2) ............................................... 14-32
SCI Transmitter Block Diagram .................................................................. 14-42
SCI Receiver Block Diagram ...................................................................... 14-43
Queue Transmitter Block Enhancements ................................................... 14-61
Queue Transmit Flow ................................................................................. 14-63
Queue Transmit Software Flow .................................................................. 14-64
Queue Transmit Example for 17 Data Bytes .............................................. 14-65
Queue Transmit Example for 25 Data Frames ........................................... 14-66
Queue Receiver Block Enhancements ....................................................... 14-67
Queue Receive Flow .................................................................................. 14-70
Queue Receive Software Flow ................................................................... 14-71
Queue Receive Example for 17 Data Bytes ............................................... 14-72
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
MIOS1 Block Diagram .................................................................................. 15-5
MIOS1 Memory Map .................................................................................... 15-7
MCPSM Block Diagram .............................................................................. 15-12
MMCSM Block Diagram ............................................................................. 15-15
MDASM Block Diagram .............................................................................. 15-19
MPWMSM Block Diagram .......................................................................... 15-27
MPIOSM One-Bit Block Diagram ............................................................... 15-32
MIOS Interrupt Structure ............................................................................ 15-34
MIOS1 Example: Double Capture Pulse Width Measurement ................... 15-41
MIOS1 Example: Double Capture Period Measurement ............................ 15-42
MIOS1 Example: Double Edge Output Compare ....................................... 15-43
MIOS1 Example: Pulse Width Modulation Output ...................................... 15-45
16-1
16-2
16-3
16-4
16-5
16-6
TouCAN Block Diagram ............................................................................... 16-1
Typical CAN Network ................................................................................... 16-3
Extended ID Message Buffer Structure ........................................................ 16-4
Standard ID Message Buffer Structure ......................................................... 16-4
Interrupt levels on IRQ with ILBS ............................................................... 16-19
TouCAN Message Buffer Memory Map ...................................................... 16-22
17-1
17-2
17-3
17-4
TPU3 Block Diagram .................................................................................... 17-1
TPU3 Interrupt Levels ................................................................................... 17-5
TCR1 Prescaler Control ............................................................................... 17-7
TCR2 Prescaler Control ............................................................................... 17-8
18-1
18-2
DPTRAM Configuration ................................................................................ 18-2
DPTRAM Memory Map ................................................................................ 18-3
19-1
19-2
19-3
19-4
CMF Array and Control Register Addressing ............................................... 19-4
Shadow Information .................................................................................... 19-15
Program State Diagram .............................................................................. 19-19
Erase State Diagram .................................................................................. 19-23
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19-5
19-6
19-7
19-8
19-9
19-10
Pulse Status Timing .................................................................................... 19-25
Censorship States and Transitions ............................................................. 19-33
EPEE Digital Filter and Latch ..................................................................... 19-34
CMF_EPEE Timing Diagram ...................................................................... 19-35
VPP and VDDL Power Switching ............................................................... 19-36
VPP Conditioning Circuit ............................................................................ 19-37
20-1
20-2
SRAM Block Diagram ................................................................................... 21-1
SRAM Memory Map ..................................................................................... 21-2
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
Watchpoints and Breakpoint Support in the CPU ....................................... 21-10
Partially Supported Watchpoint/Breakpoint Example ................................. 21-15
Instruction Support General Structure ........................................................ 21-17
Load/Store Support General Structure ....................................................... 21-20
Functional Diagram of MPC555 Debug Mode Support .............................. 21-23
Debug Mode Logic ..................................................................................... 21-25
Debug Mode Reset Configuration .............................................................. 21-27
Asynchronous Clock Serial Communications ............................................. 21-35
Synchronous Self Clock Serial Communication ......................................... 21-36
Enabling Clock Mode Following Reset ....................................................... 21-37
Download Procedure Code Example ......................................................... 21-42
Slow Download Procedure Loop ................................................................ 21-42
Fast Download Procedure Loop ................................................................. 21-42
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
JTAG Pins .................................................................................................... 22-1
Test Logic Block Diagram ............................................................................. 22-2
TAP Controller State Machine ...................................................................... 22-4
Bypass Register ........................................................................................... 22-6
Output Pin Cell (O.pin) ................................................................................. 22-8
Observe-Only Input Pin Cell (I.Obs) ............................................................. 22-8
Output Control Cell (IO.CTL) ........................................................................ 22-9
General Arrangement of Bidirectional Pin Cells ........................................... 22-9
D-1
D-2
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-10
D-11
D-12
D-13
TPU3 Memory Map ........................................................................................D-1
PTA Parameters .............................................................................................D-4
QOM Parameters ...........................................................................................D-6
TSM Parameters — Master Mode ..................................................................D-8
TSM Parameters — Slave Mode ....................................................................D-9
FQM Parameters ..........................................................................................D-11
UART Transmitter Parameters .....................................................................D-13
UART Receiver Parameters .........................................................................D-14
NITC Parameters .........................................................................................D-16
COMM Parameters, Part 1 of 2 ....................................................................D-18
COMM Parameters, Part 2 of 2 ....................................................................D-19
HALLD Parameters ......................................................................................D-20
MCPWM Parameters — Master Mode .........................................................D-22
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D-14
D-15
D-16
D-17
D-18
D-19
D-20
D-21
D-22
D-23
D-24
D-25
D-26
D-27
D-28
D-29
MCPWM Parameters — Slave Edge-Aligned Mode ....................................D-23
MCPWM Parameters — Slave Ch A Non-Inverted Center-Aligned Mode ...D-24
MCPWM Parameters — Slave Ch B Non-Inverted Center-Aligned Mode ...D-25
MCPWM Parameters — Slave Ch A Inverted Center-Aligned Mode ...........D-26
MCPWM Parameters — Slave Ch B Inverted Center-Aligned Mode ...........D-27
FQD Parameters — Primary Channel ..........................................................D-29
FQD Parameters — Secondary Channel .....................................................D-30
PPWA Parameters .......................................................................................D-32
OC Parameters ............................................................................................D-34
PWM Parameters .........................................................................................D-36
DIO Parameters ...........................................................................................D-38
SPWM Parameters, Part 1 of 2 ....................................................................D-40
SPWM Parameters, Part 2 of 2 ....................................................................D-41
Two Possible SIOP Configurations ..............................................................D-42
SIOP Parameters .........................................................................................D-43
SIOP Function Data Transition Example ......................................................D-47
E-1
E-2
E-3
E-4
E-5
E-6
E-7
E-8
MPC555 Power Distribution Diagram — 3 V .................................................. E-2
MPC555 Power Distribution Diagram — 5 V, and Analog ............................. E-3
Crystal Oscillator Circuit ................................................................................. E-4
RC Filter Example .......................................................................................... E-5
Bypass Capacitors Example (Alternative) ...................................................... E-6
RC Filter Example .......................................................................................... E-6
LC Filter Example (Alternative) ...................................................................... E-7
PLL Off-Chip Capacitor Example ................................................................... E-7
MPC555
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LIST OF FIGURES
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USER’S MANUAL
Paragraph
Number
2-1
2-2
2-3
2-4
2-5
2-6
LIST OF TABLES
Page
Number
MPC555 Pin Functions for 272-Pin PBGA ............................................................ 2-4
Pin Functionality Table .......................................................................................... 2-7
PDMCR Bit Settings ........................................................................................... 2-30
Pin Reset State.................................................................................................... 2-33
Pad Groups Based on 3-V / 5-V Select ............................................................... 2-58
Pin Names and Abbreviations ............................................................................. 2-59
3-1 RCPU Execution Units........................................................................................... 3-5
3-2 Supervisor-Level SPRs.......................................................................................... 3-9
3-3 Development Support SPRs................................................................................ 3-11
3-4 FPSCR Bit Categories ......................................................................................... 3-13
3-5 FPSCR Bit Settings ............................................................................................. 3-14
3-6 Floating-Point Result Flags in FPSCR................................................................. 3-15
3-7 Bit Settings for CR0 Field of CR .......................................................................... 3-16
3-8 Bit Settings for CR1 Field of CR .......................................................................... 3-17
3-9 CRn Field Bit Settings for Compare Instructions ................................................. 3-17
3-10 Integer Exception Register Bit Definitions ......................................................... 3-18
3-11 Time Base Field Definitions (Read Only)........................................................... 3-19
3-12 Machine State Register Bit Settings .................................................................. 3-21
3-13 Floating-Point Exception Mode Bits................................................................... 3-22
3-14 Time Base Field Definitions (Write Only)........................................................... 3-23
3-15 Uses of SPRG0–SPRG3 ................................................................................... 3-25
3-16 Processor Version Register Bit Settings............................................................ 3-26
3-17 EIE, EID, AND NRI Registers ............................................................................ 3-26
3-18 FPECR Bit Settings ........................................................................................... 3-27
3-19 Instruction Set Summary ................................................................................... 3-29
3-20 MPC555 Exception Classes .............................................................................. 3-34
3-21 Exception Vector Offset Table .......................................................................... 3-36
3-22 Instruction Latency and Blockage...................................................................... 3-38
3-23 Floating-Point Exception Mode Encoding.......................................................... 3-43
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
Exception Addresses Mapping by BBC ................................................................. 4-6
Region Base Address Registers RBA[0:1] ............................................................ 4-8
Region Attributes Registers ................................................................................... 4-8
BBC Module Configuration Register...................................................................... 4-8
MI_RBA[0:3] Bit Settings ...................................................................................... 4-9
MI_RA[0:3] Bit Settings....................................................................................... 4-10
MI_GRA Bit Settings........................................................................................... 4-11
BBCMCR Bit Settings ......................................................................................... 4-12
5-1 USIU Address Map ................................................................................................ 5-3
5-2 USIU Special-Purpose Registers........................................................................... 5-6
5-3 PowerPC Address Range...................................................................................... 5-6
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Paragraph
Number
6-1 USIU Pins Multiplexing Control.............................................................................. 6-4
6-2 SGPIO Configuration ............................................................................................. 6-8
6-3 Priority of Interrupt Sources ................................................................................. 6-13
6-4 Decrementer Time-Out Periods........................................................................... 6-14
6-5 SIUMCR Bit Settings .......................................................................................... 6-20
6-6 Debug Pins Configuration.................................................................................... 6-21
6-7 Debug Port Pins Configuration ............................................................................ 6-21
6-8 General Pins Configuration.................................................................................. 6-21
6-9 Single-Chip Select Field Pin Configuration.......................................................... 6-21
6-10 Multi-Level Reservation Control Pin Configuration ............................................ 6-22
6-11 IMMR Bit Settings ............................................................................................. 6-23
6-12 EMCR Bit Settings ............................................................................................ 6-24
6-13 SYPCR Bit Settings .......................................................................................... 6-27
6-14 SWSR Bit Settings............................................................................................ 6-28
6-15 TESR Bit Settings ............................................................................................. 6-29
6-16 TBSCR Bit Settings .......................................................................................... 6-31
6-17 RTCSCR Bit Settings........................................................................................ 6-32
6-18 PISCR Bit Settings............................................................................................ 6-33
6-19 PITC Bit Settings .............................................................................................. 6-34
6-20 PIT Bit Settings ................................................................................................. 6-34
6-21 SGPIODT1 Bit Settings .................................................................................... 6-35
6-22 SGPIODT2 Bit Settings .................................................................................... 6-36
6-23 SGPIOCR Bit Settings ...................................................................................... 6-36
6-24 Data Direction Control ....................................................................................... 6-37
7-1
7-2
7-3
7-4
7-5
Reset Action Taken For Each Reset Cause .......................................................... 7-4
Reset Configuration Word and Data Corruption/Coherency.................................. 7-4
Reset Status Register Bit Settings......................................................................... 7-5
Reset Configuration Options.................................................................................. 7-7
Hard Reset Configuration Word Bit Settings ...................................................... 7-11
8-1 Reset Clocks Source Configuration....................................................................... 8-9
8-2 TMBCLK Divisions................................................................................................. 8-9
8-3 Status of Clock Source ........................................................................................ 8-15
8-4 Power Mode Control Bit Settings........................................................................ 8-16
8-5 Power Mode Descriptions................................................................................... 8-16
8-6 Power Mode Wake-Up Operation....................................................................... 8-17
8-7 Clock Unit Power Supply ..................................................................................... 8-20
8-8 KAPWR Registers and Key Registers ................................................................. 8-24
8-9 SCCR Bit Settings .............................................................................................. 8-29
8-10 PLPRCR Bit Settings ........................................................................................ 8-32
8-11 COLIR Bit Settings............................................................................................ 8-34
8-12 VSRMCR Bit Settings ....................................................................................... 8-34
9-1 MPC555 SIU Signals ............................................................................................. 9-4
9-2 Data Bus Requirements For Read Cycles........................................................... 9-30
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Number
9-3
9-4
9-5
9-6
9-7
9-8
9-9
Data Bus Contents for Write Cycles .................................................................... 9-30
Priority Between Internal and External Masters over External Bus ..................... 9-34
Burst Length and Order ....................................................................................... 9-36
BURST/TSIZE Encoding ..................................................................................... 9-37
Address Type Pins............................................................................................... 9-37
Address Types Definition..................................................................................... 9-38
Termination Signals Protocol............................................................................... 9-47
10-1 Timing Attributes Summary ............................................................................... 10-6
10-2 Programming Rules for Strobes Timing........................................................... 10-19
10-3 Boot Bank Fields Values After Hard Reset...................................................... 10-20
10-4 Write Enable/Byte Enable Signals Function .................................................... 10-21
10-5 Memory Controller Address Map ..................................................................... 10-27
10-6 MSTAT Bit Settings ........................................................................................ 10-28
10-7 BR0 – BR3 Bit Settings................................................................................... 10-29
10-8 OR0 – OR3 Bit Settings.................................................................................. 10-31
10-9 DMBR Bit Settings .......................................................................................... 10-33
10-10 DMOR Bit Settings......................................................................................... 10-34
11-1 DMPU Registers ................................................................................................ 11-6
11-2 Reservation Snoop Support............................................................................... 11-9
11-3 L2U_MCR LSHOW Modes ................................................................................ 11-9
11-4 L2U Show Cycle Support Chart....................................................................... 11-12
11-5 L2U (PPC) Register Decode............................................................................ 11-12
11-6 Hex Address For SPR Cycles.......................................................................... 11-13
11-7 L2U_MCR Bit Settings.................................................................................... 11-14
11-8 L2U_RBAx Bit Settings................................................................................... 11-14
11-9 L2U_RAx Bit Settings ..................................................................................... 11-15
11-10 L2U_GRA Bit Settings .................................................................................. 11-16
12-1
12-2
12-3
12-4
12-5
12-6
12-7
STOP and HSPEED Bit Functionality................................................................ 12-2
Bus Cycles and System Clock Cycles ............................................................... 12-3
ILBS Signal functionality .................................................................................... 12-5
IRQMUX Functionality ....................................................................................... 12-5
UIMB Interface Register Map ............................................................................ 12-7
UMCR Bit Settings............................................................................................ 12-8
UIPEND Bit Settings .......................................................................................... 12-9
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
Multiplexed Analog Input Channels ................................................................... 13-5
Analog Input Channels .................................................................................... 13-11
Queue 1 Priority Assertion............................................................................... 13-15
QADC64 Clock Programmability ..................................................................... 13-27
QADC64 Status Flags and Interrupt Sources.................................................. 13-29
QADC64 Address Map .................................................................................... 13-31
QADC64MCR Bit Settings .............................................................................. 13-32
QADC64INT Bit Settings ................................................................................ 13-33
MPC555
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Paragraph
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13-9 PORTQA, PORTQB Bit Settings .................................................................... 13-33
13-10 DDRQA Bit Settings...................................................................................... 13-34
13-11 QACR0 Bit Settings ...................................................................................... 13-35
13-12 QACR1 Bit Settings ...................................................................................... 13-36
13-13 Queue 1 Operating Modes ............................................................................ 13-37
13-14 QACR2 Bit Settings ...................................................................................... 13-38
13-15 Queue 2 Operating Modes ............................................................................ 13-39
13-16 QASR0 Bit Settings ...................................................................................... 13-40
13-17 Queue Status................................................................................................. 13-41
13-18 QASR0 Bit Settings ...................................................................................... 13-42
13-19 CCW Bit Settings .......................................................................................... 13-46
13-20 Non-Multiplexed Channel Assignments and Pin Designations...................... 13-47
13-21 Multiplexed Channel Assignments and Pin Designations.............................. 13-47
14-1 QSMCM Register Map....................................................................................... 14-3
14-2 QSMCM Global Registers ................................................................................. 14-5
14-3 Interrupt Levels .................................................................................................. 14-6
14-4 QSMCMMCR Bit Settings.................................................................................. 14-8
14-5 QDSCI_IL Bit Settings ....................................................................................... 14-8
14-6 QSPI_IL Bit Settings .......................................................................................... 14-9
14-7 QSMCM Pin Control Registers .......................................................................... 14-9
14-8 Effect of DDRQS on QSPI Pin Function .......................................................... 14-10
14-9 QSMCM Pin Functions .................................................................................... 14-11
14-10 PQSPAR Bit Settings..................................................................................... 14-12
14-11 DDRQS Bit Settings....................................................................................... 14-13
14-12 QSPI Register Map........................................................................................ 14-16
14-13 SPCR0 Bit Settings....................................................................................... 14-17
14-14 Bits Per Transfer............................................................................................ 14-17
14-15 SPCR1 Bit Settings....................................................................................... 14-18
14-16 SPCR2 Bit Settings....................................................................................... 14-19
14-17 SPCR3 Bit Settings....................................................................................... 14-20
14-18 SPSR Bit Settings......................................................................................... 14-21
14-19 Command RAM Bit Settings ......................................................................... 14-23
14-20 QSPI Pin Functions ....................................................................................... 14-24
14-21 Example SCK Frequencies with a 40-MHz System Clock............................. 14-35
14-22 SCI Registers................................................................................................. 14-44
14-23 SCCxR0 Bit Settings..................................................................................... 14-45
14-24 SCCxR1 Bit Settings..................................................................................... 14-46
14-25 SCxSR Bit Settings....................................................................................... 14-48
14-26 SCxSR Bit Settings....................................................................................... 14-50
14-27 SCI Pin Functions .......................................................................................... 14-50
14-28 Serial Frame Formats .................................................................................... 14-51
14-29 SCI Baud Clock Sources ............................................................................... 14-52
14-30 Examples of SCIx Baud Rates ...................................................................... 14-52
14-31 Examples of SCIx Baud Rates from an 3.6864 MHz external clock.............. 14-53
14-32 Effect of Parity Checking on Data Size.......................................................... 14-53
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Paragraph
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14-33 QSCI1CR Bit Settings................................................................................... 14-59
14-34 QSCI1SR Bit Settings................................................................................... 14-60
15-1 MIOS1 I/O Ports ................................................................................................ 15-8
15-2 MBISM Address Map......................................................................................... 15-8
15-3 MIOS1TPCR Bit Settings................................................................................... 15-9
15-4 MIOS1VNR Bit Settings..................................................................................... 15-9
15-5 MIOS1MCR Bit Settings .................................................................................. 15-10
15-6 MBISM Interrupt Registers Address Map ........................................................ 15-10
15-7 MIOS1LVL0 Bit Settings .................................................................................. 15-11
15-8 MIOS1LVL1 Bit Settings .................................................................................. 15-11
15-9 MCPSM Address Map ..................................................................................... 15-13
15-10 MCPSMSCR Bit Settings............................................................................... 15-13
15-11 MMCSM Address Map................................................................................... 15-15
15-12 MMCSMCNT Bit Settings .............................................................................. 15-16
15-13 MMCSMML Bit Settings................................................................................. 15-16
15-14 MMCSMSCR Bit Settings .............................................................................. 15-18
15-15 MMCSMCR CP and MPWMSMSCR CP Values........................................... 15-18
15-16 MDASM Address Map ................................................................................... 15-21
15-17 MDASMSCR Bit Settings............................................................................... 15-25
15-18 MDASM Mode Selects................................................................................... 15-26
15-19 MPWMSM Address Map ............................................................................... 15-28
15-20 MPWMSMPERR Bit Settings ........................................................................ 15-29
15-21 MPWMSMPULR Bit Settings......................................................................... 15-29
15-22 MPWMSMCNTR Bit Settings ........................................................................ 15-30
15-23 MPWMSMSCR Bit Settings........................................................................... 15-31
15-24 PWMSM Output Pin Polarity Selection.......................................................... 15-31
15-25 MPIOSM Address Map .................................................................................. 15-32
15-26 MPIOSMDR Bit Settings................................................................................ 15-33
15-27 MPIOSMDDR Bit Settings ............................................................................. 15-33
15-28 MIRSM0 Address Map................................................................................... 15-36
15-29 MIOS1SR0 Bit Settings ................................................................................. 15-36
15-30 MIOS1ER0 Bit Settings ................................................................................. 15-37
15-31 MIOS1RPR0 Bit Settings............................................................................... 15-38
15-32 MIRSM1 Address Map................................................................................... 15-38
15-33 MIOS1SR1 Bit Settings ................................................................................. 15-39
15-34 MIOS1ER1 Bit Settings ................................................................................. 15-39
15-35 MIOS1RPR1 Bit Settings............................................................................... 15-40
15-36 MIOS1 Configuration ..................................................................................... 15-46
16-1
16-2
16-3
16-4
16-5
16-6
Common Extended/Standard Format Frames................................................... 16-4
Message Buffer Codes for Receive Buffers....................................................... 16-5
Message Buffer Codes for Transmit Buffers...................................................... 16-5
Extended Format Frames .................................................................................. 16-5
Standard Format Frames................................................................................... 16-6
Receive Mask Register Bit Values..................................................................... 16-7
MPC555
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LIST OF TABLES
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Paragraph
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16-7 Mask Examples for Normal/Extended Messages .............................................. 16-8
16-8 Example System Clock, CAN Bit Rate and S-Clock Frequencies ..................... 16-9
16-9 Interrupt Levels ................................................................................................ 16-19
16-10 TouCAN Register Map................................................................................... 16-21
16-11 TCNMCR Bit Settings ................................................................................... 16-23
16-12 CANICR Bit Settings..................................................................................... 16-25
16-13 CANCTRL0 Bit Settings................................................................................ 16-25
16-14 RX MODE[1:0] Configuration......................................................................... 16-26
16-15 Transmit Pin Configuration ............................................................................ 16-26
16-16 CANCTRL1 Bit Settings................................................................................. 16-27
16-17 PRESDIV Bit Settings................................................................................... 16-27
16-18 CANCTRL2 Bit Settings................................................................................ 16-28
16-19 TIMER Bit Settings ....................................................................................... 16-28
16-20 RXGMSKHI, RXGMSKLO Bit Settings ......................................................... 16-29
16-21 ESTAT Bit Settings ....................................................................................... 16-30
16-22 Transmit Bit Error Status ............................................................................... 16-31
16-23 Fault Confinement State Encoding ................................................................ 16-31
16-24 IMASK Bit Settings ....................................................................................... 16-32
16-25 IFLAG Bit Settings ........................................................................................ 16-32
16-26 RXECTR, TXECTR Bit Settings ................................................................... 16-33
17-1 Enhanced TCR1 Prescaler Divide Values ........................................................ 17-6
17-2 TCR1 Prescaler Values ..................................................................................... 17-6
17-3 TCR2 Counter Clock Source ............................................................................. 17-7
17-4 TCR2 Prescaler Control..................................................................................... 17-8
17-5 TPU3 Register Map ........................................................................................... 17-9
17-6 TPUMCR Bit Settings ..................................................................................... 17-11
17-7 DSCR Bit Settings .......................................................................................... 17-13
17-8 DSSR Bit Settings........................................................................................... 17-14
17-9 TICR Bit Settings ............................................................................................ 17-15
17-10 CIER Bit Settings .......................................................................................... 17-15
17-11 CFSRx Bit Settings ....................................................................................... 17-16
17-12 HSQRx Bit Settings ...................................................................................... 17-17
17-13 HSSRx Bit Settings....................................................................................... 17-18
17-14 CPRx Bit Settings ......................................................................................... 17-18
17-15 Channel Priorities .......................................................................................... 17-19
17-16 CISR Bit Settings .......................................................................................... 17-19
17-17 TPUMCR2 Bit Settings ................................................................................. 17-20
17-18 Entry Table Bank Location............................................................................. 17-21
17-19 System Clock Frequency/Minimum Guaranteed Detected Pulse.................. 17-21
17-20 TPUMCR3 Bit Settings ................................................................................. 17-21
17-21 Parameter RAM Address Offset Map ............................................................ 17-22
18-1 DPTRAM Register Map ..................................................................................... 18-3
18-2 DPTMCR Bit Settings ....................................................................................... 18-4
18-3 RAMBAR Bit Settings ....................................................................................... 18-5
MOTOROLA
xlii
LIST OF TABLES
Revised 1 March 1999
MPC555
USER’S MANUAL
Page
Number
Paragraph
Number
19-1 CMF Register Programmer’s Model .................................................................. 19-5
19-2 CMFMCR Bit Settings........................................................................................ 19-6
19-3 CMFTST Bit Settings ......................................................................................... 19-7
19-4 PAWS Programming Modes.............................................................................. 19-8
19-5 CMFCTL Bit Settings ......................................................................................... 19-9
19-6 EEPROM Array Addressing............................................................................. 19-11
19-7 CMF EEPROM Array Address Fields .............................................................. 19-11
19-8 Program Interlock State Descriptions .............................................................. 19-20
19-9 Results of Programming Margin Read............................................................. 19-21
19-10 Erase Interlock State Descriptions................................................................. 19-24
19-11 System Clock Range ..................................................................................... 19-26
19-12 Clock Period Exponent and Pulse Width Range ........................................... 19-27
19-13 Censorship Control Bits ................................................................................. 19-29
19-14 Levels of Censorship ..................................................................................... 19-29
19-15 CMF EEPROM Devices Modes and Censorship Status ............................... 19-31
19-16 NVM Fuse States........................................................................................... 19-32
20-1 SRAMMCR Bit Settings .................................................................................... 21-3
21-1 VF Pins Instruction Encodings.......................................................................... 21-3
21-2 VF Pins Queue Flush Encodings....................................................................... 21-4
21-3 VFLS Pin Encodings.......................................................................................... 21-4
21-4 Detecting the Trace Buffer Start Point ............................................................... 21-7
21-5 Fetch Show Cycles Control ............................................................................... 21-8
21-6 Instruction Watchpoints Programming Options ............................................... 21-17
21-7 Load/Store Data Events................................................................................... 21-18
21-8 Load/Store Watchpoints Programming Options .............................................. 21-19
21-9 The Check Stop State and Debug Mode ......................................................... 21-29
21-10 Trap Enable Data Shifted into Development Port Shift Register ................... 21-38
21-11 Debug Port Command Shifted Into Development Port Shift Register ........... 21-38
21-12 Status / Data Shifted Out of Development Port Shift Register....................... 21-39
21-13 Debug Instructions / Data Shifted Into Development Port Shift Register....... 21-40
21-14 Development Support Programming Model................................................... 21-44
21-15 Development Support Registers Read Access Protection ............................ 21-45
21-16 Development Support Registers Write Access Protection............................. 21-45
21-17 CMPA-CMPD Bit Settings ............................................................................. 21-46
21-18 CMPE-CMPF Bit Settings.............................................................................. 21-46
21-19 BAR Bit Settings ............................................................................................ 21-46
21-20 CMPG-CMPH Bit Settings ............................................................................. 21-47
21-21 ICTRL Bit Settings ......................................................................................... 21-48
21-22 LCTRL1 Bit Settings ...................................................................................... 21-50
21-23 LCTRL2 Bit Settings ...................................................................................... 21-51
21-24 Breakpoint Counter A Value and Control Register (COUNTA)...................... 21-52
21-25 Breakpoint Counter B Value and Control Register (COUNTB)..................... 21-53
21-26 ECR Bit Settings ............................................................................................ 21-54
21-27 DER Bit Settings ............................................................................................ 21-55
MPC555
USER’S MANUAL
LIST OF TABLES
Revised 1 March 1999
MOTOROLA
xliii
Page
Number
Paragraph
Number
22-1 JTAG Interface Pin Descriptions........................................................................ 22-3
22-2 Instruction Decoding .......................................................................................... 22-5
22-3 Boundary Scan Bit Definition ........................................................................... 22-10
A-1 SPR (Special Purpose Registers) ......................................................................... A-3
A-2 CMF (CDR MoneT Flash EEPROM) Flash Array ................................................. A-5
A-3 USIU (Unified System Interface Unit).................................................................... A-5
A-4 CMF (CDR MoneT Flash EEPROM)..................................................................... A-8
A-5 DPTRAM (Dual-Port TPU RAM) ...........................................................................A-9
A-6 DPTRAM Array...................................................................................................... A-9
A-7 TPU3 (Time Processor Unit) ................................................................................. A-9
A-8 QADC64 (Queued Analog-to-Digital Converter) ................................................. A-12
A-9 QSMCM (Queued Serial Multi-Channel Module) ................................................ A-13
A-10 MIOS1 (Modular Input/Output Subsystem) ....................................................... A-15
A-11 TouCAN (CAN 2.0B Controller).........................................................................A-20
A-12 UIMB (U-Bus to IMB3 Bus Interface) ................................................................A-21
A-13 SRAM (Static RAM Access Memory) ................................................................A-21
A-14 SRAM (Static RAM Access Memory) Array ...................................................... A-22
D-1
D-2
D-3
D-4
D-5
Bank 0 Functions ..................................................................................................D-2
Bank 1 Functions ..................................................................................................D-2
QOM Bit Encoding ................................................................................................D-5
SIOP Function Valid CHAN_Control Options......................................................D-44
SIOP State Timing ..............................................................................................D-46
E-1 External Components Value For Different Crystals (Q1) ......................................E-4
MOTOROLA
xliv
LIST OF TABLES
Revised 1 March 1999
MPC555
USER’S MANUAL
PREFACE
This manual defines the functionality of the MPC555 for use by software and hardware
developers. The MPC555 is based on the PowerPC processor used in the Motorola
MPC500 family of microcontrollers. For further information refer to the MPC500 Family RCPU Reference Manual, RCPURM/AD (Motorola order number).
Audience
This manual is intended for system software and hardware developers and applications programmers who want to develop products for the MPC555. It is assumed that
the reader understands operating systems, microprocessor and microcontroller system design, and the basic principles of RISC processing.
Additional Reading
For additional reading that provides background to or supplements the information in
this manual see:
• John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative
Approach, Morgan Kaufmann Publishers, Inc., San Mateo, CA
• PowerPC Microprocessor Family: the Programming Environments, MPCFPE/AD
(Motorola order number)
• MPC500 Family RCPU Reference Manual, RCPURM/AD (Motorola order number)
Conventions
This document uses the following notational conventions:
ACTIVE_HIGH
Names for signals that are active high are shown in uppercase
text without an overbar. Signals that are active high are referred
to as asserted when they are high and negated when they are
low.
ACTIVE_LOW
A bar over a signal name indicates that the signal is active low.
Active-low signals are referred to as asserted (active) when they
are low and negated when they are high.
0x0F
Hexadecimal numbers
0b0011
Binary numbers
REG[FIELD]
Abbreviations or acronyms for registers are shown in uppercase
text. Specific bit fields or ranges are shown in brackets.
x
In certain contexts, such as a signal encoding, this indicates a
don’t care. For example, if a field is binary encoded 0bx001, the
state of the first bit is a don’t care.
MPC555
REFERENCE MANUAL
PREFACE
Revised 1 March 1999
MOTOROLA
xlv
NOTE:
Throughout this manual references to 3V refer to the nominal supply
voltage of 3.3 volts.
Nomenclature
Logic level one is the voltage that corresponds to Boolean true (1) state.
Logic level zero is the voltage that corresponds to Boolean false (0) state.
To set a bit or bits means to establish logic level one on the bit or bits.
To clear a bit or bits means to establish logic level zero on the bit or bits.
A signal that is asserted is in its active logic state. An active low signal changes
from logic level one to logic level zero when asserted, and an active high signal
changes from logic level zero to logic level one.
A signal that is negated is in its inactive logic state. An active low signal changes
from logic level zero to logic level one when negated, and an active high signal
changes from logic level one to logic level zero.
LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes are spelled out.
MOTOROLA
xlvi
PREFACE
Revised 1 March 1999
MPC555
REFERENCE MANUAL
SECTION 1
OVERVIEW
The MPC555 is a member in the Motorola MPC500 PowerPCTM RISC Microcontroller
family. The MPC555 offers the following features:
• PowerPC core with floating-point unit
• 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM
• 448 Kbytes flash EEPROM with 5-V programming
• 5-V I/O system
• Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B
controller modules (TouCANTM)
• 50-channel timer system: dual time processor units (TPU3), modular I/O system
(MIOS1)
• 32 analog inputs: dual queued analog-to-digital converters (QADC64)
• Submicron HCMOS (CDR1) technology
• 272-pin plastic ball grid array (PBGA) packaging
• 40-MHz operation, -40° C to 125° C with dual supply (3.3 V, 5 V). (Note: throughout this manual references to 3 V refer to the nominal supply voltage of 3.3 V.)
1.1 Block Diagram
Figure 1-1 is a block diagram of the MPC555.
MPC555
USER’S MANUAL
OVERVIEW
Revised 1 March 1999
MOTOROLA
1-1
256 Kbytes
192 Kbytes
Flash
Flash
Burst
Interface
U-bus
E-bus
USIU
RCPU
16 Kbytes
10 Kbytes
SRAM
SRAM
L2U
L-bus
UIMB
QADC
QADC
QSMCM
TouCAN
IMB3
TPU3
DPTRAM
TPU3
TouCAN
MIOS1
Figure 1-1 MPC555 Block Diagram
1.2 MPC555 Features
Features of each module on the MPC555 are listed below.
1.2.1 RISC MCU Central Processing Unit (RCPU)
• 32-bit PowerPC Architecture (compliant with PowerPC Architecture Book 1)
• Core performance measured at 52.7 K MIPS (Dhrystone 2.1) @ 40 MHz. (Note:
this assumes the RCPU core is running in “normal” mode and show cycles is
turned off (ISCT_SER of the ICTRL register is set to 111). See Table 21-21.
• Fully static, low power operation
• Integrated floating-point unit
• Precise exception model
• Extensive system development support
— On-chip watchpoints and breakpoints
— Program flow tracking
— On-chip emulation (OnCETM) development interface
MOTOROLA
1-2
OVERVIEW
Revised 1 March 1999
MPC555
USER’S MANUAL
1.2.2 Four-Bank Memory Controller
• Works with SRAM, EPROM, flash EEPROM, and other peripherals
• Byte write enables
• 32-bit address decodes with bit masks
• Memory transfer start (MTS): This pin is the transfer start signal to access a
slave’s external memory by an external bus master
1.2.3 U-Bus System Interface Unit (USIU)
• Clock synthesizer
• Power management
• Reset controller
• PowerPC decrementer and time base
• Glueless interface to SRAMs and burstable FLASHs
• Real-time clock register
• Periodic interrupt timer
• Hardware bus monitor and software watchdog timer
• Interrupt controller that supports up to eight external and eight internal interrupts
• IEEE 1149.1 JTAG test access port
• External bus interface
— 24 address pins, 32 data pins
— Supports multiple master designs
— Four-beat transfer bursts, two-clock minimum bus transactions
— Tolerates 5-V inputs, provides 3.3-V outputs
1.2.4 Flexible Memory Protection Unit
• Four instruction regions and four data regions
• 4-Kbyte to 16-Mbyte region size support
• Default attributes available in one global entry
• Attribute support for speculative accesses
1.2.5 448 Kbytes of CDR MoneT Flash EEPROM Memory (CMF)
• One 256-Kbyte and one 192-Kbyte module
• Page read mode
• Block (32-Kbyte) erasable
• External 4.75-V to 5.25-V program and erase power supply
1.2.6 26 Kbytes of Static RAM
• One 16-Kbyte and one 10-Kbyte module
• Fast (one-clock) access
• Keep-alive power
• Soft defect detection (SDD)
1.2.7 General-Purpose I/O Support
• Address (24) and data (32) pins can be used for general-purpose I/O in singlechip mode
MPC555
USER’S MANUAL
OVERVIEW
Revised 1 March 1999
MOTOROLA
1-3
• 9 general-purpose I/O pins in MIOS1 unit
• Many peripheral pins can be used for general-purpose I/O when not used for primary function
• 5-V outputs
1.2.8 Two Time Processor Units (TPU3)
• Each TPU3 module provides these features:
— A dedicated micro-engine operates independently of the RCPU
— 16 independent programmable channels and pins
— Each channel has an event register consisting of a 16-bit capture register, a
16-bit compare register and a 16-bit comparator
— Nine pre-programmed timer functions are available
— Any channel can perform any time function
— Each timer function can be assigned to more than one channel
— Two timer count registers with programmable prescalers
— Each channel can be synchronized to one or both counters
— Selectable channel priority levels
— 5-V outputs
• 6-Kbyte dual port TPU RAM (DPTRAM) is shared by the two TPU3 modules for
TPU microcode
1.2.9 18-Channel Modular I/O System (MIOS1)
• Ten double action submodules (DASMs)
• Eight dedicated PWM sub-modules (PWMSMs)
• Two 16-bit modulus counter submodules (MCSMs)
• Two parallel port I/O submodules (PIOSM)
• 5-V outputs
1.2.10 Two Queued Analog-to-Digital Converter Modules (QADC)
Each QADC provides:
• Up to 16 analog input channels, using internal multiplexing
• Up to 41 total input channels, using internal and external multiplexing
• 10-bit A/D converter with internal sample/hold
• Typical conversion time of 10 µsec (100,000 samples per second)
• Two conversion command queues of variable length
• Automated queue modes initiated by:
— External edge trigger/level gate
— Software command
• 64 result registers
• Output data that is right- or left-justified, signed or unsigned
1.2.11 Two CAN 2.0B Controller Modules (TouCANs)
Each TouCAN provides these features:
• Full implementation of CAN protocol specification, version 2.0 A and B
MOTOROLA
1-4
OVERVIEW
Revised 1 March 1999
MPC555
USER’S MANUAL
• Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length
• Global mask register for message buffers 0 to 13
• Independent mask registers for message buffers 14 and 15
• Programmable transmit-first scheme: lowest ID or lowest buffer number
• 16-bit free-running timer for message time-stamping
• Low power sleep mode with programmable wake-up on bus activity
• Programmable I/O modes
• Maskable interrupts
• Independent of the transmission medium (external transceiver is assumed)
• Open network architecture
• Multimaster concept
• High immunity to EMI
• Short latency time for high-priority messages
• Low power sleep mode with programmable wakeup on bus activity
1.2.12 Queued Serial Multi-Channel Module (QSMCM)
• Queued serial peripheral interface (QSPI)
— Provides full-duplex communication port for peripheral expansion or interprocessor communication
— Up to 32 preprogrammed transfers, reducing overhead
— Has 160-byte queue
— Programmable transfer length: from eight to 16 bits, inclusive
— Synchronous interface with baud rate of up to system clock / 4
— Four programmable peripheral-select pins support up to 16 devices
• Wrap-around mode allows continuous sampling of a serial peripheral for efficient interfacing to serial A/D converters
• Two serial communications interfaces (SCI). Each SCI offers these features:
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer (SCI1)
— Advanced error detection and optional parity generation and detection
— Word length programmable as eight or nine bits
— Separate transmitter and receiver enable bits and double buffering of data
— Wakeup functions allow the CPU to run uninterrupted until either a true idle
line is detected or a new address byte is received
— External source clock for baud generation
— Multiplexing of transmit data pins with discrete outputs and receive data pins
with discrete inputs
1.3 MPC555 Address Map
The internal memory map is organized as a single 4-Mbyte block. The user can assign
this block to one of eight locations by programming a register in the USIU. The eight
possible locations are the first eight 4-Mbyte memory blocks starting with address
0x0000 0000. (Refer to Figure 1-2). The programmability of the internal memory map
location allows the user to implement a multiple-chip system.
MPC555
USER’S MANUAL
OVERVIEW
Revised 1 March 1999
MOTOROLA
1-5
0x0000 0000
0x003F FFFF
0x0040 0000
0x007F FFFF
0x0080 0000
0x00BF FFFF
0x00C0 0000
Internal 4-Mbyte Memory Block
(Resides in one of eight locations)
0x00FF FFFF
0x0100 0000
0x013F FFFF
0x0140 0000
0x017F FFFF
0x0180 0000
0x01BF FFFF
0x01C0 0000
0x01FF FFFF
0xFFFF FFFF
Figure 1-2 MPC555 Memory Map
The internal memory space is divided into the following sections:
• Flash memory (448 Kbytes)
• Static RAM memory (26 Kbytes)
• Control registers and IMB2 modules (64 Kbytes):
— USIU and flash control registers
— UIMB interface and IMB2 modules
— SRAM control registers
MOTOROLA
1-6
OVERVIEW
Revised 1 March 1999
MPC555
USER’S MANUAL
Reserved
0x00 0000
CMF Flash A
256 Kbytes
0x04 0000
0x06 FFFF
0x07 0000
0x2F C000
USIU Control Registers
1 Kbyte
CMF Flash B
192 Kbytes
FLASH Module A (64 bytes) 0x2F C800
FLASH Module B (64 bytes)
Reserved for Flash
(2.6 Mbytes -–16 Kbytes)
0x2F C840
0x2F C880
Reserved for SIU
0x 2F BFFF
0x 2F C000
0x 2F FFFF
0x 30 0000
U SI U & F lash Control
16 Kbytes
IMB3 Address Space
UIMB Interface &
IMB3 Modules
(32 Kbytes)
DPTRAM Control
(12 bytes)
Reserved (8180 bytes)
0x 30 7 FFF
0x 30 8000
DPTRAM (6 Kbytes)
Reserved for IMB3
(480 Kbytes)
TPU3_A (1 Kbyte)
TPU3_B (1 Kbyte)
QADC_A (1 Kbyte)
SR A M C on t r ol A
( 8 bytes)
QADC_B (1 Kbyte)
0x30 4800
0x30 4C00
0x30 5000
0x30 6000
MIOS1 (4 Kbytes)
Reserved
(485.98 Kbytes)
0x 3F C000
0x 3F FFFF
0x30 4000
0x30 4400
QSMCM (4 Kbytes)
SR A M C on t r ol B
( 8 bytes)
0x 38 0010
0x 3F 9800
0x30 2000
Reserved (2 Kbytes)
0x 37 FFFF
0x 38 0000
0x 38 0008
0x30 0000
TouCAN_A (1 Kbyte)
0x30 7080
TouCAN_B (1 Kbyte)
0x30 7480
SRAM A
(10 Kbytes)
Reserved (1920 bytes)
0x30 7884
SRAM B
(16 Kbytes)
UIMB_Registers
(128 bytes)
0x30 7F80
0x30 7FFF
Figure 1-3 MPC555 Internal Memory Map
MPC555
USER’S MANUAL
OVERVIEW
Revised 1 March 1999
MOTOROLA
1-7
MOTOROLA
1-8
OVERVIEW
Revised 1 March 1999
MPC555
USER’S MANUAL
SECTION 2
SIGNAL DESCRIPTIONS
2.1 Packaging and Pinout Descriptions
Figure 2-1 gives the case configuration and packaging information for the MPC555.
Figure 2-2 gives the MPC555 pinout data. Table 2-1 gives an overview of the pins on
the MPC555.
MPC555
USER’S MANUAL
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-1
PIN 1
INDEX
D
C
0.2
4X
A
272X
0.2 A
E
0.35 A
E2
D2
0.2
M
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER PARALLEL TO
PRIMARY DATUM A.
4. PRIMARY DATUM A AND THE SEATING PLANE
ARE DEFINED BY THE SPHERICAL CROWNS OF
THE SOLDER BALLS.
A B C
B
TOP VIEW
DIM
A
A1
A2
A3
b
D
D1
D2
E
E1
E2
e
(D1)
19X
19X
e
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
e
(E1)
4X
e /2
A1
A3
A2
A
SIDE VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
b 3
272X
BOTTOM VIEW
MILLIMETERS
MIN
MAX
2.05
2.65
0.50
0.70
0.50
0.70
1.05
1.25
0.60
0.90
27.00 BSC
24.13 REF
23.30
24.70
27.00 BSC
24.13 REF
23.30
24.70
1.27 BSC
0.3
M
A B C
0.15
M
A
CASE 1135A–01
ISSUE A
Figure 2-1 MPC555 Case Dimensions and Packaging
MOTOROLA
2-2
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Figure 2-2 MPC555 Pinout Data
MPC555
USER’S MANUAL
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-3
y Dees
2
3
4
B_TPUCH1
WEB_ AT[1]
RD_WRB
OEB
TSIZ0
BURSTB
P
R
T
U
V
Y
BDIPB
VDDL
CS1B
CS0B
BBB _IWP3
SGP_
IRQOUTB
IRQ4B
_SGP
VDDL
VDD SRAM
B_CNTX0
B_TPUCH9
B_TPUCH12
VDDL
VDDI
A_TPUCH5
A_TPUCH9
VSSA
VDDA
VRH
8
9
10
11
12
13
14
15
VDDL
Data_ SGP29 Data_ SGP27 Data_ SGP25 Data_ SGP23
VDDL
Data_ SGP20 RCFB_TXP
VDDI
VDDL
Addr_ SGP14 Addr_ SGP16 Addr_ SGP18 Addr_ SGP20 Addr_ SGP23 Addr_ SGP26 Data_ SGP1 Data_ SGP3 Data_ SGP5 Data_ SGP7 Data_ SGP9 Data_ SGP11 Data_ SGP13 Data_ SGP15 Data_ SGP17 IRQ5B _SGP
CLKOUT
EXTCLK
KAPWR
VDDF
VDDH
PORESETB
ECK_ BUCK
VSSSYN
XFC
VSSF
RXD2_ QGPI
EPEE
=3 volt power (I/O)
VDDi
=3 volt power (internal)
=ground
21 November 1997
VSS
VDDH
=5 volt power
MPIO13
MPIO12
MPIO9
MPIO6
MPWM3
MDA31
MDA28
A_CNRX0
Version 10.2
=Misc power
VDDH
HRESETB
SRESETB
XTAL
EXTAL
VDDSYN
VDDH
TXD2_
QGPO
SCK_ QGP6
MISO _QGP4 MOSI _QGP5
A_CNTX0
TXD1_
QGPO
VPP
20
VDDH
VF0 _MPIO0 VF1 _MPIO1
RXD1_
QGPI
PCS0
_QGP
VFLS1
_MPIO4
VFLS0
_MPIO3
MPIO14
MPIO11
MPIO7
MPWM19
MPWM2
MDA30
VDDH
Note: The pinout is a top down view of the package.
PCS1
_QGP
VDDL
VF2 _MPIO2
MPIO15
MPIO8
MPWM18
MPWM17
MPWM1
MDA29
MDA15
19
MDA13
ECK
VSS
VSS
VSS
MPIO10
MPIO5
MPWM16
MPWM0
VDDL
MDA27
MDA14
18
MDA12
PCS2
_QGP
VSS
VSS
VSS
VSS
VDDI
ETRIG1
ETRIG2
17
MDA11
PCS3
_QGP
VSS
VSS
VSS
VSS
16
VDDH
VSS
VSS
VSS
VSS
VSS
AAN1_PQB1 AAN50_PQB6 AAN55_PQA3 AAN58_PQA6 BAN50_PQB6 BAN55_PQA3 BAN58_PQA6 BAN59_PQA7
AAN2_PQB2 AAN51_PQB7 AAN56_PQA4 AAN59_PQA7 BAN49_PQB5 BAN53_PQA1 BAN56_PQA4 BAN57_PQA5
AAN3_PQB3 AAN49_PQB5 AAN53_PQA1 AAN57_PQA5 BAN1_PQB1 BAN48_PQB4 BAN52_PQA0 BAN54_PQA2
AAN0_PQB0 AAN48_PQB4 AAN52_PQA0 AAN54_PQA2 BAN0_PQB0 BAN2_PQB2 BAN3_PQB3 BAN51_PQB7
Addr_ SGP31 Addr_ SGP30 Addr_ SGP28 Addr_ SGP29
VDDI
A_TPUCH13
7
VRL
Addr_ SGP11 Addr_ SGP10 Addr_ SGP9 Addr_ SGP8 Addr_ SGP22 Addr_ SGP27 Data_ SGP31 Data_ SGP30 Data_ SGP28 Data_ SGP26 Data_ SGP24 Data_ SGP22 Data_ SGP21 Data_ SGP19 Data_ SGP18
TSB
TSIZ1
CS2B
WEB_ AT[3]
BGB_LWP1
IRQ2B
_SGP
6
Ball Map
Addr_ SGP13 Addr_ SGP15 Addr_ SGP17 Addr_ SGP19 Addr_ SGP21 Addr_ SGP24 Addr_ SGP25 Data_ SGP0 Data_ SGP2 Data_ SGP4 Data_ SGP6 Data_ SGP8 Data_ SGP10 Data_ SGP12 Data_ SGP14 Data_ SGP16 IRQ6B _mck2 IRQ7B _mck3
VDDH
BIB_STSB
TAB
TEAB
CS3B
WEB_ AT[2]
BRB_IWP2
Substrate 9/30/97a
VDDH
VDDH
W Addr_ SGP12
WEB_ AT[0]
N
IRQ1B
_SGP
IRQ3B
_SGP
SGP_FRZ
TRST_B
TDO_
DSDO
TDI_DSDI
B_CNRX0
B_TPUCH4
B_TPUCH8
B_TPUCH0
B_TPUCH3
B_TPUCH6
B_TPUCH10 B_TPUCH14
IWP1 _VFLS IWP0 _VFLS
TMS
M IRQ0B _SGP
L
K
J TCK_ DSCK
H
B_TPUCH2
B_TPUCH5
F
G
B_TPUCH7
A_TPUCH2
E
5
A_TPUCH12 A_TPUCH15
A_TPUCH10 A_TPUCH11 A_TPUCH14
A_TPUCH8
D B_TPUCH11 B_TPUCH13 A_TPUCH0
A_TPUCH6
A_TPUCH4
A_TPUCH7
A_T2CLK
VDDH
A_TPUCH1
A_TPUCH3
C B_TPUCH15
B_T2CLK
B
1
VDDH
A
MPC555
Table 2-1 MPC555 Pin Functions for 272-Pin PBGA
Functional Group
Signals1
Pins
24 Address lines
(16-Mbyte address space)
ADDR[8:31]/SGPIOA[8:31]
24
32-bit data bus
DATA[0:31]/SGPIOD[0:31]
32
3 V / 5 V2
3-V / 5-V GPIO
IRQ[0]/SGPIOC[0]
IRQ[1]/RSV/SGPIOC[1]
IRQ[2]/CR/SGPIOC[2]/MTS
External interrupts
IRQ[3]/KR/RETRY/SGPIOC[3]
8
3-V / 5-V GPIO
11
3V
8
3V
3
3V
5
3-V / 5-V GPIO
7
3V
5
3V
1
5V
IRQ[4]/AT[2]/SGPIOC[4]
IRQ[5]/SGPIOC[5]/MODCK[1]3
IRQ[6:7]/MODCK[2:3]3
TSIZ[0:1]
RD/WR
BURST
BDIP
Bus control
TS
TA
TEA
RSTCONF/TEXP3
OE
BI/STS
General purpose chip select machine
(multiplexed with development and
debug support)
CS[0:3]
WE[0:3]/BE[0:3]/AT[0:3]
PORESET3
Power-on reset and reset
configuration
HRESET3
SRESET3
SGPIOC[6]/FRZ/PTR
SGPIOC[7]/IRQOUT/LWP[0]
Development and debug support
BG/VF[0]/LWP[1]
BR/VF[1]/IWP[2]
BB/VF[2]/IWP[3]
TMS
TDI/DSDI
JTAG and debug port
TCK/DSCK
TDO/DSDO
TRST
IWP[0:1]/VFLS[0:1]
XTAL3
EXTAL3
Clocks and PLL
CLKOUT
EXTCLK3
XFC
ENGCLK/BUCLK
MOTOROLA
2-4
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-1 MPC555 Pin Functions for 272-Pin PBGA (Continued)
Functional Group
Signals1
Pins
3 V / 5 V2
12
5V
18
5V
5
3-V / 5-V GPIO
11
5V
34
5V
34
5V
PCS0/
SS/QGPIO[0]
PCS[1:3]/QGPIO[1:3]
MISO/QGPIO[4]
QSMCM
MOSI/QGPIO[5]
SCK/QGPIO[6]
TXD[1:2]/QGPO[1:2]
RXD[1:2]/QGPI[1:2]
ECK
MDA[11], [13]
MIOS
MDA[12], [14]
MDA[15], [27:31]
MPWM[0:3], [16:19]
VF[0:2]/MPIO32B[0:2]
General-Purpose I/O from MIOS
VFLS[0:1]/MPIO32B[3:4]
MPIO32B[5:15]
TPU
A_TPUCH[0:15], B_TPUCH[0:15]
A_T2CLK, B_T2CLK
ETRIG[1:2]
A_AN0/ANW/PQB0, B_AN0/ANW/PQB0
A_AN1/ANX/PQB1, B_AN1/ANX/PQB1
A_AN2/ANY/PQB2, B_AN2/ANY/PQB2
QADC
A_AN3/ANZ/PQB3, B_AN3/ANZ/PQB3
A_AN[48:51]/PQB[4:7], B_AN[48:51]/PQB[4:7]
A_AN[52:54]/MA[0:2]/PQA[0:2],
B_AN[52:54]/MA[0:2]/PQA[0:2]
A_AN[55:56]/PQA[3:4], B_AN[55:56]/PQA[3:4]
A_AN[57:59]/PQA[5:7], B_AN[57:59]/PQA[5:7]
TouCAN
A_CNTX0, B_CNTX0, A_CNRX0, B_CNRX0
4
5V
Flash EEPROM
EPEE
1
3V
Ground
VSS, VSSF, VSSSYN
18
Analog Ground
VSSA, VRL
2
Low Voltage Supply
VDDI, VDDL, VDDSRAM, VDDSYN, KAPWR3, VDDF
16
3V
High voltage Supply
VDDH, VDDA, VRH
12
5V
Programming Voltage
VPP
1
3-V / 5-V
Supplies
NOTES:
1. “/” implies that the corresponding functions are multiplexed on the pin
2. All inputs are 5 V friendly. All 5 V outputs are slow slew rate except for SCI transmit pins.
3. These pins are powered by KAPWR (Keep Alive Power Supply).
2.2 Pin Functionality
The pad ring supports 234 functional pins (284 including all power and ground). Some
pins serve multiple functions. The pad characteristics for each pin are described in
Table 2-2. This table contains the following columns:
MPC555
USER’S MANUAL
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-5
• Pin – List of functional (signal) names for each pin. (For actual pin names, see 2.7
Pin Names and Abbreviations.
• Function – Name of function (signal). Each pin supports one or more functions,
and each function (signal) name is a separate entry in the table.
• Driver Type – Type of driver that is used to drive the pin (for output functionality).
Types of output drivers are:
— Totem pole (TP). This driver type uses a push pull scheme to drive the pin.
These pins can be driven high or low or can be three-stated. Care must be taken to ensure that there is no contention on this pin (for example, an external
driver driving the pin high while an internal driver is driving it low).
— Open drain (OD). This driver type uses an open drain approach to drive the
pins. Pins with an OD driver can be either driven low or three-stated. This driver
scheme is typically used for pins that could potentially be asserted by multiple
modules.
— Active negated (ANG). This driver type fully drives a low level. A high level is
driven and then released. A pull-up resistor may be needed on this type of output.
• Receiver Type – Type of receiver used for the pin. Some inputs need to have a
synchronizer to prevent latching a metastable signal at the pins. Such requirements are indicated in this column with the abbreviation “synch.” Another possible
entry is “Glitch filter.” It is added to reset signals.
• Direction – Direction of the pin for each function it supports. The possible directions are Input (I), Output (O) and Bi-directional (I/O).
• Voltage – Voltage requirement for each function of a pin. There are two supply
voltages: 5 V and 3 V.
• Slew rate – Timing needed from the 5-V drivers. The options are with slew rate
(typically 200/50 ns with 50 pF load) or fast 5-V driver.
• Drive strength – Drive strength for 3-V drivers of the output load. For all 3-V outputs, the drive strength is 25/50 pF. For two pads (clkout and engclk) the drive
strength is 45/90 pF.
• Pad Type – Functional pad structure used for a pin. For pad type descriptions,
see 2.5 Pad Types.
MOTOROLA
2-6
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-2 Pin Functionality Table
Type
Pin
Direction1 Voltage
Function
Driver
Receiver
Slew Rate
ns / 50 pF
Drive
Strength
(pF)
Pad
Type
USIU
ADDR[8:31]
ADDR[8:31]/
SGPIOA[8:31] SGPIOA[8:31]
TP
—
I/O
3V
—
25 / 50
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
TP
—
I/O
3V
—
25 / 50
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
—
Hysteresis,
Synch
I
3V
—
—
SGPIOC[0]
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
IRQ[1]
—
Hysteresis,
Synch
I
3V
—
—
RSV
TP
—
O
3V
—
25 / 50
SGPIOC[1]
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
IRQ[2]
—
Hysteresis,
Synch
I
3V
—
—
—
—
I
3V
—
—
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
MTS
TP
—
O
3V
25 / 50
—
IRQ[3]
—
Hysteresis,
Synch
I
3V
—
—
KR, RETRY
TP
—
I/O
3V
—
SGPIOC[3]
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
IRQ[4]
—
Hysteresis,
Synch
I
3V
—
—
AT[2]
TP
—
O
3V
—
25 / 50
SGPIOC[4]
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
IRQ[5]
—
Hysteresis,
Synch
I
3V
—
—
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
—
—
I
3V
—
—
DATA[0:31]
DATA[0:31]/
SGPIOD[0:31] SGPIOD[0:31]
IRQ[0]
IRQ[0]/
SGPIOC[0]
IRQ[1]/RSV/
SGPIOC[1]
IRQ[4]/AT[2]/
SGPIOC[4]
IRQ[5]/
SGPIOC[5]/
MODCK[1]2
JD
IH
CR
IRQ[2]/CR/
SGPIOC[2]/MTS
SGPIOC[2]
IRQ[3]/KR,
RETRY/
SGPIOC[3]
J
SGPIOC[5]
MODCK[1]
MPC555
USER’S MANUAL
IH
IH
SIGNAL DESCRIPTIONS
Revised 1 March 1999
25 / 50
IH
IH
IH
MOTOROLA
2-7
Table 2-2 Pin Functionality Table (Continued)
Type
Pin
IRQ[6:7]/
MODCK[2:3]2
Direction1 Voltage
Function
IRQ[6:7]
Driver
Receiver
—
Hysteresis,
Synch
I
3V
Slew Rate
ns / 50 pF
Drive
Strength
(pF)
—
—
Pad
Type
CH
MODCK[2:3]
—
—
I
3V
—
—
TSIZ[0:1]
TP
—
I/O
3V
—
25 / 50
F
RD/WR
RD/WR
TP
—
I/O
3V
—
25 / 50
F
BURST
BURST
TP
—
I/O
3V
—
25 / 50
F
BDIP
TP
—
I/O
3V
—
25 / 50
F
TSIZ[0:1]
BDIP
TS3
TS
ANG
—
I/O
3V
—
25 / 50
E
3
TA
ANG
—
I/O
3V
—
25 / 50
E
TEA
OD
—
I/O
3V
—
25 / 50
E
RSTCONF
—
—
I
3V
—
—
TEXP
TP
—
O
3V
—
25 / 50
OE
TP
—
O
3V
—
25 / 50
BI3
ANG
—
I/O
3V
—
25 / 50
STS
TP
—
O
3V
—
25 / 50
CS[0:3]
TP
—
O
3V
—
25 / 50
TP
—
O
3V
—
25 / 50
TP
—
O
3V
—
25 / 50
TA
TEA
RSTCONF/
TEXP2
OE
E
BI/STS
CS[0:3]
A
E
WE[0:3]/BE[0:3]/ WE[0:3]/BE[0:3]
AT[0:3]
AT[0:3]
A
F
PORESET
—
Hysteresis
Glitch filter
I
3V
—
—
CNH
HRESET2
HRESET
OD
Hysteresis
Glitch filter
I/O
3V
—
25 / 50
EOH
SRESET,2
SRESET
OD
Hysteresis
Glitch filter
I/O
3V
—
25 / 50
EOH
SGPIOC[6]
TP
I/O
5V
200 / fast
—
SGPIOC[6]/FRZ/
PTR
FRZ
Hysteresis,
Synch
TP
—
O
3V
—
25 / 50
PTR
TP
—
O
3V
—
25 / 50
SGPIOC[7]
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
TP
—
O
3V
—
25 / 50
TP
—
O
3V
—
25 / 50
PORESET2
SGPIOC[7]/
IRQOUT/LWP[0] IRQOUT
LWP[0]
MOTOROLA
2-8
SIGNAL DESCRIPTIONS
Revised 1 March 1999
I
I
MPC555
USER’S MANUAL
Table 2-2 Pin Functionality Table (Continued)
Type
Pin
Direction1 Voltage
Function
Slew Rate
ns / 50 pF
Drive
Strength
(pF)
Pad
Type
Driver
Receiver
BG
TP
—
I/O
3V
—
25 / 50
VF[0]
TP
—
O
3V
—
25 / 50
LWP[1]
TP
—
O
3V
—
25 / 50
BR
TP
—
I/O
3V
—
25 / 50
VF[1]
TP
—
O
3V
—
25 / 50
IWP[2]
TP
—
O
3V
—
25 / 50
ANG
—
I/O
3V
—
25 / 50
VF[2]
TP
—
O
3V
—
25 / 50
IWP[3]
TP
—
O
3V
—
25 / 50
IWP[0:1]
TP
—
O
3V
—
25 / 50
VFLS[0:1]
TP
—
O
3V
—
25 / 50
TMS
—
—
I
3V
—
—
TDI
—
—
I
3V
—
—
DSDI
—
—
I
3V
—
—
TCK
—
—
I
3V
—
—
DSCK
—
—
I
3V
—
—
TDO
TP
—
O
3V
—
25 / 50
DSDO
TP
—
O
3V
—
25 / 50
TRST
TRST
—
—
I
3V
—
—
C
XTAL2
XTAL
TP
—
O
3V
—
—
—
EXTAL
—
—
I
3V
—
—
—
XFC
—
—
I/O
3V
—
—
—
CLKOUT
CLKOUT
TP
—
O
3V
—
45 / 90
B
EXTCLK2
EXTCLK
—
—
I
3V
—
—
—
ENGCLK
TP
—
O
5V
—
45 / 90
BUCLK
TP
—
O
5V
—
45 / 90
BG/
VF[0]/
LWP[1]
BR/
VF[1]/
IWP[2]
BB/
VF[2]/
IWP[3]
IWP[0:1]/
VFLS[0:1]
TMS
BB3
G
C
C
TCK/DSCK
D
TDO/DSDO
XFC
G
A
TDI/DSDI
EXTAL2
G
A
ENGCLK/BUCLK
S
QSMCM
PCS0/
SS/QGPIO[0]
PCS0
TP/OD
Synch/
No Synch
I/O
5V
50 / fast
—
SS
TP/OD
Synch/
No Synch
I/O
5V
50 / fast
—
QGPIO[0]
TP/OD
Synch/
No Synch
I/O
5V
50 / fast
—
MPC555
USER’S MANUAL
SIGNAL DESCRIPTIONS
Revised 1 March 1999
O
MOTOROLA
2-9
Table 2-2 Pin Functionality Table (Continued)
Type
Pin
Direction1 Voltage
Function
Slew Rate
ns / 50 pF
Drive
Strength
(pF)
Pad
Type
Driver
Receiver
PCS[1:3]
TP/OD
Synch
I/O
5V
50 / fast
—
QGPIO[1:3]
TP/OD
Synch
I/O
5V
50 / fast
—
MISO
TP/OD
Synch/
No Synch
I/O
5V
50 / fast
—
QGPIO[4]
TP/OD
Synch/
No Synch
I/O
5V
50 / fast
—
MOSI
TP/OD
Synch/
No Synch
I/O
5V
50 / fast
—
QGPIO[5]
TP/OD
Synch/
No Synch
I/O
5V
50 / fast
—
SCK
TP/OD
Synch/
No Synch
I/O
5V
50 / fast
—
QGPIO[6]
TP/OD
Synch/
No Synch
I/O
5V
50 / fast
—
TXD[1:2]/
QGPO[1:2]
TXD[1:2]
TP/OD
—
O
5V
200 / fast
—
QGPO[1:2]
TP/OD
—
O
5V
200 / fast
—
RXD[1:2]/
QGPI[1:2]
RXD[1:2]
—
—
I
5V
—
—
QGPI[1:2]
—
—
I
5V
—
—
ECK
—
—
I
5V
—
—
R
PCS[1:3]/
QGPIO[1:3]
O
MISO/QGPIO[4]
O
MOSI/QGPIO[5]
O
SCK/QGPIO[6]
ECK
O
Q
R
MIOS
MDA[11:15]
MDA[11:15]
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
P
MDA[27:31]
MDA[27:31]
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
P
MPWM[0:3],
[16:19]
MPWM[0:3],
[16:19]
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
P
VF[0:2]
VF[0:2]/
MPIO32B[0:2] MPIO32B[0:2]
TP
—
O
3V
—
25 / 50
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
VFLS[0:1]
VFLS[0:1]/
MPIO32B[3:4] MPIO32B[3:4]
TP
—
O
3V
—
25 / 50
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
MPIO32B[5:15] MPIO32B[5:15]
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
O
I/O
5V
200 / fast
—
P
H
H
TPU_A/TPU_B
A_TPUCH[0:15] TPUCH[0:15]
MOTOROLA
2-10
TP
Hysteresis,
Synch
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-2 Pin Functionality Table (Continued)
Type
Pin
A_T2CLK
T2CLK
B_TPUCH[0:15] TPUCH[0:15]
B_T2CLK
Direction1 Voltage
Function
T2CLK
Slew Rate
ns / 50 pF
Drive
Strength
(pF)
Pad
Type
Driver
Receiver
TP
Hysteresis
Synch
I/O
5V
200 / fast
—
P
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
P
TP
Hysteresis,
Synch
I/O
5V
200 / fast
—
P
N
QADC_A/QADC_B
ETRIG[1:2]
AN0/
ANW/
PQB0
AN1/ANX/PQB1
AN2/ANY/PQB2
AN3/ANZ/PQB3
AN[48:51]/
PQB[4:7]
ETRIG[1:2]
—
Synch
I
5V
—
—
AN0
—
Analog
I
5V
—
—
ANW
—
Analog
I
5V
—
—
PQB0
—
Hysteresis,
Synch
I
5V
—
—
AN1
—
Analog
I
5V
—
—
ANX
—
Analog
I
5V
—
—
PQB1
—
Hysteresis,
Synch
I
5V
—
—
AN2
—
Analog
I
5V
—
—
ANY
—
Analog
I
5V
—
—
PQB2
—
Hysteresis,
Synch
I
5V
—
—
AN3
—
Analog
I
5V
—
—
ANZ
—
Analog
I
5V
—
—
PQB3
—
Hysteresis,
Synch
I
5V
—
—
AN[48:51]
—
Analog
I
5V
—
—
PQB[4:7]
—
Hysteresis,
Synch
I
5V
—
—
AN[52:54]
—
Analog
I
5V
—
—
OD
—
O
5V
—
—
OD
Hysteresis,
Synch
I/O
5V
—
—
AN[55:56]
—
Analog
I
5V
—
—
PQA[3:4]
OD
Hysteresis,
Synch
I/O
5V
—
—
AN[52:54]/
MA[0:2]
MA[0:2]/PQA[0:2]
PQA[0:2]
AN[55:56]/
PQA[3:4]
MPC555
USER’S MANUAL
M
M
M
M
M
L
L
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-11
Table 2-2 Pin Functionality Table (Continued)
Type
Pin
AN[57:59]/
PQA[5:7]
AN0/ANW/PQB0
AN1/ANX/PQB1
AN2/ANY/PQB2
AN3/ANZ/PQB3
AN[48:51]/
PQB[4:7]
AN[57:59]/
PQA[5:7]
Slew Rate
ns / 50 pF
Drive
Strength
(pF)
Driver
Receiver
AN[57:59]
—
Analog
I
5V
—
—
PQA[5:7]
OD
Hysteresis,
Synch
I/O
5V
—
—
AN0
—
Analog
I
5V
—
—
ANW
—
Analog
I
5V
—
—
PQB0
—
Hysteresis,
Synch
I
5V
—
—
AN1
—
Analog
I
5V
—
—
ANX
—
Analog
I
5V
—
—
PQB1
—
Hysteresis,
Synch
I
5V
—
—
AN2
—
Analog
I
5V
—
—
ANY
—
Analog
I
5V
—
—
PQB2
—
Hysteresis,
Synch
I
5V
—
—
AN3
—
Analog
I
5V
—
—
ANZ
—
Analog
I
5V
—
—
PQB3
—
Hysteresis,
Synch
I
5V
—
—
AN[48:51]
—
Analog
I
5V
—
—
PQB[4:7]
—
Hysteresis,
Synch
I
5V
—
—
AN[52:54]
—
Analog
I
5V
—
—
OD
—
O
5V
—
—
PQA[0:2]
OD
Hysteresis,
Synch
I/O
5V
—
—
AN[55:56]
—
Analog
I
5V
—
—
PQA[3:4]
OD
Hysteresis,
Synch
I/O
5V
—
—
AN[57:59]
—
Analog
I
5V
—
—
PQA[5:7]
OD
Hysteresis,
Synch
I/O
5V
—
—
MA[0:2]
AN[52:54]/
MA[0:2]/PQA[0:2]
AN[55:56]/
PQA[3:4]
Direction1 Voltage
Function
Pad
Type
L
M
M
M
M
M
L
L
L
TOUCAN_A/TOUCAN_B
A_CNTX0
CNTX0_A
TP/OD
—
O
5V
50 / fast
—
Q
B_CNTX0
CNTX0_B
TP/OD
—
O
5V
50 / fast
—
Q
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Revised 1 March 1999
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USER’S MANUAL
Table 2-2 Pin Functionality Table (Continued)
Type
Pin
Direction1 Voltage
Function
Driver
Receiver
Slew Rate
ns / 50 pF
Drive
Strength
(pF)
Pad
Type
A_CNRX0
CNRX0_A
—
Synch / No
Synch
I
5V
—
—
R
B_CNRX0
CNRX0_B
—
Synch / No
Synch
I
5V
—
—
R
CMF
EPEE
VPP
EPEE
—
Sequencer
I
3V
—
—
K
VPP
—
—
I
5V
—
—
—
Global Power Supplies
VDDA
VDDA
—
—
I
5V
—
—
—
VDDF
VDDF
—
—
I
3V
—
—
—
VDDL
VDDL
—
—
I
3V
—
—
—
VDDH
VDDH
—
—
I
5V
—
—
—
VDDI
VDDI
—
—
I
3V
—
—
—
VDDSYN
—
—
I
3V
—
—
—
VRH
VRH
—
—
I
5V
—
—
—
VRL
VRL
—
—
I
—
—
—
—
VSSA
VSSA
—
—
I
—
—
—
—
VSSF
VSSF
—
—
I
—
—
—
—
VSSSYN
VSSSYN
—
—
I
—
—
—
—
KAPWR2
KAPWR
—
—
I
3V
—
—
—
VDDSRAM
—
—
I
3V
—
—
—
VSS
—
—
I
—
—
—
—
VDDSYN
VDDSRAM
VSS
NOTES:
1. All inputs are 5-V friendly. All 5-V outputs are slow slew rate. The QSMCM and TouCAN pins have some slew rate
control, but are faster than the general/purpose I/O and timer pins.
2. These pins are powered by KAPWR (Keep Alive Power Supply).
3. This pin is an active negate signal and may need an external pull-up resister.
2.3 Signal Descriptions
The pad ring supports 234 functional pins (284 including all power and ground). Each
pin and the functionality it supports are described in this section. All references to timing in this document are numbers that are expected for a typical case process with a
50-pF load at 25oC. The supply voltages are assumed to be typical, as well: 5 V or 3.3
V. The 5-V supply is generally referred to as the 5-V supply, and the 3.3-V supply is
referred to as the 3-V supply in this section.
MPC555
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
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2.3.1 USIU Pads
2.3.1.1 ADDR[8:31]/SGPIOA[8:31]
Pin Name: addr_sgpioa[8:31] (24 pins)
Address Bus – Specifies the physical address of the bus transaction. The address is
driven onto the bus and kept valid until a transfer acknowledge is received from the
slave. ADDR8 is the most significant signal for this bus.
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
2.3.1.2 DATA[0:31]/SGPIOD[0:31]
Pin Name: data_sgpiod[0:31] (32 pins)
Data Bus – Provides the general purpose data path between the chip and all other
devices. Although the data path is a maximum of 32 bits wide, it can be sized to support 8-, 16-, or 32-bit transfers. DATA[0] is the MSB of the data bus.
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
2.3.1.3 IRQ[0]/SGPIOC[0]
Pin Name: irq0_b_sgpioc0
Interrupt Request – One of the eight external lines that can request, by means of the
internal interrupt controller, a service routine from the RCPU. IRQ0 is a nonmaskable
interrupt (NMI).
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
2.3.1.4 IRQ[1]/RSV_B/SGPIOC[1]
Pin Name: irq1_b_rsv_b_sgpioc1
Interrupt Request – One of the eight external lines that can request, by means of the
internal interrupt controller, a service routine from the RCPU.
Reservation – This line used together with the address bus to indicate that the internal
core initiated a transfer as a result of a STWCX or a LWARX instruction.
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
2.3.1.5 IRQ[2]/CR_B/SGPIOC[2]/MTS
Pin Name: irq2_b_cr_b_sgpioc2_mts
Interrupt Request – One of the eight external lines that can request, by means of the
internal interrupt controller, a service routine from the RCPU.
Cancel Reservation – Instructs the chip to clear its reservation, some other master
has touched its reserved space. An external bus snooper would assert this signal.
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USER’S MANUAL
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
Memory Transfer Start – This pin is the transfer start signal from the MPC555 memory controller to allow external memory access by an external bus master.
2.3.1.6 IRQ[3]/KR/RETRY/SGPIOC[3]
Pin Name: irq3_b_kr_b_retry_b_sgpioc3
Interrupt Request – One of the eight external lines that can request, by means of the
internal interrupt controller, a service routine from the RCPU.
Kill Reservation – In case of a bus cycle initiated by a STWCX instruction issued by
the CPU core to a non-local bus on which the storage reservation has been lost, this
signal is used by the non-local bus interface to back-off the cycle.
Retry – Indicates to a master that the cycle is terminated but should be repeated. As
an input, it is driven by the external slave to retry a cycle.
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
2.3.1.7 IRQ[4]/AT[2]/SGPIOC[4]
Pin Name: irq4_b_at2_sgpioc4
Interrupt Request – One of the eight external lines that can request, by means of the
internal interrupt controller, a service routine from the RCPU.
Address Type – A bit from the address type bus which Indicates one of the 16
“address types” to which the address applies. The address type signals are valid at the
rising edge of the clock in which the Special Transfer Start (STS) is asserted.
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
2.3.1.8 IRQ[5]/SGPIOC[5]/MODCK[1]
Pin Name: irq5_b_sgpioc5_modck1
Interrupt Request – One of the eight external lines that can request, by means of the
internal interrupt controller, a service routine from the RCPU.
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
Mode Clock [1] – Sampled at the negation of PORESET in order to configure the
phase-locked loop (PLL)/clock mode of operation.
2.3.1.9 IRQ[6:7]/MODCK[2:3]
Pin Name: irq6_b_modck2 - irq7_b_modck3 (2 pins)
Interrupt Request – One of the eight external lines that can request, by means of the
internal interrupt controller, a service routine from the RCPU.
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Revised 1 March 1999
MOTOROLA
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Mode Clock [2:3] – Sampled at the negation of PORESET in order to configure the
PLL/clock mode of operation.
2.3.1.10 TSIZ[0:1]
Pin Name: tsiz0 - tsiz1 (2 pins)
Transfer size – Indicates the size of the requested data transfer in the current bus
cycle.
2.3.1.11 RD/WR
Pin Name: rd_wr_b
Read/Write – Indicates the direction of the data transfer for a transaction. A logic one
indicates a read from a slave device; a logic zero indicates a write to a slave device.
2.3.1.12 BURST
Pin Name: burst_b
Burst Indicator – Indicates whether the current transaction is a burst transaction or
not.
2.3.1.13 BDIP
Pin Name: bdip_b
Burst data in progress – Indicates to the slave that there is a data beat following the
current data beat.
2.3.1.14 TS
Pin Name: ts_b
Transfer Start – Indicates the start of a bus cycle that transfers data to/from a slave
device. This signal is driven by the master only when it gained the ownership of the
bus. Every master should negate this signal before the bus relinquish. Every master
should negate this signal before the bus is relinquished. This pin is an active negate
signal and may need an external pull-up resistor to ensure proper operation and signal
timing specifications.
2.3.1.15 TA
Pin Name: ta_b
Transfer Acknowledge – This line indicates that the slave device addressed in the
current transaction has accepted the data transferred by the master (write) or has
driven the data bus with valid data (read). The slave device negates the TA_B signal
after the end of the transaction and immediately three-state it to avoid contentions on
the line if a new transfer is initiated addressing other slave devices. This pin is an
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
active negate signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications.
2.3.1.16 TEA
Pin Name: tea_b
Transfer Error Acknowledge – This signal indicates that a bus error occurred in the
current transaction. The MCU asserts this signal when the bus monitor does not detect
a bus cycle termination within a reasonable amount of time. The assertion of TEA
causes the termination of the current bus cycle, regardless of the state of TEA. An
external pull-up device is required to negate TEA quickly, before a second error is
detected. That is, the pin must be pulled up within one clock cycle of the time it was
three-stated by the MPC555.
2.3.1.17 RSTCONF/TEXP
Pin Name: rstconf_b_texp
Reset Configuration – Input. This input line is sampled by the chip during the assertion of the HRESET signal in order to sample the reset configuration. If the line is
asserted, the configuration mode will be sampled from the external data bus. When
this line is negated, the configuration mode adopted by the chip will be the default one.
Timer Expired – This output line reflects the status of the TEXPS bit in the PLPRCR
register in the USIU. This indicates an expired timer value.
2.3.1.18 OE
Pin Name: oe_b
Output Enable – This output line is asserted when a read access to an external slave
controlled by the GPCM in the Memory Controller is initiated by the chip.
2.3.1.19 BI/STS
Pin Name: bi_b_sts_b
Burst Inhibit – This bi-directional, active low, three-state line indicates that the slave
device addressed in the current burst transaction is not able to support burst transfers.
When the chip drives out the signal for a specific transaction, it asserts or negates BI
during the transaction according to the value specified by the user in the appropriate
control registers. Negation of the signal occurs after the end of the transaction followed
by the immediate three-state. This pin is an active negate signal and may need an
external pull-up resistor to ensure proper operation and signal timing specifications.
Special Transfer Start – This output signal is driven by the chip to indicate the start
of a transaction on the external bus or signals the beginning of an internal transaction
in showcycle mode.
MPC555
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
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2.3.1.20 CS[0:3]
Pin Name: cs0_b - cs3_b (4 pins)
Chip Select – These output signals enable peripheral or memory devices at programmed addresses if defined appropriately in the memory controller. CS0 can be
configured to be the global chip select for the boot device.
2.3.1.21 WE[0:3]/BE[0:3]/AT[0:3]
Pin Name: we_b_at[0:3](4 pins)
Write Enable[0:3]/Byte Enable[0:3] – This output line is asserted when a write
access to an external slave controlled by the GPCM in the memory controller is initiated by the chip. It can be optionally be asserted all read and write accesses. See
WEBS bit definition in Table 10-7. WE0/BE0 is asserted if the data lane DATA[0:7]
contains valid data to be stored by the slave device. WE1/BE1 is asserted if the data
lane DATA[8:15] contains valid data to be stored by the slave device. WE2/BE2 is
asserted if the data line DATA[16:23] contains valid data to be stored by the slave
device. WE3/BE3 is asserted if the data lane DATA[24:31] contains valid data to be
stored by the slave device.
Address Type – Indicates one of the 16 address types to which the address applies.
The address type signals are valid at the rising edge of the clock in which the Special
Transfer Start (STS) is asserted.
2.3.1.22 PORESET
Pin Name: poreset_b
Power on Reset – This pin should be activated as a result of a voltage failure on the
keep-alive power pins. The pin has a glitch detector to ensure that low spikes of less
than 20 ns are rejected. The internal PORESET signal is asserted only if PORESET
is asserted for more than 100 ns. See SECTION 7 RESET for more details on timing.
2.3.1.23 HRESET
Pin Name: hreset_b
Hard Reset – The chip can detect an external assertion of HRESET only if it occurs
while the chip is not asserting reset. After negation of HRESET or SRESET is
detected, a 16 cycles period is taken before testing the presence of an external reset.
The internal HRESET signal is asserted only if HRESET is asserted for more than 100
ns. To meet external timing requirements, an external pull-up device is required to
negate HRESET. See SECTION 7 RESET for more details on timing.
2.3.1.24 SRESET
Pin Name: sreset_b
Soft Reset – The chip can detect an external assertion of SRESET only if it occurs
while the chip is not asserting reset. After negation of HRESET or SRESET is
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
detected, a 16-cycle period is taken before testing the presence of an external soft
reset. To meet external timing requirements, an external pull-up device is required to
negate SRESET. See SECTION 7 RESET for more details on timing.
2.3.1.25 SGPIOC[6]/FRZ/PTR
Pin Name: sgpioc6_frz_ptr_b
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
Freeze – Indicates that the RCPU is in debug mode.
Program Trace – Indicates an instruction fetch is taking place in order to allow program flow tracking.
2.3.1.26 SGPIOC[7]/IRQOUT/LWP[0]
Pin Name: sgpioc7_irqout_b_lwp0
SGPIO – This function allows the pins to be used as general purpose inputs/outputs.
Interrupt Out – Indicates that an interrupt has been requested to all external devices.
Load/Store Watchpoint 0 – This output line reports the detection of a data watchpoint
in the program flow executed by the RCPU. See SECTION 21 DEVELOPMENT SUPPORT for more details.
2.3.1.27 BG/VF[0]/LWP[1]
Pin Name: bg_b_vf0_lwp1
Bus Grant – Indicates external data bus status. Is asserted low when the arbiter of the
external bus grants to the specific master the ownership of the bus.
Visible Instruction Queue Flush Status – This output line together with VF1 and VF2
is output by the chip when a program instructions flow tracking is required by the user.
VF report the number of instructions flushed from the Instruction Queue in the Internal
Core. See SECTION 21 DEVELOPMENT SUPPORT for more details.
Load/Store Watchpoint – This output line reports the detection of a data watchpoint
in the program flow executed by the RCPU.
2.3.1.28 BR/VF[1]/IWP[2]
Pin Name: br_b_vf1_iwp2
Bus Request – Indicates that the data bus has been requested for external cycle.
Visible Instruction Queue Flush Status – This output line together with VF1 and VF2
is output by the chip when a Program instructions flow tracking is required by the user.
VF report the number of instructions flushed from the Instruction Queue in the Internal
Core. See SECTION 21 DEVELOPMENT SUPPORT for more details.
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Revised 1 March 1999
MOTOROLA
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Instruction Watchpoint 2 – This output line reports the detection of an instruction
watchpoint in the program flow executed by the RCPU.
2.3.1.29 BB/VF[2]/IWP[3]
Pin Name: bb_b_vf2_iwp3
Bus Busy – Indicates that the master is using the bus. This pin is an active negate
signal and may need an external pull-up resistor to ensure proper operation and signal
timing specifications.
Visible Instruction Queue Flush Status – This output line together with VF0 and VF1
is output by the chip when a Program instructions flow tracking is required by the user.
VF report the number of instructions flushed from the Instruction Queue in the Internal
Core.
Instruction Watchpoint 3 – This output line reports the detection of an instruction
watchpoint in the program flow executed by the Internal Core.
2.3.1.30 IWP[0:1]/VFLS[0:1]
Pin Name: iwp0_vfls0 - iwp1_vfls1 (2 pins)
Instruction Watchpoint – These output lines report the detection of an instruction
watchpoint in the program flow executed by the RCPU.
Visible History Buffer Flush Status – These signals are output by the chip to enable
program instruction flow tracking. They report the number of instructions flushed from
the history buffer in the RCPU. See SECTION 21 DEVELOPMENT SUPPORT for
details.
2.3.1.31 TMS
Pin Name: tms
Test Mode Select – This input controls test mode operations for on-board test logic
(JTAG).
2.3.1.32 TDI/DSDI
Pin Name: tdi_dsdi
Test Data In – This input is used for serial test instructions and test data for on-board
test logic (JTAG).
Development Serial Data Input – This input line is the data in for the debug port interface. See SECTION 21 DEVELOPMENT SUPPORT for details.
2.3.1.33 TCK/DSCK
Pin Name: tck_dsck
Test Clock – This input provides a clock for on-board test logic (JTAG).
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Revised 1 March 1999
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USER’S MANUAL
Development Serial Clock – This input line is the clock for the debug port interface.
See SECTION 21 DEVELOPMENT SUPPORT for details.
2.3.1.34 TDO/DSDO
Pin Name: tdo_dsdo
Test Data Out – This output is used for serial test instructions and test data for onboard test logic (JTAG).
Development Serial Data Output – This output line is the data-out line of the debug
port interface. See SECTION 21 DEVELOPMENT SUPPORT for details.
2.3.1.35 TRST
Pin Name: trst_b
Test Reset – This input provides asynchronous reset to the test logic (JTAG).
For non-JTAG test applications, TRST should be connected to ground or PORESET
via an external resistor.
2.3.1.36 XTAL
Pin Name: xtal
XTAL – This output line is one of the connections to an external crystal for the internal
oscillator circuitry.
2.3.1.37 EXTAL
Pin Name: extal
EXTAL – This line is one of the connections to an external crystal for the internal oscillator circuitry. If this pin is unused, it must be grounded.
2.3.1.38 XFC
Pin Name: xfc
External Filter Capacitance – This input line is the connection pin for an external
capacitor filter for the PLL circuitry.
2.3.1.39 CLKOUT
Pin Name: clkout
Clock Out – This output line is the clock system frequency. The CLKOUT drive
strength can be configured to full strength, half strength, or disabled. The drive
strength is configured using the COM[0:1] bits in the SCCR register in the USIU.
2.3.1.40 EXTCLK
Pin Name: extclk
MPC555
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-21
EXTCLK – Input. This is the external frequency source for the chip. If this is unused,
the pin must be grounded.
2.3.1.41 VDDSYN
Pin Name: vddsyn
VDDSYN – This is the power supply of the PLL circuitry.
2.3.1.42 VSSSYN
Pin Name: vsssyn
VSSSYN – This is the power supply of the PLL circuitry.
2.3.1.43 ENGCLK/BUCLK
Pin Name: engclk_buclk
ENGCLK – This is the engineering clock output. Drive strength can be configured to
full strength, half strength or disabled. The drive strength is configured using the
EECLK[0:1] bits in the SCCR register in the SIU.
BUCLK – When the chip is in limp mode, it is operating from a less precise on-chip
ring oscillator to allow the system to continue minimum functionality until the system
clock is fixed. This backup clock can be seen externally based on the values of the
EECLK[0:1] bits in the SCCR register in the USIU.
2.3.2 QSMCM PADS
2.3.2.1 PCS0/SS/QGPIO[0]
Pin Name: pcs0_ss_b_qgpio0
PCS0 – This signal provides QSPI peripheral chip select 0.
SS – Assertion of this bi-directional signal places the QSPI in slave mode.
QSPI GPIO[0] – When this pin is not needed for a QSPI application it can be configured as a general purpose input/output.
2.3.2.2 PCS(1:3)/QGPIO[1:3]
Pin Name: pcs1_qgpio1 - pcs3_qgpio3 (3 pins)
PCS[1:3] – These signals provide three QSPI peripheral chip selects.
QGPIO[1:3] – When these pins are not needed for QSPI applications they can be configured as a general purpose input/output.
2.3.2.3 MISO/QGPIO[4]
Pin Name: miso_qgpio4
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
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USER’S MANUAL
Master-In Slave-Out (MISO) – This bi-directional signal furnishes serial data input to
the QSPI in master mode, and serial data output from the QSPI in slave mode.
QGPIO[4] – When this pin is not needed for a QSPI application it can be configured
as a general purpose input/output.
2.3.2.4 MOSI/QGPIO[5]
Pin Name: mosi_qgpio5
Master-Out Slave-In (MOSI) – This bi-directional signal furnishes serial data output
from the QSPI in master mode and serial data input to the QSPI in slave mode.
QGPIO[5] – When this pin is not needed for a QSPI application it can be configured
as a general purpose input/output.
2.3.2.5 SCK/QGPIO[6]
Pin Name: sck_qgpio6
SCK – This bi-directional signal furnishes the clock from the QSPI in master mode or
furnishes the clock to the QSPI in slave mode.
QGPIO[6] – When this pin is not needed for a QSPI application, it can be configured
as a general purpose input/output. When the QSPI is enabled for serial transmitting,
the pin can not function as a GPIO.
2.3.2.6 TXD[1:2]/QGPO[1:2]
Pin Name: txd1_qgpo1 - txd2_qgpo2 (2 pins)
Transmit Data – These output signals are the serial data outputs from the SCI1 and
SCI2.
QSCI GPO[1:2] – When these pins are not needed for a SCI applications, they can be
configured as general-purpose outputs. When the transmit enable bit in the SCI control
register is set to a logic 1, these pins can not function as general purpose outputs
2.3.2.7 RXD[1:2]/QGPI[1:2]
Pin Name: rxd1_qgpi1 - rxd2_qgpi2 (2 pins)
Receive Data – These input signals furnish serial data inputs to the SCI1 and SCI2.
QSCI GPI[1:2] – When these pins are not needed for SCI applications they can be
configured as general purpose inputs. When the receive enable bit in the SCI control
register is set to a logic 1, these pins can not function as general purpose inputs.
2.3.2.8 ECK
Pin Name: eck
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External Baud Clock (EBCK) – This signal provides an external baud clock used by
SCI1 and SCI2.
2.3.3 MIOS PADS
2.3.3.1 MDA[11], [13]
Pin Name: mda11, mda13 (2 pins)
Double Action – Each of these pins provide a path for two 16-bit input captures and
two 16-bit output compares.
Clock Input – Each of these pins provide a clock input to the modulus counter submodule. MDA11 can be used as the clock input to the MMCSM6 modulus counter.
MDA13 can be used as the clock input to the MMCSM22 modulus counter.
2.3.3.2 MDA[12], [14]
Pin Name: mda12, mda14, (2 pins)
Double Action – Each of these pins provide a path for two 16-bit input captures and
two 16-bit output compares.
Load Input – Each of these pins provide a load input to the modulus counter submodule. MDA12 can be used as the load input to the MMCSM6 modulus counter. MDA14
can be used as the load input to the MMCSM22 modulus counter.
2.3.3.3 MDA[15], [27:31]
Pin Name: mda15, mda27 - mda31 (6 pins)
Double Action – Each of these pins provide a path for two 16-bit input captures and
two 16-bit output compares.
2.3.3.4 MPWM[0:3], [16:19]
Pin Name: mpwm0 - mpwm3, mpwm16 - mpwm19 (8 pins)
Pulse Width Modulation – These pins provide variable pulse width output signals at
a wide range of frequencies.
2.3.3.5 VF[0:2]/MPIO32B[0:2]
Pin Name: vf0_mpio32b0 - vf2_mpio32b2 (3 pins)
Visible Instruction Queue Flush Status – These lines output by the chip when Program instruction flow tracking is required by the user. VF reports the number of
instructions flushed from the Instruction Queue in the Internal Core.
MIOS GPIO – This function allows the pins to be used as general-purpose inputs/
outputs.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
2.3.3.6 VFLS[0:1]/MPIO32B[3:4]
Pin Name: vfls0_mpio32b3 - vfls1_mpio32b4 (2 pins)
Visible History Buffer Flush Status – These signals are output by the chip to allow
program instruction flow tracking. They report the number of instructions flushed from
the history buffer in the RCPU. See SECTION 21 DEVELOPMENT SUPPORT for
details.
MIOS GPIO – This function allows the pins to be used as general purpose inputs/
outputs.
2.3.3.7 MPIO32B[5:15]
Pin Name: mpio32b5 - mpio32b15 (11 pins)
MIOS GPIO – This function allows the pins to be used as general purpose inputs/
outputs.
2.3.4 TPU_A/TPU_B PADS
2.3.4.1 TPUCH[0:15]
Pin Name: a_tpuch0 - a_tpuch15 (16 pins for first TPU), b_tpuch0 - b_tpuch15 (16
pins for second TPU)
TPU Channels – These signals provide each TPU with 16 input/output programmable
timed events.
2.3.4.2 T2CLK
Pin Name: a_t2clk (1 pin for first TPU), b_t2clk (1 pin for second TPU)
T2CLK – This signal is used to clock or gate the timer count register 2 (TCR2) within
the TPU. This pin is an output-only in special test mode.
2.3.5 QADC_A/QADC_B PADS
2.3.5.1 ETRIG[1:2]
Pin Name: etrig1 - etrig2
ETRIG – These are the external trigger inputs to the QADC_A and QADC_B modules.
ETRIG[1] can be configured to be used by both QADC_A and QADC_B. Likewise,
ETRIG[2] can be used for both QADC_B and QADC_A. The trigger input pins are
associated with the scan queues.
2.3.5.2 AN[0]/ANW/PQB[0]
Pin Name: a_an0_anw_pqb0 (1 pin for first QADC), b_an0_anw_pqb0 (1 pin for second QADC)
MPC555
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-25
Analog Channel (AN0) – Internally multiplexed input-only analog channels. Passed
on as a separate signal to the QADC.
Multiplexed Analog Input (ANW) – Externally multiplexed analog input.
Port (PQB0) – Input-only port. This is a 5-V input. This path is synchronized in the pad.
The input is level-shifted before it is sent internally to the QADC.
2.3.5.3 AN[1]/ANX/PQB[1]
Pin Name: a_an1_anx_pqb1 (1 pin for first QADC), b_an1_anx_pqb1 (1 pin for second QADC)
Analog Channel (AN1) – Internally multiplexed input-only analog channels. Passed
on as a separate signal to the QADC.
Multiplexed Analog Input (ANX) – Externally multiplexed analog input.
Port (PQB1) – Input-only port. This is a 5-V input. This path is synchronized in the pad.
The input is level-shifted before being sent internally to the QADC.
2.3.5.4 AN[2]/ANY/PQB[2]
Pin Name: a_an2_any_pqb2 (1 pin for first QADC), b_an2_any_pqb2 (1 pin for second QADC)
Analog Channel (AN2) – Internally multiplexed input-only analog channel. The input
is passed on as a separate signal to the QADC.
Multiplexed Analog Input (ANY) – Externally multiplexed analog input.
Port (PQB2) – Input-only port. This is a 5-V input. This path is synchronized in the pad.
The input is level-shifted before it is sent internally to the QADC.
2.3.5.5 AN[3]/ANZ/PQB[3]
Pin Name: a_an3_anz_pqb3 (1 pin for first QADC), b_an3_anz_pqb3 (1 pin for second QADC)
Analog Input (AN3) – Internally multiplexed input-only analog channel. The input is
passed on as a separate signal to the QADC.
Multiplexed Analog Input (ANZ) – Externally multiplexed analog input.
Port (PQB3) – Input-only port. This is a 5-V input. This path is synchronized in the pad.
The input is level-shifted before it is sent internally to the QADC.
2.3.5.6 AN[48:51]/PQB[4:7]
Pin Name: a_an48_pqb4 – a_an51_pqb7 (4 pins for first QADC), b_an48_pqb4 –
b_an51_pqb7 (4 pins for second QADC).
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Analog Input (AN[48:51]) – Analog Input channel. The input is passed on as a separate signal to the QADC.
Port (PQB[4:7]) – Input-only port. Has a synchronizer with an input enable and clock.
The input is level-shifted before it is sent internally to the QADC.
2.3.5.7 AN[52:54]/MA[0:2]/PQA[0:2]
Pin Name: a_an52_ma0_pqa0 – a_an54_ma2_pqa2 (3 pins for first QADC),
b_an52_ma0_pqa0 – b_an54_ma2_pqa2 (3 pins for second QADC).
Analog Input (AN[52:54]) – Input-only. The input is passed on as a separate signal
to the QADC.
Multiplexed Address (MA[0:2]) – Output. Provides a three-bit multiplexed address
output to the external multiplexer chip to allow selection of one of the eight inputs.
Port (PQA[0:2]) – Bi-directional.
2.3.5.8 AN[55:59]/PQA[3:7]
Pin Name: a_an55_pqa3 - a_an59_pqa7 (5 pins for first QADC), b_an55_pqa3 –
b_an59_pqa7 (5 pins for second QADC).
Analog Input (AN[55:59]) – Input-only. The input is passed on as a separate signal
to the QADC.
Port (PQA[3:7]) – Bi-directional.
2.3.5.9 VRH
Pin Name: vrh
VRH – Input pin for high reference voltage for the QADC_A and QADC_B modules.
2.3.5.10 VRL
Pin Name: vrl
VRL – Input pin for low reference voltage for the QADC_A and QADC_B modules.
2.3.5.11 VDDA
Pin Name: vdda
VDDA – Power supply input to analog subsystems of the QADC_A and QADC_B
modules.
2.3.5.12 VSSA
Pin Name: vssa
VSSA – Input. Ground level for analog subsystems of the QADC_A and QADC_B
modules.
MPC555
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Revised 1 March 1999
MOTOROLA
2-27
2.3.6 TOUCAN_A/TOUCAN_B PADS
2.3.6.1 CNTX0
Pin Name: a_cntx0 (1 pin for first CAN), b_cntx0 (1 pin for second CAN)
TouCAN Transmit Data 0 – This signal is the serial data output.
2.3.6.2 CNRX0
Pin Name: a_cnrx0 (1 pin for first CAN), b_cnrx0 (1 pin for second CAN)
TouCAN Receive Data – This signal furnishes serial input data.
2.3.7 CMF PADS
2.3.7.1 EPEE
Pin Name: epee
EPEE – Input. This control signal will externally control the program or erase
operations.
2.3.7.2 VPP
Pin Name: vpp
VPP – Input. Flash supply voltage (5-V supply) used during program and erase operations of the CMF.
2.3.7.3 VDDF
Pin Name: vddf
VDDF – Flash core voltage input (3-V supply). This separate supply voltage is needed
in order to reduce noise in the read path of CMF.
2.3.7.4 VSSF
Pin Name: vssf
VSSF – Flash core zero supply input. This separate supply is needed in order to
reduce noise in the read path of CMF.
2.3.8 GLOBAL POWER SUPPLIES
2.3.8.1 VDDL
Pin Name: vddl
VDDL – 3-V voltage supply input.
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USER’S MANUAL
2.3.8.2 VDDH
Pin Name: vddh
VDDH – 5-V voltage supply input.
2.3.8.3 VDDI
Pin Name: vddi
VDDI – 3-V voltage supply input for internal logic.
2.3.8.4 VSSI
Pin Name: vssi
VSSI – Zero supply input for internal logic. In packaged devices, VSSI is not a separate input from VSS.
2.3.8.5 KAPWR
Pin Name: kapwr
Keep-Alive Power – 3-V voltage supply input for the oscillator and keep-alive
registers.
2.3.8.6 VDDSRAM
Pin Name: vddsram
SRAM Keep-Alive Power – 3-V voltage supply input for the SRAM.
2.3.8.7 VSS
Pin Name: vss
VSS – Ground level reference input.
2.4 Reset State
All input pins, with the exception of the power supply and clock related pins, are
“weakly pulled” to a value during reset by a 130-microampere resistor based on certain
conditions. In reset state all I/O pins become inputs, and all outputs except clkout,
hreset_b, sreset_b, will be pulled only by the pull-up/pull-down.
2.4.1 Pin Functionality out of Reset
The functionality out of reset of some pins that support multiple functionality is defined
in the SIUMCR through the reset configuration word. For details on which multiplexed
pins are configured by the reset configuration word and how they are configured, refer
to 7.5.2 Hard Reset Configuration Word.
MPC555
USER’S MANUAL
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-29
The 3-V related pins have selectable output buffer drive strengths which are controlled
by the COM[0] bit in the USIU’s system clock and reset control register (SCCR). The
control is as follows:
0 = 3-V bus pins full drive (50-pF load)*
1 = 3-V bus pins reduced drive (25-pF load)
* The bus pin drive selectability definition is inverted from the selectability of the pin control in the PDMCR register
(for the TPU, QADC, USIU (SGPIO), QSPI, TouCAN, QSCI, and MIOS pins).
2.4.2 Pad Module Configuration Register (PDMCR)
The slew rate and weak pull-up/pull-down characteristics of some pins are controlled
by bits in the PDMCR. This register resides in the SIU memory map. The contents of
the PDMCR are illustrated below. The PORESET signal resets all the PDMCR bits
asynchronously.
.
PDMCR – Pad Module Configuration Register
0
1
2
3
SLRC0 SLRC1 SLRC2 SLRC3
4
5
Reserved
6
7
0x2F C03C
8
9
10
PRDS SPRDS
11
12
13
14
15
Reserved
HARD RESET:
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
0
0
0
0
0
0
0
0
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
.
RESERVED
HARD RESET:
0
0
0
0
0
0
0
0
0
Table 2-3 PDMCR Bit Settings
Bit(s)
Name
0
SLRC0
SLRC0 controls the slew rate of the following modules: TPU, QADC, USIU (SGPIO).
0 = Slow slew rate for pins. Controls slew rate pins of 200 ns.
1 = Normal slew rate for pins
1
SLRC1
SLRC1 controls the slew rate of the QSPI and TouCAN modules.
0 = Slow slew rate for pins. Controls slew rate pins of 50 ns.
1 = Normal slew rate for pins
2
SLRC2
SLRC2 controls the slew rate of the QSCI module.
0 = Slow slew rate for pins. Controls slew rate pins of 200 ns.
1 = Normal slew rate for pins
3
SLRC3
SLRC3 controls the slew rate of the MIOS module.
0 = Slow slew rate for pins. Controls slew rate pins of 200 ns.
1 = Normal slew rate for pins
4:5
—
6
PRDS
MOTOROLA
2-30
Description
Reserved
The PRDS bit is used to enable or disable the weak pull-up/pull-down devices in the pads related
to SGPIO and all pads related to IMB modules. Table 2-4 illustrates which pins are affected by
PRDS.
0 = Enable pull-up/pull-down devices
1 = Disable pull-up/pull-down devices
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-3 PDMCR Bit Settings (Continued)
Bit(s)
Name
Description
7
SPRDS
The SPRDS bit is used to enable or disable the weak pull-up/pull-down devices in special 3-V
only bus pads. See page XXXX of this document for more details on the how the pull-up/pulldown devices are enabled and disabled. Table 2-4 illustrates which pins are affected by SPRDS.
For more details on how this bit affects the pins see 2.4.7 Special Pull Resistor Disable Control
(SPRDS).
0 = Enable pull-up/pull-down devices
1 = Disable pull-up/pull-down devices
8:31
—
Reserved
2.4.3 Pin State During Reset
During reset, the functionality of some pins is undetermined. Their functionality is
based on the bits in the SIUMCR. Since the SIUMCR bits are undetermined during
reset, there is no way of predicting how the pins will function. However, the pins must
not cause any spurious conditions or consume an excessive amount of power during
reset. To prevent these conditions, the pins need to have a defined reset state. Table
2-4 describes the reset state of the pins based on pin functionality.
All pins are initialized to a “reset state” during reset. This state remains active until
reset is negated or until software disables the pull-up or pull-down device based on the
pin functionality. Upon assertion of the corresponding bits in the pin control registers
and negation of reset, the pin acquires the functionality that was programmed.
2.4.4 Power-On Reset and Hard Reset
Power-on reset and hard reset affect the functionality of the pins out of reset. (During
soft reset, the functionality of the pins is unaltered.) Upon assertion of the power-on
reset signal (PORESET) the functionality of the pin is not yet known. The pull-up or
pull-down resistors are enabled. The reset configuration word configures the system,
and towards the end of reset the pin functionality is known. Based upon pin functionality, the pull-up or pull-down devices are either disabled immediately at the negation
of reset or remain enabled.
Hard reset can occur at any time, and there may be a bus cycle pending. For this reason, the bits in PDMCR that control the enabling and disabling of the pull-up or pulldown resistors in the pads are set or reset synchronously. (PORESET affects these
bits asynchronously.) This causes the pull-up or pull-down resistors to be enabled at
a time when they do not cause contention on the pins and are disabled before they
can cause any contention on the pins.
2.4.5 Pull-Up and Pull-Down Enable and Disable for 5-V Only Pins
For 5-V only pins, the enabling and disabling of the pull-up and pull-down devices is
controlled by the PRDS bit in PDMCR. If the bit is negated, the devices are active. If
the bit is asserted, the devices are inactive.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-31
2.4.6 Pull-Up and Pull-Down Enable and Disable for 3-V / 5-V Multiplexed Pins
Two signals are needed to enable or disable the pull-up/pull-down devices in the 3-V
/ 5-V multiplexed pads:
• The PRDS signal
• An encoded 3-V / 5-V select
2.4.6.1 PRDS Signal
The PRDS signal is derived from the PRDS bit in the PDMCR. A single signal controls
all affected pads (all pads related to SGPIO and all pads related to the UIMB modules).
The bit is reset by default (pull-ups enabled) and must be explicitly set by software
after reset. The bit is reset immediately following power-on reset and by hard reset
after data coherency. This bit is not affected by soft reset.
2.4.6.2 Encoded 3-V / 5-V Select
This signal selects between the 3-V functionality and the 5-V functionality of the pin.
5-V operation is selected until the function of the pin is determined (based on the reset
configuration word) and PORESET is negated. At this point the 3-V / 5-V select signal
assumes the intended state (high for 5 V and low for 3 V).
Upon hard reset assertion, if the 3-V / 5-V select line is in 3-V select mode, it remains
in this mode until any external bus access completes. After this the 3-V / 5-V select
signal switches to 5-V mode to enable the pull-ups. This ensures that there is no contention on the bus due to the pull-up being enabled. This signal is not affected by soft
reset.
Each pad group has a 3-V / 5-V select signal. Internal to the pad, logic combines these
signals to control the pull-up.
2.4.6.3 Examples
The combination of this 3-V / 5-V select signal and the resistor disable signal enables
or disables the pull-up.The logic to enable the pull-up is:
pull_enable = PRDS & 3-V / 5-V select
For example, if a pin is configured a s a GPIO pin (5 V), The 3-V / 5-V select is high
throughout reset. This causes the pull-up to be enabled. At the end of reset, the 3-V /
5-V select line remains high. The PRDS is high by default until cleared by software.
This causes the pull-up to be enabled until software clears the PRDS bit in the
SIUMCR.
If a pin is configured as a bus pin (3 V), the 3 V / 5 V remains high throughout reset.
This causes the pull-up to be enabled. At the end of reset, the 3-V / 5-V select line goes
low. This causes the pull-up to be disabled, preventing any power loss if the MCU
starts fetching from external memory immediately out of reset.
MOTOROLA
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
2.4.7 Special Pull Resistor Disable Control (SPRDS)
For the pins that support debug and opcode-tracking functionality, the pull-up and pulldown resistors are controlled by the SPRDS signal, which is somewhat like the
encoded 3-V / 5-V select. During reset this signal is used synchronously to enable the
pull-up resistors in the pads. On negation of reset, based on which functionality is
selected for the pins, this signal is set to disable the pull-up resistors or remains held
in its reset state to indicate that the pull-ups are disabled only when the output driver
is enabled.
For example, if a pin is configured as a bus arbitration pin, The SPRDS signal remains
low throughout reset. This causes the pull-up to be enabled. When reset is released,
SPRDS remains low. The output enable for the driver is negated by default. When the
output driver is enabled, the pull-up is disabled.
When a pin is configured as an opcode-tracking or debug pin, SPRDS remains low
throughout reset. This causes the pull-up to be enabled. When reset is released,
SPRDS is asserted. This disables the pull-up resistor immediately. The output driver
drives the pin to the required state after reset.
2.4.8 Pin Reset States
Table 2-4 summarizes the reset states of all the pins on the MPC555.
Table 2-4 Pin Reset State
Pin
Function
Port
Voltage
Reset State
USIU
ADDR[8:31]/
SGPIOA[8:31]
DATA[0:31]/
SGPIOD[0:31]
ADDR[8:31]
I/O
3V
PU5 until reset negates1
SGPIOA[8:31]
IO
5V
PU5 until PRDS is set
DATA[0:31]
I/O
3V
PD until reset negates
SGPIOD[0:31]
I/O
5V
PD until PRDS is set
I
3V
PU5 until reset negates1
I/O
5V
PU5 until PRDS is set
IRQ[1]
I
3V
PU5 until reset negates1
RSV
O
3V
PU5 until reset negates1
SGPIOC[1]
I/O
5V
PU5 until PRDS is set
IRQ[2]
I
3V
PU5 until reset negates1
CR
I
3V
PU5 until reset negates1
SGPIOC[2]
I/O
5V
PU5 until PRDS is set
MTS
O
3V
PU5 until PRDS negates
IRQ[0]
IRQ[0]/SGPIOC[0]
SGPIOC[0]
IRQ[1]/
RSV/SGPIOC[1]
IRQ[2]/
CR/SGPIOC[2]/
MTS
MPC555
USER’S MANUAL
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-33
Table 2-4 Pin Reset State (Continued)
Pin
Port
Voltage
I
3V
PU5 until reset negates1
KR, RETRY
I/O
3V
PU5 when driver not enabled2
SGPIOC[3]
I/O
5V
PU5 until PRDS is set
IRQ[4]
I
3V
PU5 until reset negates1
AT[2]
O
3V
PU5 until reset negates1
SGPIOC[4]
I/O
5V
PU5 until PRDS is set
I
3V
PU5 until reset negates1
SGPIOC[5]
I/O
5V
PU5 until PRDS is set
MODCK[1]
I
3V
PU5 until reset negates1
IRQ[6:7]
I
3V
PU3 until SPRDS is set
MODCK[2:3]
I
3V
PU3 until reset negates
TSIZ[0:1]
I/O
3V
PD when driver not enabled or until SPRDS
is set
RD/WR
RD/WR
I/O
3V
PU3 when driver not enabled or until SPRDS
is set
BURST
BURST
I/O
3V
PU3 when driver not enabled or until SPRDS
is set
BDIP
I/O
3V
PU3 when driver not enabled or until SPRDS
is set
TS4
TS
I/O
3V
TA4
TA
I/O
3V
IRQ[3]/
KR, RETRY/
SGPIOC[3]
IRQ[4]/
AT[2]/
SGPIOC[4]
IRQ[5]/
SGPIOC[5]/
MODCK[1]3
IRQ[6:7]/
MODCK[2:3]3
TSIZ[0:1]
BDIP
TEA
RSTCONF/TEXP3
OE
Function
IRQ[3]
IRQ[5]
TEA
WE[0:3]/BE[0:3]/
AT[0:3]
PORESET3
MOTOROLA
2-34
PU3 when driver not enabled
or until SPRDS is set
PU3 when driver not enabled or until SPRDS
is set
PU3 when driver not enabled or until SPRDS
is set
I/O
3V
RSTCONF
I
3V
PU3 when driver not enabled
TEXP
O
3V
or until SPRDS is set
OE
O
3V
PU3 until reset negates
BI4
I/O
3V
PU3 when driver not enabled
STS
O
3V
or until SPRDS is set
CS[0:3]
O
3V
PU3 until reset negates
WE[0:3]/BE[0:3]
O
3V
PU3 when driver not enabled
AT[0:3]
O
3V
or until SPRDS is set
PORESET
I
3V
BI/STS
CS[0:3]
Reset State
An external pull-up is required in order to negate the pin in appropriate time
—
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-4 Pin Reset State (Continued)
Pin
HRESET3
SRESET3
Function
HRESET
Port
I/O
Voltage
3V
Reset State
PU3 when driver not enabled or until SPRDS
is set
An external pull-up is required in order to negate the pin in appropriate time
PU3 when driver not enabled or until SPRDS
is set
SRESET
I/O
3V
SGPIOC[6]
I/O
5V
PU5 until PRDS is set
FRZ
O
3V
PU5 until reset negates1
PTR
O
3V
PU5 until reset negates1
SGPIOC[7]
I/O
5V
PU5 until PRDS is set
IRQOUT
O
3V
PU5 until reset negates1
LWP[0]
O
3V
PU5 until reset negates1
BG
I/O
3V
VF[0]
O
3V
LWP[1]
O
3V
BR
I/O
3V
VF[1]
O
3V
IWP[2]
O
3V
BB4
I/O
3V
VF[2]
O
3V
IWP[3]
O
3V
IWP[0:1]
O
3V
VFLS[0:1]
O
3V
TMS
TMS
I
3V
TDI/
DSDI
TDI
I
3V
DSDI
I
3V
TCK/
DSCK
TCK
I
3V
DSCK
I
3V
TDO/
DSDO
TDO
O
3V
DSDO
O
3V
TRST
TRST
I
3V
PU3 until SPRDS is set
XTAL3
XTAL
I
3V
—
EXTAL
I
3V
—
XFC
I
3V
—
SGPIOC[6]/
FRZ/
PTR
SGPIOC[7/
IRQOUT/LWP[0]
BG/
VF[0]/
LWP[1]
BR/
VF[1]/
IWP[2]
BB/
VF[2]/
IWP[3]
IWP[0:1]/
VFLS[0:1]
EXTAL3
XFC
MPC555
USER’S MANUAL
An external pull-up is required in order to negate the pin in appropriate time
PU3 when driver not enabled
or until SPRDS is set
PU3 when driver not enabled
or until SPRDS is set
PU3 when driver not enabled
or until SPRDS is set
PU3 until reset negates
PU3 until SPRDS is set
PU3 until SPRDS is set
PD until SPRDS is set
PU3 until reset negates
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
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Table 2-4 Pin Reset State (Continued)
Pin
Function
Port
Voltage
Reset State
CLKOUT
CLKOUT
O
3V
—
EXTCLK3
EXTCLK
I
3V
—
ENGCLK/
BUCLK
ENGCLK
O
5V
—
BUCLK
O
5V
—
QSMCM
PCS0
I/O
5V
SS
I/O
5V
QGPIO[0]
I/O
5V
PCS[1:3]
I/O
5V
QGPIO[1:3]
I/O
5V
MISO/
QGPIO[4]
MISO
I/O
5V
QGPIO[4]
I/O
5V
MOSI/
QGPIO[5]
MOSI
I/O
5V
QGPIO[5]
I/O
5V
SCK/
QGPIO[6]
SCK
I/O
5V
QGPIO[6]
I/O
5V
TXD[1:2]/
QGPO[1:2]
TXD[1:2]
O
5V
QGPO[1:2]
O
5V
RXD[1:2]/
QGPI[1:2]
RXD[1:2]
I
5V
QGPI[1:2]
I
5V
ECK
I
5V
PCS0/
SS/
QGPIO[0]
PCS[1:3]/
QGPIO[1:3]
ECK
PU5 until PRDS is set
PU5 until PRDS is set
PU5 until PRDS is set
PU5 until PRDS is set
PU5 until PRDS is set
PU5 until PRDS is set
PU5 until PRDS is set
PU5 until PRDS is set
MIOS
MDA[4:13]
MDA[4:13]
I/O
5V
PU5 until PRDS is set
MPWM[0:3], [16:19]
I/O
5V
PU5 until PRDS is set
VF[0:2]/
MPIO32B[0:2]
VF[0:2]
O
3V
MPIO32B[0:2]
I/O
5V
VFLS[0:1]/
MPIO32B[3:4]
VFLS[0:1]
O
3V
MPIO32B[3:4]
I/O
5V
MPIO32B[5:15]
MPIO32B[5:15]
I/O
5V
MPWM[0:3],
[16:19]
PU5 until PRDS is set
PU5 until PRDS is set
PU5 until PRDS is set
TPU_A/TPU_B
A: TPUCH[0:15]
A: T2CLK
B: TPUCH[0:15]
B: T2CLK
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TPUCH[0:15]
I/O
5V
PU5 until PRDS is set
T2CLK
I/O
5V
PU5 when driver not enabled2
TPUCH[0:15]
I/O
5V
PU5 until PRDS is set
T2CLK
I/O
5V
PU5 when driver not enabled2
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-4 Pin Reset State (Continued)
Pin
Function
Port
Voltage
Reset State
QADC_A/QADC_B
ETRIG[1:2]
ETRIG[1:2]
I
5V
PD
AN0
I
5V
PU5 until PRDS is set
ANW
I
5V
PU5 until PRDS is set
PQB0
I
5V
PU5 until PRDS is set
AN1
I
5V
PU5 until PRDS is set
ANX
I
5V
PU5 until PRDS is set
PQB1
I
5V
PU5 until PRDS is set
AN2
I
5V
PU5 until PRDS is set
ANY
I
5V
PU5 until PRDS is set
PQB2
I
5V
PU5 until PRDS is set
AN3
I
5V
PU5 until PRDS is set
ANZ
I
5V
PU5 until PRDS is set
PQB3
I
5V
PU5 until PRDS is set
AN[48:51]
I
5V
PU5 until PRDS is set
PQB[4:7]
I
5V
PU5 until PRDS is set
AN[52:54]
I
5V
PU5 until PRDS is set
MA[0:2]
I
5V
PU5 until PRDS is set
PQA[0:2]
I/O
5V
PU5 until PRDS is set
A: AN[55:56]]/
PQA[3:4]
AN[55:56]
I
5V
PU5 until PRDS is set
PQA[3:4]
I/O
5V
PU5 until PRDS is set
A: AN[57:59]/
PQA[5:7]
AN[57:59]
I
5V
PU5 until PRDS is set
PQA[5:7]
I/O
5V
PU5 until PRDS is set
AN0
I
5V
PU5 until PRDS is set
ANW
I
5V
PU5 until PRDS is set
PQB0
I
5V
PU5 until PRDS is set
AN1
I
5V
PU5 until PRDS is set
ANX
I
5V
PU5 until PRDS is set
PQB1
I
5V
PU5 until PRDS is set
AN2
I
5V
PU5 until PRDS is set
ANY
I
5V
PU5 until PRDS is set
PQB2
I
5V
PU5 until PRDS is set
A: AN0/ANW/
PQB0
A: AN1/ANX/
PQB1
A: AN2/ANY/
PQB2
A: AN3/ANZ/
PQB3
A: AN[48:51]/
PQB[4:7]
A: AN[52:54]/
MA[0:2]/PQA[0:2]
B: AN0/ANW/
PQB0
B: AN1/ANX/
PQB1
B: AN2/ANY/
PQB2
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
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Table 2-4 Pin Reset State (Continued)
Pin
Port
Voltage
AN3
I
5V
PU5 until PRDS is set
ANZ
I
5V
PU5 until PRDS is set
PQB3
I
5V
PU5 until PRDS is set
AN[48:51]
I
5V
PU5 until PRDS is set
PQB[4:7]
I
5V
PU5 until PRDS is set
AN[52:54]
I
5V
PU5 until PRDS is set
MA[0:2]
I
5V
PU5 until PRDS is set
PQA[0:2]
I/O
5V
PU5 until PRDS is set
B: AN[55:56]/
PQA[3:4]
AN[55:56]
I
5V
PU5 until PRDS is set
PQA[3:4]
I/O
5V
PU5 until PRDS is set
B: AN[57:59]/
PQA[5:7]
AN[57:59]
I
5V
PU5 until PRDS is set
PQA[5:7]
I/O
5V
PU5 until PRDS is set
B: AN3/ANZ/
PQB3
B: AN[48:51]/
PQB[4:7]
B: AN[52:54]/
MA[0:2]/PQA[0:2]
Function
Reset State
VRH
VRH
I
5V
—
VRL
VRL
I
—
—
VDDA
VDDA
I
5V
—
VSSA
VSSA
I
—
—
TOUCAN_A/TOUCAN_B
A: CNTX0
A_CNTX0
O
5V
PU5 until PRDS is set
B: CNTX0
B_CNTX0
O
5V
PU5 until PRDS is set
A: CNRX0
A_CNRX0
I
5V
PU5 until PRDS is set
B: CNRX0
B_CNRX0
I
5V
PU5 until PRDS is set
CMF
EPEE
EPEE
I
3V
PD
VPP
I
5V
—
VDDF
VDDF
I
3V
—
VSSF
VSSF
I
3V
—
VPP
Global Power Supplies
VDDL
VDDL
I
3V
—
VDDH
VDDH
I
5V
—
VDDI
VDDSI
I
3V
—
VSSI
VSSI
I
3V
—
KAPWR
I
3V
—
VDDSRAM
I
3V
—
VDDSYN
I
3V
—
KAPWR3
VDDSRAM
VDDSYN
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-4 Pin Reset State (Continued)
Pin
Function
VSS
VSSSYN
Port
Voltage
VSS
I
—
—
VSSSYN
I
3V
—
Reset State
NOTES:
1. During reset, the output enable to the pad driver is negated and the PU3/PU5 is active. After reset is negated,
the output enable is continuously enabled and the PU3 is disabled. The driver is responsible for driving a
valid state on the pin.
2. Pull-up/pull-down is active when pin is defined as an input and/or during reset; therefore, output enable is
negated. This also means that external pull-up/pull-down is not required unless specified.
3. These pins are powered by KAPWR (Keep-Alive Power Supply).
4. This pin is an active negate signal and may need an external pull-up resister.
2.5 Pad Types
There are different pad types based on functional characteristics. Even pads with the
same functionality may be different due to different electrical characteristics. All 5-V
inputs have hysteresis. There is no synchronization in the pads; it is all in the modules.
2.5.1 Pad Interface Signals
The pad interface consists of an internal interface and an external interface. The external interface is to the pin. The internal interface is the set of signals that interface the
pad to the chip’s internal logic. The following internal interface signals are used:
• Data – The line driven from an internal module of the chip to the pad. For bi-directional pins, the internal interface may be a single line for both input and output
or two separate paths for input and output. The descriptions of individual pad
types specify which.
• 3-V / 5-V select – Selects a 3-V or 5-V driver, for pads that support both. This signal is driven from the USIU.
• Output enable (OE) – Enables the output driver. For 3-V / 5-V pads, the appropriate driver is enabled based on the pin functionality selected.
• Input enable – Enables the receiver. For 3-V / 5-V pads, the appropriate receiver
is enabled based on the pin functionality selected.
• Drive select – Selects the drive strength of the pad. For example, data pin drivers
can be configured to drive a 25-pF load or a 50-pF load.
• Synchronizer clock – Some pins have synchronizer logic to handle metastable
signals at the input of a pin. For pads that have synchronizers and support synchronized or normal data input, the corresponding interface signals to the internal
logic are “Normal Data In” and “Sync Data In.”
• Slew rate control – GPIO pins have slow slew rates, with edge rates in the range
of 90 ns to 600 ns. The slew rate and weak pull-up/pull-down characteristics of
these pins are controlled by bits in the PDMCR, see 2.4.2 Pad Module Configuration Register (PDMCR). For a description of PDMCR bits SLRC[0:3] that have
controllable slew rates, see Table 2-3.
• Hysteresis input – Slow pads contains hysteresis input buffers to reduce the sensitivity to noises. The input hyst_sel is used to configure the pad to provide hysteresis according to the pad configuration.
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• Open drain enable – For selected 3-V / 5-V pads, this signal determines the type
of drive (open drain or totem pole) seen at the pin.
• Pull resistor disable select (PRDS) – Reflects the state of the PRDS bit in the pad
module configuration register (PDMCR). This signal controls the pull-up/pulldown resistor for the SGPIO pins and the pins for the modules on the UIMB.
• Special pull resistor disable select (SPRDS) – Reflects the state of the SPRDS
bit in the PDMCR. For pins that support bus arbitration functionality multiplexed
with opcode-tracking and debug functionality, this signal controls the pull-up resistors.
• Analog – Analog input signals to the QADC. The corresponding digital interface
signals are referred to as “Dig. In” and Dig. Out”.
• JTAG – Joint Test Access Group related signals that are used for connectivity
tests at the board level. These signals are not shown in the pad block diagrams
in this section. In addition, the effect of the pull-up/pull-down resistors is not illustrated in the pad block diagrams.
These interface signals are referred to in the following pad descriptions and shown in
the pad diagrams.
2.5.2 Three-Volt Output Pad
The output driver of a 3-V output-only pad can be configured to drive a 25-pF or 50-pF
load. There are two subtypes: one with a pull-up device and the other with a pull-down
device. The SPRDS and OE signals enable the pull-up and pull-down resistors.
2.5.2.1 Type A Interface
This pad has a pull-up device to 3 V which can be conditionally turned off based on the
value placed on OE. For a totem pole (push pull) pin with no three-state drive time, the
OE can be connected to VDD, indicating a continuous drive. For a continuous drive,
the pull-up can be disabled.
3V
Drive Sel
Sprds
Data Out
Logic
3-V
Driver
Pin
OE
Figure 2-3 Type A Interface
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SIGNAL DESCRIPTIONS
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USER’S MANUAL
2.5.2.2 Type B Interface (Clock Pad)
The pad has a capability to select the buffer for the appropriate load (45 or 90 pF). The
OE input drives the totem pole output or three-states the output.
Drive Sel
Data Out
Logic
3-V
Driver
Pin
OE
Figure 2-4 Type B Interface
2.5.3 Three-Volt Input Pad
Four subtypes are defined for the 3-V input-only pad: one with a pull-up resistor, one
with a pull-up resistor and with or without hysteresis in the receiver, one with hysteresis
(no resistor), and one with a pull-down resistor. The SPRDS signal may disable the
pull-up or pull-down resistor.
2.5.3.1 Type C Interface
The type C interface has a 3-V input with a pull-up resistor.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
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3V
Data In
Sprds
3-V
Pin
Receiver
Figure 2-5 Type C Interface
2.5.3.2 Type CH Interface
Pad type CH has a 3-V input with hysteresis and a pull-up resistor. The hyst_sel
signal selects the receiver with or without hysteresis.
3V
Data In
Receiver
Sprds
3V
hyst_sel
Pin
3V
Figure 2-6 Type CH Interface
2.5.3.3 Type CNH Interface
The CNH pad type has a 3-V input with hysteresis but no pull-up or pull-down device.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
3V
Data In
3-V
Pin
Receiver
Figure 2-7 Type CNH Interface
2.5.3.4 Type D Interface
This type of pad has a 3-V input and an internal pull-down resistor.
3V
Data In
3-V
Pin
Receiver
Sprds
Figure 2-8 Type D Interface
2.5.4 Three-Volt Input/Output Pad
This is a 3-V bi-directional pad with a pull-up device. The drive strength for the output
driver can be configured for either a 25-pF or a 50-pF load. The SPRDS and OE signals control the pull-up devices.
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2.5.4.1 Type E Interface
In this pad type the data interface to the internal logic has separate paths for input and
output. This pad also has a open drain enable input. For totem pole driven outputs, the
signal is connected to VSS to disable the open-drain drive.
3V
OD Enable
Drive Sel
Sprds
Data Out
OE
Logic
3-V
Driver
Pin
Data In
IE
3-V
Receiver
Figure 2-9 Type E Interface
2.5.4.2 Type EOH Interface
In this pad type the data interface to the internal logic has separate paths for input and
output. The receiver has hysteresis. The pull-up is active when the driver is not
enabled.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
3V
Drive Sel
Sprds
Data Out
Logic
OE
Data In
Pin
3-V
OD Driver
3-V
Receiver
IE
Figure 2-10 3-V Type EOH Interface
2.5.4.3 Type F Interface
In this pad type the data interface to the internal logic has the same path for both input
and output. The pull-up is inactive when the driver is enabled.
3V
Drive Sel
Sprds
Data IO
OE
IE
Logic
3-V
Driver
Pin
3-V
Receiver
Figure 2-11 Type F Interface
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SIGNAL DESCRIPTIONS
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2.5.4.4 Type G Interface
In this pad type the data interface to the internal logic has the same path for both input
and output. This pad type also has the SPRDS signal as an input to disable the resistor
when the pad is a non-bus function.
3V
Sprds
Drive Sel
Data Out
OE
Data In
IE
Logic
3-V
Driver
Pin
3-V
Receiver
Figure 2-12 Type G Interface
2.5.5 Five-Volt Input/Output Pad
This pad type is for 5-V bi-directional pins. There is provision to pull the pin up to 5 V
and logic to control when the pull-up is enabled. For a 5-V driver, the internal “Fast
Mode” signal selects the slow or fast driver. All 5-V inputs have hyteresis.
2.5.5.1 Type H Interface
This pad has logic for a 3-V output function as well as a 5-V input-output function. A
“3-V / 5-V sel” interface signal determines which driver gets selected.
This pad type has two separate data output paths. These paths are multiplexed onto
the output pin based on the 3-V / 5-V select signal. This pad also has a dedicated synchronous input path.
If only one of the output paths is required, the other can be connected to ground. In
this case, the 3-V / 5-V select signal must be tied to the appropriate value to disable
the other path.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
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USER’S MANUAL
5V
3-V / 5-V Sel
PRDS
Drive Sel
5V
5 V Data Out
3 V Data Out
Pin
Logic
Driver
3V
OE
SLRC
Synch.
Data In
Synch. Clk
5-V
Synch.
Receiver
Figure 2-13 Type H Interface
2.5.5.2 Type I Interface
This pad has logic for a 3-V input/output function as well as a 5-V input/output function.
A “3-V / 5-V sel” interface signal indicates which driver gets selected.The data interface to the internal logic has separate paths for input and output.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
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5V
3-V / 5-V Sel
PRDS
5V
Data Out
OE
Pin
Logic
Driver
3V
Drive Sel
SLRC
Data In
IE
5V
Receiver
3V
Figure 2-14 Type I Interface
2.5.5.3 Type IH Interface
This pad has logic for a 3-V input/output function as well as a 5-V input/output function.
A “3-V / 5-V sel” interface signal determines which driver gets selected.
In this pad type the data interface to the internal logic has separate paths for input and
output. The 3-V receiver has 2 possible paths: with or without hysteresis. The hyst_sel
signal selects the appropriate path.
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SIGNAL DESCRIPTIONS
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USER’S MANUAL
5V
3-V / 5-V Sel
PRDS
5V
Data Out
OE
Pin
Logic
Driver
3V
Drive Sel
SLRC
Data In
IE
5V
Receiver
3V
hyst_sel
3V
Figure 2-15 Type IH Interface
2.5.5.4 Type J Interface
This pad has logic for a 3-V input/output function as well as a 5-V input/output function.
A “3-V / 5-V sel” interface signal indicates which driver gets selected. The data interface to the internal logic has the same path for both input and output.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
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5V
3-V / 5-V Sel
PRDS
5V
Data
OE
Pin
Logic
Driver
Drive Sel
3V
SLRC
5V
IE
Receiver
3V
Figure 2-16 Type J Interface
2.5.5.5 Type JD Interface
This pad has logic for a 3-V input/output function as well as a 5-V input/output function.
A “3-V / 5-V sel” interface signal indicates which driver gets selected.
The data interface to the internal logic has the same path for both input and output.
The pad has a pull-down resistor which is activated by reset and/or PRDS.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
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USER’S MANUAL
3-V / 5-V Sel
PRDS
5V
Data
OE
Pin
Logic
Driver
3V
Drive Sel
SLRC
5V
IE
Receiver
3V
Figure 2-17 Type JD Interface
2.5.6 Type K Interface (EPEE Pad)
This pad has a pull-down device that is enabled at all times. The module checks to see
that a transition to a new state on the pin is maintained for at least two clocks before
the information is passed on internally to the sequencer implemented in the flash. The
synchronizer clock to this pad is GCLK2.
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SIGNAL DESCRIPTIONS
Revised 1 March 1999
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Data
Synch. Clk
0
1
1
1
0
Pin
1
1
0
0
1
0
0
Sequencer
Figure 2-18 EPEE Pad (Type K)
2.5.7 Analog Pads
The 5-V analog pads interface to the QADC modules internally. They have separate
analog and digital paths in the pad in order to implement the functionality that is multiplexed on the pin.
2.5.7.1 Type L Interface (QADC Port A)
This pad is used for interfacing to the port A of the QADC. The digital portion of the
pad supports bi-directional operation. The receiver has a synchronizer. The digital
input is level-shifted from 5 V to 3 V before it is sent internally to the QADC.
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SIGNAL DESCRIPTIONS
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USER’S MANUAL
5V
PRDS
Analog In
Analog
Dig. Out
Data Direction
Pin
OD Driver
Dig. In
Input Enable
Level
Shifter
Synch. Rx
Sync. Clk
Digital
Figure 2-19 Type L Interface
2.5.7.2 Type M Interface (QADC Port B)
This pad is used for interfacing to port B of the QADC. This is an input-only pad.
The receiver has a synchronizer. The digital input is level-shifted from 5 V to 3 V
before it is sent internally to the QADC.
5V
PRDS
Analog In
Analog
PRDS
Pin
Dig. In
Input Enable
Synch. Rx
Level
Shifter
Sync. Clk
Digital
Figure 2-20 Type M Interface
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2.5.7.3 Type N Interface (ETRIG)
This is the pad for the ETRIG function of the QADC. The input signal is level-shifted
before being sent to the QADC module. The pad also serves as an output pad in test
mode.
5V
Input Enable
Dig. In
Pin
Synch. Rx
Sync. Clk
Digital
Figure 2-21 Type N Interface
2.5.8 Pads with Fast Mode
The type O pads (for interfacing to the QSMCM) and type P pads (for interfacing to the
TPU and MIOS) have a fast mode provision.
2.5.8.1 Type O Interface (QSMCM Pads)
This pad is used for interfacing to the QSMCM. It is a 5-V, bi-directional pad and has
provision for a fast mode in which the slow slew rate driver is bypassed and data is
driven by a fast slew rate driver. When the pin is an input, the data can be driven either
synchronously or asynchronously. A pull-up device is available which can be disabled
using the PRDS signal.
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USER’S MANUAL
5V
SLRC
5-V
Driver
Slow
OD Enable
PRDS
Data Out
Logic
OE
5-V
Driver
Fast
Pin
Normal
Data In
5-V
Receiver
Synch.
5-V
Synch.
Receiver
Data In
Synch. Clk
Figure 2-22 Type O Interface
2.5.8.2 Type P Interface (TPU and MIOS Pads)
This is a 5-V, bi-directional pad that has a fast mode provision like the QSMCM pads.
The input path is always synchronous. The receiver has hysteresis in order to minimize the effect of noise on the pins. In addition, the receiver has a digital filter (somewhat like the sequencer for the EPEE pad) to check for a state on the pin for a
particular number of clocks. The pad also has a pull-up device. Depending on the reset
state (see Table 2-4) the pull-up may be controlled by the PRDS signal.
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5V
SLRC
5-V
Driver
Slow
PRDS
Data Out
5-V
Driver
Fast
Logic
OE
Pin
5-V
Synch.
Hysteresis
Receiver
Synch.
Data In
Synch. Clk
Figure 2-23 Type P Interface
2.5.9 5V Input, 5V Output Pads
These pads are 5-V only pads.
2.5.9.1 5V Output (Type Q)
This pad is a 5-V output-only pad with slow and fast drive capability. The driver is configureable to be either push pull or open drain using the OD enable signal. This pad
type has a pull-up device that can be controlled using the PRDS signal.
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MPC555
USER’S MANUAL
5V
PRDS
OD Enable
Data Out
5-V
Driver
Slow
Logic
OE
SLRC
Pin
5-V
Driver
Fast
Figure 2-24 Type Q Interface
2.5.9.2 Type R Interface
This is a 5-V input-only pad with a synchronous and asynchronous receiver. Both
synchronous and asynchronous data are driven in from the internal module that
interfaces to this pad. A pull-up device can be controlled using the PRDS signal.
5V
PRDS
Normal
Data In
Synch.
Data In
Synch. Clk
5-V
Receiver
Pin
5-V
Synch.
Receiver
Figure 2-25 Type R Interface
MPC555
USER’S MANUAL
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-57
2.5.9.3 5V Output for Clock Pad
This interface is used for a 5-V clock pad output. The drive select signal selects the
buffer for a 45- or 90-pF load.
Drive Sel
5-V
Data Out
Logic
Pin
Driver
OE
Figure 2-26 Type S Interface
2.6 Pad Groups
A pad group is a set of pins that exhibits similar functional characteristics. Within a
group the individual pads may be of different types. The functionality of some pins
is defined based on the control bits that are set in the SIUMCR from the reset
configuration word. Refer to the section on pin functionality out of reset in the
reset section of the document.
The following is a list of pad groups which were obtained based on the 3-V / 5-V
selection from the information in the “pin configuration out of reset” tables. In other
words, each group receives a different encoded 3-V / 5-V select signal.
Table 2-5 Pad Groups Based on 3-V / 5-V Select
Group
Pins
1
FRZ/PTR/SGPIOC[6], SGPIO[7]/IRQOUT/LWP[0]
2
DATA[0:31]/SGPIOD[0:31]
3
ADDR[8:31]/SGPIOA[8:31]
4
IRQ[0]/SGPIOC[0], IRQ[1]/SGPIOC[1], IRQ[4]/SGPIOC[4]
5
IRQ[2]/SGPIOC[2], IRQ[3]/SGPIOC[3], IRQ[5]/SGPIOC[5]
All pins that drive 3 V have the provision to choose between drive strengths for a
25-pF load or a 50-pF load.
MOTOROLA
2-58
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
2.7 Pin Names and Abbreviations
The following table lists the recommended abbreviations for all the pins on the
MPC555. The abbreviations can be used in applications for which the actual name
is too long. For example, they can be used to on circuit boards to map the pin
location on the boards.
Table 2-6 Pin Names and Abbreviations
Pin List
Pin Name
addr_sgpioa[8]
ADDR[8:31]/SGPIOA[8:31]
MPC555
USER’S MANUAL
Abbreviation
addr_sgp[8]
Ball
V6
addr_sgpioa[9]
addr_sgp[9]
V5
addr_sgpioa[10]
addr_sgp[10]
V4
addr_sgpioa[11]
addr_sgp[11]
V3
addr_sgpioa[12]
addr_sgp[12]
W1
addr_sgpioa[13]
addr_sgp[13]
Y2
addr_sgpioa[14]
addr_sgp[14]
W3
addr_sgpioa[15]
addr_sgp[15]
Y3
addr_sgpioa[16]
addr_sgp[16]
W4
addr_sgpioa[17]
addr_sgp[17]
Y4
addr_sgpioa[18]
addr_sgp[18]
W5
addr_sgpioa[19]
addr_sgp[19]
Y5
addr_sgpioa[20]
addr_sgp[20]
W6
addr_sgpioa[21]
addr_sgp[21]
Y6
addr_sgpioa[22]
addr_sgp[22]
V7
addr_sgpioa[23]
addr_sgp[23]
W7
addr_sgpioa[24]
addr_sgp[24]
Y7
addr_sgpioa[25]
addr_sgp[25]
Y8
addr_sgpioa[26]
addr_sgp[26]
W8
addr_sgpioa[27]
addr_sgp[27]
V8
addr_sgpioa[28]
addr_sgp[28]
U8
addr_sgpioa[29]
addr_sgp[29]
U9
addr_sgpioa[30]
addr_sgp[30]
U7
addr_sgpioa[31]
addr_sgp[31]
U6
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-59
Table 2-6 Pin Names and Abbreviations (Continued)
Pin List
DATA[0:31]/SGPIOD[0:31]
IRQ[0]/SGPIOC[0]
IRQ[1]/RSV/SGPIOC[1]
IRQ[2]/CR/SGPIOC[2]/MTS
IRQ[3]/KR, RETRY/SGPIOC[3]
IRQ[4]/AT[2]/SGPIOC[4]
IRQ[5]/SGPIOC[5]/MODCK[1]
IRQ[6:7]/MODCK[2:3]
TSIZ[0:1]
MOTOROLA
2-60
Pin Name
Abbreviation
Ball
data_sgpiod[0]
data_sgp[0]
Y9
data_sgpiod[1]
data_sgp[1]
W9
data_sgpiod[2]
data_sgp[2]
Y10
data_sgpiod[3]
data_sgp[3]
W10
data_sgpiod[4]
data_sgp[4]
Y11
data_sgpiod[5]
data_sgp[5]
W11
data_sgpiod[6]
data_sgp[6]
Y12
data_sgpiod[7]
data_sgp[7]
W12
data_sgpiod[8]
data_sgp[8]
Y13
data_sgpiod[9]
data_sgp[9]
W13
data_sgpiod[10]
data_sgp[10]
Y14
data_sgpiod[11]
data_sgp[11]
W14
data_sgpiod[12]
data_sgp[12]
Y15
data_sgpiod[13]
data_sgp[13]
W15
data_sgpiod[14]
data_sgp[14]
Y16
data_sgpiod[15]
data_sgp[15]
W16
data_sgpiod[16]
data_sgp[16]
Y17
data_sgpiod[17]
data_sgp[17]
W17
data_sgpiod[18]
data_sgp[18]
V17
data_sgpiod[19]
data_sgp[19]
V16
data_sgpiod[20]
data_sgp[20]
U16
data_sgpiod[21]
data_sgp[21]
V15
data_sgpiod[22]
data_sgp[22]
V14
data_sgpiod[23]
data_sgp[23]
U14
data_sgpiod[24]
data_sgp[24]
V13
data_sgpiod[25]
data_sgp[25]
U13
data_sgpiod[26]
data_sgp[26]
V12
data_sgpiod[27]
data_sgp[27]
U12
data_sgpiod[28]
data_sgp[28]
V11
data_sgpiod[29]
data_sgp[29]
U11
data_sgpiod[30]
data_sgp[30]
V10
data_sgpiod[31]
data_sgp[31]
V9
irq0_b_sgpioc0
irq0b_sgp
M1
irq1_b_rsv_b_sgpioc1
irq1b_sgp
M2
irq2_b_cr_b_sgpioc2_mts
irq2b_sgp
M3
irq3_b_kr_b_retry_b_sgpioc3 irq3b_sgp
L3
irq4_b_at2_sgpioc4
irq4b_sgp
L4
irq5_b_sgpioc5_modck1
irq5b_sgp
W18
irq6_b_modck2
irq6b_mck2
Y18
irq7_b_modck3
irq7b_mck3
Y19
tsiz0
tsiz0
U1
tsiz1
tsiz1
T3
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-6 Pin Names and Abbreviations (Continued)
Pin List
Pin Name
Abbreviation
Ball
RD/ WR
rd_wr_b
rd_wrb
R1
BURST
burst_b
burstb
V1
BDIP
bdip_b
bdipb
U4
TS
ts_b
tsb
U3
TA
ta_b
tab
U2
TEA
tea_b
teab
T2
rstconf_b_texp
rcfb_txp
oe_b
oeb
T1
bi_b_sts_b
bib_stsb
V2
cs0_b
cs0b
P4
cs1_b
cs1b
R4
cs2_b
cs2b
R3
cs3_b
cs3b
R2
we_b_we_b_at[0]
web_at[0]
N1
we_b_we_b_at[1]
web_at[1]
P1
we_b_we_b_at[2]
web_at[2]
P2
RSTCONF/TEXP
OE
BI/STS
CS[0:3]
WE[0:3]/BE[0:3]/AT[0:3]
U17
we_b_we_b_at[3]
web_at[3]
P3
PORESET
poreset_b
poresetb
V19
HRESET
hreset_b
hresetb
W20
SRESET
sreset_b
sresetb
V20
sgpioc6_frz_ptr_b
sgp_frz
K3
sgpioc7_irqout_b_lwp0
sgp_irqoutb
M4
BG/VF[0]/LWP[1]
bg_b_vf0_lwp1
bgb_lwp1
N3
BR/VF[1]/IWP[2]
br_b_vf1_iwp2
brb_iwp2
N2
SGPIOC[6]/FRZ/PTR/
SGPIOC[7]/IRQOUT/LWP[0]
BB/VF[2]/IWP[3]
IWP[0:1]/VFLS[0:1]
TMS
bb_b_vf2_iwp3
bbb_iwp3
N4
iwp0_vfls0
iwp0_vfls
L2
iwp1_vfls1
iwp1_vfls
L1
tms
tms
K1
TDI/DSDI
tdi_dsdi
tdi_dsdi
K2
TCK/DSCK
tck_dsck
tck_dsck
J1
TDO/DSDO
tdo_dsdo
tdo_dsdo
J2
TRST
trst_b
trst_b
J3
XTAL
xtal
xtal
U20
EXTAL
extal
extal
T20
xfc
xfc
R19
clkout
clkout
V18
XFC
CLKOUT
EXTCLK
extclk
extclk
U18
VDDSYN
vddsyn
vddsyn
R20
VSSSYN
vsssyn
vsssyn
T19
engclk_buclk
eck_buck
U19
ENGCLK/BUCLK
MPC555
USER’S MANUAL
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-61
Table 2-6 Pin Names and Abbreviations (Continued)
Pin List
Pin Name
Abbreviation
Ball
QSMCM
PCS0/SS/QGPIO[0]
PCS[1:3]/QGPIO[1:3]
pcs0_ss_b_qgpio0
pcs0_qgp
L18
pcs1_qgpio1
pcs1_qgp
L17
pcs2_qgpio2
pcs2_qgp
M18
pcs3_qgpio3
pcs3_qgp
M17
MISO/QGPIO[4]
miso_qgpio4
miso_qgp4
L19
MOSI/QGPIO[5]
mosi_qgpio5
mosi_qgp5
L20
SCK/QGPIO[6]
sck_qgpio6
sck_qgp6
M20
txd1_qgpo1
txd1_qgpo
N18
txd2_qgpo2
txd2_qgpo
N20
rxd1_qgpi1
rxd1_qgpi
N17
rxd2_qgpi2
rxd2_qgpi
N19
eck
eck
M19
mda11
mda11
A17
mda12
mda12
A18
mda13
mda13
A19
mda14
mda14
B17
mda15
mda15
B18
mda27
mda27
C17
mda28
mda28
B20
mda29
mda29
C18
mda30
mda30
C19
mda31
mda31
C20
mpwm0
mpwm0
E17
mpwm1
mpwm1
D18
mpwm2
mpwm2
D19
mpwm3
mpwm3
D20
TXD[1:2]/QGPO[1:2]
RXD[1:2]/QGPI[1:2]
ECK
MIOS
MDA[11:15]
MDA[27:31]
MPWM[0:3], [16:19]
VF[0:2]/MPIO32B[0:2]
VFLS[0:1]/MPIO32B[3:4]
MOTOROLA
2-62
mpwm16
mpwm16
F17
mpwm17
mpwm17
E18
mpwm18
mpwm18
F18
mpwm19
mpwm19
E19
vf0_mpio32b0
vf0_mpio0
J19
vf1_mpio32b1
vf1_mpio1
J20
vf2_mpio32b2
vf2_mpio2
J17
vfls0_mpio32b3
vfls0_mpio3
J18
vfls1_mpio32b4
vfls1_mpio4
K18
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-6 Pin Names and Abbreviations (Continued)
Pin List
MPIO32B[5:15]
Pin Name
Abbreviation
Ball
mpio32b5
mpio5
G17
mpio32b6
mpio6
E20
mpio32b7
mpio7
F19
mpio32b8
mpio8
G18
mpio32b9
mpio9
F20
mpio32b10
mpio10
H17
mpio32b11
mpio11
G19
mpio32b12
mpio12
G20
mpio32b13
mpio13
H20
mpio32b14
mpio14
H19
mpio32b15
mpio15
H18
a_tpuch0
a_tpuch0
D3
a_tpuch1
a_tpuch1
A2
a_tpuch2
a_tpuch2
D4
a_tpuch3
a_tpuch3
C3
a_tpuch4
a_tpuch4
A3
a_tpuch5
a_tpuch5
D5
a_tpuch6
a_tpuch6
B3
a_tpuch7
a_tpuch7
C4
a_tpuch8
a_tpuch8
A4
a_tpuch9
a_tpuch9
C5
a_tpuch10
a_tpuch10
B4
a_tpuch11
a_tpuch11
B5
a_tpuch12
a_tpuch12
A5
a_tpuch13
a_tpuch13
C6
a_tpuch14
a_tpuch14
B6
a_tpuch15
a_tpuch15
A6
a_t2clk
a_t2clk
C2
TPU_A/TPU_B
A: TPUCH[0:15]
A: T2CLK
MPC555
USER’S MANUAL
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MOTOROLA
2-63
Table 2-6 Pin Names and Abbreviations (Continued)
Pin List
B: TPUCH[0:15]
B: T2CLK
Pin Name
Abbreviation
Ball
b_tpuch0
b_tpuch0
H2
b_tpuch1
b_tpuch1
H1
b_tpuch2
b_tpuch2
G1
b_tpuch3
b_tpuch3
G2
b_tpuch4
b_tpuch4
G3
b_tpuch5
b_tpuch5
F1
b_tpuch6
b_tpuch6
F2
b_tpuch7
b_tpuch7
E1
b_tpuch8
b_tpuch8
F3
b_tpuch9
b_tpuch9
G4
b_tpuch10
b_tpuch10
E2
b_tpuch11
b_tpuch11
D1
b_tpuch12
b_tpuch12
F4
b_tpuch13
b_tpuch13
D2
b_tpuch14
b_tpuch14
E3
b_tpuch15
b_tpuch15
C1
b_t2clk
b_t2clk
B1
QADC_A/QADC_B
etrig1
etrig1
C16
etrig2
etrig2
B16
A: AN0/ANW/PQB0
a_an0_anw_pqb0
aan0_pqb0
A8
A: AN1/ANX/PQB1
a_an1_anx_pqb1
aan1_pqb1
D8
A: AN2/ANY/PQB2
a_an2_any_pqb2
aan2_pqb2
C8
A: AN3/ANZ/PQB3
a_an3_anz_pqb3
aan3_pqb3
B8
a_an48_pqb4
aan48_pqb4
A9
a_an49_pqb5
aan49_pqb5
B9
a_an50_pqb6
aan50_pqb6
D9
a_an51_pqb7
aan51_pqb7
C9
a_an52_ma0_pqa0
aan52_pqa0
A10
a_an53_ma1_pqa1
aan53_pqa1
B10
a_an54_ma2_pqa2
aan54_pqa2
A11
a_an55_pqa3
aan55_pqa3
D10
a_an56_pqa4
aan56_pqa4
C10
a_an57_pqa5
aan57_pqa5
B11
a_an58_pqa6
aan58_pqa6
D11
a_an59_pqa7
aan59_pqa7
C11
ETRIG[1:2]
A: AN[48:51]/PQB[4:7]
A: AN[52:54]/MA[0:2]/PQA[0:2]
A: AN[55:56]]/PQA[3:4]
A: AN[57:59]/PQA[5:7]
B: AN0/ANW/PQB0
b_an0_anw_pqb0
ban0_pqb0
A12
B: AN1/ANX/PQB1
b_an1_anx_pqb1
ban1_pqb1
B12
B: AN2/ANY/PQB2
b_an2_any_pqb2
ban2_pqb2
A13
B: AN3/ANZ/PQB3
b_an3_anz_pqb3
ban3_pqb3
A14
MOTOROLA
2-64
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 2-6 Pin Names and Abbreviations (Continued)
Pin List
Pin Name
Abbreviation
Ball
b_an48_pqb4
ban48_pqb4
B13
b_an49_pqb5
ban49_pqb5
C12
b_an50_pqb6
ban50_pqb6
D12
b_an51_pqb7
ban51_pqb7
A15
b_an52_ma0_pqa0
ban52_pqa0
B14
b_an53_ma1_pqa1
ban53_pqa1
C13
b_an54_ma2_pqa2
ban54_pqa2
B15
b_an55_pqa3
ban55_pqa3
D13
b_an56_pqa4
ban56_pqa4
C14
b_an57_pqa5
ban57_pqa5
C15
b_an58_pqa6
ban58_pqa6
D14
b_an59_pqa7
ban59_pqa7
D15
VRH
vrh
vrh
B7
VRL
vrl
vrl
A7
VDDA
vdda
vdda
C7
VSSA
vssa
vssa
D7
B: AN[48:51]/PQB[4:7]
B: AN[52:54]/MA[0:2]/PQA[0:2]
B: AN[55:56]/PQA[3:4]
B: AN[57:59]/PQA[5:7]
TOUCAN_A/TOUCAN_B
A: CNTX0
a_cntx0
a_cntx0
K19
B: CNTX0
b_cntx0
b_cntx0
H4
A: CNRX0
a_cnrx0
a_cnrx0
K20
b_cnrx0
b_cnrx0
H3
epee
epee
P18
VPP
vpp
vpp
P17
VDDF
vddf
vddf
R18
VSSF
vssf
vssf
P19
B: CNRX0
CMF
EPEE
Global Power Supplies
VDDL
vddl
vddl
D17, E4, K4, K17,
R17. T4, U10,
U15
VDDH
vddh
vddh
A1, A16, A20, B2,
B19, P20, Y1,
Y20, W2, W19
VDDI
vddi
vddi
T17, U5, D6, D16
kapwr
kapwr
vddsram
vddsram
KAPWR
VDDSRAM
VSS
MPC555
USER’S MANUAL
vss
SIGNAL DESCRIPTIONS
Revised 1 March 1999
vss
T18
J4
J9, J10, J11, J12,
K9, K10, K11,
K12, L9, L10,
L11, L12, M9,
M10, M11, M12
MOTOROLA
2-65
MOTOROLA
2-66
SIGNAL DESCRIPTIONS
Revised 1 March 1999
MPC555
USER’S MANUAL
SECTION 3
CENTRAL PROCESSING UNIT
The PowerPC-based RISC processor (RCPU) used in the MPC500 family of microcontrollers integrates five independent execution units: an integer unit (IU), a load/
store unit (LSU), and a branch processing unit (BPU), floating-point unit (FPU) and
integer multiplier divider (IMD). The use of simple instructions with rapid execution
times yields high efficiency and throughput for MPC555-based systems.
Most integer instructions execute in one clock cycle. Instructions can complete out of
order for increased performance; however, the processor makes execution appear
sequential.
This section provides an overview of the RCPU. For a detailed description of this processor, refer to the RCPU Reference Manual (RCPURM/AD).
3.1 RCPU Features
Major features of the RCPU include the following:
• High-performance microprocessor
— Single clock-cycle execution for many instructions
• Five independent execution units and two register files
— Independent LSU for load and store operations
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— Thirty-two general-purpose registers (GPRs) for integer operands
— Thirty-two floating-point registers (FPRs) for single- or double-precision operands
• Facilities for enhanced system performance
— Programmable big- and little-endian byte ordering
— Atomic memory references
• In-system testability and debugging features
• High instruction and data throughput
— Condition register (CR) look-ahead operations performed by BPU
— Branch-folding capability during execution (zero-cycle branch execution time)
— Programmable static branch prediction on unresolved conditional branches
— A pre-fetch queue that can hold up to four instructions, providing look-ahead
capability
— Interlocked pipelines with feed-forwarding that control data dependencies in
hardware
MPC555
USER’S MANUAL
CENTRAL PROCESSING UNIT
Revised 1 March 1999
MOTOROLA
3-1
I-ADDR
3-2
MOTOROLA
GPR
HISTORY
IMUL/
IDIV
ALU/
BFU
LOAD/STORE LOAD/STORE
ADDRESS
INTEGER DATA
L-ADDR
WRITE BACK BUS
2 SLOTS/CLOCK
CENTRAL PROCESSING UNIT
Revised 1 March 1999
(4 SLOTS/CLOCK)
GPR
(32 X 32)
INSTRUCTION
PRE-FETCH
QUEUE
FLOATING
DATA
LOAD/STORE
FPR
(32 X 64)
L-DATA
SOURCE BUSES
CONTROL
REGS
CONTROL BUS
BRANCH
PROCESSOR
UNIT
I-DATA
NEXT ADDRESS
GENERATION
INSTRUCTION SEQUENCER
FPR
HISTORY
RCPU
FPU
3.2 RCPU Block Diagram
Figure 3-1 provides a block diagram of the RCPU.
Figure 3-1 RCPU Block Diagram
USER’S MANUAL
MPC555
3.3 Instruction Sequencer
The instruction sequencer provides centralized control over data flow between execution units and register files. The sequencer implements the basic instruction pipeline,
fetches instructions from the memory system, issues them to available execution
units, and maintains a state history so it can back the machine up in the event of an
exception.
The instruction sequencer fetches instructions from the burst buffer controller into the
instruction pre-fetch queue. The BPU extracts branch instructions from the pre-fetch
queue and uses static branch prediction on unresolved conditional branches to allow
the instruction unit to fetch instructions from a predicted target instruction stream while
a conditional branch is evaluated. The BPU folds out branch instructions for unconditional branches or conditional branches unaffected by instructions in the execution
stage.
Instructions issued beyond a predicted branch do not complete execution until the
branch is resolved, preserving the programming model of sequential execution. If
branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path.
MPC555
USER’S MANUAL
CENTRAL PROCESSING UNIT
Revised 1 March 1999
MOTOROLA
3-3
INSTRUCTION MEMORY SYSTEM
32
INSTRUCTION ADDRESS GENERATOR
INSTRUCTION BUFFER
32
READ WRITE BUSES
BRANCH
CONDITION
EVALUATION
CC UNIT
INSTRUCTION
PRE-FETCH
QUEUE
32
EXECUTION UNITS AND REGISTERS FILES
Figure 3-2 Sequencer Data Path
3.4 Independent Execution Units
The PowerPC architecture supports independent floating-point, integer, load/store,
and branch processing execution units, making it possible to implement advanced features such as look-ahead operations. For example, since branch instructions do not
depend on GPRs, branches can often be resolved early, eliminating stalls caused by
taken branches.
Table 3-1 summarizes the RCPU execution units.
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Table 3-1 RCPU Execution Units
Unit
Branch processing
unit (BPU)
Load/store unit (LSU)
Description
Includes the implementation of all branch instructions
Includes implementation of all load and store instructions, whether defined as part
of the integer processor or the floating-point processor
Includes implementation of all integer instructions except load/store instructions.
This module includes the GPRs (including GPR history and scoreboard) and the
following subunits:
Integer unit (IU)
The IMUL-IDIV includes the implementation of the integer multiply and divide instructions.
The ALU-BFU includes implementation of all integer logic, add and subtract instructions, and bit field instructions.
Floating-point unit
(FPU)
Includes the FPRs (including FPR history and scoreboard) and the implementation of all floating-point instructions except load and store floating-point instructions
The following sections describe the execution units in greater detail.
3.4.1 Branch Processing Unit (BPU)
The BPU, located within the instruction sequencer, performs condition register lookahead operations on conditional branches. The BPU looks through the instruction
queue for a conditional branch instruction and attempts to resolve it early, achieving
the effect of a zero-cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional
branch. Therefore, when an unresolved conditional branch instruction is encountered,
the processor pre-fetches instructions from the predicted target stream until the conditional branch is resolved.
The BPU contains an calculation feature to compute branch target addresses and
three special-purpose, user-accessible registers: the link register (LR), the count register (CTR), and the condition register (CR). The BPU calculates the return pointer for
subroutine calls and saves it into the LR. The LR also contains the branch target
address for the branch conditional to link register (bclrx) instruction. The CTR contains
the branch target address for the branch conditional to count register (bcctrx) instruction. The contents of the LR and CTR can be copied to or from any GPR. Because the
BPU uses dedicated registers rather than general-purpose or floating-point registers,
execution of branch instructions is independent from execution of integer instructions.
3.4.2 Integer Unit (IU)
The IU executes all integer processor instructions, except the integer storage access
instructions, which are implemented by the load/store unit. The IU contains the following subunits:
• The IMUL–IDIV unit includes the implementation of the integer multiply and divide
instructions.
• The ALU–BFU unit includes the implementation of all integer logic, add and subtract, and bit field instructions.
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The IU also includes the integer exception register (XER) and the general-purpose
register file.
IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU–
BFU unit can execute one instruction per clock cycle. IMUL–IDIV instructions require
multiple clock cycles to execute. IMUL–IDIV is pipelined for multiply instructions, so
that consecutive multiply instructions can be issued on consecutive clock cycles.
Divide instructions are not pipelined; an integer divide instruction preceded or followed
by an integer divide or multiply instruction results in a stall in the processor pipeline.
Note that since IMUL–IDIV and ALU–BFU are implemented as separate execution
units, an integer divide instruction preceded or followed by an ALU–BFU instruction
does not cause a delay in the pipeline.
3.4.3 Load/Store Unit (LSU)
The load/store unit handles all data transfer between the general-purpose register file
and the internal load/store bus (L-bus). The load/store unit is implemented as an independent execution unit so that stalls in the memory pipeline do not cause the master
instruction pipeline to stall (unless there is a data dependency). The unit is fully pipelined so that memory instructions of any size may be issued on back-to-back cycles.
There is a 32-bit wide data path between the load/store unit and the general-purpose
register file. Single-word accesses can be achieved with an internal on-chip data RAM,
resulting in two clocks latency. Double-word accesses require two clocks, resulting in
three clocks latency. Since the L-bus is 32 bits wide, double-word transfers require two
bus accesses. The load/store unit performs zero-fill for byte and half-word transfers
and sign extension for half-word transfers.
Addresses are formed by adding the source one register operand specified by the
instruction (or zero) to either a source two register operand or to a 16-bit, immediate
value embedded in the instruction.
3.4.4 Floating-Point Unit (FPU)
The FPU contains a double-precision multiply array, the floating-point status and control register (FPSCR), and the FPRs. The multiply-add array allows the MPC555 to
efficiently implement floating-point operations such as multiply, multiply-add, and
divide.
The MPC555 depends on a software envelope to fully implement the IEEE floatingpoint specification. Overflows, underflows, NaNs, and denormalized numbers cause
floating-point assist exceptions that invoke a software routine to deliver (with hardware
assistance) the correct IEEE result.
To accelerate time-critical operations and make them more deterministic, the MPC555
provides a mode of operation that avoids invoking the software envelope and attempts
to deliver results in hardware that are adequate for most applications, if not in strict
conformance with IEEE standards. In this mode, denormalized numbers, NaNs, and
IEEE invalid operations are treated as legitimate, returning default results rather than
causing floating-point assist exceptions.
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3.5 Levels of the PowerPC Architecture
The PowerPC architecture consists of three layers. Adherence to the PowerPC architecture can be measured in terms of which of the following levels of the architecture
are implemented:
• PowerPC user instruction set architecture (UISA) — Defines the base user-level
instruction set, user-level registers, data types, floating-point exception model,
memory models for a uniprocessor environment, and programming model for a
uniprocessor environment.
• PowerPC virtual environment architecture (VEA) — Describes the memory model
for a multiprocessor environment, and describes other aspects of virtual environments. Implementations that conform to the VEA also adhere to the UISA, but
may not necessarily adhere to the OEA.
• PowerPC operating environment architecture (OEA) — Defines the memory management model, supervisor-level registers, synchronization requirements, and
the exception model. Implementations that conform to the OEA also adhere to the
UISA and the VEA.
3.6 RCPU Programming Model
The PowerPC architecture defines register-to-register operations for most computational instructions. Source operands for these instructions are accessed from the
registers or are provided as immediate values embedded in the instruction opcode.
The three-register instruction format allows specification of a target register distinct
from the two source operands. Load and store instructions transfer data between
memory and on-chip registers.
PowerPC processors have two levels of privilege: supervisor mode of operation (typically used by the operating environment) and user mode of operation (used by the
application software). The programming models incorporate 32 GPRs, special-purpose registers (SPRs), and several miscellaneous registers.
Supervisor-level access is provided through the processor’s exception mechanism.
That is, when an exception is taken (either due to an error or problem that needs to be
serviced, or deliberately through the use of a trap instruction), the processor begins
operating in supervisor mode. The level of access is indicated by the privilege-level
(PR) bit in the machine state register (MSR).
Figure 3-3 shows the user-level and supervisor-level RCPU programming models and
also illustrates the three levels of the PowerPC architecture. The numbers to the left
of the SPRs indicate the decimal number that is used in the syntax of the instruction
operands to access the register.
Note that registers such as the general-purpose registers (GPRs) are accessed
through operands that are part of the instructions. Access to registers can be explicit
(that is, through the use of specific instructions for that purpose such as Move to Special-Purpose Register (mtspr) and Move from Special-Purpose Register (mfspr)
instructions) or implicitly as the part of the execution of an instruction. Some registers
are accessed both explicitly and implicitly.
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SUPERVISOR MODEL OEA
USER MODEL UISA
Machine State Register
FPR0
FPR1
MSR
0
31
Supervisor-Level SPRs
FPR31
63
0
GPR0
GPR1
See table for list of supervisor-level SPRs.
Condition
Register
CR
31
0
GPR31
Development Support SPRs
31
0
Floating-Point Status
and Control Register
FPSCR
0
31
See table for list of development-support SPRs.
User-Level SPRs
Integer Exception Register (XER)
Link Register (LR)
Count Register (CTR)
31
0
USER MODEL VEA
Time Base Facility (for Reading)
Time Base Lower – Read (TBL)
Time Base Upper – Read (TBU)
Figure 3-3 RCPU Programming Model
Table 3-2 lists the MPC555 supervisor-level registers.
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Table 3-2 Supervisor-Level SPRs
SPR Number
(Decimal)
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Special-Purpose Register
18
DAE/Source Instruction Service Register (DSISR)
See 3.9.2 DAE/Source Instruction Service Register
(DSISR) for bit descriptions.
19
Data Address Register (DAR)
See 3.9.3 Data Address Register (DAR) for bit descriptions.
22
Decrementer Register (DEC)
See 3.9.5 Decrementer Register (DEC) for bit descriptions.
26
Save and Restore Register 0 (SRR0)
See 3.9.6 Machine Status Save/Restore Register 0
(SRR0) for bit descriptions.
27
Save and Restore Register 1 (SRR1)
See 3.9.7 Machine Status Save/Restore Register 1
(SRR1) for bit descriptions.
80
External Interrupt Enable (EIE)1
See 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers for bit descriptions.
81
External Interrupt Disable (EID)1
See 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers for bit descriptions.
82
Non-Recoverable Interrupt (NRI)1
See 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers for bit descriptions.
272
SPR General 0 (SPRG0)
See 3.9.8 General SPRs (SPRG0–SPRG3) for bit descriptions.
273
SPRGeneral 1 (SPRG1)
See 3.9.8 General SPRs (SPRG0–SPRG3) for bit descriptions.
274
SPR General 2 (SPRG2)
See 3.9.8 General SPRs (SPRG0–SPRG3) for bit descriptions.
275
SPR General 3 (SPRG3)
See 3.9.8 General SPRs (SPRG0–SPRG3) for bit descriptions.
284
Time Base Lower – Write (TBL)
See Table 3-14 for bit descriptions.
285
Time Base Upper – Write (TBU)
See Table 3-14 for bit descriptions.
287
Processor Version Register (PVR)
See Table 3-16 for bit descriptions.
528
IMPU Global Region Attribute (MI_GRA)1
See Table 4-7 for bit descriptions.
536
L2U Global Region Attribute (L2U_GRA)1
See Table 11-10 for bit descriptions.
560
BBC Module Configuration Register (BBCMCR)1
See Table 4-8 for bit descriptions.
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Table 3-2 Supervisor-Level SPRs (Continued)
SPR Number
(Decimal)
Special-Purpose Register
568
L2U Module Configuration Register (L2U_MCR)1
See Table 11-7 for bit descriptions.
784
IMPU Region Base Address 0 (MI_RBA0)1
See Table 4-5 for bit descriptions.
785
IMPU Region Base Address 1 (MI_RBA1)1
See Table 4-5 for bit descriptions.
786
IMPU Region Base Address 2 (MI_RBA2)1
See Table 4-5 for bit descriptions.
787
IMPU Region Base Address 3 (MI_RBA3)1
See Table 4-5 for bit descriptions.
792
L2U Region Base Address Register 0 (L2U_RBA0)1
See Table 11-8 for bit descriptions.
793
L2U Region Base Address Register 1 (L2U_RBA1)1
See Table 11-8 for bit descriptions.
794
L2U Region Base Address Register 2 (L2U_RBA2)1
See Table 11-8 for bit descriptions.
795
L2U Region Base Address Register 3 (L2U_RBA3)1
See Table 11-8 for bit descriptions.
816
IMPU Region Attribute Register 0 (MI_RA0)1
See Table 4-6 for bit descriptions.
817
IMPU Region Attribute Register 1 (MI_RA1)1
See Table 4-6 for bit descriptions.
818
IMPU Region Attribute Register 2 (MI_RA2)1
See Table 4-6 for bit descriptions.
819
IMPU Region Attribute Register 3 (MI_RA3)1
See Table 4-6 for bit descriptions.
824
L2U Region Attribute Register 0 (L2U_RA0)1
See Table 11-9 for bit descriptions.
825
L2U Region Attribute Register 1 (L2U_RA1)1
See Table 11-9 for bit descriptions.
826
L2U Region Attribute Register 2 (L2U_RA2)1
See Table 11-9 for bit descriptions.
827
L2U Region Attribute Register 3 (L2U_RA3)1
See Table 11-9 for bit descriptions.
1022
Floating-Point Exception Cause Register (FPECR)1
See 3.9.10.2 Floating-Point Exception Cause Register
(FPECR) for bit descriptions.
NOTES:
1. Implementation-specific SPR.
Table 3-3 lists the MPC555 SPRs used for development support.
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Table 3-3 Development Support SPRs1
SPR Number
(Decimal)
Special-Purpose Register
144
Comparator A Value Register (CMPA)
See Table 21-17 for bit descriptions.
145
Comparator B Value Register (CMPB)
See Table 21-17 for bit descriptions.
146
Comparator C Value Register (CMPC)
See Table 21-17 for bit descriptions.
147
Comparator D Value Register (CMPD)
See Table 21-17 for bit descriptions.
148
Exception Cause Register (ECR)
See Table 21-26 for bit descriptions.
149
Debug Enable Register (DER)
See Table 21-27 for bit descriptions.
150
Breakpoint Counter A Value and Control (COUNTA)
See Table 21-24 for bit descriptions.
151
Breakpoint Counter B Value and Control (COUNTB)
See Table 21-25 for bit descriptions.
152
Comparator E Value Register (CMPE)
See Table 21-18 for bit descriptions.
153
Comparator F Value Register (CMPF)
See Table 21-18 for bit descriptions.
154
Comparator G Value Register (CMPG)
See Table 21-20 for bit descriptions.
155
Comparator H Value Register (CMPH)
See Table 21-20 for bit descriptions.
156
L-bus Support Comparators Control 1 (LCTRL1)
See Table 21-22 for bit descriptions.
157
L-bus Support Comparators Control 2 (LCTRL2)
See Table 21-23 for bit descriptions.
158
I-bus Support Control Register (ICTRL)
See Table 21-21 for bit descriptions.
159
Breakpoint Address Register (BAR)
See Table 21-19 for bit descriptions.
630
Development Port Data Register (DPDR)
See 21.7.13 for bit descriptions.
NOTES:
1. All development-support SPRs are implementation-specific.
Where not otherwise noted, reserved fields in registers are ignored when written and
return zero when read. An exception to this rule is XER[16:23]. These bits are set to
the value written to them and return that value when read.
3.7 PowerPC UISA Register Set
The PowerPC UISA registers can be accessed by either user- or supervisor-level
instructions. The general-purpose registers are accessed through instruction
operands.
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3.7.1 General-Purpose Registers (GPRs)
Integer data is manipulated in the integer unit’s thirty-two 32-bit GPRs, shown below.
These registers are accessed as source and destination registers through operands
in the instruction syntax.
GPRs — General-Purpose Registers
0
31
GPR0
GPR1
...
...
GPR31
RESET: UNCHANGED
3.7.2 Floating-Point Registers (FPRs)
The PowerPC architecture provides thirty-two 64-bit FPRs. These registers are
accessed as source and destination registers through operands in floating-point
instructions. Each FPR supports the double-precision, floating-point format. Every
instruction that interprets the contents of an FPR as a floating-point value uses the
double-precision floating-point format for this interpretation. That is, all floating-point
numbers are stored in double-precision format.
All floating-point arithmetic instructions operate on data located in FPRs and, with the
exception of the compare instructions (which update the CR), place the result into an
FPR. Information about the status of floating-point operations is placed into the floating-point status and control register (FPSCR) and in some cases, into the CR, after the
completion of the operation’s writeback stage. For information on how the CR is
affected by floating-point operations, see 3.7.4 Condition Register (CR).
FPRs— Floating-Point Registers
0
63
FPR0
FPR1
...
...
FPR31
RESET: UNCHANGED
3.7.3 Floating-Point Status and Control Register (FPSCR)
The FPSCR controls the handling of floating-point exceptions and records status
resulting from the floating-point operations. FPSCR[0:23] are status bits.
FPSCR[24:31] are control bits.
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FPSCR[0:12] and FPSCR[21:23] are floating-point exception condition bits. These bits
are sticky, except for the floating-point enabled exception summary (FEX) and floating-point invalid operation exception summary (VX). Once set, sticky bits remain set
until they are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0 instruction.
Table 3-4 summarizes which bits in the FPSCR are sticky status bits, which are normal status bits, and which are control bits.
Table 3-4 FPSCR Bit Categories
Bits
Type
[0], [3:12], [21:23]
[1:2], [13:20]
[24:31]
Status, sticky
Status, not sticky
Control
FEX and VX are the logical ORs of other FPSCR bits. Therefore these two bits are not
listed among the FPSCR bits directly affected by the various instructions.
FPSCR — Floating-Point Status and Control Register
0
FX
15
FEX
VX
OX
UX
ZX
XX
VXSNAN
VXISI
VXIDI
VXZD
VXIMZ VXVC
Z
FR
FI
FPRF
0
RESET: UNCHANGED
16
31
FPRF[1:4]
0
VXVXVXCVI
SOFT SQRT
VE
OE
UE
ZE
XE
NI
RN
RESET: UNCHANGED
A listing of FPSCR bit settings is shown in Table 3-5.
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Table 3-5 FPSCR Bit Settings
Bit(s)
Name
Description
FX
Floating-point exception summary. Every floating-point instruction implicitly sets FPSCR[FX] if
that instruction causes any of the floating-point exception bits in the FPSCR to change from 0 to
1. The mcrfs instruction implicitly clears FPSCR[FX] if the FPSCR field containing FPSCR[FX]
is copied. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can set or clear FPSCR[FX] explicitly. This is a sticky bit.
FEX
Floating-point enabled exception summary. This bit signals the occurrence of any of the enabled
exception conditions. It is the logical OR of all the floating-point exception bits masked with their
respective enable bits. The mcrfs instruction implicitly clears FPSCR[FEX] if the result of the logical OR described above becomes zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions
cannot set or clear FPSCR[FEX] explicitly. This is not a sticky bit.
2
VX
Floating-point invalid operation exception summary. This bit signals the occurrence of any invalid
operation exception. It is the logical OR of all of the invalid operation exceptions. The mcrfs
instruction implicitly clears FPSCR[VX] if the result of the logical OR described above becomes
zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear FPSCR[VX] explicitly. This is not a sticky bit.
3
OX
Floating-point overflow exception. This is a sticky bit.
4
UX
Floating-point underflow exception. This is a sticky bit.
5
ZX
Floating-point zero divide exception. This is a sticky bit.
6
XX
Floating-point inexact exception. This is a sticky bit.
7
VXSNAN
8
VXISI
Floating-point invalid operation exception for ×-×. This is a sticky bit.
9
VXIDI
Floating-point invalid operation exception for ×/×. This is a sticky bit.
10
VXZDZ
Floating-point invalid operation exception for 0/0. This is a sticky bit.
11
VXIMZ
Floating-point invalid operation exception for ×*0. This is a sticky bit.
12
VXVC
Floating-point invalid operation exception for invalid compare. This is a sticky bit.
13
FR
Floating-point fraction rounded. The last floating-point instruction that potentially rounded the
intermediate result incremented the fraction. This bit is not sticky.
14
FI
Floating-point fraction inexact. The last floating-point instruction that potentially rounded the
intermediate result produced an inexact fraction or a disabled exponent overflow. This bit is not
sticky.
[15:19]
FPRF
Floating-point result flags. This field is based on the value placed into the target register even if
that value is undefined. Refer to Table 3-6 for specific bit settings.
15
Floating-point result class descriptor (C). Floating-point instructions other than the
compare instructions may set this bit with the FPCC bits, to indicate the class of the
result.
16–19
Floating-point condition code (FPCC). Floating-point compare instructions always
set one of the FPCC bits to one and the other three FPCC bits to zero. Other
floating-point instructions may set the FPCC bits with the C bit, to indicate the class
of the result. Note that in this case the high-order three bits of the FPCC retain their
relational significance indicating that the value is less than, greater than, or equal to
zero.
16 Floating-point less than or negative (FL or <)
17 Floating-point greater than or positive (FG or >)
18 Floating-point equal or zero (FE or =)
19 Floating-point unordered or NaN (FU or ?)
20
—
0
1
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Floating-point invalid operation exception for SNaN. This is a sticky bit.
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Table 3-5 FPSCR Bit Settings (Continued)
Bit(s)
Name
Description
21
VXSOFT
Floating-point invalid operation exception for software request. This bit can be altered only by the
mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The purpose of VXSOFT is to allow software to cause an invalid operation condition for a condition that is not necessarily associated with
the execution of a floating-point instruction. For example, it might be set by a program that computes a square root if the source operand is negative. This is a sticky bit.
22
VXSQRT
Floating-point invalid operation exception for invalid square root. This is a sticky bit. This guarantees that software can simulate fsqrt and frsqrte, and to provide a consistent interface to
handle exceptions caused by square-root operations.
23
VXCVI
24
VE
Floating-point invalid operation exception enable.
25
OE
Floating-point overflow exception enable.
26
UE
Floating-point underflow exception enable. This bit should not be used to determine whether
denormalization should be performed on floating-point stores.
27
ZE
Floating-point zero divide exception enable.
28
XE
Floating-point inexact exception enable.
29
NI
Non-IEEE mode bit.
RN
Floating-point rounding control.
00 Round to nearest
01 Round toward zero
10 Round toward +infinity
11 Round toward -infinity
30–31
Floating-point invalid operation exception for invalid integer convert. This is a sticky bit.
Table 3-6 illustrates the floating-point result flags that correspond to FPSCR[15:19].
Table 3-6 Floating-Point Result Flags in FPSCR
Result Flags
(Bits 15–19)
C<>=?
Result value class
10001
Quiet NaN
01001
– Infinity
01000
– Normalized number
11000
– Denormalized number
10010
– Zero
00010
+ Zero
10100
+ Denormalized number
00100
+ Normalized number
00101
+ Infinity
3.7.4 Condition Register (CR)
The condition register (CR) is a 32-bit register that reflects the result of certain operations and provides a mechanism for testing and branching. The bits in the CR are
grouped into eight 4-bit fields, CR0 to CR7.
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CR — Condition Register
0
31
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
RESET: UNCHANGED
The CR fields can be set in the following ways:
• Specified fields of the CR can be set by a move instruction (mtcrf) to the CR from
a GPR.
• Specified fields of the CR can be moved from one CRx field to another with the
mcrf instruction.
• A specified field of the CR can be set by a move instruction (mcrxr) to the CR
from the XER.
• Condition register logical instructions can be used to perform logical operations
on specified bits in the condition register.
• CR0 can be the implicit result of an integer operation.
• A specified CR field can be the explicit result of an integer compare instruction.
Instructions are provided to test individual CR bits.
3.7.4.1 Condition Register CR0 Field Definition
In most integer instructions, when the CR is set to reflect the result of the operation
(that is, when Rc = 1), and for addic., andi., and andis., the first three bits of CR0 are
set by an algebraic comparison of the result to zero; the fourth bit of CR0 is copied from
XER[SO]. For integer instructions, CR[0:3] are set to reflect the result as a signed
quantity. The result as an unsigned quantity or a bit string can be deduced from the
EQ bit.
The CR0 bits are interpreted as shown in Table 3-7. If any portion of the result (the 32bit value placed into the destination register) is undefined, the value placed in the first
three bits of CR0 is undefined.
Table 3-7 Bit Settings for CR0 Field of CR
CR0
Bit
Description
0
Negative (LT) — This bit is set when the result is negative.
1
Positive (GT) — This bit is set when the result is positive (and not zero).
2
Zero (EQ) — This bit is set when the result is zero.
3
Summary overflow (SO) — This is a copy of the final state of XER[SO] at the completion of the instruction.
3.7.4.2 Condition Register CR1 Field Definition
In all floating-point instructions when the CR is set to reflect the result of the operation
(that is, when Rc = 1), the CR1 field (bits 4 to 7 of the CR) is copied from FPSCR[0:3]
to indicate the floating-point exception status. For more information about the FPSCR,
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see 3.7.3 Floating-Point Status and Control Register (FPSCR). The bit settings for
the CR1 field are shown in Table 3-8.
Table 3-8 Bit Settings for CR1 Field of CR
CR1 Bit
Description
0
Floating-point exception (FX) — This is a copy of the final state of FPSCR[FX] at the completion of the instruction.
1
Floating-point enabled exception (FEX) — This is a copy of the final state of FPSCR[FEX] at the completion
of the instruction.
2
Floating-point invalid exception (VX) — This is a copy of the final state of FPSCR[VX] at the completion of
the instruction.
3
Floating-point overflow exception (OX) — This is a copy of the final state of FPSCR[OX] at the completion
of the instruction.
3.7.4.3 Condition Register CRn Field — Compare Instruction
When a specified CR field is set by a compare instruction, the bits of the specified field
are interpreted as shown in Table 3-9. A condition register field can also be accessed
by the mfcr, mcrf, and mtcrf instructions.
Table 3-9 CRn Field Bit Settings for Compare Instructions
CRn Bit1
Description
Less than, floating-point less than (LT, FL).
0
For integer compare instructions, (rA) < SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison).
For floating-point compare instructions, (frA) < (frB).
Greater than, floating-point greater than (GT, FG).
1
For integer compare instructions, (rA) > SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison).
For floating-point compare instructions, (frA) > (frB).
Equal, floating-point equal (EQ, FE).
2
For integer compare instructions, (rA) = SIMM, UIMM, or (rB).
For floating-point compare instructions, (frA) = (frB).
Summary overflow, floating-point unordered (SO, FU).
3
For integer compare instructions, this is a copy of the final state of XER[SO] at the completion of the instruction.
For floating-point compare instructions, one or both of (frA) and (frB) is not a number (NaN).
NOTES:
1. Here, the bit indicates the bit number in any one of the four-bit subfields, CR0–CR7
3.7.5 Integer Exception Register (XER)
The integer exception register (XER) is a user-level, 32-bit register.
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XER — Integer Exception Register
SPR 1
0
31
SO
OV
CA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BYTES
RESET: UNCHANGED
The bit definitions for XER, shown in Table 3-10, are based on the operation of an
instruction considered as a whole, not on intermediate results. For example, the result
of the Subtract from Carrying (subfcx) instruction is specified as the sum of three values. This instruction sets bits in the XER based on the entire operation, not on an
intermediate sum.
In most cases, reserved fields in registers are ignored when written to and return zero
when read. However, XER[16:23] are set to the value written to them and return that
value when read.
Table 3-10 Integer Exception Register Bit Definitions
Bit(s)
Name
Description
0
SO
Summary Overflow (SO) — The summary overflow bit is set whenever an instruction sets the
overflow bit (OV) to indicate overflow and remains set until software clears it. It is not altered
by compare instructions or other instructions that cannot overflow.
OV
Overflow (OV) — The overflow bit is set to indicate that an overflow has occurred during execution of an instruction. Integer and subtract instructions having OE=1 set OV if the carry out
of bit 0 is not equal to the carry out of bit 1, and clear it otherwise. The OV bit is not altered by
compare instructions or other instructions that cannot overflow.
2
CA
Carry (CA) — In general, the carry bit is set to indicate that a carry out of bit 0 occurred during
execution of an instruction. Add carrying, subtract from carrying, add extended, and subtract
from extended instructions set CA to one if there is a carry out of bit 0, and clear it otherwise.
The CA bit is not altered by compare instructions or other instructions that cannot carry, except
that shift right algebraic instructions set the CA bit to indicate whether any ‘1’ bits have been
shifted out of a negative quantity.
3:24
—
Reserved
25:31
BYTES
1
This field specifies the number of bytes to be transferred by a Load String Word Indexed (lswx)
or Store String Word Indexed (stswx) instruction.
3.7.6 Link Register (LR)
The 32-bit link register supplies the branch target address for the Branch Conditional
to Link Register (bclrx) instruction, and can be used to hold the logical address of the
instruction that follows a branch and link instruction.
Note that although the two least-significant bits can accept any values written to them,
they are ignored when the LR is used as an address.
Both conditional and unconditional branch instructions include the option of placing the
effective address of the instruction following the branch instruction in the LR. This is
done regardless of whether the branch is taken.
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LR — Link Register
SPR 8
0
31
Branch Address
RESET: UNCHANGED
3.7.7 Count Register (CTR)
The count register (CTR) is a 32-bit register for holding a loop count that can be decremented during execution of branch instructions that contain an appropriately coded
BO field. If the value in CTR is 0 before being decremented, it is –1 afterward. The
count register provides the branch target address for the Branch Conditional to Count
Register (bcctrx) instruction.
CTR — Count Register
SPR 9
0
31
Loop Count
RESET: UNCHANGED
3.8 PowerPC VEA Register Set — Time Base
The PowerPC virtual environment architecture (VEA) defines registers in addition to
those in the UISA register set. The PowerPC VEA register set can be accessed by all
software with either user- or supervisor-level privileges.
The PowerPC VEA includes the time base facility (TB), a 64-bit structure that contains
a 64-bit unsigned integer that is incremented periodically. The frequency at which the
counter is updated is implementation-dependent. For details on the time base clock in
the MPC555, refer to 6.7 MPC555 Time Base (TB), 8.6 MPC555 Internal Clock Signals, and 8.12.1 System Clock Control Register (SCCR).
The TB consists of two 32-bit registers: time base upper (TBU) and time base lower
(TBL). In the context of the VEA, user-level applications are permitted read-only
access to the TB. The OEA defines supervisor-level access to the TB for writing values
to the TB. Different SPR encodings are provided for reading and writing the time base.
TB — Time Base (Read Only)
0
SPR 268, 269
31 32
63
TBU
TBL
RESET: UNCHANGED
Table 3-11 Time Base Field Definitions (Read Only)
Bits
Name
Description
0-31
TBU
Time Base (Upper) — The high-order 32 bits of the time base
32-63
TBL
Time Base (Lower) — The low-order 32 bits of the time base
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In 32-bit PowerPC implementations such as the RCPU, it is not possible to read the
entire 64-bit time base in a single instruction. The mftb simplified mnemonic copies
the lower half of the time base register (TBL) to a GPR, and the mftbu simplified mnemonic copies the upper half of the time base (TBU) to a GPR.
3.9 PowerPC OEA Register Set
The PowerPC operating environment architecture (OEA) includes a number of SPRs
and other registers that are accessible only by supervisor-level instructions. Some
SPRs are RCPU-specific; some RCPU SPRs may not be implemented in other PowerPC processors, or may not be implemented in the same way.
3.9.1 Machine State Register (MSR)
The machine state register is a 32-bit register that defines the state of the processor.
When an exception occurs, the current contents of the MSR are loaded into SRR1,
and the MSR is updated to reflect the exception-processing machine state. The MSR
can also be modified by the mtmsr, sc, and rfi instructions. It can be read by the
mfmsr instruction.
MSR — Machine State Register
0
15
RESERVED
POW
0
ILE
0
0
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
16
EE
31
PR
FP
ME
FE0
SE
BE
FE1
0
IP
IR
DR
0
0
U
0
0
0
0
0
ID1*
0
0
RESERVED
RI
LE
0
0
RESET:
0
0
0
*Reset value of this bit depends on the value of the internal data bus line during reset.
Table 3-12 shows the bit definitions for the MSR.
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Table 3-12 Machine State Register Bit Settings
Bit(s)
Name
0:12
—
13
POW
14
—
Reserved
ILE
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to
select the endian mode for the context established by the exception.
0 = Processor runs in big-endian mode during exception processing.
1 = Processor runs in little-endian mode during exception processing.
16
EE
External interrupt enable. Interrupts should only be negated while the EE bit is disabled (0).
Software should disable interrupts in the CPU core prior to masking or disabling any interrupt
which might be currently pending at the CPU core. For external interrupts, it is recommended
that the edge triggered interrupt scheme be used.
0 = The processor delays recognition of external interrupts and decrementer exception conditions.
1 = The processor is enabled to take an external interrupt or the decrementer exception.
17
PR
Privilege level
0 = The processor can execute both user- and supervisor-level instructions.
1 = The processor can only execute user-level instructions.
18
FP
Floating-point available
0 = The processor prevents dispatch of floating-point instructions, including floating-point loads,
stores and moves. Floating-point enabled program exceptions can still occur and the FPRs
can still be accessed.
1 = The processor can execute floating-point instructions, and can take floating-point enabled
exception type program exceptions.
19
ME
Machine check enable
0 = Machine check exceptions are disabled.
1 = Machine check exceptions are enabled.
20
FE0
Floating-point exception mode 0 (See Table 3-13.)
21
SE
Single-step trace enable
0 = The processor executes instructions normally.
1 = The processor generates a single-step trace exception upon the successful execution of
the next instruction. When this bit is set, the processor dispatches instructions in strict program order. Successful execution means the instruction caused no other exception. Singlestep tracing may not be present on all implementations.
22
BE
Branch trace enable
0 = No trace exception occurs when a branch instruction is completed
1 = Trace exception occurs when a branch instruction is completed
23
FE1
Floating-point exception mode 1 (See Table 3-13.)
24
—
Reserved
25
IP
Exception prefix. The setting of this bit specifies the location of the exception vector table.
0 = Exception vector table starts at the physical address 0x0000 0000.
1 = Exception vector table starts at the physical address 0xFFF0 0000.
IR
Instruction relocation.
0 = Instruction address translation is off, the BBC IMPU does not check for address permission
attributes.
1 = Instruction address translation is on, the BBC IMPU checks for address permission attributes.
15
26
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Description
Reserved
Power management enable
0 = Power management disabled (normal operation mode)
1 = Power management enabled (reduced power mode)
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Table 3-12 Machine State Register Bit Settings (Continued)
Bit(s)
Name
Description
27
DR
Data relocation
0 = Data address translation is off, the L2U DMPU does not check for address permission attributes.
1 = Data address translation is on, the L2U DMPU checks for address permission attributes.
28:29
—
Reserved
30
RI
Recoverable exception (for machine check and non-maskable breakpoint exceptions)
0 = Machine state is not recoverable.
1 = Machine state is recoverable.
31
LE
Little-endian mode
0 = Processor operates in big-endian mode during normal processing.
1 = Processor operates in little-endian mode during normal processing.
The floating-point exception mode bits are interpreted as shown in Table
3-13.
Table 3-13 Floating-Point Exception Mode Bits
FE[0:1]
Mode
00
Ignore exceptions mode — Floating-point exceptions do not cause the
floating-point assist error handler to be invoked.
01, 10, 11
Floating-point precise mode — The system floating-point assist error
handler is invoked precisely at the instruction that caused the enabled
exception.
3.9.2 DAE/Source Instruction Service Register (DSISR)
The 32-bit DSISR identifies the cause of data access and alignment exceptions.
DSISR — DAE/Source Instruction Service Register
0
SPR 18
31
DSISR
RESET: UNCHANGED
3.9.3 Data Address Register (DAR)
After an alignment exception, the DAR is set to the effective address of a load or store
element.
DAR — Data Address Register
SPR 19
0
31
Data Address
RESET: UNCHANGED
3.9.4 Time Base Facility (TB) — OEA
As described in 3.8 PowerPC VEA Register Set — Time Base, the time base (TB)
provides a 64-bit incrementing counter. The VEA defines user-level, read-only access
to the TB. Writing to the TB is reserved for supervisor-level applications such as operMOTOROLA
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ating systems and bootstrap routines. The OEA defines supervisor-level, write access
to the TB.
TB — Time Base (Write Only)
0
SPR 284, 285
31 32
63
TBU
TBL
RESET: UNCHANGED
Table 3-14 Time Base Field Definitions (Write Only)
Bits
Name
Description
0:31
TBU
Time Base (Upper) — The high-order 32 bits of the time base
32:63
TBL
Time Base (Lower) — The low-order 32 bits of the time base
The TB can be written to at the supervisor privilege level only. The mttbl and mttbu
simplified mnemonics write the lower and upper halves of the TB, respectively. The
mtspr, mttbl, and mttbu instructions treat TBL and TBU as separate 32-bit registers;
setting one leaves the other unchanged. It is not possible to write the entire 64-bit time
base in a single instruction.
For information about reading the time base, refer to 3.8 PowerPC VEA Register Set
— Time Base.
3.9.5 Decrementer Register (DEC)
The decrementer (DEC, SPR 22) is a 32-bit decrementing counter defined by the
MPC555 to provide a decrementer exception after a programmable delay. The DEC
satisfies the following requirements:
• Loading a GPR from the DEC has no effect on the DEC.
• Storing a GPR to the DEC replaces the value in the DEC with the value in the
GPR.
• Whenever bit 0 of the DEC changes from zero to one, a decrementer exception
request (unless masked) is signaled. Multiple DEC exception requests may be received before the first exception occurs; however, any additional requests are
canceled when the exception occurs for the first request.
• If the DEC is altered by software and the content of bit 0 is changed from zero to
one, an exception request is signaled.
• HRESET stops the decrementor, SRESET does not.
The decrementer frequency is based on a subdivision of the processor clock. A bit in
the system clock control register (SCCR) in the SIU determines the clock source of
both the decrementer and the time base. For details on the decrementer and time base
clock in the MPC555, refer to 6.6 MPC555 Decrementer, 8.6 MPC555 Internal Clock
Signals, and 8.12.1 System Clock Control Register (SCCR).
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The DEC does not run after power-up. Only soft reset has no effect on DEC. Poweron and hard reset stops its counting. To enable decrementor clocking, the time base
clock should be enabled by setting the TBE bit in the TBSCR SIU register. A decrementer exception may be signaled to software prior to initialization.
DEC — Decrementer Register
SPR 22
0
31
Decrementing Counter
RESET: UNCHANGED
3.9.6 Machine Status Save/Restore Register 0 (SRR0)
The machine status save/restore register 0 (SRR0) is a 32-bit register that identifies
where instruction execution should resume when an rfi instruction is executed following an exception. It also holds the effective address of the instruction that follows the
System Call (sc) instruction.
When an exception occurs, SRR0 is set to point to an instruction such that all prior
instructions have completed execution and no subsequent instruction has begun execution. The instruction addressed by SRR0 may not have completed execution,
depending on the exception type. SRR0 addresses either the instruction causing the
exception or the immediately following instruction. The instruction addressed can be
determined from the exception type and status bits.
SRR0 — Machine Status Save/Restore Register 0
0
SPR 26
31
SRR0
RESET: UNDEFINED
When an exception occurs, SRR0 is set to point to an instruction such that all prior
instructions have completed execution and no subsequent instruction has begun execution. The instruction addressed by SRR0 may not have completed execution,
depending on the exception type. SRR0 addresses either the instruction causing the
exception or the immediately following instruction. The instruction addressed can be
determined from the exception type and status bits.
3.9.7 Machine Status Save/Restore Register 1 (SRR1)
SRR1 is a 32-bit register used to save machine status on exceptions and to restore
machine status when an rfi instruction is executed.
SRR1 — Machine Status Save/Restore Register 1
0
SPR 27
31
SRR1
RESET: UNDEFINED
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In general, when an exception occurs, SRR1[0:15] are loaded with exception-specific
information, and MSR[16:31] are placed into SRR1[16:31].
3.9.8 General SPRs (SPRG0–SPRG3)
SPRG0–SPRG3 are 32-bit registers provided for general operating system use, such
as performing a fast-state save and for supporting multiprocessor implementations.
SPRG0–SPRG3 are shown below.
SPRG0–SPRG3 — General Special-Purpose Registers 0–3
SPR 272 – SPR 275
0
31
SPRG0
SPRG1
SPRG2
SPRG3
RESET: UNCHANGED
Uses for SPRG0–SPRG3 are shown in Table 3-15.
Table 3-15 Uses of SPRG0–SPRG3
Register
Description
SPRG0
Software may load a unique physical address in this register to identify an area of memory reserved for
use by the exception handler. This area must be unique for each processor in the system.
SPRG1
This register may be used as a scratch register by the exception handler to save the content of a GPR.
That GPR then can be loaded from SPRG0 and used as a base register to save other GPRs to memory.
SPRG2
This register may be used by the operating system as needed.
SPRG3
This register may be used by the operating system as needed.
3.9.9 Processor Version Register (PVR)
The PVR is a 32-bit, read-only register that identifies the version and revision level of
the PowerPC processor. The contents of the PVR can be copied to a GPR by the
mfspr instruction. Read access to the PVR is available in supervisor mode only; write
access is not provided.
PVR — Processor Version Register
0
SPR 287
15 16
VERSION
31
REVISION
RESET: UNCHANGED
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Table 3-16 Processor Version Register Bit Settings
Bit(s)
Name
Description
0:15
VERSION
A 16-bit number that identifies the version of the processor and of the PowerPC architecture. MPC555 value is 0x0002.
16:31
REVISION
A 16-bit number that distinguishes between various releases of a particular version. The
MPC555 value is 0x0020.
3.9.10 Implementation-Specific SPRs
The MPC555 includes several implementation-specific SPRs that are not defined by
the PowerPC architecture. These registers can be accessed by supervisor-level
instructions only. These registers are listed in Table 3-2 and Table 3-3.
3.9.10.1 EIE, EID, and NRI Special-Purpose Registers
The RCPU includes three implementation-specific SPRs to facilitate the software
manipulation of the MSR[RI] and MSR[EE] bits. Issuing the mtspr instruction with one
of these registers as an operand causes the RI and EE bits to be set or cleared as
shown in Table 3-17.
A read (mfspr) of any of these locations is treated as an unimplemented instruction,
resulting in a software emulation exception.
Table 3-17 EIE, EID, AND NRI Registers
SPR Number
(Decimal)
Mnemonic
MSR[EE]
MSR[RI]
80
EIE
1
1
81
EID
0
1
82
NRI
0
0
3.9.10.2 Floating-Point Exception Cause Register (FPECR)
The FPECR is a 32-bit supervisor-level internal status and control register used by the
floating-point assist firmware envelope. It contains four status bits indicating whether
the result of the operation is tiny and whether any of three source operands are denormalized. In addition, it contains one control bit to enable or disable SIE mode. This
register must not be accessed by user code.
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FPECR — Floating-Point Exception Cause Register
0
1
2
3
4
5
6
7
SIE
8
9
10
11
12
13
14
15
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DNC
DNB
DNA
TR
0
0
0
0
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
A listing of FPECR bit settings is shown in Table 3-18.
Table 3-18 FPECR Bit Settings
Bit(s)
Name
Description
0
SIE
[1:27]
—
28
DNC
Source operand C denormalized status bit
0 = Source operand C is not denormalized
1 = Source operand C is denormalized
29
DNB
Source operand B denormalized status bit
0 = Source operand B is not denormalized
1 = Source operand B is denormalized
30
DNA
Source operand A denormalized status bit
0 = Source operand A is not denormalized
1 = Source operand A is denormalized
31
TR
SIE mode control bit
0 = Disable SIE mode
1 = Enable SIE mode
Reserved
Floating-point tiny result
0 = Floating-point result is not tiny
1 = Floating-point result is tiny
NOTE
Software must insert a sync instruction before reading the FPECR.
3.9.10.3 Additional Implementation-Specific Registers
Refer to the following sections for details on additional implementation-specific registers in the MPC555:
• 4.6 Burst Buffer Programming Model
• 6.13.1.2 Internal Memory Map Register
• 11.8 L2U Programming Model
• SECTION 21 DEVELOPMENT SUPPORT
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3.10 Instruction Set
All PowerPC instructions are encoded as single words (32 bits). Instruction formats are
consistent among all instruction types, permitting efficient decoding to occur in parallel
with operand accesses. This fixed instruction length and consistent format greatly simplifies instruction pipelining.
The PowerPC instructions are divided into the following categories:
• Integer instructions include computational and logical instructions.
— Integer arithmetic instructions
— Integer compare instructions
— Integer logical instructions
— Integer rotate and shift instructions
• Floating-point instructions include floating-point computational instructions, as
well as instructions that affect the floating-point status and control register (FPSCR).
— Floating-point arithmetic instructions
— Floating-point multiply/add instructions
— Floating-point rounding and conversion instructions
— Floating-point compare instructions
— Floating-point status and control instructions
• Load/store instructions include integer and floating-point load and store instructions.
— Integer load and store instructions
— Integer load and store multiple instructions
— Floating-point load and store
— Primitives used to construct atomic memory operations (lwarx and stwcx. instructions)
• Flow control instructions include branching instructions, condition register logical
instructions, trap instructions, and other instructions that affect the instruction
flow.
— Branch and trap instructions
— Condition register logical instructions
• Processor control instructions are used for synchronizing memory accesses.
— Move to/from SPR instructions
— Move to/from MSR
— Synchronize
— Instruction synchronize
Note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point
instructions operate on single-precision (one word) and double-precision (one double
word) floating-point operands. The PowerPC architecture uses instructions that are
four bytes long and word-aligned. It provides for byte, half-word, and word operand
loads and stores between memory and a set of 32 GPRs.
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Computational instructions do not modify memory. To use a memory operand in a
computation and then modify the same or another memory location, the memory contents must be loaded into a register, modified, and then written back to the target
location with distinct instructions.
PowerPC processors follow the program flow when they are in the normal execution
state. However, the flow of instructions can be interrupted directly by the execution of
an instruction or by an asynchronous event. Either kind of exception may cause one
of several components of the system software to be invoked.
3.10.1 Instruction Set Summary
Table 3-19 provides a summary of RCPU instructions. Refer to the RCPU Reference
Manual (RCPURM/AD) for a detailed description of the instruction set.
Table 3-19 Instruction Set Summary
Mnemonic
Operand Syntax
Name
add (add. addo addo.)
rD,rA,rB
Add
addc (addc. addco addco.)
rD,rA,rB
Add Carrying
adde (adde. addeo addeo.)
rD,rA,rB
Add Extended
addi
rD,rA,SIMM
Add Immediate
addic
rD,rA,SIMM
Add Immediate Carrying
addic.
rD,rA,SIMM
Add Immediate Carrying and Record
addis
rD,rA,SIMM
Add Immediate Shifted
addme (addme. addmeo addmeo.)
rD,rA
Add to Minus One Extended
addze (addze. addzeo addzeo.)
rD,rA
Add to Zero Extended
and (and.)
rA,rS,rB
AND
andc (andc.)
rA,rS,rB
AND with Complement
andi.
rA,rS,UIMM
AND Immediate
andis.
rA,rS,UIMM
AND Immediate Shifted
b (ba bl bla)
target_addr
Branch
bc (bca bcl bcla)
BO,BI,target_addr
Branch Conditional
bcctr (bcctrl)
BO,BI
Branch Conditional to Count Register
bclr (bclrl)
BO,BI
Branch Conditional to Link Register
cmp
crfD,L,rA,rB
Compare
cmpi
crfD,L,rA,SIMM
Compare Immediate
cmpl
crfD,L,rA,rB
Compare Logical
cmpli
crfD,L,rA,UIMM
Compare Logical Immediate
cntlzw (cntlzw.)
rA,rS
Count Leading Zeros Word
crand
crbD,crbA,crbB
Condition Register AND
crandc
crbD,crbA, crbB
Condition Register AND with Complement
creqv
crbD,crbA, crbB
Condition Register Equivalent
crnand
crbD,crbA,crbB
Condition Register NAND
crnor
crbD,crbA,crbB
Condition Register NOR
cror
crbD,crbA,crbB
Condition Register OR
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Table 3-19 Instruction Set Summary (Continued)
Mnemonic
Operand Syntax
Name
crorc
crbD,crbA, crbB
Condition Register OR with Complement
crxor
crbD,crbA,crbB
Condition Register XOR
divw (divw. divwo divwo.)
rD,rA,rB
Divide Word
divwu divwu. divwuo divwuo.
rD,rA,rB
Divide Word Unsigned
eieio
—
Enforce In-Order Execution of I/O
eqv (eqv.)
rA,rS,rB
Equivalent
extsb (extsb.)
rA,rS
Extend Sign Byte
extsh (extsh.)
rA,rS
Extend Sign Half Word
fabs (fabs.)
frD,frB
Floating Absolute Value
fadd (fadd.)
frD,frA,frB
Floating Add (Double-Precision)
fadds (fadds.)
frD,frA,frB
Floating Add Single
fcmpo
crfD,frA,frB
Floating Compare Ordered
fcmpu
crfD,frA,frB
Floating Compare Unordered
fctiw (fctiw.)
frD,frB
Floating Convert to Integer Word
fctiwz (fctiwz.)
frD,frB
Floating Convert to Integer Word with Round toward Zero
fdiv (fdiv.)
frD,frA,frB
Floating Divide (Double-Precision)
fdivs (fdivs.)
frD,frA,frB
Floating Divide Single
fmadd (fmadd.)
frD,frA,frC,frB
Floating Multiply-Add (Double-Precision)
fmadds (fmadds.)
frD,frA,frC,frB
Floating Multiply-Add Single
fmr (fmr.)
frD,frB
Floating Move Register
fmsub (fmsub.)
frD,frA,frC,frB
Floating Multiply-Subtract (Double-Precision)
fmsubs (fmsubs.)
frD,frA,frC,frB
Floating Multiply-Subtract Single
fmul (fmul.)
frD,frA,frC
Floating Multiply (Double-Precision)
fmuls (fmuls.)
frD,frA,frC
Floating Multiply Single
fnabs (fnabs.)
frD,frB
Floating Negative Absolute Value
fneg (fneg.)
frD,frB
Floating Negate
fnmadd (fnmadd.)
frD,frA,frC,frB
Floating Negative Multiply-Add (Double-Precision)
fnmadds (fnmadds.)
frD,frA,frC,frB
Floating Negative Multiply-Add Single
fnmsub (fnmsub.)
frD,frA,frC,frB
Floating Negative Multiply-Subtract (DoublePrecision)
fnmsubs (fnmsubs.)
frD,frA,frC,frB
Floating Negative Multiply-Subtract Single
frsp (frsp.)
frD,frB
Floating Round to Single
fsub (fsub.)
frD,frA,frB
Floating Subtract (Double-Precision)
fsubs (fsubs.)
frD,frA,frB
Floating Subtract Single
isync
—
Instruction Synchronize
lbz
rD,d(rA)
Load Byte and Zero
lbzu
rD,d(rA)
Load Byte and Zero with Update
lbzux
rD,rA,rB
Load Byte and Zero with Update Indexed
lbzx
rD,rA,rB
Load Byte and Zero Indexed
lfd
frD,d(rA)
Load Floating-Point Double
lfdu
frD,d(rA)
Load Floating-Point Double with Update
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Table 3-19 Instruction Set Summary (Continued)
Mnemonic
Operand Syntax
Name
lfdux
frD,rA,rB
Load Floating-Point Double with Update
Indexed
lfdx
frD,rA,rB
Load Floating-Point Double Indexed
lfs
frD,d(rA)
Load Floating-Point Single
lfsu
frD,d(rA)
Load Floating-Point Single with Update
lfsux
frD,rA,rB
Load Floating-Point Single with Update Indexed
lfsx
frD,rA,rB
Load Floating-Point Single Indexed
lha
rD,d(rA)
Load Half Word Algebraic
lhau
rD,d(rA)
Load Half Word Algebraic with Update
lhaux
rD,rA,rB
Load Half Word Algebraic with Update Indexed
lhax
rD,rA,rB
Load Half Word Algebraic Indexed
lhbrx
rD,rA,rB
Load Half Word Byte-Reverse Indexed
lhz
rD,d(rA)
Load Half Word and Zero
lhzu
rD,d(rA)
Load Half Word and Zero with Update
lhzux
rD,rA,rB
Load Half Word and Zero with Update Indexed
lhzx
rD,rA,rB
Load Half Word and Zero Indexed
lmw
rD,d(rA)
Load Multiple Word
lswi
rD,rA,NB
Load String Word Immediate
lswx
rD,rA,rB
Load String Word Indexed
lwarx
rD,rA,rB
Load Word and Reserve Indexed
lwbrx
rD,rA,rB
Load Word Byte-Reverse Indexed
lwz
rD,d(rA)
Load Word and Zero
lwzu
rD,d(rA)
Load Word and Zero with Update
lwzux
rD,rA,rB
Load Word and Zero with Update Indexed
lwzx
rD,rA,rB
Load Word and Zero Indexed
mcrf
crfD,crfS
Move Condition Register Field
mcrfs
crfD,crfS
Move to Condition Register from FPSCR
mcrxr
crfD
Move to Condition Register from XER
mfcr
rD
Move from Condition Register
mffs (mffs.)
frD
Move from FPSCR
mfmsr
rD
Move from Machine State Register
mfspr
rD,SPR
Move from Special Purpose Register
mftb
rD, TBR
Move from Time Base
mtcrf
CRM,rS
Move to Condition Register Fields
mtfsb0 (mtfsb0.)
crbD
Move to FPSCR Bit 0
mtfsb1 (mtfsb1.)
crbD
Move to FPSCR Bit 1
mtfsf (mtfsf.)
FM,frB
Move to FPSCR Fields
mtfsfi (mtfsfi.)
crfD,IMM
Move to FPSCR Field Immediate
mtmsr
rS
Move to Machine State Register
mtspr
SPR,rS
Move to Special Purpose Register
mulhw (mulhw.)
rD,rA,rB
Multiply High Word
mulhwu (mulhwu.)
rD,rA,rB
Multiply High Word Unsigned
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Table 3-19 Instruction Set Summary (Continued)
Mnemonic
Operand Syntax
Name
mulli
rD,rA,SIMM
Multiply Low Immediate
mullw (mullw. mullwo mullwo.)
rD,rA,rB
Multiply Low
nand (nand.)
rA,rS,rB
NAND
neg (neg. nego nego.)
rD,rA
Negate
nor (nor.)
rA,rS,rB
NOR
or (or.)
rA,rS,rB
OR
orc
rA,rS,rB
OR with Complement
ori
rA,rS,UIMM
OR Immediate
oris
rA,rS,UIMM
OR Immediate Shifted
rfi
—
Return from Interrupt
rlwimi (rlwimi.)
rA,rS,SH,MB,ME
Rotate Left Word Immediate then Mask Insert
rlwinm (rlwinm.)
rA,rS,SH,MB,ME
Rotate Left Word Immediate then AND with
Mask
rlwnm (rlwnm.)
rA,rS,rB,MB,ME
Rotate Left Word then AND with Mask
sc
—
System Call
slw (slw.)
rA,rS,rB
Shift Left Word
sraw (sraw.)
rA,rS,rB
Shift Right Algebraic Word
srawi (srawi.)
rA,rS,SH
Shift Right Algebraic Word Immediate
srw (srw.)
rA,rS,rB
Shift Right Word
stb
rS,d(rA)
Store Byte
stbu
rS,d(rA)
Store Byte with Update
stbux
rS,rA,rB
Store Byte with Update Indexed
stbx
rS,rA,rB
Store Byte Indexed
stfd
frS,d(rA)
Store Floating-Point Double
stfdu
frS,d(rA)
Store Floating-Point Double with Update
stfdux
frS,rB
Store Floating-Point Double with Update
Indexed
stfdx
frS,rB
Store Floating-Point Double Indexed
stfiwx
frS,rB
Store Floating-Point as Integer Word Indexed
stfs
frS,d(rA)
Store Floating-Point Single
stfsu
frS,d(rA)
Store Floating-Point Single with Update
stfsux
frS,rB
Store Floating-Point Single with Update Indexed
stfsx
frS,r B
Store Floating-Point Single Indexed
sth
rS,d(rA)
Store Half Word
sthbrx
rS,rA,rB
Store Half Word Byte-Reverse Indexed
sthu
rS,d(rA)
Store Half Word with Update
sthux
rS,rA,rB
Store Half Word with Update Indexed
sthx
rS,rA,rB
Store Half Word Indexed
stmw
rS,d(rA)
Store Multiple Word
stswi
rS,rA,NB
Store String Word Immediate
stswx
rS,rA,rB
Store String Word Indexed
stw
rS,d(rA)
Store Word
(orc.)
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Table 3-19 Instruction Set Summary (Continued)
Mnemonic
Operand Syntax
Name
stwbrx
rS,rA,rB
Store Word Byte-Reverse Indexed
stwcx.
rS,rA,rB
Store Word Conditional Indexed
stwu
rS,d(rA)
Store Word with Update
stwux
rS,rA,rB
Store Word with Update Indexed
stwx
rS,rA,rB
Store Word Indexed
subf (subf. subfo subfo.)
rD,rA,rB
Subtract From
subfc (subfc. subfco subfco.)
rD,rA,rB
Subtract from Carrying
subfe (subfe. subfeo subfeo.)
rD,rA,rB
Subtract from Extended
subfic
rD,rA,SIMM
Subtract from Immediate Carrying
subfme (subfme. subfmeo subfmeo.)
rD,rA
Subtract from Minus One Extended
subfze (subfze. subfzeo subfzeo.)
rD,rA
Subtract from Zero Extended
sync
—
Synchronize
tw
TO,rA,rB
Trap Word
twi
TO,rA,SIMM
Trap Word Immediate
xor (xor.)
rA,rS,rB
XOR
xori
rA,rS,UIMM
XOR Immediate
xoris
rA,rS,UIMM
XOR Immediate Shifted
3.10.2 Recommended Simplified Mnemonics
To simplify assembly language coding, a set of alternative mnemonics is provided for
some frequently used operations (such as no-op, load immediate, load address, move
register, and complement register).
For a complete list of simplified mnemonics, see the RCPU Reference Manual
(RCPURM/AD). Programs written to be portable across the various assemblers for the
PowerPC architecture should not assume the existence of mnemonics not described
in that manual.
3.10.3 Calculating Effective Addresses
The effective address (EA) is the 32-bit address computed by the processor when executing a memory access or branch instruction or when fetching the next sequential
instruction.
The PowerPC architecture supports two simple memory addressing modes:
• EA = (rA|0) + 16-bit offset (including offset = 0) (register indirect with immediate
index)
• EA = (rA|0) + rB (register indirect with index)
These simple addressing modes allow efficient address generation for memory
accesses. Calculation of the effective address for aligned transfers occurs in a single
clock cycle.
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For a memory access instruction, if the sum of the effective address and the operand
length exceeds the maximum effective address, the storage operand is considered to
wrap around from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit
unsigned binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
3.11 Exception Model
The PowerPC exception mechanism allows the processor to change to supervisor
state as a result of external signals, errors, or unusual conditions arising in the execution of instructions. When exceptions occur, information about the state of the
processor is saved to certain registers, and the processor begins execution at an
address (exception vector) predetermined for each exception. Processing of exceptions occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more
specific condition may be determined by examining a register associated with the
exception — for example, the DAE/source instruction service register (DSISR). Additionally, some exception conditions can be explicitly enabled or disabled by software.
3.11.1 Exception Classes
The MPC555 exception classes are shown in Table 3-20.
Table 3-20 MPC555 Exception Classes
Class
Exception Type
Asynchronous, unordered
Machine check
System reset
Asynchronous, ordered
External interrupt
Decrementer
Synchronous (ordered, precise)
Instruction-caused exceptions
3.11.2 Ordered Exceptions
In the MPC555, all exceptions except for reset, debug port non-maskable interrupts,
and machine check exceptions are ordered. Ordered exceptions satisfy the following
criteria:
• Only one exception is reported at a time. If, for example, a single instruction encounters multiple exception conditions, those conditions are encountered sequentially. After the exception handler handles an exception, instruction
execution continues until the next exception condition is encountered.
• When the exception is taken, no program state is lost.
3.11.3 Unordered Exceptions
Unordered exceptions may be reported at any time and are not guaranteed to preserve program state information. The processor can never recover from a reset
exception. It can recover from other unordered exceptions in most cases. However, if
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a debug port non-maskable interrupt or machine check exception occurs during the
servicing of a previous exception, the machine state information in SRR0 and SRR1
(and, in some cases, the DAR and DSISR) may not be recoverable; the processor may
be in the process of saving or restoring these registers.
To determine whether the machine state is recoverable, the user can read the RI
(recoverable exception) bit in SRR1. During exception processing, the RI bit in the
MSR is copied to SRR1 and then cleared. The operating system should set the RI bit
in the MSR at the end of each exception handler’s prologue (after saving the program
state) and clear the bit at the start of each exception handler’s epilogue (before restoring the program state). Then, if an unordered exception occurs during the servicing of
an exception handler, the RI bit in SRR1 will contain the correct value.
3.11.4 Precise Exceptions
In the MPC555, all synchronous (instruction-caused) exceptions are precise. When a
precise exception occurs, the processor backs the machine up to the instruction causing the exception. This ensures that the machine is in its correct architecturally-defined
state. The following conditions exist at the point a precise exception occurs:
1. Architecturally, no instruction following the faulting instruction in the code
stream has begun execution.
2. All instructions preceding the faulting instruction appear to have completed with
respect to the executing processor.
3. SRR0 addresses either the instruction causing the exception or the immediately following instruction. Which instruction is addressed can be determined from
the exception type and the status bits.
4. Depending on the type of exception, the instruction causing the exception may
not have begun execution, may have partially completed, or may have completed execution.
3.11.5 Exception Vector Table
The setting of the exception prefix (IP) bit in the MSR determines how exceptions are
vectored. If the bit is cleared, the exception vector table begins at the physical address
0x0000 0000; if IP is set, the exception vector table begins at the physical address
0xFFF0 0000. Table 3-21 shows the exception vector offset of the first instruction of
the exception handler routine for each exception type.
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Table 3-21 Exception Vector Offset Table
Vector Offset
(Hexadecimal)
Exception Type
00000
Reserved
00100
System reset, NMI interrupt
00200
Machine check
00300
Reserved
00400
Reserved
00500
External interrupt
00600
Alignment
00700
Program
00800
Floating-point unavailable
00900
Decrementer
00A00
Reserved
00B00
Reserved
00C00
System call
00D00
Trace
00E00
Floating-point assist
01000
Implementation-dependent software emulation
01100
Reserved
01200
Reserved
01300
Implementation-dependent instruction protection error
01400
Implementation-dependent data protection error
01500–01BFF
Reserved
01C00
Implementation-dependent data breakpoint
01D00
implementation-dependent instruction breakpoint
01E00
Implementation-dependent maskable external breakpoint
01F00
Implementation-dependent non-maskable external breakpoint
3.12 Instruction Timing
The MPC555 processor is pipelined. Because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of the
processor.
The instruction pipeline in the MPC555 has four stages:
1. The dispatch stage is implemented using a distributed mechanism. The central
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dispatch unit broadcasts the instruction to all units. In addition, scoreboard information (regarding data dependencies) is broadcast to each execution unit.
Each execution unit decodes the instruction. If the instruction is not implemented, a program exception is taken. If the instruction is legal and no data dependency is found, the instruction is accepted by the appropriate execution unit,
and the data found in the destination register is copied to the history buffer. If a
data dependency exists, the machine is stalled until the dependency is resolved.
2. In the execute stage, each execution unit that has an executable instruction executes the instruction. (For some instructions, this occurs over multiple cycles.)
3. In the writeback stage, the execution unit writes the result to the destination register and reports to the history buffer that the instruction is completed.
4. In the retirement stage, the history buffer retires instructions in architectural order. An instruction retires from the machine if it completes execution with no exceptions and if all instructions preceding it in the instruction stream have
finished execution with no exceptions. As many as six instructions can be retired in one clock.
The history buffer maintains the correct architectural machine state. An exception is
taken only when the instruction is ready to be retired from the machine (i.e., after all
previously-issued instructions have already been retired from the machine). When an
exception is taken, all instructions following the excepting instruction are canceled,
i.e., the values of the affected destination registers are restored using the values saved
in the history buffer during the dispatch stage.
Figure 3-4 shows basic instruction pipeline timing.
FETCH
I1
I2
DECODE
I3
I1
I2
READ AND EXECUTE
I1
I2
I1
WRITE BACK (TO DEST REG)
L ADDRESS DRIVE
I2
I1
L DATA
STORE
LOAD
LOAD WRITE BACK
BRANCH DECODE
BRANCH EXECUTE
I1
I1
I1
Figure 3-4 Basic Instruction Pipeline
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Table 3-22 indicates the latency and blockage for each type of instruction. Latency
refers to the interval from the time an instruction begins execution until it produces a
result that is available for use by a subsequent instruction. Blockage refers to the interval from the time an instruction begins execution until its execution unit is available for
a subsequent instruction. Note that when the blockage equals the latency, it is not possible to issue another instruction to the same unit in the same cycle in which the first
instruction is being written back.
Table 3-22 Instruction Latency and Blockage
Instruction Type
Precision
Latency
Blockage
Floating-point
multiply-add
Double
Single
7
6
7
6
Floating-point
add or subtract
Double
Single
4
4
4
4
Floating-point multiply
Double
Single
5
4
5
4
Floating-point divide
Double
Single
17
10
17
10
Integer multiply
—
2
1 or 21
Integer divide
—
2 to 111
2 to 111
Integer load/store
—
See note1
See note1
NOTES:
1. Refer to Section 7, “Instruction Timing,” in the RCPU Reference Manual
(RCPURM/AD) for details.
3.13 PowerPC User Instruction Set Architecture (UISA)
3.13.1 Computation Modes
The core of the MPC555 is a 32-bit implementation of the PowerPC architecture. Any
reference in the PowerPC Architecture Books (UISA, VEA, OEA) regarding 64-bit
implementations are not supported by the core. All registers except the floating-point
registers are 32 bits wide.
3.13.2 Reserved Fields
Reserved fields in instructions are described under the specific instruction definition
sections. Unless otherwise stated in the specific instruction description, fields marked
“I”, “II” and “III” in the instruction are discarded by the core decoding. Thus, this type of
invalid form instructions yield results of the defined instructions with the appropriate
field zero.
In most cases, the reserved fields in registers are ignored on write and return zeros for
them on read on any control register implemented by the core. Exception to this rule
are bits 16:23 of the fixed-point exception cause register (XER) and the reserved bits
of the machine state register (MSR), which are set by the source value on write and
return the value last set for it on read.
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3.13.3 Classes of Instructions
Non-optional instructions are implemented by the hardware. Optional instructions are
executed by implementation-dependent code and any attempt to execute one of these
commands causes the core to take the implementation-dependent software emulation
interrupt (offset 0x01000 of the vector table).
Illegal and reserved instruction class instructions are supported by implementationdependent code and, thus, the core hardware generates the implementation-dependent software emulation interrupt. Invalid and preferred instruction forms treatment by
the core is described under the specific processor compliance sections.
3.13.4 Exceptions
Invocation of the system software for any instruction-caused exception in the core is
precise, regardless of the type and setting.
3.13.5 The Branch Processor
3.13.6 Instruction Fetching
The core fetches a number of instructions into its internal buffer (the instruction prefetch queue) prior to execution. If a program modifies the instructions it intends to execute, it should call a system library program to ensure that the modifications have been
made visible to the instruction fetching mechanism prior to execution of the modified
instructions.
3.13.7 Branch Instructions
The core implements all the instructions defined for the branch processor by the UISA
in the hardware. For performance of various instructions, refer to Table 3-22 of this
manual.
3.13.7.1 Invalid Branch Instruction Forms
Bits marked with z in the BO encoding definition are discarded by the core decoding.
Thus, these types of invalid form instructions yield result of the defined instructions
with the z bit zero. If the decrement and test CTR option is specified for the bcctr or
bcctrl instructions, the target address of the branch is the new value of the CTR. Condition is evaluated correctly, including the value of the counter after decrement.
3.13.7.2 Branch Prediction
The core uses the y bit to predict path for pre-fetch. Prediction is only done for notready branch conditions. No prediction is done for branches to link or count register if
the target address is not ready. Refer to RCPU Reference Manual (Conditional Branch
Control) for more information.
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3.13.8 The Fixed-Point Processor
3.13.8.1 Fixed-Point Instructions
The core implements the following instructions:
• Fixed-point arithmetic instructions
• Fixed-point compare instructions
• Fixed-point trap instructions
• Fixed-point logical instructions
• Fixed-point rotate and shift instructions
• Move to/from system register instructions
All instructions are defined for the fixed-point processor in the UISA in the hardware.
For performance of the various instructions, refer to Table 3-22.
— Move To/From System Register Instructions. Move to/from invalid special
registers in which spr0 = 1 yields invocation of the privilege instruction error interrupt handler if the processor is in problem state. For a list of all implemented
special registers, refer to Table 3-2 Supervisor-Level SPRs, and Table 3-3
Development Support SPRs.
— Fixed-Point Arithmetic Instructions. If an attempt is made to perform any of
the divisions in the divw[o][.] instruction:
0x80000000 ÷ -1
<anything> ÷ 0
Then, the contents of RT are 0x80000000 and if Rc =1, the contents of bits in
CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is set to the correct value. If an
attempt is made to perform any of the divisions in the divw[o][.] instruction,
<anything> ÷ 0. Then, the contents of RT are 0x80000000 and if Rc = 1, the
contents of bits in CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is set to the
correct value. In cmpi, cmp, cmpli, and cmpl instructions, the L-bit is applicable
for 64-bit implementations. In 32-bit implementations, if L = 1 the instruction
form is invalid. The core ignores this bit and therefore, the behavior when L =
1 is identical to the valid form instruction with L = 0
3.13.9 Floating-Point Processor
3.13.9.1 General
The core implements all floating-point features as defined in the UISA, including the
non-IEEE working mode. Some features require software assistance. For more information refer to RCPU Reference Manual (Floating-point Load Instructions) for more
information.
3.13.9.2 Optional instructions
The only optional instruction implemented by MPC555 hardware is Store FloatingPoint as Integer Word Indexed (stfiwx). An attempt to execute any other optional
instruction causes the implementation dependent software emulation interrupt to be
taken.
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3.13.10 Load/Store Processor
The load/store processor supports all of the 32-bit implementation fixed-point PowerPC load/store instructions in the hardware.
3.13.10.1 Fixed-Point Load With Update and Store With Update Instructions
For load with update and store with update instructions, where RA = 0, the EA is written into R0. For load with update instructions, where RA = RT, RA is boundedly
undefined.
3.13.10.2 Fixed-Point Load and Store Multiple Instructions
For these types of instructions, EA must be a multiple of four. If it is not, the system
alignment error handler is invoked. For a lmw instruction (if RA is in the range of registers to be loaded), the instruction completes normally. RA is then loaded from the
memory location as follows:
RA ← MEM(EA+(RA-RT)*4, 4)
3.13.10.3 Fixed-Point Load String Instructions
Load string instructions behave the same as load multiple instructions, with respect to
invalid format in which RA is in the range of registers to be loaded. In case RA is in the
range, it is updated from memory.
3.13.10.4 Storage Synchronization Instructions
For these type of instructions, EA must be a multiple of four. If it is not, the system
alignment error handler is invoked.
3.13.10.5 Floating-Point Load and Store With Update Instructions
For Load and Store with update instructions, if RT = 0 then the EA is written into R0.
3.13.10.6 Floating-Point Load Single Instructions
In case the operand falls in the range of a single denormalized number the FloatingPoint Assist Interrupt handler is invoked.
Refer to RCPU Reference Manual (Floating-Point Assist for Denormalized Operands)
for complete description of handling denormalized floating-point numbers.
3.13.10.7 Floating-Point Store Single Instructions
In case the operand falls in the range of a single denormalized number, the FloatingPoint Assist Interrupt handler is invoked.
In case the operand is ZERO it is converted to the correct signed ZERO in single-precision format.
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In case the operand is between the range of single denormalized and double denormalized it is considered a programming error. The hardware will handle this case as if
the operand was single denormalized.
In case the operand falls in the range of double denormalized numbers it is considered
a programming error. The hardware will handle this case as if the operand was ZERO.
The following check is done on the stored operand in order to determine whether it is
a denormalized single-precision operand and invoke the Floating-Point Assist Interrupt handler:
(FRS1:11 ≠ 0) AND (FRS1:11 ≤ 896)
Refer to RCPU Reference Manual (Floating-Point Assist for Denormalized Operands)
for complete description of handling denormalized floating-point numbers.
3.13.10.8 Optional Instructions
No optional instructions are supported.
3.13.10.9 Little-Endian Byte Ordering
The load/store unit supports little-endian byte ordering as specified in the UISA. In little-endian mode, if an attempt is made to execute an individual scalar unaligned
transfer, as well as a multiple or string instruction, an alignment interrupt is taken.
3.14 PowerPC Virtual Environment Architecture (VEA)
3.14.1 Atomic Update Primitives
Both the lwarx and stwcx instructions are implemented according to the PowerPC
architecture requirements. The MPC555 does not provide support for snooping an
external bus activity outside the chip. The provision is made to cancel the reservation
inside the MPC555 by using the CR_B and KR_B input pins.
3.14.2 Effect of Operand Placement on Performance
The load/store unit hardware supports all of the PowerPC load/store instructions. An
optimal performance is obtained for naturally aligned operands. These accesses result
in optimal performance (one bus cycle) for up to 4 bytes size and good performance
(two bus cycles) for double precision floating-point operands. Unaligned operands are
supported in hardware and are broken into a series of aligned transfers. The effect of
operand placement on performance is as stated in the VEA, except for the case of 8byte operands. In that case, since the MPC555 uses a 32-bit wide data bus, the performance is good rather than optimal.
3.14.3 Storage Control Instructions
The MPC555 does not implement cache control instructions (icbi, isync, dcbt, dcbi,
dcbf, dcbz, dcbst, and dcbtst) .
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3.14.4 Instruction Synchronize (isync) Instruction
The isync instruction causes a reflect which waits for all prior instructions to complete
and then executes the next sequential instruction. Any instruction after an isync will
see all effects of prior instructions.
3.14.4.1 Enforce In-Order Execution of I/O (eieio) Instruction
When executing an eieio instruction, the load/store unit will wait until all previous
accesses have terminated before issuing cycles associated with load/store instructions following the eieio instruction.
3.14.5 Timebase
A description of the timebase register may be found in Section 6 System configuration and protection and in Section 8 Clocks and Power Control.
3.15 POWERPC Operating Environment Architecture (OEA)
The MPC555 has an internal memory space that includes memory-mapped control
registers and internal memory used by various modules on the chip. This memory is
part of the main memory as seen by the core but cannot be accessed by any external
system master.
3.15.1 Branch Processor Registers
3.15.1.1 Machine State Register (MSR)
The Floating-Point Exception mode encoding in the MPC555 core is as follows:
:
Table 3-23 Floating-Point Exception Mode Encoding
Mode
FE0
FE1
Ignore exceptions
0
0
Precise
0
1
Precise
1
0
Precise
1
1
The SF bit is reserved set to zero
The IP bit initial state after reset is set as programmed by the Reset configuration as
specified by the USIU specification.
3.15.1.2 Branch Processors Instructions
The core implements all the instructions defined for the branch processor in the UISA
in the hardware.
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3.15.2 Fixed-Point Processor
3.15.2.1 Special Purpose Registers
• Unsupported Registers — The following registers are not supported by the
MPC555: SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U, IBAT2L,
IBAT3U, IBAT3L, DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L, DBAT3U,
DBAT3L
• Added Registers — For a list of added special purpose registers, refer to Table
3-2 Supervisor-Level SPRs, and Table 3-3 Development Support SPRs.
3.15.3 Storage Control Instructions
Storage Control Instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not implemented by the MPC555.
3.15.4 Interrupts
The core implements all storage-associated interrupts as precise interrupts. This
means that a load/store instruction is not complete until all possible error indications
have been sampled from the load/store bus. This also implies that a store, or a nonspeculative load instruction is not issued to the load/store bus until all previous
instructions have completed. In case of a late error, a store cycle (or a nonspeculative
load cycle) can be issued and then aborted.
In each interrupt handler, when registers SRR0 and SRR1 are saved, MSRRI can be
set to 1.
The following paragraphs define the types of OEA interrupts The exception table vector defines the offset value by interrupt type. Refer to Table 3-21.
3.15.4.1 System Reset Interrupt
A system reset interrupt occurs when the IRQ0 pin is asserted and the following registers are set.
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Register Name
Bits
Description
Set to the effective address of the instruction that the processor attempts to execute next if no interrupt conditions are
present
Save/Restore Register 0 (SRR0)
1:4
Set to 0
10:15
Set to 0
Other
Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSRRI
Save/Restore Register 1 (SRR1)
IP
No change
ME
No change
LE
Bit is copied from ILE
Machine State Register (MSR)
Other
Set to 0
3.15.4.2 Machine Check Interrupt
A machine check interrupt indication is received from the U-bus as a possible
response either to the address or data phase. It is usually caused by one of the following conditions:
• The accessed address does not exist
• A data error is detected
As defined in the OEA, machine check interrupts are enabled when MSRME = 1. If
MSRME = 0 and a machine check interrupt indication is received, the processor enters
the checkstop state. The behavior of the core in checkstop state is dependent on the
working mode as defined in 21.4.1.1 Debug Mode Enable vs. Debug Mode Disable.
When the processor is in debug mode enable, it enters the debug mode instead of the
checkstop state. When in debug mode disable, instruction processing is suspended
and cannot be restarted without resetting the core.
An indication is sent to the SIU which may generate an automatic reset in this condition. Refer to SECTION 7 RESET for more details. If the machine check interrupt is
enabled, MSRME = 1, it is taken. If SRR1 Bit 30 = 1, the interrupt is recoverable and the
following registers are set.
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Register Name
Bits
Set to the effective address of the instruction that caused the
interrupt
Save/Restore Register 0 (SRR0)
1
Save/Restore Register 1 (SRR1)
Description
Set to 1 for instruction fetch-related errors and 0 for load/
store-related errors
2:4
Set to 0
10:15
Set to 0
Other
Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSRRI
IP
No change
ME
No change
LE
Bit is copied from ILE
Machine State Register (MSR)
Other
Set to 0
For load/store bus cases, these registers are also set:
Register Name
Data/Storage Interrupt Status
Register (DSISR)
Data Address Register (DAR)
Bits
Description
0:14
Set to 0
15:16
Set to bits 29:30 of the instruction if X-form and to 0b00 if Dform
17
Set to Bit 25 of the instruction if X-form and to Bit 5 if D-form
18:21
Set to bits 21:24 of the instruction if X-form and to bits 1:4 if
D-form
22:31
Set to bits 6:15 of the instruction
Set to the effective address of the data access that caused
the interrupt
Execution resumes at offset 0x00200 from the base address indicated by MSRIP.
3.15.4.3 Data Storage Interrupt
A data storage interrupt is never generated by the hardware. The software may branch
to this location as a result of Implementation-Specific Data Storage Protection Error
interrupt.
3.15.4.4 Instruction Storage Interrupt
An instruction storage interrupt is never generated by the hardware. The software may
branch to this location as a result of an Implementation-Specific Instruction Storage
Protection Error interrupt.
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3.15.4.5 Alignment Interrupt
An alignment exception occurs as a result of one of the following conditions:
• The operand of a floating-point load or store is not word aligned.
• The operand of load/store multiple is not word aligned.
• The operand of lwarx or stwcx is not word aligned.
• The operand of load/store individual scalar instruction is not naturally aligned
when MSRLE = 1.
• An attempt to execute multiple/string instruction is made when MSRLE = 1.
3.15.4.6 Floating-Point Enabled Exception Type Program Interrupt
A floating-point enabled exception type program interrupt is generated if ((MSRFE0 |
MSRFE1) &FPSCRFEX) is set as a result of move to FPSCR instruction, move to MSR
instruction or the execution of the rfi instruction. A floating-point enabled exception
type program interrupt is not generated by floating-point arithmetic instructions.
Instead if ((MSRFE0 | MSRFE1) &FPSCRFEX) is set, the floating-point assist interrupt
is generated.
3.15.4.7 Illegal Instruction Type Program Interrupt
An illegal instruction type program interrupt is not generated by the core. An implementation dependent software emulation interrupt is generated instead.
3.15.4.8 Privileged Instruction Type Program interrupt
A privileged instruction type program interrupt is generated for an on-core valid SPR
field or any SPR encoded as an external to the core special register if SPR0 = 1 and
MSRPR = 1, as well as an attempt to execute privileged instruction when MSRPR = 1.
3.15.4.9 Floating-Point Unavailable Interrupt
The floating-point unavailable interrupt is generated by the MPC555 core as defined
in the OEA.
3.15.4.10 Trace Interrupt
A trace interrupt occurs if MSRSE = 1 and any instruction except rfi is successfully completed or MSRBE = 1 and a branch is completed. Notice that the trace interrupt does
not occur after an instruction that caused an interrupt (for instance, sc). A monitor/
debugger software must change the vectors of other possible interrupt addresses to
single-step such instructions. If this is unacceptable, other debug features can be
used. Refer to SECTION 21 DEVELOPMENT SUPPORT for more information. The
following registers are set:
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Register Name
Bits
Description
Set to the effective address of the instruction following the executed instruction
Save/Restore Register 0 (SRR0)
1:4
Set to 0
10:15
Set to 0
Other
Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSRRI
Save/Restore Register 1 (SRR1)
IP
No change
ME
No change
LE
Bit is copied from ILE
Machine State Register (MSR)
Other
Set to 0
Execution resumes at offset 0x00D00 from the base address indicated by MSRIP.
3.15.4.11 Floating-Point Assist Interrupt
A floating-point assist interrupt occurs in the following cases:
• When a floating-point exception condition is detected, the corresponding floatingpoint enable bit in the FPSCR (floating-point status and control register) is set (exception enabled) and ((MSRFE0 | MSRFE1) = 1). Note that when ((MSRFE0 |
MSRFE1) and FPSCRFEX) is set as a result of move to FPSCR, move to MSR or
rfi, the floating-point assist interrupt handler is not invoked.
• When an intermediate result is detected and the floating-point underflow exception is disabled (FPSCRUE = 0)
• In some cases when at least one of the source operands is denormalized.
The following registers are set:
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Register Name
Bits
Set to the effective address of the instruction that caused the
interrupt
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Description
1:4
Set to 0
10:15
Set to 0
Other
Loaded from bits 16:31 of MSR1
IP
No change
ME
No change
LE
Bit is copied from ILE
Machine State Register (MSR)
Other
Set to 0
NOTES:
1. In the current implementation bit 30 of the SRR1 is never cleared other then by loading zero
value from MSR RI.
Execution resumes at offset 0x00E00 from the base address indicated by MSRIP.
3.15.4.12 Implementation-Dependent Software Emulation Interrupt
An implementation-dependent software emulation interrupt occurs in the following
instances:
• When executing any non-implemented instruction. This includes all illegal and unimplemented optional instructions and all floating-point instructions.
• When executing a mtspr or mfspr that specifies on-core non-implemented register, regardless of SPR0.
• When executing a mtspr or mfspr that specifies off-core non-implemented register and SPR0 = 0 or MSRPR = 0 (no program interrupt condition).
• Program interrupt is generated if ((MSRFE0 | MSRFE1) and FPSCRFEX) is set as
a result of move to FPSCR instruction, move to MSR instruction, or the execution
of the rfi instruction.
• Floating-point enabled exception type program interrupt is not generated by floating-point arithmetic instructions, instead if ((MSRFE0 | MSRFE1) &FPSCRFEX) is
set, the floating-point assist interrupt is generated.
In addition, the following registers are set:
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Register Name
Bits
Description
Set to the effective address of the instruction that caused the
interrupt
Save/Restore Register 0 (SRR0)
1:4
Set to 0
10:15
Set to 0
Other
Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSRRI
Save/Restore Register 1 (SRR1)
IP
No change
ME
No change
LE
Bit is copied from ILE
Machine State Register (MSR)
Other
Set to 0
Execution resumes at offset 0x01000 from the base address indicated by MSRIP.
3.15.4.13 Implementation-Specific Instruction Storage Protection Error Interrupt
The implementation-specific instruction storage protection error interrupt occurs in the
following cases:
• The fetch access violates storage protection.
• The fetch access is to guarded storage and MSRIR = 1.
The following registers are set:
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Register Name
Bits
Set to the effective address of the instruction that caused the
interrupt
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Description
1
Set to 0
2
Set to 0
3
Set to 1 if the fetch access was to a guarded storage when
MSRIR = 1, otherwise set to 0
4
Set to 1 if the storage access is not permitted by the protection mechanism; otherwise set to 0
10
Set to 0
11:15
Set to 0
Other
Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSRRI
IP
No change
ME
No change
LE
Bit is copied from ILE
Machine State Register (MSR)
Other
Set to 0
Execution resumes at offset 0x01300 from the base address indicated by MSRIP.
3.15.4.14 Implementation-Specific Data Storage Protection Error Interrupt
The implementation-specific data storage protection error interrupt occurs in the following case:
• The access violates the storage protection.
The following registers are set:
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Register Name
Bits
Description
Set to the effective address of the instruction that caused the
interrupt
Save/Restore Register 0 (SRR0)
1:4
Set to 0
10:15
Set to 0
Other
Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSRRI
Save/Restore Register 1 (SRR1)
IP
No change
ME
No change
LE
Bit is copied from ILE
Machine State Register (MSR)
Data/Storage Interrupt Status
Register (DSISR)
Other
Set to 0
0
Set to 0
1
Set to 0
2:3
Set to 0
4
Set to 1 if the storage access is not permitted by the protection mechanism. Otherwise set to 0
5
Set to 0
6
Set to 1 for a store operation and to 0 for a load operation
7:31
Data Address Register (DAR)
Set to 0
Set to the effective address of the data access that caused
the interrupt
Execution resumes at offset 0x01400 from the base address indicated by MSRIP.
3.15.4.15 Implementation-Specific Debug Interrupts
Implementation-specific debug interrupts occur in the following cases:
• When there is an internal breakpoint match (for more details, refer to SECTION
21 DEVELOPMENT SUPPORT.
• When a peripheral breakpoint request is asserted to the MPC555 core.
• When the development port request is asserted to the MPC555 core. Refer to
SECTION 21 DEVELOPMENT SUPPORT for details on how to generate the development port-interrupt request.
The following registers are set:
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Register Name
Bits
Description
For I-breakpoints, set to the effective address of the instruction that caused the interrupt. For L-breakpoint, set to the effective address of the instruction following the instruction that
caused the interrupt. For development port maskable request
or a peripheral breakpoint, set to the effective address of the
instruction that the processor would have executed next if no
interrupt conditions were present. If the development port request is asserted at reset, the value of SRR0 is undefined.
Save/Restore Register 0 (SRR0)
1:4
Set to 0
10:15
Set to 0
Other
Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSRRI.
If the development port request is asserted at reset, the value
of SRR1 is undefined.
Save/Restore Register 1 (SRR1)
IP
No change
ME
No change
LE
Bit is copied from ILE
Machine State Register (MSR)
Other
Set to 0
For L-bus breakpoint instances, these registers are set to:
Register Name
BAR
DAR and DSISR
Bits
Description
Set to the effective address of the data access as computed
by the instruction that caused the interrupt
Do not change
Execution resumes at offset from the base address indicated by MSRIP as follows:
• 0x01D00 – For instruction breakpoint match
• 0x01C00 – For data breakpoint match
• 0x01E00 – For development port maskable request or a peripheral breakpoint
• 0x01F00 – For development port non-maskable request
3.15.4.16 Partially Executed Instructions
In general, the architecture permits instructions to be partially executed when an alignment or data storage interrupt occurs. In the core, instructions are not executed at all
if an alignment interrupt condition is detected and data storage interrupt is never generated by the hardware. In the MPC555, the instruction can be partially executed only
in the case of the load/store instructions that cause multiple access to the memory
subsystem. These instructions are:
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• Multiple/string instructions
• Unaligned load/store instructions
In the last case, the store instruction can be partially completed if one of the accesses
(except the first one) causes the data storage protection error. The implementationspecific data storage protection interrupt is taken in this case. For the update forms,
the update register (RA) is not altered.
3.15.5 Timer Facilities
Descriptions of the timebase and decrementer registers can be found in SECTION 6
SYSTEM CONFIGURATION AND PROTECTION and in SECTION 8 CLOCKS AND
POWER CONTROL.
3.15.6 Optional Facilities and Instructions
Any other OEA optional facilities and instructions (except those that are discussed
here) are not implemented by the MPC555 hardware. Attempting to execute any of
these instructions causes an implementation dependent software emulation interrupt
to be taken.
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SECTION 4
BURST BUFFER
The burst buffer module consists of the burst buffer controller (BBC) and the instruction memory protection unit (IMPU).
The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto
the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order
to take full advantage of the U-bus bandwidth. It can handle both burstable and nonburstable external memories as well as non-burstable internal memories (flash
EEPROM, SRAM).
The IMPU allows the memory to be divided into four regions with different attributes,
as well as a default global region (for memory space that is not included in either of the
two regions). Each of the two regions can be of size 4 Kbytes to 4 Gbytes. Overlap
between regions is allowed.
The IMPU includes registers that contain the following information: region base
address, region size and the region’s access permissions. For each access (from the
processor to the memory), the IMPU finds which region matches the address. If more
than one region matches, the region with the lowest index is chosen. If no region is
matched, the global region is chosen.
The IMPU compares the attributes of the access from the processor to the attributes
of the appropriate region. If the access is allowed, the proper signals are sent to the
BBC. If the access is not permitted, an interrupt is sent to the processor.
The IMPU does not support address translation. The effective fetch address issued by
the processor is the one that is transferred to the U-bus.
4.1 Burst Buffer Block Diagram
Figure 4-1 is a block diagram of the burst buffer.
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IMPU
Protection-Abort to U-bus
RCPU
InstructionAddress Bus
In-Page Access
BBC
U-bus
Figure 4-1 Burst Buffer Block Diagram
4.2 Burst Buffer Features
The BBC offers the following features:
• Supports pipelined access to internal memory and burstable access to the external memory.
• Supports the de-coupled interface with the RCPU instruction unit.
• Serves as parked master on the U-bus, resulting in zero clocks delay for RCPU
fetch access to cross to the U-bus.
• Full utilization of the U-bus pipeline for fetch accesses.
• Tightly interfaced with L2U Interface module, taking advantage of full U-bus bandwidth and back-to-back accesses.
• Supports program trace and show cycle attributes.
• Supports special attribute for debug port fetch accesses.
• Is programmed using the MPC555 mtspr/mfspr instructions to/from implementation specific special-purpose registers.
• Designed for minimum power consumption.
The IMPU has the following features:
• Four regions in which the base address and size can be programmed.
• Region sizes of 4 Kbytes up to 4 Gbytes (in powers of two) can be programmed.
(A region must start on the specified region size boundary.)
• Overlap between regions is allowed.
• Each of the four regions supports the following attributes:
— Access protection (user/supervisor fetch or no access).
— Guarded attribute (causes an interrupt in case of fetch try).
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— On/off option
• Global region entry declares the default access protection and guarded attributes
for all memory areas not covered by the four regions:
• Interrupt generated upon access violation or fetch from guarded region.
• MPC555 MSR[IR] bit controls MPU protection.
• Programming is done using MPC555 mtspr/mfspr instructions to/from implementation specific special purpose registers.
• Designed for minimum power consumption.
4.3 Little-Endian Support
The BBC supports little-endian operation only when bursts are disabled (see BBC
Module Configuration Register (BBCMCR) on page 11 for more details. The BBC does
not support little-endian in the following cases:
1. For internal code/data memories
4.4 Modes Of Operation
The burst buffer module can operate in the following modes:
• Normal
• Slave
• Reset
• Debug
• Standby
• Burst
The modes of operation are described in the following paragraphs.
4.4.1 Normal Operation
During normal operation, the burst buffer module transfers fetch accesses from the
CPU to the U-bus. When a new access is issued by the CPU, it is transferred in parallel
to both the IMPU and the BBC. The IMPU compares the address of the access to its
region programming. The BBC determines whether the access can be immediately
transferred to the U-bus. If not, it requests the U-bus for the next clock.
Each new BBC U-bus access is accompanying by the burst request attribute. If burstable access is enabled, the BBC performs a burst access; otherwise, it performs a
single access.
If the IMPU detects an access violation, it does the following:
• Cancels the request that was forwarded to the BBC
• Informs the RCPU core that the requested address generated an exception
If the required address contains show cycle or program trace attributes, the BBC delivers the access to the U-bus even if the request is cancelled (due to the exception it
caused).
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The BBC forwards show cycle, program trace and debug port access attributes
accompanying the CPU access along with the U-bus access.
4.4.2 Slave Operation.
The Burst Buffer Module is operating as a U-bus slave module when the Instruction
Memory Protection Unit (IMPU) registers are accessed by the user in order to be programmed. This programming is done using the mtspr /mfspr instructions.
4.4.3 Reset Operation
On reset the BBC goes to an idle state, and all pending U-bus accesses are ignored.
The IMPU goes to a disabled state in which all memory space is accessible to both
user and supervisor.
4.4.4 Debug Mode Operation
When the CPU is in debug mode, fetch accesses are attached with a special attribute.
If this attribute is asserted, the BBC must initiate not-burstable accesses to the debug
port.
4.4.5 Standby Mode Operation
In this low-power modes the CPU stops issuing further accesses. The BBC clocks are
turned off, and the BBC enters a power save state. When the low-power mode is
exited, clocks are activated and a new access from the CPU will activate the BBC.
4.4.6 Burst Operation
The BBC can run burst accesses on the U-bus. Such burst cycles, if forwarded to
external memory, are then exported to the EBI as burst cycles (if bursts are enabled
by the USIU).
The BE bit defined in 4.6.4 BBC Module Configuration Register (BBCMCR) determines whether the BBC operates burst cycles or not. Burst requests are enabled only
when the BE bit is set.
Note that the negated state of the BE bit is useful mainly when the RCPU core runs in
serialized mode.
4.4.7 Error Detection.
If the IMPU detects access violation, the following actions must be taken:
1. Cancel the request that was forwarded to the burst buffer controller
2. Inform the RCPU core that the requested address generated an exception
If the required address contains show cycle or program trace attributes, than the BBC
delivers the access onto the U-bus even if the request is cancelled (due to the exception it caused).
The way the IMPU notifies the RCPU core for an interrupt is by feeding error information into four bits (1, 3, 4 and 10) in the SRR1 regsiter in the core. Only one bit is set
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at a time. The Exception vector (address) that the core issues for this event is 0xnnn01300. The encoding of the status bits is as follows:
• SRR1 = 0
• SRR3 = Gaurded storage.
• SRR4 = Protected storage.
• SRR10 = 0
4.5 Exception Table Relocation
The BBC has the ability to relocate the exception table. The relocation feature always
maps the exception table into the internal memory space of the MPC555. This feature
is important in multi-MPC555 systems, where more than one MCU can have internal
exception tables with the same exception addresses issued by the RCPU.
The relocation feature also saves the wasted space between exception table entries
when each exception entry contains only a branch instruction to the exception routine,
which is located elsewhere.
If exception relocation is enabled (ETRE bit is set in the BBCMCR), all exception routines (except the reset exception routine) can be controlled to either remain in the
lower addresses of the memory (base address + exception offset) or to be relocated
to memory (base address + 32 Kbytes). The reset exception routine location is fixed
in memory (base address + the reset exception offset) and can not be relocated.
See 4.6.4 BBC Module Configuration Register (BBCMCR) for programming details.
4.5.1 Exception Table Relocation Operation
When an exception is requested, the CPU initiates a fetch cycle that branches to the
exception routine associated with the exception that caused the fetch. The exception
addresses are fixed within the RCPU architecture and are 0x100 bytes apart from
each other, starting at address 0x0000_0100 or 0xr FFF0_0100, depending on the
value of the MSR[IP] bit.
If the relocation feature is disabled, the BBC transfers the exception fetch address to
the internal bus of the MPC555 with no interference.
In order to activate exception table relocation, the following steps are required:
1. Set the MSR[IP] bit. To set this bit out of reset, set the appropriate bit in the reset configuration word.
2. Set the ETRE bit in BBCMCR register. See 4.6.4 BBC Module Configuration
Register (BBCMCR) for programming details.
If the relocation feature is enabled, the BBC translates the starting address of the
exception routine into the address located at the lowest portion of the internal memory.
At that location, the user must insert a series (table) of consecutive branch instructions
that point to the appropriate exception routines. Thus, the CPU branches twice to
reach the appropriate exception routine.
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Note that the 8 Kbytes allocated for the exception table can be almost fully utilized.
This is possible if the MPC555’s address space is not mapped to the exception
address space — that is, if addresses 0xFFF0_0000 to 0xFFF0_1FFF are not part of
the MPC555 address apace. In this case, these 8 Kbytes can be fully utilized by the
compiler, except for the lower 64 words (256 bytes), which are reserved for the exception pointers.
Note also that if the CPU issues any address that falls between two successive exception entries (e.g. 0xFFF0_0104), then an exception is generated to the CPU if
exception relocation is enabled. See 4.6.4 BBC Module Configuration Register
(BBCMCR).
.
Table 4-1 Exception Addresses Mapping by BBC
Name of Exception
Address Issued by
CPU (20 LSBs)1
Mapped Address by
Exception Table Relocation Logic
BBCMCR[OERC] = 02 BBCMCR[OERC] = 1
Reserved
0x0_0000
0x0000
0x8000
System Reset
0x0_0100
0x0008
0x00083
Machine Check
0x0_0200
0x0010
0x8010
Data Storage
0x0_0300
0x0018
0x8018
Instruction Storage
0x0_0400
0x0020
0x8020
External Interrupt
0x0_0500
0x0028
0x8028
Alignment
0x0_0600
0x0030
0x8030
Program
0x0_0700
0x0038
0x8038
Floating Point unavailable
0x0_0800
0x0040
0x8040
Decrementer
0x0_0900
0x0048
0x8048
Reserved
0x0_0A00
0x0050
0x8050
Reserved
0x0_0B00
0x0058
0x8058
System Call
0x0_0C00
0x0060
0x8060
Trace
0x0_0D00
0x0068
0x8068
Floating Point Assist
0x0_0E00
0x0070
0x8070
Implementation Dependant
Software Emulation
0x0_1000
0x0080
0x8080
Implementation Dependant Storage Error
0x0_1300
0x0098
0x8098
Implementation Dependant Data Breakpoint
0x0_1C00
0x00E0
0x80E0
Implementation Dependant
Instruction Breakpoint
0x0_1D00
0x00E8
0x80E8
Implementation Dependant Maskable
External Breakpoint
0x0_1E00
0x00F0
0x80F0
Non-Maskable External Breakpoint
0x0_1F00
0x00F8
0x80F8
NOTES:
1. Assuming 12 MSBs = 0xFFF0
2. OERC bit; See 4.6.4 BBC Module Configuration Register (BBCMCR).
3. The reset exception is NOT affected by OERC.
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Exception Pointer by RCPU
Internal Memory Structure
branch to...
0
branch to...
branch to...
branch to...
100
branch to...
branch to...
branch to...
200
branch to...
branch to...
branch to...
300
branch to...
branch to...
branch to...
400
Exception Table
branch to...
branch to...
branch to...
branch to...
500
branch to...
branch to...
branch to...
600
branch to...
branch to...
branch to...
700
branch to...
branch to...
branch to...
branch to...
branch to...
1F00
branch to...
branch to...
branch to...
F8
branch to...
Main code can start here
Figure 4-2 Exception Table Entries Mapping
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4.6 Burst Buffer Programming Model
The BBC and IMPU module configuration registers are MPC555 special-purpose registers (SPRs). They are programmed with the MPC555 mtspr/mfspr instructions.
All the registers can be accessed in supervisor mode only. The processor generates
an exception internally if an attempt is made to access the registers from user mode.
The following 32-bit registers contain the starting address and the size of the region.
There is one register for each region.
Table 4-2 Region Base Address Registers RBA[0:1]
Register Name
Address
(Decimal)
ub_addr[18:27]
(hex)
MI_RBA0
784
0x2180
MI_RBA1
785
0x2380
MI_RBA2
786
0x2580
MI_RBA3
787
0x2780
The following registers hold the attributes of the corresponding regions and of the
default region. Each of the four MI_RAx registers contains access permission
attributes. The MI_GRA (global region attribute) register contains two additional bits to
enable each of the MI_RBAx registers.
Table 4-3 Region Attributes Registers
Register Name
Address
(Decimal)
ub_addr [18:27]
(Hex)
MI_RA0
816
0x2190
MI_RA1
817
0x2390
MI_RA2
818
0x2590
MI_RA3
818
0x2790
MI_GRA
528
0x2100
The BBC holds only one register, the BBC module configuration register (BBCMCR).
Table 4-4 BBC Module Configuration Register
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Register name
Addr
(Decimal)
ub_addr [0:31]
(Hex)
BBCMCR
560
0x2110
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4.6.1 Region Base Address Registers
MI_RBA[0:3] — Region Base Address Register
SPR 784 – 787
MSB
0
15
RA
RESET:
Unaffected by Reset
LSB
31
16
RA
Reserved
RESET:
Unaffected by Reset
Table 4-5 MI_RBA[0:3] Bit Settings
Bit(s)
Name
Description
0:19
RA
Region address. This field defines the base address (most significant 20 bits) for the region.
20:31
—
Reserved
4.6.2 Region Attribute Registers MI_RA[0:3] Description
MI_RA[0:3] – Region Attribute Registers
SPR 816 – 819
MSB
0
15
RS
RESET:
Unaffected by Reset
LSB
31
16
RS
PP
RESERVED
G
RESERVED
RESET:
Unaffected by Reset
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Table 4-6 MI_RA[0:3] Bit Settings
Bit(s)
Name
Description
RS
Region size. The region size is a power of two, determined as follows:
0000_0000_0000_0000_0000 - 4 Kbytes
0000_0000_0000_0000_0001 - 8 Kbytes
0000_0000_0000_0000_0011 - 16 Kbytes
0000_0000_0000_0000_0111 - 32 Kbytes
0000_0000_0000_0000_1111 - 64 Kbytes
0000_0000_0000_0001_1111 - 128 Kbytes
0000_0000_0000_0011_1111 - 256 Kbytes
0000_0000_0000_0111_1111 - 512 Kbytes
0000_0000_0000_1111_1111 - 1 Mbyte
0000_0000_0001_1111_1111 - 2 Mbytes
0000_0000_0011_1111_1111 - 4 Mbytes
0000_0000_0111_1111_1111 - 8 Mbytes
0000_0000_1111_1111_1111 - 16 Mbytes
0000_0001_1111_1111_1111 - 32 Mbytes
0000_0011_1111_1111_1111 - 64 Mbytes
0000_0111_1111_1111_1111 - 128 Mbytes
0000_1111_1111_1111_1111 - 256 Mbytes
0001_1111_1111_1111_1111 - 512 Mbytes
0011_1111_1111_1111_1111 - 1 Gbyte
0111_1111_1111_1111_1111 - 2 Gbytes
1111_1111_1111_1111_1111 - 4 Gbytes
20:21
PP
Protection bits
00 = No supervisor access, no user access
01 = Supervisor fetch access, no user access
10 = Supervisor fetch access, user fetch access
11 = Supervisor fetch access, user fetch access
22:24
—
Reserved
25
G
Guarded attribute for region
0 = Fetch is allowed from guarded region.
1 = Fetch is prohibited from guarded region. An attempted fetch will generate an exception.
26:31
—
Reserved
0:19
4.6.3 Global Region Attribute Register Description (MI_GRA)
MI_GRA — Global Region Attribute Register
SPR 528
MSB
0
ENR0
15
ENR1
ENR2 ENR3
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LSB
31
16
RESERVED
PP
RESERVED
G
RESERVED
RESET:
0
0
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0
0
0
0
0
0
0
0
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0
0
0
0
0
0
MPC555
USER’S MANUAL
Table 4-7 MI_GRA Bit Settings
Bit(s)
Name
Description
0
ENR0
Enable region 0 of IMPU
0 = Region 0 is off
1 = Region 0 is on
1
ENR1
Enable region 1 of IMPU
0 = Region 1 is off
1 = Region 1 is on
2
ENR2
Enable region 2 of IMPU
0 = Region 2 is off
1 = Region 2 is on
3
ENR3
Enable region 3 of IMPU
0 = Region 3 is off
1 = Region 3 is on
4:19
—
Reserved
20:21
PP
Protection bits
00 = No supervisor access, no user access
01 = Supervisor fetch access, no user access
10 = Supervisor fetch access, user fetch access
11 = Supervisor fetch access, user fetch access
22:24
—
Reserved
25
G
Guarded attribute for region
0 = Fetch is allowed from guarded region.
1 = Fetch is prohibited from guarded region. An attempted fetch will generate an exception.
26:31
—
Reserved
4.6.4 BBC Module Configuration Register (BBCMCR)
BBCMCR — BBC Module Configuration Register
SPR 560
MSB
0
15
Reserved
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
Reserved
BE
ETRE OERC
Reserved
RESET:
0
0
0
ID[19]*
0
0
0
0
0
0
0
* Reset value is taken from the indicated bit of the reset configuration word.
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Table 4-8 BBCMCR Bit Settings
Bit(s)
Name
Description
16:17
—
Reserved
18
BE
Burst enable
0 = BBC does not request burst accesses
1 = BBC requests burst accesses
19
ETRE
Exception table relocation enable
0 = Exception table relocation is off — the BBC does not map exception addresses
1 = Exception table relocation is on — the BBC maps exception addresses to a branch instruction
table. Refer to 4.5 Exception Table Relocation.
20
OERC
Other exceptions relocation control.
0 = All exceptions except reset are mapped to the internal memory base address.
1 = All exceptions except reset are mapped to the internal memory base address + 32Kbytes.
21:31
—
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SECTION 5
UNIFIED SYSTEM INTERFACE UNIT
The unified system interface unit (USIU) of the MPC555 controls system start-up, system initialization and operation, system protection, and the external system bus. The
MPC555 USIU functions include the following:
• System configuration and protection
• Interrupt controller
• System reset monitoring and generation
• Clock synthesizer
• Power management
• External bus interface (EBI) control
• Memory controller
• Debug support
5.1 Module Overview
The system configuration and protection function controls the overall system configuration and provides various monitors and timers, including the bus monitor, software
watchdog timer, periodic interrupt timer, PowerPC decrementer, time base, and real
time clock. The interrupt controller and USIU are also included in the system configuration and protection function. Refer to SECTION 6 SYSTEM CONFIGURATION AND
PROTECTION for details.
The reset controller receives input from a number of reset sources and takes appropriate actions, depending on the source. The reset status register (RSR) reflects the
most recent source to cause a reset. Refer to SECTION 7 RESET for details.
The clock synthesizer generates the clock signals used by the SIU as well as the other
modules and external devices. This circuitry can generate the system clock from a 4MHz or 20-MHz crystal.
The SIU supports various low-power modes. Each supplies a different range of power
consumption, functionality and wake-up time. The clock scheme supports low-power
modes for applications that use the baud rate generators and/or serial ports during the
standby mode. The main system clock can be changed dynamically while the baud
rate generators and serial ports work with a fixed frequency. Clock generation and lowpower modes are described in SECTION 8 CLOCKS AND POWER CONTROL.
The external bus interface (EBI) handles the transfer of information between the internal busses and the memory or peripherals in the external address space. The
MPC555 is designed to allow external bus masters to request and obtain mastership
of the system bus, and if required access the on-chip memory and registers. SECTION
9 EXTERNAL BUS INTERFACE describes the bus operation.
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The memory controller module provides a glueless interface to many types of memory
devices and peripherals. It supports up to four memory banks, each with its own device
and timing attributes. See SECTION 10 MEMORY CONTROLLER for more
information.
5.2 SIU Architecture
Figure 5-1 is a block diagram of the MPC555 USIU.
CLOCKS & RESET
U--bus
MEMORY
CONTROLLER
MEMORY CONTROL LINES
Address
U-bus
I/F
Data
E-bus
INTERFACE
E-bus
SLAVE
I/F
* SW WATCH DOG
* BUS MONITOR
* PERIODIC INTERRUPT
* PowerPC TIMER &
DECREMENTOR
.
* REAL-TIME CLOCK
* DEBUG
* PIN MULTIPLEXING
* INTERRUPT CONTROLLER
SGPIO
Figure 5-1 MPC555 USIU Block Diagram
5.3 USIU Address Map
Table 5-1 is an address map of the SIU registers. Where not otherwise noted, registers are 32 bits wide. The address shown for each register is relative to the base
address of the MPC555 internal memory map. The internal memory block can reside
in one of eight possible 4-Mbyte memory spaces. See Figure 1-3 in SECTION 1
OVERVIEW for details.
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Table 5-1 USIU Address Map
Address
Register
0x2F C000
SIU Module Configuration Register (SIUMCR)
See Table 6-5 for bit descriptions.
0x2F C004
System Protection Control Register (SYPCR)
See Table 6-13 for bit descriptions.
0x2F C008
Reserved
0x2F C00E1
Software Service Register (SWSR)
See Table 6-14 for bit descriptions.
0x2F C010
Interrupt Pending Register (SIPEND)
See 6.13.2.1 SIPEND Register for bit descriptions.
0x2F C014
Interrupt Mask Register (SIMASK)
See 6.13.2.2 SIU Interrupt Mask Register (SIMASK) for bit descriptions.
0x2F C018
Interrupt Edge Level Mask (SIEL)
See 6.13.2.3 SIU Interrupt Edge Level Register (SIEL) for bit descriptions.
0x2F C01C
Interrupt Vector (SIVEC)
See 6.13.2.4 SIU Interrupt Vector Register for bit descriptions.
0x2F C020
Transfer Error Status Register(TESR)
See Table 6-15 for bit descriptions.
0x2F C024
USIU General-Purpose I/O Data Register (SGPIODT1)
See Table 6-21 for bit descriptions.
0x2F C028
USIU General-Purpose I/O Data Register 2 (SGPIODT2)
See Table 6-22 for bit descriptions.
0x2F C02C
USIU General-Purpose I/O Control Register (SGPIOCR)
See Table 6-23 for bit descriptions.
0x2F C030
External Master Mode Control Register (EMCR)
See Table 6-12 for bit descriptions.
0x2F C03C1
Pads Module Configuration Register (PDMCR)
See Table 2-3 for bit descriptions.
0x2F C040 —
0x2F C0FC
Reserved
0x2F C100
Base Register 0 (BR0)
See Table 10-7 for bit descriptions.
0x2F C104
Option Register 0 (OR0)
See Table 10-8 for bit descriptions.
0x2F C108
Base Register 1 (BR1)
See Table 10-7 for bit descriptions.
0x2F C10C
Option Register 1 (OR1)
See Table 10-8 for bit descriptions.
0x2F C110
Base Register 2 (BR2)
See Table 10-7 for bit descriptions.
0x2F C114
Option Register 2 (OR2)
See Table 10-8 for bit descriptions.
0x2F C118
Base Register 3 (BR3)
See Table 10-7 for bit descriptions.
0x2F C11C
Option Register 3 (OR3)
See Table 10-8 for bit descriptions.
0x2F C120 —
0x2F C13C
Reserved
Memory Controller Registers
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Table 5-1 USIU Address Map (Continued)
Address
Register
0x2F C140
Dual-Mapping Base Register (DMBR)
See Table 10-9 for bit descriptions.
0x2F C144
Dual-Mapping Option Register (DMOR)
See Table 10-10 for bit descriptions.
0x2F C148 —
0x2F C174
Reserved
0x2F C1781
Memory Status (MSTAT)
See Table 10-6 for bit descriptions.
0x2F C17A —
0x2F C1FFC
Reserved
0x2F C200
Time Base Status and Control (TBSCR)
See Table 6-16 for bit descriptions.
0x2F C204
Time Base Reference 0 (TBREF0)
See 6.13.4.3 Time Base Reference Registers for bit descriptions.
0x2F C208
Time Base Reference 1 (TBREF1)
See 6.13.4.3 Time Base Reference Registers for bit descriptions.
0x2F C20C —
0x2F C21C
Reserved
0x2F C220
Real-Time Clock Status and Control (RTCSC)
See Table 6-17 for bit descriptions.
0x2F C224
Real-Time Clock (RTC)
See 6.13.4.6 Real-Time Clock Register (RTC) for bit descriptions.
System Integration Timers
0x2F C228
Real-Time Alarm Seconds (RTSEC) — Reserved
0x2F C22C
Real-Time Alarm (RTCAL)
See 6.13.4.7 Real-Time Clock Alarm Register (RTCAL) for bit descriptions.
0x2F C230 —
0x2F C23C
Reserved
0x2F C240
PIT Status and Control (PISCR)
See Table 6-18 for bit descriptions.
0x2F C244
PIT Count (PITC)
See Table 6-19 for bit descriptions.
0x2F C248
PIT Register (PITR)
See Table 6-20 for bit descriptions.
0x2F C24C —
0x2F C27C
Reserved
0x2F C280
System Clock Control Register (SCCR)
See Table 8-9 for bit descriptions.
0x2F C284
PLL Low-Power and Reset Control Register (PLPRCR)
See Table 8-10 for bit descriptions.
0x2F C2881
Reset Status Register (RSR)
See Table 7-3 for bit descriptions.
0x2F C28C1
Change of Lock Interrupt Register (COLIR)
See Table 8-11 for bit descriptions.
0x2F C2901
VDDSRM Control Register (VSRMCR)
See Table 8-12 for bit descriptions.
0x2F C294 —
0x2F C2FC
Reserved
Clocks and Reset
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Table 5-1 USIU Address Map (Continued)
Address
Register
System Integration Timer Keys
0x2F C300
Time Base Status and Control Key (TBSCRK)
See Table 8-8 for bit descriptions.
0x2F C304
Time Base Reference 0 Key (TBREF0K)
See Table 8-8 for bit descriptions.
0x2F C308
Time Base Reference 1 Key (TBREF1K)
See Table 8-8 for bit descriptions.
0x2F C30C
Time Base and Decrementer Key (TBK)
See Table 8-8 for bit descriptions.
0x2F C310 —
0x2F C31C
Reserved
0x2F C320
Real-Time Clock Status and Control Key (RTCSCK)
See Table 8-8 for bit descriptions.
0x2F C324
Real-Time Clock Key (RTCK)
See Table 8-8 for bit descriptions.
0x2F C328
Real-Time Alarm Seconds Key (RTSECK)
See Table 8-8 for bit descriptions.
0x2F C32C
Real-Time Alarm Key (RTCALK)
See Table 8-8 for bit descriptions.
0x2F C330 —
0x2F C33C
Reserved
0x2F C340
PIT Status and Control Key (PISCRIK)
See Table 8-8 for bit descriptions.
0x2F C344
PIT Count Key (PITCK)
See Table 8-8 for bit descriptions.
0x2F C348 —
0x2F C37C
Reserved
Clocks and Reset Keys
0x2F C380
System Clock Control Key (SCCRK)
See Table 8-8 for bit descriptions.
0x2F C384
PLL Low-Power and Reset Control Register Key (PLPRCRK)
See Table 8-8 for bit descriptions.
0x2F C388
Reset Status Register Key (RSRK)
See Table 8-8 for bit descriptions.
0x2F C38C —
0x2F C3FC
Reserved
NOTES:
1. 16-bit register.
5.4 USIU PowerPC Memory Map
Table 5-2 lists the USIU PowerPC special-purpose registers (SPR). These registers
can be accessed with the PowerPC mtspr and mfspr instructions, or from an external
master (refer to 6.2 External Master Modes for details). All registers are 32 bits wide.
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Table 5-2 USIU Special-Purpose Registers
Internal
Address[0:31]
Register
Decimal Address
spr[5:9]:spr[0:4]1
0x2C00
Decrementer (DEC)
22
0x1880
Time Base — Read (TB)
268
0x1A80
Time Base Upper — Read (TBU)
269
0x3880
Time Base — Write (TB)
284
0x3A80
Time Base Upper — Write (TBU)
285
0x3B30
Internal Memory Mapping Register (IMMR)
638
NOTES:
1. Bits [0:17] and [28:31] are all 0.
Table 5-3 shows the PowerPC special address range. For an external master accessing a PowerPC SPR, address bits [0:17] and [28:31] are compared to zeros to confirm
that an SPR access is valid.
Table 5-3 PowerPC Address Range
MOTOROLA
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0:17
18:27
28:31
0...0
spr[0:9]
0000
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USER’S MANUAL
SECTION 6
SYSTEM CONFIGURATION AND PROTECTION
The MPC555 incorporates many system functions that normally must be provided in
external circuits. In addition, it is designed to provide maximum system safeguards
again hardware and/or software faults. The system configuration and protection submodule provides the following features:
• System Configuration — The USIU allows the user to configure the system according to the particular requirements. The functions include control of show cycle
operation, pin multiplexing, and internal memory map location. System configuration also includes a register containing part and mask number constants to identify the part in software.
• Interrupt Configuration — The interrupt controller receives interrupt requests
from a number of internal and external sources and directs them on a single interrupt-request line to the RCPU.
• General-Purpose I/O — The USIU provides 64 pins for general-purpose I/O. The
SGPIO pins are multiplexed with the address and data pins.
• External Master Modes Support — External master modes are special modes
of operation that allow an alternate master on the external bus to access the internal modules for debugging and backup purposes.
• Bus Monitor — The SIU provides a bus monitor to watch internal to external accesses. It monitors the transfer acknowledge (TA) response time for internal to
external transfers. A transfer error acknowledge (TEA) is asserted if the TA response limit is exceeded. This function can be disabled.
• Software Watchdog Timer (SWT) — The SWT asserts a reset or non-maskable
interrupt (as selected by the system protection control register) if the software fails
to service the SWT for a designated period of time (e.g, because the software is
trapped in a loop or lost). After a system reset, this function is enabled with a maximum time-out period and asserts a system reset if the time-out is reached. The
SWT can be disabled or its time-out period can be changed in the SYPCR. Once
the SYPCR is written, it cannot be written again until a system reset.
• Periodic Interrupt Timer (PIT) — The SIU provides a timer to generate periodic
interrupts for use with a real-time operating system or the application software.
The PIT provides a period from 1 µs to 4 seconds with a 4-Mhz crystal or 200 ns
to 0.8 ms with a 20-Mhz crystal. The PIT function can be disabled.
• Power-PC Time Base Counter (TB) — The TB is a 64-bit counter defined by the
MPC555 architecture to provide a time base reference for the operating system
or application software. The TB has four independent reference registers which
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can generate a maskable interrupt when the time-base counter reaches the value
programmed in one of the four reference registers. The associated bit in the TB
status register will be set for the reference register which generated the interrupt.
• Power-PC Decrementer (DEC) — The DEC is a 32-bit decrementing counter defined by the MPC555 architecture to provide a decrementer interrupt. This binary
counter is clocked by the same frequency as the time base (also defined by the
MPC555 architecture). The period for the DEC when driven by a 4-Mhz oscillator
is 4295 seconds, which is approximately 71.6 minutes.
• Real-Time Clock (RTC) — The RTC is used to provide time-of-day information
to the operating system or application software. It is composed of a 45-bit counter
and an alarm register. A maskable interrupt is generated when the counter reaches the value programmed in the alarm register. The RTC is clocked by the same
clock as the PIT.
• Freeze Support — The SIU allows control of whether the SWT, PIT, TB, DEC
and RTC should continue to run during the freeze mode.
Figure 6-1 shows a block diagram of the system configuration and protection logic.
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Module
Configuration
Interrupt
Controller
TEA Signal
Bus
Monitor
Clock
Periodic Interrupt
Timer
Interrupt
Software
Watchdog Timer
Interrupt or
System Reset
MPC555
Decrementer
Decrementer
Exception
MPC555
Time Base Counter
Interrupt
Real-Time
Clock
Interrupt
Figure 6-1 System Configuration and Protection Logic
6.1 System Configuration
The SIU allows the user to configure the system according to the particular requirements. The functions include control of show cycle operation, pin multiplexing, and
internal memory map location. System configuration also includes a register containing part and mask number constants to identify the part in software.
System configuration registers include the system configuration register (SIUMCR),
the internal memory mapping register (IMMR). Refer to 6.13 System Configuration
and Protection Registers for register diagrams and bit descriptions.
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6.1.1 USIU Pins Multiplexing
Some of the functions defined in the various sections of the SIU (external bus interface, memory controller, and general-purpose I/O) share pins. Table 6-1 summarizes
how the pin functions of these multiplexed pins are assigned.
.
Table 6-1 USIU Pins Multiplexing Control
Pin Name
Multiplexing Controlled By:
IRQ0/SGPIOC0
IRQ1/RSV/SGPIOC1
IRQ2/CR/SGPIOC2/MTS
IRQ3/KR/RETRY/SGPIOC3
IRQ4/AT2/SGPIOC4
IRQ5/SGPIOC5/MODCK1
IRQ6/MODCK2
IRQ7/MODCK3
At Power-on reset: MODCK[1:3]
Otherwise: programmed in SIUMCR
SGPIOC6/FRZ/PTR
SGPIOC7/IRQ_OUT/LWP0
BG/VF0/LWP1
BR/VF1/IWP2
BB/VF2/IWP3
IWP[0:1]/VFLS[0:1]
BI/STS
WE(0:3)/BE(0:3)/AT(0:3)
TDI/DSDI
TCK/DSCK
TDO/DSDO
Programmed in SIUMCR and hard reset configuration
DATA[0:31]/SGPIOD[0:31]
ADDR[8:31]/SGPIOA[8:31]
Programmed in SIUMCR
RSTCONF/TEXP
At Power-on reset: RSTCONF
Otherwise: programmed in SIUMCR
6.1.2 Memory Mapping
The MPC555 internal memory space can be assigned to one of eight locations.
The internal memory map is organized as a single 4-Mbyte block. The user can assign
this block to one of eight locations by programming the ISB field in the internal memory
mapping register (IMMR). The eight possible locations are the first eight 4-Mbyte
memory blocks starting with address 0x0000 0000. (Refer to Figure 6-2.)
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0x0000 0000
0x003F FFFF
0x0040 0000
0X007F FFFF
0X0080 0000
0x00BF FFFF
0x00C0 0000
Internal 4-Mbyte Memory Block
(Resides in one of eight locations)
0x00FF FFFF
0x0100 0000
0x013F FFFF
0x0140 0000
0x017F FFFF
0x0180 0000
0x01BF FFFF
0x01C0 0000
0x01FF FFFF
0xFFFF FFFF
Figure 6-2 MPC555 Memory Map
6.1.3 Arbitration Support
Two bits in the SIUMCR control USIU bus arbitration. The external arbitration (EARB)
bit determines whether arbitration is performed internally or externally. If EARB is
cleared (internal arbitration), the external arbitration request priority (EARP) bit determines the priority of an external master’s arbitration request. The operation of the
internal arbiter is described in 9.5.6.4 Internal Bus Arbiter.
6.2 External Master Modes
External master modes are special modes of operation that allow an alternate master
on the external bus to access the internal modules for debugging and backup purMPC555
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poses. They provide access to the internal buses (U-bus and L-bus) and to the
intermodule bus (IMB3).
There are two external master modes. Peripheral mode (enabled by setting PRPM in
the EMCR) is a special slave mechanism in which the RCPU is shut down and an alternate master on the external bus can perform accesses to any internal bus slave. Slave
mode (enabled by setting SLVM and clearing PRPM in the EMCR) enables an external
master to access any internal bus slave while the RCPU is fully operational. Both
modes can be enabled and disabled by software. In addition, peripheral mode can be
selected from reset.
The internal bus is not capable of providing fair priority between internal RCPU
accesses and external master accesses. If the bandwidth of external master accesses
is large, it is recommended that the system forces gaps between external master
accesses in order to avoid suspension of internal RCPU activity.
The MPC555 does not support burst accesses from an external master; only single
accesses of 8, 16, or 32 bits can be performed. The MPC555 asserts burst inhibit (BI)
on any attempt to initiate a burst access to internal memory.
The MPC555 provides memory controller services for external master accesses (single and burst) to external memories. See SECTION 10 MEMORY CONTROLLER for
details.
6.2.1 Operation of External Master Modes
The external master modes are controlled by the EMCR register, which contains the
internal bus attributes. The default attributes in the EMCR enable the external master
to configure EMCR with the required attributes, and then access the internal registers.
The external master must be granted external bus ownership in order to initiate the
external master access. The SIU compares the address on the external bus to the allocated internal address space. If the address is within the internal space, the access is
performed with the internal bus. The internal address space is determined according
to ISB (see 6.13.1.2 Internal Memory Map Register for details). The external master
access is terminated by the TA, TEA or RETRY signal on the external bus.
A deadlock situation might occur if an internal-to-external access is attempted on the
internal bus while an external master access is initiated on the external bus. In this
case, the SIU will assert the RETRY on the external bus in order to relinquish and retry
the external access until the internal access is completed. The internal bus will deny
other internal accesses for the next eight clocks in order to complete the pending
accesses and prevent additional internal accesses from being initiated on the internal
bus. The SIU will also mask internal accesses to support consecutive external
accesses if the delay between the external accesses is less than 4 clocks. The external master access and retry timings are described in 9.5.11 Bus Operation in
External Master Modes.
The external master may access the internal MPC555 special registers that are
located outside the RCPU. In order to access one of these MPC555 registers, program
the EMCR to MPC555 special register access (CONT = 1 and SUPU = 0 in EMCR).
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Next, access the register by providing the address according to the MPC555 address
map. Only the first external master access that follows EMCR setting will be assigned
to the special register map; the next accesses will be directed to the normal address
map. This is done in order to enable the user to access the EMCR again after the
required MPC555 special register access.
Peripheral mode does not require external bus arbitration between the external master
and the internal RCPU, since the internal RCPU is disabled. The BR and BB signals
should be connected to ground, and the internal bus arbitration should be selected in
order to prevent the “slave” MPC555 from occupying the external bus. Internal bus
arbitration is selected by clearing the EARB bit in the SIUMCR (see 6.13.1.1 SIU Module Configuration Register).
6.2.2 Address Decoding for External Accesses
During an external master access, the USIU compares the external address with the
internal address block to determine if MPC555 operation is required. Since only 24 of
the 32 internal address bits are available on the external bus, the USIU assigns zeros
to the most significant address bits (ADDR[0:7]).
The address compare sequence can be summarized as follows:
• Normal external access. If the CONT bit in EMCR is cleared, the address is compared to the internal address map.
• MPC555 special register external access. If the CONT bit in EMCR is set by the
previous external master access, the address is compared to the MPC555 special
address range. See 5.4 USIU PowerPC Memory Map for a list of the SPRs in the
USIU.
• Memory controller external access. If the first two comparisons do not match, the
internal memory controller determines whether the address matches an address
assigned to one of the regions. If it finds a match, the memory controller generates the appropriate chip select and attribute accordingly
When trying to fetch an MPC555 special register from an external master, the address
might be aliased to one of the external devices on the external bus. If this device is
selected by the MPC555 internal memory controller, this aliasing does not occur since
the chip select is disabled. If the device has its own address decoding or is being
selected by external logic, this case should be resolved.
6.3 USIU General-Purpose I/O
The USIU provides 64 general-purpose I/O (SGPIO) pins. The SGPIO pins are multiplexed with the address and data pins. In single-chip mode, where communicating with
external devices is not required, the user can use all 64 SGPIO pins. In multiple-chip
mode, only eight SGPIO pins are available. Another configuration allows the use of the
address bus for instruction show cycles while the data bus is dedicated to SGPIO functionality. The functionality of these pins is assigned by the single-chip (SC) bit in the
SIUMCR. (See 6.13.1.1 SIU Module Configuration Register.)
SGPIO pins are grouped as follows:
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• Six groups of eight pins each, whose direction is set uniformly for the whole group
• 16 single pins whose direction is set separately for each pin
Table 6-2 describes the SGPIO signals, and all available configurations. The SGPIO
registers are described in 6.13.5 General-Purpose I/O Registers.
Table 6-2 SGPIO Configuration
SGPIO
Group Name
Individual
Pin Control
Direction
Control
Available
Available
Available
Available
When SC = 10
When SC = 00 When SC = 01
When SC = 11
(Single-Chip
(32-bit Port
(16-bit Port
(Single-Chip
Mode with
Size Mode)
Size Mode)
Mode)
Trace)
SGPIOD[0:7]
GDDR0
SGPIOD[8:15]
GDDR1
SGPIOD[16:23]
GDDR2
X
X
SDDRD[23:31]
X
X
SDDRC[0:7]
SGPIOD[24:31]
SGPIOC[0:7]
1
X
X
X
X
X
X
X
X
SGPIOA[8:15]
GDDR3
X
SGPIOA[16:23]
GDDR4
X
SGPIOA[24:31]
GDDR5
X
NOTES:
1. SGPIOC[0:7] is selected according to GPC and MLRC fields in SIUMCR. See 6.13.1.1 SIU Module Configuration Register.
Figure 6-3 illustrates the functionality of the SGPIO.
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Read
Internal
Bus
Write
OE
Clk
SGPIO
Pad
Figure 6-3 SGPIO Cell
6.4 Interrupt Controller
The USIU receives interrupts from internal sources (such as the PIT and RTC), from
the IMB3 module (which has its own interrupt controller), and from external pins
IRQ[0:7]. An overview of the MPC555 interrupt structure is shown in Figure 6-4.
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IRQ[0:7]
Edge
Detect
SWT
Selector
NMI
Generate
IRQ0
NMI
DEC
DEC
Level 7
8
TB
17
Level 6
PIT
16
15
IMB3
Interrupt
Levels
8
RTC
Level 4
14
32
Change of Lock
8
RCPU
Level 5
Level 3
13
Interrupt Controller
8
IREQ
Level 2
12
8
UIMB
Level 1
IMB3 Interrupts:
11
IRQ[0:6] →Level 0:6
Level 0
IRQ[7:31] →Level 7
10
Debug
Debug
SIU
IRQOUT
Figure 6-4 MPC555 Interrupt Structure
If programmed to generate interrupts, the SWT and external pin IRQ0 always generate
a non-maskable interrupt (NMI) to the RCPU. Notice that the RCPU takes the system
reset interrupt when an NMI is asserted and the external interrupt for any other interrupt asserted by the interrupt controller.
Each one of the external pins IRQ[1:7] has its own dedicated assigned priority level.
IRQ0 is also mapped but should be used only as a status bit indicating that IRQ0 was
asserted and generated an NMI interrupt. There are eight additional interrupt priority
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levels. Each one of the SIU internal interrupt sources, as well as the interrupt requests
generated by the IMB3 modules, can be assigned by the software to any one of those
eight interrupt priority levels.
The same interrupt request signal that is generated within the RCPU is optionally
driven on the IRQ_OUT pin. This pin may be used in peripheral mode, in which the
internal processor is shut off and the internal modules are accessed externally.
The IMB3 interrupts are controlled by the UIMB. The IMB3 provides 32 interrupt levels.
Any interrupt source can be configured to any IMB3 interrupt level. The 32-bit UIPEND
register in the UIMB holds the pending IMB3 interrupt requests. IMB3 interrupt request
levels zero to six are mapped to USIU interrupt levels zero to six, respectively. IMB3
interrupt request levels seven to 31 are mapped to USIU request level seven. The user
must read the UIPEND register to determine the actual source of the interrupt. Refer
to 12.4 Interrupt Operation for more information.
NOTE
If the same interrupt level is assigned to more than one source, software must read the appropriate status bits in the appropriate UIMB3
registers to determine which interrupt was asserted.
Figure 6-5 illustrates the operation of the interrupt controller.
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.
IRQ[0:7]
IRQ0
NMI to RCPU
Interrupt Level (0-7)
8
Interrupt Vector
Highest
S
I
V
E
C
Priority
Interrupt
Detector
(1 from 16)
(Enables Branch
to the Highest Priority
Interrupt Routine)
SIPEND
SIMASK
Interrupt Request
(to RCPU and Pads)
latch
Figure 6-5 MPC555 Interrupt Configuration
6.4.1 SIU Interrupt Sources Priority
The SIU has 15 interrupt sources that assert just one interrupt request to the RCPU.
There are eight external IRQ pins (IRQ0 should be masked since it generates a NMI)
and eight interrupt levels. The priority between all interrupt sources is shown in Table
6-3.
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Table 6-3 Priority of Interrupt Sources
Priority
Interrupt Source
Interrupt Code
0 (Highest)
IRQ0
00000000
1
Level 0
00000100
2
IRQ1
00001000
3
Level 1
00001100
4
IRQ2
00010000
5
Level 2
00010100
6
IRQ3
00011000
7
Level 3
00011100
8
IRQ4
00100000
9
Level 4
00100100
10
IRQ5
00101000
11
Level 5
00101100
12
IRQ6
00110000
13
Level 6
00110100
14
IRQ7
00111000
15 (Lowest)
Level 7
00111100
16-31
Reserved
—
6.5 Hardware Bus Monitor
The bus monitor ensures that each bus cycle is terminated within a reasonable period
of time. The USIU provides a bus monitor option to monitor internal to external bus
accesses on the external bus. The monitor counts from transfer start to transfer
acknowledge and from transfer acknowledge to transfer acknowledge within bursts. If
the monitor times out, transfer error acknowledge (TEA) is asserted internally.
The bus monitor timing bit in the system protection control register (SYPCR) defines
the bus monitor time-out period. The programmability of the time-out allows for variation in system peripheral response time. The timing mechanism is clocked by the
system clock divided by eight. The maximum value is 2040 system clock cycles.
The bus monitor enable (BME) bit in the SYPCR enables or disables the bus monitor.
The bus monitor is always enabled, however, when freeze is asserted or when a
debug mode request is pending, regardless of the state of this bit.
6.6 MPC555 Decrementer
The decrementer (DEC) is a 32-bit decrementing counter defined by the MPC555
architecture to provide a decrementer interrupt. This binary counter is clocked by the
same frequency as the time base (also defined by the MPC555 architecture). The
operation of the time base and decrementer are therefore coherent. In the MPC555,
the DEC is clocked by the TMBCLK clock. The decrementer period is computed as
follows:
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2 32
T dec = -----------------Ftmbclk
The state of the DEC is not affected by any resets and should be initialized by software. The DEC runs continuously after power-up once the time base is enabled by
setting the TBE bit of the TBSCR (see Table 6-16) (unless the clock module is programmed to turn off the clock). The decrementer continues counting while reset is
asserted.
Loading from the decrementer has no effect on the counter value. Storing to the decrementer replaces the value in the decrementer with the value in the GPR.
Whenever bit zero (the MSB) of the decrementer changes from zero to one, a decrementer exception occurs. If software alters the decrementer such that the content of
bit 0 is changed to bit 1, a decrementer exception occurs.
A decrementer exception causes a decrementer interrupt request to be pending in the
RCPU. When the decrementer interrupt is taken, the decrementer interrupt request is
automatically cleared.
Table 6-4 illustrates some of the periods available for the decrementer, assuming a 4
MHz or 20 MHz crystal, and TBS = 0 which selects tbclk division to FOUR.
Table 6-4 Decrementer Time-Out Periods
Count Value
Time-Out @ 4 MHz
Time-Out @ 20 MHz
0
1.0 µs
0.2 µs
9
10 µs
2.0 µs
99
100 µs
20 µs
999
1.0 ms
200 µs
9999
10.0 ms
2 ms
999999
1.0 s
200 ms
9999999
10.0 s
2.0 s
99999999
100.0 s
20 s
999999999
1000. s
200 s
(hex) FFFFFFFF
4295 s
859 s
Refer to 3.9.5 Decrementer Register (DEC) for more information.
6.7 MPC555 Time Base (TB)
The time base (TB) is a 64-bit free-running binary counter defined by the MPC555
architecture. The TB has two independent reference registers which can generate a
maskable interrupt when the time base counter reaches the value programmed in one
of the two reference registers. The period of the TB depends on the driving frequency.
In the MPC555, the TB is clocked by the TMBCLK clock. The period for the TB is:
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T
2 64
= ----------------------TB
F
tmbclk
The state of the time base is not affected by any resets and should be initialized by
software. Reads and writes of the TB are restricted to special instructions. Separate
special-purpose registers are defined in the MPC555 architecture for reading and writing the time base. For the MPC555 implementation, it is not possible to read or write
the entire TB in a single instruction. Therefore, the mttb and mftb instructions are
used to move the lower half of the time base (TBL) while the mttbu and mftbu instructions are used to move the upper half (TBU).
Two reference registers are associated with the time base: TBREFF0 and TBREFF1.
A maskable interrupt is generated when the TB count reaches to the value programmed in one of the two reference registers. Two status bits in the time base control
and status register (TBSCR) indicate which one of the two reference registers generated the interrupt.
Refer to 6.13.4 System Timer Registers for diagrams and bit descriptions of time
base registers. Refer to 3.9.4 Time Base Facility (TB) — OEA and to RCPU Reference Manual (RCPURM/AD) for additional information regarding the MPC555 time
base.
6.8 Real-Time Clock (RTC)
The RTC is a 32-bit counter and pre-divider used to provide a time-of-day indication to
the operating system and application software. It is clocked by the pitrtclk clock.The
counter is not affected by reset and operates in all low-power modes. It is initialized by
software. The RTC can be programmed to generate a maskable interrupt when the
time value matches the value programmed in its associated alarm register. It can also
be programmed to generate an interrupt once a second. A control and status register
is used to enable or disable the different functions and to report the interrupt source.
FREEZE
Sec
Interrupt
RTSEC
pitrtclk
Clock
Clock
Disable
Divide
By 15625
32-bit Counter (RTC)
MUX
Divide
By 78125
=
Alarm
Interrupt
4-MHz / 20-MHz crystal
32-bit Register (RTCAL)
Figure 6-6 RTC Block Diagram
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6.9 Periodic Interrupt Timer (PIT)
The periodic interrupt timer consists of a 16-bit counter clocked by the PITRCLK clock
supplied by the clock module.
The 16-bit counter counts down to zero when loaded with a value from the PITC. After
the timer reaches zero, the PS bit is set and an interrupt is generated if the PIE bit is
is a logic one. The software service routine should read the PS bit and then write it to
zero to terminate the interrupt request. At the next input clock edge, the value in the
PITC is loaded into the counter, and the process starts over again.
When a new value is loaded into the PITC, the periodic timer is updated, the divider is
reset, and the counter begins counting. If the PS bit is not cleared, an interrupt request
is generated. The request remains pending until PS is cleared. If the PS bit is set again
prior to being cleared, the interrupt remains pending until PS is cleared.
Any write to the PITC stops the current countdown, and the count resumes with the
new value in PITC. If the PTE bit is not set, the PIT is unable to count and retains the
old count value. Reads of the PIT have no effect on the counter value.
PTE
PITC
(PISCR)
(PISCR)
pitrtclk
Clock
Clock
Disable
16-bit
Modulus
Counter
PS (PISCR)
PIT
Interrupt
PIE (PISCR)
PITF (PISCR)
Figure 6-7 PIT Block Diagram
The timeout period is calculated as:
PIT
period
PITC + 1
PITC + 1
= ------------------------ = ----------------------------------------------F
ExternalClock
pitrtclk  -----------------------------


4or256
Solving this equation using a 4-MHz external clock and a pre-divider of 256 gives:
PITC + 1
PITperiod = -----------------------15625
This gives a range from 64 microseconds, with a PITC of 0x0000, to 4.19 seconds,
with a PITC of 0xFFFF. When a 20-MHz crystal is used with a pre-divider of 256, the
range is between 12.8 microseconds to 0.84 seconds.
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6.10 Software Watchdog Timer (SWT)
The software watchdog timer (SWT) prevents system lockout in case the software
becomes trapped in loops with no controlled exit. The SWT is enabled after system
reset to cause a system reset if it times out. it. The SWT requires a special service
sequence to be executed on a periodic basis. If this periodic servicing action does not
occur, the SWT times out and issues a reset or a non-maskable interrupt (NMI),
depending on the value of the SWRI bit in the SYPCR.
The SWT can be disabled by clearing the SWE bit in the SYPCR. Once the SYPCR is
written by software, the state of the SWE bit cannot be changed.
The SWT service sequence consists of the following two steps:
1. Write 0x556C to the Software Service Register (SWSR)
2. Write 0xAA39 to the SWSR
The service sequence clears the watchdog timer and the timing process begins again.
If any value other than 0x556C or 0xAA39 is written to the SWSR, the entire sequence
must start over.
Although the writes must occur in the correct order prior to time-out, any number of
instructions may be executed between the writes. This allows interrupts and exceptions to occur, if necessary, between the two writes.
Not 0x556C / Don’t Reload
Reset
0x556C / Don’t Reload
State 0
Waiting for 0x556C
State 1
Waiting for 0xAA39
0xAA39 / Reload
Not 0x556C / Don’t Reload
Not 0xAA39 / Don’t Reload
Although most software disciplines support the watchdog concept, different systems
require different time-out periods. For this reason, the software watchdog provides a
selectable range for the time-out period.
In Figure 6-8, the range is determined by the value SWTC field. The value held in the
SWTC field is then loaded into a 16-bit decrementer clocked by the system clock. An
additional divide by 2048 prescaler is used if necessary. The decrementer begins
counting when loaded with a value from the software watchdog timing count field
(SWTC). After the timer reaches 0x0, a software watchdog expiration request is issued
to the reset or NMI control logic.
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Upon reset, the value in the SWTC is set to the maximum value and is again loaded
into the software watchdog register (SWR), starting the process over. When a new
value is loaded into the SWTC, the software watchdog timer is not updated until the
servicing sequence is written to the SWSR. If the SWE is loaded with the value zero,
the modulus counter does not count.
SWSR
SWE
(SYPCR)
System
Clock
Clock
Disable
Service
Logic
SWTC
Divide By
2048
Reload
MUX
16-bit
SWR / Decrementer
Rollove = 0
Reset
or NMI
FREEZE
Time-out
SWP
(SYPCR)
Figure 6-8 SWT Block Diagram
6.11 Freeze Operation
When the FREEZE line is asserted, the clocks to the software watchdog, the periodic
interrupt timer, the real-time clock, the time base counter, and the decrementer can be
disabled. This is controlled by the associated bits in the control register of each timer.
If programmed to stop during FREEZE assertion, the counters maintain their values
while FREEZE is asserted, unless changed by the software. The bus monitor, however, remains enabled regardless of this signal.
6.12 Low Power Stop Operation
When the processor is set in a low-power mode (doze, sleep, or deep sleep), the software watchdog timer is frozen. It remains frozen and maintain its count value until the
processor exits this state and resumes executing instructions.
The periodic interrupt timer, decrementer, and time base are not affected by these lowpower modes. They continue to run at their respective frequencies. These timers are
capable of generating an interrupt to bring the MCU out of these low-power modes.
MOTOROLA
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MPC555
USER’S MANUAL
6.13 System Configuration and Protection Registers
This section provides diagrams and bit descriptions of the system configuration and
protection registers.
6.13.1 System Configuration Registers
System configuration registers include the SIUMCR, the EMCR, and the IMMR.
6.13.1.1 SIU Module Configuration Register
The SIU module configuration register (SIUMCR) configures various aspects of SIU
operation.
SIUMCR — SIU Module Configuration Register
MSB
0
1
EARB
2
3
4
5
EARP
6
7
RESERVED
8
0x2F C000
9
10
DSHW
DBGC
11
12
13
DBPC ATWC
14
GPC
15
DLK
RESET:
ID0*
16
RESERVED
0
0
0
0
0
0
0
0
ID[9:10]*
17
18
19
20
21
22
23
24
25
SC
RCTX
ID[17:18]*
0
MLRC
RESERVED
26
ID11*
27
MTSC
ID12*
28
0
0
0
29
30
LSB
31
0
0
0
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
* The reset value is a reset configuration word value, extracted from the indicated internal data bus lines.
WARNING
Software must not change any SIUMCR fields controlled by the reset
configuration word while the functions that these fields control are
active.
MPC555
USER’S MANUAL
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MOTOROLA
6-19
Table 6-5 SIUMCR Bit Settings
Bit(s)
Name
Description
0
EARB
External arbitration
0 = Internal arbitration is performed
1 = External arbitration is assumed
1:3
EARP
External arbitration request priority. This field defines the priority of an external master’s arbitration request. This field is valid when EARB is cleared. Refer to 9.5.6.4 Internal Bus Arbiter for
details.
4:7
—
Reserved
8
DSHW
Data show cycles. This bit selects the show cycle mode to be applied to U-bus data cycles (data
cycles to IMB modules and flash EEPROM). This field is locked by the DLK bit. Note that instruction show cycles are programmed in the ICTRL and L-bus data show cycles (to SRAM) are
programmed in the L2UMCR.
0 = Disable show cycles for all internal data cycles
1 = Show address and data of all internal data cycles
9:10
DBGC
Debug pins configuration. Refer to Table 6-6.
11
DBPC
Debug port pins configuration. Refer to Table 6-7.
12
ATWC
Address write type enable configuration. This bit configures the pins to function as byte write
enables or address types for debugging purposes.
0 = WE(0:3)/BE(0:3)/AT(0:3) functions as WE(0:3)/BE(0:3)1
1 = WE(0:3)/BE(0:3)/AT(0:3) functions as AT(0:3)
13:14
GPC
This bit configures the pins as shown in Table 6-8.
15
DLK
Debug register lock
0 = Normal operation
1 = SIUMCR is locked and can be written only in test mode or when the internal freeze signal is
asserted.
16
—
Reserved
17:18
SC
Single-chip select. This field configures the functionality of the address and data buses. Changing the SC field while external accesses are performed is not supported. Refer to Table 6-9.
19
RCTX
Reset configuration/timer expired. During reset the RSTCONF/TEXP pin functions as RSTCONF. After reset the pin can be configured to function as TEXP, the timer expired signal that
supports the low-power modes.
0 = RSTCONF/TEXP functions as RSTCONF
1 = RSTCONF/TEXP functions as TEXP
20:21
MLRC
Multi-level reservation control. This field selects between the functionality of the reservation logic
and IRQ pins, refer to Table 6-10.
22:23
—
24
MTSC
25:31
—
Reserved
Memory transfer start control.
0 = IRQ2/CR/SGPIOC2/MTS functions as MTS
1 = IRQ2/CR/SGPIOC2/MTS functions according to the MLRC bits setting
Reserved
NOTES:
1. WE/BE is selected per memory region by WEBS in the approprite BR register in the memory controller.
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MPC555
USER’S MANUAL
Table 6-6 Debug Pins Configuration
DBGC
Pin Function
IWP[0:1]/VFLS[0:1]
BI/STS
BG/VF0/LWP1
BR/VF1/IWP2
BB/VF2/IWP3
VFLS[0:1]
BI
BG
BR
BB
01
IWP[0:1]
STS
BG
BR
BB
10
VFLS[0:1]
STS
VF0
VF1
VF2
11
IWP[0:1]
STS
LWP1
IWP2
IWP3
00
Table 6-7 Debug Port Pins Configuration
Pin Function
DBPC
TCK/DSCK
TDI/DSDI
TDO/DSDO
0
DSCK
DSDI
DSDO
1
TCK
TDI
TDO
Table 6-8 General Pins Configuration
GPC
Pin Function
FRZ/PTR/SGPIOC6
IRQOUT/LWP0/SGPIOC7
00
PTR
LWP0
01
SGPIOC6
SGPIOC7
10
FRZ
LWP0
11
FRZ
IRQOUT
Table 6-9 Single-Chip Select Field Pin Configuration
Pin Function
SC
DATA[0:15]/
SGPIOD[0:15]
DATA[16:31]
SGPIOD[16:31]
ADDR[8:31]/
SGPIOA[8:31]
00 (multiple chip, 32-bit port
size)
DATA[0:15]
DATA[16:31]
ADDR[8:31]
01 (multiple chip, 16-bit port
size
DATA[0:15]
SPGIOD[16:31]
ADDR[8:31]
10 (single-chip with address
show cycles for debugging)
SPGIOD[0:15]
SPGIOD[16:31]
ADDR[8:31]
11 (single-chip)
SPGIOD[0:15]
SPGIOD[16:31]
SPGIOA[8:31]
MPC555
USER’S MANUAL
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MOTOROLA
6-21
Table 6-10 Multi-Level Reservation Control Pin Configuration
Pin Function
MLRC
IRQ0/SGPIOC0
IRQ1/RSV/
SGPIOC1
IRQ2/CR/
IRQ3/KR/RETRY
SGPIOC2/MTS
/SGPIOC3
IRQ4/AT2/
SGPIOC4
IRQ5/SGPIOC5/
MODCK11
00
IRQ0
IRQ1
IRQ22
IRQ3
IRQ4
IRQ5 / MODCK1
01
IRQ0
RSV
CR2
KR/RETRY
AT2
IRQ5 / MODCK1
10
SGPIOC0
SGPIOC1
SGPIOC22
SGPIOC3
SGPIOC4
SGPIOC5/
MODCK1
11
IRQ0
IRQ1
SGPIOC22
KR/RETRY
AT2
SGPIOC5/
MODCK1
NOTES:
1. Operates as MODCK1 during reset.
2. This holds if MTSC bit is reset to 0. Otherwise IRQ2/CR/SGPIOC2/MTS will function as MTS.
6.13.1.2 Internal Memory Map Register
The internal memory map register (IMMR) is a special register located within the
MPC555 special register space. The IMMR contains identification of a specific device
as well as the base for the internal memory map. Based on the value read from this
register, software can deduce availability and location of any on-chip system
resources.
This register can be read by the mfspr instruction. The ISB field can be written by the
mtspr instruction. The PARTNUM and MASKNUM fields are mask programmed and
cannot be changed.
IMMR — Internal Memory Mapping Register
MSB
0
1
2
3
4
5
6
7
SPR 638
8
9
10
11
12
13
PARTNUM
MASKNUM
Read-Only Fixed Value
Read-Only Fixed Value
14
15
30
LSB
31
RESET:
16
17
18
19
RESERVED
20
FLEN
21
22
RESERVED
23
24
CLES
25
26
27
RESERVED
28
29
ISB
0
ID[28:30]*
0
RESET:
0
0
0
0
ID20*
0
0
ID23*
0
0
0
0
* The reset value is a reset configuration word value extracted from the indicated bits of the internal data bus. Refer
to 7.5.2 Hard Reset Configuration Word.
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MPC555
USER’S MANUAL
Table 6-11 IMMR Bit Settings
Bit(s)
Name
0:7
PARTNUM
8:15
MASKNUM
16:19
—
20
FLEN
21:22
—
23
CLES
24:27
—
28:30
ISB
31
—
Description
This read-only field is mask programmed with a code corresponding to the part number of
the part on which the SIU is located. It is intended to help factory test and user code which
is sensitive to part changes. This changes when the part number changes. For example, it
would change if any new module is added, if the size of any memory module is changed. It
would not change if the part is changed to fix a bug in an existing module. The MPC555 chip
has an ID of 0x30.
This read-only field is mask programmed with a code corresponding to the mask number of
the part. It is intended to help factory test and user code which is sensitive to part changes.
Reserved
Flash enable. The default state of FLEN is negated, meaning that the boot is performed from
external memory. This bit can be set at reset by through the reset configuration word.
0 = On-chip flash memory is disabled, and all internal cycles to the allocated flash address
space are mapped to external memory
1 = On-chip flash memory is enabled
Reserved
Core little-endian swap
0 = Little-endian swap logic in the EBI is not activated for RCPU accesses after reset
1 = Little- endian swap logic in the EBI is activated for RCPU accesses after reset
Reserved
This read-write field defines the base address of the internal memory space. The initial value
of this field can be configured at reset to one of eight addresses, and then can be changed
to any value by software. Internal base addresses are as follows:
000 = 0x0000 0000
001 = 0x0040 0000
010 = 0x0080 0000
011 = 0x00C0 0000
100 = 0x0100 0000
101 = 0x0140 0000
110 = 0x0180 0000
111 = 0x01C0 0000
Reserved
6.13.1.3 External Master Control Register (EMCR)
The external master control register selects the external master modes and determines the internal bus attributes for external-to-internal accesses.
EMCR — External Master Control Register
MSB
0
1
2
3
4
5
6
7
0x2F C030
8
9
10
11
12
13
14
15
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
SUPU
INST
0
1
PRPM SLVM
0
SIZE
RESERVED
RESV CONT
0
TRAC SIZEN
RESERVED
RESET:
ID16*
0
0
0
1
0
0
1
1
0
1
1
0
0
* The reset value is a reset configuration word value, extracted from the indicated internal data bus line. Refer to 7.5.2
Hard Reset Configuration Word.
MPC555
USER’S MANUAL
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MOTOROLA
6-23
Table 6-12 EMCR Bit Settings
Bit(s)
Name
0:15
—
Description
Reserved
PRPM
Peripheral mode. In this mode, the internal RCPU core is shut off and an alternative master on
the external bus can access any internal slave module. The reset value of this bit is determined
by the reset configuration word. The bit can also be written by software.
0 = Normal operation
1 = Peripheral mode operation
17
SLVM
Slave mode (valid only if PRPM = 0). In this mode, an alternative master on the external bus can
access any internal slave module while the internal RCPU core is fully operational. If PRPM is
set, the value of SLVN is a “don’t care.”
0 = Normal operation
1 = Slave mode
18
—
16
Reserved
19:20
SIZE
Size attribute. If SIZEN = 1, the SIZE bits controls the internal bus attributes as follows:
00 = Double word (4 bytes)
01 = Word (4 bytes)
10 = Half word (2 bytes)
11 = Byte
21
SUPU
Supervisor/user attribute. SUPU controls the supervisor/user attribute as follows:
0 = Supervisor mode access permitted to all registers
1 = User access permitted to registers designated “user access”
22
INST
Instruction attribute. INST controls the internal bus instruction attribute as follows:
0 = Instruction fetch
1 = Operand or non-CPU access
23:24
—
Reserved
25
RESV
Reservation attribute. RESV controls the internal bus reservation attribute as follows:
0 = Storage reservation cycle
1 = Not a reservation
26
CONT
Control attribute. CONT drives the internal bus control bit attribute as follows:
0 = Access to MPC555 control register, or control cycle access
1 = Access to global address map
27
—
28
TRAC
Trace attribute. TRAC controls the internal bus program trace attribute as follows:
0 = Program trace
1 = Not program trace
29
SIZEN
External size enable control bit. SIZEN determines how the internal bus size attribute is driven:
0 = Drive size from external bus signals TSIZE[0:1]
1 = Drive size from SIZE0, SIZE1 in EMCR
30:31
—
Reserved
Reserved
6.13.2 SIU Interrupt Registers
The SIU interrupt controller contains the SIPEND, SIMASK, SIEL, and SIVEC
registers.
6.13.2.1 SIPEND Register
Each of the 32 bits in the SIPEND register corresponds to an interrupt request. The
bits associated with internal exceptions indicate, if set, that an interrupt service is
requested (if not masked by the corresponding bit in the SIMASK register). Each bit
reflects the status of the internal requestor device and is cleared when the appropriate
actions are initiated by the software in the device itself. Writing to these bits while they
are not set has no effect.
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USER’S MANUAL
The bits associated with the IRQ pins have a different behavior depending on the sensitivity defined for them in the SIEL register. When the IRQ is defined as a “level”
interrupt the corresponding bit behaves similar to the bits associated with internal interrupt sources. When the IRQ is defined as an “edge” interrupt and if the corresponding
bit is set, it indicates that a falling edge was detected on the line and the bit can be
reset by software by writing a 1 to it.
SIPEND — SIU Interrupt Pending Register
0x2F C010
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRQ0
LVL0
IRQ1
LVL1
IRQ2
LVL2
IRQ3
LVL3
IRQ4
LVL4
IRQ5
LVL5
IRQ6
LVL6
IRQ7
LVL7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
0
0
RESET:
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
6.13.2.2 SIU Interrupt Mask Register (SIMASK)
The SIMASK is a 32-bit read/write register. Each bit corresponds to an interrupt
request bit in the SIPEND register. Setting a bit in this register allows the interrupt
request to reach the RCPU. SIMASK is updated by the software and cleared upon
reset. It is the responsibility of the software to determine which of the interrupt sources
are enabled at a given time.
SIMASK — SIU Interrupt Mask Register
MSB
0
1
IRM0* LVM0
0x2F C014
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRM1
LVM1
IRM2
LVM2
IRM3
LVM3
IRM4
LVM4
IRM5
LVM5
IRM6
LVM6
IRM7
LVM7
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
0
0
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
*IRQ0 of the SIPEND register is not affected by the setting or clearing of the IRM0 bit of the SIMASK register. IRQ0 is
a non-maskable interrupt.
MPC555
USER’S MANUAL
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MOTOROLA
6-25
6.13.2.3 SIU Interrupt Edge Level Register (SIEL)
The SIEL is a 32-bit read/write register. Each pair of bits corresponds to an external
interrupt request. The EDx bit, if set, specifies that a falling edge in the corresponding
IRQ line will be detected as an interrupt request. When the EDx bit is 0, a low logical
level in the IRQ line will be detected as an interrupt request. The WMx (wake-up mask)
bit, if set, indicates that an interrupt request detection in the corresponding line causes
the MPC555 to exit low-power mode.
SIEL — SIU Interrupt Edge Level Register
0x2F C018
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ED0
WM0
ED1
WM1
ED2
WM2
ED3
WM3
ED4
WM4
ED5
WM5
ED6
WM6
ED7
WM7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
0
0
RESET:
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
6.13.2.4 SIU Interrupt Vector Register
The SIVEC is a 32-bit read-only register that contains an 8-bit code representing the
unmasked interrupt source of the highest priority level. The SIVEC can be read as
either a byte, half word, or word. When read as a byte, a branch table can be used in
which each entry contains one instruction (branch). When read as a half-word, each
entry can contain a full routine of up to 256 instructions. The interrupt code is defined
such that its two least significant bits are 0, thus allowing indexing into the table.
SIVEC — SIU Interrupt Vector
MSB
0
1
2
3
4
5
0x2F C01C
6
7
8
9
10
INTERRUPT CODE
11
12
13
14
15
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
0
0
RESERVED
RESET:
0
0
MOTOROLA
6-26
0
0
0
0
0
0
0
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MPC555
USER’S MANUAL
6.13.3 System Protection Registers
6.13.3.1 System Protection Control Register (SYPCR)
The system protection control register (SYPCR) controls the system monitors, the
software watchdog period, and the bus monitor timing. This register can be read at any
time, but can be written only once after system reset.
SYPCR — System Protection Control Register
MSB
0
1
2
3
4
5
6
7
0x2F C004
8
9
10
11
12
13
14
15
SWTC
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
SWF
SWE
SWRI
SWP
0
1
1
1
BMT
BME
RESERVED
RESET:
1
1
1
1
1
1
1
1
0
0
0
0
Table 6-13 SYPCR Bit Settings
Bit(s)
Name
Description
0:15
SWTC
16:23
BMT
Bus monitor timing. This field specifies the time-out period, in eight-system-clock resolution, of
the bus monitor.
24
BME
Bus monitor enable
0 = Disable bus monitor
1 = Enable bus monitor
25:27
—
28
SWF
Software watchdog freeze
0 = Software watchdog continues to run while FREEZE is asserted
1 = Software watchdog stops while FREEZE is asserted
29
SWE
Software watchdog enable. Software should clear this bit after a system reset to disable the
SWT.
0 = Watchdog is disabled
1 = Watchdog is enabled
30
SWRI
Software watchdog reset/interrupt select
0 = Software watchdog time-out causes a non-maskable interrupt to the RCPU
1 = Software watchdog time-out causes a system reset
31
SWP
Software watchdog prescale
0 = Software watchdog timer is not pre-scaled
1 = Software watchdog timer is prescaled by 2048
Software watchdog timer count. This field contains the count value of the software watchdog
timer.
Reserved
6.13.3.2 Software Service Register (SWSR)
The SWSR is the location to which the SWT servicing sequence is written. To prevent
SWT time-out, the user should write a 0x556C followed by 0xAA39 to this register. The
SWSR can be written at any time but returns all zeros when read.
MPC555
USER’S MANUAL
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MOTOROLA
6-27
SWSR — Software Service Register
MSB
0
1
2
3
4
5
0x2F C00E
6
7
8
9
10
11
12
13
14
LSB
15
0
0
0
0
0
0
0
0
SWSR
RESET:
0
0
0
0
0
0
0
0
Table 6-14 SWSR Bit Settings
Bit(s)
Name
0:15
SWSR
Description
SWT servicing sequence is written to this register. To prevent SWT time-out, the user should
write a 0x556C followed by 0xAA39 to this register. The SWSR can be written at any time but
returns all zeros when read.
6.13.3.3 Transfer Error Status Register (TESR)
The transfer error status register contains a bit for each exception source generated
by a transfer error. A bit set to logic 1 indicates what type of transfer error exception
occurred since the last time the bits were cleared by reset or by the normal software
status bit-clearing mechanism. Note that these bits may be set due to canceled speculative accesses which do not cause an interrupt. The register has two identical sets
of bit fields; one is associated with instruction transfers and the other with data
transfers.
TESR — Transfer Error Status Register
MSB
0
1
2
3
4
5
6
0x2F C020
7
8
9
10
11
12
13
14
15
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
IEXT
IBMT
DEXT
DBM
0
0
0
0
RESERVED
RESERVED
RESERVED
RESET:
0
0
MOTOROLA
6-28
0
0
0
0
0
0
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
0
0
0
0
MPC555
USER’S MANUAL
Table 6-15 TESR Bit Settings
Bit(s)
Name
Description
0:17
—
18
IEXT
Instruction external transfer error acknowledge. This bit is set if the cycle was terminated by an
externally generated TEA signal when an instruction fetch was initiated.
19
IBMT
Instruction transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor
time-out when an instruction fetch was initiated.
20:25
—
26
DEXT
Data external transfer error acknowledge. This bit is set if the cycle was terminated by an externally generated TEA signal when a data load or store is requested by an internal master.
27
DBM
Data transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor timeout when a data load or store is requested by an internal master.
28:31
—
Reserved
Reserved
Reserved
6.13.4 System Timer Registers
The following sections describe registers associated with the system timers. These
facilities are powered by the KAPWR and can preserve their value when the main
power supply is off. Refer to 8.3.3 Pre-Divider for details on the required actions
needed in order to guarantee this data retention.
6.13.4.1 Decrementer Register
The 32-bit decrementer register is defined by the MPC555 architecture. The values
stored in this register are used by a down counter to cause decrementer exceptions.
The decrementer causes an exception whenever bit zero changes from a logic zero to
a logic one. A read of this register always returns the current count value from the
down counter.
Contents of this register can be read or written to by the mfspr or the mtspr instruction. This register is not affected by reset. The decrementer is powered by standby
power and can continue to count when standby power is applied.
DEC — Decrementer Register
SPR 22
MSB
0
LSB
31
Decrementing Counter
RESET: UNCHANGED
Refer to 3.9.5 Decrementer Register (DEC) for more information on this register.
6.13.4.2 Time Base SPRs
The TB is a 64-bit register containing a 64-bit integer that is incremented periodically.
There is no automatic initialization of the TB; the system software must perform this
initialization. The contents of the register may be written by the mttbl or the mttbu
instructions, see 3.9.4 Time Base Facility (TB) — OEA.
MPC555
USER’S MANUAL
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MOTOROLA
6-29
Refer to 3.8 PowerPC VEA Register Set — Time Base and 3.9.4 Time Base Facility
(TB) — OEA for more information on reading and writing the TBU and TBL registers.
TB — Time Base (Reading)
SPR 268, 269
MSB
0
LSB
63
31 32
TBU
TBL
RESET: UNCHANGED
TB — Time Base (Writing)
SPR 284, 285
MSB
0
LSB
63
31 32
TBU
TBL
RESET: UNCHANGED
6.13.4.3 Time Base Reference Registers
Two reference registers (TBREFF0 and TBREFF1) are associated with the lower part
of the time base (TBL). Each is a 32-bit read/write register. Upon a match between the
contents of TBL and the reference register, a maskable interrupt is generated.
TBREF0 — Time Base Reference Register 0
0x2F C204
MSB
0
LSB
31
TBREF0
RESET:
TBREF1 — Time Base Reference Register 1
0x2F C208
MSB
0
LSB
31
TBREF1
RESET:
6.13.4.4 Time Base Control and Status Register
The TBSCR is 16-bit read/write register. It controls the TB, decrementer count enable,
and interrupt generation and is used for reporting the source of the interrupts. The register can be read anytime. A status bit is cleared by writing a one to it. (Writing a zero
has no effect.) More than one bit can be cleared at a time.
TBSCR — Time Base Control and Status Register
MSB
0
1
2
3
4
5
6
7
TBIRQ
8
0x2F C200
9
REFA REFB
10
11
RESERVED
12
13
REFAE REFBE
14
LSB
15
TBF
TBE
0
0
RESET:
0
0
MOTOROLA
6-30
0
0
0
0
0
0
0
0
0
0
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
0
0
MPC555
USER’S MANUAL
Table 6-16 TBSCR Bit Settings
Bit(s)
Name
Description
0:7
TBIRQ
Time base interrupt request. These bits determine the interrupt priority level of the time base.
Refer to 6.4 Interrupt Controller for interrupt level encodings.
8
REFA
Reference A interrupt status
0 = No match detected
1 = TBREFA value matches value in TBL
9
REFB
Reference B interrupt status
0 = No match detected
1 = TBREFB value matches value in TBL
10:11
—
12
REFAE
Reference A interrupt enable. If this bit is set, the time base generates an interrupt when the
REFA bit is set.
13
REFBE
Reference B interrupt enable. If this bit is set, the time base generates an interrupt when the
REFB bit is set.
14
TBF
Time base freeze. If this bit is set, the time base and decrementer stop while FREEZE is
asserted.
15
TBE
Time base enable
0 = Time base and decrementer are disabled
1 = Time base and decrementer are enabled
Reserved
6.13.4.5 Real-Time Clock Status and Control Register
The RTCSC is used to enable the different RTC functions and to report the source of
the interrupts. The register can be read anytime. A status bit is cleared by writing it to
a one. (Writing a zero does not affect a status bit’s value.) More than one status bit can
be cleared at a time.
RTCSC — Real-Time Clock Status and Control Register
MSB
0
1
2
3
4
5
6
7
RTCIRQ
0x2F C220
8
9
10
11
12
13
14
LSB
15
SEC
ALR
Reserved
4M
SIE
ALE
RTF
RTE
0
0
0
—
0
0
0
—
RESET:
0
0
0
MPC555
USER’S MANUAL
0
0
0
0
0
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MOTOROLA
6-31
Table 6-17 RTCSCR Bit Settings
Bit(s)
Name
Description
0:7
RTCIRQ
8
SEC
Once per second interrupt. This status bit is set every second. It should be cleared by the
software.
9
ALR
Alarm interrupt. This status bit is set when the value of the RTC equals the value programmed in
the alarm register.
10
—
Reserved
11
4M
Real-time clock freeze
0 = RTC assumes that it is driven by 20 MHz to generate the seconds pulse.
1 = RTC assumes that it is driven by 4 MHz
12
SIE
Second interrupt enable. If this bit is set, the RTC generates an interrupt when the SEC bit is set.
13
ALE
Alarm interrupt enable. If this bit is set, the RTC generates an interrupt when the ALR bit is set.
14
RTF
Real-time clock freeze. If this bit is set, the RTC stops while FREEZE is asserted.
15
RTE
Real-time clock enable
0 = RTC is disabled
1 = RTC is enabled
Real-time clock interrupt request. Thee bits determine the interrupt priority level of the RTC.
Refer to 5.4 Interrupt Controller for interrupt level encodings.
6.13.4.6 Real-Time Clock Register (RTC)
The real-time clock register is a 32-bit read write register. It contains the current value
of the real-time clock. A write to the RTC resets the seconds timer to zero.
RTC —Real-Time Clock Register
0x2F C224
MSB
0
LSB
31
RTC
RESET: UNCHANGED
6.13.4.7 Real-Time Clock Alarm Register (RTCAL)
The RTCAL is a 32-bit read/write register. When the value of the RTC is equal to the
value programmed in the alarm register, a maskable interrupt is generated.
The alarm interrupt will be generated as soon as there is a match between the ALARM
field and the corresponding bits in the RTC. The resolution of the alarm is 1 sec.
RTCAL — Real-Time Clock Alarm Register
MSB
0
0x2F C22C
LSB
31
ALARM
RESET: UNCHANGED
MOTOROLA
6-32
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MPC555
USER’S MANUAL
6.13.4.8 Periodic Interrupt Status and Control Register (PISCR)
The PISCR contains the interrupt request level and the interrupt status bit. It also contains the controls for the 16 bits to be loaded into a modulus counter. This register can
be read or written at any time.
PISCR — Periodic Interrupt Status and Control Register
MSB
0
1
2
3
4
5
6
7
8
PIRQ
9
PS
0x2F C240
10
11
12
RESERVED
13
14
LSB
15
PIE
PITF
PTE
0
0
0
HARD RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6-18 PISCR Bit Settings
Bit(s)
Name
Description
0:7
PIRQ
Periodic interrupt request. These bits determine the interrupt priority level of the PIT. Refer to 6.4
Interrupt Controller for interrupt level encodings.
8
PS
Periodic interrupt status. This bit is set if the PIT issues an interrupt. The PIT issues an interrupt
after the modulus counter counts to zero. PS can be negated by writing a one to it. A write of zero
has no affect.
9:12
—
Reserved
13
PIE
Periodic interrupt enable. If this bit is set, the time base generates an interrupt when the PS bit
is set.
14
PITF
PIT freeze. If this bit is set, the PIT stops while FREEZE is asserted.
15
PTE
Periodic timer enable
0 = PIT stops counting and maintains current value
1 = PIT continues to decrement
6.13.4.9 Periodic Interrupt Timer Count Register (PITC)
The PITC register contains the 16 bits to be loaded in a modulus counter. This register
is readable and writable at any time.
PITC — Periodic Interrupt Timer Count
MSB
0
1
2
3
4
5
6
0x2F C244
7
8
9
10
11
12
13
14
15
PITC
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
0
0
RESERVED
RESET:
0
0
0
MPC555
USER’S MANUAL
0
0
0
0
0
0
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MOTOROLA
6-33
Table 6-19 PITC Bit Settings
Bit(s)
Name
Description
0:15
PITC
Periodic interrupt timing count. This field contains the 16-bit value to be loaded into the modulus
counter that is loaded into the periodic timer. This register is readable and writeable at any time.
16:31
—
Reserved
6.13.4.10 Periodic Interrupt Timer Register (PITR)
The periodic interrupt register is a read-only register that shows the current value in
the periodic interrupt down counter. Read or writing this register does not affect the
register.
PITR — Periodic Interrupt Timer Register
MSB
0
1
2
3
4
5
6
0x2F C248
7
8
9
10
11
12
13
14
15
PIT
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
0
0
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
Table 6-20 PIT Bit Settings
Bit(s)
Name
Description
0:15
PIT
Periodic interrupt timing count — This field contains the current count remaining for the periodic
timer. Writes have no effect on this field.
16:31
—
Reserved
MOTOROLA
6-34
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MPC555
USER’S MANUAL
6.13.5 General-Purpose I/O Registers
6.13.5.1 SGPIO Data Register 1 (SGPIODT1)
SGPIODT1 — SGPIO Data Register 1
MSB
0
1
2
3
4
5
6
0x2F C024
7
8
9
10
SGPIOD[0:7]
11
12
13
14
15
SGPIOD[8:15]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
SGPIOD[16:23]
SGPIOD[24:31]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6-21 SGPIODT1 Bit Settings
Bit(s)
Name
Description
SIU general-purpose I/O Group D[0:7]. This 8-bit register controls the data of general-purpose I/O pins SGPIOD[0:7]. The direction (input or output) of this group of pins is controlled
by the GDDR0 bit in the SGPIO control register.
0:7
SGPIOD[0:7]
8:15
SIU general-purpose I/O Group D[8:15]. This 8-bit register controls the data of general-purSGPIOD[8:15] pose I/O pins SGPIOD[8:15]. The direction (input or output) of this group of pins is controlled
by the GDDR1 bit in the SGPIO control register.
SIU general-purpose I/O Group D[16:23]. This 8-bit register controls the data of the general16:23 SGPIOD[16:23] purpose I/O pins SGPIOD[16:23]. The direction (input or output) of this group of pins is controlled by the GDDR2 bit in the SGPIO control register
24:31
SIU general-purpose I/O Group D[24:31]. This 8-bit register controls the data of the generalpurpose I/O pins SGPIOD[24:31]. The direction of SGPIOD[24:31] is controlled by eight
SGPIOD[24:31]
dedicated direction control signals SDDRD[24:31]. Each pin in this group can be configured
separately as general-purpose input or output.
6.13.5.2 SGPIO Data Register 2 (SGPIODT2)
SGPIODT2 — SGPIO Data Register 2
MSB
0
1
2
3
4
5
6
0x2F C028
7
8
9
10
SGPIOC[0:7]
11
12
13
14
15
SGPIOA[8:15]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
SGPIOA[16:23]
SGPIOA[24:31]
RESET:
0
0
0
MPC555
USER’S MANUAL
0
0
0
0
0
0
0
0
0
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
0
MOTOROLA
6-35
Table 6-22 SGPIODT2 Bit Settings
Bit(s)
Name
Description
0:7
SGPIOC[0:7]
SIU general-purpose I/O Group C[0:7]. This 8-bit register controls the data of the generalpurpose I/O pins SGPIOC[0:7]. The direction of SGPIOC[0:7] is controlled by 8 dedicated
direction control signals SDDRC[0:7] in the SGPIO control register. Each pin in this group
can be configured separately as general-purpose input or output.
8:15
SIU general-purpose I/O Group A[8:15]. This 8-bit register controls the data of the generalSGPIOA[8:15] purpose I/O pins SGPIOA[8:15]. The GDDR3 bit in the SGPIO control register configures
these pins as a group as general-purpose input or output.
16:23
SGPIOA
[16:23]
SIU general-purpose I/O Group A[16:23]. This 8-bit register controls the data of the general-purpose I/O pins SGPIOA[16:23]. The GDDR4 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
24:31
SGPIOA
[24:31]]
SIU general-purpose I/O Group A[24:31]. This 8-bit register controls the data of the general-purpose I/O pins SGPIOA[24:31]. The GDDR5 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
6.13.5.3 SGPIO Control Register (SGPIOCR)
SGPIOCR — SGPIO Control Register
MSB
0
1
2
3
4
5
6
0x2F C02C
7
8
9
10
SDDRC[0:7]
11
12
13
14
15
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
GDDR GDDR GDDR GDDR GDDR GDDR
0
1
2
3
4
5
RESERVED
SDDRD[24:31]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6-23 SGPIOCR Bit Settings
Bit(s)
Name
Description
0:7
SDDRC[0:7]
SGPIO data direction for SGPIOC[0:7]. Each SDDR bit zero to seven controls the direction
of the corresponding SGPIOC pin zero to seven
8:15
—
16
GDDR0
Group data direction for SGPIOD[0:7]
17
GDDR1
Group data direction for SGPIOD[8:15]
18
GDDR2
Group data direction for SGPIOD[16:23]
19
GDDR3
Group data direction for SGPIOA[8:15]
20
GDDR4
Group data direction for SGPIOA[16:23]
21
GDDR5
Group data direction for SGPIOA[24:31]
22:23
—
24:31
SDDRD
[24:31]
MOTOROLA
6-36
Reserved
Reserved
SGPIO data direction for SGPIOD[24:31]. Each SDDRD bit 24:31 controls the direction of
the corresponding SGPIOD pin [24:31].
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 6-24 describes the bit values for data direction control.
Table 6-24 Data Direction Control
MPC555
USER’S MANUAL
SDDR/GDDR
Operation
0
SGPIO configured as input
1
SGPIO configured as output
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MOTOROLA
6-37
MOTOROLA
6-38
SYSTEM CONFIGURATION AND PROTECTION
Revised 1 March 1999
MPC555
USER’S MANUAL
SECTION 7
RESET
This section describes the MPC555 reset sources, operation, control, and status.
7.1 Reset Operation
The MPC555 has several inputs to the reset logic which include the following:
• Power on reset
• External hard reset pin (HRESET)
• External soft reset pin (SRESET)
• Loss of lock
• On-chip clock switch
• Software watchdog reset
• Checkstop reset
• Debug port hard reset
• Debug port soft reset
• JTAG reset
All of these reset sources are fed into the reset controller. The control logic determines
the cause of the reset, synchronizes it if necessary, and resets the appropriate logic
modules, depending on the source of the reset. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset.
External soft reset initializes internal logic while maintaining system configuration.
The reset status register (RSR) reflects the most recent source to cause a reset.
7.1.1 Power On Reset
The power-on reset pin, PORESET, is an active low input. In a system with powerdown low-power mode, this pin should be activated only as a result of a voltage failure
in the KAPWR pin. After detecting the assertion of PORESET, the MPC555 enters the
power-on reset state. During this state the MODCK[1:3] signals determine the oscillator frequency, PLL multiplication factor, and the PITRCLK and TMBCLK clock
sources. In addition, the MPC555 asserts the SRESET and HRESET pins.
The PORESET pin should be asserted for a minimum time of 100,000 cycles of clock
oscillator after a valid level has been reached on the KAPWR supply. After detecting
the assertion of PORESET, the MPC555 remains in the power-on reset state until the
last of the following two events occurs:
• The Internal PLL enters the lock state and the system clock is active.
• The PORESET pin is negated.
If the MPC555 is in single-chip mode and limp mode is enabled, the internal PLL is not
required to be locked before the chip exits power-on reset.
MPC555
USER’S MANUAL
RESET
Revised 1 March 1999
MOTOROLA
7-1
After exiting the power-on reset state, the MCU continues to drive the HRESET and
SRESET pins for 512 system clock cycles. When the timer expires (after 512 cycles),
the configuration is sampled from data bus pins, if required (see 7.5.1 Hard Reset
Configuration) and the MCU stops driving the HRESET and SRESET pins. In addition, the internal MODCK[1:3] values are sampled.
The PORESET pin has a glitch detector to ensure that low spikes of less than 20 ns
are rejected. The internal PORESET signal asserts only if the PORESET pin asserts
for more than 100 ns.
7.1.2 Hard Reset
HRESET (hard reset) is an active low, bi-directional I/O pin. The MPC555 can detect
an external assertion of HRESET only if it occurs while the MCU is not asserting reset.
When the MPC555 detects assertion of the external HRESET pin or a cause to assert
the internal HRESET line, is detected the chip starts to drive the HRESET and SRESET for 512 cycles. When the timer expires (after 512 cycles) the configuration is
sampled from data pins (refer to 7.5.1 Hard Reset Configuration) and the chip stops
driving the HRESET and SRESET pins. An external pull-up resistor should drive the
HRESET and SRESET pins high. After detecting the negation of HRESET or SRESET, the MCU waits 16 clock cycles before testing the presence of an external hard
or soft reset.
The HRESET pin has a glitch detector to ensure that low spikes of less than 20 ns are
rejected. The internal HRESET will be asserted only if HRESET is asserted for more
than 100 ns. (Note these timings are preliminary)
The HRESET is an open collector type pin.
7.1.3 Soft Reset
SRESET (soft reset) is an active low, bi-directional I/O pin. The MPC555 can only
detect an external assertion of SRESET if it occurs while the MPC555 is not asserting
reset.
When the MPC555 detects the assertion of external SRESET or a cause to assert the
internal SRESET line, the chip starts to drive the SRESET for 512 cycles. When the
timer expires (after 512 cycles) the debug port configuration is sampled from the DSDI
and DSCK pins and the chip stops driving the SRESET pin. An external pull-up resistor
should drive the SRESET pin high. After the MPC555 detects the negation of SRESET, it waits 16 clock cycles before testing the presence of an external soft reset.
7.1.4 Loss of Lock
If the PLL detects a loss of lock, erroneous external bus operation will occur if synchronous external devices use the MPC555 input clock. Erroneous operation could
also occur if devices with a PLL use the MPC555 CLKOUT signal. This source of reset
can be optionally asserted if the LOLRE bit in the PLL, low-power, and reset control
register (PLPRCR) is set. The enabled PLL loss of lock event generates an internal
MOTOROLA
7-2
RESET
Revised 1 March 1999
MPC555
USER’S MANUAL
hard reset sequence. Refer to SECTION 8 CLOCKS AND POWER CONTROL for
more information on loss of lock.
7.1.5 On-Chip Clock Switch
If the system clocked is switched to the backup clock or switched from backup clock
to another clock source an internal hard reset sequence is generated. Refer to SECTION 8 CLOCKS AND POWER CONTROL.
7.1.6 Software Watchdog Reset
When the MPC555 software watchdog counts to zero, a software watchdog reset is
asserted. The enabled software watchdog event generates an internal hard reset
sequence.
7.1.7 Checkstop Reset
When the RCPU enters a checkstop state, and the checkstop reset is enabled (the
CSR bit in the PLPRCR is set), a checkstop reset is asserted. The enabled checkstop
event generates an internal hard reset sequence. Refer to the RCPU Reference Manual (RCPURM/AD) for more information.
7.1.8 Debug Port Hard Reset
When the development port receives a hard reset request from the development tool,
an internal hard reset sequence is generated, see SECTION 8 CLOCKS AND
POWER CONTROL. In this case the development tool must reconfigure the debug
port. Refer to SECTION 21 DEVELOPMENT SUPPORT for more information.
7.1.9 Debug Port Soft Reset
When the development port receives a soft reset request from the development tool,
an internal soft reset sequence is generated, see SECTION 8 CLOCKS AND POWER
CONTROL. In this case the development tool must reconfigure the debug port. Refer
to SECTION 21 DEVELOPMENT SUPPORT for more information.
7.1.10 JTAG Reset
When the JTAG logic asserts the JTAG soft reset signal, an internal soft reset
sequence is generated, see SECTION 8 CLOCKS AND POWER CONTROL. Refer
to SECTION 22 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) for more
information.
7.2 Reset Actions Summary
Table 7-1 summarizes the action taken for each reset.
MPC555
USER’S MANUAL
RESET
Revised 1 March 1999
MOTOROLA
7-3
Table 7-1 Reset Action Taken For Each Reset Cause
Reset Source
Power On Reset
Hard Reset Sources
External Hard Reset
Loss of Lock
On-Chip Clock Switch
Illegal Low-Power Mode
Software Watchdog
Checkstop
Debug Port Hard Reset
Soft Reset Sources
External Soft Reset
Debug Port Soft Reset
JTAG Reset
Reset
System
Logic and
ConfiguraPLL States
tion Reset
Reset
Yes
Yes
Clock
Module
Reset
Yes
Debug
HRESET
Port
Pin Driven Configuration
Yes
Yes
Other
Internal
Logic
Reset
Yes
SRESET
Pin Driven
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Yes
7.3 Data Coherency During Reset
The MPC555 supports data coherency and avoids data corruption while reset. If a
cycle is to be executed when detecting any SRESET or HRESET source, then the
cycle will either complete or will not start before generating the corresponding reset
control signal. There are reset sources, however, when the MPC555 generates an
internal reset due to special internal situation where this protection is not supported.
See 7.4 Reset Status Register.
In the case of large operand size (32 or 16 bits) transaction to a smaller port size, the
cycle is split into two 16-bit or four 8-bit cycles. In this case, data coherency and data
corruption is assured.
In the case where the core executes an unaligned load/store cycle which is broken
down into multiple cycles, data coherency or data corruption is NOT assured between
these cycles.
A contention on the data pins may occur while asserting external reset (EXT_RESET)
if the data coherency mechanism is required, and thus enables a cycle to complete,
while external hardware drives the data for the configuration word. See Table 7-2 for
a description of the required EXT_RESET line source in a system.
Table 7-2 Reset Configuration Word and Data Corruption/Coherency
Reset Driven
Reset to Use for Data Coherency
(EXT_RESET)
HRESET
SRESET
SRESET
HRESET
HRESET & SRESET
HRESET || SRESET
MOTOROLA
7-4
RESET
Revised 1 March 1999
Comments
Provided only one of them is driven
into the MPC555 at a time
MPC555
USER’S MANUAL
7.4 Reset Status Register
All of the reset sources are fed into the reset controller. The 16-bit reset status register
(RSR) reflects the most recent source, or sources, of reset. (Simultaneous reset
requests can cause more than one bit to be set at the same time.) This register contains one bit for each reset source. A bit set to logic one indicates the type of reset that
occurred.
Once set, individual bits in the RSR remain set until software clears them. Can be
cleared by writing a one to the bit. A write of zero has no effect on the bit. The register
can be read at all times. The reset status register receives its default reset values during power-on reset. The RSR is powered by the KAPWR pin.
RSR — Reset Status Register
0x2F C288
MSB
0
1
2
3
4
EHRS
ESRS
LLRS
SWRS
CSRS
0
0
0
0
5
6
DBHRS DBSRS
7
8
9
JTRS
OCCS
ILBC
0
0
0
10
11
12
13
GPOR GHRST GSRST
14
15
RESERVED
RESET:
0
0
0
1
1
1
0
0
0
Table 7-3 Reset Status Register Bit Settings
Bit(s)
Name
Description
0
EHRS1
External hard reset status
0 = No external hard reset has occurred
1 = An external hard reset has occurred
1
ESRS1
External soft reset status
0 = No external soft reset has occurred
1 = An external soft reset has occurred
2
LLRS
Loss of lock reset status
0 = No enabled loss-of-lock reset has occurred
1 = An enabled loss-of-lock reset has occurred
3
SWRS
Software watchdog reset status
0 = No software watchdog reset has occurred
1 = A software watchdog reset has occurred
4
CSRS
Checkstop reset status
0 = No enabled checkstop reset has occurred
1 = An enabled checkstop reset has occurred
5
DBHRS
Debug port hard reset status
0 = No debug port hard reset request has occurred
1 = A debug port hard reset request has occurred
6
DBSRS
Debug port soft reset status
0 = No debug port soft reset request has occurred
1 = A debug port soft reset request has occurred
7
JTRS
JTAG reset status
0 = No JTAG reset has occurred
1 = A JTAG reset has occurred
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Table 7-3 Reset Status Register Bit Settings (Continued)
Bit(s)
8
9
10
11
12
13:15
Name
Description
OCCS
On-chip clock switch
0 = No on-chip clock switch reset has occurred
1 = An on-chip clock switch reset has occurred
ILBC
Illegal bit change. This bit is set when the MPC555 changes any of the following bits when they
are locked:
LPM[0:1], locked by the LPML bit
MF[0:11], locked by the MFPDL bit
DIVF[0:4], locked by the MFPDL bit
GPOR
Glitch detected on PORESET pin. This bit is set when the PORESET pin is asserted for more
than TBD ns
0 = No glitch was detected on the PORESET pin
1 = A glitch was detected on the PORESET pin
GHRST
Glitch detected on HRESET pin. This bit is set when the HRESET pin is asserted for more than
TBD ns
0 = No glitch was detected on the HRESET pin
1 = A glitch was detected on the HRESET pin
GSRST
Glitch detected on SRESET pin. If the SRESET pin is asserted for more than TBD ns the
GHRST bit will be set. If an internal or external SRESET is generated the SRESET pin is
asserted and the GSRST bit will be set. The GSRST bit remains set until software clears it. The
GSRST bit can be negated by writing a one to GSRST. A write of zero has no effect on this bit.
0 = No glitch was detected on SRESET pin
1 = A glitch was detected on SRESET pin.
—
Reserved
NOTES:
1. In the USIU RSR, if both EHRS and ESRS are set, the reset source is internal. The EHRS and ESRS bits in RSR
register are set for any internal reset source in addition to external HRESET and external SRESET events. If both
internal and external indicator bits are set, then the reset source is internal.
7.5 Reset Configuration
7.5.1 Hard Reset Configuration
When a hard reset event occurs, the MPC555 reconfigures its hardware system as
well as the development port configuration The logical value of the bits that determine
its initial mode of operation, are sampled from the following:
• The external data bus pins DATA[0:31]
• An internal default constant (0x0000 0000)
• An internal NVM register value (CMFCFIG)
If at the sampling time RSTCONF is asserted, then the configuration is sampled from
the data bus. If RSTCONF is negated and a valid NVM value exists (CMFCFIG bit
HC=0), then the configuration is sampled from the NVM register in the CMF module.
If RSTCONF is negated and no valid NVM value exists (CMFCFIG bit HC=1), then the
configuration word is sampled from the internal default. HC will be “1” if the internal
flash is erased. Table 7-4 summarizes the reset configuration options.
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USER’S MANUAL
Table 7-4 Reset Configuration Options
RSTCONF
Has Configuration (HC)
Internal Configuration Word
0
x
DATA[0:31] pins
1
0
NVM flash EEPROM register (CMFCFIG)
1
1
Internal data word default (0x0000 0000)
If the PRDS control bit in the PDMCR register is set and HRESET and RSTCONF are
asserted, the MPC555 pulls the data bus low with a weak resistor. The user can overwrite this default by driving the appropriate bit high. See Figure 7-1 for the basic reset
configuration scheme.
Has Configuration HC
Config.
Word
32
MUX
CMF
32
32
OE
Dx (Data line)
INT_RESET
Data
Coherency
EXT_RESET
(See Table 7.2)
HRESET/SRESET
RSTCONF
MPC555
Figure 7-1 Reset Configuration Basic Scheme
During the assertion of the PORESET input signal, the chip assumes the default reset
configuration. This assumed configuration changes if the input signal RSTCONF is
asserted when the PORESET is negated or the CLKOUT starts to oscillate. To ensure
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7-7
that stable data is sampled, the hardware configuration is sampled every eight clock
cycles on the rising edge of CLKOUT with a double buffer. The setup time required for
the data bus is approximately 15 cycles, and the maximum rise time of HRESET
should be less than 6 clock cycles.
Figure 7-2 to Figure 7-5 provide sample reset configuration timings.
CLKOUT
PORESET
Internal PORESET
HRESET
RSTCONF
Tsup
Internal DATA[0:31]
Default
RSTCONF Controlled
Figure 7-2 Reset Configuration Sampling Scheme
For “Short” PORESET Assertion, Limp Mode Disabled
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USER’S MANUAL
CLKOUT
(Backup Clock)
PORESET
Internal PORESET
HRESET
RSTCONF
Tsup
Internal DATA(0:31)
Default
RSTCONF Controlled
Figure 7-3 Reset Configuration Timing for
“Short” PORESET Assertion, Limp Mode Enabled
CLKOUT
PLL lock
PORESET
Internal PORESET
HRESET
RSTCONF
Tsup
Internal DATA[0:31]
Default
RSTCONF Controlled
Figure 7-4 Reset Configuration Timing for
“Long” PORESET Assertion, Limp Mode Disabled
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Figure 7-5 Reset Configuration Sampling Timing Requirements
7-10
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RESET
USER’S MANUAL
MPC555
3
4
5
6
7
8
10
11
12
13
14
15
Maximum time of reset recognition
(maximum rise time - up to 6 clocks)
9
Sample Data Configuration
Minimum Setup time of reset recognition = 15 clocks
RESET CONFIGURATION WORD
2
Sample Data Configuration
Internal
reset
Data
RSTCONF
HRESET
CLKOUT
1
16
7.5.2 Hard Reset Configuration Word
The hard reset configuration word, which is sampled from the internal data bus on the
negation of HRESET, is shown below. The reset configuration word is not a register in
the memory map. Most of the bits in the configuration are located in registers in the
USIU. The user should refer to the appropriate register definition for a detailed description of each control bit.
Hard Reset Configuration Word
MSB
0
1
2
3
EARB
IP
BDRV
BDIS
0
0
4
5
6
BPS
7
8
9
Reserved
10
DBGC
11
12
13
DBPC ATWC
14
15
Reserved
EBDF
DEFAULT:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LSB
16
17
PRPM
18
SC
19
20
ETRE
FLEN
0
0
21
22
Reserved
23
24
CLES
25
26
27
28
Reserved
29
30
ISB
31
DME
DEFAULT:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 7-5 Hard Reset Configuration Word Bit Settings
Bit(s)
0
Name
EARB
Description
External arbitration. Refer to 6.13.1.1 SIU Module Configuration Register for a detailed bit
definition.
0 = Internal arbitration is performed
1 = External arbitration is assumed
IP
Initial interrupt prefix. This bit defines the initial value of the MSR[IP] bit immediately after reset.
MSR[IP] defines the interrupt table location.
0 = MSR[IP] = 0 after reset
1 = MSR[IP] = 1 after reset
2
BDRV
Bus pins drive strength. This bit determines the driving capability of the bus pins (address, data,
and control) and the CLKOUT pin. For details, refer to description of the COM bits in 8.12.1 System Clock Control Register (SCCR). The default value is full drive strength for the bus pins and
CLKOUT.
0 = Full drive
1 = Reduced drive
3
BDIS
Boot disable. If a write to the OR0 register occurs after reset, this bit definition is ignored.
0 = Memory controller bank 0 is active and matches all addresses immediately after reset
1 = Memory controller is not activated after reset.
4:5
BPS
Boot port size. If a write to the OR0 register occurs after reset, this field definition is ignored.
00 = 32-bit port (default)
01 = 8-bit port
10 = 16-bit port
11 = Reserved
6:8
—
9:10
DBGC
1
MPC555
USER’S MANUAL
Reserved
Debug pins configuration. See 6.13.1.1 SIU Module Configuration Register for this field definition. The default value is for these pins to function as VFLS[0:1], BI, BR, BG, and BB.
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Table 7-5 Hard Reset Configuration Word Bit Settings (Continued)
Bit(s)
Name
Description
11
DGPC
Debug port pins configuration. See 6.13.1.1 SIU Module Configuration Register for this field
definition. The default value is for these pins to function as development support pins.
12
ATWC
Address type write-enable configuration. Refer to 6.13.1.1 SIU Module Configuration Register
for this field definition. The default value is for these pins to function as write-enable pins.
13:14
EBDF
External bus division factor. This field defines the initial value of the external bus frequency. Refer
to 8.12.1 System Clock Control Register (SCCR) for details. The default value is that CLKOUT
frequency is equal to that of the internal clock (divide by one).
15
—
16
PRPM
Reserved
Peripheral mode enable. This bit determines whether the chip is in peripheral mode. Refer to
6.13.3 System Protection Registers for details. The default value is that peripheral mode is not
enabled.
Single chip select. Refer to 6.13.1.1 SIU Module Configuration Register for details.
00 = Extended chip, 32 bits data
01 = Extended chip, 16 bits data
10 = Single chip and show cycles (address)
11 = Single chip
17:18
SC
19
ETRE
Exception table relocation enable. This field defines whether the exception table relocation feature in the BBC is enabled or disabled. The default state is disabled. Refer to SECTION 4 BURST
BUFFER for details.
20
FLEN
Flash enable. Refer to 6.13.1.2 Internal Memory Map Register for details.
0 = Flash disabled — boot is from external memory
1 = Flash enabled
21:22
—
23
CLES
24:27
—
28:30
ISB
Initial internal space base select. This field defines the initial value of the ISB field in the IMMR
register. Refer to 6.13.1.2 Internal Memory Map Register for details. The default state is that
the internal memory map is mapped to start at address 0x0000 0000.
DME
Dual mapping enable. This bit determines whether dual mapping of the flash EEPROM module
is enabled. Refer to 10.8.5 Dual Mapping Base Register (DMBR) for details.The default value
is for dual mapping to be disabled.
0 = Dual mapping disabled
1 = Dual mapping enabled
31
Reserved
Core little-endian swap. Refer to 6.13.1.2 Internal Memory Map Register for details.
0 = Little-endian swap logic not activated
1 = Little-endian swap logic in the EBI is activated for core (RCPU) accesses after reset.
Reserved
7.5.3 Soft Reset Configuration
When a soft reset event occurs, the MPC555 reconfigures the development port. Refer
to SECTION 21 DEVELOPMENT SUPPORT for details.
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USER’S MANUAL
SECTION 8
CLOCKS AND POWER CONTROL
8.1 Overview
The main timing reference for the MPC555 can monitor any of the following:
• A crystal with a frequency of 4 MHz or 20 MHz
• An external frequency source with a frequency of 4 MHz
• An external frequency source at the system frequency
The system operating frequency is generated through a programmable phase-locked
loop, the system PLL (SPLL). The SPLL is programmable in integer multiples of the
input oscillator frequency to generate the internal (VCO/2) operating frequency. A predivider before the SPLL enables the user to divide the high frequency crystal oscillator.
The internal operating SPLL frequency should be at least 15 MHz. It can be divided by
a power-of-two divider to generate the system operating frequencies.
In addition to the system clock, the clocks submodule provides the following:
• TMBCLK to the time base (TB) and decrementer (DEC)
• PITRTCLK to the periodic interrupt timer (PIT) and real-time clock (RTC)
The oscillator, TB, DEC, RTC, and the PIT are powered from the keep alive power
supply (KAPWR) pin. This allows the counters to continue to count (increment/decrement) at the oscillator frequency even when the main power to the MCU is off. While
the power is off, the PIT may be used to signal to the power supply IC to enable power
to the system at specific intervals. This is the power-down wake-up feature. When the
chip is not in power-down low-power mode, the KAPWR is powered to the same voltage value as the voltage of the I/O buffers and logic.
The MPC555 clock module consists of the main crystal oscillator (OSCM), the SPLL,
the low-power divider, the clock generator, the system low-power control block, and
the limp mode control block. The clock module receives control bits from the system
clock control register (SCCR), change of lock interrupt register (COLIR), the lowpower and reset-control register (PLPRCR), and the PLL.
Figure 8-1 illustrates the functional block diagram of the clock unit.
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MOTOROLA
8-1
VSSSYN
VDDSYN
XFC
MODCK[1:3]
EXTCLK
2:1
MUX
VCOOUT
2:1 MUX
SPLL
Lock
TBCLK
GCLK2
System Low-Power Control
Low
Power
Dividers
(1/2N)
Clock
Drivers
3:1 MUX
(/4 or /16)
GCLK1 / GCLK2
GCLK1C / GCLK2C
CLKOUT
Back_Up Clock
Oscillator Loss
3:1
Detector
MUX
Drivers
ENGCLK
TMBclk
Driver
TMBCLK
RTC / PIT Clock
and DRIVER
XTAL
Main Clock
Oscillator (OSCM)
PITRTCLK
/4 or /256
EXTAL
Figure 8-1 Clock Unit Block Diagram
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8.2 System Clock Sources
The system clock can be provided by the main system oscillator (OSCM), an external
clock input, or the backup clock (BUCLK) on-chip ring oscillator, see Figure 8-2.
The OSCM uses either a 4-MHz or 20-MHz crystal to generate the PLL reference
clock. When the main system oscillator output is the timing reference to the system
PLL, skew elimination between the XTAL/EXTAL pins and CLKOUT is not
guaranteed.
The external clock input receives a clock signal from an external source. The clock frequency must be either in the range of 3 MHz – 5 MHz or at the system frequency of at
least 15 MHz (1:1 mode). When the external clock input is the timing reference to the
system PLL skew elimination between the EXTCLK pin and the CLKOUT is less than
± 1 ns.
The backup clock on-chip ring oscillator enables the MCU to function with a less precise clock. When operating from the backup clock, the MCU is in limp mode. This
enables the system to continue minimum functionality until the system is fixed. The
BUCLK frequency is TBD (see Electrical Specification).
For normal operation, at least one clock source (EXTCLK or OSCM) must be active.
A configuration with both clock sources active is possible as well. At this configuration
EXTCLK provides the OSCCLK and OSCM provides the PITRTCLK. The input of an
unused timing reference (EXTCLK or EXTAL) must be grounded.
XTAL
EXTAL
1 MΩ*
CL
CL
*Resistor is not currently required on the board but space should be available for its addition in the future.
Figure 8-2 Main System Oscillator (OSCM)
8.3 System PLL
The PLL allows the processor to operate at a high internal clock frequency using a low
frequency clock input, a feature which offers two benefits. Lower frequency clock input
reduces the overall electromagnetic interference generated by the system, and the
ability to oscillate at different frequencies reduces cost by eliminating the need to add
an additional oscillator to a system.
The PLL can perform the following functions:
• Frequency multiplication
• Skew elimination
• Frequency division
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8.3.1 Frequency Multiplication
The PLL can multiply the input frequency by any integer between one and 4096. The
multiplication factor depends on the value of the MF[0:11] bits in the PLPRCR register.
While any integer value from one to 4096 can be programmed, the resulting VCO output frequency must be at least 15 MHz. The multiplication factor is set to a
predetermined value during power-on reset as defined in Table 8-1.
8.3.2 Skew Elimination
The PLL is capable of eliminating the skew between the external clock entering the
chip (EXTCLK) and both the internal clock phases and the CLKOUT pin, making it useful for tight synchronous timings. Skew elimination is active only when the PLL is
enabled and programmed with a multiplication factor of one or two (MF = 0 or 1). The
timing reference to the system PLL is the external clock input.
8.3.3 Pre-Divider
A pre-divider before the phase comparator enables additional system clock resolution
when the crystal oscillator frequency is 20 MHz. The division factor is determined by
the DIVF[0:4] bits in the PLPRCR.
8.3.4 PLL Block Diagram
As shown in Figure 8-3, the reference signal, OSCCLK, goes to the phase comparator. The phase comparator controls the direction (up or down) that the charge pump
drives the voltage across the external filter capacitor (XFC). The direction depends on
whether the feedback signal phase lags or leads the reference signal. The output of
the charge pump drives the VCO. The output frequency of the VCO is divided down
and fed back to the phase comparator for comparison with the reference signal,
OSCCLK. The MF values, zero to 4095, are mapped to multiplication factors of one to
4096. Note that when the PLL is operating in 1:1 mode (refer to Table 8-1), the multiplication factor is one (MF = 0). The PLL output frequency is twice the maximum
system frequency. This double frequency is needed to generate GCLK1 and GCLK2
clocks.
The PLL maximum lock time is determined by the input clock to the phase detector.
The PLL locks within 500 input clock cycles.
NOTE
Upon initial system power up and after KAPWR is lost, an external
circuit must assert power on reset (PORESET). If limp mode will be
enabled during power-on reset, PORESET must be asserted for at
least 100,000 cycles of input PLL clock after a valid level has been
reached on the KAPWR supply. If limp mode will be disabled,
PORESET should be asserted for approximately 3 µs after a valid
level has been reached on the KAPWR supply.
Whenever power-on reset is asserted, the MF bits are set according to Table 8-1, and
the DFNH and DFNL bits in SCCR are set to the value of 0 (÷1 and 2), respectively.
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USER’S MANUAL
XFC
OSCCLK
Division Factor
DIVF[0:4]
Feedback
Phase
Comparator
Up
Down
VCOOUT
Charge
Pump
VCO
VDDSYN / VSSSYN
Clock
Delay
Multiplication Factor
MF[0:11]
Figure 8-3 System PLL Block Diagram
8.3.5 PLL Pins
The following pins are dedicated to the PLL operation:
• VDDSYN — Drain voltage. This is the VDD dedicated to the analog PLL circuits.
The voltage should be well-regulated and the pin should be provided with an extremely low impedance path to the VDD power rail. VDDSYN should be bypassed
to VSSSYN by a 0.1 µF capacitor located as close as possible to the chip package.
• VSSSYN — Source voltage. This is the VSS dedicated to the analog PLL circuits.
The pin should be provided with an extremely low impedance path to ground.
VSSSYN should be bypassed to VDDSYN by a 0.1 µF capacitor located as close
as possible to the chip package.
• XFC — External filter capacitor. XFC connects to the off-chip capacitor for the
PLL filter. One terminal of the capacitor is connected to XFC, and the other terminal is connected to VDDSYN.
The off-chip capacitor must have the following values (preliminary):
0 < MF + 1 < 4
(680 x (MF + 1) – 120) pF
MF + 1 ≥ 4
1100 x (MF + 1) pF
Where MF = the value stored on MF[0:11]. This is one less than the desired frequency multiplication.
8.4 System Clock During PLL Loss of Lock
At reset, until the SPLL is locked, the SPLL output clock is disabled.
During normal operation (once the PLL has locked), either the oscillator or an external
clock source is generating the system clock. In this case, if loss of lock is detected and
the LOLRE (loss of lock reset enable) bit in the PLPRCR is cleared, the system clock
source continues to function as the PLL’s output clock. The USIU timers can operate
with the input clock to the PLL, so that these timers are not affected by the PLL loss of
lock. Software can use these timers to measure the loss-of-lock period. If the timer
reaches the user-preset software criterion, the MCU can switch to the backup clock by
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setting the switch to backup clock (STBUC) bit in the SCCR, provided the limp mode
enable (LME) bit in the SCCR is set.
If loss of lock is detected during normal operation, assertion of HRESET (for example,
if LOLRE is set) disables the PLL output clock until the lock condition is met. During
hard reset, the STBUC bit is set as long as the PLL lock condition is not met and clears
when the PLL is locked. If STBUC and LME are both set, the system clock switches to
the backup clock, and the chip operates in limp mode until STBUC is cleared.
Every change in the lock status of the PLL can generate a maskable interrupt.
NOTE
When the VCO is the system clock source, chip operation is unpredictable while the PLL is unlocked. Note further that a switch to the
backup clock is possible only if the LME bit in the SCCR is set.
8.5 Low-Power Divider
The output of the PLL is sent to a low-power divider block. (In limp mode the BUCLK
is sent to a low-power divider block.) This block generates all other clocks in normal
operation, but has the ability to divide the output frequency of the VCO before it generates the general system clocks sent to the rest of the MPC555.
The purpose of the low-power divider block is to allow the user to reduce and restore
the operating frequencies of different sections of the MPC555 without losing the PLL
lock. Using the low-power divider block, the user can still obtain full chip operation, but
at a lower frequency. This is called gear mode. The selection and speed of gear mode
can be changed at any time, with changes occurring immediately.
The low-power divider block is controlled in the system clock control register (SCCR).
The default state of the low-power divider is to divide all clocks by one. Thus, for a 40MHz system, the general system clocks are each 40 MHz.
8.6 MPC555 Internal Clock Signals
The internal clocks generated by the clocks module are shown in Figure 8-4. The
clocks module also generates the CLKOUT and ENGCLK external clock signals. The
PLL synchronizes these signals to each other.
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USER’S MANUAL
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
T1
T2
T3
T4
Figure 8-4 MPC555 Clocks
Note that GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than
GCLK1 and GCLK2. This is to enable the external bus operation at lower frequencies
(controlled by EBDF in the SCCR). GCLK2_50 always rises simultaneously with
GCLK2. When DFNH = 0, GCLK2_50 has a 50% duty cycle. With other values of
DFNH or DFNL, the duty cycle is less than 50%. Refer to Figure 8-7. GCLK1_50 rises
simultaneously with GCLK1. When the MPC555 is not in gear mode, the falling edge
of GCLK1_50 occurs in the middle of the high phase of GCLK2_50. EBDF determines
the division factor between GCLK1/GCLK2 and GCLK1_50/GCLK2_50.
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During power-on reset, the MOCCK1, MODCK2, and MODCK3 pins determine the
clock source for the PLL and the clock drivers. These pins are latched on the positive
edge of PORESET. Their values must be stable as long as this line is asserted. The
configuration modes are shown in Table 8-1. MODCK1 specifies the input source to
the SPLL (OSCM or EXTCLK). MODCK1, MODCK2, and MODCK3 together determine the multiplication factor at reset and the functionality of limp mode.
If the configuration of PITRTCLK and TMBCLK and the SPLL multiplication factor is to
remain unchanged in power-down low-power mode, the MODCK signals should not
be sampled at wake-up from this mode. In this case the PORESET pin should remain
negated and HRESET should be asserted during the power supply wake-up stage.
When MODCK1 is cleared, the output of the main oscillator (OSCM) is selected as the
input to the SPLL. When MODCK1 is asserted, the external clock input (EXTCLK) is
selected as the input to the SPLL. In all cases, the system clock frequency (freqgclk2)
can be reduced by the DFNH[0:2] bits in the SCCR. Note that freqgclk2(max) occurs
when the DFNH bits are cleared.
The TBS bit in the SCCR selects the time base clock to be either the SPLL input clock
or GCLK2. When the backup clock is functioning as the system clock, the backup clock
is automatically selected as the time base clock source.
The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in
the SCCR. When the backup clock is functioning as the system clock, the backup
clock is automatically selected as the time base clock source.
When the PORESET pin is negated (driven to a high value), the MODCK1, MODCK2,
and MODCK3 values are not affected. They remain the same as they were defined
during the most recent power-on reset.
Table 8-1 shows the clock configuration modes during power-on reset (PORESET
asserted).
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Table 8-1 Reset Clocks Source Configuration
Default Values @ PORESET
1
MODCK[1:3]
LME
000
SPLL Options
MF + 1
PITCLK
Division
TMBCLK
Division
0
513
4
4
Used for testing purposes.
001
0
1
256
16
Normal operation, PLL enabled.
Main timing reference is freq(OSCM) = 20 MHz.
Limp mode disabled.
010
1
5
256
4
Normal operation, PLL enabled.
Main timing reference is freq(OSCM) = 4 MHz.
Limp mode enabled.
011
1
1
256
16
Normal operation, PLL enabled.
Main timing reference is freq(OSCM) = 20 MHz.
Limp mode enabled.
100
0
1
256
16
Normal operation, PLL enabled. 1:1 Mode
freqclkout(max) = freq(EXTCLK)
Limp mode disabled.
101
0
1
256
16
Normal operation, PLL enabled. 1:1 Mode
freqclkout(max) = freq(EXTCLK)
Limp mode disabled.
110
0
5
256
4
Normal operation, PLL enabled.
Main timing reference is freq(EXTCLK) = 3-5 MHz.
Limp mode disabled.
111
1
1
256
16
Normal operation, PLL enabled. 1:1 Mode
freqclkout(max) = freq(EXTCLK)
Limp mode enabled.
NOTES:
1. For other implementations in the MPC500 family, MODCK2 could be inverted.
NOTE
The reset value of the PLL pre-divider is 1.
The values of the PITRTCLK clock division and TMBCLK clock division can be
changed by software. The RTDIV bit value in the SCCR register defines the division
of PITRTCLK. All possible combinations of the TMBCLK divisions are listed in Table
8-2.
Table 8-2 TMBCLK Divisions
SCCR[TBS]
MF + 1
TMBCLK
Division
1
—
16
0
1, 2
16
0
>2
4
8.6.1 General System Clocks
The general system clocks (GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and
GCLK2_50) are the basic clock supplied to all modules and sub-modules on the
MPC555. GCLK1C and GCLK2C are supplied to the RCPU and to the BBC. GCLK1C
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and GCLK2C are stopped when the chip enters the doze-low power mode. GCLK1
and GCLK2 are supplied to the SIU and the clock module. The external bus clock
GCLK2_50 is the same as CLKOUT. The general system clock defaults to VCO/2 =
20 MHz (assuming a 20-MHz system frequency).
The general system clock frequency can be switched between different values. The
highest operational frequency can be achieved when the system clock frequency is
determined by DFNH (CSRC bit in the PLPRCR is cleared) and DFNH = 0 (division by
one). The general system clock can be operated at a low frequency (gear mode) or a
high frequency. The DFNL bits in SCCR define the low frequency. The DFNH bits in
SCCR define the high frequency.
The frequency of the general system clock can be changed dynamically with the system clock control register (SCCR), as shown in Figure 8-5.
VCO/2 (e.g., 40 MHz)
O
DFNH Divider
DFNH
Normal
O
O General System Clock
DFNL Divider
DFNL
O
Low Power
Figure 8-5 General System Clocks Select
The frequency of the general system clock can be changed “on the fly” by software.
The user may simply cause the general system clock to switch to its low frequency.
However, in some applications, there is a need for a high frequency during certain periods. Interrupt routines, for example, may require more performance than the low
frequency operation provides, but must consume less power than in maximum frequency operation. The MPC555 provides a method to automatically switch between
low and high frequency operation whenever one of the following conditions exists:
• There is a pending interrupt from the interrupt controller. This option is maskable
by the PRQEN bit in the SCCR.
• The (POW) bit in the MSR is clear in normal operation. This option is maskable
by the PRQEN bit in the SCCR.
When neither of these conditions exists and the CSRC bit in PLPRCR is set, the general system clock switches automatically back to the low frequency.
When the general system clock is divided, its duty cycle is changed. One phase
remains the same (e.g., 12.5 ns @ 40 MHZ) while the other become longer. Note that
CLKOUT does not have a 50% duty cycle when the general system clock is divided.
The CLKOUT waveform is the same as that of GCLK2_50.
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GCLK1 Divide by 1
GCLK2 Divide by 1
GCLK1 Divide by 2
GCLK2 Divide by 2
GCLK1 Divide by 4
GCLK2 Divide by 4
Figure 8-6 Divided System Clocks Timing Diagram
The system clocks GCLK1and GCLK2 frequency is:
FREQsysmax
FREQ sys = ------------------------------------------------------DFNH
DFNL + 1
(2
)or ( 2
)
The clocks GCLK1_50 and GCLK2_50 frequency is:
FREQsysmax
1
- × -------------------------FREQ 50 = ------------------------------------------------------DFNH
DFNL + 1
(2
)or ( 2
) EBDF + 1
Figure 8-7 shows the timing of USIU clocks when DFNH = 1 or DFNL = 0.
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GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
Figure 8-7 Clocks Timing For DFNH = 1 (or DFNL = 0)
8.6.2 CLKOUT
CLKOUT has the same frequency as the general system clock (GCLK2_50). The CLKOUT frequency defaults to VCO/4. CLKOUT can drive full- or half-strength or be
disabled. The drive strength is controlled in the system clock and reset-control register
(SCCR). Disabling or decreasing the strength of CLKOUT can reduce power consumption, noise, and electromagnetic interference on the printed circuit board.
When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low
state (provided that BUCS = 0).
8.6.3 Engineering Clock
ENGCLK is an output clock with a 50% duty cycle. Its frequency defaults to VCO/4.
ENGCLK frequency can be divided by a factor from one to 64, as controlled by the
ENGDIV[0:5] bits in the SCCR. ENGCLK can drive full or half strength or be disabled
(remaining in the high state). The drive strength is controlled by the EECLK[0:1] bits in
the SCCR. Disabling ENGCLK can reduce power consumption, noise, and electromagnetic interference on the printed circuit board.
When the PLL is acquiring lock, the ENGCLK signal is disabled and remains in the low
state (provided that BUCS = 0).
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NOTE
Skew elimination between CLKOUT and ENGCLK is not guaranteed.
8.7 Clock Source Switching
For limp mode support, clock source switching is supported. If for any reason the clock
source for the chip is not functioning, the user has the option to switch the system clock
to the backup clock ring oscillator, BUCLK.
This circuit consists of a loss-of-clock detector, which sets the LOCS status bit and
LOCSS sticky bit in the PLPRCR. If the LME bit in the SCCR is set, whenever LOCS
is asserted the clock logic switches the system clock automatically to BUCLK and
asserts hard reset to the chip. Switching the system clock to BUCLK is also possible
by software setting the STBUC bit in SCCR. Switching from limp mode to normal system operation is accomplished by clearing STBUC and LOCSS bits. This operation
also asserts hard reset to the chip.
At HRESET assertion, if the PLL output clock is not valid, the BUCLK will be selected
until software clears LOCSS bit in SCCR. At HRESET assertion, if the PLL output
clock is valid, the system will switch to oscillator/external clock. If during HRESET the
PLL loses lock or the clock frequency becomes slower than the required value, the
system will switch to the BUCLK. After HRESET negation the PLL lock condition does
not effect the system clock source selection.
If the LME bit is clear, the switch to the backup clock is disabled and assertion of
STBUC bit is ignored. If the chip is in limp mode, clearing the LME bit switches the system to normal operation and asserts hard reset to the chip.
Figure 8-8 describes the clock switching control logic. Table 8-3 summarizes the status and control for each state.
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LME = 1
poreset_b = 0
poreset_b = 0
1,BUCLK
poreset_b = 1
LME = 1
buclk_enable = 1
& hreset_b = 0
else
bu
cl
hr k _e
es n
et ab
_b le
= =0
1
buclk_enable=0
& hreset_b=0
4,osc
1
2,BUCLK
=
bu
c
hr lk_
es en
et ab
_b le
=
1
LME = 0
else
hreset_b = 1
hresert_b = 0
hreset_b = 1
bu
cl
k
as _ e
se na
rt ble
hr
es = 1
et
_b
3,BUCLK
6,BULCK
buclk-enable = 1
& hreset_b = 0
hreset_b = 0
LOCS
buclk_enable = 0
& hreset_b = 0
5, osc
else
Figure 8-8 Clock Source Flow Chart
NOTES
BUCLK_ENABLE = (STBUC | LOC) & LME lock indicates loss of lock
status bit (LOCS) for all cases and loss of clock sticky bit (LOCSS)
when state 3 is active. When BUCLK_ENABLE is changed, the chip
asserts HRESET to switch the system clock to BUCLK or PLL.
At PORESET negation, if the PLL is not locked, the loss-of-clock
sticky bit (LOCSS) is asserted, and the chip should operate with
BUCLK.
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The switching from state three to state four is accomplished by clearing the STBUC and LOCSS bits. If the switching is done when the
PLL is not locked, the system clock will not oscillate until lock condition is met.
Table 8-3 Status of Clock Source
LOCS
(status)
LOCSS
(sticky)
STBUC
BUCS
Chip
Clock
Source
STATE
PORESET
HRESET
LME
1
0
0
1
0
0
0
1
BUCLK
2
1
0
1
0/1
0
0
1
BUCLK
31
1
1
1
x2
0/1
0/1
1
BUCLK
0
0
Oscillator
4
1
0
0/1
0
x2
5
1
1
0/1
0
x2
0
0
Oscillator
6
1
0
1
0/1
1
0/1
1
BUCLK
NOTES:
1. At least one of the two bits, LOCSS or BUCS, must be asserted (one) in this state.
2. X = don’t care.
The default value of the LME bit is determined by MODCK[1:3] during assertion of
the PORESET line. The configuration modes are shown in Table 8-1.
8.8 Low-Power Modes
The LPM and other bits in the PLPRCR are encoded to provide one normal operating
mode and four low-power modes. In normal and doze modes the system can be in
high state with frequency defined by the DFNH bits, or in the low state with frequency
defined by the DFNL bits. The normal-high operating mode is the state out of reset.
This is also the state of the bits after the low-power mode exit signal arrives.
There are four low-power modes:
• Doze mode
• Sleep mode
• Deep-sleep mode
• Power-down mode
8.8.1 Entering a Low-Power Mode
Low-power modes are enabled by setting the POW bit in the MSR and clearing the
LPML (low-power mode lock) bit in the PLPRCR. Once enabled, a low-power mode is
entered by setting the LPM bits to the appropriate value. This can be done only in one
of the normal modes. The user cannot change the LPM or CSRC bits when the MCU
is in doze mode.
Table 8-6 summarizes the control bit settings for the different clock power modes.
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Table 8-4 Power Mode Control Bit Settings
Power Mode
LPM[0:1]
CSRC
TEXPS
Normal-high
00
0
X
Normal-low (“gear”)
00
1
X
Doze-high
01
0
X
Doze-low
01
1
X
Sleep
10
X
X
Deep-sleep
11
X
1
Power-down
11
X
0
8.8.2 Power Mode Descriptions
Table 8-5 describes the power consumption, clock frequency, and chip functionality
for each power mode.
Table 8-5 Power Mode Descriptions
Operation Mode
SPLL
Clocks
Normal-high
Active
Full frequency ÷
2DFNH
Power Consumption
@ 40 MHz
(Preliminary)
Functionality
≈ 20 mWatt+
1/2DFNH Watt
≈ 20 mWatt+
Normal-low (“gear”)
Active
Full frequency ÷
2DFNL+1
Doze-high
Active
Full frequency ÷
2DFNH
0.4/2DFNH Watt
Doze-low
Active
Full frequency ÷
2DFNL+1
0.4/2(DFNL+1) Watt
Sleep
Active
Not active
<10 mW
Deep-sleep
Not active
Not active
4 MHz – < 1 mW
20 MHz < TBD1
Temp. = 50° C
Power-down
Not active
Not active
4 and 20 MHz < TBD1
Temperature = 50° C
VDDSRAM
Not active
Not active
TBD
Full functions not in use
are shut off
1/2(DFNL+1) Watt
≈ 20 mWatt+
≈ 20 mWatt+
Enabled: RTC, PIT,
TB and DEC,
memory controller
Disabled: extended
core
(RCPU, BBC, FPU)
Enabled: RTC, PIT, TB
and DEC
SRAM’s data
retention
NOTES:
1. See Electrical Specification for actual values.
8.8.3 Exiting from Low-Power Modes
Exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt generated by the memory controller. Any enabled asynchronous
interrupt clears the LPM bits but does not change the PLPRCR[CSRC] bit.
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The exit from normal-low, doze-high, and low modes and sleep mode to normal-high
mode is accomplished with the asynchronous interrupt. The sources of the asynchronous interrupt are:
• Asynchronous wake-up interrupt from the interrupt controller
• RTC, PIT, or time base interrupts (if enabled)
• Decrementer exception
The system response to asynchronous interrupts is fast. The wake-up time from normal-low, doze-high, doze-low, and sleep mode due to an asynchronous interrupt or
decrementer exception is only three to four clock cycles of maximum system frequency. In 40-MHz systems, this wake-up requires 75 to 100 ns. The asynchronous
wake-up interrupt from the interrupt controller is level sensitive one. It will therefore be
negated only after the reset of interrupt cause in the interrupt controller.
The timers (RTC, PIT, time base, or decrementer) interrupts indication set status bits
in the PLPRCR (TMIST). The clock module considers this interrupt to be pending
asynchronous interrupt as long as the TMIST is set. The TMIST status bit should be
cleared before entering any low-power mode.
Table 8-7 summarizes wake-up operation for each of the low-power modes.
Table 8-6 Power Mode Wake-Up Operation
Operation Mode
Wake-up
Method
Return Time from Wake-up
Event to Normal-High
Normal-low (“gear”)
Software
or
Interrupt
Doze-high
Interrupt
Doze-low
Interrupt
Sleep
Interrupt
3-4 maximum system clocks
Deep-sleep
Interrupt
< 500 Oscillator Cycles
125 µsec – 4 MHz
25 µsec – 20 MHz
Power-down
Interrupt
< 500 oscillator cycles + power
supply wake-up
VDDSRAM
External
Power-on sequence
Asynchronous interrupts:
3-4 maximum system cycles
Synchronous interrupts:
3-4 actual system cycles
8.8.3.1 Exiting from Normal-Low Mode
In normal mode (as well as doze mode), if the PLPRCR[CSRC] bit is set, the system
toggles between low frequency (defined by PLPRCR[DFNL]) and high frequency
(defined by PLPRCR[DFNH]. The system switches from normal-low mode to normalhigh mode if either of the following conditions is met:
• An interrupt is pending from the interrupt controller; or
• The MSR[POW] bit is cleared (power management is disabled).
When neither of these conditions are met, the PLPRCR[CSRC] bit is set, and the asynchronous interrupt status bits are reset, the system returns to normal-low mode.
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8.8.3.2 Exiting from Doze Mode
The system changes from doze mode to normal-high mode whenever an interrupt is
pending from the interrupt controller.
8.8.3.3 Exiting from Deep-Sleep Mode
The system switches from deep-sleep mode to normal-high mode if any of the following conditions is met:
• An interrupt is pending from the interrupt controller
• An interrupt is requested by the RTC, PIT, or time base
• A decrementer exception
In deep-sleep mode the PLL is disabled. The wake-up time from this mode is up to 500
PLL input frequency clocks. In one-to-one mode the wake-up time may be up to 100
PLL input frequency clocks. For a PLL input frequency of 4 MHz, the wake-up time is
less than 125 µs.
8.8.3.4 Exiting from Power-Down Mode
Exit from power-down mode is accomplished through hard reset. External logic should
assert HRESET in response to the TEXPS bit being set and TEXP pin being asserted.
The TEXPS bit is set by an enabled RTC, PIT, time base, or decrementer interrupt.
The hard reset should be asserted for no longer than the time it takes for the power
supply to wake-up in addition to the PLL lock time. When the TEXPS bit is cleared (and
the TEXP signal is negated), assertion of hard reset sets the bit, causes the pin to be
asserted, and causes an exit from power-down low-power mode. Refer to 8.9.3 Keep
Alive Power for more information.
8.8.3.5 Low-Power Modes Flow
Figure 8-9 shows the flow among the different power modes.
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(MSRPOW+Interrupt)+CSRC
Software *
Normal-Low
LPM = 00, CSRC = 1
Software *
((MSRPOW+Interrupt))*CSRC***
Doze-Low
LPM = 01, CSRC = 1
Interrupt
Wake-up: 3 - 4 SysFreq
Clocks
Software *
Asynchronous
Interrupts
Doze-High
LPM = 01, CSRC = 0/1
Wake-up: 3 - 4 SysFreqmax
Clocks
LPM = 00
CSRC = 0/1
Software *
Sleep Mode
LPM = 10, CSRC = 0
Software *
Deep-Sleep Mode
LPM = 11, CSRC = 0,
TEXPS = 1
Software *
Normal
High Mode
Power-Down Mode
LPM = 11, CSRC = 0,
TEXPS = 0**
Async. Wake-up or
RTC/PIT/TB/DEC Interrupt
Wake-up: 500 Input
Frequency Clocks
RTC/PIT/TB/DEC Interrupt followed
by External Hard Reset
or External Hard Reset
Software *
Hard Reset
* Software is active only in normal-high/low modes
** TEXPS receives the zero value by writing one. Writing of zero has no effect on TEXPS.
*** The switch from normal-high to normal-low is enable only if the conditions to asynchronous
interrupt are cleared
Figure 8-9 MPC555 Low-Power Modes Flow Diagram
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8.9 Basic Power Structure
8.9.1 Clock Unit Power Supply
KAPWR and VSS power the following clock unit modules: oscillator, PITRTCLK and
TMBCLK generation logic, timebase, decrementer, RTC, PIT, system clock control
register (SCCR), low-power and reset-control register (PLPRCR), and reset status
register (RSR). All other circuits are powered by the normal supply pins, VDDI, VDDL,
VDDH and VSS. The power supply for each block is listed in Table 8-7.
Table 8-7 Clock Unit Power Supply
Circuit
CLKOUT
SPLL (digital),
System low-power control
Internal logic
Clock drivers
Power Supply
VDDL/VDDI
SPLL (analog)
VDDSYN
Main oscillator
Reset machine
Limp mode mechanism
Register control
SCCR, PLLRCR and RSR
RTC, PIT, TB, and DEC
KAPWR
SRAM,
VDDSRAM detector,
VSRMCR
VDDSRAM
The following are the relations between different power supplies:
• VDDL = VDDI = VDDSYN = VDDF = 3.3 V ±10%
• KAPWR ≥ VDDL – 0.3 V (during normal operation)
• VDDSRAM ≥ VDDL – 0.3 V (during normal operation)
• VDDSRAM ≥ 2.0 V (during standby operation)
• VPP ≥ VDDL – 0.3 V, but VPP – VDDL < 4.0 volts
8.9.2 Chip Power Structure
The MPC555 provides a wide range of possibilities for power supply connections. Figure 8-10 illustrates the different power supply sources for each of the basic units on
the chip.
8.9.2.1 VDDL
The I/O buffers and logic are fed by a 3.3-V power supply.
8.9.2.2 VDDI
VDDI powers the internal logic of the MPC555, nominally 3.3 V.
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8.9.2.3 VDDSYN, VSSSYN
The charge pump and the VCO of the SPLL are fed by a separate 3.3-V power supply
(VDDSYN) in order to improve noise immunity and achieve a high stability in its output
frequency. VSSSYN provides an isolated ground reference for the PLL.
8.9.2.4 KAPWR
The oscillator, time base counter, decrementer, periodic interrupt timer and the realtime clock are fed by the KAPWR rail. This allows the external power supply unit to
disconnect all other sub-units of the MCU in low-power deep-sleep mode. The TEXP
pin (fed by the same rail) can be used by the external power supply unit to switch
between sources. The IRQ[6:7]/MODCK[2:3], IRQ5/MODCK1, XTAL, EXTAL, EXTCLK, PORESET, HRESET, SRESET, and RSTCONF/TEXP input pins are powered
by KAPWR. Circuits, including pull-up resisters, driving these inputs should be powered by KAPWR.
8.9.2.5 VDDA, VSSA
VDDA supplies power to the analog subsystems of the QADC_A and QADC_B modules; it is nominally 5.0 V. VDDA is the ground reference for the analog subsystems.
8.9.2.6 VPP
VPP supplies the programming and erase voltage for the CMF Flash modules. It is
nominally 5.0 V for program or erase operations and can be lowered to a nominal 3.3
V for read operations.
8.9.2.7 VDDF, VSSF
VDDF provides internal power to the CMF flash module; it should be a nominal 3.3 V.
VSSF provides an isolated ground for the CMF flash module.
8.9.2.8 VDDH
VDDH provides power for the 5-V I/O operations. It is a nominal 5.0 V.
8.9.2.9 VDDSRAM
VDDSRAM supplies power to the 26-Kbyte SRAM module and the DPTRAM. It can
be used to keep the contents on the SRAM stable while the rest of the MPC555 is powered down for standby operation.
8.9.2.10 VSS
VSS provides the ground reference for the MPC555.
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VPP
VDDF
I/O
VDDH
SRAM
FLASH
Oscillator,
PIT, RTC, TB,
and DEC
Internal Logic
Clock Control
PLL
VDDI
VDDSRAM
TEXP
KAPWR
VDDI
VDDL
VDDSYN
Figure 8-10 Basic Power Supply Configuration
8.9.3 Keep Alive Power
8.9.3.1 Keep Alive Power Configuration
Figure 8-11 illustrates an example of a switching scheme for an optimized low-power
system. SW1 and SW2 can be unified in only one switch if VDDSYN and VDDI/VDDL
are supplied by the same source.
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USER’S MANUAL
SW1
O
VDDSYN
Main Power
Supply
O
O
VDD
3.3 V
SW2
O
MPC555
TEXP
Switch
Logic
VDDSRAM
VDDSRAM
Power Supply
3.3 V
KAPWR
3 V - 3.3 V
Backup
Power
Supply
Figure 8-11 External Power Supply Scheme
The MPC555 asserts the TEXP signal, if enabled, when the RTC or TB time value
matches the value programmed in the associated alarm register or when the PIT or
DEC value reaches zero. The TEXP signal is negated when the TEXPS status bit is
written to one.
The KAPWR power supply feeds the main crystal oscillator (OSCM). The condition for
the main crystal oscillator stability is that the power supply value changes slowly. The
maximum slope must be less than 5 mV per oscillation cycle (τ > 200-300/freqoscm).
8.9.3.2 Keep Alive Power Registers Lock Mechanism
The USIU timer, clocks, reset, power, decrementer, and time base registers are powered by the KAPWR supply. When the main power supply is disconnected after powerdown mode is entered, the value stored in any of these registers is preserved. If
power-down mode is not entered before power disconnect, there is a chance of data
loss in these registers. To minimize the possibility of data loss, the MPC555 includes
a key mechanism that ensures data retention as long as a register is locked. While a
register is locked, writes to this register are ignored.
Each of the registers in the KAPWR region have a key that can be in one of two states:
open or locked. At power-on reset the following keys are locked: RTC, RTSEC,
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RTCAL, and RTCSC. All other registers are unlocked. Each key has an address associated with it in the internal memory map.
A write of 0x55CCAA33 to the associated key register changes the key to the open
state. A write of any other data to this location changes the key to the locked state.
Table 8-8 lists the registers powered by KAPWR and the associated key registers.
Table 8-8 KAPWR Registers and Key Registers
KAPWR Register
Address or
SPR Number
Associated Key Register
Register
Address
Register
0x2F C200
Time Base Status and Control (TBSCR)
See Table 6-16 for bit descriptions.
0x2F C204
Time Base Reference 0 (TBREF0)
See 6.13.4.3 Time Base Reference Reg- 0x2F C304
isters for bit descriptions.
Time Base Reference 0 Key (TBREF0K)
0x2F C208
Time Base Reference 1 (TBREF1)
See 6.13.4.3 Time Base Reference Reg- 0x2F C308
isters for bit descriptions.
Time Base Reference 1 Key (TBREF1K)
0x2F C220
Real Time Clock Status and Control
(RTCSC)
See Table 6-17 for bit descriptions.
0x2F C320
Real Time Clock Status and Control Key
(RTCSCK)
0x2F C224
Real Time Clock (RTC)
See 6.13.4.6 Real-Time Clock Register
(RTC) for bit descriptions.
0x2F C324
Real Time Clock Key (RTCK)
0x2F C228
Real Time Alarm Seconds (RTSEC)
Reserved
0x2F C328
Real Time Alarm Seconds Key (RTSECK)
0x2F C22C
Real Time Alarm (RTCAL)
See 6.13.4.7 Real-Time Clock Alarm
Register (RTCAL) for bit descriptions.
0x2F C32C
Real Time Alarm Key (RTCALK)
0x2F C240
PIT Status and Control (PISCR)
See Table 6-18 for bit descriptions.
0x2F C340
PIT Status and Control Key (PISCRK)
0x2F C244
PIT Count (PITC)
See Table 6-19 for bit descriptions.
0x2F C344
PIT Count Key (PITCK)
0x2F C280
System Clock Control Register (SCCR)
See Table 8-9 for bit descriptions.
0x2F C380
System Clock Control Key (SCCRK)
0x2F C284
PLL Low-Power and Rese-Control
Register (PLPRCR)
See Table 8-10 for bit descriptions.
0x2F C384
PLL Low-Power and Reset-Control Register Key (PLPRCRK)
0x2F C288
Reset Status Register (RSR)
See Table 7-3 for bit descriptions.
0x2F C388
Reset Status Register Key (RSRK)
0x2F C30C
Time Base and Decrementer Key (TBK)
SPR 22
Decrementer
See 3.9.5 Decrementer Register (DEC)
for bit descriptions.
SPR 268, 269,
284, 285,
Time Base
See Table 3-11 and Table 3-14 for bit descriptions.
0x2F C300
Time Base Status and Control Key
(TBSCRK)
Figure 8-12 illustrates the process of locking or unlocking a register powered by
KAPWR.
MOTOROLA
8-24
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MPC555
USER’S MANUAL
Power On Reset
(Valid for other registers)
Open
Write to the Key 0x55CCAA33
Write to the key other value
Locked
Power On Reset
(Valid for RTC, RTSEC,
RTCAL and RTCSC)
Figure 8-12 Keep Alive Register Key State Diagram
8.10 VDDSRAM Supply Failure Detection
A special circuit for VDDSRAM supply failure detection is provided. In the case of supply failure detection, the dedicated sticky bits LVSRS in the VSRMCR register are
asserted. Software can read or clear these bits. The user should enable the detector
and then clear these bits. If the user reads any of the LVSR bits as one, then a power
failure of VDDSRAM has occurred. The circuit is capable of detecting supply failure
below 2.6 V. Also, enable/disable control bit for the VDDSRAM detector may be used
to disconnect the circuit and save the detector power consumption.
8.11 Power Up/Down Sequencing
Figure 8-13 and Figure 8-14 detail the power-up sequencing for MPC555 during normal operation. Note that for each of the conditions detailing the voltage relationships
the absolute bounds of the minimum and maximum voltage supply cannot be violated,
i.e. the value of VDDL cannot fall below 3.0 V or exceed 3.6 V and the value of VDDH
cannot fall below 4.5 V or exceed 5.5 V for normal operation. Further information
detailing the functionality of the VPP signal for flash program and erase is outlined in
19.9.2 FLASH Program/Erase Voltage Conditioning. Power consumption during
power up sequencing can not be specified prior to evaluation and characterization of
production silicon. The goal is to keep the power consumption during power up
sequencing below the operating power consumption.
During the power down sequence the user needs to assert PORESET while VDDI and
VDDL are at a voltage equal or greater to 3 V. Below this voltage the power supply
chip can be turn off. If the turn off voltage of the power supply chip is greater than 0.74
V for the 3 V supply and greater than 0.8 V for the 5 V supply, then the circuitry inside
the MPC555 will act as a load to the respective supply and will discharge the supply
line down to these values. Since the 3 V logic represents a larger load to the supply
chip, the 3 V supply line will decay faster than the 5 V supply line.
MPC555
USER’S MANUAL
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MOTOROLA
8-25
Figure 8-13 No Standby, No KAPWR, All System Power On/Off
8-26
MOTOROLA
CLOCKS AND POWER CONTROL
Revised 1 March 1999
USER’S MANUAL
MPC555
HRESET_B
PORESET_B
VPP (3V)
VDDSYN
VDDA, VRH
VDDSRAM
KAPWR
VDDI, VDDL,VDDF
VDDH
See NOTE 2.
See NOTE 1.
when programming
VPP goes to 5V
Operating
Power On
Power Off
Figure 8-14 Standby and KAPWR, Other Power On/Off
MPC555
USER’S MANUAL
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MOTOROLA
8-27
HRESET_B
PORESET_B
VPP (3V)
VDDSYN
VDDA, VRH
VDDSRAM
KAPWR
VDDI, VDDL,VDDF
VDDH
No Battery
Connect Battery
See NOTE 1.
Power On
when programming
VPP goes to 5V
See NOTE 2.
Operating
Power Off
No Battery
NOTE
The following notes apply to Figure 8-13 and Figure 8-14 above:
VDDH ≥ VDDL - 0.35 V (0.5 V max. at temperature extremes)
VPP ≤ VDDH + 0.5 V AND VPP ≥ VDDL - 0.35 V
(The delta VPP - VDDL must be ≤ 3.6 V during power on or off)
1.
VDDA can lag VDDH, and VDDSYN can lag VDDL, but both must be at a valid level before resets are
negated.
2.
If keep alive functions are NOT used, then when system power is on:
KAPWR = VDDSRAM = VDDL ± 0.35 V
3.
If keep alive functions ARE used, then
KAPWR = VDDSRAM = VDDL = 3.3 V ± 0.35 V when system power is on
VDDSRAM ≥ 1.8 V and optionally KAPWR = 3.3 V ± 0.3 V when system power is off
Normal system power is defined as
VDDL = VDDI = VDDF = VDDSYN = VPP = VDDSRAM = KAPWR = 3.3 ± 0.3 V and VDDA = VDDH =
5.0 ± 0.5 V
Flash Programming requirements are the same as normal system power, except VPP = 5.0 ± 0.25 V
8.12 Clocks Unit Programming Model
8.12.1 System Clock Control Register (SCCR)
The SPLL has a 32-bit control register, SCCR, which is powered by keep-alive power.
SCCR — System Clock Control Register
MSB
0
1
2
DBCT
3
COM
4
5
DCSLR MFPDL LPML
6
TBS
7
0x2F C280
8
9
10
11
12
13
RTDIV STBUC RESERVED PRQEN RTSEL BUCS
14
EBDF
15
LME
POWER-ON RESET:
1
0
0
0
0
0
0
1
0
0
1
EQ2
ID2*
U
0
0
U
U
U
0
1
U
19
20
21
22
23
24
25
26
EQ3
HARD RESET:
U
0
16
17
18
EECLK
ENGDIV
—
27
DFNL
U
28
ID[13:14]*
29
—
U
LSB
31
30
DFNH
POWER-ON RESET:
0
0
0
0
0
0
0
1
U
U
U
U
U
U
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HARD RESET:
U
U
Note:
EQ2 = MODCK1
EQ3 = (MODCK1 & MODCK2 & MODCK3) | (MODCK1 & MODCK2 & MODCK3) | (MODCK1 & MODCK2 & MODCK3).
See Table 8-1.
* = The hard reset value is a reset configuration word value, extracted from the indicated internal data bus lines. Refer
to 7.5.2 Hard Reset Configuration Word.
U = Unaffected by reset
MOTOROLA
8-28
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 8-9 SCCR Bit Settings
Bit(s)
0
1:2
3
4
5
6
Name
Description
DBCT
Disable backup clock for timers. The DBCT bit controls the timers clock source while the chip
is in limp mode. If DBCT is set, the timers clock (tbclk, rtclk) source will not be the backup
clock, even if the system clock source is the backup clock ring oscillator. The real-time clock
source will be EXTAL or EXTCLK according to RTSEL bit (see description in bit 11 below),
and the time base clocks source will be determined according to TBS bit and MODCK1.
0 = If the chip is in limp mode, the timer clock source is the backup (limp) clock
1 = The timer clock source is either the external clock or the crystal (depending on the current
clock mode selected)
COM
Clock output mode. These bits control the output buffer strength of the CLKOUT and external
bus pins. These bits can be dynamically changed without generating spikes on the CLKOUT
and external bus pins. If CKLOUT is not connected to external circuits, set both bits (disabling CLKOUT) to minimize noise and power dissipation. COM1 is determined by the hard
reset configuration word.
00 = Clock output enabled full-strength output buffer, bus pins full drive
01 = Clock output enabled half-strength output buffer, bus pins reduced drive
10 = Clock output disabled, bus pins full drive
11 = Clock output disabled, bus pins reduced drive
DCSLR
Disable clock switching at loss of lock during reset. When DCSLR is clear and limp mode is
enabled, the chip will switch automaticaly to the backup clock if the PLL losses lock during
HRESET. When DCSLR is asserted, a PLL loss-of-lock event does not cause clock switching. If HRESET is asserted and DCSLR is set, the chip will not negate HRESET until the PLL
aquires lock.
0 = Enable clock switching if the PLL loses lock during reset
1 = Disable clock switching if the PLL loses lock during reset
MFPDL
MF and pre-divider lock. Setting this control bit disables writes to the MF and DIVF bits. This
helps prevent runaway software from changing the VCO frequency and causing the SPLL to
lose lock. In addition, to protect against hardware interference, a hardware reset will be
asserted if these fields are changed while LPML is asserted. This bit is writable once after
power-on reset.
0 = MF and DIVF fields are writable
1 = MF and DIVF fields are locked
LPML
LPM lock. Setting this control bit disables writes to the LPM and CSRC control bits. In addition, for added protection, a hardware reset is asserted if any mode is entered other than
normal-high mode. This protects against runaway software causing the MCU to enter lowpower modes. (The MSR[POW] bit provides additional protection). LPML is writable once
after power-on reset.
0 = LPM and CSRC bits are writable
1 = LPM and CSRC bits are locked and hard reset will occur if the MCU is not in normal-high
mode
TBS
Time base source. Note that when the chip is operating in limp mode (BUCS = 1), TBS is
ignored, and the backup clock is the time base clock source.
0 = Source is OSCCLK divided by either four or 16
1 = Source is system clock divided by 16
RTDIV
RTC (and PIT) clock divider. At power-on reset this bit is cleared if MODCK[1:3] are all low;
otherwise the bit is set.
0 = RTC and PIT clock divided by four
1 = RTC and PIT clock divided by 256
8
STBUC
Switch to backup clock control. When software sets this bit, the system clock is switched to
the on-chip backup clock ring oscillator, and the chip undergoes a hard reset. The STBUC
bit is ignored if LME is cleared.
0 = Do not switch to the backup clock ring oscillator
1 = Switch to backup clock ring oscillator
9
—
7
MPC555
USER’S MANUAL
Reserved
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MOTOROLA
8-29
Table 8-9 SCCR Bit Settings (Continued)
Bit(s)
10
11
12
13:14
Name
Description
PRQEN
Power management request enable
0 = Remains in the lower frequency (defined by DFNL) even if the power management bit in
the MSR is reset (normal operational mode) or if there is a pending interrupt from the
interrupt controller
1 = Switches to high frequency (defined by DFNH) when the power management bit in the
MSR is reset (normal operational mode) or there is a pending interrupt from the interrupt
controller
RTSEL
RTC circuit input source select. At power-on reset RTSEL receives the value of the
MODCK1 bit. Note that if the chip is operating in limp mode (BUCS = 0), the RTSEL bit is
ignored, and the backup clock is the clock source for the RT and PIT clocks
0 = OSCM clock is selected as input to RTC and PIT
1 = EXTCLK clock is selected as the RTC and PIT clock source
BUCS
Backup clock status. This status bit indicates the current system clock source. When loss of
clock is detected and the LME bit is set, the clock source is the backup clock and this bit is
set. When the user sets the STBUC bit and LME bit is set, the system switches to the backup
clock and BUCS is set.
0 = System clock is not the backup clock
1 = System clock is the backup clock
EBDF
External bus division factor. These bits define the frequency division factor between (GCLK1
and GCLK2) and (GCLK1_50 and GCLK2_50). CLKOUT is similar to GCLK2_50. The
GCLK2_50 and GCKL1_50 are used by the external bus interface and memory controller in
order to interface to the external system. The EBDF bits are initialized during hard reset
using the hard reset configuration mechanism.
00 = CLKOUT is GCKL2 divided by 1
01 = CLKOUT is GCKL2 divided by 2
1x = Reserved
Limp mode enable. When LME is set, the loss-of-clock monitor is enabled and any detection
of loss of clock will switch the system clock automatically to backup clock. It is also possible
to switch to the backup clock by setting the STBUC bit.
15
LME
If LME is cleared, the option of using limp mode is disabled. The loss of clock detector is not
active, and any write to STBUC is ignored.
The LME bit is writable once, by software, after power-on reset, when the system clock is not
backup clock (BUCS = 0). During power-on reset, the value of LME is determined by the
MODCK[1:3] bits. (Refer to Table 8-1.)
0 = Limp mode disabled
1 = Limp mode enabled
16:17
18:23
EECKL
ENGDIV
Enable engineering clock. This field controls the output buffer strength of the ENGCLK pin.
When both bits are set the ENGCLK pin is held in the high state. These bits can be dynamically changed without generating spikes on the ENGCLK pin. If ENGCLK is not connected
to external circuits, set both bits (disabling ENGCLK) to minimize noise and power dissipation. For measurement purposes the backup clock (BUCLK) can be driven externally on the
ENGCLK pin.
00 = Engineering clock enabled, full-strength output buffer
01 = Engineering clock enabled, half-strength output buffer
10 = BUCKL is the output on the ENGCLK full-strength output buffer
11 = Engineering clock disabled
Engineering clock division factor. These bits define the frequency division factor between
VCO/2 and ENGCLK. Division factor can be from 1 (ENGDIV = 000000) to 64 (ENGDIV =
111111). These bits can be read and written at any time. They are not affected by hard reset
but are cleared during power-on reset.
Note that if the engineering clock division factor is not a power of two, synchronization
between the system and ENGCLK is not guaranteed.
24
MOTOROLA
8-30
—
Reserved
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 8-9 SCCR Bit Settings (Continued)
Bit(s)
Name
Description
25:27
DFNL
Division factor low frequency. The user can load these bits with the desired divide value and
the CSRC bit to change the frequency. Changing the value of these bits does not result in a
loss of lock condition. These bits are cleared by power-on or hard reset. Refer to 8.6.1 General System Clocks and Figure 8-5 for details on using these bits.
000 = Divide by 2
001 = Divide by 4
010 = Divide by 8
011 = Divide by 16
100 = Divide by 32
101 = Divide by 64
110 = Reserved
111 = Divide by 256
28
—
29:31
Reserved
Division factor high frequency. These bits determine the general system clock frequency during normal mode. Changing the value of these bits does not result in a loss of lock condition.
These bits are cleared by power-on or hard reset. The user can load these bits at any time
to change the general system clock rate. Note that the GCLKs generated by this division factor are not 50% duty cycle.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Reserved
DFNH
8.12.2 PLL, Low-Power, and Reset-Control Register (PLPRCR)
The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered
by the keep alive power supply.
PLPRCR — PLL, Low-Power, and Reset-Control Register
MSB
0
1
2
3
4
5
6
7
8
9
0x2F C284
10
11
12
MF
13
RESERVED LOCS
14
15
LOCSS
SPLS
POWER-ON RESET:
0 OR 4
0
0
0
0
U
U
U
U
HARD RESET:
U
16
U
17
U
U
U
18
19
20
U
21
U
U
22
SPLSS TEXPS RESERVED TMIST RESERVED CSRC
23
LPM
U
24
CSR
U
25
U
U
26
27
28
LOLRE RESERVED
29
30
LSB
31
DIVF
POWER-ON RESET:
0
1
0
0
0
0
0
0
0
0
U
0
U
0
0
0
U
U
0
0
0
0
0
0
U
U
U
U
U
HARD RESET:
U
1
U = Unaffected by reset
MPC555
USER’S MANUAL
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MOTOROLA
8-31
Table 8-10 PLPRCR Bit Settings
Bit(s)
Name
Description
Multiplication factor bits. The output of the VCO is divided to generate the feedback signal to
the phase comparator. The MF bits control the value of the divider in the SPLL feedback
loop. The phase comparator determines the phase shift between the feedback signal and
the reference clock. This difference results in either an increase or decrease in the VCO output frequency.
0:11
MF
The MF bits can be read and written at any time. However, this field can be write-protected
by setting the MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the MF bits
causes the SPLL to lose lock.
The normal reset value for the DFNH bits is zero (divide by one). When the PLL is operating
in one-to-one mode, the multiplication factor is set to x1 (MF=0).
12
—
Reserved
LOCS
Loss of clock status. When the oscillator or external clock source is not at the minimum frequency, the loss-of-clock circuit asserts the LOCS bit. This bit is cleared when the oscillator
or external clock source is functioning normally. This bit is reset only on power-on reset.
Writes to this bit have no effect.
0 = No loss of oscillator is currently detected
1 = Loss of oscillator is currently detected
14
LOCSS
Loss of clock sticky. If, after negation of PORESET, the loss-of-clock circuit detects that the
oscillator or external clock source is not a t a minimum frequency, the LOCSS bit is set.
LOCSS remains set until software clears it by writing a one to it. A write of zero has no effect
on this bit. The reset value is determined during hard reset. The STBUC bit will be set provided the PLL lock condition is not met when HRESET is asserted, and cleared if the PLL is
locked when HRESET is asserted.
0 = No loss of oscillator has been detected
1 = Loss of oscillator has been detected
15
SPLS
13
16
SPLSS
System PLL lock status bit
0 = SPLL is currently not locked
1 = SPLL is currently locked
SPLL lock status sticky bit. An out-of-lock sets the SPLSS bit. The bit remains set until software clears it y writing a one to it. A write of zero has no effect on this bit. The bit is cleared
at power-on reset. This bit is not affected due to a software initiated loss-of-lock (MF change
and entering deep-sleep or power-down mode). The SPLSS bit is not affected by hard reset.
0 = SPLL has remained in lock
1 = SPLL has gone out of lock at least once (not due to software-initiated loss of lock)
Timer expired status bit. This bit controls whether the chip negates the TEXP pin in deepsleep mode, thus enabling external circuitry to switch off the VDD (power-down mode).
When LPM = 11, CSRC = 0, and TEXPS is high, the TEXP pin remains asserted. When LPM
= 11, CSRC = 0, and TEXPS is low, the TEXPS pin is negated.
17
TEXPS
To enable automatic wake-up TEXPS is asserted when one of the following occurs:
• The PIT is expired
• The real-time clock alarm is set
• The time base clock alarm is set
• The decrementer exception occurs
The bit remains set until software clears it by writing a one to it. A write of zero has no effect
on this bit. TEXPS is set by power-on or hard reset.
0 = TEXP is negated in deep-sleep mode
1 = TEXP pin remains asserted always
18
MOTOROLA
8-32
—
Reserved
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 8-10 PLPRCR Bit Settings (Continued)
Bit(s)
Name
Description
19
TMIST
Timers interrupt status.TMIST is set when an interrupt from the RTC, PIT, TB or DEC occurs.
The TMIST bit is cleared by writing a one to it. Writing a zero has no effect on this bit. The
system clock frequency remains at its high frequency value (defined by DFNH) if the TMIST
bit is set, even if the CSRC bit in the PLPRCR is set (DFNL enabled) and conditions to switch
to normal-low mode do not exist. This bit is cleared during power-on or hard reset.
0 = No timer expired event was detected
1 = A timer expire event was detected
20
—
21
CSRC
Reserved
Clock source. This bit is cleared at hard reset.
0 = General system clock is determined by the DFNH value
1 = General system clock is determined by the DFNL value
LPM
low-power mode select. These bits are encoded to provide one normal operating mode and
four low-power modes. In normal and doze modes, the system can be in high state (frequency determined by the DFNH bits) or low state (frequency defined by the DFNL bits). The
LPM field can be write-protected by setting the LPM and CSRC lock (LPML) bit in the
PLPRCR Refer to Table 8-4 and Table 8-5.
24
CSR
Checkstop reset enable. If this bit is set, then an automatic reset is generated when the
RCPU signals that it has entered checkstop mode, unless debug mode was enabled at reset.
If the bit is clear and debug mode is not enabled, then the USIU will not do anything upon
receiving the checkstop signal from the RCPU. If debug mode is enabled, then the part
enters debug mode upon entering checkstop mode. In this case, the RCPU will not assert
the checkstop signal to the reset circuitry. This bit is writable once after soft reset.
0 = No reset will occur when checkstop is asserted
1 = Reset will occur when checkstop is asserted
25
LOLRE
26
—
22:23
27:31
DIVF
Loss of lock reset enable
0 = Loss of lock does not cause HRESET assertion
1 = Loss of lock causes HRESET assertion
Reserved
The DIVF bits control the value of the pre-divider in the SPLL circuit. The DIVF bits can be
read and written at any time. However, the DIVF field can be write-protected by setting the
MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the DIVF bits causes the SPLL
to lose lock.
8.12.3 Change of Lock Interrupt Register (COLIR)
The COLIR is 16-bit read/write register. It controls the change of lock interrupt generation, and is used for reporting a loss of lock interrupt source. It contains the interrupt
request level and the interrupt status bit. This register is readable and writable at any
time. A status bit is cleared by writing a one (writing a zero does not affect a status bit’s
value). The COLIR is memory mapped into the MPC555 USIU register map.
COLIR — Change of Lock Interrupt Register
MSB
0
1
2
3
4
5
6
7
COLIRQ
0x2F C28C
8
9
10
11
12
13
14
LSB
15
U
U
U
U
U
U
COLIS COLIE
RESET:
0
0
0
0
0
0
0
0
0
0
U = Unaffected by reset
MPC555
USER’S MANUAL
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MOTOROLA
8-33
Table 8-11 COLIR Bit Settings
Bit(s)
Name
Description
0:7
COLIRQ
Change of lock interrupt request level. These bits determine the interrupt priority level of the
change of lock. To specify certain level, the appropriate one of these bits should be set.
8
COLIS
If set (“one”), the bit indicates that a change in the PLL lock status was detected. The PLL
was locked and lost lock, or the PLL was unlocked and got locked. The bit should be cleared
by writing a one.
9
COLIE
Change of Lock Interrupt enable. If COLIE bit is asserted, an interrupt will generate when the
COLIS bit is asserted.
0 = Change of lock Interrupt disable
1 = Change of lock Interrupt enable
10:15
—
Reserved
8.12.4 VDDSRAM Control Register (VSRMCR)
This register contains control bits for enabling or disabling the VDDSRAM supply
detection circuit. There are also four bits that indicate the failure detection. All four bits
have the same function and are required to improve the detection capability in extreme
cases.
VSRMCR — VDDSRAM Control Register
MSB
0
1
2
0
3
4
5
LVSRS
6
7
0x2F C290
8
9
10
11
12
13
14
LSB
15
RESERVED
VSRDE
HARD RESET:
U
U
U
U
0
U = Unaffected by reset
Table 8-12 VSRMCR Bit Settings
Bit(s)
Name
0
—
Description
Reserved
1:4
LVSRS
Loss of VDDSRAM sticky. These status bits indicate whether a VDDSRAM supply failure
occurred. In addition, when the power is turned on for the first time, VDDSRAM rises and
these bits are set. The LVSRS bits are cleared by writing them to ones. A write of zero has
no effect on these bits.
0 = No VDDSRAM supply failure was detected
1 = VDDSRAM supply failure was detected
5
VSRDE
VDDSRAM detector disable.
0 = VDDSRAM detection circuit is enabled
1 = VDDSRAM detection circuit is disabled
6:15
—
MOTOROLA
8-34
Reserved
CLOCKS AND POWER CONTROL
Revised 1 March 1999
MPC555
USER’S MANUAL
SECTION 9
EXTERNAL BUS INTERFACE
The MPC555 bus is a synchronous, burstable bus. Signals driven on this bus are
required to make the setup and hold time relative to the bus clock’s rising edge. The
bus has the ability to support multiple masters. The MPC555 architecture supports
byte, half-word, and word operands allowing access to 8-, 16-, and 32-bit data ports
through the use of synchronous cycles controlled by the size outputs (TSIZ0, TSIZ1).
For accesses to 16- and 8-bit ports, the slave must be controlled by the memory
controller.
9.1 Features
The external bus interface features are listed below.
• 32-bit address bus with transfer size indication (only 24 available on pins)
• 32-bit data bus
• Bus arbitration logic on-chip supports an external master
• Internal chip-select and wait state generation to support peripheral or static memory devices through the memory controller
• Supports various memory (SRAM, EEPROM) types: synchronous and asynchronous, burstable and non-burstable
• Supports non-wrap bursts
• Flash ROM programming support
• Compatible with PowerPC architecture
• Easy to interface to slave devices
• Bus is synchronous (all signals are referenced to rising edge of bus clock)
• Bus can operate at the same frequency as the MPC555 or half the frequency.
9.2 Bus Transfer Signals
The bus transfers information between the MPC555 and external memory of a peripheral device. External devices can accept or provide 8, 16, and 32 bits in parallel and
must follow the handshake protocol described in this section. The maximum number
of bits accepted or provided during a bus transfer is defined as the port width.
The MPC555 contains an address bus that specifies the address for the transfer and
a data bus that transfers the data. Control signals indicate the beginning and type of
the cycle, as well as the address space and size of the transfer. The selected device
then controls the length of the cycle with the signal(s) used to terminate the cycle. A
strobe signal for the address bus indicates the validity of the address and provides timing information for the data.
The MPC555 bus is synchronous. The bus and control input signals must be timed to
setup and hold times relative to the rising edge of the clock. Bus cycles can be completed in two clock cycles.
MPC555
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EXTERNAL BUS INTERFACE
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9-1
For all inputs, the MPC555 latches the level of the input during a sample window
around the rising edge of the clock signal. This window is illustrated in Figure 9-1,
where tsu and tho are the input setup and hold times, respectively. To ensure that an
input signal is recognized on a specific falling edge of the clock, that input must be stable during the sample window. If an input makes a transition during the window time
period, the level recognized by the MPC555 is not predictable; however, the MPC555
always resolves the latched level to either a logic high or low before using it. In addition
to meeting input setup and hold times for deterministic operation, all input signals must
obey the protocols described in this section.
tho
tsu
Clock
Signal
Sample
Window
Figure 9-1 Input Sample Window
9.3 Bus Control Signals
The MPC555 initiates a bus cycle by driving the address, size, address type, cycle
type, and read/write outputs. At the beginning of a bus cycle, TSIZ0 and TSIZ1 are
driven with the address type signals. TSIZ0 and TSIZ1 indicate the number of bytes
remaining to be transferred during an operand cycle (consisting of one or more bus
cycles). These signals are valid at the rising edge of the clock in which the transfer start
(TS) signal is asserted.
The read/write (RD/WR) signal determines the direction of the transfer during a bus
cycle. Driven at the beginning of a bus cycle, RD/WR is valid at the rising edge of the
clock in which TS is asserted. The logic level of RD/WR only changes when a write
cycle is preceded by a read cycle or vice versa. The signal may remain low for consecutive write cycles.
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USER’S MANUAL
32
1
1
2
4
1
ADDR[0:31]
RD/WR
BURST
TSIZ[0:1]
PTR
1
STS (BI)
1
BDIP
1
TS
1
RSV
1
1
32
1
1
1
1
1
1
1
Address
and
Transfer
Attributes
AT[0:3]
KR
CR
Transfer
Start
Reservation
Protocol
DATA[0:31]
Data
RETRY
BI (STS)
TA
TEA
Transfer
Cycle
Termination
BR
BG
Arbitration
BB
Figure 9-2 MPC555 Bus Signals
9.4 Bus Interface Signal Descriptions
Table 5-1 diatribes each signal in the bus interface unit. More detailed descriptions
can be found in subsequent subsections.
MPC555
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MOTOROLA
9-3
.
Table 9-1 MPC555 SIU Signals
Signal Name
Pins
Active
I/O
Description
Address and Transfer Attributes
ADDR[0:31]
Address bus
24
(8:31)
High
O
Specifies the physical address of the bus transaction.
I
Driven by an external bus master when it owns the external bus. Only for testing purposes.
O
Driven by the MPC555 along with the address when it
owns the external bus. Driven high indicates that a
read access is in progress. Driven low indicates that a
write access is in progress.
I
Driven by an external master when it owns the external bus. Driven high indicates that a read access is in
progress. Driven low indicates that a write access is in
progress.
O
Driven by the MPC555 along with the address when it
owns the external bus. Driven low indicates that a
burst transfer is in progress. Driven high indicates that
the current transfer is not a burst.
I
Driven by an external master when it owns the external bus. Driven low indicates that a burst transfer is in
progress. Driven high indicates that the current transfer is not a burst. The MPC555 does not support burst
accesses to internal slaves.
O
Driven by the MPC555 along with the address when it
owns the external bus. Specifies the data transfer size
for the transaction.
I
Driven by an external master when it owns the external bus. Specifies the data transfer size for the transaction.
O
Driven by the MPC555 along with the address when it
owns the external bus. Indicates additional information about the address on the current transaction.
I
Only for testing purposes.
O
Driven by the MPC555 along with the address when it
owns the external bus. Indicates additional information about the address on the current transaction.
I
Only for testing purposes.
O
Driven by the MPC555 along with the address when it
owns the external bus. Indicates additional information about the address on the current transaction.
RD/WR
1
HIgh
Read/write
BURST
1
Low
Burst transfer
TSIZ[0:1]
2
High
Transfer size
AT[0:3]
3
High
Address type
RSV
1
Low
Reservation transfer
PTR
1
High
Program trace
RETRY
MOTOROLA
9-4
1
I
Only for testing purposes.
I
In the case of regular transaction, this signal is driven
by the slave device to indicate that the MPC555 must
relinquish the ownership of the bus and retry the cycle.
O
When an external master owns the bus and the internal MPC555 bus initiates access to the external bus
at the same time, this signal is used to cause the external master to relinquish the bus for one clock to
solve the contention.
Low
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Revised 1 March 1999
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USER’S MANUAL
Table 9-1 MPC555 SIU Signals (Continued)
Signal Name
Pins
Active
I/O
Description
O
Driven by the MPC555 when it owns the external bus.
It is part of the burst protocol. When BDIP is asserted,
the second beat in front of the current one is requested by the master. This signal is negated prior to the
end of a burst to terminate the burst data phase early.
I
Driven by an external master when it owns the external bus. When BDIP is asserted, the second beat in
front of the current one is requested by the master.
This signal is negated prior to the end of a burst to terminate the burst data phase early. The MPC555 does
not support burst accesses to internal slaves.
BDIP
1
Low
Burst data in progress
Transfer Start
O
Driven by the MPC555 when it owns the external bus.
Indicates the start of a transaction on the external bus.
I
Driven by an external master when it owns the external bus. It indicates the start of a transaction on the
external bus or (in show cycle mode) signals the beginning of an internal transaction.
O
Driven by the MPC555 when it owns the external bus.
Indicates the start of a transaction on the external bus
or signals the beginning of an internal transaction in
show cycle mode.
TS
1
Low
Transfer start
STS
1
Low
Special transfer start
Reservation Protocol
I
Each PowerPC CPU has its own CR signal. Assertion
of CR instructs the bus master to clear its reservation;
some other master has touched its reserved space.
This is a pulsed signal.
I
In case of a bus cycle initiated by a STWCX instruction issued by the RCPU to a non-local bus on which
the storage reservation has been lost, this signal is
used by the non-local bus interface to backoff the cycle. Refer to 9.5.9 Storage Reservation for details.
CR
1
Low
Cancel reservation
KR
1
Kill reservation
MPC555
USER’S MANUAL
Low
EXTERNAL BUS INTERFACE
Revised 1 March 1999
MOTOROLA
9-5
Table 9-1 MPC555 SIU Signals (Continued)
Signal Name
Pins
Active
I/O
Description
Data
The data bus has the following byte lane assignments:
Data Byte
Byte Lane
DATA[0:7]
0
DATA[8:15]
1
DATA[16:23]
2
DATA[24:31]
3
DATA[0:31]
32
High
O
Data bus
Driven by the MPC555 when it owns the external bus
and it initiated a write transaction to a slave device.
For single beat transactions, the byte lanes not selected for the transfer by ADDR[30:31] and TSIZ[0:1] do
not supply valid data.
In addition, the MPC555 drives DATA[0:31] when an
external master owns the external bus and initiated a
read transaction to an internal slave module.
I
Driven by the slave in a read transaction. For single
beat transactions, the MPC555 does not sample byte
lanes that are not selected for the transfer by
ADDR[30:31] and TSIZ[0:1].
In addition, an external master that owns the bus and
initiated a write transaction to an internal slave module drives DATA[0:31].
Transfer Cycle Termination
I
Driven by the slave device to which the current transaction was addressed. Indicates that the slave has received the data on the write cycle or returned data on
the read cycle. If the transaction is a burst, TA should
be asserted for each one of the transaction beats.
O
Driven by the MPC555 when the slave device is controlled by the on-chip memory controller or when an
external master initiated a transaction to an internal
slave module.
I
Driven by the slave device to which the current transaction was addressed. Indicates that an error condition has occurred during the bus cycle.
O
Driven by the MPC555 when the internal bus monitor
detected an erroneous bus condition, or when an external master initiated a transaction to an internal
slave module and an internal error was detected.
I
Driven by the slave device to which the current transaction was addressed. Indicates that the current slave
does not support burst mode.
O
Driven by the MPC555 when the slave device is controlled by the on-chip memory controller. the MPC555
also asserts BI for any external master burst access
to internal MPC555 memory space.
TA
1
LOW
Transfer acknowledge
TEA
Transfer error
acknowledge
1
Low
BI
1
Burst inhibit
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USER’S MANUAL
Table 9-1 MPC555 SIU Signals (Continued)
Signal Name
Pins
Active
I/O
Description
ARBITRATION
BR
1
I
When the internal arbiter is enabled, BR assertion indicates that an external master is requesting the bus.
O
Driven by the MPC555 when the internal arbiter is disabled and the chip is not parked.
Low
Bus request
O
BG
1
Low
Bus grant
When the internal arbiter is enabled, the MPC555 asserts this signal to indicate that an external master
may assume ownership of the bus and begin a bus
transaction. The BG signal should be qualified by the
master requesting the bus in order to ensure it is the
bus owner:
Qualified bus grant = BG & ~ BB
I
When the internal arbiter is disabled, BG is sampled
and properly qualified by the MPC555 when an external bus transaction is to be executed by the chip.
When the internal arbiter is enabled, the MPC555 asserts this signal to indicate that it is the current owner
of the bus.
O
BB
1
Low
Bus busy
I
When the internal arbiter is disabled, the MPC555 asserts this signal after the external arbiter has granted
the ownership of the bus to the chip and it is ready to
start the transaction.
When the internal arbiter is enabled, the MPC555
samples this signal to get indication of when the external master ended its bus tenure (BB negated).
When the internal arbiter is disabled, the BB is sampled to properly qualify the BG line when an external
bus transaction is to be executed by the chip.
9.5 Bus Operations
This section provides a functional description of the system bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the
error conditions, bus arbitration, and reset operation.
The MPC555 generates a system clock output (CLKOUT). This output sets the frequency of operation for the bus interface directly. Internally, the MPC555 uses a
phase-lock loop (PLL) circuit to generate a master clock for all of the CPU circuitry
(including the bus interface) which is phase-locked to the CLKOUT output signal.
All signals for the MPC555 bus interface are specified with respect to the rising edge
of the external CLKOUT and are guaranteed to be sampled as inputs or changed as
outputs with respect to that edge. Since the same clock edge is referenced for driving
or sampling the bus signals, the possibility of clock skew could exist between various
modules in a system due to routing or the use of multiple clock lines. It is the responsibility of the system to handle any such clock skew problems that could occur.
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9-7
9.5.1 Basic Transfer Protocol
The basic transfer protocol defines the sequence of actions that must occur on the
MPC555 bus to perform a complete bus transaction. A simplified scheme of the basic
transfer protocol is illustrated in Figure 9-3.
Arbitration
Address Transfer
Data Transfer
Termination
Figure 9-3 Basic Transfer Protocol
The basic transfer protocol provides for an arbitration phase and an address and data
transfer phase. The address phase specifies the address for the transaction and the
transfer attributes that describe the transaction. The data phase performs the transfer
of data (if any is to be transferred). The data phase may transfer a single beat of data
(4 bytes or less) for nonburst operations, a 4-beat burst of data (4 x 4 bytes), an 8-beat
burst of data (8 x 2 bytes) or a 16-beat burst of data (16 x 1 bytes).
9.5.2 Single Beat Transfer
During the data transfer phase, the data is transferred from master to slave (in write
cycles) or from slave to master (on read cycles).
During a write cycle, the master drives the data as soon as it can, but never earlier than
the cycle following the address transfer phase. The master has to take into consideration the “one dead clock cycle” switching between drivers to avoid electrical
contentions. The master can stop driving the data bus as soon as it samples the TA
line asserted on the rising edge of the CLKOUT.
During a read cycle, the master accepts the data bus contents as valid at the rising
edge of the CLKOUT in which the TA signal is sampled/asserted.
9.5.2.1 Single Beat Read Flow
The basic read cycle begins with a bus arbitration, followed by the address transfer,
then the data transfer. The handshakes are illustrated in the following flow and timing
diagrams as applicable to the fixed transaction protocol.
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USER’S MANUAL
Master
Slave
Request bus (BR)
Receive bus grant (BG) from arbiter
Assert bus busy (BB) if no other master is driving bus
Assert transfer start (TS)
Drive address and attributes
Receive address
Return data
Assert transfer acknowledge (TA)
Receive data
Figure 9-4 Basic Flow Diagram of a Single Beat Read Cycle
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MOTOROLA
9-9
CLKOUT
BR
BG
Receive bus grant and bus busy negated
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
O
Data is valid
Figure 9-5 Single Beat Read Cycle–Basic Timing–Zero Wait States
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USER’S MANUAL
CLKOUT
BR
BG
Receive bus grant and bus busy negated
O
O
assert BB, drive address and assert TS
BB
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
Wait state
O
Data is valid
Figure 9-6 Single Beat Read Cycle–Basic Timing–One Wait State
9.5.2.2 Single Beat Write Flow
The basic write cycle begins with a bus arbitration, followed by the address transfer,
then the data transfer. The handshakes are illustrated in the following flow and timing
diagrams as applicable to the fixed transaction protocol.
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9-11
Master
Slave
Request bus (BR)
Receive bus grant (BG) from arbiter
Assert bus busy (BB) if no other master is driving bus
Assert transfer start (TS)
Drive address and attributes
Drive data
Assert transfer acknowledge (TA)
Interrupt data driving
Figure 9-7 Basic Flow Diagram of a Single Beat Write Cycle
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USER’S MANUAL
CLKOUT
BR
BG
Receive bus grant and bus busy negated
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
O
Data is sampled
Figure 9-8 Single Beat Basic Write Cycle Timing, Zero Wait States
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9-13
CLKOUT
BR
Receive bus grant and bus busy negated
BG
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
Wait state
O
Data is sampled
Figure 9-9 Single Beat Basic Write Cycle Timing, One Wait State
9.5.2.3 Single Beat Flow with Small Port Size
The general case of single beat transfers assumes that the external memory has a 32bit port size. The MPC555 provides an effective mechanism for interfacing with 16-bit
and 8-bit port size memories, allowing transfers to these devices when they are controlled by the internal memory controller.
In this case, the MPC555 attempts to initiate a transfer as in the normal case. If the
bus interface receives a small port size (16 or 8 bits) indication before the transfer
acknowledge to the first beat (through the internal memory controller), the MCU initiates successive transactions until the completion of the data transfer. Note that all the
transactions initiated to complete the data transfer are considered to be part of an
atomic transaction, so the MCU does not allow other unrelated master accesses or
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USER’S MANUAL
bus arbitration to intervene between the transfers. If any of the transactions except the
first is re-tried during an access to a small port, then an exception is generated to the
RCPU.
CLKOUT
BR
BG
BB
ADDR[0:1]
ADDR + 2
ADDR
RD/WR
TSIZ[0:1]
10
00
BURST, BDIP
TS
STS
Data
ABCDEFGH
EFGHEFGH
TA
Figure 9-10 Single Beat 32-Bit Data
Write Cycle Timing, 16 Bit-Port Size
9.5.3 Burst Transfer
The MPC555 uses non-wrapping burst transfers to access operands of up to 16 bytes
(four words). A non-wrapping burst access stops accessing the external device when
the word address is modulo four. The MPC555 begins the access by supplying a starting address that points to one of the words and requiring the memory device to
sequentially drive or sample each word on the data bus. The selected slave device
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MOTOROLA
9-15
must internally increment ADDR28 and ADDR29 (and ADDR30 in the case of a 16-bit
port slave device, and also ADDR31 in the case of an 8-bit port slave device) of the
supplied address for each transfer, causing the address to reach a four-word boundary, and then stop. The address and transfer attributes supplied by the MPC555
remain stable during the transfers. The selected device terminates each transfer by
driving or sampling the word on the data bus and asserting TA.
The MPC555 also supports burst-inhibited transfers for slave devices that are unable
to support bursting. For this type of bus cycle, the selected slave device supplies or
samples the first word the MPC555 points to and asserts the burst-inhibit signal with
TA for the first transfer of the burst access. The MPC555 responds by terminating the
burst and accessing the remainder of the 16-byte block. These remaining accesses
use up to three read/write bus cycles (each one for a word) in the case of a 32-bit port
width slave, up to seven read/write bus cycles in the case of a 16-bit port width slave,
or up to fifteen read/write bus cycles in the case of a 8-bit port width slave.
The general case of burst transfers assumes that the external memory has a 32-bit
port size. The MPC555 provides an effective mechanism for interfacing with 16-bit port
size memories and 8-bit port size memories allowing bursts transfers to these devices
when they are controlled by the internal memory controller.
In this case, the MPC555 attempts to initiate a burst transfer as in the normal case. If
the memory controller signals to the bus interface that the external device has a small
port size (8 or 16 bits), and if the burst is accepted, the bus interface completes a burst
of 8 or 16 beats.
Each of the data beats of the burst transfers effectively only one or two bytes. Note
that this burst of 8 or 16 beats is considered an atomic transaction, so the MPC555
does not allow other unrelated master accesses or bus arbitration to intervene
between the transfers.
9.5.4 Burst Mechanism
In addition to the standard bus signals, the MPC555 burst mechanism uses the following signals:
• The BURST signal indicates that the cycle is a burst cycle.
• The burst data in progress (BDIP) signal indicates the duration of the burst data.
• The burst inhibit (BI) signal indicates whether the slave is burstable.
At the start of the burst transfer, the master drives the address, the address attributes,
and the BURST signal to indicate that a burst transfer is being initiated, and asserts
TS. If the slave is burstable, it negates the burst-inhibit (BI) signal. If the slave cannot
burst, it asserts BI.
During the data phase of a burst write cycle the master drives the data. It also asserts
BDIP if it intends to drive the data beat following the current data beat. When the slave
has received the data, it asserts the signal transfer acknowledge to indicate to the
master that it is ready for the next data transfer. The master again drives the next data
and asserts or negates the BDIP signal. If the master does not intend to drive another
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USER’S MANUAL
data beat following the current one, it negates BDIP to indicate to the slave that the
next data beat transfer is the last data of the burst write transfer.
BDIP has two basic timings: normal and late (see Figure 9-13 and Figure 9-14). In the
late timing mode, assertion of BDIP is delayed by the number of wait states in the first
data beat. This implies that for zero-wait-state cycles, BDIP assertion time is identical
in normal and late modes. Cycles with late BDIP generation can occur only during
cycles for which the memory controller generates TA internally. Refer to SECTION 10
MEMORY CONTROLLER for more information.
In the MPC555, no internal master initiates write bursts. The MPC555 is designed to
perform this kind of transaction in order to support an external master that is using the
memory controller services. Refer to 10.7 Memory Controller External Master
Support.
During the data phase of a burst read cycle, the master receives data from the
addressed slave. If the master needs more than one data beat, it asserts BDIP. Upon
receiving the second-to-last data beat, the master negates BDIP. The slave stops driving new data after it receives the negation of the BDIP signal at the rising edge of the
clock.
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9-17
Master
Slave
Request Bus (BR)
Receive bus grant (BG) from arbiter
Assert Bus Busy (BB) if No Other Master is Driving
Assert Transfer Start (TS)
Drive Address and Attributes
Drive BURST Asserted
Receive Address
ADDR[28:29] mod 4 = ?
=0
Assert BDIP
Return Data
Assert Transfer Acknowledge (TA)
Receive Data
BDIP Asserted
=1
No
Drive Last Data
& Assert TA
Yes
Return Data
Assert Transfer Acknowledge (TA)
Assert BDIP
Receive Data
BDIP Asserted
=2
Drive Last Data
& Assert TA
No
Yes
Assert BDIP
Return Data
Assert Transfer Acknowledge (TA)
Receive Data
BDIP Asserted
No
Drive Last Data
& Assert TA
=3
Yes
Negate Burst Data in Progress (BDIP)
Return Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Receive Sata
No
Drive Last Data
& Assert TA
Yes
Figure 9-11 Basic Flow Diagram Of A Burst Read Cycle
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USER’S MANUAL
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Last Beat
O
Expects Another Data
BDIP
O
O
O
Data
TA
O
O
Data
is Valid
O
Data
is Valid
O
Data
is Valid
Data
is Valid
Figure 9-12 Burst-Read Cycle–32-Bit Port Size–Zero Wait State
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9-19
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Last Beat
O
Expects Another Data
BDIP
Normal
Late
O
O
O
Data
TA
O
Wait State
O
Data
is Valid
O
Data
is Valid
O
Data
is Valid
Data
is Valid
Figure 9-13 Burst-Read Cycle–32-Bit Port Size–One Wait State
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USER’S MANUAL
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Last Beat
BDIP
Normal or Late
O
Expects Another Data
O
O
O
O
O
Data
TA
Data
is Valid
O
Data
is Valid
O
Data
is Valid
Data
is Valid
Wait State
Figure 9-14 Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats
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9-21
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
BDIP
Data[0:15]
TA
Figure 9-15 Burst-Read Cycle, 16-Bit Port Size
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USER’S MANUAL
External Master
Slave
Request Bus (BR)
Receive Bus Grant (BG) from Arbiter
Assert Bus Busy (BB) if No Other Master is Driving
Assert Transfer Start (TS)
Drive Address and Attributes
Drive BURST Asserted
MTS Asserted (from MPC555)
Drive data
Receive Address
ADDR[28:29] mod 4 = ?
=0
Assert BDIP
Sample Data
Assert Transfer Acknowledge (TA)
Drive Data
BDIP Asserted
=1
No
Don’t Sample
Next Data
Yes
Sample Data
Assert Transfer Acknowledge (TA)
Assert BDIP
Drive Data
BDIP Asserted
=2
No
Don’t Sample
Next Data
No
Don’t Sample
Next Data
Yes
Assert BDIP
Sample Data
Assert Transfer Acknowledge (TA)
Drive Data
BDIP Asserted
=3
Yes
Negate Burst Data in Progress (BDIP)
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Stop Driving Data
No
Don’t Sample
Next Data
Yes
Figure 9-16 Basic Flow Diagram of a Burst Write Cycle
MPC555
USER’S MANUAL
EXTERNAL BUS INTERFACE
Revised 1 March 1999
MOTOROLA
9-23
CLKOUT
BR
(from external
master)
BG
(from external
master)
BB
(from external
master)
ADDR[0:31]
ADDR[28:29] = 00
RD/WR
(from external
master)
TSIZ[0:1]
00
BURST
(from external
master)
TS
(from external
master)
MTS
Last Beat
O
Will Drive Another Data
BDIP
(from external
master)
O
O
O
Data
TA
O
O
O
O
Data
Data
Data
Data
is Sampled is Sampled is Sampled is Sampled
Figure 9-17 Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
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USER’S MANUAL
CLKOUT
BR
BG
BB
ADDR[0:27]
ADDR[28:29]
0
1
2
3
ADDR[30:31]
RD/WR
TSIZ[0:1]
00
BURST*
TS
BDIP*
Data
TA
BI
* BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst,
but the USIU splits it into a sequence of normal cycles.
Figure 9-18 Burst-Inhibit Cycle, 32-Bit Port Size (Emulated Burst)
MPC555
USER’S MANUAL
EXTERNAL BUS INTERFACE
Revised 1 March 1999
MOTOROLA
9-25
CLKOUT
BR
BG
BB
ADDR(0:29)
n (n modulo 4 = 1)
ADDR[30:31]
RD/WR
TSIZ[0:1]
00
BURST
TS
Expects Another Data
BDIP
O
O
Data
TA
BI
Figure 9-19 Non-Wrap Burst with Three Beats
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EXTERNAL BUS INTERFACE
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MPC555
USER’S MANUAL
CLKOUT
BR
BG
BB
ADDR[0:29]
ADDR[30:31]
n (n modulo 4 = 3)
00
RD/WR
TSIZ[0:1]
00
BURST
TS
Is Never Asserted
BDIP
First and Last Beat
Data
TA
O
DATA
is Sampled
Figure 9-20 Non-Wrap Burst with One Data Beat
MPC555
USER’S MANUAL
EXTERNAL BUS INTERFACE
Revised 1 March 1999
MOTOROLA
9-27
9.5.5 Alignment and Packaging of Transfers
The MPC555 external bus requires natural address alignment:
• Byte accesses allow any address alignment
• Half-word accesses require address bit 31 to equal zero
• Word accesses require address bits 30 – 31 to equal zero
• Burst accesses require address bits 30 – 31 to equal zero
The MPC555 performs operand transfers through its 32-bit data port. If the transfer is
controlled by the internal memory controller, the MPC555 can support 8- and 16-bit
data port sizes.
The bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 32-bit port must reside on DATA[0:31], a 16-bit port must
reside on DATA[0:15], and an 8-bit port must reside on DATA[0:7]. The MPC555
always tries to transfer the maximum amount of data on all bus cycles. For a word
operation, it always assumes that the port is 32 bits wide when beginning the bus
cycle.
In Figure 9-21, Figure 9-22, Table 9-2, and Table 9-3, the following conventions are
used:
• OP0 is the most-significant byte of a word operand and OP3 is the least-significant byte.
• The two bytes of a half-word operand are either OP0 (most-significant) and OP1
or OP2 (most-significant) and OP3, depending on the address of the access.
• The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending
on the address of the access.
0
31
OP0
OP1
OP0
OP1
OP2
OP3
OP2
OP3
Word
Half-word
OP0
OP1
Byte
OP2
OP3
Figure 9-21 Internal Operand Representation
Figure 9-22 illustrates the device connections on the data bus.
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MPC555
USER’S MANUAL
0
31
OP0
OP1
DATA[0:7]
OP2
DATA[8:15]
OP0
OP1
OP0
OP1
OP2
OP3
Interface
Output
Register
OP3
DATA[16:23]
OP2
DATA[24:31]
OP3
32-bit Port Size
16-bit Port Size
OP0
OP1
8-bit Port Size
OP2
OP3
Figure 9-22 Interface To Different Port Size Devices
Table 9-2 lists the bytes required on the data bus for read cycles.
MPC555
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EXTERNAL BUS INTERFACE
Revised 1 March 1999
MOTOROLA
9-29
Table 9-2 Data Bus Requirements For Read Cycles
Transfer
Size
TSIZE
[0:1]
Byte
Half-word
Word
Address
32-bit Port Size
16-bit Port Size
8-bit
Port
Size
ADDR
[30:31]
DATA
[0:7]
DATA
[8:15]
DATA
[16:23]
DATA
[24:31]
DATA
[0:7]
DATA
[8:15]
DATA
[0:7]
01
00
OP0
—
—
—
OP0
—
OP0
01
01
—
OP1
—
—
—
OP1
OP1
01
10
—
—
OP2
—
OP2
—
OP2
01
11
—
—
—
OP3
—
OP3
OP3
10
00
OP0
OP1
—
—
OP0
OP1
OP0
10
10
—
—
OP2
OP3
OP2
OP3
OP2
00
00
OP0
OP1
OP2
OP3
OP0
OP1
OP0
NOTE: “—” denotes a byte not required during that read cycle.
Table 9-3 lists the patterns of the data transfer for write cycles when the MPC555 initiates an access.
Table 9-3 Data Bus Contents for Write Cycles
Transfer
Size
Byte
Half-word
Word
Address
External Data Bus Pattern
TSIZE[0:1]
ADDR
[30:31]
DATA
[0:7]
DATA
[8:15]
DATA
[16:23]
DATA
[24:31]
01
00
OP0
—
—
—
01
01
OP1
OP1
—
—
01
10
OP2
—
OP2
—
01
11
OP3
OP3
—
OP3
10
00
OP0
OP1
—
—
10
10
OP2
OP3
OP2
OP3
00
00
OP0
OP1
OP2
OP3
NOTE: “—” denotes a byte not driven during that write cycle.
9.5.6 Arbitration Phase
The external bus design provides for a single bus master at any one time, either the
MPC555 or an external device. One or more of the external devices on the bus can
have the capability of becoming bus master for the external bus. Bus arbitration may
be handled either by an external central bus arbiter or by the internal on-chip arbiter.
In the latter case, the system is optimized for one external bus master besides the
MPC555. The arbitration configuration (external or internal) is set at system reset.
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. The device that needs the bus asserts BR. The device then waits for the arbiter
to assert BG. In addition, the new master must look at BB to ensure that no other master is driving the bus before it can assert BB to assume ownership of the bus. Any time
the arbiter has taken the bus grant away from the master and the master wants to execute a new cycle, the master must re-arbitrate before a new cycle can be executed.
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USER’S MANUAL
The MPC555, however, guarantees data coherency for access to a small port size and
for decomposed bursts. This means that the MPC555 will not release the bus before
the completion of the transactions that are considered atomic. Figure 9-23 describes
the basic protocol for bus arbitration.
Requesting Device
Arbiter
Request the Bus
1. Assert BR
GRANT Bus arbitration
1.Assert BG
Acknowledge Bus Mastership
1. Wait for BB to be negated.
2. Assert BB to becom enext master
Terminate Arbitration
3. Negate BR
Operate as bus Master
1. Negate BG (or keep asserted to park
bus master
1. Perform data transfer
Release Bus Mastership
1. Negate BB
Figure 9-23 Bus Arbitration Flowchart
9.5.6.1 Bus Request
The potential bus master asserts BR to request bus mastership. BR should be negated
as soon as the bus is granted, the bus is not busy, and the new master can drive the
bus. If more requests are pending, the master can keep asserting its bus request as
long as needed. When configured for external central arbitration, the MPC555 drives
this signal when it requires bus mastership. When the internal on-chip arbiter is used,
this signal is an input to the internal arbiter and should be driven by the external bus
master.
9.5.6.2 Bus Grant
The arbiter asserts BG to indicate that the bus is granted to the requesting device. This
signal can be negated following the negation of BR or kept asserted for the current
master to park the bus.
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EXTERNAL BUS INTERFACE
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MOTOROLA
9-31
When configured for external central arbitration, BG is an input signal to the MPC555
from the external arbiter. When the internal on-chip arbiter is used, this signal is an output from the internal arbiter to the external bus master.
9.5.6.3 Bus Busy
BB assertion indicates that the current bus master is using the bus. New masters
should not begin transfer until this signal is negated. The bus owner should not relinquish or negate this signal until the transfer is complete. To avoid contention on the
BB line, the master should three-state this signal when it gets a logical one value. This
requires the connection of an external pull-up resistor to ensure that a master that
acquires the bus is able to recognize the BB line negated, regardless of how many
cycles have passed since the previous master relinquished the bus. Refer to Figure
9-24.
Master
External Bus
TS
MPC555
BB
Slave 2
Figure 9-24 Masters Signals Basic Connection
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USER’S MANUAL
CLKOUT
BR0
BG0
BR1
BG1
BB
ADDR & Attr.
TS
TA
Master 0
“Turns On” and
Drives Signals
Master 0
Master 1
Negates BB
“Turns On” and
and “Turns Off” Drives Signals
(Three-state Controls)
Figure 9-25 Bus Arbitration Timing Diagram
9.5.6.4 Internal Bus Arbiter
The MPC555 can be configured at system reset to use the internal bus arbiter. In this
case, the MPC555 will be parked on the bus. The parking feature allows the MPC555
to skip the bus request phase, and if BB is negated, assert BB and initiate the transaction without waiting for BG from the arbiter.
The priority of the external device relative to the internal MPC555 bus masters is programmed in the SIU module configuration register. If the external device requests the
bus and the MPC555 does not require it, or if the external device has higher priority
than the current internal bus master, the MPC555 grants the bus to the external
device.
Table 9-4 describes the priority mechanism used by the internal arbiter.
MPC555
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EXTERNAL BUS INTERFACE
Revised 1 March 1999
MOTOROLA
9-33
Table 9-4 Priority Between Internal and External Masters over External Bus1
Type
Direction
Priority
Parked access2
Internal → external
0
Instruction access
Internal → external
3
Data access
Internal → external
4
External access
external → external/internal
EARP3 (could be programmed to 0 – 7)
NOTES:
1. External master will be granted external bus ownership if EARP is greater than the internal access priority.
2. Parked access is instruction or data access from the RCPU which is initiated on the internal bus without
requesting it first in order to improve performance.
3. Refer to 6.13.1.1 SIU Module Configuration Register.
Figure 9-26 illustrates the internal finite-state machine that implements the arbiter
protocol.
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USER’S MANUAL
External
Owner
BG = 0
BB = t.s
1,
B
R
=1
BR
=
0
External Master
Requests Bus
MPC555 Internal Master With Higher
Priority than the External Device
Requires the Bus
BB
=
BR = 1
Ext Master
Release Bus
BB = 0
IDLE
MPC555 Bus
Wait
BG = 1
BB = t.s
BG = 1
BB = t.s
MCU Needs
the Bus
BB = 1
MPC555 No Longer
Needs the Bus
MPC555
Owner
BR = 0
BG = 1
BB = 0
External Device With Higher
Priority than the Current Internal
Bus Master Requests the Bus
MPC555 Still Needs
the Bus
Figure 9-26 Internal Bus Arbitration State Machine
9.5.7 Address Transfer Phase Signals
Address transfer phase signals include the following:
• Transfer start
• Address bus
• Transfer attributes
Transfer attributes signals include RD/WR, BURST, TSIZ[0:1], AT[0:3], STS, and
BDIP. With the exception of the BDIP, these signals are available at the same time as
the address bus.
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EXTERNAL BUS INTERFACE
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MOTOROLA
9-35
9.5.7.1 Transfer Start
This signal (TS) indicates the beginning of a transaction on the bus addressing a slave
device. This signal should be asserted by a master only after the ownership of the bus
was granted by the arbitration protocol. This signal is asserted for the first cycle of the
transaction only and is negated in successive clock cycles until the end of the transaction. The master should three-state this signal when it relinquishes the bus to avoid
contention between two or more masters in this line. This situation indicates that an
external pull-up resistor should be connected to the TS signal to avoid having a slave
recognize this signal as asserted when no master drives it. Refer to Figure 9-24.
9.5.7.2 Address Bus
The address bus consists of 32 bits, with ADDR0 the most significant bit and ADDR31
the least significant bit. The bus is byte-addressable, so each address can address
one or more bytes. The address and its attributes are driven on the bus with the transfer start signal and kept valid until the bus master receives the transfer acknowledge
signal from the slave. To distinguish the individual byte, the slave device must observe
the TSIZ signals.
9.5.7.3 Read/Write
A high value on the RD/WR line indicates a read access. A low value indicates a write
access.
9.5.7.4 Burst Indicator
BURST is driven by the bus master at the beginning of the bus cycle along with the
address to indicate that the transfer is a burst transfer.
The MPC555 supports a non-wrapping, four-beat maximum, critical word first burst
type. The maximum burst size is 16 bytes. For a 32-bit port, the burst includes four
beats. For a 16-bit port, the burst includes 8 beats. For an 8-bit port, the burst includes
16 beats at most. Note that 8- and 16-bit ports must be controlled by the memory
controller.
The actual size of the burst is determined by the address of the starting word of the
burst. Refer to Table 9-5 and Table 9-6.
Table 9-5 Burst Length and Order
Starting
Address
ADDR[28:29]
Burst Order (Assuming
32-bit Port Size)
Burst Length in
Words (Beats)
Burst Length
in Bytes
00
word 0 → word 1 →
word 2 → word 3
4
16
01
word 1 → word 2 → word 3
3
12
10
word 2 → word 3
2
8
11
word 3
1
4
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Comments
BDIP never asserted
MPC555
USER’S MANUAL
9.5.7.5 Transfer Size
The transfer size signals (TSIZ[0:1]) indicate the size of the requested data transfer.
During each transfer, the TSIZ signals indicate how many bytes are remaining to be
transferred by the transaction. The TSIZ signals can be used with BURST and
ADDR[30:31] to determine which byte lanes of the data bus are involved in the transfer. For nonburst transfers, the TSIZ signals specify the number of bytes starting from
the byte location addressed by ADDR[30:31]. In burst transfers, the value of TSIZ is
always 00.
Table 9-6 BURST/TSIZE Encoding
BURST
TSIZ(0:1)
Transfer Size
Negated
01
Byte
Negated
10
Half-word
Negated
11
x
Negated
00
Word
Asserted
00
Burst (16 bytes)
9.5.7.6 Address Types
The address type (AT[0:3]), program trace (PTR), and reservation transfer (RSV) signals are outputs that indicate one of 16 address types. These types are designated as
either a normal or alternate master cycle, user or supervisor, and instruction or data
type. The address type signals are valid at the rising edge of the clock in which the
special transfer start (STS) signal is asserted.
A special use of the PTR and RSV signals is for the reservation protocol described in
9.5.9 Storage Reservation. Refer to 9.5.13 Show Cycle Transactions for information on show cycles.
Table 9-7 summarizes the pins used to define the address type. Table 9-8 lists all the
definitions achieved by combining these pins.
Table 9-7 Address Type Pins
Pin
MPC555
USER’S MANUAL
Function
STS
0 = Special transfer
1 = Normal transfer
TS
0 = Start of transfer
1 = No transfer
AT0
Must equal zero on MPC555
AT1
0 = Supervisor mode
1 = User mode
AT2
0 = Instruction
1 = Data
AT3
Reservation/Program Trace
PTR
0 = Program trace
1 = No program trace
RSV
0 = Reservation data
1 = No reservation
EXTERNAL BUS INTERFACE
Revised 1 March 1999
MOTOROLA
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:
Table 9-8 Address Types Definition
STS
TS
AT0
AT1
AT2
AT3
PTR
RSV
1
x
x
x
x
x
1
1
No transfer
0
0
1
RCPU, normal instruction, program trace, supervisor mode
1
1
1
RCPU, normal instruction, supervisor mode
0
1
0
RCPU, reservation data, supervisor mode
1
1
1
RCPU, normal data, supervisor mode
0
0
1
RCPU, normal instruction, program trace, user mode
1
1
1
RCPU, normal instruction, user mode
0
1
0
RCPU, reservation data, user mode
1
1
1
RCPU, normal data, user mode
?
1
1
Reserved
0
0
1
RCPU, show cycle address instruction, program trace, supervisor mode
1
1
1
RCPU, show cycle address instruction, supervisor mode
0
1
0
RCPU, reservation show cycle data, supervisor mode
1
1
1
RCPU, show cycle data, supervisor mode
0
0
1
RCPU, show cycle address instruction, program trace, user
mode
1
1
1
RCPU, show cycle address instruction, user mode
0
1
0
RCPU, reservation show cycle data, user mode
1
1
1
RCPU, show cycle data, user mode
?
1
1
Reserved
0
0
1
01
0
0
1
1
1
?
?
0
0
0
1
1
0
0
1
1
1
?
?
Address Space Definitions
NOTES:
1. Cases in which both TS and STS are asserted indicate normal cycles with the show cycle attribute.
9.5.7.7 Burst Data in Progress
This signal is sent from the master to the slave to indicate that there is a data beat following the current data beat. The master uses this signal to give the slave advance
warning of the remaining data in the burst. BDIP can also be used to terminate the
burst cycle early. Refer to 9.5.3 Burst Transfer and 9.5.4 Burst Mechanism for more
information.
9.5.8 Termination Signals
The EBI uses three termination signals:
• Transfer acknowledge (TA)
• Burst inhibit (BI)
• Transfer error acknowledge (TEA)
9.5.8.1 Transfer Acknowledge
Transfer acknowledge indicates normal completion of the bus transfer. During a burst
cycle, the slave asserts this signal with every data beat returned or accepted.
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USER’S MANUAL
9.5.8.2 Burst Inhibit
A slave sends the BI signal to the master to indicate that the addressed device does
not have burst capability. If this signal is asserted, the master must transfer in multiple
cycles and increment the address for the slave to complete the burst transfer. For a
system that does not use the burst mode at all, this signal can be tied low permanently.
9.5.8.3 Transfer Error Acknowledge
The TEA signal terminates a bus cycle under one or more bus error conditions. The
current bus cycle must be aborted. This signal overrides any other cycle termination
signals, such as transfer acknowledge.
9.5.8.4 Termination Signals Protocol
The transfer protocol was defined to avoid electrical contention on lines that can be
driven by various sources. To this end, a slave must not drive signals associated with
the data transfer until the address phase is completed and it recognizes the address
as its own. The slave must disconnect from signals immediately after it has acknowledged the cycle and no later than the termination of the next address phase cycle. This
means that the termination signals must be connected to power through a pull-up
resistor to avoid the situation in which a master samples an undefined value in any of
these signals when no real slave is addressed.
Refer to Figure 9-27 and Figure 9-28.
Slave 1
External Bus
MCU
Acknowledge
Signals
Slave 2
Figure 9-27 Termination Signals Protocol Basic Connection
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Revised 1 March 1999
MOTOROLA
9-39
CLKOUT
ADDR[0:31]
Slave 1
Slave 2
RD/WR
TSIZ[0:1]
TS
Data
TA, BI, TEA
Slave 1
Slave 1
Slave 2
Slave 2
allowed to drive
negates acknowledge
allowed to drive
negates acknowledge
acknowledge signals signals and turns off acknowledge signals signals and turns off
Figure 9-28 Termination Signals Protocol Timing Diagram
9.5.9 Storage Reservation
The MPC555 storage reservation protocol supports a multi-level bus structure. For
each local bus, storage reservation is handled by the local reservation logic.
The protocol tries to optimize reservation cancellation such that a PowerPC processor
is notified of storage reservation loss on a remote bus only when it has issued a stwcx
cycle to that address. That is, the reservation loss indication comes as part of the
stwcx cycle. This method avoids the need to have very fast storage reservation loss
indication signals routed from every remote bus to every PowerPC master.
The storage reservation protocol makes the following assumptions:
• Each processor has, at most, one reservation flag
• lwarx sets the reservation flag
• lwarx by the same processor clears the reservation flag related to a previous
lwarx instruction and again sets the reservation flag
• stwcx by the same processor clears the reservation flag
• Store by the same processor does not clear the reservation flag
• Some other processor (or other mechanism) store to the same address as an existing reservation clears the reservation flag
• In case the storage reservation is lost, it is guaranteed that stwcx will not modify
the storage
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USER’S MANUAL
The reservation protocol for a single-level (local) bus is illustrated in Figure 9-29. The
protocol assumes that an external logic on the bus carries out the following functions:
• Snoops accesses to all local bus slaves
• Holds one reservation for each local master capable of storage reservations
• Sets the reservation when that master issues a load and reserve request
• Clears the reservation when some other master issues a store to the reservation
address
MPC555
External Bus
External Bus
Interface
Master
Bus
lwarx
S
Q
R
Enable
external stwcx access
AT[0:3], RSV, R/W, TS
ADDR[0:29]
CR
Reservation
Logic
CR
CLKOUT
Figure 9-29 Reservation On Local Bus
The MPC555 samples the CR line at the rising edge of CLKOUT. When this signal is
asserted, the reservation flag is reset.
The EBI samples the logical value of the reservation flag prior to externally starting a
bus cycle initiated by the RCPU stwcx instruction. If the reservation flag is set, the EBI
begins with the bus cycle. If the reservation flag is reset, no bus cycle is initiated externally, and this situation is reported to the RCPU.
The reservation protocol for a multi-level (local) bus is illustrated in Figure 9-30. The
system describes the situation in which the reserved location is sited in the remote
bus.
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MOTOROLA
9-41
External Bus (Local Bus)
External Bus
Interface
AT[0:3], RSV, R/W, TS
MPC555
ADDR[0:29]
Local Master Accesseses with
lwarx to Remove Bus Address
KR
Q
S
Buses
Interface
R
A Master in the Remote Bus Write
to the Reserved Location
Remote Bus
Figure 9-30 Reservation On Multilevel Bus Hierarchy
In this case, the bus interface block implements a reservation flag for the local bus
master. The reservation flag is set by the bus interface when a load with reservation is
issued by the local bus master and the reservation address is located on the remote
bus. The flag is reset when an alternative master on the remote bus accesses the
same location in a write cycle. If the MPC555 begins a memory cycle to the previously
reserved address (located in the remote bus) as a result of an stwcx instruction, the
following two cases can occur:
• If the reservation flag is set, the buses interface acknowledges the cycle in a normal way
• If the reservation flag is reset, the bus interface should assert the KR. However,
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USER’S MANUAL
the bus interface should not perform the remote bus write-access or abort it if the
remote bus supports aborted cycles. In this case the failure of the stwcx instruction is reported to the RCPU.
9.5.10 Bus Exception Control Cycles
The MPC555 bus architecture requires assertion of TA from an external device to signal that the bus cycle is complete. TA is not asserted in the following cases:
• The external device does not respond
• Various other application-dependent errors occur
External circuitry can provide TEA when no device responds by asserting TA within an
appropriate period of time after the MPC555 initiates the bus cycle (it can be the internal bus monitor). This allows the cycle to terminate and the processor to enter
exception-processing for the error condition (each one of the internal masters causes
an internal interrupt under this situation). To properly control termination of a bus cycle
for a bus error, TEA must be asserted at the same time or before TA is asserted. TEA
should be negated before the second rising edge after it was sampled as asserted to
avoid the detection of an error for the next initiated bus cycle. TEA is an open drain pin
that allows the “wired-or” of any different sources of error generation.
9.5.10.1 Retrying a Bus Cycle
When an external device asserts the RETRY signal during a bus cycle, the MPC555
enters a sequence in which it terminates the current transaction, relinquishes the ownership of the bus, and retries the cycle using the same address, address attributes,
and data (in the case of a write cycle).
Figure 9-31 illustrates the behavior of the MPC555 when the RETRY signal is
detected as a termination of a transfer. As seen in this figure, in the case when the
internal arbiter is enabled, the MPC555 negates BB and asserts BG in the clock cycle
following the retry detection. This allows any external master to gain bus ownership.
In the next clock cycle, a normal arbitration procedure occurs again. As shown in the
figure, the external master did not use the bus, so the MPC555 initiates a new transfer
with the same address and attributes as before.
In Figure 9-32, the same situation is shown except that the MPC555 is working with
an external arbiter. In this case, in the clock cycle after the RETRY signal is detected
asserted, BR is negated together with BB. One clock cycle later, the normal arbitration
procedure occurs again.
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CLKOUT
BR
BG (output)
Allow External
Master to Gain the Bus
BB
ADDR[0:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (input)
O
Figure 9-31 Retry Transfer Timing–Internal Arbiter
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CLKOUT
BR (output)
BG
Allow External
Master to Gain the Bus
BB
ADDR[0:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (input)
O
Figure 9-32 Retry Transfer Timing–External Arbiter
When the MPC555 initiates a burst access, the bus interface recognizes the RETRY
assertion as a retry termination only if it detects it before the first data beat was
acknowledged by the slave device. When the RETRY signal is asserted as a termination signal on any data beat of the access after the first (being the first data beat
acknowledged by a normal TA assertion), the MPC555 recognizes RETRY as a transfer error acknowledge.
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CLKOUT
BR
BG (output)
Allow External Master
to Gain the Bus
BB
ADDR[0:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
BI
RETRY
O
If Asserted Will
Cause Transfer Error
Figure 9-33 Retry On Burst Cycle
If a burst access is acknowledged on its first beat with a normal TA but with the BI signal asserted, the following single-beat transfers initiated by the MPC555 to complete
the 16-byte transfer recognizes the RETRY signal assertion as a transfer error
acknowledge.
In the case in which a small port size causes the MPC555 to break a bus transaction
into several small transactions, terminating any transaction with RETRY causes a
transfer error acknowledge. See 9.5.2.3 Single Beat Flow with Small Port Size.
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9.5.10.2 Termination Signals Protocol Summary
Table 5-2 summarizes how the MPC555 recognizes the termination signals provided
by the slave device that is addressed by the initiated transfer.
Table 9-9 Termination Signals Protocol
TEA
TA
RETRY
Action
Asserted
X
X
Transfer error termination
Negated
Asserted
X
Normal transfer termination
Negated
Negated
Asserted
Retry transfer termination
9.5.11 Bus Operation in External Master Modes
When an external master takes ownership of the external bus and the MPC555 is programmed for external master mode operation, the external master can access the
internal space of the MPC555 (see 6.2 External Master Modes). In an external master mode, the external master owns the bus, and the direction of most of the bus
signals is inverted, relative to its direction when the MPC555 owns the bus.
The external master gets ownership of the bus and asserts TS in order to initiate an
external master access. The access is directed to the internal bus only if the input
address matches the internal address space. The access is terminated with one of the
followings outputs: TA, TEA, or RETRY. If the access completes successfully, the
MPC555 asserts TA, and the external master can proceed with another external master access or relinquish the bus. If an address or data error is detected internally, the
MPC555 asserts TEA for one clock. TEA should be negated before the second rising
edge after it is sampled asserted in order to avoid the detection of an error for the next
bus cycle initiated. TEA is an open drain pin, and the negation timing depends on the
attached pullup. The MPC555 asserts the RETRY signal for one clock in order to retry
the external master access.
If the address of the external access does not match the internal memory space, the
internal memory controller can provide the chip-select and control signals for accesses
that belong to one of the memory controller regions. This feature is explained in SECTION 10 MEMORY CONTROLLER.
Figure 9-34 and Figure 9-35 illustrate the basic flow of read and write external master
accesses.
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MPC555
External Master
Request Bus (BR)
Receives Bus Grant (BG) From Arbiter
Asserts Bus Busy (BB) if No Other Master is Driving
Assert Transfer Start (TS)
Drives Address and Attributes
Receives Address
No
Address in Internal
Memory Map
Yes
Memory
Returns Data
Controller
Asserts CSx
If In Range
Asserts Transfer Acknowledge (TA)
Receives Data
Figure 9-34 Basic Flow of an External Master Read Access
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External Master
MPC555
Request Bus (BR)
Receives Bus Grant (BG) From Arbiter
Asserts Bus Busy (BB) if No Other Master is Driving
Assert Transfer Start (TS)
Drives Address and Attributes
Receives Address
Address in Internal
Memory Map
Drives Data
No
Yes
Memory
Controller
Asserts CSx
If In Range
Receives Data
Asserts Transfer Acknowledge (TA)
Figure 9-35 Basic Flow of an External Master Write Access
,Figure 9-36, Figure 9-37 and Figure 9-38 describe read and write cycles from an
external master accessing internal space in the MPC555. Note that the minimum numMPC555
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ber of wait states for such access is two clocks. The accesses in these figures are valid
for both peripheral mode and slave mode.
CLKOUT
BR (input)
Use the Internal Arbiter
BG
Receive Bus Grant and Bus Busy Negated
O
O
Assert BB, Drive Address and Assert TS
BB
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
TS (input)
O
Data
TA (output)
O
Minimum 2 Wait States
DATA is valid
Figure 9-36 Peripheral Mode: External Master Reads
from MPC555 — Two Wait States
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CLKOUT
BR(input)
Use the Internal Arbiter
BG
Receive Bus Grant and Bus Busy Negated
O
O
Assert BB, Drive Address and Assert TS
BB
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
TS (input)
O
Data
TA (output)
O
Minimum 2 Wait States
DATA is sampled
Figure 9-37 Peripheral Mode: External Master Writes to MPC555;
Two Wait States
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9.5.12 Contention Resolution on External Bus
When the MPC555 is in slave mode, external master access to the MPC555 internal
bus can be terminated with relinquish and retry in order to allow a pending internal-toexternal access to be executed. The RETRY signal functions as an output that signals
the external master to release the bus ownership and retry the access after one clock.
Figure 9-38 describes the flow of an external master retried access. Figure 9-39
shows the timing when an external access is retried and a pending internal-to-external
access follows.
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External Master
MPC555
Request Bus (BR)
Receives BusGrant (BG) from Arbiter
Asserts Bus Busy (BB) if No Other Master is Driving
Assert Transfer Start (TS)
Drives Address and Attributes
Assert Retry
Release Bus Request (BR) for One Clock and Request Bus (BR) Again
Wait Until Bus Busy Negated (No Other Master is Driving)
Assert Bus Busy (BB)
Assert Transfer Start (TS)
Drives Address and Attributes
Receives Address
Address in Internal
Memory Map
No
Yes
Returns Data
Memory
Controller
Asserts CSx
If In Range
Asserts Transfer Acknowledge (TA)
Receives Data
Figure 9-38 Flow of Retry of External Master Read Access
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CLKOUT
BR
BG (output)
Allow Internal
Access to Gain the
Bus
BB
ADDR[0:31]
ADDR (internal)
ADDR (ext)ernal
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY(output)
O
Note: the delay for the internal to external cycle may be one clock or greater.
Figure 9-39 Retry of External Master Access (Internal Arbiter)
9.5.13 Show Cycle Transactions
Show cycles are accesses to the CPU’s internal bus devices. These accesses are
driven externally for emulation, visibility, and debugging purposes. A show cycle can
have one address phase and one data phase, or just an address phase in the case of
instruction show cycles. The cycle can be a write or a read access. The data for both
the read and write accesses should be driven by the bus master. (This is different from
normal bus read and write accesses.) The address and data of the show cycle must
each be valid on the bus for one clock. The data phase must not require a transfer
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acknowledge to terminate the bus show cycle. In a burst show cycle only the first data
beat is shown externally. Refer to Table 9-8 for show cycle transaction encodings.
Instruction show cycle bus transactions have the following characteristics (see Figure
9-40):
• One clock cycle
• Address phase only
• STS assertion only (no TA assertion)
I
CLKOUT
BR (in)
BG (out)
BB
ADDR[0:31]
ADDR2
ADDR1
RD/WR
TSIZ[0:1]
BURST
TS
STS
Data (three-state)
TA
“Normal” Non-Show Cycle Bus Transaction
Instruction Show Cycle Bus Transaction
Figure 9-40 Instruction Show Cycle Transaction
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Both read and write data show cycles have the following characteristics (see Figure
9-41):
• Two clock cycle duration
• Address valid for two clock cycles
• Data is valid only in the second clock cycle
• STS signal only is asserted (no TA or TS)
CLKOUT
BR (in)
BG (out)
BB
ADDR[0:31]
ADDR1
ADDR2
RD/WR
TSIZ[0:1]
BURST
TS
STS
Data
DATA1
DATA2
TA
Read Data Show Cycle Bus Transaction
Write Data Show Cycle Bus Transaction
Figure 9-41 Data Show Cycle Transaction
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SECTION 10
MEMORY CONTROLLER
The memory controller generates interface signals to support a glueless interface to
external memory and peripheral devices. It supports four regions, each with its own
programmed attributes. The four regions are reflected on four chip-select pins. Read
and write strobes are also provided.
The memory controller operates in parallel with the external bus interface to support
external cycles. When an access to one of the memory regions is initiated, the memory
controller takes ownership of the external signals and controls the access until its termination. Refer to Figure 10-1.
ADDR[0:31]
EBI Bus
Internal Bus
External
Bus
Interface
DATA[0:31]
Control Bus
U-bus
Interface
WE[0:3]/BE[0:3]
Memory Controller
Bus
Memory
Controller
OE
CS[0:3]
Figure 10-1 Memory Controller Function within the USIU
10.1 Overview
The memory controller provides a glueless interface to EPROM, static RAM (SRAM),
Flash EPROM (FEPROM), and other peripherals. The general-purpose chip-selects
are available on lines CS0 through CS3. CS0 also functions as the global (boot)
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chip-select for accessing the boot flash EEPROM. The chip select allows zero to 30
wait states.
Figure 10-2 is a block diagram of the MPC555 memory controller.
.
INTERNAL ADDRESS(0:16),AT(0:2)
,
Base Register (BR)
Base Register (BR)
Base Register (BR)
Base Register (BR)
Base Register (BR)
Base Register (BR)
Base Register (BR)
Option Register (OR)
Dual Mapping
Base Register (DMBR)
Dual Mapping
Option Register (DMOR)
Region Match Logic
ATTRIBUTES
CS(0:3)
Expired
Wait State Counter
Load
WE/BE(0:3)
General-Purpose
Chip-Select
Machine
(GPCM)
OE
Figure 10-2 Memory Controller Block Diagram
Most memory controller features are common to all four banks. (For features unique
to the CS0 bank, refer to 10.4 Global (Boot) Chip-Select Operation.) A full 32-bit
address decode for each memory bank is possible with 17 bits having address masking. The full 32-bit decode is available, even if all 32 address bits are not sent to the
MPC555 pins.
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Each memory bank includes a variable block size of 32 Kbytes, 64 Kbytes and up to
4 Gbytes. Each memory bank can be selected for read-only or read/write operation.
The access to a memory bank can be restricted to certain address type codes for system protection. The address type comparison occurs with a mask option as well.
From zero to 30 wait states can be programmed with TA generation. Four byte-write
and read-enable signals (WE/BE(0:3)) are available for each byte that is written to
memory. An output enable (OE) signal is provided to eliminate external glue logic. A
memory transfer start (MTS) strobe permits one master on a bus to access external
memory through the chip selects on another.
The memory controller functionality allows MPC555-based systems to be built with little or no glue logic. A minimal system using no glue logic is shown in Figure 10-3. In
this example CS0 is used for the 16-bit boot EPROM and CS1 is used for the 32-bit
SRAM. The WE/BE[0:3] signals are used both to program the EPROM and to enable
write access to various bytes in the RAM.
Address
Address
CE
CE
OE
OE
CS0
OE
WE/BE[0:1]
Data
DATA[0:15]
[0:15]
EPROM
MPC555
Address
CS1
CE
WE/BE[0:3]
WE/BE[0:3]
W
[0:31]
Data
OE
SRAM
Figure 10-3 MPC555 Simple System Configuration
10.2 Memory Controller Architecture
The memory controller consists of a basic machine that handles the memory access
cycle: the general-purpose chip-select machine (GPCM).
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When a new access to external memory is requested by any of the internal masters,
the address of the transfer (with 17 bits having mask) and the address type (with 3 bits
having mask) are compared to each one of the valid banks defined in the memory controller. Refer to Figure 10-4.
Base Address
Address Mask
RB ARB A RB A RB A RB A O O O O O O O O O RB A RB A
[0]
[1]
[2]
[3]
[4]
[15]
[16]
M
[0]
M
M
M
M
[1]
[2]
[3]
[4]
M
[5]
M
[6]
M
[7]
OOOO M
[16]
M[0:16]
A[0:16]
comp comp comp comp comp comp comp comp comp comp comp
Match
Figure 10-4 Bank Base Address and Match Structure
When a match is found on one of the memory banks, its attributes are selected for the
functional operation of the external memory access:
• Read-only or read/write operation
• Number of wait states for a single memory access, and for any beat in a burst
access
• Burst-inhibit indication. Internal burst requests are still possible during burst-inhibited cycles; the memory controller emulates the burst cycles
• Port size of the external device
Note that if more than one region matches the internal address supplied, then the lowest region is selected to provide the attributes and the chip select.
10.2.1 Associated Registers
Status bits for each memory bank are found in the memory control status register
(MSTAT). The MSTAT reports write-protect violations for all the banks.
Each of the four banks has a base register (BR) and an option register (OR). The BRx
and ORx registers contain the attributes specific to bank x. The base register contains
a valid bit (V) that indicates that the register information for that chip select is valid.
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10.2.2 Port Size Configuration
The memory controller supports dynamic bus sizing. Defined 8-bit ports can be
accessed as odd or even bytes. Defined 16-bit ports, when connected to data bus lines
zero to 15, can be accessed as odd bytes, even bytes, or even half-words. Defined 32bit ports can be accessed as odd bytes, even bytes, odd half-words, even half-words,
or words on word boundaries. The port size is specified by the PS bits in the base
register.
10.2.3 Write-Protect Configuration
The WP bit in each base register can restrict write access to its range of addresses.
Any attempt to write this area results in the associated WPER bit being set in the
MSTAT.
If an attempt to access an external device results in a write-protect violation, the memory controller considers the access to be no match. No chip-select line is asserted
externally, and the memory controller does not terminate the cycle. The external bus
interface generates a normal cycle on the external bus. Since the memory controller
does not acknowledge the cycle internally, the cycle may be terminated by external
logic asserting TA or by the on-chip bus monitor asserting TEA.
10.2.4 Address and Address Space Checking
The base address is written to the BR. The address mask bits for the address are written to the OR. The address type access value, if desired, is written to the AT bits in the
BR. The ATM bits in the OR can be used to mask this value. If address type checking
is not desired, program the ATM bits to zero.
Each time an external bus cycle access is requested, the address and address type
are compared with each one of the banks. If a match is found, the attributes defined
for this bank in its BR and OR are used to control the memory access. If a match is
found in more than one bank, the lowest bank matched handles the memory access
(e.g., bank zero is selected over bank one). Note that when an external master
accesses a slave on the bus, the internal AT[0:2] lines reaching the memory controller
are forced to 100.
10.2.5 Burst Support
Burst support is for read only. The memory controller supports burst accesses of external burstable memory. To enable bursts, clear the BI in the appropriate base register.
Bursts are four beats and non-wrapping. That is, the memory controller executes up
to four one-word accesses, but when a modulo four limit is reached, the burst is terminated (even if fewer than four words have been accessed).
When the SIU initiates a burst access, if no match is found in any of the memory controller’s regions then a burst access is initiated to the external bus. The termination of
each beat for this access is externally controlled (i.e., the user is responsible for terminating each data beat using the bus termination protocol).
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To support different types of memory devices, the memory controller supports two
types of timing for the BDIP signal: normal and late. Note that the BDIP pin itself is controlled by the external bus interface logic. Refer to Figure 9-13 and Figure 9-14 in
SECTION 9 EXTERNAL BUS INTERFACE.
If the memory controller is used to support an external master accessing an external
device with bursts, the BDIP input pin is used to indicate to the memory controller
when the burst is terminated.
For addition details, refer to 9.5.3 Burst Transfer.
10.3 Chip-Select Timing
The GPCM allows a glueless and flexible interface between the MPC555 and SRAM,
EPROM, EEPROM, ROM devices and external peripherals. When an address and
address type matches the values programmed in the BR and OR for one of the memory controller banks, the attributes for the memory cycle are taken from the OR and
BR registers as well. These attributes include the following fields: CSNT, ACS, SCY,
BSCY, WP, TRLX, BI, PS, and SETA.
Byte write and read-enable signals (WE/BE(0:3)) are available for each byte that is
written to or read from memory. An output enable (OE) signal is provided to eliminate
external glue logic for read cycles. Upon system reset, a global (boot) chip select is
available. This provides a boot ROM chip select before the system is fully configured.
Table 10-1 summarizes the chip-select timing options.
Table 10-1 Timing Attributes Summary
Timing Attribute
Access speed
Intercycle space time
Synchronous or
asynchronous device
Wait states
Bits/Fields
Description
TRLX
The TRLX (timing relaxed) bit determines strobe timing to be fast or relaxed.
EHTR
The EHTR (extended hold time on read accesses) bit is provided for devices that have long disconnect times from the data bus on read accesses. EHTR specifies whether the next cycle is delayed one clock cycle
following a read cycle, to avoid data bus contentions. EHTR applies to
all cycles following a read cycle except for another read cycle to the
same region.
ACS, CSNT
The ACS (address-to-chip-select setup) and CSNT (chip-select negation time) bits cause the timing of the strobes to be the same as the address bus timing, or cause the strobes to have setup and hold times
relative to the address bus.
SCY, BSCY,
SETA, TRLX
From zero to 15 wait states can be programmed for any cycle that the
memory controller generates. The transfer is then terminated internally.
In simplest case, the cycle length equals (2 + SCY) clock cycles, where
SCY represents the programmed number of wait states (cycle length in
clocks). The number of wait states is doubled if the TRLX bit is set.
When the SETA (external transfer acknowledge) bit is set, TA must be
generated externally, so that external hardware determines the number
of wait states.
Note that when a bank is configured for TA to be generated externally (SETA bit is set)
and the TRLX is set, the memory controller requires the external device to provide at
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least one wait state before asserting TA to complete the transfer. In this case, the minimum transfer time is three clock cycles.
The internal TA generation mode is enabled if the SETA bit in the OR register is
negated. However, if the TA pin is asserted externally at least two clock cycles before
the wait states counter has expired, this assertion terminates the memory cycle. When
SETA is cleared, it is forbidden to assert external TA less than two clocks before the
wait states counter expires.
10.3.1 Memory Devices Interface Example
Figure 10-5 describes the basic connection between the MPC555 and a static memory device. In this case CSx is connected directly to the chip enable (CE) of the
memory device. The WE/BE[0:3] lines are connected to the respective W in the memory device where each WE/BE line corresponds to a different data byte.
MPC555
Memory
Address
Address
CSx
CE
OE
OE
WE/BE
W
Data
Data
Figure 10-5 MPC555 GPCM–Memory Devices Interface
In Figure 10-6, the CSx timing is the same as that of the address lines output. The
strobes for the transaction are supplied by the OE and the WE/BE lines (if programmed as WE/BE). Because the ACS bits in the corresponding ORx register = 00,
CS is asserted at the same time that the address lines are valid. Note that because
CSNT is set, the WE signal is negated a quarter of a clock earlier than normal.
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Clock
Address
TS
CSNT = 1, ACS = 00
TA
CS
WE/BE
OE
Data
Note: In this and subsequent timing diagrams in this section, the data bus refers to a read cycle. In a write cycle, the
data immediately follows TS.
Figure 10-6 Memory Devices Interface Basic Timing
(ACS = 00,TRLX = 0)
10.3.2 Peripheral Devices Interface Example
Figure 10-7 illustrates the basic connection between the MPC555 and an external
peripheral device. In this case CSx is connected directly to the chip enable (CE) of the
memory device and the R/W line is connected to the R/W in the peripheral device. The
CSx line is the strobe output for the memory access.
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MPC555
Peripheral
Address
Address
CSx
CE
RD/WR
R/W
Data
Data
Figure 10-7 Peripheral Devices Interface
The CSx timing is defined by the setup time required between the address lines and
the CE line. The memory controller allows the user to specify the CS timing to meet
the setup time required by the peripheral device. This is accomplished through the
ACS field in the base register. In Figure 10-8, the ACS bits are set to 11, so CSx is
asserted half a clock cycle after the address lines are valid.
CLOCK
ACS = 11
Address
CSNT = 1
TS
TA
CS
RD/WR
Data
Figure 10-8 Peripheral Devices Basic Timing
(ACS = 11,TRLX = 0)
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10.3.3 Relaxed Timing Examples
The TRLX field is provided for memory systems that need a more relaxed timing
between signals. When TRLX is set and ACS = 0b00, the memory controller inserts
an additional cycle between address and strobes (CS line and WE/OE).
When TRLX and CSNT are both set in a write to memory, the strobe lines (WE/BE[0:3]
and CS, if ACS = 0b00) are negated one clock earlier than in the regular case.
Note that in the case of a bank selected to work with external transfer acknowledge
(SETA = 1) and TRLX = 1, the memory controller does not support external devices
providing TA to complete the transfer with zero wait states. The minimum access duration in this case equals three clock cycles.
Figure 10-9 shows a read access with relaxed timing. Note the following:
• Strobes (OE and CS) assertion time is delayed one clock relative to address
(TRLX bit set effect).
• Strobe (CS) is further delayed (half-clock) relative to address due to ACS field being set to 11.
• Total cycle length = 5, is determined as follows:
— Two clocks for basic cycle
— SCY = 1 determines 1 wait state, which is multiplied by two due to TRLX being
set.
— Extra clock is added due to TRLX effect on the strobes.
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CLOCK
Address
TS
ACS = ‘00’ & TRLX = ‘1’
ACS = ‘11’ & TRLX = ‘1’
TA
CS
RD/WR
WEBS = ‘0’,Line Acts as BE
in Read.
WE/BE
OE
Data
Figure 10-9 Relaxed Timing–Read Access
(ACS = 11, SCY = 1, TRLX = 1)
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Figure 10-10 through Figure 10-12 are examples of write accesses using relaxed timing. In Figure 10-10, note the following points:
• Because TRLX is set, assertion of the CS and WE strobes is delayed by one clock
cycle.
• CS assertion is delayed an additional one quarter clock cycle because ACS = 10.
• The total cycle length = three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— An extra clock cycle is required due to the effect of TRLX on the strobes.
CLOCK
Address
TS
ACS = 10
TA
CS
RD/WR
WE/BE
OE
Data
Figure 10-10 Relaxed Timing–Write Access
(ACS = 10, SCY = 0, CSNT = 0, TRLX = 1)
MOTOROLA
10-12
MEMORY CONTROLLER
Revised 1 March 1999
MPC555
USER’S MANUAL
In Figure 10-11, note the following:
• Because the TRLX bit is set, the assertion of the CS and WE strobes is delayed
by one clock cycle.
• Because ACS = 11, the assertion of CS is delayed an additional half clock cycle.
• Because CSNT = 1, WE is negated one clock cycle earlier than normal. (Refer to
Figure 10-6). The total cycle length is four clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— Two extra clock cycles are required due to the effect of TRLX on the assertion
and negation of the CS and WE strobes.
Clock
Address
TS
ACS =11
ACS!=00 & CSNT = 1
TA
CS
RD/WR
WE/BE
OE
CSNT = 1
Data
Figure 10-11 Relaxed Timing–Write Access
(ACS = 11, SCY = 0, CSNT = 1, TRLX = 1)
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-13
In Figure 10-12, notice the following:
• Because ACS = 0, TRLX being set does not delay the assertion of the CS and
WE strobes.
• Because CSNT = 1, WE/BE is negated one clock cycle earlier than normal. (Refer
to Figure 10-6).
• CS is not negated one clock cycle earlier, since ACS = 00.
• The total cycle length is three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— One extra clock cycles are required due to the effect of TRLX on the negation
of the WE/BE strobes.
CLOCK
Address
TS
No Effect, ACS = 00
TA
CS
RD/WR
WE/BE
OE
CSNT = 1
Data
Figure 10-12 Relaxed Timing–Write Access
(ACS = 00, SCY = 0, CSNT = 1, TRLX = 1
10.3.4 Extended Hold Time on Read Accesses
For devices that require a long disconnection time from the data bus on read
accesses, the bit EHTR in the corresponding OR register can be set. In this case any
MPC555 access to the external bus following a read access to the referred memory
bank is delayed by one clock cycle unless it is a read access to the same bank. Figure
MOTOROLA
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MEMORY CONTROLLER
Revised 1 March 1999
MPC555
USER’S MANUAL
10-13 through Figure 10-16 show the effect of the EHTR bit on memory controller
timing.
Figure 10-13 shows a write access following a read access. Because EHTR = 0, no
extra clock cycle is inserted between memory cycles.
CLOCK
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Figure 10-13 Consecutive Accesses (Write After Read, EHTR = 0)
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-15
Figure 10-14 shows a write access following a read access when EHTR = 1. An extra
clock is inserted between the cycles. For a write cycle following a read, this is true
regardless of whether both accesses are to the same region.
CLOCK
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Extra clock before next cycle starts.
Long Tdt allowed
Figure 10-14 Consecutive Accesses (Write After Read, EHTR = 1)
MOTOROLA
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MEMORY CONTROLLER
Revised 1 March 1999
MPC555
USER’S MANUAL
Figure 10-15 shows consecutive accesses from different banks. Because EHTR = 1
(and the accesses are to different banks), an extra clock cycle is inserted.
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Extra Clock Before Next Cycle Starts
Long Tdt Allowed
Figure 10-15 Consecutive Accesses
(Read After Read From Different Banks, EHTR = 1)
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-17
Figure 10-16 shows two consecutive read cycles from the same bank. Even though
EHTR = 1, no extra clock cycle is inserted between the memory cycles. (In the case
of two consecutive read cycles to the same region, data contention is not a concern.)
CLOCK
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Figure 10-16 Consecutive Accesses
(Read After Read From Same Bank, EHTR = 1)
10.3.5 Summary of GPCM Timing Options
Table 10-2 summarizes the different combinations of timing options.
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Revised 1 March 1999
MPC555
USER’S MANUAL
Table 10-2 Programming Rules for Strobes Timing
Address
to CS
Asserted
CS
WE/BE
Address to
OE
Negated to WE/BE or Negated to Negated to
Add/Data
OE
Add/Data
Add/Data
Asserted
Invalid
Invalid
Invalid
Total
Number of
Cycles
TRLX
Access
Type
ACS
CSNT
0
read
00
X
0
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
read
10
X
1/4 * clock
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
read
11
X
1/2 * clock
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
write
00
0
0
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
10
0
1/4 * clock
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
11
0
1/2 * clock
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
00
1
0
1/4 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
0
write
10
1
1/4 * clock
1/2 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
0
write
11
1
1/2 * clock
1/2 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
1
read
00
X
0
1/4 * clock
3/4 clock
X
1/4 * clock
2+
2 * SCY
1
read
10
X
(1 + 1/4) *
clock
1/4 * clock
(1 + 3/4) *
clock
X
1/4 * clock
3+
2 * SCY
1
read
11
X
(1 + 1/2) *
clock
1/4 * clock
(1 + 3/4) *
clock
X
1/4 * clock
3+
2 * SCY
1
write
00
0
0
1/4 * clock
3/4 clock
1/4 * clock
X
2+
2 * SCY
1
write
10
0
(1 + 1/4) *
clock
1/4 * clock
(1 + 3/4) *
clock
1/4 * clock
X
3+
2 * SCY
1
write
11
0
(1 + 1/2) *
clock
1/4 * clock
(1 + 3/4)
clock
1/4 * clock
X
3+
2 * SCY
1
write
00
1
0
1/4 * clock
3/4 clock
(1 + 1/2) *
clock
X
3+
2 * SCY
1
write
10
1
(1 + 1/4) *
clock
(1 + 1/2) *
clock
(1 + 3/4)
clock
(1 + 1/2) *
clock
X
4+
2 * SCY
1
write
11
1
(1 + 1/2) *
clock
(1 + 1/2) *
clock
(1 + 3/4)
clock
(1 + 1/2) *
clock
X
4+
2 * SCY
Additional timing rules not covered in Table 10-2 include the following:
• If SETA = 1, an external TA signal is required to terminate the cycle.
• If TRLX = 1 and SETA = 1, the minimum cycle length = 3 clock cycles (even if
SCY = 0000)
• If TRLX = 1, the number of wait states = 2 * SCY & 2 * BSCY
• If EHTR = 1, an extra (idle) clock cycle is inserted between a read cycle and a
following read cycle to another region, or between a read cycle and a following
write cycle to any region.
• If LBDIP = 1 (late BDIP assertion), the BDIP pin is asserted only after the number
of wait states for the first beat in a burst have elapsed. See Figure 9-13 in SECTION 9 EXTERNAL BUS INTERFACE as well as 9.5.4 Burst Mechanism. Note
that this function can operate only when the cycle termination is internal, using the
number of wait states programmed in one of the ORx registers
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-19
10.4 Global (Boot) Chip-Select Operation
Global (boot) chip-select operation allows address decoding for a boot ROM before
system initialization. CS0 is the global chip-select output. Its operation differs from that
of the other external chip-select outputs following a system reset. When the RCPU
begins accessing memory after a system reset, CS0 is asserted for every address,
unless an internal device (register) is accessed.
The global chip select provides a programmable port size at system reset using the
reset BPS pins ([4:5]) of the reset configuration word, allowing a boot ROM to be
located anywhere in the address space. For more information, see 7.5.2 Hard Reset
Configuration Word. The global chip select does not provide write protection and
responds to all address types. CS0 operates in this way until the first write to the CS0
option register (OR0). The pin can be programmed to continue decoding a range of
addresses after this write, provided the preferred address range is first loaded into
base register zero. After the first write to OR0, the global chip select can only be
restarted with a system reset.
The memory controller operates in boot mode until the user modifies the values in OR0
and BR to the ones desired.
Table 10-3 shows the initial values of the “boot bank” in the memory controller.
Table 10-3 Boot Bank Fields Values After Hard Reset
Field
Value (Binary)
PS
From reset configuration
WP
0
V
From reset configuration
AM[0:16]
0 0000 0000 0000 0000
ATM(0:2)
000
CSNT
0
ACS[0:1]
00
BI
1
SCY(0:3)
1111
BSCY(0:2)
011
SETA
0
TRLX
0
NOTE
If the MPC555 is configured (in the reset configuration word) to use
the internal flash EEPROM as boot memory CS0 is not asserted.
10.5 Write and Byte Enable Signals
The GPCM determines the timing and value of the WE/BE signals if allowed by
the port size of the accessed bank, the transfer size of the transaction and the
address accessed.
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MEMORY CONTROLLER
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MPC555
USER’S MANUAL
The functionality of the WE/BE[0:3] pins depends upon the value of the write
enable/byte select (WEBS) bit in the corresponding BR register. Setting WEBS to
1 will enable these pins as BE, while resetting it to zero will enable them as WE.
WE is asserted only during write access, while BE is asserted for both read and
write accesses. The timing of the WE/BE pins remains the same in either case,
and is determined by the TRLX, ACS and CSNT bits.
The upper WE/BE (WE0/BE0) indicates that the upper eight bits of the data bus
(D0–D7) contains valid data during a write/read cycle. The upper-middle write
byte enable (WE1/BE1) indicates that the upper-middle eight bits of the data bus
(D8–D15) contains valid data during a write/read cycle. The lower-middle write
byte enable (WE2/BE2) indicates that the lower-middle eight bits of the data bus
(D16–D23) contains valid data during a write/read cycle. The lower write/read
enable (WE3/BE3) indicates that the lower eight bits of the data bus contains valid
data during a write cycle.
The write/byte enable lines affected in a transaction for 32-bit port (PS = 00), a
16-bit port (PS = 10) and a 8-bit port (PS = 01) are shown in Table 10-4. This
table shows which write enables are asserted (indicated with an ‘X’) for different
combinations of port size and transfer size
Table 10-4 Write Enable/Byte Enable Signals Function
Transfer
Size
Address
TSIZ
A30 A31
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
Half
Word
1
0
0
0
1
0
1
0
Word
0
0
0
0
Byte
32-bit Port Size
16-bit Port Size
8-bit Port Size
WE0/ WE1/ WE2/ WE3/ WE0/ WE1/ WE2/ WE3/ WE0/ WE1/ WE2/ WE3/
BE0 BE1 BE2 BE3 BE0 BE1 BE2 BE3 BE0 BE1 BE2 BE3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
10.6 Dual Mapping of the Internal Flash EEPROM Array
The user can enable mapping of the internal flash EEPROM (CMF) module to an
external memory region controlled by the memory controller. Only one region can be
programmed to be dual-mapped. When dual mapping is enabled (DME bit is set in
DMBR), an internal address matches the dual-mapped address range (as programmed in the DMBR), and the cycle type matches AT/ATM field in DMBR/DMOR
registers, then the following occur:
• The internal flash memory does not respond to that address
• The memory controller takes control of the external access
• The attributes for the access are taken from one of the base and option registers
of the appropriate chip select
• The chip-select region selected is determined by the “CS line select” bit field
(10.8.5 Dual Mapping Base Register (DMBR)).
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-21
Note that dual mapping can operate only for addresses within the FLASH pre-allocated address (up to 2 Mbytes). This is achieved by programming only six bits for the
base address (11:16); The upper bits are always set as follows:
bus_addr[0:10]={0000000,isb[0:2],0}
Where ISB[0:2] represents the bit field in IMMR register that determines the location
of the address map of the MPC555.
With dual mapping, aliasing of address spaces may occur. This happens when the
user maps the dual-mapped region into a region which is also mapped into one of the
four regions available in the memory controller. If the user writes code or data to the
dual-mapped region, care must be taken to avoid overwriting this code or data by normal accesses of the chip-select region.
There is a match if:
bus_address[0:16] == {0000000,isb[0:2],0,dmbr_reg_value[1:6]}
Care must also be taken to avoid overwriting “normal” CSx data with dual-mapped
code or data.
One way to avoid this situation is by disabling the chip-select region and enabling only
the dual-mapped region (DME = 1, but Vx = 0, where x = selected region, 0.3). Figure
10-17 illustrates the phenomena.
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MEMORY CONTROLLER
Revised 1 March 1999
MPC555
USER’S MANUAL
MPC555 Memory Map
Dual Mapping
Physical External Memory
CSx
Dual-Map region
Flash
External CSx
Figure 10-17 Aliasing Phenomena Illustration
The default state is to allow dual-mapping data accesses only; this means that dual
mapping is possible only for data accesses on the internal bus. Also, the default state
takes the lower 2 Mbytes of the MPC555 internal flash memory. Hence, caution should
be taken to change the dual-mapping setup before the first data access.
NOTE
Dual mapping is not supported for an external master when the memory controller serves the access; In such a case, the MPC555
terminates the cycle by asserting TEA.
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-23
10.7 Memory Controller External Master Support
The memory controller in the MPC555 supports accesses initiated by both internal and
external bus masters to external memories. If the address of any master is mapped
within the internal MPC555 address space, the access will be directed to the internal
device, and will be ignored by the memory controller. If the address is not mapped
internally, but rather mapped to one of the memory contoller regions, the memory controller will provide the appropriate chip select and strobes as programmed in the
corresponding region (see 6.13.1.3 External Master Control Register (EMCR).
The MPC555 supports only synchronous external bus masters. This means that the
external master works with CLKOUT and implements the MPC555 bus protocol to
access a slave device.
A synchronous master initiates a transfer by asserting TS. The ADDR[0:31] signals
must be stable from the rising edge of CLKOUT during which TS is sampled, until the
last TA acknowledges the transfer. Since the external master works synchronously
with the MPC555, only setup and hold times around the rising edge of CLKOUT are
important. Once the TS is detected/asserted, the memory controller compares the
address with each one of its defined valid banks to find a possible match. But, since
the external address space is shorter than the internal space, the actual addess that
is used for comparing against the memory controller regions is in the format of:
{00000000, bits 8:16 of the external address}. In the case where a match is found, the
controls to the memory devices are generated and the transfer acknowledge indication
(TA) is supplied to the master.
Since it takes two clocks for the external address to be recognized and handled by the
memory controller, the TS which is generated by the external master is ahead of the
corresponding CS and strobes which are asserted by the memory controller. This 2clock delay might cause problems in some synchronous memories. To overcome this,
the memory controller generates the MTS (memory transfer start) strobe which can be
used in the slave’s memory instead of the external master’s TS signal. As seen in Figure 10-18, the MTS strobe is synchronized to the assertion of CS by the memory
controller so that the external memory can latch the external master’s address correctly. To activate this feature, the MTSC bit must be set in the SIUMCR register. Refer
to 6.13.1.1 SIU Module Configuration Register for more information.
When the external master accesses the internal flash when it is disabled, then the
access is terminated with transfer error acknowledge (TEA pin) asserted, and the
memory controller does not support this access in any way.
When the memory controller serves an external master, the BDIP pin becomes an
input pin. This pin is watched by the memory controller to detect when the burst is
terminated.
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MEMORY CONTROLLER
Revised 1 March 1999
MPC555
USER’S MANUAL
Synchronous External Master
TA
TS
BDIP
Data
ADDR
MPC555
BURST
Memory
TA
TS
MTS
TS
Address
Address
CSx
CE
OE
OE
WE/BE
W
BDIP
BDIP
Data
Data
BURST
BURST
Note that the memory controller’s BDIP line is used as a burst_in_progress signal.
Figure 10-18 Synchronous External Master
Configuration For GPCM–Handled Memory Devices
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-25
Address
Match
&
Compare
Memory
Device
Access
CLOCK
ADDR[0:31]
RD/WR
BURST
TSIZE
TS
MTS
TA
CS
WE/BE
OE
Data
Figure 10-19 Synchronous External Master Basic Access (GPCM controlled)
Note that since the MPC555 has only 24 address pins, the eight most significant internal address lines are driven as 0x0000_0000, and so compared in the memory
controller’s regions.
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MEMORY CONTROLLER
Revised 1 March 1999
MPC555
USER’S MANUAL
10.8 Programming Model
The following registers are used to control the memory controller.
Table 10-5 Memory Controller Address Map
Address
Register
0x2F C100
Base Register Bank 0 (BR0)
0x2F C104
Option Register Bank 0 (OR0)
0x2F C108
Base Register Bank 1 (BR1)
0x2F C10C
Option Register Bank 1 (OR1)
0x2F C110
Base Register Bank 2 (BR2)
0x2F C114
Option Register Bank 2 (OR2)
0x2F C118
Base Register Bank 3 (BR3)
0x2F C11C
Option Register Bank 3 (OR3)
0x2F C120 —
0x13F
Reserved
0x2F C140
Dual-Mapping Base Register (DMBR)
0x2F C144
Dual-Mapping Option Register (DMOR)
0x2F C148 —
0x2F C174
Reserved
0x2F C178
Memory Status Register (MSTAT)
Note:
In all subsequent registers bit tables, if two reset values are given: the upper is for CSx, x = 1, 2, 3, and the lower
is dedicated to CS0
10.8.1 General Memory Controller Programming Notes
1. In the case of an external master that accesses an internal MPC555 module (in
slave or peripheral mode), if that slave device address also matches one of the
memory controller’s regions, the memory controller will not issue any CS for this
access, nor will it terminate the cycle. Thus, this practice should be avoided. Be
aware also that any internal slave access prevents memory controller operation.
2. If the memory controller serves an external master, then it can support accesses to 32-bit port devices only. This is because the MPC555 external bus interface cannot initiate extra cycles to complete an access to a smaller port-size
device as it does not own the external bus.
3. When the SETA bit in the base register is set, then the timing programming for
the various strobes (CS, OE and WE/BE) may become meaningless.
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-27
10.8.2 Memory Controller Status Registers (MSTAT)
,
MSTAT — Memory Controller Status Register
MSB
0
1
2
3
4
5
6
7
RESERVED
0x2F C178
8
9
10
11
12
WPER0WPER1WPER2WPER3
13
LSB
15
14
RESERVED
HARD RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 10-6 MSTAT Bit Settings
Bit(s)
Name
0:7
—
8:11
Description
Reserved
Write protection error for bank x. This bit is asserted when a write-protect error occurs for the
WPER0 – associated memory bank. A bus monitor (responding to TEA assertion) will, if enabled, prompt
WPER3 the user to read this register if TA is not asserted during a write cycle. WPERx is cleared by writing one to the bit or by performing a system reset. Writing a zero has no effect on WPER.
12:15
—
Reserved
10.8.3 Memory Controller Base Registers (BR0 – BR3)
,
BR0 – BR3 — Memory Controller Base Registers 0 – 3 0x2F C100, C108, C110, C118
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BA
HRESET
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
PS
RESERVED
WP
BI
V
ID[4:5]*
0
0
1
ID3**
BA
AT
RESERVED
WEBS TBDIP LBDIP SETA
HRESET
U
U
U
U
0
0
0
0
0
* Reset value is determined by the value on the internal data bus during reset.
** The BR0 Reset value is determined by the value on the internal data bus during reset (reset-configuration word). The
reset value of the V bit of BR1-3 = 0.
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MEMORY CONTROLLER
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MPC555
USER’S MANUAL
Table 10-7 BR0 – BR3 Bit Settings
Bit(s)
Name
Description
0:16
BA
Base address. These bits are compared to the corresponding unmasked address signals among
ADDR[0:16] to determine if a memory bank controlled by the memory controller is being
accessed by an internal bus master. (The address types are also compared.) These bits are used
in conjunction with the AM[0:16] bits in the OR.
17:19
AT
Address type. This field can be used to require accesses of the memory bank to be limited to a
certain address space type. These bits are used in conjunction with the ATM bits in the OR. For
a full definition of address types, refer to 9.5.7.6 Address Types.
20:21
PS
Port size
00 = 32-bit port
01 = 8-bit port
10 = 16-bit port
11 = Reserved
22
—
Reserved
23
WP
24:25
—
Write protect. An attempt to write to the range of addresses specified in a base address register
that has this bit set can cause the TEA signal to be asserted by the bus-monitor logic (if enabled),
causing termination of this cycle.
0 = Both read and write accesses are allowed
1 = Only read accesses are allowed. The CSx signal and TA are not asserted by the memory
controller on write cycles to this memory bank. WPER is set in the MSTAT register if a write
to this memory bank is attempted
Reserved
26
WEBS
Write-enable/byte-select. This bit controls the functionality of the WE/BE pads.
0 = The WE/BE pads operate as WE
1 = The WE/BE pads operate as BE
27
TBDIP
Toggle-burst data in progress. TBDIP determines how long the BDIP strobe will be asserted for
each data beat in the burst cycles.
Late-burst-data-in-progress (LBDIP). This bit determines the timing of the first assertion of the
BDIP pin in burst cycles.
28
29
30
LBDIP
SETA
BI
Note: it is not allowed to set both LBDIP and TBDIP bits in a region’s base registers; the behavior
of the design in such cases is unpredictable.
0 = Normal timing for BDIP assertion (asserts one clock after negation of TS
1 = Late timing for BDIP assertion (asserts after the programmed number of wait states
External transfer acknowledge
0 = TA generated internally by memory controller
1 = TA generated by external logic. Note that programming the timing of CS/WE/OE strobes may
have no meaning when this bit is set
Burst inhibit
0 = Memory controller drives BI negated (high). The bank supports burst accesses.
1 = Memory controller drives BI asserted (low). The bank does not support burst accesses.
Note: Following a system reset, the BI bit is set in OR0.
31
V
MPC555
USER’S MANUAL
Valid bit. When set, this bit indicates that the contents of the base-register and option-register
pair are valid. The CS signal does not assert until the V-bit is set. Note that an access to a region
that has no V-bit set may cause a bus monitor timeout. Note also that following a system reset,
the V-bit in BR0 reflects the value of ID3 in the reset configuration word.
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-29
10.8.4 Memory Controller Option Registers (OR0 – OR3)
,
OR0 – OR3 — Memory Controller Option Registers 0 – 3
MSB
0
1
2
3
4
5
6
7
0x2F C104, C10C,
C114, C11C
8
9
10
11
12
13
14
15
AM*
HRESET:
(OR[1:3])
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
HRESET
(OR0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
AM*
ATM
CSNT
ACS
EHTR
SCY
BSCY
TRLX
HRESET: (OR[1:3]):
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0
0
0
0
0
0
1
1
1
1
0
1
1
0
HRESET
(OR0)
0
0
*It is recommended that this field would hold values that are the power of 2 minus 1 (e.g., - 23 - 1 = 7 [0b111]).
MOTOROLA
10-30
MEMORY CONTROLLER
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 10-8 OR0 – OR3 Bit Settings
Bit(s)
0:16
Name
AM
Description
Address mask. This field allows masking of any corresponding bits in the associated base register. Masking the address bits independently allows external devices of different size address
ranges to be used. Any clear bit masks the corresponding address bit. Any set bit causes the
corresponding address bit to be used in comparison with the address pins. Address mask bits
can be set or cleared in any order in the field, allowing a resource to reside in more than one area
of the address map. This field can be read or written at anytime.
Following a system reset, the AM bits are reset in OR0.
17:19
ATM
Address type mask. This field masks selected address type bits, allowing more than one address
space type to be assigned to a chip-select. Any set bit causes the corresponding address type
code bits to be used as part of the address comparison. Any cleared bit masks the corresponding
address type code bit. Clear the ATM bits to ignore address type codes as part of the address
comparison.
Following a system reset, the ATM bits are reset in OR0.
20
CSNT
Chip-select negation time. This attribute is used to determine when CS/WE are negated during
an external memory write access handled by the general-purpose chip-select machine. This is
helpful to meet address/data hold time requirements for slow memories and peripherals.
0 = CS/WE are negated normally.
1 = CS/WE are negated a quarter of a clock earlier than normal
Following a system reset, the CSNT bit is set in OR0.
21:22
ACS
Address to chip-select setup. This attribute allows the delay of the CS assertion relative to the
address change.
00 = CS is asserted at the same time that the address lines are valid.
01 = Reserved
10 = CS is asserted a quarter of a clock after the address lines are valid.
11 = CS is asserted half a clock after the address lines are valid
Following a system reset, the ACS bits are set in OR0.
23
EHTR
Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after a
read access from the current bank and any MPC555 write accesses or read accesses to a different bank.
0 = Memory controller generates normal timing
1 = Memory controller generates extended hold timing
Cycle length in clocks. This four-bit value represents the number of wait states inserted in the
single cycle, or in the first beat of a burst, when the GPCM handles the external memory access.
Values range from from 0 (0b0000) to 15 (0b1111). This is the main parameter for determining
the length of the cycle.
24:27
SCY
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length is (2 + SCY) x Clocks.
If the user has selected an external TA response for this memory bank (by setting the SETA bit),
then the SCY field is not used.
Note: Following a system reset, the SCY bits are set to 0b1111 in OR0.
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-31
Table 10-8 OR0 – OR3 Bit Settings (Continued)
Bit(s)
Name
Description
Burst beats length in clocks. This field determines the number of wait states inserted in all burst
beats except the first, when the GPCM starts handling the external memory access and thus
using SCY[0:3] as the main parameter for determining the length of that cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length for the beat is is (2 + BSCY) x Clocks.
28:30
BSCY
If the user has selected an external TA response for this memory bank (by setting the SETA bit)
then BSCY[0:3] are not used.
000 = 0-clock-cycle
001 = 1-clock-cycle wait states
010 = 2-clock-cycle wait states
011 = 3-clock-cycle wait states
1xx = Reserved
31
TRLX
Timing relaxed. This bit, when set, modifies the timing of the signals that control the memory
devices during a memory access to this memory region. Relaxed timing multiplies by two the
number of wait states determined by the SCY and BSCY fields. Refer to 10.3.5 Summary of
GPCM Timing Options for a full list of the effects of this bit on pins timing.
0 = Normal timing is generated by the GPCM.
1 = Relaxed timing is generated by the GPCM
Following a system reset, the TRLX bit is set in OR0.
10.8.5 Dual Mapping Base Register (DMBR)
,
DMBR — Dual Mapping Base Register
MSB
0
1
2
3
0
4
5
6
0x2F C140
7
BA
8
9
10
RESERVED
11
12
13
AT
14
15
RESERVED
HARD RESET:
0
U
U
U
U
U
U
0
0
0
0
0
1
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
RESERVED
DMCS
DME
HARD RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ID31*
*The reset value is a reset configuration word value extracted from the indicated internal data bus lines.
MOTOROLA
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MEMORY CONTROLLER
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 10-9 DMBR Bit Settings
Bit(s)
Name
0
—
Reserved
BA
Base address. The base address field is compared (along with the address type field) to the
address of the address bus to determine whether an address should be dual-mapped by one
of the memory banks controlled by the memory controller. These bits are used in conjunction
with the AM[11:16] bits in the OR.
1:6
Description
Bit 10: is cleared at reset. That way, the default range for the dual mapping is 2 Mbyte. Note
that by setting this bit, the range becomes 4 Mbyte, which includes memory space beyond the
flash EEPROM memory.
7:9
—
Reserved
10:12
AT
Address type. This field can be used to specify that accesses involving the memory bank are
limited to a certain address space type. These bits are used in conjunction with the ATM bits
in the OR. The default value at reset is to map data only. For a full definition of address types,
refer to 9.5.7.6 Address Types.
13:27
—
Reserved
28:30
DMCS
31
DME
Dual-mapping chip select. This field determines which chip-select pin is assigned for dual
mapping.
000 = CS0
001 = CS1
010 = CS2
011 = CS3
1xx = Reserved
Dual mapping enabled. This bit indicates that the contents of the dual-mapping registers and
associated base and option registers are valid and enables the dual-mapping operation. The
default value at reset comes from the internal data bus that reflects the reset configuration
word. See 10.6 Dual Mapping of the Internal Flash EEPROM Array for more information.
0 = Dual mapping is not active
1 = Dual mapping is active
10.8.6 Dual-Mapping Option Register
,
DMOR — Dual-Mapping Option Register
MSB
0
1
2
3
0
4
AM
5
6
7
*
0x2F C144
8
9
10
RESERVED
11
12
13
ATM
14
15
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
0
0
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
*It is recommended that this field would hold values that are the power of 2 minus 1 (e.g., - 23 - 1 = 7 [0b111]).
MPC555
USER’S MANUAL
MEMORY CONTROLLER
Revised 1 March 1999
MOTOROLA
10-33
Table 10-10 DMOR Bit Settings
Bit(s)
Name
Description
0
—
Reserved
1:6
AM
Address mask. The address mask field of each option register provides for masking any of the
corresponding bits in the associated base register. By masking the address bits independently, external devices of different size address ranges can be used. Any clear bit masks the
corresponding address bit. Any set causes the corresponding address bit to be used in the
comparison with the address pins. Address mask bits can be set or cleared in any order in the
field, allowing a resource to reside in more than one area of the address map. This field can
be read or written at any time.
7:9
—
Reserved
Address type mask. This field can be used to mask certain address type bits, allowing more
than one address space type to be assigned to a chip select. Any set bit causes the corresponding address type code bits to be used as part of the address comparison. Any cleared
bit masks the corresponding address type code bit.
10:12
ATM
To instruct the memory controller to ignore address type codes as part of the address comparison, clear the ATM bits.
Note: Following a system reset, the ATM bits are cleared in DMOR, except the ATM2 bit. This
means that only data accesses are dual mapped. Refer to the address types definition in Table
9-8.
13:31
MOTOROLA
10-34
—
Reserved
MEMORY CONTROLLER
Revised 1 March 1999
MPC555
USER’S MANUAL
SECTION 11
L-BUS TO U-BUS INTERFACE (L2U)
The L-bus to U-bus interface unit (L2U) provides an interface between the load/store
bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory
protection unit (DMPU), which provides protection for data memory accesses.
The L2U is bi-directional. It allows load/store accesses not intended for the L-bus data
RAM to go to the U-bus. It also allows code execution from the L-bus data RAM and
read/write accesses from the U-bus to the L-bus.
The L2U directs bus traffic between the L-bus and the U-bus. When transactions start
concurrently on both buses, the L2U interface arbitrates to select which transaction is
handled. The top priority is assigned to U-bus to L-bus accesses; lower priority is
assigned to the load/store accesses by the RCPU.
11.1 General Features
• Non-pipelined master and slave on U-bus
— Does not start two back-to-back accesses on the U-bus
— Supports the U-bus pipelining by starting a cycle on the U-bus when U-bus
pipe depth is zero or one
— Does not accept back-to-back accesses from the U-bus master
• Non-pipelined master and slave on the L-bus
• Generates module selects for L-bus memory-mapped resources within a programmable, contiguous block of storage
• Programmable data memory protection unit (DMPU)
• L-bus and U-bus snoop logic for PowerPC reservation protocol
• L2U does not support dual mapping of L-bus or IMB3 space
• Show cycles for RCPU accesses to the SRAM (none, all, writes)
— Protection for SRAM accesses from the U-bus side (all accesses to the SRAM
from the U-bus side are blocked once the SRAM protection bit is set)
11.2 DMPU Features
• Supports four memory regions whose base address and size can be programmed
— Available sizes are 4 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128
Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, and
16 Mbytes
— Region must start on the specified region size boundary
— Overlap between regions is allowed
• Each of the four regions supports the following attributes:
• Access protection: user or supervisor
• Guarded attribute: speculative or non-speculative
• Enable/disable option
• Read only option
MPC555
USER’S MANUAL
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MOTOROLA
11-1
• Supports a default global entry for memory space not covered by other regions:
— Default access protection
— Default guarded attribute
• Interrupt generated upon:
— Access violation
— Load from guarded region
— Write to read-only region
• The PowerPC MSR[DR] bit (data relocate) controls DMPU protection on/off operation
• Programming is done using PowerPC’s mtspr/mfspr instructions to/from implementation specific special purpose registers.
• No protection for accesses to the SRAM module on the L-bus (SRAM has its own
protection options)
11.3 L2U Block Diagram
Figure 11-1 shows a block diagram of the L-bus to U-bus interface.
L-bus
L-bus Interface
Address
Reservation
Decode
Control
DMPU
U-bus Interface
U-bus
Figure 11-1 L2U Bus Interface Block Diagram
11.4 Modes Of Operation
The L2U Module can operate in the following modes:
• Normal Mode
• Reset Operation
• Factory Test Mode
• Peripheral Mode
MOTOROLA
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L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MPC555
USER’S MANUAL
11.4.1 Normal Mode
In normal mode (master or slave) the L2U module acts as a bi-directional protocol
translator. In master mode the CPU is fully operational, and there is no external master
access to the U-bus. Slave mode enables an external master to access any internal
bus slave while the CPU is fully operational. The L2U transfers load/store accesses
from the RCPU to the U-bus and the read/write accesses by the U-bus master to the
L-bus.
In addition to the bus protocol translation, the L2U supports other functions such as
show cycles, data memory protection and PowerPC reservation protocol.
When a load from the U-bus resource or store to the U-bus resource is issued by the
RCPU, it is compared against the DMPU region access (address and attribute) comparators. If none of the access attributes are violated, the access is directed to the Ubus by the L2U module. If the DMPU detects an access violation, it informs the error
status to the master initiating the cycle.
When show cycles are enabled, accesses to all of the L-bus resources by the RCPU
are made visible on the U-bus side by the L2U.
The L2U is responsible for handling the effects of reservations on the L-bus and
the U-bus. For the L-bus and the U-bus, the L2U detects reservation losses and
updates the RCPU core with the reservation status.
11.4.2 Reset Operation
Upon soft reset assertion, the L2U goes to an idle state and all pending accesses are
ignored. The L2U module control registers are not initialized on the assertion of a soft
reset, keeping the system configuration unchanged.
Upon assertion of hard reset, the L2U control registers are initialized to their reset
states.
While reset (hard or soft) is asserted on the U-bus, the L2U asserts the corresponding
L-bus reset signals. The L2U also drives the reset configuration word from the U-bus
to the L-bus upon assertion of hard reset.
11.4.3 Factory Test Mode
Factory test mode is a special mode of operation that allows access to the internal
modules for testing. This mode is not intended for general use and is not supported for
normal applications.
11.4.4 Peripheral Mode
In the peripheral mode of operation the RCPU is shut down and an alternative master
on the external bus can perform accesses to any internal bus (U-bus and L-bus) slave.
The external master can also access the internal PowerPC special registers that are
located in L2U. In order to access one of these PowerPC registers the EMCR[CONT]
bit in the USIU must be cleared.
MPC555
USER’S MANUAL
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MOTOROLA
11-3
11.5 Data Memory Protection
The data memory protection unit (DMPU) in the L2U module provides access protection for the memory regions on the U-bus side from load/store accesses by the RCPU.
(Only U-bus space is protected.) The DMPU does not protect PowerPC register
accesses initiated by the RCPU on the L-bus. The user can assign up to four regions
of access protection attributes and can assign global attributes to any space not
included in the active regions. When it detects an access violation, the L2U generates
an exception request to the CPU.
Access attribute
Address
Region0 Address and size
Region1 Address and size
Region2 Address and size
Region3 Address and size
Match
select
Region0 protection/attribute
Region1 protection/attribute
Region2 protection/attribute
Region3 protection/attribute
Global protection/attribute
Specific
Error Interrupts
to Core
RegionProtection/Attribute
MSRDR
Exception
Logic
ACCESS
GRANTED
Figure 11-2 DMP Basic Functional Diagram
11.5.1 Functional Description
Data memory protection is assigned on a regional basis. Default manipulation of the
DMPU is done on a global region. The DMPU has control registers which contain the
following information: region protection on/off, region base address, region size, and
the region’s access permissions. Each region’s protection attributes can be turned on/
off by configuring the enable attribute bit (ENRx) located in the global region attribute
register.
During each load/store access from the RCPU core to the U-bus, the address is compared to the value in the region base address register of each enabled region. Any
access that matches the specific region within its appropriate size, as defined by the
region size field (RS) of the region attribute register, sets a match indication.
MOTOROLA
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Revised 1 March 1999
MPC555
USER’S MANUAL
When more than one match indication occurs, the effective region is the region with
the highest priority. Priority is determined by region number; highest priority corresponds to the lowest region number.
When no match occurs, the effective region is the global region. The global region has
the lowest priority.
The region attribute register also contains the region’s protection fields. The protection
field (PP) of the effective region is compared to the access attributes. If the attributes
match, the access is permitted. When the access is permitted, a U-bus access may be
generated according to the specific attribute of the effective region.
When the access by the RCPU is not permitted, the L2U module asserts a data memory storage exception to the RCPU.
For speculative load/store accesses from the RCPU to a region marked as guarded
(G bit of region attribute register is set), the L2U asks the RCPU to retry the L-bus cycle
until either the access is not speculative, or it is canceled by the RCPU.
In the case of attempted accesses to a guarded region together with any other protection violation (no access), the L2U retries the access. The L2U handles this event as
a data storage violation only when the access becomes non-speculative.
Note that access protection is active only when the PowerPC’s MSR[DR] = 1. When
MSR[DR] = 0, DMPU exceptions are disabled, all accesses are considered to be to a
guarded memory area, and no speculative accesses are allowed. In this case, if the Lbus master [RCPU] initiates a non-SRAM cycle (access through the L2U) that is
marked speculative, the L2U asks the RCPU to retry the L-bus cycle until either the
access is not speculative, or it is canceled by the RCPU Core.
Note that the programmer must not overlap the SRAM memory space with any
enabled region. Overlapping an enabled region with SRAM memory space disables
the L2U data memory protection for that region.
If an enabled region overlaps with the L-bus space, the DMPU ignores all accesses to
addresses within the L-bus space. If an enabled region overlaps with PowerPC register addresses, the DMPU ignores any access marked as a PowerPC access.
11.5.2 Associated Registers
The following registers are used to control the DMPU of the L2U module. All the registers are special purpose registers which are accessed via the PowerPC mtspr/
mfspr instructions. The registers are also accessed by an external master when
EMCR[CONT] = 0. See 11.8 L2U Programming Model for register diagrams and bit
descriptions.
MPC555
USER’S MANUAL
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MOTOROLA
11-5
.
Table 11-1 DMPU Registers
Name
Description
L2U_RBA0
Region Base Address Register 0
L2U_RBA1
Region Base Address Register 1
L2U_RBA2
Region Base Address Register 2
L2U_RBA3
Region Base Address Register 3
L2U_RA0
Region Attribute Register 0
L2U_RA1
Region Attribute Register 1
L2U_RA2
Region Attribute Register 2
L2U_RA3
Region Attribute Register 3
L2U_GRA
Global Region Attribute
CAUTION
The appropriate DMPU registers must be programmed before the
MSR[DR] bit is set. Otherwise, DMPU operation is not guaranteed.
Program the region base address in the L2U_RBAx registers to the lower boundary of
the region specified by the corresponding L2U_RAx[RS] field. If the region base
address does not correspond to the boundary of the block size programmed in the
L2U_RAx, the DMPU snaps the region base to the lower boundary of that block. For
example, if the block size is programmed to 16 Kbytes for region zero (i.e.
L2U_RA0[RS] = 0 x 3) and the region base address is programmed to 0x1FFF(i.e.,
L2U_RBA0[RBA] = 0 x 1), then the effective base address of region zero is 0 x 0. See
Figure 11-3.
0x00000000
region 0
(16 Kbytes)
Resulting Region
0x00001FFF
Actual Programmed Region
0x00003FFF
0x00005FFF
Figure 11-3 Region Base Address Example
MOTOROLA
11-6
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MPC555
USER’S MANUAL
It is the user’s responsibility to program only legal region sizes. The L2U does not
check whether the value is legal. If the user programs an illegal region size, the region
calculation may not be successful.
11.5.3 L-bus Memory Access Violations
All L-bus slaves have their own access protection logic. For consistency, all storage
access violations have the same termination result. Thus access violations for load/
store accesses started by the RCPU always have the same termination from all
slaves: assertion of the data storage exception. All other L-bus masters cause
machine check exceptions.
11.6 Reservation Support
The RCPU storage reservation protocol supports a multi-level bus structure. For each
local bus, storage reservation is handled by the local reservation logic. The protocol
tries to optimize reservation cancellation such that a PowerPC processor (RCPU) is
notified of storage reservation loss on a remote bus (U-bus, IMB or external bus) only
when it has issued a stwcx cycle to that address. That is, the reservation loss indication comes as part of the stwcx cycle.
11.6.1 The Reservation Protocol
The reservation protocol operates under the following assumptions:
• Each processor has at most 1 reservation flag
• A lwarx instruction sets the reservation flag
• Another lwarx instruction by same processor clears the reservation flag related
to a previous lwarx instruction and sets again the reservation flag
• A stwcx instruction by same processor clears the reservation flag
• A store instruction by same processor does not clear the reservation flag
• Some other processor (or other mechanism) store to an address with an existing
reservation clears the reservation flag
• In case the storage reservation is lost, it is guaranteed that stwcx will not modify
the storage
11.6.2 L2U Reservation Support
The L2U is responsible for handling the effects of reservations on the L-bus and the
U-bus. For the L-bus and the U-bus, the L2U detects reservation losses.
The reservation logic in the L2U performs the following functions:
• Snoops accesses to all L-bus and U-bus slaves
• Holds one reservation (address) for the core
• Sets the reservation flag when the CPU issues a load-with-reservation request
The unit for reservation is one word. A byte or half-word store request by another master will clear the reservation flag.
MPC555
USER’S MANUAL
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MOTOROLA
11-7
A load-with-reservation request by the CPU updates the reservation address related
to a previous load-with-reservation request and sets the reservation flag for the new
location. A store-with-reservation request by the CPU clears the reservation flag. A
store request by the CPU does not clear the flag. A store request by some other master
to the reservation address clears the reservation flag.
If the storage reservation is lost, it is guaranteed that a store-with-reservation request
by the CPU will not modify the storage.
The L2U does not start a store-with-reservation cycle on the U-bus if the reserved
location on the U-bus has been touched by another master. The L2U drives the reservation status back to the core.
When the reserved location in the SRAM on the L-bus is touched by an alternate master, on the following clock, the L2U indicates to the CPU that the reservation has been
touched. On assertion of the cancel-reservation signal, the RCPU clears the internal
reservation bit. If an stwcx cycle has been issued at the same time, the RCPU aborts
the cycle.
Storage reservation is set regardless of the termination status (address or data phase)
of the lwarx access. Storage reservation is cleared regardless of the data phase termination status of the stwcx access if the address phase is terminated normally.
Storage reservation will be cleared regardless of the data phase termination status of
the write requests by another master to the reserved address if the address phase of
the write access is terminated normally on the destination (U-bus/L-bus) bus.
If the programmable memory map of the part is modified between a lwarx and a stwcx
instruction, the reservation is not guaranteed.
11.6.3 Reserved Location (Bus) and Possible Actions
Once the CPU core reserves a memory location, the L2U module is responsible for
snooping L-bus and U-bus for possible intrusion of the reserved location. Under certain circumstances, the L2U depends on the USIU or the UIMB to provide status of
reservation on external bus and the IMB3 respectively.
Table 11-2 lists all reservation protocol cases supported by the L2U snooping logic.
MOTOROLA
11-8
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 11-2 Reservation Snoop Support
Reserved Location On
Intruding Alternate Master
L-bus
L-Master
Request to cancel the reservation.1
U-Master
Request to cancel the reservation.
L-Master
Block stwcx2
U-Master
Block stwcx
L-Master
Block stwcx
U-Master
Block stwcx
U-bus
External Bus
Ext-Master
IMB3
Action Taken on stwcx cycle
Transfer Status3
L-Master
Block stwcx
U-Master
Block stwcx
IMB3-Master
Transfer Status
NOTES:
1. If the RCPU tries to modify (stwcx) that location, the L2U does not have enough time to stop the write
access from completing. In this case, the L2U will drive cancel-reservation signal back to the core as
soon as it comes to know that the alternate master on the U-bus has touched the reserved location.
2. If the RCPU tries to modify (stwcx) that location, the L2U does not start the cycle on the U-bus and it
communicates to the core that the current write has been aborted by the slave with no side effects.
3. If the RCPU tries to modify (stwcx) that location, the L2U runs a write-cycle-with-reservation request
on the U-bus. The L2U samples the status of the reservation along with the U-bus cycle termination
signals and it communicates to the core if the current write has been aborted by the slave with no side
effects.
11.7 L-Bus Show Cycle Support
The L2U module provides support for L-bus show cycles. L-bus show cycles are external visibility cycles that reflect activity on the L-bus that would otherwise not be visible
to the external bus. L-bus show cycles are software controlled.
11.7.1 Programming Show Cycles
L-bus show cycles are disabled during reset and must be configured by writing the
appropriate bits in the L2U_MCR control register. L-bus show cycles are programmed
by setting the LSHOW[0:1] bits in the L2U_MCR. The Table 11-3 shows the configurations of the LSHOW[0:1] bits.
Table 11-3 L2U_MCR LSHOW Modes
LSHOW
Action
00
Disable L-bus show cycles
01
Show address and data of all L-bus space write cycles
10
Reserved (Disable L-bus show cycles)
11
Show address and data of all L-bus space read and write cycles
11.7.2 Performance Impact
When show cycles are enabled in the L2U module, there is a performance penalty on
the L-bus. This occurs because the L2U module does not support more than one
access being processed at any time. To ensure that only one access at a time can be
MPC555
USER’S MANUAL
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MOTOROLA
11-9
processed, and not lose an L-bus access that would have been show cycled, the L2U
module will arbitrate for the L-bus whenever it is processing any access. This L-bus
arbitration will prevent any other L-bus master from starting a cycle that might turn out
to be a qualifiable L-bus show cycle.
For L-bus show cycles, the minimum performance impact on the L-bus will be three
clocks. This minimum impact assumes that the L-bus slave access is a 1-clock access,
and the L2U module acquires immediate bus grant on the U-bus. The L2U has to wait
two clocks before completing the show cycle on the U-Bus, thus using up five clocks
for the complete process.
A retried access on the L-bus (no address acknowledge) that qualifies to be show
cycled, will be accepted when it is actually acknowledged. This will cause a 1-clock
delay before an L-bus master can retry the access on the L-bus, because the L2U
module will release L-bus one clock later.
L2U asserts the internal bus request signal on the U-bus for a minimum of two clocks
when starting a show cycle on the U-bus.
11.7.3 Show Cycle Protocol
The L2U module behaves as both a master and a slave on the U-bus during show
cycles. The L2U starts the U-bus transfer as a a bus master and then completes the
address phase and data phase of the cycle as a slave. The L2U follows U-bus protocol
of in-order termination of the data phase.
The USIU can control the start of show cycles on the U-bus by asserting the no-show
cycle indicator. This will cause the L2U module to release the U-bus for at least one
clock before retrying the show cycle.
11.7.4 L-Bus Write Show Cycle Flow
The L2U performs the following sequence of actions for an L-bus-write show cycle.
1. Arbitrates for the L-bus to prevent any other L-bus cycles from starting
2. Latches the address and the data of the L-bus access, along with all address
attributes
3. Waits for the termination of the L-bus access and latches the termination status
(data error)
4. Arbitrate for the U-bus, and when granted, starts the U-bus access, asserting
show cycle request on the U-bus, along with address, attributes and the write
data. The L2U module provides address recognize and acknowledgment for
the address phase. If the no-show cycle indicator from the U-bus is asserted,
the L2U does not start the show cycle. The L2U module releases the U-bus until
the no-show cycle indicator is negated and then arbitrates for the U-bus again.
5. When the L2U module has U-bus data bus grant, it drives the data phase termination handshakes on the U-bus.
6. Releases the L-bus
MOTOROLA
11-10
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MPC555
USER’S MANUAL
11.7.5 L-Bus Read Show Cycle Flow
The L2U performs the following sequence of actions for an L-bus read show cycle.
1. Arbitrates for the L-bus to prevent any other L-bus cycle from starting
2. Latches the address of the L-bus access, along with all address attributes
3. Waits for the data phase termination on the L-bus and latch the read data, and
the termination status from the L-bus
4. Arbitrate for the U-bus, and when granted, starts the U-bus access, asserting
the show cycle request on the U-bus, along with address attributes. The L2U
module provides address recognize/acknowledgment for the address phase. If
the no-show cycle indicator from the U-bus is asserted, the L2U does not start
the show cycle. The L2U module releases the U-bus until the no-show cycle indicator is negated and then arbitrates for the U-bus again.
5. When the L2U module has U-bus data bus grant, it drives the read data and the
data phase termination handshakes on the U-bus
6. Release the L-bus.
11.7.6 Show Cycle Support Guidelines
The following are the guidelines for L2U show cycle support:
• The L2U module provides address and data for all qualifying L-bus cycles when
the appropriate mode bits are set in the L2U_MCR.
• The L2U-module-only show cycles L-bus activity that is not targeted for the U-bus
or the L2U module internal registers, irrespective of the termination status of such
activity.
• The L2U module does not show cycle any access to a PowerPC special purpose
register.
• The L2U does not start a show cycle for an L-bus access that is retried. This decision to not start the show cycle causes a clock delay before the cycle can be
retried, since the L2U module will have arbitrated away the L-bus immediately on
detecting the show cycle, before the retry information is available.
• The L2U module does not show cycle any L-bus activity that is aborted.
• The L2U module backs off the U-bus if the USIU inhibits show cycle activity on
the U-bus.
• The L2U does not show cycle any L-bus addresses that fall in the L-bus SRAM
address space if the SRAM Protection [SP] bit is set in the L2U_MCR.
Table 11-4 summarizes the L2U show cycle support.
MPC555
USER’S MANUAL
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MOTOROLA
11-11
Table 11-4 L2U Show Cycle Support Chart
Case
Destination
LB AACK
LB ABORT
Comments
1
L-bus Slave1
No
X
Not show cycled
[Cycle will be retried one clock later]4
2
L2U 2
X
X
Not show cycled
X
X
Not show cycled
3
3
U-bus/E-bus
4
L-bus slave
Yes
No
Show cycled
5
L-bus slave
Yes
Yes
Not show cycled
[L-bus will be released next clock]
1. L-bus slave includes all address in the L-bus address space.
2. L2U indicates L2U registers.
3. U-bus/E-bus refers to all destinations through the L2U interface.
4. There will be a 1-clock turnaround because the L-bus retry information is not available in time to negate the Lbus arbitration.
Note: X indicates don’t care conditions.
11.8 L2U Programming Model
The L2U control registers control the L2U bus interface and the DMPU. They are
accessible via the MPC555 mtspr and mfspr instructions. They are also accessible
by an external master when EMCR[CONT] bit is cleared. L2U control registers are
accessible from both the L-bus side and the U-bus side in one clock cycle. As with all
SPRs, L2U registers are accessible in supervisor mode only.
Any unimplemented bits in L2U registers return 0’s on a read, and the writes to those
register bits are ignored.
The Table 11-5 shows L2U registers along with their SPR numbers and hexadecimal
addresses which are used to access L2U registers during a peripheral mode access.
.
Table 11-5 L2U (PPC) Register Decode
Name
SPR #
SPR5:9
SPR0:4
Address for
External Master
Access
Access
Description
L2U_MCR
568
10001
11000
0x0000_3110
SUPR
L2U Module Configuration Register
L2U_RBA0
792
11000
11000
0x0000_3180
SUPR
Region Base Address Register 0
L2U_RBA1
793
11000
11001
0x0000_3380
SUPR
Region Base Address Register 1
L2U_RBA2
794
11000
11010
0x0000_3580
SUPR
Region Base Address Register 2
L2U_RBA3
795
11000
11011
0x0000_3780
SUPR
Region Base Address Register 3
L2U_RA0
824
11001
11000
0x0000_3190
SUPR
Region Attribute Register 0
L2U_RA1
825
11001
11001
0x0000_3390
SUPR
Region Attribute Register 1
L2U_RA2
826
11001
11010
0x0000_3590
SUPR
Region Attribute Register 2
L2U_RA3
827
11001
11011
0x0000_3790
SUPR
Region Attribute Register 3
L2U_GRA
536
10000
11000
0x0000_3100
SUPR
Global Region Attribute
For these registers a bus cycle will be performed on the L-bus and the U-bus with the
address as shown inTable 11-6.
MOTOROLA
11-12
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MPC555
USER’S MANUAL
.
Table 11-6 Hex Address For SPR Cycles
A0:17
A18:22
A23:27
A28:31
0
spr0:4
spr5:9
0
11.8.1 U-bus Access
The L2U registers are accessible from the U-bus side only if it is a supervisor mode
data access and the register address is correct and it is indicated on the U-bus that it
is a PPC register access.
A user mode access, or an access marked as instruction, to L2U registers from the Ubus side will cause a data error on the U-bus.
11.8.2 Transaction Size
All L2U registers are defined by PowerPC architecture as being 32-bit registers. There
is no PowerPC instruction to access either a half word or a byte of the special purpose
register. All L2U registers are only word accessible (read and write) in peripheral
mode. A half-word or byte access in peripheral mode will result in a word transaction.
11.8.3 L2U Module Configuration Register (L2U_MCR)
The L2U module configuration register (L2U_MCR) is used to control the L2U module
operation.
L2U_MCR — L2U Module Configuration Register
MSB
0
SP
1
2
3
4
5
6
7
8
LSHOW
SPR 568
9
10
11
12
13
14
15
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
0
0
RESERVED
RESET:
0
0
0
MPC555
USER’S MANUAL
0
0
0
0
0
0
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MOTOROLA
11-13
Table 11-7 L2U_MCR Bit Settings
Bit(s)
Name
Description
SRAM Protection (SP) bit is used to protect the SRAM on the L-bus from U-bus accesses.
This bit can be set or cleared from the L-bus side. It can be set or cleared from the U-bus side
when factory test mode is enabled. When not in factory test mode, any attempt to set or clear the
SP bit from the U-bus side has no affect.
0
SP
Once this bit is set, the L2U blocks all SRAM accesses initiated by the U-bus masters and the
access is terminated with a data error on the U-bus.
If L-bus show cycles are enabled, setting this bit will disable L-bus SRAM show cycles.
1:2
LSHOW
3:31
—
LSHOW bits are used to configure the show cycle mode for cycles accessing the L-bus slave e.g.
SRAM
00 = Disable show cycles
01 = Show address and data of all L-bus space write cycles
10 = Reserved
11 = Show address and data of all L-bus space read and write cycles
Reserved
11.8.4 Region Base Address Registers (L2U_RBAx)
The region base address register defines the base address of a specific region protected by the data memory protection unit. There are four registers (x = 0...3), one for
each supported region.
L2U_RBAx — L2U Region x Base Address Register
MSB
0
1
2
3
4
5
6
7
SPR 792 – 795
8
9
10
11
12
13
14
15
RBA
RESET:
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
RBA
RESERVED
RESET:
x
x
x
x
0
0
0
0
0
0
0
x = Undefined
Table 11-8 L2U_RBAx Bit Settings
Bit(s)
Name
Description
0:19
RBA
Region base address. The RBA field provides the base address of the region. The region base
address should start on the block boundary for the corresponding block size attribute specified
in the region attribute register (L2U_RAx).
20:31
—
MOTOROLA
11-14
Reserved
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MPC555
USER’S MANUAL
11.8.5 Region Attribute Registers (L2U_RAx)
Each region attribute register defines the protection attributes associated with a specific region protected by the data memory protection unit. There are four registers (x =
0...3), one for each supported region.
L2U_RAx — L2U Region X Attribute Register
MSB
0
1
2
3
4
5
6
7
SPR 824 – 827
8
9
10
11
RESERVED
12
13
14
15
RS
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
RS
PP
RESERVED
G
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 11-9 L2U_RAx Bit Settings
Bit(s)
Name
0:7
—
Reserved
RS
Region size
0000_0000_0000 = 4 Kbytes
0000_0000_0001 = 8 Kbytes
0000_0000_0011 = 16 Kbytes
0000_0000_0111 = 32 Kbytes
0000_0000_1111 = 64 Kbytes
0000_0001_1111 = 128 Kbytes
0000_0011_1111 = 256 Kbytes
0000_0111_1111 = 512 Kbytes
0000_1111_1111 = 1 Mbyte
0001_1111_1111 = 2 Mbytes
0011_1111_1111 = 4 Mbytes
0111_1111_1111 = 8 Mbytes
1111_1111_1111 = 16 Mbytes
20:21
PP
Protection bits
00 = No supervisor access, no user access
01 = Supervisor read/write access, no user access
10 = Supervisor read/write access, user read-only access
11 = Supervisor read/write access, user read/write access
22:24
—
Reserved
25
G
Guarded attribute
0 = Not guarded from speculative accesses
1 = Guarded from speculative accesses
26:31
—
Reserved
8:19
Description
11.8.6 Global Region Attribute Register
The global region attribute register defines the protection attributes associated with the
memory region which is not protected under the four DMPU regions. This register also
provides enable/disable control for the four DMPU regions.
MPC555
USER’S MANUAL
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MOTOROLA
11-15
L2U_GRA — L2U Global Region Attribute Register
MSB
0
1
2
3
4
5
6
7
8
SPR 536
9
ENR0 ENR1 ENR2 ENR3
10
11
12
13
14
15
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
RESERVED
PP
RESERVED
G
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 11-10 L2U_GRA Bit Settings
Bit(s)
Name
0
ENR0
Enable attribute for region 0
0 = Region attribute is off
1 = Region attribute is on
1
ENR1
Enable attribute for region 1
0 = Region attribute is off
1 = Region attribute is on
2
ENR2
Enable attribute for region 2
0 = Region attribute is off
1 = Region attribute is on
3
ENR3
Enable attribute for region 3
0 = Region attribute is off
1 = Region attribute is on
4:19
—
Reserved
20:21
PP
Protection bits
00 = No supervisor access, no user access
01 = Supervisor read/write access, no user access
10 = Supervisor read/write access, user read-only access
11 = Supervisor read/write access, user read/write access
22:24
—
Reserved
25
G
Guarded attribute
0 = Not guarded from speculative accesses
1 = Guarded from speculative accesses
26:31
—
Reserved
MOTOROLA
11-16
Description
L-BUS TO U-BUS INTERFACE (L2U)
Revised 1 March 1999
MPC555
USER’S MANUAL
SECTION 12
U-BUS TO IMB3 BUS INTERFACE (UIMB)
The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the
CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.
The UIMB interface consists of seven submodules that control bus interface timing,
address decode, data multiplexing, intrasystem communication (interrupts), and clock
generation to allow communication between U-bus and the IMB3. The seven submodules are:
• U-bus interface
• IMB3 interface
• Address decoder
• Data multiplexer
• Interrupt synchronizer
• Clock control
• Scan control
12.1 Features
• Provides complete interfacing between the U-bus and the IMB3:
— 15 bits (32 Kbytes) of address decode on IMB3
— 32-bit data bus
— Read/write access to IMB3 module registers1
— Interrupt synchronizer
— Monitoring of accesses to unimplemented addresses within UIMB interface
address range
— Burst-inhibited accesses to the modules on IMB3
• Support of 32-bit and 16-bit BIUs for IMB3 modules
• Half and full speed operation of IMB3 bus with respect to U-bus
• Simple “slave only” U-bus interface implementation
— Supports alternate master on IMB3
— Transparent mode operation not supported
— Relinquish and retry not supported
• Supports scan control for modules on the IMB3 and on the U-bus
NOTE
Modules on the IMB3 bus can only be reset by SRESET. Some modules may have a module reset, also.
1.
The user should not perform instruction fetches from modules on the IMB.
MPC555
USER’S MANUAL
U-BUS TO IMB3 BUS INTERFACE (UIMB)
Revised 1 March 1999
MOTOROLA
12-1
12.2 noUIMB Block Diagram
U-bus
Interface
Address
Decode
U-bus
IMB3
Interface
IMB3
Data
Mux
Scan Control
Interrupt
Synchronizer
Clock Control
Figure 12-1 UIMB Interface Module Block Diagram
12.3 Clock Module
The clock module within the UIMB interface generates the IMB clock. The IMB clock
is the main timing reference used within the IMB modules.
The IMB clock is generated based on the STOP and HSPEED bits in the UIMB module
configuration register (UMCR). If the STOP bit is 1, the IMB clock is not generated. If
the STOP bit is 0 and the HSPEED bit is 0, the IMB clock is generated as the inversion
of the CLKOUT signal. (See Figure 12-2.)
Table 12-1 STOP and HSPEED Bit Functionality
STOP
HSPEED
0
0
Functionality
IMB bus frequency is the same as U-bus frequency.
0
1
IMB bus frequency is half that of the U-bus frequency.
1
X
IMB clock is not generated.
CLKOUT
IMB Clock
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
B4
B1
B2
B3
B4
B1
B2
B3
Figure 12-2 IMB Clock – Full-Speed IMB Bus
MOTOROLA
12-2
U-BUS TO IMB3 BUS INTERFACE (UIMB)
Revised 1 March 1999
MPC555
USER’S MANUAL
CLKOUT
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
IMB Clock
B4
B1
B2
B3
Figure 12-3 IMB Clock – Half-Speed IMB Bus
Table 12-2 shows the number of system clock cycles that the UIMB requires to perform each type of bus cycle. It is assumed in this table that the IMB3 is available to the
UIMB at all times (fastest possible case).
Table 12-2 Bus Cycles and System Clock Cycles
Bus Cycle (from U-bus Transfer Start
to U-bus Transfer Acknowledge)
Number of System Clock Cycles
Full Speed
Half Speed
Normal write
4
6
Normal read
4
6
Dynamically-sized write
6
10
Dynamically-sized read
6
10
NOTE
The UIMB interface dynamically interprets the port size of the
addressed module during each bus cycle, allowing bus transfers to
and from 16-bit and 32-bit IMB modules. During a bus transaction,
the slave module on the IMB signals its port size (16- or 32-bit) via an
internal port size signal.
12.4 Interrupt Operation
The interrupts from the modules on the IMB3 are propagated to the interrupt controller
in the USIU through the UIMB interface. The UIMB interrupt synchronizer latches the
Interrupts from the IMB3 and drives them onto the U-bus, where they are latched by
the USIU interrupt controller.
12.4.1 Interrupt Sources and Levels on IMB
The IMB3 has eight interrupt lines. There can be a maximum of 32 levels of interrupts
from the modules on IMB bus. A single module can be a source for more than one
interrupt. For example, the QSMCM can generate two interrupts (one for QSCI1/
QSCI2 and another for QSPI). In this case, the QSMCM has two interrupt sources.
Each of these two sources can assert the interrupt on any of the 32 levels.
It is possible for multiple interrupt sources to assert the same interrupt level. To reduce
the latency, it is a good practice for each interrupt source to assert an interrupt on a
level on which no other interrupt source is mapped.
MPC555
USER’S MANUAL
U-BUS TO IMB3 BUS INTERFACE (UIMB)
Revised 1 March 1999
MOTOROLA
12-3
12.4.2 IMB Interrupt Multiplexing
The IMB has 10 lines for interrupt support. Eight lines are for interrupts and two for
ILBS. These lines will transfer the 32 interrupt levels to the interrupt synchronizer. A
diagram of the interrupt flow is shown in Figure 12-4.
IMB interrupt
U-bus Interrupt
Level[0:7]
UIPEND
8
(0:7)
8
(8:15)
Byte Count
Byte-enables
Block
Byte-enable
to IMB
4
(16:23)
U-bus Data[0:31]
(24:31)
2
Figure 12-4 Interrupt Synchronizer Signal Flow
Latching 32 interrupt levels using eight IMB interrupt lines is accomplished with a 4:1
time-multiplexing scheme. The UIMB drives two signals (ILBS[0:1]) with a multiplexer
select code that tells all interrupting modules on the IMB about which group of signals
to drive during the next clock.
12.4.3 ILBS Sequencing
The IMB interface drives the ILBS signals continuously, incrementing through a code
sequence (00, 01, 10, 11) once every clock The IRQMUX[0:1] bits in the IMB module
configuration register select which type of multiplexing the Interrupt synchronizer will
perform. The IRQMUX field can select time-multiplexing protocols for 8, 16, 24 or 32
interrupt sources. These protocols would take one, two, three or four clocks,
respectively.
Table 12-4 shows ILBS sequencing. Programming IRQMUX[0:1] to 00 disables time
multiplexing. In this case the ILBS lines remain at 00 at all times, as shown in Table
12-4. In this mode, no interrupts from IMB modules which assert on levels 8 through
31 are ever latched by the Interrupt synchronizer. Time multiplexing is disabled during
reset, but the reset default value enables time multiplexing as soon as reset is
released if the reset default value is not 00.
The timing for the scheme and the values of ILBS and the interrupt levels driven onto
the IMB IRQ lines are shown in Figure 12-5. This scheme causes a maximum latency
of four clocks and an average latency of two clocks before the interrupt request can
reach the interrupt synchronizer.
MOTOROLA
12-4
U-BUS TO IMB3 BUS INTERFACE (UIMB)
Revised 1 March 1999
MPC555
USER’S MANUAL
IMB CLOCK
ILBS [0:1]
00
01
LVL
0:7
IMB LVL[0:7]]
10
LVL
8:15
11
00
01
LVL
16:23
LVL
24:31
LVL
0:7
10
11
Figure 12-5 Time-Multiplexing Protocol for IRQ pins
Table 12-3 ILBS Signal functionality
ILBS[0:1]
Description
00
IMB interrupt sources mapped onto 0:7 levels will
drive interrupts onto IMB IRQ[0:7]
01
IMB interrupt sources mapped onto 8:15 levels will
drive interrupts onto IMB IRQ[0:7]
10
IMB interrupt sources mapped onto 16:23 levels will
drive interrupts onto IMB IRQ[0:7]
11
IMB interrupt sources mapped onto 24:31 levels will
drive interrupts onto IMB IRQ[0:7]
The IRQMUX bits determine how many levels of IMB interrupts are sampled. Refer to
Table 12-4.
.
Table 12-4 IRQMUX Functionality
IRQMUX[0:1]
ILBS sequence
Description
00
00, 00, 00.....
Latch 0:7 IMB interrupt levels
01
00, 01, 00, 01....
Latch 0:15 IMB interrupt levels
10
00, 01, 10, 00, 01, 10,.....
Latch 0:23 IMB interrupt levels
11
00, 01, 10, 11, 00, 01, 10, 11,....
Latch 0:31 IMB interrupt levels
12.4.4 Interrupt Synchronizer
The interrupt synchronizer latches the 32 levels of interrupts from the IMB bus into a
register which can be read by the CPU or other U-bus master. Since there are only
eight lines for interrupts on the IMB and 32 levels of interrupts are possible, the 32
interrupt levels are multiplexed onto eight IMB interrupt lines. Apart from latching these
interrupts in the register (UIPEND register), the interrupt synchronizer drives the interrupts onto the U-bus, where they are latched by the interrupt controller in the USIU.
If IMB modules drive interrupts on any of the 24 levels (levels eight through 31), they
will be latched in the Interrupt pending register (UIPEND) in the UIMB. If any of the reg-
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U-BUS TO IMB3 BUS INTERFACE (UIMB)
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MOTOROLA
12-5
ister bits 7 to 31 are set, then bit 7 will be set as well. Software must poll this register
to find out which of the levels 7 to 31 are asserted.
The UIPEND register contains a status bit for each of the 32 interrupt levels. Each bit
of the register is a read-only status bit, reflecting the current state of the corresponding
interrupt signal. For each of the 32 interrupt levels, a corresponding bit of the UIPEND
register is set.
Figure 12-4 shows how the eight interrupt lines are connected to the UIPEND register
to represent 32 levels of interrupts. Figure 12-6 shows the implementation of the interrupt synchronizer.
UIPEND
U-bus Interrupt Level[0:7]
LVL 0-7
8
7
LVL7
IMB LVL [0:7]
OR
LVL 8-31
24
RESET
State
Machine
32
IMBCLOCK
U-bus
Data[0:31]
ILBS [0:1]
4
Figure 12-6 Interrupt Synchronizer Block diagram
12.5 Programming Model
Table 12-5 lists the registers used for configuring and testing the UIMB module. The
address offset shown in this table is from the start of the block reserved for UIMB registers. As shown in Figure 1-3 in 1.3 MPC555 Address Map, this block begins at
offset 0x30 7F80 from the start of the MPC555 internal memory map (the last 128-byte
sub-block of the UIMB interface memory map).
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MPC555
USER’S MANUAL
Table 12-5 UIMB Interface Register Map
Access
Base Address
Register
S1
0x30 7F80
UIMB Module Configuration Register (UMCR)
See Table 12-6 for bit descriptions.
—
0x30 7F84 —
0x30 7F8C
Reserved
S/T
0x30 7F90
UIMB Test Control Register (UTSTCREG)
Reserved
—
0x30 7F94 —
0x30 7F9C
Reserved
S
0x30 7FA0
Interrupt Request Pending (UIPEND)
See 12.5.3 Pending Interrupt Request Register
(UIPEND) for bit descriptions.
NOTES:
1. S = Supervisor mode only, T = Test mode only
Any word, half-word or byte access to a 32-bit location within the UIMB interface register decode block that is unimplemented (defined as reserved) causes the UIMB
interface to asserting a data error exception on the U-bus.The entire 32-bit location
must be defined as reserved in order for a data error exception to be asserted.
Unimplemented bits in a register return zero when read.
12.5.1 UIMB Module Configuration Register (UMCR)
The UIMB module configuration register (UMCR) is accessible in supervisor mode
only.
UMCR — UIMB Module Configuration Register
MSB
0
1
STOP
IRQMUX
2
3
4
5
6
7
0x30 7F80
8
HSPEED
9
10
11
12
13
14
15
RESERVED
HRESET:
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
0
0
0
0
0
0
0
RESERVED
HRESET:
0
0
0
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0
0
0
0
0
0
U-BUS TO IMB3 BUS INTERFACE (UIMB)
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Table 12-6 UMCR Bit Settings
Bit(s)
Name
0
Description
Stop enable.
0 = Enable system clock for IMB bus
1 = Disable IMB system clock
STOP
To avoid complications at restart and data corruption, system software must stop each slave on
the IMB before setting the STOP bit. Software must also ensure that all IMB interrupts have been
serviced before setting this bit.
IRQMUX
Interrupt request multiplexing. These bits control the multiplexing of the 32 possible interrupt
requests onto the eight IMB interrupt request lines.
00 = Disables the multiplexing scheme on the interrupt controller within this interface. What this
means is that the IMB IRQ [0:7] signals are non-multiplexed, only providing 8 (0-7) interrupt
request lines to the interrupt controller
01 = Enables the IMB IRQ control logic to perform a 2-to-1 multiplexing to allow transferring of
16 (0-15) interrupt sources
10 = Enables the IMB IRQ control logic to perform a 3-to-1 multiplexing to allow transferring of
24 (0-23) interrupt sources
11 = Enables the IMB IRQ control logic to perform a 4-to-1 multiplexing to allow transferring of
32 (0-31) interrupt sources
3
HSPEED
Half speed. The HSPEED bit controls the frequency at which the IMB3 runs with respect to the
U-bus. This is a modify-once bit. Software can write the reset value of this bit any number of
times. However, once logic 0 is written to this location, any attempt to rewrite this bit to a logic 1
will have no effect.
0 = IMB frequency is the same as that of the U-bus
1 = IMB frequency is one half that of the U-bus
4:31
—
1:2
Reserved
12.5.2 Test control register (UTSTCREG)
The UTSTCREG register is used for factory testing only.
12.5.3 Pending Interrupt Request Register (UIPEND)
The UIPEND register is a read-only status register which reflects the state of the 32
interrupt levels. The state of the IRQ0 is shown in bit 0, the state of IRQ1 is shown in
bit 1 and so on. This register is accessible only in supervisor mode.
UIPEND — Pending Interrupt Request Register
0x30 7FA0
MSB
0
1
2
3
4
5
6
7
8
9
10
LVL0
LVL1
LVL2
LVL3
LVL4
LVL5
LVL6
LVL7
LVL8
LVL9
LVL0
11
12
13
14
15
LVL11 LVL12 LVL13 LVL14 LVL15
HRESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LVL16
0
LSB
31
IRQ17 LVL18 LVL19 LVL20 LVL21 LVL22 LVL23 LVL24 LVL25 LVL26 LVL27 LVL28 LVL29 LVL30 LVL31
HRESET:
0
0
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0
0
0
0
0
0
0
0
0
U-BUS TO IMB3 BUS INTERFACE (UIMB)
Revised 1 March 1999
0
0
0
0
0
MPC555
USER’S MANUAL
Table 12-7 UIPEND Bit Settings
Bit(s)
Name
Description
0:31
LVLx
Pending interrupt request level. Accessible only in supervisor mode. LVLx identifies the interrupt
source as UIMB LVLx, where x is the interrupt number.
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U-BUS TO IMB3 BUS INTERFACE (UIMB)
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USER’S MANUAL
SECTION 13
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
The MPC555 includes two independent queued analog-to-digital converter (QADC64)
modules. For details of QADC64 operation not included in this section, refer to the
QADC Reference Manual (QADCRM/AD).
13.1 Overview
The QADC64 consists of an analog front-end and a digital control subsystem, which
includes an intermodule bus (IMB3) interface block. Refer to Figure 13-1.
The analog section includes input pins, channel selection logic, an analog multiplexer,
and one sample-and-hold analog circuit. The analog conversion is performed by the
digital-to-analog converter (DAC) resistor-capacitor array, a high-gain comparator,
and a successive approximation register (SAR).
The digital control section contains the conversion sequencing logic. Also included are
the periodic/interval timer, control and status registers, the conversion command word
(CCW) table RAM, and the result word table RAM.
EXTERNAL
TRIGGERS
EXTERNAL
MUX ADDRESS
UP TO 16 ANALOG
INPUT PINS
REFERENCE
INPUTS
ANALOG POWER
INPUTS
ANALOG INPUT MULTIPLEXER AND
DIGITAL PIN FUNCTIONS
DIGITAL
CONTROL
10-BIT ANALOG TO DIGITAL CONVERTER
QUEUE OF 10-BIT CONVERSION
COMMAND WORDS (CCW), 64 ENTRIES
INTERMODULE BUS
INTERFACE
10-BIT RESULT TABLE,
64 ENTRIES
10-BIT TO 16-BIT
RESULT ALIGNMENT
IMB
Figure 13-1 QADC64 Block Diagram
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13.2 Features
Each QADC64 module offers the following features:
• Internal sample and hold
• Up to 16 analog input channels using internal multiplexing
• Directly supports up to four external multiplexers (for example, the MC14051)
• Up to 41 total input channels with internal and external multiplexing
• Programmable input sample time for various source impedances
• Two conversion command queues with a total of 64 entries
• Sub-queues possible using pause mechanism
• Queue complete and pause software interrupts available on both queues
• Queue pointers indicate current location for each queue
• Automated queue modes initiated by:
— External edge trigger [queues 1 and 2] and gated mode [queue 1 only]
— Periodic/interval timer, within QADC64 module [queues 1 and 2]
— Software command [queues 1 and 2]
• Single-scan or continuous-scan of queues
• 64 result registers
• Output data readable in three formats:
— Right-justified unsigned
— Left-justified signed
— Left-justified unsigned
• Unused analog channels can be used as digital ports
13.3 QADC64 Pin Functions
The two QADC64 modules use the following 38 pins:
• Two analog reference pins, to which all analog input voltages are scaled (shared
by the two modules)
• 32 analog input pins (16 per module, with three analog inputs per module multiplexed with multiplex address signals)
• Two analog power pins (shared by the two modules)
• Two external trigger pins (shared by the two modules)
The 16 channel/port pins in either module can support up to 41 channels when external multiplexing is used (including internal channels). All of the channel pins can also
be used as general-purpose digital port pins.
The following paragraphs describe QADC64 pin functions. Figure 13-2 shows the
QADC64 module pins.
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VSS
DIGITAL POWER
(SHARED W/ OTHER MODULES) VDD
VRH
VRL
OUTPUT DRIVER GROUND
VSSE
OUTPUT DRIVER SUPPLY
VDDH
PORT B ANALOG
INPUTS, EXT MUX
INPUTS,
DIGITAL INPUTS
PORT A ANALOG
INPUTS, EXT MUX
ADDRESS OUTPUTS,
DIGITAL I/O
AN0/ANW/PQB0
AN1/ANX/PQB1
AN2/ANY/PQB2
AN3/ANZ/PQB3
AN48/PQB4
AN49/PQB5
AN50/PQB6
AN51/PQB7
AN52/MA0/PQA0
AN53/MA1/PQA1
AN54/MA2/PQA2
AN55/PQA3
AN56/PQA4
AN57/PQA5
AN58/PQA6
AN59/PQA7
PORT B
ANALOG REFERENCES
VSSA
VDDA
QADC64
ANALOG
MULTIPLEXER
ANALOG
CONVERTER
DIGITAL RESULTS
AND CONTROL
PORT A
ANALOG POWER & GROUND
ETRIG1
ETRIG2
QADC64 PINOUT
Figure 13-2 QADC64 Input and Output Signals
13.3.1 Port A Pin Functions
The eight port A pins can be used as analog inputs, or as a bi-directional 8-bit digital
input/output port.
13.3.1.1 Port A Analog Input Pins
When used as analog inputs, the eight port A pins are referred to as AN[59:52]. Due
to the digital output drivers associated with port A, the analog characteristics of port A
are different from those of port B. All of the analog signal input pins may be used for
at least one other purpose.
13.3.1.2 Port A Digital Input/Output Pins
Port A pins are referred to as PQA when used as a bidirectional 8-bit digital input/output port. These eight pins may be used for general-purpose digital input signals or
digital output signals.
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Port A pins are connected to a digital input synchronizer during reads and may be used
as general purpose digital inputs. Since port A read captures the data on all pins,
including those used for digital outputs or analog inputs, the user should employ a
“masking” operation to filter the inappropriate bits from the input byte.
Each port A pin is configured as an input or output by programming the port data
direction register (DDRQA). Digital input signal states are read into the PORTQA data
register when DDRQA specifies that the pins are inputs. Digital data in PORTQA is
driven onto the port A pins when the corresponding bits in DDRQA specify outputs.
13.3.2 Port B Pin Functions
The eight port B pins can be used as analog inputs, or as an 8-bit digital input-only port.
Refer to the following paragraphs for more information.
13.3.2.1 Port B Analog Input Pins
When used as analog inputs, the eight port B pins are referred to as AN[51:48]/
AN[3:0]. Since port B functions as analog and digital input-only, the analog characteristics are different from those of port A. All of the analog signal input pins may be used
for at least one other purpose.
13.3.2.2 Port B Digital Input Pins
Port B pins are referred to as PQB[7:0] when used as an 8-bit digital input-only port.
In addition to functioning as analog input pins, the port B pins are also connected to
the input of a synchronizer during reads and may be used as general-purpose digital
inputs.
Since port B pins are input-only, there is no associated data direction register. Digital
input signal states are read from the PORTQB data register. Since a port B read captures the data on all pins, including those used for analog inputs, the user should
employ a “masking” operation to filter the inappropriate bits from the input byte.
13.3.3 External Trigger Input Pins
The QADC64 has two external trigger pins (ETRIG[2:1]). Each of the two external trigger pins is associated with one of the scan queues. When a queue is in external trigger
mode, the corresponding external trigger pin is configured as a digital input.
13.3.4 Multiplexed Address Output Pins
In non-multiplexed mode, the 16 channel pins are connected to an internal multiplexer
which routes the analog signals into the A/D converter.
In externally multiplexed mode, the QADC64 allows automatic channel selection
through up to four external 1-of-8 multiplexer chips. The QADC64 provides a 3-bit multiplexed address output to the external multiplexer chips to allow selection of one of
eight inputs. The multiplexed address output signals MA[2:0] can be used as multiplex
address output bits or as general-purpose I/O.
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When externally-multiplexed mode is enabled, MA[2:0] are used as the address inputs
for up to four 1-of-8 multiplexer chips (for example, the MC14051 and the
MC74HC4051). Since MA[2:0] are digital outputs in multiplexed mode, the software
programmed input/output direction and data for these pins in DDQA[2:0], DDRQA, and
PQA[2:0] is ignored, and the value for MA[2:0] is taken from the currently executing
CCW.
13.3.5 Multiplexed Analog Input Pins
In externally-multiplexed mode, four of the port B pins are redefined to each represent
a group of eight input channels. Refer to Table 13-1.
The analog output of each external multiplexer chip is connected to one of the AN[w,
x, y, z] inputs in order to convert a channel selected by the MA[2:0] multiplexed
address outputs.
Table 13-1 Multiplexed Analog Input Channels
Multiplexed Analog Input
ANw
ANx
ANy
ANz
Channels
Even-numbered channels from 0 to 14
Odd-numbered channels from 1 to 15
Even-numbered channels from 16 to 30
Odd-numbered channels from 17 to 31
13.3.6 Voltage Reference Pins
VRH and VRL are the dedicated input pins for the high and low reference voltages.
Separating the reference inputs from the power supply pins allows for additional external filtering, which increases reference voltage precision and stability, and
subsequently contributes to a higher degree of conversion accuracy.
13.3.7 Dedicated Analog Supply Pins
VDDA and VSSA pins supply power to the analog subsystems of the QADC64 module. Dedicated power is required to isolate the sensitive analog circuitry from the
normal levels of noise present on the digital power supply.
13.3.8 External Digital Supply Pin
Each port A pin includes a digital output driver, an analog input signal path, and a digital input synchronizer. The VSS pin provides the ground level for the drivers on the
port A pins. VDDH provides the supply level for the drivers on port A pins.
13.3.9 Digital Supply Pins
VDD and VSS provide the power for the digital portions of the QADC64, and for all
other digital MCU modules.
13.4 QADC64 Bus Interface
The QADC64 supports to 8-bit, 16-bit, and 32-bit data transfers, at even and odd
addresses. Coherency of results read, (ensuring that all results read were taken conMPC555
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secutively in one scan) is not guaranteed. For example, if two consecutive 16-bit
locations in a result area are read, the QADC64 could change one 16-bit location in
the result area between the bus cycles. There is no holding register for the second 16bit location. All read and write accesses that require more than one 16-bit access to
complete occur as two or more independent bus cycles. Depending on bus master
protocol, these accesses could include misaligned and 32-bit accesses.
Normal reads-from and writes-to the QADC64 require two clock cycles. However, if the
CPU tries to access locations that are also accessible to the QADC64 while the
QADC64 is accessing them, the bus cycle will require additional clock cycles. The
QADC64 may insert from one to four wait states in the process of a CPU read from or
write to such a location.
13.5 Module Configuration
The QADC64 module configuration register (QADC64MCR) defines freeze and stop
mode operation, supervisor space access, and interrupt arbitration priority. Unimplemented bits read zero and writes have no effect. QADC64MCR is typically written once
when software initializes the QADC64, and not changed thereafter. Refer to 13.12.1
QADC64 Module Configuration Register for register and bit descriptions.
13.5.1 Low-Power Stop Mode
When the STOP bit in QADC64MCR is set, the clock signal to the A/D converter is disabled, effectively turning off the analog circuitry. This results in a static, low power
consumption, idle condition. Low-power stop mode aborts any conversion sequence
in progress. Because the bias currents to the analog circuits are turned off in lowpower stop mode, the QADC64 requires some recovery time to stabilize the analog
circuits after the STOP bit is cleared.
In low-power stop mode, the BIU state machine and logic do not shut down, and the
QADC64MCR, the interrupt register (QADC64INT), and the test register
(QADC64TEST) are fully accessible and are not reset. The data direction register
(DDRQA), port data register (PORTQA/PORTQB), and control register zero (QACR0)
are not reset and are read-only accessible. The RAM is not reset and is not accessible.
Control register one (QACR1), control register two (QACR2), and the status registers
(QASR0 and QASR1) are reset and are read-only accessible. In addition, the periodic/
interval timer is held in reset during stop mode.
If the STOP bit is clear, low-power stop mode is disabled. The STOP bit must be clear
to program CCWs into RAM or read results from RAM.
13.5.2 Freeze Mode
The QADC64 enters freeze mode when background debug mode is enabled and a
breakpoint is processed. This is indicated by assertion of the FREEZE line on the
IMB3. The FRZ bit in QADC64MCR determines whether or not the QADC64 responds
to an IMB FREEZE assertion. Freeze mode is useful when debugging an application.
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When the IMB FREEZE line is asserted and the FRZ bit is set, the QADC64 finishes
any conversion in progress and then freezes. Depending on when the FREEZE is
asserted, there are three possible queue freeze scenarios:
• When a queue is not executing, the QADC64 freezes immediately
• When a queue is executing, the QADC64 completes the current conversion and
then freezes
• If during the execution of the current conversion, the queue operating mode for
the active queue is changed, or a queue 2 abort occurs, the QADC64 freezes immediately
When the QADC64 enters the freeze mode while a queue is active, the current CCW
location of the queue pointer is saved.
During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer
is held in reset. External trigger events that occur during the freeze mode are not captured. The BIU remains active to allow IMB access to all QADC64 registers and RAM.
Although the QADC64 saves a pointer to the next CCW in the current queue, the software can force the QADC64 to execute a different CCW by writing new queue
operating modes for normal operation. The QADC64 looks at the queue operating
modes, the current queue pointer, and any pending trigger events to decide which
CCW to execute.
If the FRZ bit is clear, assertion of the IMB FREEZE line is ignored.
13.5.3 Supervisor/Unrestricted Address Space
The QADC64 memory map is divided into two segments: supervisor-only data space
and assignable data space. Access to supervisor-only data space is permitted only
when the CPU is operating in supervisor mode. Assignable data space can have either
restricted to supervisor-only data space access or unrestricted supervisor and user
data space accesses. The SUPV bit in QADC64MCR designates the assignable
space as supervisor or unrestricted.
Attempts to read or write supervisor-only data space when the CPU is not in supervisor
mode cause the bus master to assert the internal transfer error acknowledge (TEA)
signal.
The supervisor-only data space segment contains the QADC64 global registers, which
include QADC64MCR, QADC64TEST, and QADC64INT. The supervisor/unrestricted
space designation for the CCW table, the result word table, and the remaining
QADC64 registers is programmable.
13.6 General-Purpose I/O Port Operation
QADC64 port pins, when used as general-purpose input, are conditioned by a synchronizer with an enable feature. The synchronizer is not enabled until the QADC64
decodes an IMB bus cycle which addresses the port data register to minimize the highcurrent effect of mid-level signals on the inputs used for analog signals. Digital input
signals must meet the input low voltage (VIL) or input high voltage (VIH) specifications.
If an analog input pin does not meet the digital input pin specifications when a digital
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port read operation occurs, an indeterminate state is read. To avoid reading inappropriate values on analog inputs, the user software should employ a “masking”
operation.
During a port data register read, the actual value of the pin is reported when its corresponding bit in the data direction register defines the pin to be an input (port A only).
When the data direction bit specifies the pin to be an output, the content of the port
data register is read. By reading the latch which drives the output pin, software instructions that read data, modify it, and write the result, like bit manipulation instructions,
work correctly.
There is one special case to consider for digital I/O port operation. When the MUX
(externally multiplexed) bit is set in QACR0, the data direction register settings are
ignored for the bits corresponding to PQA[2:0], the three multiplexed address MA[2:0]
output pins. The MA[2:0] pins are forced to be digital outputs, regardless of the data
direction setting, and the multiplexed address outputs are driven. The data returned
during a port data register read is the value of the multiplexed address latches which
drive MA[2:0], regardless of the data direction setting.
13.6.1 Port Data Register
QADC64 ports A and B are accessed through two 8-bit port data registers (PORTQA
and PORTQB). Port A pins are referred to as PQA when used as an 8-bit input/output
port. Port A can also be used for analog inputs AN[59:52] and external multiplexer
address outputs MA[2:0].
Port B pins are referred to as PQB when used as an 8-bit input-only digital port. Port
B can also be used for non-multiplexed AN[51:48]/AN[3:0] and multiplexed ANz, ANy,
ANx, ANw analog inputs.
PORTQA and PORTQB are unaffected by reset. Refer to 13.12.4 Port A/B Data Register for register and bit descriptions.
13.6.2 Port Data Direction Register
The port data direction register (DDRQA) is associated with the port A digital I/O pins.
These bi-directional pins may have somewhat higher leakage and capacitance
specifications.
Any bit in this register set to one configures the corresponding pin as an output. Any
bit in this register cleared to zero configures the corresponding pin as an input. Software is responsible for ensuring that DDRQA bits are not set to one on pins used for
analog inputs. When a DDRQA bit is set to one and the pin is selected for analog conversion, the voltage sampled is that of the output digital driver as influenced by the
load.
NOTE
Caution should be exercised when mixing digital and analog inputs.
This should be minimized as much as possible. Input pin rise and fall
times should be as large as possible to minimize AC coupling effects.
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Since port B is input-only, a data direction register is not needed. Read operations on
the reserved bits in DDRQA return zeros, and writes have no effect. Refer to 13.12.5
Port Data Direction Register for register and bit descriptions.
13.7 External Multiplexing Operation
External multiplexers concentrate a number of analog signals onto a few inputs to the
analog converter. This is helpful in applications that need to convert more analog signals than the A/D converter can normally provide. External multiplexing also puts the
multiplexer closer to the signal source. This minimizes the number of analog signals
that need to be shielded due to the close proximity of noisy, high-speed digital signals
near the MCU.
The QADC64 can use from one to four external multiplexers to expand the number of
analog signals that may be converted. Up to 32 analog channels can be converted
through external multiplexer selection. The externally multiplexed channels are automatically selected from the channel field of the CCW table, the same as internally
multiplexed channels.
All of the automatic queue features are available for externally and internally multiplexed channels. The software selects externally multiplexed mode by setting the
MUX bit in QACR0.
Figure 13-3 shows the maximum configuration of four external multiplexers connected
to the QADC64. The external multiplexers select one of eight analog inputs and connect it to one analog output, which becomes an input to the QADC64. The QADC64
provides three multiplexed address signals (MA[2:0]), to select one of eight inputs.
These outputs are connected to all four multiplexers. The analog output of each multiplexer is each connected to one of four separate QADC64 inputs — ANw, ANx, ANy,
and ANz.
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AN0
AN2
AN4
AN6
AN8
AN10
AN12
AN14
MUX
VSSA
VDDA
ANALOG POWER
V RH
VRL
ANALOG REFERENCES
VSSE
VDDH
MUX
MUX
AN17
AN19
AN21
AN23
AN25
AN27
AN29
AN31
MUX
QADC64
PORT B
AN16
AN18
AN20
AN22
AN24
AN26
AN28
AN30
AN0/ANW/PQB0
AN1/ANX/PQB1
AN2/ANY/PQB2
AN3/ANZ/PQB3
AN48/PQB4
AN49/PQB5
AN50/PQB6
AN51/PQB7
AN52/MA0/PQA0*
AN53/MA1/PQA1*
AN54/MA2/PQA2*
AN55/PQA3*
AN56/PQA4*
AN57/PQA5*
AN58/PQA6*
AN59/PQA7*
ANALOG
MULTIPLEXER
ANALOG
CONVERTER
DIGITAL RESULTS
AND CONTROL
PORT A
AN1
AN3
AN5
AN7
AN9
AN11
AN13
AN15
ETRIG1
ETRIG2
EXTERNAL TRIGGERS
Figure 13-3 Example of External Multiplexing
When the external multiplexed mode is selected, the QADC64 automatically creates
the MA[2:0] output signals from the channel number in each CCW. The QADC64 also
converts the proper input channel (ANw, ANx, ANy, and ANz) by interpreting the CCW
channel number. As a result, up to 32 externally multiplexed channels appear to the
conversion queues as directly connected signals. Software simply puts the channel
number of an externally multiplexed channel into a CCW.
Figure 13-3 shows that MA[2:0] may also be analog or digital input pins. When external multiplexing is selected, none of the MA[2:0] pins can be used for analog or digital
inputs. They become multiplexed address outputs.
13.8 Analog Input Channels
The number of available analog channels varies, depending on whether or not external
multiplexing is used. A maximum of 16 analog channels are supported by the internal
multiplexing circuitry of the converter. Table 13-2 shows the total number of analog
input channels supported with zero to four external multiplexers.
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Table 13-2 Analog Input Channels
Number of Analog Input Channels Available
Directly Connected + External Multiplexed = Total Channels1
No External
One External
Two External
Three External
Four External
MUX Chips
MUX Chip
MUX Chips
MUX Chips
MUX Chips
16
12 + 8 = 20
11 + 16 = 27
10 + 24 = 34
9 + 32 = 41
NOTES:
1. When external multiplexing is used, three input channels become multiplexed address outputs, and for each external multiplexer chip, one input channel becomes a multiplexed analog input.
13.9 Analog Subsystem
The QADC64 analog subsystem includes a front-end analog multiplexer, a digital to
analog converter (DAC) array, a comparator, and a successive approximation register
(SAR).
The analog subsystem path runs from the input pins through the input multiplexing circuitry, into the DAC array, and through the analog comparator. The output of the
comparator feeds into the SAR.
Figure 13-4 shows a block diagram of the QADC64 analog submodule.
PQA7
CCW
CCW
10
BUF
INPUT
PQA0
PQB7
2
BIAS CIRCUIT
SAMPLE
BUFFER
POWER
DOWN
STOP
RST
PQB0
QCLK
CSAMP
STATE MACHINE & LOGIC
WCCW
END OF CONV.
END OF SMP
SAR Timing
VRH
10 BIT RC
DAC
SAR
10
VRL
SIGNALS FROM/TO QUEUE CONTROL LOGIC
CHAN.[5:0]
IST
10 BIT A/D CONVERTER
6
BYP
CHAN. DECODE & MUX
16: 1
10
SAR
BUF
10
RSAR
VDDA
ANALOG
POWER
VSSA
COMPARATOR
SUCCESSIVE
APPROXIMATION
REGISTER
QADC64 DETAIL BLOCK
Figure 13-4 QADC64 Module Block Diagram
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13.9.1 Conversion Cycle Times
Total conversion time is made up of initial sample time, final sample time, and resolution time. Initial sample time refers to the time during which the selected input channel
is driven by the buffer amplifier onto the sample capacitor. The buffer amplifier can be
disabled by means of the BYP bit in the CCW. During the final sampling period, amplifier is bypassed, and the multiplexer input charges the RC DAC array directly. During
the resolution period, the voltage in the RC DAC array is converted to a digital value
and stored in the SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16
QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is
ten QCLK cycles.
Sample and resolution require a minimum of 14 QCLK clocks (7 µs with a 2-MHz
QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total
conversion time is 13.0 µs with a 2-MHz QCLK.
Figure 13-5 illustrates the timing for conversions. This diagram assumes a final
sampling period of two QCLK cycles.
BUFFER FINAL SAMPLE
TIME
SAMPLE
N CYCLES:
TIME
2 CYCLES
(2, 4, 8, 16)
RESOLUTION
TIME
10 CYCLES
QCLK
SAMPLE TIME
SUCCESSIVE APPROXIMATION RESOLUTION
SEQUENCE
Figure 13-5 Conversion Timing
13.9.1.1 Amplifier Bypass Mode Conversion Timing
If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass
(BYP) bit in the CCW, the timing changes to that shown in Figure 13-6. The buffered
sample time is eliminated, reducing the potential conversion time by two QCLKs. However, due to internal RC effects, a minimum final sample time of four QCLKs must be
allowed. This results in no savings of QCLKs. When using the bypass mode, the external circuit should be of low source impedance, typically less than 10 kΩ. Also, the
loading effects of the external circuitry by the QADC64 need to be considered, since
the benefits of the sample amplifier are not present.
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NOTE
Because of internal RC time constants, a sample time of two QCKLs
in bypass mode for high frequency operation is not recommended.
SAMPLE
TIME
N CYCLES:
(2, 4, 8, 16)
RESOLUTION
TIME
10 CYCLES
SAMPLE
TIME
SUCCESSIVE APPROXIMATION RESOLUTION
SEQUENCE
QCLK
Figure 13-6 Bypass Mode Conversion Timing
13.9.2 Front-End Analog Multiplexer
The internal multiplexer selects one of the 16 analog input pins or one of three special
internal reference channels for conversion. The following are the three special
channels:
• VRH — Reference Voltage High
• VRL — Reference Voltage Low
• (VRH – VRL)/2 — Mid-Reference Voltage
The selected input is connected to one side of the DAC capacitor array. The other side
of the DAC array is connected to the comparator input. The multiplexer also includes
positive and negative stress protection circuitry, which prevents other channels from
affecting the present conversion when excessive voltage levels are applied to the
other channels.
13.9.3 Digital-to-Analog Converter Array
The digital-to-analog converter (DAC) array consists of binary-weighted capacitors
and a resistor-divider chain. The array serves two purposes:
• The array holds the sampled input voltage during conversion
• The resistor-capacitor array provides the mechanism for the successive approximation A/D conversion
Resolution begins with the MSB and works down to the LSB. The switching sequence
is controlled by the SAR logic.
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13.9.4 Comparator
The comparator is used during the approximation process to sense whether the digitally selected arrangement of the DAC array produces a voltage level higher or lower
than the sampled input. The comparator output feeds into the SAR which accumulates
the A/D conversion result sequentially, starting with the MSB.
13.9.5 Successive Approximation Register
The input of the successive approximation register (SAR) is connected to the comparator output. The SAR sequentially receives the conversion value one bit at a time,
starting with the MSB. After accumulating the ten bits of the conversion result, the SAR
data is transferred by the queue control logic in the digital section to the appropriate
result location, where it may be read by user software.
13.10 Digital Control Subsystem
The digital control subsystem includes the clock and periodic/interval timer, control
and status registers, the conversion command word table RAM, and the result word
table RAM.
The central element for control of the QADC64 conversions is the 64-entry CCW table.
Each CCW specifies the conversion of one input channel. Depending on the application, one or two queues can be established in the CCW table. A queue is a scan
sequence of one or more input channels. By using a pause mechanism, sub-queues
can be created within the two queues. Each queue can be operated using several different scan modes. The scan modes for queue 1 and queue 2 are programmed in
QACR1 and QACR2. Once a queue has been started by a trigger event (any of the
ways to cause the QADC64 to begin executing the CCWs in a queue or sub-queue),
the QADC64 performs a sequence of conversions and places the results in the result
word table.
13.10.1 Queue Priority
Queue 1 has execution priority over queue 2 execution. Table 13-3 shows the conditions under which queue 1 asserts its priority:
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Table 13-3 Queue 1 Priority Assertion
Queue State
Inactive
Queue 1 active/trigger event
occurs for Queue 2
Queue 2 active/trigger event
occurs for Queue 1
Result
A trigger event for queue 1 or queue 2 causes the corresponding queue execution to
begin.
Queue 2 cannot begin execution until queue 1 reaches completion or the paused
state. The status register records the trigger event by reporting the queue 2 status as
trigger pending. Additional trigger events for queue 2, which occur before execution
can begin, are recorded as trigger overruns.
The current queue 2 conversion is aborted. The status register reports the queue 2
status as suspended. Any trigger events occurring for queue 2 while queue 2 is suspended are recorded as trigger overruns. Once queue 1 reaches the completion or
the paused state, queue 2 begins executing again. The programming of the resume
bit in QACR2 determines which CCW is executed in queue 2.
Simultaneous trigger events
Queue 1 begins execution and the queue 2 status is changed to trigger pending.
occur for Queue 1 and Queue 2
The pause feature can be used to divide queue 1 and/or queue 2 into multiple subsub-queues paused
queues. A sub-queue is defined by setting the pause bit in the last CCW of the subqueue.
Figure 13-7 shows the CCW format and an example of using pause to create subqueues. Queue 1 is shown with four CCWs in each sub-queue and queue 2 has two
CCWs in each sub-queue.
CONVERSION COMMAND WORD
(CCW) TABLE
P
00
0
RESULT WORD TABLE
00
BEGIN QUEUE 1
0
CHANNEL SELECT,
SAMPLE, HOLD,
AND A/D
CONVERSION
0
1
PAUSE
0
0
0
1
PAUSE
0
P
0
0
BQ2 0
1
END OF QUEUE 1
BEGIN QUEUE 2
PAUSE
0
1
PAUSE
0
1
PAUSE
0
P
1
63
0
PAUSE
63
END OF QUEUE 2
QADC64 CQP
Figure 13-7 QADC64 Queue Operation with Pause
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The queue operating mode selected for queue 1 determines what type of trigger event
causes the execution of each of the sub-queues within queue 1. Similarly, the queue
operating mode for queue 2 determines the type of trigger event required to execute
each of the sub-queues within queue 2.
The choice of single-scan or continuous-scan applies to the full queue, and is not
applied to each sub-queue. Once a sub-queue is initiated, each CCW is executed
sequentially until the last CCW in the sub-queue is executed and the pause state is
entered. Execution can only continue with the next CCW, which is the beginning of the
next sub-queue. A sub-queue cannot be executed a second time before the overall
queue execution has been completed.
Trigger events which occur during the execution of a sub-queue are ignored, except
that the trigger overrun flag is set. When continuous-scan mode is selected, a trigger
event occurring after the completion of the last sub-queue (after the queue completion
flag is set), causes execution to continue with the first sub-queue, starting with the first
CCW in the queue.
When the QADC64 encounters a CCW with the pause bit set, the queue enters the
paused state after completing the conversion specified in the CCW with the pause bit.
The pause flag is set and a pause software interrupt may optionally be issued. The status of the queue is shown to be paused, indicating completion of a sub-queue. The
QADC64 then waits for another trigger event to again begin execution of the next subqueue.
13.10.2 Queue Boundary Conditions
The following are queue operation boundary conditions:
• The first CCW in a queue contains channel 63, the end-of-queue (EOQ) code.
The queue becomes active and the first CCW is read. The end-of-queue is recognized, the completion flag is set, and the queue becomes idle. A conversion is
not performed.
• BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger
event occurs on queue 2. 13.12.6 QADC64 Control Register 0 (QACR0) on
BQ2. The end-of-queue condition is recognized, a conversion is performed, the
completion flag is set, and the queue becomes idle.
• BQ2 is set to CCW0 and a trigger event occurs on queue 1. After reading CCW0,
the end-of-queue condition is recognized, the completion flag is set, and the
queue becomes idle. A conversion is not performed.
• BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64 - 127)
and a trigger event occurs on queue 2. Refer to 7.6.3 Control Register two for information on BQ2. The end-of-queue condition is recognized immediately, the
completion flag is set, and the queue becomes idle. A conversion is not performed.
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NOTE
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in the QADC64 behavior. For example,
if BQ2 is set to CCW0, CCW0 contains the EOQ code, and a trigger
event occurs on queue 1, the QADC64 reads CCW0 and detects
both end-of-queue conditions. The completion flag is set for queue 1
only and it becomes idle.
Boundary conditions also exist for combinations of pause and end-of-queue. One case
is when a pause bit is in one CCW and an end-of-queue condition is in the next CCW.
The conversion specified by the CCW with the pause bit set completes normally. The
pause flag is set. However, since the end-of-queue condition is recognized, the completion flag is also set and the queue status becomes idle, not paused. Examples of
this situation include:
• The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6
• The pause bit is set in CCW63
• During queue 1 operation, the pause bit is set in CCW14 and BQ2 points to
CCW15
Another pause and end-of-queue boundary condition occurs when the pause and an
end-of-queue condition occur in the same CCW. Both the pause and end-of-queue
conditions are recognized simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW and the pause flag is not set. The
QADC64 sets the completion flag and the queue status becomes idle. Examples of
this situation are:
• The pause bit is set in CCW0 and EOQ is programmed into CCW0
• During queue 1 operation, the pause bit is set in CCW20, which is also BQ2
13.10.3 Scan Modes
The QADC64 queuing mechanism provides several methods for automatically scanning input channels. In single-scan mode, a single pass through a sequence of
conversions defined by a queue is performed. In continuous-scan mode, multiple
passes through a sequence of conversions defined by a queue are executed. The possible modes are:
• Disabled and reserved mode
• Software initiated single-scan mode
• External trigger single-scan mode
• External gated single-scan mode (queue 1 only)
• Interval timer single-scan mode
• Software initiated continuous-scan mode
• External trigger continuous-scan mode
• External gated continuous-scan mode (queue 1 only)
• Interval timer continuous-scan mode
The following paragraphs describe the disabled/reserved, single-scan, and continuous-scan operations.
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13.10.3.1 Disabled Mode
When the disabled mode is selected, the queue is not active. Trigger events cannot
initiate queue execution. When both queue 1 and queue 2 are disabled, wait states are
not encountered for IMB accesses of the RAM. When both queues are disabled, it is
safe to change the QCLK prescaler values.
13.10.3.2 Reserved Mode
Reserved mode allows for future mode definitions. When the reserved mode is
selected, the queue is not active.
CAUTION
Do not use a reserved mode. Unspecified operations may result.
13.10.3.3 Single-Scan Modes
When the application software wants to execute a single pass through a sequence of
conversions defined by a queue, a single-scan queue operating mode is selected. By
programming the MQ field in QACR1 or QACR2, the following modes can be selected:
• Software initiated single-scan mode
• External trigger single-scan mode
• External gated single-scan mode (queue 1 only)
• Interval timer single-scan mode
NOTE
Queue 2 can not be programmed for external gated single-scan
mode.
In all single-scan queue operating modes, the software must also enable the queue to
begin execution by writing the single-scan enable bit to a one in the queue’s control
register. The single-scan enable bits, SSE1 and SSE2, are provided for queue 1 and
queue 2 respectively.
Until the single-scan enable bit is set, any trigger events for that queue are ignored.
The single-scan enable bit may be set to a one during the write cycle, which selects
the single-scan queue operating mode. The single-scan enable bit can be written as a
one or a zero, but is always read as a zero. The completion flag, completion interrupt,
or queue status are used to determine when the queue has completed.
After the single-scan enable bit is set, a trigger event causes the QADC64 to begin
execution with the first CCW in the queue. The single-scan enable bit remains set until
the queue is completed. After the queue reaches completion, the QADC64 resets the
single-scan enable bit to zero. If the single-scan enable bit is written to a one or a zero
by the software before the queue scan is complete, the queue is not affected. However, if the software changes the queue operating mode, the new queue operating
mode and the value of the single-scan enable bit are recognized immediately. The
conversion in progress is aborted and the new queue operating mode takes effect.
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In the software initiated single-scan mode, the writing of a one to the single-scan
enable bit causes the QADC64 to internally generate a trigger event and the queue
execution begins immediately. In the other single-scan queue operating modes, once
the single-scan enable bit is written, the selected trigger event must occur before the
queue can start. The single-scan enable bit allows the entire queue to be scanned
once. A trigger overrun is captured if a trigger event occurs during queue execution in
the external trigger single-scan mode and the interval timer single-scan mode.
In the interval timer single-scan mode, the next expiration of the timer is the trigger
event for the queue. After the queue execution is complete, the queue status is shown
as idle. The software can restart the queue by setting the single-scan enable bit to a
one. Queue execution begins with the first CCW in the queue.
Software Initiated Single-Scan Mode. Software can initiate the execution of a scan
sequence for queue 1 or 2 by selecting the software initiated single-scan mode, and
writing the single-scan enable bit in QACR1 or QACR2. A trigger event is generated
internally and the QADC64 immediately begins execution of the first CCW in the
queue. If a pause occurs, another trigger event is generated internally, and then execution continues without pausing.
The QADC64 automatically performs the conversions in the queue until an end-ofqueue condition is encountered. The queue remains idle until the software again sets
the single-scan enable bit. While the time to internally generate and act on a trigger
event is very short, software can momentarily read the status conditions, indicating
that the queue is paused. The trigger overrun flag is never set while in the software
initiated single-scan mode.
The software initiated single-scan mode is useful in the following applications:
• Allows software complete control of the queue execution
• Allows the software to easily alternate between several queue sequences
External Trigger Single-Scan Mode. The external trigger single-scan mode is a variation of the external trigger continuous-scan mode, and is also available with both
queue 1 and queue 2. The software programs the polarity of the external trigger edge
that is to be detected, either a rising or a falling edge. The software must enable the
scan to occur by setting the single-scan enable bit for the queue.
The first external trigger edge causes the queue to be executed one time. Each CCW
is read and the indicated conversions are performed until an end-of-queue condition
is encountered. After the queue is completed, the QADC64 clears the single-scan
enable bit. Software may set the single-scan enable bit again to allow another scan of
the queue to be initiated by the next external trigger edge.
The external trigger single-scan mode is useful when the input trigger rate can exceed
the queue execution rate. Analog samples can be taken in sync with an external event,
even though the software is not interested in data taken from every edge. The software
can start the external trigger single-scan mode and get one set of data, and at a later
time, start the queue again for the next set of samples.
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When a pause bit is encountered during external trigger single-scan mode, another
trigger event is required for queue execution to continue. Software involvement is not
needed to enable queue execution to continue from the paused state.
The external trigger single-scan mode is also useful when the software needs to
change the polarity of the external trigger so that both the rising and falling edges
cause queue execution.
External Gated Single-Scan Mode. The QADC64 provides external gating for queue
1 only. When external gated single-scan mode is selected, a transition on the associated external trigger pin initiates queue execution. The polarity of the external gated
signal is fixed so only a high level opens the gate and a low level closes the gate. Once
the gate is open, each CCW is read and the indicated conversions are performed until
the gate is closed. Software must enable the scan to occur by setting the single-scan
enable bit for queue 1. If a pause in a CCW is encountered, the pause flag will not
set, and execution continues without pausing.
While the gate is open, queue 1 executes one time. Each CCW is read and the indicated conversions are performed until an end-of-queue condition is encountered.
When queue 1 completes, the QADC64 sets the completion flag (CF1) and clears the
single-scan enable bit. Software may set the single-scan enable bit again to allow
another scan of queue 1 to be initiated during the next open gate.
If the gate closes before queue 1 completes execution, the current CCW completes,
execution of queue 1 stops, the single-scan enable bit is cleared, and the PF1 bit is
set. Software can read the CWPQ1 to determine the last valid conversion in the queue.
Software must set the single-scan enable bit again and should clear the PF1 bit before
another scan of queue 1 is initiated during the next open gate. The start of queue 1 is
always the first CCW in the CCW table.
Interval Timer Single-Scan Mode. Both queues can use the periodic/interval timer in
a single-scan queue operating mode. The timer interval can range from 128 to 128
Kbytes times the QCLK period in binary multiples. When the interval timer single-scan
mode is selected and the software sets the single-scan enable bit in QACR1(2), the
timer begins counting. When the time interval elapses, an internal trigger event is created to start the queue and the QADC64 begins execution with the first CCW.
The QADC64 automatically performs the conversions in the queue until a pause or an
end-of-queue condition is encountered. When a pause occurs, queue execution stops
until the timer interval elapses again, and queue execution continues. When the queue
execution reaches an end of queue situation the single-scan enable bit is cleared.
Software may set the single-scan enable bit again, allowing another scan of the queue
to be initiated by the interval timer.
The interval timer generates a trigger event whenever the time interval elapses. The
trigger event may cause the queue execution to continue following a pause, or may be
considered a trigger overrun. Once the queue execution is completed, the single-scan
enable bit must be set again to enable the timer to count again.
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Normally only one queue will be enabled for interval timer single-scan mode and the
timer will reset at the end of queue. However, if both queues are enabled for either single-scan or continuous interval timer mode, the end of queue condition will not reset
the timer while the other queue is active. In this case, the timer will reset when both
queues have reached end of queue.
The interval timer single-scan mode can be used in applications which need coherent
results, for example:
• When it is necessary that all samples are guaranteed to be taken during the same
scan of the analog pins
• When the interrupt rate in the periodic timer continuous-scan mode would be too
high
• In sensitive battery applications, where the single-scan mode uses less power
than the software initiated continuous-scan mode
13.10.3.4 Continuous-Scan Modes
When the application software wants to execute multiple passes through a sequence
of conversions defined by a queue, a continuous-scan queue operating mode is
selected. By programming the MQ1(2) field in QACR1(2), the following software initiated modes can be selected:
• Software initiated continuous-scan mode
• External trigger continuous-scan mode
• External gated continuous-scan mode (queue 1 only)
• Interval timer continuous-scan mode
When a queue is programmed for a continuous-scan mode, the single-scan enable bit
in the queue control register does not have any meaning or effect. As soon as the
queue operating mode is programmed, the selected trigger event can initiate queue
execution.
In the case of the software initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. In the other continuous-scan
queue operating modes, the selected trigger event must occur before the queue can
start. A trigger overrun is captured if a trigger event occurs during queue execution in
the external trigger continuous-scan mode and the periodic timer continuous-scan
mode.
After the queue execution is complete, the queue status is shown as idle. Since the
continuous-scan queue operating modes allow the entire queue to be scanned multiple times, software involvement is not needed to enable queue execution to continue
from the idle state. The next trigger event causes queue execution to begin again,
starting with the first CCW in the queue.
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NOTE
In this version of QADC64, coherent samples can be guaranteed.
The time between consecutive conversions has been designed to be
consistent, provided the sample time bits in both the CCW and IST
are identical. However, there is one exception. For queues that end
with a CCW containing EOQ code (channel 63), the last queue conversion to the first queue conversion requires one additional CCW
fetch cycle. Therefore continuous samples are not coherent at this
boundary.
In addition, the time from trigger to first conversion can not be guaranteed since it is a function of clock synchronization, programmable
trigger events, queue priorities, and so on.
Software Initiated Continuous-Scan Mode. When the software initiated continuousscan mode is programmed, the trigger event is generated automatically by the
QADC64. Queue execution begins immediately. If a pause is encountered, another
trigger event is generated internally, and then execution continues without pausing.
When the end-of-queue is reached, another internal trigger event is generated, and
queue execution begins again from the beginning of the queue.
While the time to internally generate and act on a trigger event is very short, software
can momentarily read the status conditions, indicating that the queue is idle. The trigger overrun flag is never set while in the software initiated continuous-scan mode.
The software initiated continuous-scan mode keeps the result registers updated more
frequently than any of the other queue operating modes. The software can always
read the result table to get the latest converted value for each channel. The channels
scanned are kept up-to-date by the QADC64 without software involvement. Software
can read a result value at any time.
The software initiated continuous-scan mode may be chosen for either queue, but is
normally used only with queue 2. When the software initiated continuous-scan mode
is chosen for queue 1, that queue operates continuously and queue 2, being lower in
priority, never gets executed. The short interval of time between a queue 1 completion
and the subsequent trigger event is not sufficient to allow queue 2 execution to begin.
The software initiated continuous-scan mode is a useful choice with queue 2 for converting channels that do not need to be synchronized to anything, or for the slow-tochange analog channels. Interrupts are normally not used with the software initiated
continuous-scan mode. Rather, the software reads the latest conversion result from
the result table at any time. Once initiated, software action is not needed to sustain
conversions of channel. Data read at different locations, however, may or may not be
coherent (that is, from the same queue scan sequence).
External Trigger Continuous-Scan Mode. The QADC64 provides external trigger
pins for both queues. When the external trigger software initiated continuous-scan
mode is selected, a transition on the associated external trigger pin initiates queue
execution. The polarity of the external trigger signal is programmable, so that the softMOTOROLA
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USER’S MANUAL
ware can choose to begin queue execution on the rising or falling edge. Each CCW is
read and the indicated conversions are performed until an end-of-queue condition is
encountered. When the next external trigger edge is detected, the queue execution
begins again automatically. Software initialization is not needed between trigger
events.
When a pause bit is encountered in external trigger continuous-scan mode, another
trigger event is required for queue execution to continue. Software involvement is not
needed to enable queue execution to continue from the paused state.
Some applications need to synchronize the sampling of analog channels to external
events. There are cases when it is not possible to use software initiation of the queue
scan sequence, since interrupt response times vary.
External Gated Continuous-Scan Mode. The QADC64 provides external gating for
queue 1 only. When external gated continuous-scan mode is selected, a transition on
the associated external trigger pin initiates queue execution. The polarity of the external gated signal is fixed so a high level opens the gate and a low level closes the gate.
Once the gate is open, each CCW is read and the indicated conversions are performed until the gate is closed. When the gate opens again, the queue execution
automatically begins again from the beginning of the queue. Software initialization is
not needed between trigger events. If a pause in a CCW is encountered, the pause
flag will not set, and execution continues without pausing.
The purpose of external gated continuous-scan mode is to continuously collect digitized samples while the gate is open and to have the most recent samples available.
To ensure consistent sample times in waveform digitizing, for example, the programmer must ensure that all CCWs have identical sample time settings in IST.
It is up to the programmer to ensure that the queue is large enough so that a maximum
gate open time will not reach an end of queue. However it is useful to take advantage
of a smaller queue in the manner described in the next paragraph.
In the event that the queue completes before the gate closes, a completion flag will be
set and the queue will roll over to the beginning and continue conversions until the gate
closes. If the gate remains open and the queue completes a second time, the trigger
overrun flag will be set and the queue will roll-over again. The queue will continue to
execute until the gate closes or the mode is disabled.
If the gate closes before queue 1 completes execution, the current CCW completes,
execution of queue 1 stops and QADC64 sets the PF1 bit to indicate an incomplete
queue. Software can read the CWPQ1 to determine the last valid conversion in the
queue. In this mode, if the gate opens again execution of queue 1 begins again. The
start of queue 1 is always the first CCW in the CCW table.
Interval Timer Continuous-Scan Mode. The QADC64 includes a dedicated periodic/
interval timer for initiating a scan sequence on queue 1 and/or queue 2. Software
selects a programmable timer interval ranging from 128 to 128 Kbytes times the QCLK
period in binary multiples. The QCLK period is prescaled down from the intermodule
bus (IMB) MCU clock.
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When a periodic timer continuous-scan mode is selected for queue 1 and/or queue 2,
the timer begins counting. After the programmed interval elapses, the timer generated
trigger event starts the appropriate queue. Meanwhile, the QADC64 automatically performs the conversions in the queue until an end-of-queue condition or a pause is
encountered. When a pause occurs, the QADC64 waits for the periodic interval to
expire again, then continues with the queue. Once end-of-queue has been detected,
the next trigger event causes queue execution to begin again with the first CCW in the
queue.
The periodic timer generates a trigger event whenever the time interval elapses. The
trigger event may cause the queue execution to continue following a pause or queue
completion, or may be considered a trigger overrun. As with all continuous-scan queue
operating modes, software action is not needed between trigger events.
Software enables the completion interrupt when using the periodic timer continuousscan mode. When the interrupt occurs, the software knows that the periodically collected analog results have just been taken. The software can use the periodic interrupt
to obtain non-analog inputs as well, such as contact closures, as part of a periodic look
at all inputs.
13.10.4 QADC64 Clock (QCLK) Generation
Figure 13-8 is a block diagram of the clock subsystem. The QCLK provides the timing
for the A/D converter state machine, which controls the timing of the conversion. The
QCLK is also the input to a 17-stage binary divider which implements the periodic/
interval timer. To retain the specified analog conversion accuracy, the QCLK frequency (FQCLK) must be within a specified tolerance. See Electrical Characteristics
document.
Before using the QADC64, the software must initialize the prescaler with values that
put the QCLK within the specified range. Though most software applications initialize
the prescaler once and do not change it, write operations to the prescaler fields are
permitted.
NOTE
For software compatibility with earlier versions of QADC64, the definition of PSL, PSH, and PSA have been maintained. However, the
requirements on minimum time and minimum low time no longer
exist.
CAUTION
A change in the prescaler value while a conversion is in progress is
likely to corrupt the result from any conversion in progress. Therefore, any prescaler write operation should be done only when both
queues are in the disabled modes.
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USER’S MANUAL
RESET QCLK
ZERO
DETECT
5
SYSTEM CLOCK (FSYS)
5-BIT
DOWN COUNTER
LOAD PSH
CLOCK
GENERATE
5
PRESCALER RATE SELECTION
(FROM CONTROL REGISTER 0):
HIGH TIME CYCLES (PSH)
QCLK
3
ONE'S COMPLEMENT
COMPARE
LOW TIME CYCLES (PSL)
SET QCLK
3
ADD HALF CYCLE TO HIGH (PSA)
QADC64 CLOCK
( Fsys / ÷2 TO Fsys/÷40 )
INPUT SAMPLE TIME (FROM CCW) 2
A/D CONVERTER
STATE MACHINE
SAR CONTROL
SAR
10
BINARY COUNTER
27 28 29 210 211 212 213 214 215 216 217
Queue 1 & 2 TIMER MODE RATE SELECTION
8
PERIODIC/INTERVAL
TIMER SELECT
2
PERIODIC/INTERVAL
TRIGGER EVENT
FOR Q1 AND Q2
Figure 13-8 QADC64 Clock Subsystem Functions
To accommodate wide variations of the main MCU clock frequency (IMB system clock
— FSYS), QCLK is generated by a programmable prescaler which divides the MCU
system clock to a frequency within the specified QCLK tolerance range. To allow the
A/D conversion time to be maximized across the spectrum of system clock frequencies, the QADC64 prescaler permits the frequency of QCLK to be software selectable.
It also allows the duty cycle of the QCLK waveform to be programmable.
The software establishes the basic high phase of the QCLK waveform with the PSH
(prescaler clock high time) field in QACR0, and selects the basic low phase of QCLK
with the prescaler clock low time (PSL) field. The combination of the PSH and PSL
parameters establishes the frequency of the QCLK.
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NOTE
The guideline for selecting PSH and PSL is select is to maintain
approximately 50% duty cycle. So for prescaler values less then 16,
or PSH ~= PSL. For prescaler values greater than 16 keep PSL as
large as possible.
Figure 13-8 shows that the prescaler is essentially a variable pulse width signal generator. A 5-bit down counter, clocked at the system clock rate, is used to create both
the high phase and the low phase of the QCLK signal. At the beginning of the high
phase, the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector
finds that the high phase is finished, the QCLK is reset. A 3-bit comparator looks for a
one’s complement match with the 3-bit PSL value, which is the end of the low phase
of the QCLK. The PSA bit was maintained for software compatibility, but has no effect
on QADC64.
The following equations define QCLK frequency:
High QCLK Time = (PSH + 1) ÷ FSYS
Low QCLK Time = (PSL + 1) ÷ FSYS
FQCLK= 1 ÷ (High QCLK Time + Low QCLK Time)
Where:
• PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
• PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
• FSYS = System clock frequency
• FQCLK = QCLK frequency
The following are equations for calculating the QCLK high/low phases in Example 1:
High QCLK Time = (11 + 1) ÷ 40 x 106 = 300 ns
Low QCLK Time = (7 + 1) ÷ 40 x 106 = 200 ns
FQCLK = 1/(300 + 200) = 2 MHz
The following are equations for calculating the QCLK high/low phases in Example 2:
High QCLK Time = (7 + 1) ÷ 32 x 106 = 250 ns
Low QCLK Time = (7 + 1) ÷ 32 x 106 = 250 ns
FQCLK = 1/(250 + 250) = 2 MHz
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Figure 13-9 and Table 13-4 show examples of QCLK programmability. The examples
include conversion times based on the following assumption:
• Input sample time is as fast as possible (IST = 0, 2 QCLK cycles).
Figure 13-9 and Table 13-4 also show the conversion time calculated for a single conversion in a queue. For other MCU system clock frequencies and other input sample
times, the same calculations can be made.
SYSTEM CLOCK
FSYS
QCLK EXAMPLES
40 MHz EX1
32 MHz EX2
20 CYCLES
QADC64 QCLK EX
Figure 13-9 QADC64 Clock Programmability Examples
Table 13-4 QADC64 Clock Programmability
Control Register 0 Information
Example
Number
1
2
Frequency
PSH
PSA
PSL
40 MHz
32 MHz
11
7
0
0
7
7
Input Sample Time (IST) =%00
QCLK
Conversion Time
(MHz)
(µs)
2.0
7.0
2.0
7.0
NOTE
PSA is maintained for software compatibility but has no functional
benefit to this version of the module.
The MCU system clock frequency is the basis of the QADC64 timing. The QADC64
requires that the system clock frequency be at least twice the QCLK frequency. The
QCLK frequency is established by the combination of the PSH and PSL parameters in
QACR0. The 5-bit PSH field selects the number of system clock cycles in the high
phase of the QCLK wave. The 3-bit PSL field selects the number of system clock
cycles in the low phase of the QCLK wave.
Example 1 in Figure 13-9 shows that when PSH = 11, the QCLK remains high for
twelve cycles of the system clock. It also shows that when PSL = 7, the QCLK remains
low for eight system clock cycles. In Example 2, PSH = 7, the QCLK remains high for
eight cycles of the system clock. It also shows that when PSL = 7, the QCLK remains
low for eight system clock cycles.
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13.10.5 Periodic/Interval Timer
The on-chip periodic/interval timer is enabled to generate trigger events at a programmable interval, initiating execution of queue 1 and/or 2. The periodic/interval timer
stays reset under the following conditions:
• Queue 1 and queue 2 are programmed to any queue operating mode which does
not use the periodic/interval timer
• Interval timer single-scan mode is selected, but the single-scan enable bit is set
to zero
• IMB system reset or the master reset is asserted
• Stop mode is selected
• Freeze mode is selected
Two other conditions which cause a pulsed reset of the timer are:
• Roll-over of the timer counter
• A queue operating mode change from one periodic/interval timer mode to another
periodic/interval timer mode, depending on which queues are active in timer
mode.
NOTE
The periodic/interval timer will not reset for a queue 2 operating mode
change from one periodic/interval timer mode to another periodic/
interval timer mode while queue 1 is in an active periodic/interval
timer mode.
During the low power stop mode, the periodic/interval timer is held in reset. Since low
power stop mode causes QACR1 and QACR2 to be reset to zero, a valid periodic or
interval timer mode must be written after stop mode is exited to release the timer from
reset.
When the IMB internal FREEZE line is asserted and a periodic or interval timer mode
is selected, the timer counter is reset after the conversion in-progress completes.
When the periodic or interval timer mode has been enabled (the timer is counting), but
a trigger event has not been issued, the freeze mode takes effect immediately, and the
timer is held in reset. When the internal FREEZE line is negated, the timer counter
starts counting from the beginning.
13.11 Interrupts
The QADC64 supports both polled and interrupt driven operation. Status bits in QASR
reflect the operating condition of each queue and can optionally generate interrupts
when enabled by the appropriate bits in QACR1 and/or QACR2.
Figure 13-10 displays the QADC64 interrupt flow.
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USER’S MANUAL
INTERRUPT
CONTROL
PIE1
CONVERSION PAUSE ENABLE
PF1
CONVERSION PAUSE FLAG
QUEUE 1
CIE1
CONVERSION COMPLETE INTERRUPT ENABLE
(IRL1)
CF1
CONVERSION COMPLETE FLAG
INTERRUPT
GENERATOR
PIE2
CONVERSION PAUSE ENABLE
PF2
CONVERSION PAUSE FLAG
QUEUE 2
CIE2
CONVERSION COMPLETE INTERRUPT ENABLE
(IRL2)
CF2
CONVERSION COMPLETE FLAG
IRQ[7:0]
Figure 13-10 QADC64 Interrupt Flow Diagram
13.11.1 Interrupt Sources
The QADC64 has four interrupt service sources, each of which is separately enabled.
Each time the result is written for the last CCW in a queue, the completion flag for the
corresponding queue is set, and when enabled, an interrupt request is generated. In
the same way, each time the result is written for a CCW with the pause bit set, the
queue pause flag is set, and when enabled, an interrupt request is generated.
Table 13-5 displays the status flag and interrupt enable bits which correspond to
queue 1 and queue 2 activity.
Table 13-5 QADC64 Status Flags and Interrupt Sources
Queue
Queue 1
Queue 2
Queue Activity
Result written for the last CCW in queue 1
Result written for a CCW with pause bit set in
queue 1
Result written for the last CCW in queue 2
Result written for a CCW with pause bit set in
queue 2
Status Flag
CF1
Interrupt Enable Bit
CIE1
PF1
PIE1
CF2
CIE2
PF2
PIE2
Both polled and interrupt-driven QADC64 operations require that status flags must be
cleared after an event occurs. Flags are cleared by first reading QASR with the appropriate flag bits set to one, then writing zeros to the flags that are to be cleared. A flag
can be cleared only if the flag was a logic one at the time the register was read by the
CPU. If a new event occurs between the time that the register is read and the time that
it is written, the associated flag is not cleared.
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13.11.2 Interrupt Register
The QADC64 interrupt register QADC64INT specifies the priority level of QADC64
interrupt requests
The values contained in the IRL1 and IRL2 fields in QADC64INT determine the priority
of QADC64 interrupt service requests.The interrupt levels for queue 1 and queue 2
may be different.
13.11.3 Interrupt Levels and Time Multiplexing
The QADC64 conditionally generates interrupts to the bus master via the IMB IRQ signals. When the QADC64 sets a status bit assigned to generate an interrupt, the
QADC64 drives the IRQ bus. The value driven onto IRQ[7:0] represents the interrupt
level assigned to the interrupt source. Under the control of ILBS, each interrupt request
level is driven during the time multiplexed bus during one of four different time slots,
with eight levels communicated per time slot. No hardware priority is assigned to interrupts. Furthermore, if more than one source on a module requests an interrupt at the
same level, the system software must assign a priority to each source requesting at
that level. Figure 13-11 displays the interrupt levels on IRQ with ILBS.
IMB3 CLOCK
ILBS [1:0]
00
IMB3 IRQ [7:0]
01
IRQ
0:7
10
IRQ
8:15
11
00
01
IRQ
16:23
IRQ
24:31
IRQ
0:7
10
11
Figure 13-11 Interrupt levels on IRQ with ILBS
13.12 Programming Model
Each QADC64 occupies 1 Kbyte (512 16-bit entries) of address space. The address
space consists of ten 16-bit control, status, and port registers; 64 16-bit entries in the
CCW table; and 64 16-bit entries in the result table. The result table occupies 192 16bit address locations because the result data is readable in three data alignment
formats.
Table 13-6 shows the QADC64 memory map. The lowercase “x” appended to each
register name represents “A” or “B” for the QADC64_A or QADC64_B module, respectively. The address offset shown is from the base address of the module. Refer to 1.3
MPC555 Address Map to locate each QADC64 module in the MPC555 memory map.
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Table 13-6 QADC64 Address Map
MSB
0
LSB
15
Access
Address
S1
0x30 4800
0x30 4C00
QADC64 Module Configuration Register
(QADC64MCR_x)
See Table 13-7 for bit descriptions.
T2
0x30 4802
0x30 4C02
QADC64 Test Register (QADC64TEST_x)
S
0x30 4804
0x30 4C04
Interrupt Register (QADC64INT_x)
See Table 13-8 for bit descriptions.
S/U3
0x30 4806
0x30 4C06
S/U
0x30 4808
0x30 4C08
Port A Data Direction Register (DDRQA_x)
See Table 13-10 for bit descriptions.
S/U
0x30 480A
0x30 4C0A
QADC64 Control Register 0 (QACR0_x)
See Table 13-11 for bit descriptions.
S/U
0x30 480C
0x30 4C0C
QADC64 Control Register 1 (QACR1_x)
See Table 13-12 for bit descriptions.
S/U
0x30 480E
0x30 4C0E
QADC64 Control Register 2 (QACR2_x)
See Table 13-14 for bit descriptions.
S/U
0x30 4810,
0x30 4C10
QADC64 Status Register 0 (QASR0_x)
See Table 13-16 for bit descriptions.
S/U
0x30 4812,
0x30 4C12
QADC64 Status Register 1 (QASR1_x)
See Table 13-18 for bit descriptions.
---
0x30 4814 – 0x30 49FE
0x30 4C14 – 0x30 4DFE
Reserved
S/U
0x30 4A00 – 0x30 4A7E
0x30 4E00 – 0x30 4E7E
Conversion Command Word (CCW_x) Table
See Table 13-19 for bit descriptions.
S/U
0x30 4A80 – 0x30 4AFE
0x30 4E80 – 0x30 4EFE
Result Word Table
Right-Justified, Unsigned Result Register
(RJURR_x)
See 13.12.12 for bit descriptions.
S/U
0x30 4B00 – 0x30 4B7E
0x30 4F00 – 0x30 4F7E
Result Word Table
Left-Justified, Signed Result Register (LJSRR_x)
See 13.12.12 for bit descriptions.
S/U
0x30 4B80 – 0x30 4BFE
0x30 4F80 – 0x30 4FFE
Result Word Table
Left-Justified, Unsigned Result Register
(LJURR_x)
See 13.12.12 for bit descriptions.
Port A Data
(PORTQA_x)
See Table 13-10 for bit
descriptions.
Port B Data
(PORTQB_x)
NOTES:
1. S = Supervisor only
2. Access is restricted to supervisor only and factory test mode only.
3. S/U = Unrestricted or supervisor depending on the state of the SUPV bit in the QADC64MCR.
The QADC64 has three global registers for configuring module operation: the module
configuration register (QADC64MCR), the interrupt register (QADC64INT), and a test
register (QADC64TEST). The global registers are always defined to be in supervisor
data space. The CPU allows software to establish the global registers in supervisor
data space and the remaining registers and tables in user space.
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All QADC64 analog channel/port pins that are not used for analog input channels can
be used as digital port pins. Port values are read/written by accessing the port A and
B data registers (PORTQA and PORTQB). Port A pins are specified as inputs or outputs by programming the port data direction register (DDRQA). Port B is an input-only
port.
13.12.1 QADC64 Module Configuration Register
QADC64MCR — QADC64 Module Configuration Register
MSB
0
1
STOP
FRZ
2
3
4
5
6
7
8
RESERVED
9
0x30 4800
0x30 4C00
10
11
SUPV
12
13
14
LSB
15
0
0
0
RESERVED
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
Table 13-7 QADC64MCR Bit Settings
Bit(s)
Name
Description
STOP
Low-power stop mode enable. When the STOP bit is set, the clock signal to the QADC64 is disabled, effectively turning off the analog circuitry.
0 = Enable QADC64 clock
1 = Disable QADC64 clock
1
FRZ
FREEZE assertion response. The FRZ bit determines whether or not the QADC64 responds to
assertion of the IMB3 FREEZE signal.
0 = QADC64 ignores the IMB3 FREEZE signal
1 = QADC64 finishes any current conversion, then freezes
2:7
—
0
Reserved
8
SUPV
9:15
—
Supervisor/unrestricted data space. The SUPV bit designates the assignable space as supervisor or unrestricted.
0 = Only the module configuration register, test register, and interrupt register are designated as
supervisor-only data space. Access to all other locations is unrestricted
1 = All QADC64 registers and tables are designated as supervisor-only data space
Reserved
13.12.2 QADC64 Test Register
QADC64TEST — QADC64 Test Register
Used for factory test only.
0x30 4802, 0x30 4C02
13.12.3 QADC64 Interrupt Register
QADC64INT — QADC64 Interrupt Register
MSB
0
1
2
3
4
5
6
IRL1
7
0x30 4804
0x30 4C04
8
9
10
11
12
13
14
LSB
15
0
0
RESERVED
IRL2
RESET:
0
0
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0
0
0
0
0
0
0
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USER’S MANUAL
Table 13-8 QADC64INT Bit Settings
Bit(s)
Name
Description
0:4
IRL1
Interrupt level for queue 1. A value of 0b00000 provides an interrupt level of 0; 0b11111 provides
a level interrupt. All interrupts are presented on the IMB3. Interrupt level priority software determines which level has the highest priority request.
5:9
IRL2
Interrupt level for queue 2. A value of 0b00000 provides an interrupt level of 0; 0b11111 provides
a level interrupt. All interrupts are presented on the IMB3. Interrupt level priority software determines which level has the highest priority request.
10:15
—
Reserved
13.12.4 Port A/B Data Register
QADC64 ports A and B are accessed through two 8-bit port data registers (PORTQA
and PORTQB).
PORTQA — Port QA Data Register
PORTQB — Port QB Data Register
MSB
0
PQA7
1
2
PQA6 PQA5
0x30 4806
0x30 4C06
6
7
8
9
10
11
12
13
14
LSB
15
3
4
5
PQA4
PQA3
PQA2
U
U
U
U
U
U
U
U
U
U
U
U
U
AN56
AN55
AN54
AN53
AN52
AN51
AN50
AN49
AN48
AN3
AN2
AN1
AN0
MA2
MA1
MA0
ANz
ANy
ANx
ANw
PQA1 PQA0 PQB7 PQB6 PQB5 PQB4 PQB3 PQB2 PQB1 PQB0
RESET:
U
U
U
ANALOG CHANNEL:
AN59
AN58
AN57
MULTIPLEXED ADDRESS OUTPUTS:
MULTIPLEXED ANALOG INPUTS:
Table 13-9 PORTQA, PORTQB Bit Settings
Bit(s)
Name
Description
0:7
PQA[0:7]
Port A pins are referred to as PQA when used as an 8-bit input/output port. Port A can also be
used for analog inputs (AN[59:52]), and external multiplexer address outputs (MA[2:0]).
8:15
PQB[0:7]
Port B pins are referred to as PQB when used as an 8-bit input-only port. Port B can also be used
for non-multiplexed (AN[51:48])/AN[3:0]) and multiplexed (ANz, ANy, ANx, ANw) analog inputs.
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13.12.5 Port Data Direction Register
DDRQA — Port QA Data Direction Register
MSB
0
DDQA7
1
2
3
4
5
6
7
0x30 4808
0x30 4C08
8
9
10
DDQA DDQA DDQA DDQA DDQA DDQA DDQA
6
5
4
3
2
1
0
11
12
13
14
LSB
15
0
0
0
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 13-10 DDRQA Bit Settings
Bit(s)
0:7
Name
Description
Bits in this register control the direction of the port QA pin drivers when pins are configured for I/
DDQA[7:0] O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input. This register can be read or written at any time.
13.12.6 QADC64 Control Register 0 (QACR0)
Control register zero establishes the QCLK with prescaler parameter fields and
defines whether external multiplexing is enabled. All of the implemented control register fields can be read or written, reserved fields read zero and writes have no effect.
They are typically written once when the software initializes the QADC64, and not
changed afterwards.
QACR0 — QADC64 Control Register 0
MSB
0
MUX
1
2
RESERVED
3
4
TRG
5
6
0x30 480A
0x30 4C0A
7
8
RESERVED
9
10
11
PSH
12
13
PSA
14
LSB
15
PSL
RESET:
0
0
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0
0
0
0
0
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0
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1
1
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Table 13-11 QACR0 Bit Settings
Bit(s)
Name
Description
0
MUX
Externally multiplexed mode. The MUX bit configures the QADC64 for externally multiplexed
mode, which affects the interpretation of the channel numbers and forces the MA[2:0] pins to be
outputs.
0 = Internally multiplexed, 16 possible channels
1 = Externally multiplexed, 41 possible channels
1:2
—
Reserved
Trigger assignment. TRG allows the software to assign the ETRIG[2:1] pins to queue 1 and
queue 2.
0 = ETRIG1 triggers queue 1; ETRIG2 triggers queue 2
1 = ETRIG1 triggers queue 2; ETRIG2 triggers queue 1
3
TRG
4:6
—
7:11
PSH
Prescaler clock high time. The PSH field selects the QCLK high time in the prescaler. PSH value
plus 1 represents the high time in system clocks
12
PSA
Note that this bit location is maintained for software compatibility with previous versions of the
QADC64. It serves no functional benefit in the MPC555 and is not operational.
13:15
PSL
Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value
plus 1 represents the low time in system clocks
Reserved
13.12.7 QADC64 Control Register 1 (QACR1)
Control register 1 is the mode control register for the operation of queue 1. The applications software defines the queue operating mode for the queue, and may enable a
completion and/or pause interrupt. All of the control register fields are read/write data.
However, the SSE1 bit always reads as zero unless the test mode is enabled. Most of
the bits are typically written once when the software initializes the QADC64, and not
changed afterwards.
QACR1 — Control Register 1
MSB
0
1
2
CIE1
PIE1
SSE1
0
0
3
4
0x30 480C
0x30 4C0C
5
6
7
8
9
10
MQ1
11
12
13
14
LSB
15
0
0
0
RESERVED
RESET:
0
MPC555
USER’S MANUAL
0
0
0
0
0
0
0
0
0
0
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 1 March 1999
MOTOROLA
13-35
Table 13-12 QACR1 Bit Settings
Bit(s)
0
1
2
Name
Description
CIE1
Queue 1 completion interrupt enable. CIE1 enables completion interrupts for queue 1. The interrupt request is generated when the conversion is complete for the last CCW in queue 1.
0 = Queue 1 completion interrupts disabled
1 = Generate an interrupt request after completing the last CCW in queue 1
PIE1
Queue 1 pause interrupt enable. PIE1 enables pause interrupts for queue 1. The interrupt
request is generated when the conversion is complete for a CCW that has the pause bit set.
0 = Queue 1 pause interrupts disabled
1 = Generate an interrupt request after completing a CCW in queue 1 which has the pause bit set
SSE1
Queue 1 single-scan enable. SSE1 enables a single-scan of queue 1 after a trigger event occurs.
The SSE1 bit may be set to a one during the same write cycle that sets the MQ1 bits for the single-scan queue operating mode. The single-scan enable bit can be written as a one or a zero,
but is always read as a zero.
The SSE1 bit allows a trigger event to initiate queue execution for any single-scan operation on
queue 1. The QADC64 clears SSE1 when the single-scan is complete.
3:7
MQ1
8:15
—
MOTOROLA
13-36
Queue 1 operating mode. The MQ1 field selects the queue operating mode for queue 1. Table
13-13 shows the different queue 1 operating modes.
Reserved
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 13-13 Queue 1 Operating Modes
MQ1
Operating Modes
0b00000
Disabled mode, conversions do not occur
0b00001
Software triggered single-scan mode (started with SSE1)
0b00010
External trigger rising edge single-scan mode
0b00011
External trigger falling edge single-scan mode
0b00100
Interval timer single-scan mode: time = QCLK period x 27
0b00101
Interval timer single-scan mode: time = QCLK period x 28
0b00110
Interval timer single-scan mode: time = QCLK period x 29
0b00111
Interval timer single-scan mode: time = QCLK period x 210
0b01000
Interval timer single-scan mode: time = QCLK period x 211
0b01001
Interval timer single-scan mode: time = QCLK period x 212
0b01010
Interval timer single-scan mode: time = QCLK period x 213
0b01011
Interval timer single-scan mode: time = QCLK period x 214
0b01100
Interval timer single-scan mode: time = QCLK period x 215
0b01101
Interval timer single-scan mode: time = QCLK period x 216
0b01110
Interval timer single-scan mode: time = QCLK period x 217
0b01111
External gated single-scan mode (started with SSE1)
0b10000
Reserved mode
0b10001
Software triggered continuous-scan mode
0b10010
External trigger rising edge continuous-scan mode
0b10011
External trigger falling edge continuous-scan mode
0b10100
Periodic timer continuous-scan mode: time = QCLK period x 27
0b10101
Periodic timer continuous-scan mode: time = QCLK period x 28
0b10110
Periodic timer continuous-scan mode: time = QCLK period x 29
0b10111
Periodic timer continuous-scan mode: time = QCLK period x 210
0b11000
Periodic timer continuous-scan mode: time = QCLK period x 211
0b11001
Periodic timer continuous-scan mode: time = QCLK period x 212
0b11010
Periodic timer continuous-scan mode: time = QCLK period x 213
0b11011
Periodic timer continuous-scan mode: time = QCLK period x 214
0b11100
Periodic timer continuous-scan mode: time = QCLK period x 215
0b11101
Periodic timer continuous-scan mode: time = QCLK period x 216
0b11110
Periodic timer continuous-scan mode: time = QCLK period x 217
0b11111
External gated continuous-scan mode
MPC555
USER’S MANUAL
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 1 March 1999
MOTOROLA
13-37
13.12.8 QADC64 Control Register 2 (QACR2)
Control register two is the mode control register for the operation of queue 2. Software
specifies the queue operating mode of queue 2, and may enable a completion and/or
a pause interrupt. All control register fields are read/write data, except the SSE2 bit,
which is readable only when the test mode is enabled. Most of the bits are typically
written once when the software initializes the QADC64, and not changed afterwards.
QACR2 — Control Register 2
MSB
0
1
2
CIE2
PIE2
SSE2
0
0
3
4
0x30 480E
0x30 4C0E
5
6
7
MQ2
8
9
10
11
RESUME
12
13
14
LSB
15
0
0
0
BQ2
RESET:
0
0
0
0
0
0
0
1
0
0
0
Table 13-14 QACR2 Bit Settings
Bit(s)
0
1
2
Name
Description
CIE2
Queue 2 completion interrupt enable. CIE2 enables completion interrupts for queue 2. The interrupt request is generated when the conversion is complete for the last CCW in queue 2.
0 = Queue 2 completion interrupts disabled.
1 = Generate an interrupt request after completing the last CCW in queue 2.
PIE2
Queue 2 pause interrupt enable. PIE2 enables pause interrupts for queue 2. The interrupt
request is generated when the conversion is complete for a CCW that has the pause bit set.
0 = Queue 2 pause interrupts disabled.
1 = Generate an interrupt request after completing a CCW in queue 2 which has the pause bit set.
SSE2
Queue 2 single-scan enable bit. SSE2 enables a single-scan of queue 2 after a trigger event
occurs. The SSE2 bit may be set to a one during the same write cycle that sets the MQ2 bits for
the single-scan queue operating mode. The single-scan enable bit can be written as a one or a
zero, but is always read as a zero.
The SSE2 bit allows a trigger event to initiate queue execution for any single-scan operation on
queue 2. The QADC64 clears SSE2 when the single-scan is complete.
3:7
8
9:15
MQ2
Queue 2 resume. RESUME selects the resumption point after queue 2 is suspended by queue
1. If RESUME is changed during execution of queue 2, the change is not recognized until an endRESUME of-queue condition is reached, or the queue operating mode of queue 2 is changed.
0 = After suspension, begin execution with the first CCW in queue 2 or the current sub-queue.
1 = After suspension, begin execution with the aborted CCW in queue 2.
BQ2
MOTOROLA
13-38
Queue 2 operating mode. The MQ2 field selects the queue operating mode for queue 2. Table
13-15 shows the bits in the MQ2 field which enable different queue 2 operating modes.
Beginning of queue 2. The BQ2 field indicates the location in the CCW table where queue 2
begins. The BQ2 field also indicates the end of queue 1 and thus creates an end-of-queue condition for queue 1. Setting BQ2 to any value ≥ 64 (0b1000000) allows the entire RAM space for
queue 1 CCWs.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 13-15 Queue 2 Operating Modes
MQ2
0b00000
0b00001
0b00010
0b00011
Operating Modes
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE2)
External trigger rising edge single-scan mode
External trigger falling edge single-scan mode
0b00100
Interval timer single-scan mode: interval = QCLK period x 27
0b00101
Interval timer single-scan mode: interval = QCLK period x 28
0b00110
Interval timer single-scan mode: interval = QCLK period x 29
0b00111
Interval timer single-scan mode: interval = QCLK period x 210
0b01000
Interval timer single-scan mode: interval = QCLK period x 211
0b01001
Interval timer single-scan mode: interval = QCLK period x 212
0b01010
Interval timer single-scan mode: interval = QCLK period x 213
0b01011
Interval timer single-scan mode: interval = QCLK period x 214
0b01100
Interval timer single-scan mode: interval = QCLK period x 215
0b01101
Interval timer single-scan mode: interval = QCLK period x 216
0b01110
0b01111
0b10000
0b10001
0b10010
0b10011
Interval timer single-scan mode: interval = QCLK period x 217
Reserved mode
Reserved mode
Software triggered continuous-scan mode (started with SSE2)
External trigger rising edge continuous-scan mode
External trigger falling edge continuous-scan mode
0b10100
Periodic timer continuous-scan mode: period = QCLK period x 27
0b10101
Periodic timer continuous-scan mode: period = QCLK period x 28
0b10110
Periodic timer continuous-scan mode: period = QCLK period x 29
0b10111
Periodic timer continuous-scan mode: period = QCLK period x 210
0b11000
Periodic timer continuous-scan mode: period = QCLK period x 211
0b11001
Periodic timer continuous-scan mode: period = QCLK period x 212
0b11010
Periodic timer continuous-scan mode: period = QCLK period x 213
0b11011
Periodic timer continuous-scan mode: period = QCLK period x 214
0b11100
Periodic timer continuous-scan mode: period = QCLK period x 215
0b11101
Periodic timer continuous-scan mode: period = QCLK period x 216
0b11110
Periodic timer continuous-scan mode: period = QCLK period x 217
Reserved mode
0b11111
13.12.9 QADC64 Status Register 0 (QASR0)
QASR0 contains information about the state of each queue and the current A/D conversion. Except for the four flag bits (CF1, PF1, CF2, and PF2) and the two trigger
overrun bits (TOR1 and TOR2), all of the status register fields contain read-only data.
The four flag bits and the two trigger overrun bits are cleared by writing a zero to the
bit after the bit was previously read as a one.
MPC555
USER’S MANUAL
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 1 March 1999
MOTOROLA
13-39
QASR0 — QADC64 Status Register
MSB
0
1
2
3
4
5
CF1
PF1
CF2
PF2
TOR1
TOR2
0
0
0
0
0
0x30 4810
0x30 4C10
6
7
8
9
10
11
12
QS
13
14
LSB
15
0
0
0
CWP
RESET:
0
0
0
0
0
0
0
0
Table 13-16 QASR0 Bit Settings
Bit(s)
0
1
2
3
Name
Description
CF1
Queue 1 completion flag. CF1 indicates that a queue 1 scan has been completed. CF1 is set by
the QADC64 when the conversion is complete for the last CCW in queue 1, and the result is
stored in the result table.
0 = Queue 1 scan is not complete
1 = Queue 1 scan is complete
PF1
Queue 1 pause flag. PF1 indicates that a queue 1 scan has reached a pause. PF1 is set by the
QADC64 when the current queue 1 CCW has the pause bit set, the selected input channel has
been converted, and the result has been stored in the result table.
0 = Queue 1 has not reached a pause
1 = Queue 1 has reached a pause
CF2
Queue 2 completion flag. CF2 indicates that a queue 2 scan has been completed. CF2 is set by
the QADC64 when the conversion is complete for the last CCW in queue 2, and the result is
stored in the result table.
0 = Queue 2 scan is not complete
1 = Queue 2 scan is complete
PF2
Queue 2 pause flag. PF2 indicates that a queue 2 scan has reached a pause. PF2 is set by the
QADC64 when the current queue 2 CCW has the pause bit set, the selected input channel has
been converted, and the result has been stored in the result table.
0 = Queue 2 has not reached a pause
1 = Queue 2 has reached a pause
— Queue 1 trigger overrun. TOR1 indicates that an unexpected queue 1 trigger event has
occurred. TOR1 can be set only while queue 1 is active.
4
TOR1
A trigger event generated by a transition on ETRIG1/ETRIG2 may be recorded as a trigger overrun. TOR1 can only be set when using an external trigger mode. TOR1 cannot occur when the
software initiated single-scan mode or the software initiated continuous-scan mode is selected.
0 = No unexpected queue 1 trigger events have occurred
1 = At least one unexpected queue 1 trigger event has occurred
Queue 2 trigger overrun. TOR2 indicates that an unexpected queue 2 trigger event has occurred.
TOR2 can be set when queue 2 is in the active, suspended, and trigger pending states.
5
TOR2
MOTOROLA
13-40
A trigger event generated by a transition depending on the value of TRG in QACR or ETRIG1/
ETRIG2 or by the periodic/interval timer may be recorded as a trigger overrun. TOR2 can only
be set when using an external trigger mode or a periodic/interval timer mode. Trigger overruns
cannot occur when the software initiated single-scan mode and the software initiated continuousscan mode are selected.
0 = No unexpected queue 2 trigger events have occurred
1 = At least one unexpected queue 2 trigger event has occurred
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 13-16 QASR0 Bit Settings (Continued)
Bit(s)
Name
6:9
Description
Queue status. This 4-bit read-only field indicates the current condition of queue 1 and queue 2.
QS[0:1] are associated with queue 1, and QS[2:3] are associated with queue 2. Since the queue
priority scheme interlinks the operation of queue 1 and queue 2, the status bits should be considered as one 4-bit field.
QS
Table 13-17 shows the bit encodings of the QS field.
10:15
CWP
Command word pointer. CWP indicates which CCW is executing at present, or was last completed. The CWP is a read-only field; writes to it have no effect.
Table 13-17 Queue Status
QS
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
Description
Queue 1 idle, queue 2 idle
Queue 1 idle, queue 2 paused
Queue 1 idle, queue 2 active
Queue 1 idle, queue 2 trigger pending
Queue 1 paused, queue 2 idle
Queue 1 paused, queue 2 paused
Queue 1 paused, queue 2 active
Queue 1 paused, queue 2 trigger pending
Queue 1 active, queue 2 idle
Queue 1 active, queue 2 paused
Queue 1 active, queue 2 suspended
Queue 1 active, queue 2 trigger pending
Reserved
Reserved
Reserved
Reserved
13.12.10 QADC64 Status Register 1 (QASR1)
The QASR1 contains two fields: command word pointers for queue 1 and queue 2.
QASR1 — Status Register1
MSB
0
1
2
3
RESERVED
4
0x30 4812
0x30 4C12
5
6
7
CWPQ1
8
9
10
11
RESERVED
12
13
14
LSB
15
1
1
CWPQ2
RESET:
0
0
1
MPC555
USER’S MANUAL
1
1
1
1
1
0
0
1
1
1
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 1 March 1999
1
MOTOROLA
13-41
Table 13-18 QASR0 Bit Settings
Bit(s)
Name
0:1
—
Description
Reserved
Command word pointer for queue 1. This field is a software read-only field, and write operations
have no effect. CWPQ1 allows software to read the last executed CCW in queue 1, regardless
which queue is active. The CWPQ1 field is a CCW word pointer with a valid range of 0 to 63.
2:7
CWPQ1
In contrast to CWP, CPWQ1 is updated when the conversion result is written. When the QADC64
finishes a conversion in queue 1, both the result register is written and the CWPQ1 are updated.
Finally, when queue 1 operation is terminated after a CCW is read that is defined as BQ2, CWP
points to BQ2 while CWPQ1 points to the last CCW queue 1.
During the stop mode, the CWPQ1 is reset to 63, since the control registers and the analog logic
are reset. When the freeze mode is entered, the CWPQ1 is unchanged; it points to the last executed CCW in queue 1.
8:9
—
Reserved
Command word pointer for queue 2. This field is a software read-only field, and write operations
have no effect. CWPQ2 allows software to read the last executed CCW in queue 2, regardless
which queue is active. The CWPQ2 field is a CCW word pointer with a valid range of 0 to 63.
10:15
CWPQ2
In contrast to CWP, CPWQ2 is updated when the conversion result is written. When the QADC64
finishes a conversion in queue 2, both the result register is written and the CWPQ2 are updated.
During the stop mode, the CWPQ2 is reset to 63, since the control registers and the analog logic
are reset. When the freeze mode is entered, the CWP is unchanged; it points to the last executed
CCW in queue 2.
13.12.11 Conversion Command Word Table
The CCW table is a RAM, 64 words long and 10 bits wide, which can be programmed
by the software to request conversions of one or more analog input channels. The
entries in the CCW table are 10-bit conversion command words. The CCW table is
written by software and is not modified by the QADC64. Each CCW requests the conversion of an analog channel to a digital result. The CCW specifies the analog channel
number, the input sample time, and whether the queue is to pause after the current
CCW.
The ten implemented bits of the CCW word are read/write data. They may be written
when the software initializes the QADC64. Unimplemented bits are read as zeros, and
write operations have no effect. Each location in the CCW table corresponds to a location in the result word table. When a conversion is completed for a CCW entry, the 10bit result is written in the corresponding result word entry. The QADC64 provides 64
CCW table entries.
The beginning of queue 1 is always the first location in the CCW table. The first location of queue 2 is specified by the beginning of queue 2 pointer (BQ2) in QACR2. To
dedicate the entire CCW table to queue 1, software must do the following:
• Program queue 2 to be in the disabled mode, and
• Program the beginning of BQ2 to ≥ 64.
To dedicate the entire CCW table to queue 2, software must do the following:
• Program queue 1 to be in the disabled mode
• Program BQ2 to be the first location in the CCW table.
MOTOROLA
13-42
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Revised 1 March 1999
MPC555
USER’S MANUAL
Figure 13-12 illustrates the operation of the queue structure.
CONVERSION COMMAND WORD
(CCW) TABLE
00
RESULT WORD TABLE
00
BEGIN Queue 1
CHANNEL SELECT,
SAMPLE, HOLD, AND
A/D CONVERSION
END OF Queue 1
BQ2
BEGIN Queue 2
END OF Queue 2
63
63
10-BIT CONVERSION COMMAND
WORD FORMAT
LSB
6
7
P
BYP
8
9
IST
10
11
12
13
14
10-BIT RESULT, READABLE IN
THREE 16-BIT FORMATS
MSB
15
MSB
0 1
0
CHAN
2
0 0
3 4
5
0
0
0
6 7
8
LSB
10 11 12 13 14 15
9
RESULT
RIGHT JUSTIFIED, UNSIGNED RESULT
P = PAUSE AFTER CONVERSION UNTIL NEXT TRIGGER
BYP = BYPASS BUFFER AMPLIFIER
IST = INPUT SAMPLE TIME
CHAN = CHANNEL NUMBER AND END-OF-QUEUE CODE
MSB
0 1
2
3 4
5
6 7
8
9
RESULT
LSB
10 11 12 13 14 15
0
0 0
0
0
0
LEFT JUSTIFIED, UNSIGNED RESULT
MSB
0 1
2
3 4
S
5
6 7
8
9
RESULT
LSB
10 11 12 13 14 15
0
0 0
0
0
0
LEFT JUSTIFIED, SIGNED RESULT
S = SIGN BIT
QADC64 C
Figure 13-12 QADC64 Conversion Queue Operation
To prepare the QADC64 for a scan sequence, the software writes to the CCW table to
specify the desired channel conversions. The software also establishes the criteria for
initiating the queue execution by programming the queue operating mode. The queue
operating mode determines what type of trigger event causes queue execution to
begin. “Trigger event” refers to any of the ways to cause the QADC64 to begin executing the CCWs in a queue or sub-queue. An external trigger is only one of the possible
trigger events.
A scan sequence may be initiated by the following:
MPC555
USER’S MANUAL
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 1 March 1999
MOTOROLA
13-43
• A software command
• Expiration of the periodic/interval timer
• External trigger signal
• External gated signal (queue 1 only)
The software also specifies whether the QADC64 is to perform a single pass through
the queue or is to scan continuously. When a single-scan mode is selected, the software selects the queue operating mode and sets the single-scan enable bit. When a
continuous-scan mode is selected, the queue remains active in the selected queue
operating mode after the QADC64 completes each queue scan sequence.
During queue execution, the QADC64 reads each CCW from the active queue and
executes conversions in three stages:
• Initial sample
• Final sample
• Resolution
During initial sample, a buffered version of the selected input channel is connected to
the sample capacitor at the output of the sample buffer amplifier.
During the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges the sample capacitor directly. Each CCW specifies a final input
sample time of 2, 4, 8, or 16 QCLK cycles. When an analog-to-digital conversion is
complete, the result is written to the corresponding location in the result word table.
The QADC64 continues to sequentially execute each CCW in the queue until the end
of the queue is detected or a pause bit is found in a CCW.
When the pause bit is set in the current CCW, the QADC64 stops execution of the
queue until a new trigger event occurs. The pause status flag bit is set, which may
cause an interrupt to notify the software that the queue has reached the pause state.
After the trigger event occurs, the paused state ends and the QADC64 continues to
execute each CCW in the queue until another pause is encountered or the end of the
queue is detected.
The following indicate the end-of-queue condition:
• The CCW channel field is programmed with 63 ($3F) to specify the end of the
queue
• The end of queue 1 is implied by the beginning of queue 2, which is specified in
the BQ2 field in QACR2
• The physical end of the queue RAM space defines the end of either queue
When any of the end-of-queue conditions are recognized, a queue completion flag is
set, and if enabled, an interrupt is issued to the software. The following situations prematurely terminate queue execution:
• Since queue 1 is higher in priority than queue 2, when a trigger event occurs on
queue 1 during queue 2 execution, the execution of queue 2 is suspended by
aborting the execution of the CCW in progress, and the queue 1 execution begins. When queue 1 execution is completed, queue 2 conversions restart with the
MOTOROLA
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Revised 1 March 1999
MPC555
USER’S MANUAL
first CCW entry in queue 2 or the first CCW of the queue 2 sub-queue being executed when queue 2 was suspended. Alternately, conversions can restart with
the aborted queue 2 CCW entry. The RESUME bit in QACR2 allows the software
to select where queue 2 begins after suspension. By choosing to re-execute all of
the suspended queue 2 queue and sub-queue CCWs, all of the samples are guaranteed to have been taken during the same scan pass. However, a high trigger
event rate for queue 1 can prohibit the completion of queue 2. If this occurs, the
software may choose to begin execution of queue 2 with the aborted CCW entry.
• Software can change the queue operating mode to disabled mode. Any conversion in progress for that queue is aborted. Putting a queue into the disabled mode
does not power down the converter.
• Software can change the queue operating mode to another valid mode. Any conversion in progress for that queue is aborted. The queue restarts at the beginning
of the queue, once an appropriate trigger event occurs.
• For low power operation, software can set the stop mode bit to prepare the module for a loss of clocks. The QADC64 aborts any conversion in progress when the
stop mode is entered.
• When the freeze enable bit is set by software and the IMB internal FREEZE line
is asserted, the QADC64 freezes at the end of the conversion in progress. When
internal FREEZE is negated, the QADC64 resumes queue execution beginning
with the next CCW entry.
CCW — Conversion Command Word Table
MSB
0
1
2
3
4
5
RESERVED
6
7
P
BYP
U
U
0x30 4A00 – 0x30 4A7E
0x30 4E00 – 0x30 4E7E
8
9
10
11
12
IST
13
14
LSB
15
U
U
CHAN
RESET:
0
0
0
MPC555
USER’S MANUAL
0
0
0
U
U
U
U
U
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Revised 1 March 1999
U
MOTOROLA
13-45
Table 13-19 CCW Bit Settings
Bit(s)
Name
0:5
—
Reserved
P
Pause. The pause bit allows the creation of sub-queues within queue 1 and queue 2. The
QADC64 performs the conversion specified by the CCW with the pause bit set, and then the
queue enters the pause state. Another trigger event causes execution to continue from the pause
to the next CCW.
0 = Do not enter the pause state after execution of the current CCW.
1 = Enter the pause state after execution of the current CCW.
BYP
Sample amplifier bypass. Setting BYP enables the amplifier bypass mode for a conversion, and
subsequently changes the timing. Refer to 13.9.1.1 Amplifier Bypass Mode Conversion Timing for more information.
0 = Amplifier bypass mode disabled.
1 = Amplifier bypass mode enabled.
IST
Input sample time. The IST field specifies the length of the sample window. Longer sample times
permit more accurate A/D conversions of signals with higher source impedances, especially if
BYP = 1.
00 = QCKL period x 2
01 = QCKL period x 4
10 = QCKL period x 8
11 = QCKL period x 16
6
7
8:9
Description
Channel number. The CHAN field selects the input channel number corresponding to the analog
input pin to be sampled and converted. The analog input pin channel number assignments and
the pin definitions vary depending on whether the QADC64 is operating in multiplexed or nonmultiplexed mode. The queue scan mechanism sees no distinction between an internally or
externally multiplexed analog input.
10:15
CHAN
If CHAN specifies a reserved channel number (channels 32 to 47) or an invalid channel number
(channels 4 to 31 in non-multiplexed mode), the low reference level (VRL) is converted. Programming the channel field to channel 63 indicates the end of the queue. Channels 60 to 62 are
special internal channels. When one of these channels is selected, the sample amplifier is not
used. The value of VRL, VRH, or (VRH – VRL)/2 is placed directly into the converter. Programming the input sample time to any value other than two for one of the internal channels has no
benefit except to lengthen the overall conversion time.
Table 13-20 shows the channel number assignments for the non-multiplexed mode. Table 1321 shows the channel number assignments for the multiplexed mode.
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USER’S MANUAL
Table 13-20 Non-Multiplexed Channel Assignments and Pin Designations
Port Pin Name
PQB0
PQB1
PQB2
PQB3
—
—
PQB4
PQB5
PQB6
PQB7
PQA0
PQA1
PQA2
PQA3
PQA4
PQA5
PQA6
PQA7
—
—
—
—
Non-multiplexed Input Pins
Channel Number in CHAN
Analog Pin Name Other Functions Pin Type (I/O)
Binary
Decimal
AN0
—
I
000000
0
AN1
—
I
000001
1
AN2
—
I
000010
2
AN3
—
I
000011
3
—
Invalid
—
000100 to 011111
4 to 31
—
Reserved
—
10XXXX
32 to 47
I
110000
48
AN48
—
110001
49
AN49
—
I
50
AN50
—
I
110010
110011
51
—
I
AN51
52
AN52
—
I/O
110100
I/O
110101
53
AN53
—
AN54
—
I/O
110110
54
AN55
—
I/O
110111
55
AN56
—
I/O
111000
56
AN57
—
I/O
111001
57
AN58
—
I/O
111010
58
AN59
—
I/O
111011
59
VRL
—
I
111100
60
VRH
—
I
111101
61
—
(VRH – VRL)/2
—
111110
62
—
End of Queue Code
—
111111
63
Table 13-21 Multiplexed Channel Assignments and Pin Designations
Port Pin Name
PQB0
PQB1
PQB2
PQB3
—
PQB4
PQB5
PQB6
PQB7
PQA0
PQA1
PQA2
PQA3
PQA4
PQA5
PQA6
PQA7
—
—
—
—
Multiplexed Input Pins
Analog Pin Name Other Functions Pin Type (I/O)
ANw
—
I
ANx
—
I
ANy
—
I
ANz
—
I
Reserved
—
—
—
I
AN48
—
I
AN49
AN50
—
I
AN51
—
I
—
MA0
I/O
—
MA1
I/O
—
MA2
I/O
AN55
—
I/O
AN56
—
I/O
AN57
—
I/O
AN58
—
I/O
AN59
—
I/O
VRL
—
I
VRH
—
I
—
(VRH -VRL)/2
—
—
End of Queue Code
—
MPC555
USER’S MANUAL
Channel Number in CHAN
Binary
Decimal
00xxx0
0 to 14 even
00xxx1
1 to 15 odd
01xxx0
16 to 30 even
01xxx1
17 to 31 odd
10xxxx
32 to 47
110000
48
110001
49
110010
50
110011
51
110100
52
110101
53
110110
54
110111
55
111000
56
111001
57
111010
58
111011
59
111100
60
111101
61
111110
62
111111
63
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Revised 1 March 1999
MOTOROLA
13-47
13.12.12 Result Word Table
The result word table is a 64-word long, 10-bit wide RAM. The QADC64 writes a result
word after completing an analog conversion specified by the corresponding CCW. The
result word table can be read or written, but in normal operation, software reads the
result word table to obtain analog conversions from the QADC64. Unimplemented bits
are read as zeros, and write operations have no effect.
While there is only one result word table, the data can be accessed in three different
alignment formats:
• Right-justified, with zeros in the higher order unused bits.
• Left-justified, with the most significant bit inverted to form a sign bit, and zeros in
the unused lower order bits.
• Left-justified, with zeros in the unused lower order bits.
The left-justified, signed format corresponds to a half-scale, offset binary, two’s complement data format. The data is routed onto the IMB according to the selected format.
The address used to access the table determines the data alignment format. All write
operations to the result word table are right-justified.
RJURR — Right-Justified, Unsigned Result Register
MSB
0
1
2
3
4
5
6
7
8
0x30 4A80 – 0x30 4AFE
0x30 4E80 – 0x30 4EFE
9
RESERVED
10
11
12
13
14
LSB
15
RESULT
RESET:
0
0
0
0
0
0
The conversion result is unsigned, right-justified data. Unused bits return zero when
read.
LJSRR — Left-Justified, Signed Result Register
0x30 4B00 – 0x30 4B7E
0x30 4F00 – 0x30 4F7E
MSB
0
1
S1
2
3
4
5
6
7
8
9
10
11
RESULT
12
13
14
LSB
15
0
0
RESERVED
RESET:
0
0
0
0
NOTES:
1. S = Sign bit.
The conversion result is signed, left-justified data. Unused bits return zero when read.
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USER’S MANUAL
LJURR — Left-Justified, Unsigned Result Register
MSB
0
1
2
3
4
5
6
7
8
0x30 4B80 – 0x30 4BFE
0x30 4F80 – 0x30 4FFE
9
10
11
RESULT
12
13
14
LSB
15
0
0
RESERVED
RESET:
0
0
0
0
The conversion result is unsigned, left-justified data. Unused bits return zero when
read.
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MOTOROLA
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Revised 1 March 1999
MPC555
USER’S MANUAL
SECTION 14
QUEUED SERIAL MULTI-CHANNEL MODULE
14.1 Overview
The queued serial multi-channel module (QSMCM) provides three serial communication interfaces: the queued serial peripheral interface (QSPI) and two serial
communications interfaces (SCI1 and SCI2). These submodules communicate with
the CPU via a common slave bus interface unit (SBIU).
The QSPI is a full-duplex, synchronous serial interface for communicating with peripherals and other MCUs. It is enhanced from the original SPI in the QSMCM (queued
serial module) to include a total of 160 bytes of queue RAM to accommodate more
receive, transmit, and control information. The QSPI is fully compatible with the SPI
systems found on other Motorola devices.
The dual, independent SCIs are used to communicate with external devices and other
MCUs via an asynchronous serial bus. Each SCI is a full-duplex universal asynchronous receiver transmitter (UART) serial interface. The original QSMCM SCI is
enhanced by the addition of an SCI and a common external baud clock source.
The SCI1 has the ability to use the resultant baud clock from SCI2 as the input clock
source for the SCI1 baud rate generator. Also, the SCI1 has an additional mode of
operation that allows queuing of transmit and receive data frames. If the queue feature
is enabled, a set of 16 entry queues is allocated for the receive and/or transmit
operation.
14.2 Block Diagram
Figure 14-1 depicts the major components of the QSMCM.
MPC555
USER’S MANUAL
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Revised 1 March 1999
MOTOROLA
14-1
IMB3*
SBIU
MISO/QGPIO4
MOSI/QGPIO5
SCK/QGPIO6
7
QSPI QUEUE RAM
Port QS
PCS0/SS/QGPIO0
QSPI
PCS1/QGPIO1
PCS2/QGPIO2
PCS3/QGPIO3
DSCI
2
TXD1/QGPO1
SCI1
RXD1/QGPI1
Receive and Transmit Queue
TXD2/QGPO2
2
SCI2
RXD2/QGPI2
ECK
*Note: SBIU Bus and interface to IMB3 are each 16 bits wide.
Figure 14-1 QSMCM Block Diagram
14.3 Signal Descriptions
The QSMCM has 12 external pins, as shown in Figure 14-1. Seven of the pins, if not
in use for their submodule function, can be used as general-purpose I/O port pins. The
RXDx and TXDx pins can alternately serve as general-purpose input-only and outputonly signals, respectively. ECK is a dedicated clock pin.
For detailed descriptions of QSMCM signals, refer to 14.6 QSMCM Pin Control Registers, 14.7.3 QSPI Pins, and 14.8.6 SCI Pins.
14.4 Memory Map
The QSMCM memory map, shown in Table 14-1, includes the global registers, the
QSPI and dual SCI control and status registers, and the QSPI RAM. The QSMCM
memory map can be divided into supervisor-only data space and assignable data
space. The address offsets shown are from the base address of the QSMCM module.
Refer to 1.3 MPC555 Address Map for a diagram of the MPC555 internal memory
map.
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USER’S MANUAL
Table 14-1 QSMCM Register Map
Access1
Address
S
0x30 5000
T
0x30 5002
S
0x30 5004
S
0x30 5006
S/U
0x30 5008
S/U
0x30 500A
S/U
0x30 500C
S/U
0x30 500E
S/U
S/U
0x30 5010
0x30 5012
S/U
0x30 5014
S/U
0x30 5016
S/U
0x30 5018
S/U
0x30 501A
S/U
0x30 501C
S/U
0x30 501E
S/U
S/U
S/U
S/U
0x30 5020
0x30 5022
0x30 5024
0x30 5026
S/U
0x30 5028
S/U
0x30 502A
MPC555
USER’S MANUAL
MSB2
0
LSB
15
QSMCM Module Configuration Register (QSMCMMCR)
See Table 14-4 for bit descriptions.
QSMCM Test Register (QTEST)
Dual SCI Interrupt Level (QDSCI_IL)
Reserved
See Table 14-5 for bit descriptions.
Queued SPI Interrupt Level (QSPI_IL)
Reserved
See Table 14-6 for bit descriptions.
SCI1Control Register 0 (SCC1R0)
See Table 14-23 for bit descriptions.
SCI1Control Register 1 (SCC1R1)
See Table 14-24 for bit descriptions.
SCI1 Status Register (SC1SR)
See Table 14-25 for bit descriptions.
SCI1 Data Register (SC1DR)
See Table 14-26 for bit descriptions.
Reserved
Reserved
QSMCM Port Q Data Register (PORTQS)
Reserved
See 14.6.1 Port QS Data Register (PORTQS) for bit descriptions.
QSMCM Pin Assignment Register (PQSPAR) QSMCM Data Direction Register (DDRQS)
See Table 14-10 for bit descriptions.
See Table 14-11 for bit descriptions.
QSPI Control Register 0 (SPCR0)
See Table 14-13 for bit descriptions.
QSPI Control Register 1 (SPCR1)
See Table 14-15 for bit descriptions.
QSPI Control Register 2 (SPCR2)
See Table 14-16 for bit descriptions.
QSPI Control Register 3 (SPCR3)
QSPI Status Register (SPSR)
See Table 14-17 for bit descriptions.
See Table 14-18 for bit descriptions.
SCI2 Control Register 0 (SCC2R0)
SCI2 Control Register 1 (SCC2R1)
SCI2 Status Register (SC2SR)
SCI2 Data Register (SC2DR)
QSCI1 Control Register (QSCI1CR)
See Table 14-33 for bit descriptions.
QSCI1 Status Register (QSCI1SR)
See Table 14-34 for bit descriptions.
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Revised 1 March 1999
MOTOROLA
14-3
Table 14-1 QSMCM Register Map (Continued)
Access1
S/U
S/U
S/U
S/U
S/U
S/U
Address
0x30 502C –
0x30 504A
0x30 504C –
0x30 506A
0x30 506C –
0x30 513F3
0x30 5140 –
0x30 517F
0x30 5180 –
0x30 51BF
0x30 51C0 –
0x30 51DF
MSB2
0
LSB
15
Transmit Queue Locations (SCTQ)
Receive Queue Locations (SCRQ)
Reserved
Receive Data RAM (REC.RAM)
Transmit Data RAM (TRAN.RAM)
Command RAM (COMD.RAM)
NOTES:
1. S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
2. 8-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-bit
boundaries.
3. Note that QRAM offsets have been changed from the original (modular family) QSMCM.
The supervisor-only data space segment contains the QSMCM global registers.
These registers define parameters needed by the QSMCM to integrate with the MCU.
Access to these registers is permitted only when the CPU is operating in supervisor
mode.
Assignable data space can be either restricted to supervisor-only access or unrestricted to both supervisor and user accesses. The supervisor (SUPV) bit in the
QSMCM module configuration register (QSMCMMCR) designates the assignable
data space as either supervisor or unrestricted. If SUPV is set, then the space is designated as supervisor-only space. Access is then permitted only when the CPU is
operating in supervisor mode. If SUPV is clear, both user and supervisor accesses are
permitted. To clear SUPV, the CPU must be in supervisor mode.
The QSMCM assignable data space segment contains the control and status registers
for the QSPI and SCI submodules, as well as the QSPI RAM. All registers and RAM
can be accessed on byte (8-bits), half-word (16-bits), and word (32-bit) boundaries.
Word accesses require two consecutive IMB3 bus cycles.
14.5 QSMCM Global Registers
The QSMCM global registers contain system parameters used by the QSPI and SCI
submodules for interfacing to the CPU and the intermodule bus. The global registers
are listed in Table 14-2 QSMCM Global Registers
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MPC555
USER’S MANUAL
Table 14-2 QSMCM Global Registers
Access1
Address
MSB2
S
0x30 5000
QSMCM Module Configuration Register (QSMCMMCR)
See Table 14-4 for bit descriptions.
T
0x30 5002
QSMCM Test Register (QTEST)
S
0x30 5004
Dual SCI Interrupt Level (QDSCI_IL)
See Table 14-5 for bit descriptions.
Reserved
S
0x30 5006
Reserved
Queued SPI Interrupt Level (QSPI_IL)
See Table 14-6 for bit descriptions.
LSB
NOTES:
1. S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
2. 8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries.
14.5.1 Low-Power Stop Operation
When the STOP bit in QSMCMMCR is set, the system clock input to the QSMCM is
disabled and the module enters a low-power operating state. QSMCMMCR is the only
register guaranteed to be readable while STOP is asserted. The QSPI RAM is not
readable in low-power stop mode. However, writes to RAM or any register are guaranteed valid while STOP is asserted. STOP can be written by the CPU and is cleared
by reset.
System software must bring each submodule to an orderly stop before setting STOP
to avoid data corruption. The SCI receiver and transmitter should be disabled after
transfers in progress are complete. The QSPI can be halted by setting the HALT bit in
SPCR3 and then setting STOP after the HALTA flag is set.
14.5.2 Freeze Operation
The FRZ1 bit in QSMCMMCR determines how the QSMCM responds when the IMB3
FREEZE signal is asserted. FREEZE is asserted when the CPU enters background
debug mode. Setting FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE assertion. FREEZE causes the SCI1 transmit queue to halt on the first
transfer boundary following FREEZE assertion.
14.5.3 Access Protection
The SUPV bit in the QMCR defines the assignable QSMCM registers as either supervisor-only data space or unrestricted data space.
When the SUPV bit is set, all registers in the QSMCM are placed in supervisor-only
space. For any access from within user mode, the IMB3 address acknowledge (AACK)
signal is asserted and a bus error is generated.
Because the QSMCM contains a mix of supervisor and user registers, AACK is
asserted for either supervisor or user mode accesses, and the bus cycle remains internal. If a supervisor-only register is accessed in user mode, the module responds as if
MPC555
USER’S MANUAL
QUEUED SERIAL MULTI-CHANNEL MODULE
Revised 1 March 1999
MOTOROLA
14-5
an access had been made to an unauthorized register location, and a bus error is
generated.
14.5.4 QSMCM Interrupts
The interrupt structure of the IMB3 supports a total of 32 interrupt levels that are time
multiplexed on the IRQB[0:7] lines as seen in Figure 14-2.
IMB3 CLOCK
ILBS[1:0]
IMB3 IRQ[7:0]
00
01
10
IRQ
7:0
IRQ
15:8
11
00
01
IRQ
23:16
IRQ
31:24
IRQ
7:0
10
11
Figure 14-2 QSMCM Interrupt Levels
In this structure, all interrupt sources place their asserted level on a time multiplexed
bus during four different time slots, with eight levels communicated per slot. The
ILBS[0:1] signals indicate which group of eight are being driven on the interrupt
request lines.
Table 14-3 Interrupt Levels
ILBS[0:1]
Levels
00
0:7
01
8:15
10
16:23
11
24:31
The QSMCM module is capable of generating one of the 32 possible interrupt levels
on the IMB3. The levels that the interrupt will drive can be programmed into the interrupt request level (ILDSCI and ILQSPI) bits located in the interrupt configuration
register (QDSCI_IL and QSPI_IL). This value determines which interrupt signal
(IRQB[0:7]) is driven onto the bus during the programmed time slot. Figure 14-3
shows a block diagram of the interrupt hardware.
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MPC555
USER’S MANUAL
2
ILBS[1:0]
5
SCI1 and 2 Int
Lev Reg. [4:0]
5
QSPI[4:0] Int
Lev Reg. [4:0]
SCI_1 Interrupt
Interrupt
SCI_2 Interrupt
Level
Encoder
QSPI Interrupt
8
8
Interrupt
Level
Decoder
8
IRQ[7:0]
Figure 14-3 QSPI Interrupt Generation
14.5.5 QSMCM Configuration Register (QSMCMMCR)
The QSMCMMCR contains parameters for interfacing to the CPU and the intermodule
bus. This register can be modified only when the CPU is in supervisor mode.
QSMCMMCR — QSMCM Configuration Register
MSB
0
1
STOP
FRZ1
2
3
4
5
6
7
RESERVED
8
0x30 5000
9
SUPV
10
11
12
13
RESERVED
14
LSB
15
0
0
IARB
RESET:
0
0
0
MPC555
USER’S MANUAL
0
0
0
0
0
1
0
0
0
QUEUED SERIAL MULTI-CHANNEL MODULE
Revised 1 March 1999
0
0
MOTOROLA
14-7
Table 14-4 QSMCMMCR Bit Settings
Bit(s)
Name
Description
0
STOP
Stop enable. Refer to 14.5.1 Low-Power Stop Operation.
0 = Normal clock operation
1 = Internal clocks stopped
1
FRZ1
Freeze1 bit. Refer to 14.5.2 Freeze Operation.
0 = Ignore the FREEZE signal
1 = Halt the QSMCM (on transfer boundary)
2:7
—
8
SUPV
9:11
—
12:15
IARB
Reserved
Supervisor /Unrestricted. Refer to 14.5.3 Access Protection.
0 = Assigned registers are unrestricted (user access allowed)
1 = Assigned registers are restricted (only supervisor access allowed)
Reserved
This field currently has no effect. It is implemented for future interrupt arbitration
schemes.
14.5.6 QSMCM Test Register (QTEST)
The QTEST register is used for factory testing of the MCU.
14.5.7 QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL)
The QDSCI_ILI and QSPI_IL registers determine the interrupt level requested by the
QSMCM. The two SCI submodules (DSCI) share a 5-bit interrupt level field, ILDSCI.
The QSPI uses a separate field, ILQSPI. The level value is used to determine which
interrupt is serviced first when two or more modules or external peripherals simultaneously request an interrupt. The user can select among 32 levels. This register can
be accessed only when the CPU is in supervisor mode.
QDSCI_IL — QSM2 Dual SCI Interrupt Level Register
MSB
0
1
2
3
4
Reserved
5
6
7
8
9
0x30 5004
10
ILDSCI
11
12
13
14
LSB
15
RESERVED
RESET:
0
0
0
0
0
0
0
0
Table 14-5 QDSCI_IL Bit Settings
Bit(s)
Name
0:2
—
3:7
ILSCI1
8:15
—
MOTOROLA
14-8
Description
Reserved
Interrupt level of SCIs
00000 = lowest interrupt level request (level 0)
11111 = highest interrupt level request (level 31)
Reserved
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Revised 1 March 1999
MPC555
USER’S MANUAL
QSPI_IL — QSPI Interrupt Level Register
MSB
0
1
2
3
4
5
6
0x30 5006
7
8
9
10
11
12
13
14
LSB
15
ILQSPI
RESERVED
RESET:
0
0
0
0
0
0
0
0
Table 14-6 QSPI_IL Bit Settings
Bit(s)
Name
0:10
—
11:15
ILQSPI
Description
Reserved
Interrupt level of SCIs
00000 = lowest interrupt level request (level 0)
11111 = highest interrupt level request (level 31)
14.6 QSMCM Pin Control Registers
Table 14-7 lists the three QSMCM pin control registers.
Table 14-7 QSMCM Pin Control Registers
Address
Register
0x30 5014
QSMCM Port Data Register (PORTQS)
See 14.6.1 Port QS Data Register (PORTQS) for bit
descriptions.
0x30 5016
PORTQS Pin Assignment Register (PQSPAR)
See Table 14-11 for bit descriptions.
0x30 5017
PORTQS Data Direction Register (DDRQS)
See Table 14-11 for bit descriptions.
The QSMCM uses 12 pins. Eleven of the pins, when not being used by the serial subsystems, form a parallel port on the MCU. (The ECK pin is a dedicated external clock
source.)
The port QS pin assignment register (PQSPAR) governs the usage of QSPI pins.
Clearing a bit assigns the corresponding pin to general-purpose I/O; setting a bit
assigns the pin to the QSPI.
PQSPAR does not affect operation of the SCI. When the SCIx transmitter is disabled,
TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a discrete
input. When the SCIx transmitter or receiver is enabled, the associated TXDx or RXDx
pin is assigned its SCI function.
The port QS data direction register (DDRQS) determines whether QSPI pins are
inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit
makes the pin an output. DDRQS affects both QSPI function and I/O function. Table
14-10 summarizes the effect of DDRQS bits on QSPI pin function.
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14-9
DDRQS does not affect SCI pin function. TXDx pins are always outputs, and RXDx
pins are always inputs, regardless of whether they are functioning as SCI pins or as
PORTQS pins.
The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins
defined as outputs. PORTQS reads return data present on the pins. To avoid driving
undefined data, write the first data to PORTQS before configuring DDRQS.
Table 14-8 Effect of DDRQS on QSPI Pin Function
QSMCM Pin
Mode
DDRQS Bit
Bit State
0
1
0
1
0
1
0
1
—
—
0
1
0
1
0
1
0
1
Master
MISO
DDQS0
Slave
Master
MOSI
DDQS1
Slave
Master
Slave
SCK1
DDQS2
Master
PCS0/SS
DDQS3
Slave
Master
PCS[1:3]
DDQS[4:6]
Slave
Pin Function
Serial data input to QSPI
Disables data input
Disables data output
Serial data output from QSPI
Disables data output
Serial data output from QSPI
Serial data input to QSPI
Disables data input
Clock output from QSPI
Clock input to QSPI
Assertion causes mode fault
Chip-select output
QSPI slave select input
Disables slave select input
Disables chip-select output
Chip-select output
Inactive
Inactive
NOTES:
1. SCK/QGPIO6 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which
case it becomes the QSPI serial clock SCK.
14.6.1 Port QS Data Register (PORTQS)
PORTQS determines the actual input or output value of a QSMCM port pin if the pin
is defined as general-purpose input or output. All QSMCM pins except the ECK pin can
be used as general-purpose input and/or output. When the SCIx transmitter is disabled, TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a
discrete input. Writes to this register affect the pins defined as outputs; reads of this
register return the actual value of the pins.
PORTQS — Port QS Data Register
MSB
0
1
2
3
RESERVED
4
5
0x30 5014
6
7
QDRXD2 QDTXD2 QDRXD1 QDTXD1
8
0
9
10
11
12
QDPCS3 QDPCS2 QDPCS1 QDPCS0
13
QDSCK
14
LSB
15
QDMOSI QDMISO
RESET:
0
0
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0
1
0
1
0
0
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Revised 1 March 1999
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0
0
0
MPC555
USER’S MANUAL
14.6.2 PORTQS Pin Assignment Register (PQSPAR)
PQSPAR determines which of the QSPI pins, with the exception of the SCK pin, are
used by the QSPI submodule, and which pins are available for general-purpose I/O.
Pins may be assigned on a pin-by-pin basis. If the QSPI is disabled, the SCK pin is
automatically assigned its general-purpose I/O function (QGPIO6).
QSPI pins designated by PQSPAR as general-purpose I/O pins are controlled only by
PQSDDR and PQSPDR; the QSPI has no effect on these pins. PQSPAR does not
affect the operation of the SCI submodule.
Table 14-9 summarizes the QSMCM pin functions.
Table 14-9 QSMCM Pin Functions
PORTQS Function
QSMCM Function
QGPI2
RXD2
QGPO2
TXD2
QGPI1
RXD1
QGPO1
TXD1
QGPIO6
SCK
QGPIO5
MOSI
QGPIO4
MISO
QGPIO3
PCS3
QGPIO2
PCS2
QGPIO1
PCS1
QGPIO0
PCS0
PQSPAR — PORTQS Pin Assignment Register
MSB
0
0
1
2
3
4
QPAPCS3 QPAPCS2 QPAPCS1 QPAPCS0
5
0
6
7
8
0x30 5016
9
QPAMOSI QPAMISO
10
11
12
13
14
LSB
15
DDRQS*
RESET:
0
0
0
0
0
0
0
0
*See bit descriptions in Table 14-11.
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Revised 1 March 1999
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14-11
Table 14-10 PQSPAR Bit Settings
Bit(s)
Name
Description
0
—
1
QPAPCS3
0 = Pin is assigned QGPIO3
1 = Pin is assigned PCS3 function
2
QPAPCS2
0 = Pin is assigned QGPIO2
1 = Pin is assigned PCS2 function
3
QPAPCS1
0 = Pin is assigned QGPIO1
1 = Pin is assigned PCS1 function
4
QPAPCS0
0 = Pin is assigned QGPIO0
1 = Pin is assigned PCS0 function
5
—
6
QPAMOSI
0 = Pin is assigned QGPIO5
1 = Pin is assigned MOSI function
7
QPAMISO
0 = Pin is assigned QGPIO4
1 = Pin is assigned MISO function
8:15
DDRQS
Reserved
Reserved
PORSTQS data direction register. See 14.6.3 PORTQS Data Direction Register
(DDRQS).
14.6.3 PORTQS Data Direction Register (DDRQS)
DDRQS assigns QSPI pin as an input or an output regardless of whether the QSPI
submodule is enabled or disabled. All QSPI pins are configured during reset as general-purpose inputs.
This register does not affect SCI operation. The TXD1 and TXD2 remain output pins
dedicated to the SCI submodules, and the RXD1, RXD2 and ECK pins remain input
pins dedicated to the SCI submodules.
DDRQS — PORTQS Data Direction Register
MSB
0
1
2
3
4
5
PQSPAR*
6
7
0x30 5016
8
0
9
10
11
12
13
14
LSB
15
QDDPCS3QDDPCS2QDDPCS1QDDPCS0 QDDSCK QDDMOSI QDDMISO
RESET:
0
0
0
0
0
0
0
0
*See bit descriptions in Table 14-10.
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Table 14-11 DDRQS Bit Settings
Bit(s)
Name
Description
0:7
PQSPAR
8
—
9
QDDPCS3
QSPI pin data direction for the pin PCS3
0 = Pin direction is input
1 = Pin direction is output
10
QDDPCS2
QSPI pin data direction for the pin PCS2
0 = Pin direction is input
1 = Pin direction is output
11
QDDPCS1
QSPI pin data direction for the pin PCS1
0 = Pin direction is input
1 = Pin direction is output
12
QDDPCS0
QSPI pin data direction for the pin PCS0
0 = Pin direction is input
1 = Pin direction is output
13
QDDSCK
QSPI pin data direction for the pin SCK
0 = Pin direction is input
1 = Pin direction is output
14
QPAMOSI
QSPI pin data direction for the pin MOSI
0 = Pin direction is input
1 = Pin direction is output
15
QPAMISO
QSPI pin data direction for the pin MISO
0 = Pin direction is input
1 = Pin direction is output
PORTSQS pin assignment register. See 14.6.2 PORTQS Pin Assignment Register
(PQSPAR).
Reserved
14.7 Queued Serial Peripheral Interface
The queued serial peripheral interface (QSPI) is used to communicate with external
devices through a synchronous serial bus. The QSPI is fully compatible with SPI systems found on other Motorola products, but has enhanced capabilities. The QSPI can
perform full duplex three-wire or half duplex two-wire transfers. Several transfer rates,
clocking, and interrupt-driven communication options are available. Figure 14-4 is a
block diagram of the QSPI.
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MOTOROLA
14-13
QUEUE CONTROL
BLOCK
QUEUE
POINTER
COMPARATOR
4
A
D
D
R
E
S
S
DONE
4
END QUEUE
POINTER
160-BYTE
QSPI RAM
R
E
G
I
S
T
E
R
CONTROL
LOGIC
STATUS
REGISTER
CONTROL
REGISTERS
4
DELAY
COUNTER
CHIP SELECT
4
COMMAND
MSB
M
S
LSB
8/16-BIT SHIFT REGISTER
PROGRAMMABLE
LOGIC ARRAY
MOSI
Rx/Tx DATA REGISTER
M
S
MISO
PCS0/SS
2
PCS[2:1]
BAUD RATE
GENERATOR
SCK
QSPI BLOCK
Figure 14-4 QSPI Block Diagram
Serial transfers of eight to 16 bits can be specified. Programmable transfer length simplifies interfacing to devices that require different data lengths.
An inter-transfer delay of approximately 0.8 to 204 µs (using a 40-MHz system clock)
can be programmed. The default delay is 17 clocks (0.425 µs at 40 MHz). Programmable delay simplifies the interface to devices that require different delays between
transfers.
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MPC555
USER’S MANUAL
A dedicated 160-byte RAM is used to store received data, data to be transmitted, and
a queue of commands. The CPU can access these locations directly. This allows serial
peripherals to be treated like memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 32 serial transfers without CPU
intervention. Each queue entry contains all the information needed by the QSPI to
independently complete one serial transfer.
A pointer identifies the queue location containing the data and command for the next
serial transfer. Normally, the pointer address is incremented after each serial transfer,
but the CPU can change the pointer value at any time. Support for multiple-tasks can
be provided by segmenting the queue.
The QSPI has four peripheral chip-select pins. The chip-select signals simplify interfacing by reducing CPU intervention. If the chip-select signals are externally decoded,
16 independent select signals can be generated.
Wrap-around mode allows continuous execution of queued commands. In wraparound mode, newly received data replaces previously received data in the receive
RAM. Wrap-around mode can simplify the interface with A/D converters by continuously updating conversion values stored in the RAM.
Continuous transfer mode allows transfer of an uninterrupted bit stream. From 8 to 512
bits can be transferred without CPU intervention. Longer transfers are possible, but
minimal intervention is required to prevent loss of data. A standard delay of 17 system
clocks (0.8 µs with a 40-MHz system clock) is inserted between the transfer of each
queue entry.
14.7.1 QSPI Registers
The QSPI memory map, shown in Table 14-12, includes the QSMCM global and pin
control registers, four QSPI control registers (SPCR[0:3]), the status register (SPSR),
and the QSPI RAM. Registers and RAM can be read and written by the CPU. The
memory map can be divided into supervisor-only data space and assignable data
space. The address offsets shown are from the base address of the QSMCM module.
Refer to 1.3 MPC555 Address Map for a diagram of the MPC555 internal memory
map.
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14-15
Table 14-12 QSPI Register Map
Access1
Address
MSB2
S/U
0x30 5018
QSPI Control Register 0 (SPCR0)
See Table 14-13 for bit descriptions.
S/U
0x30 501A
QSPI Control Register 1 (SPCR1)
See Table 14-15 for bit descriptions.
S/U
0x30 501C
QSPI Control Register 2 (SPCR2)
See Table 14-16 for bit descriptions.
S/U
0x30 501E/
0x30 501F
S/U
0x30 5140 –
0x30 517F
Receive Data RAM (32 half-words)
S/U
0x30 5180 –
0x30 51BF
Transmit Data RAM (32 half-words)
S/U
0x30 51C0 –
0x30 51DF
Command RAM (32 bytes)
LSB
QSPI Control Register 3 (SPCR3)
See Table 14-17 for bit descriptions.
QSPI Status Register (SPSR)
See Table 14-18 for bit descriptions.
NOTES:
1. S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
2. 8-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-bit
boundaries.
To ensure proper operation, set the QSPI enable bit (SPE) in SPCR1 only after initializing the other control registers. Setting this bit starts the QSPI.
Rewriting the same value to a control register does not affect QSPI operation with the
exception of writing NEWQP in SPCR2. Rewriting the same value to these bits causes
the RAM queue pointer to restart execution at the designated location.
Before changing control bits, the user should halt the QSPI. Writing a different value
into a control register other than SPCR2 while the QSPI is enabled may disrupt operation. SPCR2 is buffered, preventing any disruption of the current serial transfer. After
the current serial transfer is completed, the new SPCR2 value becomes effective.
14.7.1.1 QSPI Control Register 0
SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU
has read/write access to SPCR0, but the QSPI has read access only. SPCR0 must be
initialized before QSPI operation begins. Writing a new value to SPCR0 while the
QSPI is enabled disrupts operation.
SPCR0 — QSPI Control Register 0
MSB
0
1
2
3
MSTR WOMQ
4
5
BITS
0x30 5018
6
7
8
9
10
11
CPOL CPHA
12
13
14
LSB
15
1
0
0
SPBR
RESET:
0
0
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0
0
0
1
0
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USER’S MANUAL
Table 14-13 SPCR0 Bit Settings
Bit(s)
Name
0
MSTR
Master/slave mode select
0 = QSPI is a slave device and only responds to externally generated serial transfers.
1 = QSPI is the system master and can initiate transmission to external SPI devices.
WOMQ
Wired-OR mode for QSPI pins. This bit controls the QSPI pins regardless of whether they are
used as general-purpose outputs or as QSPI outputs, and regardless of whether the QSPI is
enabled or disabled.
0 = Pins designated for output by DDRQS operate in normal mode.
1 = Pins designated for output by DDRQS operate in open drain mode.
1
2:5
BITS
Description
Bits per transfer. In master mode, when BITSE is set in a command RAM byte, BITS determines
the number of data bits transferred. When BITSE is cleared, eight bits are transferred regardless
of the value in BITS. In slave mode, the BITS field always determines the number of bits the QSPI
will receive during each transfer before storing the received data.
Data transfers from 8 to 16 bits are supported. Illegal (reserved) values default to eight bits.Table
14-14 shows the number of bits per transfer.
6
7
CPOL
Clock polarity. CPOL is used to determine the inactive state of the serial clock (SCK). It is used
with CPHA to produce a desired clock/data relationship between master and slave devices.
0 = The inactive state of SCK is logic zero.
1 = The inactive state of SCK is logic one.
CPHA
Clock phase. CPHA determines which edge of SCK causes data to change and which edge
causes data to be captured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices.
0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK.
1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
Serial clock baud rate. The QSPI uses a modulus counter to derive the SCK baud rate from the
MCU system clock. Baud rate is selected by writing a value from 2 to 255 into SPBR. The following equation determines the SCK baud rate:
8:15
SPBR
f
SYS
SCK Baud Rate = --------------------------2 × SPBR
Refer to 14.7.5.2 Baud Rate Selection for more information.
Table 14-14 Bits Per Transfer
BITS[3:0]
0000
0001 to 0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits per Transfer
16
Reserved (defaults to 8)
8
9
10
11
12
13
14
15
14.7.1.2 QSPI Control Register 1
SPCR1 enables the QSPI and specifies transfer delays. The CPU has read/write
access to SPCR1, but the QSPI has read access only to all bits except SPE. SPCR1
must be written last during initialization because it contains SPE. The QSPI automatiMPC555
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Revised 1 March 1999
MOTOROLA
14-17
cally clears this bit after it completes all serial transfers or when a mode fault occurs.
Writing a new value to SPCR1 while the QSPI is enabled disrupts operation.
SPCR1 — QSPI Control Register 1
MSB
0
1
2
3
SPE
4
5
0x30 501A
6
7
8
9
10
11
DSCKL
12
13
14
LSB
15
0
1
0
0
DTL
RESET:
0
0
0
0
0
1
0
0
0
0
0
0
Table 14-15 SPCR1 Bit Settings
Bit(s)
Name
0
SPE
Description
QSPI enable. Refer to 14.7.4.1 Enabling, Disabling, and Halting the SPI.
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
Delay before SCK. When the DSCK bit is set in a command RAM byte, this field determines the
length of the delay from PCS valid to SCK transition. The following equation determines the
actual delay before SCK:
1:7
DSCKL
DSCKL
PCS to SCK Delay = -------------------fSYS
where DSCKL equals is in the range of 1 to 127.
Refer to 14.7.5.3 Delay Before Transfer for more information.
Length of delay after transfer. When the DT bit is set in a command RAM byte, this field determines the length of the delay after a serial transfer. The following equation is used to calculate
the delay:
8:15
DTL
32 × D TL
Delay after Transfer = ------------------------f
SYS
where DTL is in the range of 1 to 255.
A zero value for DTL causes a delay-after-transfer value of 8192 ÷ fSYS (204.8 µs with a 40-MHz
system clock).
Refer to 14.7.5.4 Delay After Transfer for more information.
14.7.1.3 QSPI Control Register 2
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt
enable bit. The CPU has read/write access to SPCR2, but the QSPI has read access
only. Writes to this register are buffered. New SPCR2 values become effective only
after completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes
execution to restart at the designated location. Reads of SPCR2 return the current
value of the register, not the buffer.
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USER’S MANUAL
SPCR2 — QSPI Control Register 2
MSB
0
1
2
3
4
SPIFIE WREN WRTO
5
0x30 501C
6
7
8
ENDQP
9
10
11
12
Reserved
13
14
LSB
15
0
0
NEWQP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 14-16 SPCR2 Bit Settings
Bit(s)
Name
Description
0
SPIFIE
SPI finished interrupt enable. Refer to 14.7.4.2 QSPI Interrupts.
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
1
WREN
Wrap enable. Refer to 14.7.5.7 Master Wraparound Mode.
0 = Wraparound mode disabled.
1 = Wraparound mode enabled.
WRTO
Wrap to. When wraparound mode is enabled and after the end of queue has been reached,
WRTO determines which address the QSPI executes next. The end of queue is determined by
an address match with ENDQP.
0 = Wrap to pointer address 0x0
1 = Wrap to address in NEWQP
3:7
ENDQP
Ending queue pointer. This field determines the last absolute address in the queue to be completed by the QSPI. After completing each command, the QSPI compares the queue pointer
value of the just-completed command with the value of ENDQP. If the two values match, the
QSPI sets SPIF to indicate it has reached the end of the programmed queue. Refer to 14.7.4
QSPI Operation for more information.
8:10
—
11:15
NEWQP
2
Reserved
New queue pointer value. This field contains the first QSPI queue address. Refer to 14.7.4 QSPI
Operation for more information.
14.7.1.4 QSPI Control Register 3
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and
the halt control bit. The CPU has read/write access to SPCR3, but the QSPI has read
access only. SPCR3 must be initialized before QSPI operation begins. Writing a new
value to SPCR3 while the QSPI is enabled disrupts operation.
SPCR3 — QSPI Control Register
MSB
0
1
2
3
4
Reserved
5
0x30 501E
6
LOOPQ HMIE
7
8
9
HALT
10
11
12
13
14
LSB
15
SPSR*
RESET:
0
0
0
0
0
0
0
0
*See bit descriptions in Table 14-18.
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Table 14-17 SPCR3 Bit Settings
Bit(s)
Name
0:4
—
5
LOOPQ
Description
Reserved
QSPI loop mode. LOOPQ controls feedback on the data serializer for testing.
0 = Feedback path disabled.
1 = Feedback path enabled.
HMIE
HALTA and MODF interrupt enable. HMIE enables interrupt requests generated by the HALTA
status flag or the MODF status flag in SPSR.
0 = HALTA and MODF interrupts disabled.
1 = HALTA and MODF interrupts enabled.
7
HALT
Halt QSPI. When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state
from which it can later be restarted. Refer to 14.7.4.1 Enabling, Disabling, and Halting the SPI.
0 = QSPI operates normally.
1 = QSPI is halted for subsequent restart.
8:15
—
6
SPSR. SeeTable 14-18 for bit descriptions.
14.7.1.5 QSPI Status Register
The SPSR contains information concerning the current serial transmission. Only the
QSPI can set bits in this register. To clear status flags, the CPU reads SPSR with the
flags set and then writes the SPSR with zeros in the appropriate bits. Writes to CPTQP
have no effect.
SPSR — QSPI Status Register
MSB
0
1
2
3
4
5
SPCR3*
0x30 501E
6
7
8
SPIF
0
9
10
11
12
MODF HALTA
0
0
13
14
LSB
15
0
0
CPTQP
0
0
0
*See bit descriptions in Table 14-17.
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Table 14-18 SPSR Bit Settings
Bit(s)
Name
0:7
SPCR3
8
9
10
SPIF
MODF
HALTA
Description
See bit descriptions in Table 14-17.
QSPI finished flag. SPIF is set after execution of the command at the address in ENDQP in
SPCR2. If wraparound mode is enabled (WREN = 1), the SPIF is set, after completion of the
command defined by ENDQP, each time the QSPI cycles through the queue.
0 = QSPI is not finished
1 = QSPI is finished
Mode fault flag. The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the
SS input pin is negated by an external driver. Refer to 14.7.8 Mode Fault for more information.
0 = Normal operation
1 = Another SPI node requested to become the network SPI master while the QSPI was enabled
in master mode (SS input taken low).
Halt acknowledge flag. HALTA is set when the QSPI halts in response to setting the HALT bit in
SPCR3. HALTA is also set when the IMB3 FREEZE signal is asserted, provided the FRZ1 bit in
the QSMCMMCR is set. To prevent undefined operation, the user must not modify any QSPI
control registers or RAM while the QSPI is halted.
If HMIE in SPCR3 is set the QSPI sends interrupt requests to the CPU when HALTA is asserted.
0 = QSPI is not halted.
1 = QSPI is halted
11:15
CPTQP
Completed queue pointer. CPTQP points to the last command executed. It is updated when the
current command is complete. When the first command in a queue is executing, CPTQP contains
either the reset value 0x0 or a pointer to the last command completed in the previous queue.
If the QSPI is halted, CPTQP may be used to determine which commands have not been executed. The CPTQP may also be used to determine which locations in the receive data segment
of the QSPI RAM contain valid received data.
14.7.2 QSPI RAM
The QSPI contains a 160-byte block of dual-ported static RAM that can be accessed
by both the QSPI and the CPU. Because of this dual access capability, up to two wait
states may be inserted into CPU access time if the QSPI is in operation.
The size and type of access of the QSPI RAM by the CPU affects the QSPI access
time. The QSPI allows byte, half-word, and word accesses. Only word accesses of the
RAM by the CPU are coherent because these accesses are an indivisible operation.
If the CPU makes a coherent access of the QSPI RAM, the QSPI cannot access the
QSPI RAM until the CPU is finished. However, a word or misaligned word access is
not coherent because the CPU must break its access of the QSPI RAM into two parts,
which allows the QSPI to access the QSPI RAM between the two accesses by the
CPU.
The RAM is divided into three segments: receive data RAM, transmit data RAM, and
command data RAM. Receive data is information received from a serial device external to the MCU. Transmit data is information stored for transmission to an external
device. Command data defines transfer parameters. Figure 14-5 shows RAM
organization.
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MOTOROLA
14-21
RR0
RR1
RR2
0X140
0X180
TR0
TR1
TR2
0X1C0
CR0
CR1
CR2
Receive
RAM
Transmit
RAM
Command
RAM
RRD
RRE
RRF
TRD
TRE
TRF
CRD
CRE
CRF
0X17F
Half-Word
0X1BF
0X1DF
Half-Word
Byte
Figure 14-5 QSPI RAM
14.7.2.1 Receive RAM
Data received by the QSPI is stored in this segment, to be read by the CPU. Data
stored in the receive RAM is right-justified, i.e., the least significant bit is always in the
right-most bit position within the word regardless of the serial transfer length. Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using byte, half-word, or word
addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU
uses this information to determine which locations in receive RAM contain valid data
before reading them.
14.7.2.2 Transmit RAM
Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally
writes one word of data into this segment for each queue command to be executed. If
the corresponding peripheral, such as a serial input port, is used solely to input data,
then this segment does not need to be initialized.
Data must be written to transmit RAM in a right-justified format. The QSPI cannot modify information in the transmit RAM. The QSPI copies the information to its data
serializer for transmission. Information remains in transmit RAM until overwritten.
14.7.2.3 Command RAM
Command RAM is used by the QSPI in master mode. The CPU writes one byte of control information to this segment for each QSPI command to be executed. The QSPI
cannot modify information in command RAM.
Command RAM consists of 32 bytes. Each byte is divided into two fields. The peripheral chip-select field, enables peripherals for transfer. The command control field
provides transfer options.
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USER’S MANUAL
A maximum of 32 commands can be in the queue. These bytes are assigned an
address from 0x00 to 0x1F. Queue execution by the QSPI proceeds from the address
in NEWQP through the address in ENDQP. (Both of these fields are in SPCR2.)
CR[0:F] — Command RAM
0x30 51C0 – 0x30 51DF
7
6
5
4
3
2
1
0
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS01
—
—
—
—
—
—
—
—
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS01
Command Control
Peripheral Chip Select
NOTES:
1. The PCS0 bit represents the dual-function PCS0/SS.
Table 14-19 Command RAM Bit Settings
Bit(s)
Name
Description
0
CONT
Continue
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete.
1
BITSE
Bits per transfer enable
0 = Eight bits
1 = Number of bits set in BITS field of SPCR0.
2
DT
3
DSCK
4:7
PCS[3:0]
Delay after transfer
0 = Delay after transfer is 17 ÷ fSYS.
1 = SPCR1 DTL[7:0] specifies delay after transfer PCS valid to SCK.
PCS to SCK Delay
0 = PCS valid to SCK delay is one-half SCK.
1 = SPCR1 DSCKL[6:0] specifies delay from PCS valid to SCK.
Peripheral chip selects. Use peripheral chip-select bits to select an external device for serial data
transfer. More than one peripheral chip select may be activated at a time, and more than one
peripheral chip can be connected to each PCS pin, provided proper fanout is observed. PCS0
shares a pin with the slave select (SS) signal, which initiates slave mode serial transfer. If SS is
taken low when the QSPI is in master mode, a mode fault occurs.
Refer to 14.7.5 Master Mode Operation for more information on the command RAM.
14.7.3 QSPI Pins
Seven pins are associated with the QSPI. When not needed by the QSPI, they can be
configured for general-purpose I/O. Table 14-20 identifies the QSPI pins and their
functions. Register DDRQS determines whether the pins are designated as input or
output. The user must initialize DDRQS for the QSPI to function correctly.
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Table 14-20 QSPI Pin Functions
Pin Names
Mnemonic
Mode
Master in slave out
MISO
Master
Slave
Serial data input to QSPI
Serial data output from QSPI
Master out slave in
MOSI
Master
Slave
Serial data output from QSPI
Serial data input to QSPI
Serial clock
SCK1
Master
Slave
Clock output from QSPI clock
Input to QSPI
PCS[1:3]
Master
Outputs select peripheral(s)
PCS0/
SS
Master
Slave
Output selects peripheral(s)
Input selects the QSPI
SS
Master
May cause mode fault
Peripheral chip selects
Peripheral chip
Slave select3
Slave select4
select2
Function
NOTES:
1. All QSPI pins (except SCK) can be used as general-purpose I/O if they are not used by the QSPI while the QSPI
is operating. SCK can only be used for general-purpose I/O if the QSPI is disabled.
2. An output (PCS0) when the QSPI is in master mode.
3. An input (SS) when the QSPI is in slave mode.
4. An input (SS) when the QSPI is in master mode; useful in multimaster systems.
14.7.4 QSPI Operation
The QSPI uses a dedicated 160-byte block of static RAM accessible by both the QSPI
and the CPU to perform queued operations. The RAM is divided into three segments:
32 command control bytes, 64 transmit data bytes, and 64 receive data bytes.
Once the CPU has set up a queue of QSPI commands, written the transmit data segment with information to be sent, and enabled the QSPI, the QSPI operates
independently of the CPU. The QSPI executes all of the commands in its queue, sets
a flag indicating completion, and then either interrupts the CPU or waits for CPU
intervention.
QSPI RAM is organized so that one byte of command data, one word of transmit data,
and one word of receive data correspond to each queue entry, 0x0 to 0x2F.
The CPU initiates QSPI operation by setting up a queue of QSPI commands in command RAM, writing transmit data into transmit RAM, then enabling the QSPI. The
QSPI executes the queued commands, sets a completion flag (SPIF), and then either
interrupts the CPU or waits for intervention.
There are four queue pointers. The CPU can access three of them through fields in
QSPI registers. The new queue pointer (NEWQP), contained in SPCR2, points to the
first command in the queue. An internal queue pointer points to the command currently
being executed. The completed queue pointer (CPTQP), contained in SPSR, points to
the last command executed. The end queue pointer (ENDQP), contained in SPCR2,
points to the final command in the queue.
The internal pointer is initialized to the same value as NEWQP. During normal operation, the command pointed to by the internal pointer is executed, the value in the
internal pointer is copied into CPTQP, the internal pointer is incremented, and then the
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sequence repeats. Execution continues at the internal pointer address unless the
NEWQP value is changed. After each command is executed, ENDQP and CPTQP are
compared. When a match occurs, the SPIF flag is set and the QSPI stops and clears
SPE, unless wraparound mode is enabled.
At reset, NEWQP is initialized to 0x0. When the QSPI is enabled, execution begins at
queue address 0x0 unless another value has been written into NEWQP. ENDQP is initialized to 0x0 at reset but should be changed to the last queue entry before the QSPI
is enabled. NEWQP and ENDQP can be written at any time. When NEWQP changes,
the internal pointer value also changes. However, if NEWQP is written while a transfer
is in progress, the transfer is completed normally. Leaving NEWQP and ENDQP set
to 0x0 transfers only the data in transmit RAM location 0x0.
14.7.4.1 Enabling, Disabling, and Halting the SPI
The SPE bit in the SPCR1 enables or disables the QSPI submodule. Setting SPE
causes the QSPI to begin operation. If the QSPI is a master, setting SPE causes the
QSPI to begin initiating serial transfers. If the QSPI is a slave, the QSPI begins monitoring the PCS0/SS pin to respond to the external initialization of a serial transfer.
When the QSPI is disabled, the CPU may use the QSPI RAM. When the QSPI is
enabled, both the QSPI and the CPU have access to the QSPI RAM. The CPU has
both read and write access to all 160 bytes of the QSPI RAM. The QSPI can read-only
the transmit data segment and the command control segment and can write-only the
receive data segment of the QSPI RAM.
The QSPI turns itself off automatically when it is finished by clearing SPE. An error
condition called mode fault (MODF) also clears SPE. This error occurs when PCS0/
SS is configured for input, the QSPI is a system master (MSTR = 1), and PCS0/SS is
driven low externally.
Setting the HALT bit in SPCR3 stops the QSPI on a queue boundary. The QSPI halts
in a known state from which it can later be restarted. When HALT is set, the QSPI finishes executing the current serial transfer (up to 16 bits) and then halts. While halted,
if the command control bit (CONT of the QSPI RAM) for the last command was
asserted, the QSPI continues driving the peripheral chip select pins with the value designated by the last command before the halt. If CONT was cleared, the QSPI drives
the peripheral chip-select pins to the value in register PORTQS.
If HALT is set during the last command in the queue, the QSPI completes the last command, sets both HALTA and SPIF, and clears SPE. If the last queue command has
not been executed, asserting HALT does not set SPIF or clear SPE. QSPI execution
continues when the CPU clears HALT.
To stop the QSPI, assert the HALT bit in SPCR3, then wait until the HALTA bit in SPSR
is set. SPE can then be safely cleared, providing an orderly method of shutting down
the QSPI quickly after the current serial transfer is completed. The CPU can disable
the QSPI immediately by clearing SPE. However, loss of data from a current serial
transfer may result and confuse an external SPI device.
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14.7.4.2 QSPI Interrupts
The QSPI has three possible interrupt sources but only one interrupt vector. These
sources are SPIF, MODF, and HALTA. When the CPU responds to a QSPI interrupt,
the user must ascertain the interrupt cause by reading the SPSR. Any interrupt that
was set may then be cleared by writing to SPSR with a zero in the bit position corresponding to the interrupt source.
The SPIFIE bit in SPCR2 enables the QSPI to generate an interrupt request upon
assertion of the SPIF status flag. Because it is buffered, the value written to SPIFIE
applies only upon completion of the queue (the transfer of the entry indicated by
ENDPQ). Thus, if a single sequence of queue entries is to be transferred (i.e., no
WRAP), then SPIFIE should be set to the desired state before the first transfer.
If a sub-queue is to be used, the same CPU write that causes a branch to the subqueue may enable or disable the SPIF interrupt for the sub-queue. The primary queue
retains its own selected interrupt mode, either enabled or disabled.
The SPIF interrupt must be cleared by clearing SPIF. Subsequent interrupts may then
be prevented by clearing SPIFIE. Clearing SPIFIE does not immediately clear an interrupt already caused by SPIF.
14.7.4.3 QSPI Flow
The QSPI operates in either master or slave mode. Master mode is used when the
MCU initiates data transfers. Slave mode is used when an external device initiates
transfers. Switching between these modes is controlled by MSTR in SPCR0. Before
entering either mode, appropriate QSMCM and QSPI registers must be initialized
properly.
In master mode, the QSPI executes a queue of commands defined by control bits in
each command RAM queue entry. Chip-select pins are activated, data is transmitted
from the transmit RAM and received by the receive RAM.
In slave mode, operation proceeds in response to SS pin assertion by an external SPI
bus master. Operation is similar to master mode, but no peripheral chip selects are
generated, and the number of bits transferred is controlled in a different manner. When
the QSPI is selected, it automatically executes the next queue transfer to exchange
data with the external device correctly.
Although the QSPI inherently supports multi-master operation, no special arbitration
mechanism is provided. A mode fault flag (MODF) indicates a request for SPI master
arbitration. System software must provide arbitration. Note that unlike previous SPI
systems, MSTR is not cleared by a mode fault being set nor are the QSPI pin output
drivers disabled. The QSPI and associated output drivers must be disabled by clearing
SPE in SPCR1.
Figure 14-6 shows QSPI initialization. Figure 14-7 through Figure 14-11 show QSPI
master and slave operation. The CPU must initialize the QSMCM global and pin registers and the QSPI control registers before enabling the QSPI for either mode of
operation. The command queue must be written before the QSPI is enabled for master
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mode operation. Any data to be transmitted should be written into transmit RAM before
the QSPI is enabled. During wraparound operation, data for subsequent transmissions
can be written at any time.
Begin
Initialize QSMCM
Global Registers
Initialize PQSPAR,
PORTQS, and DDRQS
in this Order
QSPI Initialization
Initialize QSPI
Control Registers
Initialize QSPI RAM
Enable QSPI
Y
MSTR = 1 ?
N
A2
A1
Figure 14-6 Flowchart of QSPI Initialization Operation
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QSPI Cycle Begins
(Master Mode)
A1
Is QSPI
Disabled?
Y
N
Has NEWQP
Been Written?
Y
Working Queue Pointer
Changed to NEWQP
N
Read Command Control
and Transmit Data
From RAM Using Queue
Pointer Address
Assert Peripheral
Chip Select(s)
Is PCS To
SCK Delay
Programmed?
Y
Execute Programmed Delay
N
Execute Standard Delay
Execute Serial Transfer
Store Received Data
In RAM Using Queue
Pointer Address
B1
Figure 14-7 Flowchart of QSPI Master Operation (Part 1)
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B1
Write Queue Pointer
To CPTQP Status Bits
Is Continue
Bit Asserted?
Y
N
Negate Peripheral
Chip Selects
Is Delay
After Transfer
Asserted?
Y
Execute Programmed Delay
N
Execute Standard Delay
C1
Figure 14-8 Flowchart of QSPI Master Operation (Part 2)
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C1
Is this the
Last Command
in the Queue?
Y
Assert SPIF
Status Flag
N
Is Interrupt
Enable Bit SPIFIE
Set?
Y
Request Interrupt
N
Increment Working
Queue Pointer
Is Wrap
Enable Bit
Set?
Y
Reset Working Queue
Pointer to NEWQP or 0x0000
N
Disable QSPI
A1
Is HALT
Or FREEZE
Asserted?
Y
Halt QSPI and
Set HALTA
N
Is Interrupt
Enable Bit
HMIE Set?
Y
Request Interrupt
N
Is HALT
Or FREEZE
Asserted?
Y
N
A1
Figure 14-9 Flowchart of QSPI Master Operation (Part 3)
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QSPI Cycle Bgins
(Slave Mode
A2
Is QSPI
Disabled?
Y
N
Has NEWQP
Been Written?
Y
Queue Pointer
Changed to NEWQP
N
Read Transmit Data
From RAM Using Queue
Pointer Address
Is Slave
Select Pin
Asserted?
Y
N
Execute Serial Transfer
When SCK Received
Store Received Data
In RAM Using Queue
Pointer Address
Write Queue Pointer to
CPTQP Status Bits
B2
Figure 14-10 Flowchart of QSPI Slave Operation (Part 1)
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C2
Is this the
Last Command
in the Queue?
Y
Set SPIF
Status Flag
N
Is Interrupt
Enable Bit
SPIFIE Set?
Y
Request Interrupt
N
Is Wrap
Enable Bit
Asserted?
Increment Working
Queue Pointer
Y
Reset Working Queue
Pointer To NEWQP or 0x0000
N
Disable QSPI
A2
Is HALT
or FREEZE
Asserted?
Y
Halt QSPI and
Set HALTA
N
Is Interrupt
Enable Bit
HMIE Set?
Y
Request Interrupt
N
Is HALT
Or FREEZE
Asserted?
Y
N
A2
QSPI SLV2 FLOW6
Figure 14-11 Flowchart of QSPI Slave Operation (Part 2)
Normally, the SPI bus performs synchronous bi-directional transfers. The serial clock
on the SPI bus master supplies the clock signal SCK to time the transfer of data. Four
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possible combinations of clock phase and polarity can be specified by the CPHA and
CPOL bits in SPCR0.
Data is transferred with the most significant bit first. The number of bits transferred per
command defaults to eight, but can be set to any value from eight to sixteen bits by
writing a value into the BITS field in SPCR0 and setting BITSE in command RAM.
Typically, SPI bus outputs are not open drain unless multiple SPI masters are in the
system. If needed, the WOMQ bit in SPCR0 can be set to provide wired-OR, open
drain outputs. An external pull-up resistor should be used on each output line. WOMQ
affects all QSPI pins regardless of whether they are assigned to the QSPI or used as
general-purpose I/O.
14.7.5 Master Mode Operation
Setting the MSTR bit in SPCR0 selects master mode operation. In master mode, the
QSPI can initiate serial transfers, but cannot respond to externally initiated transfers.
When the slave select input of a device configured for master mode is asserted, a
mode fault occurs.
Before QSPI operation begins, PQSPAR must be written to assign the necessary pins
to the QSPI. The pins necessary for master mode operation are MISO, MOSI, SCK,
and one or more of the chip-select pins. MISO is used for serial data input in master
mode, and MOSI is used for serial data output. Either or both may be necessary,
depending on the particular application. SCK is the serial clock output in master mode
and must be assigned to the QSPI for proper operation.
The PORTQS data register must next be written with values that make the QGPIO6/
SCK (bit 13 QDSCK of PORTQS) and QGPIO[3:0]/PCS[3:0] (bits 12:9 QDPCS[3:0] of
PORTQS) outputs inactive when the QSPI completes a series of transfers. Pins allocated to the QSPI by PQSPAR are controlled by PORTQS when the QSPI is inactive.
PORTQS I/O pins driven to states opposite those of the inactive QSPI signals can generate glitches that momentarily enable or partially clock a slave device.
For example, if a slave device operates with an inactive SCK state of logic one (CPOL
= 1) and uses active low peripheral chip-select PCS0, the QDSCK and QDPCS0 bits
in PORTQS must be set to 0b11. If QDSCK and QDPCS0 = 0b00, falling edges will
appear on QGPIO6/SCK and GPIO0/PCS0 as the QSPI relinquishes control of these
pins and PORTQS drives them to logic zero from the inactive SCK and PCS0 states
of logic one.
Before master mode operation is initiated, QSMCM register DDRQS is written last to
direct the data flow on the QSPI pins used. Configure the SCK, MOSI and appropriate
chip-select pins PCS[3:0] as outputs. The MISO pin must be configured as an input.
After pins are assigned and configured, write appropriate data to the command queue.
If data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers
as appropriate.
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QSPI operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set,
the QSPI executes the command at the command RAM address pointed to by
NEWQP. Data at the pointer address in transmit RAM is loaded into the data serializer
and transmitted. Data that is simultaneously received is stored at the pointer address
in receive RAM.
When the proper number of bits have been transferred, the QSPI stores the working
queue pointer value in CPTQP, increments the working queue pointer, and loads the
next data for transfer from transmit RAM. The command pointed to by the incremented
working queue pointer is executed next, unless a new value has been written to
NEWQP. If a new queue pointer value is written while a transfer is in progress, that
transfer is completed normally.
When the CONT bit in a command RAM byte is set, PCS pins are continuously driven
to specified states during and between transfers. If the chip-select pattern changes
during or between transfers, the original pattern is driven until execution of the following transfer begins. When CONT is cleared, the data in register PORTQS is driven
between transfers. The data in PORTQS must match the inactive states of SCK and
any peripheral chip-selects used.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wraparound mode is enabled.
14.7.5.1 Clock Phase and Polarity
In master mode, data transfer is synchronized with the internally-generated serial
clock SCK. Control bits, CPHA and CPOL, in SPCR0, control clock phase and polarity.
Combinations of CPHA and CPOL determine upon which SCK edge to drive outgoing
data from the MOSI pin and to latch incoming data from the MISO pin.
14.7.5.2 Baud Rate Selection
Baud rate is selected by writing a value from two to 255 into the SPBR field in SPCR0.
The QSPI uses a modulus counter to derive the SCK baud rate from the MCU system
clock.
The following expressions apply to the SCK baud rate:
f SYS
SCK Baud Rate = ------------------------2 × SPBR
or
f SYS
SPBR = -------------------------------------------------------------------------2 × SCK Baud Rate Desired
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Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled
and assumes its inactive state. At reset, the SCK baud rate is initialized to one eighth
of the system clock frequency.
Table 14-21 provides some example SCK baud rates with a 40-MHz system clock.
Table 14-21 Example SCK Frequencies
with a 40-MHz System Clock
SPBR Value
SCK
Frequency
4
2
10.00 MHz
6
3
6.67 MHz
8
4
5.00 MHz
14
7
2.86 MHz
28
14
1.43 MHz
58
29
689 kHz
280
140
143 kHz
510
255
78.43 kHz
Division Ratio
14.7.5.3 Delay Before Transfer
The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or
user-specified (DSCK = 1) delay from chip-select assertion until the leading edge of
the serial clock. The DSCKL field in SPCR1 determines the length of the user-defined
delay before the assertion of SCK. The following expression determines the actual
delay before SCK:
DSCKL
PCS to SCK Delay = -------------------f SYS
where DSCKL is in the range from 1 to 127.
NOTE
A zero value for DSCKL causes a delay of 128 system clocks, which
equals 3.2 µs for a 40-MHz system clock. Because of design limits,
a DSCKL value of one defaults to the same timing as a value of two.
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transition is one-half the SCK period.
14.7.5.4 Delay After Transfer
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. Writing a value to the DTL field in SPCR1 specifies a delay period.
The DT bit in each command RAM byte determines whether the standard delay period
(DT = 0) or the specified delay period (DT = 1) is used. The following expression is
used to calculate the delay:
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32 × DTL
Delay after Transfer = -----------------------f SYS
where DTL is in the range from one to 255.
A zero value for DTL causes a delay-after-transfer value of 8192 ÷ system clock frequency (204.8 µs with a 40-MHz system clock).
If DT is zero in a command RAM byte, a standard delay is inserted.
17
Standard Delay after Transfer = ------------f SYS
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to complete conversion.
Adequate delay between transfers must be specified for long data streams because
the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices
need at least the standard delay between successive transfers. If the system clock is
operating at a slower rate, the delay between transfers must be increased
proportionately.
14.7.5.5 Transfer Length
There are two transfer length options. The user can choose a default value of eight
bits, or a programmed value from eight (0b1000) to 16 (0b0000) bits, inclusive.
Reserved values (from 0b0001 to 0b0111) default to eight bits. The programmed value
must be written into the BITS field in SPCR0. The BITSE bit in each command RAM
byte determines whether the default value (BITSE = 0) or the BITS value (BITSE = 1)
is used.
14.7.5.6 Peripheral Chip Selects
Peripheral chip-select signals are used to select an external device for serial data
transfer. Chip-select signals are asserted when a command in the queue is executed.
Signals are asserted at a logic level corresponding to the value of the PCS[3:0] bits in
each command byte. More than one chip-select signal can be asserted at a time, and
more than one external device can be connected to each PCS pin, provided proper
fanout is observed. PCS0 shares a pin with the slave select SS signal, which initiates
slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a
mode fault occurs.
To configure a peripheral chip select, set the appropriate bit in PQSPAR, then configure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value
of the bit in PORTQS that corresponds to the chip-select pin determines the base state
of the chip-select signal. If the base state is zero, chip-select assertion must be active
high (PCS bit in command RAM must be set); if base state is one, assertion must be
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ing reset. If no new data is written to PORTQS before pin assignment and
configuration as an output, the base state of chip-select signals is zero and chip-select
pins are configured for active-high operation.
14.7.5.7 Master Wraparound Mode
Wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap
to pointer address 0x0 or to the address pointed to by NEWQP, depending on the state
of the WRTO bit in SPCR2.
In wraparound mode, the QSPI cycles through the queue continuously, even while the
QSPI is requesting interrupt service. SPE is not cleared when the last command in the
queue is executed. New receive data overwrites previously received data in receive
RAM. Each time the end of the queue is reached, the SPIF flag is set. SPIF is not automatically reset. If interrupt-driven QSPI service is used, the service routine must clear
the SPIF bit to end the current interrupt request. Additional interrupt requests during
servicing can be prevented by clearing SPIFIE, but SPIFIE is buffered. Clearing it does
not end the current request.
Wraparound mode is exited by clearing the WREN bit or by setting the HALT bit in
SPCR3. Exiting wraparound mode by clearing SPE is not recommended, as clearing
SPE may abort a serial transfer in progress. The QSPI sets SPIF, clears SPE, and
stops the first time it reaches the end of the queue after WREN is cleared. After HALT
is set, the QSPI finishes the current transfer, then stops executing commands. After
the QSPI stops, SPE can be cleared.
14.7.6 Slave Mode
Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the
QSPI is unable to initiate serial transfers. Transfers are initiated by an external SPI bus
master. Slave mode is typically used on a multi-master SPI bus. Only one device can
be bus master (operate in master mode) at any given time.
Before QSPI operation is initiated, QSMCM register PQSPAR must be written to
assign necessary pins to the QSPI. The pins necessary for slave mode operation are
MISO, MOSI, SCK, and PCS0/SS. MISO is used for serial data output in slave mode,
and MOSI is used for serial data input. Either or both may be necessary, depending
on the particular application. SCK is the serial clock input in slave mode and must be
assigned to the QSPI for proper operation. Assertion of the active-low slave select signal SS initiates slave mode operation.
Before slave mode operation is initiated, DDRQS must be written to direct data flow
on the QSPI pins used. Configure the MOSI, SCK and PCS0/SS pins as inputs. The
MISO pin must be configured as an output.
After pins are assigned and configured, write data to be transmitted into transmit RAM.
Command RAM is not used in slave mode, and does not need to be initialized. Set the
queue pointers, as appropriate.
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When SPE is set and MSTR is clear, a low state on the slave select PCS0/SS pin
begins slave mode operation at the address indicated by NEWQP. Data that is
received is stored at the pointer address in receive RAM. Data is simultaneously
loaded into the data serializer from the pointer address in transmit RAM and transmitted. Transfer is synchronized with the externally generated SCK. The CPHA and
CPOL bits determine upon which SCK edge to latch incoming data from the MISO pin
and to drive outgoing data from the MOSI pin.
Because the command RAM is not used in slave mode, the CONT, BITSE, DT, DSCK,
and peripheral chip-select bits have no effect. The PCS0/SS pin is used only as an
input.
The SPBR, DT and DSCKL fields in SPCR0 and SPCR1 bits are not used in slave
mode. The QSPI drives neither the clock nor the chip-select pins and thus cannot control clock rate or transfer delay.
Because the BITSE option is not available in slave mode, the BITS field in SPCR0
specifies the number of bits to be transferred for all transfers in the queue. When the
number of bits designated by BITS[3:0] has been transferred, the QSPI stores the
working queue pointer value in CPTQP, increments the working queue pointer, and
loads new transmit data from transmit RAM into the data serializer. The working queue
pointer address is used the next time PCS0/SS is asserted, unless the RCPU writes
to NEWQP first.
The QSPI shifts one bit for each pulse of SCK until the slave select input goes high. If
SS goes high before the number of bits specified by the BITS field is transferred, the
QSPI resumes operation at the same pointer address the next time SS is asserted.
The maximum value that the BITS field can have is 16. If more than 16 bits are transmitted before SS is negated, pointers are incremented and operation continues.
The QSPI transmits as many bits as it receives at each queue address, until the BITS
value is reached or SS is negated. SS does not need to go high between transfers as
the QSPI transfers data until reaching the end of the queue, whether SS remains low
or is toggled between transfers.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wraparound mode is enabled.
Slave wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can
wrap to pointer address 0x0 or to the address pointed to by NEWQP, depending on
the state of the WRTO bit in SPCR2. Slave wraparound operation is identical to master
wraparound operation.
14.7.6.1 Description of Slave Operation
After reset, the QSMCM registers and the QSPI control registers must be initialized as
described above. Although the command control segment is not used, the transmit
and receive data segments may, depending upon the application, need to be initial-
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ized. If meaningful data is to be sent out from the QSPI, the user should write the data
to the transmit data segment before enabling the QSPI.
If SPE is set and MSTR is not set, a low state on the slave select (PCS0/SS) pin commences slave mode operation at the address indicated by NEWQP. The QSPI
transmits the data found in the transmit data segment at the address indicated by
NEWQP, and the QSPI stores received data in the receive data segment at the address indicated by NEWQP. Data is transferred in response to an external slave clock
input at the SCK pin.
Because the command control segment is not used, the command control bits and
peripheral chip-select codes have no effect in slave mode operation. The QSPI does
not drive any of the four peripheral chip-selects as outputs. PCS0/SS is used as an
input.
Although CONT cannot be used in slave mode, a provision is made to enable receipt
of more than 16 data bits. While keeping the QSPI selected (PCS0/SS is held low), the
QSPI stores the number of bits, designated by BITS, in the current receive data segment address, increments NEWQP, and continues storing the remaining bits (up to the
BITS value) in the next receive data segment address.
As long as PCS0/SS remains low, the QSPI continues to store the incoming bit stream
in sequential receive data segment addresses, until either the value in BITS is reached
or the end-of-queue address is used with wraparound mode disabled.
When the end of the queue is reached, the SPIF flag is asserted, optionally causing
an interrupt. If wraparound mode is disabled, any additional incoming bits are ignored.
If wraparound mode is enabled, storing continues at either address 0x0 or the address
of NEWQP, depending on the WRTO value. When using this capability to receive a
long incoming data stream, the proper delay between transfers must be used. The
QSPI requires time, approximately 0.425 µs with a 40-MHz system clock, to prefetch
the next transmit RAM entry for the next transfer. Therefore, the user may select a
baud rate that provides at least a 0.6-µs delay between successive transfers to ensure
no loss of incoming data. If the system clock is operating at a slower rate, the delay
between transfers must be increased proportionately.
Because the BITSE option in the command control segment is no longer available,
BITS sets the number of bits to be transferred for all transfers in the queue until the
CPU changes the BITS value. As mentioned above, until PCS0/SS is negated
(brought high), the QSPI continues to shift one bit for each pulse of SCK. If PCS0/SS
is negated before the proper number of bits (according to BITS) is received, the next
time the QSPI is selected it resumes storing bits in the same receive-data segment
address where it left off. If more than 16 bits are transferred before negating the PCS0/
SS, the QSPI stores the number of bits indicated by BITS in the current receive data
segment address, then increments the address and continues storing as described
above. Note that PCS0/SS does not necessarily have to be negated between
transfers.
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Once the proper number of bits (designated by BITS) are transferred, the QSPI stores
the received data in the receive data segment, stores the internal working queue
pointer value in CPTQP, increments the internal working queue pointer, and loads the
new transmit data from the transmit data segment into the data serializer. The internal
working queue pointer address is used the next time PCS0/SS is asserted, unless the
CPU writes to the NEWQP first.
The DT and DSCK command control bits are not used in slave mode. As a slave, the
QSPI does not drive the clock line nor the chip-select lines and, therefore, does not
generate a delay.
In slave mode, the QSPI shifts out the data in the transmit data segment. The transmit data is loaded into the data serializer (refer to Figure 14-1) for transmission. When
the PCS0/SS pin is pulled low the MISO pin becomes active and the serializer then
shifts the 16 bits of data out in sequence, most significant bit first, as clocked by the
incoming SCK signal. The QSPI uses CPHA and CPOL to determine which incoming
SCK edge the MOSI pin uses to latch incoming data, and which edge the MISO pin
uses to drive the data out.
The QSPI transmits and receives data until reaching the end of the queue (defined as
a match with the address in ENDQP), regardless of whether PCS0/SS remains
selected or is toggled between serial transfers. Receiving the proper number of bits
causes the received data to be stored. The QSPI always transmits as many bits as it
receives at each queue address, until the BITS value is reached or PCS0/SS is
negated.
14.7.7 Slave Wraparound Mode
When the QSPI reaches the end of the queue, it always sets the SPIF flag, whether
wraparound mode is enabled or disabled. An optional interrupt to the CPU is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless
wraparound mode is enabled. A description of SPIFIE bit can be found in 4.3.3 QSPI
Control Register 2 (SPCR2).
In wraparound mode, the QSPI cycles through the queue continuously. Each time the
end of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF, it
remains set, and the QSPI continues to send interrupt requests to the CPU (assuming
SPIFIE is set). The user may avoid causing CPU interrupts by clearing SPIFIE.
As SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately
stop the CPU interrupts, but only prevents future interrupts from this source. To clear
the current interrupt, the CPU must read QSPI register SPSR with SPIF asserted, followed by a write to SPSR with zero in SPIF (clear SPIF). Execution continues in
wraparound mode even while the QSPI is requesting interrupt service from the CPU.
The internal working queue pointer is incremented to the next address and the commands are executed again. SPE is not cleared by the QSPI. New receive data
overwrites previously received data located in the receive data segment.
Wraparound mode is properly exited in two ways: a) The CPU may disable wraparound mode by clearing WREN. The next time end of the queue is reached, the QSPI
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sets SPIF, clears SPE, and stops; and, b) The CPU sets HALT. This second method
halts the QSPI after the current transfer is completed, allowing the CPU to negate
SPE. The CPU can immediately stop the QSPI by clearing SPE; however, this method
is not recommended, as it causes the QSPI to abort a serial transfer in process.
14.7.8 Mode Fault
MODF is asserted by the QSPI when the QSPI is the serial master (MSTR = 1) and
the slave select (PCS0/SS) input pin is pulled low by an external driver. This is possible only if the PCS0/SS pin is configured as input by QDDR. This low input to SS is not
a normal operating condition. It indicates that a multimaster system conflict may exist,
that another MCU is requesting to become the SPI network master, or simply that the
hardware is incorrectly affecting PCS0/SS. SPE in SPCR1 is cleared, disabling the
QSPI. The QSPI pins revert to control by QPDR. If MODF is set and HMIE in SPCR3
is asserted, the QSPI generates an interrupt to the CPU.
The CPU may clear MODF by reading SPSR with MODF asserted, followed by writing
SPSR with a zero in MODF. After correcting the mode fault problem, the QSPI can be
re-enabled by asserting SPE.
The PCS0/SS pin may be configured as a general-purpose output instead of input to
the QSPI. This inhibits the mode fault checking function. In this case, MODF is not
used by the QSPI.
14.8 Serial Communication Interface
The dual, independent, serial communication interface (DSCI) communicates with
external devices through an asynchronous serial bus. The two SCI modules are functionally equivalent, except that the SCI1 also provides 16-deep queue capabilities for
the transmit and receive operations. The SCIs are fully compatible with other Motorola
SCI systems. The DSCI has all of the capabilities of previous SCI systems as well as
several significant new features.
Figure 14-12 is a block diagram of the SCI transmitter. Figure 14-13 is a block diagram of the SCI receiver.
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(WRITE-ONLY)
SCxDR Tx BUFFER
PIN BUFFER
AND CONTROL
0
15
PF
OPEN DRAIN OUTPUT MODE ENABLE
SCxSR STATUS REGISTER
FE
IDLE
RAF
RDRF
TC
TDRE
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
WAKE
M
SCCxR1 CONTROL REGISTER 1
TxD
0
TIE
TCIE
15
PE
PT
ILT
WOMS
LOOPS
TRANSMITTER
CONTROL LOGIC
NF
FORCE PIN DIRECTION (OUT)
PREAMBLE—JAM 1's
JAM ENABLE
SHIFT ENABLE
BREAK—JAM 0's
PARITY
GENERATOR
TRANSFER Tx BUFFER
SIZE 8/9
H (8) 7 6 5 4 3 2 1 0 L
OR
10 (11)-BIT Tx SHIFT REGISTER
START
STOP
TRANSMITTER
BAUD RATE
CLOCK
TDRE
TC
INTERNAL
DATA BUS
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
Figure 14-12 SCI Transmitter Block Diagram
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÷16
RxD
DATA
RECOVERY
PIN BUFFER
10 (11)-BIT
Rx SHIFT REGISTER
START
STOP
RECEIVER
BAUD RATE
CLOCK
H (8) 7 6 5 4 3 2 1 0 L
MSB
ALL ONES
PARITY
DETECT
15
SCCxR1 CONTROL REGISTER 1
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
WAKE
M
PE
PT
ILT
WOMS
0
LOOPS
WAKE-UP
LOGIC
0
SCxDR Rx BUFFER
15
SCI Tx
REQUESTS
SCxSR STATUS REGISTER
PF
OR
NF
FE
IDLE
RDRF
RAF
TC
TDRE
(READ-ONLY)
0
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 14-13 SCI Receiver Block Diagram
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14.8.1 SCI Registers
The SCI programming model includes the QSMCM global and pin control registers
and the DSCI registers.
The DSCI registers, listed in Table 14-22, consist of five control registers, three status
registers, and 34 data registers. All registers may be read or written at any time by the
CPU. Rewriting the same value to any DSCI register does not disrupt operation; however, writing a different value into a DSCI register when the DSCI is running may
disrupt operation. To change register values, the receiver and transmitter should be
disabled with the transmitter allowed to finish first. The status flags in register SCxSR
can be cleared at any time.
Table 14-22 SCI Registers
Address
Name
Usage
SCI1 Control Register 0
0x30 5008
SCC1R0
See Table 14-23 for bit descriptions.
SCI1 Control Register 1
0x30 500A
SCC1R1
See Table 14-24 for bit descriptions.
SCI1 Status Register
0x30 500C
SC1SR
See Table 14-25 for bit descriptions.
SCI1 Data Register
0x30 500E
Transmit Data Register (TDR1)*
SC1DR
(non-queue mode only)
Receive Data Register (RDR1)*
See Table 14-26 for bit descriptions.
0x30 5020
SCC2R0
SCI2 Control Register 0
0x30 5022
SCC2R1
SCI2 Control Register 1
0x30 5024
SC2SR
SCI2 Status Register
SCI2 Data Register
0x30 5026
SC2DR
Transmit Data Register (TDR2)*
Receive Data Register (RDR2)*
QSCI1 Control Register
Interrupts, wrap, queue size and enables
0x30 5028
QSCI1CR
for receive and transmit, QTPNT.
See Table 14-33 for bit descriptions.
QSCI1 Status Register
OverRun error flag, queue status flags,
0x30 502A
QSCI1SR
QRPNT, and QPEND.
See Table 14-34 for bit descriptions.
QSCI1 Transmit Queue QSCI1 Transmit Queue Data locations (on
0x30 502C — 0x30 504A
Memory Area
half-word boundary)
QSCI1 Receive Queue QSCI1 Receive Queue Data locations (on
0x30 504C-6A
Memory Area
half-word boundary)
*Reads access the RDRx; writes access the TDRx.
During SCIx initialization, two bits in the SCCxR1 should be written last: the transmitter
enable (TE) and receiver enable (RE) bits, which enable SCIx. Registers SCCxR0 and
SCCxR1 should both be initialized at the same time or before TE and RE are asserted.
A single half-word write to SCCxR1 can be used to initialize SCIx and enable the transmitter and receiver.
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14.8.2 SCI Control Register 0
SCCxR0 contains the SCIx baud rate selection field and two bits controlling the clock
source. The baud rate must be set before the SCI is enabled. The CPU can read and
write SCCxR0 at any time.
Changing the value of SCCxR0 bits during a transfer operation can disrupt the transfer. Before changing register values, allow the SCI to complete the current transfer,
then disable the receiver and transmitter.
SCCxR0 — SCI Control Register 0
MSB
0
1
2
OTHR LNKBD
3
4
5
0x30 5008
6
7
8
0
9
10
11
12
13
14
LSB
15
0
0
0
1
0
0
SCxBR
RESET:
0
0
0
0
0
0
0
0
0
0
Table 14-23 SCCxR0 Bit Settings
Bit(s)
Name
Description
OTHR
Select baud rate source clock other than system clock. OTHR determines which clock source is
used by the baud rate generator—the internal system clock or another source determined by the
LNKBD bit. Refer to 14.8.7.3 Baud Clock for more information.
0 = Internal system clock source selected
1 = Other clock source selected, determined by LNKBD bit
1
LNKBD
Link baud. The SCI1 can use the resultant baud rate clock from SCI2 as the input clock source
for the SCI baud rate generator or use the clock provided externally on the ECK pin. The link
baud option is not available for SCI2. Refer to 14.8.7.3 Baud Clock for more information.
0 = External clock selected
1 = Link baud selected
2
—
0
Reserved
SCI baud rate. The SCI baud rate is programmed by writing a 13-bit value to this field. Writing a
value of zero to SCxBR disables the baud rate generator. Baud clock rate is calculated as
follows:
3:15
SCxBR
fSYS
SCI Baud Rate = ---------------------------------32 × SCxBR
where SCxBR is in the range of 1 to 8191.
Refer to 14.8.7.3 Baud Clock for more information.
14.8.3 SCI Control Register 1
SCCxR1 contains SCIx configuration parameters, including transmitter and receiver
enable bits, interrupt enable bits, and operating mode enable bits. The CPU can read
or write this register at any time. The SCI can modify the RWU bit under certain
circumstances.
Changing the value of SCCxR1 bits during a transfer operation can disrupt the transfer. Before changing register values, allow the SCI to complete the current transfer,
then disable the receiver and transmitter.
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SCCxR1 — SCI Control Register 1
MSB
0
0
1
2
LOOPS WOMS
0x30 500A, 0x30 5022
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
ILT
PT
PE
M
WAKE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
0
Table 14-24 SCCxR1 Bit Settings
Bit(s)
Name
0
—
1
LOOPS
Loop mode
0 = Normal SCI operation, no looping, feedback path disabled.
1 = SCI test operation, looping, feedback path enabled.
2
WOMS
Wired-OR mode for SCI Pins
0 = If configured as an output, TXD is a normal CMOS output.
1 = If configured as an output, TXD is an open drain output.
3
ILT
Idle-line detect type. Refer to 14.8.7.7 Idle-Line Detection.
0 = Short idle-line detect (start count on first one).
1 = Long idle-line detect (start count on first one after stop bit(s)).
4
PT
Parity type. Refer to 14.8.7.4 Parity Checking.
0 = Even parity.
1 = Odd parity.
5
PE
Parity enable. Refer to 14.8.7.4 Parity Checking.
0 = SCI parity disabled.
1 = SCI parity enabled.
6
M
Mode select. Refer to 14.8.7.2 Serial Formats.
0 = 10-bit SCI frame.
1 = 11-bit SCI frame.
7
WAKE
8
TIE
Transmit interrupt enable
0 = SCI TDRE interrupts disabled.
1 = SCI TDRE interrupts enabled.
9
TCIE
Transmit complete interrupt enable
0 = SCI TC interrupts disabled.
1 = SCI TC interrupts enabled.
10
RIE
Receiver interrupt enable
0 = SCI RDRF and OR interrupts disabled.
1 = SCI RDRF and OR interrupts enabled.
11
ILIE
Idle-line interrupt enable
0 = SCI IDLE interrupts disabled.
1 = SCI IDLE interrupts enabled.
12
TE
Transmitter enable
0 = SCI transmitter disabled (TXD pin can be used as general-purpose output)
1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter).
13
RE
Receiver Enable
0 = SCI receiver disabled (RXD pin can be used as general-purpose input).
1 = SCI receiver enabled (RXD pin is dedicated to SCI receiver).
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Description
Reserved
Wakeup by address mark. Refer to 14.8.7.8 Receiver Wake-Up.
0 = SCI receiver awakened by idle-line detection.
1 = SCI receiver awakened by address mark (last bit set).
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Table 14-24 SCCxR1 Bit Settings (Continued)
Bit(s)
Name
Description
14
RWU
Receiver wakeup. Refer to 14.8.7.8 Receiver Wake-Up.
0 = Normal receiver operation (received data recognized).
1 = Wakeup mode enabled (received data ignored until receiver is awakened).
15
SBK
Send break
0 = Normal operation.
1 = Break frame(s) transmitted after completion of current frame.
14.8.4 SCI Status Register (SCxSR)
SCxSR contains flags that show SCI operating conditions. These flags are cleared
either by SCIx hardware or by a read/write sequence. The sequence consists of reading the SCxSR (either the upper byte, lower byte, or the entire half-word) with a flag bit
set, then reading (or writing, in the case of flags TDRE and TC) the SCxDR (either the
lower byte or the half-word).
The contents of the two 16-bit registers SCxSR and SCxDR appear as upper and
lower half-words, respectively, when the SCxSR is read into a 32-bit register. An upper
byte access of SCxSR is meaningful only for reads. Note that a word read can simultaneously access both registers SCxSR and SCxDR. This action clears the receive
status flag bits that were set at the time of the read, but does not clear the TDRE or
TC flags. To clear TC, the SCxSR read must be followed by a write to register SCxDR
(either the lower byte or the half-word). The TDRE flag in the status register is readonly.
If an internal SCI signal for setting a status bit comes after the CPU has read the
asserted status bits but before the CPU has read or written the SCxDR, the newly set
status bit is not cleared. Instead, SCxSR must be read again with the bit set and
SCxDR must be read or written before the status bit is cleared.
NOTE
None of the status bits are cleared by reading a status bit while it is
set and then writing zero to that same bit. Instead, the procedure outlined above must be followed. Note further that reading either byte of
SCxSR causes all 16 bits to be accessed, and any status bits already
set in either byte are armed to clear on a subsequent read or write of
SCxDR.
SCxSR — SCIx Status Register
MSB
0
1
2
3
4
5
0x30 500C, 0x30 5024
6
RESERVED
7
8
9
10
11
12
13
14
LSB
15
TDRE
TC
RDRF
RAF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
0
RESET:
0
0
0
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0
0
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Table 14-25 SCxSR Bit Settings
Bit(s)
Name
0:6
—
7
8
TDRE
TC
Description
Reserved
Transmit data register empty. TDRE is set when the byte in TDRx is transferred to the transmit
serial shifter. If this bit is zero, the transfer is yet to occur and a write to TDRx will overwrite the
previous value. New data is not transmitted if TDRx is written without first clearing TDRE.
0 = Transmit data register still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to the transmit data register.
For transmit queue operation, this bit should be ignored by software.
Transmit complete. TC is set when the transmitter finishes shifting out all data, queued preambles (mark/idle-line), or queued breaks (logic zero).
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
For transmit queue operation, TC is cleared when SCxSR is read with TC set, followed by a write
to SCTQ[0:15].
9
10
RDRF
Receive data register full. RDRF is set when the contents of the receive serial shifter are transferred to register RDRx. If one or more errors are detected in the received word, the appropriate
flag(s) (NF, FE, or PF) are set within the same clock cycle.
0 = Receive data register is empty or contains previously read data.
1 = Receive data register contains new data.
For receiver queue operation, this bit should be ignored by software.
RAF
Receiver active flag. RAF indicates whether the receiver is busy. This flag is set when the
receiver detects a possible start bit and is cleared when the chosen type of idle line is detected.
RAF can be used to reduce collisions in systems with multiple masters.
0 = SCI receiver is idle.
1 = SCI receiver is busy.
Idle line detected. IDLE is set when the receiver detects an idle-line condition (reception of a minimum of 10 or 11 consecutive ones as specified by ILT in SCCxR1). This bit is not set by the idleline condition when RWU in SCCxR1 is set. Once cleared, IDLE is not set again until after RDRF
is set (after the line is active and becomes idle again). If a break is received, RDRF is set, allowing a subsequent idle line to be detected again.
11
IDLE
Under certain conditions, the IDLE flag may be set immediately following the negation of RE in
SCCxR1. System designs should ensure this causes no detrimental effects.
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
For receiver queue operation, IDLE is cleared when SCxSR is read with IDLE set, followed by a
read of SCRQ[0:15].
Overrun error. OR is set when a new byte is ready to be transferred from the receive serial shifter
to register RDRx, and RDRx is already full (RDRF is still set). Data transfer is inhibited until OR
is cleared. Previous data in RDRx remains valid, but additional data received during an overrun
condition (including the byte that set OR) is lost.
12
OR
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Note that whereas the other receiver status flags (NF, FE, and PF) reflect the status of data
already transferred to RDRx, the OR flag reflects an operational condition that resulted in a loss
of data to RDRx.
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
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Table 14-25 SCxSR Bit Settings (Continued)
Bit(s)
Name
Description
Noise error flag. NF is set when the receiver detects noise on a valid start bit, on any of the data
bits, or on the stop bit(s). It is not set by noise on the idle line or on invalid start bits. Each bit is
sampled three times for noise. If the three samples are not at the same logic level, the majority
value is used for the received data value, and NF is set. NF is not set until the entire frame is
received and RDRF is set.
13
NF
Although no interrupt is explicitly associated with NF, an interrupt can be generated with RDRF,
and the interrupt handler can check NF.
0 = No noise detected in the received data.
1 = Noise detected in the received data.
For receiver queue operation NF is cleared when SCxSR is read with NF set, followed by a read
of SCRQ[0:15].
Framing error. FE is set when the receiver detects a zero where a stop bit (one) was expected.
A framing error results when the frame boundaries in the received bit stream are not synchronized with the receiver bit counter. FE is not set until the entire frame is received and RDRF is set.
14
FE
Although no interrupt is explicitly associated with FE, an interrupt can be generated with RDRF,
and the interrupt handler can check FE.
0 = No framing error detected in the received data.
1 = Framing error or break detected in the received data.
Parity error. PF is set when the receiver detects a parity error. PF is not set until the entire frame
is received and RDRF is set.
15
Although no interrupt is explicitly associated with PF, an interrupt can be generated with RDRF,
and the interrupt handler can check PF.
0 = No parity error detected in the received data.
1 = Parity error detected in the received data.
PF
14.8.5 SCI Data Register (SCxDR)
The SCxDR consists of two data registers located at the same address. The receive
data register (RDRx) is a read-only register that contains data received by the SCI
serial interface. Data is shifted into the receive serial shifter and is transferred to
RDRx. The transmit data register (TDRx) is a write-only register that contains data to
be transmitted. Data is first written to TDRx, then transferred to the transmit serial
shifter, where additional format bits are added before transmission.
SCxDR — SCI Data Register
MSB
0
1
2
3
4
0x30 500E
5
6
RESERVED
7
8
9
10
11
12
13
14
LSB
15
R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
RESET:
0
0
0
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0
0
0
U
U
U
U
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U
U
U
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Table 14-26 SCxSR Bit Settings
Bit(s)
Name
0:6
—
7:15
R[8:0]/
T[8:0]
Description
Reserved
R[7:0]/T[7:0] contain either the eight data bits received when SCxDR is read, or the eight data
bits to be transmitted when SCxDR is written. R8/T8 are used when the SCI is configured for
nine-bit operation (M = 1). When the SCI is configured for 8-bit operation, R8/T8 have no meaning or effect.
Accesses to the lower byte of SCxDR triggers the mechanism for clearing the status bits or for
initiating transmissions whether byte, half-word, or word accesses are used.
14.8.6 SCI Pins
The RXD1 and RXD2 pins are the receive data pins for the SCI1 and SCI2, respectively. TXD1 and TXD2 are the transmit data pins for the two SCI modules. An external
clock pin, ECK, is common to both SCIs. The pins and their functions are listed in
Table 14-27.
Table 14-27 SCI Pin Functions
Pin Names
Mnemonic
Receive Data
RXD1, RXD2
Receiver disabled
Receiver enabled
General purpose input
Serial data input to SCI
Transmit Data
TXD1, TXD2
Transmitter disabled
Transmitter enabled
General purpose output
Serial data output from SCI
ECK
Receiver disabled
Receiver enabled
Transmitter disabled
Transmitter enabled
Not used
Alternate input source to baud
Not used
Alternate input source to baud
External Clock
Mode
Function
14.8.7 SCI Operation
The SCI can operate in polled or interrupt-driven mode. Status flags in SCxSR reflect
SCI conditions regardless of the operating mode chosen. The TIE, TCIE, RIE, and ILIE
bits in SCCxR1 enable interrupts for the conditions indicated by the TDRE, TC, RDRF,
and IDLE bits in SCxSR, respectively.
14.8.7.1 Definition of Terms
• Bit-time — The time required to transmit or receive one bit of data, which is equal
to one cycle of the baud frequency.
• Start bit — One bit-time of logic zero that indicates the beginning of a data frame.
A start bit must begin with a one-to-zero transition and be preceded by at least
three receive time samples of logic one.
• Stop bit— One bit-time of logic one that indicates the end of a data frame.
• Frame — A complete unit of serial information. The SCI can use 10-bit or 11-bit
frames.
• Data frame — A start bit, a specified number of data or information bits, and at
least one stop bit.
• Idle frame — A frame that consists of consecutive ones. An idle frame has no start
bit.
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• Break frame — A frame that consists of consecutive zeros. A break frame has no
stop bits.
14.8.7.2 Serial Formats
All data frames must have a start bit and at least one stop bit. Receiving and transmitting devices must use the same data frame format. The SCI provides hardware
support for both 10-bit and 11-bit frames. The M bit in SCCxR1 specifies the number
of bits per frame.
The most common data frame format for NRZ (non-return to zero) serial interfaces is
one start bit, eight data bits (LSB first), and one stop bit (ten bits total). The most common 11-bit data frame contains one start bit, eight data bits, a parity or control bit, and
one stop bit. Ten-bit and 11-bit frames are shown in Table 14-28.
Table 14-28 Serial Frame Formats
Start
1
1
1
Start
1
1
10-bit Frames
Data
Parity/Control
7
—
7
1
8
—
11-Bit Frames
Data
Parity/Control
7
1
8
1
Stop
2
1
1
Stop
2
1
14.8.7.3 Baud Clock
The SCI baud rate is programmed by writing a 13-bit value to the SCxBR field in SCI
control register zero (SCCxR0). The baud rate is derived from the MCU system clock
by a modulus counter. Writing a value of zero to SCxBR[12:0] disables the baud rate
generator. The baud rate is calculated as follows:
f SYS
SCI Baud Rate = -------------------------------32 × SCxBR
or
f SYS
SCxBR = --------------------------------------------------------------------------32 × SCI Baud Rate Desired
where SCxBR is in the range {1, 2, 3, ..., 8191}.
Note that if the OTHR bit in SCCxR0 is set, the system clock frequency in the previous
equations is replaced with the frequency of the selected baud clock source—either an
external clock source, or the link baud clock source, depending on the value of the
LNKBD bit in SCCxR0.
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LNKBD enables SCI1 to use the resultant baud rate clock from SCI2 as the input clock
source for the SCI1 baud rate generator.
NOTE
This option is not available for SCI2. If LNKBD is set for SCI2 the
input clock source for SCI2 will be disabled.
If selected, the external clock frequency must be less than four times the system clock
frequency so that correct synchronization for this signal can be provided. The same
external clock is common to both independent SCIs.
Table 14-29 summarizes the possible sources for the SCI baud clock.
Table 14-29 SCI Baud Clock Sources
OTHR
LNKBD
Clock Source
0
X
Internal system clock
1
0
External clock source
1
1
Link baud clock source
The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an incoming data stream. The SCI baud rate generator produces a receive
time sampling clock with a frequency 16 times that of the SCI baud rate. The SCI determines the position of bit boundaries from transitions within the received waveform, and
adjusts sampling points to the proper positions within the bit period.
Table 14-30 shows possible baud rates for a 40-MHz system clock. The maximum
baud rate with this system clock speed is 1250 Kbaud.
Table 14-30 Examples of SCIx Baud Rates1
Nominal
Baud Rate
Actual
Baud Rate
Percent
Error
Value of
SCxBR
1,250,000.00
57,600.00
38,400.00
32,768.00
28,800.00
19,200.00
14,400.00
9,600.00
4,800.00
2,400.00
1,200.00
600.00
300.00
1,250,000.00
56,818.18
37,878.79
32,894.74
29,069.77
19,230.77
14,367.81
9,615.38
4,807.69
2,399.23
1,199.62
600.09
299.98
0.00
-1.36
-1.36
0.39
0.94
0.16
-0.22
0.16
0.16
-0.03
-0.03
0.02
-0.01
1
22
33
38
43
65
87
130
260
521
1042
2083
4167
NOTES:
1. These rates are based on a 40-MHz system clock.
More accurate baud rates can be obtained by varying the system clock frequency.
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Using the external clock, standard baud rates such as 1200, 2400, and 9600 can be
achieved with reasonable error (less than 0.1%). Table 14-31 shows an example of
standard baud rates produced from a common crystal frequency, 3.6864 MHz.
SCIx Baud = External Clock/(32 * SCxBR)(5-1)
where SCxBR equals {1, 2, 3, ... 8191}. Note that zero is a disallowed value for
SCxBR.
Table 14-31 Examples of SCIx Baud Rates from an 3.6864 MHz external clock
Nominal
Baud Rate
115,200.00
57,600.00
28,800.00
14,400.00
9,600.00
2,400.00
1,200.00
64.00
Actual
Baud Rate
115,200.00
57,600.00
28,800.00
14,400.00
9,600.00
2,400.00
1,200.00
64.00
Percent
Error
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
Value of
SCxBR
1
2
4
8
12
48
96
1800
14.8.7.4 Parity Checking
The PT bit in SCCxR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects
received and transmitted data. The PE bit in SCCxR1 determines whether parity
checking is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data
in a frame (i.e., the bit preceding the stop bit) is used for the parity function. For transmitted data, a parity bit is generated. For received data, the parity bit is checked. When
parity checking is enabled, the PF bit in the SCI status register (SCxSR) is set if a parity error is detected.
Enabling parity affects the number of data bits in a frame, which can in turn affect
frame size. Table 14-32 shows possible data and parity formats.
Table 14-32 Effect of Parity Checking on Data Size
M
0
0
1
1
PE
0
1
0
1
Result
8 data bits
7 data bits, 1 parity bit
9 data bits
8 data bits, 1 parity bit
14.8.7.5 Transmitter Operation
The transmitter consists of a serial shifter and a parallel data register (TDRx) located
in the SCI data register (SCxDR). The serial shifter cannot be directly accessed by the
CPU. The transmitter is double-buffered, which means that data can be loaded into the
TDRx while other data is shifted out. The TE bit in SCCxR1 enables (TE = 1) and disables (TE = 0) the transmitter.
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The shifter output is connected to the TXD pin while the transmitter is operating (TE =
1, or TE = 0 and transmission in progress). Wired-OR operation should be specified
when more than one transmitter is used on the same SCI bus. The WOMS bit in
SCCxR1 determines whether TXD is an open drain (wired-OR) output or a normal
CMOS output. An external pull-up resistor on TXD is necessary for wired-OR operation. WOMS controls TXD function, regardless of whether the pin is used by the SCI
or as a general-purpose output pin.
Data to be transmitted is written to SCxDR, then transferred to the serial shifter. Before
writing to TDRx, the user should check the transmit data register empty (TDRE) flag
in SCxSR. When TDRE = 0, the TDRx contains data that has not been transferred to
the shifter. Writing to SCxDR again overwrites the data. If TDRE = 1, then TDRx is
empty, and new data may be written to TDRx, clearing TDRE.
As soon as the data in the transmit serial shifter has shifted out and if a new data frame
is in TDRx (TDRE = 0), then the new data is transferred from TDRx to the transmit
serial shifter and TDRE is set automatically. An interrupt may optionally be generated
at this point.
The transmission complete (TC) flag in SCxSR shows transmitter shifter state. When
TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is
not automatically cleared. The processor must clear it by first reading SCxSR while TC
is set, then writing new data to SCxDR, or writing to SCTQ[0:15] for transmit queue
operation.
The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame
is transmitted as a preamble to the following data frame. If TC = 0, the current operation continues until the final bit in the frame is sent, then the preamble is transmitted.
The TC bit is set at the end of preamble transmission.
The SBK bit in SCCxR1 is used to insert break frames in a transmission. A non-zero
integer number of break frames are transmitted while SBK is set. Break transmission
begins when SBK is set, and ends with the transmission in progress at the time either
SBK or TE is cleared. If SBK is set while a transmission is in progress, that transmission finishes normally before the break begins. To ensure the minimum break time,
toggle SBK quickly to one and back to zero. The TC bit is set at the end of break transmission. After break transmission, at least one bit-time of logic level one (mark idle) is
transmitted to ensure that a subsequent start bit can be detected.
If TE remains set, after all pending idle, data and break frames are shifted out, TDRE
and TC are set and TXD is held at logic level one (mark).
When TE is cleared, the transmitter is disabled after all pending idle, data, and break
frames are transmitted. The TC flag is set, and control of the TXD pin reverts to
PQSPAR and DDRQS. Buffered data is not transmitted after TE is cleared. To avoid
losing data in the buffer, do not clear TE until TDRE is set.
Some serial communication systems require a mark on the TXD pin even when the
transmitter is disabled. Configure the TXD pin as an output, then write a one to either
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QDTX1 or QDTX2 of the PORTQS register. See 14.6.1. When the transmitter releases
control of the TXD pin, it reverts to driving a logic one output.
To insert a delimiter between two messages, to place non-listening receivers in wakeup mode between transmissions, or to signal a re-transmission by forcing an idle-line,
clear and then set TE before data in the serial shifter has shifted out. The transmitter
finishes the transmission, then sends a preamble. After the preamble is transmitted, if
TDRE is set, the transmitter marks idle. Otherwise, normal transmission of the next
sequence begins.
Both TDRE and TC have associated interrupts. The interrupts are enabled by the
transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits
in SCCxR1. Service routines can load the last data frame in a sequence into SCxDR,
then terminate the transmission when a TDRE interrupt occurs.
Two SCI messages can be separated with minimum idle time by using a preamble of
10 bit-times (11 if a 9-bit data format is specified) of marks (logic ones). Follow these
steps:
1. Write the last data frame of the first message to the TDRx
2. Wait for TDRE to go high, indicating that the last data frame is transferred to the
transmit serial shifter
3. Clear TE and then set TE back to one. This queues the preamble to follow the
stop bit of the current transmission immediately.
4. Write the first data frame of the second message to register TDRx
In this sequence, if the first data frame of the second message is not transferred to
TDRx prior to the finish of the preamble transmission, then the transmit data line
(TXDx pin) marks idle (logic one) until TDRx is written. In addition, if the last data frame
of the first message finishes shifting out (including the stop bit) and TE is clear, TC
goes high and transmission is considered complete. The TXDx pin reverts to being a
general-purpose output pin.
14.8.7.6 Receiver Operation
The RE bit in SCCxR1 enables (RE = 1) and disables (RE = 0) the receiver. The
receiver contains a receive serial shifter and a parallel receive data register (RDRx)
located in the SCI data register (SCxDR). The serial shifter cannot be directly
accessed by the CPU. The receiver is double-buffered, allowing data to be held in the
RDRx while other data is shifted in.
Receiver bit processor logic drives a state machine that determines the logic level for
each bit-time. This state machine controls when the bit processor logic is to sample
the RXD pin and also controls when data is to be passed to the receive serial shifter.
A receive time clock is used to control sampling and synchronization. Data is shifted
into the receive serial shifter according to the most recent synchronization of the
receive time clock with the incoming data stream. From this point on, data movement
is synchronized with the MCU system clock. Operation of the receiver state machine
is detailed in the Queued Serial Module Reference Manual (QSMRM/AD).
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The number of bits shifted in by the receiver depends on the serial format. However,
all frames must end with at least one stop bit. When the stop bit is received, the frame
is considered to be complete, and the received data in the serial shifter is transferred
to the RDRx. The receiver data register flag (RDRF) is set when the data is
transferred.
The stop bit is always a logic one. If a logic zero is sensed during this bit-time, the FE
flag in SCxSR is set. A framing error is usually caused by mismatched baud rates
between the receiver and transmitter or by a significant burst of noise. Note that a
framing error is not always detected; the data in the expected stop bit-time may happen to be a logic one.
Noise errors, parity errors, and framing errors can be detected while a data stream is
being received. Although error conditions are detected as bits are received, the noise
flag (NF), the parity flag (PF), and the framing error (FE) flag in SCxSR are not set until
data is transferred from the serial shifter to the RDRx.
RDRF must be cleared before the next transfer from the shifter can take place. If
RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR)
flag in SCxSR is set. OR indicates that the RDRx needs to be serviced faster. When
OR is set, the data in the RDRx is preserved, but the data in the serial shifter is lost.
When a completed frame is received into the RDRx, either the RDRF or OR flag is
always set. If RIE in SCCxR1 is set, an interrupt results whenever RDRF is set. The
receiver status flags NF, FE, and PF are set simultaneously with RDRF, as appropriate. These receiver flags are never set with OR because the flags apply only to the
data in the receive serial shifter. The receiver status flags do not have separate interrupt enables, since they are set simultaneously with RDRF and must be read by the
user at the same time as RDRF.
When the CPU reads SCxSR and SCxDR in sequence, it acquires status and data,
and also clears the status flags. Reading SCxSR acquires status and arms the clearing mechanism. Reading SCxDR acquires data and clears SCxSR.
14.8.7.7 Idle-Line Detection
During a typical serial transmission, frames are transmitted isochronically and no idle
time occurs between frames. Even when all the data bits in a frame are logic ones, the
start bit provides one logic zero bit-time during the frame. An idle line is a sequence of
contiguous ones equal to the current frame size. Frame size is determined by the state
of the M bit in SCCxR1.
The SCI receiver has both short and long idle-line detection capability. Idle-line detection is always enabled. The idle-line type (ILT) bit in SCCxR1 determines which type
of detection is used. When an idle-line condition is detected, the IDLE flag in SCxSR
is set.
For short idle-line detection, the receiver bit processor counts contiguous logic one bittimes whenever they occur. Short detection provides the earliest possible recognition
of an idle-line condition, because the stop bit and contiguous logic ones before and
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after it are counted. For long idle-line detection, the receiver counts logic ones after the
stop bit is received. Only a complete idle frame causes the IDLE flag to be set.
In some applications, software overhead can cause a bit-time of logic level one to
occur between frames. This bit-time does not affect content, but if it occurs after a
frame of ones when short detection is enabled, the receiver flags an idle line.
When the ILIE bit in SCCxR1 is set, an interrupt request is generated when the IDLE
flag is set. The flag is cleared by reading SCxSR and SCxDR in sequence. For
receiver queue operation, IDLE is cleared when SCxSR is read with IDLE set, followed
by a read of SCRQ[0:15]. IDLE is not set again until after at least one frame has been
received (RDRF = 1). This prevents an extended idle interval from causing more than
one interrupt.
14.8.7.8 Receiver Wake-Up
The receiver wake-up function allows a transmitting device to direct a transmission to
a single receiver or to a group of receivers by sending an address frame at the start of
a message. Hardware activates each receiver in a system under certain conditions.
Resident software must process address information and enable or disable receiver
operation.
A receiver is placed in wake-up mode by setting the RWU bit in SCCxR1. While RWU
is set, receiver status flags and interrupts are disabled. Although the software can
clear RWU, it is normally cleared by hardware during wake-up.
The WAKE bit in SCCxR1 determines which type of wake-up is used. When WAKE =
0, idle-line wake-up is selected. When WAKE = 1, address-mark wake-up is selected.
Both types require a software-based device addressing and recognition scheme.
Idle-line wake-up allows a receiver to sleep until an idle line is detected. When an idle
line is detected, the receiver clears RWU and wakes up. The receiver waits for the first
frame of the next transmission. The data frame is received normally, transferred to the
RDRx, and the RDRF flag is set. If software does not recognize the address, it can set
RWU and put the receiver back to sleep. For idle-line wake-up to work, there must be
a minimum of one frame of idle line between transmissions. There must be no idle time
between frames within a transmission.
Address mark wake-up uses a special frame format to wake up the receiver. When the
MSB of an address-mark frame is set, that frame contains address information. The
first frame of each transmission must be an address frame. When the MSB of a frame
is set, the receiver clears RWU and wakes up. The data frame is received normally,
transferred to the RDRx, and the RDRF flag is set. If software does not recognize the
address, it can set RWU and put the receiver back to sleep. Address mark wake-up
allows idle time between frames and eliminates idle time between transmissions. However, there is a loss of efficiency because of an additional bit-time per frame.
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14.8.7.9 Internal Loop Mode
The LOOPS bit in SCCxR1 controls a feedback path in the data serial shifter. When
LOOPS is set, the SCI transmitter output is fed back into the receive serial shifter. TXD
is asserted (idle line). Both transmitter and receiver must be enabled before entering
loop mode.
14.9 SCI Queue Operation
14.9.1 Queue Operation of SCI1 for Transmit and Receive
The SCI1 serial module allows for queueing on transmit and receive data frames. In
the standard mode, in which the queue is disabled, the SCI1 operates as previously
defined (i.e. transmit and receive operations done via SC1DR). However, if the SCI1
queue feature is enabled (by setting the QTE and/or QRE bits within QSCI1CR) a set
of 16 entry queues is allocated for the receive and/or transmit operation. Through software control the queue is capable of continuous receive and transfer operations within
the SCI1 serial unit.
14.9.2 Queued SCI1 Status and Control Registers
The SCI1 queue uses the following registers:
• QSCI1 control register (QSCI1CR, address offset 0x28)
• QSCI1 status register (QSCI1SR, address offset 0x2A)
14.9.2.1 QSCI1 Control Register
QSCI1CR — QSCI1 Control Register
0x30 5028
MSB
0
LSB
1
2
3
QTPNT
4
5
6
7
8
9
10
11
QTHFI
QBHFI
QTHEI
QBHEI
0
QTE
QRE
QTWE
0
0
0
0
0
0
0
0
12
13
14
15
QTSZ
RESET:
0
0
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Table 14-33 QSCI1CR Bit Settings
Bit(s)
Name
Description
0:3
QTPNT
Queue transmit pointer. QTPNT is a 4-bit counter used to indicate the next data frame within the
transmit queue to be loaded into the SC1DR. This feature allows for ease of testability. This field
is writable in test mode only; otherwise it is read-only.
QTHFI
Receiver queue top-half full interrupt. When set, QTHFI enables an SCI1 interrupt whenever the
QTHF flag in QSCI1SR is set. The interrupt is blocked by negating QTHFI. This bit refers to the
queue locations SCRQ[0:7].
0 = QTHF interrupt inhibited
1 = Queue top-half full (QTHF) interrupt enabled
QBHFI
Receiver queue bottom-half full interrupt. When set, QBHFI enables an SCI1 interrupt whenever
the QBHF flag in QSCI1SR is set. The interrupt is blocked by negating QBHFI. This bit refers to
the queue locations SCRQ[8:15].
0 = QBHF interrupt inhibited
1 = Queue bottom-half full (QBHF) interrupt enabled
QTHEI
Transmitter queue top-half empty interrupt. When set, QTHEI enables an SCI1 interrupt whenever the QTHE flag in QSCI1SR is set. The interrupt is blocked by negating QTHEI. This bit refers
to the queue locations SCTQ[0:7].
0 = QTHE interrupt inhibited
1 = Queue top-half empty (QTHE) interrupt enabled
7
QBHEI
Transmitter queue bottom-half empty interrupt. When set, QBHEI enables an SCI1 interrupt
whenever the QBHE flag in QSCI1SR is set. The interrupt is blocked by negating QBHEI. This
bit refers to the queue locations SCTQ[8:15].
0 = QBHE interrupt inhibited
1 = Queue bottom-half empty (QBHE) interrupt enabled
8
—
4
5
6
Reserved
QTE
Queue transmit enable. When set, the transmit queue is enabled and the TDRE bit should be
ignored by software. The TC bit is redefined to indicate when the entire queue is finished transmitting. When clear, the SCI1 functions as described in the previous sections and the bits related
to the queue (Section 5.5 and its subsections) should be ignored by software with the exception
of QTE.
0 = Transmit queue is disabled
1 = Transmit queue is enabled
QRE
Queue receive enable. When set, the receive queue is enabled and the RDRF bit should be
ignored by software. When clear, the SCI1 functions as described in the previous sections and
the bits related to the queue (Section 5.5 and its subsections) should be ignored by software with
the exception of QRE.
0 = Receive queue is disabled
1 = Receive queue is enabled
11
QTWE
Queue transmit wrap enable. When set, the transmit queue is allowed to restart transmitting from
the top of the queue after reaching the bottom of the queue. After each wrap of the queue, QTWE
is cleared by hardware.
0 = Transmit queue wrap feature is disabled
1 = Transmit queue wrap feature is enabled
12:15
QTSZ
Queue transfer size. The QTSZ bits allow programming the number of data frames to be transmitted. From 1 (QTSZ = 0b0000) to 16 (QTSZ = 0b1111) data frames can be specified. QTSZ is
loaded into QPEND initially or when a wrap occurs.
9
10
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14.9.2.2 QSCI1 Status Register
QSCI1SR — QSCI1 Status Register
0x30 502A
MSB
0
LSB
1
2
RESERVED
3
QOR
4
5
6
7
8
QTHF QBHF QTHE QBHE
9
10
11
12
QRPNT
13
14
15
QPEND
RESET:
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Table 14-34 QSCI1SR Bit Settings
Bit(s)
Name
0:2
—
Description
Reserved
QOR
Receiver queue overrun error. The QOR is set when a new data frame is ready to be transferred
from the SC1DR to the queue and the queue is already full (QTHF or QBHF are still set). Data
transfer is inhibited until QOR is cleared. Previous data transferred to the queue remains valid.
Additional data received during a queue overrun condition is not lost provided the receive queue
is re-enabled before OR (SC1SR) is set. The OR flag is set when a new data frame is received
in the shifter but the data register (SC1DR) is still full. The data in the shifter that generated the
OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost.
0 = The queue is empty before valid data is in the SC1DR
1 = The queue is not empty when valid data is in the SC1DR
QTHF
Receiver queue top-half full. QTHF is set when the receive queue locations SCRQ[0:7] are completely filled with new data received via the serial shifter. QTHF is cleared when register
QSCI1SR is read with QTHF set, followed by a write of QTHF to zero.
0 = The queue locations SCRQ[0:7] are partially filled with newly received data or is empty
1 = The queue locations SCRQ[0:7] are completely full of newly received data
QBHF
Receiver queue bottom-half full. QBHF is set when the receive queue locations SCRQ[8:15] are
completely filled with new data received via the serial shifter. QBHF is cleared when register
QSCI1SR is read with QBHF set, followed by a write of QBHF to zero.
0 = The queue locations SCRQ[8:15] are partially filled with newly received data or is empty
1 = The queue locations SCRQ[8:15] are completely full of newly received data
QTHE
Transmitter queue top-half empty. QTHE is set when all the data frames in the transmit queue
locations SCTQ[0:7] have been transferred to the transmit serial shifter. QTHE is cleared when
register QSCI1SR is read with QTHE set, followed by a write of QTHE to zero.
0 = The queue locations SCTQ[0:7] still contain data to be sent to the transmit serial shifter
1 = New data may now be written to the queue locations SCTQ[0:7]
7
QBHE
Transmitter queue bottom-half empty. QBHE is set when all the data frames in the transmit
queue locations SCTQ[8:15] has been transferred to the transmit serial shifter. QBHE is cleared
when register QSCI1SR is read with QBHE set, followed by a write of QBHE to zero.
0 = The queue locations SCTQ[8:15] still contain data to be sent to the transmit serial shifter
1 = New data may now be written to the queue locations SCTQ[8:15]
8:11
QRPNT
Queue receive pointer. QRPNT is a 4-bit counter used to indicate the position where the next
valid data frame will be stored within the receive queue. This field is writable in test mode only;
otherwise it is read-only.
QPEND
Queue pending. QPEND is a 4-bit decrementer used to indicate the number of data frames in
the queue that are awaiting transfer to the SC1DR. This field is writable in test mode only; otherwise it is read-only. From 1 (QPEND = 0b0000) to 16 (or done, QPEND = 1111) data frames can
be specified.
3
4
5
6
12:15
14.9.3 QSCI1 Transmitter Block Diagram
The block diagram of the enhancements to the SCI transmitter is shown in Figure 1414.
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SCI Interrupt Request
QBHE
QTHE
QPEND[0:3]
Queue Status
QTWE
QTSZ[0:3]
QBHEI
QTHEI
QTE
Queue Control
Queue Control
Logic
4-bits
9-bit 16:1 Mux
SCI1 Non-Queue Operation
SCTQ[0]
SCTQ[1]
data bus
SC1DR Tx BUFFER
10 (11) - BIT
Tx Shift Register
START
Transmitter
Baud Rate
Clock
STOP
SCTQ[15]
TxD
H (8) 7 6 5 4 3 2 1 0 L
Figure 14-14 Queue Transmitter Block Enhancements
14.9.4 QSCI1 Additional Transmit Operation Features
• Available on a single SCI channel (SCI1) implemented by the queue transmit enable (QTE) bit set by software. When enabled, (QTE = 1) the TDRE bit should be
ignored by software and the TC bit is redefined (as described later).
• When the queue is disabled (QTE = 0), the SCI functions in single buffer transfer
mode where the queue size is set to one (QTSZ = 0000), and TDRE and TC function as previously defined. Locations SCTQ[0:15] can be used as general purpose 9-bit registers. All other bits pertaining to the queue should be ignored by
software.
• Programmable queue up to 16 transmits (SCTQ[0:15]) which may allow for infinite and continuous transmits.
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• Available transmit wrap function to prevent message breaks for transmits greater
than 16. This is achieved by the transmit wrap enable (QTWE) bit. When QTWE
is set, the hardware is allowed to restart transmitting from the top of the queue
(SCTQ[0]). After each wrap, QTWE is cleared by hardware.
— Transmissions of more than 16 data frames must be performed in multiples of
16 (QTSZ = 0b1111) except for the last set of transmissions. For any single
non-continuous transmissions of 16 or less or the last transmit set composed
of 16 or fewer data frames, the user is allowed to program QTSZ to the corresponding value of 16 or less where QTWE = 0.
• Interrupt generation when the top half (SCTQ[0:7]) of the queue has been emptied (QTHE) and the bottom half (SCTQ[8:15]) of the queue has been emptied
(QBHE). This may allow for uninterrupted and continuous transmits by indicating
to the CPU that it can begin refilling the queue portion that is now emptied.
— The QTHE bit is set by hardware when the top half is empty or the transmission has completed. The QTHE bit is cleared when the QSCI1SR is read with
QTHE set, followed by a write of QTHE to zero.
— The QBHE bit is set by hardware when the bottom half is empty or the transmission has completed. The QBHE bit is cleared when the QSCI1SR is read
with QBHE set, followed by a write of QBHE to zero.
— In order to implement the transmit queue, QTE must be set (QSCI1CR), TE
must be set (SCC1R1), QTHE must be cleared (QSCI1SR), and TDRE must
be set (SC1SR).
• Enable and disable options for the interrupts QTHE and QBHE as controlled by
QTHEI and QBHEI respectfully.
• Programmable 4-bit register queue transmit size (QTSZ) for configuring the
queue to any size up to 16 transfers at a time. This value may be rewritten after
transmission has started to allow for the wrap feature.
• 4-bit status register to indicate the number of data transfers pending (QPEND).
This register counts down to all 0’s where the next count rolls over to all 1’s. This
counter is writable in test mode; otherwise it is read-only.
• 4-bit counter (QTPNT) is used as a pointer to indicate the next data frame within
the transmit queue to be loaded into the SC1DR. This counter is writable in test
mode; otherwise it is read-only.
• A transmit complete (TC) bit re-defined when the queue is enabled (QTE = 1) to
indicate when the entire queue (including when wrapped) is finished transmitting.
This is indicated when QPEND = 1111 and the shifter has completed shifting data
out. TC is cleared when the SCxSR is read with TC = 1 followed by a write to
SCTQ[0:15]. If the queue is disabled (QTE = 0), the TC bit operates as originally
designed.
• When the transmit queue is enabled (QTE = 1), writes to the transmit data register
(SC1DR) have no effect.
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14.9.5 QSCI1 Transmit Flow Chart Implementing the Queue
Refers to Action Performed
in Parallel
TE=0, TC=1, TDRE=1
QTE=0, QTPNT=0, QTWE=0
QTHEI=0, QTHE=1
QBHEI=0, QBHE=1
QTE=1, TE=1
TDRE=1, QTHE=0?
Set QTE=1
Set QTHEI, QBHEI
Write QTSZ=n
Clear QTHE, TC
Write SCTQ[0:n]
Set TE
Reset
Hardware
Software
No
Yes
Load QPEND with QTSZ,
Reset QTPNT to 0000
No
QTE, TE=1?
Yes
Load TDR (SC1DR)
With SCTQ[QTPNT]
Shift Data Out(TDRE=1)
Write QTSZ for Wrap
Clear QTHE
Possible Set of QTWE
Decrement QPEND,
Increment QTPNT
Yes
Set QTHE
QTPNT=1000?
Clear QBHE
No
Yes
QBHE=0?
Yes
Set QBHE
QTPNT = 1111?
No
no
No
QPEND = 1111
yes
Clear QTWE
Yes
QTWE = 1
& QTHE = 0?
no
Set QTHE, QBHE
Clear QTE
Figure 14-15 Queue Transmit Flow
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Reset
Configure the Transmit Flow
for First Use of the Queue.
Enable Queue Interrupt
QTHEI = 1,
If Transmitting Greater
than 16 Data Frames,
Enable Queue Interrupt
QBHEI = 1
Write QTSZ=n for First
Pass Use of the Queue
Read Status Register with TC = 1,
Write SCTQ[0:n] (Clears TC)
Read Status Register with QTHE=1
Write QTHE = 0 (and QBHE if
Transmitting More than 8 Data
Frames)
Set QTE and TE = 1
Yes
QTHE = 1?
No
To Wrap, Write New QTSZ=n
Set QTWE (Previous QTSZ
Must Have Equaled 16)
Read QTHE=1, Write QTHE=0
Write New Data SCTQ[0:7]
No
QBHE = 1?
If Finished Transmitting,
Then Clear QTE and/or TE
DONE
Yes
If Transmitting Greater
Than 8 Data Frames on Wrap
Read QBHE=1,Write QBHE=0
Write New Data to SCTQ[8:15]
If Finished Transmitting,
Then Clear QTE and/or TE
DONE
Figure 14-16 Queue Transmit Software Flow
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14.9.6 Example QSCI1 Transmit for 17 Data Bytes
Figure 14-17 below shows a transmission of 17 data frames. The bold type indicates
the current value for QTPNT and QPEND. The italic type indicates the action just performed by hardware. Regular type indicates the actions that should be performed by
software before the next event.
1
Transmit Queue Enabled
QTSZ=1111 (16 Data Frames)
QPEND
QTPNT
0000
1111
SCTQ[0]
0111
1000
1111
SCTQ[7]
SCTQ[8]
SCTQ[15]
2
QTHE Interrupt Received
QTSZ=1111 (16 Data Frames)
QPEND
QTPNT
0000
1111
SCTQ[0]
SCTQ[7]
1000
0111
0111
1000
SCTQ[8]
0111
0000
1111
SCTQ[15]
0000
1000
Write New QTSZ for When Wrap Occurs
QTSZ=0 (16+1=17),Set QTWE, Clear QTHE
Write SCTQ[0] for 17th Transfer
QBHE Interrupt Received
(Wrap Occurred)
3
QTSZ=0000 (1 Data Frame)
QTPNT
0000
SCTQ[0]
0001
QPEND
0000
1111
Data to beTransferred
0111
SCTQ[7]
1000
SCTQ[8]
1111
SCTQ[15]
Available Register Space
Load QPEND with QTSZ (0)
Clear QTWE
Reset QTPNT
Figure 14-17 Queue Transmit Example for 17 Data Bytes
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14.9.7 Example SCI Transmit for 25 Data Bytes
Figure 14-18 below is an example of a transmission of 25 data frames.
1
2
Transmit Queue Enabled
QTSZ=1111 (16 Data Frames)
QTPNT
0000
SCTQ[0]
QPEND
1111
QTHE Interrupt Received
QTSZ=1111 (16 Data Frames)
QTPNT
0000
SCTQ[0]
QPEND
1111
0111
SCTQ[7]
1000
0111
SCTQ[7]
1000
1000
SCTQ[8]
0111
1000
SCTQ[8]
0111
1111
SCTQ[15]
0000
1111
SCTQ[15]
0000
Write QTSZ = 8 (16 + 9 = 25)
Write SCTQ [0:7] for 8 More Data Frames
Set QTWE
Clear QTHE
Data to be Transferred
QBHE Interrupt Received
(Wrap Occurred)
3
QTSZ=1000 (9 Data Frames)
QTPNT
0000
SCTQ[0]
4
QPEND
1000
Available Register Space
QTHE Interrupt Received
QTSZ=1000 (9 Data Frames)
QTPNT
0000
SCTQ[0]
QPEND
1000
0111
SCTQ[7]
0001
0111
SCTQ[7]
0001
1000
SCTQ[8]
0000
1000
SCTQ[8]
0000
1001
1111
1111
SCTQ[15]
1111
SCTQ[15]
Load QPEND with QTSZ
Clear QTWE
Reset QTPNT
Write SCTQ[8]
Clear QBHE
Figure 14-18 Queue Transmit Example for 25 Data Frames
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STOP
Receiver Baud Rate
Clock
10 (11) - BIT
Rx Shift Register
H (8) 7
RxD
START
14.9.8 QSCI1 Receiver Block Diagram
The block diagram of the enhancements to the SCI receiver is shown below in Figure
14-19.
6
5
4
3
2
1
0
L
SCRQ[0]
SCxDR Rx BUFFER
16:1 Mux
SCRQ[1]
SCI1 Non-Queue Operation
Data Bus
SCRQ[15]
4-bits
Queue Control
QOR
QBHF
QTHF
QRPNT[0:3]
QRE
QBHFI
QTHFI
Queue Control
Logic
Queue Status
SCI Interrupt Request
Figure 14-19 Queue Receiver Block Enhancements
14.9.9 QSCI1 Additional Receive Operation Features
• Available on a single SCI channel (SCI1) implemented by the queue receiver enable (QRE) bit set by software. When the queue is enabled, software should ignore the RDRF bit.
• When the queue is disabled (QRE = 0), the SCI functions in single buffer receive
mode (as originally designed) and RDRF and OR function as previously defined.
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Locations SCRQ[0:15] can be used as general purpose 9-bit registers. Software
should ignore all other bits pertaining to the queue.
• Only data that has no errors (FE and PF both false) is allowed into the queue. The
status flags FE and PF, if set, reflect the status of data not allowed into the queue.
The receive queue is disabled until the error flags are cleared via the original SCI
mechanism and the queue is re-initialized. The pointer QRPNT indicates the
queue location where the data frame would have been stored.
• Queue size capable to receive up to 16 data frames (SCRQ[0:15]) which may allow for infinite and continuous receives.
• Interrupt generation can occur when the top half (SCRQ[0:7]) of the queue has
been filled (QTHF) and the bottom half (SCRQ[8:15]) of the queue has been filled
(QBHF). This may allow for uninterrupted and continuous receives by indicating
to the CPU to start reading the queue portion that is now full.
— The QTHF bit is set by hardware when the top half is full or the receive has
completed. The QTHF bit is cleared when the SCxSR is read with QTHF set,
followed by a write of QTHF to zero.
— The QBHF bit is set by hardware when the bottom half is full or the receive has
completed. The QBHF bit is cleared when the SCxSR is read with QBHF set,
followed by a write of QBHF to zero.
• In order to implement the receive queue, the following conditions must be met:
QRE must be set (QSCI1CR); RE must be set (SCC1R1); QOR and QTHF must
be cleared (QSCI1SR); and OR, PF, and FE must be cleared (SC1SR).
• Enable and disable options for the interrupts QTHF and QBHF as controlled by
the QTHFI and QBHFI, respectfully.
• 4-bit counter (QRPNT) is used as a pointer to indicate where the next valid data
frame will be stored.
• A queue overrun error flag (QOR) to indicate when the queue is already full when
another data frame is ready to be stored into the queue (similar to the OR bit in
single buffer mode). The QOR bit can be set for QTHF = 1 or QBHF = 1, depending on where the store is being attempted.
• The queue can be exited when an idle line is used to indicate when a group of
serial transmissions is finished. This can be achieved by using the ILIE bit to enable the interrupt when the IDLE flag is set. The CPU can then clear QRE and/or
RE allowing the receiver queue to be exited.
• For receiver queue operation, IDLE is cleared when SC1SR is read with IDLE set,
followed by a read of SCRQ[0:15].
• For receiver queue operation, NF is cleared when the SC1SR is read with NF set,
followed by a read of SCRQ[0:15]. When noise occurs, the data is loaded into the
receive queue, and operation continues unaffected. However, it may not be possible to determine which data frame in the receive queue caused the noise flag to
be asserted.
• The queue is successfully filled (16 data frames) if error flags (FE and PF) are
clear, QTHF and QBHF are set, and QRPNT is reset to all zeroes.
• QOR indicates that a new data frame has been received in the data register
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(SC1DR), but it cannot be placed into the receive queue due to either the QTHF
or QBHF flag being set (QSCI1SR). Under this condition, the receive queue is disabled (QRE = 0). Software may service the receive queue and clear the appropriate flag (QTHF, QBHF). Data is not lost provided that the receive queue is reenabled before OR (SC1SR) is set, which occurs when a new data frame is received in the shifter but the data register (SC1DR) is still full. The data in the
shifter that generated the OR assertion is overwritten by the next received data
frame, but the data in the SC1DR is not lost.
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14.9.10 QSCI1 Receive Flow Chart Implementing The Queue
Refers to Action Performed
In Parallel
Reset
RE=0, QRWE=0
QRPNT=0000
QRE=0, QOR=0
QTHF=1, QBHF=1
QTHFI=0, QBHFI=0
Software
QRE/RE=1
QTHF/QOR=0
FE/PE/OR=0
Set QRE
Set QTHFI, QBHFI
Clear QTHF, QBHF
Set RE
Hardware
No
Yes
Reset QRPNT to 0000
Clear QRE
No
QRE, RE=1?
Yes
No
RDRF=1?
Yes
No
FE, PE = 0?
Yes
QRPNT=8 & QBHF
QRPNT=0 & QTHF
Yes
Set QOR
No
Load RX Data to
SCRQ[QRPNT],
Clear QTHF
Increment QRPNT
Yes
Set QTHF
QRPNT = 1000?
No
Clear QBHF
Yes
Set QBHF
QRPNT = 0000?
No
Figure 14-20 Queue Receive Flow
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14.9.11 QSCI1 Receive Queue Software Flow Chart
Reset
Configure the Receive Queue
Enable Queue Interrupts
QTHFI, QBHFI = 1,
Read Status Register with
QTHF & QBHF = 1,
Write QTHF & QBHF = 0
FunctionCan Be Used To
Indicate When a Group
Of Serial Transmissions
Is Finished
Enable ILIE=1 to Detect
An Idle Line
Set QRE and RE = 1
Yes
QTHF=1?
No
Read Status Register With
QTHF = 1
Read SCRQ[0:7]
Write QTHF = 0
Yes
QBHF = 1?
No
Read Status Register With
QBHF = 1
Read SCRQ[8:15]
Write QBHF = 0
Yes
IDLE = 1?
No
Clear QRE and/or RE
To Exit the Queue
DONE
Figure 14-21 Queue Receive Software Flow
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14.9.12 Example QSCI1 Receive Operation of 17 Data Frames
Figure 14-22 shows an example receive operation of 17 data frames. The bold type
indicates the current value for the QRPNT. Action of the queue may be followed by
starting at the top of the figure and going left to right and then down the page.
1
Receive Queue Enabled
QRPNT
0000
SCRQ[0]
QTHF Interrupt Received
2
QRPNT
0000
Data
Received
SCRQ[0]
Available
Space
0111
SCRQ[7]
0111
SCRQ[7]
1000
SCRQ[8]
1000
SCRQ[8]
1111
SCRQ[15]
1111
SCRQ[15]
Read SCSR and SCRQ[0:7]
Clear QTHF
3
QBHF Interrupt Received
QRPNT
0000
SCRQ[0]
4
IDLE Interrupt Received
QRPNT
0000
SCRQ[0]
0001
0111
SCRQ[7]
0111
SCRQ[7]
1000
SCRQ[8]
1000
SCRQ[8]
1111
SCRQ[15]
1111
SCRQ[15]
Read SCRQ[8:15]
Clear QBHF
Read SCRQ[0]
Clear QRE/RE
Figure 14-22 Queue Receive Example for 17 Data Bytes
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SECTION 15
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
The modular I/O system (MIOS) consists of a library of flexible I/O and timer functions
including I/O port, counters, input capture, output compare, pulse and period measurement, PWM and angle degree clock. Because the MIOS is composed of submodules,
it is easily configurable for different kinds of applications. MIOS1 is the implementation
of the MIOS architecture used in the MPC555.
The MIOS1 is composed of the following submodules:
• 1 MIOS bus interface submodule (MBISM)
• 1 MIOS counter prescaler submodule (MCPSM)
• 2 MIOS modulus counter submodules (MMCSM)
• 10 MIOS double action submodules (MDASM)
• 8 MIOS pulse width modulation submodules (MPWMSM)
• 1 MIOS 16-bit parallel port I/O submodule (MPIOSM)
• 2 MIOS interrupt request submodules (MIRSM)
15.1 MIOS1 Features
The basic features of the MIOS1 are as follows:
• Modular architecture at the silicon implementation level
• Disable capability in each submodule to allow power saving when its function is
not needed
• Two 16-bit buses to allow action submodules to use counter data
• When not used for timing functions, every channel pin can be used as a port pin:
I/O, output only or input only, depending on the channel function
• Submodules pin status bits:
• MIOS counter prescaler submodule (MCPSM):
— Centralized counter clock generator
— Programmable 4-bit modulus down-counter
— Wide range of possible division ratios: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15 and 16
— Count inhibit under software control
• Two MIOS modulus counter submodules (MMCSM), each with these features:
— Programmable 16-bit modulus up-counter with built-in programmable 8-bit
prescaler clocked by MCPSM output
— Maximum increment frequency of the counter:
• clocked by the internal Counter Clock: fSYS /2
• clocked by the external pin: fSYS /4
— Flag setting and possible interrupt generation on overflow of the up-counter
— Time counter on internal clock with interrupt capability after a pre-determined
time
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— Optional pin usable as an external event counter (pulse accumulator) with
overflow and interrupt capability after a pre-determined number of external
events
— Usable as a regular free-running up-counter
— Capable of driving a dedicated 16-bit counter bus to provide timing information
to action submodules — the value driven is the contents of the 16-bit upcounter register
— Optional pin to externally force a load of the counter with modulus value
• Ten MIOS double action submodules (MDASM), each with these features:
— Versatile 16-bit dual action unit allowing two events to occur before software
intervention is required
— Six software selectable modes allowing the MDASM to perform pulse width
and period measurements, PWM generation, single input capture and output
compare operations as well as port functions
— Software selection of one of the two possible 16-bit counter buses used for timing operations
— Flag setting and possible interrupt generation after MDASM action completion
— Software selection of output pulse polarity
— Software selection of totem-pole or open-drain output
— Software readable output pin status
• Eight MIOS pulse width modulation submodules (MPWMSM), each with these
features:
— Output pulse width modulated (PWM) signal generation with no software involvement
— Built-in 8-bit programmable prescaler clocked by the MCPSM
— PWM period and pulse width values provided by software:
• Double-buffered for glitch-free period and pulse width changes
• 2-cycle minimum output period/pulse-width increment
(50 ns at fSYS = 40 MHz)
• 50% duty-cycle output maximum frequency: 10 MHz
• Up to 16 bits output pulse width resolution
• Wide range of periods:
— 16 bits of resolution: period range from 3.27 ms (with 50 ns steps) to 6.71
s (with 102.4 µs steps)
— 8 bits of resolution: period range from 12.8 µs (with 50 ns steps) to 26.2 ms
(with 102.4 µs steps)
• Wide range of frequencies:
— Maximum output frequency at fSYS = 40 MHz with 16 bits of resolution and
divide-by-2 prescaler selection: 305 Hz (3.27 ms.)
— Minimum output frequency at fSYS = 40 MHz with 16 bits of resolution and
divide-by-4096 prescaler selection: 0.15 Hz (6.7 s.)
— Maximum output frequency at fSYS = 40 MHz with 8 bits of resolution and
divide-by-2 prescaler selection: 78125 Hz (12.8 µs.)
— Minimum output frequency at fSYS = 40 MHz with 8 bits of resolution and
divide-by-4096 prescaler selection: 38.14 Hz (26.2 ms.)
— Programmable duty cycle from 0% to 100%
— Possible interrupt generation after every period
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— Software selectable output pulse polarity
— Software readable output pin status
— Possible use of pin as I/O port when PWM function is not needed
• MIOS 16-bit parallel port I/O submodule (MPIOSM):
— 16 parallel input/output pins
— Simple data direction register (DDR) concept for selection of pin direction
15.2 Submodule Numbering, Naming and Addressing
A block is a group of four 16-bit registers. Each of the blocks within the MIOS1
addressing range is assigned a block number. The first block is located at the base
address of the MIOS1. The blocks are numbered sequentially starting from 0.
Every submodule instantiation is also assigned a number. The number of a given
submodule is the block number of the first block of this submodule.
A submodule is assigned a name made of its acronym followed by its submodule
number. For example, if submodule number 18 were an MPWMSM, it would be
named MPWMSM18.
This numbering convention does not apply to the MBISM, the MCPSM and the
MIRSMs. The MBISM and the MCPSM are unique in the MIOS1 and do not need
a number. The MIRSMs are numbered incrementally starting from zero.
The MIOS1 base address is defined at the chip level and is referred to as the
“MIOS1 base address.” The MIOS1 addressable range is 4 Kbytes.
The base address of a given implemented submodule within the MIOS1 is the sum
of the base address of the MIOS1 and the submodule number multiplied by eight.
(Refer to Table 15-36.)
This does not apply to the MBISM, the MCPSM and the MIRSMs. For these submodules, refer to the MIOS1 memory map (Figure 15-2).
15.3 MIOS1 Signals
The MIOS1 requires 34 pins: 10 MDASM pins, 8 MPWMSM pins and 16 MPIOSM
pins. The usage of these pins is shown in the block diagram of Figure 15-1 and in
the configuration description of Table 15-36. In the figure, MDASM pins have a prefix MDA, MPWMSM pins have a prefix of MPWM and the port pins have a prefix of
MPIO. The modulus counter clock and load pins are multiplexed with MDASM pins.
The MIOS1 input and output pin names are composed of five fields according to
the following convention:
• “M”
• <submodule short_prefix>
• <submodule number>
• <pin attribute suffix> (optional)
• <bit number> (optional)
MPC555
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MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
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15-3
The pin prefix and suffix for the different MIOS submodules are as follows:
• MMCSM:
— submodule short_prefix: “MC”
— pin attribute suffix: C for the Clock pin
— pin attribute suffix: L for the Load pin
— For example, an MMCSM placed as submodule number n would have its corresponding input clock pin named MMCnC and its input load pin named
MMCnL. On the MPC555 MMC6C is input on MDA11 and MMC22C is input
on MDA13. The MMC6L is input on MDA12 and MMC22C is input on MDA14.
• MDASM:
— submodule short_prefix: “DA”
— pin attribute suffix: none
— For example a MDASM placed as submodule number n would have its corresponding channel I/O pin named MDAn
• MPWMSM:
— submodule short_prefix: “PWM”
— pin attribute suffix: none
— For example a MPWMSM placed as submodule number n would have its corresponding channel I/O pin named MPWMn
• MPIOSM:
— submodule short_prefix: “PIO”
— pin attribute suffix: B
— For example a MPIOSM placed as submodule number n would have its corresponding I/O pins named MPIOnB0 to MPIOnB15 for bit-0 to bit-15, respectively.
In the MIOS1, some pins are multiplexed between submodules using the same pin
names for the inputs and outputs which are connected as shown in Table 15-36.
15.4 Block Diagram
Figure 15-1 is a block diagram of the MIOS1.
MOTOROLA
15-4
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
16-bit Counter Bus 22
(CB22)
Channel and
I/O Pins:
34 Pins
MDASM11
MDA11
Double Action
MDA14
MDA13
L
MMCSM22
C
Modulus Counter
5xDASM
MDASM15
MDA15
Double Action
16-Bit Counter Bus 6
(CB6)
MDASM27
MDA27
Double Action
5xDASM
MDA12
L
MMCSM6
MDASM31
MDA11
C
Modulus Counter
Double Action
MPWMSM0
MDA31
MPWM0
PWM
4xPWMSM
Counter
Clock
MPWMSM3
MPWM3
PWM
Modular I/O Bus (MIOB)
MPWMSM16
(To all Submodules)
PWM
MPWM16
4xPWMSM
MPWMSM19
MPWM19
PWM
MCPSM
Bus Interface
Interrupt
Unit Submodule
Submodules
MPIO32B0
MPIOSM32
16-bit Port I/O
MPIO32B15
IMB3 Clock
(FSYS)
IMB3
Figure 15-1 MIOS1 Block Diagram
MPC555
USER’S MANUAL
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-5
15.5 MIOS1 Bus System
The internal bus system within the MIOS1 is called the modular I/O bus (MIOB). The
MIOB makes communications possible between any submodule and the IMB3 bus
master through the MBISM.
The MIOB is divided into three dedicated buses:
• The read/write and control bus
• The request bus
• The counter bus set
15.5.1 Read/Write and Control Bus
The read/write and control bus (RWCB) allows read and write data transfers to and
from any I/O submodule through the MBISM. It includes signals for data and
addresses as well as control signals. The control signals allow 16-bit simple synchronous single master accesses and supports fast or slow master accesses.
15.5.2 Request Bus
The request bus (RQB) provides interrupt request signals along with I/O submodule
identification and priority information to the MBISM.
Note that some submodules do not generate interrupts and are therefore independent
of the RQB.
15.5.3 Counter Bus Set
The 16-bit counter bus set (CBS) is a set of two 16-bit counter buses. The CBS makes
it possible to transfer information between submodules. Typically, counter submodules drive the CBS, while action submodules process the data on these buses. Note,
however, that some submodules are self-contained and therefore independent of the
counter bus set.
15.6 MIOS1 Programmer’s Model
The address space of the MIOS1 consist of 4 Kbytes starting at the base address of
the module. The MIOS1 base address is a multiple of the addressable range. The
overall address map organization is shown in Figure 15-2.
To find the base address of a given implementation, refer to 1.3 MPC555 Address
Map. To find the submodule base address, refer to Table 15-36.
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15-6
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
MPWMSM0
MPWMSM1
MPWMSM2
MPWMSM3
Reserved
MMCSM6
0x30 6000
0x30 6008
0x30 6010
0x30 6018
0x30 6030
Reserved
MDASM11
MDASM12
MDASM13
Base Address
MDASM14
0x30 6000
MDASM15
Channels
0x30 6060
0x30 6068
0x30 6070
0x30 6078
MPWMSM16
0x30 6080
MPWMSM17
0x30 6088
MPWMSM18
Supervisor/
Unrestricted
0x30 6058
MPWMSM19
0x30 6090
0x30 6098
Reserved
MMCSM22
Reserved
0x30 60B0
Reserved
0x30 6800
0x30 6810
MDASM27
MBISM
MDASM28
MCPSM
MDASM29
MDASM30
MDASM31
Supervisor
MPIOSM32
0x30 60D8
0x30 60E0
0x30 60E8
0x30 60F0
0x30 60F8
0x30 6100
0x30 6C00
0x30 6C40
MIRSM0
MIRSM1
Supervisor
Reserved
0x30 6FFF
Submodules 15 to 0
Reserved
MIOS1SR0
Reserved
MIOS1ER0
MIOS1RPR0
0x30 6C00
0x30 6C02
0x30 6C04
0x30 6C06
Reserved
MIOS1LVL0
0x30 6C30
Submodules 31 to 16
Reserved
MIOS1SR1
Reserved
MIOS1ER1
MIOS1RPR1
0x30 6C40
0x30 6C42
0x30 6C44
0x30 6C46
Reserved
MIOS1LVL1
0x30 6C70
Reserved
Figure 15-2 MIOS1 Memory Map
MPC555
USER’S MANUAL
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-7
If a supervisor privilege address space is accessed in user mode, the module returns
a bus error.
All MIOS1 unimplemented locations within the addressable range, return a logic 0
when accessed. In addition, the internal TEA (transfer error acknowledge) signal is
asserted.
All unused bits within MIOS1 registers return a 0 when accessed.
15.7 MIOS1 I/O Ports
Each pin of each submodule can be used as an input, output, or I/O port:
Table 15-1 MIOS1 I/O Ports
Submodule
Number
Type
MPIOSM
16
I/O
MMCSM
2
Input
MDASM
1
I/O
MPWMSM
1
I/O
15.8 MIOS Bus Interface Submodule (MBISM)
The MIOS bus interface submodule (MBISM) is used as an interface between the
MIOB (modular I/O bus) and the IMB3. It allows the CPU to communicate with the
MIOS1 submodules.
15.8.1 MIOS Bus Interface (MBISM) Registers
Table 15-2 is the address map for the MBISM submodule.
Table 15-2 MBISM Address Map
Address
Register
0x30 6800
MIOS1 Test and Pin Control Register (MIOS1TPCR)
See Table 15-3 for bit descriptions.
0x30 6802
Reserved (MIOS1 Vector Register in some implementations
0x30 6804
MIOS1 Module Version Number Register (MIOS1VNR)
See Table 15-4 for bit descriptions.
0x30 6806
MIOS1 Module Control Register (MIOS1MCR)
See Table 15-4 for bit descriptions.
0x30 6808 –
Reserved
0x30 680E
15.8.1.1 MIOS1 Test and Pin Control Register
MIOS1TPCR — Test and Pin Control Register
MSB
0
1
2
3
4
5
6
TEST
7
8
0x30 6800
9
10
11
12
13
RESERVED
14
LSB
15
VF
VFLS
0
0
RESET:
0
0
MOTOROLA
15-8
0
0
0
0
0
0
0
0
0
0
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
0
0
MPC555
USER’S MANUAL
This register is used for MIOS1 factory testing and selecting between the MIOS1 pin
functions for the MPIO32B[0:3] and the developement support pin functions of
VFLS[0:1] and VF[0-2].
Table 15-3 MIOS1TPCR Bit Settings
Bit(s)
Name
0
TEST
1:13
—
14
Reserved
Pin multiplex. This bit is used to determine the usage of the MIOS1 pins. Refer to the pad-ring
specification of the chip for details about the usage of this bit. This bit is set to 0 by reset.
VF
15
Description
This bit is reserved for factory testing of the MIOS1. The test mode is disabled by reset.
0 = the concerned pins are dedicated to the MIOS1.
1 = alternate function
VFLS
Pin multiplex. This bit is used to determine the usage of the MIOS1 pins. Refer to the pad-ring
specification of the chip for details about the usage of this bit. This bit is set to 0 by reset.
0 = the concerned pins are dedicated to the MIOS1.
1 = alternate function
15.8.1.2 MIOS1 Vector Register
This register is used only in MCUs that use vectored interrupts. The MPC555 does not
use this register.
15.8.1.3 MIOS1 Module and Version Number Register
This read-only register contains the hard-coded values of the module and version
number.
MIOS1VNR — MIOS1 Module/Version Number Register
MSB
0
1
2
3
4
5
6
7
8
9
0x30 6804
10
11
MN
12
13
14
LSB
15
VN
Table 15-4 MIOS1VNR Bit Settings
Bit(s)
Name
Description
0:7
MN
Module number = 1 on the MPC555. The MPC555 implements the MIOS1 module.
8:15
VN
Version number
15.8.1.4 MIOS1 Module Configuration Register
MIOS1MCR — MIOS1 Module Configuration Register
MSB
0
1
2
3
STOP
0
FRZ
RST
0
0
0
4
5
6
7
RESERVED
8
9
0x30 6806
10
11
12
RESERVED
SUPV
13
14
LSB
15
RESERVED (IARB)
RESET:
0
MPC555
USER’S MANUAL
0
0
0
0
0
0
0
0
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
0
0
0
0
MOTOROLA
15-9
Table 15-5 MIOS1MCR Bit Settings
Bit(s)
Name
Description
0
STOP
Stop enable. Setting the STOP bit activates the MIOB freeze signal regardless of the state of
the IMB3 FREEZE signal. The MIOB freeze signal is further validated in some submodules with
internal freeze enable bits in order for the submodule to be stopped. The MBISM continues to
operate to allow the CPU access to the submodule’s registers. The MIOB freeze signal remains
active until reset or until the STOP bit is written to zero by the CPU (via the IMB3). The STOP
bit is cleared by reset.
0 = Enables MIOS1 operation.
1 = Selectively stops MIOS1 operation.
1
—
Reserved
FRZ
Freeze enable. Setting the FRZ bit, activates the MIOB freeze signal only when the IMB3
FREEZE signal is active. The MIOB freeze signal is further validated in some submodules with
internal freeze enable bits in order for the submodule to be frozen. The MBISM continues to
operate to allow the CPU access to the submodule’s registers. The MIOB freeze signal remains
active until the FRZ bit is written to zero or the IMB3 FREEZE signal is negated. The FRZ bit is
cleared by reset.
0 = Ignores the FREEZE signal on the IMB3, allowing MIOS1 operation.
1 = Selectively stops MIOS1 operation when the FREEZE signal appears on the IMB3.
3
RST
Module reset. The RST bit always returns 0 when read and can be written to 1. When the RST
bit is written to 1, the MBISM activates the reset signal on the MIOB. This completely stops the
operation of the MIOS1 and resets all the values in the submodules registers that are affected
by reset. This bit provides a way of resetting the complete MIOS1 module regardless of the reset
state of the CPU. The RST bit is cleared by reset.
0 = Writing a 0 to RST has no effect.
1 = Reset the MIOS1 submodules
4:7
—
2
Reserved
8
SUPV
Supervisor data space selector. The SUPV bit specifies whether the address space from 0x0000
to 0x07FF in the MIOS1 is accessed at the supervisor privilege level. When SUPV is cleared,
these addresses are accessed at the Unrestricted privilege level. The SUPV bit is cleared by
reset.
0 = Unrestricted data space.
1 = Supervisor data space.
9:15
—
Reserved. In implementations that use hardware interrupt arbitration, bits 12:15 represent the
IARB field.
15.8.2 MBISM Interrupt Registers
Table 15-6 shows the MBISM interrupt registers.
Table 15-6 MBISM Interrupt Registers Address Map
Address
Register
0x30 6830
MIOS1 Interrupt Level Register 0 (MIOS1LVL0)
See Table 15-7 for bit descriptions.
0x30 6870
MIOS1 Interrupt Level Register 1 (MIOS1LVL1)
See Table 15-8 for bit descriptions.
15.8.2.1 MIOS1 Interrupt Level Register 0 (MIOS1LVL0)
This register contains the interrupt level that applies to the submodules number 15 to
zero.
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15-10
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
MIOS1LVL0 — MIOS1 Interrupt Level Register 0
MSB
0
1
2
3
4
5
RESERVED
6
7
8
LVL
0x30 6C30
9
10
11
TM
12
13
14
LSB
15
0
0
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-7 MIOS1LVL0 Bit Settings
Bit(s)
Name
Description
0:4
—
Reserved
5:7
LVL
Interrupt request level. This field represents one of eight possible levels.
8:9
TM
Time multiplexing. This field determines the multiplexed time slot
10:15
—
Reserved
15.8.2.2 MIOS1 Interrupt Level Register 1 (MIOS1LVL1)
This register contains the interrupt level that applies to the submodules number 31 to
16.
MIOS1LVL1 — MIOS1 Interrupt Level 1 Register
MSB
0
1
2
3
4
5
RESERVED
6
7
8
LVL
0x30 6C70
9
10
11
TM
12
13
14
LSB
15
0
0
RESERVED
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-8 MIOS1LVL1 Bit Settings
Bit(s)
Name
Description
0:4
—
5:7
LVL
Reserved
Interrupt request level. This field represents one of eight possible levels.
8:9
TM
Time multiplexing. This field determines the multiplexed time slot.
10:15
—
Reserved
15.8.3 Interrupt Control Section (ICS)
The interrupt control section delivers the interrupt level to the CPU. The interrupt control section adapts the characteristics of the MIOB request bus to the characteristics
of the interrupt structure of the IMB3.
When at least one of the flags is set on an enabled level, the ICS receives a signal
from the corresponding IRQ pending register. This signal is the result of a logical “OR”
between all the bits of the IRQ pending register.
The signal received from the IRQ pending register is associated with the interrupt level
register within the ICS. This level is coded on five bits in this register: three bits represent one of eight levels and the two other represent the four time multiplex slots.
MPC555
USER’S MANUAL
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-11
According to this level, the ICS sets the correct IRQ[7:0] lines with the correct
ILBS[1:0] time multiplex lines on the peripheral bus. The CPU is then informed as to
which of the thirty-two interrupt levels is requested.
Based on the interrupt level requested, the software must determine which submodule
requested the interrupt. The software may use a find-first-one type of instruction to
determine, in the concerned MIRSM, which of the bits is set. The CPU can then serve
the requested interrupt.
15.9 MIOS Counter Prescaler Submodule (MCPSM)
The MIOS counter prescaler submodule (MCPSM) divides the MIOS1 clock (fSYS) to
generate the counter clock. It is designed to provide all the submodules with the same
division of the main MIOS1 clock (division of fSYS). It uses a 4-bit modulus counter.
The clock signal is prescaled by loading the value of the clock prescaler register into
the prescaler counter every time it overflows. This allows all prescaling factors
between two and 16. Counting is enabled by asserting the PREN bit in the control register. The counter can be stopped at any time by negating this bit, thereby stopping all
submodules using the output of the MCPSM (counter clock).
fSYS
Dec.
CP0
Clock
CP1
Register
Counter Clock
4-bit
Prescaler
= 1?
CP2
Decrementer
CP3
Enable
MCPSMSCR
Load
PREN
Figure 15-3 MCPSM Block Diagram
15.9.1 MIOS Counter Prescaler Submodule (MCPSM) Registers
Table 15-9 is the address map for the MCPSM submodule.
MOTOROLA
15-12
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 15-9 MCPSM Address Map
Address
Register
0x30 6810 –
Reserved
0x30 6814
0x30 6816
MCPSM Status/Control Register (MCPSMSCR)
See Table 15-10 for bit descriptions.
15.9.1.1 MCPSM Status/Control Register (MCPSMCSCR)
This register contains status and control information for the MCPSM.
MCPSMSCR — MCPSM Status/Control Register
MSB
0
1
2
3
4
5
6
7
8
0x30 6816
9
10
11
12
13
RESERVED
PREN FREN
14
LSB
15
0
0
PSL
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-10 MCPSMSCR Bit Settings
Bit(s)
0
Name
PREN
Description
Prescaler enable. This active high read/write control bit enables the MCPSM counter. The
PREN bit is cleared by reset.
0 = MCPSM counter disabled.
1 = MCPSM counter enabled.
Freeze enable. This active high read/write control bit when set make possible a freeze of the
MCPSM counter if the MIOB freeze line is activated. Note that this line is active when the
MIOS1MCR STOP bit is set or when the MIOS1MCR FREN bit and the IMB3 FREEZE line are
set.
1
FREN
2:11
—
12:15
PSL
MPC555
USER’S MANUAL
When the MCPSM is frozen, it stops counting. Then when the FREN bit is reset or when the
freeze condition on the MIOB is negated, the counter restarts from where it was before being
frozen. The FREN bit is cleared by reset.
0 = MCPSM counter not frozen.
1 = Selectively stops MIOS1 operation when the FREEZE signal appears on the IMB3.
Reserved
Clock prescaler. This 4-bit read/write data register stores the modulus value for loading into
the clock prescaler. The new value is loaded into the counter on the next time the counter
equals one or when disabled (PREN bit = 0). Divide ratios are as follows:
0000 = 16
0001 = No counter clock output
0010 = 2
0011 = 3
.
.
.
1110 = 14
1111 = 15
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-13
15.10 MIOS Modulus Counter Submodule (MMCSM)
The MMCSM is a versatile counter submodule capable of performing complex counting and timing functions, including modulus counting, in a wide range of applications.
The MMCSM may also be configured as an event counter, allowing the overflow flag
to be set after a predefined number of events (internal clocks or external events), or
as a time reference for other submodules. Note that the MMCSM can also operate as
a free running counter by loading the modulus value of zero.
The main components of the MMCSM are an 8-bit prescaler counter, an 8-bit prescaler register, a 16-bit up-counter register, a 16-bit modulus latch register, counter
loading and interrupt flag generation logic.
The contents of the modulus latch register is transferred to the counter under the following three conditions:
1. When an overflow occurs
2. When an appropriate transition occurs on the external load pin
3. When the program writes to the counter register. In this case, the value is first
written into the modulus register and immediately transferred to the counter.
Software can also write a value to the modulus register for later loading into the
counter with one of the two first criteria.
A software control register selects whether the clock input to the counter is the prescaler output or the corresponding input pin. The polarity of the external input pin is also
programmable.
Refer to Table 15-36 for the MMCSM relative I/O pin implementation.
MOTOROLA
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MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
16-bit Counter Bus
8-bit Clock
Counter Clock
Prescaler
Clock input pin
(MDA11/MDA13)
Edge
Clock
Clock
Detect
Select
Enable
Clock
Request Bus
Flag
MMCSMSCR
CP0 - CP7
PINC
8-bit Prescaler
Modulus Register
CLS0
CLS1
FREN
MMCSMCNT
16-bit Up-Counter Register
Modulus Load Pin
Load
(MDA12/MDA14)
Edge
Detect
MMCSMSCR
PINL
EDGN
EDGP
Load
Control
Overflow
MMCSMML 16-bit Modulus Latch Register
MIOB
Figure 15-4 MMCSM Block Diagram
15.10.1 MIOS Modulus Counter Submodule (MMCSM) Registers
Each of the two MMCSM submodules in the MPC555 includes the register set shown
in Table 15-11.
Table 15-11 MMCSM Address Map
Address
Register
MMCSM6
0x30 6030
MMCSM6 Up-Counter Register (MMCSMCNT)
See Table 15-12 for bit descriptions.
0x30 6032
MMCSM6 Modulus Latch Register (MMCSMML)
See Table 15-13 for bit descriptions.
0x30 6034
MMCSM6 Status/Control Register Duplicated (MMCSMSCRD)
See 15.10.1.3 MMCSM Status/Control Register (Duplicated) for bit
descriptions.
0x30 6036
MMCSM6 Status/Control Register (MMCSMSCR)
MMCSM22
0x30 60B0
MMCSM Up-Counter Register (MMCSMCNT)
0x30 60B2
MMCSM Modulus Latch Register (MMCSMML)
0x30 60B4
MMCSM Status/Control Register Duplicated (MMCSMSCRD)
0x30 60B6
MMCSM Status/Control Register (MMCSMSCR)
MPC555
USER’S MANUAL
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-15
15.10.1.1 MMCSM Up-Counter Register (MMCSMCNT)
The MMCSMCNT register contains the 16-bit value of the up counter. Note that writing
to MMCSMCNT simultaneously writes to MMCSMML.
MMCSMCNT — MMCSM Up-Counter Register
MSB
0
1
2
3
4
5
6
7
0x30 6030
0x30 60B0
8
9
10
11
12
13
14
LSB
15
U
U
U
U
U
U
U
U
CNT
RESET:
U
U
U
U
U
U
U
U
U = Unaffected by reset
Table 15-12 MMCSMCNT Bit Settings
Bit(s)
Name
Description
0:15
CNT
Counter value. These read/write data bits represent the 16-bit value of the up-counter. CNT contains the value that is driven onto the 16-bit counter bus.
15.10.1.2 MMCSM Modulus Latch Register (MMCSMML)
The MMCSMML is a read/write register containing the 16-bit value of the up-counter.
MMCSMML — MMCSM Modulus Latch Register
MSB
0
1
2
3
4
5
6
7
0x30 6032
0x30 60B2
8
9
10
11
12
13
14
LSB
15
U
U
U
U
U
U
U
U
ML
RESET:
U
U
U
U
U
U
U
U
U = Unaffected by reset
Table 15-13 MMCSMML Bit Settings
Bit(s)
Name
Description
Modulus latches. These bits are read/write data bits containing the 16-bit modulus value to be
loaded into the up-counter.
0:15
ML
The value loaded in this register must be the two’s complement of the desired modulus count.
The up-counter increments from this two’s complement value up to 0xFFFF to get the correct
number of steps before an overflow is generated to reload the modulus value into the upcounter. A value of 0x0000 should be used for a free-running counter.
15.10.1.3 MMCSM Status/Control Register (Duplicated)
The MMCSMSCRD and the MMCSMSCR are the same registers accessed at two different addresses. Reading or writing to one of these two addresses has exactly the
same effect.
MOTOROLA
15-16
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
NOTE
The user should not write directly to the address of the MMCSMSCRD. This register’s address may be reserved for future use and
should not be accessed by the software to assure future software
compatibility.
MMCSMSCRD — MMCSM Status/Control Register (Duplicated)
MSB
0
1
PINC
PINL
2
3
4
5
FREN EDGN EDGP
6
CLS
7
8
9
10
0x30 6034
0x30 60B4
11
—
12
13
14
LSB
15
U
U
U
U
CP
RESET:
—
—
0
0
0
0
0
0
U
U
U
U
15.10.1.4 MMCSM Status/Control Register (MMCSMSCR)
This register contains both read-only status bits and read/write control bits.
MMCSMSCR — MMCSM Status/Control Register
MSB
0
1
PINC
PINL
2
3
4
5
FREN EDGN EDGP
6
CLS
7
8
0x30 6036
0x30 60B6
9
10
11
—
12
13
14
LSB
15
U
U
U
U
CP
RESET:
—
—
0
MPC555
USER’S MANUAL
0
0
0
0
0
U
U
U
U
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-17
Table 15-14 MMCSMSCR Bit Settings
Bit(s)
Name
0
PINC
Clock input pin status. This read-only status bit reflects the logic state of the clock input pin
MMCnC (MDA11 or MDA13).
1
PINL
Modulus load input pin status. This read-only status bit reflects the logic state of the modulus
load pin MMCnL (MDA12 or MDA14).
2
FREN
Freeze enable. This active high read/write control bit enables the MMCSM to recognize the
MIOB freeze signal.
EDGN,
EDGP
Modulus load falling edge/rising edge sensitivity. These active high read/write control bits set
falling-edge and rising edge sensitivity, respectively, for the MMCnL pin (MDA12 or MDA14).
00 = Disabled
01 = MMCSMCNT load on rising edges
10 = MMCSMCNT load on falling edges
11 = MMCSMCNT load on rising and falling edges
3:4
Description
Clock select. These read/write control bits select the clock source for the modulus counter.
00 = Disabled
01 = Falling edge of MMCnC (MDA11 or MDA13) pin
10 = Rising edge of MMCnC (MDA11 or MDA13) pin
11 = MMCSM clock prescaler
5:6
CLS
7
—
—
CP
Clock prescaler. This 8-bit read/write data register stores the two’s complement of the desired
modulus value for loading into the built-in 8-bit clock prescaler. The new value is loaded into the
prescaler counter when the next counter overflow occurs or when the CLS bits are set to select
the clock prescaler as the clock source.Table 15-15 gives the clock divide ratio according to the
CP values
8:15
Table 15-15 MMCSMCR CP and
MPWMSMSCR CP Values
Prescaler Value
(CP in hex)
MIOS Prescaler Clock
Divided by
FF
1
FE
2
FD
3
FC
4
FB
5
FA
6
F9
7
F8
8
......
........
02
254 (2^8 -2)
01
255 (2^8 -1)
00
256 (2^8)
15.11 MIOS Double Action Submodule (MDASM)
The MIOS double action submodule (MDASM) provides two consecutive 16-bit input
captures or two consecutive 16-bit output compare functions that can occur automatically without software intervention. The input edge detector is programmable to trigger
the capture function to occur on the desired edge. The output flip-flop is set by one of
MOTOROLA
15-18
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
the output compares and is reset by the other one. In all modes except disable mode,
an optional interrupt is available to the software. Software selection is provided to
select which of the incoming 16-bit counter buses is used for the input capture or the
output compare.
The MDASM has six different software selectable modes:
• Disable mode
• Pulse width measurement
• Period measurement
• Input capture mode
• Single pulse generation
• Continuous pulse generation
The MDASM has three data registers that are accessible to the software from the various modes. For some of the modes, two of the registers are cascaded together to
provide double buffering. The value in one register is transferred to the other register
automatically at the correct time so that the minimum pulse (measurement or generation) is just one 16-bit counter bus count.
Refer to Table 15-36 for the MDASM relative I/O pin implementation.
MPC555
USER’S MANUAL
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-19
CBn
CBn+1
4 X 16-bit
Counter Buses
CBn+2
CBn+3
Counter Bus
Select
BSL1
BSL0
FORCA FORCB
WOR
Output
Flip-Flop
Output
Buffer
16-bit Comparator A
PIN
I/O Pin
EDPOL
16-bit Register A
Edge
Detect
16-bit Register B1
Register B
FLAG
16-bit Register B2
16-bit Comparator B
MODE0
MODE1
MODE2
MODE3
Request Bus
Control Register Bits
MIOB
Figure 15-5 MDASM Block Diagram
15.11.1 MIOS Double Action Submodule (MDASM) Registers
One set of registers is associated with each MDASM submodule. The base address
of the particular submodule is shown in the table below.
MOTOROLA
15-20
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 15-16 MDASM Address Map
Address
Register
MDASM11
0x30 6058
MDASM11 Data A Register (MDASMAR)
See 15.11.1.1 MDASM Data A Register for bit descriptions.
0x30 605A
MDASM11 Data B Register (MDASMBR)
See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions.
0x30 605C
MDASM11 Status/Control Register Duplicated (MDASMSCRD)
See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit
descriptions.
0x30 605E
MDASM11 Status/Control Register (MDASMSCR)
See Table 15-17 for bit descriptions.
MDASM12
0x30 6060
MDASM12 Data A Register (MDASMAR)
0x30 6062
MDASM12 Data B Register (MDASMBR)
0x30 6064
MDASM12 Status/Control Register Duplicated (MDASMSCRD)
0x30 6066
MDASM12 Status/Control Register (MDASMSCR)
MDASM13
0x30 6068
MDASM13 Data A Register (MDASMAR)
0x30 606A
MDASM13 Data B Register (MDASMBR)
0x30 606C
MDASM13 Status/Control Register Duplicated (MDASMSCRD)
0x30 606E
MDASM13 Status/Control Register (MDASMSCR)
MDASM14
0x30 6070
MDASM14 Data A Register (MDASMAR)
0x30 6072
MDASM14 Data B Register (MDASMBR)
0x30 6074
MDASM14 Status/Control Register Duplicated (MDASMSCRD)
0x30 6076
MDASM14 Status/Control Register (MDASMSCR)
0x30 6078
MDASM15 Data A Register (MDASMAR)
0x30 607A
MDASM15 Data B Register (MDASMBR)
0x30 607C
MDASM15 Status/Control Register Duplicated (MDASMSCRD)
0x30 607E
MDASM15 Status/Control Register (MDASMSCR)
MDASM15
MDASM27
0x30 60D8
MDASM27 Data A Register (MDASMAR)
0x30 60DA
MDASM27 Data B Register (MDASMBR)
0x30 60DC MDASM27 Status/Control Register Duplicated (MDASMSCRD)
0x30 60DE
MDASM27 Status/Control Register (MDASMSCR)
MDASM28
0x30 60E0
MDASM28 Data A Register (MDASMAR)
0x30 60E2
MDASM28 Data B Register (MDASMBR)
0x30 60E4
MDASM28 Status/Control Register Duplicated (MDASMSCRD)
0x30 60E6
MDASM28 Status/Control Register (MDASMSCR)
MDASM29
0x30 60E8
MPC555
USER’S MANUAL
MDASM29 Data A Register (MDASMAR)
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-21
Table 15-16 MDASM Address Map (Continued)
Address
Register
0x30 60EA
MDASM29 Data B Register (MDASMBR)
0x30 60EC
MDASM29 Status/Control Register Duplicated (MDASMSCRD)
0x30 60EE
MDASM29 Status/Control Register (MDASMSCR)
MDASM30
0x30 60F0
MDASM30 Data A Register (MDASMAR)
0x30 60F2
MDASM30 Data B Register (MDASMBR)
0x30 60F4
MDASM30 Status/Control Register Duplicated (MDASMSCRD)
0x30 60F6
MDASM30 Status/Control Register (MDASMSCR)
0x30 60F8
MDASM31 Data A Register (MDASMAR)
0x30 60FA
MDASM31 Data B Register (MDASMBR)
0x30 60FC
MDASM31 Status/Control Register Duplicated (MDASMSCRD)
0x30 60FE
MDASM31 Status/Control Register (MDASMSCR)
MDASM31
15.11.1.1 MDASM Data A Register
MDASMAR is the data register associated with channel A. Its use varies with the mode
of operation:
• In the DIS mode, MDASMAR can be accessed to prepare a value for a subsequent mode selection
• In the IPWM mode, MDASMAR contains the captured value corresponding to the
trailing edge of the measured pulse
• In the IPM and IC modes, MDASMAR contains the captured value corresponding
to the most recently detected dedicated edge (rising or falling edge)
• In the OCB and OCAB modes, MDASMAR is loaded with the value corresponding
to the leading edge of the pulse to be generated. Writing to MDASMAR in the
OCB and OCAB modes also enables the corresponding channel A comparator
until the next successful comparison.
• In the OPWM mode, MDASMAR is loaded with the value corresponding to the
leading edge of the PWM pulse to be generated
MDASMAR — MDASM Data A Register
MSB
0
1
2
3
4
5
6
0x30 6058*
7
8
9
10
11
12
13
14
LSB
15
U
U
U
U
U
U
U
U
AR
RESET:
U
U
U
U
U
U
U
U
* Refer to Table 15-16 for a complete list of all the base addresses for the MDASM registers.
15.11.1.2 MDASM Data B Register (MDASMBR)
MDASMBR is the data register associated with channel B. Its use varies with the
mode of operation. Depending on the mode selected, software access is to register
B1 or register B2.
MOTOROLA
15-22
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
• In the DIS mode, MDASMBR can be accessed to prepare a value for a subsequent mode selection. In this mode, register B1 is accessed in order to prepare
a value for the OPWM mode. Unused register B2 is hidden and cannot be read,
but is written with the same value when register B1 is written.
• In the IPWM mode, MDASMBR contains the captured value corresponding to the
leading edge of the measured pulse. In this mode, register B2 is accessed; buffer
register B1 is hidden and cannot be accessed.
• In the IPM and IC modes, MDASMBR contains the captured value corresponding
to the most recently detected period edge (rising or falling edge). In this mode,
register B2 is accessed; buffer register B1 is hidden and cannot be accessed.
• In the OCB and OCAB modes, MDASMBR is loaded with the value corresponding
to the trailing edge of the pulse to be generated. Writing to MDASMBR in the
OCB and OCAB modes also enables the corresponding channel B comparator
until the next successful comparison. In this mode, register B2 is accessed; buffer register B1 is hidden and cannot be accessed.
• In the OPWM mode, MDASMBR is loaded with the value corresponding to the
trailing edge of the PWM pulse to be generated. In this mode, register B1 is accessed; buffer register B2 is hidden and cannot be accessed.
MDASMBR — MDASM Data B Register
MSB
0
1
2
3
4
5
6
0x30 605A*
7
8
9
10
11
12
13
14
LSB
15
U
U
U
U
U
U
U
U
BR
RESET:
U
U
U
U
U
U
U
U
* Refer to Table 15-16 for a complete list of all the base addresses for the MDASM registers.
15.11.1.3 MDASM Status/Control Register (Duplicated)
The MDASMSCRD and the MDASMSCR are the same registers accessed at two different addresses. Reading or writing to either of these two addresses has exactly the
same effect.
NOTE
The user should not write directly to the address of the MDASMSCRD. This register’s address may be reserved for future use and
should not be accessed by the software to assure future software
compatibility.
MDASMSCRD — MDASM Status/Control Register (Duplicated)
MSB
0
1
2
3
4
PIN
WOR
FREN
0
EDPOL
0
0
0
0
5
6
FORC FORC
A
B
7
8
9
RESERVED
10
BSL
11
0x30 605C*
12
13
0
14
LSB
15
0
0
MOD
RESET:
—
0
0
0
0
0
0
0
0
0
* Refer to Table 15-16 for a complete list of all the base addresses for the MDASM registers.
MPC555
USER’S MANUAL
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-23
15.11.1.4 MDASM Status/Control Register
The status/control register contains a read-only bit reflecting the status of the MDASM
pin as well as read/write bits related to its control and configuration.
MDASMSCR — MDASM Status/Control Register
MSB
0
1
2
3
4
PIN
WOR
FREN
0
EDPOL
0
0
0
0
5
6
FORC FORC
A
B
7
8
0x30 605E*
9
RESERVED
10
BSL
11
12
13
0
14
LSB
15
0
0
MOD
RESET:
—
0
0
0
0
0
0
0
0
0
* Refer to Table 15-16 for a complete list of all the base addresses for the MDASM registers.
MOTOROLA
15-24
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 15-17 MDASMSCR Bit Settings
Bit(s)
Name
0
PIN
Description
Pin input status. The pin input status bit reflects the status of the corresponding pin.
1
WOR
Wired-OR. In the DIS, IPWM, IPM and IC modes, the WOR bit is not used; reading this bit returns
the value that was previously written. In the OCB, OCAB and OPWM modes, the WOR bit selects
whether the output buffer is configured for open-drain or totem-pole operation.
0 = Output buffer is totem-pole.
1 = Output buffer is open-drain.
2
FREN
Freeze enable. This active high read/write control bit enables the MDASM to recognize the MIOB
freeze signal.
0 = The MDASM is not frozen even if the MIOB freeze line is active.
1 = The MDASM is frozen if the MIOB freeze line is active.
3
—
0
Polarity. In the DIS mode, this bit is not used; reading it returns the last value written.
In the IPWM mode, this bit is used to select the capture edge sensitivity of channels A and B.
0 = Channel A captures on a rising edge. Channel B captures on a falling edge.
1 = Channel A captures on a falling edge. Channel B captures on a rising edge.
4
EDPOL
In the IPM and IC modes, the EDPOL bit is used to select the input capture edge sensitivity of
channel A.
0 = Channel A captures on a rising edge.
1 = Channel A captures on a falling edge.
In the OCB, OCAB and OPWM modes, the EDPOL bit is used to select the voltage level on the
output pin.
0 = The output flip-flop logic level appears on the output pin: a compare on channel A sets the
output pin, a compare on channel B resets the output pin.
1 = The complement of the output flip-flop logic level appears on the output pin: a compare on
channel A resets the output pin; a compare on channel B sets the output pin.
5
FORCA
Force A. In the OCB, OCAB and OPWM modes, the FORCA bit allows the software to force the
output flip-flop to behave as if a successful comparison had occurred on channel A (except that
the FLAG line is not activated). Writing a one to FORCA sets the output flip-flop; writing a zero
to it has no effect.
In the DIS, IPWM, IPM and IC modes, the FORCA bit is not used and writing to it has no effect.
FORCA is cleared by reset and is always read as zero. Writing a one to both FORCA and
FORCB simultaneously resets the output flip-flop.
6
FORCB
Force B. In the OCB, OCAB and OPWM modes, the FORCB bit allows the software to force the
output flip-flop to behave as if a successful comparison had occurred on channel B (except that
the FLAG line is not activated). Writing a one to FORCB resets the output flip-flop; writing a zero
to it has no effect.
In the DIS, IPWM, IPM and IC modes, the FORCB bit is not used and writing to it has no effect.
FORCB is cleared by reset and is always read as zero. Writing a one to both FORCA and
FORCB simultaneously resets the output flip-flop.
7:8
—
9:10
BSL
11
—
12:15
MOD
MPC555
USER’S MANUAL
Reserved
Bus select.These bits are used to select which of the four possible 16-bit counter bus passing
nearby is used by the MDASM. Refer to Table 15-36 to see how the MDASM is connected to the
16-bit counter buses in the MIOS1.
0
Mode select. These four mode select bits select the mode of operation of the MDASM. To avoid
spurious interrupts, it is recommended that MDASM interrupts are disabled before changing the
operating mode. It is also imperative to go through the disable mode before changing the operating mode. See Table 15-18 for details.
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-25
Table 15-18 MDASM Mode Selects
MDASM Control Register Bits
MOD
Bits of
Resolution
Counter
Bus Bits
Ignored
0000
—
—
DIS – Disabled
0001
16
—
IPWM – Input pulse width measurement
0010
16
—
IPM – Input period measurement
0011
16
—
IC – Input capture
0100
16
—
OCB – Output compare, flag on B compare
0101
16
—
OCAB – Output compare, flag on A and B compare
0110
—
—
Reserved
0111
—
—
Reserved
1000
16
—
OPWM – Output pulse width modulation
1001
15
0
OPWM – Output pulse width modulation
1010
14
0,1
OPWM – Output pulse width modulation
1011
13
0-2
OPWM – Output pulse width modulation
1100
12
0-3
OPWM – Output pulse width modulation
1101
11
0-4
OPWM – Output pulse width modulation
1110
9
0-6
OPWM – Output pulse width modulation
1111
7
0-8
OPWM – Output pulse width modulation
MOTOROLA
15-26
MDASM Mode of Operation
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
15.12 MIOS Pulse Width Modulation Submodule (MPWMSM)
The purpose of the MIOS pulse width modulation submodule (MPWMSM) is to create
a variable pulse width output signal at a wide range of frequencies, independent of
other MIOS1 output signals. The MPWMSM includes its own 8-bit prescaler and
counter and, thus, does not use the MIOS1 16-bit counter buses.
The MPWMSM pulse width can vary from 0.0% to 100.0%, with up to 16 bits of resolution. The finest output resolution is the MCU system clock time divided by two (for a
fSYS of 40.0 MHz, the finest output pulse width resolution is 50 ns). With the full sixteen bits of resolution and the overall prescaler divide ratio varying from divide-by-2 to
divide-by-4096, the period of the PWM output can range from 3.28 ms to 6.7 s (assuming a fSYS of 40 MHz). By reducing the counting value, the output signal period can
be reduced. The period can be as fast as 205 µs (4.882 kHz) with twelve bits of resolution, as fast as 12.8 µs (78.125 kHz) with eight bits of resolution and as fast as 3.2 µs
(312.500 kHz) with six bits of resolution (still assuming a fSYS of 40 MHz and a first
stage prescaler divide-by-2 clock selection).
Refer to Table 15-36 for the MPWMSM relative I/O pin implementation.
PS0 - PS7
8- bit Prescaler
Counter
Clock
FREN
(NCOUNT)
EN
TRSP
16-bit Down Counter
EN
POL
PIN
DDR
Output
Output
Output
Flip-Flop
Buffer
Logic
MPWMC
16-bit
<= Comparator
= 0x0001
Output
Pin
LOAD
Pulse Width Register
PWMB2
PWMB
Next Period Register
MPWMA
Next Pulse Width
Register MPWMB1
FLAG
Request Bus
MIOB
Figure 15-6 MPWMSM Block Diagram
MPC555
USER’S MANUAL
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MOTOROLA
15-27
15.12.1 MIOS Pulse Width Modulation Submodule (MPWMSM) Registers
One set of registers is associated with each MPWMSM submodule. The base address
is given in the table below.
Table 15-19 MPWMSM Address Map
Address
Register
MPWMSM0
0x30 6000
MPWMSM0 Period Register (MPWMSMPERR)
See Table 15-20 for bit descriptions.
0x30 6002
MPWMSM0 Pulse Register (MPWMSMPULR)
See Table 15-21 for bit descriptions.
0x30 6004
MPWMSM0 Count Register (MPWMSMCNTR)
See Table 15-22 for bit descriptions.
0x30 6006
MPWMSM0 Status/Control Register (MPWMSMSCR)
See Table 15-23 for bit descriptions.
MPWMSM1
0x30 6008
MPWMSM1 Period Register (MPWMSMPERR)
0x30 600A
MPWMSM1 Pulse Register (MPWMSMPULR)
0x30 600C
MPWMSM1 Count Register (MPWMSMCNTR)
0x30 600E
MPWMSM1 Status/Control Register (MPWMSMSCR)
MPWMSM2
0x30 6010
MPWMSM2 Period Register (MPWMSMPERR)
0x30 6012
MPWMSM2 Pulse Register (MPWMSMPULR)
0x30 6014
MPWMSM2 Count Register (MPWMSMCNTR)
0x30 6016
MPWMSM2 Status/Control Register (MPWMSMSCR)
0x30 6018
MPWMSM3 Period Register (MPWMSMPERR)
0x30 601A
MPWMSM3 Pulse Register (MPWMSMPULR)
0x30 601C
MPWMSM3 Count Register (MPWMSMCNTR)
0x30 601E
MPWMSM3 Status/Control Register (MPWMSMSCR)
MPWMSM3
MPWMSM16
0x30 6080
MPWMSM16 Period Register (MPWMSMPERR)
0x30 6082
MPWMSM16 Pulse Register (MPWMSMPULR)
0x30 6084
MPWMSM16 Count Register (MPWMSMCNTR)
0x30 6086
MPWMSM16 Status/Control Register (MPWMSMSCR)
MPWMSM17
0x30 6088
MPWMSM17 Period Register (MPWMSMPERR)
0x30 608A
MPWMSM17 Pulse Register (MPWMSMPULR)
0x30 608C
MPWMSM17 Count Register (MPWMSMCNTR)
0x30 608E
MPWMSM17 Status/Control Register (MPWMSMSCR)
MPWMSM18
MOTOROLA
15-28
0x30 6090
MPWMSM18 Period Register (MPWMSMPERR)
0x30 6092
MPWMSM18 Pulse Register (MPWMSMPULR)
0x30 6094
MPWMSM18 Count Register (MPWMSMCNTR)
0x30 6096
MPWMSM18 Status/Control Register (MPWMSMSCR)
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
MPC555
USER’S MANUAL
Table 15-19 MPWMSM Address Map (Continued)
Address
Register
MPWMSM19
0x30 6098
MPWMSM19 Period Register (MPWMSMPERR)
0x30 609A
MPWMSM19 Pulse Register (MPWMSMPULR)
0x30 609C
MPWMSM19 Count Register (MPWMSMCNTR)
0x30 609E
MPWMSM19 Status/Control Register (MPWMSMSCR)
15.12.1.1 MPWMSM Period Register (MPWMSMPERR)
The period register contains the binary value corresponding to the period to be
generated.
MPWMSMPERR — MPWMSM Period Register
MSB
0
1
2
3
4
5
6
7
0x30 6000*
8
9
10
11
12
13
14
LSB
15
U
U
U
U
U
U
U
U
PER
RESET:
U
U
U
U
U
U
U
U
* Refer to Table 15-19 for a complete list of all the base addresses for the MPWMSM registers.
Table 15-20 MPWMSMPERR Bit Settings
Bit(s)
Name
0:15
PER
Description
Period. These bits contain the binary value corresponding to the period to be generated.
15.12.1.2 MPWMSM Pulse Width Register (MPWMSMPULR)
This register contains the binary value of the pulse width to be generated.
MPWMSMPULR — MPWMSM Pulse Width Register
MSB
0
1
2
3
4
5
6
7
0x30 6002*
8
9
10
11
12
13
14
LSB
15
U
U
U
U
U
U
U
U
PUL
RESET:
U
U
U
U
U
U
U
U
* Refer to Table 15-19 for a complete list of all the base addresses for the MPWMSM registers.
Table 15-21 MPWMSMPULR Bit Settings
Bit(s)
Name
0:15
PUL
MPC555
USER’S MANUAL
Description
Pulse width. These bits contain the binary value of the pulse width to be generated.
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
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15.12.1.3 MPWMSM Counter Register (MPWMSMCNTR)
This register reflects the actual value of the MPWMSM counter.
MPWMSMCNTR — MPWMSM Counter Register
MSB
0
1
2
3
4
5
6
7
0x30 6004*
8
9
10
11
12
13
14
LSB
15
U
U
U
U
U
U
U
U
CNT
RESET:
U
U
U
U
U
U
U
U
* Refer to Table 15-19 for a complete list of all the base addresses for the MPWMSM registers. A write to the
MPWMSMCNTR register also writes the same value to MPWMSMPERR.
Table 15-22 MPWMSMCNTR Bit Settings
Bit(s)
Name
0:15
CNT
Description
Counter. These bits reflect the actual value of the MPWMSM counter.
15.12.1.4 MPWMSM Status/Control Register(MPWMSMCR)
This register contains read-only status bits and read/write control bits.
MPWMSMSCR — MPWMSM Status/Control Register
MSB
0
1
PIN
DDR
2
3
FREN TRSP
4
5
POL
EN
0
0
6
7
8
9
0x30 6006*
10
11
RESERVED
12
13
14
LSB
15
U
U
U
U
CP
RESET:
—
0
0
0
0
0
U
U
U
U
* Refer to Table 15-19 for a complete list of all the base addresses for the MPWMSM registers.
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MPC555
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Table 15-23 MPWMSMSCR Bit Settings
Bit(s)
Name
0
PIN
Description
Pin input status. The PIN bit reflects the state present on the MPWMSM pin. The software can
thus monitor the signal on the pin.
The PIN bit is a read-only bit. Writing to the PIN bit has no effect.
Data direction register. The DDR bit indicates the direction for the pin when the PWM function is
not used (disable mode). Note that when the PWM function is used, the DDR bit has no effect.
1
DDR
2
FREN
3
TRSP
4
POL
5
EN
6:7
—
8:15
CP
Table 15-24 lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data
direction register (DDR) bit.
0 = Pin is in input.
1 = Pin is in output.
Freeze enable. This active high read/write control bit enables the MPWMSM to recognize the
freeze signal on the MIOB.
0 = MPWMSM not frozen even if the MIOB freeze line is active.
1 = MPWMSM frozen if the MIOB freeze line is active.
Transparent mode. The TRSP bit indicates that the MPWMSM double buffers are transparent:
when the software writes to either the MPWMA or MPWMB1 register the value written is immediately transferred to respectively the counter or register MPWMB2.
0 = Transparent mode de-activated.
1 = Transparent mode activated.
Output polarity control. The POL bit works in conjunction with the EN bit and controls whether
the MPWMSM drives the pin with the true or the inverted value of the output flip-flop
Table 15-24 lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data
direction register (DDR) bit.
Enable PWM signal generation. The EN bit defines whether the MPWMSM generates a PWM
signal or is used as an I/O channel:
Table 15-24 lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data
direction register (DDR) bit.
0 = PWM generation disabled (pin can be used as I/O).
1 = PWM generation enabled (pin is output only).
Reserved
Clock Prescaler. This 8-bit read/write register stores the two’s complement of the desired modulus value for loading into the built-in 8-bit clock prescaler. The value loaded defines the divide
ratio for the signal that clocks the MPWMSM period counter. Table 15-15 gives the clock divide
ratio according to the CP values.
Table 15-24 PWMSM Output Pin Polarity Selection
Control Bits
POL
EN
DDR
Pin Direction
(I/O)
0
0
0
I
Low
—
—
—
0
0
1
O
Always Low
—
—
—
0
1
—
O
High Pulse
Rising Edge
Falling Edge
Rising Edge
1
0
0
I
High
—
—
—
1
0
1
O
Always High
—
—
—
1
1
—
O
Low Pulse
Falling Edge
Rising Edge
Falling Edge
MPC555
USER’S MANUAL
Pin State
Periodic
Edge
Variable
Edge
Optional
Interrupt On
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Revised 1 March 1999
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15.13 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM)
An MIOS 16-bit parallel port I/O submodule (MPIOSM) can handle up to 16 input/output pins. Its control register is composed of two 16-bit registers: the data register (DR)
and the data direction register (DDR). Each pin of the MPIOSM may be programmed
as an input or an output under software control. The direction of a pin is determined by
the state of the corresponding bit in the DDR.
DATA
DIRECTION
REGISTER
MIOB
DATA
REGISTER
I/O
PIN
Output
Driver
Input
Figure 15-7 MPIOSM One-Bit Block Diagram
Refer to Table 15-36 for the MPIOSM relative I/O pin implementation.
15.13.1 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM) Registers
One set of registers is associated with the MPIOSM submodule. The base addresses
of the submodules are given in the table below.
Table 15-25 MPIOSM Address Map
Address
Register
0x30 6100
MPIOSM Data Register (MPIOSMDR)
See Table 15-26 for bit descriptions.
0x30 6102
MPIOSM Data Direction Register (MPIOSMDDR)
See Table 15-27 for bit descriptions.
0x30 6104
Reserved
0x30 6106
Reserved
15.13.1.1 MPIOSM Data Register (MPIOSMDR)
This read/write register defines the value to be driven to the pad in output mode, for
each implemented I/O pin of the MPIOSM.
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MPIOSMDR — MPIOSM Data Register
0x30 6100
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
RESET:
U
Table 15-26 MPIOSMDR Bit Settings
Bit(s)
0:15
Name
Description
D[15:0]
Data BITS. These bits are read/write data bits that define the value to be driven to the pad in output mode for each implemented I/O pin of the MPIOSM. While in output mode, a read returns the
value of the pad. Note that, when little-endian bit ordering is used, bit 0 corresponds to D15 and
bit 15 corresponds to D0.
NOTE
D[0:4] controls the signals MPIO32B[0:4]. These functions are
shared on the MPC555 pins VF[0:2]/MPIO32B[0:2] VFLS[0:1]/
MPIO32B[3:4] and can be configured as the alternate function
(VF[0:2] and VFLS[0:1]). See 15.8.1.1 MIOS1 Test and Pin Control
Register.
15.13.1.2 MPIOSM Data Direction Register (MPIOSMDDR)
This read/write register defines the data direction for each implemented I/O pin of the
MPIOSM.
MPIOSMDDR — MPIOSM Data Direction Register
MSB
0
1
2
3
4
DDR15 DDR14 DDR13 DDR12 DDR11
0x30 6102
5
6
7
8
9
10
11
12
13
14
LSB
15
DDR10
DDR9
DDR8
DDR7
DDR6
DDR5
DDR4
DDR3
DDR2
DDR1
DDR0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
Table 15-27 MPIOSMDDR Bit Settings
Bit(s)
0:15
Name
Description
Data direction. These bits are read/write data bits that define the data direction status for each
implemented I/O pin of the MPIOSM. Note that, when little-endian bit ordering is used, bit 0 corDDR[15:0] responds to D15 and bit 15 corresponds to D0.
0 = Corresponding pin is input.
1 = Corresponding pin is output.
15.14 MIOS1 Interrupts
The MIOS1 and its submodules are capable of generating interrupts to be transmitted
to the CPU via the IMB3. Inside the MIOS1, all the information required for requesting
and servicing the interrupts are treated in two different blocks:
• The interrupt control section (ICS)
• The MIOS interrupt request submodules (MIRSM).
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The MIOS interrupt request submodule gathers service request flags from each group
of up to 16 submodules and transfers those requests to the MIOS1 interrupt control
section (ICS). Figure 15-8 shows a block diagram of the interrupt architecture.
Submodule 13
Submodule 2
(Flags)
Status Register
Enable Register
Level n
IRQ Level Register
Request
IRQ Pend. Register
Acknowledge
RQSM #0
RQSM #1
Submodules 16 to 23
Interrupt Control Section
MBISM
IMB3
Figure 15-8 MIOS Interrupt Structure
15.14.1 MIOS Interrupt Request Submodule (MIRSM)
Each submodule that is capable of generating an interrupt can assert a flag line when
an event occurs. In the MIOS1 configuration, there are eighteen flag lines and two
MIRSMs are needed.
Within the MIOS1, each MIRSM includes:
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• One 16-bit status register (for the flags)
• One 16-bit enable register
• One 16-bit IRQ pending register
One bit position in each of the above registers is associated with one submodule. Note
that if a submodule in a group of 16 cannot generate interrupts, then its corresponding
flag bit in the status register is inactive and reads as zero.
When an event occurs in a submodule that activates a flag line, the corresponding flag
bit in the status register is set. The status register is read/write, but a flag bit can be
reset only if it has previously been read as a one. Writing a one to a flag bit has no
effect. When the software intends to clear only one flag bit within a status register, the
software must write an 16-bit value of all ones except for a zero in the bit position to
be cleared.
The enable register is initialized by the software to indicate whether each interrupt
request is enabled for the level defined in the ICS.
Each bit in the IRQ pending register is the result of a logical “AND” between the corresponding bits in the status and in the enable registers. If a flag bit is set and the level
enable bit is also set, then the IRQ pending bit is set and the information is transferred
to the interrupt control section that is in charge of sending the corresponding level to
the CPU. The IRQ pending register is read only.
NOTE
When the enable bit is not set for a particular submodule, the corresponding status register bit is still set when the corresponding flag is
set. This allows the traditional software approach of polling the flag
bits to see which ones are set. The status register makes flag polling
easy, since up to sixteen flag bits are contained in one register.
The submodule number of an interrupting source defines the corresponding MIRSM
number and the bit position in the status registers. To find the MIRSM number and bit
position of an interrupting source, divide the interrupting submodule number by 16.
The integer result of the division gives the MIRSM number. The remainder of the division gives the bit pos">