NXP MC68302 Integrated Multi-Protocol Processor Reference Manual

Freescale Semiconductor, Inc.
GENERAL INFORMATION
CHAPTER 1 - GENERAL INFORMATION
1•1
INTRODUCTION
This manual provides general information, preparation for use, installation and operating instructions,
functional description, and support information for the M68302FADS Application Development System
board.
1•2
GENERAL FEATURES
Freescale Semiconductor, Inc...
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A complete system development board for 3 processors. The MC68302, MC68LC302 and
MC68PM302.
Expansion connectors providing all 302 processor signals.
Logic analyzer connectors similar to the expansion connectors.
Single 5V supply.
MC68302 core running at 25MHz.
MC68LC302 core running at 20MHz.
MC68302 core running at 20MHz.
512K byte, zero wait state static RAM, expandable up to 1M byte. (16 bit orientation)
1M byte FLASH. (16 bit orientation)
2K byte EEPROM. (8 bit orientation)
Application Development Interface (ADI) port connector.
MC68681 DUART, with wo RS232 serial ports.
RESET and ABORT controls.
RUN and HALT status indicators. (LED’s).
Supports PCMCIA card standard 2.01. (For the MC68PM302)
Board power can be controlled from the PCMCIA connector of an host PC. (Important when the
ADS is used for developing a PCMCIA applications)
An extender board for plugging into PCMCIA port is supplied with the M68302FADS ADS board.
Bus expansion connector pin out, is compatible with the 302ADS.
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GENERAL INFORMATION
1•3
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SPECIFICATIONS
The M68302FADS specifications and cooling requirements are given in Table 1-1.
Table 1-1 M68302FADS Specifications
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CHARACTERISTICS
SPECIFICATIONS
Power requirements (no other boards attached)
+5Vdc @ 0.8 A (typical), 3.15 A (maximum)
Microprocessor
MC68302, MC68LC302, MC68PM302
- MC68302 @ 25 MHz
- MC68LC302 @ 20 MHz
- MC68PM302 @ 20 MHz
302 processor addressing
Total address range.
SRAM
FLASH memory
EEPROM
16M byte (4Mb external, for the LC302 and Pchip).
512K byte, 16 bit wide. (Expandable to 1M bytes)
1M byte, 16 bits wide.
2K byte, 8 bit wide.
Operating temperature
0 degrees to 30 degrees C ambient air temperature
Storage temperature
-25 degrees to 85 degrees C
Relative humidity
5% to 90% (non-condensing)
Dimensions
Height
Depth
Thickness
9.196 inches (233.58 mm)
8.387 inches (213.03 mm)
0.063 inches (1.6 mm)
1•4
COOLING REQUIREMENTS
The M68302FADS is specified designed, and tested to operate reliably with ambient air temperature range
from 0 to 70 degrees C. Dynamic Burn-in is performed while the board is table mounted with no other
boards attached to it. Test software is executed as the board is subjected to temperature variations. If the
board is attached to other boards, the thermal conditions may worsen and it is recommended that
operating temperature should not exceed 30 degrees C.
2
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1•5
GENERAL INFORMATION
GENERAL DESCRIPTION
The M68302FADS is a development tool for the MC68302, MC68LC302 and MC68PM302 devices. This
board is used for hardware and software development of applications using any member of the 302 family.
The M68302FADS has logic analyzer connectors as well as expansion connectors, providing physical
connection to all processors‘ pins. The logic analyzer connectors, enable to monitor bus activity, by
providing a direct connection to HP or other logic analyzers. The expansion connectors let the user, to
attach hardware applications and to use board resources, to verify the design.
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1•6
RELATED DOCUMENTATION
The following publications are applicable to the M68302FADS and may provide additional helpful
information.
• MC68302 IMP User’s Manual.
• MC68LC302 IMP User’s Manual.
• MC68PM302 IMP User’s Manual.
• PCMCIA specifications paper
1•7
ABBREVIATIONS USED IN THE DOCUMENT
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1•8
IMP - The MC68302 integrated communication processor.
LC302 or LCIMP - A low cost version of the MC68302 integrated communication processor.
PM302 or Pchip - MC68302 integrated with a PCMCIA card interface.
302 processor - Any of the IMP, LC302 and PM302.
ADS - Application Development System for the 302 family processor.
ADI - Application Development Interface.
UART - Universal Asynchronous Receiver/Transmitter.
spec - Engineering specification document.
nsec - nano second.
µsec - micro second.
NMI - Non Maskable Interrupt.
REQUIRED EQUIPMENT
The M68302FADS can be operated in two working environments:
• Host controlled
•
Stand-alone
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GENERAL INFORMATION
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FIGURE 1-1 describes the setup of an host controlled mode.
The required equipment in this mode is as follows:
• +5V/3A power supply.
• Host Computer, one of the following:
o Sun - 4 (Sbus interface)
o IBM-PC/XT/AT
• ADI board - compatible with the host computer.
• 37 line flat cable with female 37 pin D-type connectors on each end.
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FIGURE 1-1 Host Controlled Configuration
ADI cable
P1
M68302FADS
P10
5V supply
1•8•1
Running the debugger
When the board is connected as shown in FIGURE 1-1, turn on the 5V power supply and run the host
software, by typing:
host <ADI sbus slot No.> <ADS ADI address>
The manufacturer settings for ADS ADI address is 0. For more details on ADI addresses setting, please
see section 2•3•2.
For example, to run the host on a sun machine with an ADI card installed in its Sbus slot number 1 and
with ADS ADI address, set to 3, you should type, at command line prompt:
host 1 3
4
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GENERAL INFORMATION
The prompt you get, depends on the processor installed, as listed in the following table
Table 1-2 Debugger prompt
Processor
MC68302
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MC68LC302
MC68PM302
Prompt
IMP Monitor/Debugger - Version 0.0
(C) Copyright 1995 by Motorola Inc.
Cold Start
IMPbug>
LC302 Monitor/Debugger - Version 0.0
(C) Copyright 1995 by Motorola Inc.
Cold Start
LC302bug>
PCHIP Monitor/Debugger - Version 0.0
(C) Copyright 1995 by Motorola Inc.
Cold Start
PCHIPbug>
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GENERAL INFORMATION
1•8•2
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Stand alone setup
FIGURE 1-2 describes the setup of a stand-alone operating mode.
The required equipment in this mode is:
• +5V/3A power supply.
• VT100 compatible terminal.
• RS-232 cable with male 9 pin D-type connector on the ADS side.
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FIGURE 1-2 Stand-alone Configuration
RS232 cable
P2
M68302FADS
P10
5V supply
1•8•2•1
Terminal settings
The terminal connected to a M68302FASDS board, should be initialized to work with the following settings:
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Speed - 9600 bps.
Character size - 8 bits.
Stop bit length - 1 bit. (1.5 or 2 is fine but 1 is preferred for being a bit faster)
No parity.
These settings are written shortly as - 9600, 8, 1 N.
After setting the terminal as specified and turning on the power, a debugger prompt as in Table 1-2, should
appear on terminal screen.
6
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1•8•2•2
GENERAL INFORMATION
Parallel ADI / Serial port, priority.
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There is no control on board, to select between the parallel ADI or the serial port communication. The
debugger decides automatically, with which it should communicate, by giving a priority to the serial port, in
case, a terminal is detected. The serial port has some signals, by with the debugger can detect the
presence of a terminal. If it is present, then the ADI connection is ignored and all board communication,
goes to the serial port. When a terminal is not detected on the serial port, all communication, goes to the
ADI port.
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GENERAL INFORMATION
8
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HARDWARE PREPERATION AND INSTALLATION
CHAPTER 2 - HARDWARE PREPERATION AND INSTALLATION
2•1
INTRODUCTION
This chapter provides unpacking instructions, hardware preparation, and installation instructions for the
M68302FADS.
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2•2
UNPACKING INSTRUCTIONS
NOTE
If the shipping carton is damaged upon receipt,
request carrier’s agent be present during
unpacking and inspection of equipment.
Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save
packing material for storing and reshipping of equipment.
CAUTION
AVOID TOUCHING AREAS OF INTEGRATED
CIRCUITRY;
STATIC
DISCHARGE
CAN
DAMAGE CIRCUITS.
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HARDWARE PREPERATION AND INSTALLATION
2•3
HARDWARE PREPARATION
To select the desired configuration and ensure proper operation of the M68302FADS board, changes of
the Dip-Switch/Jumpers settings may be required before installation. Switches, LEDs, Dip-Switches, and
connectors are illustrated in FIGURE 1-3 M68302FADS Location diagram on page 11. The board has been
factory tested and is shipped with Dip-Switch settings as described in the following paragraphs.
Parameters can be changed for the following conditions:
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- On board resources enable (SRAM, Flash, EEPROM, ADI port and DUART)
- Bus width.
- PLL ON/OFF.
- Processor type selection.
- ADI port address selection.
- Pchip PCMCIA enable.
- Pchip PCMCIA block power source.
10
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P8
P7
P6
P9
GND
HOOK
CONTROL
DATA
ADDR HIGH
ADDR LOW
U5
U4
RN3
ADI PORT
A
B
C
D
E
F
G
H
J
K
L
M
N
RN4
U13
U12
U11
U10
1 2 3 4 5 6 7 8 9 10 11 12 13
U9
U8
U7
U6
A
B
C
D
E
F
G
H
J
K
L
M
N
U16
U15
U20
U21
U22
U17
U18
U19
TERMINAL
F1
C1
+
J1
Y1
+5V GND
P10
LC302 PLL
OFF ON
U23
1 2 3 4 5 6 7 8 9 10 11 12 13
U14
P2
RLY1
D1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
RN5
HOST
U25
U24
U26
OFF
ON
Pchip PLL
INT
P12
PC
J3
PCMCIA PWR
P11
J2
U27
P4
LD1
U33
U32
U31
U34
RN7
C2
U36
U35
+
U38
U37
U39
SW2
SW1
RN8
GND HOOK
Y2
D2
DS2
DS1
LD4
RESET
ABORT
CHIPTYPE
IOIS16
MODCLK
BUSW
PCEN
PCVCCEN
RAMEN
FLASHEN
EEPROMEN
ADIEN
DUARTEN
ADSA0
ADSA1
ADSA2
PCOFF POWER
LD3
RN6
HALT
LD2
U30
U29
U28
PCMCIA
RUN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P3
+
P5
U2
U3
RN2
U1
RN1
P1
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HARDWARE PREPERATION AND INSTALLATION
FIGURE 1-3 M68302FADS Location diagram
+
11
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HARDWARE PREPERATION AND INSTALLATION
2•3•1
DS1 DIP switch configuration.
FIGURE 1-4 Dip-Switch DS1
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OFF
DS1
ON
1
PCEN
2
PCVCCEN
3
RAMEN
4
FLSHEN
5
EEPREN
6
ADIEN
7
DUARTEN
8
ADSA0
9
ADSA1
10
ADSA2
Table 1-3 describes the function of switches 1 - 7.
Table 1-3 Dip-Switch DS1 Description
Switch
Name
1
PCEN
2
PCVCCEN
3
12
Function
Default
setting
Direct control over the Pchip signal PCEN. When set to On, the
internal Pchip PCMCIA interface is disabled.
ON
When set to ON, the board is powered unconditionally, with respect to
PCMCIA host power. When set to OFF, the board is powered, only when
the host connected to the board through the PCMCIA port, is turned on.
ON
RAMEN
When set to ON, on board SRAM is enabled. (1Mbyte space)
ON
4
FLSHEN
When set to ON, on board FLASH memory is enabled.
ON
5
EEPREN
When set to ON, on board EEPROM is enabled.
ON
6
ADIEN
When set to ON, ADI interface is enabled.
ON
7
DUARTEN
When set to ON, DUART MC68681 along with its RS232 port
are enabled.
ON
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HARDWARE PREPERATION AND INSTALLATION
2•3•2
ADI Port Address Selection (Dip-Switch DS1 switches 8-10)
Each M68302FADS can have eight possible ADI port addresses, enabling up to eight M68302FADS
boards to be connected to the same ADI card in a host computer. Address selection is done by setting
switches 8, 9, 10 in DS1 Dip-Switch. Switch 10 is the most significant bit of the address while switch 8 is
the least. A switch set to its ’ON’ state, stands for logical ’0’. The default setting is ADI address - 7.
Table 2-1 describes the switch settings for each slave address:
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Table 2-1 ADI Address Selection
ADDRESS
Switch 10
Switch 9
Switch 8
0
ON
ON
ON
1
ON
ON
OFF
2
ON
OFF
ON
3
ON
OFF
OFF
4
OFF
ON
ON
5
OFF
ON
OFF
6
OFF
OFF
ON
7
OFF
OFF
OFF
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HARDWARE PREPERATION AND INSTALLATION
2•3•3
DS2 DIP switch configuration (for LC302/PM302).
FIGURE 1-5 Dip-Switch DS2
OFF
DS2
ON
1
IOIS16
2
MODCLK
3
BUSW
4
5
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6
7
8
9
10
CHIPTYPE
Table 2-2 Dip-Switch DS2 description.
Switch
Name
Function
Default
1
IOIS16
Set IOIS16 PCMCIA signal level. IOIS16, is not supported
by the Pchip.
When set to on, PCMCIA I/O transfers are 8 bits width.
When set to off,
PCMCIA I/O transfers, are 16 bits width.
ON
2
MODCLK
Select PLL multiplication factor when PLL is enabled. (See
J1, J2 jumpers) ON - selects x4 multiplication factor and
OFF - selects x401 for 32KHz crystal.
ON
3
BUSW
Controls BUSW input of the processor. Selects 16 bit bus
when OFF and 8 bit bus width when set to ON.
OFF
10
CHIPTYPE
Selects between IMP and LC302/Pchip mode. ON - IMP,
OFF - LC302 and Pchip.
ON = IMP
OFF = LC302/PM302 (*)
* FIGURE 1-5, shows default settings for the LC302 and PM302. When the IMP is
plugged in, switch 10 should be set to ON. All other switches are the same as
for the LC302/PM302.
14
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HARDWARE PREPERATION AND INSTALLATION
2•4
INSTALLATION INSTRUCTIONS
When the M68302FADS has been configured as desired by the user, it can be installed according to the
required working environment as follows:
2•4•1
+5V Power Supply Connection
The M68302FADS requires +5Vdc @ 1A max, power supply for operation. The ADS has 3.15A fuses on
the +5V line, and it is protected against reverse connection of the power supply. Connect the +5V power
supply to connector P10 as shown below:
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FIGURE 1-6 P18: +5V Power Connector
VCC
1
Gnd
2
Gnd
3
P10 is a 3 terminal block power connector with power plug. The plug is designed to accept 14 to 22 AWG
wires. It is recommended to use 14 to 18 AWG wires. To insure solid ground, two Gnd terminals are
supplied. It is recommended to connect both Gnd wires to the common of the power supply, while VCC is
connected with a single wire.
NOTE
Since hardware applications can be connected to the
M68302FADS using the expansion connectors P9 and P12,
the additional power consumption should be taken into
consideration when a power supply is connected to the ADS.
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HARDWARE PREPERATION AND INSTALLATION
2•4•2
ADI Installation
For ADI installation on various host computers, refer to APPENDIX A - ADI BOARD INSTALLATION on
page 50.
2•4•3
Host computer to ADS connection
The M68302FADS ADI interface connector, P1, is a 37 pin, male, D type connector. The connection
between the M68302FADS and the host computer is made by a 37 line flat cable, supplied with the ADI
board. FIGURE 1-7 below shows the connector pin arrangement of the connector.
FIGURE 1-7 ADI Port Connector P1
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Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
(+ 12 v) N.C.
HOST_VCC
HOST_VCC
HOST_VCC
HOST_ENABLE~
Gnd
Gnd
Gnd
PD0
PD2
PD4
PD6
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
INT_ACK
N.C.
HST_ACK
ADS_ALL
ADS_RESET
ADS_SEL2
ADS_SEL1
ADS_SEL0
HOST_REQ
ADS_REQ
ADS_ACK
ADS_INT
HOST_BRK~
ADS_BRK
N.C.
PD1
PD3
PD5
PD7
NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the ADS.
2•4•4
Terminal to M68302FADS RS-232 Connection. (DCE port)
In a stand-alone operation mode, a VT100 compatible terminal should be connected to the RS-232
connector P2. The RS-232 connector is a 9 pin, female, D-type connector as shown in FIGURE 1-8.
FIGURE 1-8 RS-232 Serial Port Connector P2
CD
TX
1
2
RX
DTR
3
4
5
GND
6
7
8
9
DSR
RTS
CTS
N.C.
NOTE: The RTS line (pin 7) is not connected in the M68302FADS.
16
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2•4•5
Secondary RS-232 port. (DTE port)
The second RS232 port, is controlled, is not supported by the debugger. The user should write his own
drivers to use this port. The connector pin out is shown in FIGURE 1-8.
FIGURE 1-9 RS-232 Serial Port Connector P3
TX
1
2
RX
DTR
3
4
5
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GND
6
7
8
9
DSR
RTS
CTS
N.C.
NOTE: The CTS line (pin 8) is not connected in the M68302FADS.
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OPERATING INSTRUCTIONS
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CHAPTER 3 - OPERATING INSTRUCTIONS
3•1
INTRODUCTION
This chapter provides necessary information to use the M68302FADS in host-controlled and in a standalone configuration. This includes controls, indicators, memory map details, and software initialization of
the board.
3•2
CONTROLS AND INDICATORS
The M68302FADS has the following switches and indicators.
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3•2•1
NMI (Abort) Switch SW1
The NMI switch SW2 asserts level 7 interrupt to the processor. The switch signal is debounced, and It is
not possible to disable it by software. The NMI (Abort) switch is normally used to abort program execution
and return the debugger control.
3•2•2
RESET Switch SW2
The RESET switch SW2, resets all ADS devices and performs reset to the 302 processor. The switch
signal is debounced, and it is not possible to disable it by software.
3•2•3
LC302 PLL enable jumper - J1.
The PLL of the LC302, is controlled by applying or preventing PLL block power, on the VCCSYN pin. The
selection, is done with J1 jumper, as shown in FIGURE 1-10.
FIGURE 1-10 LC302 PLL enable jumper (J1)
LC302 PLL
LC302 PLL - Disabled
ON
When the jumper is installed on pins 2 - 3,
LC302 PLL is disabled. This actually shorts the
LC302 VCCSYN pin, to ground.
1
LC302 PLL
LC302 PLL enabled
ON
When the jumper is installed on pins 1 - 2, the
LC302 PLL is enabled. This actually connects
VCCSYN pin of the LC302 to VCC.
18
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3•2•4
OPERATING INSTRUCTIONS
Pchip PLL enable jumper - J2.
The PLL of the Pchip, is controlled by applying or preventing PLL block power, on the VCCSYN pin. The
selection, is done with J2 jumper, as shown in FIGURE 1-10.
FIGURE 1-11 Pchip PLL enable jumper (J2)
Pchip PLL
Pchip PLL - Disabled
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When the jumper is installed on pins 2 - 3, the
Pchip PLL is disabled. This actually shorts the
Pchip VCCSYN pin, to ground.
ON
OFF
1
Pchip PLL
Pchip PLL enabled
ON
OFF
When the jumper is installed between pins 1 - 2,
the Pchip PLL is enabled. This actually connects
VCCSYN pin of the Pchip to VCC.
3•2•5
PCMCIA power source selection - J3.
The PCMCIA block in the Pchip, can be powered by one of two sources. The first is the board common
VCC supply and the second is an external power, supplied through a PC host, plugged into the PCMCIA
connector. The selection, is done with J3 jumper, as shown in FIGURE 1-12.
FIGURE 1-12 Pchip PLL enable jumper (J3)
Pchip PCMCIA block is powered by a host PC
When the jumper is installed on pins 2 - 3, the
Pchip PCMCIA block, get its power from a host
PC, connected to PCMCIA connector - P4.
Pchip PCMCIA block is powered by board supply board
PCMCIA PWR
INT
PC
1
PCMCIA PWR
INT
PC
When the jumper is installed on pins 1 - 2, the
Pchip PCMCIA block, get its power from the
board common supply.
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OPERATING INSTRUCTIONS
3•2•6
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RUN indicator LD1
This yellow indicator is connected to the 302 processor address strobe (AS~) signal. It lit when AS~ is low
(asserted) to indicate a bus activity.
3•2•7
HALT indicator LD2
This red indicator, lit whenever the 302 processor HALT~ pin is low (asserted).
3•2•8
PCOFF indicator LD3
This orange indicator, lit when PCMCIA power control is selected by the DIP-Switch DS1 switch 2
(PCVCCON set to the OFF position) and no external power is detected on the PCMCIA connector - P4.
This is a reminder to the user, that the board is not powered, despite power existence, on P10 connector.
The board would be powered, upon detection of a turned on PC, on the PCMCIA connector - P4.
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3•2•9
Power indicator LD4
This green indicator, lit when the board is powered. Please be aware that suppling 5V to P10 connector
does not assure it is powered. When DIP switch DS2 switch number 2, is set to its off position, board power,
is PCMCIA power dependent. The on board relay switches the power off, unless a 5V power is detected
on the PCMCIA port. When DIP switch DS2 switch number 2, is set to its on position, the board is powered
when 5V is supplied trough P10, unconditionally of PCMCIA port status.
20
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3•3
OPERATING INSTRUCTIONS
IMP MEMORY MAP
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FIGURE 1-13 IMP memory map on page 21, is one of two maps. After a cold or warm reset, the 302
processor’s CS0, is automatically enabled for the first block of 8K bytes. In this page the 302 processor
sees the first 8K bytes of the 1M bytes FLASH memory installed. No other space than those 8K, is
available this time. At this point, the stack pointer and the program counter are fetched from Flash and the
debugger starts. One of the debugger first tasks, is to enable the map shown in FIGURE 1-13. It is done
by copying the code for the swap task, into the 302 processor’s dual port Ram and jump to execute the
code. The code redefines CS0, CS1 and CS2 to enable the map shown in FIGURE 1-13 and goes back to
the debugger which has been moved due to the new map, to offset 20000H. The swap task is executed
from the dual port RAM, so it would not be interrupted by the swap. The swap is done, in order to map a
RAM at the 302 processor vector table (start at $0), so the user would be able to change those vectors.
(and not a FLASH at $0 - a must after reset)
FIGURE 1-13 IMP memory map
D15
D8
D7
D0
FFFFFF
FFFFFE
Reserved for MC68302 internal
space and user applications.
700001
6FFFFF
700000
6FFFFE
610000
600000
5FFFFE
ADI handshake
MC68681 DUART
2K byte EEPROM
ADI port data
500000
4FFFFE
630001
620001
610001
600001
5FFFFF
510001
500001
4FFFFF
410001
400000
3FFFFE
400001
3FFFFF
300000
2FFFFE
300001
2FFFFF
1M byte FLASH memory*
200000
1FFFFE
200001
1FFFFF
100000
0FFFFE
080000
07FFFE
000000
100001
0FFFFF
080001
07FFFF
000001
512K byte static RAM expansion memory
512K byte static RAM base memory*
*Note: The debugger uses 0-7FFF in the Static RAM
and from 200000 to 21FFFF in the Dynamic RAM.
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Each board comes with 1M byte of Flash memory (oriented as 512K words of 16 bits each) and a 512K
bytes of static RAM (oriented as 256K words 16 bits each). The RAM can be expanded, on board to a total
of 1M bytes. ADI logic, DUART MC68681 and 2K byte EEPROM, occupies each 64K byte which is the
minimum division available, by on board chip select logic. Each empty space in the map, is considered
available for the user. Any of the on board resources, can be disabled, to free its memory allocation for the
user. Please see Table 1-3 Dip-Switch DS1 Description on page 12.
3•3•1
DUART MC68681 registers.
Table 2-3, shows the MC68681 internal registers. This is an eight bit device, connected to D0-D7 and thus
located on odd addresses.
Freescale Semiconductor, Inc...
Table 2-3 MC68681 internal registers
Register
address
$620001
$620003
$620005
$620007
$620009
$62000B
$62000D
$62000F
$620011
$620013
$620015
$620017
$620019
$62001B
$62001D
$62001F
Read (R/W~ = 1)
Mode register A (MR1A, MR2A)
Status register A (SRA)
Do not access *
Receiver buffer A (RBA)
Input port change register (IPCR)
Interrupt status register (ISR)
Counter mode: Current MSB of counter
(CUR)
Counter mode: Current LSB of counter (CLR)
Mode register B (MR1B, MR2B)
Status register B (SRB)
Do not access *
Receiver buffer B (RBB)
Interrupt vector register (IVR)
Input port (unlatched)
Start counter command **
Stop counter command **
Write (R/W~ = 0)
Mode register A (MR1A, MR2A)
Clock select register A (CSRA)
Command register A (CRA)
Transmitter buffer A (TBA)
Auxiliary control register (ACR)
Interrupt mask register (IMR)
Counter/Timer upper register (CTUR)
Counter/Timer lower register (CTLR)
Mode register B (MR1B, MR2B)
Clock select register B (CSRB)
Command register B (CRB)
Transmitter buffer B (TBB)
Interrupt vector register (IVR)
Output port configuration register (OPCR)
Output port register (OPR) bit set command
Output port register (OPR) bit reset command
* This address is used for factory testing and should not be accessed by the user.
** A trigger command.
For more details about the MC68681 DUART, please refer to M68000 family reference.
22
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3•3•2
OPERATING INSTRUCTIONS
ADI handshake signals
ADI handshake signals consist of in and out, going signals. In going signals can be read from the MC68681
DUART input port found in address $62001B or from the ADI input port located at address $600000. The
second is preferred due to the user ability to map the DUART off. The outgoing signals of the ADI interface
are found in the DUART output port latch. In order to let the ADI port, be functional, when the DUART is
disabled, all DUART register involved with the ADI outgoing handshake signals, were logically duplicated
into the ADI space. So now, the outgoing signals, can be accessed trough two base addresses. The
DUART as well as the ADI. Of course the second is preferred from the same reason explained above.
The following tables shows relevant ADI registers as well as the internal bit map of each register.
Table 2-4 ADI registers.
Freescale Semiconductor, Inc...
Address
$600000
$60001B
$60001D
$60001F
Read (R/W~ = 1)
Write (R/W~ = 0)
ADI input port
DUART input port
Do not access
Do not access
Do not access
DUART output port configuration register (OPCR)
DUART output port (OPR) bit set command
DUART output port (OPR) bit reset command
To set a DUART output bit, a "1", should be written to the desired bit of the DUART OPR reset command
register. To reset a DUART output bit, a "1", should be written into the DUART OPR set command register.
Table 2-5 DUART output port bit set/reset map @$60001D/@$60001F
7
ADS ACK
6
5
CTS, DSR & CD
to the terminal.
N.C.
4
3
EEPROM
wr enable
ADS INT
2
1
0
ADS REQ
Not used
Int mode
Table 2-6 DUART input port bit map @$60001B
5
4
3
DTR from terminal.
Read as’0’
INT ACK
2
1
HST_EN~
HST REQ
0
HST ACK
Table 2-7 ADI input port bit map @600000
7
6
5
Read as’0’
Read as’0’
Read as’0’
4
INT ACK
3
HST ACK
2
HST REQ
1
ADS BRK
0
ADS_SEL~
ADS_SEL~ signal, is not a member in the ADI protocol, but is a signal, generated on board, to report, the
ADS, is selected by the host. For more details on the ADI protocol, please refer to APPENDIX B - ADI
PORT HANDSHAKE DESCRIPTION on page 55.
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3•4
Freescale Semiconductor, Inc.
The IMP debugger.
Each M68302FADS board, is installed with a debugger, resides on the first two sectors of FLASH
memories, U6, U7. Each sector of AM29F040 device, is 64K bytes, thus a total of 128K bytes (1 sectors
per FLASH), are allocated for the debugger. Those two sectors are protected by software against,
accidental programming.
3•4•1
Debugger upgrade.
The debugger supports an on board upgrade capabilities. A new debugger release, is programmed on
board, without the need to take the FLASHes out of their sockets and without the need of a special
programmer. Further instruction will be supplied, with each upgrade.
3•4•2
The debugger programming, of internal 302 processor registers.
Freescale Semiconductor, Inc...
The initialization done by the debugger to an internal 302 family processor registers, is writing to the base
address register (BAR) and programming CS0, CS1 and CS2.
• The BAR is initialized, so the processor register block, resides starting from $700000.
• CS0 is initilized for 1M bytes FLASH starting at 200000H.
• CS1 is initilized for 1M bytes RAM (512K bytes acttualy installed) starting at 000000H.
• CS2 is initilized for 30000H bytes starting at 600000H. CS3 is used for the ADI, EEPROM and
DUART. The internal division of this space, is done by an additional logic, outside the302
processor.
24
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3•5
OPERATING INSTRUCTIONS
Functional description
FIGURE 1-14 HARDWARE BLOCK DIAGRAM
Expansion
Connectors
Freescale Semiconductor, Inc...
PCMCIA
Connector
Logic Analyzer
Connectors
Pchip
LC302
Address
and Data
Buffers
MC68302
*
1 MByte Flash
2 x Am29F040
Clock
Generator
512 KByte SRAM
4 x MCM6229A
* Only one of the three
processors, can be used
at a time.
512 KByte SRAM
4 x MCM6229A
2 KByte EEPROM
AT28C16
DUART
MC68681
RS-232
Ports
Control
logic
ADI Port
Logic
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ADI Port
25
OPERATING INSTRUCTIONS
3•5•1
Freescale Semiconductor, Inc.
MC68LC302 - LCIMP. (Sheet 1)
The LC302 is a low cost version of the original MC68302 - IMP, with an additional on chip PLL.The LC302,
lacks a third SCC and has less pins in total. Pins that were taken off, includes the 4 upper address lines
(A20-A23), function code (F0-F2), arbitration logic (BR~, BG~, BGACK) and more. For more details please
refer to the MC68LC302 user manual. There are 2 packages available for the LC302. An 100 pin TQFP
and 132 pin PGA package. The first has less functional pins and it is the low cost package you intended to
put in your application. The PGA package is intended primary for development tools and is used in the
M68302FADS. The pins added in the PGA package only are - FC0 - FC2, FRZ~, AVEC~ and IAC.
3•5•2
MC68302 - IMP. (Sheet 2)
The IMP is the first chip of the 302 family. It is an integrated multi-protocol processor, using the well known
68000 core.
Freescale Semiconductor, Inc...
3•5•3
MC68PM302 - Pchip. (Sheet 3)
The Pchip is integration of the original MC68302 - IMP, with a PCMCIA card logic.As the LC302, it lacks a
third SCC and has less pins in total. Pins that were taken off, includes the 4 upper address lines (A20-A23),
function code (F0-F2), arbitration logic (BR~, BG~, BGACK) and more. For more details please refer to the
MC68PM302 user manual. There are 2 packages available for the Pchip. An 130 pin TQFP and 181 pin
PGA package. The first has less functional pins and it is the low cost package you intended to put in your
application. The PGA package is intended primary for development tools. The pins added in the PGA
package only are - FC0 - FC2, FRZ~, AVEC~ and IAC.
3•5•4
The on board processors, in general
The pins of all 3 processors, are available unbuffered to the user, through the expansion and the logic
analyzer connectors. The user can monitor the processor activity and connects the ADS to his own
hardware application during its development stage.All processors’ pins, are buffered from all devices on
the ADS to minimize their load and to enable easy connection to the user hardware application.
3•5•5
Processors’ clock (sheet 4)
The system clock can be generated from one of 3 sources. On board clock oscillator, on board crystal
circuit and an external clock source. The ADS is shipped with the first option. It consist of a clock oscillator
running at twice the processor speed, followed by a divide by two flip flop. The divider assure a duty cycle
of almost 50%. The clock oscillator device is mounted on a socket and can be easily replaced to get a
different clock speed as requested. In case a crystal circuit or an external clock option is desired, please
connect your Motorola dealer.
3•5•6
Indicators and controls (sheet 5)
The ADS reset and abort, control buttons, each equipped with a debounce circuit to prevent oscillations.
The board has run, halt power and pc power indicators.
3•5•7
Control logic (sheet 6)
The IMP control logic is programmed into a MACH220 device. It consist of the following units:
• Chip select logic Provides chip select for SRAM, FLASH, EEPROM, ADI, DUART. The chip selects are generated
from the IMP CS0, CS1 and CS2. In the first two, the MACH reflect the signal as is. In the case
of CS2, the MACH divide its range into three sections, 64K bytes each, for the ADI, EEPROM and
the ADI.
• DTACK generator DTACK is returned for all devices, accessed by the chip select logic, except the DUART, which
has its own DTACK generator and the FLASH which has its CS0 default, for supplying an internal
DTACK.
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•
•
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•
•
•
3•5•8
OPERATING INSTRUCTIONS
Interrupt controller There are 3 level 7 (NMI) interrupt sources, on board. Abort switch, ADI abort and an external
interrupt line. The interrupt controller, assert a level 7 interrupt with auto vector line and supports
both IMP interrupt modes.Those modes are normal and dedicated. The interrupt controller, is
reported with DUART output port bit 0, the interrupt operating mode. The debugger initializes the
IMP with normal mode.
resources enable Resources like SRAM, FLASH, etc. can be taken out of the memory map (disabled) by this logic,
by a user Dip switches selection.
wait state logic The wait state logic, delays a DTACK generation by several system clock out pulses, as
programed into the MACH device for each resource.
Chip type selection The bus interface for the LC302 and the Pchip, is different from the original IMP. The first two has
a glue less design concept and interface to external devices, through AS~, OE~, WEL~, WEH~
signal. The IMP, on contrary, uses AS~, DS~ and R/W~ signals. The MACH is used to interface
those signals, according to the processor installed on board. (A selection between LC302/Pchip
or IMP, is done by switch 10 of DIP switch set - DS2)
buffers control This logic control data buffers in 16 and 8 bits bus width.
ADI control logic (sheet 7)
A MACH100 device, controls the ADI interface. The ADI interface appears on sheet 10. (See APPENDIX
B - ADI PORT HANDSHAKE DESCRIPTION, for more details on the ADI interface.
3•5•9
Buffers (sheet 8)
To minimize signal load on the 302 processors pins, all address and data lines are buffered. The buffers
support 8 bit bus width as well.
3•5•10
SRAM (sheet 9)
The ADS is supplied with 512 Kilobyte of SRAM, which is implemented by four MCM6229A devices. The
devices are organized as word (16 bits wide). The SRAM access time is 35 nsec.
Another bank of four MCM6229A devices can be soldered on the ADS to increase the SRAM memory
space up to a 1 Mbyte.
3•5•11
Flash Memory (sheet 9)
Two 512 Kilobyte Flash Memory devices, the 29F040, are used to form 1 Mbyte program storage memory.
The devices are organized as word (16 bits wide). The Flash Memory access time is 90 nsec.
The Flash Memory devices are mounted on sockets, enable the user to load code, out of the board.
3•5•12
EEPROM. (sheet 9)
The EEPROM used in the ADS is the AT28C16 device (250 nano-seconds access time, 2K x 8 bit). It
appears as a static RAM for read or write cycle, with a write cycle extended up to 1 millisecond. During an
internal write cycle, the 68302 must not access the EEPROM, but it may access any other device or
performs a data polling on the EEPROM to detect end of a write cycle. The data polling feature of the
EEPROM, enables the 68302 to detect the end of an internal write cycle. During an internal write cycle, the
302 processor, may read the last byte written to the EEPROM. If the internal write cycle is in process, then
the result is the complement of the written data on bit 7, else the result is the true data. Only data pulling
access, will return correct results from the EEPROM, during an internal write cycle. The AT28C16 has
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OPERATING INSTRUCTIONS
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internal hardware protection, against inadvertent writes to the EEPROM, that might happen during power
up or power down time.
3•5•13
ADI port (sheet 10)
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The ADI interface uses LS TTL drivers to communicate with the host. The ADI parallel port supplies parallel
link from the ADS to various host computers. This port is connected via a 37 line cable to a special board
called ADI (Application Development Interface) installed in the host computer. It is possible to connect the
ADS board to an IBM-PC/XT/AT or to SUN-4 SPARC station, provided that they have an ADI board with
the appropriate software drivers installed on them. Each ADS, has 8 possible slave addresses, for its ADI
port, enabling up to 8 ADS boards to be connected to the same AD part. The ADS address is selected by
the DS1 dip switch found on sheet 3. The ADI port connector P1 is a 37 pin, male, D type connector. (Same
connector used for communicating with the on board command converter). The connection between the
ADS and the host computer is by a 37 line flat cable, supplied with the ADI board. FIGURE 1-15 below
shows the pin configuration of the connector.
FIGURE 1-15 ADI Port Connector
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
N.C.
HOST_VCC
HOST_VCC
HOST_VCC
HOST_ENABLE~
Gnd
Gnd
Gnd
PD0
PD2
PD4
PD6
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
INT_ACK
N.C.
HST_ACK
ADS_ALL
ADS_RESET
ADS_SEL2
ADS_SEL1
ADS_SEL0
HOST_REQ
ADS_REQ
ADS_ACK
ADS_INT
HOST_BRK~
ADS_BRK
N.C.
PD1
PD3
PD5
PD7
3•5•13•1 ADI Port Signal Description
In the list below, the directions ’I’, ’O’ and ’I/O’ refer to the ADS board. (I.E. ’I’ means input to the ADS)
•ADS_SEL(0:2) -’I’
These three inputs determine the ADS board address. The address being set, would be the only
one to which the board respond, when referenced by the host computer. Up to 8 boards can be
addressed by one ADI port.
• ADS_ALL -’I’
This input line is used to reset or abort program execution on all ADS development boards that
are connected to the same ADI board. When this line is active, the IMP ADI and the on board
command converter, are simultaneously referenced.
•HOST_ENABLE~ -’I’
This line is always driven low by the ADI board. The ADS hardware uses this line to determine if
a host is connected to the ADI port.
•ADS_BRK -’I’
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OPERATING INSTRUCTIONS
This line is used in conjunction with the addressing lines or with the ADS_ALL line to generate a
non-maskable interrupt (interrupt level 7) to the processor.
•ADS_RESET -’I’
When a host is connected, this line is used in conjunction with the addressing lines or with the
ADS_ALL line to reset the ADS board.
•HOST_REQ -’I’
This signal initiates a host to ADS write cycle.
•ADS_ACK -’O’
This signal is the ADS response to the HOST_REQ signal, indicating that the ADS board has
detected the assertion of HOST_REQ.
•ADS_REQ -’O’
This signal initiates an ADS to host write cycle.
•HST_ACK -’I’
This signal serves as the host’s response to an ADS_REQ signal.
•HOST_BRK~ -’O’
This open-collector signal, generates an interrupt to the host. This signal is common to all ADS
boards that are connected to the same ADI.
•ADS_INT -’O’
This line is polled by the host computer during its interrupt acknowledge cycle to determine which
ADS board has generated an interrupt.
•INT_ACK -’I’
This line is asserted by the host at the end of its interrupt acknowledge cycle. This signal is used
by the ADS hardware to negate the HOST_BRK~ signal. The ADS software, must negate the
ADS_INT signal upon detecting an assertion of INT_ACK, to support the daisy-chain interrupt
structure.
•HOST_VCC -’I’ (three lines)
These +5V power lines, are used by the ADI logic, to determine if a host computer is powered on.
The ADS does not use these lines for power supply.
•PD(0:7) -’I/O’
These eight I/O lines are the parallel data bus. This bus is used to transmit and receive data from
the host computer.
3•5•14
MC68681 DUART (sheet 11)
The MC68681 is DUART device connected to the 68302 part that provides the ADS with the following
functions:
• 16 bit programmable counter/timer.
• ADI Port interface for the 68302 part.
• 2 RS-232 ports interface.
The debugger initializes port A of the DUART, to work with - 9600bps, 8 bit data, 1 stop bit and no parity.
3•5•14•1 DUART Clock Source
The MC68681 uses a 3.6864Mhz crystal as its clock source, thus its communication rate, is independent
of the system clock. The crystal is connected, between X1 and X2 pins, of the DUART.
3•5•15
RS-232 serial ports. (sheet 11)
The RS-232 serial ports of the ADS are connected to channels A and B, of the MC68681 DUART. The ADS
can be connected to a VT100 compatible terminal through the primary serial port (P2 connector), which is
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the only one supported by the debugger. Both ports has a 9 pin, D-type, female connector as shown in
FIGURE 1-8.
FIGURE 1-16 RS-232 Serial Ports Connector
CD
TX
1
2
RX
DTR
3
4
5
GND
6
7
8
9
DSR
RTS (N.C)
CTS
N.C.
1
2
RX
DTR
3
4
5
GND
P2 - Primery port
(DCE port)
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CD
TX
6
7
8
9
DSR
RTS
CTS (N.C)
N.C.
P2 - Secoundary port
(DTE port)
3•5•15•1 Primary RS-232 port Signal Description
In the list below, the directions ’I’, ’O’ and ’I/O’ refer to the ADS board.
(I.E.’I’ means input to the ADS)
• CD (O) - Data Carrier Detect. This line is always asserted by the ADS.
• TX (O) - Transmit Data.
• RX (I) - Receive Data.
• DTR (I) - Data Terminal Ready. This signal is used by the software in the ADS to detect if a
terminal is connected to the ADS board.
• DSR (O) - Data Set Ready. This line is always asserted by the ADS.
• RTS (I) - Request To Send. This line is not connected in the ADS.
• CTS (O) - Clear To Send. This line is always asserted by the ADS.
* The secondary port has the above signals with the opposite flow direction.
3•5•16
PCMCIA Connector (sheet 12)
The PCMCIA interface pins of the Pchip appears on an Sbus miniature connector, which is interfaced, into
a PCMCIA port, trough an extender. The ADS does not use host PCMCIA power, but a relay on the ADS
is used to power the ADS, upon power detection, on the PCMCIA connector pins. The user can choose to
use this relay by a Dip switch selection.
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SUPPORT INFORMATION
CHAPTER 4 - SUPPORT INFORMATION
4•1
INTRODUCTION
This chapter provides the interconnection signals, parts list, and schematic diagrams of the M68302FADS
board.
4•2
INTERCONNECT SIGNALS
Freescale Semiconductor, Inc...
The M68302FADS board interconnects with external devices through the following connectors, listed in
Table 2-8.
Table 2-8 Board interconnection
Reference
Type
P1
P2
P3
P4
P5 - P8
37 pin, male D type connector
9 pin, female D type connector
9 pin, female D type connector
68 pin male, miniature Sbus connector
20 pin, male connectors, compatible with
HP logic analyzer connector
96 pin, male DIN connector
96 pin, female DIN connector
3 pin power connector
P11
P9, P12
P10
Function
ADI port
RS232 terminal port (DCE)
RS232 host port (DTE)
PCMCIA extender interface
logic analyzer connectors
logic analyzer connectors
expansion port connectors
5v power supply input
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SUPPORT INFORMATION
4•2•1
Connector P1 Interconnect Signals
P1 is a 37 pin, male D type connector. It is the ADI port of the M68302FADS. P1 signals, are listed in Table
2-9. (In the following table, input and output signals, refer to the ADS board)
Freescale Semiconductor, Inc...
Table 2-9 Connector P1 Interconnect Signals
Pin No.
Signal Name
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 - 25
26
INT_ACK
HST_ACK
ADS_ALL
ADS_RESET
ADS_SEL2
ADS_SEL1
ADS_SEL0
HOST_REQ
ADS_REQ
ADS_ACK
ADS_INT
HOST_BRK~
ADS_BRK
PD1
PD3
PD5
PD7
GND
-
27 - 29
HOST_VCC
30
31 - 33
34
35
36
37
HOST_ENABLE~
GND
PD0
PD2
PD4
PD6
Interrupt Acknowledge input signal.
Not connected
Host Acknowledge input signal.
ADS All, input signal.
ADS Reset input signal.
ADS Select 2, input signal. (ADI address bit 2)
ADS Select 1, input signal. (ADI address bit 1)
ADS Select 0, input signal. (ADI address bit 0)
HOST Request, input signal.
ADS Request, output signal.
ADS Acknowledge, output signal.
ADS Interrupt, output signal.
HOST Break open collector, output signal.
ADS Break, input signal.
Not connected
Bit 1 of the ADI port data bus
Bit 3 of the ADI port data bus
Bit 5 of the ADI port data bus
Bit 7 of the ADI port data bus
board common ground
Not connected. The host supplies +12V on this pin, but it is not connected on
the M68302FADS
HOST VCC input (+5V). The M68302FADS does not use these inputs for
power supply.
HOST Enable, input signal.
Ground signal of the M68302FADS
Bit 0 of the ADI port data bus
Bit 2 of the ADI port data bus
Bit 4 of the ADI port data bus
Bit 6 of the ADI port data bus
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4•2•2
SUPPORT INFORMATION
Connector P2 Interconnect Signals
P2 is a 9 pin, female D type connector. It is the RS232 serial port of the M68302FADS. P2 signals are listed
in Table 2-9. (In the following table, input and output signals, refer to the ADS board)
Table 2-10 Connector P2, Interconnect Signals
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Pin No.
1
2
3
4
5
6
7
8
9
4•2•3
Signal Name
Description
CD
TX
RX
DTR
GND
DSR
RTS (N.C.)
CTS
-
Carrier Detect output.
Transmit Data output.
Receive Data input.
Data Terminal Ready input.
Ground signal of the ADS.
Data Set Ready output.
Request To Send. This line is not connected in the ADS.
Clear To Send output.
Not connected
Connector P3 Interconnect Signals
P3 is a 9 pin D type female connector. It is a host secondary RS232 port. Signals are listed in Table
2-13.
Table 2-11 Connector P3, Interconnect Signals
Pin No.
1
2
3
4
5
6
7
8
9
4•2•4
Signal Name
Description
TX
RX
DTR
GND
DSR
RTS
CTS (N.C)
-
Transmit Data input.
Not connected
Receive Data output.
Data Terminal Ready output.
Ground signal of the ADS.
Data Set Ready input.
Request To Send output.
Clear To Send input. This line is not connected in the ADS
Not connected
Connector P4 interconnect signals
P4, is 68 pin, SBUS type connector. It is the PCMCIA extender port. P4 signals are listed in Table 2-12.
Table 2-12 Connector P4 interconnect signals
Pin No.
Signal name
I/O
1
2
3
4
5
GND
D3
D4
D5
D6
I/O
I/O
I/O
I/O
Description
Board common ground
PCMCIA data bit 3
PCMCIA data bit 4
PCMCIA data bit 5
PCMCIA data bit 6
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Table 2-12 Connector P4 interconnect signals
Signal name
I/O
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
D7
CE1~
A10
OE~
A11
A9
A8
A13
A14
WE~
RDY
VCC
VPP1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16~
GND
GND
CD1~
D11
D12
D13
D14
D15
CE2~
RFRSH
IORD
IOWR
I/O
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
I/O
I/O
I/O
I/O
I/O
I
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Pin No.
34
I
I
Description
PCMCIA data bit 7
Card enable 1
PCMCIA address bit 10
PCMCIA output enable
PCMCIA address bit 11
PCMCIA address bit 9
PCMCIA address bit 8
PCMCIA address bit 13 (Not supported)
PCMCIA address bit 14 (Not supported)
PCMCIA write enable
PCMCIA ready output.
Host power.
Programming voltage (Not supported)
PCMCIA address bit 16 (Not supported)
PCMCIA address bit 15 (Not supported)
PCMCIA address bit 12 (Not supported)
PCMCIA address bit 7
PCMCIA address bit 6
PCMCIA address bit 5
PCMCIA address bit 4
PCMCIA address bit 3
PCMCIA address bit 2
PCMCIA address bit 1
PCMCIA address bit 0
PCMCIA data bit 0
PCMCIA data bit 1
PCMCIA data bit 2
I/O is 16. (Set by on board jumper)
Board common ground
Board common ground
PCMCIA card detect 1 (Grounded)
PCMCIA data bit 11
PCMCIA data bit 12
PCMCIA data bit 13
PCMCIA data bit 14
PCMCIA data bit 15
PCMCIA card enable 2
Not supported
PCMCIA I/O read
PCMCIA I/O write
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Table 2-12 Connector P4 interconnect signals
Pin No.
Signal name
I/O
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
A17
A18
A19
A20
A21
VCC
VPP2
A22
A23
A24
A25
RFU
RST
WAIT
IPACK
REG
SPKR
SCHG~
D8
D9
D10
CD2~
GND
I
I
I
I
I
I
I
I
I
4•2•4•1
Connector P5 Interconnect Signals
I
O
O
I
I
I/O
I/O
I/O
O
-
Description
PCMCIA address bit 17
PCMCIA address bit 18
PCMCIA address bit 19
PCMCIA address bit 20
PCMCIA address bit 21
Host VCC
Not supported
PCMCIA address bit 22
PCMCIA address bit 23
PCMCIA address bit 24
PCMCIA address bit 25
Reserved for future use
PCMCIA reset
PCMCIA wait
Input port ack
Reg memory attribute
Not supported
PCMCIA status changed
PCMCIA data bit 8
PCMCIA data bit 9
PCMCIA data bit 10
PCMCIA card detect 2 (Grounded)
Board common ground
P10 is a dual row, 20 pin, male connector. The upper address bus and control signals of the processor,
appear on this connector, for easy monitoring by a logic analyzer. P5 connector signals are listed in Table
2-13.
Table 2-13 P5 connector interconnect signals
Pin NO
Signal name
Description
1
2
3
4
5
6
7
8
9
10
NC
NC
WEH~/UDS~
A15
A14
A13
A12
A11
A10
A9
No connection
No connection
write enable high/upper data strobe
address line 15
address line 14
address line 13
address line 12
address line 11
address line 10
address line 9
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Table 2-13 P5 connector interconnect signals
Signal name
Description
11
12
13
14
16
16
17
18
19
20
A8
A7
A6
A5
A4
A3
A2
A1
WEH~/UDS~
GND
address line 8
address line 7
address line 6
address line 5
address line 4
address line 3
address line 2
address line 1
write enable high/upper data strobe
Board common ground
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Pin NO
4•2•5
Connector P6 Interconnect Signals
P9 is a dual row, 20 pin, male connector. The upper address bus and bus control signal of the processor,
appear on this connector, for easy monitoring by a logic analyzer.P9 connector signals are listed in Table
2-14.
Table 2-14 P6 connector interconnect signals
36
Pin NO.
Signal name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
NC
WEL~/LDS~
BGACK~
FC2
FC1
FC0
IAC
WEH~/UDS~
WEL~/LDS~
OE~/R/W~
A23
A22
A21
A20
A19
A18
A17
A16
GND
Description
No connection
No connection
write enable low/lower data storbe
bus grant acknowledge
function code 2
function code 1
function code 0
internal access
write enable high/upper data strobe
write enable low/lower data strobe
output enable/read write
address line 23
address line 22
address line 21
address line 20
address line 19
address line 18
address line 17
address line 16
Board common ground
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Connector P7 interconnect Signals
P7 is a dual row, 20 pin, male connector. The processor data bus appears on this connector, for easy
monitoring by a logic analyzer. P7 signals are listed in Table 2-16.
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Table 2-15 P7 interconnect signals
Pin NO
Signal name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
NC
AS~
D15
D14
D13
D12
D11
D10
D9
D8
D6
D7
D5
D4
D3
D2
D1
D0
GND
4•2•7
Description
No connection
No connection
address strobe
data line 15
data line 14
data line 13
data line 12
data line 11
data line 10
data line 9
data line 8
data line 7
data line 6
data line 5
data line 4
data line 3
data line 2
data line 1
data line 0
Board common ground
Connector P8 interconnect Signals
P8 is a dual row, 20 pin, male connector. The processor data bus appears on this connector, for easy
monitoring by a logic analyzer. P8 signals are listed in Table 2-16
Table 2-16 P8 interconnect signals
Pin NO
Signal name
1
2
3
4
5
6
7
8
NC
NC
CLKO
CS3~
CS2~
AVEC~
BERR~
RST~
Description
No connection
No connection
clock out
chip select line 3
chip select line 2
auto vector
bus error
reset
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Table 2-16 P8 interconnect signals
Pin NO
Signal name
9
10
11
12
13
14
15
16
17
18
19
20
CLKO
DTACK~
HALT~
BR~
CS1~
IPL2~
IPL1~
IPL0~
BG~
CS0~
AS~
GND
4•2•8
Description
clock out
data transfer acknowledge
halt control
bus request
chip select line 1
interrupt priority level 2
interrupt priority level 1
interrupt priority level 0
bus grant
chip select line 0
address strobe
Board common ground
Connector P9 interconnect signals
P9 is a 3 row, 96 pin female DIN connector. All processors signals, are routed directly to P9 and P12, for
user hardware applications. P9 signals are listed in Table 2-17.
Table 2-17 Connector P9 interconnect signals
Pin NO
Signal name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
GND
GND
GND
A7
A4
A9
A14
A19
A16
A21
FC2
RMC~
CS3~
PB3
IAC
GND
PB1
FC1
D14
D11
OE~/R/W~
38
Description
Board common ground
Board common ground
Board common ground
address line bit 7
address line bit 4
address line bit 9
address line bit 14
address line bit 19
address line bit 16
address line bit 21
function code bit 2
read modify write cycle
chip select 3
port B bit 3
internal access
common
port B bit 1
function code bit 1
data bit 14
data bit 11
output enable/read write
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Table 2-17 Connector P9 interconnect signals
Pin NO
Signal name
Description
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
D6
DTACK~
BERR~
IPL1~
IPL2~
PA15
BGACK~
FRZ~
PA13
BG~
VCC
GND
A1
GND
A2
A5
A10
A15
A12
A17
A22
FC0
CS0~
PB11
PB10
PB2
PB8
PB4
WEH~/UDS~
D10
D13
AS~
D9
D2
AVEC~
IPL0~
BR~
EXTAL
RST~
PA12
data bit 6
data transfer acknowledge
bus error
interrupt priority level 1
interrupt priority level 1
port A bit 15
bus grant acknowledge
freeze
port A bit 13
bus grant
board common +5V supply
Board common ground
address bit 1
Board common ground
address bit 2
address bit 5
address bit 10
address bit 15
address bit 12
address bit 17
address bit 22
function code 0
chip select bit 0
port B bit 11
port B bit 10
port B bit 2
port B bit 8
port B bit 4
write enable high/upper data strobe
data bit 10
data bit 13
address strobe
data bit 9
data bit 2
auto vector
interrupt priority 0
bus request
external clock input/crystal
reset
port A bit 12
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Table 2-17 Connector P9 interconnect signals
Signal name
Description
B30
B31
B32
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
D3
busw
VCC
GND
GND
GND
A3
A6
A11
A8
A13
A18
A23
A20
CS1~
CS2~
PB6
PB5
PB7
PB9
PB0
D15
D12
WEL~/LDS
D8
D7
D1
CLKO
D5
BCLR~
D4
D0
HALT~
PA14
VCC
data bit 3
bus width
board common +5V supply
board common ground
board common ground
board
address bit 3
address bit 6
address bit 11
address bit 8
address bit 13
address bit 18
address bit 23
address bit 20
chip select 1
chip select 2
port B bit 6
port B bit 5
port B bit 7
port B bit 9
port B bit 0
data bit 15
data bit 12
write enable low/lower data strobe
data bit 8
data bit 7
data bit 1
clock out
data bit 5
bus clear
data bit 4
data bit 0
halt control
port A bit 14
board common +5V supply
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Pin NO
4•2•9
Connector P10 Interconnect Signals
P18 is 3 pin connector for 5v power supply. The connector is supplied with 3 pin plug for convenient
40
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connection to the power supply. P10 connector signals, are listed in Table 2-9.
Table 2-18 Connector P10 interconnect Signals
Pin No.
1
2
3
4•2•10
Signal Name
Description
VCC
GND
GND
Power supply, +5V connection.
Power supply, ground connection.
Power supply, ground connection.
Connector P11 Interconnect Signals
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P11 is a 3 row, 96 pin, male DIN connector. This connector, together with P5, P6, P7 and P8, has all
processor pins for easy interfacing to a logic analyzer. P11 signals, are listed in Table 2-19.
Table 2-19 Connector P11 interconnect signals
Pin NO
Signal name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
GND
GND
GND
IPB0
IPB1
IPB2
IPB3
IPB4
IPB5
IPB6
IPB7
IPB8
IPB9
IPB10
IPB11
GND
PDI(8)
PDI(9)
PDI(10)
PDI(11)
PDI(12)
PDI(13)
PDI(14)
GND
GND
RXD1
TXD1
CD1~
CTS1~
Description
Board common ground
Board common ground
Board common ground
port B bit 0
port B bit 1
port B bit 2
port B bit 3
port B bit 4
port B bit 5
port B bit 6
port B bit 7
port B bit 8
port B bit 9
port B bit 10
port B bit 11
Board common ground
port D bit 8
port D bit 9
port D bit 10
port D bit 11
port D bit 12
port D bit 13
port D bit 14
Board common ground
Board common ground
SCC1 receive data input
SCC1 transmit data output
SCC1 carrier detect
SCC1 clear to send
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Table 2-19 Connector P11 interconnect signals
Signal name
Description
A30
A31
A32
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
C1
C2
C3
C4
C5
RTS1~
GND
GND
GND
GND
GND
PCD0
PCD1
PCD2
PCD3
N.C.
GND
PCA3
PCA4
PCA5
GND
PCRDY
PCOE~
PCCE1~
GND
PCREG~
PCWAIT~
PCSTSCH~
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PA0
PA1
SCC1 request to sent
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
PCMCIA data bit 0
PCMCIA data bit 1
PCMCIA data bit 2
PCMCIA data bit 3
No connect
Board common ground
PCMCIA address bit 3
PCMCIA address bit 4
PCMCIA address bit 5
Board common ground
PCMCIA ready signal
PCMCIA output enable
PCMCIA card enable 1
Board common ground
PCMCIA reg signal
PCMCIA wait signal
PCMCIA status change signal
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
port A bit 0
port A bit 1
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Pin NO
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Table 2-19 Connector P11 interconnect signals
Pin NO
Signal name
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
GND
BRG1~
GND
RCLK1
GND
TCLK1
GND
CTS3~
RTS3~
CD3~
GND
GND
GND
4•2•11
Description
port A bit 2
port A bit 3
port A bit 4
port A bit 5
port A bit 6
port A bit 7
port A bit 8
port A bit 9
port A bit 10
port A bit 11
port A bit 12
port A bit 13
port A bit 14
port A bit 15
Board common ground
baud rate generator 1 output
Board common ground
SCC 1 receive clock
Board common ground
SCC 1 receive clock
Board common ground
SCC3 clear to send
SCC3 request to send
SCC 3 carrier detect
Board common ground
Board common ground
Board common ground
Connector P12 interconnect signals
P12 is a 3 row, 96 pin female DIN connector. Processor signals, are directly routed to P9 and P12
connectors, for user hardware applications. P19 connector signals, are listed in Table 2-20.
Table 2-20 Connector P12 interconnect signals
Pin NO
Signal name
A1
A2
A3
A4
A5
VCC
VCC
GND
PB0
PB1
Description
Board common +5V supply
Board common +5V supply
Board common ground
port B bit 0
port B bit 1
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Table 2-20 Connector P12 interconnect signals
Signal name
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
GND
PDI8
PDI9
PDI10
PDI11
PDI12
PDI13
PDI14
GND
GND
RXD1
TXD1
CD1~
CTS1~
RTS1~
GND
GND
VCC
EXTNMI~
GND
PCD0
PCD1
PCD2
PCD3
N.C.
GND
PCA3
PCA4
PCA5
GND
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Pin NO
44
Description
port B bit 2
port B bit 3
port B bit 4
port B bit 5
port B bit 6
port B bit 7
port B bit 8
port B bit 9
port B bit 10
port B bit 11
Board common ground
port D bit 8
port D bit 9
port D bit 10
port D bit 11
port D bit 12
port D bit 13
port D bit 14
Board common ground
Board common ground
SCC1 receive data
SCC1 transmit data
SCC1 carrier detect
SCC1 clear to send
SCC1 request to send
Board common ground
Board common ground
Board common +5V supply
external level 7 interrupt source
Board common ground
PCMCIA data bit 0
PCMCIA data bit 1
PCMCIA data bit 2
PCMCIA data bit 3
No connect
Board common ground
PCMCIA address bit 3
Board common ground
Board common ground
Board common ground
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Table 2-20 Connector P12 interconnect signals
Pin NO
Signal name
Description
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
PCRDY
PCOE~
PCCE1~
GND
PCREG~
PCWAIT~
PCSTSCHG~
GND
BCLR~
RMC~
GND
DISCPU
GND
GND
GND
GND
GND
VCC
VCC
VCC
GND
GND
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
GND
BRG1
PCMCIA ready signal
PCMCIA output enable
PCMCIA card enable 1
Board common ground
PCMCIA reg signal
PCMCIA wait signal
PCMCIA status change
Board common ground
bus clear
read modify write cycle
Board common ground
disable CPU
Board common ground
Board common ground
Board common ground
Board common ground
Board common ground
Board common +5V supply
Board common +5V supply
Board common +5V supply
Board common ground
Board common ground
port A bit 0
port A bit 1
port A bit 2
port A bit 3
port A bit 4
port A bit 5
port A bit 6
port A bit 7
port A bit 8
port A bit 9
port A bit 10
port A bit 11
port A bit 12
port A bit 13
port A bit 14
port A bit 15
Board common ground
baud rate generator 1
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Table 2-20 Connector P12 interconnect signals
Signal name
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
GND
RCLK1
NC
TCLK1
GND
CTS3~
RTS3~
CD3|
GND
GND
VCC
Freescale Semiconductor, Inc...
Pin NO
46
Description
Board common ground
SCC 1 receive clock
no connect
SCC 1 transmit clock
Board common ground
SCC 3 clear to send
SCC 3 request to send
SCC 3 carrier detect
Board common ground
Board common ground
board common +5V supply
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Table 2-21 Part list
Freescale Semiconductor, Inc...
Reference
C1
(Alternative to C1A)
C1A (Alternative to C1)
C2
(Alternative to C2A)
C2A (Alternative to C2)
C3 C4 C5 C6 (C7) C8 C9
C10 C11 C12 C13 C14 C15
C16 C17 C19 C20 C21 C22
C23 C24 C25 C26 C27 C28
C29 C30 C31 C32 C34 C35
C36 C38 C40 C41 C42 C45
C46 C47 C48 C49 C50 C51
C52 C53 C54 C56 C61 C66
C67C68 C69 C70 C71 C72
C73 C74 C76 C77 C78 C82
C83 C84 C85 C86
C18 C33 C55 C57 C58 C59
C60 C62 C63 C64 C65 C75
C37 C43
(C39) (C44)
C79
C80
C81
D1 D2
(Alternative to D1A, D2A)
D1A D2A
(Alternative to D1, D2)
D3
D4
DS1 DS2
F1
J1 J2 J3
LD1
LD2
LD3
LD4
P1
P2 P3
P4
P5 P6 P7 P8
P9 P12
Part NO/Value
Manufacturer
total
220uF/25V - Alum.
220uF/10V SMD - TPSE227K010R
47uF/16V - Alum.
47uF/10V SMD - TAJD476K010
0.1uF/50V 1206
Nippon
AVX
Nippon
AVX
AVX
1
1
1
1
65
10uF/20V 10% 5A-100KAT00J
Nippon
12
1.5nF/50V 1206
10pF/50V 10% 1206
1nF/50V 10% 1206
4.7pF/50V 10% 1206-5A4R7KAT00J
15pF/50V 10% 1206-5A150KAT00J
1N4148
AVX
AVX
AVX
AVX
AVX
2
2
1
1
1
2
LL4148
TSC
2
MBRD620CT
1SMC50AT3
DIP SW 10PST 90 HBW10S
Fuse 3.155A/250V Fast
5x20mm 2170005
+ PCB Fuse holder PTF15
3 pin jumper
Yellow LED LY-T670-HK
Red LED
LR-T670-HK
Orange LED LO-T670-HK
Green LED LG-T670-HK
D-type 37p male 90’ w clip conn.
D-type 9p female 90’ w clip conn.
68p male 90’ PC mini SBUS conn.
20p logic analyzer conn.
DIN96p female 90’ w clip
Motorola
Motorola
Grayhill
1
1
2
Siemens
Siemens
Siemens
Siemens
Keltron
Keltron
ODU
Molex
Elco
1
1
3
1
1
1
1
1
2
1
4
2
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Table 2-21 Part list
Freescale Semiconductor, Inc...
Reference
P10
P11
R1 R7
(R2) R8
R3 R9 R18 R21 R22 R23
R25
R4 R13 R19
(R5) R17
(R6) R11 R16 R20
R10
R12 R14
R15
R24
RLY1
RN1 RN4 RN5 RN6 RN7
RN8
RN2 RN3
SW1 SW2
U1 U5
U2 U13 U25 U26
*U3
U4
*U6 *U7
*U8
(U9) (U39)
**U10
(U11) U12 (U14) U15 (U17)
U18 (U20) U21
U16 U19 U22
**U23
*U24
**U27
U28 U29
U30
48
Part NO/Value
Manufacturer
total
3 pin male power conn.
DIN96p m straight 168477096001025
2K 5% 1/4W 1206
220 5% 1/4W 1206
10K 5% 1/4W 1206
Molex
Elco
AVX
AVX
AVX
1
1
2
2
7
1K 5% 1/4W 1206
470K 5% 1/4W 1206
330 5% 1/4W 1206
100 5% 1/4W 1206
100K 5% 1/4W 1206
47K 5% 1/4W 1206
1M 5% 1/4W 1206
Relay 5V 8A SPDT 42319005
13x4.7K Res NW DIP SOMC1401472
AVX
AVX
AVX
AVX
AVX
AVX
AVX
Finder
Dale
3
2
4
1
2
1
1
1
6
8x22 Res NW 16DIP SOMC1603220J
Push button SPDT E121SD1AV2GE
+ Red cap
8018/3 (For SW2)
+ Black cap
8018/2 (For SW1)
74LS244D
74ACT244D
MACH110-2oJC
+ 44p PLCC socket
74F543
AM29F040-90
+ 32p PLCC socket 205-032-10
AT28C16-15JC
+ 32p PLCC socket 205-032-10
SPARE
MC68302RC
+ 132p PGA socket 13x13 PC
MCM6229A
Dale
Motorola
Motorola
AMD
AMP
Motorola
AMD
AMP
Atmel
AMP
Motorola
Precidip
Motorola
2
2
1
1
2
4
1
1
1
2
2
1
1
2
1
1
8
74ACT245
MC68LC302
+ 132p PGA socket 13x13 PC
MACH220-12JC
+ 68p PLCC socket 205-068-10
MC68PM302RC
+ 181p PGA socket 15x15 PC
MC145407
MC68681FN
Motorola
Motorola
Precidip
AMD
AMP
Motorola
Precidip
Motorola
Motorola
3
1
1
1
1
1
1
2
1
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Table 2-21 Part list
Reference
Freescale Semiconductor, Inc...
U31
U32 U35
U33
*U34
U36
U37
U38
(Y1)
Y2
Part NO/Value
74ACT08D
74ACT00D
74ACT74D
8, 32 or 40MHz Osc. HXO-125532
+ 14 pin DIP socket.
74LS05D
74HC4538D
74ACT14D
32KHz or 4MHz crystal HC49U
3.6864MHz crystal HCU46
Rubber leg
Manufacturer
Motorola
Motorola
Motorola
Precidip
Motorola
Motorola
Motorola
total
1
2
1
1
1
1
1
1
1
1
5
How to read the table.
(U1)
*U1
**U1
- Component U1 is not assembled.
- Component U1 should be mounted on a socket.
- Only the socket for U1, should be assembled.
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APPENDIX A - ADI BOARD INSTALLATION
A•1
INTRODUCTION
This appendix describes the hardware installation of the ADI board into various host computers.
The installation instructions, cover the following host computers:
1. IBM-PC/XT/AT
2. SUN - 4 (SBus interface)
A•2
IBM-PC/XT/AT to M68302FADS Interface
Freescale Semiconductor, Inc...
The ADI board should be installed in one of the IBM-PC/XT/AT mother board system, expansion slots. A
single ADI can control, up to eight M68302FADS boards. ADI address, in the host computer, is configured
to be at I/O addresses space,100-102 (hex), but it may be reconfigure, for an alternate address space.
A•2•1
CAUTION
BEFORE REMOVING OR INSTALLING ANY
EQUIPMENT
IN
THE
IBM-PC/XT/AT
COMPUTER, TURN THE POWER OFF AND
REMOVE THE POWER CORD.
ADI Installation in IBM-PC/XT/AT
Refer to the appropriate Installation and Setup manual of the IBM-PC/XT/AT computer, for instructions on
removing computer cover.
The ADI board address block, should be configured at a free I/O address space. The address must be
unique and it must not fall within the address range, of another card installed in the computer.
The ADI board address block can be configured to start at one of the three following addresses:
• $100 - This address is unassigned in the IBM-PC
• $200 - This address is usually used for the game port
• $300 - This address is defined as a prototype port
The ADI board is factory configured for address decoding at 100-102 hex in the IBM-PC/XT/AT I/O address
map. These are undefined peripheral addresses.
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FIGURE A-1 Physical Location of jumper JG1 and JG2
Freescale Semiconductor, Inc...
JG1
JG2
NOTE: Jumper JG2 should be left unconnected.
The following figure, shows the required jumper connection, for each address configuration. Address 0 hex
is not recommended and its usage might cause problems.
FIGURE A-2 JG1 Configuration Options
0 hex
100 hex
200 hex
300 hex
To properly install the ADI board, position its front bottom corner in the plastic card guide channel, at the
front of the IBM-PC/XT/AT chassis. Keeping ADI board top and any ribbon cables, out of the way, lower
the board until its connectors are aligned with the computer expansion slot connectors. Using evenly
distributed pressure, press the ADI board straight down until it seats in the expansion slot.
Secure the ADI board to computer’s chassis, using a bracket retaining screw. Refer to computer
Installation and Setup manual, for instructions on reinstalling, computer cover.
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A•3
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SUN-4 to M68302FADS Interface
The ADI board should be installed in one of the SBus expansion slots in a Sun-4 SPARCstation. A single
ADI, can control up to eight M68302FADS boards.
A•3•1
CAUTION
BEFORE REMOVING OR INSTALLING ANY
EQUIPMENT IN THE SUN-4 COMPUTER, TURN
THE POWER OFF AND REMOVE POWER
CORD.
ADI Installation in a SUN-4 machine
Freescale Semiconductor, Inc...
There are no jumper options, on the ADI board, for a Sun-4 machine. The ADI board can be inserted into
any available SBus expansion slot, on the mother board.
Refer to the appropriate Installation and Setup manual for the Sun-4 computer for instructions on removing
the computer cover and installing the board in an expansion slot.
FIGURE A-3 ADI board for SBus
ADI
Connector
SBus
Connector
Following are the Sun’s manual, instructions summary:
1. Turn off the power to your system, but keep power cord, plugged in. Be sure to save all open files
and follow the steps bellow, to shut down your system:
• hostname% /bin/su
• Password: mypasswd
• hostname# /usr/etc/halt
• wait for the following messages.
Syncing file systems... done
Halted
Program Terminated
Type b(boot), c(continue), n(new command mode)
• When these messages appear, you can safely turn off, your system power.
2. Open the system unit. Be sure to attach a grounding strap, to your wrist and to the power supply,
metal casing. Follow the instructions supplied with your system, to gain access to the SBus slots.
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3. Remove SBus slot filler panel, from the inner surface of the back panel of your system unit. Note that
the ADI board, is a slave only board and thus will function in any available SBus slot.
4. Slide the ADI board at an angle, into the back panel of your system unit. Make sure, the mounting
plate on the ADI board, hooks into the holes on the back panel of your system unit.
5. Push the ADI board against the back panel, align the connector with its mate and gently press board
corners, to plug the connector firmly.
6. Close your system unit.
7. Connect a 37 pin interface flat cable to the ADI board and secure.
8. Turn on system power and check for proper operation.
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APPENDIX B - ADI PORT HANDSHAKE DESCRIPTION
B•1
INTRODUCTION
The M68302FADS ADI port, can be connected to an ADI board, mounted in a host computer.
There are ADI boards for the following host computers:
1. IBM-PC/XT/AT
2. SUN - 4 (SBus interface)
Freescale Semiconductor, Inc...
B•2
ADI Port Concept and Operation Description
Each ADI board, can be connected with up to 8 M68302FADS boards. Each ADS has its own address
which is fixed by setting Dip-Switch DS1 switches 8-10, on the board.
The following operations can be performed using the ADI port:
• The host computer can write a byte to the ADS
• The ADS can write a byte to the host computer
• The ADS can interrupt the host computer
• The host computer can interrupt the ADS (interrupt level 7)
• The host computer can reset the ADS
If more than one ADS, is connected to the same ADI board, the host computer can perform the following
operations simultaneously on all M68302FADS boards:
• Abort all boards (interrupt level 7)
• Reset all boards
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B•3
Handshake Description
Every action between the ADS and the host, is asynchronous and implemented by asserting and negating
handshake signals trough software.
All signals have TTL levels. A control signal is asserted, when driven to logic’1’ TTL level, and it is negated
when driven to logic’0’ level.
The connection between a host computer and ADS, is shown in FIGURE B-1 below.
FIGURE B-1 Host Computer (ADI) to M68302FADS Connection
HOST_REQ
Freescale Semiconductor, Inc...
ADS_ACK
ADS_REQ
HST_ACK
ADS_BRK
HOST
COMPUTER
ADI board
HOST_BRK~
ADS_INT
M68302FADS
INT_ACK
ADS_RESET
ADS_ALL
ADS_SEL(0:2)
PD(0:7)
HOST_ENABLE~
HOST_VCC
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B•3•1
SUPPORT INFORMATION
Write Cycle from Host to M68302FADS
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The application software in the Host, uses handshake signals, to coordinate data transfer across parallel
link. The software installed on the ADS, is responsible for accepting data, and responding to handshake
signals. The signals are shown in FIGURE B-2.
The sequence of events during a byte write to a M68302FADS, is as follows:
1. The Host selects the M68302FADS board, by placing the board address, on
ADS_SEL(0:2) lines.
2. The Host places a data byte, in a data bus latch (Its output buffer, is in high-impedance
state).
3. The Host asserts HOST_REQ signal (data buffer is enabled. data appears on the bus).
4. The ADS, detects the HOST_REQ signal and reads the data byte.
5. The ADS respond by asserting ADS_ACK signal.
6. The Host detects the ADS_ACK signal and negates HOST_REQ signal (data buffer is
disabled).
7. The ADS detects HOST_REQ negation and negates ADS_ACK to end the cycle.
FIGURE B-2 Host Write to M68302FADS
1
ADDRESS VALID
ADS_SEL(0:2)
3
6
HOST_REQ
5
7
ADS_ACK
2
PD(0:7)
4
DATA VALID
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Write Cycle from M68302FADS to Host
Signal handshake during an ADS to Host write cycle is shown in FIGURE B-3. The sequence of events, is
as follows:
1. The M68302FADS places a data byte on the parallel port data bus (buffer disabled) and
asserts ADS_REQ signal. (the ADS_REQ signal does not appear on the port, until the
board is selected by the Host)
2. The Host polls each ADS address and detects the ADS_REQ signal from the requesting
board. The Host asserts the HST_ACK signal in response, which enables ADS data buffer.
3. The ADS negates ADS_REQ signal. Data appears on the bus, as long as the HST_ACK
signal is asserted.
4. The Host reads the data.
5. The Host negates HST_ACK signal, to end the cycle. The ADS ends the cycle.
Freescale Semiconductor, Inc...
FIGURE B-3 M68302FADS Write Cycle to Host
1
3
ADS_REQ
4
DATA VALID
PD(0:7)
ADS_SEL(0:2)
ADDRESS VALID
2
5
HST_ACK
B•3•3
M68302FADS Interrupt to the Host
The M68302FADS can generate an interrupt to the Host. Interrupt request and acknowledge sequence, is
shown in FIGURE B-4.
The sequence is as follows:
1. The ADS, places a service request code on the parallel port data bus (buffer disabled)
asserts ADS_INT and HOST_BRK~ signals. The HOST_BRK~ signal is an open-collector
signal, asserted low, common to all ADS boards, that appears immediately on the port. The
ADS_INT signal does not appear on the port, until the board is selected by the Host.
2. The Host detects an HOST_BRK~ signal and polls each ADS address to determine the
interrupting board.
3. The Host asserts an HST_ACK signal, enabling the ADS data buffer.
4. The Host reads the service request code on the data bus.
5. The Host negates the HST_ACK signal.
6. The Host asserts an INT_ACK signal, which resets the HOST_BRK latch, in the ADS and
negates the HOST_BRK~ signal. the HOST_BRK~ signal can remain low (asserted) if
another ADS board is driving it low.
7. The selected ADS, detects an INT_ACK signal and negates the ADS_INT signal.
8. The Host negates the INT_ACK signal and ends the cycle.
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FIGURE B-4 M68302FADS Interrupt to Host
hardware
HOST_BRK~
7
1
software
ADS_INT
4
DATA VALID
PD(0:7)
Freescale Semiconductor, Inc...
2
ADDRESS VALID
ADS_SEL(0:2)
3
5
HST_ACK
6
8
INT_ACK
B•3•4
Host Interrupt to the M68302FADS
The Host can interrupt the ADS (interrupt level 7) to abort program execution, running on the board. This
is done by selecting an address of the required ADS and momentarily asserting an ADS_BRK signal, which
sets the ADS latch. The latch output, interrupts the processor on the ADS and can be cleared by the
interrupt handling software on the ADS.
B•3•5
Host Reset to the M68302FADS
The Host can perform reset to the ADS. Reset is done by selecting the address of the required board and
asserting the ADS_RESET signal, for more than 26 microseconds.
B•3•6
Addressing All M68302FADS
The Host can reset or interrupt all M68302FADS boards, which are connected to the same ADI card. The
host should assert an ADS_ALL signal, in conjunction with either ADS_RESET or ADS_BRK. The contents
of the ADS_SEL(0:2) lines have no affect.
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APPENDIX C - PLD equations.
C•1
IMP control logic - U24.
Freescale Semiconductor, Inc...
"******************************************************************************
"* 302 family ADS control logic.
*
"* Logic includes CS logic, DTACK generator, interrupt controller, bus
*
"* arbiter, resources enable, buffers control and NMI reg.
*
"******************************************************************************
module _302fmlyADS
title '302 family ADS control logic.
"******************************************************************************
"* Device declaration.
*
"******************************************************************************
U01 device 'mach220a';
"******************************************************************************
"* Pins declaration.
*
"******************************************************************************
"******************************************************************************
"* 302 signals.
*
"******************************************************************************
CLKO
PIN 15;
"Clock.
AS~
PIN 16;
"Address strobe.
IAC
PIN 54;
"Internal access.
A1, A2, A3
PIN 41, 45, 60; "Address lines. (Int level)
A16, A17, A18, A19
PIN 57,56,40,37;"Address lines and int ack.
CS0~, CS1~, CS2~
PIN 4, 23, 55; "Chip select lines.
FC0, FC1, FC2
PIN 26, 25, 24; "Function code lines.
WEL~
PIN 50;
"WEL~/WE~ or LDS~/DS~ in the IMP.
WEH~
PIN 49;
"WEH~/A0 or UDS~/A0 in the IMP.
OE~
PIN 20;
"OE~ or R/W~ in the IMP control (in).
BR_W~
PIN 28;
"Buffered R/W~ (out.)
BUSW
PIN 17;
"Bus width control.
Rst~
PIN 47;
"Reset signal.
Halt~
PIN 67;
"Halt signal.
IPL0~, IPL1~, IPL2~
PIN 38, 36, 39; "Interrupt priority;
AVEC~
PIN 48;
"Auto vector.
"******************************************************************************
"* Buffer control signals.
*
"******************************************************************************
BusL~
PIN 31;
"Data buffer D0-D7 enable.
BusL2H~
PIN 30;
"D0-D7 to D8-D15 bus, enable.
BusH~
PIN 29;
"Data buffer D8-D15 enable.
"******************************************************************************
"* C/S and R/W signals.
*
"******************************************************************************
RamLCs~
PIN 13;
"RAM low CS.
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RamHCs~
PIN 12;
"RAM high CS.
ExpRamLCs~
PIN 10;
"Expansion RAM low CS.
ExpRamHCs~
PIN 11;
"Expansion RAM high CS.
FlashLCs~
PIN 5;
"FLASH low CS.
FlashHCs~
PIN 3;
"FLASH high CS.
EepromCs~
PIN 14;
"EEPROM CS. (Connected to D0-D7)
DuartCs~
PIN 9;
"DUART CS.
AdiRd~
AdiWr~
PIN 21;
PIN 22;
"Adi port, read enable.
"Adi port, write enable.
"Low/High bus R/W control split, is only for deviding signal load.
RdL~
PIN 7;
"Bus low, read signal.
RdH~
PIN 2;
"Bus high, read signal.
WrL~
PIN 6;
"Bus low, write signal.
WrH~
PIN 32;
"Bus high, write signal.
"******************************************************************************
"* Resources enable signals.
*
"******************************************************************************
RamEn~
PIN 63;
"On board RAM enable signal.
FlashEn~
PIN 62;
"On board FLASH enable signal.
EepromEn~
PIN 64;
"On board EEPROM enable signal.
EepromWriteEnable~
PIN 65;
"EEPROM write enable From DUART port.
DuartEn~
PIN 66;
"On board DUART enable signal.
AdiEn~
PIN 43;
"On board RAM enable signal.
"******************************************************************************
"* Processor type selection.
*
"******************************************************************************
ChipType
PIN 58;
"Processor type selection.
"******************************************************************************
"* DTACK generator signals.
*
"******************************************************************************
Dtack~
PIN 33;
"DTACK~ to the processor;
DtackOe
NODE;
"DtackOe, controls Dtack~ output
"enable. It is a logical inverse of
"the Dtack~ signal, with a delay of
"about 15nsec. This way, Dtack~
"output enable, stayes active 15nsec
"after Dtack~ posage so an active
"pullup behavior is obtained.
"******************************************************************************
"* Reset control.
*
"******************************************************************************
ExtRst~
PIN 51;
"External reset. Reset sources are :
62
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"Power up, ADI, PCMCIA, or reset
"switch.
Freescale Semiconductor, Inc...
"******************************************************************************
"* Local interrupt controller. An NMI come from 3 sources :
*
"*
ADI, External and abort switch.
*
"******************************************************************************
ExtNmi~
PIN 46;
"NMI input.
ExtNmiState0, ExtNmiState1 NODE;
"NMI F.F.
ExtNmiState0, ExtNmiState1 ISTYPE 'reg, buffer';
ExtNmiFlag
NODE;
"Reports of an external NMI condition.
IntMode
PIN 44;
"Int. mode selection. (Normal/Dedicated)
ExtNmiAck
NODE;
"External NMI acknowledge.
"******************************************************************************
"* Delayed CS2~ for DUART. (Postponed it after R/W~, for the DUART)
*
"******************************************************************************
CS2~_DLY1
NODE;
"First delay F.F.
CS2~_DLY1
ISTYPE 'reg, neg';
CS2~_DLY2
NODE;
"Second delay F.F.
CS2~_DLY2
ISTYPE 'reg, neg';
"******************************************************************************
"* Wait state logic, signals.
*
"******************************************************************************
WaitState3, WaitState2,
WaitState1, WaitState0
NODE;
"Wait state counter.
WaitState3, WaitState2,
WaitState1, WaitState0
ISTYPE 'reg, buffer';
"******************************************************************************
"* Constant declaration.
*
"******************************************************************************
H, L, X, Z = 1, 0, .X., .Z.;
C, D, U
= .C., .D., .U.;
READ = 1;
WRITE = !READ;
BYTE
WORD
= 0;
= !BYTE;
CS0~_ACTIVE
CS1~_ACTIVE
CS2~_ACTIVE
OE~_ACTIVE
WEL~_ACTIVE
WEH~_ACTIVE
LDS~_ACTIVE
UDS~_ACTIVE
=
=
=
=
=
=
=
=
0;
0;
0;
0;
0;
0;
0;
0;
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Freescale Semiconductor, Inc...
ADI_RD~_ACTIVE
ADI_WR~_ACTIVE
AS~_ACTIVE
RAM_EN~_ACTIVE
RAM_L_CS~_ACTIVE
RAM_H_CS~_ACTIVE
EEPROM_EN~_ACTIVE
EEPROM_CS~_ACTIVE
EEPROM_WRITE_ENABLE~_ACTIVE
FLASH_EN~_ACTIVE
FLASH_L_CS~_ACTIVE
FLASH_H_CS~_ACTIVE
DUART_EN~_ACTIVE
DUART_CS~_ACTIVE
ADI_EN~_ACTIVE
IAC_ACTIVE
EXT_NMI~_ACTIVE
EXT_RST~_ACTIVE
RST~_ACTIVE
EXT_NMI_ACK_ACTIVE
DTACK~_ACTIVE
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0;
0;
0;
0;
0;
0;
0;
0;
0;
0;
0;
0;
0;
0;
0;
1;
0;
0;
0;
1;
0;
FUNC_INT_ACK_CYCLE = [1, 1, 1];
ADDR_INT_ACK_CYCLE = [1, 1, 1, 1];
EXT_NMI_INT_LEVEL = [1, 1, 1];
NORMAL_INT_LEVEL_7
= [0, 0, 0];
DEDICATED_INT_LEVEL_7 = [0, 1, 1];
INT_LEVEL_0
= [1, 1, 1];
"Normal mode level 7 int = 0,0,0.
"Dedicated mode level 7 int : IPL2~=0.
"No active interrupt, level.
NORMAL_INT_MODE
= 1;
DEDICATED_INT_MODE = !NORMAL_INT_MODE;
Address
FunctionCode
IntLevel
IPL~
WaitState
=
=
=
=
[A19, A18, A17, A16];
[FC2, FC1, FC0];
[A3, A2, A1];
[IPL2~, IPL1~, IPL0~];
= [WaitState3, WaitState2, WaitState1, WaitState0];
"Wait state macroes.
ONE_WAIT_STATE
TWO_WAIT_STATES
THREE_WAIT_STATES
FOUR_WAIT_STATES
FIVE_WAIT_STATES
SIX_WAIT_STATES
SEVEN_WAIT_STATES
EIGHT_WAIT_STATES
NINE_WAIT_STATES
TEN_WAIT_STATES
ELEVEN_WAIT_STATES
TWELVE_WAIT_STATES
THIRTEEN_WAIT_STATES
64
=
=
=
=
=
=
=
=
=
=
=
=
=
1;
2;
3;
4;
5;
6;
7;
8;
9;
10;
11;
12;
13;
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SUPPORT INFORMATION
FOURTEEN_WAIT_STATES = 14;
FIFTEEN_WAIT_STATES = 15;
"Processor types.
IMP
= 0;
LC302 = IMP+1;
Freescale Semiconductor, Inc...
"Address resolution is 64K bytes.
RAM_ADDRESS
= [0,X,X,X];
EXP_RAM_ADDRESS = [1,X,X,X];
ADI_ADDRESS
= [0,0,0,0];
EEPROM_ADDRESS = [0,0,0,1];
DUART_ADDRESS
= [0,0,1,0];
ADI_PORT_ACCESS = ( (AdiRd~==ADI_RD~_ACTIVE) # (AdiWr~==ADI_WR~_ACTIVE) );
EXT_NMI_ACK_CYCLE = ( ExtNmiAck.fb==EXT_NMI_ACK_ACTIVE );
"******************************************************************************
"* Vector macroes.
*
"******************************************************************************
"******************************************************************************
"* Enternal NMI machine states.
*
"******************************************************************************
ExtNmiState = [ExtNmiState1, ExtNmiState0];
WAIT_FOR_NMI_RELEASE_STATE = 0;
WAIT_FOR_NMI_INSERT_STATE = WAIT_FOR_NMI_RELEASE_STATE + 1;
NMI_ACTIVE_STATE
= WAIT_FOR_NMI_INSERT_STATE + 1;
"******************************************************************************
"* Vector macroes.
*
"******************************************************************************
"******************************************************************************
"* Equations, state diagrams.
*
"******************************************************************************
"*
*
"* #######
*
"* #
####
#
#
##
#####
#
####
#
#
####
*
"* #
#
# #
#
# #
#
#
#
# ##
# #
*
"* #####
#
# #
# #
#
#
#
#
# # # #
####
*
"* #
# # # #
# ######
#
#
#
# # # #
#
*
"* #
#
#
#
# #
#
#
#
#
# #
## #
#
*
"* #######
### #
####
#
#
#
#
####
#
#
####
*
"*
*
"******************************************************************************
"******************************************************************************
"* Buffers control.
*
"* BUSL~ enables D0-D7, BUSH~ enable D8-D15, BUSL2H enables the 302 to
*
"* connect to D8-D15 with its lines D0-D7, This feature enable the 302 to
*
"* access 16 bit bus when running in 8 bit width mode.
*
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"******************************************************************************
equations
!BusL~
= ((BUSW==WORD) # ((BUSW==BYTE) & (WEH~==1))) & (AS~==AS~_ACTIVE) &
( ((CS0~==CS0~_ACTIVE) & (FlashEn~==FLASH_EN~_ACTIVE)) #
((CS1~==CS1~_ACTIVE) & (RamEn~==RAM_EN~_ACTIVE)) #
((CS2~==CS2~_ACTIVE) &
(((Address==EEPROM_ADDRESS) & (EepromEn~==EEPROM_EN~_ACTIVE)) #
((Address==ADI_ADDRESS) & (AdiEn~==ADI_EN~_ACTIVE)) #
((Address==DUART_ADDRESS) & (DuartEn~==DUART_EN~_ACTIVE)))) );
Freescale Semiconductor, Inc...
!BusL2H~ = (BUSW==BYTE) & (WEH~==0) & (AS~==AS~_ACTIVE) &
"WEH~/A0
( ((CS0~==CS0~_ACTIVE) & (FlashEn~==FLASH_EN~_ACTIVE)) #
((CS1~==CS1~_ACTIVE) & (RamEn~==RAM_EN~_ACTIVE)) #
((CS2~==CS2~_ACTIVE) &
(((Address==EEPROM_ADDRESS) & (EepromEn~==EEPROM_EN~_ACTIVE)) #
((Address==ADI_ADDRESS) & (AdiEn~==ADI_EN~_ACTIVE)) #
((Address==DUART_ADDRESS) & (DuartEn~==DUART_EN~_ACTIVE)))) );
!BusH~
= (BUSW==WORD) & (AS~==AS~_ACTIVE) &
( ((CS0~==CS0~_ACTIVE) & (FlashEn~==FLASH_EN~_ACTIVE)) #
((CS1~==CS1~_ACTIVE) & (RamEn~==RAM_EN~_ACTIVE)) #
((CS2~==CS2~_ACTIVE) &
(((Address==EEPROM_ADDRESS) & (EepromEn~==EEPROM_EN~_ACTIVE)) #
((Address==ADI_ADDRESS) & (AdiEn~==ADI_EN~_ACTIVE)) #
((Address==DUART_ADDRESS) & (DuartEn~==DUART_EN~_ACTIVE)))) );
"******************************************************************************
"* Delayed CS2~.
*
"* CS2~ is delayed to generate R/W~ before CS2~, for the DUART.
*
"******************************************************************************
equations
CS2~_DLY1.clk = CLKO;
CS2~_DLY2.clk = CLKO;
CS2~_DLY1.ar
CS2~_DLY2.ar
= !Rst~;
= !Rst~;
CS2~_DLY1 := CS2~;
CS2~_DLY2 := CS2~_DLY1;
"******************************************************************************
"* C/S signals.
*
"* C/S for RAM, FLASH, EEPROM, DUART.
*
"******************************************************************************
equations
!RamLCs~
= (CS1~==CS1~_ACTIVE) & (Address==RAM_ADDRESS) &
(RamEn~==RAM_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==1)) ); "WEH~ is A0, in 8 bit mode.
!RamHCs~
66
= (CS1~==CS1~_ACTIVE) & (Address==RAM_ADDRESS) &
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(RamEn~==RAM_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==0)) ); "WEH~ is A0, in 8 bit mode.
Freescale Semiconductor, Inc...
!ExpRamLCs~ = (CS1~==CS1~_ACTIVE) & (Address==EXP_RAM_ADDRESS) &
(RamEn~==RAM_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==1)) ); "WEH~ is A0, in 8 bit mode.
!ExpRamHCs~ = (CS1~==CS1~_ACTIVE) & (Address==EXP_RAM_ADDRESS) &
(RamEn~==RAM_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==0)) ); "WEH~ is A0, in 8 bit mode.
!FlashLCs~ = (CS0~==CS0~_ACTIVE) &
(FlashEn~==FLASH_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==1)) ); "WEH~ is A0, in 8 bit mode.
!FlashHCs~ = (CS0~==CS0~_ACTIVE) &
(FlashEn~==FLASH_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==0)) ); "WEH~ is A0, in 8 bit mode.
!EepromCs~ = (CS2~==CS2~_ACTIVE) & (Address==EEPROM_ADDRESS) &
(EepromEn~==EEPROM_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==1)) ); "WEH~ is A0, in 8 bit mode.
!DuartCs~
= (CS2~_DLY2==CS2~_ACTIVE) &
( ((Address==DUART_ADDRESS) &
(DuartEn~==DUART_EN~_ACTIVE)) #
((Address==ADI_ADDRESS) &
(AdiEn~==ADI_EN~_ACTIVE) &
(A3==1)) ) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==1)) ); "WEH~ is A0, in 8 bit mode.
when (ChipType==IMP) then
!AdiRd~
= (CS2~==CS2~_ACTIVE) &
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(Address==ADI_ADDRESS) &
(A3==0) &
(AdiEn~==ADI_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
(OE~==READ) &
( (WEL~==LDS~_ACTIVE) #
(WEH~==UDS~_ACTIVE) );
"OE~ is R/W~ in the IMP.
"WEL~ is LDS~ in the IMP.
"WEH~ is UDS~ in the IMP.
Freescale Semiconductor, Inc...
else
!AdiRd~
= (CS2~==CS2~_ACTIVE) &
(Address==ADI_ADDRESS) &
(A3==0) &
(AdiEn~==ADI_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
(OE~==OE~_ACTIVE);
when (ChipType==IMP) then
!AdiWr~
= (CS2~==CS2~_ACTIVE) &
(Address==ADI_ADDRESS) &
(A3==0) &
(AdiEn~==ADI_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
(OE~==WRITE) &
"OE~ is R/W~ in the IMP.
(WEL~==LDS~_ACTIVE) &
"WEL~ is LDS~ in the IMP.
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==1)) ); "WEH~ is A0, in 8 bit mode.
else
!AdiWr~
= (CS2~==CS2~_ACTIVE) &
(Address==ADI_ADDRESS) &
(A3==0) &
(AdiEn~==ADI_EN~_ACTIVE) &
(AS~==AS~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
(WEL~==WEL~_ACTIVE) &
( (BUSW==WORD) #
((BUSW==BYTE) & (WEH~==1)) ); "WEH~ is A0, in 8 bit mode.
"******************************************************************************
"* RAM, FLASH, EEPROM, read/write control.
*
"******************************************************************************
equations
"*************************
"* Read low byte signal. *
"*************************
when (ChipType==IMP) then
!RdL~ = (OE~==READ) &
"OE~ is R/W~ in the IMP.
(WEL~==LDS~_ACTIVE) &
"WEL~ is LDS~/DS~ in the IMP
(Rst~==!RST~_ACTIVE) &
(IAC==!IAC_ACTIVE);
else
!RdL~ = (OE~==OE~_ACTIVE) &
(Rst~==!RST~_ACTIVE) &
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(IAC==!IAC_ACTIVE);
Freescale Semiconductor, Inc...
"**************************
"* Read high byte signal. *
"**************************
when (ChipType==IMP) then
!RdH~ = (OE~==READ) &
(WEH~==UDS~_ACTIVE) &
(Rst~==!RST~_ACTIVE) &
(IAC==!IAC_ACTIVE);
else
!RdH~ = (OE~==OE~_ACTIVE) &
(Rst~==!RST~_ACTIVE) &
(IAC==!IAC_ACTIVE);
"OE~ is R/W~ in the IMP.
"WEH~ is UDS~/A0 in the IMP
"**************************
"* Write low byte signal. *
"**************************
when (ChipType==IMP) then
!WrL~
= (OE~==WRITE) &
"OE~ is R/W~ in the IMP.
(WEL~==LDS~_ACTIVE) &
"WEL~ is LDS~/DS~ in the IMP
(Rst~==!RST~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
!( (EepromWriteEnable~==!EEPROM_WRITE_ENABLE~_ACTIVE) &
(EepromCs~==EEPROM_CS~_ACTIVE) );
else
!WrL~
= (WEL~==WEL~_ACTIVE) &
(Rst~==!RST~_ACTIVE) &
(IAC==!IAC_ACTIVE) &
!( (EepromWriteEnable~==!EEPROM_WRITE_ENABLE~_ACTIVE) &
(EepromCs~==EEPROM_CS~_ACTIVE) );
"***************************
"* Write high byte signal. *
"***************************
when ( (ChipType==IMP) & (BUSW==WORD) ) then
!WrH~ = (OE~==WRITE) &
"OE~ is R/W~ in the IMP.
(WEH~==UDS~_ACTIVE) &
"WEH~ is UDS~ in the IMP.
(Rst~==!RST~_ACTIVE) &
(IAC==!IAC_ACTIVE);
else when ( (ChipType==IMP) & (BUSW==BYTE) ) then
!WrH~ = (OE~==WRITE) &
"OE~ is R/W~ in the IMP.
(WEL~==LDS~_ACTIVE) &
"LDS~ becomes DS~ in 8 bit mode.
(Rst~==!RST~_ACTIVE) &
(IAC==!IAC_ACTIVE);
else when ( (ChipType!=IMP) & (BUSW==WORD) ) then
!WrH~ = (WEH~==WEH~_ACTIVE) &
(Rst~==!RST~_ACTIVE) &
(IAC==!IAC_ACTIVE);
else
!WrH~ = (WEL~==WEL~_ACTIVE) &
"WEL~ becomes WE~ in 8 bit mode.
(Rst~==!RST~_ACTIVE) &
(IAC==!IAC_ACTIVE);
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SUPPORT INFORMATION
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"***************************
"* R/W~ signal.
*
"***************************
when (ChipType==IMP) then
BR_W~ = OE~;
else
BR_W~ = !OE~;
"******************************************************************************
"* Dtack output.
*
"******************************************************************************
equations
Dtack~.oe = DtackOe;
Freescale Semiconductor, Inc...
when ( ((CS1~==CS1~_ACTIVE) & (RamEn~==RAM_EN~_ACTIVE)) #
((CS2~==CS2~_ACTIVE) & (WaitState.fb>=FIVE_WAIT_STATES) &
(((Address==EEPROM_ADDRESS) & (EepromEn~==EEPROM_EN~_ACTIVE)) #
((Address==ADI_ADDRESS) & (AdiEn~==ADI_EN~_ACTIVE)))) ) then
Dtack~ = DTACK~_ACTIVE;
else
Dtack~ = !DTACK~_ACTIVE;
DtackOe = !Dtack~.fb;
"******************************************************************************
"* Wait state counter.
*
"* Up to 15 wait state with a 4 bit counter.
*
"******************************************************************************
equations
WaitState.clk = CLKO;
WaitState.ar = AS~;
WaitState := WaitState.fb + 1;
"******************************************************************************
"* External NMI F.F.
*
"******************************************************************************
equations
ExtNmiState.clk = CLKO;
ExtNmiState.ar = !Rst~;
state_diagram ExtNmiState
state WAIT_FOR_NMI_RELEASE_STATE:
if ( ExtNmi~==EXT_NMI~_ACTIVE ) then
WAIT_FOR_NMI_RELEASE_STATE
else
WAIT_FOR_NMI_INSERT_STATE;
state WAIT_FOR_NMI_INSERT_STATE:
if ( ExtNmi~==EXT_NMI~_ACTIVE ) then
NMI_ACTIVE_STATE
else
WAIT_FOR_NMI_INSERT_STATE;
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state NMI_ACTIVE_STATE:
if EXT_NMI_ACK_CYCLE then
WAIT_FOR_NMI_RELEASE_STATE
else
NMI_ACTIVE_STATE;
equations
ExtNmiFlag = ( ExtNmiState.fb==NMI_ACTIVE_STATE );
Freescale Semiconductor, Inc...
"******************************************************************************
"* 302 reset.
*
"******************************************************************************
equations
Rst~.oe = !Rst~.fb;
!Rst~
= (ExtRst~==EXT_RST~_ACTIVE);
"******************************************************************************
"* 302 halt.
*
"******************************************************************************
equations
Halt~.oe = !Halt~.fb;
!Halt~
= (ExtRst~==EXT_RST~_ACTIVE);
"******************************************************************************
"* Interrupt priority.
*
"******************************************************************************
equations
IPL0~.oe = !IPL0~.fb;
IPL1~.oe = !IPL0~.fb;
"IPL0~, IPL1~ have the same function. Only 2 OE
"functions are available per MACH block.
IPL2~.oe = !IPL2~.fb;
when ExtNmiFlag &
(IntMode==NORMAL_INT_MODE) &
(ExtRst~==!EXT_RST~_ACTIVE) then
IPL~ = NORMAL_INT_LEVEL_7;
else
when ExtNmiFlag &
(IntMode==DEDICATED_INT_MODE) &
(ExtRst~==!EXT_RST~_ACTIVE) then
IPL~ = DEDICATED_INT_LEVEL_7;
else
IPL~ = INT_LEVEL_0;
"******************************************************************************
"* External NMI acknowledge.
*
"******************************************************************************
equations
ExtNmiAck = ( (IntLevel==EXT_NMI_INT_LEVEL) &
(FunctionCode==FUNC_INT_ACK_CYCLE) &
(Address==ADDR_INT_ACK_CYCLE) &
(AS~==AS~_ACTIVE) );
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"******************************************************************************
"* Auto vector signal.
*
"******************************************************************************
equations
AVEC~.oe = !AVEC~.fb;
!AVEC~ = EXT_NMI_ACK_CYCLE & (ExtRst~==!EXT_RST~_ACTIVE);
Freescale Semiconductor, Inc...
"******************************************************************************
"* Test vectors
*
"******************************************************************************
"*
*
"* #######
*
"*
#
######
####
#####
*
"*
#
#
#
#
*
"*
#
#####
####
#
*
"*
#
#
#
#
*
"*
#
#
#
#
#
*
"*
#
######
####
#
*
"*
*
"* #
#
*
"* #
# ######
####
#####
####
#####
####
*
"* #
# #
#
#
#
#
# #
# #
*
"* #
# #####
#
#
#
# #
#
####
*
"* #
#
#
#
#
#
# #####
#
*
"*
# #
#
#
#
#
#
# #
#
#
#
*
"*
#
######
####
#
####
#
#
####
*
"*
*
"******************************************************************************
"test_vectors
end _302fmlyADS
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C•2
SUPPORT INFORMATION
ADI control logic - U3.
"******************************************************************************
"* ADI control logic.
*
"* Controls ADI interface for the IMP side and the command converter.
*
"******************************************************************************
module _302ADIctrl
title 'ADI control logic.
Shlomo Reches - Motorola semiconductor - March 3rd, 1994.'
Freescale Semiconductor, Inc...
"******************************************************************************
"* Device declaration.
*
"******************************************************************************
U03 device 'mach110a';
"******************************************************************************
"* Pins declaration.
*
"******************************************************************************
AdiA2, AdiA1, AdiA0
PIN 19, 17, 14; "ADI address.
AdsA2, AdsA1, AdsA0
PIN 9, 5, 4;
"ADS board local address.
AdsAll
PIN 2;
"ADS all.
AdsBrk
PIN 13;
"ADS break.
AdsRst
PIN 26;
"ADS reset.
HostEn~
PIN 35;
"Host enable.
HostVcc
PIN 32;
"Host VCC.
HostAck
PIN 29;
"Host acknowledge.
HostReq
PIN 36;
"Host request.
IntAck
PIN 38;
"Interrupt ack from host.
AdsGrp
PIN 24;
"ADS group. (Not supported)
AdsSel~
PIN 25;
"IMP ADI interface, selected.
Rst~
PIN 6;
"Reset IMP.
HstBrkAck~
PIN 40;
"Reset host break external F.F.
RstSwitch
PcmciaRst~
PwrUpRst
PIN 41;
PIN 21;
PIN 10;
"Reset IMP, switch.
"Reset from PCMCIA.
"Reset from power up circuit.
Nmi~
AbortSwitch
ExtNmi~
PIN 3;
PIN 33;
PIN 11;
"Common NMI output to the processor.
"User abort switch.
"External NMI source.
HostRd~
PIN 20;
"Enable ADS data read by host.
"******************************************************************************
"* Constant declaration.
*
"******************************************************************************
H, L, X, Z = 1, 0, .X., .Z.;
C, D, U
= .C., .D., .U.;
HOST_VCC_ACTIVE
HOST_EN~_ACTIVE
= 1;
= 0;
M68302FADS User’s Manual
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73
SUPPORT INFORMATION
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
HOST_ACK_ACTIVE
HOST_REQ_ACTIVE
ADS_ALL_ACTIVE
ADS_BRK_ACTIVE
ADS_RST_ACTIVE
INT_ACK_ACTIVE
RST_SWITCH_ACTIVE
PCMCIA_RST~_ACTIVE
PWR_UP_RST_ACTIVE
RST~_ACTIVE
BRK~_ACTIVE
HOST_RD~_ACTIVE
ADS_SEL~_ACTIVE
HST_BRK_ACK~_ACTIVE
EXT_NMI~_ACTIVE
ABORT_SWITCH_ACTIVE
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
1;
1;
1;
1;
1;
1;
1;
0;
1;
0;
0;
0;
0;
0;
0;
1;
ADS_TO_HOST_DIRECTION = 1;
HOST_TO_ADS_DIRECTION = !ADS_TO_HOST_DIRECTION;
AdsAddr = [AdsA2, AdsA1, AdsA0];
AdiAddr = [AdiA2, AdiA1, AdiA0];
"******************************************************************************
"* Equations, state diagrams.
*
"******************************************************************************
"*
*
"* #######
*
"* #
####
#
#
##
#####
#
####
#
#
####
*
"* #
#
# #
#
# #
#
#
#
# ##
# #
*
"* #####
#
# #
# #
#
#
#
#
# # # #
####
*
"* #
# # # #
# ######
#
#
#
# # # #
#
*
"* #
#
#
#
# #
#
#
#
#
# #
## #
#
*
"* #######
### #
####
#
#
#
#
####
#
#
####
*
"*
*
"******************************************************************************
"******************************************************************************
"* IMP selected from ADI.
*
"******************************************************************************
equations
!AdsSel~ = (HostVcc==HOST_VCC_ACTIVE) &
(HostEn~==HOST_EN~_ACTIVE) &
( (AdsAddr==AdiAddr) # (AdsAll==ADS_ALL_ACTIVE) );
"******************************************************************************
"* IMP reset.
*
"******************************************************************************
equations
!Rst~ = (PcmciaRst~==PCMCIA_RST~_ACTIVE) #
(RstSwitch==RST_SWITCH_ACTIVE) #
(PwrUpRst==PWR_UP_RST_ACTIVE) #
( (AdsRst==ADS_RST_ACTIVE) &
(AdsSel~==ADS_SEL~_ACTIVE) );
74
M68302FADS User’s Manual
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SUPPORT INFORMATION
Freescale Semiconductor, Inc...
"******************************************************************************
"* Host break ack. (Reset host break external F.F.)
*
"******************************************************************************
equations
!HstBrkAck~ = ( Rst~==RST~_ACTIVE ) #
( (IntAck==INT_ACK_ACTIVE) &
(AdsSel~==ADS_SEL~_ACTIVE) );
"******************************************************************************
"* IMP PD0-PD7 buffer direction control signal.
*
"******************************************************************************
equations
when ( (AdsSel~==ADS_SEL~_ACTIVE) &
(AdsAll==!ADS_ALL_ACTIVE) &
(HostReq==!HOST_REQ_ACTIVE) &
(HostAck==HOST_ACK_ACTIVE) ) then
HostRd~ = HOST_RD~_ACTIVE;
else
HostRd~ = !HOST_RD~_ACTIVE;
"******************************************************************************
"* ADS group. (Not supported)
*
"******************************************************************************
equations
AdsGrp.oe = L;
"******************************************************************************
"* Nmi~
*
"******************************************************************************
equations
!Nmi~ = ( (AdsBrk==ADS_BRK_ACTIVE) & (AdsSel~==ADS_SEL~_ACTIVE) ) #
(AbortSwitch==ABORT_SWITCH_ACTIVE) #
(ExtNmi~==EXT_NMI~_ACTIVE);
end _302ADIctrl
M68302FADS User’s Manual
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75
A
B
B
C
C
D
D
E
F
D(0:15)
A(1:23)
FC(0:2)
CS(0:3)
OE
D(0:15)
A(1:23)
FC(0:2)
CS(0:3)
MC68LC302EMU
OE
LDS
UDS
AS
U23
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
RST
HALT
BUSW
DISCPU
FRZ
LDS
UDS
AS
AS
UDS
LDS
OE
CS(0)
CS(1)
CS(2)
CS(3)
DTACK
IAC
K1
J1
H3
H2
H1
F2
F3
E1
D1
C1
B1
D2
D3
C2
A1
E4
D5
C3
B2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
XTAL
M9
F
XTAL
br/ipl0/irq1 N8 IPL(0)
M8
IPL(1)
bgack/ipl1/irq6 L8
bg/ipl2/irq7 N11 IPL(2)
AVEC
AVEC
D9
RXD1/L1RXD H12 RXD1
TXD1/L1TXD J13 TXD1
RCLK1/L1CLK H11 RCLK1
TCLK1
TCLK1/L1SY0/SDS1
D10
cd1/L1SY1 A13 CD1
cts1/L1GR L13 CTS1
RTS1
rts1/L1RQ/GCIDCL
D11
RXD2/PA0 D12 PA(0)
TXD2/PA1 B13 PA(1)
RCLK2/PA2 D13 PA(2)
TCLK2/PA3 E13 PA(3)
cts2/PA4 F11 PA(4)
rts2/PA5 F12 PA(5)
cd2/PA6 G11 PA(6)
BRG2/SDS2/PA7 E10 PA(7)
SPRXD/PA8 C12 PA(8)
SPTXD/PA9 J12 PA(9)
SPCLK/PA10 H13 PA(10)
PA(12)
MODCLK/PA12
N3
PB3/TIN1 M4 PB(3)
PB5/TIN2 L4 PB(5)
PB6/tout2 M3 PB(6)
PB7/wdog M2 PB(7)
PB8 L3 PB(8)
PB9 K4 PB(9)
PB10 N1 PB(10)
PB(11)
PB11
N12 CLKO
CLKO
C37 1.5nF
L11
XFC
J10
VCCSYN
M11
GNDSYN
N9 EXTAL
EXTAL
L6
L12
RESET K10
M5 AS
HALT L10
N4 uds/weh/A0
lds/ds/wel/we
BUSW M10
M6 R/w/oe
DISCPU/TEST N10
M1
FRZ
K2 cs0/iout2
K3 CS1
L2 CS2
CS3
K12
L1 DTACK
IAC
G3
G2 FC0
F1 FC1
FC2
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
C11
B12
B11
C10
A11
C9
B9
A10
C6
A5
A4
B5
A3
A2
B4
C4
FC(0)
FC(1)
FC(2)
D(0)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
E
IPL(0:2)
PA(0:15)
PB(0:11)
G
G
C38
0.1uF
2
1
VCC
3
J1
GND
H
Shlomo Reches
PROJECT : 302 family ADS
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
I
DESCRIP :
BLOCK :
REV : ENG
LC302
MOTOROLA INC.
I
J
SHEET
J
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OF
18
K
K
1
2
8
7
6
5
4
3
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2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
B
B
CS(0:3)
FC(0:2)
A(1:23)
D(0:15)
C
C
AS
UDS
LDS
OE
AVEC
RMC
CS(0)
CS(1)
CS(2)
CS(3)
DTACK
FC(0)
FC(1)
FC(2)
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
A(22)
A(23)
M6
N5
L6
N6
L9
K2
K1
J2
L1
M1
K9
H1
H3
J1
G1
G3
G2
F2
F3
E1
D1
E2
E3
C1
B1
D3
C2
A1
D4
D5
C3
B2
B3
B4
A2
A3
C5
L7
D(0) B11
D(1) C10
D(2) B10
D(3) A12
D(4) C9
D(5) B9
D(6) A10
D(7) A9
D(8) B8
D(9) A8
D(10) B7
D(11) C7
D(12) A6
D(13) B6
D(14) C6
D(15) A5
EXTAL N7
XTAL is left
unconnected
in the IMP
D
U10
AS
uds/A0
lds/ds
R/w
MC68302RC
RESET
HALT
BUSW
DISCPU
IAC
br
bgack
bg
bclr
berr
frz
ipl0/irq1
ipl1/irq6
ipl2/irq7
PB8
PB9
PB10
PB11
CLKO
NC1
NC3
PB6/tout2
PB7/wdog
PB5/TIN2
PB4/tout1
PB3/TIN1
PB0/iack7
PB1/iack6
PB2/iack1
dreq/PA13
dack/PA14
done/PA15
cts3/SPRXD
rts3/SPTXD
cd3/SPCLK
BRG2/SDS2/PA7
RXD3/PA8
TXD3/PA9
RCLK3/PA10
TCLK3/PA11
BRG3/PA12
cts2/PA4
rts2/PA5
cd2/PA6
BRG1
RXD2/PA0
TXD2/PA1
RCLK2/PA2
TCLK2/PA3
cd1/L1SY1
cts1/L1GR
rts1/L1RQ/GCIDCL
RXD1/L1RXD
TXD1/L1TXD
RCLK1/L1CLK
TCLK1/L1SY0/SDS1
avec/iout0
rmc/iout1
cs0/iout2
CS1
CS2
CS3
DTACK
FC0
FC1
FC2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
EXTAL
XTAL
D
E
N11
N12
K13
J13
M10
M11
M12
L11
K3
M9
H11
L8
N9
N10
A13
K11
N13
L12
C11
D10
K12
J11
D9
E10
C12
D11
B13
C13
E11
E12
E13
F11
F12
F13
G11
G12
H13
H12
B12
M13
L13
M5
L5
N3
N2
L4
M3
M2
K5
J4
K4
N1
L2
M8
L10
J12
E
RST
HALT
BUSW
DISCPU
BR
BGACK
BG
BCLR
IAC
BERR
FRZ
IPL(0)
IPL(1)
IPL(2)
RXD1
TXD1
RCLK1
TCLK1
CD1
CTS1
RTS1
BRG1
PA(0)
PA(1)
PA(2)
PA(3)
PA(4)
PA(5)
PA(6)
PA(7)
PA(8)
PA(9)
PA(10)
PA(11)
PA(12)
PA(13)
PA(14)
PA(15)
CTS3
RTS3
CD3
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
PB(8)
PB(9)
PB(10)
PB(11)
CLKO
IPL(0:2)
F
PA(0:15)
CLKO
PB(0:11)
F
G
G
H
PROJECT :
ENG :
CHK :
H
Shlomo Reches
302 family ADS
Freescale Semiconductor, Inc...
1
A
I
DESCRIP :
BLOCK :
REV : ENG
IMP
MOTOROLA INC.
I
J
SHEET
J
2
OF
18
K
K
1
2
8
7
6
5
4
3
For More Information On This Product,
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2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
B
B
C
C
J2
VCC
1
3
GND
2
CS(0:3)
FC(0:2)
A(1:23)
D(0:15)
C45
0.1uF
D
D
AS
UDS
LDS
OE
CS(0)
CS(1)
CS(2)
CS(3)
DTACK
AVEC
IAC
C12
D5
C8
D4
A13
A12
A11
A10
N9
N7
A9
E
MC68PM302RC
F
RESET
HALT
BUSW/PCABUF
DISCPU
FRZ
F
ipl0/irq1/br
ipl1/irq6/bgack
ipl2/irq7/bg
PA0/RXD2/PCD8
PA1/TXD2/PCD9
PA2/RCLK2/PCD10
PA3/TCLK2/PCD11
PA4/cts2/PCD12
PA5/rts2/PCD13
PA6/cd2/PCD14
PA7/BRG2/SDS2/PCD15
PA8/RXD3
PA9/TXD3
PA10/RCLK3
PA11/TCLK3
PA12/MODCLK0/BRG3
PA13/dreq/pciord
PA14/dack/pciowr
PA15/done/pcwe
PDI8/PCA0
PDI9/PCA1
PDI10/PCA2
PDI11/PCA6
PDI12/PCA7
PDI13/PCA8
PDI14/PCA9
PB0/iack7/PCA11
PB1/iack1/pcce2
PB2/iack6/PCA25
PB3/TIN1
PB4/tout1/PCA10
PB5/TIN2/TRIS
PB6/tout2/PCEN
PB7/wdog
PB8
PB9/ri
PB10/dte
PB11
RXD1/L1RXD
TXD1/L1TXD
RCLK1/L1CLK
TCLK1/L1SY0/SDS1
cd1/L1SY1
cts1/L1GR
rts1/L1RQ/GCIDCL
cd3/SPCLK
rts3/SPTXD
cts3/SPRXD
PCD0
FC0/PCD1
FC1/PCD2
FC2/PCD3
frz/PCA5
lds/ds/pcce1
uds/A0/pcreg
rw/PCRDY/pcireq
berr/PCA3
avec/PCA4
bg/pcwait
br/pcstschg
bgack/pcoe
AS
weh/uds/A0
wel/we/lds/ds
oe/R/w
cs0/iout2
CS1
CS2
CS3
DTACK
AVEC
IAC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20/PCD4
A21/PCD5
A22/PCD6
A23/PCD7
B6 FC0
B7 FC1
B8 FC2
A14
D9
D11
E15
F15
G15
B14
C14
D14
G14
C13
D13
F12
H11
H12
J12
K12
L12
H13
A8
B2
B3
B4
FC(0)
FC(1)
FC(2)
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
A(22)
A(23)
R11
R12
R13
R15
L15
K15
J15
H15
M14
L14
K14
J14
M13
L13
K13
J13
N3 EXTAL
L1 GNDSYN
P1 VCCSYN
M1 XFC
P2 CLKO
D(0)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
CLKO
C43 1.5nF
EXTAL
XTAL
U27
L2 XTAL
E
M12
N8
C5
J1
N6
D6
C7
C6
P6
P4
P3
R7
R3
R2
M7
M5
P9
P8
N13
N12
M9
G1
H1
C2
K1
N2
M2
L3
K3
J3
M4
F4
H3
E4
C11
G4
D8
B11
B12
D7
C9
B9
B13
R8
P14
P12
P13
R10
R9
P11
M8
M10
M11
E1
A5
A6
A7
M3
G3
D2
F2
K2
J2
D3
G2
E3
RST
HALT
BUSW
DISCPU
FRZ
IPL(0)
IPL(1)
IPL(2)
PA(0)
PA(1)
PA(2)
PA(3)
PA(4)
PA(5)
PA(6)
PA(7)
PA(8)
PA(9)
PA(10)
PA(11)
PA(12)
PA(13)
PA(14)
PA(15)
PDI(8)
PDI(9)
PDI(10)
PDI(11)
PDI(12)
PDI(13)
PDI(14)
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
PB(8)
PB(9)
PB(10)
PB(11)
RXD1
TXD1
RCLK1
TCLK1
CD1
CTS1
RTS1
CD3
RTS3
CTS3
PCD0
PCD1
PCD2
PCD3
PCA5
PCCE1
PCREG
PCRDY
PCA3
PCA4
PCWAIT
PCSTSCHG
PCOE
G
IPL(0:2)
PA(0:15)
PDI(0:15)
PB(0:11)
G
I
BLOCK :
REV :
H
302 family ADS
ENG
Pchip
MOTOROLA INC.
PROJECT :
DESCRIP :
Shlomo Reches
I
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
J
SHEET
J
3
OF
18
K
K
1
2
8
7
6
5
4
3
For More Information On This Product,
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2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
B
C
U34
CLK
OUT
8
VCC
D
R9
10K
2
3
D
4
SET
Q
5
6
E
R5
470K
74ACT74
CLK
Q
CLR
1 U33
C44 10pF
Y1
25MHz
EXTAL
R6 330
F
XTAL
F
GND
G
EXTAL
C73
0.1uF
R10
100
G
External clock
termination
H
CLKO
GND
Shlomo Reches
PROJECT : 302 family ADS
ENG :
CHK :
H
Freescale Semiconductor, Inc...
50MHz
Mounted
on a socket
GND
C39 10pF
E
Parts in the dashed box, are an option and should not be mounted on the PC board.
D
C7
0.1uF
R2
220
I
Clock out
termination
DESCRIP :
BLOCK :
REV : ENG
J
SHEET
Clock circuit
MOTOROLA INC.
I
J
4
OF
18
K
K
1
C
1
B
2
A
8
7
6
5
4
3
For More Information On This Product,
Go to: www.freescale.com
2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
GND
GND
SW2
-
+
VCC
SW1
R15
47K
C2
47uF
GND
B
VCC
14
4.7K
RN6
4.7K
RN6
12
13
1
2
4.7K
5
14
6
14
RN6
2
VCC
1
14
RN6
4.7K
9
10
4
5
C
RSTSW
Reset debouncer.
U32
74ACT00
3
11
U32
74ACT00
ABORTSW
Abort debouncer
U32
74ACT00
8
6
U32
74ACT00
8
R19
1K
C
PWRUPRST
PWR5V
Power up reset
14
U38
74ACT14_PWR
9
D2
1N4148
B
D
D
E
VCC
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
10
R12
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
VCC
14
7
14
4.7K
RN6
GND
100K
5
3
14
2
F
4
5
3
2
U37 16
VCC
A
B
RST
RX/CX
GND
14
14
14
74HC4538_PWR
14
0.1uF
C82
14
12
14
1
F
4
14
3
11
14
13
10
14
12
9
14
11
14
8
14
G
14
9
PWR5V
PCRST
VCC
1K
VCC
R13
14
1
14
10
G
8
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
RN8 RN8 RN8 RN8 RN8 RN8 RN8 RN8 RN8 RN8
14
13
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
RN6 RN6 RN6 RN6 RN6 RN6 RN6 RN1 RN6
14
6
Q
7
Q
PCMCIA reset duration extender.
B
B
U38
14
11
74ACT14_PWR
R14
PCRST
C79
GND
A1
A2
A3
A4
A5 A
A6
A7
A8
A9
A10
DS2
A1
A2
A3
A4
A5 A
A6
A7
A8
A9
A10
DS1
100K
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
1nF
GND
GND
GND
E
R23
10K
10K
R21 10K
R22
H
C
Power indicator
A
LD4 (GREEN)
C
I
R20
330
220
A
LD1 (YELLOW) R8
330
C
I
GND
J
VCC
14
RN7
AS
4.7K
U31
3
74ACT08
9
8
10
5
PCVCCEN
PWR5V
HALT
J
User and other controls.
SHEET
U31
74ACT08
12
11
13
DESCRIP :
BLOCK :
REV : ENG
MOTOROLA INC.
14
6
5
R16 330
U38
74ACT14_PWR
R11
A
C
LD2 (RED)
A
LD3 (ORANGE)
(MODCLK)
(PCEN)
PC power control
indicator..
VCC
PB(6)
PCVCCEN
RAMEN
FLSHEN
EEPRMEN
ADIEN
DUARTEN
ADSA0
ADSA1
ADSA2
IOIS16
PA(12)
BUSW
BUSWDIP
CHIPTYP
Shlomo Reches
PROJECT : 302 family ADS
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
OF
18
K
K
1
2
8
7
6
5
4
3
For More Information On This Product,
Go to: www.freescale.com
2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
B
C
D
E
BRDH
FLHCS
CS(0)
FLLCS
BWRL
BRDL
UARTCS
ORMLCS
ORMHCS
RMHCS
RMLCS
EPRCS
ADSRD
ADSWR
CS(1)
FC(2)
FC(1)
FC(0)
BR_W
CLKO
AS
BUSWDIP
OE
UDS
LDS
EXTRST
IAC
2
3
4
5
6
7
9
10
11
12
13
14
21
22
23
24
25
26
28
15
16
17
20
49
50
51
54
E
MACH220
I0/CLK0
I1/CLK1
I2
I3
I4/CLK2
I5/CLK3
I6
I7
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
U24
F
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
F
29
30
31
32
33
36
37
38
39
40
41
43
44
45
46
47
48
55
56
57
58
59
60
62
63
64
65
66
67
G
BUSH
BUSL2H
BUSL
BWRH
DTACK
IPL(1)
A(19)
IPL(0)
IPL(2)
A(18)
A(1)
ADIEN
NR_DE
A(2)
NMI
RST
AVEC
CS(2)
A(17)
A(16)
CHIPTYP
U18-59
A(3)
FLSHEN
RAMEN
EEPRMEN
EEPWREN
DUARTEN
HALT
G
J6
H
I
302 family ADS
BLOCK :
REV : ENG
J
SHEET
J
control logic.
MOTOROLA INC.
PROJECT :
DESCRIP :
Shlomo Reches
I
ENG :
CHK :
H
Freescale Semiconductor, Inc...
D
6
OF
18
K
K
1
C
1
B
2
A
8
7
6
5
4
3
For More Information On This Product,
Go to: www.freescale.com
2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
B
C
D
J11
J10
J9
J8
E
PWRUPRST
EXTNMI
ADSBRK
HSTVCC
ABORTSW
HSTEN
ADSALL
NMI
ADSA0
ADSA1
EXTRST
U3-7
U3-8
ADSA2
ADIA0
U3-15
U3-16
ADIA1
E
10
11
13
32
33
35
2
3
4
5
6
7
8
9
14
15
16
17
U3
F
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
MACH110
I0
I1
I2/CLK0
I3
I4
I5/CLK1
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
F
18
19
20
21
24
25
26
27
28
29
30
31
36
37
38
39
40
41
42
43
U3-18
ADIA2
HSTRD
PCRST
ADSGRP
ADSSEL
ADSRST
U3-27
U3-26
HSTACK
U3-30
U3-31
U3-37
HSTREQ
U3-39
INTACK
BRKCLR
RSTSW
U3-42
U3-43
G
G
J12
J7
J13
J14
J15
J16
J17
J19
J18
H
I
302 family ADS
BLOCK :
REV :
J
SHEET
J
ADI control logic.
ENG
MOTOROLA INC.
PROJECT :
DESCRIP :
Shlomo Reches
I
ENG :
CHK :
H
Freescale Semiconductor, Inc...
D
7
OF
18
K
K
1
C
1
B
2
A
8
7
6
5
4
3
For More Information On This Product,
Go to: www.freescale.com
2
8
7
6
5
4
3
Freescale Semiconductor, Inc.
A
B
B
D(0:15)
BD(0:15)
BR_W
BUSL
BUSL2H
BUSH
A(1:23)
BA(1:23)
C
C
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
D
2
4
6
8
11
13
15
17
1
19
BD(0) 2
BD(1) 3
BD(2) 4
BD(3) 5
BD(4) 6
BD(5) 7
BD(6) 8
BD(7) 9
1
19
GND
D
U22
B1
B2
B3
B4
B5
B6
B7
B8
74ACT245
A1
A2
A3
A4
A5
A6
A7
A8
DIR
G
U13
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
74ACT244
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
18
17
16
15
14
13
12
11
18
16
14
12
9
7
5
3
D(0)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
E
E
F
BD(8) 2
BD(9) 3
BD(10) 4
BD(11) 5
BD(12) 6
BD(13) 7
BD(14) 8
BD(15) 9
1
19
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
2
4
6
8
11
13
15
17
1
19
GND
F
U19
B1
B2
B3
B4
B5
B6
B7
B8
74ACT245
A1
A2
A3
A4
A5
A6
A7
A8
DIR
G
U26
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
74ACT244
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
18
17
16
15
14
13
12
11
18
16
14
12
9
7
5
3
D(0)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
BA(8)
BA(9)
BA(10)
BA(11)
BA(12)
BA(13)
BA(14)
BA(15)
G
G
H
2
4
6
8
11
13
15
17
1
19
2
BD(8)
3
BD(9)
BD(10) 4
BD(11) 5
BD(12) 6
BD(13) 7
BD(14) 8
BD(15) 9
1
19
A(16)
A(17)
A(18)
A(19)
GND
U16
B1
B2
B3
B4
B5
B6
B7
B8
74ACT245
A1
A2
A3
A4
A5
A6
A7
A8
DIR
G
U25
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
74ACT244
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
18
17
16
15
14
13
12
11
18
16
14
12
9
7
5
3
Shlomo Reches
PROJECT : 302 family ADS
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
BA(16)
BA(17)
BA(18)
BA(19)
I
DESCRIP :
BLOCK :
REV : ENG
Buffers
MOTOROLA INC.
I
J
SHEET
J
8
OF
18
K
K
1
2
8
7
6
5
4
3
For More Information On This Product,
Go to: www.freescale.com
2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
BD(0:15)
BA(1:23)
BRDL
BRDH
BWRL
BWRH
RMLCS
RMHCS
FLLCS
FLHCS
EPRCS
BD(0:15)
BA(1:23)
BRDL
BRDH
BWRL
BWRH
ORMLCS
ORMHCS
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
BA(8)
BA(9)
BA(10)
BA(11)
BA(12)
BA(13)
BA(14)
BA(15)
BA(16)
BA(17)
BA(18)
B
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
U21
MCM6229A
A0
A1
A2
A3
DQ0
A4
DQ1
A5
DQ2
A6
DQ3
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
U20
MCM6229A
A0
A1
A2
A3
A4
DQ0
A5
DQ1
A6
DQ2
A7
DQ3
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
13 G
12 E
15 W
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
BA(8)
BA(9)
BA(10)
BA(11)
BA(12)
BA(13)
BA(14)
BA(15)
BA(16)
BA(17)
BA(18)
13 G
12 E
15 W
B
16
17
18
19
16
17
18
19
BD(0)
BD(1)
BD(2)
BD(3)
BD(0)
BD(1)
BD(2)
BD(3)
C
C
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
BA(8)
BA(9)
BA(10)
BA(11)
BA(12)
BA(13)
BA(14)
BA(15)
BA(16)
BA(17)
BA(18)
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
U18
MCM6229A
A0
A1
A2
A3
DQ0
A4
DQ1
A5
DQ2
A6
DQ3
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
U17
MCM6229A
A0
A1
A2
A3
A4
DQ0
A5
DQ1
A6
DQ2
A7
DQ3
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
13 G
12 E
15 W
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
BA(8)
BA(9)
BA(10)
BA(11)
BA(12)
BA(13)
BA(14)
BA(15)
BA(16)
BA(17)
BA(18)
13 G
12 E
15 W
16
17
18
19
D
16
17
18
19
D
BD(4)
BD(5)
BD(6)
BD(7)
BD(4)
BD(5)
BD(6)
BD(7)
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
BA(8)
BA(9)
BA(10)
BA(11)
BA(12)
BA(13)
BA(14)
BA(15)
BA(16)
BA(17)
BA(18)
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
E
U15
MCM6229A
A0
A1
A2
A3
DQ0
A4
DQ1
A5
DQ2
A6
DQ3
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
U14
MCM6229A
A0
A1
A2
A3
A4
DQ0
A5
DQ1
A6
DQ2
A7
DQ3
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
13 G
12 E
15 W
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
BA(8)
BA(9)
BA(10)
BA(11)
BA(12)
BA(13)
BA(14)
BA(15)
BA(16)
BA(17)
BA(18)
13 G
12 E
15 W
E
16
17
18
19
16
17
18
19
BD(8)
BD(9)
BD(10)
BD(11)
BD(8)
BD(9)
BD(10)
BD(11)
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
F
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
BA(8)
BA(9)
BA(10)
BA(11)
BA(12)
BA(13)
BA(14)
BA(15)
BA(16)
BA(17)
BA(18)
U12
MCM6229A
A0
A1
A2
A3
DQ0
A4
DQ1
A5
DQ2
A6
DQ3
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
16
17
18
19
16
17
18
19
BD(12)
BD(13)
BD(14)
BD(15)
BD(12)
BD(13)
BD(14)
BD(15)
G
G
BA(19)
BA(18)
BA(17)
BA(16)
BA(15)
BA(14)
BA(13)
BA(12)
BA(11)
BA(10)
BA(9)
BA(8)
BA(7)
BA(6)
BA(5)
BA(4)
BA(3)
BA(2)
BA(1)
256K word option
U11
MCM6229A
A0
A1
A2
A3
A4
DQ0
A5
DQ1
A6
DQ2
A7
DQ3
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
13 G
12 E
15 W
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
13 G
12 E
15 W
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
BA(8)
BA(9)
BA(10)
BA(11)
BA(12)
BA(13)
BA(14)
BA(15)
BA(16)
BA(17)
BA(18)
F
1
30
2
3
29
28
4
25
23
26
27
5
6
7
8
9
10
11
12
U6
H
21
20
19
18
17
15
14
13
22
24
31
BD(7)
BD(6)
BD(5)
BD(4)
BD(3)
BD(2)
BD(1)
BD(0)
BA(19)
BA(18)
BA(17)
BA(16)
BA(15)
BA(14)
BA(13)
BA(12)
BA(11)
BA(10)
BA(9)
BA(8)
BA(7)
BA(6)
BA(5)
BA(4)
BA(3)
BA(2)
BA(1)
1
30
2
3
29
28
4
25
23
26
27
5
6
7
8
9
10
11
12
U7
I
29F040
A18 O7
A17 O6
A16 O5
A15 O4
A14 O3
A13 O2
A12 O1
A11 O0
A10
A9
A8
A7
A6
A5
A4
A3
A2 CE
A1 OE
A0 WE
21
20
19
18
17
15
14
13
22
24
31
BD(15)
BD(14)
BD(13)
BD(12)
BD(11)
BD(10)
BD(9)
BD(8)
BLOCK :
REV :
29F040
A18 O7
A17 O6
A16 O5
A15 O4
A14 O3
A13 O2
A12 O1
A11 O0
A10
A9
A8
A7
A6
A5
A4
A3
A2 CE
A1 OE
A0 WE
302 family ADS
ENG
J
BA(1)
BA(2)
BA(3)
BA(4)
BA(5)
BA(6)
BA(7)
BA(8)
BA(9)
BA(10)
BA(11)
EPRCS
BRDL
BWRL
SHEET
J
11
10
9
8
7
6
5
4
29
28
24
23
25
31
Memory block
MOTOROLA INC.
PROJECT :
DESCRIP :
Shlomo Reches
I
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
OF
D0
D1
D2
D3
D4
D5
D6
D7
U8
AT28C16PGA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
OE
WE
9
13
14
15
18
19
20
21
22
18
K
BD(0)
BD(1)
BD(2)
BD(3)
BD(4)
BD(5)
BD(6)
BD(7)
K
1
2
8
7
6
5
4
3
For More Information On This Product,
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2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
INTACK
ADSGRP
B
C
ADSSEL
ADSBRK
HSTREQ
HSTACK
INTACK
HSTBRK
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
GND
D
U1
A1
A2
A3
A4
G
LS244_4
18
Y1
16
Y2
14
Y3
12
Y4
2
4
6
8
1
GND
E
2
R1
E
2K
GND
RN1 4.7K
VCC
14
GND
ADSREQ
ADSACK
ADSINT
BHSTVCC
BHSTREQ
BHSTEN
BADSBRK
BD(0)
BD(1)
BD(2)
BD(3)
BD(4)
BD(5)
BD(6)
BD(7)
3
4
5
6
7
8
9
10
2
23
1
GND
F
U5
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1A1
1A2
1A3
1A4
1G
2A1
2A2
2A3
2A4
2G
9
Y1
7
Y2
5
Y3
3
Y4
74LS244
U1
A1
A2
A3
A4
G
B0
B1
B2
B3
B4
B5
B6
B7
OEAB
EAB
LEAB
LS244_4
F
74F543
U4
A0
A1
A2
A3
A4
A5
A6
A7
OEBA
EBA
LEBA
11
13
15
17
19
18
16
14
12
U2
2
4
6
8
11
13
15
17
1
19
14
U36
74LS05_PWR
8
INTACK
ADSGRP
HSTACK
ADSALL
18
16
14
12
9
7
5
3
9
U33
74ACT244
VCC
SET
Q
8
74ACT74
CLK
Q
CLR
D
10
HSTACK
ADSALL
12
9
7
5
3
BD(8)
BD(9)
BD(10)
BD(11)
BD(12)
BD(13)
BD(14)
BD(15)
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
9
D
ADSRST
ADIA2
ADIA1
ADIA0
(HSTBRK)
11
13
C
ADSRST
ADIA2
ADIA1
ADIA0
ADSREQ
ADSACK
ADSINT
ADSSEL
HSTREQ
HSTVCC
HSTEN
ADSBRK
BD(0:15)
ADSRD
ADSWR
HSTRD
PWR5V
BD(9)
ADSWR
BRKCLR
B
2
4
6
8
1
11
13
15
17
19
22
21
20
19
18
17
16
15
13
11
14
GND
GND
G
BINTACK
BADSGRP
BHSTACK
BADSALL
RN3 22
BADSRST
BADIA2
BADIA1
BADIA0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BHSTVCC
G
H
RN2 22
16
15
14
13
12
11
10
9
I
GND
BINTACK
GND
GND
BADSGRP
BHSTACK
GND
BADSALL
GND
GND
BADSRST
BADIA2
GND
BADIA1
BADIA0
BHSTVCC
BHSTREQ
BHSTVCC
BADSREQ
BHSTVCC
BADSACK
BHSTEN
BADSINT
GND
HSTBRK
GND
BADSBRK
GND
BPD0
BPD1
BPD2
BPD3
BPD4
BPD5
BPD6
BPD7
BLOCK :
REV :
1
2
3
4
5
6
7
8
302 family ADS
J
1
20
2
21
3
22
4
23
5
24
6
25
7
26
8
27
9
28
10
29
11
30
12
31
13
32
14
33
15
34
16
35
17
36
18
37
19
SHEET
J
ADI port interface
ENG
MOTOROLA INC.
PROJECT :
DESCRIP :
Shlomo Reches
I
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
10
P1
OF
18
K
K
1
2
8
7
6
5
4
3
For More Information On This Product,
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2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
B
C
PB(11)
DTACK
BA(1:23)
BD(0:7)
BR_W
UARTCS
RST
HSTACK
HSTREQ
HSTEN
INTACK
D
VCC
BA(1)
BA(2)
BA(3)
BA(4)
BD(0)
BD(1)
BD(2)
BD(3)
BD(4)
BD(5)
BD(6)
BD(7)
E
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
F
VCC
C64
10uF
G
C65
10uF
10uF
C59
VCC
10uF
C60
G
20
MC145407
C1P
C1P
C2P
1
3
C2N
4
VSS
6
TX1
5
RX1
8
TX2
7
RX2
10
TX3
9
RX3
1
3
C2N
4
VSS
6
TX1
5
RX1
8
TX2
7
RX2
10
TX3
9
RX3
C2P
MC145407
U29
18
C1N
17
VDD
15
DI1
16
DO1
13
DI2
14
DO2
11
DI3
12
DO3
20
18
C1N
17
VDD
15
DI1
16
DO1
13
DI2
14
DO2
11
DI3
12
DO3
U28
H
-
ENG :
CHK :
H
C62
10uF
GND
C63
10uF
C58
10uF
I
P2
CD
DSR
TX
RTS
RX
CTS
DTR
NC
GND
TX
DSR
RTS
RX
CTS
DTR
NC
GND
J
J
Serial ports
SHEET
Terminal port (DTE)
1
6
2
7
3
8
4
9
5
GND
P3
Host port (DCE)
1
6
2
7
3
8
4
9
5
GND
ENG
MOTOROLA INC.
BLOCK :
REV :
DESCRIP :
302 family ADS
I
Shlomo Reches
GND
C57
10uF
+
+
PROJECT :
-
-
Freescale Semiconductor, Inc...
32
14
31
15
30
16
29
17
13
TxDB
11
RxDB
33
TxDA
35
RxDA
MC68681FN
2
10
RS1
DTACK
4
24
RS2
IRQ
6
RS3
7
RS4
28
18
27
19
26
20
25
21
D0
D1
D2
D3
D4
D5
D6
D7
9
R/W
39
CS
38
RESET
41
IACK
8
5
40
3
43
42
IP0
IP1
IP2
IP3
IP4
IP5
36
X1/CLK
37
X2
U30
F
+
+
(PB11 is a parallel I/O with interrupt capability)
C81
15pF
Y2
3.6864MHz
GND
ADSACK
EEPWREN
C80
4.7pF
ADSACK
EEPWREN
ADSINT
ADSREQ
NR_DE
E
ADSINT
ADSREQ
NR_DE
D
-
11
OF
18
K
K
8
7
6
5
4
3
1
C
+
1
B
-
+
2
A
For More Information On This Product,
Go to: www.freescale.com
+
-
+
-
2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
B
B
C
PCVCC
C75
10uF
C
+
GND
D
D
PCVCC
A(20)
A(22)
PCCE1
PCOE
PDI(14)
PA(15)
PDI(11)
PCA4
PDI(10)
PDI(8)
PCD1
IOIS16
PA(3)
PA(5)
PA(7)
PA(14)
PCWAIT
PCREG
PCSTSCHG
PA(1)
(PCD4)
(PCD6)
(PCCE1)
(PCOE)
(PCA9)
(PCA13)
(PCWE)
‘VCC
(PCA16)
(PCA12)
(PCA6)
(PCA4)
(PCA2)
(PCA0)
(PCD1)
(IOIS16)
GND
(PCD11)
(PCD13)
(PCD15)
(PCRFRSH)
(PCIOWR)
(PCA18)
(PCA20)
VCC
(PCA22)
(PCA24)
RFU
(PCWAIT)
(PCREG)
(PCSTSCHG)
(PCD9)
(PCCD2)
E
GND
E
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
P4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
F
GND
F
(PCD3)
(PCD5)
(PCD7)
(PCA10)
(PCA11)
(PCA8)
(PCA14)
(PCRDY)
(PCVPP1)
(PCA15)
(PCA7)
(PCA5)
(PCA3)
(PCA1)
(PCD0)
(PCD2)
GND
(PCCD1)
(PCD12)
(PCD14)
(PCCE2)
(PCIORD)
(PCA17)
(PCA19)
(PCA21)
(PCVPP2)
(PCA23)
(PCA25)
(PCRST)
(PCIPACK)
(PCSPKR)
(PCD8)
(PCD10)
GND
PCD3
A(21)
A(23)
PB(4)
PB(0)
PDI(13)
PCRDY
PDI(12)
PCA5
PCA3
PDI(9)
PCD0
PCD2
PA(4)
PA(6)
PB(1)
PA(13)
PCIPCK
PB(2)
PCRST
PA(0)
PA(2)
G
U31
74ACT08
4
6
5
G
H
14
12
4.7K
RN7
PDI(0:15)
A(1:23)
VCC
14
6
4.7K
RN8
PB(0:11)
7
14
4.7K
RN8
PA(0:15)
Shlomo Reches
PROJECT : 302 family ADS
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
I
DESCRIP :
BLOCK :
REV : ENG
J
SHEET
J
PCMCIA connector
MOTOROLA INC.
I
12
OF
18
K
K
1
2
8
7
6
5
4
3
For More Information On This Product,
Go to: www.freescale.com
2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
C4
0.1uF
C29
0.1uF
C66
0.1uF
C69
0.1uF
C23
0.1uF
C3
0.1uF
10uF
C55
+
-
C53
0.1uF
C71
0.1uF
C22
0.1uF
B
C5
0.1uF
C40
0.1uF
C50
0.1uF
C16
0.1uF
10uF
C18
+
-
B
C6
0.1uF
C35
0.1uF
C52
0.1uF
C74
0.1uF
C20
0.1uF
C8
0.1uF
10uF
C33
+
-
C48
0.1uF
C86
0.1uF
C19
0.1uF
C
C9
0.1uF
C25
0.1uF
C51
0.1uF
C26
0.1uF
C68
0.1uF
C
C11
0.1uF
C15
0.1uF
C70
0.1uF
C27
0.1uF
C56
0.1uF
C12
0.1uF
C42
0.1uF
C61
0.1uF
C36
0.1uF
C34
0.1uF
C13
0.1uF
C30
0.1uF
C76
0.1uF
C31
0.1uF
C72
0.1uF
D
D
C10
0.1uF
C24
0.1uF
C46
0.1uF
C17
0.1uF
C54
0.1uF
C41
0.1uF
C21
0.1uF
C67
0.1uF
C14
0.1uF
C49
0.1uF
C28
0.1uF
C32
0.1uF
E
C77
0.1uF
GND
E
C78
0.1uF
C85
0.1uF
VCC
GND
C83
0.1uF
F
C1
220uF/25V
+
-
F
D1
1N4148
RLY1
5V
G
2
U36
74LS05_PWR
4
U36
74LS05_PWR
6
U36
74LS05_PWR
G
14
14
14
1
3
5
D4
1SMC50AT3
GND
3
H
14
U35
74ACT00_PWR
1
1
2
3
1
1
GND
GND
2
I
16
VCC
10
12
Q
A
9
11
Q
B
13
RST
14
RX/CX
0.1uF
C84
U37
74HC4538_PWR
GND
2
2
D3
MBRD620CT
J4
J5
GND
I
12
14
13
Power input
J
J
PCVCCEN
PWR5V
5A
10K
R18
PCVCC
GND
F1
1
2
3
2
P10
VCC
3
1
OF
PCVCC
C47
0.1uF
13
GND
VCCPC
SHEET
VCC from the
PCMCIA connector
VCC supply
for the Pchip
PCMCIA block
GND
U38
74ACT14_PWR
R17
470K
DESCRIP :
BLOCK :
REV : ENG
MOTOROLA INC.
Ground hooks
Shlomo Reches
PROJECT : 302 family ADS
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
J3
18
K
K
1
2
8
7
6
5
4
3
For More Information On This Product,
Go to: www.freescale.com
2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
B
B
AS
C
D(0:15)
LDS
IAC
FC(0:2)
BGACK
UDS
OE (R/W)
A(1:23)
C
D(14)
D(12)
D(10)
D(8)
D(6)
D(4)
D(2)
D(0)
LDS
FC(2)
FC(0)
UDS
OE
A(22)
A(20)
A(18)
A(16)
1
3
5
7
9
11
13
15
17
19
1
3
5
7
9
11
13
15
17
19
D
D
P7
P6
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
D(15)
D(13)
D(11)
D(9)
D(7)
D(5)
D(3)
D(1)
GND
BGACK
FC(1)
IAC
LDS
A(23)
A(21)
A(19)
A(17)
GND
E
E
F
F
UDS
A(1:23)
BERR
CLKO
HALT
BG
AS
IPL(0:2)
CS(0:3)
G
G
UDS
A(14)
A(12)
A(10)
A(8)
A(6)
A(4)
A(2)
A(0)
CLKO
CS(2)
BERR
HALT
CS(1)
IPL(1)
BG
AS
1
3
5
7
9
11
13
15
17
19
1
3
5
7
9
11
13
15
17
19
H
P5
P8
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
A(15)
A(13)
A(11)
A(9)
A(7)
A(5)
A(3)
A(1)
GND
CS(3)
AVEC
RST
DTACK
BR
IPL(2)
IPL(0)
CS(0)
I
AVEC
RST
DTACK
BR
BLOCK :
REV :
GND
302 family ADS
ENG
J
SHEET
J
14
Logic analyzer connectors.
MOTOROLA INC.
PROJECT :
DESCRIP :
Shlomo Reches
I
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
OF
18
K
K
1
2
8
7
6
5
4
3
For More Information On This Product,
Go to: www.freescale.com
2
8
7
6
5
4
3
Freescale Semiconductor, Inc.
A
B
B
C
C
P11
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
D
GND
D
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
PB(8)
PB(9)
PB(10)
PB(11)
PDI(8)
PDI(9)
PDI(10)
PDI(11)
PDI(12)
PDI(13)
PDI(14)
RXD1
TXD1
CD1
CTS1
RTS1
E
E
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
GND
PCD0
PCD1
PCD2
PCD3
PCA3
PCA4
PCA5
PCRDY
PCOE
PCCE1
PCREG
PCWAIT
PCSTSCHG
F
F
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
CTS3
RTS3
CD3
TCLK1
RCLK1
BRG1
PA(0)
PA(1)
PA(2)
PA(3)
PA(4)
PA(5)
PA(6)
PA(7)
PA(8)
PA(9)
PA(10)
PA(11)
PA(12)
PA(13)
PA(14)
PA(15)
G
GND
G
PB(0:11)
PA(0:15)
PDI(0:15)
H
Shlomo Reches
PROJECT : 302 family ADS
ENG :
CHK :
H
Freescale Semiconductor, Inc...
1
A
I
DESCRIP :
BLOCK :
REV : ENG
J
SHEET
J
15
OF
Logic analyzer expansion connector
MOTOROLA INC.
I
18
K
K
1
2
8
7
6
5
4
3
For More Information On This Product,
Go to: www.freescale.com
2
3
8
7
6
5
4
Freescale Semiconductor, Inc.
A
B
B
C
C
P12
D
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
D
VCC
GND
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
PB(8)
PB(9)
PB(10)
PB(11)
PDI(8)
PDI(9)
PDI(10)
PDI(11)
PDI(12)
PDI(13)
PDI(14)
RXD1
TXD1
CD1
CTS1
RTS1
E
E
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
GND
EXTNMI
PCD0
PCD1
PCD2
PCD3
PCA3
PCA4
PCA5
PCRDY
PCOE
PCCE1
F
PCREG
PCWAIT
PCSTSCHG
BCLR
RMC
DISCPU
F
G
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
G
GND
BRG1
PA(0)
PA(1)
PA(2)
PA(3)
PA(4)
PA(5)
PA(6)
PA(7)
PA(8)
PA(9)
PA(10)
PA(11)
PA(12)
PA(13)
PA(14)
PA(15)
RCLK1
TCLK1
CTS3
RTS3
CD3
VCC
H
I
BLOCK :
REV :
PB(0:11)
PDI(0:15)
PA(0:15)
302 family ADS
ENG
J
SHEET
J
16
Expansion connector
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A
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18
K
K
1
2
8
7
6
5
4
3
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3
8
7
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A
B
B
C
C
D
P9
D
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
GND
A(7)
A(4)
A(9)
A(14)
A(19)
A(16)
A(21)
FC(2)
RMC
CS(3)
PB(3)
IAC
PB(1)
FC(1)
D(14)
D(11)
OE (R/W)
D(6)
DTACK
BERR
IPL(1)
IPL(2)
PA(15)
BGACK
FRZ
PA(13)
BG
E
E
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
GND
F
A(1)
A(2)
A(5)
A(10)
A(15)
A(12)
A(17)
A(22)
FC(0)
CS(0)
PB(11)
PB(10)
PB(2)
PB(8)
PB(4)
UDS
D(10)
D(13)
AS
D(9)
D(2)
AVEC
IPL(0)
BR
EXTAL
RST
PA(12)
D(3)
BUSW
F
G
G
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
GND
A(3)
A(6)
A(11)
A(8)
A(13)
A(18)
A(23)
A(20)
CS(1)
CS(2)
PB(6)
PB(5)
PB(7)
PB(9)
PB(0)
D(15)
D(12)
LDS
D(8)
D(7)
D(1)
CLKO
D(5)
BCLR
D(4)
D(0)
HALT
PA(14)
H
D(0:15)
IPL(0:2)
PA(0:15)
A(1:23)
FC(0:2)
CS(0:3)
PB(0:11)
VCC
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A
I
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BLOCK :
J
SHEET
J
Expansion connector
REV : ENG
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K
K
1
2
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7
6
5
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3
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A
B
PB(0:11)
IPL(0:2)
B
AVEC
OE
BERR
HALT
AS
BR
BGACK
UDS
DTACK
CTS3
LDS
PB(11)
CD3
TCLK1
RCLK1
RXD1
EXTNMI
BCLR
FRZ
CD1
CTS1
IPL(0)
IPL(1)
IPL(2)
C
C
14
14
14
14
7
14
14
2
14
14
8
D
14
14
3
14
14
2
14
14
13
14
14
12
14
14
12
14
14
11
VCC
14
14
VCC
1
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
14
10
RN5 RN5 RN4 RN7 RN5 RN4 RN4 RN5 RN5 RN4 RN5 RN7
5
14
5
8
1
6
4
9
13
4
2
1
RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN5 RN5 RN5
11
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
10
D
E
E
F
DISCPU
PB(5)
3 state control
signal (TRIS), on
the Pchip.
RST
PCA3
BERR
PA(7)
(BOOT)
F
GND
GND
VCC
VCC
VCC
R7
2K
R3
10K
R4
1K
R24
1M
10K
R25
G
GND
G
4
5
1
3
14
2
10
H
PWR5V
I
J
SPARE
1
2
3
4
5
6
7
8
9
10
11
13
U9
22V10A
CK/I1
I2
I/O10
I3
I/O9
I4
I/O8
I5
I/O7
I6
I/O6
I7
I/O5
I8
I/O4
I9
I/O3
I10
I/O2
I11
I/O1
I12
U39
22V10A
CK/I1
I2
I/O10
I3
I/O9
I4
I/O8
I5
I/O7
I6
I/O6
I7
I/O5
I8
I/O4
I9
I/O3
I10
I/O2
I11
I/O1
I12
J
23
22
21
20
19
18
17
16
15
14
23
22
21
20
19
18
17
16
15
14
18
PullUps and spare gates.
SHEET
SPARE
1
2
3
4
5
6
7
8
9
10
11
13
BLOCK :
REV :
U38
74ACT14_PWR
4
U38
74ACT14_PWR
14
14
6
U35
74ACT00_PWR
14
9
8
10
U35
74ACT00_PWR
14
14
12
11
13
U35
74ACT00_PWR
11
U36
74LS05_PWR
14
12
3
74ACT08
U31
U36
74LS05_PWR
13
1
2
302 family ADS
ENG
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MOTOROLA
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1.0 M68302 FADS Addendum to CPU32BUG Debug Monitor User's
Manual:
1.1
Overview
The following is an addendum to the CPU32BUG Debug Monitor User's Manual. The CPU32Bug debugger (V0.4) for
the M68302 Family Application Development System is almost compatible with the M68CPU32BUG Debug Monitor.
The CPU32BUG Debug Monitor User's Manual is the primary documentation. The version of the CPU32Bug that runs
on the M68302 FADS board is referred to as the FADSbug. The CPU32Bug or FADSbug is sometimes used as abbreviations to refer to the debugger that runs on the M68302 FADS board.
NOTE:
The debugger prompt on the M68302FADS board will indicate which part is plugged into the board:
LCIMPbug> is used for the MC68LC302
PCHIPbug> is used for the MC68PM302
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ENIMPbug> is used for the MC68EN302
IMPbug> is used for the MC68302.
NOTE:
1.2
The FADSbug debugger uses locations through 0x8000. You should always start any programs you
run in DRAM from address 0x8000.
Changes to the FADSbug
There are some enhancements and some changes to the FADSbug software and a brief summary is included below.
1.2.1
1.2.1.1
Features that are in M68CPU32Bug but not currently on the FADSbug version running on the
M68302 FADS board
SD:
The SD - Switch Directories feature is not included with the FADSbug version running on the M68302 FADS board.
1.2.1.2
PA/NOPA:
The Printer Attach/Detach feature is not included with the FADSbug version running on the M68302 FADS board.
1.2.1.3
PF:
The Port Format feature is not included with the FADSbug version running on the M68302 FADS board.
1.2.1.4
TM:
The Transparent Mode feature is not included with the FADSbug version running on the M68302 FADS board.
page 1
Addendum to the CPU32Bug Debug Monitor User’s Manual
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1.3
Oct 17, 1995
Enhancements to CPU32Bug (FADSbug) running on the MC68360FADS board
1.3.1
HELP Command:
The enhancement consists in adding the syntax of each individual help.
For example:
>HE GT
GT
Go to Temporary Breakpoint
GT <ADDR> [:<COUNT>]
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The syntax is taken as is from the Manual. This enhancement is not
displayed when the full list of help commands is requested ( i.e., when
you type: HE )
1.3.2
Macro Expansion Listing Status (MALS):
This allows the user to interrogate whether the debugger Macro
Expansion is currently on or off (the output is: ON or OFF). Remember that MAL and
NOMAL set/reset the macro expansion.
1.3.3
MAP Command
This is a menu driven direct interface to the registers of the MC68XX302 Family Peripherals.
1.3.3.1
Exit
The board exits the user-interface module and enters the FADSbug monitor/debugger.
1.3.3.2
Flip r/w
When set (a highlighted '+' sign appears), chosen structures are read and then written;
if not set, the structures are just read.
1.3.3.3
SCC tx
The two SCC transmit BD tables are displayed in a concise format.
1.3.3.4
SCC rx
The two SCC transmit BD tables are displayed in a concise format.
1.3.3.5
General Purpose DMA
All registers of the general purpose DMA are displayed. These are the DMA mode
register, status register, source and destination addresses, count and FC registers.
page 2
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1.3.3.6
Oct 17, 1995
Chip Select
All registers of the chip select block are displayed. These are the base and option
registers for each of the four chip select areas.The debugger gives you the felixibility to
write to all registers and chip selects(CS) . Be careful not to write to an area you do not
want to change. For example, you can modify CS0, CS!, and CS2, however it is suggested that you do not modify these chip selects on the FADS board because these chip
selects are used to decode memory on the FADS board.
1.3.3.7
Parallel I/O
All registers of the parallel I/O block are displayed. These are the control, direction
and data registers for both parallel port A, B and D (D in the Pchipbug only).
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1.3.3.8
Interrupt Controller
All registers of the interrupt controller block are displayed. These are the interrupt
mode, pending, in-service and mask registers.
1.3.3.9
Timers
The registers of the timer block are displayed. They are the mode, status, reference,
capture and count registers for timers 1 and 2, and the reference and count registers
for the watchdog timer.
1.3.3.10
SCC1 registers
This option displays all the registers associated with SCC channel 1. These are the
channel's configuration, mode, sync, event, mask, and status registers
1.3.3.11
SCC2 registers
This option displays all the registers associated with SCC channel 2. These are the
channel's configuration, mode, sync, event, mask, and status registers
1.3.3.12
SCC3 registers (Pchipbug ONLY)
This option displays all the registers associated with SCC channel 3. These are the
channel's configuration, mode, sync, event, mask, and status registers
1.3.3.13
PCMCIA registers (Pchipbug ONLY)
This option displays all the registers associated with PCMCIA interface.
1.3.3.14
PCMCIA CARD registers (Pchipbug ONLY)
This option displays all the registers associated with PCMCIA Card
Configuration interface.
1.3.3.15
16550 registers (Pchipbug ONLY)
This option displays all the registers associated with 16550 emulation.
1.3.3.16
MC68XX302 Commands
This option may be used to writing commands directly to the command register of the
MC68XX302. By entering '?', a help screen containing all defined commands is displayed;
this screen may be scrolled and the desired command selected from this menu.
page 3
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1.3.3.17
Oct 17, 1995
SCP block
This option displays the data structures associated with the SCP
(Serial Communications Port).
1.3.3.18
SMC block
This option displays the data structures associated with the SMC
(Serial Management Controller).
1.3.3.19
Serial interface
This option displays the data structures associated with the serial
interface block.
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1.3.3.20
DRAM Refresh
This option displays the parameters associated with this block. Note that they are overlaid
on the last two buffer descriptors in the SCC2 Transmit BD Table. If you wish to use the
DRAM Refresh Controller, you must only use up to 6 BD's in this table
1.3.4
Symbols:
The user can define (currently up to 30) symbols which are equated to
values of expressions, in the following manner:
SYM [<symbol>] [<expression>]
NOSYM [<symbol>]
Options:
(1) SYM
displays all defined symbols and their value both in
hexadecimal and in decimal).
(2) SYM <symbol>
displays the symbol and its value.
(3) SYM <symbol> <expression>
evaluates the expression and gives its value to the
symbol.
Usage:
The symbols can be used at the debugger's command level
and with the in-line assembler.
The symbol name is limited to 30 characters in length.
Example:
(1) FADSbug> SYM DPRBASE 20000
FADSbug> SYM REGBASE DPRBASE+1000
FADSbug> SYM PEPAR REGBASE+16
FADSbug> md PEPAR
(2) FADSbug> mm 410;di
00000410 1000 move.b d0,d0 ? move.l #pepar, d0
FADSbug>md 410:1 ; di
00000410 203c0002 1016 MOVE.L #$21016,D0
page 4
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1.3.5
Oct 17, 1995
Reprogramming the Flash EPROMS:
There is a new command added that enables users to reprogram
the flash EPROMs on the FADS board.
The command is called LOF.
Syntax:
"LOF <range> <addr>[;B|W|L]"
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The LOF command loads from the memory addresses defined by
<range> to another place in the flash memory, beginning at <addr>.
The option field is only allowed when <range> is specified using a
count. In this case, the B, W, or L defines the size of data to
which the count is referring. For example, a count of four with
an option of L would mean to load four long words (or 16 bytes)
from DRAM to the <addr> location in flash. If the range beginning
address is greater than the end address an error results. An error
also results if an option field is specified without a count in
the range.
In order to erase and program the flash 12v is needed. If 12v is
not applied to the board an error results.
Example:
Suppose you want to load your own program to the flash starting
at address (0x200000). The program length is about 0x20000 bytes.
The program must be linked to address 0x200000. The next step is
to load that program to the DRAM. There are two ways to do it:
1) Use the parallel port (pdl)
or
2) Use the serial port. (lo)
Since the program was linked to 0x200000 you must use the LO
command (serial load) or the PDL command ( parallel load) with
their offset option to load it to an address in the DRAM. For
example with the parallel load the command executed is:
> psrec -sub 1F0000 program.srx 100
The last step is to type the LOF command. For example if the
program was loaded to 0x10000(DRAM address) then the
starting address location of the program is at 0x200000, so
the ending address would be approximately 0x220000. The
starting address of flash memory is 200000, so the LOF command is:
> lof 10000 30000 200000
1.4
1.4.1
Changes to the CPU32Bug running on the M68360FADS board
Macros:
The user can define 8 macros of 128 chars each, instead of an unlimited
number of macros when the total number of characters is only 512 chars.
page 5
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1.4.2
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Oct 17, 1995
Addressing Modes:
There have been some minor changes in the assembler addressing modes
format.
The following addressing modes :
• An+Xn+bd
•.PC+Xn+addr
can be represented in the CPU32Bug in the two following syntaxes:
I: (bd,An,Xi) - (addr,PC,Xi)
II: bd(An,Xi) - addr(PC,Xi)
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In the CPU32Bug running on the M68360FADS board (FADSbug), only the second
syntax is acceptable.
The CPU32Bug running on the M68360FADS board also allows you to
skip or omit entries with the following addressing modes:
• Address register indirect with index, base displacement.
• Program counter indirect with index, base displacement.
The M68CPU32BUG does not.
1.5
Differences between 302bug and CPU32bug compliant debuggers:
The TRAP routines are different fromthe 302bug to the new debuggers (LCIMPbug, PCHIPbug, IMPbug, and ENIMPbug). The TRAP #15 handler which allows system calls from the user programs has a different format than for
302bug. Refer to the chapter on System Calls in the CPU32 Debug Monitor User’s Manual for details on how to format
the TRAP command in the user program.
1.6
Chip Selects and Registers
The debugger gives you the felixibility to write to all registers and chip selects(CS) . Be careful not to write to an area
you do not want to change. For example, you can modify CS0, CS!, and CS2, however it is suggested that you do not
modify these chip selects on the FADS board because these chip selects are used to decode memory on the FADS
board.
page 6
Addendum to the CPU32Bug Debug Monitor User’s Manual
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