NXP MC68302 Integrated Multi-Protocol Processor Reference Manual

Freescale Semiconductor, Inc.
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MC68302UMADD33V
MC68302
Addendum to
MC68302 Integrated Multiprotocol Processor
User Manual
Freescale Semiconductor, Inc...
July 19, 2000
This addendum to the initial release of the MX68302UM/AD User’s Manual and provides information of 3.3v
operation not included in the original document.
6.0 ELECTRICAL CHARACTERISTICS
The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the clock (CLKO
pin) and possibly to one or more other signals.
6.1 MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage
VDD
- 0.3 to + 7.0
V
Input Voltage
Vin
- 0.3 to + 7.0
V
Operating Temperature Range
TA
0 to 70
- 40 to 85
°C
- 55 to + 150
°C
MC68302
MC68302C
Tstg
Storage Temperature Range
This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric fields; however, it is advised
that normal precautions be taken
to avoid application of any voltage
higher than maximum-rated voltages to his high-impedance circuit.
Reliability of operation is enhanced if unused inputs are tied to
an appropriate logic voltage level
(e.g., either GND or VDD)
6.2 THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance for PGA
Thermal Resistance for CQFP
Thermal Resistance for PQFP
Symbol
Value
Unit
θJA
25
°C/W
θJC
2
°C/W
θJA
40
°C/W
θJC
15
°C/W
θJA
42
°C/W
θJC
20
°C/W
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Revision 0.1
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TJ = TA + (PD ⋅ A)
PD = (VDD ⋅ IDD) + PI/O
where:
PI/O is the power dissipation on pins.
For TA = 70°C and PI/O + 0 W, 16.67 MHz, 3.6 V, and CQFP package,
the worst case value of TJ is:
TJ = 70°C + (3.6V ⋅ 25mA ⋅ 40°C/W) = 73.6C
6.3 POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can be obtained from:
TJ
=
TA + (PD • θJA)(1)
Freescale Semiconductor, Inc...
where:
TA
θJA
=
=
PD
=
PINT =
PI/O =
Ambient Temperature, °C
Package Thermal Resistance, Junction to Ambient, °C/W
PINT + PI/O
IDD x VDD, Watts—Chip Internal Power
Power Dissipation on Input and Output Pins—User Determined
For most applications PI/O < 0.3 • PINT and can be neglected.
If PI/O is neglected, an approximate relationship between PD and TJ is
PD
=
K ÷ (TJ + 273°C)(2)
Solving equations (1) and (2) for K gives:
K
=
PD • (TA + 273°C) + θJA • PD2(3)
where K is a constant pertaining to the particular part. K can be determined from equation
(3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD
and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
6.4 POWER DISSIPATION
Characteristic
Power Dissipation at 3.3V 16.67 MHz-Rev C.65µ (see Note 2)
Symbol
Typ
Max
Unit
PD
25
50
mA
NOTES:
2.The IMP is tested with the M68000 core executing, all three baud rate generators enabled and clocking at a rate of
64 kHz, and the two general-purpose timers running with a prescaler of 256. Power measurements are not
significantly impacted by baud rate generators or timers until their clocking frequency becomes a much more
sizable fraction of the system frequency than in these test conditions.
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6.5 DC ELECTRICAL CHARACTERISTICS
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Characteristic
Symbol
Min
Max
Unit
Input High Voltage (Except EXTAL)
VIH
2.0
VDD
V
Input Low Voltage (Except EXTAL)
VIL
VSS - 0.3
0.8
V
Input High Voltage (EXTAL)
VCIH
VDD*0.8
VDD
V
Input Low Voltage (EXTAL)
VCIL
VSS - 0.3
0.6
V
Input Leakage Current
IIN
—
20
µA
Input Capacitance All Pins
CIN
—
15
pF
Three-State Leakage Current (2.4/0.5 V)
ITSI
—
20
µA
Open Drain Leakage Current (2.4 V)
IOD
—
20
µA
Output High Voltage (IOH = 400 µA) (see Note)
VOH
2.4
—
V
Output Low Voltage
(IOL = 3.2 mA)
A1–A23, PB0–PB11, FC0–FC2, CS0–CS3
VOL
—
0.5
—
0.5
(IOL = 5.3 mA)
IAC, AVEC, BG, RCLK1, RCLK2, RCLK3,
TCLK1, TCLK2, TCLK3, RTS1, RTS2, RTS3,
SDS2, PA12, RXD2, RXD3, CTS2, CD2, CD3
DREQ, BRG1
AS, UDS, LDS, R/W, BERR
V
BGACK, BCLR, DTACK, DACK,
RMC, D0–D15, RESET
(IOL = 7.0 mA)
TXD1, TXD2, TXD3
—
0.5
(IOL = 8.9 mA)
DONE, HALT, BR (as output)
(IOL = 3.2 mA)
CLKO
—
—
0.5
0.4
Output Drive CLKO
Output Drive ISDN I/F (GCI Mode)
Output Drive All Other Pins
OCLK
OGCI
OALL
—
—
—
50
150
130
pF
pF
pF
Output Drive Derating Factor for CLKO of 0.030 ns/pF
Output Drive Derating Factor for CLKO of 0.035 ns/pF
Output Drive Derating Factor for All Other Pins 0.035 ns/pF
Output Drive Derating Factor for All Other Pins 0.055 ns/pF
OKF
OKF
OKF
OKF
20
50
20
130
50
130
130
220
pF
pF
pF
pF
Power
VDD
3.0
3.6
V
Common
VSS
0
0
V
NOTE: The maximum IOH for a given pin is one-half the IOL rating for that pin. For an IOH between 400 µA and IOL/2
mA, the minimum VOH is calculated as: VDD - (1 +.05 V/mA(IOH -.400 mA)).
NOTE: All AC specs are assume an output load of 130pf (except for CLKO).
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6.6 DC ELECTRICAL CHARACTERISTICS—NMSI1 IN IDL MODE
Characteristic
Symbol
Min
Max
Unit
Condition
Input Pin Characteristics: L1CLK, L1SY1, L1RXD, L1GR
Input Low Level Voltage
VIL
-10%
+ 20%
V
(% of VDD)
Input High Level Voltage
VIH
VDD - 20%
VDD + 10%
V
Input Low Level Current
IIL
—
± 10
µA
Vin = Vss
Input High Level Current
IIH
—
± 10
µA
Vin = VDD
Freescale Semiconductor, Inc...
Output Pin Characteristics: L1TXD, SDS1- SDS2, L1RQ
Output Low Level Voltage
VOL
0
1.0
V
IOL = 5.0 mA
Output High Level Voltage
VOH
VDD - 1.0
VDD
V
IOH = 400 µA
6.7 AC ELECTRICAL SPECIFICATIONS—CLOCK TIMING
(see Figure 6-1, Figure 6-2, Figure 6-3, and Figure 6-4)
16.67 MHz
Num.
Characteristic
Symbol
Min
f
8
tcyc
60
125
ns
Frequency of Operation
1
Clock Period (EXTAL) (See note 3)
Max
Unit
16.67 MHz
2, 3
Clock Pulse Width (EXTAL)
tCL, tCH
25
62.5
ns
4, 5
Clock Rise and Fall Times (EXTAL)
tCr, tCf
—
5
ns
5a
EXTAL to CLKO Delay (See Notes 1 and 2)
tCD
5
12
ns
NOTE:
1. CLKO loading is 50 pF max.
2. CLKO skew from the rising and falling edges of EXTAL will not differ from each other by more than 1 ns, if the
EXTAL rise time equals the EXTAL fall time.
3. You may not stop the clock input at any time.
1
EXTAL
2
VCIH = 4V
VCIL = 0.6V
3
5
4
5a
5a
CLKO
Figure 6-1. Clock Timing Diagram
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6.8 AC ELECTRICAL SPECIFICATIONS—IMP BUS MASTER CYCLES
(see Figure 6-2, Figure 6-3, Figure 6-4, and Figure 6-5))
16.67 MHz
Freescale Semiconductor, Inc...
Num.
Characteristic
Symbol
Min
Max
Unit
tCHFCADV
0
45
ns
6
Clock High to FC, Address Valid
7
Clock High to Address, Data Bus High Impedance (Maximum)
tCHADZ
—
50
ns
8
Clock High to Address, FC Invalid (Minimum)
tCHAFI
0
—
ns
9
Clock High to AS, DS Asserted (see Note 1)
tCHSL
3
30
ns
11
Address, FC Valid to AS, DS Asserted
(Read) AS Asserted Write (see Note 2)
tAFCVSL
15
—
ns
12
Clock Low to AS, DS Negated (see Note 1)
tCLSH
—
30
ns
13
AS, DS Negated to Address, FC Invalid (see
Note 2)
tSHAFI
15
—
ns
14
AS (and DS Read) Width Asserted (see
Note 2)
tSL
120
—
ns
14A
DS Width Asserted, Write (see Note 2)
tDSL
60
—
ns
15
AS, DS Width Negated (see Note 2)
tSH
60
—
ns
16
Clock High to Control Bus High Impedance
tCHCZ
—
50
ns
17
AS, DS Negated to R/W Invalid (see Note 2)
tSHRH
15
—
ns
18
Clock High to R/W High (see Note 1)
tCHRH
—
30
ns
20
Clock High to R/W Low (see Note 1)
tCHRL
—
30
ns
20A
AS Asserted to R/W Low (Write) (see Notes
2 and 6)
tASRV
—
10
ns
21
Address FC Valid to R/W Low (Write) (see
Note 2)
tAFCVRL
15
—
ns
22
R/W Low to DS Asserted (Write) (see Note
2)
tRLSL
30
—
ns
23
Clock Low to Data-Out Valid
tCLDO
—
30
ns
25
AS, DS, Negated to Data-Out Invalid (Write)
(see Note 2)
tSHDOI
15
—
ns
16.67 MHz
Num.
Characteristic
Symbol
Min
Max
Unit
26
Data-Out Valid to DS Asserted (Write) (see
Note 2)
tDOSL
15
—
ns
27
Data-In Valid to Clock Low (Setup Time on
Read) (see Note 5)
tDICL
7
—
ns
28
AS, DS Negated to DTACK Negated (Asynchronous Hold) (see Note 2)
tSHDAH
0
110
ns
29
AS, DS Negated to Data-In Invalid (Hold
Time on Read)
tSHDII
0
—
ns
30
AS, DS Negated to BERR Negated
tSHBEH
0
—
ns
31
DTACK Asserted to Data-In Valid (Setup
Time) (see Notes 2 and 5)
tDALDI
—
50
ns
32
HALT and RESET Input Transition Time
tRHr, tRHf
—
150
ns
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33
Clock High to BG Asserted
tCHGL
—
30
ns
34
Clock High to BG Negated
tCHGH
—
30
ns
35
BR Asserted to BG Asserted (see Note 11)
tBRLGL
2.5
4.5
clks
36
BR Negated to BG Negated (see Note 7)
tBRHGH
1.5
2.5
clks
37
BGACK Asserted to BG Negated
tGALGH
2.5
4.5
clks
37A
BGACK Asserted to BR Negated (see Note
8)
tGALBRH
10
1.5
ns/
clks
38
BG Asserted to Control, Address, Data Bus
High Impedance (AS Negated)
tGLZ
—
50
ns
39
BG Width Negated
tGH
1.5
—
clks
40
BGACK Asserted to Address Valid
tGALAV
15
—
ns
41
BGACK Asserted to AS Asserted
tGALASA
30
—
ns
44
AS, DS Negated to AVEC Negated
tSHVPH
0
50
ns
1.5
—
clks
46
BGACK Width Low
tGAL
47
Asynchronous Input Setup Time (see Note
5)
tASI
12
—
ns
48
BERR Asserted to DTACK Asserted (see
Notes 2 and 3)
tBELDAL
10
—
ns
53
Data-Out Hold from Clock High
tCHDOI
0
—
ns
55
R/W Asserted to Data Bus Impedance
Change
tRLDBD
0
—
ns
56
HALT/RESET Pulse Width (see Note 4)
tHRPW
10
—
clks
57
BGACK Negated to AS, DS, R/W Driven
tGASD
1.5
—
clks
BGACK Negated to FC
tGAFD
1
—
clks
BR Negated to AS, DS, R/W Driven (see
Note 7)
tRHSD
1.5
—
clks
BR Negated to FC (see Note 7)
tRHFD
1
—
clks
60
Clock High to BCLR Asserted
tCHBCL
—
30
ns
61
Clock High to BCLR High Impedance (See
Note 10)
tCHBCH
—
30
ns
57A
58
58A
16.67 MHz
Num.
Characteristic
Symbol
Min
Max
Unit
62
Clock Low (S0 Falling Edge during read) to
RMC Asserted
tCLRML
—
30
ns
63
Clock High (during write) to RMC Negated
tCHRMH
—
30
ns
64
RMC Negated to BG Asserted (see Note 9)
tRMHGL
—
30
ns
NOTES:
1. For loading capacitance of less than or equal to 50 pF, subtract 4 ns from the value given in the maximum
columns.
2. Actual value depends on clock period since signals are driven/latched on different CLKO edges. To calculate the
actual spec for other clock frequencies, the user may derive the formula for each specification. First, derive the
margin factor as: M = N(P/2) - Sa
where N is the number of one-half CLKO periods between the two events as derived from the timing diagram, P
is the rated clock period of the device for which the specs were derived (e.g., 60 ns with a 16.67-MHz device),
and Sa is the actual spec in the data sheet. Thus, for spec 14 at 16.67 MHz:
M = 5(60 ns/2) - 120 ns = 30 ns.
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Once the margin (M) is calculated for a given spec, a new value of that spec (Sn) at another clock frequency
with period (Pa) is calculated as:
Sn = N(Pa/2) - M
Thus for spec 14 at 12.5 MHz:
Sn = 5(80 ns/2) - 30 ns = 170 ns.
These two formulas assume a 50% duty cycle. Otherwise, if N is odd, the previous values N(P/2) and N(Pa/2)
must be reduced by X, where X is the difference between the nominal pulse width and the minimum pulse width
of the EXTAL input clock for that duty cycle.
3. If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is a
synchronous input using the asynchronous input setup time (#47).
4. For power-up, the MC68302 must be held in the reset state for 100 ms to allow stabilization of on-chip circuit. After
the system is powered up #56 refers to the minimum pulse width required to reset the processor.
5. If the asynchronous input setup (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup
time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the
following clock cycle.
6. When AS and R/W are equally loaded (±20%), subtract 5 ns from the values given in these columns.
7. The MC68302 will negate BG and begin driving the bus if external arbitration logic negates BR before asserting
BGACK.
8. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be
reasserted.
9. This specification is valid only when the RMCST bit is set in the SCR register.
10.Occurs on S0 of SDMA read/write access when the SDMA becomes bus master.
11.Specification may be exceeded during the TAS instruction if the RMCST bit in the SCR is set.
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S0
S1
S2
S3
S4
S5
S6
S7
CLKO
FC2–FC0
8
6
A23–A1
12
7
14
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AS
15
9
13
11
174
CS
151
150
175
152
173
LDS–UDS
18
17 176
R/W
47
28
DTACK
48
171
27
29
178
31
DATA IN
47
BERR / BR
(NOTE 2)
30
47
47
32
32
HALT / RESET
56
47
ASYNCHRONOUS
INPUTS (NOTE 1)
NOTES:
1. Setup time for the asynchronous inputs IPL2–IPL0 guarantees their recognition at the next falling edge of
the clock.
2. BR need fall at this time only to insure being recognized at the end of the bus cycle.
3. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts,
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall is linear between 0.8 volts and 2.0 volts.
Figure 6-2. Read Cycle Timing Diagram
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S0
S1
S2
S3
S4
S5
S6
S7
CLKO
FC2-FC0
8
6
A23-A1
12
7
14
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AS
15
9
13
11
174
CS
151
9
152
175
150
173
14A
LDS-UDS
20A
18
17
177
20
176
22
R/W
21
28
47
55
DTACK
26
7
53
23
48
172 25
DATA OUT
47
30
BERR / BR
(NOTE 2)
47
47
32
HALT / RESET
32
56
47
ASYNCHRONOUS
INPUTS (NOTE 1)
NOTES:
1. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts,
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall is linear between between 0.8 volt and 2.0 volts.
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge
of S2 (specification #20A)
3. Each wait state is a full clock cycle inserted between S4 and S5.
Figure 6-3. Write Cycle Timing Diagram
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S0
S1
S2
S3
S4 S5
S6
S7
S8
S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19
CLKO
12
AS
(NOTE 2)
(OUTPUT)
9
9
12
AS
(NOTE 3)
(OUTPUT)
62
63
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RMC
(OUTPUT)
9
UDS–LDS
(OUTPUT)
20
18
18
R/W
(OUTPUT)
DTACK
27
23
25
29
D15–D0
DATA IN
DATA OUT
INDIVISIBLE CYCLE
NOTES:
1. For other timings than RMC, see Figures 6-2 and 6-3.
2. RMCST = 0 in the SCR.
3. RMCST = 1 in the SCR.
4. Wait states may be inserted between S4 and S5 during the write cycle and between S16 and S17 during the read cycle.
5. Read-modify-write cycle is generated only by the TAS instruction.
Figure 6-4. Read-Modify-Write Cycle Timing Diagram
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35
33
38
41
46
34
37
37A
39
47
36
58
57
NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, AND IPL2–IPL0 guarantees their recognition
at the next falling edge of the clock.
CLKO
BG
(OUTPUT)
BGACK
(I/O)
BR
(INPUT)
STROBES
AND R/W
40
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58A
57A
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Figure 6-5. Bus Arbitration Timing Diagram
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6.9 AC ELECTRICAL SPECIFICATIONS—DMA (see Figure 6-6 and Figure 6-7)
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16.67 MHz
Num.
Characteristic
Symbol
Min
Max
Unit
80
DREQ Asynchronous Setup Time (see Note
1)
tREQASI
15
—
ns
81
DREQ Width Low (see Note 2)
tREQL
2
—
clks
82
DREQ Low to BR Low (see Notes 3 and 4)
tREQLBRL
—
2
clks
83
Clock High to BR Low (see Notes 3 and 4)
tCHBRL
—
30
ns
84
Clock High to BR High Impedance (see
Notes 3 and 4)
tCHBRZ
—
30
ns
85
BGACK Low to BR High Impedance (see
Notes 3 and 4)
tBKLBRZ
30
—
ns
86
Clock High to BGACK Low
tCHBKL
—
30
ns
87
AS and BGACK High (the Latest One) to
BGACK Low (when BG Is Asserted)
tABHBKL
1.5
2.5
+30
clks
ns
88
BG Low to BGACK Low (No Other Bus
Master) (see Notes 3 and 4)
tBGLBKL
1.5
2.5
+30
clks
ns
89
BR High Impedance to BG High (see Notes
3 and 4)
tBRHBGH
0
—
ns
90
Clock on which BGACK Low to Clock on
which AS Low
tCLBKLAL
2
2
clks
91
Clock High to BGACK High
tCHBKH
—
30
ns
92
Clock Low to BGACK High Impedance
tCLBKZ
—
30
ns
93
Clock High to DACK Low
tCHACKL
—
30
ns
94
Clock Low to DACK High
tCLACKH
—
30
ns
95
Clock High to DONE Low (Output)
tCHDNL
—
30
ns
96
Clock Low to DONE High Impedance
tCLDNZ
—
30
ns
97
DONE Input Low to Clock Low (Asynchronous Setup)
tDNLTCH
15
—
ns
NOTES:
1. DREQ is sampled on the falling edge of CLK in cycle steal and burst modes.
2. If #80 is satisfied for DREQ, #81 may be ignored.
3. BR will not be asserted while BG, HALT, or BERR is asserted.
4. Specifications are for DISABLE CPU mode only.
5. DREQ, DACK, and DONE do not apply to the SDMA channels.
6. DMA and SDMA read and write cycle timing is the same as that for the M68000 core.
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80
83
82
81
47
87
88
86
85
84
90
S1
89
S3
S4
S5
S6
S7
95
S0
SEE M68000 READ CYCLES FOR
ADDITIONAL BUS SIGNALS
AND TIMING.
S2
NOTES:
1. BR and BG shown above are only active in disable CPU mode; otherwise, they do not apply to the diagram.
2. Assumes the ECO bit in the CMR = 1.
3. For the case when DONE is an input, assumes ECO bit in the CMR = 1.
DONE
(I/O)
(NOTE 3)
DACK
(OUTPUT)
(NOTE 2)
R/W
(OUTPUT)
AS
(OUTPUT)
BGACK
(I/O)
BG
(INPUT)
NOTE 1
BR
(OUTPUT)
NOTE 1
DREQ
(INPUT)
CLKO
S0
S1
S3
S4
S5
S6
S7
92
93
97
96
94
SEE M68000 WRITE CYCLES FOR
ADDITIONAL BUS SIGNALS
AND TIMING.
S2
Freescale Semiconductor, Inc...
91
Freescale Semiconductor, Inc.
83
60
88
87
47
86
85
90
84
S1
89
S2
S4
S5
S6
S7
92
SEE M68000 READ/WRITE
CYCLES FOR ADDITIONAL
BUS SIGNALS AND TIMING.
S3
NOTES:
1. DRAM refresh controller timing is identical to SDMA timing.
2. BR and BG shown above are only active in disable CPU mode; otherwise they do not apply to the diagram.
AS
(OUTPUT)
BGACK
(I/O)
BG
(INPUT)
(NOTE 2)
BR
(OUTPUT)
(NOTE 2)
BCLR
(OUTPUT)
CLKO
S0
Freescale Semiconductor, Inc...
91
Freescale Semiconductor, Inc.
Figure 6-6. DMA Timing Diagram (IDMA)
Figure 6-7. DMA Timing Diagram (SDMA)
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Freescale Semiconductor, Inc.
6.10 AC ELECTRICAL SPECIFICATIONS—EXTERNAL MASTER
INTERNAL ASYNCHRONOUS READ/WRITE CYCLES
(see Figure 1 and Figure 6-8)
16.67 MHz
Freescale Semiconductor, Inc...
Num.
Characteristic
Symbol
Min
Max
Unit
100
R/W Valid to DS Low
tRWVDSL
0
—
ns
101
DS Low to Data-In Valid
tDSLDIV
—
30
ns
102
DTACK Low to Data-In Hold Time
tDKLDH
0
—
ns
103
AS Valid to DS Low
tASVDSL
0
—
ns
104
DTACK Low to AS, DS High
tDKLDSH
0
—
ns
105
DS High to DTACK High
tDSHDKH
—
45
ns
106
DS Inactive to AS Inactive
tDSIASI
0
—
ns
107
DS High to R/W High
tDSHRWH
0
—
ns
108
DS High to Data High Impedance
tDSHDZ
—
45
ns
108A
DS High to Data-Out Hold Time (see Note)
tDSHDH
0
—
ns
109A
Data Out Valid to DTACK Low
tDOVDKL
15
—
ns
NOTE: If AS is negated before DS, the data bus could be three-stated (spec 126) before DS is negated.
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DTACK
(OUTPUT)
D15-D0
(OUTPUT)
R/W
(INPUT)
UDS
LDS
(INPUT)
IAC
(OUTPUT)
AS
(INPUT)
A23-A1
(INPUT)
CLKO
(OUTPUT)
S1
129
114
110
S0
S2
103
S3
47
119
S4
Sw
Sw
109A
125
Sw
Sw
Sw
122
Sw
104
S5
Freescale Semiconductor, Inc...
105
108A
106
S6
S7
108
128
S0
124
120
Freescale Semiconductor, Inc.
Figure 1. External Master Internal Asynchronous Read Cycle Timing Diagram
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DTACK
(OUTPUT)
D15-D0
(INPUT)
R/W
(INPUT)
UDS
LDS
(INPUT)
IAC
(OUTPUT)
AS
(INPUT)
A23-A1
(INPUT)
CLKO
(OUTPUT)
S0
114
129
110
S1
S2
100
119
103
S3
S4
101
47
Sw
Sw
Sw
122
Sw
Sw
S4
102
104
S5
Freescale Semiconductor, Inc...
S6
105
S7
113
107
120
124
Freescale Semiconductor, Inc.
Figure 6-8. External Master Internal Asynchronous Write Cycle Timing Diagram
Freescale Semiconductor, Inc.
6.11 AC ELECTRICAL SPECIFICATIONS—EXTERNAL MASTER
INTERNAL SYNCHRONOUS READ/WRITE CYCLES
(see Figure 6-9, Figure 6-10, and Figure 6-11)
16.67 MHz
Freescale Semiconductor, Inc...
Num.
Characteristic
Symbol
Min
Max
Unit
110
Address Valid to AS Low
tAVASL
15
—
ns
111
AS Low to Clock High
tASLCH
30
—
ns
112
Clock Low to AS High
tCLASH
—
45
ns
113
AS High to Address Hold Time on Write
tASHAH
0
—
ns
114
AS Inactive Time
tASH
1
—
clk
115
UDS/LDS Low to Clock High (see Note 2)
tSLCH
40
—
ns
116
Clock Low to UDS/LDS High
tCLSH
—
45
ns
117
R/W Valid to Clock High (see Note 2)
tRWVCH
30
—
ns
118
Clock High to R/W High
tCHRWH
—
45
ns
119
AS Low to IAC High
tASLIAH
—
40
ns
120
AS High to IAC Low
tASHIAL
—
40
ns
121
AS Low to DTACK Low (0 Wait State)
tASLDTL
—
45
ns
122
Clock Low to DTACK Low (1 Wait State)
tCLDTL
—
30
ns
123
AS High to DTACK High
tASHDTH
—
45
ns
124
DTACK High to DTACK High Impedance
tDTHDTZ
—
15
ns
125
Clock High to Data-Out Valid
tCHDOV
—
30
ns
126
AS High to Data High Impedance
tASHDZ
—
45
ns
127
AS High to Data-Out Hold Time
tASHDOI
0
—
ns
128
AS High to Address Hold Time on Read
tASHAI
0
—
ns
129
UDS/LDS Inactive Time
tSH
1
—
clk
130
Data-In Valid to Clock Low
tCLDIV
30
—
ns
131
Clock Low to Data-In Hold Time
tCLDIH
15
—
ns
NOTES:
1. Synchronous specifications above are valid only when SAM = 1 in the SCR.
2. It is required that this signal not be asserted prior to the previous rising CLKO edge (i.e., in the previous clock
cycle). It must be recognized by the IMP no sooner than the rising CLKO edge shown in the diagram.
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S0
S1
S2
S3
S4
S5
S6
S0
S7
CLKO
(OUTPUT)
128
A23-A1
(INPUT)
110
112
111
AS
(INPUT)
114
Freescale Semiconductor, Inc...
119
120
IAC
(OUTPUT)
116
115
UDS
LDS
(INPUT)
129
R/W
(INPUT)
126
127
125
D15–D0
(OUTPUT)
121
123
124
DTACK
(OUTPUT)
Figure 6-9. External Master Internal Synchronous Read Cycle Timing Diagram
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S0
S1
S2
S3
S4
Sw
Sw
S5
S6
S7
S0
CLKO
(OUTPUT)
128
A23–A1
(INPUT)
110
112
111
AS
(INPUT)
114
119
120
Freescale Semiconductor, Inc...
IAC
(OUTPUT)
116
115
UDS
LDS
(INPUT)
129
R/W
(INPUT)
126
125
127
D15–D0
(OUTPUT)
124
122
123
DTACK
(OUTPUT)
Figure 6-10. External Master Internal Synchronous Read Cycle Timing Diagram (One
Wait State)
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S0
S1
S2
S3
S4
S5
S6
S7
S0
CLKO
A23–A1
(INPUT)
110
112
111
AS
(INPUT)
113
114
120
119
Freescale Semiconductor, Inc...
IAC
(OUTPUT)
116
UDS
LDS
(INPUT)
115
129
118
117
R/W
(INPUT)
130
131
D0–D15
(INPUT)
DTACK
(OUTPUT)
121
123
124
Figure 6-11. External Master Internal Synchronous Write Cycle Timing Diagram
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6.12 AC ELECTRICAL SPECIFICATIONS—INTERNAL MASTER
INTERNAL READ/WRITE CYCLES (see Figure 6-12)
16.67 MHz
Freescale Semiconductor, Inc...
Num.
Characteristic
Symbol
Min
Max
Unit
140
Clock High to IAC High
tCHIAH
—
40
ns
141
Clock Low to IAC Low
tCLIAL
—
40
ns
142
Clock High to DTACK Low
tCHDTL
—
45
ns
143
Clock Low to DTACK High
tCLDTH
—
40
ns
144
Clock High to Data-Out Valid
tCHDOV
—
30
ns
145
AS High to Data-Out Hold Time
tASHDOH
0
—
ns
S0
S1
S2
S3
S4
S5
S6
S7
S0
CLKO
(OUTPUT)
A23-A1
(OUTPUT)
AS
(OUTPUT)
141
140
IAC
(OUTPUT)
UDS
LDS
(OUTPUT)
R/W
(OUTPUT)
145
144
D15-D0
(OUTPUT)
142
143
DTACK
(OUTPUT)
Figure 6-12. Internal Master Internal Read/Write Cycle Timing Diagram
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6.13 AC ELECTRICAL SPECIFICATIONS—CHIP-SELECT TIMING
INTERNAL MASTER (see Figure 6-13)
Freescale Semiconductor, Inc...
16.67 MHz
Num.
Characteristic
Symbol
Min
Max
Unit
150
Clock High to CS, IACK Low (see Note 2)
tCHCSIAKL
0
40
ns
151
Clock Low to CS, IACK High (see Note 2)
tCLCSIAKH
0
40
ns
152
CS Width Negated
tCSH
60
—
ns
153
Clock High to DTACK Low (0 Wait State)
tCHDTKL
—
45
ns
154
Clock Low to DTACK Low (1–6 Wait
States)
tCLDTKL
—
30
ns
155
Clock Low to DTACK High
tCLDTKH
—
40
ns
156
Clock High to BERR Low (see Note 1)
tCHBERL
—
40
ns
157
Clock Low to BERR High Impedance (see
Note 1)
tCLBERH
—
40
ns
158
DTACK High to DTACK High Impedance
tDTKHDTKZ
—
15
ns
171
Input Data Hold Time from S6 Low
tIDHCL
5
—
ns
172
CS Negated to Data-Out Invalid (Write)
tCSNDOI
10
—
ns
173
Address, FC Valid to CS Asserted
tAFVCSA
15
—
ns
174
CS Negated to Address, FC Invalid
tCSNAFI
15
—
ns
175
CS Low Time (0 Wait States)
tCSLT
120
—
ns
176
CS Negated to R/W Invalid
tCSNRWI
10
—
ns
177
CS Asserted to R/W Low (Write)
tCSARWL
—
10
ns
178
CS Negated to Data-In Invalid (Hold Time
on Read)
tCSNDII
0
—
ns
NOTE:
1.This specification is valid only when the ADCE or WPVE bits in the SCR are set.
2.For loading capacitance less than or equal to 50 pF, subtract 4 ns from the maximum value given.
3.Since AS and CS are asserted/negated on the same CLKO edges, no AS to CS relative timings can be
specified. However, CS timings are given relative to a number of other signals, in the same manner as AS.
See Figure 6-2 and Figure 6-3 for diagrams.
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S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
Sw
Sw
S5
S6
CLKO
(OUTPUT)
CS0–CS3
IACK1,IACK6,
IACK7
(OUTPUT)
152
150
151
153
155
154
DTACK
(OUTPUT)
158
157
Freescale Semiconductor, Inc...
156
BERR
(OUTPUT)
Figure 6-13. Internal Master Chip-Select Timing Diagram
6.14 AC ELECTRICAL SPECIFICATIONS—CHIP-SELECT TIMING
EXTERNAL MASTER (see Figure 6-14)
16.67 MHz
Num.
Characteristic
Symbol
Min
Max
Unit
154
Clock Low to DTACK Low (1-6 Wait States)
tCLDTKL
—
30
ns
160
AS Low to CS Low
tASLCSL
—
30
ns
161
AS High to CS High
tASHCSH
—
30
ns
162
Address Valid to AS Low
tAVASL
15
—
ns
163
R/W Valid to AS Low (see Note 1)
tRWVASL
15
—
ns
164
AS Negated to Address Hold Time
tASHAI
0
—
ns
165
AS Low to DTACK Low (0 Wait State)
tASLDTKL
—
45
ns
167
AS High to DTACK High
tASHDTKH
—
30
ns
168
AS Low to BERR Low (see Note 2)
tASLBERL
—
30
ns
169
AS High to BERR High Impedance (see
Notes 2 and 3)
tASHBERH
—
30
ns
NOTES:
1.The minimum value must be met to guarantee write protection operation.
2.This specification is valid when the ADCE or WPVE bits in the SCR are set.
3.Also applies after a timeout of the hardware watchdog.
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S7
S0
Freescale Semiconductor, Inc.
S0
S1
S2
S3
S4
S5
S6
S7
S0
CLKO
164
A23-A1
(INPUT)
162
AS
(INPUT)
161
160
Freescale Semiconductor, Inc...
CS3-CS0
(OUTPUT)
163
R/W
(INPUT)
167
165
158
DTACK
(OUTPUT)
169
168
BERR
(OUTPUT)
Figure 6-14. External Master Chip-Select Timing Diagram
6.15 AC ELECTRICAL SPECIFICATIONS—PARALLEL I/O
(see Figure 6-15)
16.67 MHz
Num.
Characteristic
Symbol
Min
Max
Unit
180
Input Data Setup Time (to Clock Low)
tDSU
20
—
ns
181
Input Data Hold Time (from Clock Low)
tDH
10
—
ns
182
Clock High to Data-out Valid
(CPU Writes Data, Control, or Direction)
tCHDOV
—
35
ns
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CLKO
DATA IN
180
181
DATA OUT
Freescale Semiconductor, Inc...
182
CPU WRITE (S6) OF PORT DATA, CONTROL, OR DIRECTION REG
Figure 6-15. Parallel I/O Data-In/Data-Out Timing Diagram
6.16 AC ELECTRICAL SPECIFICATIONS—INTERRUPTS
(seeFigure 6-16)
16.67 MHz
Num.
Characteristic
Symbol
Min
Max
Unit
190
Interrupt Pulse Width Low IRQ (Edge Triggered Mode) or PB8-11
tIPW
50
—
ns
191
Minimum Time Between Active Edges
tAEMT
3
—
clk
NOTE: Setup time for the asynchronous inputs IPL2–IPL0 and AVEC guarantees their recognition at the next falling
edge of the clock.
IRQ
(INPUT)
190
191
Figure 6-16. Interrupts Timing Diagram
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6.17 AC ELECTRICAL SPECIFICATIONS—TIMERS
(see Figure 6-17)
16.67 MHz
Freescale Semiconductor, Inc...
Num.
Characteristic
Symbol
Min
Max
Unit
200
Timer Input Capture Pulse Width
tTPW
50
—
ns
201
TIN Clock Low Pulse Width
tTICLT
50
—
ns
202
TIN Clock High Pulse Width and Input
Capture High Pulse Width
tTICHT
2
—
clk
203
TIN Clock Cycle Time
tcyc
3
—
clk
204
Clock High to TOUT Valid
tCHTOV
—
35
ns
205
FRZ Input Setup Time (to Clock High) (see
Note 1)
tFRZSU
20
—
ns
206
FRZ Input Hold Time (from Clock High)
tFRZHT
10
—
ns
NOTES:
1. FRZ should be negated during total system reset.
2. The TIN specs above do not apply to the use of TIN1 as a baud rate generator input clock. In such a case,
specifications 1–3 may be used.
CLKO
TOUT
(OUTPUT)
204
TIN
(INPUT)
201
200
202
203
205
FRZ
(INPUT)
Figure 6-17. Timers Timing Diagram
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206
Freescale Semiconductor, Inc.
6.18 AC ELECTRICAL SPECIFICATIONS—SERIAL
COMMUNICATIONS PORT (see Figure 6-18).
16.67 MHz
Freescale Semiconductor, Inc...
Num.
Characteristic
Min
Max
Unit
250
SPCLK Clock Output Period
4
64
clks
251
SPCLK Clock Output Rise/Fall Time
0
15
ns
252
Delay from SPCLK to Transmit (see Note 1)
0
40
ns
253
SCP Receive Setup Time (see Note 1)
40
—
ns
254
SCP Receive Hold Time (see Note 1)
10
—
ns
NOTES:
1. This also applies when SPCLK is inverted by CI in the SPMODE register.
2. The enable signals for the slaves may be implemented by the parallel I/O pins.
250
251
SPCLK
(OUTPUT)
252
SPTXD
(OUTPUT)
1
2
3
4
5
6
7
8
6
7
8
253
254
SPRXD
(INPUT)
1
2
3
4
5
Figure 6-18. Serial Communication Port Timing Diagram
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6.19 AC ELECTRICAL SPECIFICATIONS—IDL TIMING (All timing measurements,
unless otherwise specified, are referenced to the L1CLK at 50% point of VDD) (see Figure 6-19).
Freescale Semiconductor, Inc...
16.67 MHz
Num.
Characteristic
Min
Max
Unit
260
L1CLK (IDL Clock) Frequency (see Note 1)
—
6.66
MHz
261
L1CLK Width Low
262
L1CLK Width High (see Note 3)
263
55
—
ns
P+10
—
ns
L1TXD, L1RQ, SDS1–SDS2 Rising/Falling
Time
—
20
ns
264
L1SY1 (sync) Setup Time (to L1CLK Falling
Edge)
30
—
ns
265
L1SY1 (sync) Hold Time (from L1CLK Falling Edge)
50
—
ns
266
L1SY1 (sync) Inactive Before 4th L1CLK
0
—
ns
267
L1TxD Active Delay (from L1CLK Rising
Edge)
0
75
ns
268
L1TxD to High Impedance (from L1CLK Rising Edge) (see Note 2)
0
50
ns
269
L1RxD Setup Time (to L1CLK Falling Edge)
50
—
ns
270
L1RxD Hold Time (from L1CLK Falling
Edge)
50
—
ns
271
Time Between Successive IDL syncs
20
—
L1CLK
272
L1RQ Valid before Falling Edge of L1SY1
1
—
L1CLK
273
L1GR Setup Time (to L1SY1 Falling Edge)
50
—
ns
274
L1GR Hold Time (from L1SY1 Falling Edge)
50
—
ns
275
SDS1–SDS2 Active Delay from L1CLK Rising Edge
10
75
ns
276
SDS1–SDS2 Inactive Delay from L1CLK
Falling Edge
10
75
ns
NOTES:
1. The ratio CLKO/L1CLK must be greater than 2.5/1.
2. High impedance is measured at the 30% and 70% of VDD points, with the line at VDD/2 through 10K in
parallel with130 pF.
3. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns.
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267
Figure 6-19. IDL Timing Diagram
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L1GR
(INPUT)
L1RQ
(OUTPUT)
SDS1–SDS2
(OUTPUT)
L1RXD
(INPUT)
L1TXD
(OUTPUT)
L1CLK
(INPUT)
L1SY1
(INPUT)
270
1
262
264
273
272
275
B17
269
B17
2
265
B16
B16
3
B15
5
B14
B14
263
B15
261
4
260
266
274
B13
B13
6
B12
B12
7
B11
B11
8
B10
B10
9
276
D1
D1
10
A
A
B27
B26
B26
12
268
B27
11
271
B25
B25
13
B24
B24
14
B23
B23
15
Freescale Semiconductor, Inc...
B22
B22
16
B21
B21
17
B20
B20
18
D2
D2
19
M
M
20
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
6.20 AC ELECTRICAL SPECIFICATIONS—GCI TIMING
GCI supports the NORMAL mode and the GCI channel 0 (GCN0) in MUX mode. Normal
mode uses 512 kHz clock rate (256K bit rate). MUX mode uses 256 x n - 3088 kbs (clock
rate is data rate x 2). The ratio CLKO/L1CLK must be greater than 2.5/1 (see Figure 6-20).
16.67 MHz
Num.
Characteristic
Freescale Semiconductor, Inc...
L1CLK GCI Clock Frequency (Normal Mode) (see
Note 1)
Min
Max
Unit
—
512
kHz
280
L1CLK Clock Period Normal Mode (see Note 1)
281
L1CLK Width Low/High Normal Mode
840
1450
ns
282
L1CLK Rise/Fall Time Normal Mode (see Note 4)
—
—
ns
L1CLK (GCI Clock) Frequency (MUX Mode) (see
Note 1)
—
280
L1CLK Clock Period MUX Mode (see Note 1)
150
—
ns
281
L1CLK Width Low MUX Mode
55
—
ns
P+10
—
ns
—
—
ns
281A
L1CLK Width High MUX Mode (see Note 5)
1800 2100
ns
6.668 MHz
282
L1CLK Rise/Fall Time MUX Mode (see Note 4)
283
L1SY1 Sync Setup Time to L1CLK Falling Edge
30
—
ns
284
L1SY1 Sync Hold Time from L1CLK Falling Edge
50
—
ns
285
L1TxD Active Delay (from L1CLK Rising Edge) (see
Note 2)
0
100
ns
286
L1TxD Active Delay (from L1SY1 Rising Edge) (see
Note 2)
0
100
ns
287
L1RxD Setup Time to L1CLK Rising Edge
20
—
ns
288
L1RxD Hold Time from L1CLK Rising Edge
50
—
ns
289
Time Between Successive L1SY1in
Normal 64
SCIT Mode 192
—
—
L1CLK
L1CLK
290
SDS1–SDS2 Active Delay from L1CLK Rising Edge
(see Note 3)
10
90
ns
291
SDS1–SDS2 Active Delay from L1SY1 Rising Edge
(see Note 3)
10
90
ns
292
SDS1–SDS2 Inactive Delay from L1CLK Falling
Edge
10
90
ns
293
GCIDCL (GCI Data Clock) Active Delay
0
50
ns
NOTES:
1.The ratio CLKO/L1CLK must be greater than 2.5/1.
2. Condition CL = 150 pF. L1TD becomes valid after the L1CLK rising edge or L1SY1, whichever is later.
3.SDS1–SDS2 become valid after the L1CLK rising edge or L1SY1, whichever is later.
4.Schmitt trigger used on input buffer.
5.Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns.
MC68302 USER’S MANUAL ADDENDUM
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Figure 6-20. GCI Timing Diagram
MC68302 USER’S MANUAL ADDENDUM
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GCIDCL
(OUTPUT)
SDS1–SDS2
(OUTPUT)
L1RXD
(INPUT)
286
L1TXD
(OUTPUT)
285
L1SY1
(INPUT)
L1CLK
(INPUT)
287
284
293
291
290
283
288
280
282
281
289
Freescale Semiconductor, Inc...
292
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
6.21 AC ELECTRICAL SPECIFICATIONS—PCM TIMING
There are two sync types:
Short Frame—Sync signals are one clock cycle prior to the data
Long Frame—Sync signals are N-bits that envelope the data, N > 0; see Figure 6-21
and Figure 6-22).
Freescale Semiconductor, Inc...
16.67 MHz
Num.
Characteristic
Min
Max
Unit
300
L1CLK (PCM Clock) Frequency (see Note
1)
—
6.66
MHz
301
L1CLK Width Low
55
—
ns
P+10
—
ns
301A
L1CLK Width High (see Note 4)
302
L1SY0–L1SY1 Setup Time to L1CLK
Rising Edge
0
—
ns
303
L1SY0–L1SY1 Hold Time from L1CLK
Falling Edge
40
—
ns
304
L1SY0–L1SY1 Width Low
1
—
L1CLK
305
Time Between Successive Sync Signals
(Short Frame)
8
—
L1CLK
306
L1TxD Data Valid after L1CLK Rising Edge
(see Note 2)
0
70
ns
307
L1TxD to High Impedance (from L1CLK
Rising Edge)
0
50
ns
308
L1RxD Setup Time (to L1CLK Falling
Edge) (see Note 3)
20
—
ns
309
L1RxD Hold Time (from L1CLK Falling
Edge) (see Note 3)
50
—
ns
NOTES:
1. The ratio CLK/L1CLK must be greater than 2.5/1.
2. L1TxD becomes valid after the L1CLK rising edge or the sync enable, whichever is later, if long frames are used.
This note should only be used if the user can guarantee that only one sync pin (L1SY0 and L1SY1) is changed
simultaneously in the selection and de-selection of the desired PCM channel time slot. A safe example of this is
using only PCM CH-1. Another example is using CH-1 and CH-2 only, where CH-1 and CH-2 are not contiguous on
the PCM highway.
3. Specification valid for both sync methods.
4. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns.
MC68302 USER’S MANUAL ADDENDUM
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L1CLK
(INPUT)
2
1
3
4
n-1
5
n
303
302
302
L1SY0/1
(INPUT)
306
307
Freescale Semiconductor, Inc...
L1TXD
(OUTPUT)
1
2
3
n-1
n
2
3
n-1
n
308
309
L1RXD
(INPUT)
1
Figure 6-21. PCM Timing Diagram (SYNC Envelopes Data)
L1CLK
(INPUT)
1
2
3
5
4
6
7
8
303
302
L1SY0/1
(INPUT)
304
(*)
305
307
306
L1TXD
(OUTPUT)
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
308
309
L1RXD
(INPUT)
1
NOTE: (*) If L1SYn is guaranteed to make a smooth low to high transition (no spikes) while the clock is high, setup time can be defined as shown
(min 20 ns).
Figure 6-22. PCM Timing Diagram (SYNC Prior to 8-Bit Data)
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6.22 AC ELECTRICAL SPECIFICATIONS—NMSI TIMING
The NMSI mode uses two clocks, one for receive and one for transmit. Both clocks can be
internal or external. When t he clock is internal, it is generated by the internal baud rate generator and it is output on TCLK or RCLK. All the timing is related to the external clock pin.
The timing is specified for NMSI1. It is also valid for NMSI2 and NMSI3 (see Figure 6-23).
16.67 MHz 16.67 MHz
Num.
Characteristic
Internal
Clock
External
Clock
Unit
Freescale Semiconductor, Inc...
Min Max Min Max
315
RCLK1 and TCLK1 Frequency (see Note 1)
—
5.55
—
316
RCLK1 and TCLK1 Low
(see Note 4)
65
—
P+10
—
ns
316a RCLK1 and TCLK1 High
65
—
55
—
ns
6.668 MHz
317
RCLK1 and TCLK1 Rise/Fall
Time (see Note 3)
—
20
—
—
ns
318
TXD1 Active Delay from
TCLK1 Falling Edge
0
40
0
70
ns
319
RTS1 Active/Inactive Delay
from TCLK1 Falling Edge
0
40
0
100
ns
320
CTS1 Setup Time to TCLK1
Rising Edge
50
—
10
—
ns
321
RXD1 Setup Time to RCLK1
Rising Edge
50
—
10
—
ns
322
RXD1 Hold Time from
RCLK1 Rising Edge (see
Note 2)
10
—
50
—
ns
323
CD1 Setup Time to RCLK1
Rising Edge
50
—
10
—
ns
NOTES:
1. The ratio CLKO/TCLK1 and CLKO/RCLK1 must be greater than or equal to 2.5/1 for external clock. The input clock
to the baud rate generator may be either an internal clock or TIN1, and may be as fast as EXTAL. However, the
output of the baud rate generator must provide a CLKO/TCLK1 and CLKO/RCLK1 ratio greater than or equal to 3/1.
In asynchronous mode (UART), the bit rate is 1/16 of the TCLK1/RCLK1 clock rate.
2. Also applies to CD hold time when CD is used as an external sync in BISYNC or totally transparent mode.
3. Schmitt triggers used on input buffers.
4. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns.
MC68302 USER’S MANUAL ADDENDUM
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Figure 6-23. NMSI Timing Diagram
MC68302 USER’S MANUAL ADDENDUM
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CD1
(SYNC INPUT)
CD1
(INPUT)
RXD1
(INPUT)
RCLK1
CTS1
(INPUT)
RTS1
(OUTPUT)
TXD1
(OUTPUT)
TCLK1
321
317
317
322
316
317
319
318
316
317
315
315
320
Freescale Semiconductor, Inc...
323
322
319
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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