NXP P89LPC952FBD 8-bit microcontroller Data Sheet

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P89LPC952/954

8-bit microcontroller with accelerated two-clock 80C51 core

8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC

Rev. 04 — 24 July 2008 Product data sheet

1. General description

The P89LPC952/954 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC952/954 in order to reduce component count, board space, and system cost.

2. Features

2.1 Principal features

8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

256-byte RAM data memory and a 256-byte auxiliary on-chip RAM.

8-input multiplexed 10-bit ADC with window comparator that can generate an interrupt for in or out of range results. Two analog comparators with selectable inputs and reference source.

Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output) and a 23-bit system timer that can also be used as a RTC.

Two enhanced UARTs with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I

C-bus communication port and SPI communication port.

High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. Fast switching between the internal RC oscillator and any oscillator source provides optimal support of minimal power active mode with fast switching to maximum performance.

2.4 V to 3.6 V V

operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).

44-pin and 48-pin packages with 40 and 42 I/O pins minimum while using on-chip oscillator and reset options.

Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip.

Watchdog timer with separate on-chip oscillator, requiring no external components.

The watchdog prescaler is selectable from eight values.

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

2.2 Additional features

A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced

EMI.

Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.

Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application.

In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application.

Low voltage (brownout) detect allows a graceful system shutdown when power fails.

May optionally be configured as an interrupt.

Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1

A (total power-down with voltage comparators disabled).

On-chip power-on reset allows operation without external reset components. A software reset function is also available.

Programmable external reset pin (P1.5) configuration options: open drain bidirectional reset input/output, reset input with pull-up, push-pull reset output, input-only port. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets.

Only power and ground connections are required to operate the P89LPC952/954 when internal reset option is selected.

Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz.

Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.

Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.

Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.

Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.

Four interrupt priority levels.

Eight keypad interrupt inputs, plus two additional external interrupt inputs.

Schmitt trigger port inputs.

Second data pointer.

Extended temperature range.

Emulation support.

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Product data sheet

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

3. Ordering information

Table 1.

Ordering information

Type number Package

Name

P89LPC952FA

P89LPC952FBD

PLCC44

LQFP44

P89LPC954FA

P89LPC954FBD44

P89LPC954FBD48

PLCC44

LQFP44

LQFP48

Description

plastic leaded chip carrier; 44 leads plastic low profile quad flat package; 44 leads; body 10

1.4 mm plastic leaded chip carrier; 44 leads plastic low profile quad flat package; 44 leads; body 10

1.4 mm plastic low profile quad flat package; 48 leads; body 7

1.4 mm

Version

SOT187-2

SOT389-1

SOT187-2

SOT389-1

SOT313-2

3.1 Ordering options

Table 2.

Ordering options

Type number Flash memory

P89LPC952FA

P89LPC952FBD

8 kB

P89LPC954FA

P89LPC954FBD44

P89LPC954FBD48

16 kB

Temperature range

−

C to +85

−

C to +85

−

C to +85

−

C to +85

−

C to +85

Frequency

0 MHz to 18 MHz

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

4. Block diagram

P5[7:0]

P4[7:0]

P3[1:0]

P2[5:0]

(1)

P2[7:0]

(2)

P1[7:0]

P0[7:0]

CRYSTAL

RESONATOR

XTAL1

XTAL2

P89LPC952/954

ACCELERATED 2-CLOCK 80C51 CPU

8 kB/16 kB

CODE FLASH

256-BYTE

DATA RAM

256-BYTE

AUXILIARY RAM

PORT 5

CONFIGURABLE I/Os

PORT 4

CONFIGURABLE I/Os

PORT 3

CONFIGURABLE I/Os

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR internal bus

PROGRAMMABLE

OSCILLATOR DIVIDER

CONFIGURABLE

OSCILLATOR

CPU clock

ON-CHIP RC

OSCILLATOR WITH

CLOCK DOUBLER

UART0

UART1

C-BUS

ADC0

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0

TIMER 1

ANALOG

COMPARATORS

DEBUGGER

INTERFACE

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

002aab305

(1) 44-pin package.

(2) 48-pin package.

Fig 1.

Block diagram

TXD0

RXD0

TXD1

RXD1

SCL

SDA

AD00

AD02

AD04

AD06

SPICLK

MOSI

MISO

AD01

AD03

AD05

AD07

CMP2

CIN2A

CIN1A

CIN2B

CMP1

CIN1B

TRIG

TCLK

TDI

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

5. Functional diagram

AD05

AD00

AD01

AD02

AD03

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

CLKOUT

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

XTAL2

XTAL1

PORT 0

PORT 3

PORT 5

P89LPC952

P89LPC954

002aab358

(1)

PORT 1

PORT 2

TXD0

RXD0

INT0

INT1

RST

AD04

AD07

AD06

MOSI

MISO

SPICLK

SCL

SDA

PORT 4

TRIG

TXD1

RXD1

TDI

TCLK

(1) 48-pin package.

Fig 2.

Functional diagram

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6. Pinning information

6.1 Pinning

P89LPC952/954

8-bit microcontroller with 10-bit ADC

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD0

P1.0/TXD0

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P5.7

P5.6

P5.5

P5.4

P89LPC952FA

P89LPC954FA

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

37 P0.6/CMP1/KBI6

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P4.0

P4.1/TRIG

002aab307

Fig 3.

PLCC44 pin configuration

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD0

P1.0/TXD0

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P5.7

P5.6

P5.5

P5.4

P89LPC952FBD

P89LPC954FBD

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P4.0

P4.1/TRIG

002aab306

Fig 4.

LQFP44 pin configuration

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD0

P1.0/TXD0

P2.7

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P5.7

P5.6

P5.5

P5.4

P89LPC954FBD48

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

VREFP

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P2.6

P4.0

002aad095

Fig 5.

LQFP48 pin configuration

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

6.2 Pin description

Table 3.

Pin description

Symbol Pin

LQFP48

P0.0 to P0.7

PLCC44 LQFP44

P0.0/CMP2/

KBI0/AD05

P0.1/CIN2B/

KBI1/AD00

P0.2/CIN2A/

KBI2/AD01

P0.3/CIN1B/

KBI3/AD02

P0.4/CIN1A/

KBI4/AD03

P0.5/CMPREF/

KBI5

Type Description

I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 7.13.1 “Port configurations”

and

Table 11 “Static characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

I/O P0.0 — Port 0 bit 0.

O CMP2 — Comparator 2 output.

I KBI0 — Keyboard input 0.

AD05 — ADC0 channel 5 analog input.

I/O P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.

I KBI1 — Keyboard input 1.

AD00 — ADC0 channel 0 analog input.

I/O P0.2 — Port 0 bit 2.

CIN2A — Comparator 2 positive input A.

I KBI2 — Keyboard input 2.

AD01 — ADC0 channel 1 analog input.

I/O P0.3 — Port 0 bit 3.

CIN1B — Comparator 1 positive input B.

I KBI3 — Keyboard input 3.

AD02 — ADC0 channel 2 analog input.

I/O P0.4 — Port 0 bit 4.

CIN1A — Comparator 1 positive input A.

I KBI4 — Keyboard input 4.

AD03 — ADC0 channel 3 analog input.

I/O P0.5 — Port 0 bit 5.

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

Table 3.

Pin description

…continued

Symbol Pin

P0.6/CMP1/

KBI6

LQFP48

PLCC44

LQFP44

P0.7/T1/KBI7

P1.0 to P1.7

P1.0/TXD0

P1.1/RXD0

P1.2/T0/SCL

P1.3/INT0/SDA

P1.4/INT1

Type Description

I/O

P0.6 — Port 0 bit 6.

CMP1 — Comparator 1 output.

KBI6 — Keyboard input 6.

I/O P0.7 — Port 0 bit 7.

I/O T1 — Timer/counter 1 external count input or overflow output.

KBI7 — Keyboard input 7.

I/O, I

[1]

Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to

Section 7.13.1

“Port configurations”

and

Table 11 “Static characteristics”

for details. P1.2 to P1.3 are open drain when used as outputs.

P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

I/O P1.0 — Port 1 bit 0.

O TXD0 — Transmitter output for serial port 0.

I/O P1.1 — Port 1 bit 1.

I RXD0 — Receiver input for serial port 0.

I/O P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O T0 — Timer/counter 0 external count input or overflow output (open-drain when used as output).

I/O SCL — I

C-bus serial clock input/output.

I/O P1.3 — Port 1 bit 3 (open-drain when used as output).

I INT0 — External interrupt 0 input.

I/O SDA — I

C-bus serial data input/output.

I/O P1.4 — Port 1 bit 4.

INT1 — External interrupt 1 input.

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

Table 3.

Pin description

…continued

Symbol Pin

P1.5/RST

LQFP48

PLCC44

LQFP44

Type Description

P1.6

P1.7/AD04

P2.0 to P2.5

P2.0/AD07

P2.1/AD06

P2.2/MOSI

P2.3/MISO

P2.4/SS

I P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during power-on or maybe a reset input/output if selected via UCFG1 and UCFG2. When functioning as a reset input or input/output, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When functioning as a reset output or input/output an internal reset source will drive this pin LOW. Also used during a power-on sequence to force

ISP mode. When using an oscillator frequency above

12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V

has reached its specified level. When system power is removed V

DD will fall below the minimum specified operating voltage.

When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

DD falls below the minimum specified operating voltage.

I/O P1.6 — Port 1 bit 6.

I/O P1.7 — Port 1 bit 7.

I AD04 — ADC0 channel 4 analog input.

I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 7.13.1 “Port configurations”

and

Table 11 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below:

I/O P2.0 — Port 2 bit 0.

I AD07 — ADC0 channel 7 analog input.

I/O P2.1 — Port 2 bit 1.

I AD06 — ADC0 channel 6 analog input.

I/O P2.2 — Port 2 bit 2.

I/O MOSI — SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input.

I/O P2.3 — Port 2 bit 3.

I/O MISO — When configured as master, this pin is input, when configured as slave, this pin is output.

I/O P2.4 — Port 2 bit 4.

I/O SS — SPI Slave select.

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

Table 3.

Pin description

…continued

Symbol Pin

P2.5/SPICLK

LQFP48

PLCC44

LQFP44

P2.6

P2.7

P3.0 to P3.1

P3.0/XTAL2/

CLKOUT

P3.1/XTAL1

P4.0 to P4.7

P4.0

P4.1/TRIG

P4.2/TXD1

P4.3/RXD1

P89LPC952_954_4

Product data sheet

Type Description

I/O P2.5 — Port 2 bit 5.

I/O SPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input.

I/O P2.6 — Port 2 bit 6.

I/O P2.7 — Port 2 bit 7.

I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 7.13.1 “Port configurations”

and

Table 11 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

I/O P3.0 — Port 3 bit 0.

O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration.

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer.

I/O P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration).

It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if

XTAL1/XTAL2 are not used to generate the clock for the

RTC/system timer.

I/O Port 4: Port 4 is an 8-bit I/O port with a user-configurable output type. During reset Port 4 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 4 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 7.13.1 “Port configurations”

and

Table 11 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 4 also provides various special functions as described below:

I/O P4.0 — Port 4 bit 0.

I/O P4.1 — Port 4 bit 1.

O TRIG — Debugger trigger output.

I/O P4.2 — Port 4 bit 2.

O TXD1 — Transmitter output for serial port 1.

I/O P4.3 — Port 4 bit 3.

RXD1 — Receiver input for serial port 1.

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NXP Semiconductors

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8-bit microcontroller with 10-bit ADC

Table 3.

Pin description

…continued

Symbol Pin

P4.4

P4.5/TDI

P4.6

P4.7/TCLK

P5.0 to P5.7

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

VREFN

LQFP48

17, 45

8, 32

PLCC44

3, 22

13, 36

LQFP44

16, 41

7, 30

VREFP 33 -

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

Type Description

I/O P4.4 — Port 4 bit 4.

I/O P4.5 — Port 4 bit 5.

I/O TDI — Serial data input/output for debugger interface.

I/O P4.6 — Port 4 bit 6.

I/O P4.7 — Port 4 bit 7.

I TCLK — Serial clock input for debugger interface.

I/O Port 5: Port 5 is an 8-bit I/O port with a user-configurable output type. During reset Port 5 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 5 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 7.13.1 “Port configurations”

and

Table 11 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 5 also provides various special functions as described below:

I/O P5.0 — Port 5 bit 0. High current source.

I/O P5.1 — Port 5 bit 1. High current source.

I/O P5.2 — Port 5 bit 2. High current source.

I/O P5.3 — Port 5 bit 3. High current source.

I/O P5.4 — Port 5 bit 4. High current source.

I/O P5.5 — Port 5 bit 5. High current source.

I/O P5.6 — Port 5 bit 6. High current source.

I/O P5.7 — Port 5 bit 7. High current source.

Ground: 0 V reference.

negative ADC reference voltage

Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.

positive ADC reference voltage

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

7. Functional description

Remark: Please refer to the P89LPC952/954 User’s Manual for a more detailed functional description.

7.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

•

User must not attempt to access any SFR locations not defined.

•

Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

•

SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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Table 4.

Special function registers

Name Description SFR addr.

Bit functions and addresses

MSB

E7 E6 E5 E4 E3 E2 E1

LSB

Reset value

Hex Binary

Bit address

ACC

[1]

AD0CON

Accumulator

ADC0 control register

AD0INS ADC0 input select

AD0MODA ADC0 mode register A

E0H

97H

A3H

C0H

AD0MODB ADC0 mode register B

AUXR1 Auxiliary function register

A1H

A2H

ENBI0

ADI07

BNDI0

CLK2

CLKLP

ENADCI0

ADI06

BURST0

CLK1

EBRR

TMM0

ADI05

SCC0

CLK0

ENT1

EDGE0

ADI04

SCAN0

ENT0

ADCI0

ADI03

SRST

ENADC0 ADCS01 ADCS00 00

ADI02

ADI01

ADI00 00

DPS

0000 0000

000x 0000

0000 00x0

F7 F6 F5 F4 F3 F2 F1 F0

[1]

B register

Bit address

F0H

BEH BRGR0_0 Baud rate generator 0 rate low

BRGR1_0 Baud rate generator 0 rate high

BFH

BDH BRGCON_0 Baud rate generator 0 control

CMP1

CMP2

Comparator 1 control register

Comparator 2 control register

DIVM CPU clock divide-by-M control

DPTR Data pointer

(2 bytes)

ACH

ADH

95H

CE1

CE2

CP1

CP2

CN1

CN2

OE1

OE2

SBRGS_0

BRGEN_0 00

[3]

CO1

CO2

CMF1

[2]

CMF2

[2]

0000 0000

0000 0000 xxxx xx00 xx00 0000 xx00 0000

0000 0000

Table 4.

Special function registers

…continued

Name

DPH

Description SFR addr.

83H

Bit functions and addresses

MSB LSB

Reset value

Hex

Binary

0000 0000

DPL

FMADRH

FMADRL

FMCON

FMDATA

I2ADR

Data pointer high

Data pointer low

Program flash address high

Program flash address low

Program flash control (Read)

Program flash control (Write)

Program flash data

C-bus slave address register

82H

E7H

E6H

E4H

E5H

BUSY

DBH I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

HVA

I2ADR.2

HVE

I2ADR.1

I2ADR.0

E4H FMCMD.7

FMCMD.6

FMCMD.5

FMCMD.4

FMCMD.3

FMCMD.2

FMCMD.1

FMCMD.0

0000 0000

0111 0000

0000 0000

I2CON

[1]

I2DAT

I2SCLH

I2SCLL

I2STAT

Bit address

C-bus control register

D8H

C-bus data register

DAH

DDH Serial clock generator/SCL duty cycle register high

Serial clock generator/SCL duty cycle register low

C-bus status register

DCH

D9H

STA.4

I2EN

STA.3

STA

STA.2

STO

STA.1

STA.0

CRSEL 00

F8 x000 00x0

0000 0000

1111 1000

Table 4.

Special function registers

…continued

Name Description SFR addr.

Bit address

Bit functions and addresses

MSB

AF AE AD AC AB AA A9

LSB

Reset value

Hex Binary

IEN0

[1]

Interrupt enable 0

A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 0000

IEN1

[1]

EST

ESPI

EKBI

EI2C

[2]

00x0 0000

IEN2

IP0

[1]

IP0H

IP1

[1]

IP1H

IP2

IP2H

KBCON

KBMASK

KBPATN

[1]

Interrupt enable 1

Interrupt enable 2

Bit address

E8H

D5H

Bit address

B8H Interrupt priority 0

Interrupt priority 0 high

B7H

Bit address

Interrupt priority 1

Interrupt priority 1 high

F8H

F7H

D6H Interrupt priority 2

Interrupt priority 2 high

D7H

Keypad control register

Keypad interrupt mask register

94H

86H

Keypad pattern register

Port 0

93H

Bit address

80H

Port 1

Bit address

90H

T1/KB7

PWDRT

PWDRTH

PST

PSTH

CMP1

/KB6

PBO

PBOH

CMPREF

/KB5

RST

PS/PSR

PSH/

PSRH

CIN1A

/KB4

INT1

EST1

PT1

PT1H

PSPI

PSPIH

PEST1

PEST1H

ES1/ESR1

PX1

PX1H

PCH

PES1/

PESR1

PES1H/

PESR1H

CIN1B

/KB3

CIN2A

/KB2

INT0/SDA T0/SCL

EADC

PT0

PT0H

PKBI

PKBIH

PADC

PADCH

PATN

_SEL

CIN2B

/KB1

RXD0

PX0

PX0H

PI2C

CMP2

/KB0

TXD0

[2]

PI2CH

[2]

KBIF

[2]

00x0 0000 x000 0000 x000 0000

00x0 0000

00x0 0000 xxxx xx00

0000 0000

1111 1111

Table 4.

Special function registers

…continued

Name

[1]

P0M1

P0M2

P1M1

P1M2

P2M1

P2M2

P3M1

P3M2

PCON

PCONA

Description SFR addr.

Bit functions and addresses Reset value

Bit address

MSB

97 96 95 94 93 92 91

LSB

Hex

Port 2 A0H SPICLK SS MISO MOSI -

[2]

Port 3

Port 4

Port 5

Port 0 output mode 1

Bit address B7 B6 B5 B4 B3 B2 B1 B0

B0H XTAL1 XTAL2

[2]

B3H TMS RXD1 TXD1 TRIG T3EX

[2]

B4H T3 -

[2]

84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF

[2]

Port 0 output mode 2

85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0)

[2]

Port 1 output mode 1

91H (P1M1.7) (P1M1.6) (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3

[2]

Port 1 output mode 2

92H (P1M2.7) (P1M2.6) (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0)

[2]

Port 2 output mode 1

A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF

[2]

Port 2 output mode 2

A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0)

[2]

Port 3 output mode 1

B1H (P3M1.1) (P3M1.0)

[2]

Port 3 output mode 2

B2H (P3M2.1) (P3M2.0)

[2]

SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 Power control register

Power control register A

87H

B5H

Bit address

SMOD1

RTCPD

VCPD

ADPD

I2PD

SPPD

SPD

[2]

Binary

1111 1111

0000 0000

11x1 xx11

00x0 xx00

1111 1111

0000 0000 xxxx xx11 xxxx xx00

0000 0000

PSW

[1]

Program status word

D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000

PT0AD F6H PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

00 xx00 000x

RSTSRC

Port 0 digital input disable

Reset source register

DFH BOF POF R_BK R_WD R_SF R_EX

[4]

Table 4.

Special function registers

…continued

Name Description SFR addr.

Bit functions and addresses Reset value

RTCCON

RTCH

RTC control

RTC register high

D1H

D2H

MSB

RTCF RTCS1 RTCS0 ERTC

LSB Hex

RTCEN

[2][7]

[7]

Binary

011x xx00

0000 0000

RTCL RTC register low

D3H

[7]

0000 0000

S0ADDR 00 0000 0000

S0ADEN

S0BUF

S0CON

[1]

S0STAT

SPCTL

SPSTAT

SPDAT

S1CON

S1STAT

TAMOD

Serial port address register

Serial port address enable

A9H

B9H

Serial Port data buffer register

99H

Bit address

Serial port control

Serial port extended status register

Stack pointer

SPI control register

98H SM0_0/FE

BAH DBMOD_0 INTLO_0 CIDIS_0 DBISEL_0

81H

E2H SSIG

SM1_00

SPEN

SM2_0

DORD

REN_0

MSTR

E1H SPIF WCOL SPI status register

SPI data register

E3H

Serial port 1 control

Serial port 1 extended status register

Timer 0 and 1 auxiliary mode

B6H SM0_1/FE

SM1_1 SM2_1 REN_1

D4H DBMOD_1 INTLO_1 CIDIS_1 DBISEL_1

8FH T1M2

TB8_0

FE_0

CPOL

TB8_1

FE_1

RB8_0

BR_0

CPHA

RB8_1

BR_1

TI_0

OE_0

SPR1

TI_1

OE_1

RI_0

SPR0

RI_1

00 xx

STINT_0 00

STINT_1 00

T0M2 00

0000 0000 xxxx xxxx

0000 0000

0000 0111

0000 0100

00xx xxxx

0000 0000

0000 0000 xxx0 xxx0

Table 4.

Special function registers

…continued

Name Description SFR addr.

Bit address

Bit functions and addresses

MSB

8F 8E 8D 8C 8B 8A 89

LSB

Reset value

Hex Binary

TCON

[1]

Timer 0 and 1 control

88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000

TH0

TH1

TL0

TL1

TMOD

TRIM

WDCON

WDL

WFEED1

WFEED2

Timer 0 high

Timer 1 high

Timer 0 low

Timer 1 low

Timer 0 and 1 mode

Internal oscillator trim register

96H

Watchdog control register

A7H

Watchdog load C1H

C2H Watchdog feed 1

Watchdog feed 2

C3H

8CH

8DH

8AH

8BH

89H T1GATE

RCCLK

PRE2

T1C/T

ENCLK

PRE1

T1M1

TRIM.5

PRE0

T1M0

TRIM.4

T0GATE

TRIM.3

T0C/T

TRIM.2

WDRUN

T0M1

TRIM.1

WDTOF

T0M0 00

TRIM.0

WDCLK

[6] [7]

[5] [7]

0000 0000

1111 1111

[1] Indicates SFRs that are bit addressable.

[2] All ports are in input only (high-impedance) state after power-up.

[3] BRGR1_0 and BRGR0_0 must only be written if BRGEN_0 in BRGCON_0 SFR is logic 0. If any are written while BRGEN_0 = 1, the result is unpredictable.

[4] The RSTSRC register reflects the cause of the P89LPC952/954 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000.

[5] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[7] The only reset source that affects these SFRs is power-on reset.

Table 5.

Extended special function registers

Name Description SFR addr.

FFEFH

Bit functions and addresses

MSB LSB

Reset value

Hex Binary

FF 1111 1111 ADC0HBND ADC0 high_boundary register, left (MSB)

ADC0LBND ADC0 low_boundary register (MSB)

AD0DAT0R ADC0 data register 0, right

(LSB)

AD0DAT0L ADC0 data register 0, left

(MSB)

AD0DAT1R ADC0 data register 1, right

(LSB)

AD0DAT1L ADC0 data register 1, left

(MSB)

AD0DAT2R ADC0 data register 2, right

(LSB)

AD0DAT2L ADC0 data register 2, left

(MSB)

AD0DAT3R ADC0 data register 3, right

(LSB)

AD0DAT3L ADC0 data register 3, left

(MSB)

AD0DAT4R ADC0 data register 4, right

(LSB)

AD0DAT4L ADC0 data register 4, left

(MSB)

AD0DAT5R ADC0 data register 5, right

(LSB)

AD0DAT5L ADC0 data register 5, left

(MSB)

AD0DAT6R ADC0 data register 6, right

(LSB)

AD0DAT6L ADC0 data register 6, left

(MSB)

AD0DAT7R ADC0 data register 7, right

(LSB)

FFEEH

FFFEH

FFFFH

FFFCH

FFFDH

FFFAH

FFFBH

FFF8H

FFF9H

FFF6H

FFF7H

FFF4H

FFF5H

FFF2H

FFF3H

FFF0H

AD0DAT0[7:0]

AD0DAT0[9:2]

AD0DAT1[7:0]

AD0DAT1[9:2]

AD0DAT2[7:0]

AD0DAT2[9:2]

AD0DAT3[7:0]

AD0DAT3[9:2]

AD0DAT4[7:0]

AD0DAT4[9:2]

AD0DAT5[7:0]

AD0DAT5[9:2]

AD0DAT6[7:0]

AD0DAT6[9:2]

AD0DAT7[7:0]

00 0000 0000

Table 5.

Extended special function registers

…continued

Name Description SFR addr.

Bit functions and addresses

MSB LSB

Reset value

Hex Binary

AD0DAT7L ADC0 data register 7, left

(MSB)

BNDSTA0 ADC0 boundary status register

BRGCON_1 Baud rate generator 1 control

BRG0_1 Baud rate generator 1 rate low

BRG1_1

FREEZE

Baud rate generator 1 rate high

Peripheral clock freeze

FFF1H

FFEDH

FFB3H

FFB4H

FFB5H

AD0DAT7[9:2]

SBRGS_1 BRGEN_1 00

[2]

xxxx xx00

P4M1

P4M2

P5M1

P5M2

Port 4 output mode 1

Port 4 output mode 2

Port 5 output mode 1

Port 5 output mode 3

FFD0H RTC_F CCU_F WDT_F T1_F T0_F 00 xxx0 0000

FFB8H (P4M1.7) (P4M1.6) (P4M1.5) (P4M1.4) (P4M1.3) (P4M1.2) (P4M1.1) (P4M1.0) FF

[1]

FFB9H (P4M2.7) (P4M2.6) (P4M2.5) (P4M2.4) (P4M2.3) (P4M2.2) (P4M2.1) (P4M2.0) 00

[1]

1111 1111

0000 0000

FFBAH (P5M1.7) (P5M1.6) (P5M1.5) (P5M1.4) (P5M1.3) (P5M1.2) (P5M1.1) (P5M1.0) FF

[1]

FFBBH (P5M2.7) (P5M2.6) (P5M2.5) (P5M2.4) (P5M2.3) (P5M2.2) (P5M2.1) (P5M2.0) 00

[1]

1111 1111

0000 0000

S1ADDR FFB2H 00 0000 0000

S1ADEN

S1BUF

Serial port 1 address register

Serial port 1 address enable

Serial port 1 data buffer register

FFB1H

FFB0H

00 0000 0000 xx xxxx xxxx

[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs.

[2] BRGR1_1 and BRGR0_1 must only be written if BRGEN_1 in BRGCON_1 SFR is logic 0. If any are written while BRGEN_1 = 1, the result is unpredictable.

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

7.2 Enhanced CPU

The P89LPC952/954 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

7.3 Clocks

7.3.1 Clock definitions

The P89LPC952/954 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see

Figure 6 ) and can also be optionally divided to a slower frequency (see

Section 7.8 “CCLK modification: DIVM register” ).

Note: f osc

is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is

CCLK

⁄

7.3.2 CPU clock (OSCCLK)

The P89LPC952/954 provides several user-selectable oscillator options in generating the

CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.

7.3.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

7.3.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

7.3.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration. When using a clock frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V

has reached its specified level. When system power is removed V

will fall below the minimum specified operating voltage. When using a clock frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device

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8-bit microcontroller with 10-bit ADC in reset when V

falls below the minimum specified operating voltage. These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode.

7.3.6 Clock output

The P89LPC952/954 supports a user-selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC952/954. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is

⁄

2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.

7.4 On-chip RC oscillator option

The P89LPC952/954 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz

1 % at room temperature.

End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1), the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at

8 MHz or slower.

The requirements in

Section 7.3.5 “High speed oscillator option”

for configuring P1.5 as an external reset input and using an external reset circuit when the clock frequency is greater than 12 MHz do not apply when using the internal RC oscillator’s clock doubler option.

7.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

7.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the

P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be used as a standard port pin or a clock output.

When using an external clock input frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V

DD has reached its specified level. When system power is removed V

will fall below the minimum specified operating voltage. When using an external clock input frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

falls below the minimum specified operating voltage. These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode.

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

XTAL1

XTAL2

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

RTC

ADC0

RC OSCILLATOR

WITH CLOCK DOUBLER

RCCLK

(7.3728 MHz/14.7456 MHz

1 %)

WATCHDOG

OSCILLATOR

(400 kHz +30 %

−

20 %)

OSCCLK

DIVM

RCCLK

PCLK

CCLK

PCLK

CPU

WDT

TIMER 0 AND

TIMER 1

C-BUS SPI UARTS

002aab409

Fig 6.

Block diagram of oscillator control

7.7 CCLK wake-up delay

The P89LPC952/954 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus

µ s to 100

µ s. If the clock source is either the internal RC oscillator, watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60

µ s to 100

µ s.

7.8 CCLK modification: DIVM register

The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

7.9 Low power select

The P89LPC952/954 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access.

This bit can then be set in software if CCLK is running at 8 MHz or slower.

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

7.10 Memory organization

The various P89LPC952/954 memory spaces are as follows:

•

DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.

•

IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

•

SFR

Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

•

XDATA

‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC952/954 has 256 bytes of on-chip

XDATA memory, plus extended SFRs located in XDATA.

•

CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC952/954 has 8 kB/16 kB of on-chip Code memory.

7.11 Data RAM arrangement

The 768 bytes of on-chip RAM are organized as shown in

Table 6 .

Table 6.

On-chip data memory usages

Type Data RAM

DATA

IDATA

XDATA

Memory that can be addressed directly and indirectly

Memory that can be addressed indirectly

Auxiliary (‘External Data’) on-chip memory that is accessed using the MOVX instructions

Size (bytes)

128

256

7.12 Interrupts

The P89LPC952/954 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC952/954 supports 17 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port 0 TX, serial port 0 RX, combined serial port 0 RX/TX, serial port 1 TX, serial port 1 RX, combined serial port 1 RX/TX, brownout detect, watchdog/RTC, I

C-bus, keyboard, comparators 1 and 2, SPI, and ADC completion.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0, IEN1 or IEN2. The IEN0 register also contains a global disable bit, EA, which disables all interrupts.

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, IP1H, IP2, and

IP2H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.

7.12.1 External interrupt inputs

The P89LPC952/954 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request.

If an external interrupt is enabled when the P89LPC952/954 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to

Section 7.15 “Power reduction modes”

for details.

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

RTCF

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF2

CMF1

EA (IE0.7)

TF0

ET0

TF1

ET1

TI_0 and RI_0/RI_0

ES/ESR

TI_0

EST

EI2C

SPIF

ESPI

TI_1 and RI_1/RI_1

ES1/ESR1

TI_1

EST1

IE0

EX0

IE1

EX1

BOF

EBO

KBIF

EKBI

ENADCI0

ADCI0

ENBI0

BNDI0

EADC

Fig 7.

Interrupt sources, interrupt enables, and power-down wake-up sources

002aab408 wake-up

(if in power-down) interrupt to CPU

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

7.13 I/O ports

The P89LPC952/954 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5.

Ports 0, 1, 2, 4, and 5 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options and package chosen, as shown in

Table 7 .

Table 7.

Number of I/O pins available

Clock source

On-chip oscillator or watchdog oscillator

Reset option

No external reset (except during power-up) 42

External RST pin supported

Number of I/O pins

(48-pin package)

External clock input

Low/medium/high speed oscillator

(external crystal or resonator)

No external reset (except during power-up) 41

External RST pin supported

[1]

No external reset (except during power-up) 40

External RST pin supported

[1]

Number of I/O pins

(44-pin package)

[1] Required for operation above 12 MHz.

7.13.1 Port configurations

All but three I/O port pins on the P89LPC952/954 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin.

1. P1.5/RST can only be an input and cannot be configured.

2. P1.2/T0/SCL and P1.3/INT0/SDA may only be configured to be either input-only or open-drain.

7.13.1.1

Quasi-bidirectional output configuration

Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC952/954 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to V

, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit.

7.13.1.2

Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V

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An open-drain port pin has a Schmitt triggered input that also has a glitch suppression circuit.

7.13.1.3

Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt triggered input that also has a glitch suppression circuit.

7.13.1.4

Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a

Schmitt triggered input that also has a glitch suppression circuit.

7.13.2 Port 0 analog functions

The P89LPC952/954 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-Only

(high-impedance) mode.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.

On any reset, PT0AD[1:5] defaults to ‘0’s to enable digital functions.

7.13.3 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from

the LPC76x series of devices.

•

After power-up, all I/O pins except P1.5, may be configured by software.

•

Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open-drain.

Every output on the P89LPC952/954 has been designed to sink typical LED drive current.

However, there is a maximum total output current for all ports which must not be exceeded. Please refer to

Table 11 for detailed specifications.

All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

7.14 Power monitoring functions

The P89LPC952/954 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation.

This is accomplished with two hardware functions: Power-on detect and brownout detect.

7.14.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a brownout detection to cause a processor reset, however it may alternatively be configured to generate an interrupt.

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Brownout detection may be enabled or disabled in software.

If brownout detection is enabled the brownout condition occurs when V

falls below the brownout trip voltage, V bo

(see

Table 11 “Static characteristics”

), and is negated when V

DD rises above V bo

. If the P89LPC952/954 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating.

For correct activation of brownout detect, the V

rise and fall times must be observed.

Please see

Table 11 “Static characteristics” for specifications.

7.14.2 Power-on detection

The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.

7.15 Power reduction modes

The P89LPC952/954 supports three different power reduction modes. These modes are

Idle mode, Power-down mode, and total Power-down mode.

7.15.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

7.15.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The

P89LPC952/954 exits Power-down mode via any reset, or certain interrupts. In

Power-down mode, the power supply voltage may be reduced to the data retention supply voltage V

DDR

. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after V

DD has been lowered to V

DDR

, therefore it is highly recommended to wake-up the processor via reset in this case. V

must be raised to within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.

7.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.

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7.16 Reset

The P1.5/RST pin can function as either a digital input (P1.5), an active-LOW reset input with an internal pull-up, a bidirectional reset input/output (open drain output with an internal pull-up), or as push-pull reset output. These modes are selected by the RPE

(Reset Pin Enable) bit in UCFG1 and the RPE1 (Reset Pin Enable 1) bit in UCFG2.

Table 8.

Reset pin modes

P1.5/RST mode

General purpose input

Reset input with pull-up

Bidirectional reset input/output (open drain with pull-up)

Reset output

RPE1 (UCFG2.0) RPE (UCFG1.6)

Remark: During a power-up sequence, the RPE and RPE1 selection is overridden and this pin always functions as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the

device in reset. After power-up this pin will function as defined by the RPE and RPE1 bits. Only a power-up reset will temporarily override the selection defined by RPE and

RPE1 bits. Other sources of reset will not override the RPE and RPE1 bits.

Remark: During a power cycle, V

must fall below V

POR

before power is reapplied, in order to ensure a power-on reset (see

Table 11 “Static characteristics” on page 51

Remark: When using an oscillator frequency above 12 MHz, the reset input function of

P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V

has reached its specified level. When system power is removed V

DD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

falls below the minimum specified operating voltage.

Reset can be triggered from the following sources:

•

External reset pin (during power-up or if user configured via UCFG1, UCGF2);

•

Power-on detect;

•

Brownout detect;

•

Watchdog timer;

•

Software reset;

•

UART break character detect reset.

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit may be set:

•

During a power-on reset, both POF and BOF are set but the other flag bits are cleared.

•

For any other reset, previously set flag bits that have not been cleared will remain set.

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7.16.1 Reset vector

Following reset, the P89LPC952/954 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot

Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC952/954 User’s Manual). Otherwise, instructions will be fetched from address

0000H.

7.17 Timers/counters 0 and 1

The P89LPC952/954 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters. An option to automatically toggle the T0 and/or

T1 pins upon timer overflow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle.

Timer 0 and Timer 1 have five operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.

7.17.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a

13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

7.17.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

7.17.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.

7.17.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

7.17.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

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7.17.6 Timer overflow toggle output

Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.

7.18 RTC/system timer

The P89LPC952/954 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a

16-bit loadable down counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use

CCLK as its clock source. Only power-on reset will reset the RTC and its associated SFRs to the default state.

7.19 UARTs

The P89LPC952/954 has two enhanced UARTs that are compatible with the conventional

80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The

P89LPC952/954 does include an independent Baud Rate Generator for each UART

(BRG0 for UART 0 and BRG1 for UART 1). The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate

Generator associated with the specific UART. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options.

The UARTs can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

7.19.1 Mode 0

Serial data enters and exits through RXDn. TXDn outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at

⁄

of the CPU clock frequency.

7.19.2 Mode 1

10 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0),

8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8_n in Special Function Register SnCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in

Section

7.19.5 “Baud rate generator and selection” ).

7.19.3 Mode 2

11 bits are transmitted (through TXDn) or received (through RXDn): start bit (logic 0),

8 data bits (LSB first), a programmable 9 th

data bit, and a stop bit (logic 1). When data is transmitted, the 9 th

data bit (TB8_n in SnCON) can be assigned the value of ‘0’ or ‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8_n. When data is received, the 9 th data bit goes into RB8_n in Special Function Register SnCON, while the

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stop bit is not saved. The baud rate is programmable to either

⁄

16 or

⁄

32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. The SMOD1 bit controls the Timer

1 output rate available to both UARTs.

7.19.4 Mode 3

11 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0), 8 data bits (LSB first), a programmable 9 th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in

Section 7.19.5 “Baud rate generator and selection” ).

7.19.5 Baud rate generator and selection

Each enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1_n and BRGR0_n SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as

Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions.

The UARTs can use either Timer 1 or their respective baud rate generator output (see

Figure 8 ). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared.

The independent Baud Rate Generators use OSCCLK.

timer 1 overflow

(PCLK-based)

SMOD1 = 1

SMOD1 = 0 baud rate generator

(CCLK-based)

Fig 8.

Baud rate sources for UART (Modes 1, 3)

SBRGS = 0 baud rate modes 1 and 3

SBRGS = 1

002aaa897

7.19.6 Framing error

Framing error is reported in the status register (SnSTAT). In addition, if SMOD0 (PCON.6) is ‘1’, framing errors can be made available in SnCON.7 respectively. If SMOD0 is ‘0’,

SnCON.7 is SM0_n. It is recommended that SM0_n and SM1_n (SnCON.7:6) are set up when SMOD0 is ‘0’.

7.19.7 Break detect

Break detect is reported in the status register (SnSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.

7.19.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character.

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Double buffering can be disabled. If disabled (DBMOD_n, i.e., SnSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to

SnBUF while the previous data is being shifted out. Double buffering is only allowed in

Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled

(DBMOD_n = 0).

7.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TI_n interrupt is generated when the double buffer is ready to receive new data.

7.19.10 The 9 th

bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8_n can be written before or after SnBUF is written, as long as TB8_n is updated some time before that bit is shifted out. TB8_n must not be changed until the bit is shifted out, as indicated by the TI_n interrupt.

If double buffering is enabled, TB8_n must be updated before SnBUF is written, as TB8_n will be double-buffered together with SnBUF data.

7.20 I

C-bus serial interface

C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:

•

Bidirectional data transfer between masters and slaves

•

Multi master bus (no central master)

•

Arbitration between simultaneously transmitting masters without corruption of serial data on the bus

•

Serial clock synchronization allows devices with different bit rates to communicate via one serial bus

•

Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer

•

The I

C-bus may be used for test and diagnostic purposes.

A typical I

C-bus configuration is shown in

Figure 9 . The P89LPC952/954 device provides

a byte-oriented I

C-bus interface that supports data transfers up to 400 kHz.

P89LPC952_954_4

Product data sheet

RPU RPU

C-bus

P1.3/SDA P1.2/SCL

C MCU

OTHER DEVICE

WITH I

C-BUS

INTERFACE

OTHER DEVICE

WITH I

C-BUS

INTERFACE

002aab410

SDA

SCL

Fig 9.

C-bus configuration

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P1.3/SDA

P1.2/SCL

ADDRESS REGISTER

I2ADR

P1.3

COMPARATOR

INPUT

FILTER

OUTPUT

STAGE

INPUT

FILTER

OUTPUT

STAGE

P1.2

SHIFT REGISTER

ACK

I2DAT

BIT COUNTER /

ARBITRATION

AND SYNC LOGIC

TIMING

AND

CONTROL

LOGIC

SERIAL CLOCK

GENERATOR timer 1 overflow

I2CON

I2SCLH

I2SCLL

CONTROL REGISTERS AND

SCL DUTY CYCLE REGISTERS

CCLK interrupt status bus

STATUS

DECODER

I2STAT STATUS REGISTER

002aaa899

Fig 10. I

C-bus serial interface block diagram

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7.21 SPI

The P89LPC952/954 provides another high-speed serial communication interface — the

SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either

Master or Slave mode. It has a Transfer Completion Flag and Write Collision Flag

Protection.

CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT

SPI clock (master)

8-BIT SHIFT REGISTER

READ DATA BUFFER clock

CLOCK LOGIC

CONTROL

LOGIC

MISO

P2.3

MOSI

P2.2

SPICLK

P2.5

P2.4

MSTR

SPEN

SPI CONTROL

SPI STATUS REGISTER

SPI interrupt request

SPI CONTROL REGISTER internal data bus

002aaa900

Fig 11. SPI block diagram

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

•

SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e.,

SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.

•

SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected.

Typical connections are shown in

Figure 12

through

Figure 14 .

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7.21.1 Typical SPI configurations

P89LPC952/954

8-bit microcontroller with 10-bit ADC

master

8-BIT SHIFT

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK

PORT

Fig 12. SPI single master single slave configuration

MISO

MOSI

SPICLK

SS slave

8-BIT SHIFT

002aaa901 master

8-BIT SHIFT

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK

MISO

MOSI

SPICLK

SS slave

8-BIT SHIFT

SPI CLOCK

GENERATOR

Fig 13. SPI dual device configuration, where either can be a master or a slave

002aaa902

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master

8-BIT SHIFT

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK port

MISO

MOSI

SPICLK

SS slave

8-BIT SHIFT

MISO

MOSI slave

8-BIT SHIFT

SPICLK

002aaa903

Fig 14. SPI single master multiple slaves configuration

7.22 Analog comparators

Two analog comparators are provided on the P89LPC952/954. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes.

The overall connections to both comparators are shown in

Figure 15 . The comparators

function to V

= 2.4 V.

When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10

µ s. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

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(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

V ref(bg)

CP1 comparator 1

CO1

OE1 change detect

CN1

CMF1

CMP1 (P0.6) interrupt

CP2 comparator 2 change detect

CMF2

(P0.2) CIN2A

(P0.1) CIN2B

CMP2 (P0.0)

CO2

OE2

CN2

Fig 15. Comparator input and output connections

002aaa904

7.22.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as

V ref(bg)

, is 1.23 V

10 %.

7.22.2 Comparator interrupt

Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt.

7.22.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via

PCONA.5, or put the device in Total Power-down mode.

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7.23 KBI

The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag

(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use.

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.

7.24 Watchdog timer

The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt.

Figure 16 shows the watchdog timer in Watchdog mode.

Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few

µ s to a few seconds. Please refer to the

P89LPC952/954 User’s Manual for more details.

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Product data sheet Rev. 04 — 24 July 2008

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

WDL (C1H)

MOV WFEED1, #0A5H

MOV WFEED2, #05AH watchdog oscillator

PCLK

PRESCALER

8-BIT DOWN

COUNTER

SHADOW REGISTER reset

(1)

WDCON (A7H) PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK

002aaa905

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence.

Fig 16. Watchdog timer in Watchdog mode (WDTE = 1)

7.25 Additional features

7.25.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.

7.25.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two

Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.

7.25.3 Debugger interface

This device contains a two-wire serial debugger interface designed to be used with commercially available debugging tools. An additional trigger output is provided that maybe triggered using the two-wire debugger interface.

The Freeze register allows the user to selectively disable clocking of peripheral device timers while in the debugger mode.

The two-wire serial debugger interface can also be used be used to program the code memory of these devices.

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

7.26 Flash program memory

7.26.1 General description

The P89LPC952/954 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page

Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC952/954 flash reliably stores memory contents even after 400,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC952/954 uses V

as the supply voltage to perform the Program/Erase algorithms.

7.26.2 Features

•

Programming and erase over the full operating voltage range.

•

Byte erase allows code memory to be used for data storage.

•

Read/Programming/Erase using ISP, IAP, ICP, or two-wire serial debugger.

•

Internal fixed boot ROM, containing low-level IAP routines available to user code.

•

Default loader providing ISP via the serial port, located in upper end of user program memory.

•

Boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing flexibility to the user.

•

Any flash program/erase operation in 2 ms.

•

Programming with industry-standard commercial programmers.

•

Programmable security for the code in the flash for each sector.

•

400,000 typical erase/program cycles for each byte.

•

20 year minimum data retention.

7.26.3 Flash organization

The program memory consists of eight/sixteen 1 kB sectors on the P89LPC952/954 devices. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from

1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.

7.26.4 Using flash as data storage

The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.

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8-bit microcontroller with 10-bit ADC

7.26.5 Flash programming and erasing

Four different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP) under control of the application’s firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. As shipped from the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port. The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space.

7.26.6 ICP

ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the

P89LPC952/954 through a two-wire serial interface. The Philips ICP facility has made in-circuit programming in an embedded application—using commercially available programmers—possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature.

Additional details may be found in the P89LPC952/954 User’s Manual.

7.26.7 IAP

IAP is performed in the application under the control of the microcontroller’s firmware. The

IAP facility consists of internal hardware resources to facilitate programming and erasing.

The Philips IAP has made in-application programming in an embedded application possible without additional components. Two methods are available to accomplish IAP. A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface, PGM_MTP. Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, configuration bytes, and device ID. These functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM occupies the program memory space at the top of the address space from FF00H to

FEFFH, thereby not conflicting with the user program memory space.

In addition, IAP operations can be accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC952/954 User’s Manual.

7.26.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC952/954 through the serial port. This firmware is provided by Philips and embedded within each P89LPC952/954 device. The

Philips ISP facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (V

, V

, TXD, RXD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

7.26.9 Power-on reset code execution

The P89LPC952/954 contains two special flash elements: the Boot Vector and the Boot

Status bit. Following reset, the P89LPC952/954 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code. When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to 00H.

Table 9

shows the factory default Boot Vector setting for these devices. A factory-provided bootloader is pre-programmed into the address space indicated and uses the indicated bootloader entry point to perform ISP functions. This code can be erased by the user.

Users who wish to use this loader should take precautions to avoid erasing the

1 kB sector that contains this bootloader. Instead, the page erase function can be

used to erase the first eight 64-byte pages located in this sector. A custom bootloader can be written with the Boot Vector set to the custom bootloader, if desired.

Table 9.

Default boot vector values and ISP entry points

Device

P89LPC952

Default boot vector

1FH

Default bootloader entry point

1F00H

Default bootloader code range

1E00H to 1FFFH

P89LPC954 3FH 3F00H 3E00H to 3FFFH

1 kB sector range

1C00H to 1FFFH

3C00H to 3FFFH

7.26.10 Hardware activation of the bootloader

The bootloader can also be executed by forcing the device into ISP mode during a power-on sequence (see the P89LPC952/954

User’s Manual for specific information).

This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation. If the factory default setting for the boot vector (1FH/3FH) is changed, it will no longer point to the factory pre-programmed ISP bootloader code. After programming the flash, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address 0000H.

7.27 User configuration bytes

Some user-configurable features of the P89LPC952/954 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1. Please see the P89LPC952/954

User’s Manual for additional details.

7.28 User sector security bytes

There are eight/sixteen User Sector Security Bytes on the P89LPC952/954. Each byte corresponds to one sector. Please see the P89LPC952/954

User’s Manual for additional details.

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P89LPC952/954

8-bit microcontroller with 10-bit ADC

8. ADC

8.1 General description

The P89LPC952/954 has a 10-bit, 8-channel multiplexed successive approximation ADC module. A block diagram of the ADC is shown in

Figure 17

. The ADC consists of an

8-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a DAC which provides the other input to the comparator. The output of the comparator is fed to the SAR.

8.2 Features

10-bit, 8-channel multiplexed input, successive approximation ADC.

Eight result register pairs.

Six operating modes: u

Fixed channel, single conversion mode.

Fixed channel, continuous conversion mode.

Auto scan, single conversion mode.

Auto scan, continuous conversion mode.

Dual channel, continuous conversion mode.

Single step mode.

Three conversion start modes: u

Timer triggered start.

Start immediately.

Edge triggered.

10-bit conversion time of 4

µ s at an A/D clock of 9 MHz.

Interrupt or polled operation.

High and low boundary limits interrupt; selectable in or out-of-range.

Clock divider.

Power-down mode.

8.3 Block diagram

INPUT

MUX comp

–

DAC0

SAR

CONTROL

LOGIC

CCLK

002aab103

P89LPC952_954_4

Product data sheet

Fig 17. ADC block diagram

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8-bit microcontroller with 10-bit ADC

8.4 ADC operating modes

8.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes.

8.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the eight result register pairs. The user may select whether an interrupt can be generated after every four or every eight conversions.

Additional conversion results will again cycle through the result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user.

8.4.3 Auto scan, single conversion mode

Any combination of the eight input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel. The user may select whether an interrupt, if enabled, will be generated after either the first four conversions have occurred or all selected channels have been converted. If the user selects to generate an interrupt after the four input channels have been converted, a second interrupt will be generated after the remaining input channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode.

8.4.4 Auto scan, continuous conversion mode

Any combination of the eight input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel. The user may select whether an interrupt, if enabled, will be generated after either the first four conversions have occurred or all selected channels have been converted. If the user selects to generate an interrupt after the four input channels have been converted, a second interrupt will be generated after the remaining input channels have been converted. After all selected channels have been converted, the process will repeat starting with the first selected channel. Additional conversion results will again cycle through the eight result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user.

8.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in the result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The first channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L, etc. An interrupt is generated, if enabled, after every set of four or eight conversions (user selectable).

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8-bit microcontroller with 10-bit ADC

8.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the eight input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the ADC waits for the next start condition. May be used with any of the start modes.

8.5 Conversion start modes

8.5.1 Timer triggered start

An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all ADC operating modes.

8.5.2 Start immediately

Programming this mode immediately starts a conversion. This start mode is available in all

ADC operating modes.

8.5.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all ADC operating modes.

8.6 Boundary limits interrupt

The ADC has both a high and low boundary limit register. The user may select whether an interrupt is generated when the conversion result is within (or equal to) the high and low boundary limits or when the conversion result is outside the boundary limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria. The boundary limit may be disabled by clearing the boundary limit interrupt enable.

An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits. In this case, after the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits) an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt criteria, the boundary limits will again be compared after all 8 MSBs have been converted.

A boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt.

8.7 Clock divider

The ADC requires that its internal clock source be in the range of 320 kHz to 9 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose.

P89LPC952_954_4

Product data sheet

8.8 Power-down and Idle mode

In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit

Idle mode when the conversion is completed if the A/D interrupt is enabled. In

Power-down mode or Total Power-down mode, the ADC does not function. If the ADC is enabled, it will consume power. Power can be reduced by disabling the ADC.

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8-bit microcontroller with 10-bit ADC

9. Limiting values

Table 10.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions

T amb(bias)

T stg

OH(I/O) bias ambient temperature storage temperature

OL(I/O)

HIGH-level output current per input/output pin

LOW-level output current per input/output pin

I/Otot(max) maximum total input/output current

P n tot(pack) voltage on any other pin except V

, with respect to

DD total power dissipation (per package) based on package heat transfer, not device power consumption

Min

−

Max

+125

+150

100

3.5

1.5

Unit

C mA mA mA

[1] The following applies to

Table 10 :

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise noted.

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8-bit microcontroller with 10-bit ADC

10. Static characteristics

(dV/dt) r

(dV/dt) f

POR

DDR

V th(HL)

V th(LH)

V hys

Table 11.

Static characteristics

T amb

= 2.4 V to 3.6 V unless otherwise specified.

−

C to +85

C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions Min

DD(oper) operating supply current

[2]

= 3.6 V; f osc

= 12 MHz

= 3.6 V; f osc

= 18 MHz

[2]

DD(idle)

Idle mode supply current

[2]

= 3.6 V; f osc

= 12 MHz

= 3.6 V; f osc

= 18 MHz

[2]

DD(pd)

Power-down mode supply current

= 3.6 V; voltage comparators powered down

[2]

DD(tpd) total Power-down mode supply current

= 3.6 V

[3]

rise rate fall rate power-on reset voltage data retention supply voltage

HIGH-LOW threshold voltage

LOW-level input voltage

LOW-HIGH threshold voltage

HIGH-level input voltage hysteresis voltage

LOW-level output voltage of V

DD of V

DD except SCL, SDA

SCL, SDA only except SCL, SDA

SCL, SDA only

[4]

1.5

0.22V

−

0.5

0.7V

HIGH-level output voltage port 1

= 20 mA;

= 2.4 V to 3.6 V all ports, all modes except high-Z

= 3.2 mA; V

= 2.4 V to 3.6 V all ports, all modes except high-Z

−

= 2.4 V to 3.6 V; all ports, quasi-bidirectional mode

−

3.2 mA;

= 2.4 V to 3.6 V; all ports, push-pull mode

−

20 mA;

= 2.4 V to 3.6 V;

Port 5, push-pull mode

[4]

0.8V

−

0.3

0.7

V xtal crystal voltage

−

0.5

V n voltage on any other pin on XTAL1, XTAL2 pins; with respect to V

SS except XTAL1, XTAL2,

; with respect to V

[5]

−

0.5

P89LPC952_954_4

Product data sheet Rev. 04 — 24 July 2008

Typ

3.25

−

+4.0

+5.5

Unit

mA mA mA mA

0.5

0.4V

0.3V

0.6V

0.7V

5.5

0.2V

0.6

1.0

V mV/

µ s mV/

µ s

0.2

[1]

−

Max

0.3

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Table 11.

Static characteristics

…continued

T amb

= 2.4 V to 3.6 V unless otherwise specified.

−

C to +85

C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions Min

input capacitance

[6]

C iss

THL

LOW-level input current input leakage current

HIGH-LOW transition current

= 0.4 V

= V

, V

, or V th(HL)

[7]

[8]

[9]

−

RST_N(int) internal pull-up resistance on pin RST all ports; V

= 3.6 V

= 1.5 V at pin RST 10 brownout trip voltage BOE = 1 2.4

V bo

V ref(bg)

TC bg band gap reference voltage band gap temperature coefficient

1.19

Typ

1.23

[1]

Max

−

450

2.7

1.27

Unit

A k

Ω ppm/

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] The I

DD(oper)

, I

DD(idle)

, and I

DD(pd) specifications are measured using an external clock with the following functions disabled: comparators, real-time clock, and watchdog timer.

[3] The I

DD(tpd)

specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer.

[4] See

Section 9 “Limiting values”

for steady state (non-transient) limits on I

or I

. If I

exceeds the test condition, V

may exceed the related specification.

[5] This specification can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to V

[6] Pin capacitance is characterized but not tested.

[7] Measured with port in quasi-bidirectional mode.

[8] Measured with port in high-impedance mode.

[9] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when V

is approximately 2 V.

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8-bit microcontroller with 10-bit ADC

11. Dynamic characteristics

Table 12.

Dynamic characteristics (12 MHz)

T amb

= 2.4 V to 3.6 V unless otherwise specified.

−

C to +85

C for industrial applications, unless otherwise specified.

[1][2]

Symbol Parameter Conditions Variable clock

Min Max

f osc(RC) internal RC oscillator frequency nominal f = 7.3728 MHz trimmed to

1 % at

T amb

= 25

C; clock doubler option = OFF

(default) nominal f = 14.7456 MHz; clock doubler option = ON,

= 2.7 V to 3.6 V

7.189

14.378

7.557

15.114

f f f osc(WD)

T osc cy(clk)

CLKLP internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency see

Figure 19

320

520

8 t

Glitch filter

t gr glitch rejection time sa

P1.5/RST pin any pin except P1.5/RST signal acceptance time P1.5/RST pin any pin except P1.5/RST

External clock

t t

CHCX t

CLCX t

CLCH clock HIGH time clock LOW time clock rise time t

CHCL clock fall time

Shift register (UART mode 0)

XLXL

QVXH serial port clock cycle time output data set-up to clock rising edge time t t

XHQX

XHDX output data hold after clock rising edge time input data hold after clock rising edge time t

XHDV input data valid to clock rising edge time

SPI interface

SPI see see see see see see see see see

Figure 19

Figure 18

SPI operating frequency slave master

125

16T

13T

50 cy(clk) cy(clk)

150

T cy(clk)

− t

CLCX

T cy(clk)

− t

CHCX

cy(clk)

CCLK

+ 20

CCLK

⁄

f osc

Min

= 12 MHz

7.189

14.378 15.114 MHz

320

125

1333

1083

150

Max

7.557

520

15 ns

103

2.0

3.0

Unit

MHz kHz

MHz ns

MHz ns ns ns ns ns ns ns ns ns ns ns ns

MHz

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8-bit microcontroller with 10-bit ADC

Table 12.

Dynamic characteristics (12 MHz)

…continued

T amb

= 2.4 V to 3.6 V unless otherwise specified.

−

C to +85

C for industrial applications, unless otherwise specified.

[1][2]

Symbol Parameter Conditions Variable clock

Min Max

SPICYC

SPI cycle time see

Figure 20 ,

21 , 22 ,

slave master

⁄

CCLK

⁄

CCLK

SPILEAD

SPI enable lead time slave see

Figure 22 ,

250 t

SPILAG see

Figure 22 ,

SPICLKH

SPI enable lag time slave

SPICLK HIGH time master see

Figure 20 ,

21 , 22 ,

⁄

250

CCLK

⁄

CCLK

SPICLKL slave

SPICLK LOW time master slave see

Figure 20 ,

21 , 22 ,

⁄

CCLK

t t

SPIDSU

SPIDH

SPI data set-up time master or slave

SPI data hold time master or slave see

see

100

100 -

SPIA see

Figure 22 ,

t t t

SPIDIS

SPIDV

SPIOH

SPI access time slave

SPI disable time slave

SPI enable to output data valid time slave master

SPI output data hold time see see see

120

240

167

t t

SPIR

SPIF

SPI rise time

SPI outputs (SPICLK,

MOSI, MISO)

SPI inputs (SPICLK,

MOSI, MISO, SS)

SPI fall time

SPI outputs (SPICLK,

MOSI, MISO)

SPI inputs (SPICLK,

MOSI, MISO, SS) see

see

100

2000

100

2000

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

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Product data sheet Rev. 04 — 24 July 2008

54 of 69 f osc

= 12 MHz Unit

Min Max

500

333

ns ns

250

250 -

ns ns

165

250

165

250

ns ns

100

120 ns ns

240 ns

167 ns

100 ns

2000 ns

100 ns

2000 ns

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

Table 13.

Dynamic characteristics (18 MHz)

T amb

= 3.0 V to 3.6 V unless otherwise specified.

−

C to +85

C for industrial applications, unless otherwise specified.

[1][2]

Symbol Parameter Conditions Variable clock

f osc(RC) internal RC oscillator frequency

Min

7.189

Max

7.557

nominal f = 7.3728 MHz trimmed to

1 % at

T amb

= 25

C; clock doubler option = OFF

(default) nominal f = 14.7456 MHz; clock doubler option = ON

14.378

15.114

f osc(WD) internal watchdog oscillator frequency f osc

T cy(clk) f

CLKLP oscillator frequency clock cycle time low-power select clock frequency see

Figure 19

320

520

8 t t

Glitch filter

gr glitch rejection time sa

P1.5/RST pin any pin except P1.5/RST signal acceptance time P1.5/RST pin any pin except P1.5/RST

External clock

t t

CHCX t

CLCX t

CLCH clock HIGH time clock LOW time clock rise time t

CHCL clock fall time

Shift register (UART mode 0)

XLXL

QVXH serial port clock cycle time output data set-up to clock rising edge time t t

XHQX

XHDX output data hold after clock rising edge time input data hold after clock rising edge time t

XHDV input data valid to clock rising edge time

SPI interface

SPI see see see see see see see see see

Figure 19

Figure 18

SPICYC

SPI operating frequency slave master

SPI cycle time see

Figure 20

21 , 22 ,

slave master

⁄

16T

13T

125

50 cy(clk) cy(clk)

150

CCLK

T cy(clk)

− t

CLCX

T cy(clk)

− t

CHCX

cy(clk)

CCLK

⁄

+ 20

f osc

Min

320

125

888

722

150

333

222

= 18 MHz Unit

7.189

Max

7.557

MHz

14.378 15.114 MHz

520

15 ns

3.0

4.5

kHz

MHz ns

MHz ns ns ns ns ns ns ns ns ns ns ns ns

MHz

MHz ns ns

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Product data sheet Rev. 04 — 24 July 2008

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

Table 13.

Dynamic characteristics (18 MHz)

…continued

T amb

= 3.0 V to 3.6 V unless otherwise specified.

−

C to +85

C for industrial applications, unless otherwise specified.

[1][2]

Symbol Parameter Conditions Variable clock

Min Max

SPILEAD

SPI enable lead time see

Figure 22

SPILAG slave

SPI enable lag time see

Figure 22

250 t

SPICLKH slave

SPICLK HIGH time see

Figure 20

21 , 22 ,

250 slave master

⁄

CCLK

⁄

CCLK

t t

SPICLKL

SPICLK LOW time slave

SPIDSU master

SPI data set-up time see

see

⁄

CCLK

⁄

CCLK

SPIDH master or slave

SPI data hold time see

Figure 20

21 , 22 ,

100 t

SPIA master or slave

SPI access time see

Figure 22

100 t

SPIDIS slave

SPI disable time see

Figure 22

0 80 t

SPIDV slave

SPI enable to output data valid time slave see

Figure 20

21 , 22 ,

160

160 t

SPIOH see

Figure 20

21 , 22 ,

111

t t

SPIR

SPIF master

SPI output data hold time

SPI rise time

SPI outputs (SPICLK,

MOSI, MISO)

SPI inputs (SPICLK,

MOSI, MISO, SS)

SPI fall time

SPI outputs (SPICLK,

MOSI, MISO)

SPI inputs (SPICLK,

MOSI, MISO, SS) see see

100

2000

100

2000

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

167

111

167

111

f osc

= 18 MHz Unit

Min Max

ns 250

250 ns

ns ns ns ns

100

100 -

ns ns

80 ns

160 ns

111 ns

100 ns

2000 ns

100 ns

2000 ns

P89LPC952_954_4

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

11.1 Waveforms

XLXL clock output data write to SBUF input data t

QVXH t

XHDV clear RI

0 valid t

XHQX t

XHDX

1 valid

2 3 valid valid

4 5 valid valid

6 valid

7 set TI valid set RI

002aaa906

Fig 18. Shift register mode timing

CHCL t

CLCX

T cy(clk) t

CHCX t

CLCH

002aaa907

Fig 19. External clock timing

SS t

SPIF t

SPICLKH

SPICYC t

SPICLKL t

SPIR

SPICLK

(CPOL = 0)

(output) t

SPIF t

SPICLKL t

SPIR t

SPICLKH

SPICLK

(CPOL = 1)

(output)

MISO

(input) t

SPIDSU t

SPIDH

MSB/LSB in t

SPIDV

MOSI

(output) t

SPIF master MSB/LSB out t

SPIOH

LSB/MSB in t

SPIDV t

SPIR master LSB/MSB out

002aaa908

Fig 20. SPI master timing (CPHA = 0)

P89LPC952_954_4

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

SS t

SPIF

SPICYC t

SPIR t

SPICLKL t

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPICLK

(CPOL = 1)

(output) t t

SPIF

SPICLKH

MISO

(input)

MOSI

(output) t

SPIF t

SPIDSU t

SPIDH

MSB/LSB in t

SPIDV master MSB/LSB out t

SPICLKL t

SPIOH t

SPIR

LSB/MSB in t

SPIDV master LSB/MSB out

002aaa909 t

SPIDV t

SPIR

Fig 21. SPI master timing (CPHA = 1)

SS t

SPIR t

SPILEAD t

SPIF t

SPICLKH

SPICYC t

SPICLKL t

SPIR

SPICLK

(CPOL = 0)

(input)

SPICLK

(CPOL = 1)

(input) t

SPIA

MISO

(output) t

SPIF t

SPICLKL t

SPIR t

SPICLKH t

SPIOH t

SPIDV slave MSB/LSB out

MOSI

(input) t

SPIDSU t

SPIDH

MSB/LSB in

Fig 22. SPI slave timing (CPHA = 0)

SPIDSU t

SPIOH t

SPIDV t

SPILAG t

SPIR t

SPIOH slave LSB/MSB out not defined t

SPIDIS t

SPIDSU t

SPIDH

LSB/MSB in

002aaa910

P89LPC952_954_4

Product data sheet Rev. 04 — 24 July 2008

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

SS t

SPIR t

SPILEAD

SPICYC t

SPIF t

SPICLKH t

SPICLKL t

SPIR t

SPILAG t

SPIR

SPICLK

(CPOL = 0)

(input)

SPICLK

(CPOL = 1)

(input) t

SPIF t

SPICLKL t

SPIR t

SPICLKH t

SPIA

MISO

(output) t

SPIOH t

SPIDV not defined t

SPIOH t

SPIDV slave MSB/LSB out t

SPIOH t

SPIDV slave LSB/MSB out t

SPIDIS

MOSI

(input) t

SPIDSU t

SPIDH

MSB/LSB in t

SPIDSU

Fig 23. SPI slave timing (CPHA = 1)

11.2 ISP entry mode

Table 14.

Dynamic characteristics, ISP entry mode

T amb

= 2.4 V to 3.6 V, unless otherwise specified.

−

C to +85

C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions Min

t t

RH t

DD active to RST active delay time pin RST

RST HIGH time

RST LOW time pin RST pin RST

1 t

SPIDSU t

SPIDH

LSB/MSB in

002aaa911

Typ

Max

Unit

µ s

RST

Fig 24. ISP entry waveform

VR t

RH t

002aaa912

P89LPC952_954_4

Product data sheet

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

12. Other characteristics

12.1 Comparator electrical characteristics

Table 15.

Comparator electrical characteristics

T amb

= 2.4 V to 3.6 V, unless otherwise specified.

−

C to +85

C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions

CMRR t res(tot) t

(CE-OV)

LI input offset voltage common-mode input voltage common-mode rejection ratio total response time chip enable to output valid time input leakage current 0 V < V

< V

Min

[1]

[1] This parameter is characterized, but not tested in production.

Typ

250

Max Unit

10 mV

−

0.3

−

50 dB

500

10 ns

µ s

P89LPC952_954_4

Product data sheet Rev. 04 — 24 July 2008

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

12.2 ADC electrical characteristics

L(adj)

E u(tot)

CTC

α ct(port)

SR in

Table 16.

ADC electrical characteristics

T amb

= 2.4 V to 3.6 V, unless otherwise specified.

−

C to +85

C for industrial applications, unless otherwise specified.

All limits valid for an external source impedance of less than 10 k

Ω

Symbol Parameter Conditions

DDA(ADC)

SSA

VREFP

VREFN

IA ia

ADC analog supply voltage analog ground voltage voltage on pin VREFP voltage on pin VREFN analog input voltage analog input capacitance differential linearity error -

Min

−

0.4 -

−

0.4 -

−

0.4 -

−

0.4 -

−

0.4 -

Typ

integral non-linearity offset error gain error total unadjusted error channel-to-channel matching crosstalk between port inputs input slew rate

0 kHz to 100 kHz

T cy(ADC) t

ADC

ADC clock cycle time

ADC conversion time ADC enabled -

111

Max

+ 0.4

+4/

−

100

3125

36T cy(ADC)

LSB

LSB dB

V/ms ns

µ s

V pF

Unit

P89LPC952_954_4

Product data sheet Rev. 04 — 24 July 2008

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NXP Semiconductors

13. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

P89LPC952/954

8-bit microcontroller with 10-bit ADC

SOT187-2

D e

E y

Z E

A b p

40 b

1 w

E pin 1 index e

β k

7 e

Z D v

M A

B v

M B detail X

L p

0 5 scale

10 mm

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

UNIT A

A1 min.

A4 max.

bp b1 D

(1)

(1) e eD eE HD HE

4.57

4.19

0.51

inches

0.180

0.165

0.02

0.25

0.01

3.05

0.12

0.53

0.33

0.81

0.66

16.66

16.51

16.66

16.51

1.27

0.021

0.013

0.032

0.026

0.656

0.650

0.656

0.650

0.05

16.00

14.99

16.00

14.99

17.65

17.40

17.65

17.40

0.63

0.59

0.63

0.59

1.22

1.07

1.44

1.02

0.18

0.1

(1) max.

2.16

(1) max.

2.16

0.695

0.685

0.695

0.685

0.048

0.042

0.057

0.040

0.007

0.007 0.004

0.085

45 o

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE

VERSION

SOT187-2

IEC

112E10

REFERENCES

JEDEC JEITA

MS-018 EDR-7319

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27

01-11-14

Fig 25. Package outline SOT187-2 (PLCC44)

P89LPC952_954_4

Product data sheet Rev. 04 — 24 July 2008

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm

SOT389-1

22 ZE e

1 pin 1 index e w

M b p bp

D w

B v

M A v

M B c

1 detail X

0 2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A max.

3 b p c

mm 1.6

0.15

0.05

1.45

1.35

0.25

0.45

0.30

0.20

0.12

(1)

10.1

9.9

10.1

9.9

e H

0.8

12.15

11.85

12.15

11.85

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

L p

0.75

0.45

0.2

0.1

(1)

1.14

0.85

1.14

0.85

7 o

0 o

OUTLINE

VERSION

SOT389-1

IEC

136E08

REFERENCES

JEDEC JEITA

MS-026

EUROPEAN

PROJECTION

ISSUE DATE

00-01-19

02-06-07

Fig 26. Package outline SOT389-1 (LQFP44)

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Product data sheet Rev. 04 — 24 July 2008

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c y

24 Z E

A e

48 pin 1 index

1 e b p

D w

B w

M b p v

A v

M B

1 detail X

L p

0 2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A max.

3 b p c

mm 1.6

0.20

0.05

1.45

1.35

0.25

0.27

0.17

0.18

0.12

(1)

7.1

6.9

(1)

7.1

6.9

0.5

9.15

8.85

9.15

8.85

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

L p

0.75

0.45

0.2

w y

0.12

0.1

(1)

0.95

0.55

0.95

0.55

7 o

0 o

OUTLINE

VERSION

SOT313-2

IEC

136E05

REFERENCES

JEDEC JEITA

MS-026

EUROPEAN

PROJECTION

ISSUE DATE

00-01-19

03-02-25

Fig 27. Package outline SOT313-2 (LQFP48)

P89LPC952_954_4

Product data sheet Rev. 04 — 24 July 2008

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

14. Abbreviations

Table 17.

Abbreviations

Acronym

ADC

Description

Analog-to-Digital Converter

BOE

CPU

CCU

CRC

BrownOut Enable

Central Processing Unit

Capture/Compare Unit

Cyclic Redundancy Check

DAC

EPROM

EMI

IAP

LSB

MSB

PWM

RAM

Digital-to-Analog Converter

Erasable Programmable Read-Only Memory

ElectroMagnetic Interference

In-Application Programming

Least Significant Bit

Most Significant Bit

Pulse Width Modulator

Random Access Memory

RTC

SAR

SFR

SPI

UART

Resistance-Capacitance

Real-Time Clock

Successive Approximation Register

Special Function Register

Serial Peripheral Interface

Universal Asynchronous Receiver/Transmitter

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Product data sheet Rev. 04 — 24 July 2008

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

15. Revision history

Table 18.

Revision history

Document ID

P89LPC952_954_4

Modifications:

P89LPC952_954_3

Release date Data sheet status Change notice

20080724 Product data sheet -

•

Figure 2 “Functional diagram” : Updated port 2 information.

20080605 Product data sheet -

P89LPC952_954_2

P89LPC952_1

20071219

20050916

Preliminary data sheet

Preliminary data sheet -

Supersedes

P89LPC952_954_3

P89LPC952_954_2

P89LPC952_1

P89LPC952_954_4

Product data sheet Rev. 04 — 24 July 2008

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NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

16. Legal information

16.1

Data sheet status

Document status

[1][2]

Objective [short] data sheet

Product status

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[3]

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

16.2

Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

16.3

Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.4

Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit:

http://www.nxp.com

For sales office addresses, please send an email to:

[email protected]

P89LPC952_954_4

Product data sheet

67 of 69 Rev. 04 — 24 July 2008

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

18. Contents

2.1

2.2

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Principal features . . . . . . . . . . . . . . . . . . . . . . . 1

Additional features . . . . . . . . . . . . . . . . . . . . . . 2

3.1

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.1

6.2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

Pinning information . . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

7 Functional description . . . . . . . . . . . . . . . . . . 14

Special function registers . . . . . . . . . . . . . . . . 14

Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 23

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 23

CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 23

Low speed oscillator option . . . . . . . . . . . . . . 23

Medium speed oscillator option . . . . . . . . . . . 23

High speed oscillator option . . . . . . . . . . . . . . 23

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24

On-chip RC oscillator option . . . . . . . . . . . . . . 24

Watchdog oscillator option . . . . . . . . . . . . . . . 24

External clock input option . . . . . . . . . . . . . . . 24

CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 25

CCLK modification: DIVM register . . . . . . . . . 25

Low power select . . . . . . . . . . . . . . . . . . . . . . 25

Memory organization . . . . . . . . . . . . . . . . . . . 26

Data RAM arrangement . . . . . . . . . . . . . . . . . 26

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

External interrupt inputs . . . . . . . . . . . . . . . . . 27

7.13

7.13.1

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Port configurations . . . . . . . . . . . . . . . . . . . . . 29

7.13.1.1

Quasi-bidirectional output configuration . . . . . 29

7.13.1.2

Open-drain output configuration . . . . . . . . . . . 29

7.13.1.3

Input-only configuration . . . . . . . . . . . . . . . . . 30

7.13.1.4

Push-pull output configuration . . . . . . . . . . . . 30

7.13.2

7.13.3

Port 0 analog functions . . . . . . . . . . . . . . . . . . 30

Additional port features. . . . . . . . . . . . . . . . . . 30

Power monitoring functions. . . . . . . . . . . . . . . 30

Brownout detection . . . . . . . . . . . . . . . . . . . . . 30

Power-on detection . . . . . . . . . . . . . . . . . . . . . 31

Power reduction modes . . . . . . . . . . . . . . . . . 31

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power-down mode . . . . . . . . . . . . . . . . . . . . . 31

Total Power-down mode . . . . . . . . . . . . . . . . . 31

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . 33

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Timer overflow toggle output . . . . . . . . . . . . . 34

RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 34

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Baud rate generator and selection . . . . . . . . . 35

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 35

Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Double buffering . . . . . . . . . . . . . . . . . . . . . . . 35

Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . 36

7.19.10

The 9 th

bit (bit 8) in double buffering

7.20

(Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . 36

C-bus serial interface . . . . . . . . . . . . . . . . . . 36

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Typical SPI configurations . . . . . . . . . . . . . . . 39

Analog comparators . . . . . . . . . . . . . . . . . . . . 40

Internal reference voltage. . . . . . . . . . . . . . . . 41

Comparator interrupt . . . . . . . . . . . . . . . . . . . 41

Comparators and power reduction modes . . . 41

KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 42

Additional features . . . . . . . . . . . . . . . . . . . . . 43

Software reset . . . . . . . . . . . . . . . . . . . . . . . . 43

Dual data pointers . . . . . . . . . . . . . . . . . . . . . 43

Debugger interface. . . . . . . . . . . . . . . . . . . . . 43

Flash program memory . . . . . . . . . . . . . . . . . 44

General description . . . . . . . . . . . . . . . . . . . . 44

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Flash organization . . . . . . . . . . . . . . . . . . . . . 44

Using flash as data storage . . . . . . . . . . . . . . 44

Flash programming and erasing. . . . . . . . . . . 45

ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.26.8

7.26.9

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Power-on reset code execution . . . . . . . . . . . 46

7.26.10

Hardware activation of the bootloader . . . . . . 46

7.27

User configuration bytes. . . . . . . . . . . . . . . . . 46

7.28

User sector security bytes . . . . . . . . . . . . . . . 46

continued >>

P89LPC952_954_4

Product data sheet

68 of 69 Rev. 04 — 24 July 2008

NXP Semiconductors

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

General description. . . . . . . . . . . . . . . . . . . . . 47

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 47

ADC operating modes . . . . . . . . . . . . . . . . . . 48

Fixed channel, single conversion mode . . . . . 48

Fixed channel, continuous conversion mode . 48

Auto scan, single conversion mode . . . . . . . . 48

Auto scan, continuous conversion mode . . . . 48

Dual channel, continuous conversion mode . . 48

Single step mode . . . . . . . . . . . . . . . . . . . . . . 49

Conversion start modes . . . . . . . . . . . . . . . . . 49

Timer triggered start . . . . . . . . . . . . . . . . . . . . 49

Start immediately . . . . . . . . . . . . . . . . . . . . . . 49

Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 49

Boundary limits interrupt. . . . . . . . . . . . . . . . . 49

Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Power-down and Idle mode . . . . . . . . . . . . . . 49

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 50

Static characteristics. . . . . . . . . . . . . . . . . . . . 51

Dynamic characteristics . . . . . . . . . . . . . . . . . 53

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . 59

Other characteristics . . . . . . . . . . . . . . . . . . . . 60

Comparator electrical characteristics . . . . . . . 60

ADC electrical characteristics . . . . . . . . . . . . . 61

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 62

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 66

Legal information. . . . . . . . . . . . . . . . . . . . . . . 67

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 67

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Contact information. . . . . . . . . . . . . . . . . . . . . 67

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

P89LPC952/954

8-bit microcontroller with 10-bit ADC

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 24 July 2008

Document identifier: P89LPC952_954_4

Sveiki! Aš esu AI pokalbių robotas, specialiai apmokytas padėti jums su NXP P89LPC952FBD 8-bit microcontroller Data Sheet. Aš kruopščiai peržiūrėjau dokumentą ir galiu padėti jums rasti tikslią reikiamą informaciją arba paaiškinti turinį aiškiais ir paprastais terminais. Nesvarbu, ar ieškote patarimų dėl konkrečių funkcijų, trikčių šalinimo veiksmų ar bendro naudojimo, nedvejodami užduokite savo klausimus. Kuo daugiau informacijos pateiksite apie savo rūpesčius ar poreikius, tuo tiksliau ir efektyviau galėsiu jums padėti!

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Reklama

8-bit microcontroller with accelerated two-clock 80C51 core

8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC

1.

General description

2.

Features

3.

Ordering information

4.

Block diagram

5.

Functional diagram

6.

Pinning information

7.

Functional description

8.

ADC

9.

Limiting values

10. Static characteristics

11. Dynamic characteristics

12. Other characteristics

13. Package outline

14. Abbreviations

15. Revision history

16. Legal information

17. Contact information

18. Contents

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