NXP 68HC705KJ1 Microcontroller Data Sheet
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MC68HC705KJ1
MC68HRC705KJ1
MC68HLC705KJ1
Data Sheet
M68HC05
Microcontrollers
MC68HC705KJ1
Rev. 4.1
07/2005
freescale.com
MC68HC705JK1
MC68HRC705KJ1
MC68HLC705KJ1
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com
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© Freescale Semiconductor, Inc., 2005. All rights reserved.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 3
Revision History
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
Revision
Level
April, 2002
May, 2003
July, 2005
3.0
4.0
4.1
Description
Figure 1-4. Crystal Connections with Oscillator Internal Resistor Mask
Option — changed PA7 designator to OSC1 in two places
Figure 1-5. Crystal Connections without Oscillator Internal Resistor Mask
Option — changed PA7 designator to OSC1 in two places
Figure 1-6. Ceramic Resonator Connections with Oscillator Internal
Resistor Mask Option — changed PA7 designator to OSC1 in two places
Figure 1-7. Ceramic Resonator Connections without Oscillator Internal
Resistor Mask Option — changed PA7 designator to OSC1 in two places
Figure 1-8. External Clock Connections — changed PA7 designator to
OSC1 in two places
Figure B-1. Crystal Connections — added OSC2 designation
Table B-3. MC68HLC705KJ1 (Low Frequency) Order Numbers —
Corrected table title
Reformatted to new publications standards.
Figure A-2. Typical Internal Operating Frequency for Various VDD at 25 ° C
— RC Oscillator Option Only — replaced graph
Updated to meet Freescale identity guidelines.
Page
Number(s)
Throughout
Throughout
4
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
List of Chapters
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 5
List of Chapters
6
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Table of Contents
Chapter 1
Introduction
Chapter 2
Memory
Chapter 3
Computer Operating Properly Module (COP)
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 7
Table of Contents
Chapter 4
Central Processor Unit (CPU)
Chapter 5
External Interrupt Module (IRQ)
8
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 6
Low-Power Modes
Chapter 7
Parallel I/O Ports (PORTS)
Chapter 8
Resets and Interrupts
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 9
Table of Contents
Chapter 9
Multifunction Timer Module
Chapter 10
Electrical Specifications
Chapter 11
Ordering Information and Mechanical Specifications
10
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Appendix A
MC68HRC705KJ1
Typical Internal Operating Frequency Versus Temperature (No External Resistor) . . . . . . . . 104
Appendix B
MC68HLC705KJ1
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 11
Table of Contents
12
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 1
Introduction
1.1 Features
Features on the MC68HC705KJ1 include:
• Robust noise immunity
• 4.0-MHz internal operating frequency at 5.0 V
• 1240 Bytes of EPROM/OTPROM (electrically programmable read-only memory/one-time programmable read-only memory), including eight bytes for user vectors
• 64 bytes of user RAM
• Peripheral modules:
– 15-stage multifunction timer
– Computer operating properly (COP) watchdog
• 10 bidirectional input/output (I/O) lines, including:
– 10-mA sink capability on all I/O pins
– Software programmable pulldowns on all I/O pins
– Keyboard scan with selectable interrupt on four I/O pins
– 5.5-mA source capability on six I/O pins
• Selectable sensitivity on external interrupt (edge- and level-sensitive or edge-sensitive only)
• On-chip oscillator with connections for:
– Crystal
– Ceramic resonator
– Resistor-capacitor (RC) oscillator (MC68HRC705KJ1) with or without external resistor
– External clock
– Low-speed (32-kHz) crystal (MC68HLC705KJ1)
• Memory-mapped I/O registers
• Fully static operation with no minimum clock speed
• Power-saving stop, halt, wait, and data-retention modes
• External interrupt mask bit and acknowledge bit
• Illegal address reset
• Internal steering diode and pullup resistor from RESET pin to V
DD
• Selectable EPROM security
(1)
• Selectable oscillator bias resistor
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 13
Introduction
1.2 Structure
OSC1
OSC2
INTERNAL
OSCILLATOR
RESET
IRQ/V
PP
DIVIDE
BY ³2
15-STAGE
MULTIFUNCTION
TIMER SYSTEM
WATCHDOG AND
ILLEGAL ADDRESS
DETECT
CPU CONTROL
68HC05 CPU
ALU
PB3
(1)
CPU REGISTERS
ACCUMULATOR
INDEX REGISTER
0 0 0 0 0 0 0 0 1 1 STK PTR
PROGRAM COUNTER
CONDITION CODE
REGISTER
1 1 1 H I N Z C
PB2
(1)
STATIC RAM (SRAM) – 64 BYTES
PA7
PA6
PA5
PA4
PA3
(1) (2)
PA2
(1) (2)
PA1
(1) (2)
PA0
(1) (2)
USER EPROM – 1240 BYTES
MASK OPTION REGISTER (MOR)
Figure 1-1. Block Diagram
10-mA sink capability on all I/O pins
Notes:
1. 5.5 mA source capability
2. External interrupt capability
14
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Programmable Options
1.3 Programmable Options
The options in Table 1-1 are programmable in the mask option register.
Table 1-1. Programmable Options
Feature
COP watchdog timer
External interrupt triggering
Port A IRQ pin interrupts
Port pulldown resistors
STOP instruction mode
Crystal oscillator internal resistor
EPROM security
Short oscillator delay counter
Option
Enabled or disabled
Edge-sensitive only or edge- and level-sensitive
Enabled or disabled
Enabled or disabled
Stop mode or halt mode
Enabled or disabled
Enabled or disabled
Enabled or disabled
1.4 Pin Functions
Pin assignments are shown in Figure 1-2 with the functions described in the following subsections.
RESET 1
OSC1 2
OSC2 3
PB3 4
PB2 5
16 IRQ/V
PP
15 PA0
14 PA1
13 PA2
12 PA3
V
DD
6
V
SS
7
PA7 8
11 PA4
10 PA5
9 PA6
Figure 1-2. Pin Assignments
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 15
Introduction
1.4.1 V
DD
and V
SS
V
DD
and V
SS
are the power supply and ground pins. The MCU operates from a single power supply.
Very fast signal transitions occur on the MCU pins, placing high, short-duration current demands on the power supply. To prevent noise problems, take special care, as
shows, by placing the bypass capacitors as close as possible to the MCU. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels.
V+
V
DD
V
DD
C2 C1
MCU
C1
0.1
µ
F
+
C2
V
SS
V
SS
Figure 1-3. Bypassing Layout Recommendation
1.4.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The oscillator can be driven by any of the following:
1.
Standard crystal (See Figure 1-4 and Figure 1-5 .)
2.
Ceramic resonator (See Figure 1-6
and
3.
Resistor/capacitor (RC) oscillator (Refer to
.)
4.
External clock signal as shown in (See Figure 1-8
.)
5.
Low speed (32 kHz) crystal connections (Refer to Appendix B MC68HLC705KJ1 .)
The frequency, f
OSC
, of the oscillator or external clock source is divided by two to produce the internal operating frequency, f
OP
.
1.4.2.1 Crystal Oscillator
and
Figure 1-5 show a typical crystal oscillator circuit for an AT-cut, parallel resonant crystal.
Follow the crystal supplier’s recommendations, as the crystal parameters determine the external component values required to provide reliable startup and maximum stability. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances.
To minimize output distortion, mount the crystal and capacitors as close as possible to the pins. An internal startup resistor of approximately 2 M
Ω
is provided between OSC1 and OSC2 for the crystal oscillator as a programmable mask option.
NOTE
Use an AT-cut crystal and not an AT-strip crystal because the MCU can overdrive an AT-strip crystal.
16
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Pin Functions
V
SS
MCU
C3
OSC1
XTAL
OSC2
C4
XTAL
C3
27 pF
C4
27 pF
V
DD
C2 C1
V
SS
C3
27 pF
Figure 1-4. Crystal Connections with
Oscillator Internal Resistor Mask Option
V
SS
MCU
C3
OSC1
XTAL R
R
10 M
Ω
OSC2
C4
XTAL
V
DD
C4
27 pF
C2 C1
V
SS
Figure 1-5. Crystal Connections without
Oscillator Internal Resistor Mask Option
1.4.2.2 Ceramic Resonator Oscillator
To reduce cost, use a ceramic resonator instead of the crystal. The circuits shown in Figure 1-6
and
show ceramic resonator circuits. Follow the resonator manufacturer’s recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately 2 M
Ω
is provided between OSC1 and OSC2 as a programmable mask option.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 17
Introduction
MCU
V
SS
C3
OSC1
C3
27 pF
OSC2
CERAMIC
RESONATOR
C4
27 pF
C4
V
DD
C2 C1
V
SS
Figure 1-6. Ceramic Resonator Connections with
Oscillator Internal Resistor Mask Option
V
SS
C3
MCU
OSC1
R
R
10 M
Ω OSC2
C4
V
DD
C3
27 pF
CERAMIC
RESONATOR
C4
27 pF
C2 C1
V
SS
Figure 1-7. Ceramic Resonator Connections without
Oscillator Internal Resistor Mask Option
1.4.2.3 RC Oscillator
Refer to Appendix A MC68HRC705KJ1 .
18
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Pin Functions
1.4.2.4 External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the
OSC2 input not connected, as shown in Figure 1-8
. This configuration is possible regardless of whether the crystal/ceramic resonator or the RC oscillator is enabled.
MCU
EXTERNAL
CMOS CLOCK
Figure 1-8. External Clock Connections
1.4.3 RESET
Applying a logic 0 to the RESET pin forces the MCU to a known startup state. An internal reset also pulls the RESET pin low. An internal resistor to V
DD
pulls the RESET pin high. A steering diode between the
RESET and V
DD pins discharges any RESET pin voltage when power is removed from the MCU. The
RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. Refer to
Chapter 8 Resets and Interrupts
for more information.
1.4.4 IRQ/V
PP
The external interrupt/programming voltage pin (IRQ/V
PP
) drives the asynchronous IRQ interrupt function of the CPU. Additionally, it is used to program the user EPROM and mask option register. (See
and Chapter 5 External Interrupt Module (IRQ) .)
The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function.
If level-sensitive triggering is selected, the IRQ/V
PP
input requires an external resistor to V
DD
for wired-OR operation. If the IRQ/V
PP
pin is not used, it must be tied to the V
DD
supply.
The IRQ/V
PP
pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin should not exceed V
DD
except when the pin is being used for programming the
EPROM.
NOTE
The mask option register can enable the PA0 – PA3 pins to function as external interrupt pins.
1.4.5 PA0–PA7
These eight input/output (I/O) lines comprise port A, a general-purpose bidirectional I/O port. (See
Chapter 5 External Interrupt Module (IRQ) for information on PA0–PA3 external interrupts.)
1.4.6 PB2 and PB3
These two I/O lines comprise port B, a general-purpose bidirectional I/O port.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 19
Introduction
20
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
This section provides:
• Memory map (
•
Summary of the input/output registers ( Figure 2-2 )
• Description of:
– Random-access memory (RAM)
– EPROM/OTPROM (electrically programmable read-only memory/one-time programmable read-only memory)
– Mask option register
Memory features include:
• 1232 Bytes of User EPROM, Plus Eight Bytes for User Vectors
• 64 Bytes of User RAM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can have unpredictable effects on MCU operation. In
and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-2 and in
register figures in this document, reserved locations are marked with the word Reserved or with the letter R.
2.4 Memory Map
See
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 21
Memory
$0100
↓
$02FF
$0300
↓
$07CF
$07D0
↓
$07ED
$07EE
$0000
↓
$001F
$0020
↓
$00BF
$00C0
↓
$00FF
$07EF
$07F0
↓
$07FF
I/O REGISTERS
32 BYTES
UNIMPLEMENTED
160 BYTES
RAM
64 BYTES
UNIMPLEMENTED
512 BYTES
EPROM
1232 BYTES
UNIMPLEMENTED
30 BYTES
TEST ROM
2 BYTES
PORT A DATA REGISTER (PORTA)
PORT B DATA REGISTER (PORTB)
$0000
$0001
$0002
UNIMPLEMENTED
DATA DIRECTION REGISTER A (DDRA)
$0003
$0004
DATA DIRECTION REGISTER B (DDRB) $0005
$0006
UNIMPLEMENTED
$0007
TIMER STATUS AND CONTROL REGISTER (TSCR) $0008
TIMER CONTROL REGISTER (TCR)
IRQ STATUS AND CONTROL REGISTER (ISCR)
UNIMPLEMENTED
PULLDOWN REGISTER PORT A (PDRA)
PULLDOWN REGISTER PORT B (PDRB)
$0009
$000A
$000B
↓
$000F
$0010
UNIMPLEMENTED
EPROM PROGRAMMING REGISTER (EPROG)
UNIMPLEMENTED
RESERVED
$0011
$0012
↓
$0017
$0018
$0019
↓
$001E
$001F
COP REGISTER (COPR)
(1)
MASK OPTION REGISTER (MOR)
RESERVED
REGISTERS AND EPROM
16 BYTES
TIMER INTERRUPT VECTOR HIGH
TIMER INTERRUPT VECTOR LOW
EXTERNAL INTERRUPT VECTOR HIGH
EXTERNAL INTERRUPT VECTOR LOW
SOFTWARE INTERRUPT VECTOR HIGH
SOFTWARE INTERRUPT VECTOR LOW
RESET VECTOR HIGH
RESET VECTOR LOW
Note 1.
Writing to bit 0 of $07F0 clears the COP watchdog.
Figure 2-1. Memory Map
$07F9
$07FA
$07FB
$07FC
$07FD
$07FE
$07FF
$07F0
$07F1
$07F2
↓
$07F7
$07F8
22
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
2.5 Input/Output Register Summary
Addr.
Bit 7 6
$0000
$0001
Register Name
Port A Data Register
(PORTA)
Read:
Write:
Reset:
Port B Data Register
(PORTB)
Read:
Write:
Reset:
PA7
0
PA6
0
5
PA5
4
PA4
3
PA3
Unaffected by reset
Refer to
Chapter 7 Parallel I/O Ports (PORTS)
PB3
Unaffected by reset
Input/Output Register Summary
2
PA2
1
PA1
Bit 0
PA0
PB2
Refer to
Chapter 7 Parallel I/O Ports (PORTS)
$0002
$0003
Unimplemented
Unimplemented
$0004
$0005
Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Read:
Write:
Reset:
Read:
Write:
Reset:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
0
0
Refer to
0
0
Chapter 7 Parallel I/O Ports (PORTS)
0
0
DDRB3
0
0
DDRB2
0
0
Refer to
Chapter 7 Parallel I/O Ports (PORTS)
0
0
0
$0006
$0007
Unimplemented
Unimplemented
$0008
$0009
$000A
Timer Status and Control
Register (TSCR)
Read:
Write:
Reset:
TOF
0
Timer Counter Register
(TCR)
IRQ Status and Control Register (ISCR)
Read:
Write:
Reset:
Read:
Write:
Reset:
TCR7
0
IRQE
1
RTIF
0
TCR6
0
0
0
TOIE
0
TCR5
0
0
0
RTIE
0
TCR4
0
0
R
0
0
TOFR
0
TCR3
0
IRQF
0
0
RTIFR
0
TCR2
0
0
0
RT1
1
TCR1
0
0
IRQR
0
0
0
0
RT0
1
TCR0
= Unimplemented R = Reserved
Figure 2-2. I/O Register Summary (Sheet 1 of 2)
U = Unaffected
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 23
Memory
Addr.
$000B
↓
$000F
Register Name
Unimplemented
Unimplemented
$0012
↓
$0017
Unimplemented
Unimplemented
Bit 7
$0010
$0011
Pulldown Register Port A
(PDRA)
Read:
Write:
Reset:
Read:
PDIA7
0
Pulldown Register Port B
(PDRB)
Write:
Reset: 0
6
PDIA6
0
0
5
PDIA5
0
4
PDIA4
0
3
PDIA3
0
Refer to
Chapter 7 Parallel I/O Ports (PORTS)
0 0
PDIB3
0
2
PDIA2
0
PDIB2
0
1
PDIA1
0
Bit 0
PDIA0
0
Refer to
Chapter 7 Parallel I/O Ports (PORTS)
0 0
$0018
EPROM Programming
Register (EPROG)
Read:
Write:
Reset:
0
0
0
R
0
0
R
0
0
R
0
0
R
0
$0019
↓
$001E
$001F
Unimplemented
Unimplemented
Reserved R R R R R
$07F0
$07F1
COP Register (COPR)
Read:
Write:
Reset:
Read:
Mask Option Register (MOR)
Write:
Reset:
U U U U
SOSCD EPMSEC OSCRES SWAIT
U
PDI
Unaffected by reset
ELAT
0
R
U
PIRQ
MPGM
0
EPGM
0
R R
U
LEVEL
COPC
0
COPEN
= Unimplemented R = Reserved
Figure 2-2. I/O Register Summary (Sheet 2 of 2)
U = Unaffected
24
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
RAM
2.6 RAM
The 64 addresses from $00C0 to $00FF serve as both the user RAM and the stack RAM. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements when the CPU stores a byte on the stack and increments when the CPU retrieves a byte from the stack.
NOTE
Be careful when using nested subroutines or multiple interrupt levels. The
CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
2.7 EPROM/OTPROM
An MCU with a quartz window has 1240 bytes of erasable, programmable ROM (EPROM). The quartz window allows EPROM erasure with ultraviolet light.
NOTE
Keep the quartz window covered with an opaque material except when erasing the MCU. Ambient light can affect MCU operation.
In an MCU without the quartz window, the EPROM cannot be erased and serves as 1240 bytes of one-time programmable ROM (OTPROM).
The following addresses are user EPROM/OTPROM locations:
• $0300–$07CF
• $07F8–$07FF, used for user-defined interrupt and reset vectors
The COP register (COPR) is an EPROM/OTPROM location at address $07F0.
The mask option register (MOR) is an EPROM/OTPROM location at address $07F1.
2.7.1 EPROM/OTPROM Programming
The two ways to program the EPROM/OTPROM are:
• Manipulating the control bits in the EPROM programming register to program the
EPROM/OTPROM on a byte-by-byte basis
• Programming the EPROM/OTPROM with the M68HC705J In-Circuit Simulator (M68HC705JICS) available from Freescale
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 25
Memory
2.7.2 EPROM Programming Register
The EPROM programming register (EPROG) contains the control bits for programming the
EPROM/OTPROM.
Address: $0018
Read:
Bit 7
0
Write:
Reset: 0
R
0
6
0
= Unimplemented
R
0
5
0
R
0
4
0
R
R
0
3
0
= Reserved
2
ELAT
0
1
MPGM
0
Figure 2-3. EPROM Programming Register (EPROG)
Bit 0
EPGM
0
ELAT — EPROM Bus Latch Bit
This read/write bit latches the address and data buses for EPROM/OTPROM programming. Clearing the ELAT bit automatically clears the EPGM bit. EPROM/OTPROM data cannot be read while the
ELAT bit is set. Reset clears the ELAT bit.
1 = Address and data buses configured for EPROM/OTPROM programming the EPROM
0 = Address and data buses configured for normal operation
MPGM — MOR Programming Bit
This read/write bit applies programming power from the IRQ/V
PP
pin to the mask option register. Reset clears MPGM.
1 = Programming voltage applied to MOR
0 = Programming voltage not applied to MOR
EPGM — EPROM Programming Bit
This read/write bit applies the voltage from the IRQ/V
PP pin to the EPROM. To write the EPGM bit, the
ELAT bit must be set already. Reset clears EPGM.
1 = Programming voltage (IRQ/V
PP
pin) applied to EPROM
0 = Programming voltage (IRQ/V
PP
pin) not applied to EPROM
NOTE
Writing logic 1s to both the ELAT and EPGM bits with a single instruction sets ELAT and clears EPGM. ELAT must be set first by a separate instruction.
Bits [7:3] — Reserved
Take the following steps to program a byte of EPROM/OTPROM:
1.
Apply the programming voltage, V
PP
, to the IRQ/V
PP
pin.
2.
Set the ELAT bit.
3.
Write to any EPROM/OTPROM address.
4.
Set the EPGM bit and wait for a time, t
EPGM
.
5.
Clear the ELAT bit.
2.7.3 EPROM Erasing
The erased state of an EPROM bit is logic 0. Erase the EPROM by exposing it to 15 Ws/cm
2
of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source one inch from the EPROM.
Do not use a shortwave filter.
26
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Mask Option Register
2.8 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that controls the following options:
• COP watchdog (enable or disable)
• External interrupt pin triggering (edge-sensitive only or edge- and level-sensitive)
• Port A external interrupts (enable or disable)
• Port pulldown resistors (enable or disable)
• STOP instruction (stop mode or halt mode)
• Crystal oscillator internal resistor (enable or disable)
• EPROM security (enable or disable)
• Short oscillator delay (enable or disable)
Take the following steps to program the mask option register (MOR):
1.
Apply the programming voltage, V
PP
, to the IRQ/V
PP
pin.
2.
Write to the MOR.
3.
Set the MPGM bit and wait for a time, t
MPGM
.
4.
Clear the MPGM bit.
5.
Reset the MCU.
Address: $07F1
Bit 7
Read:
6 5 4
SOSCD EPMSEC OSCRES SWAIT
Write:
Reset:
3
SWPDI
Unaffected by reset
2
PIRQ
Figure 2-4. Mask Option Register (MOR)
1
LEVEL
Bit 0
COPEN
SOSCD — Short Oscillator Delay Bit
The SOSCD bit controls the oscillator stabilization counter. The normal stabilization delay following reset or exit from stop mode is 4064 t cyc
. Setting SOSCD enables a 128 t cyc
stabilization delay.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
EPMSEC — EPROM Security Bit
The EPMSEC bit controls access to the EPROM/OTPROM.
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
OSCRES — Oscillator Internal Resistor Bit
The OSCRES bit enables a 2-M
Ω
internal resistor in the oscillator circuit.
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
NOTE
Program the OSCRES bit to logic 0 in devices using low-speed crystal or
RC oscillators with external resistor.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 27
Memory
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the CPU interprets the STOP instruction as a WAIT instruction, and the MCU enters halt mode. Halt mode is the same as wait mode, except that an oscillator stabilization delay of 1 to 4064 t cyc
occurs after exiting halt mode.
1 = Halt mode enabled
0 = Halt mode not enabled
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown devices. The SWPDI bit overrides the pulldown inhibit bits in the port pulldown inhibit registers.
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
PIRQ — Port A External Interrupt Bit
The PIRQ bit enables the PA0–PA3 pins to function as external interrupt pins.
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
LEVEL —External Interrupt Sensitivity Bit
The LEVEL bit controls external interrupt triggering sensitivity.
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
COPEN — COP Enable Bit
The COPEN bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
2.9 EPROM Programming Characteristics
Table 2-1. EPROM Programming Characteristics
(1)
Symbol Min Characteristic
Programming Voltage
IRQ/V
PP
Programming Current
IRQ/V
PP
Programming Time
Per Array Byte
MOR
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= –40
°
C to +85
°
C
V
PP
I
PP t
EPGM t
MPGM
16.0
—¦
4
4
Typ
16.5
3.0
—
—
Max
17.0
10.0
—
—
Unit
V mA ms
28
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 3
Computer Operating Properly Module (COP)
3.1 Introduction
The computer operating properly (COP) watchdog resets the MCU in case of software failure. Software that is operating properly periodically services the COP watchdog and prevents COP reset. The COP watchdog function is programmable by the COPEN bit in the mask option register.
3.2 Features
The computer operating properly module (COP) includes these features:
• Protection from runaway software
• Wait mode and halt mode operations
3.3 Operation
Operation of the COP module is discussed here.
3.3.1 COP Watchdog Timeout
Four counter stages at the end of the timer make up the COP watchdog. The COP resets the MCU if the timeout period occurs before the COP watchdog timer is cleared by application software and the IRQ/V
PP pin voltage is between V
SS
and V
DD
. Periodically clearing the counter starts a new timeout period and prevents COP reset. A COP watchdog timeout indicates that the software is not executing instructions in the correct sequence.
NOTE
The internal clock drives the COP watchdog. Therefore, the COP watchdog cannot generate a reset for errors that cause the internal clock to stop.
The COP watchdog depends on a power supply voltage at or above a minimum specification and is not guaranteed to protect against brownout.
3.3.2 COP Watchdog Timeout Period
The COP watchdog timer function is implemented by dividing the output of the real-time interrupt circuit
(RTI) by eight. The RTI select bits in the timer status and control register control RTI output, and the selected output drives the COP watchdog. (See timer status and control register in
NOTE
The minimum COP timeout period is seven times the RTI period. The COP is cleared asynchronously with the value in the RTI divider; hence, the COP timeout period will vary between 7x and 8x the RTI period.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 29
Computer Operating Properly Module (COP)
3.3.3 Clearing the COP Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register at location $07F0
(see Figure 3-1 ). Clearing the COP bit disables the COP watchdog timer regardless of
the IRQ/V
PP
pin voltage.
If the main program executes within the COP timeout period, the clearing routine should be executed only once. If the main program takes longer than the COP timeout period, the clearing routine must be executed more than once.
NOTE
Place the clearing routine in the main program and not in an interrupt routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating properly.
3.4 Interrupts
The COP watchdog does not generate interrupts.
3.5 COP Register
The COP register (COPR) is a write-only register that returns the contents of EPROM location $07F0 when read.
Address: $07F0
Bit 7
Read:
Write:
Reset: U
6 5 4 3 2 1
U
Bit 0
COPC
0 U
= Unimplemented
U U
U = Unaffected
U
Figure 3-1. COP Register (COPR)
U
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0 returns undefined results.
3.6 Low-Power Modes
The STOP and WAIT instructions have the following effects on the COP watchdog.
3.6.1 Stop Mode
The STOP instruction clears the COP watchdog counter and disables the clock to the COP watchdog.
NOTE
To prevent the STOP instruction from disabling the COP watchdog, program the stop-to-wait conversion bit (SWAIT) in the mask option register to logic 1.
30
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Low-Power Modes
Upon exit from stop mode by external reset:
• The counter begins counting from $0000.
• The counter is cleared again after the oscillator stabilization delay and begins counting from $0000 again.
Upon exit from stop mode by external interrupt:
• The counter begins counting from $0000.
• The counter is not cleared again after the oscillator stabilization delay and continues counting throughout the oscillator stabilization delay.
NOTE
Immediately after exiting stop mode by external interrupt, service the COP to ensure a full COP timeout period.
3.6.2 Wait Mode
The WAIT instruction has no effect on the COP watchdog.
NOTE
To prevent a COP timeout during wait mode, exit wait mode periodically to service the COP.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 31
Computer Operating Properly Module (COP)
32
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 4
Central Processor Unit (CPU)
4.1 Introduction
The central processor unit (CPU) consists of a CPU control unit, an arithmetic/logic unit (ALU), and five
CPU registers. The CPU control unit fetches and decodes instructions. The ALU executes the instructions. The CPU registers contain data, addresses, and status bits that reflect the results of CPU operations.
4.2 Features
Features of the CPU include:
• 4.0-MHz bus frequency on standard part
• 8-bit accumulator
• 8-bit index register
• 11-bit program counter
• 6-bit stack pointer
• Condition code register with five status flags
• 62 instructions
• 8 addressing modes
• Power-saving stop, wait, halt, and data-retention modes
The programming model is shown in Figure 4-1
.
4.3 CPU Control Unit
The CPU control unit fetches and decodes instructions during program operation. The control unit selects the memory locations to read and write and coordinates the timing of all CPU operations.
4.4 Arithmetic/Logic Unit
The arithmetic/logic unit (ALU) performs the arithmetic, logic, and manipulation operations decoded from the instruction set by the CPU control unit. The ALU produces the results called for by the program and sets or clears status and control bits in the condition code register (CCR).
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 33
Central Processor Unit (CPU)
CPU CONTROL UNIT ARITHMETIC/LOGIC UNIT
7 6 5 4 3 2 1 0
ACCUMULATOR (A)
7 6 5 4 3 2 1 0
INDEX REGISTER (X)
15
0
14 13 12 11 10 9 8 7 6
0 0 0 0 0 0 0 1 1
5 4 3 2 1 0
STACK POINTER (SP)
15 14 13 12 11 10 9
0 0 0 0 0
8 7 6 5 4 3 2 1 0
PROGRAM COUNTER (PC)
7 6 5 4 3 2 1 0
1 1 1 H I N Z C CONDITION CODE REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 4-1. Programming Model
34
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
CPU Registers
4.5 CPU Registers
The M68HC05 CPU contains five registers that control and monitor MCU operation:
• Accumulator
• Index register
• Stack pointer
• Program counter
• Condition code register
CPU registers are not memory mapped.
4.5.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of ALU operations.
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 4-2. Accumulator (A)
4.5.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the index register to determine the conditional address of the operand. The index register also can serve as a temporary storage location or a counter.
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 4-3. Index Register (X)
4.5.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset or after the reset stack pointer instruction (RSP), the stack pointer is preset to $00FF. The address in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked.
3 2 1
Bit
0
Read:
Write:
Bit
15 14 13 12 11 10 9
0 0 0 0 0 0 0
Reset: 0 0 0 0
= Unimplemented
0 0 0
8
0
0
7
1
1
6
1
1
5
1
Figure 4-4. Stack Pointer (SP)
4
1 1 1 1 1
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 35
Central Processor Unit (CPU)
The 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations; an interrupt uses five locations.
4.5.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. The five most significant bits of the program counter are ignored and appear as 00000.
Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bit
0
Reset: 0 0 0 0 0 Loaded with vector from $07FE and $07FF
Figure 4-5. Program Counter (PC)
4.5.5 Condition Code Register
The condition code register is an 8-bit register whose three most significant bits are permanently fixed at
111. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed.
Read:
Write:
Reset:
Bit 7
1
6
1
5
1
4
H
3
I
2
N
1
Z
Bit 0
C
1 1 1
= Unimplemented
U 1
U = Unaffected
U
Figure 4-6. Condition Code Register (CCR)
U U
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations.
I — Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is logic 0, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is logic 1, the interrupt request is latched. Normally, the CPU processes the latched interrupt request as soon as the interrupt mask is cleared again.
A return from interrupt instruction (RTI) unstacks the CPU registers, restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is set and can be cleared only by a software instruction.
N — Negative Flag
The CPU sets the negative flag when an ALU operation produces a negative result.
36
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Freescale Semiconductor
Instruction Set
Z — Zero Flag
The CPU sets the zero flag when an ALU operation produces a result of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag.
4.6 Instruction Set
The MCU instruction set has 62 instructions and uses eight addressing modes.
4.6.1 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
4.6.1.1 Inherent
Inherent instructions are those that have no operand, such as return-from-interrupt (RTI) and stop
(STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
4.6.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long.
The opcode is the first byte, and the immediate data value is the second byte.
4.6.1.3 Direct
Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
4.6.1.4 Extended
Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 37
Central Processor Unit (CPU)
When using the Freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
4.6.1.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or input/output (I/O) location.
4.6.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510
($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
4.6.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory.
As with direct and extended addressing, the Freescale assembler determines the shortest form of indexed addressing.
4.6.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction.
When using the Freescale assembler, the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch.
38
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Instruction Set
4.6.2 Instruction Types
The MCU instructions fall into the following five categories:
• Register/memory instructions
• Read-modify-write instructions
• Jump/branch instructions
• Bit manipulation instructions
• Control instructions
4.6.2.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory.
Table 4-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Compare Accumulator
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
Subtract Memory Byte from Accumulator
ORA
SBC
STA
STX
SUB
EOR
LDA
LDX
MUL
Mnemonic
ADC
ADD
AND
BIT
CMP
CPX
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 39
Central Processor Unit (CPU)
4.6.2.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register.
NOTE
Do not use read-modify-write instructions on registers with write-only bits.
Table 4-2. Read-Modify-Write Instructions
Instruction
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Mnemonic
ASL
Bit Clear
Bit Set
ASR
BCLR
(1)
BSET
(1)
CLR Clear Register
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left (Same as ASL)
Logical Shift Right
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
COM
DEC
INC
LSL
LSR
NEG
ROL
ROR
Test for Negative or Zero TST
(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
4.6.2.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first
256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the
40
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Instruction Set branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register.
NOTE
Do not use BRCLR or BRSET instructions on registers with write-only bits.
Table 4-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
Branch if Bit Clear
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
BLS
BMC
BMI
BMS
BHS
BIH
BIL
BLO
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
BNE
BPL
BRA
BRCLR
BRN
BRSET
BSR
JMP
JSR
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 41
Central Processor Unit (CPU)
4.6.2.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations.
Table 4-4. Bit Manipulation Instructions
Instruction
Bit Clear
Branch if Bit Clear
Branch if Bit Set
Bit Set
Mnemonic
BCLR
BRCLR
BRSET
BSET
NOTE
Do not use bit manipulation instructions on registers with write-only bits.
4.6.2.5 Control Instructions
These instructions act on CPU registers and control CPU operation during program execution.
Table 4-5. Control Instructions
Clear Carry Bit
Clear Interrupt Mask
Instruction
No Operation
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
SEC
SEI
STOP
SWI
TAX
TXA
WAIT
Mnemonic
CLC
CLI
NOP
RSP
RTI
RTS
42
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Instruction Set
ADC # opr
ADC opr
ADC opr
ADC opr ,X
ADC opr ,X
ADC ,X
ADD # opr
ADD opr
ADD opr
ADD opr ,X
ADD opr ,X
ADD ,X
AND # opr
AND opr
AN D opr
AND opr ,X
AND opr ,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr ,X
ASL ,X
ASR opr
ASRA
ASRX
ASR opr ,X
ASR ,X
BCC rel
4.6.3 Instruction Set Summary
Source
Form
BCLR n opr
BCS rel
BEQ rel
BHCC rel
BHCS rel
BHI rel
BHS rel
BIH rel
BIL rel
Add with Carry
Add without Carry
Logical AND
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Branch if Carry Bit Clear
Clear Bit n
Table 4-6. Instruction Set Summary (Sheet 1 of 6)
Operation
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Description
Effect on CCR
H I N Z C
A
←
A
A
(A) + (M) + (C)
←
←
(A) + (M)
(A)
∧
(M)
—
—
— — —
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
C b7 b0
0 — —
DIR
INH
INH
IX1
IX b7 b0
C — —
DIR
INH
INH
IX1
IX
37
47
57
67
77 dd ff
PC
←
(PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3
Mn ← 0 — — — — —
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
19
1B
1D
1F
11
13
15
17 dd dd dd dd dd dd dd dd
PC
←
(PC) + 2 + rel ? C = 1
PC
←
(PC) + 2 + rel ? Z = 1
PC
←
(PC) + 2 + rel ? H = 0
PC
←
(PC) + 2 + rel ? H = 1
— — — — —
— — — — —
— — — — —
— — — — —
REL
REL
REL
REL
25
27
28
29 rr rr rr rr
3
3
3
3
PC
←
(PC) + 2 + rel ? C
∨
Z = 0 — — — — — REL 22 rr 3
PC
←
(PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3
PC
←
(PC) + 2 + rel ? IRQ = 1 — — — — — REL 2F rr 3
PC
←
(PC) + 2 + rel ? IRQ = 0 — — — — — REL 2E rr 3
5
5
5
5
5
5
5
5
3
6
5
3
5
A9
B9
C9
D9
E9
F9 ii dd hh ll ee ff ff
4
5
2
3
4
3
AB
BB
CB
DB
EB
FB ii dd hh ll ee ff ff
4
5
2
3
4
3
38
48
58
68
78
A4
B4
C4
D4
E4
F4 ii dd hh ll ee ff ff
4
5
2
3
4
3 dd ff
3
6
5
3
5
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 43
Central Processor Unit (CPU)
Source
Form
BIT # opr
BIT opr
BIT opr
BIT opr ,X
BIT opr ,X
BIT ,X
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Bit Test Accumulator with Memory Byte
BRCLR n opr rel Branch if Bit n Clear
BRN rel Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
BSR rel
CLC
CLI
Set Bit n
Table 4-6. Instruction Set Summary (Sheet 2 of 6)
Operation
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
Branch to Subroutine
Clear Carry Bit
Clear Interrupt Mask
Description
Effect on CCR
H I N Z C
PC
←
(A)
∧
(M)
(PC) + 2 + rel ? Mn = 0
— —
— — — —
—
IMM
DIR
EXT
IX2
IX1
IX
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
A5
B5
C5
D5
E5
F5
01
03
05
07
09
0B
0D
0F ii dd hh ll ee ff ff
PC
←
(PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3
PC
←
(PC) + 2 + rel ? C
∨
Z = 1 — — — — — REL 23 rr 3
PC ← (PC) + 2 + rel ? I = 0
PC
←
(PC) + 2 + rel ? N = 1
PC
←
(PC) + 2 + rel ? I = 1
— — — — —
— — — — —
— — — — —
REL
REL
REL
2C
2B
2D rr rr rr
3
3
3
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC
←
(PC) + 2 + rel ? 1 = 1
— — — — —
— — — — —
— — — — —
REL
REL
REL
26
2A
20 rr rr rr
3
3
3 dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr
4
5
2
3
4
3
5
5
5
5
5
5
5
5
PC ← (PC) + 2 + rel ? 1 = 0 — — — — — REL 21 rr 3
PC
←
(PC) + 2 + rel ? Mn = 1 — — — —
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
08
0A
0C
0E
00
02
04
06 dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr
5
5
5
5
5
5
5
5
Mn
←
1 — — — — —
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
18
1A
1C
1E
10
12
14
16 dd dd dd dd dd dd dd dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
C
←
0
I
←
0
— — — — —
— — — — 0
— 0 — — —
REL
INH
INH
AD
98
9A rr 6
2
2
44
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
EOR # opr
EOR opr
EOR opr
EOR opr ,X
EOR opr ,X
EOR ,X
INC opr
INCA
INCX
INC opr ,X
INC ,X
JMP opr
JMP opr
JMP opr ,X
JMP opr ,X
JMP ,X
JSR opr
JSR opr
JSR opr ,X
JSR opr ,X
JSR ,X
CLR opr
CLRA
CLRX
CLR opr ,X
CLR ,X
CMP # opr
CMP opr
CMP opr
CMP opr ,X
CMP opr ,X
CMP ,X
COM opr
COMA
COMX
COM opr ,X
COM ,X
CPX # opr
CPX opr
CPX opr
CPX opr ,X
CPX opr ,X
CPX ,X
DEC opr
DECA
DECX
DEC opr ,X
DEC ,X
Source
Form
Instruction Set
Clear Byte
Table 4-6. Instruction Set Summary (Sheet 3 of 6)
Operation Description
Effect on CCR
H I N Z C
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
Decrement Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Increment Byte
Unconditional Jump
Jump to Subroutine
M
A
X
M
M
←
←
←
←
←
PC
A
M
A
X
M
M
←
M
←
$00
(A) – (M)
(A) = $FF – (A)
(X) = $FF – (X)
(X) – (M)
M
A
X
M
M
A
←
$00
X
←
$00
M
←
$00
M
←
←
←
←
←
←
←
←
←
←
←
←
$00
(M) = $FF – (M)
(M) = $FF – (M)
(M) = $FF – (M)
(M) – 1
(A) – 1
(X) – 1
(M) – 1
(M) – 1
(A) ⊕ (M)
(M) + 1
(A) + 1
(X) + 1
(M) + 1
(M) + 1
Jump Address
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
— — 0
— —
— —
— —
1 —
1
— — —
— — —
— — —
— — — — —
— — — — —
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
A3
B3
C3
D3
E3
F3 ii dd hh ll ee ff ff dd
4
5
2
3
4
3 ff
3
6
5
3
5
3C
4C
5C
6C
7C
A8
B8
C8
D8
E8
F8 ii dd hh ll ee ff ff dd
4
5
2
3
4
3 ff
3
6
5
3
5
3F
4F
5F
6F
7F dd ff
33
43
53
63
73
A1
B1
C1
D1
E1
F1 ii dd hh ll ee ff ff dd
4
5
2
3
4
3 ff
3
6
5
3
5
3
6
5
3
5
BC
CC
DC
EC
FC dd hh ll ee ff ff
4
3
2
3
2
BD
CD
DD
ED
FD dd hh ll ee ff ff
7
6
5
6
5
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 45
LDA # opr
LDA opr
LDA opr
LDA opr ,X
LDA opr ,X
LDA ,X
LDX # opr
LDX opr
LDX opr
LDX opr ,X
LDX opr ,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr ,X
LSL ,X
LSR opr
LSRA
LSRX
LSR opr ,X
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG opr ,X
NEG ,X
NOP
ORA # opr
ORA opr
ORA opr
ORA opr ,X
ORA opr ,X
ORA ,X
ROL opr
ROLA
ROLX
ROL opr ,X
ROL ,X
ROR opr
RORA
RORX
ROR opr ,X
ROR ,X
RSP
Central Processor Unit (CPU)
Source
Form
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
Logical Shift Right
Unsigned Multiply
Negate Byte (Two’s Complement)
No Operation
Table 4-6. Instruction Set Summary (Sheet 4 of 6)
Operation
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
Rotate Byte Right through Carry Bit
Reset Stack Pointer
C
0
M
←
–(M) = $00 – (M)
A
←
–(A) = $00 – (A)
X
←
–(X) = $00 – (X)
M
←
–(M) = $00 – (M)
M
←
–(M) = $00 – (M)
C b7 b7
Description b7
X : A
←
(X)
×
(A)
A
←
(A)
∨
(M) b7
A
←
(M)
X
←
(M) b0 b0
SP
←
$00FF b0 b0
C
0
C
Effect on CCR
H I N Z C
— —
— —
— —
— — 0
0 — — — 0
— —
—
—
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
INH
DIR
INH
INH
IX1
IX
— — — — — INH 9D
— —
— —
—
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
39
49
59
69
79
AA
BA
CA
DA
EA
FA ii dd hh ll ee ff ff dd ff
2
3
6
5
3
5
4
5
2
3
4
3
— —
DIR
INH
INH
IX1
IX
36
46
56
66
76 dd ff
3
6
5
3
5
A6
B6
C6
D6
E6
F6 ii dd hh ll ee ff ff
4
5
2
3
4
3
38
48
58
68
78
AE
BE
CE
DE
EE
FE ii dd hh ll ee ff ff dd
4
5
2
3
4
3 ff
3
6
5
3
5
34
44
54
64
74 dd ff
42
3
6
5
3
5
1
1
30
40
50
60
70 dd ff
3
6
5
3
5
— — — — — INH 9C 2
46
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
RTS
SBC # opr
SBC opr
SBC opr
SBC opr ,X
SBC opr ,X
SBC ,X
SEC
SEI
STA opr
STA opr
STA opr ,X
STA opr ,X
STA ,X
STOP
STX opr
STX opr
STX opr ,X
STX opr ,X
STX ,X
SUB # opr
SUB opr
SUB opr
SUB opr ,X
SUB opr ,X
SUB ,X
RTI
Source
Form
SWI
TAX
TST opr
TSTA
TSTX
TST opr ,X
TST ,X
Instruction Set
Table 4-6. Instruction Set Summary (Sheet 5 of 6)
Operation
Return from Interrupt
Return from Subroutine
Subtract Memory Byte and Carry Bit from
Accumulator
Set Carry Bit
Set Interrupt Mask
Store Accumulator in Memory
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
Subtract Memory Byte from Accumulator
Software Interrupt
Transfer Accumulator to Index Register
Test Memory Byte for Negative or Zero
Effect on CCR
Description
H I N Z C
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP
←
(SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
INH
80
81
9
6
A
←
(A) – (M) – (C)
C
I
M
←
←
←
1
1
(A)
— —
IMM
DIR
EXT
IX2
IX1
IX
— — — — 1 INH
A2
B2
C2
D2
E2
F2 ii dd hh ll ee ff ff
99 2
— 1 — — — INH 9B
— — —
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7 dd hh ll ee ff ff
2
6
5
4
5
4
4
5
2
3
4
3
A
M
←
←
(X)
(A) – (M)
— 0 — — — INH 8E
— — —
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF dd hh ll ee ff ff
2
6
5
4
5
4
— —
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP
←
(SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP
←
(SP) – 1; I
←
1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
X
←
(A)
— 1 — — — INH
— — — — — INH
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0 ii dd hh ll ee ff ff
4
5
2
3
4
3
83
97 2
1
0 dd
(M) – $00 — — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D ff
3
5
4
3
4
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 47
Central Processor Unit (CPU)
Table 4-6. Instruction Set Summary (Sheet 6 of 6)
Source
TXA
Form
Operation
Transfer Index Register to Accumulator
WAIT Stop CPU Clock and Enable Interrupts
IX1
IX2
M
N n
A
C
Accumulator
Carry/borrow flag
CCR Condition code register dd Direct address of operand dd rr Direct address of operand and relative offset of branch instruction
DIR Direct addressing mode ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode ff
H
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
I hh ll High and low bytes of operand address in extended addressing
Interrupt mask ii Immediate operand byte
IMM Immediate addressing mode
INH
IX
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
Effect on CCR
Description
H I N Z C
A
←
(X) — — — — — INH 9F
— 0 — — — INH 8F
X
Z
#
∧
∨
⊕
( )
–( )
←
?
: opr
PC
Operand (one or two bytes)
Program counter
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode rel Relative program counter offset byte rr
SP
Relative program counter offset byte
Stack pointer
—
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
2
2
4.7 Opcode Map
See
48
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Table 4-7. Opcode Map
Bit Manipulation Branch
DIR DIR REL DIR
Read-Modify-Write
INH INH IX1 IX
Control
INH INH
LSB
MSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0 1 2 3 4 5 6 7 8
5
3
BRSET0
DIR 2
5
BSET0
DIR 2
3
BRCLR0
5
DIR
BRSET6
BRCLR6
BRSET7
BRCLR7
5
3
BRSET1
DIR
2
5
BCLR0
DIR 2
2
5
BSET1
DIR 2
3
BRCLR1
5
DIR
5
3
BRSET2
DIR
2
5
BCLR1
DIR 2
2
5
BSET2
DIR 2
3
3
3
3
3
BRCLR5
5
DIR
5
DIR
5
DIR
5
DIR
5
DIR
2
2
2
2
2
5
BCLR5
DIR
5
BSET6
DIR
5
BCLR6
DIR
5
BSET7
DIR
5
BCLR7
DIR
2
2
2
2
2
BRA
3
REL
3
BRN
REL
3
BHI
REL
3
BLS
REL
3
BCC
REL
2
2
2
3
BMI
REL
3
BMC
REL 2
BMS
3
REL
3
BIL
REL
2
3
BIH
REL 2
NEG
INC
CLR
5
DIR
5
COM
DIR
5
LSR
DIR
5
DIR
4
TST
DIR
5
DIR
1
1
1
1
1
1
1
NEGA
MUL
INH
3
COMA
INH
LSRA
INH
INCA
INH
TSTA
INH
CLRA
3
INH
11
3
3
3
3
INH
1
1
1
1
1
1
INCX
CLRX
3
NEGX
INH
3
COMX
INH
3
LSRX
INH
3
INH
3
TSTX
INH
3
INH
2
2
2
2
2
2
NEG
6
IX1 1
6
COM
IX1 1
6
LSR
IX1 1
NEG
COM
LSR
5
IX 1
5
IX
5
IX
3
BRCLR2
5
DIR
5
3
BRSET3
DIR
3
3
3
3
BRCLR3
BRSET4
BRCLR4
BRSET5
5
DIR
5
DIR
5
DIR
5
DIR
2
2
5
BSET3
DIR 2
2
2
2
2
5
BCLR2
DIR
5
BCLR3
DIR
5
BSET4
DIR
5
BCLR4
DIR
5
BSET5
DIR
2
BCS/BLO
3
REL
2
2
2
2
BNE
3
REL 2
ROR
5
DIR 1
3
RORA
INH 1
ROR
5
IX
BEQ
3
REL
3
BHCC
REL
2
2
5
ASR
DIR 1
ASL/LSL
5
DIR
ASRA
3
INH
3
ASLA/LSLA
1 INH
1
3
ASRX
INH 2
3
ASLX/LSLX
1 INH
ASR
6
IX1
6
2
ASL/LSL
IX1
1
ASR
5
IX
5
1
ASL/LSL
IX
3
BHCS
REL 2
3
BPL
REL 2
5
ROL
DIR 1
5
DEC
DIR 1
3
ROLA
INH 1
3
DECA
INH 1
3
RORX
INH 2
3
ROLX
INH 2
3
DECX
INH 2
6
ROR
IX1 1
6
ROL
IX1 1
6
DEC
IX1 1
ROL
DEC
5
IX
5
IX
INC
6
IX1
5
TST
IX1
CLR
6
IX1
1
1
1
INC
TST
CLR
5
IX
4
IX
5
IX
1
1
1
1
RTI
RTS
SWI
9
INH
6
INH
10
INH
1
1
1
1
1
1
1
2
STOP
INH
2
WAIT
INH 1
9
2
2
2
2
2
2
2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
2
TXA
INH
2
IMM
A
DIR
B
Register/Memory
EXT
C
IX2
D
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
6
BSR
REL 2
2
LDX
IMM 2
2
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
IX1 IX
E F
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
3
SUB
IX
3
CMP
IX
3
SBC
IX
3
CPX
IX
3
AND
IX
3
BIT
IX
3
LDA
IX
4
STA
IX
3
EOR
IX
3
ADC
IX
3
ORA
IX
3
ADD
IX
2
JMP
IX
5
JSR
IX
3
LDX
IX
4
STX
IX
MSB
LSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
LSB of Opcode in Hexadecimal
LSB
MSB
0
0
5
3
BRSET0
DIR
MSB of Opcode in Hexadecimal
Number of Cycles
Opcode Mnemonic
Number of Bytes/Addressing Mode
Central Processor Unit (CPU)
50
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 5
External Interrupt Module (IRQ)
5.1 Introduction
The external interrupt (IRQ) module provides asynchronous external interrupts to the CPU. The following sources can generate external interrupts:
• IRQ/V
PP
pin
• PA0–PA3 pins
5.2 Features
The external interrupt module (IRQ) includes these features:
• Dedicated external interrupt pin (IRQ/V
PP
)
• Selectable interrupt on four input/output (I/O) pins (PA0–PA3)
• Programmable edge-only or edge- and level-interrupt sensitivity
5.3 Operation
The interrupt request/programming voltage pin (IRQ/V
PP
) and port A pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the mask option register (MOR) enables PA0–PA3 as IRQ interrupt
sources, which are combined into a single OR’ing function to be latched by the IRQ latch. Figure 5-1
shows the structure of the IRQ module.
After completing its current instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register and the IRQE bit in the IRQ status and control register. If the
I bit is clear and the IRQE bit is set, the CPU then begins the interrupt sequence. This interrupt is serviced by the interrupt service routine located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return
from interrupt, the CPU can recognize the new interrupt request. Figure 5-3
shows the sequence of events caused by an interrupt.
5.3.1 IRQ/V
PP
Pin
An interrupt signal on the IRQ/V
PP
pin latches an external interrupt request. The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function.
If edge- and level-sensitive triggering is selected, a falling edge or a low level on the IRQ/V
PP
pin latches an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR external interrupt sources. An external interrupt request is latched as long as any source is holding the
IRQ/V
PP
pin low.
If level-sensitive triggering is selected, the IRQ/V
PP
input requires an external resistor to V
DD
for wired-OR operation. If the IRQ/V
PP
pin is not used, it must be tied to the V
DD
supply.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 51
External Interrupt Module (IRQ)
IRQ
TO BIH & BIL
INSTRUCTION
PROCESSING
PA3
PA2
PA1
PA0
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
V
DD
D
IRQ
LATCH
Q
CK
CLR
IRQF
IRQE
EXTERNAL
INTERRUPT
REQUEST
PIRQ
(MOR)
RESET
IRQ VECTOR FETCH
IRQR
Figure 5-1. IRQ Module Block Diagram
Addr.
$000A
Register Name
Read:
IRQ Status and Control
Register (ISCR)
Write:
Reset:
Bit 7
IRQE
1
6
0
0
= Unimplemented
0
5
0
R
0
4
0
R
3
IRQF
0
= Reserved
Figure 5-2. IRQ Module I/O Register Summary
2
0
0
1
0
IRQR
0
Bit 0
0
0
If edge-sensitive-only triggering is selected, a falling edge on the IRQ/V
PP
pin latches an external interrupt request. A subsequent external interrupt request can be latched only after the voltage level on the
IRQ/V
PP
pin returns to logic 1 and then falls again to logic 0.
The IRQ/V
PP
pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin can affect the mode of operation and should not exceed V
DD
.
5.3.2 Optional External Interrupts
The inputs for the lower four bits of port A (PA0–PA3) can be connected to the IRQ pin input of the CPU if enabled by the PIRQ bit in the mask option register. This capability allows keyboard scan applications where the transitions or levels on the I/O pins will behave the same as the IRQ/V
PP
pin except for the inverted phase (logic 1, rising edge). The active state of the IRQ/V
PP
pin is a logic 0 (falling edge).
The PA0–PA3 pins are selected as a group to function as IRQ interrupts and are enabled by the IRQE bit in the IRQ status and control register. The PA0–PA3 pins can be positive-edge triggered only or positive-edge and high-level triggered.
52
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
FROM RESET
YES
I BIT SET?
NO
EXTERNAL
INTERRUPT?
NO
YES
CLEAR IRQ LATCH.
TIMER
INTERRUPT?
NO
YES
STACK PCL, PCH, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CCR, A, X, PCH, PCL.
NO
EXECUTE INSTRUCTION.
Figure 5-3. Interrupt Flowchart
Operation
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 53
External Interrupt Module (IRQ)
If edge- and level-sensitive triggering is selected, a rising edge or a high level on a PA0–PA3 pin latches an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR external interrupt sources. As long as any source is holding a PA0–PA3 pin high, an external interrupt request is latched, and the CPU continues to execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3 pin latches an external interrupt request. A subsequent external interrupt request can be latched only after the voltage level of the previous interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE
The BIH and BIL instructions apply only to the level on the IRQ/V
PP
pin itself and not to the output of the logic OR function with the PA0 – PA3 pins. The state of the individual port A pins can be checked by reading the appropriate port A pins as inputs.
Enabled PA0 – PA3 pins cause an IRQ interrupt regardless of whether these pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external interrupts
(PA0 – PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables all maskable interrupt requests, including external interrupt requests.
5.4 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. All unused bits in the ISCR read as logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset.
Address: $000A
Read:
Write:
Reset:
Bit 7
IRQE
1
6
0
0
= Unimplemented
0
5
0
R
0
4
0
R
3
IRQF
0
= Reserved
2
0
0
1
0
IRQR
0
Bit 0
0
0
Figure 5-4. IRQ Status and Control Register (ISCR)
IRQR — Interrupt Request Reset Bit
This write-only bit clears the external interrupt request flag.
1 = Clears external interrupt and IRQF bit
0 = No effect on external interrupt and IRQF bit
IRQF — External Interrupt Request Flag
The external interrupt request flag is a clearable, read-only bit that is set when an external interrupt request is pending. Reset clears the IRQF bit.
1 = External interrupt request pending
0 = No external interrupt request pending
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE bit.
1 = External interrupt requests enabled
0 = External interrupt requests disabled
54
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Timing
The STOP and WAIT instructions set the IRQE bit so that an external interrupt can bring the MCU out of these low-power modes. In addition, reset sets the I bit which masks all interrupt sources.
5.5 Timing
t
ILIL
IRQ/V
PP
PIN t
ILIH t
ILIH
IRQ
1
.
.
.
IRQ n
IRQ (INTERNAL)
Figure 5-5. External Interrupt Timing
Table 5-1. External Interrupt Timing (V
DD
= 5.0 Vdc)
(1)
Characteristic Symbol Min Max
IRQ Interrupt Pulse Width Low (Edge-Triggered) t
ILIH
1.5
—
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered) t
ILIH
1.5
Note
(3)
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered) t
ILIL
1.5
—
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered) t
ILIH
1.5
1. V
DD
= 5.0 Vdc ± 10%, V
SS
2. t cyc
= 1/f
OP
; f
OP
= f
OSC
/2.
= 0 Vdc, T
A
= –40 ° C to + 85 ° C, unless otherwise noted.
3. The minimum t
ILIL
should not be less than the number of interrupt service routine cycles plus 19 t cyc
.
Note
(3)
Table 5-2. External Interrupt Timing (V
DD
= 3.3 Vdc)
(1)
Characteristic Symbol Min Max
IRQ Interrupt Pulse Width Low (Edge-Triggered) t
ILIH
1.5
—
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered) t
ILIH
1.5
Note
(3)
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered)
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered) t t
ILIL
ILIH
1.5
1.5
1. V
DD
2. t cyc
= 3.3 Vdc ± 10%, V
SS
= 1/f
OP
; f
OP
= f
OSC
/2.
= 0 Vdc, T
A
= –40 ° C to + 85 ° C, unless otherwise noted.
3. The minimum t
ILIL
should not be less than the number of interrupt service routine cycles plus 19 t cyc
.
—
Note
(3)
Unit t cyc
(2) t cyc t cyc t cyc
Unit t cyc
(2) t cyc t cyc t cyc
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 55
External Interrupt Module (IRQ)
56
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 6
Low-Power Modes
6.1 Introduction
The MCU can enter the following low-power standby modes:
• Stop mode — The STOP instruction puts the MCU in its lowest power-consumption mode.
• Wait mode — The WAIT instruction puts the MCU in an intermediate power-consumption mode.
• Halt mode — Halt mode is identical to wait mode, except that an oscillator stabilization delay of 1 to 4064 internal clock cycles occurs when the MCU exits halt mode. The stop-to-wait conversion bit, SWAIT, in the mask option register, enables halt mode.
Enabling halt mode prevents the computer operating properly (COP) watchdog from being inadvertently turned off by a STOP instruction.
• Data-retention mode — In data-retention mode, the MCU retains RAM contents and CPU register contents at V
DD
voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during which it retains data, but the CPU cannot execute instructions.
6.2 Exiting Stop and Wait Modes
The following events bring the MCU out of stop mode and load the program counter with the reset vector or with an interrupt vector:
Exiting Stop Mode
• External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF.
• External interrupt — A high-to-low transition on the IRQ/V
PP
pin or a low-to-high transition on an enabled port A external interrupt pin starts the CPU clock and loads the program counter with the contents of locations $07FA and $07FB.
Exiting Wait Mode
• External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF.
• External interrupt — A high-to-low transition on the IRQ/V
PP
pin or a low-to-high transition on an enabled port A external interrupt pin starts the CPU clock and loads the program counter with the contents of locations $07FA and $07FB.
• COP watchdog reset — A timeout of the COP watchdog resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF. Software can enable timer interrupts so that the MCU periodically can exit wait mode to reset the COP watchdog.
• Timer interrupt — Real-time interrupt requests and timer overflow interrupt requests start the MCU clock and load the program counter with the contents of locations $07F8 and $07F9.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 57
Low-Power Modes
6.3 Effects of Stop and Wait Modes
The STOP and WAIT instructions have the following effects on MCU modules.
6.3.1 Clock Generation
Effects of STOP and WAIT on clock generation are discussed here.
6.3.1.1 STOP
The STOP instruction disables the internal oscillator, stopping the CPU clock and all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral clocks begin running after the oscillator stabilization delay.
NOTE
The oscillator stabilization delay holds the MCU in reset for the first 4064 internal clock cycles.
6.3.1.2 WAIT
The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral clocks immediately begin running.
6.3.2 CPU
Effects of STOP and WAIT on the CPU are discussed here.
6.3.2.1 STOP
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
6.3.2.2 WAIT
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts
• Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
6.3.3 COP Watchdog
Effects of STOP and WAIT on the COP watchdog are discussed here.
58
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Effects of Stop and Wait Modes
6.3.3.1 STOP
The STOP instruction:
• Clears the COP watchdog counter
• Disables the COP watchdog clock
NOTE
To prevent the STOP instruction from disabling the COP watchdog, program the stop-to-wait conversion bit (SWAIT) in the mask option register to logic 1.
After exit from stop mode by external interrupt, the COP watchdog counter immediately begins counting from $0000 and continues counting throughout the oscillator stabilization delay.
NOTE
Immediately after exiting stop mode by external interrupt, service the COP to ensure a full COP timeout period.
After exit from stop mode by reset:
• The COP watchdog counter immediately begins counting from $0000.
• The COP watchdog counter is cleared at the end of the oscillator stabilization delay and begins counting from $0000 again.
6.3.3.2 WAIT
The WAIT instruction has no effect on the COP watchdog.
NOTE
To prevent a COP timeout during wait mode, exit wait mode periodically to service the COP.
6.3.4 Timer
Effects of STOP and WAIT on the timer are discussed here.
6.3.4.1 STOP
The STOP instruction:
• Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and control register, disabling timer interrupt requests and removing any pending timer interrupt requests
• Disables the clock to the timer
After exiting stop mode by external interrupt, the timer immediately resumes counting from the last value before the STOP instruction and continues counting throughout the oscillator stabilization delay.
After exiting stop mode by reset and after the oscillator stabilization delay, the timer resumes operation from its reset state.
6.3.4.2 WAIT
The WAIT instruction has no effect on the timer.
6.3.5 EPROM/OTPROM
Effects of STOP and WAIT on the EPROM/OTPROM are discussed here.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 59
Low-Power Modes
6.3.5.1 STOP
The STOP instruction during EPROM programming clears the EPGM bit in the EPROM programming register, removing the programming voltage from the EPROM.
6.3.5.2 WAIT
The WAIT instruction has no effect on EPROM/OTPROM operation.
6.4 Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU register contents at V
DD
voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
1.
Drive the RESET pin to logic 0.
2.
Lower the V
DD voltage. The RESET pin must remain low continuously during data-retention mode.
To take the MCU out of data-retention mode:
1.
Return V
DD
to normal operating voltage.
2.
Return the RESET pin to logic 1.
6.5 Timing
OSC
(NOTE 1) t
RL
RESET
IRQ/V
PP
(NOTE 2)
IRQ/V
PP
(NOTE 3) t
ILIH
OSCILLATOR STABILIZATION DELAY
(5)
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
$07FE
(NOTE 4)
$07FE $07FE $07FE $07FE $07FF
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
5. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
Figure 6-1. Stop Mode Recovery Timing
RESET OR INTERRUPT
VECTOR FETCH
60
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
STOP
SWAIT
BIT SET?
YES
NO
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR.
TURN OFF INTERNAL OSCILLATOR.
HALT WAIT
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
TIMER CLOCK ACTIVE.
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
TIMER CLOCK ACTIVE.
EXTERNAL
RESET?
NO
EXTERNAL
INTERRUPT?
NO
YES
YES
TURN ON INTERNAL OSCILLATOR.
RESET STABILIZATION TIMER.
END OF
STABILIZATION
DELAY?
NO
YES
TURN ON CPU CLOCK.
YES EXTERNAL
RESET?
NO
YES EXTERNAL
INTERRUPT?
NO
YES TIMER
INTERRUPT?
NO
YES
COP
RESET?
NO
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT.
a. SAVE CPU REGISTERS ON STACK.
b. SET I BIT IN CCR.
c. LOAD PC WITH INTERRUPT VECTOR.
Figure 6-2. STOP/HALT/WAIT Flowchart
YES EXTERNAL
RESET?
NO
YES EXTERNAL
INTERRUPT?
NO
YES TIMER
INTERRUPT?
NO
YES
COP
RESET?
NO
Timing
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 61
Low-Power Modes
62
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 7
Parallel I/O Ports (PORTS)
7.1 Introduction
Ten bidirectional pins form one 8-bit input/output (I/O) port and one 2-bit I/O port. All the bidirectional port pins are programmable as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either V
DD
or
V
SS.
Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
Addr.
$0000
Register Name:
Port A Data Register (POR-
TA)
Read:
Write:
Reset:
Bit 7
PA7
6
PA6
5
PA5
4
PA4
3
PA3
Unaffected by reset
2
PA2
1
PA1
Bit 0
PA0
$0001
$0004
$0005
$0010
Port B Data Register
(PORTB)
Read:
Write:
Reset:
Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Read:
Write:
Reset:
Read:
Write:
Reset:
0
DDRA7
0
0
0
Port A Pulldown Register
(PDRA)
Port B Pulldown Register
(PDRB)
Read:
Write:
Reset:
Read:
Write:
Reset:
PDIA7
0
0
DDRA6
0
0
0
PDIA6
0
DDRA5
0
0
PDIA5
0
See Note PB3
Unaffected by reset
DDRA4
See Note
0
0
PDIA4
0
DDRA3
0
DDRB3
0
PDIA3
0
PB2
DDRA2
0
DDRB2
0
PDIA2
0
See Note
DDRA1
0
0
See Note
PDIA1
0
DDRA0
0
0
PDIA0
0
$0011
0
See Note
0
PDIB3
0
PDIB2
0 0
See Note
0
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-1. Parallel I/O Port Register Summary
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 63
Parallel I/O Ports (PORTS)
7.2 Port A
Port A is an 8-bit bidirectional port.
7.2.1 Port A Data Register
The port A data register contains a latch for each port A pin.
Address: $0000
Bit 7
Read:
Write:
Reset:
PA7
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
Unaffected by reset
Figure 7-2. Port A Data Register (PORTA)
1
PA1
Bit 0
PA0
PA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data.
7.2.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input or an output.
Address: $0004
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset:
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
0
DDRA0
0
Figure 7-3. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1.
shows the I/O logic of port A.
64
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Port A
READ DDRA
WRITE DDRA
WRITE PORTA
DDRAx
PAx
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
PAx
(PA0–PA3 TO
IRQ MODULE)
READ PORTA
WRITE PDRA
PDRAx
100-
µ
A
PULLDOWN
RESET
SWPDI
Figure 7-4. Port A I/O Circuitry
Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data latch. When bit DDRAx is a logic
0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
Table 7-1. Port A Pin Operation
Data Direction Bit I/O Pin Mode
0
1
Input, high-impedance
Output
1. Writing affects the data register but does not affect input.
Accesses to Data Bit
Read Write
Pin
Latch
Latch
(1)
Latch
7.2.3 Pulldown Register A
Pulldown register A inhibits the pulldown devices on port A pins programmed as inputs.
NOTE
If the SWPDI bit in the mask option register is programmed to logic 1, reset initializes all port A pins as inputs with disabled pulldown devices.
Address: $0010
6 5 4 3 2 1 Bit 0 Bit 7
Read:
Write: PDIA7
Reset: 0
PDIA6
0
PDIA5
= Unimplemented
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
Figure 7-5. Pulldown Register A (PDRA)
PDIA[7:0] — Pulldown Inhibit A Bits
PDIA[7:0] disable the port A pulldown devices. Reset clears PDIA[7:0].
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 65
Parallel I/O Ports (PORTS)
7.2.4 Port LED Drive Capability
All outputs can drive light-emitting diodes (LEDs). These pins can sink approximately 10 mA of current to
V
SS
.
7.2.5 Port A I/O Pin Interrupts
If the PIRQ bit in the mask option register is programmed to logic 1, PA0–PA3 pins function as external interrupt pins. (See
Chapter 5 External Interrupt Module (IRQ) .)
7.3 Port B
Port B is a 2-bit bidirectional port.
7.3.1 Port B Data Register
The port B data register contains a latch for each port B pin.
Address: $0001
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
0 0
See Note PB3 PB2 See Note
Reset: Unaffected by reset
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-6. Port B Data Register (PORTB)
PB[3:2] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data.
NOTE
PB4–PB5 and PB0–PB1 should be configured as inputs at all times. These bits are available for read/write but are not available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly terminating them.
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MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Port B
7.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an output.
Address: $0005
Bit 7
Read:
Write:
0
6
0
5
See Notes
4 3
DDRB3
2
DDRB2
1
See Note
Bit 0
Reset: 0 0
= Unimplemented
0 0 0 0 0 0
Note:
DDRB5, DDRB4, DDRB1, and DDRB0 should be configured as inputs at all times. These bits are available for read/write but are not available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-7. Data Direction Register B (DDRB)
DDRB[3:2] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[3:2], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1.
shows the I/O logic of port B.
READ DDRB
WRITE DDRB
WRITE PORTB
DDRBx
PBx PBx
READ PORTB
WRITE PDRB
PDRBx
RESET
SWPDI
Figure 7-8. Port B I/O Circuitry
100-
µ
A
PULLDOWN
Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 67
Parallel I/O Ports (PORTS)
Data Direction Bit
0
1
Table 7-2. Port B Pin Operation
I/O Pin Mode
Input, high-impedance
Output
1. Writing affects the data register, but does not affect input.
Accesses to Data Bit
Read Write
Pin
Latch
Latch
(1)
Latch
7.3.3 Pulldown Register B
Pulldown register B inhibits the pulldown devices on port B pins programmed as inputs.
NOTE
If the SWPDI bit in the mask option register is programmed to logic 1, reset initializes all port B pins as inputs with disabled pulldown devices.
Address: $0011
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 0
See Note
0
PDIB3
0
PDIB2
0 0
See Note
0
= Unimplemented
Note:
These pulldown devices are permanently enabled when PB5, PB4, PB1 and PB0 are configured as inputs.
Figure 7-9. Pulldown Register B (PDRB)
PDIB[3:2] — Pulldown Inhibit B Bits
PDIB[3:2] disable the port B pulldown devices. Reset clears PDIB[3:2].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
68
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
I/O Port Electrical Characteristics
7.4 I/O Port Electrical Characteristics
Table 7-3. I/O Port DC Electrical Characteristics (V
DD
= 5.0 V)
(1)
Characteristic
Current Drain Per Pin
Output High Voltage
(I
Load
= –2.5 mA) PA4–PA7
(I
Load
= –5.5 mA) PB2–PB3, PA0–PA3
Output Low Voltage
(I
Load
= 10.0 mA) PA0–PA7, PB2–PB3
Input High Voltage
PA0–PA7, PB2–PB3
Symbol
V
V
V
I
OH
OL
IH
V
V
Min
DD
DD
—
–0.8
–0.8
—
0.7 x V
DD
Input Low Voltage
PA0–PA7, PB2–PB3
V
IL
V
SS
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB2–PB3 (Without Individual
Pulldown Activated)
I
IL
—
Input Pulldown Current
PA0–PA7, PB2–PB3 (With Individual
Pulldown Activated)
I
IL
35
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= –40 ° C to +85 ° C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 ° C.
Typ
(2)
—
—
—
—
—
—
0.2
80
Max
25
—
—
0.8
V
DD
0.2 x V
DD
± 1
200
Unit mA
V
V
V
V
µ A
µ A
Table 7-4. I/O Port DC Electrical Characteristics (V
DD
= 3.3 V)
(1)
Characteristic Symbol Min
Current Drain Per Pin
Output High Voltage
(I
Load
= –0.8 mA) PA4–PA7
(I
Load
= –1.5 mA) PA0–PA3, PB2–PB3
Output Low Voltage
(I
Load
= 5.0 mA) PA4–PA7
(I
Load
= 3.5 mA) PA0–PA3, PB2–PB3
Input High Voltage
PA0–PA7, PB2–PB3
Input Low Voltage
PA0–PA7, PB2–PB3
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB2–PB3 (Without Individual Pulldown
Activated)
V
V
V
V
I
I
OH
OL
IH
IL
IL
V
V
DD
DD
–0.3
–0.3
—
—
0.7 x V
V
—
SS
—
DD
Input Pulldown Current
PA0–PA7, PB2–PB3 (With Individual Pulldown Activated)
I
IL
12
1. V
DD
= 3.3 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= –40 ° C to +85 ° C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 ° C.
Typ
(2)
—
—
—
—
—
—
—
0.1
30
Max
25
—
—
0.5
0.5
V
DD
0.2 x V
DD
± 1
100
Unit mA
V
V
µ A
µ A
V
V
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 69
Parallel I/O Ports (PORTS)
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MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 8
Resets and Interrupts
8.1 Introduction
Reset initializes the MCU by returning the program counter to a known address and by forcing control and status bits to known states.
Interrupts temporarily change the sequence of program execution to respond to events that occur during processing.
8.2 Resets
A reset immediately stops the operation of the instruction being executed, initializes certain control and status bits, and loads the program counter with a user-defined reset vector address. The following sources can generate a reset:
• Power-on reset (POR) circuit
• RESET pin
• Computer operating properly (COP) watchdog
• Illegal address
V
DD
RESET PIN
ILLEGAL ADDRESS
COP WATCHDOG
POWER-ON RESET
INTERNAL CLOCK
S
D
CK
RESET
LATCH
Q
RST
Figure 8-1. Reset Sources
TO CPU AND
PERIPHERAL
MODULES
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 71
Resets and Interrupts
8.2.1 Power-On Reset
A positive transition on the V
DD
pin generates a power-on reset.
NOTE
The power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage.
A 4064-t cyc
(internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. If any reset source is active at the end of this delay, the MCU remains in the reset condition until all reset sources are inactive.
V
DD
(NOTE 1)
OSC1 PIN
OSCILLATOR STABILIZATION DELAY
(2)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS $07FE $07FE $07FE $07FE $07FE $07FE $07FF
INTERNAL
DATA BUS
NEW PCH NEW PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
3. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 8-2. Power-On Reset Timing
8.2.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 t cyc
generates an external reset. A Schmitt trigger senses the logic level at the RESET pin.
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
$07FE $07FE $07FE $07FE $07FF NEW PC NEW PC
INTERNAL
DATA BUS
NEW
PCH
NEW
PCL
DUMMY
OP
CODE t
RL
RESET
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 8-3. External Reset Timing
RESET Pulse Width
Table 8-1. External Reset Timing
Characteristic Symbol t
RL
Min
1.5
Max
—
Unit t cyc
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MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Interrupts
8.2.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register at location $07F0.
8.2.4 Illegal Address Reset
An opcode fetch from an address not in RAM or EPROM generates a reset.
8.3 Interrupts
The following sources can generate interrupts:
• SWI instruction
• External interrupt pins
– IRQ/V
PP
pin
– PA0–PA3 pins
• Timer
– Real-time interrupt flag (RTIF)
– Timer overflow flag (TOF)
An interrupt temporarily stops the program sequence to process a particular event. An interrupt does not stop the operation of the instruction being executed, but takes effect when the current instruction completes its execution. Interrupt processing automatically saves the CPU registers on the stack and loads the program counter with a user-defined interrupt vector address.
8.3.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable interrupt.
8.3.2 External Interrupt
An interrupt signal on the IRQ/V
PP
pin latches an external interrupt request. When the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register. If the I bit is clear, the CPU then begins the interrupt sequence.
The CPU clears the IRQ latch during interrupt processing, so that another interrupt signal on the IRQ/V
PP pin can latch another interrupt request during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request.
IRQ/V
PP
pin interrupt logic.
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register enables pins PA0–PA3 to function as external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register controls interrupt triggering sensitivity of external interrupt pins. The IRQ/V
PP
pin can be negative-edge triggered only or negative-edge and low-level triggered. Port A external interrupt pins can be positive-edge triggered only or both positive-edge and high-level triggered. The level-sensitive triggering option allows multiple external interrupt sources to be wire-ORed to an external interrupt pin. An external interrupt request, shown in
Figure 8-5 , is latched as long as any source is holding an external interrupt pin low.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 73
Resets and Interrupts
IRQ
TO BIH & BIL
INSTRUCTION
PROCESSING
PA3
PA2
PA1
PA0
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
V
DD
D IRQ
LATCH
Q
CK
CLR
IRQF
IRQE
EXTERNAL
INTERRUPT
REQUEST
PIRQ
(MOR)
EXT. INT. PIN
RESET
IRQ VECTOR FETCH
IRQR
Figure 8-4. External Interrupt Logic t
ILIL t
ILIH
EXT. INT. PIN
1
.
.
.
EXT. INT. PIN n
IRQ
(INTERNAL) t
ILIH
Figure 8-5. External Interrupt Timing
Table 8-2. External Interrupt Timing (V
DD
= 5.0 Vdc)
(1)
Characteristic
Interrupt Pulse Width Low (Edge-Triggered)
Symbol t
ILIH
Min
125
Interrupt Pulse Period t
ILIL Note
(2)
1. V
DD
= 5.0 Vdc ± 10%, V
SS
2. The minimum t
ILIL
= 0 Vdc, T
A
= –40 ° C to +85 ° C, unless otherwise noted.
should not be less than the number of interrupt service routine cycles plus 19 t cyc
.
Max
—
—
Unit ns t cyc
Table 8-3. External Interrupt Timing (V
DD
= 3.3 Vdc)
(1)
Characteristic
Interrupt Pulse Width Low (Edge-Triggered)
Symbol t
ILIH
Min
250
Interrupt Pulse Period t
ILIL Note
(2)
1. V
DD
= 3.3 Vdc ± 10%, V
SS
2. The minimum t
ILIL
= 0 Vdc, T
A
= –40 ° C to +85 ° C unless otherwise noted.
should not be less than the number of interrupt service routine cycles plus 19 t cyc
.
Max
—
—
Unit ns t cyc
74
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Interrupts
8.3.3 Timer Interrupts
The timer can generate the following interrupt requests:
• Real time
• Timer overflow
Setting the I bit in the condition code register disables timer interrupts.
8.3.3.1 Real-Time Interrupt
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer status and control register.
8.3.3.2 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF, becomes set while the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE are in the timer status and control register.
8.3.4 Interrupt Processing
The CPU takes the following actions to begin servicing an interrupt:
•
Stores the CPU registers on the stack in the order shown in Figure 8-6
• Sets the I bit in the condition code register to prevent further interrupts
• Loads the program counter with the contents of the appropriate interrupt vector locations:
– $07FC and $07FD (software interrupt vector)
– $07FA and $07FB (external interrupt vector)
– $07F8 and $07F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover the CPU registers from the stack as shown in
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 75
Resets and Interrupts
3
2
1
5
4
UNSTACKING
ORDER
3
4
5
1
2
•
•
•
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
•
•
•
STACKING
ORDER
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 8-6. Interrupt Stacking Order
Table 8-4. Reset/Interrupt Vector Addresses
Function Source
Local
Mask
Global
Mask
Reset
Power-On
RESET Pin
COP Watchdog
(1)
Illegal Address
None None
Software Interrupt
(SWI)
External Interrupt
User Code None
Timer Interrupts
IRQ/V
PP
Pin
RTIF Bit
TOF Bit
IRQE
RTIE Bit
TOIE Bit
1. The COP watchdog is programmable in the mask option register.
None
I Bit
I Bit
Priority
(1 = Highest)
1
Same Priority as Instruction
2
3
Vector
Address
$07FE
$07FC
$07FA
$07F8
–
$07FF
–
$07FD
–
$07FB
–
$07F9
76
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
FROM RESET
YES
I BIT SET?
NO
EXTERNAL
INTERRUPT?
NO
YES
CLEAR IRQ LATCH.
TIMER
INTERRUPT?
NO
YES
STACK PC, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
NO
YES
RTI
INSTRUCTION?
YES
UNSTACK CCR, A, X, PC.
NO
EXECUTE INSTRUCTION.
Figure 8-7. Interrupt Flowchart
Interrupts
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 77
Resets and Interrupts
78
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 9
Multifunction Timer Module
9.1 Introduction
The multifunction timer provides a timing reference with programmable real-time interrupt capability.
shows the timer organization.
9.2 Features
Features of the multifunction timer include:
• Timer overflow
• Four selectable interrupt rates
• Computer operating properly (COP) watchdog timer
9.3 Operation
A 15-stage ripple counter, preceded by a prescaler that divides the internal clock signal by four, provides the timing reference for the timer functions. The value of the first eight timer stages can be read at any time by accessing the timer counter register at address $0009. A timer overflow function at the eighth stage allows a timer interrupt every 1024 internal clock cycles.
The next four stages lead to the real-time interrupt (RTI) circuit. The RT1 and RT0 bits in the timer status and control register at address $0008 allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock cycles. The last four stages drive the selectable COP system. For information on the COP, refer to
Chapter 3 Computer Operating Properly Module (COP)
.
Addr.
Register Name Bit 7
$0008
Timer Status and Control Register
(TSCR)
Read: TOF
Write:
Reset: 0
$0009
Timer Counter Register
(TCR)
Read: TMR7
Write:
Reset: 0
6
RTIF
0
TMR6
5
TOIE
0
0
= Unimplemented
0
4
RTIE
0
TMR5 TMR4
0
Figure 9-1. I/O Register Summary
3
0
TOFR
0
TMR3
0
2
0
RTIFR
0
TMR2
1
RT1
1
TMR1
0 0
Bit 0
RT0
1
TMR0
0
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 79
Multifunction Timer Module
OVERFLOW
RESET
TIMER COUNTER REGISTER
BITS [0:7] OF 15-STAGE
RIPPLE COUNTER
RESET
÷
4
INTERNAL CLOCK
(XTAL ÷ 2)
INTERRUPT
REQUEST
TIMER STATUS/CONTROL REGISTER
RTI RATE SELECT RESET
RESET
÷
2
÷
2
÷
2
÷
2
÷
2
÷
2
÷
2
BITS [8:14] OF 15-STAGE RIPPLE COUNTER
÷ 8 S Q COP RESET
R
Figure 9-2. Multifunction Timer Block Diagram
9.4 Interrupts
The following timer sources can generate interrupts:
• Timer overflow flag (TOF) — The TOF bit is set when the first eight stages of the counter roll over from $FF to $00. The timer overflow interrupt enable bit, TOIE, enables TOF interrupt requests.
• Real-time interrupt flag (RTIF) — The RTIF bit is set when the selected RTI output becomes active.
The real-time interrupt enable bit, RTIE, enables RTIF interrupt requests.
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MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
I/O Registers
9.5 I/O Registers
The following registers control and monitor the timer operation:
• Timer status and control register (TSCR)
• Timer counter register (TCR)
9.5.1 Timer Status and Control Register
The read/write timer status and control register performs the following functions:
• Flags timer interrupts
• Enables timer interrupts
• Resets timer interrupt flags
• Selects real-time interrupt rates
Address: $0008
Bit 7
Read:
Write:
TOF
Reset: 0
6
RTIF
5
TOIE
4
RTIE
3
0
TOFR
0
2
0
RTIFR
0
1
RT1
0
= Unimplemented
0 0 1
Figure 9-3. Timer Status and Control Register (TSCR)
Bit 0
RT0
1
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the counter roll over from $FF to $00.
TOF generates a timer overflow interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected RTI output becomes active. RTIF generates a real-time interrupt request if RTIE is also set. Clear RTIF by writing a logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables timer overflow interrupts. Reset clears TOIE.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
TOFR — Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always reads as logic 0. Reset clears
TOFR.
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR always reads as logic 0. Reset clears
RTIFR.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 81
Multifunction Timer Module
RT1 and RT0 — Real-Time Interrupt Select Bits
These read/write bits select one of four real-time interrupt rates, as shown in
. Because the selected RTI output drives the COP watchdog, changing the real-time interrupt rate also changes the counting rate of the COP watchdog. Reset sets RT1 and RT0.
NOTE
Changing RT1 and RT0 when a COP timeout is imminent can cause a real-time interrupt request to be missed or an additional real-time interrupt request to be generated. To prevent this occurrence, clear the COP timer before changing RT1 and RT0.
RT1:RT0
0 0
0 1
1 0
1 1
Table 9-1. Real-Time Interrupt Rate Selection
RTI Rate f f
OP
÷ 2
14
OP
÷ 2
15 f
OP
÷ 2
16 f
OP
÷ 2
17
RTI Period
(f
OP
= 2 MHz)
8.2 ms
16.4 ms
32.8 ms
65.5 ms
COP Timeout Period
(–0/+1 RTI Period)
8 x RTI Period
8 x RTI Period
8 x RTI Period
8 x RTI Period
Minimum COP Timeout
Period
(f
OP
= 2 MHz)
65.5 ms
131.1 ms
262.1 ms
524.3 ms
9.5.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first eight stages is readable at any time from the read-only timer counter register shown in
Address: $0009
Bit 7
Read: TCR7
Write:
Reset: 0
6
TCR6
5
TCR5
4
TCR4
3
TCR3
2
TCR2
1
TCR1
0
Bit 0
TCR0
0 0
= Unimplemented
0 0 0 0
Figure 9-4. Timer Counter Register (TCR)
Power-on clears the entire counter chain and the internal clock begins clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in the mask option register is set), the power-on reset circuit is released, clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer interrupt every 1024 internal clock cycles.
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MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Low-Power Modes
9.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby states.
9.6.1 Stop Mode
The STOP instruction has the following effects on the timer:
• Clears the timer counter
• Clears interrupt flags (TOF and RTIF) and interrupt enable bits (TOFE and RTIE) in TSCR, removing any pending timer interrupt requests and disabling further timer interrupts
9.6.2 Wait Mode
The timer remains active after a WAIT instruction. Any enabled timer interrupt request can bring the MCU out of wait mode.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 83
Multifunction Timer Module
84
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 10
Electrical Specifications
10.1 Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
For guaranteed operating conditions, refer to
10.6 3.3-V DC Electrical Characteristics
Rating
Supply Voltage
Current Drain per Pin (Excluding V
DD
, V
SS
)
Input Voltage
IRQ/V
PP
Pin
Storage Temperature Range
1. Voltages are referenced to V
SS
.
Table 10-1. Maximum Ratings
(1)
Symbol
V
DD
I
V
In
V
PP
T
STG
Value
–0.3 to +7.0
25
V
SS
– 0.3 to V
DD
+ 0.3
V
SS
– 0.3 to 2 x V
DD
+ 0.3
–65 to +150
Unit
V mA
V
V
° C
10.2 Operating Temperature Range
Package Type
MC68HC705KJ1C
(1)
P
(2)
, CDW
(3)
, CS
(4)
1. C = extended temperature range
2. P = plastic dual in-line package (PDIP)
3. DW = small outline integrated circuit (SOIC)
4. S = ceramic DIP (Cerdip)
Symbol
T
A
Value (T
L
to T
H
)
–40 to +85
Unit
° C
10.3 Thermal Characteristics
Characteristic
Thermal Resistance
MC68HC705KJ1P
(1)
MC68HC705KJ1DW
(2)
MC68HC705KJ1S
(3)
1. P = plastic dual in-line package (PDIP)
2. DW = small outline integrated circuit (SOIC)
3. S = ceramic DIP (Cerdip)
Symbol
θ
JA
Value
60
Unit
° C/W
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 85
Electrical Specifications
10.4 Power Considerations
The average chip junction temperature, T
J
, in
°
C can be obtained from:
T J = T A + ( P D × θ
JA
) where:
T
A
θ
JA
= ambient temperature in ° C
= package thermal resistance, junction to ambient in
°
C/W
P
D
= P
INT
P
INT
= I
+ P
I/O
CC
×
V
CC
= chip internal power dissipation
P
I/O
= power dissipation on input and output pins (user-determined)
For most applications, P
I/O
P
INT and can be neglected.
Ignoring P
I/O
, the relationship between P
D and T
J
is approximately:
P D =
T J + 273
°
C
(1)
(2)
Solving equations (1) and (2) for K gives:
= P
D
x (T
A
+ 273°C) +
Θ
J
A
x (P
D
)
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P
D
(at equilibrium) for a known T
A
. Using this value of K, the values of P
D obtained by solving equations (1) and (2) iteratively for any value of T
A
.
and T
J can be
86
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
5.0-V DC Electrical Characteristics
10.5 5.0-V DC Electrical Characteristics
Characteristic
(1)
Output high voltage
(I
Load
= –2.5 mA) PA4–PA7
(I
Load
= –5.5 mA) PB2–PB3, PA0–PA3
Output low voltage
(8)
(I
Load
= 10.0 mA) PA0–PA7, PB2–PB3
Input high voltage
PA0–PA7, PB2–PB3, IRQ/V
PP
, RESET, OSC1
Input low voltage
PA0–PA7, PB2–PB3, IRQ/V
PP
, RESET, OSC1
Supply current (f
OP
= 2.1 MHz; f
OSC
= 4.2 MHz)
Run mode
(3)
Wait mode
(4)
Stop mode
(5)
Supply current (f
OP
= 4.0 MHz; f
OSC
= 8.0 MHz)
Run mode
(3)
Wait mode
(4)
Stop mode
(5)
I/O Ports Hi-Z leakage current
PA0–PA7, PB2–PB3 (without individual pulldown activated)
Input pulldown current
PA0–PA7, PB2–PB3 (with individual pulldown activated)
Input pullup current
RESET
Input current
(6)
RESET, IRQ/V
PP
, OSC1
Symbol
V
V
I
I
V
V
I
I
I
I
OH
OL
IH
IL
DD
DD
IL
IL
IL
In
V
V
Min
DD
DD
0.7
V
×
–0.8
–0.8
—
V
SS
—
—
—
—
—
—
—
35
–15
—
DD
Typ
—
—
—
—
—
4.0
1.0
0.1
5.2
1.1
0.1
0.2
80
0.2
(2)
–35
Max
0.2
—
—
0.8
V
×
6.0
2.8
5.0
7.0
3.3
5.0
±
DD
V
1
200
–85
±
1
DD
Unit
V
V
V
V mA mA
µ A mA mA
µ A
µ
µ
µ
µ
A
A
A
A
Capacitance
Ports (As Inputs or Outputs)
RESET, IRQ, OSC1, OSC2
C
Out
C
In
—
—
—
—
12
8 pF
Crystal/ceramic resonator oscillator mode internal resistor
OSC1 to OSC2
(7)
R
OSC
1.0
2.0
3.0
M Ω
1. V
DD
= 5.0 Vdc ± 10%, V
2. Typical values at midpoint of voltage range, 25 ° C only
3. Run mode I
DD
is measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; C
L
4. Wait mode I
DD
SS
= 0 Vdc, T
= 20 pF on OSC2.
A
= –40 ° C to +85 ° C, unless otherwise noted.
: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured with all ports configured as inputs; V
IL
= 0.2 V; V
IH
= V
DD
is measured with OSC1 = V
– 0.2 V. Wait mode I
DD
is measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; C
L
= 20 pF on OSC2.
SS
. Stop mode I
DD
is measured with all ports configured as inputs; V
IL
= 0.2 V; 5. Stop mode I
DD
V
IH
= V
6. Only input high current rated to +1 µ A on RESET.
7. The R
DD
OSC
– 0.2 V.
value selected for RC oscillator versions of this device is unspecified.
8. Maximum current drain for all I/O pins combined should not exceed 100 mA.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 87
Electrical Specifications
10.6 3.3-V DC Electrical Characteristics
Characteristic
(1) Symbol Min Typ
(2) Max Unit
Output high voltage
(I
Load
= –0.8 mA) PA4–PA7
(I
Load
= –1.5 mA) PA0–PA3, PB2–PB3
Output low voltage
(I
Load
= 5.0 mA) PA4–PA7
(I
Load
= 3.5 mA) PA0–PA3, PB2–PB3
Input high voltage
PA0–PA7, PB2–PB3, IRQ/V
PP
, RESET, OSC1
Input low voltage
PA0–PA7, PB2–PB3, IRQ/V
PP
, RESET, OSC1
Supply current (f
OP
= 1.0 MHz; f
OSC
= 2.0 MHz)
Run mode
(3)
Wait mode
(4)
Stop mode
(5)
Supply current (f
OP
= 2.1 MHz; f
OSC
= 4.2 MHz)
Run mode
(3)
Wait mode
(4)
Stop mode
(5)
I/O ports hi-z leakage current
PA0–PA7, PB2–PB3 (without individual pulldown activated)
Input pulldown current
PA0–PA7, PB2–PB3 (with individual pulldown activated)
V
V
I
I
V
V
I
I
OH
OL
IH
IL
DD
DD
IL
IL
V
V
DD
DD
0.7
V
–0.3
–0.3
—
—
× V
SS
—
—
—
—
—
—
—
12
DD
—
—
—
—
—
—
1.2
0.3
0.1
1.4
0.3
0.1
0.1
30
0.2
—
—
0.5
0.5
V
×
2.5
0.8
5.0
3.0
1.0
5.0
±
DD
V
1
100
DD
V
V
V
V mA mA
µ A mA mA
µ
A
µ
µ
A
A
Input pullup current
RESET
Input current
(6)
RESET, IRQ/V
PP
, OSC1
I
I
IL
In
–10
—
–25
0.1
–45
± 1
µ
µ
A
A
Capacitance
Ports (as inputs or outputs)
RESET, IRQ/V
PP
, OSC1, OSC2
C
Out
C
In
—
—
—
—
12
8 pF
Crystal/ceramic resonator oscillator mode internal resistor
OSC1 to OSC2
(7)
R
OSC
1.0
2.0
3.0
M Ω
1. V
DD
= 3.3 Vdc ± 10%, V
2. Typical values at midpoint of voltage range, 25 ° C only
3. Run mode I
DD
is measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; C
L
4. Wait mode I
DD
SS
= 0 Vdc, T
= 20 pF on OSC2.
A
= –40 ° C to +85 ° C, unless otherwise noted.
: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured with all ports configured as inputs; V
IL
= 0.2 V; V
IH
= V
DD
– 0.2 V. Wait mode I
DD
is measured using external square wave
= 20 pF on OSC2.
clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; C
L
5. Stop mode I
V
IH
= V
7. The R
DD
OSC
DD
is measured with OSC1 = V
– 0.2 V.
SS
. Stop mode I
DD
is measured with all ports configured as inputs; V
6. Only input high current rated to +1 µ A on RESET. value selected for RC oscillator versions of this device is unspecified.
IL
= 0.2 V;
88
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Driver Characteristics
10.7 Driver Characteristics
800
700
600
500
400
300
200
100
0
0
85 ° C 25 ° C
–40
°
C
V
DD
= 5.0 V
800
700
600
500
400
300
200
100
0
0
85
°
C 25
°
C
–40
°
C
–2 –4
I
OH
(mA)
–6 –8 –10 –2 –4
I
OH
(mA)
–6
Notes:
1. At V
DD
= 5.0 V, devices are specified and tested for (V
DD
– V
OH
2. At V
DD
= 3.3 V, devices are specified and tested for (V
DD
– V
OH
) ≤ 800 mV @ I
OH
= –2.5 mA.
)
≤
300 mV @ I
OH
= –0.8 mA.
V
DD
= 3.3 V
–8
Figure 10-1. PA4–PA7 Typical High-Side Driver Characteristics
–10
800
700
600
500
400
300
200
100
0
0
85
°
C
25 ° C
–40
°
C
V
DD
= 5.0 V
800
700
600
500
400
300
200
100
0
0
85
°
C
25
°
C
–40
°
C
–2 –4
I
OH
(mA)
–6 –8 –10 –2 –4
I
OH
(mA)
–6
Notes:
1. At V
DD
= 5.0 V, devices are specified and tested for (V
DD
2. At V
DD
= 3.3 V, devices are specified and tested for (V
DD
– V
OH
– V
OH
) ≤ 800 mV @ I
) ≤ 300 mV @ I
OH
= –5.5 mA.
OH
= –1.5 mA.
V
DD
= 3.3 V
–8
Figure 10-2. PA0–PA3 and PB2–PB3 Typical High-Side Driver Characteristics
–10
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 89
Electrical Specifications
800
700
600
500
400
300
200
100
85
°
C 25
°
C
–40
°
C
V
DD
= 5.0 V
800
700
600
500
400
300
200
100
85 ° C 25
°
C
–40
°
C
0
0 10 20
I
OL
(mA)
30 40 50
0
0 10 20
I
OL
(mA)
30
Notes:
1. At V
DD
= 5.0 V, devices are specified and tested for V
OL
2. At V
DD
= 3.3 V, devices are specified and tested for V
OL
≤
800 mV @ I
OL
= 10.0 mA.
≤ 500 mV @ I
OL
= 5.0 mA.
Figure 10-3. PA4–PA7 Typical Low-Side Driver Characteristics
V
DD
= 3.3 V
40 50
800
700
600
500
400
300
200
100
0
0
85
°
C
10
I
OL
(mA)
20
25 ° C
–40
°
C
V
DD
= 5.0 V
800
700
600
500
400
300
200
100
0
0
85
°
C
25
°
C
–40
°
C
V
DD
= 3.3 V
30 10
I
OL
(mA)
20
Notes:
1. At V
DD
= 5.0 V, devices are specified and tested for V
OL
2. At V
DD
= 3.3 V, devices are specified and tested for V
OL
≤ 800 mV @ I
≤ 500 mV @ I
OL
= 10.0 mA.
OL
= 3.5 mA.
Figure 10-4. PA0–PA3 and PB2–PB3 Typical Low-Side Driver Characteristics
30
90
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Typical Supply Currents
10.8 Typical Supply Currents
7.0 mA
6.0 mA
5.0 mA
4.0 mA
3.0 mA
2.0 mA
1.0 mA
0
0
SEE NOTE 2
SEE NOTE 1
5.5 V
4.5 V
3.6 V
3.0 V
1.0 MHz 2.0 MHz 3.0 MHz 4.0 MHz
Notes:
1. At V
DD
= 5.0 V, devices are specified and tested for I
DD
≤ 7.0 mA @ f
OP
= 4.0 MHz.
2. At V
DD
= 3.3 V, devices are specified and tested for I
DD
≤ 4.25 mA @ f
OP
= 2.1 MHz.
INTERNAL OPERATING FREQUENCY (f
OP
)
Figure 10-5. Typical Operating I
DD
(25
°
C)
SEE NOTE 2
SEE NOTE 1
5.5 V
4.5 V
700
µ
A
600
µ
A
500
µ
A
400 µ A
300
µ
A
200
µ
A
100
µ
A
0
0
3.6 V
3.0 V
1.0 MHz 2.0 MHz 3.0 MHz 4.0 MHz
Notes:
1. At V
DD
= 5.0 V, devices are specified and tested for I
DD
≤
3.25 mA @ f
OP
= 4.0 MHz.
2. At V
DD
= 3.3 V, devices are specified and tested for I
DD
≤
1.75 mA @ f
OP
= 2.1 MHz.
INTERNAL OPERATING FREQUENCY (f
OP
)
Figure 10-6. Typical Wait Mode I
DD
(25
°
C)
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 91
Electrical Specifications
10.9 EPROM Programming Characteristics
Characteristic
(1)
Symbol
Programming voltage
IRQ/V
PP
Programming current
IRQ/V
PP
V
I
PP
PP
Programming time
Per array byte
MOR t
EPGM t
MPGM
1. V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= – 40
°
C to +85
°
C, unless otherwise noted.
Min
16.0
—¦
4
4
Typ
16.5
3.0
—
—
Max
17.0
10.0
—
—
Unit
V mA ms
10.10 Control Timing
Table 10-2. Control Timing (V
DD
= 5.0 Vdc)
(1)
Characteristic
Oscillator frequency
Crystal oscillator option
External clock source
Internal operating frequency (f
OSC
÷ 2)
Crystal oscillator
External clock
Cycle time (1 ÷ f
OP
)
RESET pulse width low
Symbol f f
OSC
OP
Min
— dc
— dc
Max
8.0
8.0
4.0
4.0
Unit
MHz
MHz t cyc t
RL
250
1.5
—
— ns t cyc
IRQ interrupt pulse width low
(edge-triggered)
IRQ interrupt pulse width low
(edge- and level-triggered)
PA0–PA3 Interrupt pulse width high
(edge-triggered)
PA0–PA3 interrupt pulse width
(edge- and level-triggered) t t t t
ILIH
ILIL
IHIL
IHIH
1.5
1.5
1.5
1.5
—
Note
—
Note
(2)
(2) t t t t cyc cyc cyc cyc
OSC1 pulse width t
OH
, t
OL
100 — ns
1. V
DD
= 5.0 Vdc ± 10%, V
SS
2. The maximum width t
ILIL routine plus 19 t cyc
= 0 Vdc,
or t
ILIH
T
A
= – 40
°
C to +85
°
C, unless otherwise noted.
should not be more than the number of cycles it takes to execute the interrupt service
or the interrupt service routine will be re-entered.
92
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Control Timing
Table 10-3. Control Timing (V
DD
= 3.3 Vdc)
(1)
Characteristic Symbol Min Max Unit
Oscillator frequency
Crystal oscillator option
External clock source
Internal operating frequency (f
OSC
÷ 2)
Crystal oscillator
External clock
Cycle time (1 ÷ f
OP
) f f
OSC
OP
— dc
— dc
4.2
4.2
2.1
2.1
MHz
MHz
RESET pulse width low t cyc t
RL
476
1.5
—
— ns t cyc
IRQ interrupt pulse width low
(edge-triggered)
IRQ interrupt pulse width low
(edge- and level-triggered)
PA0–PA3 interrupt pulse width high
(edge-triggered)
PA0–PA3 interrupt pulse width
(edge- and level-triggered) t t t t
ILIH
ILIL
IHIL
IHIH
1.5
1.5
1.5
1.5
—
Note
—
Note
(2)
(2) t t t t cyc cyc cyc cyc
OSC1 pulse width t
OH
, t
OL
200 — ns
1. V
DD
= 3.3 Vdc ± 10%, V
2. The maximum width t routine plus 19 t cyc
SS
ILIL
= 0 Vdc, T
A
=
or t
ILIH
– 40
°
C to +85
°
C, unless otherwise noted.
should not be more than the number of cycles it takes to execute the interrupt service
or the interrupt service routine will be re-entered.
t
ILIL
IRQ PIN
IRQ
1
.
.
.
IRQ n
IRQ
(INTERNAL) t
ILIH t
ILIH
Figure 10-7. External Interrupt Timing
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 93
Electrical Specifications
OSC (NOTE 1) t
RL
RESET t
ILIH
IRQ (NOTE 2)
OSCILLATOR STABILIZATION DELAY
(5)
IRQ (NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
07FE
(NOTE 4)
07FE 07FE 07FE 07FE 07FF
RESET OR INTERRUPT
VECTOR FETCH
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
5. 4064 t cyc
or 128 t cyc
, depending on the state of SOSCD bit in MOR
Figure 10-8. Stop Mode Recovery Timing
V
DD
(NOTE 1)
OSCILLATOR STABILIZATION DELAY
(3)
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
07FE 07FE 07FE 07FE
INTERNAL
DATA BUS
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
3. 4064 t cyc
or 128 t cyc
depending on the state of SOSCD bit in MOR
Figure 10-9. Power-On Reset Timing
07FE 07FE
NEW
PCH
07FF
NEW
PCL
94
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Control Timing
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
INTERNAL
DATA BUS
07FE 07FE 07FE 07FE 07FF NEW PC NEW PC
NEW
PCH
NEW
PCL
DUMMY
OP
CODE t
RL
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 10-10. External Reset Timing
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 95
Electrical Specifications
96
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Chapter 11
Ordering Information and Mechanical Specifications
11.1 Introduction
The MC68HC705J1A, the RC oscillator, and low-speed option devices described in
and Appendix B MC68HLC705KJ1 are available in these packages:
• 648 — Plastic dual in-line package (PDIP)
• 751G — Small outline integrated circuit (SOIC)
• 620A — Ceramic DIP (Cerdip) (windowed)
This section contains ordering information and mechanical specifications for the available package types.
11.2 MCU Order Numbers
Table 11-1 lists the MC order numbers.
Table 11-1. Order Numbers
(1)
Package
Type
PDIP
SOIC
Cerdip
Case
Outline
648
751G
620A
Pin
Count
16
16
16
Operating
Temperature
Order Number
–40 to +85
°
C MC68HC705KJ1C
(2)
–40 to +85 ° C MC68HC705KJ1CDW
–40 to +85 ° C MC68HC705KJ1CS
(4)
(3)
1. Refer to Appendix A MC68HRC705KJ1
and
for ordering information on optional low-speed and resistor-capacitor oscillator devices.
2. C = extended temperature range
3. DW = small outline integrated circuit (SOIC)
4. S = ceramic dual in-line package (Cerdip)
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 97
Ordering Information and Mechanical Specifications
11.3 16-Pin PDIP — Case #648
–A–
16
1
H
G
9
B
8
F
C
S
–T–
SEATING
PLANE
K
D
16 PL
0.25 (0.010) M T A M
J
STYLE 1:
PIN 1.
CATHODE
L
M
STYLE 2:
PIN 1.
COMMON DRAIN
11.4 16-Pin SOIC — Case #751G
16
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
MILLIMETERS
MIN MAX
A 0.740
0.770
18.80
19.55
B 0.250
0.270
6.35
6.85
C 0.145
0.175
D 0.015
0.021
3.69
0.39
4.44
0.53
F 0.040
G
0.70
0.100 BSC
H 0.050 BSC
J 0.008
0.015
K 0.110
0.130
1.02
1.77
2.54 BSC
1.27 BSC
0.21
2.80
0.38
3.30
L 0.295
0.305
M 0
_
10
S 0.020
0.040
_
7.50
0
0.51
_
7.74
10
1.01
_
-A-
9
-B-
8
D
16X
0.010 (0.25) M T A S B S
8X
P
0.010 (0.25) M B M
J
F
R
X 45
DIM
A
B
M
P
J
K
R
F
G
C
D
MILLIMETERS
MIN
10.15
7.40
MAX
10.45
7.60
2.35
0.35
2.65
0.49
0.50
1.27 BSC
0.90
0.25
0.10
0 °
10.05
0.25
0.32
0.25
7 °
10.55
0.75
MIN
0.400
0.292
INCHES
MAX
0.411
0.299
0.093
0.014
0.104
0.019
0.020
0.035
0.050 BSC
0.010
0.004
0 °
0.395
0.010
0.012
0.009
7 °
0.415
0.029
G
14X
K
C
-T-
SEATING
PLANE
M
98
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
16-Pin Cerdip — Case #620A
11.5 16-Pin Cerdip — Case #620A
B
B
16
1
A
9
8
A
L
E
F
C
K
N
G
16X
D
0.25 (0.010) M T A
T
SEATING
PLANE
M
16X
J
0.25 (0.010) M T B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750
0.785
19.05
19.93
B 0.240
0.295
6.10
7.49
C ––– 0.200
D 0.015
0.020
–––
0.39
5.08
0.50
E 0.050 BSC
F 0.055
0.065
G 0.100 BSC
H 0.008
0.015
K 0.125
0.170
1.27 BSC
1.40
1.65
2.54 BSC
0.21
3.18
0.38
4.31
L
M
0.300 BSC
0
_
15
N 0.020
0.040
_
7.62 BSC
0
0.51
_
15
1.01
_
STYLE 1:
PIN 1.
CATHODE
2.
CATHODE
3.
CATHODE
4.
CATHODE
5.
CATHODE
6.
CATHODE
7.
CATHODE
8.
CATHODE
9.
ANODE
10.
ANODE
11 ANODE
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 99
Ordering Information and Mechanical Specifications
100
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Appendix A
MC68HRC705KJ1
A.1 Introduction
This appendix introduces the MC68HRC705KJ1, a resistor-capacitor (RC) oscillator mask option version of the MC68HC705KJ1. All of the information in MC68HC705KJ1 Technical Data applies to the
MC68HRC705KJ1 with the exceptions given in this appendix.
A.2 RC Oscillator Connections
to drive the on-chip oscillator. Mount the RC components as close as possible to the pins for startup stabilization and to minimize output distortion.
R
OSC1
OSC2
MCU
R
V
DD
C2 C1
V
SS
Figure A-1. RC Oscillator Connections
NOTE
The optional internal resistor is not recommended for configurations that use the RC oscillator connections as shown in
configurations, the oscillator internal resistor (OSCRES) bit of the mask option register should be programmed to a logic 0.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 101
MC68HRC705KJ1
A.3 Typical Internal Operating Frequency for RC Oscillator Option
Figure A-2 shows typical internal operating frequencies at 25
°
C for the RC oscillator option.
NOTE
Tolerance for resistance is
±
50%. When selecting resistor size, consider the tolerance to ensure that the resulting oscillator frequency does not exceed the maximum operating frequency.
10
1
5.5 V
5.0 V
4.5 V
3.6 V
3.0 V
0.1
1 10 100
RESISTANCE (k Ω )
Figure A-2. Typical Internal Operating Frequency for Various V
DD
at 25
°
C — RC Oscillator Option Only
1000
102
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
RC Oscillator Connections (No External Resistor)
A.4 RC Oscillator Connections (No External Resistor)
For maximum cost reduction, the RC oscillator mask connections shown in
oscillator to be driven with no external components. This can be accomplished by programming the oscillator internal resistor (OSCRES) bit in the mask option register to a logic 1. When programming the
OSCRES bit for the MC68HRC705KJ1, an internal resistor is selected which yields typical internal oscillator frequencies as shown in
Figure A-4 . The internal resistance for this device is different than the
resistance of the selectable internal resistor on the MC68HC705KJ1 and the MC68HRC705KJ1 devices.
R
MCU
OSC1
OSC2
V
DD
C2 C1
(EXTERNAL CONNECTIONS LEFT OPEN)
V
SS
Figure A-3. RC Oscillator Connections (No External Resistor)
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 103
MC68HRC705KJ1
A.5 Typical Internal Operating Frequency Versus Temperature
(No External Resistor)
3.00
2.50
2.00
1.50
1.00
0.50
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
0.00
–50 0 50
Temperature ( ° C)
100
Figure A-4. Typical Internal Operating Frequency versus Temperature (OSCRES Bit = 1)
150
NOTE
Due to process variations, operating voltages, and temperature requirements, the internal resistance and tolerance are unspecified.
Typically for a given voltage and temperature, the frequency should not vary more than
±
500 kHz. However, this data is not guaranteed. It is the user’s responsibility to ensure that the resulting internal operating frequency meets user’s requirements.
A.6 Package Types and Order Numbers
Table A-1. MC68HRC705KJ1 (RC Oscillator Option)
Order Numbers
(1)
Package
Type
PDIP
SOIC
Cerdip
Case
Outline
648
751G
620A
Pin
Count
16
16
16
Operating
Temperature
–40 to +85 ° C
–40 to +85 ° C
–40 to +85 ° C
Order Number
MC68HRC705KJ1C
(2)
MC68HRC705KJ1CDW
MC68HRC705KJ1CS
P
(3)
(4)
(5)
1. Refer to Chapter 11 Ordering Information and Mechanical Specifications for standard part
ordering information.
2. C = extended temperature range
3. P = plastic dual in-line package (PDIP)
4. DW = small outline integrated circuit (SOIC)
5. S = ceramic dual in-line package (Cerdip)
104
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
Appendix B
MC68HLC705KJ1
B.1 Introduction
This appendix introduces the MC68HLC705KJ1, a low-frequency version of the MC68HC705KJ1 optimized for 32-kHz oscillators. All of the information in MC68HC705KJ1 Technical Data applies to the
MC68HLC705KJ1 with the exceptions given in this appendix.
B.2 DC Electrical Characteristics
Table B-1. DC Electrical Characteristics (V
DD
= 5 V)
Symbol Min Characteristic
Supply Current (f
OP
= 16.0 kHz, f
OSC
= 32.0 kHz)
Run
Wait
I
DD
—
—
Typ
45
20
Max
60
30
Unit
µ A
Table B-2. DC Electrical Characteristics (V
DD
= 3.3 V)
Symbol Min Characteristic
Supply Current (f
OP
= 16.0 kHz, f
OSC
= 32.0 kHz)
Run
Wait
I
DD
—
—
Typ
25
10
Max
35
15
Unit
µ A
MCU
R
S
R
P
C
L
32 kHz
C
L
Figure B-1. Crystal Connections
NOTE
Supply current is impacted by crystal type and external components.Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values for external components.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor 105
MC68HLC705KJ1
B.3 Package Types and Order Numbers
Table B-3. MC68HLC705KJ1 (Low Frequency) Order Numbers
(1)
Package
Type
PDIP
SOIC
Cerdip
Case
Outline
648
751G
620A
Pin
Count
16
16
16
Operating
Temperature
–40 to +85 ° C
–40 to +85 ° C
–40 to +85 ° C
Order Number
MC68HLC705KJ1C
(2)
MC68HLC705KJ1CDW
MC68HLC705KJ1CS
P
(3)
(4)
1. Refer to Chapter 11 Ordering Information and Mechanical Specifications for standard part
ordering information.
2. C = extended temperature range
3. DW = small outline integrated circuit (SOIC)
4. S = ceramic dual in-line package (Cerdip)
106
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
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MC68HC705KJ1
Rev. 4.1, 07/2005
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