NXP C-3E C-3e Network Processor Data Sheet
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Data Sheet
C-3e NETWORK PROCESSOR
SILICON REVISION B0
C3ENPB0-DS
Rev 03 PRODUCTION
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Data Sheet
C-3e Network Processor
Silicon Revision B0
C3ENPB0-DS
Rev 03
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CONTENTS
About This Guide
Functional Description
Signal Descriptions
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6 CONTENTS
C
3
Electrical Specifications
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CONTENTS 7
100
Mechanical Specifications
103
105
105
107
107
Index
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8 CONTENTS
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LIST OF FIGURES
C-3e Network Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Locations (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pin Locations (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
GMII/TBI Transmit and Receive Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PROM Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PROM Interface Timing Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Observe-Only Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Cell Design That Can Be Used for Both Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . 67
Bringup Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package Cross Section View with Several Heat Sink Options . . . . . . . . . . . . . . . . . . . . . . . . 76
Package with Heat Sink Mounted to the Printed Circuit Board . . . . . . . . . . . . . . . . . . . . . . . 77
Test Loading Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
System Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
DS1/DS3 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10/100 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Gigabit Ethernet and TBI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
OC-3 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
OC-12 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PCI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MDIO Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Low Speed Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PROM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Fabric Processor Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
TLU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
QMU SRAM (Internal Mode) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
QMU to Q-5 (External Mode) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
C-3e Network Processor BGA Package (Side View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
C-3e Network Processor BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
C-3e Network Processor BGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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10 LIST OF FIGURES
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LIST OF TABLES
Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Navigating Within a PDF Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
C-Port Silicon Documentation Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
C-3e Network Processor Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TLU SRAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CP Physical Interface Signals and Pins (Grouped by Clusters) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DS1/T1 Framer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10/100 Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel . . . . . . . . . . . 35
Gigabit Ethernet (GMII/MII) Signals One Cluster Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Gigabit Ethernet and Fibre Channel TBI Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
OC-3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
OC-12 Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Fabric Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Utopia1*, 2, 3 ATM Mode, C-3e Network Processor to Fabric Interface Pin Mapping . . . . . . 49
Utopia1*, 2, 3 PHY Mode, C-3e Network Processor to Fabric Interface Pin Mapping . . . . . . . 49
BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
QMU SRAM (Internal Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
QMU to Q-5 (External Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines . . . . . . . . . . . . . . . . 56
Signals Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
JTAG Internal Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
JTAG Identification Code and Its Sub-components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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12 LIST OF TABLES
Instruction Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
C-3e Network Processor Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
C-3e Network Processor Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .72
C-3e Network Processor DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
C-3e Network Processor Capacitance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
C-3e Network Processor Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
System Clock Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
DS1/DS3 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
10/100 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Gigabit GMII/MII Ethernet Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Gigabit TBI Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
OC-3 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
OC-12 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
PCI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
MDIO Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Low Speed Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
PROM Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Fabric Processor Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
BMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Signal Groups in BMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
TLU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Signal Groups in TLU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
QMU SRAM (Internal Mode) Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . .99
QMU to Q-5 TMC (External Mode) Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Signal Groups in QMU to Q-5 TMC (External Mode) Timing Diagrams . . . . . . . . . . . . . . . . . . . 101
Package Measurements (Reference Figure 28 , and Figure 29 for Symbols) . . . . . . . . . . . . . 105
Keep Out Zone’s Measurements (Reference Figure 30 for Symbols) . . . . . . . . . . . . . . . . . . . . 106
C-3e Network Processor Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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ABOUT THIS GUIDE
Guide Overview
The C-3e Network Processor Data Sheet describes the hardware layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical specifications.
Motorola reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
This guide assumes a good understanding of the C-3e TM Network Processor (NP) architecture. See the C-5e/C3e Network Processor Architecture Guide (part number
C5EC3EARCH-RM) for more detail about how the hardware works.
This guide also assumes good working knowledge of the C-Ware Software Toolset.
This guide covers the following topics:
•
•
•
•
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14 ABOUT THIS GUIDE
Data Sheet Classifications
Table 1 describes the Data Sheet classifications of Advance, Preliminary, and Production.
Table 1 Data Sheet Classifications
CLASSIFICATION DESCRIPTION
Advance
Information
Used to advise customers of the proposed addition to the product line. This document will typically contain some useful information including interfacing with the user’s system and some specifications. The goal of this document is to allow customers to begin designs but with expectation of changes. Specification details may be changed later without notice.
Preliminary
Information
Describes pre-production or first production devices and is usually indicative of production stage performance. Minor changes should be expected as characteristic spreads become better controlled. Specification details may be changed slightly without notice, but the customer can design their product based on this data sheet.
Production Data Defines the long-term specified production limits based on fully characterized data. It includes a disclaimer to allow improvements in specifications and modifications that do not affect form, fit or function in original applications; if absolute maximum ratings are changed, they should improve rather than downgrade.
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16 ABOUT THIS GUIDE
Guide Conventions
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Related Product Documentation 17
Related Product
Documentation
Table 3 lists the user and reference documentation for Motorola ‘s C-Port silicon
documentation set.
Table 3 C-Port Silicon Documentation Set
DOCUMENT NAME PURPOSE
C-5e/C-3e Network Processor Architecture Guide Describes the full architecture of the C-5e and C-3e network processors.
C-5e Network Processor Data Sheet
C-3e Network Processor Data Sheet
Describes hardware design specifications for the C-5e network processor.
Describes hardware design specifications for the C-3e network processor.
C-5 Network Processor to C-5e Network Processor
Comparison Delta Document
M-5 Channel Adapter Architecture Guide
M-5 Channel Adapter Data Sheet
Describes key architectural features of the C-5e, and highlights main differences between C-5 and C-5e.
DOCUMENT ID
C5EC3EARCH-RM
C5ENPB0-DS
C3ENPB0-DS
C5C5EDELTA-RM
Describes the full architecture of the M-5 channel adapter. M5CAARCH-RM
Describes hardware design specifications for the M-5 channel adapter.
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18 ABOUT THIS GUIDE
Revision History
Table 4 provides details about changes made for each revision of this guide.
Table 4 C-3e Network Processor Data Sheet Revision History
REVISION CHANGES
03 • Chapter 3, OC-12 timing specifications section, Tc12o modified to allow a greater variety of phy components. The maximum value is consistent with previously specified 10.0ns value.
• Corrected revision history.
02
01
• Chapter 2, corrected OC-3, CP n _3 signal I/O type from O
PU
to I
PU
.
• Chapter 2, corrected JTAG identification code part number binary value.
• Chapter 2, clarified the function of the QACLKI signal for Internal Mode.
• Reflects the specification changes of the V
DD
Supply Voltage from 1.2V to 1.2V.
• Chapter 3, updated timing values from final characterization.
• Chapter 3, added BMU, TLU and QMU input clocks rise and fall times.
• Chapter 3, modified power sequencing information, added I
DDT
values.
• Chapter 4, modified keep out zone information.
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Chapter 1
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FUNCTIONAL DESCRIPTION
Features
Key features of the C-3e TM Network Processor (NP) are its massive processing capabilities and its high level of functional integration on one chip.
Massive Processing
Power
• Operating frequencies: up to 180MHz
• 3Gbps of bandwidth (for non-blocking throughput)
• More than 3,000MIPS of computing power (for adding services throughout the protocol stack)
•
Up to 9 million packets per second transmitted at wire speed
•
17 programmable RISC Cores (for cell/packet forwarding)
•
32 programmable Serial Data Processors (for processing bit streams)
•
Up to 125 million table lookups per second
•
Three internal buses for 46Gbs of aggregate bandwidth
High Functional
Integration
•
728 pin Ball Grid Array (BGA) package
•
16 Channel Processors (8 CP’s configurable for full I/O or recirculation, and 8 CP’s configurable for bit and byte level recirculation) including:
– Embedded OC-3c, OC-12, OC-12c SONET framers
– Programmable MAC interface
– RISC Cores
– Programmable pin PHY interfaces
• Embedded coprocessors for table lookup (classification), buffer management (payload control), and queue management (QoS implementation)
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20 CHAPTER 1: FUNCTIONAL DESCRIPTION
Block Diagram
•
Dedicated Fabric Processor and port
•
Embedded RISC Executive Processor
•
Integrated 32bit 33/66MHz PCI bus interface
The C-3e TM NP, has an architecture specifically designed for networking applications. The following sections describe each component of the C-3e NP.
The main components of the C-3e NP are:
•
•
•
•
•
•
The C-3e NP conforms with both SONET and SDH. Therefore, OC-3(STS-3/STM-1), and
OC-12 (STS-12/STM-4).
shows a block diagram of the C-3e NP, including its potential external interfaces.
For more information about the architecture of the C-3e NP, see the C-5e/C-3e Network
Processor Architecture Guide (part number C5EC3EARCH-RM) .
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Block Diagram 21
Figure 1 C-3e Network Processor Block Diagram
Q-5
(optional) SRAM SRAM
Fabric
Fabric
Processor
Table
Lookup
Unit
External
Host CPU
(optional)
External
PROM
(optional)
Control
Logic
(optional)
PCI Serial PROM
Executive Processor
SDRAM
Queue
Mgmt
Unit
Buses (64Gbps Bandwidth)
Buffer
Mgmt
Unit
C-3e
NP
Cluster
CP-0 CP-1 CP-2 CP-3 CP-12 CP-13 CP-14 CP-15
Channel
Processors
Cluster
Processor Boundary
PHY PHY PHY PHY
16 Channel Processors:
8 (CP0 to CP7) full functionality
8 (CP8 to CP15) Internal-only
PHY Interface Examples:
10/100 Ethernet
Gigabit Ethernet - Aggregated
OC-3
OC-12
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22 CHAPTER 1: FUNCTIONAL DESCRIPTION
Channel Processors
The C-3e NP contains eight programmable external Channel Processors (CPs) that receive, process, and transmit network data, plus an additional eight internal CPs that process data. Typically one CP is assigned to each port for medium bandwidth applications (Fast
Ethernet to OC-3). Multiple CPs can be assigned to a port in a configuration called channel aggregation in high bandwidth applications (greater than OC-3). Multiple logical ports can be assigned to a single CP, with the addition of an external multiplexor, for low bandwidth applications, such as DS1 to DS3.
The C-3e NP’s architecture supports a variety of industry-standard serial and parallel protocols and individual port data rates including:
•
10/100Mb Ethernet (RMII)
•
1Gb Ethernet (GMII and TBI)
•
OC-3c
•
OC-12
•
100Mbit FibreChannel
•
DS1/DS3, supported through the use of external framers/multiplexors
The C-3e NP’s programmability can also support a variety of special interfaces, such as various xDSL encapsulations and proprietary protocols.
Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet processing and a set of microprogrammable, special-purpose processors, called Serial
Data Processors (SDPs), that provide features such as Ethernet MAC and SONET/SDH framing, multichannel HDLC, and ATM cell delineation. This means you usually only need to include PHYs to complete the system.
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Executive Processor 23
Executive Processor
The Executive Processor (XP) serves as a centralized computing resource for the C-3e NP and manages the system interfaces.
The XP performs conventional supervisory tasks in the C-3e NP, including:
•
Reset and initialization of the C-3e NP
•
Program loading and control of CPs
•
Centralized exception handling
•
Management of a host interface through the PCI
•
Management of system interfaces (PCI, Serial Bus, PROM)
System Interfaces
The system interfaces to the XP are:
•
PCI — Provides an industry standard 32bit 33/66MHz PCI channel used for chip-level shared resources. The PCI has both initiator and target capabilities. The PCI interface is typically connected to a host processor.
•
Serial Bus Interface — Provides a general purpose bi-directional, two-wire serial bus and I/O port that allows the C-3e NP to control external logic with either of two standard protocols:
– The MDIO (high-speed) protocol : uses a 16bit data format with 10bits of addressing and supports transfers up to 25MHz.
– The low-speed protocol : uses an 8bit data format followed by an acknowledge bit and supports transfers up to 400kbps.
Software is used to select which protocol to use, by setting the appropriate bits in the
Serial Bus Configuration Register. When a serial bus transfer is active, an external pin is driven by the C-3e NP to indicate which protocol is being used (SPLD=0 indicates
MDIO protocol; SPLD=1 indicates low-speed protocol).
Both SIDA and SICL are bi-directional lines that are connected, via an external pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH because of the pull-up resistor. The output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism.
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24 CHAPTER 1: FUNCTIONAL DESCRIPTION
•
PROM Interface — Allows the XP to boot from nonvolatile, flash memory. The PROM interface is a low-speed, serial I/O port that runs at 1 /
2
to 1 /
16
the core clock rate. The maximum PROM size addressable is 4MBytes, and must use a “by 16” part. External board logic is required to perform serial-to-parallel conversion for PROM address outputs and parallel-to-serial conversion for PROM data inputs.
Fabric Processor
The Fabric Processor (FP) acts as a high-speed network interface port with advanced functionality. It allows the C-3e NP to interface to an application-specific switching solution internal to your design. The FP port supports the bidirectional transfer of segments from the C-3e NP to a hardware interface that provides connectivity to other network processors or other similar line processing hardware. There are numerous parameters that can be configured within the FP to allow the interface to be adapted to different fabric protocols. The FP can be configured to conform to three (3) different fabric interfaces that include: UTOPIA-1, -2, -3.
The FP can be configured to run at any frequency up to 125MHz, with the receive and transmit data buses up to 16 bits wide. This allows a wide range of supported bandwidths to and from the switching fabric, all the way up to 2000 Mbps full duplex bandwidth.
Buffer Management Unit
The Buffer Management Unit (BMU) interfaces the C-3e NP to external pipeline architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It is also used as second level storage in the XP memory hierarchy.
The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two internal control bits, and nine SECDED (single error correction-double error detection) ECC
(error correction code) bits. The interface is compliant with the PC100 standard and operates at up to 125MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the
C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM) for more details).
The C-3e NP non-configurable interface transfers four beats of data for each read and write using a sequential burst type. In addition, the C-3e NP uses an auto-refresh mode for the RAM’s.
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Table Lookup Unit
Table Lookup Unit 25
Some of these parameters are programmed into the SDRAMs’ mode register and can be applied only once per power cycle. The ECC functionality can be enabled or disabled via configuration register writes.
If needed, the interface can narrowed to 128bits by disabling ECC and providing board pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU supports SDRAM devices that use 12 address lines. Internal address calculation paths limit the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.
The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used for statistics accumulation and retrieval and as general data storage. The TLU simultaneously supports multiple application-defined tables and multiple search strategies, such as those needed for routing, circuit switching, and QoS lookup tasks.
The C-3e NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules
(at frequencies up to 125MHz) for storage of its tables. These modules allow implementation of tables with 2 25 x 64bit entries using 8Mbit SRAM technology. The maximum amount of memory supported by the TLU is 128MBytes in four banks, when
SRAM technology supports 4M x 18pins parts.
Table 5 TLU SRAM Configurations
SRAM TECHNOLOGY
1Mbit (32k x 32pins)
MIN TABLE SIZE
(ONE BANK)
256kBytes
2Mbit (64k x 32pins) 512kBytes
4Mbit (256k x 18pins) 2MBytes
8Mbit (512k x 18pins) 4MBytes
16Mbit (1M x 18pins) 8MBytes
32Mbit (2M x 18pins) 16MBytes
64Mbit (4M x 18pins) 32MBytes
MAXIMUM TABLE SIZE
(FOUR BANKS)
1MBytes
2MBytes
8MBytes
16MBytes
32MBytes
64MBytes
128MBytes
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26 CHAPTER 1: FUNCTIONAL DESCRIPTION
Queue Management Unit
The Queue Management Unit (QMU) autonomously manages a number of application-defined descriptor queues. It handles inter-CP and inter-C-3e NP descriptor flows by providing switching and buffering. It also performs descriptor replication for multicast applications. A number of up to 128 queues can be assigned to each CPRC for
QoS-based services.
The QMU provides a queuing engine internal to the chip and uses external SRAM to store the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and
16, 384 descriptor buffers. A descriptor buffer holds an application-defined “descriptor”, which is a structure that defines the payload buffer handle and other attributes of the forwarded cell or packet.
The QMU’s external SRAM interface uses ZBT synchronous SRAMs organized in a single bank of up to 128k, 32bit words. This interface runs at up to 150MHz frequency.
The C-3e provides two modes for managing queues. They consist of:
•
Internal Mode (using the internal QMU only)
•
External Mode (using the internal QMU and the external Q-5 Traffic Management
Coprocessor).
See the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM), for more details.
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SIGNAL DESCRIPTIONS
Signal Summary
There are nine (9) functional groupings of signals in the C-3e Network Processor:
•
Clock — 7 pins
• Channel Processors (CP0 - CP7) — 8x7 = 56 pins
•
Executive Processor (XP) — 57 pins
– PCI Interface — 50 pins
– PROM Interface — 4 pins
– Serial Bus Interface — 2 pins
– General System Interface — 1 pin
• Fabric Processor (FP) — 42 pins
•
Buffer Management Unit (BMU) — 160 pins
• Table Lookup Unit (TLU) — 99 pins
•
Queue Management Unit (QMU) — 59 pins
• Power — 234 pins
•
Test — 14 pins
Two (2) of the sections (CPs and FP) are configurable, depending on the type of device being implemented.
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28 CHAPTER 2: SIGNAL DESCRIPTIONS
Pinout Diagram
The C-3e NP contains 728 pins. These pin numbers are referenced throughout the
shows the pin locations from the top view. In contrast,
shows the pin locations from the bottom view.
AD
AC
AB
AA
Y
W
AG
AF
AE
H
G
K
J
V
U
T
R
M
L
P
N
F
E
D
C
B
A
Figure 2 Pin Locations (Top View)
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MD20
MD26
MD34
MD41
MD49
MD55
MD63
MD70
MD78
MD84
MD91
CP0_0 CP0_6 CP1_3 CP2_2 CP2_6 CP3_5 CP4_2
CP0_1
CP0_2
VDD33 CP1_4
CP1_0 CP1_5
CP2_3
VDD33
CP3_0 GND
CP3_1 CP3_6
CP4_3
CP4_4
CP0_3 GND CP1_6 CP2_4 CP3_2 VDD33 CP4_5
CP0_4
CP0_5
CP1_1 CP2_0
CP1_2 CP2_1
GND
CP2_5
MD0
MD6
VDD33
MD7
MD1
MD8
MD2
GND
CP3_3 CP4_0
CP3_4 CP4_1
CP4_6
CP5_0
MD3
MD9
GND
MD10
MD4
MD11
MD13 MD14 MD15 VDD33 MD16 MD17 MD18
CP5_1 CP6_0 CP6_5 FOUT0 FOUT2 FOUT8 FOUT14 FTXCTL2 FIN3 FIN9 FIN15 FRXCLK
CP5_2 CP6_1 VDD33 FOUT1 FOUT3 FOUT9 GND FTXCTL6 FIN4 FIN10 VDD33
CP5_3 CP6_2 CP6_6 CP7_3 FOUT4 FOUT10 FOUT15 FTXCLK FIN5 FIN11 FRXCTL0
PAD3
PAD2
CP5_4 GND CP7_0 CP7_4 FOUT5 FOUT11 VDD33 FIN0 FIN6 FIN12 FRXCTL1 GND
CP5_5 CP6_3 CP7_1 CP7_5 FOUT6 FOUT12 FTXCTL0 FIN1
CP5_6 CP6_4 CP7_2 CP7_6 FOUT7 FOUT13 FTXCTL1 FIN2
FIN7
FIN8
FIN13
FIN14
VDD33 GND VDD33
FRXCTL2
FRXCTL6
PAD1
PAD0
MD5
MD12
VDD33 GND VDD33
GND VDD GND
GND
VDD
VDD33
GND
GND
VDD GND VDD GND
GND
VDD
VDD33
GND
MD19 VDD33 GND VDD GND VDD GND VDD GND VDD GND VDDT
PAD9
PAD8
PAD7
PAD6
PAD15 PAD19 PAD25 PAD29 PCBEX1 PDEVSELX PPAR
PAD14
PAD13
GND PAD24 PAD28 PCBEX2 VDD33 PCLK
PAD18 PAD23 VDD33 PCBEX3 PSTOPX PRSTX
PAD12 VDD33 PAD22 PAD27 PSERRX GND PREQX
PAD5
PAD4
PGNTX
SPCK
PAD11
PAD10
PAD17 PAD21 GND PPERRX
PAD16 PAD20 PAD26 PAD31
PIRDYX PINTA
PCBEX0 PTRDYX
PFRAMEX
SPLD
GND
SPDI
PIDSEL SIDA PAD30
SPDO GND XPUHOT
VDDT
TA21
SICL
TA20
TA19 TA18 TA17 TA16 VDDT TA15 TA14 TA13
GND
MD27
MD35
MD42
MD28
MD36
MD43
VDD33
MD56
MD50
MD57
MD64
MD71
MD65
MD72
GND
MD21
MD85
MD92
MD98 VDD33 MD99 MD100
MD104 MD105 MD106 MD107
MD101 GND MD102
MD108 MD109 MD110
MD103 VDD33 GND VDD33
MD111 MBA0 MA3 MA8
GND VDD33
CCLK0 SCLKX
MD112
MD119
MD113
GND
MD79
MD86
MD93
MD114
MD120
MD22
MD29
GND
MD44
MD51
MD58
VDD33
MD73
MD80
GND
VDD33
GND
MD121
MD23
MD30 MD31
MD37 MD38
MD45 MD46
MD52
MD59
GND
MD60
MD66
MD74
MD67
MD75
MD81 VDD33 MD82
MD87
MD94
MD115
VDD33
MD88
MD95
MD116
MD122 VDD33
MDECC6 VDD33 MDECC5 MDECC4 MDECC3 GND
MD24
MD32
MD39
MD47
MD53
MD61
MD68
MD76
MD89
MD96
MD117
MD123
MD25
MD33 VDD33 GND
MD40 GND VDD
MD48 VDD33 GND
MD54
MD62
GND
VDD33
VDD
GND
MD69
MD77
GND VDD
VDD33 GND
MD83
MD90 VDD33 GND
MD97
MD118
MD124
MDECC0 MDCLK MCSX MCASX MRASX MWEX MDQML MDQM
27 26 25 24 23 22 21 20
GND
GND
GND VDD33 GND
MBA1
GND
MD125 MD126 MD127 VDD33 MD128 MD129 MDECC8 MDECC7 MA0
MDECC2 MDECC1 MA1
MA2
19
VDD
VDD
MA4
MA7
18
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
MA9
VDD33 JTCK
JTMS
17
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
16
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD33
GND VDD GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND VDD
VDD GND
GND VDD
VDD
GND
GND
VDD
VDD GND
GND VDD
GND
VDD
GND
VDD GND
GND VDD
VDD GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDDT
GND
VDDT
GND
VDDT
GND
VDDT
GND
VDDT
GND
GND
SCLK
VDD33 GND VDDT
QA14 QA9 QA3
GND VDDT
QARDY QACLKO
TA12 TA11 VDDT TA10
TD29
TA9
TD28
TA8
TA6 TA5 TA4 TA3 TA2 TA1
TCE2X TCE1X TCE0X TPAR3 GND
TWE3X TWE2X TWE1X TWE0X TCLKI
TPAR2
TD63
TD60
TD54
TD46
TD39
TD59
TD53
TD45
TD38
GND
TD52
TD44
TD37
TD58
TD51
TD43
TD36
TD57
TD50
VDDT
TD35
TD56
TD49
TD42
TD34
TD31 TD30 VDDT TD27
TD25
TD18
TD24
TD17
TD23
TD16
TD22
TD15
GND
VDDT
TD21
TD14
TD11
TD5
TD10
TD4
GND
TD3
TD9
TD2
TD8
TD1
TD7
TD0
CCLK1 CCLK2 CCLK3
MA5 MA10 CPREF JSE
MA6 MA11 JTDI JSO5
JHIGHZ
JTRSTX JCLKBYP
15
VDD33 QA16 QA11 QA5
JTDO JSO0 QA12 QA6
JSO3
JSO4
14
QA15 QA10 QA4
JSO1 GND QA7
JSO2 QA13 QA8
13 12 11
QWEX
QA0
QA1
VDDT
QA2
10
QACLKI
GND
QDPL
QDPH
QD30
QD31
QDQPAR
QBCLKO
QD25
QD26
QD27
QD28
QNQRDY QBCLKI QD29
9 8 7
QD22 QD17 GND
VDDT
GND
QD24
6
QD18
QD20
QD14
QD15
QD21 QD16
5 4
QD9
QD10
QD23 QD19 VDDT QD11
QD12
QD13
3
GND TA7
TA0
TPAR1
TD62
VDDT
TD48
TD41
TD33
TCE3X
TPAR0
TD61
TD55
TD47
TD40
TD32
GND TD26
TD20
TD13
VDDT
QD5
QD6
GND
QD7
VDDT
QD8
2
TD19
TD12
TD6
QD0
QD1
QD2
QD3
QD4
1
B
A
D
C
Y
W
V
U
T
R
M
L
P
N
AG
AF
AE
AD
AC
AB
AA
H
G
K
J
F
E
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Pinout Diagram 29
Figure 3 Pin Locations (Bottom View)
V
U
T
R
M
L
P
N
K
J
H
G
F
AD
AC
AB
AA
Y
W
AG
AF
AE
E
D
C
B
A
1
1 2
PPAR PDEVSELX PCBEX1 PAD29 PAD25 PAD19 PAD15 PAD9 FRXCLK FIN15 FIN9 FIN3 FTXCTL2 FOUT14 FOUT8 FOUT2 FOUT0 CP6_5 CP6_0 CP5_1 CP4_2 CP3_5 CP2_6 CP2_2 CP1_3 CP0_6 CP0_0
PCLK VDD33 PCBEX2 PAD28 PAD24 GND PAD14
PRSTX PSTOPX PCBEX3 VDD33 PAD23 PAD18 PAD13
PAD8
PAD7
PREQX GND PSERRX PAD27 PAD22 VDD33 PAD12 PAD6
PAD3 VDD33 FIN10 FIN4 FTXCTL6 GND FOUT9 FOUT3 FOUT1 VDD33 CP6_1 CP5_2
PAD2 FRXCTL0 FIN11 FIN5 FTXCLK FOUT15 FOUT10 FOUT4 CP7_3 CP6_6 CP6_2 CP5_3
CP4_3 GND CP3_0 CP2_3
CP4_4 CP3_6 CP3_1 VDD33
CP1_4 VDD33 CP0_1
CP1_5 CP1_0 CP0_2
TA13 TA14 TA15 VDDT TA16 TA17 TA18 TA19
GND FRXCTL1 FIN12 FIN6 FIN0
VDDT GND VDD GND VDD
VDD33 FOUT11 FOUT5 CP7_4 CP7_0
PINTA PIRDYX PPERRX
PTRDYX PCBEX0
SICL
TA20
VDDT
TA21
PAD31
PAD30
XPUHOT
GND PAD21 PAD17
PAD26 PAD20 PAD16
SIDA PIDSEL
GND SPDO
GND PFRAMEX PGNTX VDD33
SPDI
PAD11
PAD10
SPLD
PAD5
PAD4
SPCK
PAD1 FRXCTL2 FIN13 FIN7
PAD0 FRXCTL6 FIN14 FIN8
GND
GND VDD33 GND VDD33
VDD GND VDD
FIN1
FIN2
GND
FTXCTL0 FOUT12 FOUT6 CP7_5 CP7_1 CP6_3 CP5_5
FTXCTL1 FOUT13 FOUT7 CP7_6 CP7_2 CP6_4 CP5_6
GND
VDD
VDD33 GND VDD33
GND VDD GND
GND VDD33 MD5
VDD GND MD12
CP4_6 CP4_0 CP3_3
CP5_0
MD4
CP4_1 CP3_4
GND
MD11 MD10
MD3
MD9
GND
CP2_5
MD2
GND
GND VDD GND VDD GND
GND CP5_4
VDD33 MD19
CP4_5 VDD33 CP3_2
MD18 MD17 MD16
CP2_4
VDD33
CP1_6 GND
CP2_0 CP1_1
CP2_1 CP1_2
MD1
MD8
MD15
VDD33
MD7
MD14
CP0_3
CP0_4
CP0_5
MD0
MD6
MD13
TA7
TCE3X
GND
TA0
TPAR0
TD61
TPAR1
TD62
TD55
TD47
TD40
TD32
VDDT
TD48
TD41
TD33
TD26
TD19
TD12
TD6
GND
TD20
TD13
VDDT
QD0 QD5
QD1
QD2
QD3
QD4
QD6
GND
QD7
VDDT
QD8
2
3
TD0
QD9
QD10
4
TD1
5
TD2
6
TD3
7
TD4
GND QD17 QD22 QD25
QD14 QD18 VDDT QD26
8
QD30
QD31
9
TA8
TA1
TA9
TA2
TA10
TA3
VDDT
TA4
TA11
TA5
TA12
TA6
GND
VDDT
TPAR2
TD63
TD56
TD49
TD42
TD34
GND TPAR3 TCE0X TCE1X TCE2X GND
TCLKI TWE0X TWE1X TWE2X TWE3X VDDT
TD57
TD50
TD58
TD51
VDDT TD43
TD35 TD36
GND
TD52
TD44
TD37
TD59
TD53
TD45
TD38
TD60
TD54
TD46
TD39
GND
VDDT
GND
VDDT
TD28 TD29 TD27
TD21 GND TD22
VDDT
TD23
TD30
TD24
TD31
TD25
GND
VDDT
TD14
TD7
VDDT TD15
TD8 TD9
TD16
GND
TD17
TD10
TD18
TD11
GND
VDDT
GND
10
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
QACLKI QWEX
QA0
11
QA4
12
TD5 QACLKO QARDY QA3 QA9
QA10
13
QA14
QA15
14
CCLK3
15 16
SCLK SCLKX CCLK0
CCLK2 CCLK1
17
MA8
MA9
18
MA3
MA4
QA5 QA11 QA16 VDD33 JSE CPREF MA10 MA5
19 20
MBA1 MD118
21 22 23
MBA0 MD111 MD110 MD109 MD108
MD117 MD116 MD115
24
GND VDD
VDD GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD GND MD25
GND VDD33 MD33
MD24 VDD33 MD23
MD32 MD31 MD30
MD22
MD29
GND
VDD
GND
VDD
GND
VDD
VDD
GND
VDD
GND
VDD
GND
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
GND
VDD
GND
VDD
GND
VDD
VDD
GND
VDD
GND
VDD
GND
GND
VDD
GND
VDD
GND
VDD
VDD GND
GND VDD33
MD40
GND VDD33 MD48
VDD GND
GND VDD33
MD54
MD62
VDD GND MD69
MD77
MD39
MD47
MD53
MD61
MD68
MD76
MD38
MD46
GND
MD60
MD67
MD75
MD37
MD45
MD52
MD59
MD66
MD74
GND
MD44
MD51
MD58
VDD33
MD73
GND
VDD
GND
VDD
GND
VDD
VDD
GND
VDDT GND VDD33
VDD GND VDD GND
VDD GND
VDD33
VDD
GND
GND
VDD GND
VDD
GND
VDD33
GND
VDD33
GND
MD83
MD90
MD97
GND
MD82
MD89
VDD33
MD88
MD81
MD87
MD80
GND
MD96 MD95 MD94 VDD33
VDD33 GND VDD33 GND VDD33 MD103 MD102 GND MD101 MD100
MD107
GND
GND MD124 MD123 VDD33 MD122 MD121
25
MD21
26
GND
MD28 MD27
MD36
MD43
MD35
MD42
MD50
MD57
VDD33
MD56
MD65 MD64
MD72 MD71
MD79 GND
MD86 MD85
MD93 MD92
MD99 VDD33
MD106 MD105
27
MD20
MD26
MD34
MD41
MD49
MD55
MD63
MD70
MD78
MD84
MD91
MD98
MD104
MD114 MD113 MD112
MD120 GND MD119
QD11
QD12 QD15 QD20 GND
QD13
3
VDDT QD19 QD23
QD16 QD21
4 5
QD24
6
QD27 QDQPAR QDPL
QD28 QBCLKO QDPH VDDT
QD29
7
QA1
QBCLKI QNQRDY QA2
8 9 10
QA6 QA12 JSO0
QA7
QA8
11
GND
QA13
12
JSO1
JSO2
13
JTDO JSO5 JTDI MA11 MA6 MA0 MDECC7 MDECC8 MD129 MD128 VDD33 MD127 MD126 MD125
JSO3 JHIGHZ GND JTCK VDD33 MA1 MDECC1 MDECC2 GND MDECC3 MDECC4 MDECC5 VDD33 MDECC6
JSO4 JCLKBYPJTRSTX JTMS
14 15 16 17
MA7
18
MA2 MDQM MDQML MWEX MRASX MCASX
19 20 21 22 23 24
MCSX MDCLK MDECC0
25 26 27
C
B
A
E
D
V
U
T
R
M
L
P
N
K
J
H
G
F
AD
Y
W
AC
AB
AA
AG
AF
AE
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30 CHAPTER 2: SIGNAL DESCRIPTIONS
Pin Descriptions Grouped by Function
The C-3e NP pins are categorized in groups, reflecting interfaces to the chip:
•
•
•
Executive Processor System Interface Signals
•
Fabric Processor Interface Signals
•
•
•
QMU SRAM (Internal Mode) Interface Signals
•
QMU to Q-5 TMC (External Mode) Interface Signals
•
•
Pins conform to Joint Electronic Devices Engineering Council (JEDEC) standards.
LVTTL and LVPECL
Specifications
C-3e NP pins are the following types:
• Low Voltage TTL-Compatible (LVTTL). The C-3e NP’s LVTTL pins conform to the JEDEC
JESD8-B specification.
• Low Voltage Positive Emitter Coupled Logic (LVPECL).
All of the signals in the following tables in this chapter denote whether the individual signal is an Input (I), Output (O), both Input and Output (I/O), or power (P). In addition, a
PU, PD, and nc are used. The PU indicates that an internal resistor will pullup the pad if left unconnected. PD indicates an internal pulldown resistor. NC means the pad is to be left unconnected.
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Pin Descriptions Grouped by Function 31
Clock Signals
Table 6 describes the C-3e NP clock signals.
Table 6 Clock and Reference Signals
SIGNAL NAME
SCLK*
SCLKX*
CCLK0
CCLK1
CCLK2
CCLK3
CPREF†
PIN #
F14
F15
F16
E16
E15
E14
D16
TOTAL
1
1
1
1
1
1
1
TYPE
LVPECL
LVPECL
LVTTL
LVTTL
LVTTL
LVTTL
I
PD
I
PD
I
PD
I
PD
LVPECL I
PD
I
I
I/O SIGNAL DESCRIPTION
Core Clock Rate (Differential)
Programmable CP Clock Input
Programmable CP Clock Input
Programmable CP Clock Input
Programmable CP Clock Input
Reference
TOTAL 7
†
* SCLK and SCLKX must not be AC-coupled.
If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must be wired to an external reference, as specified in
Table 34 on page 73. If none of the CPs are configured for
LVPECL operation, then the CPREF pin can be left unconnected.
CP Interface Signals
The C-3e NP’s 8 external CPs support various network physical interfaces, providing a serial interface to the PHY layer. Interfaces are configured via bits in the C-3e NP register set. Many interfaces are possible by programming the configuration registers. CPs can be used individually or in a cluster (four CPs) to implement the various interfaces.
Table 7 provides a quick reference of all the CP pins organized by clusters. There are seven
physical I/O pins associated with each CP. All pins are capable of receiving data, with some configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can be configured as differential pairs for LVPECL compatibility.
In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four
CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for receive and four for transmit) or four CPs that share the transmit and receive functions for non-wire speed applications.
During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial
Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the
SDPs, with each getting access to the necessary I/O pins.
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32 CHAPTER 2: SIGNAL DESCRIPTIONS
Table 7 CP Physical Interface Signals and Pins (Grouped by Clusters)
CP CLUSTER 1
SIGNAL PIN #
CP0_0 AG27
CP0_1 AF27
CP0_2 AE27
CP0_3 AD27
CP0_4 AC27
CP0_5 AB27
CP0_6 AG26
CP1_0 AE26
CP1_1 AC26
CP1_2 AB26
CP1_3 AG25
CP1_4 AF25
CP1_5 AE25
CP1_6 AD25
CP2_0 AC25
CP2_1 AB25
CP2_2 AG24
CP2_3 AF24
CP2_4 AD24
CP2_5 AB24
CP2_6 AG23
CP3_0 AF23
CP3_1 AE23
CP3_2 AD23
CP3_3 AC23
CP3_4 AB23
CP3_5 AG22
CP3_6 AE22
CP CLUSTER 2
SIGNAL PIN #
CP4_0 AC22
CP4_1 AB22
CP4_2 AG21
CP4_3 AF21
CP4_4 AE21
CP4_5 AD21
CP4_6 AC21
CP5_0 AB21
CP5_1 AG20
CP5_2 AF20
CP5_3 AE20
CP5_4 AD20
CP5_5 AC20
CP5_6 AB20
CP6_0 AG19
CP6_1 AF19
CP6_2 AE19
CP6_3 AC19
CP6_4 AB19
CP6_5 AG18
CP6_6 AE18
CP7_0 AD18
CP7_1 AC18
CP7_2 AB18
CP7_3 AE17
CP7_4 AD17
CP7_5 AC17
CP7_6 AB17
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Pin Descriptions Grouped by Function 33
The signals for the following CP physical interfaces are included in this section:
•
DS1/T1 Framer Interface Configuration
•
10/100 Ethernet (RMII) Configuration
•
Gigabit Ethernet (GMII) Configuration
•
Gigabit Ethernet and Fibre Channel TBI Configuration
•
SONET OC-3 Transceiver Interface Configuration
•
SONET OC-12 Transceiver Interface Configuration
DS1/T1 Framer Interface Configuration
Table 8 describes the serial framer interface signals. For each CP (0-7), you can implement
one serial Framer interface.
Table 8 DS1/T1 Framer Interface Signals
SIGNAL NAME* PIN #† TOTAL TYPE
CP n _0
CP
CP
CP
CP
CP
CP n n n n n n
_1
_2
_3
_4
_5
_6
1
1
1
1
1
1
1
LVTTL
I/O
O
PD
LVTTL I
PU
LVTTL O
PD
LVTTL O
PU
LVTTL I
PD
LVTTL I
PU nc nc
PU
TOTAL PINS
7
LABEL
TCLK
RCLK
TData
TFrame
RData
RFrame nc
*
† n can be from 0 to 7. See
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
SIGNAL DESCRIPTION
Transmit Clock (1.544MHz)
Receive Clock (1.544MHz)
Transmit Data
Transmit Frame Synchronization
Receive Data
Receive Frame Synchronization nc
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34 CHAPTER 2: SIGNAL DESCRIPTIONS
CP n _2
CP n _3
CP n _4
CP n _5
CP n _6
1
1
1
1
1
10/100 Ethernet (RMII) Configuration
Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface
(RMII) signals. For each CP (0-7), you can implement one 10/100 Ethernet interface.
Table 9 10/100 Ethernet Signals
SIGNAL NAME* PIN #
CP
CP n n
_0
_1
1
1
TOTAL TYPE I/O
LVTTL O
PD
LVTTL I
PU
LVTTL O
PD
LVTTL O
PU
LVTTL I
PD
LVTTL I
PU
LVTTL O
PU
LABEL SIGNAL DESCRIPTION
REF_CLK Transmit and Receive Clock (50MHz)
CRS_DV Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that traffic is on the link, and is asserted if the signal is a 1 or an alternating 1010... RX_DV indicates that a receive frame is in progress and the data present on the RXD pins is valid. It is asserted if this signal is a 1 for more than one cycle.
TXD(0) Transmit Data 0 (first on wire)
TXD(1)
RXD(0)
RXD(1)
TX_EN
Transmit Data 1 (second on wire)
Receive Data 0 (first on wire)
Receive Data 1 (second on wire)
Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable.
TOTAL PINS
7
* n can be from 0 to 7. See
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Pin Descriptions Grouped by Function 35
Gigabit Ethernet (GMII) Configuration
Gigabit Ethernet Media Independent Interface (GMII) is configured in one of two ways:
•
Use one CP cluster when density is more important than wire-speed performance because you can then implement up to four Gigabit Ethernet ports per C-3e NP.
•
Use two CP clusters for wire-speed performance and additional processing power. You can implement up to two Gigabit Ethernet ports per C-3e NP.
Table 10 lists the possible CP cluster combinations you can use and Figure 4
shows receive
and transmit pin configurations by cluster. Table 11
lists the signals and pinouts for
Gigabit Ethernet (GMII).
Table 10 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel
CLUSTER SINGLE CLUSTER MODE (TBI OR GMII)
0 Port 1 Tx and Rx
1 Port 2 Tx and Rx
TWO CLUSTER MODE (GMII)*
Port 1 Tx
Port 1 Rx
* The Two Cluster Mode column lists typical configurations. Any cluster can be set up to either receive or transmit. So you could configure a dual cluster mode where cluster 0 receives and cluster 3 transmits.
Figure 4 GMII/TBI Transmit and Receive Pin Configurations
Single Cluster Mode
Pin Configuration
Two Cluster Mode
Pin Configuration
Cluster
0
Tx
Rx
}
Port 1 Cluster
0
Cluster
1
Tx
Rx
}
Port 2 Cluster
1
Tx
Rx nc
Tx nc
Rx
}
Port 1
Cluster
2
NOTE: Cluster 2 & 3 are Internal Loopback Only.
Cluster
3
Cluster
2
Cluster
3 nc = not connected
NOTE: Cluster 2 & 3 are Internal Loopback Only.
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36 CHAPTER 2: SIGNAL DESCRIPTIONS
Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example
SIGNAL NAME* PIN #† TOTAL TYPE I/O LABEL
CP n _0
1 LVTTL O
PD
T_CLK
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP n n n n n n
_1
_2
_3
_4
_5
_6 n+1 n+1 n+1 n+1 n+1 n+1 n+1 n+2 n+2 n+2 n+2 n+2 n+2 n+2 n+3
_0
_1
_2
_3
_4
_5
_6
_0
_1
_2
_3
_4
_5
_6
_0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LVTTL I
PU
LVTTL O
LVTTL O
LVTTL O
LVTTL O
LVTTL nc
O nc
PD
LVTTL I
PU
LVTTL O
LVTTL O
LVTTL O
LVTTL O
LVTTL nc nc
O nc
PD
PU
PD
PU
PU
PD
PU
PD
PU
PU nc
PD
LVTTL I
PU
LVTTL I
PD
LVTTL I
PU
LVTTL I
PD
LVTTL I
PU
LVTTL I
PU
PD
TCLKI
TXD(0)
TXD(1)
TXD(2)
TXD(3)
TX_EN nc
COL
TXD(4)
TXD(5)
TXD(6)
TXD(7)
TX_ER nc
RCLK
RXD(0)
RXD(1)
RXD(2)
RXD(3)
RX_DV nc
SIGNAL DESCRIPTION
GMII Transmit Clock (125MHz). This clock is used to synchronize the transmit data.
MII transmit clock. Transmit data aligned to this clock input from phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT
Transmit Data (byte-wide data, least significant bit)
Transmit Data
Transmit Data
Transmit Data
Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable.
nc
Collision. Asserted when both RX_DV and TX_EN are valid during half duplex operation.
Transmit Data
Transmit Data
Transmit Data
Transmit Data (byte-wide receive data, most significant bit)
Transmit Error. Asserting TX_ER when TX_EN is a 1 causes transmission of the designated “bad code” in lieu of the normal encoded data on the twisted pair data.
nc
Receive Clock (125MHz)
Receive Data (byte-wide receive data, least significant bit)
Receive Data
Receive Data
Receive Data
Receive Data Valid. Indicates that there is a receive frame in progress and that the data present on the RXD signals is valid.
nc
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Pin Descriptions Grouped by Function 37
Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)
SIGNAL NAME* PIN #† TOTAL TYPE I/O LABEL
CP n+3 _1
CP
CP
CP
CP
CP n+3 n+3 n+3 n+3 n+3
_2
_3
_4
_5
_6
1
1
1
1
1
1
LVTTL
LVTTL I
LVTTL I
LVTTL I
LVTTL I
LVTTL
I
I
PU
PD
PU
PD
PU
PU
CRS
RXD(4)
RXD(5)
RXD(6)
RXD(7)
RX_ER
SIGNAL DESCRIPTION
Carrier Sense. Indicates traffic is on the link. CRS is asserted when a non-idle condition is detected on the receive data stream. CRS is deasserted when an end of frame or idle condition is detected.
Receive Data
Receive Data
Receive Data
Receive Data (most significant bit)
Receive Error Detected. Indicates that there has been an error received in the receive frame.
TOTAL PINS
28
*
† n can be 0, or 4.
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
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38 CHAPTER 2: SIGNAL DESCRIPTIONS
CP n+1 _2
CP n+1 _3
CP n+1 _4
CP n+1 _5
CP n+1 _6
CP n+2 _0
CP n+2 _1
CP n+2 _2
CP n _1
CP n _2
CP n _3
CP n _4
CP n _5
CP n _6
CP n+1 _0
CP n+1 _1
CP n+2 _3
CP n+2 _4
CP n+2 _5
CP n+2 _6
CP n+3 _0
Gigabit Ethernet and Fibre Channel TBI Configuration
1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same
way as Gigabit Ethernet (GMII). Table 10
shows the possible CP pin combinations you can use and
Figure 4 shows receive and transmit pin configurations by cluster.
shows the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI.
The unused pins for the two cluster configurations should be wired down using a resistor.
Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example
SIGNAL NAME* PIN #† TOTAL TYPE
CP n _0
1 LVTTL
I/O
O
PD
LABEL
TCLK
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL nc
LVTTL
LVTTL nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL nc nc
LVTTL
LVTTL
LVTTL
LVTTL nc
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TXD(5)
TXD(4)
TXD(3)
TXD(2)
TXD(0) nc
RCLK
RXD(9) nc
TXD(9)
TXD(8)
TXD(7)
TXD(6)
TXD(1) nc nc
RXD(8)
RXD(7)
RXD(6)
RXD(1) nc
O
PU nc
PD
I
PU
I
PD
O
PD
O
PU
O
PD
O
PU
I
PU
I
PD
I
PU
I
PU nc
PD
O
PU
O
PU nc
PD nc
PU nc
PU
O
PD
O
PU
O
PD
SIGNAL DESCRIPTION
Transmit Clock (125MHz). This clock is used to synchronize the transmit data.
nc
Transmit Data (ten bits wide, last on wire)
Transmit Data
Transmit Data
Transmit Data
Transmit Data nc nc
Transmit Data
Transmit Data
Transmit Data
Transmit Data
Transmit Data (ten bits wide, first on wire) nc
Receive Clock (62.5 MHz)
Receive Data (ten bits wide, last on wire)
Receive Data
Receive Data
Receive Data
Receive Data nc
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Pin Descriptions Grouped by Function 39
Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)
SIGNAL NAME* PIN #† TOTAL TYPE
CP n+3 _1
1 LVTTL
CP n+3 _2
CP n+3 _3
1
1
LVTTL
LVTTL
CP n+3 _4
CP n+3 _5
CP n+3 _6
TOTAL PINS
1
1
1
28
LVTTL
LVTTL
LVTTL
I/O
I
PU
I
PD
I
PU
I
PD
I
PU
I
PU
LABEL
RCLKN
RXD(5)
RXD(4)
RXD(3)
RXD(2)
RXD(0)
*
† n can be 0, or 4.
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
SIGNAL DESCRIPTION
Receive Clock Inverted
Receive Data
Receive Data
Receive Data
Receive Data
Receive Data (ten bits wide, first on wire)
SONET OC-3 Transceiver Interface Configuration
Table 13 describes the SONET Optical Carrier (OC) 3 transceiver interface signals. For each
CP (0-15), you can implement a single OC-3 interface.
Table 13 OC-3 Signals
SIGNAL NAME* PIN #†
CP n _0
CP
CP
CP
CP
CP
CP n n n n n n
_1
_2
_3
_4
_5
_6
TOTAL TYPE
1
1
1
1
1
1
1
LVPECL I
I/O
PD
LVPECL I
PU
LVPECL O
PD
LVPECL O
PU
LVPECL I
PD
LVPECL I
PU
LVPECL I
PU
LABEL
RCLK_H
RCLK_L
TXD_H
SIGNAL DESCRIPTION
Receive Clock noninverted side of pair (155.52MHz)
Receive Clock inverted side of pair (155.52MHz)
Transmit Data noninverted side of pair
TXD_L
RXD_H
Transmit Data inverted side of pair
Receive Data noninverted side of pair
RXD_L Receive Data inverted side of pair
SIGNAL_DET A light level above a certain threshold is present at the optical receiver - single ended LVPECL.
TOTAL PINS
7
*
† n can be from 0 to 7.
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
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40 CHAPTER 2: SIGNAL DESCRIPTIONS
SONET OC-12 Transceiver Interface Configuration
SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a
CP within a cluster spends half its time performing receive functions, and the other half performing transmit functions.
Table 14 shows a CP Cluster configured for one OC-12
interface.
Table 14 OC-12 Signals Example
SIGNAL NAME* PIN #†
CP n _0
TOTAL TYPE
1 LVTTL
I/O
O
PD
LABEL
TCLK
CP n _1
CP n+1 _3
CP n+1 _4
CP n+1 _5
CP n+1 _6
CP n+2 _0
CP n+2 _1
CP n+2 _2
CP n+2 _3
CP n _2
CP n _3
CP n _4
CP n _5
CP n _6
CP n+1 _0
CP n+1 _1
CP n+1 _2
CP n+2 _4
CP n+2 _5
CP n+2 _6
CP n+3 _0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LVTTL I
PU
LVTTL O
PD
LVTTL O
PU
LVTTL O
PD
LVTTL O
PU
LVTTL O
PU nc nc
PD nc nc
PU
LVTTL O
PD
LVTTL O
PU
LVTTL O
PD
LVTTL O
PU nc nc
PU nc nc
PD
LVTTL I
PU
LVTTL I
PD
LVTTL I
PU
LVTTL I
PD
LVTTL I
PU
LVTTL I
PU nc nc
PD
TCLKI
TXD(5)
TXD(6)
TXD(7) nc nc
RCLK
RXD(0)
RXD(1)
TXD(0)
TXD(1)
TXD(2)
TXD(3)
OOF nc nc
TXD(4)
RXD(2)
RXD(3)
FP nc
SIGNAL DESCRIPTION
Deskewed Transmit Clock (77.76MHz). This clock is used to synchronize the transmit data.
Transceiver Transmit Clock. This clock sets the frequency of the transmit data and is typically sourced by the PHY chip.
Transmit Data (byte-wide data, least significant bit)
Transmit Data
Transmit Data
Transmit Data
Out of Frame nc nc
Transmit Data
Transmit Data
Transmit Data
Transmit Data (byte-wide data, most significant bit) nc nc
Receive Clock (77.76MHz)
Receive Data (byte-wide receive data, least significant bit)
Receive Data
Receive Data
Receive Data
Frame Synchronization Pulse. This is valid during the third A2 of the receive SONET frame.
nc
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Pin Descriptions Grouped by Function 41
Table 14 OC-12 Signals Example (continued)
SIGNAL NAME* PIN #†
CP n+3 _1
CP
CP
CP
CP
CP n+3 n+3 n+3 n+3 n+3
_2
_3
_4
_5
_6
TOTAL TYPE
1
1
1
1
1
1 nc
I/O nc
PU
LVTTL I
PD
LVTTL I
PU
LVTTL I
PD
LVTTL I
PU nc nc
PU
TOTAL PINS
28
*
† n can be 0, or 4.
Reference Table 7 for pin numbers for a different cluster.
LABEL nc
RXD(4)
RXD(5)
RXD(6)
RXD(7) nc
SIGNAL DESCRIPTION nc
Receive Data
Receive Data
Receive Data
Receive Data (most significant bit) nc
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42 CHAPTER 2: SIGNAL DESCRIPTIONS
Executive Processor
System Interface Signals
The XP’s system interface manages the supervisory controls for the network interfaces, as well as the set of pins that provide interfaces to other components in the system that are not memories or network interfaces. It is also the primary interface used for initializing the
C-3e NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM interface signals.
PFRAMEX
PTRDYX
PIRDYX
PSTOPX
PDEVSELX
PPERRX
PSERRX
PCLK
PRSTX
PREQX
PCI Signals
The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or
66MHz. The PCI is fully compliant with PCI Specification revision 2.1.
the PCI signals.
Table 15 PCI Signals
SIGNAL NAME
PAD0 - PAD31
PIN #
AB9, AC9, AE9, AF9, AB8, AC8,
AD8, AE8, AF8, AG8, AB7, AC7,
AD7, AE7, AF7, AG7, AB6, AC6,
AE6, AG6, AB5, AC5, AD5, AE5,
AF5, AG5, AB4, AD4, AF4, AG4,
AA3, AB3,
PCBEX0 - PCBEX3 AB2, AG3, AF3, AE3
TOTAL TYPE
32 PCI
4 PCI
I/O SIGNAL DESCRIPTION
I/O Multiplexed Address/Data Bus. These signals are multiplexed address and data bits. The C-3e NP receives addresses as target and drives addresses as master. It drives the data and receives read data as master.
PPAR AG1
AG2
AC3
AD3
AF1
AA7
AB1
AC2
AE2
AE1
AD1
1
1
1
1
1
1
1
1
1
1
1
PCI
PCI
PCI
PCI
I
PD
PCI
PCI
PCI
PCI
PCI
PCI
I/O Command byte enables. These signals are multiplexed command and byte enabled signals.
The C-3e NP receives byte enables as target and drives byte enables as master.
I/O Parity. This signal carries even parity for AD and CBE# pins. It has the same receive and drive characteristics as the address and data bus, except that it is one PCI cycle later.
I/O Cycle frame
I/O Target ready for data transfer
I/O Initiator ready for data transfer
I/O Target transaction stop request
I/O Target device selected
I/O Bus parity error
I
O
I
I/O System error
Bus clock
Bus reset
Initiator bus request (arbitration)
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Pin Descriptions Grouped by Function 43
Table 15 PCI Signals (continued)
SIGNAL NAME
PGNTX
PIDSEL
PINTA
TOTAL PINS
PIN #
AA8
AA5
AC1
TOTAL TYPE
1
1
I
PD
PCI
1
50
PCI
I
O
I
I/O SIGNAL DESCRIPTION
Initiator bus grant (arbitration)
Initialization device select
Interrupt (active low)
Serial Interface Signals
The Serial interface is a bidirectional two-wire serial bus. It can use one of the following formats:
•
An 8bit data format followed by an acknowledge bit, which supports transfers at up to
400kbps (low speed).
•
A 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports transfers up to 25MHz (high speed).
The signals and pins are identical for both the high and low speed protocols.
Which of the two data rates used is selected by the state of the PROM interface’s SPLD signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is selected.
The bus only supports a single master hierarchy that can operate as either a receiver or a transmitter.
Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism.
Table 16 Serial Interface Signals
SIGNAL NAME
SICL
SIDA
TOTAL PINS
PIN #
AA1
AA4
TOTAL TYPE
1
1
LVTTL I
I/O SIGNAL DESCRIPTION
PD
/O Serial Clock line
LVTTL I
PD
/O Serial Data line
2
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44 CHAPTER 2: SIGNAL DESCRIPTIONS
PROM Interface Signals
The PROM interface is a low speed I/O port that allows the C-3e NP to communicate through external logic to PROM. The PROM clock is 1 /
2
to 1 /
16
the core clock rate. The maximum PROM size addressable is 4MBytes, and must use a “by 16” part. The PROM signals are listed in
Table 17 PROM Interface Signals
SIGNAL
NAME
SPDO
SPDI
SPLD
PIN #
Y5
Y6
Y7
SPCK
TOTAL PINS
Y8 1
4
1
1
TOTAL TYPE I/O SIGNAL DESCRIPTION
1 LVTTL O Serial Data Out
LVTTL I
PD
LVTTL O
Serial Data In
When load is asserted on a positive clock edge, the external logic performs a parallel load. On each positive clock edge when load is de-asserted, the shift registers shift.
When the PROM interface is idle:
• if SPLD is asserted HI it indicates low speed serial protocol,
• if asserted LOW it indicates MDIO serial protocol.
LVTTL O Clock
shows the connections between the PROM Interface and external board logic.
The application is required to provide an external shift register with parallel-in and parallel-out capabilities, and a parallel load register. Both devices should be positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When
SPLD is deasserted the shift register shifts.
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Pin Descriptions Grouped by Function 45
Figure 5 PROM Interface Diagram
21
C-3e Network Processor
0
PROM_ADDR<21:1> CE
External Logic
SPDO
21
21
6
1
0
SPDI
21
Internal Shift
Register
15
31
16
PROM _H_Word
15
PROM _LO_Word
0
6 0
External Shift
Register
21
PROM_ADDR<21:1>
CE
0
21 1
PROM _Return_Data
PROM Clock Gen.
PROM Sequencer
SPCLK
SPLD
PROM
16
PROM_Data
The PROM interface operates in the following manner (Note that two accesses are
piplined together to execute one 32-bit fetch). The steps are shown in Figure 6
.
1 The PROM_ADDR is loaded into the network processor internal shift register.
2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.
3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register.
4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit PROM_DATA.
At the same time, the next PROM_ADDR is shifted into the external shift register.
5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register and the first PROM_DATA into the external shift register.
6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network processor internal shift register.
7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network processor PROM_RETURN_DATA register and the second PROM_DATA into the external shift register.
8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the network processor internal shift register.
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46 CHAPTER 2: SIGNAL DESCRIPTIONS
XP PROM Interface outline
`
SPLD
SPDTO A1
9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the network processor PROM_RETURN_DATA register.
Figure 6 PROM Interface Timing Outline
`
A2
`
A3
`
A4
`
A5
SPDTI D1 D2 D3
XP PROM Interface detail
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7
SPCLK
SPLD
SPDTO
A2 A3
1
A
20
A
19
A
18
A
17
A
16
A
15
A1
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
The PROM_ADDR is loaded into the
C-5's internal shift register.
The PROM_ADDR is shifted into the external shift register.
(SPCLK Rising Edge used for shifting)
2
A
2
A
1 CE
3 5
The PROM_ADDR is loaded into the external presentation register.
The PROM_DATA is presenting.
SPDTI
6 8
4
7
D
14
The PROM_DATA is loaded into the external shift register.
D1
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0 x x x x x x
The PROM_DATA is shifted into the C-5's
Internal shift register.
9
The PROM_DATA is loaded into the C-5's
internal PROM_RETURN_DATA register.
A4
D2
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Pin Descriptions Grouped by Function 47
General System Interface Signal
Table 18 provides the signal for the Executive Processor reset power status and I/O clock.
The C-3e NP can be powered up with the XP either running or with the XP in reset mode similar to the CPs. When the XP remains in reset mode, an external host can be used to control the initialization of the C-3e NP.
Table 18 General System Interface Signal
SIGNAL NAME
XPUHOT
PIN # TOTAL TYPE
Y3 1 LVTTL I
I/O
PD
SIGNAL DESCRIPTION
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low equals reset and High equals active. During normal operation, this is an external interrupt, triggered asynchronously on the rising edge of XPUHOT.
TOTAL PINS
1
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48 CHAPTER 2: SIGNAL DESCRIPTIONS
Fabric Processor Interface
Signals
The FP has logical signal interfaces: a receive data interface and a transmit data interface, each with its own control, data, and clock signals. The interface has the following characteristics:
•
The interface clocks, FRXCLK and FTXCLK can have a different frequency from the core
C-3e NP clock frequency. The FP supports a fabric interface frequency from 10MHz to
125MHz.
• FRXCLK and FTXCLK can be independent of each other; typically they have the same frequency, but are allowed to be skewed relative to each other.
• Each data bus can be configured for widths of 8 (data bits 7:0 are used), or 16 (bits
15:0). In 8bit mode, data bits 15:8 are unused.
Table 19 Fabric Interface Signals
SIGNAL NAME
FIN0 - FIN15
PIN #
AD13, AC13, AB13, AG12, AF12, AE12, AD12,
AC12, AB12, AG11, AF11, AE11, AD11, AC11,
AB11, AG10
FOUT0 - FOUT15
FRXCLK
FTXCLK
AG17, AF17, AG16, AF16, AE16, AD16, AC16,
AB16, AG15, AF15, AE15, AD15, AC15, AB15,
AG14, AE14
AG9
AE13
FRXCTL0 - FRXCTL2 &
FRXCTL6
AE10, AD10, AC10, AB10
FTXCTL0 - FRXCTL2 &
FTXCTL6
AC14, AB14, AG13, AF13
TOTAL PINS
1
1
4
TOTAL TYPE
16 LVTTL I
I/O
PD
16
4
42
LVTTL O
SIGNAL DESCRIPTION
Fabric Data Bus In
Fabric Data Bus Out
LVTTL I
PD
LVTTL I
PD
Receive Clock
Transmit Clock
LVTTL I
PD
, O Receive Control Signals
LVTTL I
PD
, O Transmit Control Signals
The following tables list the Fabric Interface pin mappings:
•
Utopia1, Utopia2, Utopia3 ATM Mode mappings are listed in
• Utopia1, Utopia2, Utopia3 PHY Mode mappings are listed in
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Pin Descriptions Grouped by Function 49
Table 20 Utopia1*, 2*, 3 ATM Mode, C-3e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
C-3e NETWORK
PROCESSOR
FRXCTL0
I/O
Output
UTOPIA
RxEnb*
NOTE
Pullup or No
Connection
FRXCTL1
FRXCTL2
FRXCTL6
Input
Input
Input
RxClav
RxSOC
RxPrty
* Cell size must be 4Byte aligned. Both RxEnb and TxEnb are Active Low.
TRANSMIT SIGNALS
C-3e NETWORK
PROCESSOR
FTXCTL0
I/O
Output
FTXCTL1
FTXCTL2
FTXCTL6
Input
Output
Output
UTOPIA
TxEnb*
TxClav
TxSOC
TxPrty
NOTE
Pullup or No
Connection
Table 21 Utopia1*, 2*, 3 PHY Mode, C-3e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
C-3e NETWORK
PROCESSOR
FRXCTL0
FRXCTL1
FRXCTL2
FRXCTL6
I/O
Input
Output
Input
Input
UTOPIA
TxEnb*
TxClav
TxSOC
TxPrty
NOTE
Pullup
* Cell size must be 4Byte aligned. Both TxEnb and RxEnb are Active Low.
TRANSMIT SIGNALS
C-3e NETWORK
PROCESSOR
FTXCTL0
No Connection FTXCTL1
FTXCTL2
FTXCTL6
I/O
Input
Output
Output
Output
UTOPIA
RxEnb*
RxClav
RxSOC
RxPrty
NOTE
Pullup
No Connection
When configuring two C-3e network processors back-to-back using the Fabric Port, set up the transmit side of each C-3e network processor in Utopia ATM mode and the receive side of each C-3e network processor in Utopia PHY mode.
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50 CHAPTER 2: SIGNAL DESCRIPTIONS
BMU SDRAM Interface
Signals
The BMU and SDRAM interface signals are described in
.
The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines and all 12 address lines must be connected to the SDRAM in order for the BMU to be able to read and write external SDRAM properly.
Table 22 BMU SDRAM Interface Signals
SIGNAL NAME
MD0 - MD129
PIN #
AA27, AA25, AA24, AA23, AA21,
AA20, Y27, Y26, Y25, Y23, Y22, Y21,
Y20, W27, W26, W25, W23, W22,
W21, W20, V27, V25, V24, V23, V21,
V20, U27, U26, U25, U24, U23, U22,
U21, U20, T27, T26, T25, T23, T22,
T21, T20, R27, R26, R25, R24, R23,
R22, R21, R20, P27, P25, P24, P23,
P21, P20, N27, N26, N25, N24, N23,
N22, N21, N20, M27, M26, M25,
M23, M22, M21, M20, L27, L26, L25,
L24, L23, L22, L21, L20, K27, K25,
K24, K23, K21, K20, J27, J26, J25,
J23, J22, J21, J20, H27, H26, H25,
H23, H22, H21, H20, G27, G25, G24,
G23, G21, G20, F27, F26, F25, F24,
F23, F22, F21, F20, E27, E26, E25,
E23, E22, E21, E20, D27, D25, D24,
D23, D21, D20, C27, C26, C25, C23,
C22
TOTAL TYPE
130
I/O SIGNAL DESCRIPTION
LVTTL I
PD
/O Data Lines
9 LVTTL I
PD
/O Stored as data, ECC bits MDECC0 - MDECC8 A27, B20, B21, B23, B24, B25, B27,
C20, C21
MA0 - MA11 C19, B19, A19, F18, E18, D18, C18,
A18, F17, E17, D17, C17
12 LVTTL O
PD
MBA0 - MBA1 F19, E19 2 LVTTL O
PD
Address Outputs: A0-A11 are sampled during the
ACTIVE command and READ/WRITE to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during a LOAD MODE REGISTER command
Bank Address Outputs: BA0 and BA1 define which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied
MCASX A24 1 LVTTL O
PD
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered.
NOTE: MCSX is considered part of the command code.
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Pin Descriptions Grouped by Function 51
Table 22 BMU SDRAM Interface Signals (continued)
SIGNAL NAME
MRASX
PIN #
A23
MWEX
MCSX
MDQM
MDQML
MDCLK
TOTAL PINS
A22
A25
A20
A21
A26
1
1
1
1
TOTAL TYPE
1 LVTTL
I/O
O
PD
1
LVTTL O
PD
LVTTL O
PD
LVTTL
LVTTL
LVTTL I
O
PD
O
PD
PD
SIGNAL DESCRIPTION
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX is considered part of the command code.
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX is considered part of the command code.
Chip Select: MCSX enables (registered LOW) and disables (registered HIGH) the command decoder.
All commands are masked when MCSX is registered HIGH. MCSX provides the external bank selection on systems with multiple banks. MCSX is considered part of the command code.
Input/Output Mask: MDQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when MDQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a high Z state (two-clock latency) when MDQM is sampled
HIGH during the READ cycle.
NOTE: MDQML is an identical copy of MDQM used to drive the loading on SDRAM configurations with 2 DQM pins.
Clock: MDCLK is driven by the system clock. All
SDRAM input signals are sampled on the positive edge of the MDCLK. MDCLK also increments the internal burst counter and controls the output registers.
160
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52 CHAPTER 2: SIGNAL DESCRIPTIONS
TLU SRAM Interface
Signals
The TLU SRAM interface supports up to 128MBytes of SRAM at frequencies to 125MHz using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to
64Mbits. The TLU SRAM interface signals are described in
Table 23 TLU SRAM Interface Signals
SIGNAL NAME
TD0 - TD63
TA0 - TA21
TPAR0 - TPAR3
TCE0X - TCE3X
TWE0X - TWE3X
TCLKI
TOTAL PINS
PIN #
F3, F4, F5, F6, F7, F8, G1, G3, G4, G5, G7, G8, H1, H2,
H3, H5, H6, H7, H8, J1, J2, J3, J5, J6, J7, J8, K1, K3,
K4, K5, K7, K8, L1, L2, L3, L4, L5, L6, L7, L8, M1, M2,
M3, M5, M6, M7, M8, N1, N2, N3, N4, N5, N6, N7,
N8, P1, P3, P4, P5, P7, P8, R1, R2, R3
U2, U3, U4, U5, U6, U7, U8, V1, V3, V4, V5, V7, V8,
W1, W2, W3, W5, W6, W7, W8, Y1, Y2
T1, T2, T3, T5
T6, T7, T8, U1
R5, R6, R7, R8
R4
TOTAL TYPE I/O SIGNAL DESCRIPTION
64 LVTTL I
PD
/O TLU Memory Data
22
4
4
4
1
99
LVTTL O
PD
TLU Memory Address
LVTTL I
PD
/O Word Data Parity (i.e. TPAR0 across
TD15:0)
LVTTL O
PD
LVTTL O
PD
LVTTL I
PD
TLU Memory Chip Enable
TLU Memory Write Enable
TLU Clock Input
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Pin Descriptions Grouped by Function 53
QMU SRAM (Internal
Mode) Interface Signals
The QMU signals are described in
Table 24 QMU SRAM (Internal Mode) Interface Signals
SIGNAL NAME
QA0 - QA16
QD0 - QD31
QDQPAR
QARDY
QNQRDY
QWEX
QBCLKO
QBCLKI
QACLKO
QACLKI
QDPL
QDPH
TOTAL PINS
PIN #
D10, C10, A10, F11, E11, D11, C11, B11, A11, F12,
E12, D12, C12, A12, F13, E13, D13
F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, B3, A3,
D4, B4, A4, E5, D5, C5, B5, A5, E6, C6, A6, E7, D7,
C7, B7, A7, E8, D8
32
B8
A8
F9
E9
C8
F10
A9
E10
C9
B9
TOTAL TYPE
17
1
1
1
1
1
1
1
1
1
1
59
LVTTL
LVTTL I
I/O
O
PD
LVTTL I
PD
LVTTL I
PD
LVTTL O
LVTTL I
PD
LVTTL O
LVTTL I
PD
SIGNAL DESCRIPTION
Address [16:0]
/O Data nc nc
LVTTL I
PD nc
LVTTL O Write Enable nc nc nc
Input Clock (drives QMU and external SRAM)
LVTTL I
PD
/O Data Parity Low
LVTTL I
PD
/O Data Parity High
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54 CHAPTER 2: SIGNAL DESCRIPTIONS
QMU to Q-5 TMC (External
Mode) Interface Signals
The QMU to Q-5 TMC signals are described in Table 25
.
QD24 - QD31
QDQPAR
QARDY
QNQRDY
QWEX
QBCLKO
QBCLKI
QACLKO
QACLKI
QDPL
QDPH
TOTAL PINS
Table 25 QMU to Q-5 (External Mode) Interface Signals
SIGNAL NAME
QA0 - QA15
QA16
QD0 - QD23
PIN #
D10, C10, A10, F11, E11, D11, C11, B11, A11,
F12, E12, D12, C12, A12, F13, E13
E9
C9
B9
D13
F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3,
B3, A3, D4, B4, A4, E5, D5, C5, B5, A5, E6, C6
E10
B8
A8
F9
A6, E7, D7, C7, B7, A7, E8, D8
C8
F10
A9
TOTAL TYPE
16 LVTTL
I/O
O
1
24
8
1
1
1
1
1
1
1
1
1
1
59
LVTTL
LVTTL I
O
PD
LVTTL I
PD
LVTTL I
PD
LVTTL I
PD
LVTTL O
LVTTL O
LVTTL O
LVTTL I
PD
LVTTL O
LVTTL I
PD
LVTTL O
LVTTL O
SIGNAL DESCRIPTION
Enqueue Data [8:23]
Enqueue Parity
Dequeue Data [0:23]
Enqueue Data [0:7]
Dequeue Parity
Dequeue Ack Ready
Enqueue Ready
Dequeue Ready
Output ClockB
Input ClockB
Output ClockA
Input ClockA
Dequeue Ack [0]
Dequeue Ack [1]
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Pin Descriptions Grouped by Function 55
Power Supply Signals
Power supply and ground signals are described in Table 26 .
Table 26 Power Supply Signals
SIGNAL NAME
VDD
VDD33
GND
VDDT
TOTAL PINS
PIN # TOTAL
H10, H12, H16, J11, J13, J15, J17, K10, K12, K14, K16,
K18, L11, L13, L15, L17, M10, M12, M14, M16, M18,
N11, N13, N15, N17, P10, P12, P14, P16, P18, R11,
R13, R15, R17, T10, T12, T14, T16, T18, U11, U13, U15,
U17, V10, V12, V14, V16, V18, W11, W13, W15, W17,
Y10, Y12, Y14, Y16, Y18
57
B18, B26, C24, D14, D22, G13, G15, G17, G19, G26,
H14, H18, H24, J19, K22, L19, M24, N19, P26, R19,
U19, V22, W19, W24, AA9, AA11, AA13, AA15, AA17,
AA19, AA26, AD6, AD14, AD22, AE4, AE24, AF2,
AF10, AF18, AF26
40
B6, B12, B16, B22, D2, D9, D19, D26, E4, E24, G6, G10,
G12, G14, G16, G18, G22, H9, H11, H13, H15, H17,
H19, J4, J10, J12, J14, J16, J18, J24, K2, K9, K11, K13,
K15, K17, K19, K26, L10, L12, L14, L16, L18, M9, M11,
M13, M15, M17, M19, N10, N12, N14, N16, N18, P6,
P9, P11, P13, P15, P17, P19, P22, R10, R12, R14, R16,
R18, T4, T9, T11, T13, T15, T17, T19, T24, U10, U12,
U14, U16, U18, V2, V9, V11, V13, V15, V17, V19, V26,
W10, W12, W14, W16, W18, Y4, Y9, Y11, Y13, Y15,
Y17, Y19, Y24, AA6, AA10, AA12, AA14, AA16, AA18,
AA22, AC4, AC24, AD2, AD9, AD19, AD26, AF6, AF14,
AF22
117
B2, B10, C4, D6, G2, G9, G11, H4, J9, K6, L9, M4, N9,
P2, R9, U9, V6, W4, W9, AA2
20
234
TYPE
P
P
P
P
SIGNAL DESCRIPTION
Core Supply Voltage (1.1V Input)
I/O Supply Voltage (3.3V Input)
Ground
TLU and QMU I/O supply (3.3V)
V 03
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56 CHAPTER 2: SIGNAL DESCRIPTIONS
Test Signals
Test signals are described in
Table 27 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
SIGNAL NAME
JTCK
JTMS
PIN #
B17
A17
JTRSTX
JTDI
JTDO
JHIGHZ
JCLKBYP
JSE
JS00-JS05
TOTAL PINS
A16
C16
C14
B15
A15
D15
C13, B13, A13, B14, A14, C15
1
6
14
1
1
1
1
TOTAL TYPE
1
1
LVTTL I
I/O SIGNAL DESCRIPTION
PD
LVTTL I
PD
Test Clock
Test Mode Select. High selects modes as defined in the IEEE 1149.1 JTAG specification.
1
LVTTL
LVTTL I
I
PD
PD
LVTTL O
LVTTL I
PD
LVTTL I
PD
Test Reset (low active)
Test Data In
Test Data Out
Turns off all output drivers when High
1X or 2X Clock Mode Select. Low selects 1X, High selects 2X. Motorola recommends using 1X mode
(pulldown or leave JCLKBYP unconnected).
LVTTL I
PD
LVTTL O
Scan Enable. High enables scan test.
Scan Out Pins
During JTAG, SCLK and SCLKX must remain as differential inputs.
C3EN
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Signals Grouped by Pin Number 57
Signals Grouped by Pin
Number
The C-3e NP signals are listed by pin number in Table 28 .
Table 28 Signals Listed by Pin Number
PIN FUNCTION PIN
C5
C6
C7
C8
C1
C2
C3
C4
B5
B6
B7
B8
B1
B2
B3
B4
A5
A6
A7
A8
A1
A2
A3
A4
Not present A9
QD8
QD13
QD16
QD21
QD24
QD29
QBCLKI
QD4
VDDT
QD12
QD15
QD20
GND
QD28
QBCLKO
QD3
QD7
QD11
VDDT
QD19
QD23
QD27
QDQPAR
A10
A11
A12
A13
A14
A15
A16
B9
B10
B11
B12
B13
B14
B15
B16
C9
C10
C11
C12
C13
C14
C15
C16
QDPH
VDDT
QA7
GND
JS01
JS03
JHIGHZ
GND
QDPL
QA1
QA6
QA12
JS00
JTDO
JS05
JTDI
QNQRDY
QA2
QA8
QA13
JS02
JS04
JCLKBYP
JTRSTX
FUNCTION PIN
A 1-27
A17
A18
A19
A20
A21
A22
A23
A24
C 1-27
C17
C18
C19
C20
C21
C22
C23
C24
B 1-27
B17
B18
B19
B20
B21
B22
B23
B24
FUNCTION
MA11
MA6
MA0
MDECC7
MDECC8
MD129
MD128
VDD33
JTCK
VDD33
MA1
MDECC1
MDECC2
GND
MDECC3
MDECC4
JTMS
MA7
MA2
MDQM
MDQML
MWEX
MRASX
MCASX
PIN
A25
A26
A27
B25
B26
B27
C25
C26
C27
FUNCTION
MCSX
MDCLK
MDECC0
MDECC5
VDD33
MDECC6
MD127
MD126
MD125
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58 CHAPTER 2: SIGNAL DESCRIPTIONS
Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN
F5
F6
F7
F8
F1
F2
F3
F4
E5
E6
E7
E8
E1
E2
E3
E4
D5
D6
D7
D8
D1
D2
D3
D4
QD2
GND
QD10
QD14
QD18
VDDT
QD26
QD31
QD1
QD6
QD9
GND
QD17
QD22
QD25
QD30
QD0
QD5
TD0
TD1
TD2
TD3
TD4
TD5
D9
D10
D11
D12
D13
D14
D15
D16
E9
E10
E11
E12
E13
E14
E15
E16
F9
F10
F11
F12
F13
F14
F15
F16
QACLKI
QWEX
QA4
QA10
QA15
CCLK3
CCLK2
CCLK1
QACLKO
QARDY
QA3
QA9
QA14
SCLK
SCLKX
CCLK0
GND
QA0
QA5
QA11
QA16
VDD33
JSE
CPREF
FUNCTION PIN
D 1-27
D17
D18
D19
D20
D21
D22
D23
D24
F 1-27
F17
F18
F19
F20
F21
F22
F23
F24
E 1-27
E17
E18
E19
E20
E21
E22
E23
E24
FUNCTION PIN
MA10
MA5
GND
MD124
MD123
VDD33
MD122
MD121
MA9
MA4
MBA1
MD118
MD117
MD116
MD115
GND
MA8
MA3
MBA0
MD111
MD110
MD109
MD108
MD107
D25
D26
D27
E25
E26
E27
F25
F26
F27
FUNCTION
MD120
GND
MD119
MD114
MD113
MD112
MD106
MD105
MD104
C3EN
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Signals Grouped by Pin Number 59
Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN
J5
J6
J7
J8
J1
J2
J3
J4
H5
H6
H7
H8
H1
H2
H3
H4
G5
G6
G7
G8
G1
G2
G3
G4
TD6
VDDT
TD7
TD8
TD9
GND
TD10
TD11
TD12
TD13
TD14
VDDT
TD15
TD16
TD17
TD18
TD19
TD20
TD21
GND
TD22
TD23
TD24
TD25
G9
G10
G11
G12
G13
G14
G15
G16
H9
H10
H11
H12
H13
H14
H15
H16
J9
J10
J11
J12
J13
J14
J15
J16
GND
VDD
GND
VDD
GND
VDD33
GND
VDD
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
VDDT
GND
VDDT
GND
VDD33
GND
VDD33
GND
FUNCTION PIN
G 1-27
G17
G18
G19
G20
G21
G22
G23
G24
J 1-27
J17
J18
J19
J20
J21
J22
J23
J24
H 1-27
H17
H18
H19
H20
H21
H22
H23
H24
FUNCTION PIN
VDD33
GND
VDD33
MD103
MD102
GND
MD101
MD100
GND
VDD33
GND
MD97
MD96
MD95
MD94
VDD33
VDD
GND
VDD33
MD90
MD89
MD88
MD87
GND
G25
G26
G27
H25
H26
H27
J25
J26
J27
FUNCTION
MD99
VDD33
MD98
MD93
MD92
MD91
MD86
MD85
MD84
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60 CHAPTER 2: SIGNAL DESCRIPTIONS
Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN
M5
M6
M7
M8
M1
M2
M3
M4
L5
L6
L7
L8
L1
L2
L3
L4
K5
K6
K7
K8
K1
K2
K3
K4
TD26
GND
TD27
TD28
TD29
VDDT
TD30
TD31
TD32
TD33
TD34
TD35
TD36
TD37
TD38
TD39
TD40
TD41
TD42
VDDT
TD43
TD44
TD45
TD46
K9
K10
K11
K12
K13
K14
K15
K16
L9
L10
L11
L12
L13
L14
L15
L16
M9
M10
M11
M12
M13
M14
M15
M16
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
FUNCTION PIN
K 1-27
K17
K18
K19
K20
K21
K22
K23
K24
M 1-27
M17
M18
M19
M20
M21
M22
M23
M24
L 1-27
L17
L18
L19
L20
L21
L22
L23
L24
FUNCTION PIN
GND
VDD
GND
MD83
MD82
VDD33
MD81
MD80
VDD
GND
VDD33
MD77
MD76
MD75
MD74
MD73
GND
VDD
GND
MD69
MD68
MD67
MD66
VDD33
K25
K26
K27
L25
L26
L27
M25
M26
M27
FUNCTION
MD79
GND
MD78
MD72
MD71
MD70
MD65
MD64
MD63
C3EN
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Signals Grouped by Pin Number 61
Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN
R5
R6
R7
R8
R1
R2
R3
R4
P5
P6
P7
P8
P1
P2
P3
P4
N5
N6
N7
N8
N1
N2
N3
N4
TD47
TD48
TD49
TD50
TD51
TD52
TD53
TD54
TD55
VDDT
TD56
TD57
TD58
GND
TD59
TD60
TD61
TD62
TD63
TCLKI
TWE0X
TWE1X
TWE2X
TWE3X
N9
N10
N11
N12
N13
N14
N15
N16
P9
P10
P11
P12
P13
P14
P15
P16
R9
R10
R11
R12
R13
R14
R15
R16
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
FUNCTION PIN
N 1-27
N17
N18
N19
N20
N21
N22
N23
N24
R 1-27
R17
R18
R19
R20
R21
R22
R23
R24
P 1-27
P17
P18
P19
P20
P21
P22
P23
P24
FUNCTION PIN
VDD
GND
VDD33
MD62
MD61
MD60
MD59
MD58
GND
VDD
GND
MD54
MD53
GND
MD52
MD51
VDD
GND
VDD33
MD48
MD47
MD46
MD45
MD44
N25
N26
N27
P25
P26
P27
R25
R26
R27
FUNCTION
MD57
MD56
MD55
MD50
VDD33
MD49
MD43
MD42
MD41
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62 CHAPTER 2: SIGNAL DESCRIPTIONS
Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN
V5
V6
V7
V8
V1
V2
V3
V4
U5
U6
U7
U8
U1
U2
U3
U4
T5
T6
T7
T8
T1
T2
T3
T4
TPAR0
TPAR1
TPAR2
GND
TPAR3
TCE0X
TCE1X
TCE2X
TCE3X
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TA7
GND
TA8
TA9
TA10
VDDT
TA11
TA12
T9
T10
T11
T12
T13
T14
T15
T16
U9
U10
U11
U12
U13
U14
U15
U16
V9
V10
V11
V12
V13
V14
V15
V16
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
FUNCTION PIN
T 1-27
T17
T18
T19
T20
T21
T22
T23
T24
V 1-27
V17
V18
V19
V20
V21
V22
V23
V24
U 1-27
U17
U18
U19
U20
U21
U22
U23
U24
FUNCTION PIN
GND
VDD
GND
MD40
MD39
MD38
MD37
GND
VDD
GND
VDD33
MD33
MD32
MD31
MD30
MD29
GND
VDD
GND
MD25
MD24
VDD33
MD23
MD22
T25
T26
T27
U25
U26
U27
V25
V26
V27
FUNCTION
MD36
MD35
MD34
MD28
MD27
MD26
MD21
GND
MD20
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Signals Grouped by Pin Number 63
Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION
AA5
AA6
AA7
AA8
AA1
AA2
AA3
AA4
Y5
Y6
Y7
Y8
Y1
Y2
Y3
Y4
W5
W6
W7
W8
W1
W2
W3
W4
TA13
TA14
TA15
VDDT
TA16
TA17
TA18
TA19
TA20
TA21
XPUHOT
GND
SPDO
SPDI
SPLD
SPCK
SICL
VDDT
PAD30
SIDA
PIDSEL
GND
PFRAMEX
PGNTX
W9
W10
W11
W12
W13
W14
W15
W16
Y13
Y14
Y15
Y16
Y9
Y10
Y11
Y12
PIN
AA9 VDD33
AA10 GND
AA11 VDD33
AA12 GND
AA13 VDD33
AA14 GND
AA15 VDD33
AA16 GND
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDDT
GND
VDD
GND
VDD
GND
VDD
GND
FUNCTION PIN
W 1-27
W17
W18
W19
W20
W21
W22
W23
W24
FUNCTION
Y 1-27
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
AA 1-27
AA17 VDD33
AA18 GND
AA19 VDD33
AA20 MD5
AA21 MD4
AA22 GND
AA23 MD3
AA24 MD2
GND
VDD
GND
MD12
MD11
MD10
MD9
GND
VDD
GND
VDD33
MD19
MD18
MD17
MD16
VDD33
PIN
W25
W26
W27
Y25
Y26
Y27
FUNCTION
MD15
MD14
MD13
MD8
MD7
MD6
AA25 MD1
AA26 VDD33
AA27 MD0
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64 CHAPTER 2: SIGNAL DESCRIPTIONS
Table 28 Signals Listed by Pin Number (continued)
PIN
AD5
AD6
AD7
AD8
AD1
AD2
AD3
AD4
AC5
AC6
AC7
AC8
AC1
AC2
AC3
AC4
AB5
AB6
AB7
AB8
AB1
AB2
AB3
AB4
FUNCTION
PTRDYX
PCBEX0
PAD31
PAD26
PAD20
PAD16
PAD10
PAD4
PINTA
PIRDYX
PPERRX
GND
PAD21
PAD17
PAD11
PAD5
PREQX
GND
PSERRX
PAD27
PAD22
VDD33
PAD12
PAD6
PIN FUNCTION PIN FUNCTION
AB9 PAD0
AB10 FRXCTL6
AB11 FIN14
AB12 FIN8
AB13 FIN2
AB14 FTXCTL1
AB15 FOUT13
AB16 FOUT7
AB 1-27
AB17 CP7_6
AB18 CP7_2
AB19 CP6_4
AB20 CP5_6
AB21 CP5_0
AB22 CP4_1
AB23 CP3_4
AB24 CP2_5
AC9 PAD1
AC10 FRXCTL2
AC11 FIN13
AC12 FIN7
AC13 FIN1
AC14 FTXCTL0
AC15 FOUT12
AC16 FOUT6
AC 1-27
AC17 CP7_5
AC18 CP7_1
AC19 CP6_3
AC20 CP5_5
AC21 CP4_6
AC22 CP4_0
AC23 CP3_3
AC24 GND
AD9 GND
AD10 FRXCTL1
AD11 FIN12
AD12 FIN6
AD13 FIN0
AD14 VDD33
AD15 FOUT11
AD16 FOUT5
AD 1-27
AD17 CP7_4
AD18 CP7_0
AD19 GND
AD20 CP5_4
AD21 CP4_5
AD22 VDD33
AD23 CP3_2
AD24 CP2_4
PIN FUNCTION
AB25 CP2_1
AB26 CP1_2
AB27 CP0_5
AC25 CP2_0
AC26 CP1_1
AC27 CP0_4
AD25 CP1_6
AD26 GND
AD27 CP0_3
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Signals Grouped by Pin Number 65
Table 28 Signals Listed by Pin Number (continued)
PIN
AG5
AG6
AG7
AG8
AG1
AG2
AG3
AG4
AF5
AF6
AF7
AF8
AF1
AF2
AF3
AF4
AE5
AE6
AE7
AE8
AE1
AE2
AE3
AE4
FUNCTION
PRSTX
PSTOPX
PCBEX3
VDD33
PAD23
PAD18
PAD13
PAD7
PCLK
VDD33
PCBEX2
PAD28
PAD24
GND
PAD14
PAD8
PPAR
PDEVSELX
PCBEX1
PAD29
PAD25
PAD19
PAD15
PAD9
PIN
AE9 PAD2
AE10 FRXCTL0
AE11 FIN11
AE12 FIN5
AE13 FTXCLK
AE14 FOUT15
AE15 FOUT10
AE16 FOUT4
FUNCTION PIN FUNCTION
AE 1-27
AE17 CP7_3
AE18 CP6_6
AE19 CP6_2
AE20 CP5_3
AE21 CP4_4
AE22 CP3_6
AE23 CP3_1
AE24 VDD33
AF9 PAD3
AF10 VDD33
AF11 FIN10
AF12 FIN4
AF13 FTXCTL6
AF14 GND
AF15 FOUT9
AF16 FOUT3
AF 1-27
AF17 FOUT1
AF18 VDD33
AF19 CP6_1
AF20 CP5_2
AF21 CP4_3
AF22 GND
AF23 CP3_0
AF24 CP2_3
AG9 FRXCLK
AG10 FIN15
AG11 FIN9
AG12 FIN3
AG13 FTXCTL2
AG14 FOUT14
AG15 FOUT8
AG16 FOUT2
AG 1-27
AG17 FOUT0
AG18 CP6_5
AG19 CP6_0
AG20 CP5_1
AG21 CP4_2
AG22 CP3_5
AG23 CP2_6
AG24 CP2_2
PIN FUNCTION
AE25 CP1_5
AE26 CP1_0
AE27 CP0_2
AF25 CP1_4
AF26 VDD33
AF27 CP0_1
AG25 CP1_3
AG26 CP0_6
AG27 CP0_0
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66 CHAPTER 2: SIGNAL DESCRIPTIONS
JTAG Support
The C-3e NP contains Joint Test Action Group (JTAG) test logic compliant with the IEEE
1149.1 specification. All required public instructions are implemented, as well as some optional instructions. This section contains information regarding the pinout, instructions, identification codes, and boundary scan cell types.
Pinout
The C-3e NP uses the standard JTAG pins including the optional test reset pin.
describes the pins and their functions.
JTAG Data Registers
The C-3e NP contains the standard internal registers as specified in IEEE 1149.1. These registers are described in
Table 29 JTAG Internal Register Descriptions
REGISTER NAME
Bypass
Boundary
Device Identification
REGISTER LENGTH
1
1549
32
DESCRIPTION
Standard JTAG bypass register
Boundary Scan Register
Standard JTAG IDCODE Register
Boundary Scan Restriction
SCLK/SCLKX inputs must not toggle when exercising the boundary scan function for
JTAG.
Boundary Scan Cell Types
The C-3e NP boundary scan register contains only two cell types. All input cells are observe only cells of type BC_4. All enable and output cells are standard cells of type BC_1. In IEEE
1149.1-1990 specification, the BC_4 cell is shown in Figure 7
and the BC_1 cell is shown in
.
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JTAG Support 67
Figure 7 Observe-Only Cell
From System Pin
G1
0
1
1D
C1
To next cell
To System Logic
Figure 8 Cell Design That Can Be Used for Both Input and Output Pins
Node
To next cell
Shift DR
G1
To/From
System Pin
0
1
G1
0
1
From last cell Clock DR
1D
C1
1D
C1
Update DR
From/To
System
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68 CHAPTER 2: SIGNAL DESCRIPTIONS
IDcode Register
The C-3e NP implements a standard 32bit JTAG identification register.
value of the code for full identification and its sub-components.
Table 30 JTAG Identification Code and Its Sub-components
FIELD NAME
Version
Part Number
Manufacturer Identity
LSB
WIDTH
4
16
11
1
BIT POSITIONS
31-28
27-12
11-1
0
BINARY VALUE
0000
0000_0000_0010_0010
001_1001_0110
1
The concatenated 32bit value is hexidecimal 0002232d.
JTAG Instruction Register
The C-3e NP contains a 4bit instruction register. Table 31 lists the instructions that are
supported.
Table 31 Instruction Register Instructions
INSTRUCTION MNEMONIC SELECTED REGISTER
Extest Boundary Scan
Idcode
Sample/Preload
Identification Register
Boundary Scan
INSTRUCTION OPCODE
0000
0001
0010
Highz
Clamp
Bypass
Reserved*
Bypass Register
Bypass Register
Bypass Register
Bypass Register
0011
0100
0101
0110
Reserved*
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass Register
Bypass Register
Bypass Register
Bypass Register
Bypass Register
Bypass Register
Bypass Register
0111
1000
1001
1010
1011
1100
1101
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JTAG Support 69
Table 31 Instruction Register Instructions (continued)
INSTRUCTION MNEMONIC SELECTED REGISTER
Bypass Bypass Register
Bypass Bypass Register
INSTRUCTION OPCODE
1110
1111
* There are two reserved instructions intended for Motorola Corporation’s internal use. These should not be programmed by users.
Boundary Scan
Description Language
In order to simplify board test, Motorola Corporation has provided a boundary scan description language (BSDL) file (c3e.bsdl) in the Motorola web site that describes the complete set of instructions, boundary scan order, and identification code value in an industry standard format. http://www.motorola.com/networkprocessors
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70 CHAPTER 2: SIGNAL DESCRIPTIONS
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ELECTRICAL SPECIFICATIONS
Absolute Maximum
Ratings
Table 32 lists the absolute maximum ratings for the C-3e network processor. Stresses
beyond those listed may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under
“ Recommended Operating Conditions ” ( Table 33 ) is possible.
Exposure to conditions beyond
• Reduce device reliability
• Result in premature device failure, even with no immediate sign of failure
Prolonged exposure to conditions at or near the absolute maximum ratings could also result in reduced useful life and reliability of the C-3e NP.
Table 32 C-3e Network Processor Absolute Maximum Ratings
PARAMETER
V
DD33/VDDT
Supply Voltage (3.3V input)*
V
DD
Voltage on any pin
Static Discharge Voltage
Storage Temperature
Absolute Maximum Junction Temperature
MIN
-0.5
-0.5
-0.5
2000/200‡
-40
-40
‡
†
* Voltages are relative to Ground
5.5V allowed on PCI pins (pin name beginning with letter “P”)
HBM/MM
MAX
+5
+2.2
V
DD33
+ 0.5†
+125
+125
V
°C
°C
V
V
UNIT
V
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72 CHAPTER 3: ELECTRICAL SPECIFICATIONS
Recommended Operating
Conditions
The recommended operating conditions describe an environment the C-3e NP network processor is expected to encounter during normal operation.
delineates the recommended operating parameters for the C-3e NP.
Table 33 C-3e Network Processor Recommended Operating Conditions
PARAMETER
V
DD33
Supply Voltage
V
DDT
Supply Voltage
V
DD
Supply Voltage
I
DD33
(V
DD33
Supply Current)
I
DDT
(V
DDT
Supply Current)
I
DD
(V
DD
Supply Current)
T j
Junction Temperature
MIN
3.135
3.135
1.14
-40
NOMINAL MAX
3.3
3.465
UNIT
V
3.3
1.2
3.465
1.26
V
V
0.4
0.2
5.0
125
A
A
A
°C
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DC Characteristics
DC Characteristics 73
The DC electrical characteristics define the input operating conditions for proper operation and the output responses to applied DC signals and switch characteristics over specified voltage and temperature ranges. The DC electrical characteristics are specified within the recommended operating conditions including operating temperature and power
supply range as stated in this data sheet. Table 34 outlines the C-3e NP DC characteristics.
Table 34 C-3e Network Processor DC Characteristics
PARAMETER*
LVTTL Input High Voltage
LVTTL Input High Voltage
(PCI pins)
LVTTL Input Low Voltage
MIN
2.0
2.0
MAX
V
DD33
+.3
5.5
UNIT NOTES
V
V PCI pins begin with letter “P” in pin name.
-0.3
0.8
V
LVTTL Output High Voltage
LVTTL Output Low Voltage
LVTTL Input Current
2.4
-150
0.4
+150
LVPECL Input High Voltage V
DD33
-1.165
V
DD33
+.3V
LVPECL Input Low Voltage -0.3
V
V
DD33
-1.475
V
LVPECL Output High Voltage V
DD33
-1.025
V
DD33
-0.60
V
LVPECL Output Low Voltage V
DD33
-2.20
V
DD33
-1.620
V
LVPECL Input Current -100 +100
µ
A
V @I
OH
= -2mA
V @I
OL
= +2mA
µ
A V
IN
= 0V or V
DD33
†
Load = 50ohm to V
Load = 50ohm to V
DD33
DD33
- 2V
- 2V
CPREF V
DD33
-1.38
V
DD33
-1.26
V Single-ended LVPECL reference
*
†
All voltages are relative to Ground unless otherwise indicated.
Reflects current due to pullup/pulldown internal resistors.
Each control input pin has a capacitance associated with it. The capacitance at the control input is due to the package and the input circuitry connected to the pin. Capacitance is based on these conditions: T
A
= 25 °C ; V
DD33 capacitance data.
= 3.3V; f = 1MHz. Table 35 provides
Table 35 C-3e Network Processor Capacitance Data
PARAMETER
All Pins
TYPICAL
5
UNIT pF
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74 CHAPTER 3: ELECTRICAL SPECIFICATIONS
Power Sequencing
It is intended that the VDD33/VDDT and VDD rails are sequenced to their final value together. VDD33, VDDT and VDDF must be above VDD at all times to prevent internal parasitic diodes from turning on and possibly damaging the device. VDD must be brought to its final value within 100ms of sequencing on VDD33, VDDT and VDDF. During this
100ms, significant current may be drawn by the three IO supplies (up to 30A total) until
VDD is asserted to reset the IO drivers. To minimize this current draw during power-on, it is recommended that this sequencing time be minimized in the power supply design.
It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running
or begin running during power sequencing to propagate reset inside the C-3e NP. Figure 9
indicates the relationship between the clocks and PRSTX. There is no requirement that the asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be asserted within 100
µ s of power initiation. Typically, reset is held low during power initiation.
Figure 9 Bringup Clock Timing Diagram
VDD, VDD33,
VDDT
≤ 100
µ s
PRSTX
TCLKI, PCLK,
SCLK, SCLKX,
MDCLK, FTXCLK,
FRXCLK
≥ 1ms
) (
≥ 100
µ s
) (
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Power and Thermal
Characteristics
Power and Thermal Characteristics 75
Table 36 provides the derived power and thermal characteristics for the production
version of the C-3e NP.
Table 36 C-3e Network Processor Power and Thermal Characteristics
PARAMETER
Power Dissipation, P
D
Maximum Junction
Temperature, T
J
Thermal Resistance, junction to case,
θ
JC
Thermal Resistance, junction to printed circuit board,
θ
JB
MIN TYP
2.5
5.5
<0.1
5.5
MAX UNITS TEST CONDITIONS
7.5
W 180MHz core clock *
125 o C o C/W o C/W
* Power dissipation values assume the following conditions: BMU memory operating at 125MHz. TLU operating at 125MHz. QMU operating at 150MHz. VDD= 1.1V, VDD33/VDDT= 3.3V, TJ at approximately 50 ° C for typical values. VDD and VDD33/VDDT are 5% higher for maximum values. “Minimum” PD based on idle conditions (clocks running and no programs executing). “Typical” PD based on test application that implements Fast Ethernet forwarding actively running on all CPs. “Maximum” PD based on maximum consumption for any high-bandwidth communications application executing on all CPs, FP and XP.
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76 CHAPTER 3: ELECTRICAL SPECIFICATIONS
Thermal Management
Information
This section provides thermal management information for the ceramic ball grid array
(CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods—spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (refer to
); however, due to the potential large mass of the heat sink, attachment through the printed circuit board is suggested. If a spring clip is used, the spring force should not exceed 5.5 pounds.
Figure 10 Package Cross Section View with Several Heat Sink Options
Heat Sink
Heat Sink Clip
Thermal Interface Material
CBGA Package
Printed Circuit Board
Internal Package Conduction Resistance
For the exposed-die packaging technology the intrinsic conduction thermal resistance paths are as follows:
•
The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
• The die junction-to-ball thermal resistance
Figure 11 depicts the primary heat transfer path for a package with an attached heat sink
mounted to a printed-circuit board.
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Power and Thermal Characteristics 77
Figure 11 Package with Heat Sink Mounted to the Printed Circuit Board
External Resistance Radiation Convection
Heat Sink
Internal Resistance
Printed Circuit Board (PCB)
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
External Resistance
Radiation Convection
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by convection.
Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms.
Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
T j
= T
a
+ T r
+ (
θ jc
+
θ int
+
θ sa
) x P
d where:
T
j
is the die-junction temperature
T a
is the inlet cabinet ambient temperature
T r
is the air temperature rise within the computer cabinet
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78 CHAPTER 3: ELECTRICAL SPECIFICATIONS
θ jc
is the junction-to-case thermal resistance
θ int is the adhesive or interface material thermal resistance
θ sa
is the heat sink base-to-ambient thermal resistance
P d
is the power dissipated by the device
During operation, the die-junction temperatures (T
j
) should be maintained less than the value specified in
. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T a
) may range from 30° to
40°C. The air temperature rise within a cabinet (T r) may be in the range of 5° to 10°C. The thermal resistance of the thermal interface material ( example, assuming a T a
of 30°C, a T
θ int
) is typically about 1.5°C/W. For r
of 5°C, a CBGA package
θ jc
= 0.1, and a maximum power consumption (P d
) of 7.5 W, the following expression for T j is obtained:
Die-junction temperature: T
j
= 30°C + 5°C + (0.1°C/W + 1.5°C/W +
θ sa
) x 7.5 W
For this example, a
θ sa value of 10.4°C/W or less is required to maintain the die junction temperature below the maximum value of
.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature—airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs.
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AC Timing Specifications 79
AC Timing Specifications
AC timing specifications consist of input requirements and output responses. The input requirements include setup and hold times, pulse widths, and high and low times. The output responses include delays from clock to signal. The AC timing specifications are defined separately for each interface to the C-3e NP.
See
. Output timing specifications for LVTTL pins are given with a 20pF load on the output. Other loads can be simulated with the IBIS model available from Motorola.
The LVPECL driver is specified into a 50
Ω
load terminated to a (VDD33 - 2V) reference.
Figure 12 Test Loading Conditions
LVTTL
DUT
20pF
LVPECL
DUT
50
Ω
+ 2V
VDD33
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80 CHAPTER 3: ELECTRICAL SPECIFICATIONS
Clock Timing
Specifications
Cycle 1
The system clock timing is shown in Figure 13 and described in Table 37
.
Figure 13 System Clock Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
SCLK
SCLKX
T sc
T sh
T sl
CCLKn
T cch
T ccN
T ccl
Table 37 System Clock Timing Description
SYMBOL PARAMETER
Tsc System Cycle Time
MIN
5.56
Tsh
Tsl
Sys Clk High Pulse
Sys Clk Low Pulse
45
45
Tcc0
Tcc1
Tcc2
Tcc3
Tcch
Tccl
CCLK0 Cycle Time
CCLK1 Cycle Time
CCLK2 Cycle Time
CCLK3 Cycle Time
CCLKm High Time
CCLKm Low Time
40%
40%
TYP
6.43
6.43
6.43
6.43
MAX UNIT COMMENT ns 180MHz core clock
55
55
60%
60% ns ns ns ns
Duty cycle*
Duty cycle*
†
†
†
†
% cycle pulse is high
% cycle pulse is low
* Pulse duty cycle measured at crossing voltage of SCLK/SCLKX
† The frequencies specified for CCLK0 - CCLK3 allow full flexibility for the C-3e NP. It is also possible to use one or more CCLK n inputs for other frequencies; contact your Motorola representative for more information.
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AC Timing Specifications 81
CP Timing Specifications
This section describes the timing for the following CP interfaces:
•
DS1/DS3
•
10/100 Ethernet
•
Gigabit Ethernet
•
OC-3
•
OC-12
DS1/DS3 Timing Specifications
The DS1/DS3 interface timing is shown in
and described in
Cycle 1
Figure 14 DS1/DS3 Ethernet Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn_0 (TCLK)
T cdt
CPn_2/3 (Tx)
T cdo
Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn_1 (RCLK)
T cdr
CPn_4/5 (Rx)
T cds
T cdh
Table 38 DS1/DS3 Ethernet Timing Description
SYMBOL PARAMETER
Tcdt DS1/DS3 Transmit Cycle Time
Tcdo
Tcdr
DS1/DS3 Output Time
DS1/DS3 Receive Cycle Time
MIN
3.0/3.0
TYP
647/22.4
647/22.4
MAX UNIT ns
400/15.0
ns ns
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82 CHAPTER 3: ELECTRICAL SPECIFICATIONS
Table 38 DS1/DS3 Ethernet Timing Description (continued)
SYMBOL PARAMETER
Tcds
Tcdh
DS1/DS3 Setup Time
DS1/DS3 Hold Time
MIN
2.0
0
TYP MAX UNIT ns ns
10/100 Ethernet Timing Specifications
The 10/100 Ethernet interface timing is shown in
Figure 15 and described in Table 39 .
Cycle 1
Figure 15 10/100 Ethernet Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn_0 (TCLK)
CPn_2/3/6 (Tx)
CPn_1/4/5 (Rx)
T cet
T ceo
T ces
T ceh
Table 39 10/100 Ethernet Timing Description
SYMBOL PARAMETER
Tcet
Tceo
Tces
Tceh
Transmit Cycle Time*
Output Time
Setup Time
Hold Time
* STD/Fast Ethernet
MIN
3.0
2.0
0
TYP
20
MAX
15.0
UNIT ns ns ns ns
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AC Timing Specifications 83
GMII / TBI Tx
CPn_0 (TCLK)
CPn_2-6 (Tx)
CPn+1_2-6 (Tx)
MII Tx
MII CPn_1 (TCLKI)
MII CPn_2-6 (Tx)
Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications
The Gigabit GMII Ethernet interface timing is shown in
and described in
Table 40 . The TBI interface timing is shown in
Figure 16 Gigabit Ethernet and TBI Interface Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
T cgt
T cgo
Cycle 1 Cycle 3 Cycle 2
T cmt
T cmo
TBI Rx
CPn+2_1 (RCLK)
CPn+3_1 (RCLKN)
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn+2_2-6 (Rx)
CPn+3_2-6 (Rx)
GMII/MII Rx
CPn+2_1 (RCLK)
CPn+2_2-6 (Rx)
CPn+3_1-6 (Rx)
Cycle 1
T ctr
T ctd
T cts
T cth
T cgr
Cycle 2
T cgs
T cgh
Cycle 3 Cycle 4 Cycle 5
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84 CHAPTER 3: ELECTRICAL SPECIFICATIONS
Table 40 Gigabit GMII/MII Ethernet Interface Timing Description
SYMBOL
GIGABIT PARAMETER
Tcgt
Tcgo
Transmit Cycle Time, GMII
Output Time, GMII
Tcgr
Tcgs
Tcgh
Tcmt
Tcmo
Receive Cycle Time
Setup Time
Hold Time
Transmit Cycle Time, MII
Output Time, MII
MIN
3.0
2.0
0.0
2
TYP
8.0
8.0
40/400
MAX
6.0
12 ns ns ns ns
UNIT ns ns ns
COMMENT
100BaseT/10BaseT
Table 41 Gigabit TBI Interface Timing Description
SYMBOL
TBI
Tctt
Tcto
Tctr
Tctd
Tcts
Tcth
PARAMETER
Transmit Cycle Time
Output Time
Receive Cycle Time
Rclk/Rclkn Deviation
Setup Time
Hold Time
MIN
3.0
2.0
0.0
TYP
8.0
16.0
MAX
6.0*
TOL
1.0
* For Fibre Channel applications this value is 7.0ns for a transmit cycle time of 9.4ns.
UNIT ns ns ns ns ns ns
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CPn_2
CPn_3
Cycle 1
Cycle 1
AC Timing Specifications 85
OC-3 Timing Specifications
The OC-3 interface timing is shown in
Figure 17 and described in Table 42 .
Figure 17 OC-3 Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
T c3t
Cycle 2
T c3i
Cycle 3 Cycle 4 Cycle 5
CPn_0
CPn_1
T c3r
T c3d
CPn_4
CPn_5
T c3s
T c3h
T c3s
T c3h
Table 42 OC-3 Timing Description
SYMBOL PARAMETER
Tc3t OC-3 Transmit Cycle Time
Tc3i
Tc3r
OC-3 Pulse Width
OC-3 Receive Cycle Time*
Tc3d
Tc3s
Tc3h
OC-3 Clock Duty Cycle
OC-3 Setup Time
OC-3 Hold Time
* 155.52MHz
MIN
2.0
6.0
40
2.0
0.0
TYP
6.43
MAX
60 % ns ns
UNIT ns ns ns
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86 CHAPTER 3: ELECTRICAL SPECIFICATIONS
CPn_1 (TCLKI)
CPn_0 (TCLK)
CPn_2-6 (Tx)
CPn+1_2-5 (Tx)
Cycle 1
OC-12 Timing Specifications
The OC-12 interface timing is shown in
Figure 18 and described in Table 43 .
Figure 18 OC-12 Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
T c12d
T c12i
T c12t
Cycle 1
T c12o
Cycle 2
CPn+2_1 (RCLK)
CPn+2_2-6 (Rx)
CPn+3_2-5 (Rx)
T c12r
T c12s
T c12h
Table 43 OC-12 Timing Description
SYMBOL PARAMETER
Tc12i OC-12 Transmit Cycle Time*
Tc12d
Tc12t
OC-12 Clock Duty Cycle
OC-12 Transmit Cycle Time†
Tc12o
Tc12r
Tc12s
Tc12h
OC-12 Output Time‡
OC-12 Receive Cycle Time
OC-12 Setup Time
OC-12 Hold Time
‡
†
* Input from PHY
Output from C-3e NP
Aligned to TCLK, negative edge
-0.1
12.0
2.0
0.0
MIN TYP
12.86
40
12.86
12.86
MAX
60
2.2
ns ns ns ns
UNIT ns
% ns
Cycle 3
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AC Timing Specifications 87
Executive Processor
Timing Specifications
Cycle 1
The XP timing specifications include:
•
•
MDIO Serial Interface Timing Specifications
•
Low Speed Serial Interface Timing Specifications
•
PROM Interface Timing Specifications
PCI Timing Specifications
The PCI timing is shown in Figure 19
Figure 19 PCI Timing Diagram
Cycle 2 Cycle 3 Cycle 4
PCLK
T pc
PAD/P_ctl
(output)
T pao
T paz
T pav
PAD/P_ctl
(input)
T pas
T pah
PGNTX
(input)
T pgs
T pgh
PIDSEL
(input)
T pis
T pih
Cycle 5
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88 CHAPTER 3: ELECTRICAL SPECIFICATIONS
Table 44 PCI Timing Description
SYMBOL PARAMETER
Tpc PCI Cycle Time*
Tpas
Tpah
PAD/P_ctl† Setup
PAD/P_ctl Hold
Tpao
Tpaz
Tpav
Tpgs
PAD/P_ctl Output
PAD/P_ctl Clk to Tri‡
2.0
2.0
PAD/P_ctl Clk to Driven‡ 2.0
PGNTX Setup 5.1
MIN
15.0
3.0
0.0
Tpgh
Tpis
Tpih
PGNTX Hold
PIDSEL Setup
PIDSEL Hold
PRSTX**
PINTA**
0.0
3.0
0.0
TYP MAX
6.0
6.0
6.0
* 66MHz PCI
† P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX,
PSTOPX, PDEVSELX, PPERRX, PSERRX
‡ Not fully tested, values based on design/characterization.
** Asynchronous ns ns ns ns
UNIT ns ns ns ns ns ns ns ns
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SICL
SIDA
(output)
SIDA
(input)
AC Timing Specifications 89
MDIO Serial Interface Timing Specifications
The MDIO serial interface timing is shown in
Figure 20 and described in Table 45 .
Figure 20 MDIO Serial Interface Timing Diagram
Cycle 2 Cycle 3 Cycle 4
T sic
T sods
T sodh
T sids
Table 45 MDIO Serial Interface Timing Description
SYMBOL PARAMETER
Tsic
Tsids
Tsidh
Tsods
Tsodh
SICL Cycle Time
SIDA Input Setup
SIDA Input Hold
MIN
40
10
0.0
SIDA Output Setup 10
SIDA Output Hold 10
TYP MAX UNIT ns ns ns ns ns
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90 CHAPTER 3: ELECTRICAL SPECIFICATIONS
Low Speed Serial Interface Timing Specifications
The low speed serial interface timing is shown in
and described in
.
Figure 21 Low Speed Serial Interface Timing Diagram
Cycle 2 Cycle 3
SICL
SIDA
T slss
T slhs
T slhd
T slsd
T slc
T slst
T slb
Table 46 Low Speed Serial Interface Timing Description
SYMBOL PARAMETER
Tslc SICL Cycle Time
Tslss
Tslhs
Set-up Time for Repeated START Condition
Hold Time START Condition
Tslsd
Tslhd
Tslst
Tslb
Cmax
Data Set-up Time
Data Hold Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Capacitive load for each line of the bus
MIN
2500
600
600
250
0.0
600
1250
MAX
400 ns ns ns ns pF
UNIT ns ns ns
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SPCK
SPDI
SPLD
SPDO
AC Timing Specifications 91
PROM Interface Timing Specifications
The PROM interface timing is shown in
Figure 22 and described in Table 47
.
Cycle 1
Figure 22 PROM Interface Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
T spc
T spis
T spih
T splo
T spdo
Table 47 PROM Interface Timing Description
SYMBOL PARAMETER
Tspc SPCK Cycle Time
MIN
40.0
Tspis
Tspih
SPDI Setup
SPDI Hold
10.0
0.0
Tsplo
Tspdo
SPLD Output
SPDO Output
Tsc
Tsc
TYP MAX
Tsc + 3.0
Tsc + 3.0
UNIT ns ns ns ns ns
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92 CHAPTER 3: ELECTRICAL SPECIFICATIONS
Fabric Processor Timing
Specifications
The FP timing specifications are shown in Figure 23
Cycle 1
Figure 23 Fabric Processor Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
FRXCLK
T frc
FRXCTL
(output)
FRXCTL
(input)
FINn
T frco
T frcz
T frcs
T frch
T frcv
T frds
T frdh
FTXCLK
FTXCTL
(output)
FTXCTL
(input)
FOUTn
T ftco
T ftc
T ftcz
T ftcs
T ftch
T ftcv
T ftdo
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AC Timing Specifications 93
Table 48 Fabric Processor Timing Description
SYMBOL PARAMETER
Tfrc
Tfrcs
Tfrch
Tfrco
Tfrcz
Tfrcv
Tfrds
Tfrdh
Tftc
Tftcs
Tftch
Tftco
Tftcz
Tftcv
Tftdo
FRX Cycle Time
FRXCTL Setup
FRXCTL Hold
FRXCTL Output
FRXCTL Clk to Tri*
FRXCTL Clk to Driven*
FIN Setup
FIN Hold
FTX Cycle Time
FTXCTL Setup
FTXCTL Hold
FTXCTL Output
FTXCTL Clk to Tri*
FTXCTL Tri to Driven*
FOUT Output
0.0
1.0
1.0
1.0
4.0
1.5
MIN
8.0
4.0
1.5
0.0
8.0
4.0
1.5
0.0
1.0
1.0
1.0
1.0
TYP
* Not fully tested, values based on design/characterization.
5.0
4.0
5.0
5.0
4.0
5.0
5.0
MAX ns ns ns ns ns ns ns ns ns ns ns ns ns
UNIT ns ns
COMMENT
Utopia2 Mode
All other modes
Utopia2 Mode
All other modes
Utopia2 Mode
All other modes
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94 CHAPTER 3: ELECTRICAL SPECIFICATIONS
BMU Timing
Specifications
The BMU timing specifications are shown in
Figure 24 and described in Table 49 .
The BMU synchronous DRAM interface is PC100-compliant and designed to work with industry standard SDRAM components with 12 or fewer address lines. The information below is intended to provide the output, setup, and hold data required to design this interface without duplicating the transaction waveform diagrams in SDRAM data sheets.
Cycle 1
Figure 24 BMU Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
MDCLK
T mc
M_ctl
T mco
MAn
T mao
MDn
(output)
T mdo
T mdz
T mdv
MDn
(input)
Table 49 BMU Timing Description
SYMBOL PARAMETER
Tmc BMU Cycle Time
Tmco
Tmao
Tmds
Tmdh
BMU Ctrl Output
BMU Addr Output
BMU Data Setup
BMU Data Hold
Tmdo
Tmdz
Tmdv
Tr, Tf
BMU Data Output
BMU Data Clk to Tri*
0.8
0.8
BMU Data Clk to Driven* 0.8
MDCLK Rise, Fall
MIN
8.0
0.8
0.8
0.5
1.1
T mds
TYP
T mdh
MAX
4.1
4.1
4.8
4.8
4.8
2.0 † ns ns ns ns
UNIT ns ns ns ns ns
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AC Timing Specifications 95
* Not fully tested, values based on design/characterization.
† Measured 0.8V to 2.0V.
Table 50 Signal Groups in BMU Timing Diagrams
SIGNAL GROUP
Control (M_ctl)
Address (MAn)
Data (MDn)
INCLUDED SIGNALS
MBA0, MBA1, MCASX, MRASX, MWEX, MCSX, MDQM, MDQML
MA0 - MA11
MD0 - MD129, MDECC0 - MDECC8
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96 CHAPTER 3: ELECTRICAL SPECIFICATIONS
TLU Timing Specifications
The TLU timing specifications are shown in Figure 25 and described in Table 51 .
Figure 25 TLU Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
TCLKI
T tc
T_ctl
T tco
TAn
T tao
TDn
(output)
T tdo
T tdv
T tdz
TDn
(input)
T tds
T tdh
Table 51 TLU Timing Description
SYMBOL PARAMETER
Ttc TLU Cycle Time
Ttco TLU Ctrl Output
Ttao
Ttds
Ttdh
Ttdo
TLU Addr Output
TLU Data Setup
TLU Data Hold
TLU Data Output
Ttdz
Ttdv
Tr, Tf
TLU Data Clk to Tri*
TLU Data Clk to Driven*
TCLKI Rise, Fall
MIN
8.0
0.8
0.8
1.0
1.2
0.8
0.8
0.8
TYP
*
†
Not fully tested, values based on design/characterization.
Measured 0.8V to 2.0V.
MAX
4.4
4.4
4.8
4.8
4.8
2.0 † ns ns ns ns ns ns ns
UNIT ns ns
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AC Timing Specifications 97
Table 52 Signal Groups in TLU Timing Diagrams
SIGNAL GROUP
Control (T_ctl)
Address (TAn)
Data (TDn)
INCLUDED SIGNALS
TCE0X - TCE3X, TWE0X - TWE3X
TA0 - TA21
TD0 - TD63, TPAR0-3
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98 CHAPTER 3: ELECTRICAL SPECIFICATIONS
QMU SRAM (Internal
Mode) Timing
Specifications
The QMU SRAM (Internal Mode) timing specifications are shown in
and
Cycle 1
Figure 26 QMU SRAM (Internal Mode) Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
QACLKI
T qc
Q_ctl
T qco
QAn
T qao
QDn
(output)
T qdo
T qdv
T qdz
QDn
(input)
T qds
T qdh
Table 53 QMU SRAM (Internal Mode) Timing Description
SYMBOL PARAMETER
Tqc
Tqco
QMU Cycle Time
QMU Ctrl Output
MIN
6.7
0.8
TYP MAX
4.4
4.4
Tqao
Tqds
Tqdh
Tqdo
QMU Addr Output
QMU Data Setup
QMU Data Hold
QMU Data Output
0.8
0.8
0.8
0.9
Tqdz QMU Data Clk to Tri* 0.9
4.4
4.4
ns ns ns ns
UNIT ns ns
COMMENT
Loading is 50
Ω transmission line.
Loading is 50
Ω transmission line.
Loading is 50
Ω transmission line. ns
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AC Timing Specifications 99
Table 53 QMU SRAM (Internal Mode) Timing Description (continued)
SYMBOL PARAMETER
Tqdv QMU Data Clk to
Driven*
Tr, Tf QACLKI Rise, Fall
MIN
0.9
TYP
†
* Not fully tested, values based on design/characterization.
Measured 0.8V to 2.0V.
MAX
4.4
2.0 †
UNIT ns ns
Table 54 Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams
SIGNAL GROUP
Control (Q_ctl)
Address (QAn)
Data (QDn)
INCLUDED SIGNALS
QWEX
QA0-QA16
QD0-QD31, QDPL, QDPH
COMMENT
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100 CHAPTER 3: ELECTRICAL SPECIFICATIONS
QMU to Q-5 TMC (External
Mode) Timing
Specifications
The QMU to Q-5 TMC (External Mode) timing specifications are shown in
Figure 27 QMU to Q-5 (External Mode) Timing Diagram
Cycle 1
T qec
Cycle 2
QACLKI
T qep
T qep
QBCLKI
T qec
DQDATA
T qes
T qeh
T qes
T qeh
T qec
QACLKO
T qep
T qep
QBCLKO
T qec
NQDATA
T qeomax
T qeomin
T qeomax
T qeomin
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AC Timing Specifications 101
Table 55 QMU to Q-5 TMC (External Mode) Timing Description
SYMBOL PARAMETER
Tqec QMU External Cycle Time
Tqep
MIN TYP MAX UNIT COMMENT
10.0
4.8
ns ns
QACLKO/QBCLKO derived from
QACLKI/QBCLKI
Tqes
Tqeh
Tqeo
QMU CLKA-CLKB delta between rising edges
QMU Input Data Setup
QMU Input Data Hold
QMU Data Output
0.6
0.8
-.85
1.3
ns ns ns Determines valid time for data from each clock rising edge
Tr, Tf QACLKI, QBCLKI Rise, Fall
* Measured 0.8V to 2.0V.
2.0 * ns
Table 56 Signal Groups in QMU to Q-5 TMC (External Mode) Timing Diagrams
SIGNAL GROUP
Input Clocks (QnCLKI)
Output Clocks (QnCLKO)
Input Data (DQDATA)
Output Data (NQDATA)
INCLUDED SIGNALS
QACLKI, QBCLKI
QACLKO, QBCLKO
QD0-23, QARDY, QDPL, QDPH, QNQRDY, QDQPAR
QA0-16, QWEX, QD24-31
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102 CHAPTER 3: ELECTRICAL SPECIFICATIONS
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MECHANICAL SPECIFICATIONS
Package Views
The C-3e network processor is an 728 pin (27 pins x 27 pins) Ball Grid Array (BGA) package as shown in the following illustrations.
Table 57 defines the package measurements.
Figure 28 C-3e Network Processor BGA Package (Side View)
A A
1
HiTCE: Green ceramic is thermally matched to FR4 circuit board.
A
4
A
2
Seating Plane
A
3
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104 CHAPTER 4: MECHANICAL SPECIFICATIONS
P
N
M
L
K
W
V
U
T
R
AG
AF
AE
AD
AC
AB
AA
Y
B
A
D
C
J
H
G
F
E
Figure 29 C-3e Network Processor BGA Package (Bottom View)
D
D
1 e b
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 e
E
1
E
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Package Measurements 105
Package Measurements
Table 57 defines the C-3e NP package measurements, providing nominal, minimum, and
maximum sizes where appropriate.
Table 57 Package Measurements (Reference
E
1 e
D
1
E b
SYMBOL DEFINITION
A Overall
A
1
A
2
A
3
A
4
D
Ball height
Die height
Body thickness
Capacitor height
Body size
Ball footprint (X)
Body size
Ball footprint (Y)
Ball pitch
Ball diameter
NOM. (MM) MIN. (MM) MAX. (MM)
3.11
2.83
3.39
0.70
0.86
0.6
0.8
1.55
1.41
29.00
26.00
29.00
26.00
1.00
0.70
28.80
28.80
1.69
0.6
29.20
29.20
Keep Out Zones
Figure 30 shows the C-3e NP keep out zones and Table 58 defines their measurements,
providing minimum and maximum sizes where appropriate.
Since 14 capacitors are present on all devices, caution must be taken not to short capacitors or exposed metal capacitor pads on package top. This can be achieved by noting the capacitors zones as detailed here.
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106 CHAPTER 4: MECHANICAL SPECIFICATIONS
Figure 30 C-3e Network Processor BGA (Top View)
D
4
Probe Pad
Die D
2
Capacitor
Pads
18ARS10517D001
D
3
Table 58 Keep Out Zone’s Measurements (Reference
D
2
D
3
E
3
E
4
SYMBOL DEFINITION
Keep out zones
D
4
E
2
NOM. (MM) MIN. (MM) MAX. (MM)
1.125
6.95
9.5
9.25
11.8
7.875
E
2
E
3
E
4
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Marking Codes
Reflow
Marking Codes 107
Table 59 explains the marking on the C-3e NP.
Table 59 C-3e Network Processor Marking Codes
MARKING (EXPLANATION OF CODES)
Top Logo/Part#/Date Code
Bottom N/A
Pin 1 Marking Chamfered Corner
Typical Reflow Profile for the C-3e Switch Module comprises:
1 Follow the guidelines recommended by your solder paste supplier.
Flux requirements must be met for best solderability.
2 The temperature profile should be carefully characterized to ensure uniform temperature across the board and package.
Solder ball voiding may be affected by ramp rates and dwell times below and above liquids.
3 A nitrogen atmosphere is not required, but will make the process more robust. It can make a difference for marginally solderable PC board pads.
4 Full convection forced air furnaces work best, but IR, Convection/IR, or vapor phase can be used.
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108 CHAPTER 4: MECHANICAL SPECIFICATIONS
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INDEX
Symbols
10/100 Ethernet (RMII) Configuration
10/100 Ethernet Signals
10/100 Ethernet Timing Description
10/100 Ethernet Timing Diagram
10/100 Ethernet Timing Specifications
A
Absolute Maximum Ratings
AC Timing Specifications
B
Block Diagram, C-3e Network Processor
BMU SDRAM Interface Signals
BMU Signal Groups
BMU Timing Description
BMU Timing Diagram
BMU Timing Specifications
Boundary Scan Cell Types
Boundary Scan Description Language
Bringup Clock Timing Diagram
Buffer Management Unit
C
C-3e Network Processor Absolute Maximum Ratings
C-3e Network Processor BGA Package, Bottom View
C-3e Network Processor BGA Package, Side View
C-3e Network Processor Capacitance Data
C-3e Network Processor DC Characteristics
C3e Network Processor Power and Thermal Characteristics
C-3e NP Channel Processors
Channel Processor Interface Signals
Channel Processors
Channel Processors Physical Interface Signals and Pins
Grouped by Clusters
Clock and Reference Signals
Clock Signals
Clock Timing Specifications
Configuration
10/100 Ethernet (RMII)
DS1/T1 Framer Interface
FibreChannel TBI
Gigabit Ethernet
Gigabit Ethernet (GMII)
SONET OC-12 Transceiver Interface
SONET OC-3 Transceiver Interface
Configurations
GMII/TBI Transmit and Receive Pin
CP Timing Specifications
D
Data Registers
JTAG
DC Characteristics
Description
Functional
Description Language
Boundary Scan
Descriptions
Signal
Diagram
10/100 Ethernet Timing
BMU Timing
Bringup Clock Timing
DS1/DS3 Ethernet Timing
Fabric Processor Timing
Gigabit Ethernet (TBI) Timing
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110 INDEX
Low Speed Serial Interface Timing
MDIO Serial Interface Timing
OC-3 Timing
PCI Timing
Pinout
PROM Interface
PROM Interface Timing
QMU Timing
Signal Groups in BMU Timing
Signal Groups in QMU Timing
Signal Groups in TLU Timing
System Clock Timing
TLU Timing
Diagram, Block
C-3e Network Processor
DS1/DS3 Ethernet Timing Description
DS1/DS3 Ethernet Timing Diagram
DS1/DS3 Timing Specifications
DS1/T1 Framer Interface Configuration
DS1/T1 Framer Interface Signals
E
Electrical Specifications
Absolute Maximum Ratings
Executive Processor
PCI
PROM Interface
Serial Bus Interface
System Interface Signals
System Interfaces
Executive Processor Timing Specifications
F
Fabric Interface Pin Mapping
Utopia2/Utopia3 ATM Mode
Utopia2/Utopia3 PHY Mode
Fabric Processor
Fabric Processor Interface Signals
Fabric Processor Timing Description
Fabric Processor Timing Diagram
Fabric Processor Timing Specifications
Functional Description
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G
General System Interface Signal
Gigabit Ethernet (GMII) Configuration
Gigabit Ethernet (GMII) Signals
One Cluster Example
Gigabit Ethernet (TBI) Timing Description
Gigabit Ethernet (TBI) Timing Diagram
Gigabit Ethernet and FibreChannel TBI Configuration
Gigabit Ethernet and FibreChannel TBI Signals
Example
Gigabit GMII Ethernet, TBI and MII Interface Timing Specification
GMII/TBI Transmit and Receive Pin Configurations
I
IDcode Register
Instruction Register Instructions
J
JTAG Data Registers
JTAG Identification Code and Its Sub-components
JTAG Instruction Register
JTAG Internal Register Descriptions
JTAG Support
Pinouts
L
Low Speed Serial Interface Timing Description
Low Speed Serial Interface Timing Diagram
Low Speed Serial Interface Timing Specifications
LVPECL Specifications
LVTTL Specifications
M
MDIO Serial Interface Timing Description
MDIO Serial Interface Timing Diagram
MDIO Serial Interface Timing Specifications
Measurements
C-3e Network Processor
Mechanical Specifications
Freescale Semiconductor, Inc.
Miscellaneous Test Signals for JTAG, Scan, and Internal Test
Routines
O
OC-12 Signals
OC-12 Timing Description
OC-12 Timing Specifications
OC-3 Signals
OC-3 Timing Description
OC-3 Timing Diagram
OC-3 Timing Specifications
Operating Conditions, Recommended
P
Package Measurements
PCI Signals
PCI Timing Description
PCI Timing Diagram
PCI Timing Specifications
Pin Descriptions
Grouped by Function
Pin Locations
Pin Number Signals Groups
Pinout Diagram
Power Sequencing
Power Supply Signals
Processor, Executive
Processor, Fabric
PROM Interface Diagram
PROM Interface Signals
PROM Interface Timing Description
PROM Interface Timing Diagram
PROM Interface Timing Outline
PROM Interface Timing Specifications
Q
QMU Signal Groups
QMU SRAM (Internal Mode) Interface Signals
QMU SRAM (Internal Mode) Timing Diagram
QMU Timing Description
QMU Timing Specifications
QMU to Q-5 (External Mode) Timing Diagram
INDEX 111
QMU to Q-5 TMC (External Mode) Interface Signals
Queue Management Unit
R
Recommended Operating Conditions
Register
IDcode
JTAG Instruction
S
Serial Interface Signals
Serial Port Signals
Signal
General System Interface
Signal Descriptions
Signal Summary
Signals
10/100 Ethernet
BMU SDRAM Interface
Channel Processor Interface
Clock
Clock and Reference
DS1/T1 Framer Interface
Fabric Processor Interface
Grouped by Pin Number
OC-12
OC-3
PCI
Power Supply
PROM Interface
QMU SRAM (Internal Mode) Interface
QMU to Q-5 TMC (External Mode) Interface
Serial Interface
Serial Port
Test
TLU SRAM Interface
SONET OC-12 Transceiver Interface Configuration
SONET OC-3 Transceiver Interface Configuration
Specifications
10/100 Ethernet Timing
AC Timing
BMU Timing
Clock Timing
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112 INDEX
CP Timing
DS1/DS3 Timing
Electrical
Executive Processor Timing
Fabric Processor Timing
Gigabit GMII Ethernet, TBI and MII Interface Timing
Specification
Low Speed Serial Interface Timing
MDIO Serial Interface Timing
Mechanical
OC-12 Timing
OC-3 Timing
PCI Timing
PROM Interface Timing
QMU Timing
TLU Timing
XP Timing
System Clock Timing Description
System Clock Timing Diagram
System Interfaces
Executive Processor
T
Table Lookup Unit
Test Signals
Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test
Routines
Timing Outline
PROM Interface
TLU Signal Groups
TLU SRAM Interface Signals
TLU Timing Description
TLU Timing Diagram
TLU Timing Specifications
Transceiver Interface Configuration
SONET OC-12
SONET OC-3
Transmit and Receive Pin Combinations for Gigabit Ethernet and
FibreChannel
U
Utopia2/Utopia3 ATM Mode, C-3e Network Processor to Fabric
Interface Pin Mapping
Utopia2/Utopia3 PHY Mode, C-3e Network Processor to Fabric
Interface Pin Mapping
X
XP Timing Specifications
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