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Order this document by DSP56652UM/D
Rev. 0, 04/1999
DSP56652
Baseband Digital Signal Processor
UserÕs Manual
Motorola, Incorporated
Semiconductor Products Sector
6501 William Cannon Drive West
Austin TX 78735-8598
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This document contains information on a new product. Specifications and information herein are subject to change without notice.
This manual is one of a set of three documents. Three manuals are required for complete product information: the family manual, the userÕs manual, and the technical data sheet.
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Table of Contents
Motorola Table of Contents
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Core Operation and Configuration
Debug Port and Timer Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
MCU-Side Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Shared Memory Access Contention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
iv DSP56652 UserÕs Manual
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Shared Memory in DSP STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Displaying the Internal Bus (Show Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Programmable Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
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Queued Serial Peripheral Interface
Programmable Queue Lengths and Continuous Transfers. . . . . . . . . . . . . . . 8-2
Programmable Peripheral Chip-Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Programmable Delay after Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Loading a Programmable Address at the End of Queue . . . . . . . . . . . . . . . . 8-3
Pause Enable at Queue Entry Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
vi DSP56652 UserÕs Manual
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GP Timer and PWM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Timing Signals and Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
General Purpose Input/Output (GPIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Protocol Timer Programming Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
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Standby and Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Noise Suppression on Keypad Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Serial Audio and Baseband Ports
viii DSP56652 UserÕs Manual
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Synchronous and Asynchronous Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
SAP and BBP Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
Entering MCU OnCE Mode via JTAG Control. . . . . . . . . . . . . . . . . . . . . 15-12
Release from Debug Mode for DSP and MCU . . . . . . . . . . . . . . . . . . . . . 15-13
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Comments on Normal Boot Mode Usage . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
Example of Program Download and Execution. . . . . . . . . . . . . . . . . . . . . . A-14
x DSP56652 UserÕs Manual
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List of Figures
DSP56652 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
DSP56652 Clock Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
DSP PLL and Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
MUX Connectivity Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
MDI: DSP-Side Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
MDI: MCU-Side Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
MDI Message Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
DSP-to-MCU General Purpose Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Example EIM Interface to Memory and Peripherals . . . . . . . . . . . . . . . . 6-2
Hardware Priority Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Internal IRQAÐD Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
QSPI Serial Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
PIT Timing Using the PITMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Watchdog Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
GP Timer/PWM Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
GP Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Motorola List of Figures
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PWM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Figure 12-2. SCP: Port Interface and Auto Power Down Logic . . . . . . . . . . . . . . . . . 12-3
Figure 15-2. DSP56600 Core JTAG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
Figure A-3. Format of memory_write.request Message . . . . . . . . . . . . . . . . . . . . . . . A-5
Figure A-4. Format of message_write.response Message. . . . . . . . . . . . . . . . . . . . . . A-6
Figure A-5. Format of memory_read.request Message. . . . . . . . . . . . . . . . . . . . . . . . A-7
Figure A-6. Format of memory_read.response Message . . . . . . . . . . . . . . . . . . . . . . A-8
Figure A-7. Format of memory_check.request Message . . . . . . . . . . . . . . . . . . . . . . A-9
Figure A-8. Format of memory_check.request Message . . . . . . . . . . . . . . . . . . . . . A-10
Figure A-9. Format of start_application.request Message . . . . . . . . . . . . . . . . . . . . A-11
xii DSP56652 UserÕs Manual
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Figure A-10. Format of invalid_opcode.response Message . . . . . . . . . . . . . . . . . . . . A-12
Figure A-11. Mapping of DSP Program Memory words to MDI message words. . . . A-13
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xiv DSP56652 UserÕs Manual
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List of Tables
DSP56652 Signal Functional Group Allocations . . . . . . . . . . . . . . . . . . . 2-1
Reset, Mode, and Multiplexer Control Signals . . . . . . . . . . . . . . . . . . . . 2-7
Protocol Timer Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
MCU and MCU Peripherals Clock Source . . . . . . . . . . . . . . . . . . . . . . . . 4-3
MCU Peripherals in Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
DSP Peripherals in Low Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Programmable Power-Saving Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
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Debug Port Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Pin Function in DSP Address Visibility Mode. . . . . . . . . . . . . . . . . . . . 4-20
MCU MDI Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
MDI Registers and Symmetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
MCU Wake-up Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
MCU-Side Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
MDI Signalling and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
MCUÐDSP Register Correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Chip Select Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Interface Requirements for Read and Write Cycles . . . . . . . . . . . . . . . . . 6-6
xvi DSP56652 UserÕs Manual
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NIPR and FIPR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Interrupt Source Priorities within an IPL . . . . . . . . . . . . . . . . . . . . . . . . 7-13
QSPI Register/Memory Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
QSPI Control RAM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
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TPWMR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Protocol Timer Operation Mode Summary . . . . . . . . . . . . . . . . . . . . . 10-10
Protocol Timer Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
PT Port Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Protocol Timer Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Protocol Timer Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Additional Conditions for Generating PT Interrupts . . . . . . . . . . . . . . 10-18
Suggested GPIO Pins for UART Signals . . . . . . . . . . . . . . . . . . . . . . . . 11-4
UART Low Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
xviii DSP56652 UserÕs Manual
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UART Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
SCP Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
SCP Pin GPIO Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
SCPPCR Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
Keypad Port pull-up Resistor Control . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Keypad Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
SAP/BBP Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
SAP and BBP Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Serial Audio Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
Baseband Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
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SAP/BBP CRA Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
SAP/BBP CRB Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
SAP/BBP CRC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Entering MCU OnCE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Releasing the MCU and DSP from Debug Modes . . . . . . . . . . . . . . . 15-14
DSP56652 Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
MCU Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
MCU Instruction Syntax Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6
MCU Instruction Opcode Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6
DSP Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
Program Word and Timing Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . D-13
Condition Code Register (CCR) Symbols . . . . . . . . . . . . . . . . . . . . . . . D-13
Condition Code Register Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-13
MCU Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-14
DSP Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-19
List of ProgrammerÕs Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
xx DSP56652 UserÕs Manual
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List of Examples
Example 5-1. Program Loop That Stalls MCU Access to Shared Memory . . . . . . . . . . 5-4
Example 5-3. Dummy Event to Allow MCU to Track DSP Power Mode Change . . . 5-13
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Preface
This section provides information on the data conventions used in this manual, as well as a list of complete product documentation.
Conventions
The following conventions are used in this manual:
¥ Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB).
¥ 1 byte = 8 bits
1 halfword = 16 bits = 2 bytes
1 word = 32 bits = 4 bytes
¥ Bits within a register are indicated AA[n:0] when more than one bit is involved in a description. For purposes of description, the bits are presented as if they were contiguous within a register, regardless of their actual physical locations in a register.
¥ All bits in a register are read/write unless otherwise noted.
¥ When a bit is described as Òset,Ó its value is 1. When a bit is described as Òcleared,Ó its value is 0.
¥ Register bits that are unused or reserved for future use are read as 0 and should be written with 0 to ensure future compatibility. In the register descriptions, each of these bits is indicated with a shaded box ( ).
¥ The word ÒresetÓ is used in three different contexts in this manual:
Ñ There is a reset instruction that is always written as ÒRESETÓ.
Ñ In lower case, ÒresetÓ refers to the reset function. A leading capital letter is used as grammar dictates.
Ñ ÒResetÓ refers to the Reset state.
¥ The word ÒpinÓ is a generic term for any pin on the chip. Because of on-chip pin multiplexing, more than one signal may be present on any given pin.
¥ Pins or signals that are asserted low (made active when pulled to ground) have an overbar over their name; for example, the SS0 pin is asserted low.
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¥ Hex values are indicated with a dollar sign ($) preceding the hex value as follows:
X:$FFFF is the X memory address for the Interrupt Priority RegisterÑCore
(IPR-C).
Code examples are displayed in a monospaced font, as shown in Example 1.
BFSET #$0007,X:PCC
Example 1.
Code Example
; Configure: line 1
; MISO0, MOSI0, SCK0 for SPI masterline 2
; ~SS0 as PC3 for GPIO line 3
¥ In code examples, the names of pins or signals that are asserted low are preceded by a tilde. In the previous example, line 3 refers to the SS0 pin (shown as
~SS0
).
¥ The word ÒassertÓ means that a high true (active high) signal is pulled high to V
CC or that a low true (active low) signal is pulled low to ground. The word ÒdeassertÓ means that a high true signal is pulled low to ground or that a low true signal is pulled high to V
CC
. These conventions are summarized in Table 1.
Table 1.
Signal States
Signal/Symbol Logic State Signal State Voltage
PIN True Asserted
Ground
1
PIN False Deasserted
V
CC
2
PIN True Asserted V
CC
Ground PIN False Deasserted
1.
Ground is an acceptable low-voltage level. See the appropriate data sheet for the range of acceptable low-voltage levels (typically a TTL logic low).
2.
V
CC
is an acceptable high-voltage level. See the appropriate data sheet for the range of acceptable high-voltage levels (typically a TTL logic high).
Documentation
This manual (DSP56652UM/D) is one of a set of five documents that provides complete product information for the DSP56652. The other four documents include the following:
¥
¥
¥
¥
M¥CORE Reference Manual (MCORERM/AD)
MMC2001 Reference Manual (MMC2001M/AD
DSP56600 Family Manual (DSP56600FM/AD)
DSP56652 Technical Data Sheet (DSP56652/D) xxiv DSP56652 UserÕs Manual
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Chapter 1
Introduction
Motorola designed the ROM-based DSP56652 to support the rigorous demands of the cellular subscriber market. The high level of on-chip integration in the DSP56652 minimizes application system design complexity and component count, resulting in very compact implementations. This integration also yields very low power consumption and cost-effective system performance. The DSP56652 chip combines MotorolaÕs 32-bit
M¥COREª MicroRISC Engine and the DSP56600 Digital Signal Processor (DSP) core with on-chip memory, a protocol timer, and custom peripherals to provide a single-chip
cellular base-band processor. A block diagram of the 56652 is shown in Figure 1-1.
1.1 DSP56652 Key Features
The following list summarizes the key features of the DSP56652.
¥ M¥CORE (MCU) core
Ñ 32-bit load/store M¥CORE RISC architecture
Ñ Fixed 16-bit instruction length
Ñ 16-entry 32-bit general-purpose register file
Ñ 32-bit internal address and data buses
Ñ Efficient four-stage, fully interlocked execution pipeline
Ñ Single-cycle execution for most instructions, two cycles for branches and memory accesses
Ñ Special branch, byte, and bit manipulation instructions
Ñ Support for byte, halfword, and word memory accesses
Ñ Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file
1-1 Motorola Introduction
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DSP56652 Key Features
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Timer/PWM
Watchdog
Timer
Programmable
Interrupt Timer
Edge I/O
1-2
External
Memory
RAM
512 x 32
ROM
4K x 32
M¥Core
MicroRISC
Core
Smart Card
I/F
Keypad
I/F
Queued
SPI
UART
MUX
Clocks
DSP PLL
JTAG
MCU
OnCE
MCU
OnCE
MCU Ð DSP
Interface
1K x 16 Dual-Port
X Data RAM
Messaging
Unit
JTAG Serial
Audio
CODEC I/F
X Data
RAM
(7+1)K x 16
Y Data
RAM
6K x 16
Program
RAM
512 x 24
X Data
ROM
10K x 16
Y Data
ROM
10K x 16
X Data
RAM
48K x 24
56600
DSP
Core
Protocol
Timer
Serial Audio
Codec I/F
Baseband
Codec I/F
DSP56652
Figure 1-1. DSP56652 Block Diagram
¥ DSP core
Ñ DSP56600 architecture
Ñ Single-cycle arithmetic instructions
Ñ Fully pipelined 16
´
16-bit parallel multiply accumulator (MAC)
Ñ Two 40-bit accumulators including extension bits
Ñ 40-bit parallel barrel shifter
Ñ Highly parallel instruction set with unique DSP addressing modes
Ñ Position-independent code support
Ñ Nested hardware DO loops
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DSP56652 Key Features
Ñ Fast auto-return interrupts
Ñ On-chip support for software patching and enhancements
Ñ Real-time trace capability via external address bus
¥ On-chip memory
Ñ 4K
´
32-bit MCU ROM
Ñ 512
´
32-bit MCU RAM
Ñ 48K
´
24-bit DSP program ROM
Ñ 512
´
24-bit DSP program RAM
Ñ 10K
´
16-bit DSP X data ROM
Ñ 10K
´
16-bit DSP Y data ROM
Ñ (7+1)K
´
16-bit X data RAM
Ñ 6K
´
16-bit Y data RAM
¥ On-chip peripherals
Ñ Fully programmable phase-locked loop (PLL) for DSP clock generation
Ñ External interface module (EIM) for glueless system integration
Ñ External 22-bit address and 16-bit data MCU buses
Ñ 32-source MCU interrupt controller
Ñ Intelligent MCU/DSP interface (MDI) with 1K
´
16-bit dual-port RAM as well as messaging status and control unit
Ñ Serial audio codec port (SAP)
Ñ Serial baseband codec port (BBP)
Ñ Protocol timer frees the MCU from radio channel timing events
Ñ Queued serial peripheral interface (QSPI)
Ñ Keypad port capable of scanning up to an 8
´
8 matrix keypad
Ñ General-purpose MCU and DSP timers
Ñ Pulse width modulation (PWM) output
Ñ Universal asynchronous receiver/transmitter (UART) with FIFO
Ñ IEEE 1149.1-compliant boundary scan JTAG test access port (TAP)
Ñ Integrated DSP/MCU On-Chip Emulation (OnCEª) module
Ñ DSP program address bus visibility mode for system development
Ñ ISO 7816-compatible smart card port
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Architecture Overview
¥ Operating features
Ñ Comprehensive static and dynamic power management
Ñ MCU operating frequency: DC to 16.8 MHz at 1.8 V
Ñ DSP operating frequency: DC to 58.8 MHz at 1.8 V
Ñ Internal operating voltage range: 1.8Ð2.5 V with 3.1 V-tolerant I/O
Ñ Operating temperature: Ð40û to 85ûC ambient
Ñ Package option: 15
´
15 mm, 196-lead PBGA
1.2 Architecture Overview
The DSP56652 combines the control and I/O capability of the M¥CORE MCU with the data processing power of the DSP56600 core to provide a complete system solution for a cellular baseband system. The DSP subsystem has a closed architecture, meaning that all
DSP memory is contained on the device and the DSP address and data buses do not appear external to the device. The MCU subsystem provides both on-chip memory and an external bus interface. Both processors provide external interrupt pins.
The two cores communicate through the MDI, which includes a block of dual-access
RAM.
Each core generates its own independent clock, and the DSP core contains a PLL as part of its clock generation subsystem. Each processor and its associated peripherals have several low-power standby modes.
A single JTAG port is shared by the two cores for debug and test purposes. The JTAG port is integrated with on-chip emulation modules for both the MCU and the DSP, providing a non-intrusive way to interact with the processors and their peripherals and memory. The
MCU has additional external debug pins for in-circuit emulation. The DSP program address bus is multiplexed on other DSP56652 pins.
The pins associated with most peripherals can be programmed individually to function as general-purpose input/output signals (GPIO) if their primary functions are not required.
(The exceptions are the MCU pulse width modulator and general-purpose timer, which have no GPIO capability, and the SmartCard Port (SCP), whose five pins must all function either as SCP pins or GPIO (i.e., cannot be individually programmed).
1.2.1 MCU
This section describes the MCU core, peripherals, and memory.
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Architecture Overview
1.2.1.1 Core Description
The M¥CORE MCU utilizes a four-stage pipeline for instruction execution. The instruction fetch, instruction decode/register file read, execute, and register write-back stages operate in an overlapped fashion, allowing most instructions to execute in a single clock cycle. Sixteen general-purpose registers are provided for source operands and instruction results.
The execution unit consists of a 32-bit arithmetic/logic unit (ALU), a 32-bit barrel shifter, a find-first-one unit (FFO), result feed-forward hardware, and miscellaneous support hardware for multiplication and multiple register loads and stores. Arithmetic and logical operations are executed in a single cycle with the exception of the multiply and divide instructions. The FFO unit operates in a single clock cycle.
The program counter unit contains a PC incrementer and a dedicated branch address adder to minimize delays during change-of-flow operations. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero extension of byte and halfword load data. These instructions can execute in two clock cycles. Load and store multiple register instructions allow low overhead context save and restore operations.
A single condition code/carry (C) bit is provided for condition testing and to implement arithmetic and logical operations greater than 32 bits. A 16-entry alternate register file is provided to minimize exception processing overhead, and the CPU supports both vectored and auto-vectored interrupts.
The user programming model contains the program counter, sixteen 32-bit generalpurpose registers, and the carry bit. A separate supervisor mode is provided for exception processing. The supervisor programming model includes all of the user registers plus an additional sixteen 32-bit general-purpose registers, 12 control registers, and 5 scratch registers.
For a complete description of M¥CORE architecture, refer to the M¥CORE Reference
Manual .
1.2.1.2 MCU-Side Peripherals
The MCU-side peripherals for the DSP56652 support a variety of I/O functions, including radio channel timing, signal generation, periodic interrupts, smart card interface, LCD displays, and key pads.
¥ A keypad port supports up to 8 rows and 8 columns.
¥ The QSPI enables serial communication to multiple peripheral devices through a single port.
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Architecture Overview
¥ The SCP provides user information to an external device through a smart card port.
¥ A UART connects to a modem or another computer.
¥ An edge I/O port enables up to eight external interrupts.
¥ An interrupt controller prioritizes up to 32 peripheral interrupts.
¥ Four timers are provided, including
Ñ a periodic interval timer to generate periodic interrupts
Ñ a watchdog timer to protect against system failure
Ñ a pwm and general-purpose timer to generate custom signals
Ñ a protocol timer with TDMA counters for radio channel control, event scheduling, QSPI triggers or generating interrupts to either core.
¥ MCU OnCE facilitates test and debug.
1.2.1.3 MCU-Side Memory
All MCU memory is 32 bits (1 word) wide. On-chip MCU memory includes 512 words of
RAM and 4K words of ROM. In addition, the EIM provides a 22-bit address/16-bit data bus with control signals to access external memory. Programmable timing on this bus allows the use of a wide range of memory devices. As many as six external memory banks can be connected.
1.2.2 DSP
This section describes the DSP core, peripherals, and memory.
1.2.2.1 Core Description
The DSP56600 core contains a data arithmetic logic unit, an address generation unit, a program control unit, and program patch logic.
1.2.2.1.1 Data Arithmetic Logic Unit
The data arithmetic logic unit (ALU) performs all data arithmetic and logical operations in the DSP core. The components of the data ALU include the following:
¥ Four 16-bit input general purpose registers: X1, X0, Y1, and Y0
¥ A parallel, fully pipelined MAC
¥ Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two general-purpose, 40-bit accumulators, A and B
¥ An accumulator shifter that is an asynchronous parallel shifter with a 40-bit input and a 40-bit output
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Architecture Overview
¥ A bit field unit (BFU) with a 40-bit barrel shifter
¥ Two data bus shifter/limiter circuits
The data ALU registers can be read or written over the X data bus (XDB) and the Y data bus (YDB) as 16- or 32-bit operands. The source operands for the data ALU, which can be
16, 32, or 40 bits, always originate from data ALU registers. The results of all data ALU operations are stored in an accumulator.
A seven-stage pipeline executes one instruction per clock cycle. The destination of every arithmetic operation can be used as a source operand for the immediate following operation without penalty.
The MAC unit comprises the main arithmetic processing unit of the DSP core and performs all of the calculations on data operands. For arithmetic instructions, the unit accepts as many as three input operands and outputs one 40-bit result, formatted as
Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).
The multiplier executes 16-bit
´
16-bit, parallel, fractional multiplies, between twoÕscomplement signed, unsigned, or mixed operands. The 32-bit product is right-justified and added to the 40-bit contents of either the A or B accumulator. A 40-bit result can be stored as a 16-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified.
1.2.2.1.2 Address Generation Unit
The address generation unit (AGU) performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation overhead.
The AGU is divided into two halves, each with its own address ALU. Each address ALU has four sets of register triplets, and each register triplet is composed of an address register, an offset register, and a modifier register. The two address ALUs are identical.
Each contains a 16-bit full adder (referred to as an offset adder).
A second full adder (referred to as a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. A third full adder
(called a reverse-carry adder) is also provided.
The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that they carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output.
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Architecture Overview
Each address ALU can update one address register from its respective address register file during one instruction cycle. The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation. The modifier value is decoded in the address ALU.
1.2.2.1.3 Program Control Unit
The program control unit (PCU) performs instruction prefetch, instruction decoding, hardware DO loop control and exception processing. The PCU implements a seven-stage pipeline and controls the different processing states of the DSP core. The PCU consists of three hardware blocks:
¥ program decode controller (PDC)
¥ program address generator (PAG)
¥ program interrupt controller (PIC)
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. The PAG contains all the hardware needed for program address generation, system stack and loop control. The PIC arbitrates among all interrupt requests and generates the appropriate interrupt vector address.
The PCU implements its functions using the following registers:
¥ PCÑProgram Counter register
¥ SRÑStatus Register
¥ LAÑLoop Address register
¥ LCÑLoop Counter register
¥ VBAÑVector Base Address register
¥ SZÑSize register
¥ SPÑStack Pointer
¥ OMRÑOperating Mode Register
¥ SCÑStack Counter register
The PCU also includes a hardware System Stack (SS).
1.2.2.1.4 Program Patch Logic
The program patch logic (PPL) block provides a way to adjust program code in the onchip ROM without generating a new mask. Implementing the code correction is done by replacing a piece of ROM-based code with a patch program stored in RAM. The PPL consists of four patch address registers (PAR0ÐPAR3) and four patch address
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Architecture Overview comparators. Each PAR points to a starting location in the ROM code where the program flow is to be changed. The PC register in the PCU is compared to each PAR. When an address of a fetched instruction is identical to an address stored in one of the PARs, the program data bus is forced to a corresponding JMP instruction, replacing the instruction that otherwise would have been fetched from the ROM.
1.2.2.2 DSP-Side Peripherals
The DSP-side peripherals for the DSP56652 are primarily targeted at handling baseband and audio processing.
¥ Two improved synchronous serial ports connect to external codecs to process received baseband information.
Ñ The SAP connects to a standard audio codec. This port also provides a generalpurpose timer.
Ñ The BBP connects to a standard RF/IF codec.
¥ DSP OnCE facilitates test and debug.
1.2.2.3 DSP-Side Memory
All DSP memory is contained on-chip. DSP program memory is 24 bits wide, while data memory is 16 bits (1 halfword) wide. Program ROM is 48K by 24-bits, and program
RAM is 512 by 24-bits. Data memory is organized into two separate areas, X and Y, each accessed by its own address and data buses. X and Y data ROM are 10K by 16 bits each.
X data RAM is 7K by 16 bits, and Y data RAM is 6K by 16 bits. In addition, 1K of X data memory space serves as dual-port RAM for the MDI.
1.2.3 MCUÐDSP Interface
The MDI provides a way for the MCU and DSP cores to communicate with each other. It contains a message and control unit as well as 1K
´
16-bit dual-ported RAM.
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Chapter 2
Signal/Connection Description
The DSP56652 input and output signals are organized into functional groups in Table 2-1
below and in Figure 2-1 on page 2-2. Many of the pins in the DSP56652 have multiple
functions. In Table 2-1, pin function is described to reflect primary pin function.
Subsequent tables in this section are named for these primary functions and provide full descriptions of all signals on the pins.
Table 2-1. DSP56652 Signal Functional Group Allocations
Functional Group
Power (V
CCX
)
Function-specific ground (GND
X
)
General ground (GND)
PLL and clocks
External Interface
Module (EIM)
Address bus
Data bus
Bus control
Chip selects
Reset, mode, and multiplexer control
External interrupts
Protocol Timer
Keypad port
UART
Queued Serial Peripheral Interface (QSPI)
Smart Card Port (SCP)
Serial Audio Codec Port (SAP)
Baseband Codec Port (BBP)
Development & Test
Emulation port
Debug control port
JTAG test access port (TAP)
Number of
Signals
20
17
6
6
8
5
6
2
6
16
4
9
8
20
5
22
16
4
6
5
Detailed
Description
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2-2
DSP56652
Power
Function-
Specific
Ground
General
Ground
PLL and
Clocks
External
Interface
Module
(EIM)
GNDA
GNDB
GNDC
GNDD
GNDE
GNDF
GNDG
GNDH
GNDK
GNDP
GNDP1
GNDQ
GND
VCCA
VCCB
VCCC
VCCD
VCCE
VCCF
VCCG
VCCH
VCCHQ
VCCK
VCCP
VCCQ
CKIH
CKIL
CKO
CKOH
PCAP
A0ÐA21
D0ÐD15
R/W
EB0
EB1
OE
CS0
CS1ÐCS4
CS5
Reset, Mode and
Multiplexer
Control
RESET_IN
RESET_OUT
MOD
MUX_CTL
STO
1
1
1
22
16
4
1
1
1
2
1
1
1
1
1
2
1
1
4
4
1
1
1
4
20
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
1
3
1
1
5
1
1
1
1
1
1
1
2
4
1
1
1
1
1
1
1
1
6
1
8
1
1
1
1
5
6
1
Figure 2-1. Signal Group Organization
INT0ÐINT5
INT6/STDA/DSR or TRST
INT7/SRDA/DTR/SCK or TMS
DSP_IRQ
TOUT0ÐTOUT7
COL0ÐCOL5
COL6/OC1
COL7/PWM
ROW0ÐROW4
ROW5/IC2B
ROW6/SC2A/DCD or DSP_DE
ROW7/SCKA/RI or TCK
TxD or TDO
RxD/IC1 or TDI
RTS/IC2 or RESET_IN
CTS or MCU_DE
SPICS0ÐSPICS4
SCK
MISO
MOSI
SIMCLK
SENSE
SIMDATA
SIMRESET
PWR_EN
STDA
SRDA
SCKA
SC0AÐSC2A
STDB
SRDB
SCKB
SC0BÐSC2B
SIZ0ÐSIZ1
PSTAT0ÐPSTAT3
MCU_DE
DSP_DE
TCK
TDI
TDO
TMS
TRST
TEST
External
Interrupts
Protocol
Timer
Keypad
Port
UART
Queued Serial
Peripheral
Interface
(QSPI)
Smart Card
Port
(SCP)
Serial Audio
Codec Port
(SAP)
Baseband
Codec Port
(BBP)
Emulation
Port
Debug
Control Port
JTAG Test
Access Port
(TAP)
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Power
2.1 Power
The DSP56652 power pins are listed in Table 2-2.
Power Signals
V
CCA
V
CCB
V
CCC
V
CCD
V
CCE
V
CCF
V
CCG
V
CCH
V
CCHQ
V
CCK
V
CCP
V
CCQ
Table 2-2. Power
Description
Address bus power ÑLines C1 and F1 supply isolated power to the address bus drivers.
SIM power ÑLine L8 supplies isolated power for the smart card I/O drivers.
Bus control power ÑLine L3 supplies power to the bus control logic.
Data bus power ÑThese lines supply power to the data bus.
Audio codec port power ÑThis line supplies power to audio codec I/O drivers.
Clock output power ÑThis line supplies a quiet power source for the CKOUT output. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the V
CC
power rail. Use a 0.1 m F bypass capacitor located as close as possible to the chip package to connect between the V
CCF
line and the GND
F
line.
GPIO power ÑThis line supplies power to the GPIO, keypad, data port, interrupts, STO, and
JTAG I/O drivers.
Baseband codec and timer power ÑThis line supplies power to the baseband codec and
Timer I/O drivers.
Quiet power high ÑThese lines supply a quiet power source to the pre-driver voltage converters. This value should be equal to the maximum value of the power supplies of the chip I/O drivers (i.e., the maximum of V
CCA
, V
CCB
, V
CCC
, V
CCD
, V
CCE
, V
CCF
, V
CCG
, V
CCH
, and V
CCK
).
Emulation port power ÑThis line supplies power to the emulation port I/O drivers.
Analog PLL circuit power ÑThis line is dedicated to the analog PLL circuits and must remain noise-free to ensure stable PLL frequency and performance. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the V
CC
power rail. Use a 0.1 m F capacitor and a 0.01 m F capacitor located as close as possible to the chip package to connect between the V
CCP
line and the GND
P
and GND
P1
lines.
Quiet power ÑThese lines supply a quiet power source to the internal logic circuits. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the V
CC
power rail. Use a 0.1 m F bypass capacitor located as close as possible to the chip package to connect between the V
CCQ
lines and the GND
Q
lines.
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Ground
2.2 Ground
The DSP56652 ground pins are listed in Table 2-3.
Table 2-3. Ground
Ground Signals
GND
A
GND
B
GND
C
GND
D
GND
E
GND
F
GND
GND
GND
GND
GND
GND
GND
G
H
K
P
P1
Q
Description
Address bus ground ÑThese lines connect system ground to the address bus.
SIM ground ÑThese lines connect system ground to the smart card bus.
Bus control ground ÑThis line connects ground to the bus control logic.
Data bus ground ÑThese lines connect system ground to the data bus.
Audio codec port ground ÑThese lines connect system ground to the audio codec port.
Clock output ground ÑThis line supplies a quiet ground connection for the clock output drivers.
GPIO ground ÑThese lines connect system ground to GPIO, keypad, data port, interrupts,
STO, and JTAG I/O drivers.
Baseband codec and timer ground ÑThese lines connect system ground to the baseband codec and timer I/O drivers.
Emulation port ground ÑThese lines connect system ground to the emulation port I/O drivers.
Analog PLL circuit ground ÑThis line supplies a dedicated quiet ground connection for the analog PLL circuits.
Analog PLL circuit ground ÑThis line supplies a dedicated quiet ground connection for the analog PLL circuits.
Quiet ground ÑThese lines supply a quiet ground connection for the internal logic circuits.
Substrate ground ÑThese lines must be tied to ground.
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Clock and Phase-Locked Loop
2.3 Clock and Phase-Locked Loop
The pins controlling DSP56652 clocks and PLL are listed in Table 2-4.
Table 2-4. PLL and Clock Signals
Signal Name
CKIH
CKIL
CKO
CKOH
PCAP
Type Reset State Signal Description
Input
Input
Input
Input
High frequency clock input ÑThis input can be connected to either a
CMOS square wave or sinusoid clock source.
Low frequency clock input ÑThis input should be connected to a square wave with a frequency less than or equal to CKIH. This is the default input clock after reset.
Output
Output
Input/
Output
Driven low
Driven low
DSP/MCU output clock ÑThis signal provides an output clock synchronized to the DSP or MCU core internal clock phases, according the selected programming option. The choices of clock source and enabling/disabling the output signal are software selectable.
High frequency clock output ÑThis signal provides an output clock derived from the CKIH input. This signal can be enabled or disabled by software.
Indeterminate PLL capacitor ÑThis signal is used to connect the required external filter capacitor to the PLL filter.
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2.4 External Interface Module
Table 2-5. Address and Data Buses
Signal Name
A0ÐA21
Type Reset State
Output Driven low
D0ÐD15 Input/
Output
Input
Signal Description
Address busÑ These signals specify the address for external memory accesses. If there is no external bus activity, A0ÐA21 remain at their previous values to reduce power consumption.
Data bus ÑThese signals provide the bidirectional data bus for external memory accesses. They remain in their previous logic state when there is no external bus activity to reduce power consumption.
Table 2-6. Bus Control
Signal Name
R/W
Type Reset State
Output Driven high
EB0
EB1
OE
Output
Output
Output
Driven high
Driven high
Driven high
Signal Description
Read/Write ÑThis signal indicates the bus access type. A high signal indicates a bus read. A low signal indicates a write to the bus. This signal can also be used as a memory write enable (WE) signal. When accessing a peripheral chip, the signal acts as a read/write.
Enable Byte 0 ÑWhen driven low, this signal indicates access to data byte 0 (D8ÐD15) during a read or write cycle. This pin may also act as a write byte enable, if so programmed. This output is used when accessing
8-bit wide SRAM.
Enable Byte 1 ÑWhen driven low, this signal indicates access to data byte 1 (D0ÐD7) during a read or write cycle. This pin may also act as a write byte enable, if so programmed. This output is used when accessing
8-bit wide SRAM.
Bus selectÑ When driven low, this signal indicates that the current bus access is a read cycle and enables slave devices to drive the data bus with a read.
Table 2-7. Chip Select Signals
Signal Name
CS0
Type Reset State
Output Chip-driven
CS1ÐCS4
CS5
Output
Output
Driven high
Driven low
Signal Description
Chip Select 0Ñ This signal is asserted low based on the decode of the internal address bus bits A[31:24] and is typically used as the external flash memory chip select. After reset, accesses using CS0 have a default of 15 wait states.
Chip Selects 1Ð4Ñ These signals are asserted low based on the decode of the internal address bus bits A[31:24] of the access address. When not configured as chip selects, these signals become general purpose outputs (GPOs). After reset, these signals are GPOs that are driven high.
Chip Select 5Ñ This signal is asserted high based on the decode of the internal address bus bits A[31:24] of the access address. When not configured as a chip select, this signal functions as a GPO. After reset, this signal is a GPO that is driven low.
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Reset, Mode, and Multiplexer Control
2.5 Reset, Mode, and Multiplexer Control
The reset, mode select, and multiplexer control pins are listed in Table 2-8.
l
Table 2-8. Reset, Mode, and Multiplexer Control Signals
Signal Name
RESET_IN
RESET_OUT
MOD
MUX_CTL
Type
Input
Output
Input
Input
Reset State
Input
Pulled low
Input
Input
Signal Description
Reset Input ÑThis signal is an active low Schmitt trigger input that provides a reset signal to the internal circuitry. The input is valid if it is asserted for at least three CKIL clock cycles.
Note: If MUX_CTL is held high, the RTS signal of the serial data port
(UART) becomes the RESET_IN input line.
(See Table 2-12 on page 2-13.)
Reset Output ÑThis signal is asserted low for at least seven CKIL clock cycles under any one of the following three conditions:
¥ RESET_IN is pulled low for at least three CKIL clock cycles
¥ The alternate RESET_IN signal is enabled by MUX_CTL and is pulled low for at least three CKIL clock cycles
¥ The watchdog count expires.
This signal is asserted immediately after the qualifier detects a valid
RESET_IN signal, remains asserted during RESET_IN assertion, and is stretched for at least seven more CKIL clock cycles after RESET_IN is deasserted. Three CKIL clock cycles before RESET_OUT is deasserted, the MCU boot mode is latched from the MOD signal.
Mode Select ÑThis signal selects the MCU boot mode during hardware reset. It should be driven at least four CKIL clock cycles before
RESET_OUT is deasserted.
¥ MOD driven highÑMCU fetches the first word from internal MCU
ROM.
¥ MOD driven lowÑMCU fetches the first word from external flash memory.
Multiplexer Control ÑThis input allows the designer to select an alternate set of pins to be used for RESET_IN, the debug control port signals, and the JTAG signals as follows:
Interrupt signals
Keypad signals
Serial Data Port
(UART) signals
Normal
(MUX_CTL low)
INT6/STDA/DSR
INT7/SRDA/DTR/SCLK
ROW6/SC2A/DCD
ROW7/SCKA/RI
TxD
RxD/IC1
RTS/IC2A
CTS
Alternate
(MUX_CTL high)
TRST
TMS
DSP_DE
TCK
TDO
TDI
RESET_IN
MCU_DE
STO Output Chip driven Soft Turn Off ÑThis is a GPO pin. Its logic state is not affected by reset.
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Internal Interrupts
2.6 Internal Interrupts
With the exception of alternate signal functions TRST, TMS, and DSP_IRQ, the signals
described in Table 2-9 are GPIO when not programmed otherwise, and default as
general-purpose inputs (GPI) after reset.
Table 2-9. Interrupt Signals
Signal Name Type
Output
Reset State Signal Description
Interrupts 0Ð5
1
ÑThese signals can be programmed as interrupt inputs or GPIO signals. As interrupt inputs, they can be programmed to be level sensitive, positive edge-triggered, or negative edge-triggered.
NormalÑMUX_CTL driven low
STDA
DSR
Output
Output
Output
Interrupt 6
ÑWhen selected, this signal can be programmed as an
interrupt input or a GPIO signal. As an interrupt input, it can be programmed to be level sensitive, positive edge-triggered, or negative edge-triggered.
Audio Codec Serial Transmit Data (alternate)ÑWhen programmed as
STDA, this signal transmits data from the serial transmit shift register in the serial audio codec port.
Note: When this signal functions as STDA, the primary STDA signal is
disabled. (See Table 2-15 on page 2-16.)
Data Set Ready ÑWhen programmed as GPIO output, this signal can be
used as the DSR output for the serial data port. (See Table 2-12.)
AlternateÑMUX_CTL driven high
TRST Input Input Test Reset (alternate) ÑWhen selected, this signal acts as the TRST input for the JTAG test access port (TAP) controller. The signal is a
Schmitt trigger input that asynchronously initializes the JTAG test controller when asserted.
Note: When this signal is enabled, the primary TRST signal is
disconnected from the TAP controller. (See Table 2-19 on page 2-19.)
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Protocol Timer
Table 2-9. Interrupt Signals (Continued)
Signal Name Type Reset State Signal Description
NormalÑMUX_CTL driven low
INT7
SRDA
DTR
SCLK
Input or
Output
Input
Input
Input
Input
Interrupt 7
ÑWhen selected, this signal can be programmed as an
interrupt input or a GPIO signal. As an interrupt input, it can be programmed to be level sensitive, positive edge-triggered, or negative edge-triggered.
Audio Codec Serial Receive Data (alternate)ÑWhen programmed as
SRDA, this signal receives data into the serial receive shift register in the serial audio codec port.
Note: When this signal is used as SRDA, the primary SRDA signal is
disabled. (See Table 2-15 on page 2-16.)
Data Terminal Ready ÑWhen programmed as GPIO, this signal is used as the DTR positive and negative edge-triggered interrupt input for the
serial data port. (See Table 2-12 on page 2-13.)
Serial Clock ÐThis signal provides the input clock for the serial data port
(UART). (See Table 2-12 on page 2-13.)
AlternateÑMUX_CTL driven high
TMS Input Input Test Mode Select (alternate) ÑThis signal is the TMS input for the
JTAG test access port (TAP) controller. TMS is used to sequence the
TAP controller state machine. It is sampled on the rising edge of TCK.
Note: When this signal is enabled, the primary TMS signal is
disconnected from the TAP controller. See Table 2-19 on page 2-19
DSP_IRQ Input Input DSP External Interrupt Request ÑThis active low Schmitt trigger input can be programmed as a level-sensitive or negative edge-triggered maskable interrupt request input during normal instruction processing. If the DSP is in the STOP state and DSP_IRQ is asserted, the DSP exits the STOP state.
1.
As Schmitt trigger interrupt inputs, these signals can be programmed to be level sensitive, positive edge-triggered, or negative edge-triggered. An edge-triggered interrupt is initiated when the input signal reaches a particular voltage level, regardless of the rise or fall time. However, as signal transition time increases, the probability of noise generating extraneous interrupts also increases.
2.7 Protocol Timer
Table 2-10 describes the eight Protocol Timer signals.
Name
TOUT0Ð
TOUT7
Table 2-10. Protocol Timer Output Signals
Type Reset State
Input or
Output
Input
Signal Description
Timer Outputs 0Ð7Ñ These timer output signals can also be configured as GPIO. The default function after reset is GPI.
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Keypad Port
2.8 Keypad Port
With the exception of alternate signal functions DSP_DE and TCK, the signals described
in Table 2-11 are GPIO when not programmed otherwise and default as GPI after reset.
t
Table 2-11. Keypad Port Signals
Signal Name Type Reset State
COL0ÐCOL5 Input or
Output
COL6
Input
OC1
Input or
Output
Output
Input
Signal Description
Column Strobe 0Ð5Ñ As keypad column strobes, these signals can be programmed as regular or open drain outputs.
Column Strobe 6Ñ As a keypad column strobe, this signal can be programmed as regular or open drain output.
MCU Timer Output Compare 1 ÑThis signal is the MCU timer output compare 1 signal.
COL7
PWM
ROW0Ð
ROW4
ROW5
IC2
Input or
Output
Output
Input
Input or
Output
Input
Input or
Output
Input
Input
Programming of this signal function is performed using the general port control register and the keypad control register.
Column Strobe 7Ñ As a keypad column strobe, this signal can be programmed as regular or open drain output.
PWM Output
Note: Programming of this signal function is performed using the general port control register and the keypad control register.
Row Sense 0Ð4Ñ These signals function as keypad row senses.
Row Sense 5Ñ This signal functions as a keypad row sense.
MCU Timer Input Capture 2 ÑThis signal is the input capture for the
MCU input capture 2 timer.
Note: Programming of this signal function is performed using the general port control register.
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Keypad Port
Table 2-11. Keypad Port Signals (Continued)
Signal Name Type Reset State
NormalÑMUX_CTL driven low
ROW6
SC2A
Input or
Output
Input or
Output
Input
DCD Output
Signal Description
Row Sense 6Ñ This signal functions as a keypad row sense.
Audio Codec Serial Control 2 (alternate) ÑThis signal provides I/O frame synchronization for the serial audio codec port. In synchronous mode, the signal provides the frame sync for both the transmitter and receiver. In asynchronous mode, the signal provides the frame sync for the transmitter only.
Note: When this signal is used as SC2A, the primary SC2A signal is
disabled. (See Table 2-15 on page 2-16.)
Data Carrier Detect ÑThis signal can be used as the DCD output for the
serial data port. (See Table 2-12 on page 2-13.)
Note: Programming of these functions is done through the general port control register and the SAP control register.
AlternateÑMUX_CTL driven high
DSP_DE Input or
Output
Input Digital Signal Processor Debug Event ÑThis signal functions as
DSP_DE. In normal operation, DSP_DE is an input that provides a means to enter the debug mode of operation from an external command converter. When the DSP enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts DSP_DE as an output signal for three clock cycles to acknowledge that it has entered debug mode.
Note: When this signal is enabled, the primary DSP_DE signal is disabled.
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Keypad Port
Table 2-11. Keypad Port Signals (Continued)
Signal Name Type Reset State
NormalÑMUX_CTL driven low
ROW7
SCKA
Input or
Output
Input
Input
RI Output
Signal Description
Row Sense 7Ñ This signal functions as a keypad row sense.
Audio Codec Serial Clock (alternate) ÑThis signal provides the serial bit rate clock for the serial audio codec port. In synchronous mode, the signal provides the clock input or output for both the transmitter and receiver. In asynchronous mode, the signal provides the clock for the transmitter only.
Note: When this signal is used as SCKA, the primary SCKA signal is
disabled. (See Table 2-15 on page 2-16.)
Ring Indicator ÑThis signal can be used as the RI output for the serial
data port. (See Table 2-12 on page 2-13.)
Note: Programming of these functions is done through the general port control register and the SAP control register.
AlternateÑMUX_CTL driven high
TCK Input Input Test Clock (alternate) ÑThis signal provides the TCK input for the JTAG test access port (TAP) controller. TCK is used to synchronize the JTAG test logic.
Note: When this signal is enabled, the primary TCK signal is
disconnected from the TAP controller. (See Table 2-19 on page 2-19.)
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UART
2.9 UART
With the exception of alternate signal functions TDO, TDI, RESET_IN, and MCU_DE,
the signals described in Table 2-12 are GPIO when not programmed otherwise and default
as GPI after reset.
The remaining UART signals can be implemented with GPIO pins. Suggested allocations include the following:
¥
DSRÑalternate function for INT6. (See Table 2-9 on page 2-8.)
¥
DTRÑalternate function for INT7. (See Table 2-9 on page 2-8.)
¥
DCDÑalternate function for ROW6. (See Table 2-11 on page 2-10.)
¥
RIÑalternate function for ROW7. (See Table 2-11 on page 2-10.)
Table 2-12. UART Signals
Signal Name Type Reset State
NormalÑMUX_CTL driven low
TxD Input or
Output
Input
AlternateÑMUX_CTL driven high
TDO Output
Signal Description
UART TransmitÑ This signal transmits data from the UART.
Test Data Output (alternate) ÑThis signal provides the TDO serial output for test instructions and data from the JTAG TAP controller. TDO is a tri-state signal that is actively driven in the shift-IR and shift-DR controller states.
Note: When this signal is enabled, the primary TDO signal is
disconnected from the TAP controller. (See Table 2-19 on page 2-19.)
NormalÑMUX_CTL driven low
RxD
IC1
Input or
Output
Input
Input UART ReceiveÑ This signal receives data into the UART.
MCU Timer Input Capture 1 ÑThe signal connects to an input capture/output compare timer used for autobaud mode support.
AlternateÑMUX_CTL driven high
TDI Input Input Test Data In (alternate) ÑThis signal provides the TDI serial input for test instructions and data for the JTAG TAP controller. TDI is sampled on the rising edge of TCK.
Note: When this signal is enabled, the primary TDI signal is
disconnected from the TAP controller. (See Table 2-19 on page 2-19.)
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UART
Table 2-12. UART Signals (Continued)
Signal Name Type Reset State
NormalÑMUX_CTL driven low
RTS
IC2
Input or
Output
Input
Input
Signal Description
Request To SendÑ This signal functions as the UART RTS signal.
MCU Timer Input Capture 2 ÑThis signal connects to an input capture timer channel.
AlternateÑMUX_CTL driven high
RESET_IN Input Input Reset Input ÑThis signal is an active low Schmitt trigger input that provides a reset signal to the internal circuitry. The input is valid if it is asserted for at least three CKIL clock cycles.
Note: When this signal is enabled, the primary RESET_IN signal is
disabled. (See Table 2-8 on page 2-7.)
NormalÑMUX_CTL driven low
CTS Input or
Output
Input
AlternateÑMUX_CTL driven high
MCU_DE Input or
Output
Clear To SendÑ This signal functions as the UART CTS signal.
Microcontroller Debug Event ÑAs an input, this signal provides a means to enter the debug mode of operation from an external command converter.
As an output signal, it acknowledges that the MCU has entered the debug mode. When the MCU enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts
MCU_DE as an output signal for several clock cycles.
Note: When this signal is enabled, the primary MCU_DE signal is disabled.
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QSPI
2.10 QSPI
The signals described in Table 2-13 are GPIO when not programmed otherwise and
default as GPI after reset.
Table 2-13. QSPI Signals
Signal Name
SPICS0Ð
SPICS4
Type Reset State
Output Input
SCK
MISO
MOSI
Output
Input
Output
Input
Input
Input
Signal Description
Serial Peripheral Interface Chip Select 0Ð4 ÑThese output signals provide chip select signals for the QSPI. The signals are programmable as active high or active low.
Serial Clock ÑThis output signal provides the serial clock from the QSPI for the accessed peripherals. The delay (number of clock cycles) between the assertion of the chip select signals and the first transmission of the serial clock is programmable. The polarity and phase of SCK are also programmable.
Synchronous Master In Slave Out ÑThis input signal provides serial data input to the QSPI. Input data can be sampled on the rising or falling edge of SCK and received in QSPI RAM most significant bit or least significant bit first.
Synchronous Master Out Slave In ÑThis output signal provides serial data output from the QSPI. Output data can be sampled on the rising or falling edge of SCK and transmitted most significant bit or least significant bit first.
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SCP
2.11 SCP
The signals described in Table 2-14 are GPIO when not programmed otherwise, and
default as GPI after reset.
Table 2-14. SCP Signals
Signal Name
SIMCLK
Type Reset State
Output Input
SENSE
SIMDATA
SIMRESET
PWR_EN
Input
Input or
Output
Output
Input
Input
Input
Output Input
Signal Description
SIM ClockÑ This signal is an output clock from the SCP to the smart card.
SIM SenseÑ This signal is a Schmitt trigger input that signals when a smart card is inserted or removed.
SIM DataÑ This bidirectional signal is used to transmit data to and receive data from the smart card.
SIM ResetÑ The SCP can activate the reset of an inserted smart card by driving SIMRESET low.
SIM Power EnableÑ This active high signal enables an external device that supplies V
CC
to the smart card, providing effective power management and power sequencing for the SIM. If the port drives this signal high, the external device supplies power to the smart card. Driving the signal low disables power to the card.
2.12 SAP
The signals described in Table 2-15 are GPIO when not programmed otherwise and
default as GPI after reset.
Note: SAP signals STDA, SRDA, SCKA, and SC2A have alternate functions (as
described in Table 2-9 on page 2-8 and Table 2-11 on page 2-10). When those
alternate functions are selected, the SAP signals are disabled.
Table 2-15. SAP Signals
Signal Name
STDA
Type Reset State
Output Input
SRDA
SCKA
SC0A
Input
Input or
Output
Input or
Output
Input
Input
Input
Signal Description
Audio Codec Transmit Data ÑThis output signal transmits serial data from the audio codec serial transmitter shift register.
Audio Codec Receive Data ÑThis input signal receives serial data and transfers the data to the audio codec receive shift register.
Audio Codec Serial Clock ÑThis bidirectional signal provides the serial bit rate clock. It is used by both transmitter and receiver in synchronous mode or by the transmitter only in asynchronous mode.
Audio Codec Serial Clock 0Ñ This signalÕs function is determined by the transmission mode.
¥ Synchronous modeÑserial I/O flag 0
¥ Asynchronous modeÑ receive clock I/O
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SAP
Table 2-15. SAP Signals (Continued)
Signal Name
SC1A
Type Reset State
Input or
Output
Input
SC2A Input or
Output
Input
Signal Description
Audio Codec Serial Clock 1Ñ This signalÕs function is determined by the transmission mode.
¥ Synchronous modeÑserial I/O flag 1
¥ Asynchronous modeÑreceiver frame sync I/O
Audio Codec Serial Clock 2Ñ This signalÕs function is determined by the transmission mode.
¥ Synchronous modeÑtransmitter and receiver frame sync I/O
¥ Asynchronous modeÑtransmitter frame sync I/O
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BBP
2.13 BBP
The signals described in Table 2-16 are GPIO when not programmed otherwise and
default as GPI after reset.
Table 2-16. BBP Signals
Signal Name
STDB
Type Reset State
Output Input
SRDB
SCKB
SC0B
SC1B
SC2B
Input
Input or
Output
Input or
Output
Input or
Output
Input or
Output
Input
Input
Input
Input
Input
Signal Description
Baseband Codec Transmit Data ÑThis output signal transmits serial data from the baseband codec serial transmitter shift register.
Baseband Codec Receive Data ÑThis input signal receives serial data and transfers the data to the baseband codec receive shift register.
Baseband Codec Serial Clock ÑThis bidirectional signal provides the serial bit rate clock. It is used by both transmitter and receiver in synchronous mode or by the transmitter only in asynchronous mode.
Baseband Codec Serial Clock 0Ñ This signalÕs function is determined by the SCLK mode.
¥ Synchronous modeÑserial I/O flag 0
¥ Asynchronous modeÑreceive clock I/O
Baseband Codec Serial Clock 1Ñ This signalÕs function is determined by the SCLK mode.
¥ Synchronous modeÑserial I/O flag 0
¥ Asynchronous modeÑreceiver frame sync I/O
Baseband Codec Serial Clock 2Ñ This signalÕs function is determined by the SCLK mode.
¥ Synchronous modeÑtransmitter and receiver frame sync I/O
¥ Asynchronous modeÑtransmitter frame sync I/O
2.14 MCU Emulation Port
The signals described in Table 2-17 are GPIO when not programmed otherwise and
default as GPI after reset.
Table 2-17. Emulation Port Signals
Signal Name
SIZ0ÐSIZ1
Type Reset State
Output Input
PSTAT0Ð
PSTAT3
Output Input
Signal Description
Data Size ÑThese output signals encode the data size for the current
MCU access.
Pipeline State ÑThese output signals encode the internal MCU execution status.
2.15 Debug Port Control
The signals described in Table 2-18 are GPIO when not programmed otherwise and
default as GPI after reset.
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JTAG Test Access Port
Table 2-18. Debug Control Signals
Signal Name
MCU_DE
Type Reset State
Input or
Output
Input
Signal Description
Microcontroller Debug Event ÑAs an input, this signal provides a means to enter the debug mode of operation from an external command converter.
DSP_DE Input or
Output
Input
As an output signal, it acknowledges that the MCU has entered the debug mode. When the MCU enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts
MCU_DE as an output signal for several clock cycles.
Digital Signal Processor Debug Event ÑThis signal functions as
DSP_DE. In normal operation, DSP_DE is an input that provides a means to enter the debug mode of operation from an external command converter. When the DSP enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts DSP_DE as an output signal for three clock cycles to acknowledge that it has entered debug mode.
2.16 JTAG Test Access Port
When the bottom connector pins are selected by holding the MUX_CTL pin at a logic high, all JTAG pins become inactive, i.e., disconnected from the JTAG TAP controller.
Table 2-19. JTAG Port Signals
Signal Name
TMS
TDI
TDO
TCK
TRST
TEST
Type
Input
Input
Output
Input
Input
Input
Reset State
Input
Input
Tri-stated
Input
Input
Input
Signal Description
Test Mode Select ÑTMS is an input signal used to sequence the test controllerÕs state machine. TMS is sampled on the rising edge of TCK.
Test Data Input ÑTDI is an input signal used for test instructions and data. TDI is sampled on the rising edge of TCK.
Test Data Output ÑTDO is an output signal used for test instructions and data. TDO can be tri-stated and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK.
Test Clock ÑTCK is an input signal used to synchronize the JTAG test logic.
Test Reset ÑTRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller.
Factory Test Mode ÑSelects factory test mode. Reserved.
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Chapter 3
Memory Maps
This section describes the internal memory map of the DSP56652. The memory maps for
MCU and DSP are described separately.
3.1 MCU Memory Map
The MCU side of the DSP56652 has a single, contiguous memory space with four separate partitions:
¥ Internal ROM
¥ Internal RAM
¥ Memory-mapped peripherals
¥ External memory space
These spaces are shown in Figure 3-1 on page 3-2.
3.1.1 ROM
The MCU memory map allocates 1 Mbyte for internal ROM. The actual ROM size is
16 kbytes, starting at address $0000_0000, and is modulo-mapped into the remainder of the 1 Mbyte space. Read access to internal ROM space returns the transfer acknowledge
(TA) signal except in user mode while supervisor protection is active, in which case a transfer error acknowledge signal (TEA) is returned, resulting in termination and an access error exception. Any attempt to write to the MCU ROM space also returns TEA.
Software should not rely on modulo-mapping because future DSP5665 x chip implementations may behave differently.
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MCU Memory Map
Base Address
$FFFF_FFFF
Reserved
$4600_0000
External Memory
6 x 16 Mbytes Allocated
6 x 4 Mbytes Addressable
$4000_0000
CS5
CS4
CS3
CS2
CS1
CS0
$4500_0000
$4400_0000
$4300_0000
$4200_0000
$4100_0000
$4000_0000
$0040_0000
$0020_0000
$0010_0000
$0000_0000
Reserved (12M)
Peripherals (2M)
2 kbytes Internal RAM,
Modulo-Mapped in
1 Mbyte Space
16 kbytes Internal ROM,
Modulo-Mapped in
1 Mbyte Space
Reserved
General Port Control
Emulation Port Control
RSR Register
CKCTL Register
SIM Card
Keypad/GPIO
Interrupt Pins Control
Watchdog Timer
PIT
MCU Timers/PWM
QSPI
UART
Protocol Timer
MDI
External Interface Module
Interrupt Controller
$0020_6000
$0020_5000
$0020_4000
$0020_3000
$0020_2000
$0020_1000
$0020_0000
$0020_D000
$0020_CC00
$0020_C800
$0020_C400
$0020_C000
$0020_B000
$0020_A000
$0020_9000
$0020_8000
$0020_7000
Figure 3-1. MCU Memory Map
3.1.2 RAM
The MCU memory map allocates 1 Mbyte for internal RAM. The actual size of the RAM is 2 KB, starting at address $0010_0000, and is modulo-mapped into the remainder of the
1 Mbyte space. Read and write access to internal RAM space returns TA except in user
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MCU Memory Map mode while supervisor protection is active, in which case TEA is returned, resulting in termination and an access error exception. Software should not rely on modulo-mapping because future DSP5665 x chip implementations may behave differently.
3.1.3 Memory-Mapped Peripherals
Interface requirements for MCU peripherals are defined to simplify the hardware interface implementation while providing a reasonable and extendable software model. The following requirements are currently defined (others may be added in the future):
¥ A given peripheral device appears only in the 4-kbytes region(s) allocated to it.
¥ For on-chip devices, registers are defined to be 16 or 32 bits wide. For registers that do not implement all 32 bits, the unimplemented bits return zero when read, and writes to unimplemented bits have no effect. In general, unimplemented bits should be written to zero to ensure future compatibility.
¥ All peripherals define the exact results for 32-bit, 16-bit, and 8-bit accesses, according to individual peripheral definitions. Misaligned accesses are not supported, nor is bus sizing performed for accesses to registers smaller than the access size.
The MCU memory map allocates 2 Mbyte for internal MCU peripherals starting at address $0020_0000. Twelve of the sixteen DSP56652 peripherals are allocated 4 kbytes each, and four peripherals are allocated 1 kbyte each for a total of 52 kbytes. The remainder of the 2-Mbyte space is reserved for future peripheral expansion.
Each peripheral space may contain several registers. Details of these registers are located in the respective peripheral description sections. Software should explicitly address these registers, making no assumptions regarding modulo-mapping. A complete list of these
registers and their addresses is given in Table D-8 on page D-14.
Read accesses to unmapped areas within the first 52 kbytes of peripheral address space returns the TA signal if supervisor permission allows. Uninitialized write accesses within the first 52 kbytes also return the TA signal and may alter the peripheral register contents.
Any attempted access within the reserved portion of the peripheral memory space
($0020_D000 to $003F_FFFF) results in TEA termination and an access error exception from an EIM watchdog time-out after 128 MCU clock cycles.
3.1.4 External Memory Space
The MCU memory map allocates 96 Mbytes for external chip access, starting at address
$4000_0000. Six external chip selects are allocated 16 Mbytes each. Only the first
4Mbytes in each 16-Mbyte space are addressable by the 22 address lines A0ÐA21. An
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DSP Memory Map and Descriptions access to an address more than 4 Mbytes above the chip select base address is
modulo-mapped into the first 4 Mbytes. See Table 6-2 on page 6-4
, for more information regarding this portion of the memory map.
3.1.5 Reserved Memory
Two portions of the MCU memory map are reserved: $0040_0000 to $3FFF_FFFF, and
$4600_0000 to $FFFF_FFFF. Any attempted access within these reserved portions of the memory space results in TEA termination and an access error exception from an EIM watchdog time-out after MCU 128 clock cycles.
3.2 DSP Memory Map and Descriptions
The DSP56652 DSP core contains three distinct memory spaces:
¥ X data memory space
¥ Y data memory space
¥ program (P) memory space
Each of these spaces contains both RAM and ROM. In addition, the X data space has partitions for peripherals and the MCU-DSP interface (MDI). All memory on the DSP side is contained on-chipÑthere is no provision for connection to external memory.
The three memory spaces are shown in Figure 3-2.
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DSP Memory Map and Descriptions
$FFFF
$FF80
X Data (16-Bit)
Internal X-I/O
$FFFF
Y Data (16-Bit)
$FFFF
Program (24-Bit)
Reserved (14K)
$C800
Internal Ð
Reserved (22K)
Internal Ð
Reserved (~22K)
$A800 $A800
48K Internal
P ROM
10K Internal
X ROM
10K Internal
Y ROM
$8000 $8000
$2000
Internal Ð
Reserved (24K)
MDI
RAM (1K)
7K Internal
X RAM
$1800
Internal Ð
Reserved (26K)
6K Internal
Y RAM
$0800
$1C00
$0200
InternalÐ
Reserved (0.5K)
0.5K Internal
P RAM
$0000 $0000
Figure 3-2. DSP Memory Map
$0000
3.2.1 X Data Memory
X data RAM is a 16-bit-wide, internal, static memory occupying the lowest 8K locations in X memory space. The upper 1K of this space (X:$1C00Ð1CFF) is dedicated to the
MDI.
X data ROM is a 16-bit-wide, internal, static memory occupying 10K located at
X:$8000Ð$A7FF.
The top 128 locations of the X data memory ($FF80Ð$FFFF) contain the DSP-side peripheral registers and addressable core registers. This area, referred to as X-I/O space, can be accessed by MOVE, MOVEP, and the bit-oriented instructions (BCHG, BCLR,
BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR and JSSET). The
specific addresses for DSP registers are listed in Table D-9 on page D-19.
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DSP Memory Map and Descriptions
3.2.2 Y Data Memory
Y data RAM is a 16-bit-wide, internal, static memory occupying the lowest 6K locations in Y memory space, Y:$0000Ð$17FF.
Y data ROM is a 16-bit-wide, internal, static memory occupying 10K locations in
Y memory space at Y:$8000Ð$A7FF.
3.2.3 Program Memory
Program RAM is a 24-bit-wide, high-speed, static memory occupying the lowest 512 locations in the P memory space, P:$0000Ð$01FF.
Program ROM is a 24-bit-wide, internal, static memory occupying 48K locations at
P:$0800Ð$C7FF. The first 1K of this space (P:$0800Ð$0BFF) contains factory code that enables the user to download code to program RAM via the MDI. This code is described
and listed in Appendix A, ÒDSP56652 DSP BootloaderÓ.
3.2.4 Reserved Memory
All memory locations not specified in the above description are reserved and should not be accessed. These areas include the following:
¥ X:$2000Ð$7FFF and X:$A800Ð$FF7F
¥ Y:$1800Ð$7FFF and Y:$A800Ð$FFFF
¥ P:$0200Ð$07FF and P:$C800Ð$FFFF.
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Chapter 4
Core Operation and Configuration
This section describes features of the DSP56652 not covered by the sections describing individual peripherals. These features include the following:
¥ Clock configurations for both the MCU and DSP
¥ Low power operation
¥ Reset
¥ DSP featuresÑoperating mode, patch addresses, and device identification.
¥ I/O/ multiplexing
4.1 Clock Generation
Two internal processor clocks, MCU_CLK and DSP_CLK, drive the MCU and DSP cores respectively. Each of these clocks can be derived from either the CKIH or CKIL clock input pins. Both pins should be driven, even if one input is used for both internal clocks.
¥ CKIH is typically in the frequency range of 10Ð20 MHz. The DSP56652 converts
CKIH to a buffered CMOS square wave which can be brought out externally on the
CKOH pin by clearing the CKOHD bit in the Clock Control Register (CKCTL).
The buffer can be disabled by setting the CKIHD bit in the CKCTL, but only if
MCU_CLK is driven by CKIL.
¥ CKIL is usually a 32.768 kHz square wave input.
The frequency of each core clock can be adjusted by manipulating control register bits.
At reset, the MCU_CLK is output on the CKO pin. Software can change the output to
DSP_CLK by setting the CKOS bit in the CKCTL. The CKO pin can be disabled by setting the CKOD bit in the CKCTL.
The DSP56652 clock scheme is shown in Figure 4-1.
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Clock Generation
CKIHD Buffered CKIH
DSP
Peripherals
CKIH
CKOH
Sine-to-CMOS
CKOHD
DSP
Selector
DSP
PLL
Ö2n
Power-On-Reset
Logic
DCS_REF
DSP
Clock
Generator
Ö2
DCS
DSP_CLK
CKIL
MCU
Peripherals
MCS
MCU
Selector
MCU Clock Divider
(Ö2n; n=0Ð4)
MCU_CLK
CKOD
MCD[0:2]
CKO
CKO
Selector
CKOS
Figure 4-1. DSP56652 Clock Scheme
4.1.1 MCU_CLK
MCU_CLK is driven by either CKIL or (buffered) CKIH, according to the MCS bit in the
CKCTL. The input is divided by a power of 2 (i.e., 1, 2, 4, 8 or 16) selected by the MCD bits in the CKCTL. The divider has two outputs, one for the core clock and one for peripherals, to support various low-power modes. MCU peripherals use a combination of
CKIL, CKIH, and MCU_CLK, as shown in Table 4-1.
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Clock Generation
Table 4-1. MCU and MCU Peripherals Clock Source
Peripheral Peripheral Clock Source
MCU
Protocol Timer
QSPI
UART
Interrupt Controller
MCU Timers
Watchdog Timer
O/S Interrupt (PIT)
GPIO/Keypad
SCP
MCU_CLK
MCU_CLK
MCU_CLK
CKIH (MCU_CLK for interface to MCU)
Serial clock should be slower than MCU_CLK by 1:4 rate.
MCU_CLK
MCU_CLK
CKIL (MCU_CLK for interface to MCU)
CKIL (MCU_CLK for interface to MCU)
MCU_CLK (CKIL for interrupt debouncer)
CKIH (MCU_CLK for interface to MCU)
Serial clock should be slower than or equal to MCU_CLK.
4.1.2 DSP_CLK
The DSP clock input, DSP_REF, is selected from either CKIL or (buffered) CKIH by the
DCS bit in the CKCTL. DSP_REF drives the DSP clock generator either directly or through a PLL, according to the PEN bit in PLL Control Register 1 (PCTL1). The clock generator divides its input by two and puts out the core DSP_CLK signal and a two-phase
clock to drive peripherals. DSP peripherals can also use CKIH as an input. Figure 4-2 is a
block diagram of the DSP clock system.
DSP_REF
Predivider
Fext
Fext
PLL
PLL Loop
Frequency
Multiplication
Fext¥MF¥2
PLL
Out
PDF: 1 to 128 MF: 1 to 4096
Low Power
Divider
PEN=0
Fext¥MF¥2
PDF¥DF
PEN=1
Ö 2
DF: 20 to 27
CLKGEN
COD
2-Phase
Chip
Clock
DSP_REF
PVCC
+
PGND PVCC PCAP
Figure 4-2. DSP PLL and Clock Generator
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Clock Generation
When the PLL is enabled, its input is divided by a predivide factor (PD bits in PCTL1 and
PCTL0) and another divide factor (DF bits in PCTL1) which is intended to decrease the
DSP_CLK frequency in low power modes. The DF bits can be adjusted without losing
PLL lock. The PLL also multiplies the input by a factor determined by the MF bits in
PCTL0. The PLL output frequency is
PLLOUT = DSP_REF
´
MF
´
2
¾¾¾¾¾¾¾¾¾
PD
´
DF and the clock generator output frequency is
DSP_CLK = DSP_REF
´
MF
PD
´
DF
The PLL can be bypassed by clearing the PEN bit in PCTL1. It can also be disabled in low power modes by clearing the PSTP bit in PCTL1. In either case, the clock generator output is
DSP_CLK = DSP_REF
¾¾¾¾¾
2
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Clock Generation
4.1.3 Clock and PLL Registers
CKCTL
BIT 15 14
RESET 0 0
13
0
12
0
11
Clock Control Register
10 9 8 7 6 5
DCS CKOHD CKOD CKOS
0 0 0 0 0 0 0
Table 4-2. CKCTL Description
4 3
MCD[2:0]
2
$0020_C000
1 BIT 0
MCS CKIHD
1 0 0 0 0
Description Settings Name
DCS
Bit 8
CKOHD
Bit 7
CKOD
Bit 6
CKOS
Bit 5
MCD[2:0]
Bits 4Ð2
DSP Clock SelectÑ Selects the input to the DSP clock generator.
0 = CKIH (default).
1 = CKIL.
CKOH DisableÑ
CKOH pin.
Controls the output at the
CKO DisableÑ Controls the output of the CKO pin.
CKO Source SelectÑ Selects the clock to be reflected on the CKO pin.
MCU Clock Divide factorÑ Selects the divisor for the MCU clock.
0 = CKOH is a buffered CKIH (default).
1 = CKOH held low.
0 = CKO outputs either MCU_CLK or DSP_CLK according to CKOS bit (default).
1 = CKO held high.
0 = MCU_CLK (default).
1 = DSP_CLK.
MCD[2:0]
$0
$1
$2
$3
$4
$5...$7
Divisor
4
8
1
2
16
Reserved
MCS
Bit 1
CKIHD
Bit 0
MCU Clock SelectÑ Determines MCU clock input
CKIH DisableÑ Controls the CKIH input buffer
0 = CKIL (default).
1 = CKIH.
0 = Buffer enabled (default).
1 = Buffer disabled if MCS is cleared.
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Clock Generation
PCTL0
BIT 15 14
RESET 0
Name
PD[3:0]
Bits 15Ð12
MF[11:0]
Bits 11Ð0
0
13
PD[3:0]
0
12
0
11
PLL Control Register 0
10 9 8 7 6 5
MF[11:0]
0 0 0 0 0 0 0
Table 4-3. PCTL0 Descriptions
Description
Predivider Factor BitsÑ Concatenated with
PD[6:4] (PCTL1 bits 11Ð9) to define the PLL input PDF.
Multiplication Factor BitsÑ Define the MF applied to the PLL input frequency.
4
0
3
0
Settings
MF[11:0]
$000
$001
$002
.
.
.
$FFE
$FFF
2
0
MF
1 (default)
2
3
.
.
.
4095
4096
X:$FFFD
1 BIT 0
0 0
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Clock Generation
PCTL1
BIT 15 14
RESET 0 0
13
0
12
0
11
PLL Control Register 1
10
PD[6:4]
9 8 7 6 5 4 3
COD PEN PSTP XTLD XTLR
0 0 0 0 0 0 1 0
Table 4-4. PCTL1 Description
Settings
2
0
X:$FFFC
1 BIT 0
DF[2:0]
0 0
Name Description
PD[6:4]
Bits 11Ð9
Predivider FactorÑ Concatenated with PD[3:0] from PCTL0 to define the PLL input frequency divisor. The divisor is equal to one plus the value of PD[6:0].
PD[6:0] PLL Divisor
$00
$01
1 (default)
2
- - -
$7F 128
COD
Bit 7
PEN
Bit 6
PSTP
Bit 5
Clock Output DisableÑ This bit disconnects DSP_CLK from the CKO pin in some implementations.
In the DSP56652 this bit has no effect.
PLL EnableÑ Enables PLL operation. Disabling the PLL shuts down the VCO and lowers power consumption. The PEN bit can be set or cleared by software any time during the chip operation.
0 = PLL is disabled (default). DSP_CLK is derived directly from DSP_REF.
1 = PLL is enabled. DSP_CLK is derived from the PLL VCO output.
STOP Processing StateÑ Controls the behavior of the PLL during the STOP processing state.
Shutting down the PLL in STOP mode decreases power consumption but increases recovery time.
0 = Disable PLL in STOP mode (default).
1 = Enable PLL in STOP mode.
These bits affect the on-chip crystal oscillator in certain implementations. They are not used in the
DSP56652.
XTLD,
XTLR
Bits 4Ð3
DF[2:0]
Bits 2Ð0
Division FactorÑ Internal clock divisor that determines the frequency of the low-power clock.
Changing the value of the DF bits does not cause a loss of lock condition. These bits should be changed rather than MF[11:0] to change the clock frequency (e.g., when entering a low-power mode to conserve power).
DF[2:0]
000
001
111
- - -
DF
2
0
(default)
2
1
2
7
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Low Power Modes
4.2 Low Power Modes
The DSP56652 features several modes of operation to conserve power under various conditions. Each core can run independently in either the normal, WAIT, or STOP mode.
The MCU can also run in the DOZE mode, which operates at an activity level between
WAIT and STOP. Each low-power mode is initiated by a software instruction, and terminated by an interrupt. The wake-up interrupt can come from any running peripheral.
In STOP mode, certain stopped peripherals can also generate a wake-up interrupt.
Peripheral operation in low power modes for the MCU and DSP is summarized in
Table 4-5 and Table 4-6, respectively.
Table 4-5. MCU Peripherals in Low Power Mode
Peripheral Normal WAIT DOZE
MCU
Protocol Timer
QSPI
UART
Interrupt Controller
MCU Timers
Watchdog Timer
PIT (O/S interrupt)
GPIO/Keypad
MDI (MCU side)
SCP
JTAG/OnCE
External interrupt
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
STOP
Stopped Stopped
Programmable Stopped
Programmable Stopped
Programmable Stopped; can trigger wake-up
Running Stopped; can trigger wake-up
Programmable Stopped
Programmable Stopped
Running Running
Running Stopped; can trigger wake-up
Programmable Stopped; can trigger wake-up
Programmable Stopped
Programmable Stopped; can trigger wake-up
Running Stopped; can trigger wake-up
MDI (DSP side)
BBP
SAP
Table 4-6. DSP Peripherals in Low Power Modes
Peripheral Normal WAIT
Running
Running
Running
Running
Running
Running
STOP
Stopped; can trigger wake-up
Stopped
Stopped
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Reset
For further power conservation, any running peripheral in a given mode, as well as the
features summarized in Table 4-7, can be explicitly disabled by software.
Table 4-7. Programmable Power-Saving Features
Description Register Reference
Disable CKOH
Disable CKO
Disable CKIH buffer
Disable DSP_CLK
Disable PLL
Disable PLL in STOP mode bit 6 bit 0 bit 6 bit 5
4.3 Reset
Four events can cause a DSP56652 reset:
1. Power-on reset
2. RESET_IN pin is asserted
3. Bottom connector RTS pin (acting as RESET_IN) is asserted
4. Watchdog timer times out
Reset from power-on or the watchdog timer time-out is immediately qualified. An input circuit qualifies the RESET_IN signal from either pin, based on the duration of the signal in CKIL clock cycles:
¥ 2 cyclesÑnot qualified
¥ 3 cyclesÑmay or may not be qualified
¥ 4 cyclesÑqualified
A qualified reset signal asserts the RESET_OUT signal, and the following reset conditions are established:
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Reset
¥ All peripherals and both cores are initialized to their default values.
¥ Both MCU_CLK and DSP_ CLK are derived from CKIL.
¥ The CKO pin is enabled, driving MCU_CLK.
¥ The CKIH CMOS converter is enabled, and drives the CKOH pin.
An eight-cycle ÒstretchÕ circuit guarantees that RESET_OUT is asserted for at least eight
CKIL clock cycles. This circuit also stretches the negation of RESET_OUT. (The precise time between the negation of RESET_IN and RESET_OUT is between seven and eight
CKIL cycles.) Four cycles before RESET_OUT is negated, the MOD pin is latched. This externally-driven pin determines whether the first instruction is fetched from internal
MCU ROM or external flash memory connected to CS0, as described in Section 4.3.1 on page 4-11.
Reset timing is illustrated in Figure 4-3.
RESET_OUT
Pin
Low-Frequency Reference
RESET_IN
(LV Detector In)
Pin
3 Cycle
Qualified
4 Cycle
Stretcher
4 Cycle
Stretcher
To Internal
Resets
RTS/RESET_IN
Pin
Pin
MUX
MOD
Watchdog
Timer
Power-Up
Bypass
MOD Pin
Latch Signal
Reset Status
Register
EN
D Q
Internal MOD
Signal to EIM
Figure 4-3. DSP56652 Reset Circuit
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Reset
The DSP56652 provides a read-only Reset Source Register (RSR) to determine the cause of the last hardware reset.
RSR
BIT 15 14
RESET 0
Name
WDR
Bit 1
EXR
Bit 0
13 12 11
Reset Source Register
10 9 8 7 6 5 4 3
$0020_C400
2 1 BIT 0
0
WDR EXR
0 0 0 0 0 0 0 0 0 0 0
Table 4-8. RSR Description
0
Description
Watchdog ResetÑ Watchdog timer time-out
External ResetÑ RESET_IN pin assertion
0 0
Settings
0 = Last reset not caused by watchdog timer.
1 = Last reset caused by watchdog timer.
0 = Last reset not caused by RESET_IN.
1 = Last reset caused by RESET_IN.
If both external and watchdog reset conditions occur simultaneously, the external reset has precedence, and only the EXR bit is set. If a power-on reset occurs with no external reset or watchdog reset, both bits remain cleared.
4.3.1 MCU Reset
All MCU peripherals and the MCU core are configured with their default values when
RESET_OUT is asserted.
Note: The STO bit in the General-Purpose Configuration Register (GPCR), which is reflected on the STO pin, is not affected by reset. It is uninitialized by a power-on reset and retains its current value after RESET_OUT is asserted.
The MOD input pin specifies the location of the reset boot ROM device. The pin must be driven at least four CKIL cycles before RESET_OUT is deasserted. If MOD is driven low, the internal MCU ROM is disabled and CS0 is asserted for the first MCU cycle. The MCU fetches the reset vector from address $0 of the CS0 memory space, which is located at the absolute address $4000_0000 in the MCU address space. The internal MCU ROM is disabled for the first MCU cycle only and is available for subsequent accesses. Out of
is enabled and the MCU fetches the reset vector from internal ROM at address
$0000_0000.
4.3.2 DSP Reset
Any qualified MCU reset also resets the DSP core and its peripherals to their default values. In addition, the MCU can issue a hardware or software reset to the DSP through
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DSP Configuration the MCU-DSP Interface (MDI). A hardware reset is generated by setting the DHR bit in the MCR. A software reset can be generated by setting the MC bit in the MCVR to issue a
DSP interrupt. In this case, the interrupt service routine might include the following tasks:
¥ Issue a RESET instruction.
¥ Reset other core registers that are not affected by the RESET instruction such as the
SR and the stack pointer.
¥ Jump to the initial address of the DSP reset routine, P:$0800.
Once the DSP exits the reset state, it executes the bootloader program described in
Appendix A, "DSP56652 DSP Bootloader".
Out of reset, CKIL drives the DSP clock until RESET_OUT is negated, when the clock source is switched to DSP_REF. To ensure a stable clock, the DSP is held in the reset state for 16 DSP_REF clocks after RESET_OUT is negated. The PLL is disabled and the default source for DSP_REF is CKIH, so the DSP_CLK frequency is equal to CKIH
¸
2.
It is recommended that clock sources be present on both the CKIH and CKIL pins.
However, should CKIH be inactive at reset, the DSP remains in reset until the MCU sets the DCS bit in the CKCTL register, selecting CKIL as the DSP clock source. In this case, the following MCU sequence is recommended:
1. Set the DHR bit.
2. Set the DCS bit
3. After a minimum of 18 CKIL cycles, clear the DHR bit.
4.4 DSP Configuration
The DSP contains an Operating Mode Register (OMR) to configure many of its features.
Four Patch Address Registers (PARs) allow the user to insert code corrections to ROM. A
Device Identification Register (IDR) is also provided.
4.4.1 Operating Mode Register
The OMR is a 16-bit read/write DSP core register that controls the operating mode of the
DSP56652 and provides status flags on its operation. The OMR is affected only by processor reset, by instructions that directly reference it (for example, ANDI and ORI), and by instructions that specify the OMR as a destination, such as the MOVEC instruction.
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DSP Configuration
OMR
BIT 15 14
ATE
RESET 0 0
Name
ATE
Bit 15
SEN
Bit 12
WR
Bit 11
EOV
Bit 10
EUN
Bit 9
XY
Bit 8
SD
Bit 6
13
0
12 11
Operating Mode Register
10 9 8
SEN WR EOV EUN XYS
7 6 5 4
SD PCD EBD
0 0 0 0 0 0 0 0 0
Table 4-9. OMR Description
3
0
2
0
1
MB
Ñ
BIT 0
MA
1
Description Settings
Address Trace EnableÑ Used in debugging for internal activity that can be traced via a logic analyzer.
Stack Extension Enable
XY Select for Stack ExtensionÑ Determines memory space for stack extension
Stop DelayÑ Controls the amount of delay after wake-up from STOP mode. A long delay may be necessary to allow the internal clock to stabilize.
Note: The SD bit is overridden if the PSTP bit in
PCTL1 is set, forcing wake-up with no delay.
0 = Disabled (default)Ñnormal operation.
1 = Enabled. External bus reflects DSP internal program address bus.
0 = Disabled (default).
1 = Enabled.
Extended Stack Wrap FlagÑ The DSP sets this bit when it recognizes that the stack extension memory requires a copy of the on-chip hardware stack. This flag is useful in debugging to determine if the speed of software-implemented algorithms must be increased. Once this bit is set it can only be cleared by reset or a MOVE operation to the OMR.
0 = No copy required (default).
1 = Copy of on-chip hardware stack to stack extension memory is required.
Extended Stack Overflow FlagÑ This flag is set when a stack overflow occurs in the Stack Extended mode. The Extended Stack Overflow is generated when SP equals SZ and an additional push operation is requested while the Extended mode is enabled by the SEN bit. The EOV bit is a Òsticky bitÓ (i.e., can be cleared only by hardware reset or an explicit MOVE operation to the OMR). The transition of EOV from 0 to 1 causes an IPL 3 Stack Error interrupt.
0 = No overflow has occurred (default).
1 = Stack overflow in stack extended mode.
Extended Stack Underflow FlagÑ Set when a stack underflow occurs in the Stack Extended mode. The
Extended Stack Underflow is generated when the SP equals 0 and an additional pull operation is requested while the Extended mode is enabled by the SEN bit.
The EUN bit is a Òsticky bitÓ (i.e., can be cleared only by hardware reset or an explicit MOVE operation to the OMR). The transition of EUN from 0 to 1 causes an Interrupt Priority Level (IPL) Level 3 Stack Error interrupt.
0 = No underflow has occurred (default).
1 = Stack underflow in stack extended mode.
0 = X memory space (default).
1 = Y memory space.
0 = Long delayÑ128K DSP_CLK cycles
(default).
1 = Short delayÑ16 DSP_CLK cycles.
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DSP Configuration
Name
PCD
Bit 5
EBD
Bit 4
MB
Bit 1
MA
Bit 0
Table 4-9. OMR Description
Description Settings
PC Relative Logic DisableÑ Used to reduce power consumption when PC-relative instructions
(branches and DO loops) are not used. A PC-relative instruction issued while the PC bit is set causes undetermined results. If this bit is set and then cleared, software should wait for the instruction pipeline to clear (at least seven instruction cycles) before issuing the next instruction.
0 = PC-relative instructions can be used
(default).
1 = PC-relative instructions disabled.
External Bus DisableÑ Setting this bit disables the core external bus drivers, and is recommended for normal operation to reduce power consumption. EBD must be cleared to use Address Tracing.
0 = External bus circuitry enabled (default).
1 = External bus circuitry disabled.
Operating Mode BÑ Used to determine the operating mode in certain devices. On the DSP56652, this bit reflects the state of the DSP_IRQ pin at the negation of RESET_IN.
Operating Mode AÑ Used to determine the operating mode in certain devices. On the DSP56652, this bit is set after reset.
4.4.2 Patch Address Registers
Program patch logic block provides a way to amend program code in the on-chip DSP
ROM without generating a new mask. Implementing the code correction is done by replacing a piece of ROM-based code with a patch program stored in RAM.
There are four patch address registers (PAR0ÐPAR3) at DSP I/O addresses
X:$FFF8ÐFFF5. Each PAR has an associated address comparator. When an address of a fetched instruction is identical to the address stored in a PAR, that instruction is replaced by a JMP instruction to the PARÕs jump target address, where the patch code resides. The
patch registers, register addresses and jump targets are listed in Table 4-10.
Table 4-10. Patch JUMP Targets
Patch
Register
PAR0
PAR1
PAR2
PAR3
Register
Address
X:$FFF8
X:$FFF7
X:$FFF6
X:$FFF5
JUMP
Target
$0018
$0078
$0098
$00F8
For more information, refer to the DSP56600 Family Manual (DSP56600FM/AD).
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I/O Multiplexing
4.4.3 Device Identification Register
The IDR is a 16-bit read-only factory-programmed register used to identify the different
DSP56600 core-based family members. This information may be used in testing or by software.
IDR
BIT 15 14 13
Revision number
12
RESET 0 0 0 0
Device Identification Register
11 10 9 8 7 6 5 4
Derivative number = $652
0 1 1 0 0 1 0 1
3
0
2
X:$FFF9
1 BIT 0
0 1 0
4.5 I/O Multiplexing
To accommodate all of the functions of the DSP56652 in a 196-pin package, 28 of the pins multiplex two or more functions. Eleven of these pins multiplex various peripherals, primarily with the JTAG Debug Port. The other 17 pins multiplex peripherals with the
DSP Address Trace function.
4.5.1 Debug Port and Timer Multiplexing
The functions of these pins are determined by the following controls:
1. Asserting the MUX_CTL pin configures all of the pins in Table 4-11 as debugging
signals, effectively creating an alternate set of pins for RESET_IN, MCU_DE,
DSP_DE, and the five JTAG signals. These eight pins can be brought out externally to facilitate debugging. Asserting MUX_CTL overrides all other
controls for these pins. MUX_CTL does not affect the pins in Table 4-12.
2. Each of eight bits in the GPCR selects the peripheral to which the associated pin is
3. Once a pin is assigned to a peripheral (MUX_CTL = 0 and/or the associated GPCR bit is written), that peripheralÕs Port Configuration Register determines if the pin is configured for the peripheral function or GPIO.
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I/O Multiplexing
Pin
No.
Table 4-11. Debug Port Pin Multiplexing
MUX_CTL =0
GPCR
Bit No.
MUX_CTL =1 GPCR Bit = 1 GPCR = 0
Module Pin Module Pin UART
K11 0 TRST SAP STDA
DSR
1
J12 1 TMS SAP SRDA
Controller
Interrupt
Controller
KP
INT7
DTR or SCLK
2
G13
G11
5
6
DSP_DE
TCK
SAP
SAP
SC2A
SCKA KP
ROW6
ROW7
DCD
3
RI
4
Ñ E11
D14
E14
7
Ñ
Ñ
RESET_IN
MCU_DE
TDO
MCU Timer IC2A UART
UARTÑCTS
UARTÑTxD
RTS
E12 Ñ TDI
UARTÑRxD / MCU TimerÑICI
5
1.
The DSR function for K11 is enabled by setting GPCR bit 0 AND using the pin as GPIO in the Edge Port.
2.
The DTR function for J12 is enabled by setting GPCR bit 1 AND using the pin as an Edge Port interrupt.
The SCLK function for J12 is enabled by setting GPCR bit 1 AND setting the CLKSRC bit in UCR2.
3.
The DCD function for G13 is enabled by clearing GPCR bit 5 AND using the pin as GPIO in the Keypad Port.
4.
The RI function for G11 is enabled by clearing GPCR bit 6 AND using the pin as GPIO in the Keypad Port.
5.
When MUX_CTL = 0, the E12 pin is connected to both the UART RxD input and the Timer IC1 input.
Pin
No.
N13
M13
H14
Table 4-12. Timer Pin Multiplexing
GPCR Bit = 1
GPCR Bit #
2
3
4
Port
MCU Timer
MCU Timer
MCU Timer
Pin
OC1
PWM
IC2B
Port
KP
KP
KP
GPCR = 0
Pin
COL6
COL7
ROW5
Figure 4-4 shows the relationship between these 11 pins and their controls.
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I/O Multiplexing
SCK (UART)
IC1
IC2 Input
(MCU Timer)
GPC2
COLUMN6/GPIO
OC1
COLUMN6
GPC3
COLUMN7/GPIO
PWM
COLUMN7
GPC4
ROW5/GPIO
IC2B
ROW5
GPC0
MUX_CTL
INT6/DSR/GPIO
STDA/GPIO INT6
TRST
GPC1
MUX_CTL
INT7/DTR/GPIO
SRDA/GPIO INT7
TMS
GPC5
MUX_CTL
ROW6/DCD/GPIO
SC2A/GPIO ROW6
DSP_DE
GPC6
MUX_CTL
ROW7/RI/GPIO
SCKA/GPIO ROW7
TCK
MUX_CTL
GPC7
Tx/GPIO
TDO
Tx
MUX_CTL
Rx/GPIO
Rx
TDI
GPC7
MUX_CTL
RTS/GPIO
IC2A
RESET_IN
MUX_CTL
CTS/GPIO
MCU_DE
Figure 4-4. MUX Connectivity Scheme
RTS
CTS
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I/O Multiplexing
GPCR
Name
STO
Bit 15
GPC7
Bit 7
GPC6
Bit 6
GPC5
Bit 5
GPC4
Bit
GPC3
Bit 3
GPC2
Bit 2
Bit 15 14
STO
RESET Ñ 0
13
0
12
0
General Port Control Register
11 10 9 8 7 6 5 4 3
$0020_CC00
2 1 Bit 0
GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0
0 0 0 0 0 0 0 0 0 0 0 0
Table 4-13. GPCR Description
Description Settings
Soft Turn OffÑ The value written to this bit is reflected on the STO pin. This bit is not affected by reset or the state of the MUX_CTL pin.
General Port Control for E11Ñ determines if pin E11 functions as the UART RTS signal or the Timer IC2 signal.
Setting the MUX_CTL pin configures pin E11 as an alternate
RESET_IN signal.
0 = RTS (default).
1 = IC2.
General Port Control for G11Ñ determines if pin G11 functions as the Keypad ROW7 signal or the SAP SCKA signal.
The UART RI signal can be implemented on pin G11 by using ROW7 as a general-purpose output.
Setting the MUX_CTL pin configures pin G11 as an alternate
JTAG TCK signal.
0 = ROW7 / RI.
1 = SCKA.
General Port Control for G13Ñ determines if pin G13 functions as the Keypad ROW6 signal or the SAP SC2A signal.
The UART DCD signal can be implemented on pin G13 by clearing GPC5 and using ROW6 as a general-purpose output.
Setting the MUX_CTL pin configures pin G13 as an alternate
DSP_DE signal.
0 = ROW6 / DCD.
1 = SC2A.
0 = ROW5 (default).
1 = IC2.
General Port Control for H14Ñ determines if pin H14 functions as the Keypad ROW5 signal or the Timer IC2 signal. This pin is not affected by MUX_CTL.
General Port Control for M13Ñ determines if pin M13 functions as the Keypad COL7 signal or the Timer PWM signal. This pin is not affected by MUX_CTL.
0 = COL7 (default).
1 = PWM.
General Port Control for N13Ñ determines if pin M13 functions as the Keypad COL6 signal or the Timer OC1 signal. This pin is not affected by MUX_CTL.
0 = COL6 (default).
1 = OC1.
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Name
GPC1
Bit 1
GPC0
Bit 0
Table 4-13. GPCR Description (Continued)
Description Settings
General Port Control for J12Ñ determines if pin J12 functions as the EP INT7 signal or the SAP SRDA signal.
Either of two UART signals can be implemented on pin J12 if
GPC1 is cleared. The DTR signal requires programming the pin as an interrupt in the edge port. The SCLK signal requires disabling the edge port interrupt and enabling SCLK in UCR2.
Setting the MUX_CTL pin configures pin J12 as an alternate
JTAG TMS signal.
0 = INT7 / DTR / SCLK
1 = SRDA.
General Port Control for K11Ñ determines if pin K11 functions as the EP INT6 signal or the SAP STDA signal.
0 = INT6 (default).
1 = STDA.
The UART DSR signal can be implemented on pin K11 by clearing GPC0, clearing bit 11 in the NIER and FIER to disable the interrupt, and configuring the pin as GPIO.
Setting the MUX_CTL pin configures pin K11 as an alternate
JTAG TRST signal.
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I/O Multiplexing
L7
P8
M9
N9
K7
J13
J11
J14
H13
N12
P13
M12
K14
P10
N11
M11
P12
4.5.2 DSP Address Visibility
DSP internal activity can be accessed for debugging by enabling the DSP Address
Visibility Mode. In this mode, the 16 DSP program address lines and an address strobe
signal are brought out on the pins listed in Table 4-14.
.
Table 4-14. Pin Function in DSP Address Visibility Mode
Pin No.
Peripheral Port Primary Signal Function In ÒDSP Trace Address ModeÓ
Ñ
Borrowed from
Keypad Port
Borrowed from
SmartCard Port
ROW1
ROW2
ROW3
ROW4
SIMCLK
SENSE
SIMDATA
SIMRESET
PWR_EN
MOD
COLUMN0
COLUMN1
COLUMN2
COLUMN3
COLUMN4
COLUMN5
ROW0
DSP_AT (DSP Address Tracing Strobe)
DSP_ADDR0
DSP_ADDR1
DSP_ADDR2
DSP_ADDR3
DSP_ADDR4
DSP_ADDR5
DSP_ADDR6
DSP_ADDR7
DSP_ADDR8
DSP_ADDR9
DSP_ADDR10
DSP_ADDR11
DSP_ADDR12
DSP_ADDR13
DSP_ADDR14
DSP_ADDR15
The Address Visibility Multiplexing is enabled by writing $4 to the OnCE Test and Logic
Control Register (OTLCR). The OTCLR is accessed by writing 10011 to the RS[4:0] field in the OnCE Command Register (OCR). For more information on OnCE operation, refer to the DSP56600 Family Manual.
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Chapter 5
MCUÐDSP Interface
The MDI provides a mechanism for transferring data and control functions between the two cores on the DSP56652. The MDI consists of two independent sub-blocks: a shared memory space with read/write access for both processors and a status and message control unit. The primary features of the MDI include the following:
¥ 1024
´
16-bit shared memory in DSP X data memory space
¥ interrupt- or poll-driven message control
¥ flexible, software-controlled message protocols
¥ MCU can trigger any DSP interrupt (regular or non-maskable) by writing to the command vector control register.
¥ Each core can wake the other from low-power modes.
The basic block diagram of the MDI module is shown in Figure 5-1.
Address & Data
Buffers
Shared Memory
1K Dual Access
DSP RAM
MCU-Side
Control
DSP-Side
Control
Motorola
MCU-Side Registers
Message & Control
DSP-Side Registers
Figure 5-1. MDI Block Diagram
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MDI Memory
5.1 MDI Memory
The DSP56652 provides special memory areas for the MDI on both the MCU and DSP sides. This section describes where these areas are mapped, how access contention between the two areas is resolved, and memory access timing.
Note: There is no mechanism in MDI hardware to prevent either core from overwriting an area of shared memory written by the other core. It is the responsibility of software to ensure data integrity in shared memory for each core.
5.1.1 DSP-Side Memory Mapping
MDI shared RAM is mapped to the X data memory space of the DSP at the top of its internal X data RAM. From the functional point of view of the DSP, the shared memory is indistinguishable from regular X data RAM. A parallel data path allows the MCU to write to shared memory without restricting or stalling DSP accesses in any way. In case of simultaneous access from both the MCU and the DSP to the same memory space, the DSP access has precedence. The DSP programmer must be aware, however, that data written to that area can be changed by the MCU.
The MDI message control and status registers are mapped to DSP X I/O memory as a regular peripheral, accessible via special I/O instructions.
X:$FFFF
X:$FF80
DSP X Data Memory
X I/O Memory
MDI DSP Base Address + X:$F
MDI DSP Base Address
MDI Control
Registers
5-2
X:$2000
X:$1C00
X:$0000
MDI Shared
Memory
Figure 5-2. MDI: DSP-Side Memory Mapping
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MDI Memory
5.1.2 MCU-Side Memory Mapping
The MCU allocates a 4-kbyte peripheral space to the MDI, as shown in Figure 5-3.
Control and status registers are mapped to the upper 16 words of this space, and shared memory is mapped to the lower 2 kbytes.
$FFFF_FFFF
$0020_2FFF
$0020_2FF0
$0020_27FF
$0020_2000
MDI Control
Registers
Reserved
MDI Shared
Memory
$0040_0000
Peripherals (2M)
$0020_0000
$0000_0000
Figure 5-3. MDI: MCU-Side Memory Mapping
Note: Writes to reserved locations are ignored. Reads from reserved locations latch indeterminate data. Neither access terminates in an access error.
The offset conversion formula between the MDI internal address offset (which is also equal to the DSP offset) and the 16-bit MCU addresses offset is
OFF
MCU
= OFF
INT
*
2
All MCU accesses to the MDI shared memory should be evenly aligned, 16-bit accesses to ensure valid operation.
5.1.3 Shared Memory Access Contention
Access contentions are resolved in hardware. DSP access has precedence because it runs on a faster clock than the MCU, which is stalled until the DSP access is completed.
ÒContentionÓ is defined as simultaneous access (read or write) by both MCU and DSP to the same 1/4 Kword of the shared memory. Simultaneous access to different 1/4K blocks of shared memory or to the MDI control registers proceed without stall.
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MDI Memory
The MCU side contains a data buffer to store a halfword from a write request, enabling the
MCU to write with no stall even if the memory array is busy with a DSP access. However, if a second access (read or write) is attempted before the buffer is cleared, the MDI will stall the MCU.
Some stalls may last less then one MCU clock, and so may not even be evident on the
MCU side. On the other hand, several consecutive 1-cycle accesses by the DSP to the
MDI memory can stall an MCU access for the equivalent number of clock cycles. For
example, Example 5-1 show a program loop that transfers data from X to Y memory. Any
attempt by the MCU to access the shared memory while the loop is running will be stalled until the loop terminates.
Example 5-1. Program Loop That Stalls MCU Access to Shared Memory move x:(r0)+,a move x:(r0)+,b
DO #(N/2-1), _BE_NASTY_TO_MCU move x:(r0)+,a move x:(r0)+,b a,y:(r4)+ b,y:(r4)+
_BE_NASTY_TO_MCU move a,y:(r4)+ move b,y:(r4)+
;r0 points to MDI memory
;r4 points to other memory
To avoid a lengthy MCU stall, the DO loop above can be written to allow two cycles per
move, making time slots available for MCU accesses, as illustrated in Example 5-2.
Example 5-2. Program Loop With No Stall
DO #N,_IM_OK_MCU_OK move x:(r0)+,x0 move x0,y:(r4)+
_IM_OK_MCU_OK
;r0 points to MDI memory
;r4 points to other memory
The second instruction in the loop allows pending MCU accesses to execute.
5.1.4 Shared Memory Timing
The DSP always has priority over the MCU when accessing the shared memory. Every
DSP access to MDI shared memory or control register lasts one cycle, and is executed as part of the DSP pipeline without stalling it.
In general, an MCU peripheral access is two clock cycles, excluding instruction fetch time. MCU accesses to MDI control registers are always two clock cycles, but shared memory accesses usually take longer, according to the following parameters:
1.
Clock source of the shared memory: If the DSP is in STOP mode, the shared memory will operate using the MCU clocks generated at half frequency. If the DSP
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MDI Memory is active, it will generate the memory clocks at full frequency and all MCU accesses should be synchronized to it.
2.
Access type: An MCU write is done to a buffer at the MCU side. If the buffer is empty, the MCU takes two cycles to write to the buffer and proceeds without stall; the MDI writes the buffer to the shared memory later, in a minimum of another two
MCU cycles, freeing the buffer. In case of a read, or a write when the buffer is not yet free from a previous write, the access will stall.
3.
Relative frequency of the MCU and the DSP clocks: An MCU access generates a request to the DSP side that must be synchronized to the DSP clock (2 DSP clocks in the worst case), and an acknowledge from the DSP to the MCU side, that must be synchronized to the MCU clock (2 MCU clocks in the worst case). The synchronization stall therefore depends on the frequency of both processors. The slower the DSP frequency is, relative to the MCU frequency, the longer the access time (measured in MCU clocks). In a typical system configuration, the DSPÕs frequency is higher or equal to the MCUÕs frequency. In this assumption, the maximum MCU stall is if the frequencies of the MCU and the DSP are equal. If the
DSP frequency is lower than the MCU frequency, the access time (measured in
MCU clocks) may in principle be very long, depending on how slow the DSP is.
4.
DSP parallel accesses: Any DSP access in parallel to an MCU access to the same
1/4K memory block can further stall a pending MCU access. If the DSP does not run consecutive one-cycle accesses and the MCU frequency is not faster than the
DSPÕs frequency, an MCU contention stall will be no more than one MCU cycle.
5.
DSP PLL: If the PLL is reprogrammed during MCU program execution, (e.g., after a DSP reset) the MCU should not access shared memory until the PLL has reacquired lock. If the MCU attempts to access the MDI shared memory before the
PLL acquires lock, the MCU can time out and generate an error. One way to avoid this condition is to take the following steps: a. DSP software sets an MDI flag bit immediately after setting the PLL.
b. MCU software polls the flag bit until it is set before accessing MDI shared memory.
MCU-side access timing is summarized in Table 5-1.
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Access Type
Shared memory read Inactive
Active
Shared memory write Either
Buffer busy after shared memory write
Inactive
Active
MCU-DSP shared memory contention
Active
Table 5-1. MCU MDI Access Timing
MCU Cycles
1
DSP
Clocks
Minimum
+ 8
+ 2
+ 0
11
4
2
Maximum
+ 8
+ 4
+ 1
11
8
2
Comments
Assumes write buffer is empty.
Assumes write buffer is empty.
Consecutive accesses incur MCU stall cycles.
MCU stalls until DSP access completes.
Multiple DSP one-cycle instructions stall the MCU further.
Ñ Control registers Either 2 2
1.
Minimum case: DSP clock frequency >> MCU clock frequency.
Maximum case: DSP clock frequency = MCU clock frequency.
(More cycles required if DSP clock < MCU clock.)
5.2 MDI Messages and Control
The MDI provides a means for the MCU and DSP to exchange messages independent of the shared memory array. A typical message might be ÒI have just written a message of N words, starting at offset X in memory,Ó or ÒI have just finished reading the last data block sent.Ó For ease and flexibility, the protocol for exchanging these messages is not predefined in hardware but can be implemented with a few simple software commands.
5.2.1 MDI Messaging System
Messages are exchanged between the two processors through special-purpose control registers. Most of these registers are symmetric and work together to exchange messages in the following ways:
1. Each of two 16-bit write-only transmit registers is copied in a corresponding read-only receive register on the other processorÕs side. These registers can be used to transfer 16-bit messages or frame information about messages written to the shared memory, such as number of words, initial address, and message code type.
2. Writing to a transmit register clears a Òtransmitter emptyÓ bit in the status register on the transmitter side and sets a Òreceiver fullÓ bit in the status register on the receiver side, which can trigger a maskable receive interrupt on the receiver side if so programmed.
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MDI Messages and Control
3. Reading a receive register automatically clears the Òreceiver fullÓ bit in the status register on the receiver side and sets the Òtransmitter emptyÓ bit in the status register on the transmitter side, which can trigger a maskable transmit interrupt on the transmitter side if so programmed.
4. Three general purpose flags are provided for each transmitter and reflected in the status register at the receiver side.
The symmetry of the MDI registers is illustrated in Figure 5-4 and Table 5-2.
MCVR MCR
MCU Module Bus
MSR
MRR0 MRR1
MTR0 MTR1
Acronym
MRR0
MRR1
MTR0
MTR1
MSR
MCR
MCVR
DSR DCR
DSP Peripheral Bus
DTR0 DTR1
DRR0
Figure 5-4. MDI Register Symmetry
DRR1
Table 5-2. MDI Registers and Symmetry
MCU Registers DSP Registers
Name
MCU Receive Register 0
MCU Receive Register 1
MCU Transmit Register 0
MCU Transmit Register 1
MCU Status Register
MCU Control Register
MCU Command Vector Register
Acronym
DTR0
DTR1
DRR0
DRR1
DCR
DSR
Name
DSP Transmit Register 0
DSP Transmit Register 1
DSP Receive Register 0
DSP Receive Register 1
DSP Control Register
DSP Status Register
Ñ
The message exchange mechanism is shown in greater detail in Figure 5-5.
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Transmit Side Receiver Side
Transmit
Register
Receive
Register
Data
Write
Data
Read
Status Register
TE
Clear
Set
Set
Clear
Status Register
RF
Transmit
Interrupt
Request
Control Register
TEIE
Bit
TE
RF
TEIE
RFIE
Name
Transmit Register Empty
Receive Register Full
Transmit Register Empty
Interrupt Enable
Receive Register Full
Interrupt Enable
Control Register
RFIE
Figure 5-5. MDI Message Exchange
Receive
Interrupt
Request
In addition to exchanging messages, the MDI registers also provide the following special- purpose control functions:
1. Each coreÕs power mode is reflected in the other coreÕs status register.
2. Each core can issue an interrupt to wake the other core from its low-power modes
(STOP and WAIT modes on either side, plus DOZE mode on the MCU side).
3. The MCU can issue a Command Interrupt to the DSP by setting the MC bit in the
MCU Command Vector Register (MCVR). Software can write the vector address of this interrupt to a register on the MCU side. The Command Interrupt can be maskable or non-maskable.
4. The MCU can issue a hardware reset to the DSP. (The DSP cannot issue a hardware reset to the MCU.)
5. The DSP can issue two general-purpose interrupt requests to the MCU by setting the DGIR0 or DGIR1 bit in the DSP-Side Status Register (DSR). These interrupts
are user-maskable on the MCU side. Figure 5-6 details the mechanism by which
the DSP issues a general-purpose interrupt to the MCU.
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MDI Messages and Control
Write1
DSP-Side
Status Register
GIR
Set
MCU-Side
Status Register
GIP
Write1 to Clear
Clear
Control Register
Bit
GIR
GIP
GIE
Name
General-Purpose Interrupt Request
General-Purpose Interrupt Pending
General-Purpose Interrupt Enable
GIE
Figure 5-6. DSP-to-MCU General Purpose Interrupt
General
Interrupt
Request
The MCU-to-DSP interrupt mechanism (Command Interrupt) differs from Figure 5-6 in
the following ways:
1. The interrupt pending bit (the MCP bit in the DSR) is cleared automatically when the interrupt is acknowledged.
2. The trigger bit on the MCU side (the MC bit) is in the MCVR.
3. When a non-maskable interrupt is generated, the interrupt enable bit on the DSP side (the MCIE bit in the DCR) is ignored.
5.2.2 Message Protocols
The message hardware can be used by software to implement message protocols for a wide array of message types. Full support is given for both interrupt and polling management. The following are examples of different message protocols:
¥ A message of up to 16 bits is written directly to one of the transmit registers.
¥ Both transmit registers are used to pass a 2-word message. The corresponding receive register of the first word disables its interrupt; the register receiving the second word enables its interrupt. An interrupt is triggered when the second word is received.
¥ Transmit registers pass frame information describing longer messages written to the shared memory. Such frame information usually includes an initial address, the number of words, and often a message type code.
¥ A DSP general interrupt or the MCU Command Interrupt signals an event or request that does not include data words, such as acknowledging the read of a long message from the shared memory.
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¥ Fixed-length, formatted data is written in a predetermined location in the shared memory. A general purpose interrupt (DSP) or command interrupt (MCU) signals the other processor that the data is ready.
¥ One processor uses the three general-purpose flags to inform the other processor of its current program state.
5.2.3 MDI Interrupt Sources
The MDI provides several ways to generate interrupts to both the DSP and MCU.
5.2.3.1 DSP Interrupts
There are five independent ways for the MCU to interrupt the DSP through the MDI:
1. MCU Command Vector interrupt
2. MDI receive/transmit interrupt
3. MDI DSP wake from STOP / general-purpose interrupt (using the IRQC interrupt input)
4. Protocol Timer DSP wake from STOP / general-purpose interrupt (using the IRQD interrupt input)
5. External DSP wake from STOP / general-purpose interrupt (using the IRQB interrupt input)
The first three interrupts are MDI functions. The other two are protocol timer functions that make use of MDI hardware but have no specific MDI instructions. The interrupts can
be prioritized in Core Interrupt Priority Register (IPRC). See Table 7-9 on page 7-15.
The relative priority of the MDI receive/transmit interrupts is fixed as follows:
1. Receive register 0 full (RFIE0)
2. Receive register 1 full (RFIE1)
3. Transmit register 0 empty (TEIE0)
4. Transmit register 1 empty (TEIE1)
5.2.3.2 MCU Interrupts
There is only one interrupt request line to the MCU interrupt controller. The interrupt service routine must examine the MCU-Side Status Register (MSR) to determine the interrupt source. The Find First One (FF1) instruction can be used for this purpose. If some of the interrupts are disabled, software can read the MDI Control Register (MCR)
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Low-Power Modes and perform an AND operation with the MSR before executing the FF1 instruction. The interrupt service routine should clear the General Purpose Interrupt Pending bits
(MGIP[1:0], MSR bits 11Ð10) to deassert the request to the interrupt controller.
5.2.4 Event Update Timing
An information exchange between the two processors that is reflected in the status register of the receiving processor (an ÒeventÓ) incurs some latency. This latency is the delay between the event occurrence at one processor and the resulting update in the status register of the other processor. The latency can be expressed as the sum of a number of transmitting-side clocks (TC) and receiving-side clocks (RC).
The minimum event latency occurs when there are no other events pending, and is equal to
TC + 2(RC).
The maximum event latency is incurred when the event occurs immediately after a previous event is issued. It is equal to 4(TC) + 6(RC).
5.2.5 MCU-DSP Troubleshooting
The MCU can use the MDI in the following three ways to identify and correct the source of a DSP malfunction:
1. Examine the DPM bit in the MSR to determine if the DSP is stuck in STOP mode.
If so, the MCU can wake the DSP by setting the DWS bit.
2. Issue an NMI using the Command Interrupt (setting the MC bit in the MCVR). The
NMI service routine can incorporate a diagnostic procedure designed for such an event. Note that the MNMI bit must also be set to enable non-maskable interrupts.
3. If neither of the first two measures is effective, the MCU can issue a hardware reset to the DSP by setting the DRS bit in the MCR.
5.3 Low-Power Modes
Each side of the MDI is fully active in all low-power modes except STOP. Each processor can enter and exit a low-power mode independently. The processor state is unchanged by a transition to and from a low-power modeÑstatus and control registers do not return to default values.
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Low-Power Modes
5.3.1 MCU Low-Power Modes
Various DSP events can awaken the MCU from a low-power mode (WAIT, DOZE, or
STOP) by generating a corresponding interrupt. Table 5-3 lists the events and the
associated interrupt enable bits in the MCR.
Table 5-3. MCU Wake-up Events
Event
Transmitting a message to MRR0
Transmitting a message to MRR1
Receiving a message from MTR0
Receiving a message from MTR1
Setting the DGIR0 bit in the DSR (General Interrupt request 0)
Setting the DGIR1 bit in the DSR (General Interrupt request 1)
Interrupt Enable Bit in MCR
15 (MRIE0)
14 (MRIE1)
13 (MTIE0)
12 (MTIE1)
11 (MGIE0)
10 (MGIE1)
The software designer should consider the following points before placing the MCU in
STOP mode:
1. Compatibility with DSP STOP mode protocol.
MCU software should accommodate the possibility that the DSP is in STOP when the MCU awakens from its STOP mode.
2. Pending shared memory writes.
A shared memory write that has not completed when the MCU enters STOP mode will execute reliably after the MCU has awakened. Nevertheless, the user may wish to ensure that all shared memory writes are completed before entering STOP. This can be done by polling MSR bit 6 until it is cleared before issuing the STOP instruction.
3. Pending MCU events.
MCU software should poll the MEP bit in the MSR until it is cleared just before issuing the STOP instruction. This ensures that the DSP has acknowledged all previous MCU-generated events so that it can be made aware of the MCU power mode change.
5.3.2 DSP Low-Power Modes
The MCU can wake the DSP from WAIT mode by issuing any of the interrupts listed in
MCU software can wake the DSP from STOP in one of the following three ways:
1. A DSP Wake from STOP command (setting the DWS bit in the MSR).
2. A Protocol Timer DSP interrupt.
3. A DSP hardware reset (setting the DHR bit in the MCR).
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Low-Power Modes
The MCU can also wake the DSP externally with an external DSP interrupt, external DSP debug request, JTAG DSP debug command, or system reset.
DSP software should ensure that the MCU can track each DSP transition to and from
STOP mode before the next one occurs. This is essential for proper control of the shared
memory clock (see Section 5.3.3). One way to accomplish this is to provide a minimum
delay (measured in MCU clocks) between consecutive DSP entrances to STOP mode.
Another method involves waiting for MDI register events to terminate to supply the needed delay. With this method the DSP sends at least one MDI register event and waits until the DEP bit in the DSR is cleared before it enters STOP mode. To be sure that an event takes place, DSP code can issue a dummy event such as the one illustrated in
Example 5-3. The DEP check should be the last MDI access before issuing the STOP
instruction to guarantee that the MSR is updated properly.
Example 5-3. Dummy Event to Allow MCU to Track DSP Power Mode Change
_wait movep movep nop nop nop jset stop x:<<DCR,x0 x0,x:<<DCR; ;dummy event - write back flags
;nops for pipeline delay
#DEP,x:<<DSR,_wait
After a DSP wake from STOP command, IRQC should be deasserted by writing Ò1Ó to the
DWSC bit in the DSR. Similarly, after a protocol timer interrupt event, IRQD should be deasserted by writing Ò1Ó to the DTIC bit in the DSR. Clearing either of these bits just as the DSP exits STOP can serve as the MDI register event for the delay required before the next entry to STOP mode.
5.3.3 Shared Memory in DSP STOP Mode
The shared memory array operates from the DSP clock for either processor unless the
DSP is in STOP mode. MCU access to the shared memory is internally synchronized to the DSP clock. Memory access signals from the MCU require 2 DSP cycles to synchronize to the DSP clock, and 2 MCU cycles to synchronize the DSP acknowledgment to the MCU clock. If the DSP runs at a relatively low frequency, extra wait states are added to the MCU access.
Note: The synchronization wait states are not related to wait states resulting from memory contention.
When the DSP is in STOP mode and the MCU is in normal mode, the shared memory operates from the MCU clock. The memory controller is alerted when the DSP has exited
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Resetting the MDI
STOP mode and stalls any pending MCU shared memory access until the memory clocks are switched back to the DSP.
Note: Waking the DSP from STOP can take several MCU clocks. The parameters affecting the relative time length include the DSP frequency relative to the
MCU frequency, the need for PLL relock, and the state of the SD bit in the
OMR. If the total wake from STOP delay is greater than 128 MCU clocks, a pending MCU shared memory access can be lost due to an MCU time-out interrupt. MCU shared memory writes that are separated by MSR bit 6 checks are not subject to this loss because the write is done to a buffer and the MCU bus is released.
5.4 Resetting the MDI
The MDI can be reset by any of the conditions in Table 5-4.
Action
Table 5-4. MDI Reset Sources
Description Reset Type
MDI Reset Setting the MDIR bit in the MCR
Only the MDI system is resetÑall status and control registers are returned to their default values. None of the rest of the DSP56652 system is affected.
Note: MDIR assertion is ignored if the DSP is in STOP mode.
DSP Hardware
Reset
Setting the DHR bit in the
MCR
In addition to the MDI reset conditions above, the entire DSP side is reset. Memory, including MDI shared memory, is not affected. MCU software should poll the DRS bit (MSR bit 7) to determine when the reset sequence on the DSP side has ended (and wait for PLL relock
if the PLL is reprogrammedÑsee page 5-5) before accessing the
shared memory.
System Reset Power on reset
RESET_IN asserted
Watchdog timer time-out
The entire system, including memory, is reset.
Note that the DSP software RESET instruction does not reset the MDI.
Before initiating an MDI reset, the following items should be considered:
1.
Pending shared memory writeÑ If an MCU write to the shared memory is pending in the write buffer when an MDI reset is initiated, the access may be lost.
To ensure that the data is written, software should poll the MSMP bit in the MSR until it is cleared before triggering the MDI reset.
2.
DSP MDI operationsÑ MDIR assertion is asynchronous to DSP operation, and can cause unpredictable behavior if it occurs while the DSP is testing an MDI
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MDI Software Restriction Summary register bit with an instruction such as jset #DTE0,x:DSR,tx_sbr .
MCU software should verify that the DSP is not engaged in MDI signalling activity before asserting MDIR. This can be done by performing the following steps: a. Disable the DSP interrupt event in the Protocol Timer by clearing the DSIE bit in the PTIER.
b. Verify that both DWS and MTIR (MSR bits 8 and 9) are cleared.
The instruction immediately following assertion of the MDIR bit may be overridden by the reset sequence, with all registers retaining their reset values. Therefore, software should wait at least one instruction before writing to MDI registers.
5.5 MDI Software Restriction Summary
Tables 5-5 through 5-7 summarize the various constraints on MDI software.
Action
Writing to a transmit register
Reading from a receive register
Table 5-5. General Restrictions
Restriction
Wait for a Transmitter Empty interrupt or poll the Transmitter Empty bit in the status register
Wait for a Receiver Full interrupt or poll the Receiver Full bit in the status register.
Table 5-6. DSP-Side Restrictions
Restriction Action
Setting DGIR(0,1) to issuing general interrupt request
Configuring IRQC and IRQD
Verify that DGIR(0,1) is cleared
Define IRQC as level-triggered by clearing the ICTM bit in the IPRC.
Define IRQD as level-triggered by clearing the IDTM bit in the IPRC.
Delay between MDI register write and reflection in DSR
A delay of up to four instructions can occur between an MDI register write and the resulting change in the DSR. Refer to the 56600 Family Manual , Appendix
B, Section 5 (ÒPeripheral Pipeline RestrictionsÓ) for a description of possible problems and work-arounds. Testing the DEP bit in the DSR requires one additional clock delay above the 56600 manual description.
Continuous one-cycle accesses to the Shared Memory
Entering DSP STOP mode
Can stall MCU. Refer to Example 5-2 on page 5-4 for sample code that avoids
lengthy MCU stalls.
Enable IRQCÑwrite a non-zero value to the ICPL bits in the IPRC.
Enable IRQDÑwrite a non-zero value to the IDPL bits in the IPRC.
Ensure minimum delay from previous STOP mode (Section 5.3.2 on page 5-12).
Ensure the DEP bit in the DSR is cleared.
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MDI Software Restriction Summary
Action
Clearing serviced interrupts
Table 5-6. DSP-Side Restrictions
Restriction
Write 1 to the DWSC bit in the DSR to clear IRQC.
Write 1 to the DTIC bit in the DSR to clear IRQD.
Action
Byte-wide writes to shared memory
Writing to MCVR
Setting the DWS bit in the MSR
PT timer DSP interrupt
Entering MCU STOP mode
MDI reset
After DSP reset
Table 5-7. MCU-Side Restrictions
Restriction
The MDI latches all 16 bits when receiving data written to it. In byte-wide writes, the MCU drives only the written 8 bits; the unspecified byte in the shared memory location may contain corrupt data.
Ensure that the MC bit in the MCVR is cleared before writing.
Ensure DWS is cleared before setting it.
If the MSIR bit in the MSR is set when the protocol timer issues a dsp_int event
(i.e., a previous DSP interrupt event has not been serviced) the second interrupt request is lost.
Verify that the MEP bit in the MSR is clear.
Before setting the MDIR bit in the MCR or DHR (MCR bit 7), do the following:
1. Disable the DSP Protocol Timer interrupt by clearing the DSIE bit in the
PT Interrupt Enable Register (PTIER).
2. Verify that the DWS bit in the MSR is cleared to ensure that the DSP has serviced the last wake-up from STOP.
3. Verify that the DTIC bit in the DSR is cleared to ensure that there are no outstanding protocol timer interrupt requests.
4. Poll the MSMP bit in the MSR until it is cleared to ensure all shared memory writes occur.
In addition, before setting MDIR, do the following:
1. Verify that the DSP side is not engaged in MDI activity (e.g. by issuing
NMI).
2. Check that the DPM bit in the MSR is cleared, indicating that DSP is not in STOP mode. (Hardware will ignore the MDIR bit if DSP is in STOP mode).
After asserting MDIR, delay at least one instruction time before writing to an
MDI register to ensure it is not overwritten by reset.
After any MDI reset (MCU or DSP hardware reset, asserting MDIR, or asserting DHR) poll the DRS bit in the MSR until it is cleared before accessing the shared memory to ensure DSP reset is complete.
Ensure that the DSP PLL has been relocked (e.g., item 5 on page 5-5) before
the MCU accesses shared memory.
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MDI Registers
5.6 MDI Registers
In general, the MDI registers on the DSP side and MCU side are symmetrical. They are
Table 5-8. MDI Signalling and Control Registers
MCU Side DSP Side
Function
MCU Command Vector Register
Control Register
Status Register
Transmit Register 1
Transmit Register 0
Receive Register 1
Receive Register 0
Name
MCVR
MCR
MSR
MTR1
MTR0
MRR1
MRR0
Address
$0020_2FF2
$0020_2FF4
$0020_2FF6
$0020_2FF8
$0020_2FFA
$0020_2FFC
$0020_2FFE
Name
DCR
DSR
DTR1
DTR0
DRR1
DRR0
Ñ
Address
X:$FF8A
X:$FF8B
X:$FF8C
X:$FF8D
X:$FF8E
X:$FF8F
The correspondence between transmit registers on one side and receive registers on the
other side is listed in Table 5-9.
Table 5-9. MCUÐDSP Register Correspondence
MCU Register
MTR1
MTR0
MRR1
MRR0
MCU Address
$0020_2FF8
$0020_2FFA
$0020_2FFC
$0020_2FFE
DSP Register
DRR1
DRR0
DTR1
DTR0
DSP Address
X:$FF8E
X:$FF8F
X:$FF8C
X:$FF8D
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MDI Registers
5.6.1 MCU-Side Registers
MCVR
BIT 15 14
RESET 0 0
13
0
12
MCU Command Vector Register
11 10 9 8 7 6 5
MC
4
MCV[6:0]
0 0 0 0 0 0 1 1 0
3
0
Table 5-10. MCVR Description
$0020_2FF2
2
0
1
0
BIT 0
MNMI
0
Name Type
1 Description Settings
MC
Bit 8
MCV[6:0]
Bits 7Ð1
MNMI
Bit 0
R/1S MCU CommandÑ Used to initiate a DSP interrupt. Setting the MC bit sets the MCP bit in the DSR. If the MNMI bit in this register is set, a non-maskable MCU command interrupt is issued at the DSP side. If MNMI is cleared and the MCIE bit in the DCR is set, a maskable interrupt request is issued at the
DSP side. The MC bit is cleared only when the command interrupt is serviced on the DSP side, providing a way for the MCU to monitor interrupt service status. The MCVR cannot be written while the MC bit is set.
0 = No outstanding DSP command interrupt (default).
1 = DSP command interrupt has been issued and has not been serviced.
R/W
R/W
MCU Command VectorÑ Vector address displacement for the DSP command interrupt.
With this mechanism the MCU can activate any interrupt from the DSP interrupt table. The actual vector value is twice the value of MCV[6:0]. The MCV bits can only be written if the
MC bit is cleared.
MCU Non-Maskable InterruptÑ Determines if the Command Interrupt issued to the DSP by setting the MC bit is maskable or non- maskable. The MNMI bit can only be written if the MC bit is cleared.
0 = Maskable interrupt issued when MC is set, if DSP DCR bit 8 (maskable interrupt enable) is set (default).
1 = Non-maskable interrupt generated when MC is set. DCR bit 8 is ignored.
1.
R = Read only.
R/W = Read/write
R/1S = Read; write with 1 to set (write with 0 ingored).
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MDI Registers
MCR
BIT 15 14 13 12
MCU-Side Control Register
11 10 9 8 7 6
MRIE0 MRIE1 MTIE0 MTIE1 MGIE0 MGIE1 DHR MDIR
RESET 0 0 0 0 0 0 0 0 0 0
5 4 3
0
$0020_2FF4
2 1 BIT 0
0
MDF[2:0]
0 0 0 0
The MCR is a 16-bit read/write register that enables the MDI interrupts on the MCU side and enables the trigger events on the DSP side (e.g. awaken from Stop mode, hardware reset, flag update, etc.).
Note: Either the EMDI bit in the NIER or the EFMDI bit in the FIER must be set in
order to generate any of the interrupts enabled in the MCR (see page 7-7).
Name
MRIE0
Bit 15
MRIE1
Bit 14
MTIE0
Bit 13
MTIE1
Bit 12
MGIE0
Bit 11
MGIE1
Bit 10
Table 5-11. MCR Description
Type
1
R/W
R/W
R/W
R/W
R/W
R/W
Description Settings
MCU Receive Interrupt Enable 0Ñ When
MRIE0 is set, a receive interrupt request 0 is issued when the MRF0 bit in the MSR is set.
When MRIE0 is cleared, MRF0 is ignored and no receive interrupt request 0 is issued.
0 = Receive interrupt 0 request disabled
(default).
1 = Enabled.
MCU Receive Interrupt Enable 1Ñ When
MRIE1 is set, a receive interrupt request 1 is issued when the MRF1 bit in the MSR is set.
When MRIE1 is cleared, MRF1 is ignored and no receive interrupt request 1 is issued.
0 = Receive interrupt 1 request disabled
(default).
1 = Enabled.
MCU Transmit Interrupt Enable 0Ñ If MTIE0 is set, a transmit interrupt 0 request is generated when the MTE0 bit in the MSR is set. If MTIE0 bit is cleared, MTE0 is ignored and no transmit interrupt request 0 is issued.
0 = Transmit interrupt 0 request disabled
(default).
1 = Enabled.
MCU Transmit Interrupt Enable 1Ñ If MTIE1 is set, a transmit interrupt 1 request is generated when the MTE1 bit in the MSR is set. If MTIE1 bit is cleared, MTE1 is ignored and no transmit interrupt request 1 is issued.
0 = Transmit interrupt 1 request disabled
(default).
1 = Enabled.
MCU General Interrupt Enable 0Ñ If this bit is set, a general interrupt 0 request is issued when the MGIP0 bit in the MSR is set. If
MGIE0 is clear, MGIP0 is ignored and no general interrupt request 0 is issued.
MCU General Interrupt Enable 1Ñ If this bit is set, a general interrupt 1 request is issued when the MGIP1 bit in the MSR is set. If
MGIE1 is clear, MGIP1 is ignored and no general interrupt request 1 is issued.
0 = General interrupt 0 request disabled
(default).
1 = Enabled.
0 = General interrupt 1 request disabled
(default)
1 = Enabled
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MDI Registers
Table 5-11. MCR Description (Continued)
Name Type
1 Description Settings
DHR
Bit 7
R/W DSP Hardware ResetÑ Setting DHR issues a hardware reset to the DSP. Clearing DHR de-asserts the reset. Setting DHR also causes MDI reset, returning all MDI control and status bits to their default values (except the DHR bit itself).
DHR should be held asserted for a minimum of three CKIL cycles. (See Reset, Mode
Select, and Interrupt Timing in the DSP56652 Technical Data Sheet.
) After clearing DHR, software should poll the DRS bit in the MSR until it is cleared before attempting an access to MDI shared memory. If an MDI reset (caused by MDIR or DHR being set) is done while an MCU write to the shared memory is pending in the write buffer, the access may be lost.
MDIR
Bit 6
R0/1S MDI ResetÑ Setting MDIR resets the message and control sections on both DSP and MCU sides. All control and status registers except DHR are returned to their default values and all internal states are cleared. Data in the shared memory array remains intact; only the access control logic is affected. After setting MDIR, software should poll DRS to determine when the reset sequence on the DSP side has ended before accessing the shared memory.
MDF[2:0]
Bits 2Ð0
R/W MCU-to-DSP FlagsÑ General-purpose flag bits that are reflected on the DSP side in the
DF[2:0] bits in the DSR.
1.
R/W = Read/write
R0/1S = Always read as 0; write with 1 to set (write with 0 ingored).
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MDI Registers
MSR
BIT 15 14 13 12
MCU-Side Status Register
11 10 9 8 7 6 5 4
MRF0 MRF1 MTE0 MTE1 MGIP0 MGIP1 MTIR DWS DRS MSMP DPM MEP
RESET 0 0 1 1 0 0 0 0 1 0 Ñ 0
Name
MRF0
Bit 15
MRF1
Bit 14
MTE0
Bit 13
MTE1
Bit 12
MGIP0
Bit 11
MGIP1
Bit 10
MTIR
Bit 9
3
$0020_2FF6
2 1 BIT 0
0
MF[2:0]
Ñ Ñ Ñ
Table 5-12. MSR Description
Type
1 Description
R
R
MCU Receive Register 0 FullÑ Set when the
DSP writes to DTR0, indicating to the MCU that the reflected data is available in MRR0. MRF0 is cleared when the MCU reads MRR0.
MCU Receive Register 0 FullÑ Set when the
DSP writes to DTR1, indicating to the MCU that the reflected data is available in MRR1. MRF1 is cleared when the MCU reads MRR1.
R
R
MCU Transmit Register 0 EmptyÑ Cleared when the MCU writes to MTR0; set when the
DSP reads the reflected data in DRR0.
MCU Transmit Register 1 EmptyÑ Cleared when the MCU writes to MTR1; set when the
DSP reads the reflected data in DRR1.
R/1C MCU General Interrupt 0 PendingÑ Indicates that the DSP has requested an interrupt by setting the DGIR0 bit in the DSR.
R/1C MCU General Interrupt 1 PendingÑ Indicates that the DSP has requested an interrupt by setting the DGIR1 bit in the DSR.
R MCU Protocol Timer Interrupt RequestÑ Set by the protocol timer when it issues a dsp_int
event (see Table 10-4 on page 10-13) which
asserts DSP IRQD (waking the DSP from
STOP mode) and IRQA, which is wire-orÕd to
IRQD. MTIR is cleared when the DSP sets the
DTIC bit in the DSR (Table 5-18 on page 5-25)
at the end of its IRQD service routine. For proper MTIR operation, IRQD should be enabled via IPRC bits 10Ð9 and made level-sensitive by clearing IPRC bit 11.
Software should verify that MTIR is cleared before issuing an MDI reset (setting the MDIR bit in the MCR).
Settings
0 = Latest MRR0 data has been read
(default).
1 = New data in MRR0.
0 = Latest MRR1 data has been read
(default).
1 = New data in MRR1.
0 = DRR0 has not been read.
1 = DRR0 has been read (default).
0 = DRR1 has not been read.
1 = DRR1 has been read (default).
0 = No interrupt request (default).
1 = DSP has issued interrupt request 0.
0 = No interrupt request (default).
1 = DSP has issued interrupt request 1.
0 = No outstanding MTIR-generated interrupt request (default).
1 = DSP has not serviced last
MTIR-generated interrupt.
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MDI Registers
Table 5-12. MSR Description (Continued)
Name
DWS
Bit 8
DRS
Bit 7
MSMP
Bit 6
DPM
Bit 5
Type
1 Description
R/1S DSP Wake From STOPÑ Set by MCU software to wake the DSP from STOP mode. Setting
DWS also asserts DSP IRQC (waking the DSP from STOP mode) and IRQA, which is wire-orÕd to IRQC. DWS is cleared when the DSP sets
the DWSC bit in the DSR (Table 5-18 on page 5-25) at the end of its IRQC service
routine. IRQC should be enabled via the ICPL bit in the IPRC and made level-sensitive by clearing the ICTM bit in the IPRC. Software should verify that DWS is cleared before issuing an MDI reset.
R DSP Reset StateÑ Set by any DSP reset:
¥ MCU system reset
¥ DSP hardware reset (caused by setting the
DHR bit in the MCR)
¥ MDI reset (caused by setting the MDIR bit in the MCR)
DRS is cleared by DSP hardware as it completes the reset sequence. Software should ensure that DRS is cleared before accessing
MDI shared memory.
R
R
MCU Shared Memory Access PendingÑ Set by an MCU write to MDI shared memory.
Cleared when write access is complete.
Software should ensure that MSMP is cleared before issuing an MDI reset to ensure that no pending write is lost.
DSP Power ModeÑ Reflects the DSP mode of operation.
Settings
0 = No outstanding DWS-generated interrupt request (default).
1 = DSP has not serviced last
DWS-generated interrupt.
0 = DSP has completed the most recent reset sequence.
1 = DSP has not completed the most recent reset sequence (default).
0 = No outstanding MCU-MDI write
(default).
1 = Last MCU write to MDI shared memory has not been completed.
0 = DSP is in normal or WAIT mode
(default).
1 = DSP is in STOP mode.
0 = Last event update request to DSP has been acknowledged.
1 = Event update request to DSP pending.
MEP
Bit 4
MF[2:0]
Bits 2Ð0
R MCU-Side Event PendingÑ Set when the
MCU sends an event update request to the
DSP side. Cleared when the event update acknowledge has been received. An ÒeventÓ is any hardware message that should be reflected in the DSR on the DSP-side (e.g., Òtransmit register 0 writtenÓ). Software should poll MEP until it is cleared before entering STOP mode.
Reading the MSR to check the MEP bit should be the last MDI access before entering STOP, otherwise the MEP can be set as a result of that additional action. If MEP is not properly verified, entering the MCU STOP power mode may not to be reflected at the DSR.
MCU FlagsÑ General-purpose flag bits reflecting the state of DMF[2:0] (DCR bits 2Ð0).
1.
R = Read only.
R/1S = Read, or write with 1 to set (write with 0 ignored).
R/1C = Read, or write with 1 to clear (write with 0 ignored).
0 = Corresponding DMF bit cleared.
1 = Corresponding DMF bit set.
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MDI Registers
MTR1
BIT 15 14 13 12 11
MCU Transmit Register 1
10 9 8 7 6
Ñ
5
Ñ
Transmitted data from MCU to DSP
Ñ Ñ Ñ Ñ Ñ
4 3
$0020_2FF8
2 1 BIT 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 5-13. MTR1 Description
MTR1 is a 16-bit write-only register. Data written to MTR1 is reflected on the DSP side in DRR1. MTR1 and DRR1 are not double buffered. Writing to MTR1 overwrites the data in DRR1, clears the MCU Transmit Register 1 Empty bit (MTE1) in the MSR, and sets the DSP Receive Register 1 Full bit (DRF1) in the DSR. It can also trigger a receive interrupt on the DSP side if the DRIE1 bit in the DCR is set. A single 8-bit write to MTR1 also updates all status information.
MTR0
BIT 15 14 13 12 11
MCU Transmit Register 0
10 9 8 7 6
Ñ
5
Ñ
Transmitted data from MCU to DSP
Ñ Ñ Ñ Ñ Ñ
4 3
$0020_2FFA
2 1 BIT 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 5-14. MTR0 Description
MTR0 is a 16-bit write-only register. Data written to MTR0 is reflected on the DSP side in DRR0. MTR0 and DRR0 are not double buffered. Writing to MTR0 overwrites the data in DRR0, clears the MCU Transmit Register 0 Empty
(MTE0) bit in the MSR, and sets the DSP Receive Register 0 Full bit (DRF0) in the DSR. It can also trigger a receive interrupt on the DSP side if the DRIE0 bit in the DCR is set. A single 8-bit write to MTR0 also updates all status information.
MRR1
BIT 15 14 13 12 11
MCU Receive Register 1
10 9 8 7 6
Ñ
5
Ñ
Transmitted data from MCU to DSP
Ñ Ñ Ñ Ñ Ñ
4 3
$0020_2FFC
2 1 BIT 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 5-15. MRR1 Description
MRR1 is a 16-bit read-only register that reflects the data written on the DSP side to DTR1. Reading MRR1 clears the MCU Receive Register 1 Full bit (MRF1) in the MSR and sets the DSP Transmit Register 1 Empty bit (DTE1) in the DSR. It can also trigger a transmit interrupt on the DSP side if the DTIE1 bit in the DCR is set. A single 8-bit read from MRR1 also updates all status information.
MRR0
BIT 15 14 13 12 11
MCU Receive Register 0
10 9 8 7 6
Ñ
5
Ñ
Transmitted data from MCU to DSP
Ñ Ñ Ñ Ñ Ñ
4 3
$0020_2FFE
2 1 BIT 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 5-16. MRR0 Description
MRR0 is a 16-bit read-only register that reflects the data written on the DSP side to DTR0. Reading MRR0 clears the MCU Receive Register 0 Full bit (MRF0) in the MSR and sets the DSP Transmit Register 0 Empty bit (DTE0) in the DSR. It can also trigger a transmit interrupt on the DSP side if the DTIE0 bit in the DCR is set. A single 8-bit read from MRR0 also updates all status information.
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MDI Registers
5.6.2 DSP-Side Registers
DCR
BIT 15 14 13 12
DTIE0 DTIE1 DRIE0 DRIE1
RESET 0 0 0 0
DSP-Side Control Register
11 10 9 8 7 6
0 0 0
MCIE
0 0 0
5
0
4 3
X:$FF8A
1 BIT 0 2
0
DMF[2:0]
0 0 0 0
Note: The MDIPL bits in the Peripheral Interrupt Priority Register (IPRP) must written with a non-zero value in order to generate any of the interrupts enabled
Table 5-17. DCR Description
Description Name
DTIE0
Bit 15
DTIE1
Bit 14
DRIE0
Bit 13
DRIE1
Bit 12
MCIE
Bit 8
DMF[2:0]
Bits 2Ð0
Settings
DSP Transmit Interrupt Enable 0ÑI f DTIE0 is set, a transmit interrupt 0 request is generated when the
DTE0 bit in the DSR is set. If DTIE0 bit is cleared,
DTE0 is ignored and no transmit interrupt request 0 is issued.
DSP Transmit Interrupt Enable 1Ñ If DTIE1 is set, a transmit interrupt 1 request is generated when the
DTE1 bit in the DSR is set. If DTIE1 bit is cleared,
DTE1 is ignored and no transmit interrupt request 1 is issued.
0 = Transmit interrupt 0 request disabled
(default).
1 = Enabled.
0 = Transmit interrupt 1 request disabled
(default).
1 = Enabled.
DSP Receive Interrupt Enable 0Ñ When DRIE0 is set, a receive interrupt request 0 is issued when the
DRF0 bit in the DSR is set. When DRIE0 is cleared,
DRF0 is ignored and no receive interrupt request 0 is issued.
0 = Receive interrupt 0 request disabled
(default).
1 = Enabled.
DSP Receive Interrupt Enable 1Ñ When DRIE1 is set, a receive interrupt request 1 is issued when the
DRF1 bit in the DSR is set. When DRIE1 is cleared,
DRF1 is ignored and no receive interrupt request 1 is issued.
0 = Receive interrupt 1 request disabled
(default).
1 = Enabled.
MCU Command Interrupt EnableÑI f this bit is set, the MCP bit in the DSR is set, and the MNMI bit in the MCVR is clear, a maskable command interrupt is issued. If MNMI is set, MCIE is ignored. In this case, if the MCP bit in the DSR is set, a non-maskable interrupt is issued.
0 = Maskable interrupts disabled (default).
1 = Maskable interrupts enabled.
DSP-to-MCU FlagsÑ General-purpose flag bits that are reflected on the MCU side in the MF[2:0] bits in the MSR.
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MDI Registers
DSR
BIT 15 14 13 12 11
DSP-Side Status Register
10 9 8 7 6 5 4
DTE0 DTE1 DRF0 DRF1 DGIR0 DGIR1 DTIC MCP DWSC MPM1 MPM0 DEP
RESET 1 1 0 0 0 0 0 0 0 Ñ Ñ 0
3
0
Table 5-18. DSR Description
Name Type
1 Description Settings
2
Ñ
X:$FF8B
1 BIT 0
DF[2:0]
Ñ Ñ
DTE0
Bit 15
DTE1
Bit 14
DRF0
Bit 13
DRF1
Bit 12
DGIR0
Bit 11
DGIR1
Bit 10
DTIC
Bit 9
MCP
Bit 8
R
R
R
R
DSP Receive Register 0 FullÑ Set when the
MCU writes to MTR0, indicating to the DSP that the reflected data is available in DRR0.
DRF0 is cleared when the DSP reads DRR0.
0 = Latest DRR0 data has been read
(default).
1 = New data in DRR0.
DSP Receive Register 1 FullÑ Set when the
MCU writes to MTR1, indicating to the DSP that the reflected data is available in DRR1.
DRF1 is cleared when the DSP reads DRR1.
0 = Latest DRR1 data has been read
(default).
1 = New data in DRR1.
0 = No interrupt request 0 (default).
1 = DSP has issued interrupt request 0.
R/1S DSP General Interrupt Request 0Ñ Setting this bit generates an interrupt request to the
MCU if the MGIE0 bit in the MCR is set. It is reflected in the MGIP0 bit in the MSR. It is cleared when the MCU clears MGIP0, indicating to the DSP that the MCU has serviced the interrupt.
R/1S DSP General Interrupt Request 1Ñ Setting this bit generates an interrupt request to the
MCU if the MGIE1 bit in the MCR is set. It is reflected in the MGIP1 bit in the MSR. It is cleared when the MCU clears MGIP1, indicating to the DSP that the MCU has serviced the interrupt.
0 = No interrupt request 1 (default).
1 = DSP has issued interrupt request 1.
1S
DSP Transmit Register 0 EmptyÑ Indicates if the MCU has read the most recent transmission to MRR0. This bit is subject to
DSP pipeline restrictions (See Table 5-6 on page 5-15.)
0 = Last transmission to MRR0 has not been read
1 = Last transmission to MRR0 has been read (default).
DSP Transmit Register 1 EmptyÑ Indicates if the MCU has read the most recent transmission to MRR1. This bit is subject to
DSP pipeline restrictions. (See Table 5-6 on page 5-15.)
0 = Last transmission to MRR1 has not been read
1 = Last transmission to MRR1 has been read (default).
R
DSP Protocol Timer Interrupt ClearÑ Used by the Protocol Timer DSP interrupt (IRQD) service routine to clear the interrupt. Writing Ò1Ó to this bit clears the MTIR bit in the MSR, thus deasserting IRQD (and IRQA, which is wire-orÕd to IRQD) and enabling MTIR to receive another interrupt. DTIC always reads zero.
MCU Command PendingÑ Set when the MC
bit in the MCVR is set (page 5-18); cleared
when the interrupt generated by setting MC is serviced.
0 = No outstanding DSP command interrupt (default).
1 = DSP command interrupt has been issued and has not been serviced.
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MDI Registers
Table 5-18. DSR Description (Continued)
Name Type
1 Description Settings
DWSC
Bit 7
MPM[1:0]
Bits 6Ð5
DEP
Bit 4
1S
R
R
DSP Wake from STOP and Interrupt ClearÑ Used by the MDI Wake from STOP and general interrupt (IRQC) service routine to clear the interrupt. Writing Ò1Ó to this bit clears the DWS bit in the MSR, thus de-asserting IRQC (and IRQA) and enabling DWS to receive another interrupt.
MCU Power ModeÑ Reflect the MCU power mode.
00 = STOP
01 = WAIT
10 = DOZE
11 = Normal
DSP-Side Event PendingÑ Set when the
DSP sends an event update request to the
MCU side. Cleared when the event update acknowledge has been received. An ÒeventÓ is any hardware message that should be reflected in the MSR on the MCU-side (e.g.,
Òtransmit register 0 writtenÓ). Software should poll DEP until it is cleared before entering
STOP mode. Reading the DSR to check the
DEP bit should be the last MDI access before entering STOP, otherwise the DEP can be set as a result of that additional action. Allow three NOPs (or their equivalent timing) after an instruction that sets an event before DEP is updated to accommodate pipeline effects.
Proper verification of DEP value can prevent loss of shared memory accesses and failure to inform the MCU side of events while the
DSP is in STOP mode.
0 = Last event update request to MCU has been acknowledged (default).
1 = Event update request to MCU pending.
DF[2:0]
Bits 2Ð0
R MCU FlagsÑ
MSR.
Reflect the MDF[2:0] bits in the
1.
R = Read only.
1S = Write 1 only (write with 0 ingored).
R/1S Read; write 1 only (write with 0 ingored)
0 = Corresponding MDF bit cleared.
1 = Corresponding MDF bit set.
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MDI Registers
DTR1
BIT 15 14 13 12 11
DSP Transmit Register 1
10 9 8 7 6
Ñ
5
Ñ
Transmitted data from MCU to DSP
Ñ Ñ Ñ Ñ Ñ
4 3 2
X:$FF8C
1 BIT 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 5-19. DTR1 Description
DTR1 is a 16-bit write-only register. Data written to DTR1 is reflected on the MCU side in MRR1. DTR1 and MRR1 are not double buffered. Writing to DTR1 overwrites the data in MRR1, clears the DTE1 bit in the DSR, and sets the
MRF1 bit in the MSR. It can also trigger a receive interrupt on the MCU side if the MRIE1 bit in the MCR is set.
DTR0
BIT 15 14 13 12 11
DSP Transmit Register 0
10 9 8 7 6
Ñ
5
Ñ
Transmitted data from MCU to DSP
Ñ Ñ Ñ Ñ Ñ
4 3 2
X:$FF8D
1 BIT 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 5-20. DTR0 Description
DTR0 is a 16-bit write-only register. Data written to DTR0 is reflected on the MCU side in MRR0. DTR0 and MRR0 are not double buffered. Writing to DTR0 overwrites the data in MRR0, clears the DTE0 bit in the DSR, and sets the
MRF0 bit in the MSR. It can also trigger a receive interrupt on the MCU side if the MRIE0 bit in the MCR is set.
DRR1
BIT 15 14 13 12 11
DSP Receive Register 1
10 9 8 7 6
Ñ
5
Ñ
Transmitted data from DSP to DSP
Ñ Ñ Ñ Ñ Ñ
4 3 2
X:$FF8E
1 BIT 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 5-21. DRR1 Description
DRR1 is a 16-bit read-only register that reflects the data written on the MCU side to MTR1. Reading DRR1 clears the DRF1 bit in the DSR, sets the DTE1 bit in the MSR, and can trigger a transmit interrupt on the MCU side if the
MTIE1 bit in the MCR is set.
DRR0
BIT 15 14 13 12 11
DSP Receive Register 0
10 9 8 7 6
Ñ
5
Ñ
Transmitted data from DSP to DSP
Ñ Ñ Ñ Ñ Ñ
4 3 2
X:$FF8F
1 BIT 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 5-22. DRR0 Description
DRR0 is a 16-bit read-only register that reflects the data written on the MCU side to MTR0. Reading DRR0 clears the DRF0 bit in the DSR, sets the DTE0 bit in the MSR, and can trigger a transmit interrupt on the MCU side if the
MTIE0 bit in the MCR is set.
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MDI Registers
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Chapter 6
External Interface Module
The EIM provides signals and logic to connect memory and other external devices to the
DSP56652. EIM features include the following:
¥ Twenty-two-bit external address bus and 16-bit external data bus
¥ Six chip selects for external devices, each of which provides
Ñ A 4-Mbyte range
Ñ Programmable wait state generator
Ñ Selectable protection
Ñ Programmable data port size
Ñ General output signal if not used as a chip select
¥ External or internal boot ROM device selection
¥ Bus watchdog counter for all bus cycles
¥ External monitoring of internal bus cycles
Figure 6-1 shows a block diagram of the EIM.
Motorola
A0ÐA31, R/W, TSIZ, TC
D0ÐD31
TREQ, TBUSY, ABORT
TA, TEA
External
Interface
Module
Figure 6-1. EIM Block Diagram
MOD
EB0ÐEB1
OE
R/W
A0ÐA21
D0ÐD15
CS0
CS1
CS2
CS3
CS4
CS5
SIZ0ÐSIZ1
PSTAT0ÐPSTAT1
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Figure 6-2 shows an example of an EIM interface to memory and peripherals.
A[0Ð21]
CS2
OE
Data [0Ð15]
A[0Ð16]
EB1
D[0Ð7]
Address [0Ð16]
CS
WE
OE
RAM
128Kx8
Data [0Ð7]
External
Interface
Module
EB1
EB0
CS1
R/W
CS0
A[1Ð16]
EB1
EB0
R/W
OE
A[1Ð19]
EB1
OE
Address [0Ð15]
LB
UB
CS
WE
RAM
64Kx16
OE
Data [0Ð15]
Address [0Ð18]
CS
WE
OE
Flash
512Kx16
Data [0Ð15]
CS5
A0
R/W
RS
E
R/W
LCD
Control
Data [0Ð7]
Figure 6-2. Example EIM Interface to Memory and Peripherals
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EIM Signals
6.1 EIM Signals
The EIM signal descriptions in Section 2.4, ÒExternal Interface Module,Ó are repeated and
expanded in Table 6-1 for convenience.
Table 6-1. EIM Signal Description
Signal Name
A0ÐA21
Type Reset State
Output Driven low
D0ÐD15
R/W
EB0
EB1
OE
MOD
CS0
CS1ÐCS4
CS5
Input/
Output
Output
Output
Output
Output
Input
Output
Output
Output
Input
Driven high
Driven high
Driven high
Driven high
Input
Chip-driven
Driven high
Driven low
Signal Description
Address busÑ These signals specify the address for external memory accesses. If there is no external bus activity, A0ÐA21 remain at their previous values to reduce power consumption.
Data bus ÑThese signals provide the bidirectional data bus for external memory accesses. They remain in their previous logic state when there is no external bus activity to reduce power consumption.
Read/write ÑThis signal indicates the bus access type. A high signal indicates a bus read. A low signal indicates a write to the bus. This signal can also be used as a memory write enable (WE) signal. When accessing a peripheral chip, the signal acts as a read/write.
Enable byte 0 ÑWhen driven low, this signal indicates access to data byte 0 (D8ÐD15) during a read or write cycle. This pin may also act as a write byte enable, if so programmed.
Enable byte 1 ÑWhen driven low, this signal indicates access to data byte 1 (D0ÐD7) during a read or write cycle. This pin may also act as a write byte enable, if so programmed.
Output EnableÑ When driven low, this signal indicates that the current bus access is a read cycle and enables slave devices to drive the data bus with a read.
Mode Select ÑThis signal selects the MCU boot mode during hardware reset. It should be driven at least four CKIL clock cycles before
RESET_OUT is deasserted.
¥ MOD driven highÑMCU fetches the first word from internal MCU
ROM.
¥ MOD driven lowÑMCU fetches the first word from the external memory (CS0).
Chip select 0Ñ This signal is asserted low based on the decode of the internal address bus bits A[31:24] and the state of the MOD pin at reset. It is often used as the external flash memory chip select. After reset, CS0 access has a default of 15 wait states and a port size of 16 bits.
Chip selects 1Ð4Ñ These signals are asserted low based on the decode of the internal address bus bits A[31:24] of the access address. When not configured as chip selects, these signals become general purpose outputs (GPOs). After reset, these signals are GPOs that are driven high.
Chip select 5Ñ This signal is asserted high based on the decode of the internal address bus bits A[31:24] of the access address. When not configured as a chip select, this signal functions as a GPO. After reset, this signal is a GPO that is driven low.
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6.2 Chip Select Address Ranges
Each of the six chip select signals corresponds to a 16-Mbyte block in the MCU address space. Note that only 22 address lines are available, so only the first four Mbytes in each chip select space can be addressed. An access above the 4-Mbyte limit modulo-wraps
back into the addressable space and is not recommended. Table 6-2 lists the allocated and
addressable ranges for each chip select.
Chip Select
Table 6-2. Chip Select Address Range
A[31:24]
CS0 01000000
CS1 01000001
CS2
CS3
01000010
01000011
CS4
CS5
01000100
01000101
Allocated Memory Space (16
Mbytes)
$4000_0000Ð$40FF_FFFF
$4100_0000Ð$41FF_FFFF
$4200_0000Ð$42FF_FFFF
$4300_0000Ð$43FF_FFFF
$4400_0000Ð$44FF_FFFF
$4500_0000Ð$45FF_FFFF
Addressable Range (4 Mbytes)
$4000_0000Ð$403F_FFFF
$4100_0000Ð$413F_FFFF
$4200_0000Ð$423F_FFFF
$4300_0000Ð$433F_FFFF
$4400_0000Ð$443F_FFFF
$4500_0000Ð$453F_FFFF
6.3 EIM Features
This section discusses the following features of the EIM:
¥ Configurable bus sizing
¥ External boot ROM control
¥ Bus watchdog operation
¥ Error condition reporting
¥ External display of internal bus activity
¥ Emulation Port
¥ General-purpose outputs
6.3.1 Configurable Bus Sizing
The EIM supports byte, halfword, and word operands, allowing access to 8- and 16-bit ports. It does not support misaligned transfers. The port size for each chip select is programmed through the DSZ[1:0] bits in the associated CS control register. In addition, the portion of the data bus used for transfer to or from an 8-bit port is programmable via
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EIM Features the same bits. An 8-bit port can reside on external data bus bits D[15:8] or D[7:0].
Connecting 8-bit devices to D[15:8] reduces the load on the lower data lines.
A word access to or from an 8-bit port requires four bus cycles to complete. A word access to or from a 16-bit port requires two bus cycles to complete. A halfword access to or from an 8-bit port requires two bus cycles to complete. In a multi-cycle transfer, the lower two address bits (A[1:0]) are incremented appropriately.
The EIM contains a data multiplexer that routes the four bytes of the MCU interface data bus to their required positions for proper interface to memory and peripherals.
Table 6-3 summarizes the possible transfer sizes, alignments, and port widths as well as
the SIZ1ÐSIZ0 signals, A1ÐA0 signals, and DSZ[1:0] bits used to generate them.
6.3.2 External Boot ROM Control
The MOD input signal is used to specify the location of the boot ROM device during hardware reset. If an external boot ROM is used instead of the internal ROM, the CS0 output can be used to select the external ROM coming out of reset.
If MOD is driven low at least four CKIL clock cycles before RESET_OUT deassertion, the internal MCU ROM is disabled and CS0 is asserted for the first MCU cycle. The MCU fetches the reset vector from address $0 of the CS0 memory space, which is located at the absolute address $4000_0000 in the MCU address space. The internal MCU ROM is disabled for the first MCU cycle only and is available for subsequent accesses. Out of
Reset, CS0 is configured for 15 wait states and a 16-bit port size. If MOD is driven high at least four CKIL clock cycles before RESET_OUT deassertion, the internal ROM is enabled and the MCU fetches the reset vector from internal ROM at address $0000_0000.
6.3.3 Bus Watchdog Operation
The EIM contains a bus watchdog timer that monitors the length of all request accesses from the MCU. If an access does not terminate (i.e., the bus watchdog timer does not receive an internal Transfer Acknowledge (TA) signal or Transfer Error Acknowledge
(TEA) signal) within 128 clock cycles of being initiated, the bus watchdog timer expires and forces the access to be terminated by negating the Chip Select output and any control signals that were asserted during the access. The bus watchdog timer then asserts a TEA signal back to the MCU, resulting in an access error exception. The bus watchdog timer is automatically reset after the termination of each access. If for some reason an internal
MCU peripheral does not terminate its access to the MCU, or if the MCU accesses an unmapped location, the bus watchdog times out and prevents the MCU from locking up.
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EIM Features
Table 6-3. Interface Requirements for Read and Write Cycles
Signal Encoding
Port
Width
Active Interface Bus Sections
1
Transfer
Size
SIZ1 SIZ0 A1 A0 DSZ[1:0]
Internal
D[31:24]
Internal
D[23:16]
Internal
D[15:8]
Internal
D[7:0]
Byte
Halfword
0
1
1
0
0
0
1
1
0
0
1
0
1 x
10
00
01
10
01
10
00
01
00
01
10
00
00
01
10
D[15:8]
D[7:0]
D[15:8]
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
D[15:8]
D[7:0]
D[15:8]
Ñ
Ñ
Ñ
D[15:8]
D[7:0]
D[7:0]
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
D[15:8]
D[7:0]
D[7:0]
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
D[15:8]
D[7:0]
D[15:8]
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Word 0 0
1 x x x
00
01
10
00
Ñ
Ñ
Ñ
D[15:8]
Ñ
Ñ
Ñ
D[15:8]
D[15:8]
D[7:0]
D[15:8]
D[15:8]
D[15:8]
D[7:0]
D[7:0]
D[15:8]
01
10
D[7:0]
D[15:8]
D[7:0]
D[7:0]
D[7:0]
D[15:8]
D[7:0]
D[7:0]
1.
Bytes labeled with a dash are not required. They are ignored on read transfers and driven with undefined data on write transfers.
Ñ
Ñ
D[15:8]
D[7:0]
D[7:0]
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
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EIM Features
6.3.4 Error Conditions
The following conditions cause a Transfer Error Acknowledge (TEA) to be asserted to the
MCU:
¥ An access to a disabled chip-select (i.e., an access to a mapped chip-select address space where the CSEN bit in the corresponding CS control register is clear).
¥ A write access to a write-protected chip-select address space (i.e., the WP bit in the corresponding CS control register is set).
¥ A user access to a supervisor-protected chip-select address space (i.e., the SP bit in the corresponding CS control register is set).
¥ A bus watchdog time-out when an access does not terminate within 128 clocks of being initiated.
¥ A user access to a supervisor-protected internal ROM, RAM, or peripheral space
(i.e., the corresponding SP bit in the EIM Configuration register is set).
6.3.5 Displaying the Internal Bus (Show Cycles)
Although the MCU can transfer data between internal modules without using the external bus, it may be useful to display an internal bus cycle on the external bus for debugging purposes. Such external bus cycles, called show cycles, are enabled by the SHEN[1:0] bits in the EIM Configuration Register (EIMCR).
When show cycles are enabled, the EIM drives the internal address bus A[21:0] onto the external address bus pins A21ÐA0. In addition, the internal data bus D[31:16] or D[15:0] is driven onto the external data bus pins D15ÐD0 according to the HDB bit in the EIMCR.
6.3.6 Programmable Output Generation
Any chip select signal except CS0 can be used as general-purpose output by clearing the
CSEN bit in the corresponding CS control register. (When the CSEN bit in the CS0 register is cleared, CS0 is inactive.)
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EIM Features
6.3.7 Emulation Port
The DSP56652 provides a six-pin Emulation Port for debugging to provide information about the data size and pipeline status of the current bus cycle. The SIZ[1:0] pins indicate
bit in the EIMCR and serve as GPIO pins if the port is not enabled.
Table 6-4. SIZ[1:0] Encoding
SIZ1 SIZ0 Transfer Size
1
1
0
0
0
1
0
1
Word (32 bits)
Byte (8 bits)
Halfword (16 bits)
Reserved
Table 6-5. PSTAT[3:0] Encoding
1
1
1
1
1
1
1
PSTAT3 PSTAT2 PSTAT1 PSTAT0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Internal Processor Status
Execution Stalled
Execution Stalled
Execute Exception
Reserved
Processor in Stop, Wait, or Doze mode
Execution Stalled
Processor in Debug Mode
Reserved
Launch instruction
1
Launch ldm, stm, ldq, stq
Launch Hardware Accelerator instruction
Launch lrw
Launch change of Program Flow instruction
Launch rte or rfi
Reserved
Launch jmpi or jsri
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EIM Registers
1.
Except rte, rfi, ldm, stm, ldq, stq, lrw, hardware accelerator, or change of flow instructions
6.4 EIM Registers
CSCR0
CSCR1
CSCR2
CSCR3
CSCR4
CSCR5
31Ð16 15 14 13 12
WSC[3:0]
Chip Select 0 Control Register
Chip Select 1 Control Register
Chip Select 2 Control Register
Chip Select 3 Control Register
Chip Select 4 Control Register
Chip Select 5 Control Register
11 10 9 8 7 6 5 4
WWS EDC CSA OEA WEN EBC DSZ[1:0]
RESET CS0
CS1
CS2
CS3
CS4
CS5
1 1 1 1
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ
1
Ñ
Ñ
Ñ
Ñ
Ñ
0
Ñ
Ñ
Ñ
Ñ
Ñ
0
Ñ
Ñ
Ñ
Ñ
Ñ
0
Ñ
Ñ
Ñ
Ñ
Ñ
0
Ñ
Ñ
Ñ
Ñ
Ñ
1
Ñ
Ñ
Ñ
Ñ
Ñ
1
Ñ
Ñ
Ñ
Ñ
Ñ
0
Ñ
Ñ
Ñ
Ñ
Ñ
Table 6-6. CSCRn Description
Settings Name
WSC[3:0]
Bits15Ð12
Description
Wait State Control BitsÑ Determine the number of wait states for an access to the external device connected to the Chip Select. When WWS is cleared, setting WSC[3:0] = 0000 results in one-clock transfers, WSC[3:0] = 0001 results in two-clock transfers, and WSC[3:0] = 1111 results in
16-clock transfers. When WSC[3:0] = 0000, the
WEN, OEA, and CSA bits are ignored.
0
Ñ
Ñ
Ñ
Ñ
Ñ
3
$0020_1000
$0020_1004
$0020_1008
$0020_100C
$0020_1010
$0020_1014
2 1 BIT 0
SP WP PA CSEN
0
Ñ
Ñ
Ñ
Ñ
Ñ
1
1
1
1
0
0
0
1
0
0
0
WSC
[3:0]
0000
0001
0010
:
1101
1110
1111
Number of Wait States
WWS = 0 WWS = 1
Read Write Read Write
13
14
15
2
:
0
1
0
1
2
:
13
14
15
0
1
2
:
13
14
15
14
15
15
3
:
1
2
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EIM Registers
Name
WWS
Bit 11
EDC
Bit 10
CSA
Bit 9
OEA
Bit 8
WEN
Bit 7
EBC
Bit 6
DSZ[1:0]
Bits 5Ð4
Table 6-6. CSCRn Description (Continued)
Description Settings
Write Wait StateÑ Specifies whether an additional wait state is inserted for write cycles. When WWS is set, an additional wait state is inserted for write cycles (unless WSC[3:0] = 1111, which results in a
16- clock cycle write time, regardless of the WWS bit). Read cycles are not affected. When this bit is cleared, reads and writes are of the same length.
Setting this bit is useful for writing to slower memories (such as Flash memories) that require additional data setup time.
0 = Reads and writes are same length.
1 = Writes have an additional wait state
(except when WSC[3:0] = 1111).
Extra Dead CycleÑ When set, inserts an idle cycle after a read cycle for back-to-back external transfers, unless the next cycle is a read cycle to the same CS bank to eliminate data bus contention. This is useful for slow memory and peripherals that have long CS or OE to output data tri-state times.
0 = Back-to-back external transfers occur normally.
1 = Extra idle cycle inserted in back-to-back external transfers unless the next cycle is a read cycle to the same CS.
Chip Select AssertÑ When CSA is set, Chip
Select is asserted one clock cycle later during both read and write cycles, and an idle cycle is inserted between back-to-back external transfers. Useful for devices that require additional address setup time and address/data hold times. If WSC[3:0] = 0000, the CSA bit is ignored.
0 = Chip Select asserted normally (i.e., as early as possible); no idle cycle inserted.
1 = Chip Select asserted one cycle later; idle cycle inserted in back-to-back external transfers.
OE AssertÑ When OEA is set, OE is asserted one half-clock later during a read to the CSÕs address space. Cycle length is not affected, and write cycles are not affected. If WSC[3:0] = 0000, OEA is ignored and OE is asserted for half a clock only. If
EBC in the corresponding register is cleared, the
EB0Ð1 outputs are similarly affected.
0 = OE asserted normally (i.e., as early as possible).
1 = OE asserted one half cycle later during a read.
Write EB NegateÑ When WEN is set, EB0Ð1 are negated one half-clock earlier during a write to the
CSÕs address space. Cycle length is not affected, and read cycles are not affected. If WSC[3:0] =
0000, WEN is ignored and is EB0Ð1 are asserted for half a clock only. WEN is useful for meeting data hold time requirements for slow memories.
0 = EB0Ð1 negated normally (i.e., as late as possible).
1 = EB0Ð1 negated one half cycle earlier during a write.
Enable Byte ControlÑ When EBC is set, only write accesses assert the EB0Ð1 outputs, thus configuring them as byte write enables. EBC should be set for accesses to dual x8 memories.
0 = EB0Ð1 asserted for both reads and writes.
1 = EB0Ð1 asserted for writes only.
Data Port SizeÑ These bits define the width of the device data port.
00 = 8-bit port on D[15:8] pins.
01 = 8-bit port on D[7:0] pins.
10 = 16-bit port on D[15:0] pins.
11 = Reserved.
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EIM Registers
Name
SP
Bit 3
WP
Bit 2
PA
Bit 1
CSEN
Bit 0
Table 6-6. CSCRn Description (Continued)
Description Settings
Supervisor ProtectÑ Prohibits User Mode accesses to the CS address space. When SP is set, a read or write to the CS space while in User
Mode generates a TEA error and the CS signal is not asserted.
Write ProtectÑ Prohibits writes to the CS address space. When WP is set, a write attempt to the CS space generates a TEA error and the CS signal is not asserted.
0 = User Mode access allowed.
1 = User Mode access prohibited.
0 = Writes allowed.
1 = Writes prohibited.
Pin AssertÑ Controls the Chip Select pin when it is operating as a general-purpose output (i.e., the
CSEN bit is cleared). This bit is ignored if the CSEN bit is set. Note that Chip Select 0 does not have a
PA bit.
0 = CS pin at logic low.
1 = CS pin at logic high.
Chip Select EnableÑ When CSEN is set, the CS pin is asserted during an access to its address space. When CSEN is cleared, an access to the
CS address space generates a TEA error and the
CS pin is not asserted.
0 = CS pin disabled.
1 = CS pin enabled.
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EIM Registers
EIMCR
RESET
BIT 31
0
EIM Configuration Register
7 6 5 4 3
$0020_1018
2 1 BIT 0
EPEN SPIPER SPRAM SPROM HDB SHEN1[:0]
0 1 1 1 0 0 0
Table 6-7. EIMCR Description
Name Description Settings
EPEN
Bit 6
SPIPER
Bit 5
SPRAM
Bit 4
SPROM
Bit 3
HDB
Bit 2
SHEN[1:0]
Bits 1Ð0
Emulation Port EnableÑ Controls the functions of the Emulation Port pins, SIZ[1:0] and PSTAT[3:0].
0 = Pins function as GPIO (default).
1 = Emulation Port drives the pins with the
MCU SIZ[1:0] and PSTAT[3:0] signals.
Supervisor Protect Internal PeripheralÑ
Prohibits User Mode access to all internal peripheral space. When SPIPER is set, a read or write to the internal peripheral space while in User
Mode generates a TEA error. This bit does not affect CSCR0Ð5 or EIMCR, which can only be accessed in supervisor mode.
0 = User Mode access to internal peripherals allowed.
1 = User Mode access to internal peripherals prohibited (default).
Supervisor Protect Internal RAMÑ Prohibits User
Mode access to internal RAM. When SPRAM is set, a read or write to the internal RAM while in
User Mode generates a TEA error.
0 = User Mode access to internal RAM allowed.
1 = User Mode access to internal RAM prohibited (default).
Supervisor Protect Internal ROMÑ Prohibits User
Mode access to internal ROM. When SPROM is set, a read or write to the internal ROM while in
User Mode generates a TEA error.
0 = User Mode access to internal ROM allowed.
1 = User Mode access to internal ROM prohibited (default).
High Data BusÑ selects the internal halfword to be placed on the external data bus during a Show
Cycle. This bit is ignored when SHEN[1:0] are cleared.
0 = Lower halfword (D[15:0]) (default).
1 = Upper halfword (D[31:16]).
Show Cycle EnableÑ These bits enable the internal buses to be reflected on the external buses during accesses to internal RAM, ROM, or peripherals. They can also delay internal termination to the MCU during idle cycles caused
by EDC or CSA being set (page 6-10). This
ensures that all internal transfers can be externally monitored, although this setting can impact performance.
00 = Show cycles disabled (default).
01 = Show cycles enabled. Internal termination to the MCU during idle cycles caused by EDC or CSA being set is not delayed, and internal transfers that occur during these EDA/CSA idle cycles will not be visible externally.
10 = Show cycles enabled. Internal termination to the MCU during idle cycles caused by EDC or CSA being set is delayed by one cycle. This ensures that all internal transfers can be externally monitored, at the expense of performance.
11 = Reserved.
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EIM Registers
EMDDR Emulation Port Data Direction Register
15 14 13 12 11 10 9 8 7 6 5 4 3
RESET 0 0 0 0 0 0 0 0 0 0
$0020_C800
1 BIT 0 2
EMDD5
(PSTAT3)
EMDD4
(PSTAT2)
EMDD3
(PSTAT1)
EMDD2
(PSTAT0)
EMDD1
(SIZ1)
0 0 0 0 0
EMDD0
(SIZ0)
0
Table 6-8. QDDR Description
Name Description Settings
EMDD[5:0]
Bits 7Ð0
Emulation Port Data Direction[5:0]Ñ determines whether each pin functions as an input or an output when the port functions as GPIO (Emulation Port is disabled).
0 = Input (default)
1 = Output
EMDR Emulation Port Data Register
15 14 13 12 11 10 9 8 7 6 5 4
RESET 0 0 0 0 0 0 0 0 0 0
3 2
EMD5
(PSTAT3)
EMD4
(PSTAT2)
EMD3
(PSTAT1)
EMD2
(PSTAT0)
0 0 0 0
$0020_C802
1 BIT 0
EMD1
(SIZ1)
0
EMD0
(SIZ0)
0
Table 6-9. QPDR Description
Name Description
EMD[5:0]
Bits 7Ð0
Emulation Port GPIO Data [5:0]Ñ Each of these bits contains data for the corresponding
Emulation Port pin if the port is configured as GPIO. Writes to EMDR are stored in an internal latch, and driven on any port pin configured as an output. Reads of this register return the value sensed on input pins and the latched data driven on outputs.
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Chapter 7
Interrupts
This section describes both the MCU and DSP interrupt controllers, including the various interrupt and exception sources and how they are configured and prioritized. The Edge I/O port, which provides eight pins for external MCU interrupts, is also described.
7.1 MCU Interrupt Controller
The MCU interrupt controller combines the speed of a highly microcoded architecture with the flexibility of polling techniques commonly employed in RISC designs. The result is a centralized mechanism that permits polling and prioritizing of the 32 interrupt sources with minimal software overhead. This mechanism includes the following features:
¥ Find-First-One instruction. This instruction provides a fast mechanism to prioritize pending interrupt requests. It scans the contents of a register and reports the position of the most significant set bit.
¥ Highest priority status.
Any interrupt can be configured as the highest priority, in which case it is assigned a vectored interrupt. Directly-vectored interrupts can be serviced with fewer instructions than autovectored interrupts, because polling to determine the interruptÕs source is not required. For more information refer to the
M¥CORE Reference Manual.
¥ Alternate register set. The MCU provides an alternate register set for interrupts, including general registers, status register and program counter, eliminating the need to save program context to the stack.
¥ Fast interrupts.
Critical interrupts can be processed using separate, dedicated program counter and status shadow registers not used by the other interrupts. Any source can be programmed to generate a normal or fast interrupt.
¥ Individual enable bits.
Each interrupt source is individually configured.
7.1.1 Functional Overview
The MCU interrupt controller is comprised of six registers:
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¥ ISR Ñ The Interrupt Source Register reflects the current state of all interrupt sources within the chip.
¥ NIER Ñ The Normal Interrupt Enable Register provides a centralized place to enable/disable interrupt requests and to assign interrupt sources to a normal interrupt.
¥ NIPR Ñ The Normal Interrupt Pending Register reflects the current state of all pending non-masked normal interrupt requests.
¥ FIER Ñ The Fast Interrupt Enable Register provides a centralized place to enable/disable interrupt requests and to assign interrupt sources to a fast interrupt.
¥ FIPR Ñ The Fast Interrupt Pending register reflects the current state of all pending non-masked fast interrupt requests.
¥ ICR Ñ The Interrupt Control Register selects the highest priority interrupt and its vector.
Figure 7-1 is a block diagram of the MCU interrupt controller.
ISR FIER FIPR ICR
Interrupts
From
Peripherals
Reg
Data Bus
Reg
Priority
Circuit
Fast
Interrupt to Core
Vector Number
Autovector
Low
Power
Wake-up
Reg
Interrupt to Core
NIER NIPR
Figure 7-1. MCU Interrupt Controller
7.1.2 Exception Priority
The MCU core imposes the following priority (from highest to lowest) among the various exceptions:
¥ Hardware Reset
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MCU Interrupt Controller
¥ Software Reset
¥ Hardware Breakpoint
¥ Fast Interrupt
¥ Normal Interrupt
¥ Instruction Generated Exceptions
¥ Trace
The interrupt controller registers prioritize the peripheral interrupts by designating each request as either an autovectored normal interrupt, autovectored fast interrupt, or vectored
fast interrupt. Figure 7-2 illustrates the priority mechanism in flowchart format.
Evaluate Once Per Clock
Highest
Priority Interrupt
Pending
?
No
Yes Assert Fast Interrupt and
Supply Vector Number
Fast
Interrupt Pending
?
No
Yes Assert Fast Interrupt and
Autovector
Normal
Interrupt Pending
?
No
Yes
No Interrupts Pending
Assert Normal Interrupt and
Autovector
Figure 7-2. Hardware Priority Flowchart
7.1.3 Enabling MCU Interrupt Sources
Three steps are required to enable MCU interrupt sources:
1. Assign each interrupt to either normal or fast processing, and set the appropriate bits in the NIER or FIER.
Each interrupt source can be assigned to either of two interrupt request inputs, normal or fast. Fast requests are serviced before normal requests; there is no difference in latency.
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The choice of interrupt request for each source depends on several factors driven by the end application, including:
¥ Rate of service requests
¥ Latency requirements
¥ Access to the alternate register bank
¥ Length of service routine
¥ Total number of interrupt sources in the system
Each interrupt source is enabled as a normal or fast interrupt by setting the appropriate bit in either the NIER or FIER. The enable bit should not be set in both registers simultaneously or both a normal and fast interrupt request will be generated.
2. Enable interrupts in the core by setting the following bits in the M¥CORE Program
Status Register:
Ñ Exception Enable (EE)
Ñ Interrupt Enable (IE)
Ñ Fast Interrupt Enable (FE)
Refer to the M¥CORE Reference Manual for more information on this register.
Steps 1 and 2 are normally done once during system initialization.
3. For each source from which interrupts are to be used, program the appropriate peripheral registers to generate interrupt requests.
7.1.4 Interrupt Sources
Table 7-1 lists each MCU interrupt source, the ISR bit that indicates when the interrupt is
asserted, and a page reference to the register that enables the interrupt. Several interrupt sources are logically ORed because there are more sources than there are inputs to the interrupt controller. In these cases, the peripheralÕs status register must be queried to determine the source of the interrupt within the peripheral.
Interrupt
Source
MDI
1
Remarks
6 ORed
Table 7-1. MCU Interrupt Sources
ISR Bit
Name & No.
Source(s)
MDI 23 MCU Transmit Interrupt 0, 1
MCU Receive Interrupt 0, 1
MCU General Interrupt 0, 1
Where
Enabled
MCR
Page
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MCU Interrupt Controller
Table 7-1. MCU Interrupt Sources (Continued)
Interrupt
Source
Remarks
ISR Bit
Name & No.
Source(s)
Where
Enabled
Page
Edge I/O port
1,2
8 separate INT7
Ð
INT0
QSPI
12Ð5 INT7ÐINT0 Pin Asserted Ñ
QSPI 4 ORed 24 QSPI HALT Command
QSPI Trigger Collision
QSPI Queue Pointer Wraparound
End of Transfer
SPCR
QSPI Control
RAM
PITCSR PIT
GPT
1 separate
8 ORed
PIT
TPW
16
17
Periodic Interrupt Timer = 0
PWM Count Rollover
GP Timer Count Overflow
PWM Output Compare
Input Capture 1, 2, 4
Output Compare 1, 3
PT Events mcu_int 2, 1, 0
TPWIR
Protocol
Timer
3 separate +
5 ORed
PT2Ð
PT0
PTM
28Ð2
6
25
PTIER
PT Error
PT HALT Command
PT Reference Slot Counter = 0
PT Channel Frame Counter = 0
PT Channel Time Interval Counter =
0
UART Receiver Ready UCR1 UART 2 separate +
2 ORed
URX
UTX
31
29 UART Transmitter Ready
UART Transmitter Empty
RTS Pin State Change
SmartCard 1 separate +
4 ORed
URT
S
SMP
C
SCP
13
30 SIM Sense Change SCPIER
22 SCP Transmit Complete
SCP Receive FIFO Not Empty
SCP Receive FIFO Full
SCP Receive Error
KPD Key Closure Keypad
Interface
Software
1 separate KPD 14 KPCR
3 separate S2ÐS
0
2Ð0 Software Interrupts 2, 1, 0 Ñ
1.
The MDI and Edge I/Ointerrupts are asynchronous. All other interrupts are synchronous.
2.
The Edge I/O interrupts can be edge- or level-sensitive. All other interrupts are level-sensitive only.
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7.1.5 MCU Interrupt Registers
Note: All Interrupt Controller registers require full 32-bit accesses.
ISR
RESET
1
BIT 31 30 29 28
Interrupt Source Register
27 26 25 24 23 22
URX SMPC UTX PT2 PT1 PT0 PTM QSPI MDI SCP
0 0 0 0 0 0 0 0 0 0
21
0
20
0
19
0
$0020_0000
18 17 BIT 16
TPW PIT
0 0 0
Name
TPW
PIT
KPD
URTS
INT7Ð0
S2Ð0
URX
SMPC
UTX
PT2Ð0
PTM
QSPI
MDI
SCP
RESET
1
BIT 15 14 13 12 11 10 9 8 7 6 5
KPD URTS INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
0 0 0 0 0 0 0 0 0 0 0
4
0
3
0
2 1 BIT 0
S2 S1 S0
1 1 1
1.
The state of each defined bit out of reset is determined by the interrupt request input of the associated peripheral; normally, the request is inactive.
The ISR is a read-only that reflects the status of all interrupt request inputs to the interrupt controller. The requests are synchronized so that reading the ISR always returns a stable value. All unused bits always read as 0, except for S[2:0], which always read as 1. Writes to this register have no effect.
Bit(s)
Table 7-2. ISR Description
Interrupt Source Setting
0 = No interrupt request.
1 = Interrupt request pending.
17
16
14
13
12Ð5
2Ð0
25
24
23
22
31
30
UART Receiver Ready
SIM Position Change
29 UART Transmitter (2 ORed)
28Ð26 Protocol Timer 2Ð0
Protocol Timer (5 ORed)
QSPI (4 ORed)
MDI (6 ORed)
SCP (3 ORed)
Timer/PWM (8 ORed)
PIT
Keypad Interface
UART RTS
External Interrupt 7Ð0
Software Interrupt 2Ð0
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MCU Interrupt Controller
NIER
BIT 31 30 29 28
Normal Interrupt Enable Register
27 26 25 24 23 22
EURX ESMPC EUTX EPT2 EPT1 EPT0 EPTM EQSPI EMDI ESCP
21
RESET 0 0 0 0 0 0 0 0 0 0 0
20
0
19
0
$0020_0004
18 17 BIT 16
0
ETPW EPIT
0 0
BIT 15 14 13 12 11 10 9 8 7 6 5
EKPD EURTS EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0
RESET 0 0 0 0 0 0 0 0 0 0 0
4
0
3
0
2 1 BIT 0
ES2 ES1 ES0
0 0 0
FIER
BIT 31 30 29 28
Fast Interrupt Enable Register
27 26 25 24 23 22
EFURXEFSMPC EFUTX EFPT2 EFPT1 EFPT0 EFPTM EFQSPI EFMDI EFSCP
$0020_0008
21 20 19 18 17 BIT 16
EFTPW EFPIT
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT 15 14 13 12 11 10 9 8 7 6 5
EFKPD EFURTS EFINT7 EFINT6 EFINT5 EFINT4 EFINT3 EFINT2 EFINT1 EFINT0
RESET 0 0 0 0 0 0 0 0 0 0 0
4
0
3
0
2 1 BIT 0
NES2NES1 NES0
0 0 0
The NIER is used to enable pending interrupt requests to the core. Each defined bit in this register corresponds to an MCU interrupt source. If an interrupt is asserted and the corresponding NIER bit is set, the interrupt controller asserts a normal interrupt request to the core. If the corresponding NIER bit is cleared (i.e., if the interrupt is masked), the interrupt is not passed to the core and does not affect the high priority interrupt circuit. All interrupts are masked out of reset.
Register bits corresponding to unused interrupts may be read and written but have no affect on interrupt controller operation. Only word writes will update the NIER. Byte or half-word writes will terminate normally, but will not update the register.
The FIER works identically to the NIER, except that a fast interrupt is generated for a given request rather than a normal interrupt. Care should be taken to avoid setting the same bit position in both registers or both a normal and fast interrupt will be generated.
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s Table 7-3. NIER/FIER Description
Bit(s) Interrupt Name Setting
NIER
EURX
ESMPC
EUTX
EPT2Ð0
EPTM
EQSPI
EMDI
ESCP
ETPW
EPIT
EKPD
EURTS
EINT7Ð0
ES2Ð0
1
FIER
EFURX
EFSMPC
EFUTX
EFPT2Ð0
EFPTM
EFQSPI
EFMDI
EFSCP
EFTPW
EFPIT
EFKPD
EFURTS
EFINT7Ð0
EFS2Ð0
1
31
30
29
28Ð26 Protocol Timer 2Ð0
25
24
23
22
17
16
14
UART Receiver Ready
SCP Position Change
UART Transmitter
Protocol Timer Interrupts
QSPI
MDI
SCP RxD, TxD, or Error
Timer/PWM
PIT
Keypad Interface
13 UART RTS
12Ð5 External Interrupt 7Ð0
2Ð0 Software Interrupts
0 = Interrupt source masked.
1 = Interrupt source enabled.
1.
Setting any of the software interrupt enable bits (ES2Ð0, NES2Ð0) immediately generates an interrupt to the MCU.
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NIPR
BIT 31 30 29
Normal Interrupt Pending Register
28 27 26 25 24 23 22
NURX NSMPC NUTX NPT2 NPT1 NPT0 NPTM NQSPI NMDI NSCP
21
RESET 0 0 0 0 0 0 0 0 0 0 0
20
0
19
0
$0020_000C
18 17 BIT 16
0
NTPW NPIT
0 0
BIT 15 14 13 12 11 10 9 8 7 6 5
NKPD NURTS NINT7 NINT6 NINT5 NINT4 NINT3 NINT2 NINT1 NINT0
RESET 0 0 0 0 0 0 0 0 0 0 0
4 3 2 1 BIT 0
NS2 NS1 NS0
0 0 0 0 0
The NIPR is used to monitor impending normal interrupts. Writes to this register are ignored. All unused bits always read as 0, except for bits 2Ð0, which always read as 1.
FIPR
BIT 31 30 29 28
Fast Interrupt Pending Register
27 26 25 24 23 22
FURX FSMPC FUTX FPT2 FPT1 FPT0 FPTM FQSPI FMDI FSCP
21
RESET 0 0 0 0 0 0 0 0 0 0 0
20
0
19
0
$0020_0010
18 17 BIT 16
0
FTPW FPIT
0 0
BIT 15 14 13 12 11 10 9 8 7 6 5
FKPD FURTS FINT7 FINT6 FINT5 FINT4 FINT3 FINT2 FINT1 FINT0
RESET 0 0 0 0 0 0 0 0 0 0 0
4 3
0 0
The FIPR works in the same fashion as the NIPR to monitor fast interrupts.
2 1 BIT 0
FS2 FS1 FS0
0 0 0
NIPR
NURX
NSMPC
NUTX
NPT2Ð0
NPTM
NQSPI
NMDI
NSCP
NTPW
NPIT
NKPD
NURTS
NINT7Ð0
NS2Ð0
Name
FIPR
FURX
FSMPC
FUTX
FPT2Ð0
FPTM
FQSPI
FMDI
FSCP
FTPW
FPIT
FKPD
FURTS
FINT7Ð0
FS2Ð0
Table 7-4. NIPR and FIPR Description
Bit(s) Interrupt
31
30
UART Receiver Ready
SIM Position Change
29 UART Transmitter
28Ð26 Protocol Timer 2Ð0
25
24
23
22
Protocol Timer Interrupts
QSPI
MDI
SCP RxD, TxD, or Error
17
16
14
13
Timer/PWM
PIT
Keypad Interface
UART RTS
12Ð5 External Interrupt 7Ð0
2Ð0 Software Interrupt 2Ð0
Setting
0 = No interrupt request.
1 = Interrupt request pending.
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ICR
BIT 31 30 29 28 27
Interrupt Control Register
26 25 24 23 22 21 20 19
$0020_0014
18 17 BIT 16
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT 15 14
EN
RESET 0 0
13 12 11 10 9
Source Number
8
0 0 0
7 6 5 4 3
Vector Number
2
0 0 0
1 BIT 0
0 0 0 0 0 0 0 0
The ICR selects a fast interrupt source to elevate to the highest priority, and specifies the vector to be used to service the interrupt. Only word writes will update the ICR. Byte or half-word writes will terminate normally, but will not update the register.
Name
EN
Bit 15
Bits 11Ð7
Bits 6Ð0
Table 7-5. ICR Description
Description Settings
Enable Highest Priority Interrupt Hardware 0 = Priority hardware disabled (default).
1 = Priority hardware enabled.
Source NumberÑ Bit position of source to raise to the highest priority.
Vector NumberÑ Vector number to supply when highest priority interrupt is pending. Refer to the
M¥CORE Reference Manual for the appropriate vector number.
7.2 DSP Interrupt Controller
The interrupt controller on the DSP side of the DSP56652 is based on the 56600 core. Its operation is described in Section 7.3 of the DSP56600 Family Manual .
7.2.1 DSP Interrupt Sources
Table 7-6 on page 7-11 lists all of the DSP interrupt sources according to their interrupt
vectors. The vectors are offsets from the program address written to the Vector Base
Address (VBA) register in the program control unit.
If more than one interrupt request is pending when an instruction is executed, the interrupt source with the highest priority level is serviced first. When multiple interrupt requests having the same IPL are pending, a second fixed-priority structure within that IPL
determines which interrupt source is serviced. Table 7-7 shows the relative priority order
of the DSP interrupts. Priority level 3 is the highest, and 0 the lowest. Level 3 vectors cannot change their priority level, but all other vectors can be assigned a level of 0, 1, or 2.
The table lists these vectors in their relative priority if they are assigned the same priority level.
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IRQAÐD are wired internally as shown in Figure 7-3. IRQA is the DSP wake from stop
interrupt, and is wire-ORed to the other three interrupts because they are all intended to wake the DSP as well. IRQA should be disabled by clearing IPRC bits 10Ð9.
DSP_IRQ Pin
MDI Wake From STOP
Protocol Timer
Synchronization Logic
IRQA IRQB IRQC IRQD
DSP Core
Figure 7-3. Internal IRQAÐD Connection
VBA
Offset
IPL
Table 7-6. DSP Interrupt Sources
Interrupt Source
$00
$02
$04
$06
$08
3
3
3
3
3
Reserved
Stack Error
Illegal Instruction
Debug Request Interrupt
Trap
$0AÐ$0E 3
$10
$12
Reserved
0 -
IRQA
1
0 - IRQB (DSP_IRQ)
$14
$16
0 -
0 -
IRQC (MDI)
IRQD (Protocol Timer)
$18
$1A
$1C
$1E
$20
$22
0 -
0 -
0 -
0 -
0 -
0 -
Reserved
Reserved
Reserved
Reserved
Protocol Timer CVR0
Protocol Timer CVR1
VBA
Offset
IPL
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
$52
$54
$56
$58
$4A
$4C
$4E
$50
$40
$42
$44
$46
$48
$5A
$5C
$5E
Interrupt Source
SAP Receive Data
SAP Receive Data With Overrun Error
SAP Receive Last Slot
SAP Transmit Data
SAP Transmit Data with Underrun Error
SAP Transmit Last Slot
SAP Timer Counter Rollover
Reserved
BBP Receive Data
BBP Receive Data With Overrun Error
BBP Receive Last Slot
BBP Receive Frame Counter
BBP Transmit Data
BBP Transmit Data with Underrun Error
BBP Transmit Last Slot
BBP Transmit Frame Counter
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Table 7-6. DSP Interrupt Sources (Continued)
VBA
Offset
IPL Interrupt Source
VBA
Offset
IPL Interrupt Source
$2C
$2E
$30
$32
$24
$26
$28
$2A
0 - Protocol Timer CVR2
0 - Protocol Timer CVR3
0 - Protocol Timer CVR4
0 - Protocol Timer CVR5
0 - Protocol Timer CVR6
0 - Protocol Timer CVR7
0 - Protocol Timer CVR8
0 - Protocol Timer CVR9
$60
$62
$64
$66
$68
$6A...$F
0 - 2 / 3
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
MDI MCU default command / MCU NMI
MDI Receive 0
MDI Receive 1
MDI Transmit 0
MDI Transmit 1
Reserved
2
$34
$36
$38
$3A
0 - Protocol Timer CVR10
0 - Protocol Timer CVR11
0 - Protocol Timer CVR12
0 - Protocol Timer CVR13
$3C
$3E
0 -
0 -
Protocol Timer CVR14
Protocol Timer CVR15
1.
IRQA should be disabled.
2.
Any Interrupt starting address (including a reserved address) can be used for MCU NMI (IPL = 3) or the MCU command interrupt (IPL = 0-2). These interrupts are issued by setting the appropriate bits in MCVR. See
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Highest
Lowest
Highest
Table 7-7. Interrupt Source Priorities within an IPL
Level 3 (Non-maskable)
Hardware RESET
Stack Error
Illegal Instruction
Debug Request Interrupt
Trap
MDI MCU NMI
Levels 0, 1, 2 (Maskable)
IRQA
IRQB - from DSP_IRQ pin
IRQC - from MDI
IRQD - from Protocol Timer
MDI MCU command
BBP Receive Data with Overrun Error
BBP Receive Data
BBP Receive Last Slot
BBP Receive Frame Counter
BBP Transmit Data with Underrun Error
BBP Transmit Last Slot
BBP Transmit Data
BBP Transmit Frame Counter
SAP Receive Data with Overrun Error
SAP Receive Data
SAP Receive Last Slot
SAP Transmit Data with Underrun Error
SAP Transmit Last Slot
SAP Transmit Data
SAP Timer Counter Rollover Lowest
Protocol Timer CVR0
Protocol Timer CVR1
Protocol Timer CVR2
Protocol Timer CVR3
Protocol Timer CVR4
Protocol Timer CVR5
Protocol Timer CVR6
Protocol Timer CVR7
Protocol Timer CVR8
Protocol Timer CVR9
Protocol Timer CVR10
Protocol Timer CVR11
Protocol Timer CVR12
Protocol Timer CVR13
Protocol Timer CVR14
Protocol Timer CVR15
MDI Receive 0
MDI Receive 1
MDI Transmit 0
MDI Transmit 1
7.2.2 Enabling DSP Interrupt Sources
Two steps are required to enable DSP interrupt sources:
1. Assign the desired priority level to each peripheral and write to the Peripheral
Interrupt Priority Register (IPRP).
Each of the four peripherals that can interrupt the DSP (MDI, PT, SAP, and BBP) as well as the MDI Command interrupt can be assigned a priority level from 0 (lowest) to 2
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(highest). This assignment is done by writing to the IPRP. The choice of priority level for each peripheral depends on several factors driven by the end application, including:
¥ Rate of service requests
¥ Latency requirements
¥ Access to the alternate register bank
¥ Length of service routine
¥ Total number of interrupt sources in the system
This step is normally done once during system initialization.
2. Program the appropriate peripheral registers to generate the desired interrupt requests.
7.2.3 DSP Interrupt Control Registers
IPRP
BIT 15 14
RESET 0 0
13
0
Interrupt Priority Register, Peripherals
12 11 10 9 8
MDIPL[1:0]
7 6
PTPL[1:0]
5 4 3 2
X:$FFFE
1 BIT 0
SAPPL[1:0] BBPPL[1:0] MDCPL[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
Table 7-8. IPRP Description
Name Description
MDIPL[1:0]
Bits 9Ð8
PTPL[1:0]
Bits 7Ð6
SAPPL[1:0]
Bits 5Ð4
BBPPL[1:0]
Bits 3Ð2
MDCPL[1:0]
Bits 1Ð0
MDI Interrupt Priority Level
Protocol Timer Interrupt Priority Level
SAP Interrupt Priority Level
BBP Interrupt Priority Level
MDI Command Priority Level
Setting
00 = Disabled (default).
01 = Priority level 0.
10 = Priority level 1.
11 = Priority level 2.
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Edge Port
IPRC
BIT 15 14
RESET 0
Name
IDTM
Bit 11
ICTM
Bit 8
IBTM
Bit 5
IATM
Bit 2
IDPL[1:0]
Bits 10Ð9
ICPL[1:0]
Bits 7Ð6
IDPL[1:0]
Bits 4Ð3
IAPL[1:0]
Bits 1Ð0
0
13
0
12
0
Interrupt Priority Register, Core
11
IDTM
10 9 8
IDPL[1:0] ICTM
7 6 5 4 3
ICPL[1:0] IBTM IBPL[1:0]
0 0 0 0 0 0 0 0 0
Table 7-9. IPRC Description
Description
Interrupt D Trigger ModeÑ Should remain level-sensitive.
Interrupt C Trigger ModeÑ Should remain level-sensitive.
Interrupt B Trigger ModeÑ Should remain level-sensitive.
I nterrupt A Trigger Mode
2
0
X:$FFFF
Interrupt D Priority LevelÑ This interrupt should be enabled before the DSP enters STOP mode.
Interrupt C Priority LevelÑ This interrupt should be enabled before the DSP enters STOP mode.
Interrupt B Priority LevelÑ This interrupt is generated by the
DSP_IRQ pin. It should be activated using a software protocol between the DSP and the external source, signaling the external device when to deassert the interrupt.
Interrupt A Priority LevelÑ This interrupt should remain disabled.
00 = Disabled (default).
01 = Priority level 0.
10 = Priority level 1.
11 = Priority level 2.
1
IATM IAPL[1:0]
0
Setting
0 = Level-sensitive (default).
1 = Edge sensitive.
BIT 0
0
7.3 Edge Port
The Edge Port (EP) consists of eight GPIO pins, INT7Ð0, each of which can generate an interrupt if the associated bit in the NIER or FIER is set. This port is controlled by four configuration registers:
¥ EPPAR Ñ The EP Pin Assignment Register configures the trigger mechanism for each pin: level-sensitive or rising and/or falling edge triggered.
¥ EPFR Ñ The EP Flag Register contains bits that are set when the associated Edge
I/O inputs are triggered.
¥ EPDDR Ñ The EP Data Direction Register configures each pin as either an input or output.
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Edge Port
¥ EPDR Ñ The EP Data Register serves as a GPIO buffer. A write to this register determines the data driven on output pins; data received on input pins can be read from this register.
A diagram of an Edge I/O pin is shown in Figure 7-4.
EPPARn
EPPAR 2n+1
EPPAR 2n
EPPAR 2n+1
Falling Edge
Detect
EPPAR 2n
Rising Edge
Detect
EPFRn
To Interrupt
Controller
EPDRn
EPDDRn
Figure 7-4. Edge I/O Pin
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Edge Port
EPPAR
BIT 15 14
RESET 0
EPPA7
0
Name
EPPA7Ð0
13
EPPA6
12
Edge Port Pin Assignment Register
11 10 9 8 7 6 5
EPPA5 EPPA4 EPPA3 EPPA2
4
0 0 0 0 0 0 0 0 0 0
Table 7-10. EPPAR Description
3
EPPA1
0
$0020_9000
2 1 BIT 0
0 0
EPPA0
0
Description Settings
Edge Port Pin Assignment 7Ð0Ñ Each pair of bits determines the trigger mechanism for an Edge I/O input. Interrupt requests are always generated from this block, but may be masked within the
MCU interrupt controller. The functionality of this register is independent of the programmed pin direction.
00 = Level-sensitive
(default).
01 = Rising edge-sensitive.
10 = Falling edge-sensitive.
11 = Both rising and falling edge-sensitive.
Pins configured as level-sensitive are inverted so that a logic low on the external pin represents a valid interrupt request. Level-sensitive interrupt inputs are not latched. The interrupt source must assert the signal until it is acknowledged by software to guarantee that a level-sensitive interrupt request is acknowledged. Pins configured as edge-sensitive interrupts are latched and need not remain asserted. Pins programmed as edge-detecting are monitored regardless of the configuration as input or output.
EPDDR
BIT 15 14
RESET 0
Name
EPDD[7:0]
Bits 7Ð0
0
13
0
12
0
Edge Port Data Direction Register
11 10 9 8 7 6 5 4 3 2
$0020_9002
1 BIT 0
EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDD0
0 0 0 0 0 0 0 0 0 0 0 0
Table 7-11. EPDDR Description
Description
Each of these bits controls the data direction of the corresponding Edge I/O pin. Pin direction is independent of its programmed level/edge mode.
0 = Input (default)
1 = Output
Settings
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Edge Port
EPDR
BIT 15 14
RESET 0
Name
EPD[7:0]
Bits 7Ð0
0
13
0
12
0
11
0
Edge Port Data Register
10 9 8 7 6 5 4 3 2
$0020_9004
1 BIT 0
EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 EPD0
0 0 0 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 7-12. EPDR Description
Description
Each of these bits contains data for the corresponding Edge I/O pin. Writes to EPDR are stored in an internal latch and driven on any port pin configured as an output. Reads of this register return the value sensed on input pins and the latched data driven on outputs.
EPFR
BIT 15 14
RESET 0
Name
EPF7Ð0
Bits 7Ð0
0
13
0
12
0
11
Edge Port Flag Register
10 9 8 7 6 5 4 3
$0020_9006
2 1 BIT 0
EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPF0
0 0 0 0 0 0 0 0 0 0 0 0
Table 7-13. EPFR Description
Description
Edge Port Flag 7Ð0Ñ Each bit in this register is set when the associated pin detects the edge input programmed in the corresponding EPPA bit. The bit remains set until it is cleared by writing a Ò1Ó to it. A pin configured as level-sensitive does not affect this register. A write to EPDR that triggers a pinÕs level or edge will set the corresponding EPF bit. The outputs of this register drive the corresponding input of the interrupt controller for those bits configured as edge detecting.
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Chapter 8
Queued Serial Peripheral Interface
The Queued Serial Peripheral Interface (QSPI) is a full-duplex synchronous serial interface providing SPI-compatible data transfer between the DSP56652 and up to five peripherals. Four prioritized data queues (Queue3ÐQueue0; Queue3 is highest priority) can be triggered by the protocol timer and the MCU. Each queue can contain several sub-queues, and each sub-queue can be transferred to any of the five peripherals. The queues can be variable sizes of 8- or 16-bit multiples.
Note: A queue is defined as a series of data that is transferred sequentially. Data can be 8 or 16 bits, and each data entry occupies a 16-bit location in QSPI Data
RAM. Each datum in an 8-bit data queue occupies the lower byte of its RAM location; the upper byte is zero-filled.
A sub-queue is a sequence of data within a queue that is transmitted without interruption.
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Features
8.1 Features
The primary QSPI features include the following:
¥ Full-duplex, three wire synchronous transfers
¥ Half-duplex, two wire synchronous transfers
¥ End-of-transfer interrupt flag
¥ Programmable serial clock polarity and serial clock phase
¥ Programmable delay between chip-select and serial clock
¥ Programmable baud rates
¥ Programmable queue lengths and continuous transfer mode
¥ Programmable peripheral chip-selects
¥ Programmable queue pointers
¥ Four transfer activation triggers
¥ Programmable delay after transfer
¥ Automatic loading of programmable address at end of queue
¥ Pause enable at queue entry boundaries
Several of these features are not found on standard SPIs and are further described below.
8.1.1 Programmable Baud Rates
Each of the peripheral chip-select lines in the QSPI has its own programmable baud rate.
The frequency of the internally-generated serial clock can range from MCU_CLK to
(MCU_CLK
¸
504).
8.1.2 Programmable Queue Lengths and Continuous Transfers
The number of entries in a queue is programmable, allowing the QSPI to transfer up to 63 halfwords or bytes without MCU intervention. Continuous transfers of information to several peripherals can be activated with a single trigger, resulting in greatly reduced
MCU/QSPI interaction.
8.1.3 Programmable Peripheral Chip-Selects
Five chip-select pins are provided for connection to up to five SPI peripherals. Software can activate any one pin at a given time, and each pin can be programmed to be active high or active low. The active chip-select signal can be changed at any time, including during a queue transfer.
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QSPI Architecture
8.1.4 Programmable Queue Pointers
Each of the four queues has a programmable queue pointer that contains the RAM address for the next data to be transmitted or received. The MCU can configure the QSPI to switch from one task to another by writing the address of the next task to the queue pointer during queue setup.
8.1.5 Four Transfer Activation Triggers
QSPI transfers are activated by any of four transfer triggers from the protocol timer or the
MCU. Each timer or MCU transfer trigger initiates a transfer of successive data from
RAM, starting at the address pointed to by the queue pointer for that trigger.
8.1.6 Programmable Delay after Transfer
Some serial peripherals require additional chip-select hold time after a transfer is completed. To simplify the interface to these devices, a delay of 1 to 128 serial clock cycles between queues can be programmed at the completion of a queue transfer.
8.1.7 Loading a Programmable Address at the End of Queue
A queue can be configured so that its last data entry is written to its queue pointer, thus programming the start address for the next queue trigger from the queue itself. This enables wrapping to the beginning of the queue or branching from one sequence to another when a new transfer trigger activates the queue.
8.1.8 Pause Enable at Queue Entry Boundaries
A queue transfer can be programmed to terminate at queue entry boundaries by inserting a
PAUSE command in the control halfword of the queue entry at that boundary. This feature enables each of the four transfer triggers to provide programmable multiple-task support and considerably reduces MCU intervention.
8.2 QSPI Architecture
This section describes the QSPI pins, control registers, functional modules, and special-purpose RAM. Most of these components are shown in the QSPI flow diagram in
The QSPI port can also function as GPIO, which is governed by three control registers that are also described.
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QSPI Architecture
8.2.1 QSPI Pins
The QSPI pin description in Section 8.2 is repeated in Table 8-1 for convenience. All pins
are GPIO when not programmed otherwise, and default as general-purpose inputs after reset.
Note: The DSP56652 QSPI always functions as SPI master.
Table 8-1. Serial Control Port Signals
Signal Name
SPICS0Ð
SPICS4
Type Reset State
Output GPI
SCK
MISO
MOSI
Output
Input
Output
GPI
GPI
GPI
Signal Description
Serial peripheral interface chip select 0Ð4Ñ These output signals provide chip select signals for the Queued Serial Peripheral Interface
(QSPI). The signals are programmable as active high or active low.
SPICS0Ð3 have internal pull-up resistors, and SPICS4 has an internal pull-down resistor.
Serial clockÑ This output signal provides the serial clock from the QSPI for the accessed peripherals. The delay (number of clock cycles) between the assertion of the chip select signals and the first transmission of the serial clock is programmable. The polarity and phase of SCK are also programmable.
Synchronous master in slave outÑ This input signal provides serial data input to the QSPI. Input data can be sampled on the rising or falling edge of SCK and received in QSPI RAM most significant bit or least significant bit first.
Synchronous master out slave inÑ This output signal provides serial data output from the QSPI. Output data can be sampled on the rising or falling edge of SCK and transmitted most significant bit or least significant bit first.
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QSPI Architecture
Protocol Timer
Triggers
Clock Signals
Address Bus
Control Signals
Data Bus
16
4
12
Address
Control RAM
64x7
Status Register
SPSR
Data
Queue Pointers
QP 0Ð3
Queue Control
Registers
QCR 0Ð3
SPI Control
Register
SPCR
Receive
Buffer
Shift-In
Register
Control Logic
Transmit
Buffer
Shift-Out
Register
Figure 8-1. QSPI Signal Flow
Address
Data RAM
64x16
Data
Chip Selects
Serial Channel
Control Registers
SCCR 0Ð4
Serial Clock
Generator
5
SPICS0Ð4
SCK
MISO
MOSI
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QSPI Architecture
8.2.2 Control Registers
A brief summary of the control registers for QSPI and GPIO operation is given below.
More detailed descriptions can be found in Section 8.4 on page 8-12.
The QSPI uses the following control registers:
¥ SPSR Ñ The Serial Peripheral Status Register indicates which of the four queues is active, executing or has ended a transfer with an interrupt. It also contains flags for a HALT request acknowledge, trigger collision, or queue pointer wraparound.
¥ SPCR Ñ The Serial Peripheral Control Register enables QSPI operation, enables the four queues, sets the polarity of the five chip selects, enables trigger accumulation (queue 1 only), initiates a QSPI HALT, selects QSPI behavior in
DOZE mode, and enables interrupts for HALT acknowledge, trigger collision and queue wraparound.
¥ QCR3Ð0 Ñ Each of Queue Control Registers 3Ð0 contains the queue pointer for its associated queue, enables use of the last data entry in the queue as the start address of the next queue, and determines if the queue responds to a HALT at the next sub-queue boundary or queue command. QCR1 also contains a counter for a trigger accumulator.
¥ SCCR4Ð0 Ñ Each of Serial Channel Control Registers 4Ð0 controls the serial clock frequency, phase, and polarity for its associated channel, the delay between chip-select assertion and the serial clock activation, the delay between chip-select deassertion and the start of the next transfer, and the order of data transmission
(least significant bit first or last).
These registers determine the GPIO functions of the QSPI pins:
¥ QPCR Ñ The QSPI Port Configuration Register configures each of the eight pins as either QSPI or GPIO.
¥ QDDR Ñ The QSPI Data Direction Register determines if each pin that is configured as GPIO is an input or an output.
¥ QPDR Ñ The QSPI Port Data Register contains the data that is latched on each GPI pin and written to each GPO pin.
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QSPI Architecture
8.2.3 Functional Modules
The QSPI functional modules include the following:
¥ The chip select module uses data from a queueÕs control RAM entry to select the appropriate SPICS pin and Serial Channel Control Register (SCCR) for the serial transfer of the queue entry.
¥ The serial clock generator derives the serial clock SCK from the system clock based on information in the active SCCR.
¥ The shift-in register uses SCK to shift in received data bits at the MISO pin and assembles the bits into a received data halfword or byte. When the last bit is received the data is immediately latched in the receive buffer so that the shift in register can receive the next data with no delay.
¥ If receive is enabled, the receive buffer latches each received byte or halfword from the shift in register and writes it to the QSPI Data RAM at the address contained in the queue pointer in the queueÕs QCR.
¥ The shift-out register uses SCK to shift out transmitted data bits at the MOSI pin.
It loads the next data from the transmit buffer to be transferred immediately after the last bit of the current datum is sent, enabling smooth transmission with no delay.
¥ The transmit buffer holds the next byte or halfword to be transmitted. While the current datum is being transmitted, the QSPI loads the next datum to the transmit buffer from Data RAM. The address of the next datum is contained in the queue pointer in the queueÕs QCR.
8.2.4 RAM
There are two byte-addressable QSPI RAM segments:
¥ The Data RAM is a 64
´
16 bit block that stores transmitted and received QSPI data. The MCU writes data to be transmitted in the Data RAM. If receive is enabled, the QSPI writes received data from the receive buffer to the Data RAM, overwriting the transmitted data. The MCU can then read the received data from
RAM.
¥ The Control RAM is a 64
´
16 bit block that contains a control halfword for each datum in the Data RAM. The control information includes chip select or QSPI command (end of queue, end of transmission, or no activity), data width of a queue entry (8 or 16 bits), receive enable, and pause at end of a sub-queue.
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QSPI Operation
Each datum and corresponding control halfword constitute a queue entry. The MCU initializes the Data RAM and the Control RAM by loading them with transmission data and queue transfer control information.
8.3 QSPI Operation
The QSPI operates in master mode and is always in control of the SPI bus. Data is transferred as either least or most significant bit first, depending on the LSBF n bit in
SCCR n . A transfer can be either 8 or 16 bits, depending on the value of the BYTE bit for the queue entry. When the BYTE bit is set, the least significant byte of the Data RAM entry is transferred, and if receiving is enabled, the least significant byte of the data halfword is valid while the most significant byte is filled with 0s.
The QSPI has priority in using its internal bus. If an MCU access occurs while the QSPI is using the bus, the MCU waits for one cycle.
8.3.1 Initialization
The following steps are required to begin QSPI operation:
1. Write the QPCR to configure unused pins for GPIO and the rest for QSPI.
2. Write the SPCR to adjust Chip Select pin polarities and enable queues and interrupts.
3. Write the QCRs to initialize the queue pointers and determine behavior when executing queues are preempted.
4. Write the SCCR registers to adjust the baud rate, phase, polarity, and delays for the
SCK for each CS pin, as well as the order bits are sent.
5. Write the Data RAM with information to be transmitted for each queue.
6. Write the Control RAM with control information for each queue, including c. Data width (8 or 16 bits) d. Enable data reception if applicable e. Chip select or queue termination
7. Enable the QSPI by setting the QSPE bit in the SPCR.
At this point, the QSPI awaits a queue trigger to initiate a transfer.
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QSPI Operation
8.3.2 Queue Transfer Cycle
A QSPI transfer is initiated by a transfer trigger. There are eight possible sources of transfer triggers, four from the MCU and four from the Protocol Timer. An MCU trigger is activated by writing to one of the four trigger addresses at $0020_5FF8Ð$0020_5FFE.
The content of the write is ignored; the write itself is the trigger.
In normal operation, the following sequence occurs:
1. The MCU or Protocol Timer issues a transfer trigger.
2. The targeted queue becomes active . The QSPI asserts QA n in the SPSR. (The
MCU has previously enabled operation for this queue by setting its enable bit QE n in the SPCR.)
3. If no higher priority queue is transferring data, the targeted queue begins executing .
The QSPI asserts QX n in the SPSR.
4. The QSPI uses the queue pointer QP n in QCR n to determine the offset of the queueÕs entry in RAM.
5. The QSPI reads the datum and command halfword of the queue entry from RAM, and writes the datum to the transmit buffer.
6. The datum is latched into the shift-out register
7. The QSPI selects the peripheral chip-select line from the PCS field in the control halfword and asserts it.
8. The shift-out register uses SCK to shift its contents out to the peripheral through the MOSI pin.
9. Received datum is also clocked in to the shift-in register if the RE bit in the queue entryÕs control halfword is set.
10. As transfer begins, QP n is incremented, the next datum and control halfword are read from RAM, and the datum is latched in the transmit out buffer.
11. All 8 or 16 bits in the queue entry are transmitted. When the last bit is transferred, the next datum in the transmit buffer is immediately latched into the shift-out register and received datum, if any, is immediately latched to the receive buffer so that there is no delay between transfers.
Steps 7Ð11 repeat until the cycle is ended or broken by a QSPI command, a higher priority
QSPI trigger, or a power-down mode.
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QSPI Operation
8.3.3 Ending a Transfer Cycle
A transfer cycle ends when all data in the queue has been transferred. This condition is indicated in the last control halfword by either setting the PAUSE bit or programming the
PCS field with NOP or EOQ (refer to the Control RAM description on page 8-22).
8.3.3.1 PAUSE
At the completion of transfer of each queue entry, the QSPI checks whether the PAUSE bit is set in the control halfword for that entry. If so, the QSPI assumes it has reached the end of the programmed queue and clears the QA n and the QX n flags. If EOTIE is detected in the PCS field of the control halfword for that queue entry, the QSPI sets the EOT n flag in the SPSR and generates an interrupt to the MCU. If the PAUSE bit is cleared, the QSPI continues the transfer process.
8.3.3.2 NOP and EOQ
Each time the QSPI loads a queue entry from RAM (step 5 or 10 in the transfer cycle on
page 8-9) it checks for EOQ (end of queue) or NOP (no operation) in the PCS field. If the
QSPI detects one of these codes, it assumes it will reach the end of the programmed queue after it completes the transfer of the current datum and clears the QA n and QX n flags. If
EOTIE is detected for the present queue entry, the QSPI asserts the EOT n flag and generates an interrupt to the MCU.
The EOQ command can also be used to program the next entry point for the queue without
MCU intervention. If LE n in QCR n is set when a cycle terminates with EOQ, the QSPI writes the 6 least significant bits of the queue entryÕs datum into the QP n field of QCR n .
8.3.4 Breaking a Transfer Cycle
Normally, once a queue is started, transfer continues until an end of queue is indicated.
When the queue completes its transfer, the next active queue with the highest priority begins execution. However, a queue can be interrupted at a sub-queue boundary to enable a higher priority queue to execute rather than waiting for the current queue to finish. If a higher priority queue is triggered while a lower priority queue is executing and the HMD bit of the lower priority queueÕs QCR is cleared, the QSPI suspends the execution of the lower priority queue at the next sub-queue boundary and starts executing the higher priority queue. The QA bit of the suspended queue remains set, and the QSPI resumes execution of the lower priority queue after it has completed the execution of the higher priority queue.
A sub-queue boundary is a queue entry whose control halfword contains a cleared CONT bit and/or a PCS field that activates a different SPICS line than the currently active one.
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QSPI Operation
Setting the CONT bit keeps the current chip select line active. Clearing the CONT bit deasserts the current chip-select line and stops the current transfer. If the CONT bit is set and the chip selection in the next queue entry is different than that of the present one, the chip select line remains active between queue entry transfers and is deactivated two
MCU_CLK cycles before the new chip select line for the next queue entry is activated.
If both the CONT bit and the PAUSE bit in the queue entry's control halfword are set, or if
EOQ is detected in the next control halfword, the chip select line also continues to be activated after the sub-queue/queue transfer has been completed.
8.3.5 Halting the QSPI
When the MCU wants to Òsoft disableÓ the QSPI at a queue boundary, it asserts the HALT bit in SPCR. If the QSPI is in the process of transferring a queue, it suspends the transfer at the next sub-queue or queue boundary, depending on the queueÕs HMD bit. It then asserts the HALTA bit in the SPSR and QSPI operation stops. If the HLTIE bit in the
SPCR is set, asserting HALTA generates an interrupt to the MCU. The QSPI state machines and the QSPI registers are not reset during the HALT process, and the QSPI resumes operation where it left off when the MCU deasserts HALTA. During the HALT mode, the QSPI continues to accept new transfer triggers from the protocol timer and
MCU, and the MCU can access any of the QSPI registers and RAM addresses.
The MCU can immediately disable the QSPI by clearing the QSPE bit in the SPCR. All
QSPI state machines and the SPSR are reset. Data in an ongoing transfer can be lost, and the external SPI device can be disrupted.
8.3.6 Error Interrupts
If a queue pointer contains $3F when the next control halfword is fetched and the QP is not loaded from the data halfword, it wraps around to $00 and the QPWF flag in the SPSR is set. If the WIE bit in the SPCR is set, an interrupt is generated to the MCU.
If a trigger for a queue occurs while the queue is active the TRC flag in the SPSR is set. If the TRCIE bit in the SPCR is set, an interrupt is generated to the MCU.
8.3.7 Low Power Modes
If the QSPI detects a DOZE signal and the DOZE bit in the SPCR is set, the QSPI halts its operation as if the HALT bit had been set. When the MCU exits DOZE mode, it must clear the HALTA bit to resume QSPI operation.
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When the QSPI detects a STOP signal, it halts immediately by shutting off its clocks. The status of the QSPI is left unchanged, but any ongoing transfer is lost and the peripheral can be disrupted.
8.4 QSPI Registers and Memory
This section describes the QSPI control registers, data and control RAM, and GPIO
registers. These areas are summarized in Table 8-2.
Table 8-2. QSPI Register/Memory Summary
Address
1
CONT. RAM
$000 - $07F
$080 - $3FF
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
BYTE RE PAUSE CONT PCS / EOTIE / NOP /
EOQ
DATA RAM
$400 - $47F
$480 - $EFF
QPCR
$F00
QDDR
$F02
QPDR
$F04
SPCR
$F06
MOST SIGNIFICANT BYTE
Reserved
LEAST SIGNIFICANT BYTE
PC7
(SCK)
PD7
(SCK)
PC6
(MOSI)
PD6
(MOSI)
PC5
(MISO)
PD5
(MISO)
PC4
(CS4)
PD4
(CS4)
D7
(SCK)
D6
(MOSI)
D5
(MISO)
D4
(CS4)
CSPOL4 CSPOL3 CSPOL2 CSPOL1 CSPOL0 QE3 QE2 QE1 QE0 HLTIE TRCIE WIE
PC3
(CS3)
PD3
(CS3)
D3
(CS3)
PC2
(CS2)
PD2
(CS2)
D2
(CS2)
PC1
(CS1)
PD1
(CS1)
D1
(CS1)
PC0
(CS0)
PD0
(CS0)
D0
(CS0)
HALT DOZE QSPE
LE0 HMD0 QP0 QCR0
$F08
QCR1
$F0A
QCR2
$F0C
QCR3
$F0E
LE1
LE2
LE3
HMD1
HMD2
HMD3
TRCNT1 QP1
QP2
QP3
QX0 QA3 QA2 QA1 QA0 HALTA TRC QPWF EOT3 EOT2 EOT1 EOT0 SPSR
$F10
SCCR0
$F12
SCCR1
$F14
SCCR2
$F16
QX3 QX2 QX1
CPHA0 CKPOL0 LSBF0
CPHA1 CKPOL1 LSBF1
CPHA2 CKPOL2 LSBF2
SCCR3
$F18
SCCR4
$F1A
$F1C - $FF7
$FF8
$FFA
$FFC
$FFE
CPHA3 CKPOL3 LSBF3
CPHA4 CKPOL4 LSBF4
DATR0
DATR1
DATR2
DATR3
DATR4
CSCKD0
CSCKD1
CSCKD2
CSCKD3
CSCKD4
Reserved
MCU Trigger for Queue 0
MCU Trigger for Queue 1
MCU Trigger for Queue 2
MCU Trigger for Queue 3
SCKDF0
SCKDF1
SCKDF2
SCKDF3
SCKDF4
1.
All addresses are offsets from $0020_5000.
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QSPI Registers and Memory
8.4.1 QSPI Control Registers
The following registers govern QSPI operation:
¥ SPCRÑSerial Port Control Register
¥ QCR0Ð3 Ñ QSPI Control Registers
¥ SPSR Ñ Serial Port Status Register
¥ SCCR0Ð4 Ñ Serial Channel Control Registers
SPCR
BIT 15 14 13 12
Serial Port Control Register
11 10 9 8 7 6 5 4 3
$0020_5F06
2 1 BIT 0
CSPOL4CSPOL3CSPOL2CSPOL1CSPOL0 QE3 QE2 QE1 QE0 HLTIE TRCIE WIE TACE HALT DOZE QSPE
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: Either the EQSPI bit in the NIER or the EFQSPI bit in the FIER must be set in
order to generate any of the interrupts enabled in the SPCR (see page 7-7).
Name
CSPOL[4:0]
Bits 15Ð11
QE[3:0]
Bits 10Ð7
HLTIE
Bit 6
TRCIE
Bit 5
WIE
Bit 4
TACE
Bit 3
Table 8-3. SPCR Description
Description Settings
Chip Select Polarity[4:0]Ñ These bits determine the active logic level of the QSPI chip select outputs.
0 = SPICS n is active low (default).
1 = SPICS n is active high.
Queue Enable[3:0]Ñ Each of these bits enables its respective queue to be triggered. If QE n is cleared, a trigger to this queue is ignored. If QE n is set, a trigger for
Queue n makes Queue n active, and the QA n bit in the
SPSR is asserted. Queue n executes when it is the highest priority active queue.
0 = Queue n is disabled (default).
1 = Queue n is enabled.
Each of these bits can be set or cleared independently of the others.
HALTA Interrupt EnableÑ Enables an interrupt when the HALTA status flag in the SPSR asserted.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
Trigger Collision Interrupt EnableÑ Enables an interrupt when the TRC status flag in the SPSR is asserted.
Wraparound Interrupt EnableÑ Enables an interrupt when the QPWF status flag in the SPSR is asserted.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
Trigger Accumulation EnableÑ Enables trigger accumulation for Queue 1. The trigger count is contained in the TRCNT1 field in QCR1. When TACE is set, a trigger to Queue 1 increments TRCNT1, and completion of a Queue 1 transfer decrements TRCNT1.
Note: This function and the TRCNT1 field in QCR1 are available only for Queue 1. Setting or clearing the TACE bit has no effect on Queues 3, 2, or 0.
0 = Trigger accumulation is disabled and the TRCNT1 field is cleared
(default).
1 = Trigger accumulation enabled.
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Name
HALT
Bit 2
DOZE
Bit 1
QSPE
Bit 0
Table 8-3. SPCR Description (Continued)
Description Settings
Halt RequestÑ When the MCU sets the HALT bit, the
QSPI finishes any ongoing serial transfer, asserts
HALTA, and halts. If a queue is executing when HALT is asserted, the QSPI checks the value of the HMD bit in its
QCR. If HMD is clear, the QSPI halts only at the next
PAUSE, NOP or EOQ commands. If HMD is set, the
QSPI halts at the next sub-queue boundary.
During Halt mode the QSPI continues to accept new transfer triggers from the protocol timer and MCU, and the MCU can access any of the QSPI registers and RAM addresses.
The HALT bit is cleared when HALTA is deasserted, so that only one MCU access is required to exit the Halt state. The QSPI state machines and the SPCR are not reset during the Halt process, so the QSPI resumes operation where it left off.
NOTE: The HALT bit is checked only at sub-queue or queue boundaries. If the HALT bit is asserted and then deasserted before a sub-queue transfer has completed, the QSPI does not recognize a Halt request.
0 = Normal operation.
1 = Halt request.
DOZE EnableÑ Determines the QSPI response to Doze mode. If the DOZE bit is set when DOZE mode is identified, the QSPI finishes any ongoing serial transfer and halts as if the HALT bit were set. When the DOZE mode is exited, the MCU must clear HALTA for the QSPI to resume operation. If the DOZE bit is cleared, DOZE mode is ignored.
0 = QSPI ignores DOZE mode
(default).
1 = QSPI halts in DOZE mode.
QSPI EnableÑ Setting QSPE enables QSPI operation.
The QSPI begins monitoring transfer triggers from the
Protocol Timer and the MCU. Both the QSPI and the
MCU have access to the QSPI RAM.
Clearing QSPE disables the QSPI. All QSPI state machines and the status bits in the SPSR are reset; other registers are not affected. The MCU can use the
QSPI RAM and access its registers, and all the QSPI pins revert to GPIO configuration, regardless of the value of the QPCR bits.
To avoid losing an ongoing data transfer and disrupting an external device, issue a HALT request and wait for
HALTA before clearing QSPE. Pending transfer triggers will still be lost.
0 = QSPI disabled; QSPI pins are
GPIO (default).
1 = QSPI enabled.
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QSPI Registers and Memory
ÿ
QCR0
BIT 15 14
LE0 HMD0
RESET 0 0
QCR1
BIT 15 14
LE1 HMD1
RESET 0 0
13
0
13
0
QCR2
BIT 15 14
LE2 HMD2
RESET 0 0
13
0
12
0
12
0
12
11
0
Queue Control Register 0
10
0
10
9
0
9
8
0
8
7
0
7
6
0
11
Queue Control Register 1
10 9 8 7 6
0
11
0 0
TRCNT1
0 0 0
Queue Control Register 2
6
5
0
5
0
5
4
0
4
0
4
3
QP0
$0020_5F08
2 1 BIT 0
0 0 0 0
3
QP1
$0020_5F0A
2 1 BIT 0
0 0 0 0
3
QP2
$0020_5F0C
2 1 BIT 0
0 0 0 0 0 0 0 0 0 0 0 0 0
QCR3
BIT 15 14
LE3 HMD3
RESET 0 0
13 12 11
Queue Control Register 3
10 9 8 7 6 5 4 3
QP3
$0020_5F0E
2 1 BIT 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
The MCU can read and write QCR0Ð3. The QSPI can read these registers but can only write to the queue pointer fields, QP[5:0]. Writing to an active QCR is prohibited while it is executing a transfer. It is highly recommended that writing to the QCRs be done only when the QSPI is disabled or in HALT state.
Table 8-4. QCR Description
LEn
Bit 15
Name
HMDn
Bit 14
Description Settings
Load Enable for Queue nÑ Enables loading a new value to the queue pointer (QP n ) of
Queue n. If LE n is set when the QSPI reaches an End Of Queue (EOQ) command
(PCS = 111 in the Queue n control halfword) the value of the least significant byte of the data halfword of that queue entry is loaded into QP n . This allows the next triggering of queue n to resume transfer at the address loaded from the data halfword.
0 = QP loading disabled (default).
1 = QP loading enabled.
Halt Mode for Queue nÑ Defines the point at which the execution of queue n is halted when the MCU sets the HALT bit in the SPCR or when a higher priority transfer trigger is activated.
0 = Halts at any sub-queue boundary.
1 = Halts only at PAUSE, NOP, or EOQ.
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Name
TRCNT1
Bits 9-6
QPn
Bits 5Ð0
Table 8-4. QCR Description (Continued)
Description Settings
Trigger Count for Queue 1Ñ When the TACE bit in the SPCR is set, trigger accumulation is enabled, and the TRCNT1 field can take values other than 0. If Queue 1 receives a transfer trigger while it is active (i.e., the QA1 bit in the SPSR is set), the TRCNT1 field is incremented. The TRCNT1 field is decremented when a Queue 1 transfer completes. As many as 16 triggers can be accumulated and subsequently processed. The TRCNT1 field cannot be incremented beyond the value of 1111 or decremented below 0. If a trigger for
Queue 1 arrives when the TACE bit and all the bits of TRCNT field are set, the TRC flag in the SPSR is asserted to signify a trigger collision. If transfer of Queue 1 is completed when all the bits in TRCNT field are cleared, QA1 is deasserted.
This field can only be read by the MCU; writes to this field are ignored.
There is no TRCNT field in QCR0, QCR2, or QCR3. Bits 9Ð6 of these registers are reserved.
Queue Pointer for Queue nÑ This field contains the address of the next queue entry for the associated queue. The MCU initializes the QP to point to the first address in a queue. As queue n executes, the QP n is incremented each time a queue entry is fetched from RAM.
If an EOQ command is identified in the queue entryÕs control halfword, and the LE n bit is asserted, the six least significant bits of the data halfword in the queue entry are loaded into
QP n before queue execution is completed. This initializes the queue pointer for the next queue without MCU intervention.
A write to the QP field while its queue is executing is disregarded.
NOTE: The QP range is $00Ð$3F for 64 queue entries. Because the queue entries themselves are 16-bit halfwords that are byte-addressable, the actual offset that QP points to is two times the number contained in QP.
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QSPI Registers and Memory
ÿ
SPSR
BIT 15 14 13 12 11
Serial Port Status Register
10 9 8
QX3 QX2 QX1 QX0 QA3 QA2 QA1 QA0
7 6 5 4 3
$0020_5F10
2 1 BIT 0
HALTA TRC QPWF EOT3 EOT2 EOT1 EOT0
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The MCU can read the SPSR to obtain status information, and can write to it in order to clear the HALTA, TRC, QPWF, and EOT[3:0] status flags. Only the QSPI can assert bits in this register.
Table 8-5. SPSR Description
Name
Type
1
Description Settings
QX[3:0]
Bits 15Ð12
QA[3:0]
Bits 11Ð8
HALTA
Bit 6
R
R
Queue ExecutingÑ The QSPI sets a queueÕs
QX bit when the queue begins execution, and clears the bit when queue execution stops.
Queue execution begins when a queue is active and no higher priority (higher-numbered) queue is executing. Execution stops under any of the following circumstances:
¥ The queue transfer is completed and the queue becomes inactive
¥ A higher priority queue is asserted
¥ The MCU issues a HALT command.
0 = Queue not executing (default).
1 = Queue executing.
Queue ActiveÑ The QSPI sets a queueÕs QA bit when it receives a transfer trigger for that queue, and clears the bit upon completion of the queue transfer.
0 = Queue not active (default).
1 = Queue active.
R/1C Halt Acknowledge FlagÑ The QSPI asserts this bit when it has come to an orderly halt at the request of the MCU via an assertion of the
HALT bit. If the HALT bit is asserted while the
QSPI is transferring a queue, the QSPI continues the transfer until it either reaches the first sub-queue boundary, or until it reaches a
PAUSE, NOP, or EOQ command, depending on the value of the HMD bit for that queue.
Then the QSPI asserts HALTA, clears the QX bit for the executing queue, and halts. If the
HALT bit is asserted while the QSPI is idle,
HALTA is asserted and the QSPI halts immediately. If the HLTIE bit is set in the SPCR, an interrupt is generated to the MCU when
HALTA is asserted.
The MCU clears HALTA by writing it with 1.
0 = No Halt since last acknowledge or current halt has not been acknowledged (default).
1 = Current Halt has been acknowledged.
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Name
TRC
Bit 5
QPWF
Bit 4
Table 8-5. SPSR Description (Continued)
Type
1
Description Settings
R/1C Trigger CollisionÑ Asserted when a transfer trigger for one of the queues occurs while the queue is activated (QA n = 1). Software should allow sufficient time for a queue to finish executing a queue in normal operation before the queue is retriggered. If the TRCIE bit is set in the SPCR, assertion of the TRC bit generates an interrupt to the MCU. This bit can be cleared by the MCU by writing a value of logic 1 into it.
0 = No collision.
1 = A collision has occurred.
For Queue 1, TRC is only asserted when the trigger counter (TRCNT) = 1111b and a new trigger occurs.
The MCU clears TRC by writing it with 1.
R/1C Queue Pointer Wraparound FlagÑ If a queue pointer contains the value $7F and is incremented to read the next word in the queue
(step 10), the QP wraps around to address $00
and QPWF is asserted. If the WIE bit in the
SPCR has been set, an MCU interrupt is generated.
0 = No wraparound.
1 = A wraparound has occurred.
The MCU clears QPWF by writing it with 1.
EOT[3:0]
Bits 3Ð0
Note: QPWF is not asserted when a QP is explicitly written with $00 as a result of an EOQ command from Control RAM.
R/1C End of TransferÑ When the PCS field of a queue entry is EOTIE (PCS = 110), the QSPI asserts the associated EOT bit and generates an interrupt to the MCU. Because the source for this interrupt is the execution of a command in
RAM, it may be difficult in some cases to detect the control halfword that was the source for the interrupt.
0 = No end of transfer.
1 = End of transfer has occurred.
The MCU clears each EOT by writing it with 1.
1.
R = Read only.
R/1C = Read, or write with 1 to clear (write with 0 ingored).
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QSPI Registers and Memory
SCCR0
SCCR1
SCCR2
SCCR3
SCCR4
BIT 15 14 13
CPHA CKPOL LSBF
RESET 0 0 0
12
Serial Channel Control Register 0
Serial Channel Control Register 1
Serial Channel Control Register 2
Serial Channel Control Register 3
Serial Channel Control Register 4
11 10 9 8 7 6 5
0
DATR[2:0]
0 0 0
CSCKD[2:0]
0 0 0 0
4
0
3
SCKDF[6:0]
$0020_5F12
$0020_5F14
$0020_5F16
$0020_5F18
$0020_5F1A
2 1 BIT 0
0 0 0 0
Each of these registers controls the baud-rate, timing, delays, phase and polarity of the serial clock (SCK) and the bit order for a corresponding chips select line, SPICS0Ð4. The
MCU has full access to these registers, while the QSPI has only read access to them. The
MCU cannot write to the SCCR of an active line, and it is highly recommended that writes to the SCCRs only be done when the QSPI is disabled or in HALT state.
Name
CPHAn
Bit 15
CKPOLn
Bit 14
Table 8-6. SCCR Description
Description Settings
Clock Phase for SPICSnÑ Together with
CKPOL n , this bit determines the relation between SCK and the data stream on MOSI and MISO. When the CPHA n bit is set, data is changed on the first transition of SCK when the SPICS n line is active. When the CPHA n bit is cleared, data is latched on the first transition of SCK when the SPICS n line is active. The timing diagrams for QSPI transfer when CPHA n is 0 and when CPHA n is 1 are
shown in Figure 8-2 on page 8-21.
0 = Data is changed on the first transition of
SCK (default).
1 = Data is latched on the first transition of
SCK.
Clock Polarity for SPICSnÑ Selects the logic level of SCK when the QSPI is not transferring data (the QSPI is inactive). When the CKPOLn bit is set, the inactive state for
SCK is logic 1. When the CKPOLn bit is cleared, the inactive state for SCK is logic 0.
CKPOL is useful when changes in SCK polarity are required while SPICSn is inactive.
The timing diagrams for QSPI transfer when
CKPOLn is 0 and when CKPOLn is 1 are
shown in Figure 8-2 on page 8-21.
0 = Inactive SCK state = logic low (default).
1 = Inactive SCK state = logic high.
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Name
LSBFn
Bit 13
DATRn[2:0]
Bits 12Ð10
CSCKDn[2:0]
Bits 9Ð7
Table 8-6. SCCR Description (Continued)
Description Settings
Transfer Least Significant Bit First for
SPICSnÑ These bits select the order in which data is transferred over the MOSI and
MISO lines when the SPICSn line is activated for the transfer. When the LSBFn is set, data is transferred least significant bit (LSB) first.
When the LSBFn bit is cleared, data is transferred most significant bit (MSB) first.
When the BYTE bit in the control halfword is asserted, only the least significant byte of the data halfword is transferred (the MSB is then bit 7), so the data must be right-aligned.
0 = MSB transferred first (default).
1 = LSB transferred first.
Delay After Transfer for SPICSnÑ These bits controls the delay time between deassertion of the associated SPICS line
(when queue or sub-queue transfer is completed), and the time a new queue transfer can begin. Delay after transfer can be used to meet the deselect time requirement for certain peripherals.
CS Assertion to SCK Activation DelayÑ
These bits control the delay time between the assertion of the associated chip-select pin and the activation of the serial clock. This enables the QSPI port to accommodate peripherals that require some activation time.
DATR[2:0]
CSCKD[2:0]
000
001
010
011
100
101
110
111
Delay (SCK Cycles)
1 (default)
2
4
8
16
32
64
128
SCKDFn[6:0]
Bits 6Ð0
SCK Division FactorÑ These bits determine the baud rate for the associated peripheral.
The SCKDF field includes two division factors. The MSB (SCKDF6) is a prescaler bit that divides MCU_CLK by a factor of 4 if set or by 1 if cleared, while SCKDF[5:0] divide
MCU_CLK by a factor of 1 to 63 ($00Ð$3E).
There is an additional division by 2. The effective SCK baud rate is
(SCKDF[5:0] + 1) á (3 á SCKDF[6] + 1) á 2
The lone exception is SCKDF[6:0] = $7F, in which case SCK = MCU_CLK.
SCKDF Examples
SCKDF[6:0]
000_0000
000_0001
000_0111
100_0000
100_1011
111_1110
111_1111
Division Factor
16
8
2
4
96
504
1
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CPHA=0
SCK
CKPOL=0
SCK
CKPOL=1
CS
CSPOL=1
MOSI
MISO
LSB
LSB
Bit-1
Bit-1
MSB
MSB
CSCKD
1 Serial
Cycle
CPHA=1
SCK
CKPOL=0
SCK
CKPOL=1
CS
CSPOL=1
MOSI
MISO
LSB Bit-1 MSB
X
CSCKD
LSB Bit-1 MSB
Figure 8-2. QSPI Serial Transfer Timing
1 Serial
Cycle
DATR
DATR
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8.4.2 MCU Transfer Triggers
The last four 16-bit addresses in the utilized memory area, $0020_5FF8 to $$0020_5FFE, are used for MCU triggers to Queue0ÐQueue3, respectively. When the MCU writes to one of these addresses, the QSPI generates a trigger for the appropriate queue in the same fashion as a protocol timer trigger. The content of the write is irrelevant.
8.4.3 Control And Data RAM
Data to be transferred reside in Data RAM, and each 16-bit data halfword has a corresponding 16-bit control halfword in Control RAM with the same address offset. Each data halfword / control halfword pair constitutes a queue entry. There are a total of 64 queue entries. The values in RAM are undefined at Reset and should be explicitly programmed.
8.4.3.1 Control RAM
Only the 7 LSBs (bits 6Ð0) of each 16-bit queue control halfword are used; the 9 MSBs
(bits 15Ð7) of each control halfword always read 0. The MCU can read and write to control RAM, while the QSPI has read only access.
Name
BYTE
Bit 6
RE
Bit 5
BIT 15 14 13 12 11
RESET 0
10
Control RAM
9 8 7
0 0 0 0
6
$0020_5000 to $0020_507F
5 4 3
BYTE RE PAUSE CONT
2 1
PCS[2:0]
BIT 0
0 0 0 0 0 0 0 0 0 0 0
Table 8-7. QSPI Control RAM Description
Description Settings
BYTE EnableÑ This bit controls the width of transferred data halfwords. When BYTE is set, the QSPI transfers only the 8 least significant bits of the corresponding 16-bit queue entry in
Data RAM. If receiving is enabled, a received halfword is also
8 bits. The received byte is written to the least significant 8 bits of the data halfword, and the most significant byte of the data halfword is filled with 0s. When BYTE is cleared, the QSPI transfers the full 16 bits of the queue entryÕs data halfword.
0 = 16-bit data transferred.
1 = 8-bit data transferred.
Receive EnableÑ This bit enables or disables data reception by the QSPI. The QSPI enables reception of data from the
MISO pin for each queue entry in which the RE bit is set, and writes the received halfword into the data halfword of that queue entry. The received halfword will overwrite the transmitted data that was previously stored in that RAM address.
0 = Receive disabled.
1 = Receive enabled.
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Name
PAUSE
Bit 4
CONT
Bit 3
PCS[2:0]
Bits 2Ð0
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Table 8-7. QSPI Control RAM Description (Continued)
Description Settings
PAUSEÑ This bit specifies whether the QSPI pauses after the transfer of a queue entry. When the QSPI identifies an asserted PAUSE bit in a queue entryÕs control halfword, the
QSPI recognizes that it has reached the end of a queue. After transfer of that queue entry, the QSPI terminates execution of the queue by clearing the associate QX and QA bits in SPSR.
It then processes the next activated queue with the highest priority. When the QSPI identifies a cleared PAUSE bit, it proceeds to transfer the next entry in that queue.
0 = Not a queue boundary.
1 = Queue boundary.
0 = Deactivate chip select.
1 = Keep chip select active.
Continuous Chip-SelectÑ Specifies if the chip-select line is activated or deactivated between transfers. When the CONT bit is set, the chip-select line continues to be activated between the transfer of the present queue entry and the next one. When the CONT bit is cleared, the chip-select line is deactivated after the transfer of the present queue entry.
Peripheral Chip Select FieldÑ Determines the action to be taken at the end of the current queue entry transfer:
SPIC n
NOPÑ
Activated ÑThe specified chip select line is asserted.
transfer the QSPI deasserts the SPICS lines and waits for a new transfer trigger to resume operation. The queue pointer is set to point to the next queue entry.
EOTIEÑ
PCS field from the previous queue entry determines the
SPICS line asserted for this transfer. At the end of the current transfer the QSPI asserts the associated EOT flag in the
SPSR and generates an interrupt to the MCU.
EOQÑ
No SPICS line activated. At the end of the current
End of Transfer interrupt enabled. The value of the
End of Queue. The QSPI completes the transfer of the current queue entry, clears the QA and QX bits of the current queue, and processes the next active queue with the highest priority. If the LE bit in the QCR of the current queue is asserted, the value in the least significant byte of the data halfword in that queue entry is written into the queueÕs QP.
PCS[2:0] QSPI Action
000
001
010
011
100
101
110
111
SPIC0 Activated
SPIC1 Activated
SPIC2 Activated
SPIC3 Activated
SPIC4 Activated
NOP
1
EOTIE
EOQ
1
1.
All other bits in the control halfword are disregarded.
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8.4.3.2 Data RAM
Data halfwords can contain transmission data stored in RAM by the MCU or data received by the QSPI from external peripherals. The MCU can read the received data halfwords from RAM. Data is transmitted and received by the QSPI as either least or most significant bit first, depending on the LSBF bit in SCCR for the associated channel.
Access to the RAM is arbitrated between the QSPI and the MCU. Because of this arbitration, wait states can be inserted into MCU access times when the QSPI is in operation.
Received data is written to the same address at which the transmitted data is stored and overwrites it, so care must be taken to ensure that no data is lost when receiving is enabled.
8.4.4 GPIO Registers
Any of the eight QSPI pins can function as GPIO. The registers governing GPIO functions are described below.
QPCR QSPI Port Configuration Register
15 14 13 12 11 10 9 8 7 6 5 4
RESET 0 0 0 0 0 0 0 0
QPC7
(SCK)
0
QPC6
(MOSI)
0
$0020_5F00
1 BIT 0 3 2
QPC5
(MISO)
QPC4 QPC3 QPC2 QPC1 QPC0
(SPICS4) (SPICS3) (SPICS2) (SPICS1) (SPICS0)
0 0 0 0 0 0
Table 8-8. QPCR Description
Name
QPC[7:0]
Bits 7Ð0
Description
QSPI Pin ConfigurationÑ Each bit determines whether its associated pin functions as QSPI or
GPIO.
0 = GPIO (default).
1 = QSPI.
Settings
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QDDR QSPI Data Direction Register
15 14 13 12 11 10 9 8 7 6 5 4
RESET 0 0 0 0 0 0 0 0
QDD7
(SCK)
0
$0020_5F02
1 BIT 0 3 2
QDD6
(MOSI)
QDD5
(MISO)
QDD4 QDD3 QDD2 QDD1 QDD0
(SPICS4) (SPICS3) (SPICS2) (SPICS1) (SPICS0)
0 0 0 0 0 0 0
Table 8-9. QDDR Description
Name Description Settings
QDD[7:0]
Bits 7Ð0
QSPI Data Direction[7:0]Ñ Determines whether each pin that is configured as GPIO functions as an input or an output, whether or not the QSPI is enabled.
0 = Input (default).
1 = Output.
.
QPDR QSPI Port Data Register
15 14 13 12 11 10 9 8 7 6 5
RESET 0 0 0 0 0 0 0 0
QPD7
(SCK)
Ñ
$0020_5F04
1 BIT 0 4 3 2
QPD6
(MOSI)
QPD5
(MISO)
QPD4 QPD3 QPD2 QPD1 QPD0
(SPICS4) (SPICS3) (SPICS2) (SPICS1) (SPICS0)
Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 8-10. QPDR Description
Name
QPD[7:0]
Bits 7Ð0
Description
QSPI Port GPIO Data [7:0]Ñ Each of these bits contains data for the corresponding QSPI pin if it is configured as GPIO. Writes to QPDR are stored in an internal latch, and driven on any port pin that is configured as an output. Reads of this register return the value sensed on input pins and the latched data driven on outputs.
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Chapter 9
Timers
This section describes three of the four DSP56652 timer modules controlled by the MCU:
¥ The periodic interval timer (PIT) creates a periodic signal that is used to generate a regularly timed interrupt. It operates in all low power modes.
¥ The watchdog timer protects against system failures by resetting the DSP56652 if it is not serviced periodically. The watchdog can operate in both WAIT and DOZE low power modes. Its time-out intervals are programmable from 0.5 to 32 seconds
(for a 32 kHz input clock).
¥ The pulse width modulator (PWM) and general purpose (GP) timers run on independent clocks derived from a common MCU_CLK prescaler. The PWM can be used to synthesize waveforms. The GP timers can measure the interval between external events or generate timed signals to trigger external events.
The protocol timer is described in Chapter 10.
9.1 Periodic Interrupt Timer
The PIT is a 16-bit Òset-and-forgetÓ timer that provides precise interrupts at regular intervals with minimal processor intervention. The timer can count down either from the maximum value ($FFFF) or the value written in a modulus latch.
9.1.1 PIT Operation
Figure 9-1 shows a block diagram of the PIT.
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MCU Peripheral Bus
OSC
OSC/4
PITCNT
PITMR
ITIF
PITMR
Load Counter
CKIL Ö4 PITCNT
Count=0
Figure 9-1. PIT Block Diagram
Interrupt
The PIT uses the following registers:
¥ PITCSR Ñ The Periodic Interrupt Timer Control and Status Register determines whether the counter is loaded with $FFFF or the value in the Module Latch, controls operation in Debug mode, and contains the interrupt enable and flag bits.
¥ PITMR Ñ The Periodic Interrupt Timer Module Latch contains the rollover value loaded into the counter.
¥ PITCNT Ñ The Periodic Interrupt Timer Counter reflects the current timer count.
Each cycle of the PIT clock decrements the counter, PITCNT. When PITCNT reaches zero, the ITIF flag in the PITCSR is set. An interrupt is also generated if the ITIE bit in the
PITCSR has been set by software. The next tick of the PIT clock loads either $FFFF or the value in the PITMR, depending on the state of the RLD bit in the PITCSR.
The PIT clock is a fixed rate of CKIL/4. Internal clock synchronization logic enables the
MCU to read the counter value accurately. This logic requires that the frequency of
MCU_CLK, which drives the MCU peripherals, be greater than or equal to CKIL.
Therefore, when CKIL drives the MCU clock the division factor should be 1 (i.e.,
MCS[2:0] in the CKCTL register are clearedÑsee page 4-5).
Figure 9-2 is a timing diagram of PIT operation using the PITMR to reload the counter.
$0002 $0001 $0000 $0005
$0005
$0004 $0003
Figure 9-2. PIT Timing Using the PITMR
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Periodic Interrupt Timer
Setting the OVW bit in the ITCSR enables the counter to be updated at any time. A write to the PITMR register simultaneously writes the same value to PITCNT if OVW is set.
The PIT is not affected by the low power modes. It continues to operate in STOP, DOZE and WAIT modes.
PIT operation can be frozen when the MCU enters Debug mode if the DBG bit in the
PITCSR is set. When Debug mode is exited, the timer resumes operation from its state prior to entering Debug mode. If the DBG bit is cleared, the PIT continues to run in Debug mode.
Note: The PIT has no enable control bit. It is always running except in debug mode.
9.1.2 PIT Registers
The following is a bit description of the three PIT registers.
PITCSR
Bit 15 14
RESET 0 0
13
0
12
0
PIT Control/Status Register
11 10 9 8 7 6 5 4 3
$0020_7000
2 1
DBG OVW ITIE ITIF RLD
Bit 0
0 0 0 0 0 0 0 0 0 0 0 0
Table 9-1. ITCSR Description
Name
Type
1
Description Settings
DBG
Bit 5
OVW
Bit 4
ITIE
Bit 3
ITIF
Bit 2
RLD
Bit 1
R/W DebugÑ Controls PIT function in Debug mode.
0 = PIT runs normally (default).
1 = PIT is frozen.
R/W Counter Overwrite EnableÑ Determines if a write to PITMR is simultaneously passed through to PITCNT.
0 = PITMR write does not affect
PITCNT (default).
1 = PITMR write immediately overwrites
PITCNT.
R/W PIT Interrupt EnableÑ Enables an interrupt when ITIF is set.
Note: Either the EPIT bit in the NIER or the
EFPIT bit in the FIER must also be set in order to generate this interrupt (see
0 = Interrupt disabled (default).
1 = Interrupt enabled.
R/1C PIT Interrupt FlagÑ Set when the counter value reaches zero; cleared by writing it with 1 or writing to the PITMR.
0 = Counter has not reached zero
(default).
1 = Counter has reached zero.
R/W Counter ReloadÑ Determines the value loaded into the counter when it rolls over.
1.
R/W = Read/write.
R/1C = Read, or write with 1 to clear (write with 0 ingored).
0 = $FFFF (default)
1 = Value in PITMR
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PITMR
Bit 15 14 13 12 11
1
PIT Modulus Register
10 9 8 7 6
1 1
PIT Modulus Value
1 1 1
5 4 3
$0020_7002
2 1 Bit 0
RESET 1 1 1 1 1 1 1 1 1
This register contains the value that is loaded into the PITCNT when it rolls over if the
RLD bit in the PITCSR is set. The default value is $FFFF.
1
PITCNT
Bit 15 14 13 12 11 10
PIT Counter
9 8 7 6 5 4 3
$0020_7004
2 1 Bit 0
RESET -
This read-only register provides access to the PIT counter value. The reset value is indeterminate.
-
9.2 Watchdog Timer
The watchdog timer protects against system failures by providing a means to escape from unexpected events or programming errors. Once the timer is enabled, it must be periodically serviced by software or it will time out and assert the Reset signal.
9.2.1 Watchdog Timer Operation
The watchdog timer uses the following registers:
¥ WCR Ñ The Watchdog Control Register enables the timer, loads the watchdog counter, and controls operation in Debug and DOZE modes.
¥ WSR Ñ The Watchdog Service Register is used to reinitialize the timer periodically to prevent it from timing out.
The watchdog timer is disabled at reset. Once it is enabled by setting the WDE bit in the
WCR, it cannot be disabled again. The timer contains a 6-bit counter that is initialized to the value in the WT field in the WCR. This counter is decremented by each cycle of the watchdog clock, which runs at a fixed rate of CKIL
¸2 14
. Thus, for CKIL=32.768KHz, the watchdog timeout period can range from 0.5 seconds to 32 seconds.
The counter is initialized to the value in the WT field when the watchdog timer is enabled and each time the timer is serviced. The timer must be serviced before the counter rolls over or it will reset the system. The timer can only be serviced by performing the following steps, in sequence:
1. Write $5555 to the WSR.
2. Write $AAAA to the WSR.
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Watchdog Timer
Any number of instructions can occur between these two steps. In fact, it is recommended that the steps be in different code sections and not in the same loop. This prevents the
MCU from servicing the timer when it is erroneously bound in a loop or code section.
The watchdog timer is subject to the same synchronization logic restrictions as the PIT, i.e., MCU_CLK > CKIL.
Figure 9-3 is a block diagram of the Watchdog Timer.
WSR
WCR
DOZE (From MCU)
WDZE
WDE WDBG WDZE
(WT[0Ð5]
WDBG
Debug (From MCU)1
6-Bit Counter
Underflow
WDE (One-Time Write)
CKIL
~2Hz
(for CKIL=32kHz)
Prescaler
Ö214 NOTE:
Debug is an active low signal from the MCU indicating Debug mode.
Figure 9-3. Watchdog Timer Block Diagram
Reset
The timer is unaffected by WAIT mode and halts in STOP mode. It can either halt or continue to run in DOZE mode, depending on the state of the WDZE bit in the WCR.
In Debug mode, the watchdog timer can either halt or continue to run, depending on the state of the WDBG bit in the WCR. If WDBG is set when the MCU enters Debug mode, the timer stops, register read and write accesses function normally, and the WDE bit onetime-write lock is disabled. If the WDE bit is cleared while in Debug mode, it will remain cleared when Debug mode is exited. If the WDE bit is not cleared while in Debug mode, the watchdog count will continue from its value before Debug mode was entered.
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9.2.2 Watchdog Timer Registers
WCR
Name
WT[5:0]
Bits 15Ð10
WDE
Bit 2
WDBG
Bit 1
WDZE
Bit 0
Bit 15 14
RESET 0 0
Watchdog Control Register
11 10 9 8 7 6 5 13 12
WT[5:0]
0 0 0 0 0 0 0 0
Table 9-2. WCR Description
0
Description
4
0
3
0
$0020_8000
2 1 Bit 0
WDE WDBG WDZE
0 0 0
Settings
Watchdog Timer FieldÑ These bits determine the value loaded in the watchdog counter when it is initialized and after the timer is serviced.
Watchdog EnableÑ Setting this bit enables the watchdog timer. It can only be cleared in Debug mode or by Reset.
Watchdog Debug EnableÑ Determines timer operation in Debug mode.
Watchdog Doze EnableÑ Determines timer operation in DOZE mode.
0 = Disabled (default).
1 = Enabled.
0 = Continues to run in Debug mode (default)
1 = Halts in Debug mode.
0 = Continues to run in DOZE mode (default).
1 = Halts in DOZE mode.
WSR
Bit 15 14
RESET 0 0
13
0
12
0
Watchdog Service Register
11 10 9 8 7 6 5
0 0 0
WSR[15:0]
0 0 0 0
4
0
3
0
$0020_8002
2
0
1
0
Bit 0
0
This register services the watchdog timer and prevents it from timing out. To service the timer, perform the following steps:
1. Write $5555 to the WSR.
2. Write $AAAA to the WSR.
9.3 GP Timer and PWM
This section describes the MCU GP timer and pulse width modulator (PWM). Although these are separate functions, they derive their clocks from a common 8-bit MCU_CLK
divider, shown in Figure 9-4. They also share several control registers.
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GP Timer and PWM
TPWCR:PST[0Ð2] MCU_CLK
8-Bit
Divider
/2
/4
/8
/16
/32
/64
/128
/256
1 of 8
Clock for
GP Timer
Counter
(TCNT)
1 of 8
Clock for
PWM
Counter
(PWCNT)
TPWCR:PSPW[0Ð2]
Figure 9-4. GP Timer/PWM Clocks
9.3.1 GP Timer
The GP timer provides two input capture (IC) channels and three output compare (OC) channels. The input capture channels use a 16-bit free-running up counter, TCNT, to record the time of external events indicated by signal transitions on the IC input pins. The output compare channels use the same counter to time the initiation of three different events.
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9.3.1.1 GP Timer Operation
The GP timer uses the following registers:
¥ TPWCR
1
Ñ The Timer Control Register enables the GP timer, selects the TCNT clock frequency, and determines GP timer operation in Debug and DOZE modes.
¥ TPWMR1 Ñ The Timer Mode Register selects the edges that trigger the IC functions, determines the action taken for the OC function, and can force an output compare on any of the OC channels.
¥ TPWSR1 Ñ The Timer Status Register contains flag bits for each IC and OC event and counter rollover.
¥ TPWIR1 Ñ The Timer Interrupt Register enables interrupts for each IC and OC event and counter rollover.
¥ TICR1,2 Ñ The Timer Input Capture Registers latch the TCNT value when the programmed edge occurs on the associated IC input.
¥ TOCR1,3,4 Ñ The Timer Output Compare Registers contain the TCNT values that trigger the programmed OC outputs.
¥ TCNT Ñ The Timer Counter reflects the current TCNT value.
Figure 9-5 is a block diagram of the GP timer.
All GP timer functions are based on a 16-bit free-running counter, TCNT. The PST[2:0] bits in TPWCR select one of eight possible divisions of MCU_CLK as the clock for
TCNT. PST[2:0] can be changed at any time to select a different frequency for the TCNT clock; the change does not take effect until the 8-bit divider rolls over to zero. TCNT begins counting when the TE bit in TPWCR is set. If TE is later cleared, the counter freezes at its current value, and resumes counting from that value when TE is set again.
The MCU can read TCNT at any time to get the current value of TCNT.
TCNT is frozen when the MCU enters STOP mode, DOZE mode (if the TD bit in
TPWCR is set) or Debug mode (if the TDBG bit in TPWCR is set). In each case, TCNT resumes counting from its frozen value when the respective mode is exited. If TD or
TDBG are cleared, entering the associated mode does not affect GP timer operation.
9-8
1.These registers also contain bits used by the pulse width modulator.
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GP Timer and PWM
Timer Prescaler
Clock Input
TCNT
16
TOV TOVIE
Interrupt
OF1IE
Interrupt
FO1
CMP OF1
TOCR1
OF3IE
OM10
FO3
OM11
Interrupt
OC1
CMP OF3
TOCR3
OF4IE
OM30
FO4
OM31
Interrupt
CMP OF4
TOCR4
IF1IE
OM40 OM41
Interrupt
TICR1
LD
IF1
IF2IE
IM10
SYNC
IM11
Interrupt
RxD/IC1
TICR2
LD
IF2
IM21
SYNC
RTS/IC2
IM20
Figure 9-5. GP Timer Block Diagram
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9.3.1.1.1 Input Capture
The inputs to IC1 and IC2 are UART pins RxD and RTS respectively. Each input capture pin has a dedicated 16-bit latch (TICR1,2) and input edge detection/selection logic. Each input capture function can be programmed to trigger on the rising edge, falling edge, or both edges of the associated IC pin through the associated IM[1:0] bits in the TPWMR.
When the programmed edge transition occurs on an input capture pin, the associated TICR captures the content of TCNT and sets an associated flag bit (IF1,2) in the TPWSR. If the associated interrupt enable bit (IFIE1,2) in TPWIR) has been set, an interrupt request is also generated when the transition is detected. Input capture events are asynchronous to the GP timer counter, so they are conditioned by a synchronizer and a digital filter. The events are synchronized with MCU_CLK so that TCNT is latched on the opposite halfcycle of MCU_CLK from TCNT increment. An input transition shorter than one
MCU_CLK period has no effect. A transition longer than two MCU_CLK periods is guaranteed to be captured, with a maximum uncertainty of one MCU_CLK cycle. TICR1 and 2 can be read at any time without affecting their values.
Both input capture registers retain their values during STOP and DOZE modes, and when the GP timer is disabled (TE bit cleared).
9.3.1.1.2 Output Compare
Each output compare channel has an associated compare register (TOCR1,3,4). When
TCNT equals the 16-bit value in a compare register, a status flag (OCF1,3,4) in TPWSR is set. If the associated interrupt enable bit (OCIE1,3,4) in TPWIR has been set, an interrupt is generated. OC1 can also set, clear or toggle the OC1 output pin, depending on the state of OM1[1:0] in the TPWMR. OC3 and OC4 are not pinned out but their flags and interrupt enables can be used to time event generation.
The OC1 pin can be forced to its compare value at any time by setting FO1 in the
TPWMR. The action taken as a result of a forced compare is the same as when an output compare match occurs, except that status flags are not set. OC3 and OC4 also have forcing bits, but they have no effect because the functions are not pinned out.
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9.3.2 Pulse Width Modulator
The pulse width modulator (PWM) uses a 16-bit free-running counter, PWCNT, to generate an output pulse on the PWM pin with a specific period and frequency.
9.3.2.1 PWM Operation
The PWM uses the following registers:
¥ TPWCR
1
Ñ The PWM Control Register enables the PWM, selects the PWCNT clock frequency, and determines PWM operation in Debug and DOZE modes.
¥ TPWMR
1
Ñ The PWM Mode Register connects the PWM function to the PWM output pin and determines the output polarity.
¥ TPWSR
1
Ñ The PWM Status Register contains flag bits indicating pulse assertion
(PWCNT=PWOR) and deassertion (PWCNT rolls over).
¥ TPWIR
1
Ñ The PWM Interrupt Register enables interrupts for each edge of the pulse.
¥ PWOR Ñ The PWM Output Compare Register contains the PWCNT value that initiates the pulse.
¥ PWMR Ñ The PWM Modulus Register contains the value loaded into PWCNT when it rolls over. This value determines the pulse period.
¥ PWCNT Ñ The PWM Counter reflects the current PWCNT value.
Figure 9-6 is a block diagram of the pulse width modulator.
The pulse width modulator is based on a 16-bit free-running down counter, PWCNT. The
PSPW[2:0] bits in TPWCR select one of eight possible divisions of MCU_CLK as the clock for PWCNT. PSPW[2:0] can be changed at any time to select a different frequency for the PWCNT clock; the change does not take effect until the 8-bit divider rolls over to zero. When the PWE bit in TPWCR is set, PWCNT is loaded with the value in PWMR and begins counting down. If PWE is later cleared, the counter freezes at its current value.
If PWE is set again, PWCNT is reloaded with PWMR and begins counting down. The
MCU can read PWCNT at any time to get the current value of PWCNT.
1.These registers also contain bits used by the GP timer.
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GP Timer and PWM
PWM Prescaler
Clock Output
PWO
PWMR
PWCNT
Counter
16 Interrupt
PWOIE
CMP S
R
PWOR
PWF
PWM
Pin
PWP , PWC
Interrupt
PWFIE
Figure 9-6. PWM Block Diagram
PWCNT is frozen when the MCU enters STOP mode, DOZE mode (if the PWD bit in
TPWCR is set) or Debug mode (if the PWDBG bit in TPWCR is set). In each case,
PWCNT resumes counting from its frozen value when the respective mode is exited. If
PWD or PWDBG are cleared, entering the associated mode does not affect PWM operation.
When PWCNT counts down to the value preprogrammed in the PWOR, the pulse is asserted, and following events occur:
1. The PWF bit in TPWSR is set.
2. An interrupt is generated if the PWFIE bit in TPWCR has been set.
3. If the PWC bit in TPWMR is set, the PWM output pin is driven to its active state, which is determined by the PWP bit in TPWMR.
When PWCNT counts down to zero, the pulse is deasserted, generating the following events:
1. The PWO bit in TPWSR is set.
2. An interrupt is generated if the PWOIE bit in TPWCR has been set.
3. If the PWC bit in TPWMR is set, the PWM output pin is driven to its inactive state.
4. The PWMR value is reloaded to PWCNT.
The pulse duty cycle can range from 0 (PWOR=0) to 99.9985%=65535/65536*100
(PWOR=PWMR=$FFFF). The PWM period can vary between a minimum of 2
MCU_CLK cycles and a maximum of 65536*256 MCU_CLK cycles.
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GP Timer and PWM
9.3.3 GP Timer and PWM Registers
TPWCR
Bits 15 14
RESET 0 0
13
0
12
Timer and PWM Control Register
11 10 9 8 7 6 5
PWDBG TDBG PWD PWE TD TE
4
PSPW[2:0]
3
0 0 0 0 0 0 0 0 0 0
Table 9-3. TPWCR Description
Description Settings
$0020_6000
2 1 Bit 0
0
PST[2:0]
0 0
Name
PWDBG
Bit 11
TDBG
Bit 10
PWM DebugÑ Enables PWM operation during
Debug mode.
GP Timer DBGÑ Enables IC and OC operation during Debug mode.
0 = PWM frozen in Debug mode (default).
1 = PWM runs in Debug mode.
0 = GP timer frozen in Debug mode (default).
1 = GP timer runs in Debug mode.
PWD
Bit 9
PWE
Bit 8
TD
Bit 7
TE
Bit 6
PWM DOZEÑ Enables PWM operation during
DOZE mode.
PSPW[2:0]
Bits 5Ð3
PST[2:0]
Bits 2Ð0
Prescaler for PWMÑ These bits select the
MCU_CLK divisor for the clock that drives
PWCNT.
Prescaler for GP TimersÑ These bits select the
MCU_CLK divisor for the clock that drives TCNT.
0 = PWM enabled in DOZE mode (default).
1 = PWM disabled in DOZE mode.
PWM EnableÑ Enables PWM operation. If PWE and TE are both cleared, the prescaler is stopped.
0 = PWM disabled; PWCNT stopped (default).
1 = PWM enabled; PWCNT is running.
GP Timer DOZEÑ Enables IC and OC operation during DOZE mode.
0 = GP timer enabled in DOZE mode (default).
1 = GP timer disabled in DOZE mode.
GP Timer EnableÑ Enables IC and OC operation. If PWE and TE are both cleared, the prescaler is stopped.
0 = IC and OC disabled; TCNT stopped
(default).
1 = IC and OC enabled; TCNT is running.
PSPW[2:0]
PST[2:0]
000
001
010
011
100
101
110
111
PWCNT Prescaler
TCNT Prescaler
2
1
(default)
2
2
2
3
2
4
2
5
2
6
2
7
2
8
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GP Timer and PWM
FO4
Bit 12
FO3
Bit 11
FO1
Bit 10
IM2[1:0]
Bits 9Ð8
IM1[1:0]
Bits 7Ð6
OM1[1:0]
Bits 1Ð0
TPWMR
Bit 15 14 13 12
Timers and PWM Mode Register
11 10 9 8 7 6 5
PWC PWP FO4 FO3 FO1 IM2[1:0] IM1[1:0]
RESET 0 0 0 0 0 0 0 0 0 0 0
Table 9-4. TPWMR Description
Name
PWC
Bit 14
PWP
Bit 13
4
0
3
0
$0020_6002
2
0
1 Bit 0
OM1[1:0]
0 0
Description Settings
PWM ControlÑ Connects the PWM function to the PWM output pin.
PWM Pin PolarityÑ Controls the polarity of the
PWM output during the active time of the pulse, defined as time between output compare and
PWCNT rollover.
0 = Disconnected (default).
1 = Connected.
0 = Active-high polarity (default).
1 = Active-low polarity.
Forced Output CompareÑ Writing 1 to FOC1 immediately forces the OC1 pin to the output compare state programmed in the associated OM1[1:0] bits. The OF1 flag in TPWSR is not affected. Setting FOC3 and FOCC4 have no effect because these functions are not pinned out.
Each FOC bit is self-negating, i.e., always reads 0. Writing 0 to these bits has no effect.
Input Capture Operating ModeÑ Each pair of bits determines the input signal edge that triggers the associated input compare response.
00 = Disabled (default).
01 = Rising edge.
10 = Falling edge.
11 = Both edges.
These bits determine the OC1 output response when the compare 1 function is triggered.
00 = Timer disconnected from pin (default).
01 = Toggle output.
10 = Clear output.
11 = Set output.
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GP Timer and PWM
TPWSR
Bit 15 14 13 12
Timers and PWM Status Register
11 10 9 8 7 6 5 4
PWO TOV PWF IF2
0 0 0 0 0 0 0 0 0
3
$0020_6004
2 1 Bit 0
IF1 OF4 OF3 OF1
0 0 0 0 RESET 0 0 0
Each of the bits in this register is cleared by writing it with 1. Writing zero to a bit has no effect.
Name
PWO
Bit 7
TOV
Bit 6
PWF
Bit 5
IF2
Bit 4
IF1
Bit 3
OF4
Bit 2
OF3
Bit 1
OF1
Bit 0
Table 9-5. TPWSR Description
Description Settings
PWM Count RolloverÑ Indicates if PWCNT has rolled over.
0 = PWCNT has not rolled over (default)
1 = PWCNT has rolled over since PWO was last cleared
Timer Count OverflowÑ Indicates if TCNT has overflowed.
0 = TCNT has not overflowed (default)
1 = TCNT has overflowed since TOV was last cleared
PWM Output Compare FlagÑ Indicates whether the PWM compare occurred.
0 = PWM compare has not occurred (default)
1 = PWM compare has occurred since PWF was last cleared
Input Capture FlagsÑ Each bit indicates that the associated input capture function has occurred
0 = Capture has not occurred (default)
1 = Capture has occurred since IF bit was last cleared
Output Compare FlagsÑ Each bit indicates that the associated output compare function has occurred
0 = Compare has not occurred (default)
1 = Compare has occurred since OF bit was last cleared
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GP Timer and PWM
Name
IF1IE
Bit 3
OF4IE
Bit 2
OF3IE
Bit 1
OF1IE
Bit 0
PWOIE
Bit 7
TOVIE
Bit 6
PWFIE
Bit 5
IF2IE
Bit 4
TPWIR
Bit 15 14 13
0
Timers and PWM Interrupt Enable Register
12 11 10 9 8 7 6 5 4 3
0 0 0 0 0
2
$0020_0006
1 Bit 0
PWOIE TOVIE PWFIE IF2IE IF1IE OF4IE OF3IE OF1IE
0 0 0 0 0 0 0 0 RESET 0 0
Note: Either the ETPW bit in the NIER or the EFTPW bit in the FIER must be set in
order to generate any of the interrupts enabled in the TPWIR (see page 7-7).
Table 9-6. GNRC Description
Description
PWM Count Rollover Interrupt Enable
Settings
0 = Interrupt disabled (default)
1 = Interrupt generated when corresponding
TPWSR flag bit is set
Timer Count Overflow Interrupt Enable
PWM Output Compare Flag Interrupt Enable
Input Capture 2 Interrupt Enable
Input Capture 1 Interrupt Enable
Output Compare 4 Interrupt Enable
Output Compare 3 Interrupt Enable
Output Compare 1 Interrupt Enable
TOCR1
TOCR3
TOCR4
Bit 15 14 13 12
Output Compare 1 Register
Output Compare 3 Register
Output Compare 4 Register
11 10 9 8 7 6 5
0 0 0
TOCRn[15:0]
0 0 0 0
4 3
$0020_6008
$0020_600A
$0020_600C
2 1 Bit 0
RESET 0 0 0 0 0 0 0 0 0
When TCNT equals the value stored in one of these registers, the corresponding output compare function is triggered.
TICR1
TICR2
Bit 15 14
RESET 0 0
13
0
12
0
11
Input Capture 1 Register
Input Capture 2 Register
10 9 8 7 6
0 0 0
TICRn[15:0]
0 0 0
5
0
4
0
3
0
$0020_600E
$0020_6010
2 1 Bit 0
0 0 0
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GP Timer and PWM
When TCNT equals the value stored in one of these registers, the corresponding input compare function is triggered.
PWOR
Bit 15 14 13 12
PWM Output Compare Register
11 10 9 8 7 6 5
0 0 0 0
PWOR[15:0]
0 0 0 0
4 3
RESET 0 0 0 0 0
When PWCNT equals the value written to this register, the pulse is initiated.
0
$0020_6012
2 1 Bit 0
0 0
TCNT
Bit 15 14 13 12 11 10
Timer Counter
9 8 7
0 0
TCNT[15:0]
0 0
6 5 4 3
RESET 0 0 0 0 0 0 0 0 0
This read-only register reflects the value of the GP timer counter, TCNT.
0 0
ZO PWMR
Bit 15 14 13 12 11
PWM Modulus Register
10 9 8 7 6
0 0 0
PWMR[15:0]
0 0 0
5 4 3
$0020_6016
2 1 Bit 0
RESET 0 0 0 0 0 0 0 0 0 0
The value written to this register is loaded into the PWCNT when the PWM is enabled and each time PWCNT rolls over. The PWCNT roll-over period equals the value loaded + 1.
ZO PWCNT
Bit 15 14 13 12 11 10
PWM Counter
9 8 7
0 0
PWCNT[15:0]
0 0
6 5 4 3
RESET 0 0 0 0 0 0 0 0 0
This read-only register reflects the value of the PWM counter, PWCNT.
$0020_6014
2
0
0
1
0
Bit 0
$0020_6018
2 1 Bit 0
0
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Chapter 10
Protocol Timer
The Protocol Timer (PT) serves as the control module for all radio channel timing. It relieves the MCU from the event scheduling associated with radio communication protocol so that software need only reprogram the PT once per frame or less. The events the PT can generate include the following:
¥ QSPI triggers can be used to program external devices that have SPI ports.
¥ External events driven on the PT pins TOUT[7Ð0] can be used to control external devices.
¥ MCU and DSP interrupts can be used in a variety of ways, for example to alert the cores to prepare for a change to a different channel or slot.
¥ Transmit and Receive Macros with programmable delays generate repeating event sequences with a single event call. A transmit and receive macro can run simultaneously.
¥ Control events governing PT operation and synchronization.
Each of these events can be represented by an event code in the protocol timerÕs event table. Each entry that contains an event code is paired with a Time Interval Count ( TIC ) value. The entries are written in order of decreasing TIC value. As the value in a down counter matches each TIC value, an event represented by the corresponding event code is generated. The result is a series of events with specific timing and sequence.
10.1 Protocol Timer Architecture
This section describes the PT functional blocks, including the timing components, event table, and event generation hardware.
A block diagram of the PT is shown in Figure 10-1.
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MCU Peripheral Bus
MCU
Interface
Address[8:1] Data[15:0]
MTPTR[6:0]
Frame Table 0
Event
Table
Frame Table 1
RxPTR[6:0]
FT_EC[6:0]
Rx_EC[6:0]
7
7
Rx Macro Table
TxPTR[6:0]
RDPTR[6:0]
TDPTR[6:0]
Tx Macro Table
Rx Delay Table
Tx Delay Table
RTIC[13:0] (Rx)
Tx_EC[6:0] 7
Event
Control
Unit
8
TOUT7Ð
21
Rx Hit
21
MTCU
RTIC[13:0] (Tx) Tx Hit
4
QSPI
Triggers
MTCU
ATIC[13:0] 14
FT Hit
FTEC
14
CFE
CFC
CFNI
DSP/MCU
Interrupts
7
VAB[7:1]
MCU_CLK
TICG
MCU Accessible
TICK
CTIC
RSPC
(MOD 2400)
RSE
SPBP
RSC
RSNI
Interrupt
Generator
DSPI
4
MCU
Interrupts
Error
Detector
Figure 10-1. Protocol Timer Block Diagram
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Protocol Timer Architecture
10.1.1 Timing Signals and Components
The Time Interval Clock Generator (TICG) generates the primary timing PT reference signal, the Time Interval Clock (TICK). This signal is related to symbol duration, and typically functions as a sub-symbol clock.
TICK drives two timing chains. The primary timing chain generates event timing. It contains a Channel Time Interval Counter (CTIC) which drives a Channel Frame Counter
( CFC ). The primary chain has a programmable modulus. The auxiliary chain, which has a fixed modulus, is used as a time slot reference. This chain contains a Reference Slot
Prescale Counter (RSPC) which drives a Reference Slot Counter (RSC).
10.1.1.1 Time Interval Clock Generator
The TICG is a 9-bit programmable prescaler that divides MCU_CLK to generate the PT reference clock, TICK. The TICK frequency range is MCU_CLK/2 to MCU_CLK/512.
The TICG modulus value is programmed in the Time Interval Modulus Register (TIMR), which is loaded into the TICG when it rolls over. Changing the TICG value Òon the flyÓ is not supported.
10.1.1.2 Channel Time Interval Counter
The CTIC is a programmable read/write, free-running 14-bit modulo down counter decremented by the TICK signal. It is used to trigger frame table events and generate the frame reference signal Channel Frame Expire (CFE ). An event is triggered each time the value in CTIC matches the TIC value pointed to in a Frame Table. CFE is asserted when the CTIC decrements to zero, which can trigger a Channel Frame Interrupt (CFI) to the
MCU if the CFIE bit in the Protocol Timer Interrupt Enable Register (PTIER) is set. CTIC rolls over to a modulo value contained in the Channel Time Interval Modulus Register
(CTIMR), which is usually the number of TICKs in a radio channel frame.
The PT can be synchronized to radio channel timing by reloading CTIC at a specific time.
This can be done either by writing CTIC directly or writing a new value to CTIMR (if needed) and generating a reload_counter event.
10.1.1.3 Channel Frame Counter
The CFC is a programmable read/write, free-running 9-bit modulo down counter decremented by the CFE signal. It is used to count channel frames. If the CFNIE bit in the
PTIER is set, the CFC generates a Channel Frame Number Interrupt (CFNI) when it decrements to zero The CFC rolls over to a modulo value contained in the Channel Frame
Modulus Register (CFMR).
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10.1.1.4 Reference Slot Prescale Counter
The RSPC is 12-bit free running modulo 2400 down counter decremented by TICK. The output of the counter is a slot reference signal, Reference Slot Expire (RSE), which drives the RSC. Systems that do not need this modulo 2400 divider can bypass the RSPC by setting the SPBP bit in the Protocol Timer Control Register (PTCR), so that TICK drives the RSC directly.
10.1.1.5 Reference Slot Counter
The RSC is a programmable 8-bit read/write free-running down counter decremented by
RSE. It can be used, for example, to keep track of slot timing in an adjacent cell. If the
RSNIE bit in the PTIER is set when the RSC decrements to zero, a Reference Slot
Number Interrupt (RSNI) is generated. The RSC rolls over to a modulo value contained in the Reference Slot Modulus Register (RSMR).
10.1.2 Event Table
The event table is an 80-word dual-port RAM starting at the base of the protocol timer peripheral space, $0020_3000. Each entry contains a 14-bit field and a 7-bit field; all fields are halfword-aligned. The event table can be dynamically partitioned into two frame tables, two macro tables and two delay tables by initializing the base address registers
FTBAR, MTBAR, and DTPTR respectively. A frame table, a receive macro, and a
transmit macro can all be active simultaneously. Figure 10-2 shows the structure of the
event table.
Note: The base address and pointer registers contain entry numbers. The actual address in MCU memory is equal to $0020_3000 plus 4 times the entry number.
The MCU can read and write the event table, whether or not the PT is enabled. PT control logic has read-only access to the event table. Arbitration logic ensures that the event table is accessed correctly, adding wait states to MCU cycles when necessary.
10.1.3 Event Generation
The components involved in generating events in the PT include a Frame Table Event
Comparator, two Macro Timing Control Units, an Event Control Unit, and an Interrupt
Generator.
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Protocol Timer Architecture
FTBAR
$0020_3000
(FTBA0[6:0])
(FTBA1[6:0])
ATIC (14 Bits) EC (7 Bits)
Frame Table 0
ATIC (14 Bits) EC (7 Bits)
Frame Table 1
MTBAR
(RxBA[6:0])
(TxBA[6:0])
(RDBA[3:0]) << 3
DTPTR
(TDBA[3:0]) << 3
RTIC (14 Bits)
RTIC (14 Bits)
TID (14 Bits)
TID (14 Bits)
EC (7 Bits)
Rx Macro Table
EC (7 Bits)
Tx Macro Table
FD (7 Bits)
Rx Delay Table
FD (7 Bits)
Tx Delay Table
$0020_3140
Figure 10-2. Event Table Structure
The Frame Table Event Comparator (FTEC) fetches the Absolute Time Interval Count
(ATIC) in the Frame Table entry pointed to by the Frame Table Pointer Register
(FTPTR). The FTEC compares its ATIC value with the current value of CTIC. When the values match, the FTEC generates an internal signal, FT Hit, initiating activity corresponding to the entryÕs event code. The pointer is then incremented to the next entry in the table.
There are two Macro Timing Control Units (MTCUs), one each for the receive macro and the transmit macro. The MTCU for the receive macro loads a down counter with the relative time interval count (RTIC) in the entry in the Receive Macro Table pointed to by the Receive Macro Table Pointer (RxPTR) field in the Macro Table Pointer Register
(MTPTR). When the counter reaches zero, the receive MTCU generates an internal signal,
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PT Operation
Rx Hit, initiating activity corresponding to the entryÕs event code. The pointer is then incremented to the next entry in the table. In similar fashion, the transmit macro uses the
Transmit Macro Table Pointer (TxPTR) in MTPTR to generate Tx Hit.
The Event Control Unit (ECU) responds to FT Hit, Tx Hit, or Rx Hit by reading the event code (EC) associated with the table entry that generated the hit. The ECU decodes the EC and initiates one of the following events:
¥ Force one of the eight TOUT pins high or low.
¥ Issue one of the four QSPI triggers.
¥ Control event table sequencing.
¥ Alert the interrupt controller to generate one of these interrupts:
Ñ one of the three MCU interrupts.
Ñ DSP interrupt (DSP IRQD.
Ñ one of the sixteen DSP vector interrupts.
In addition, the ECU can initiate a Transmit or Receive Macro. (A macro cannot initiate another macro.)
The Interrupt Controller receives inputs from the ECU, CFC, RSC, and Error Detector to
10.2 PT Operation
This section describes all aspects of PT operation, including sequencing and generating events within a frame and in the transmit and receive macros, the various PT operating modes, error detection, and a summary of the interrupts generated by the PT.
10.2.1 Frame Events
The PT provides two frame tables to contain the primary lists of events to be triggered.
The base addresses of these tables are stored in the Frame Table Base Address Register
(FTBAR). Each entry in a frame table has a 14-bit Absolute TIC field and a 7-bit Event
Code field, as shown in Figure 10-3.
Only one of the frame tables is active at a given time; the inactive table can be updated for later use. The active table can be switched by encoding an end_of_frame_switch or table_change command. If the active table is Frame Table 1, it can be switched to Frame
Table 0 with the end_of_frame_halt command.
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PT Operation
15
Byte Offset 0
6
EC
Byte Offset 1
0
Offset:
0
15 13 0
ATIC
Byte Offset 3 Byte Offset 2
Figure 10-3. Frame Table Entry
2
Frame table entries are subject to the following restrictions:
1. All entries in each frame table must be in sequential order, i.e., with decreasing
ATIC fields.
2. The ATIC value of each entry in a frame table must be less than the CTIC modulus,
CTIMR.
3. Only one event can be scheduled per ATIC.
4. An end_of_frame command must be executed before CTIC rolls over.
5. The delay and end_of_macro events are for macros only.
6. Writing to a frame table entry that is currently being executed can generate erratic results. To guard against this possibility, MCU software can be written so as not to write to the active frame table.
When the protocol timer is enabled or exits the HALT state, FTPTR is initialized to the first entry in frame table 0 (the FTBA0 field in FTBAR). When the value in CTIC matches the ATIC field pointed to by FTPTR, the FTEC asserts an internal Frame Hit signal to the
ECU, which generates the event specified by the EC field of the FTPTR entry. FTPTR is then incremented. The cycle repeats until one of the end_of_frame commands or the table_ change command is executed. Each of these commands reinitializes FTPTR to the first entry of one of the frame tables.
10.2.2 Macro Tables
The protocol timer can generate a separate, independent sequence of events for both a transmission burst and a receive burst. Both of these sequences, or macros, can run concurrently with the basic frame table sequence. Each of the macros occupies a partition in the event table referred to as a macro table. Each macro is called as an event from the frame table. In most cases, the transmit and receive macro tables only need to be written at initialization, providing a substantial reduction in MCU overhead.
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PT Operation
Unlike frame table events, which are based on the absolute value in CTIC, macro events are timed relative to the previous macro event. Each entry in a macro table has a 14-bit
Relative TIC field and a 7-bit Event Code field, as shown in Figure 10-4. The RTIC value
represents the delay, in timer intervals, from the previous macro event (or from the macro call for the first macro event) to the event specified in the EC field. An RTIC value of 0 or
1 generates the event at the next time interval.
15
Byte Offset 0
6
EC
Byte Offset 1
0
Offset:
0
15 13 0
RTIC
Byte Offset 3 Byte Offset 2
Figure 10-4. Macro Table Entry
2
When a receive macro is called, RxPTR is initialized to the first entry in the receive macro table. The address of this first entry is contained in the RxBAR field in the Macro Table
Base Address Register (MTBAR). The RTIC value of this first entry is loaded into a
14-bit down counter in the receive MTCU. When this counter, decremented by the TICK signal, reaches zero, the MTCU asserts an internal Rx Hit signal to the ECU, which generates the event signal specified by the EC field of the macro pointer entry. The macro pointer is incremented, and the cycle repeats until an end_of_macro command is executed.
The transmit macro operates in similar fashion. The base address of the transmit macro table is stored in the TxBAR field in MTBAR. The TxPTR field in MTPTR is the address pointer. A transmit MTCU generates an internal Tx Hit signal to the ECU.
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PT Operation
Macro table entries are subject to the following restrictions:
1. A macro cannot invoke another macro (i.e., macros cannot be nested).
2. Commands that affect frame table operation, which include all end_of_frame commands and the table_change command, are for frame tables only.
3. The last entry in a macro must be the end_of_macro command.
10.2.2.1 Delay Event
The delay event invokes a programmed delay of a specified number of frames and time intervals before the next command in the macro is executed. This event is only valid in macros, and cannot appear in the frame tables.
There are actually eight event codes for invoking the receive macro and eight for the transmit macro. Each of these event codes specifies a different entry in the receive or transmit delay table to be used when the macro calls a delay event. Each delay table entry contains a 7-bit frame delay (FD) and a 14-bit time interval delay (TID), as shown in
15
Byte Offset 0
6
FD
Byte Offset 1
0
15 13 0
TID
Byte Offset 3 Byte Offset 2
Figure 10-5. Delay Table Entry
Offset:
0
2
When a receive macro is called, the delay index (0 through 7) determined by the particular event code used for the call is loaded into the Receive Delay Pointer (RDPTR) field in the
Delay Table Pointer (DTPTR). This number represents the offset from the Receive Delay
Table Base Address (RDBA), encoded in the DTPTR at initialization. Thus, DTPTR points to a specific number of frame delays and time interval delays invoked each time the macro uses the delay command. For example, if a frame table entry calls Rx_macro2, the
TID and the FD are read from the third entry of the receive delay table. When this macro calls a delay, the event after it is delayed by a total of
[ (FD * (time intervals per frame)) + TID ] time intervals.
The transmit macro works in similar fashion using the TDBA and TDPTR fields in
DTPTR to point to an entry in the transmit delay table.
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PT Operation
10.2.3 Operating Modes
The PT provides control bits to determine enable, halt, and low power operation. The
various operating modes are summarized in Table 10-1.
: Table 10-1. Protocol Timer Operation Mode Summary
Mode Description Activity Entry to Mode
Exit from
Mode
Clocks and
Counters disabled
Event
Execution disabled Disabled Timer disabled; GPIO activity only
Normal Full PT operation
HALT PT enters HALT state enabled enabled enabled disabled
TE=0 TE=1
TE=1
Set HLTR bit or end_of_frame_ halt command
MCU enters
DOZE mode
TE=0
Clear THS and
HLTR bits
MCU exits
DOZE mode
DOZE,
TDZD=0
DOZE,
TDZD=1
STOP
MCU enters DOZE mode with peripheral active.
MCU enters DOZE mode with peripheral stop
MCU in STOP mode enabled disabled enabled disabled disabled disabled MCU enters
STOP mode
MCU exits
STOP mode
10.2.3.1 Enabling the PT
The PT is enabled by setting the TE bit in PTCR. If the TIME bit in PTCR is set, the PT is enabled immediately; if TIME is cleared, PT operation starts at the first CFE after TE is set. The TIME bit should only be changed while the PT is disabled (TE cleared).
10.2.3.2 Halting the PT
PT event execution can be halted in one of two ways:
1. Executing the end_of_frame_halt command at the end of a table. Frame table event execution stops immediately.
2. Setting the HLTR bit in PTCR . Frame table event execution continues until one of the end_of_frame commands (event codes $7AÐ$7C) is executed.
In either event, the THIP bit in the PTIER is set to indicate that the PT is in the process of halting.
Note: The PTCR should not be written while a halt is in process, or erratic behavior can result.
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PT Operation
If the MTER bit in PTCR is set, macro activity stops immediately after the end_of_frame event is executed. If MTER is cleared, macro activity continues until the end_of_macro command. When all PT activity has finished, the THS bit in PTSR is set to indicate that the PT is in halt mode. A timer halt interrupt is asserted if the THIE in PTIER is set.
During halt mode, the PT counters and registers remain active. The PT remains in halt mode until the THS bit is cleared by writing it with 1. Event table execution resumes at the beginning of frame table 0.
10.2.3.3 PT Operation in Low Power Modes
The PT remains active in MCU WAIT mode, and also in DOZE mode if the TDZD bit in
TCTR is cleared. When the MCU enters STOP mode (or DOZE mode if TDZD set), PT activity immediately stops, and all PT counters and registers are frozen.
For proper PT operation, the following steps should be taken before entering DOZE mode
(when the TDZD bit in the PTCR is set) or STOP mode:
1. Halt the PT with an end_of_frame_halt command or by setting HLTR.
2. Wait for THS to be asserted.
3. Disable the PT by clearing TE.
When the MCU wakes up, software must reenable the PT by setting the TE bit.
10.2.4 Error Detection
The PTÕs error detector monitors for three types of error during PT activity. It sets a bit in the PTSR when an error is detected, and generates a Protocol Timer Error Interrupt
(TERI) if the TERIE bit in PTIER is set. These errors include:
¥ End Of Frame Error. A CFE has occurred but the timer has not sequenced through one of the end of frame commands (EC = $7AÐ$7C). EOFE is set.
¥ Macro Being Used Error. A frame table calls a macro that is already active. MBUE is set.
¥ Pin Contention Error. Contradicting values drive a PT output pin during the same
Time Interval. PCE is set.
10.2.5 Interrupts
Table 10-2 is a summary of the interrupts generated by the PT.
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PT Operation
Table 10-2. Protocol Timer Interrupt Sources
Name Source Acronym
CFI
CFN
RSNI
MCUI0
MCUI1
MCUI2
DSPI
DVI0
DVI1
......
DVI15
TERI
THI
Channel Frame Interrupt Channel Frame Expire (CFE) signal (CTIC output)
Channel Frame Number Interrupt Channel Frame Counter (CFC) expires
Reference Slot Number Interrupt Reference Slot Counter (RSC) expires
MCU Interrupt 0
MCU Interrupt 1
MCU Interrupt 2 mcu_int0 event mcu_int1 event mcu_int2 event
DSP Interrupt
DSP Vector Interrupt 0
DSP Vector Interrupt 1
. . . . .
DSP Vector Interrupt 15
Timer Error Interrupt
Timer Halt Interrupt dsp_int event
CVR0 event
CVR1 event
. . . . .
CVR15 event
End of Frame Error (EOFE)
Macro Being Used Error (MBUE)
Pin Contention Error (PCE) end_of_frame_halt command
HLTR bit in PTCR set
The PT interrupt generator provides four outputs to the MCU interrupt controller. Each of the first three is dedicated to a single interrupt source: MCUI0, MCUI1 and MCUI2. The fourth output is a logical OR combination of DVI, CFI, CFNI, RSNI, TERI and THI.
Note: To enable the reception of CFI, CFNI, and RSNI during a halt state, the THIE bit in the PTIER should be cleared after the PT is halted.
The PT provides for 16 DSP vectored interrupts (DVIs) through the CVR15Ð0 events, each of which specifies its own DSP vector addresses on VAB[7Ð0]. Another event, dsp_int, affects the DSP indirectly by generating DSP IRQD through the MDI. Refer to
the description of the MTIR bit in the MSR on page 5-21. Dsp_irq differs from the CVR
events in that it can wake the DSP from STOP mode.
10.2.6 General Purpose Input/Output (GPIO)
Any of the eight PT output pins TOUT7Ð0 can be configured as GPIO. GPIO functionality is determined by three registers:
¥ The Protocol Timer Port Control Register (PTPCR) determines which pins are
GPIO and which function as PT pins.
¥ The Protocol Timer Direction Register (PTDDR) configures each GPIO pin as either an input or output
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PT Event Codes
¥ The Protocol Timer Port Data Register (PTPDR) contains input data from GPI pins and data to be driven on GPO pins.
GPIO register functions are summarized in Table 10-3.
Table 10-3. PT Port Pin Assignment
PTPCR[i]
1
0
0
PTDDR[i]
X
0
1
Port Pin[i] Function
Protocol Timer
GP input
GP output
Tx_macro0
1
Tx_macro1
Tx_macro2
Tx_macro3
Tx_macro4
Tx_macro5
Tx_macro6
Tx_macro7
Rx_macro0
Rx_macro1
Rx_macro2
Rx_macro3
Rx_macro4
Rx_macro5
Rx_macro6
Rx_macro7
Negate_Tout0
2
Assert_Tout0
Negate_Tout
Assert_Tout1
10.3 PT Event Codes
Table 10-4 lists the 128 possible PT events and their corresponding event codes.
Event Name
Table 10-4. Protocol Timer Event List
Event
Code
$00
$0D
$0E
$0F
$10
$09
$0A
$0B
$0C
$05
$06
$07
$08
$01
$02
$03
$04
$11
$12
$13
Start Tx macro with delay 0
Start Tx macro with delay 1
Start Tx macro with delay 2
Start Tx macro with delay 3
Start Tx macro with delay 4
Start Tx macro with delay 5
Start Tx macro with delay 6
Start Tx macro with delay 7
Start Rx macro with delay 0
Start Rx macro with delay 1
Start Rx macro with delay 2
Start Rx macro with delay 3
Start Rx macro with delay 4
Start Rx macro with delay 5
Start Rx macro with delay 6
Start Rx macro with delay 7
Tout0 = 0
Tout0 = 1
Tout1 = 0
Tout1 = 1
Description
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PT Event Codes
CVR6
CVR7
CVR8
CVR9
CVR10
CVR11
CVR12
CVR13
Trigger3 reserved
CVR0
CVR1
CVR2
CVR3
CVR4
CVR5
CVR14
CVR15 reserved
Negate_Tout2
Assert_Tout2
Negate_Tout3
Assert_Tout3
Negate_Tout4
Assert_Tout4
Negate_Tout5
Assert_Tout5
Negate_Tout6
Assert_Tout6
Negate_Tout7
Assert_Tout7 reserved
Trigger0
Trigger1
Trigger2
Event Name
Table 10-4. Protocol Timer Event List (Continued)
Event
Code
$18
$19
$1A
$1B
$14
$15
$16
$17
Tout2 = 0
Tout2 = 1
Tout3 = 0
Tout3 = 1
Tout4 = 0
Tout4 = 1
Tout5 = 0
Tout5 = 1
$1C
$1D
$1E
$1F
Tout6 = 0
Tout6 = 1
Tout7 = 0
Tout7 = 1
$2F-$20 Reserved for future use
$30 Activate QSPI Trigger 0
$31
$32
Activate QSPI Trigger 1
Activate QSPI Trigger 2
$4A
$4B
$4C
$4D
$46
$47
$48
$49
$33 Activate QSPI Trigger 3
$3F-$34 Reserved for future use
$40
$41
DSP vector Interrupt 0
DSP vector Interrupt 1
$42
$43
$44
$45
DSP vector Interrupt 2
DSP vector Interrupt 3
DSP vector Interrupt 4
DSP vector Interrupt 5
$4E
$4F
$57-50
DSP vector Interrupt 6
DSP vector Interrupt 7
DSP vector Interrupt 8
DSP vector Interrupt 9
DSP vector Interrupt 10
DSP vector Interrupt 11
DSP vector Interrupt 12
DSP vector Interrupt 13
DSP vector Interrupt 14
DSP vector Interrupt 15
Reserved for future use
Description
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PT Registers
Table 10-4. Protocol Timer Event List (Continued)
Event Name
Event
Code
Description mcu_int0 mcu_int1 mcu_int2 reserved dsp_int reserved reload_counter table_change
3 end_of_frame_halt
3 end_of_frame_repeat
3 end_of_frame_switch
3 end_of_macro
4 delay
4 nop
$58
$59
$60
$77-61
$78
$79
$7A
$7B
$7C
$7D
$7E
Assert MCUINT0 signal
Assert MCUINT1signal
$5A Assert MCUINT2 signal
$5B-$5F Reserved for future use
Assert DSPINT signal
Reserved for future use
Load CTIMR register to CTIC.
Load first opcode of non-active table.
Last event of frame and PT halt.
Last event of frame and load first opcode of current table.
Last event of frame and load first opcode of non-active table.
Last macro event.
Activate delay.
$7F No operation
1.
Macros can only be called from the frame tables.
2.
The negate/assert_Tout n
events are the only events that affect external pins.
3.
Can be activated only from frame table.
4.
Can be activated only from macro table.
10.4 PT Registers
Table 10-5 is a summary of the 19 user-programmable PT control and GPIO registers,
including the acronym, bit names, and address (least-significant halfword) of each register. The most-significant halfword of all register addresses is $0020.
Table 10-5. Protocol Timer Register Summary
PTCR 15 14 13 12 11 10 9
$3800
8
RSCE CFCE
7 6 5 4 3 2 1 0
HLTR SPBP TDZD MTER TIME TE
PTIER 15 14 13 12
$3802
11 10 9
TERIE THIE DVIE DSIE
PTSR 15 14 13
$3804
12 11
PCE MBUE EOFE THS
10 9
DVI DSPI
PTEVR
$3806
15 14 13 12 11 10 9 8
8 7 6 5
MCIE[2:0]
4 3 2 1 0
RSNIE CFNIE CFIE
8
7
7
6
6 5
MCUI[2:0]
5 4
4
3
3
RSNI CFNI
2
2
1
1
CFI
0
0
THIP TXMA RXMA ACT
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PT Registers
TIMR
$3808
CTIC
$380A
CTIMR
$380C
CFC
$380E
CFMR
$3810
RSC
$3812
RSMR
$3814
PTPCR
$3816
15
15
15
15
15
15
15
15
14
14
14
14
14
14
14
14
13
13
13
13
13
13
13
13
12
12
12
12
12
12
12
12
11
11
11
11
11
11
11
11
10
10
10
10
10
10
10
10
9
9
9
9
9
9
9
9
PTDDR 15 14 13 12 11 10 9
$3818
PTPDR 15 14 13 12 11 10 9
$381A
FTPTR 15 14 13 12 11 10 9
$381C
MTPTR 15 14 13 12 11 10 9
$381E TxPTR[6:0]
8
8
FTBAR 15 14 13 12 11 10 9
$3820 FTBA1[6:0]
MTBAR 15 14 13 12 11 10 9
$3822 TxBAR[6:0]
8
8
DTPTR 15 14 13 12 11 10 9
$3824 TDBA[3:0] TDPTR[2:0]
8
8 7 6
8
8
8
7 6
CTIV[13:0]
7 6
CTIPV[13:0]
7 6
5
5 4
TIPV[8:0]
3
5 4 3
4 3
5 4
CFCV[8:0]
3
8 7 6
8 7 6
5 4
CFPV[8:0]
3
5 4 3
RSCV[7:0]
8 7 6 5
8
8
8
7
7
7
6
6
6
5
5
5
4 3
RSPV[7:0]
4 3
PTPC[7:0]
4 3
PTDD[7:0]
4 3
PTPD[7:0]
7
7
7
7
7
6
6
6
6
6
5
5
2
2
2
2
2
2
2
2
2
2
4 3
FTPTR[7:0]
2
4 3
RxPTR[6:0]
2
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
5
5
5
4 3
FTBA0[6:0]
2
4 3
RxBAR[6:0]
2
4
RDBA[3:0]
3
1
1
0
0
2 1
RDPTR[2:0]
0
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PT Registers
10.4.1 PT Control Registers
PTCR
Name
RSCE
Bit 9
CFCE
Bit 8
HLTR
Bit 5
SPBP
Bit 4
TDZD
Bit 3
MTER
Bit 2
TIME
Bit 1
TE
Bit 0
Bit 15 14
RESET 0 0
13
0
12
0
Protocol Timer Control Register
11 10 9 8
RSCE CFCE
7 6 5 4 3
$0020_3800
2 1 Bit 0
HLTR SPBP TDZD MTER TIME TE
0 0 0 0 0 0 0 0 0 0 0 0
Table 10-6. PTCR Description
Description Settings
Reference Slot Counter Enable
Channel Frame Counter Enable
0 = Disabled (default).
1 = Enabled.
0 = Disabled (default).
1 = Enabled.
Halt RequestÑ Setting this bit halts PT operation at the next end_of_frame event. Macros may or may not complete depending on the state of the
MTER bit.
0 = No halt request (default).
1 = Halt request.
Slot Prescaler BypassÑ This bit determines if
RSC is driven by the prescaler output (RSE) or the TICK signal
Timer DOZE Disable
0 = Not bypassedÑRSC input =
TICK/2400(defalut).
1 = BypassedÑRSC input = TICK.
Macro TerminationÑ This bit determines if macros are allowed to complete (i.e., continue to run until the end_of_macro command) when a halt event or halt request is issued.
Timer Initiate EnableÑ This bit determines if event execution begins immediately or waits for the next frame signal (CFE) after the PT is enabled (TE set) or the PT exits the halt state.
0 = PT ignores DOZE mode (default).
1 = PT stops in DOZE mode.
0 = Macros run to completion (default).
1 = Macros halted immediately.
0 = Execution delayed until next CFE (default).
1 = Execution begins immediately after TE is set or halt state terminates, as soon as CTIC equal the first ATIC value in the event table.
Timer EnableÑ This bit is a ÒhardÓ enable/disable of PT activity. Clearing TE stops all PT activity immediately, regardless of the state of MTER.
0 = PT disabled (default).
1 = PT enabled.
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PT Registers
PTIER
Bit 15 14 13
0
Protocol Timer Interrupt Enable Register
12 11 10 9 8 7 6 5 4
TERIE THIE DVIE DSIE
0 0 0 0 0 0
MCIE2 MCIE1 MCIE0
0 0 0
3
$0020_3802
2 1 Bit 0
RSNIE CFNIE CFIE
0 0 0 RESET 0 0 0
Note:
The conditions in Table 10-7 must be met in addition to setting the individual
interrupt enable bits in the PTIER.
Table 10-7. Additional Conditions for Generating PT Interrupts
PTIER Bit
MCIE2
MCIE1
MCIE0
TERIE
THIE
DVIE
RSNIE
CFNIE
CFIE
DSIE
Additional Conditions
Set EPT2 bit in the NIER or EFPT2 bit in the FIER.
Set EPT1 bit in the NIER or EFPT1 bit in the FIER.
Set EPT0 bit in the NIER or EFPT0 bit in the FIER.
Set EPTM bit in the NIER or EFPTM bit in the FIER.
Write the IDPL field in the IPRC with a non-zero value.
The NIER and FIER registers are described on page 7-7.
The IPRC register is described on page 7-14.
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MCIE2
Bit 6
MCIE1
Bit 5
MCIE0
Bit 4
RSNIE
Bit 2
Name
TERIE
Bit 12
THIE
Bit 11
DVIE
Bit 10
DSIE
Bit 9
CFNIE
Bit 1
CFIE
Bit 0
Table 10-8. PTIER Description
Description Settings
Timer Error Interrupt EnableÑ Enables an MCU interrupt when a timer error has been detected (see
Section 10.2.4 on page 10-11).
Timer HALT Interrupt EnableÑ Enables an MCU interrupt when the PT enters the halt state either from a frame table command or setting the HLTR bit in
PTCR.
DSP Vector Interrupt EnableÑ Enables an MCU interrupt when a CVR command is executed.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
DSP Interrupt EnableÑ Enables a DSP IRQD interrupt to the DSP through the MDI when a dsp_int command is executed.
MCU Interrupt 2 EnableÑ Enables an MCU interrupt when an mcu_int2 command is executed.
MCU Interrupt 1 EnableÑ Enables an MCU interrupt when an mcu_int1 command is executed.
MCU Interrupt 0 EnableÑ Enables an MCU interrupt when an mcu_int0 command is executed.
Reference Slot Number Interrupt EnableÑ enables an MCU interrupt when the RSC decrements to zero.
Channel Frame Number Interrupt EnableÑ
Enables an MCU interrupt when the CFC decrements to zero.
Channel Frame Interrupt EnableÑ Enables an
MCU interrupt when the CTIC decrements to zero.
PT Registers
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PT Registers
Name
PCE
Bit 14
EOFE
Bit 12
THS
Bit 11
MCUI0
Bit 4
RSNI
Bit 2
CFNI
Bit 1
CFI
Bit 0
DVI
Bit 10
DSPI
Bit 9
MCUI2
Bit 6
MCUI1
Bit 5
PTSR
Bit 15 14 13 12
Protocol Timer Status Register
11 10 9
PCE MBUE EOFE THS DVI DSPI
8 7 6 5 4
MCU2 MCU1 MCU0
RESET 0 0 0 0 0 0 0 0 0 0 0 0
3
$0020_3804
2 1 Bit 0
RSNI CFNI CFI
0 0 0 0
Each of these bits is cleared by writing it with 1.Writing zero to a bit has no effect.
MBUE
Bit 13
Table 10-9. PTSR Description
Description
Pin Contention ErrorÑ Set when two events attempt to drive opposite values to a PT pin simultaneously.
Macro Being Used ErrorÑ Set when a frame table command calls a macro that is already active.
End of Frame ErrorÑ Set when CFE occurs before an end_of_frame command.
Timer Halt StateÑ Indicates if the PT is in halt state. Operation resumes from the beginning of frame table 0 when THS is cleared.
DSP Vector InterruptÑ Set by a CVR event.
DSP InterruptÑ Set by a dsp_int event.
MCU2 InterruptÑ Set by an mcu_int2 event.
MCU1 InterruptÑ Set by an mcu_int1 event.
MCU0 InterruptÑ Set by an mcu_int0 event.
Reference Slot Number InterruptÑ Set when the RSC decrements to zero.
Channel Frame Number InterruptÑ Set when the CFC decrements to zero.
Channel Frame InterruptÑ Set when the CTIC decrements to zero.
Settings
0 = PCE has not occurred (default).
1 = PCE has occurred.
0 = MBUE has not occurred (default).
1 = MBUE has occurred
0 = EOFE has not occurred (default).
1 = EOFE has occurred.
0 = Normal mode (default).
1 = Halt mode.
0 = DVI has not occurred (default).
1 = DVI has occurred.
0 = DSPI has not occurred (default).
1 = DSPI has occurred.
0 = MCUI2 has not occurred (default).
1 = MCUI2 has occurred.
0 = MCUI1 has not occurred (default).
1 = MCUI1 has occurred.
0 = MCUI0 has not occurred (default).
1 = MCUI0 has occurred.
0 = RSNI has not occurred (default).
1 = RSNI has occurred.
0 = CFNI has not occurred (default).
1 = CFNI has occurred.
0 = CFI has not occurred (default).
1 = CFI has occurred.
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PT Registers
PTEVR
Bit 15 14
Name
THIP
Bit 3
TxMA
Bit 2
RxMA
Bit 1
ACT
Bit 0
13 12
Protocol Timer Event Register
11 10 9 8 7 6 5 4
0
3
$0020_3806
2 1 Bit 0
THIP TXMA RXMA ACT
0 0 0 0 RESET 0 0 0 0 0
PTEVR is a read-only register.
0 0 0 0 0 0
Table 10-10. PTEVR Description
Description Settings
Timer Halt in ProcessÑ Indicates if the PT is in the process of halting.
Transmit Macro Active
Receive Macro Active
Active Frame Table
0 = Normal mode (default).
1 = Halt mode in progress.
0 = Not active(default).
1 = Active.
0 = Not active(default).
1 = Active.
0 = Frame table 0 active (default).
1 = Frame table 1 active.
TIMR
Bit 15 14
RESET 0
Name
TIMV
Bits 8Ð0
0
13
0
12
0
Time Interval Modulus Register
11 10 9 8 7 6 5 4
TIMV[8:0]
3
0 0 0 0 0 0 0 0 0
Table 10-11. TIMR Description
Description
$0020_3808
2
0
1
0
Bit 0
0
Time Interval Modulus ValueÑ This field contains the value loaded into CTIG when it rolls over.
When TIMV = n, the PT reference clock TICK frequency is MCU_CLK/(n+1). This register should be written before the PT is enabled.
Note: In normal operation, TIMR must be greater than 5 to ensure reliable PT event generation.
However, TIMR values of 2 to 5 are sufficient for tracking channel activity when the PT does not execute events, such as in low power modes. TIMR values of 0 and 1 are not supported.
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PT Registers
CTIC
Bit 15 14
RESET 0
Name
CTIV[13:0]
Bits 13Ð0
0
13
0
12
0
Channel Time Interval Counter
11 10 9 8 7 6 5
0 0 0 0
CTIV[13:0]
0 0 0
Table 10-12. CTIC Description
Description
4
0
3
0
$0020_380A
2
0
1
0
Bit 0
0
Channel Time Interval ValueÑ This field contains the current CTIC value. CTIC is described on
CTIMR
Bit 15 14
RESET 0 0
13
0
Channel Time Interval Modulus Register
12 11 10 9 8 7 6 5 4
0 0 0 0 0
CTIMV[13:0]
0 0 0 0
Table 10-13. CTIMR Description
Description
3
0
$0020_380C
2
0
1
0
Bit 0
0
Name
CTIMV
Bits 13Ð0
Time Interval Modulus ValueÑ This field contains the value loaded into CTIC when it rolls over or when a reload_counter command. The actual CTIC modulus is equal to CTIMV + 1. For example, to obtain a CTIC modulus value of 2400, this field should be written with 2399 (=$95F).
CFC
Bit 15 14
RESET 0
Name
CFCV[8:0]
Bits 8Ð0
0
13
0
12
0
11
Channel Frame Counter
10 9 8 7 6
0 0 0 0 0 0
Table 10-14. CFC Description
Description
5 4
CFCV[8:0]
3
0 0 0
$0020_380E
2
0
1
0
Bit 0
Channel Time Interval ValueÑ This field contains the current CFC value. CFC is described on
Note: Writing CFC with zero when it is enabled sets the CFNI bit in PTSR and generates an interrupt if the CFNIE bit in PTIER is set.
0
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PT Registers
CFMR
Bit 15 14
RESET 0
Name
CFMV
Bits 8Ð0
0
13
0
12
Channel Frame Modulus Register
11 10 9 8 7 6 5 4
CFMV[8:0]
3
0 0 0 0 0 0 0 0 0 0
Table 10-15. CFMR Description
Description
$0020_3810
2
0
1
0
Bit 0
0
Channel Frame Modulus ValueÑ This field contains the value loaded into CFC when it is enabled and when it rolls over. A CFMV value of 0 is not supported. This register should be written before the
CFC is enabled.
RSC
Bit 15 14
RESET 0
Name
RSCV[7:0]
Bits 7Ð0
11
Reference Slot Counter
10 9 8 7 6
$0020_3812
2 1 Bit 0 13 12 5 4 3
RSCV[7:0]
0 0 0 0 0 0 0 0 0 0 0 0
Table 10-16. RSC Description
Description
0 0
Reference Slot Count ValueÑ This field contains the current RSC value. RSC is described on
Note: Writing RSC with zero when it is enabled sets the RSNI bit in PTSR and generates an interrupt if the RSNIE bit in PTIER is set.
0
RSMR
Bit 15 14
RESET 0
Name
RSMV
Bits 7Ð0
0
13
0
12
Reference Slot Modulus Register
11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
Table 10-17. RSMR Description
Description
4 3
RSMV[7:0]
0 0
$0020_3814
2
0
1
0
Bit 0
0
Reference Slot Modulus ValueÑ This field contains the value loaded into RSC when it is enabled and when it rolls over. An RSMV value of 0 is not supported. This register should be written before the RSC is enabled.
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PT Registers
FTPTR
Bit 15 14
RESET 0
Name
FTPTR[6:0]
Bits 6Ð0
0
13
0
12 11
Frame Table Pointer
10 9 8 7 6 5
0 0 0 0 0 0 Ñ Ñ
Table 10-18. FTPTR Description
Description
4 3
FTPTR[6:0]
$0020_381C
2 1 Bit 0
Ñ Ñ Ñ Ñ Ñ
Frame Table Pointer[6:0]Ñ These read-only bits contain a pointer to the next frame table entry.
MTPTR
Bit 15 14
RESET 0
Name
TxPTR[6:0]
Bits 14Ð8
RxPTR[6:0]
Bits 6Ð0
Ñ
13
Ñ
12 11
TxPTR[6:0]
Macro Table Pointer
10 9 8 7 6
Ñ Ñ Ñ Ñ Ñ 0 Ñ
5
Ñ
Table 10-19. MTPTR Description
Description
4 3
RxPTR[6:0]
$0020_381E
2 1 Bit 0
Ñ Ñ Ñ Ñ Ñ
Transmit Macro Pointer[6:0]Ñ These read-only bits contain a pointer to the next transmit macro table entry.
Receive Macro Pointer[6:0]Ñ These read-only bits contain a pointer to the next receive macro table entry.
FTBAR
Bit 15 14
RESET 0
Name
FTBA1[6:0]
Bits 14Ð8
FTBA0[6:0]
Bits 6Ð0
Ñ
13
Ñ
Frame Table Base Address Register
12 11 10 9 8 7 6 5 4
FTBA1[6:0]
3
FTBA0[6:0]
$0020_3820
2 1 Bit 0
Ñ Ñ Ñ Ñ Ñ 0 Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 10-20. FTBAR Description
Description
Frame Table 1 Base Address[6:0]Ñ These bits specify the offset from the beginning of PT RAM
($0020_3000) of the first entry in Frame Table 1. They should be initialized before the PT is enabled.
Frame Table 0 Base Address[6:0]Ñ These bits specify the offset from the beginning of PT RAM of the first entry in Frame Table 0. They should be initialized before the PT is enabled.
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PT Registers
MTBAR
Bit 15 14
RESET 0
Name
TxBA1[6:0]
Bits 14Ð8
RxBA0[6:0]
Bits 6Ð0
Ñ
13
Ñ
Macro Table Base Address Register
12 11 10 9 8 7 6 5 4
TxBA1[6:0]
3
RxBA0[6:0]
$0020_3822
2 1 Bit 0
Ñ Ñ Ñ Ñ Ñ 0 Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 10-21. MTBAR Description
Description
Transmit Macro Base Address[6:0]Ñ These bits specify the offset from the beginning of PT RAM of the first entry in the transmit macro. They should be initialized before the first transmit macro is activated.
Receive Macro Base Address[6:0]Ñ These bits specify the offset from the beginning of PT RAM of the first entry in the receive macro. They should be initialized before the first receive macro is activated.
DTPTR
Bit 15 14
RESET 0
Name
TDBA[3:0]
Bits 14Ð11
TDPTR[2:0]
Bits 10Ð8
RDBA[3:0]
Bits 6Ð3
RDPTR[2:0]
Bits 2Ð0
Ñ
13 12
TDBA[3:0]
Ñ Ñ
11
Ñ
Delay Table Pointer
10 9 8
Ñ
TDPTR[2:0]
Ñ Ñ
7
0
6
Ñ
5 4
RDBA[3:0]
Ñ Ñ
Table 10-22. DTPTR Description
Description
3
Ñ
$0020_3824
2 1 Bit 0
Ñ
RDPTR[2:0]
Ñ Ñ
Transmit Macro Delay Table Base Address[3:0]Ñ These bits determine the location in memory of the first entry in the transmit macro delay table. They contain the four most significant bits of the
7-bit offset from the beginning of PT RAM. TDBA should be initialized before the first transmit macro is activated.
Transmit Macro Delay Pointer[2:0]Ñ These read-only bits are the three-bit offset from TDBA that point to the delay table entry of the active transmit macro. They are specified by the particular event code that called the macro.
Receive Macro Delay Table Base Address[3:0]Ñ These bits determine the location in memory of the first entry in the receive macro delay table. They contain the four most significant bits of the
7-bit offset from the beginning of PT RAM. RDBA should be initialized before the first receive macro is activated.
Receive Macro Delay Pointer[2:0]Ñ These read-only bits are the three-bit offset from TDBA that point to the delay table entry of the active receive macro. They are specified by the particular event code that called the macro.
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PT Registers
10.4.2 GPIO Registers
PTPCR
Bit 15 14
RESET 0
Name
PTPC[7:0]
Bits 7Ð0
0
13
0
11
PT Port Control Register
10 9 8 7 6 12
0
5
0 0 0 0 0 0 0
Table 10-23. PTPCR Description
Description
4 3
PTPC[7:0]
0 0
Settings
$0020_3816
2 1 Bit 0
0 0 0
PT Port ControlÑ Each of these bits determines if the corresponding TOUT pin functions as a PT
TOUT pin or GPIO.
0 = GPIO (default).
1 = Protocol timer pin (TOUT)
PTDDR
Bit 15 14
RESET 0
Name
PTDD[7:0]
Bits 7Ð0
13 12
PT Data Direction Register
11 10 9 8 7 6 5 4 3
PTDD[7:0]
0 0
$0020_3818
2 1 Bit 0
0 0 0 0 0 0 0 0 0 0 0 0 0
Table 10-24. PTDDR Description
Description
PT Data DirectionÑ For each PT pin that is configured as GPIO, the corresponding PTDD pin determines if it is an input or output.
0 = Input (default).
1 = Output
Settings
PTPDR
Bit 15 14
RESET 0
Name
PTPD[7:0]
Bits 7Ð0
13 12 11
PT Port Data Register
10 9 8 7 6 5 4 3
PTPD[7:0]
Ñ Ñ
$0020_381A
2 1 Bit 0
Ñ Ñ Ñ 0 0 0 0 0 0 0 Ñ Ñ Ñ
Table 10-25. PTPDR Description
Description
PT Port DataÑ The function of each of these bits depends on how the corresponding TOUT pin is configured.
¥ PT Reading PTPDn reflects the internal latch.
Writing PTPDn writes the data latch. If the PT is disabled (TE = 0), the PTPDn is the initial state of the TOUT driver.
¥ GPI Reading PTPDn reflects the pin value.
Writing PTPDn writes the data latch.
¥ GPO Reading PTPDn reflects the data latch, which equals the pin value.
Writing PTPDn writes the data latch which drives the pin value.
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Protocol Timer Programming Example
10.5 Protocol Timer Programming Example
The following lines illustrate a typical series of entries in the event table.
Frame Table No. 0
<abs TIC> trigger QSPI_0
<abs TIC> Rx_macro0Start Rx burst timing macro
<abs TIC> Tx_macro1start Tx burst timing macro
<abs TIC> trigger CVR5
<abs TIC> Rx_macro2start Rx burst timing macro
<abs TIC> Table_change
Frame Table No. 1
<abs TIC> Rx_macro2start Rx burst timing macro
<abs TIC> DSP_int DSP interrupt
<abs TIC> MCU_int_0
<abs TIC> trigger QSPI_2
MCU interrupt
<abs TIC> Tx_macro3start Tx burst timing macro
<abs TIC> End_of_frame_repeat
Receive Macro Table
<rel TIC> Assert_Tout3
<rel TIC> delay
<rel TIC> trigger QSPI_1
<rel TIC> Negate_Tout3
<rel TIC> End_of_macro
Transmit Macro Table
<rel TIC> Assert_Tout6
<rel TIC> Assert_Tout7
<rel TIC> trigger CVR2
<rel TIC> delay
<rel TIC> MCU_int_0
<rel TIC> Negate_Tout6
<rel TIC> End_of_macro activate delay activate delay
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Protocol Timer Programming Example
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Chapter 11
UART
The Universal Asynchronous Receiver/Transmitter (UART) module provides communication with external devices such as modems and other serial devices. Key features of the UART include the following:
¥ Full duplex operation.
¥ Full 8-wire serial interface.
1
¥ Direct support of the Infrared Data Association (IrDA) mechanism.
¥ Robust receiver data sampling with noise filtering.
¥ 16-word FIFOs for transmit and receive, block-addressable with the LDM and
STM instructions.
¥ 7- or 8-bit characters with optional even or odd parity and one or two stop bits.
¥ BREAK signal generation and detection.
¥ 16x bit clock generator providing bit rates from 300 bps to 525 Kbps.
¥ Four maskable interrupts.
¥ RTS interrupt providing wake from STOP mode.
¥ Low power modes.
¥ Internal or external 16x clock.
¥ Far-end baud rate can be automatically determined (autobaud).
2
The UART performs all normal operations associated with Òstart-stopÓ asynchronous communication. Serial data is transmitted and received at standard bit rates in either NRZ or IrDA format.
11.1 UART Definitions
The following definitions apply to both transmitter and receiver operation:
1.Using GPIO pins for DSR, DCD, DTR, and RI.
2.Using the GP timer.
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UART Architecture
Bit TimeÑ The time allotted to transmit or receive one bit of data.
Start BitÑ One bit-time of logic zero that indicates the beginning of a data frame. A start bit must begin with a one-to-zero transition.
Stop BitÑ One bit-time of logic one that indicates the end of a data frame.
FrameÑ A series of bits consisting of the following sequence:
1. A start bit
2. 7 or 8 data bits
3. optional parity bit
4. one or two stop bits
BREAKÑ A frame in which all bits, including the stop bit, are logic zero. This frame is normally sent to signal the end of a message or the beginning of a new message.
Framing ErrorÑ An error condition in which the expected stop bit is a logic zero. This can be caused by a misaligned frame, noise, a BREAK frame, or differing numbers of data and/or stop bits between the two devices. Note that if a UART is configured for two stop bits and only one stop bit is received, this condition is not considered a frame error.
Parity ErrorÑ An error condition in which the calculated parity of the received data bits in a frame differs from the frameÕs parity bit. Parity error is only calculated after an entire frame is received.
Overrun ErrorÑ An error condition in which the receive FIFO is full when another character is received. The received character is ignored to prevent overwriting the existing data. An overrun error indicates that the software reading the FIFO is not keeping up with character reception on the RxD line.
11.2 UART Architecture
This section provides a brief description of the UART transmitter, receiver, clock generator, infrared interface, pins, and frame configuration. A block diagram of the UART
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UART Architecture
Rx FIFO and Shifter
DCE
Interface
RTS
CTS
MCU
Peripheral
Bus
Tx FIFO and Shifter
Infrared
Interface
TxD
RxD
16x Bit
Clock
Autobaud
Input Capture 1
CKIH SCLK
Clock
Generator
Data
Control
Interrupt Control
Figure 11-1. UART Block Diagram
GPIO
INT7/ DTR
RI
DCD
DSR
11.2.1 Transmitter
The UART transmitter contains a 16-word FIFO (UTX) with one character (byte) per word. Word-aligned characters enable the MCU to perform block writes using the Store
Multiple (STM) command. The transmitter adds start, stop and optional parity bits to each character to generate a transmit frame. It then shifts the frame out serially on the UART transmission pin, TxD. One bit is shifted on each cycle of a Ò1xÓ transmit clock. It derives the 1x clock from the Ò16xÓ clock produced by the clock generator. Transmission can begin as soon as UTX is written, or can be delayed until the far-end receiver asserts the
RTS signal. Interrupts can be generated when RTS changes state and when UTX is empty or the number of untransmitted words falls below a programmed threshold. The transmitter is enabled by setting the TxEN bit in UART Control Register 1 (UCR1).
11.2.2 Receiver
The UART receiver contains a 16-word FIFO (URX), one character per word, enabling the MCU to perform block reads using the Load Multiple (LDM) command. It receives bits serially from the UART receive pin, RxD, strips the start, stop, and parity (if present) bits and stores the characters in URX. To provide jitter and noise tolerance, the receiver samples each bit 16 times and applies a voting technique to determine the bitÕs value. The receiver monitors data for proper frame construction, BREAK characters (all zeros), parity errors, and receiver overrun. Each of the 16 URX words contains a received character data field, error flags and a Ôcharacter readyÕ flag to indicate when the character
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UART Architecture is ready to be read. Errors flags include those for frame, parity, BREAK, and receiver overrun, as well as a general error flag. In the event of a receiver overrun, the receiver can deassert the CTS signal to turn off the far-end transmitter. The receiver is enabled by setting the RxEN bit in UCR1.
11.2.3 Clock Generator
The clock generator provides a 16x clock signal for the transmitter and receiver. The input can be either CKIH or an external clock, SCLK, applied to the INT7/DTR pin, depending on the state of the CLKSRC bit in UART Control Register 2 (UCR2). CKIH is divided by a 12-bit value written in the UART Bit Rate Generator Register (UBRGR ) .
11.2.4 Infrared Interface
The Infrared Interface converts data to be transmitted or received as specified in the IrDA
Serial Infrared Physical Layer Specification. Each ÒzeroÓ driven on the TxD pin is a narrow logic high pulse, 3/16 of a bit time in duration; each ÒoneÓ is a full logic low. The receiver in kind interprets a narrow pulse on RxD as a ÒzeroÓ and no pulse as a ÒoneÓ.
External circuitry is required to drive an infrared LED with TxD and to convert received infrared signals to electrical signals for RxD. The Infrared Interface is enabled by setting the IREN bit in UCR1.
11.2.5 UART Pins
The DSP56652 provides pins for RTS, CTS, TxD, and RxD. The remaining UART signals can be implemented with GPIO pins. Suggested GPIO pin allocations are listed in
Table 11-1, but any GPIO pins can be used.
Table 11-1. Suggested GPIO Pins for UART Signals
UART Signal Suggested Pin Peripheral
DCD (Data Carrier Detect)
RI (Ring Indicator)
DSR (Data Set Ready)
DTR (Data Terminal Ready)
ROW6
ROW7
INT6
INT7
Keypad PortÑsee Section 13.2 on page 13-4
Edge PortÑsee Section 7.3 on page 7-15
In addition, any unused UART pins can be configured for GPIO.
11.2.6 Frame Configuration
The DSP56652 UART configuration must match that of the external device. The most common frame format consists of one start bit, eight data bits (LSB first), no parity bit,
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UART Operation and one stop bit, for a total of 10 bit times per frame. All elements of the frameÑthe number of data and stop bits, parity enabling and odd/even parityÑare determined by bits in UCR2.
11.3 UART Operation
This section describes UART transmission and reception, clock generation, and operation in low power and Debug modes.
The UART is enabled by setting the UEN bit in UCR1.
11.3.1 Transmission
The MCU writes data for UART transmission to UTX. Normally, the UART waits for
RTS to be asserted before beginning transmission. The RTS pin can be monitored by reading the RTSS bit in the UART Status Register (USR). When RTS changes state, the
RTSD bit in USR is set. If the RTSDIE bit in UCR1 has been set, an interrupt is generated as well. This interrupt can wake the MCU from STOP mode. If RTS is deasserted in mid-character, the UART completes transmission of the character before shutting off the transmitter. Transmitter operation can also proceed without RTS by setting the IRTS bit in
UCR2. In this case, RTS has no effect on the transmitter or RTSD and cannot generate an interrupt.
A BREAK character can be sent by setting the SNDBRK bit in UCR1. When the MCU sets SNDBRK, the transmitter completes any frame in progress and transmits zeros, sampling SNDBRK after every bit is sent. UTX can be written with more transmit data while SNDBRK is set. When it samples SNDBRK cleared, the transmitter sends two marks before transmitting data (if any) in UTX. Care must be taken to ensure that
SNDBRK is set for a sufficient length of time to generate a valid BREAK.
When all data in UTX has been sent and the FIFO and shifter are empty, the TXE bit in
USR is set. If the amount of untransmitted data falls below a programmed threshold, the
TRDY bit in USR is set. The threshold can be set for one, four, eight, or fourteen characters by writing TxFL[1:0] in UCR1. Both TXE and TRDY can trigger an interrupt if the TXEIE and TRDYIE bits respectively in UCR1 are set. The two interrupts are internally wire-orÕd to the interrupt controller.
11.3.2 Reception
The RxD line is at a logic one when it is idle. If the pin goes to a logic low, and the receiver detects a qualified start bit, it proceeds to decode the succeeding transitions on the
RxD pin, monitoring for the correct number of data and stop bits and checking for parity according to the configuration in UCR2. When a complete character is decoded, the data
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UART Operation is written to the data field in a URX register and the CHARRDY bit in that register is set.
If a valid stop bit is not detected a frame error is flagged by setting the URX FRMERR bit.
A parity error is flagged by setting the PRERR bit. If a BREAK frame is detected the BRK and FRMERR flags are set. If the URX is about to overflow (i.e., the FIFO is full as another character is being received), the OVRRUN flag is set. If any of these four flags is set, the ERR bit is also set. If the number of unread words exceeds a threshold programmed by the RxFL[1:0] bits in UCR1, the RRDY bit in USR is set, and an interrupt is generated if the RRDYIE bit in UCR1 has been set. Adjusting the threshold to a value of one can effectively generate an interrupt every time a character is ready. Reading the
URX clears the interrupt and all the flags.
The CTS pin can be asserted to enable the far-end transmitter, and deasserted to prevent receiver overflow. CTS is driven by receiver hardware if the CTSC bit in UCR2 is set. The pin is driven by software via the CTSD bit in UCR2 if CTSC is cleared.
11.3.3 UART Clocks
The clock generator provides a 16x bit clock for the transmitter and receiver. Software can select either an external or internally-generated clock through the CLKSRC bit in UCR2.
Clearing CLKSRC selects the internal clock which is derived by dividing CKIH by a number between 1 and 4096, determined by UBRGR. This provides sufficient flexibility to generate standard baud rates from a variety of clock sources. Clock error calculation is
straightforward, as shown in Example 11-1.
Example 11-1. UART Baud Error Calculation
Desired baud rate = 115.2 kbps
Input clock = 16.8 MHz
Divide ratio
Actual baud rate
= 9 (UBRGR[11:0] = 8)
= 16.8 MHz / 9 / 16 = 116.67 kHz
Actual/required ratio = 116.67 / 115.2 = 1.0127
Error per bit = 1.27%
Error per 12-bit frame = 15%
Setting the CLKSRC bit selects an external clock, SCLK, which is input on the
INT7/DTR pin.
11.3.4 Baud Rate Detection (Autobaud)
The baud rate from the far-end transmitter can be determined in software by observing the duration of the logic one and logic zero states of the Input Capture 1 (IC1) module, which is internally connected to RxD for this purpose.
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UART Operation
.
11.3.5 Low-Power Modes
The UART serial interface operates as long as the 16x bit clock generator is provided with a clock and the UART is enabled (the UARTEN bit in UCR1 is set). The internal bus interface is operational if the system clock is running. The RXEN, TXEN, and UARTEN bits enable low-power control through software. UART functions in the various
hardware-controlled low power modes is shown in Table 11-2.
System Clock
UART Serial I/F
Internal Bus
Table 11-2. UART Low Power Mode Operation
DOZE Mode
Normal
Mode
WAIT
Mode
ON
ON
ON
ON
ON
ON
DOZE = 0
ON
ON
ON
DOZE = 1
ON
OFF
OFF
STOP
Mode
OFF
OFF
OFF
If DOZE mode is entered with the DOZE bit asserted while the UART serial interface is receiving or transmitting data, the UART completes the receive or transmit of the current character, then signals to the far-end transmitter or receiver to stop sending or receiving.
Control, status, and data registers do not change when entering or exiting low-power modes.
11.3.6 Debug Mode
In Debug mode, URX reads do not advance the internal RX FIFO pointer, so repeated
URX reads do not cause the URX to change once it contains a valid character.
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UART Registers
11.4 UART Registers
Table 11-3 is a summary of the UART control and GPIO registers, including the acronym,
bit names, and address (least-significant halfword) of each register. The most-significant halfword of all register addresses is $0020.
Table 11-3. UART Register Summary
URX
$4000Ð
403C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHARRDY ERR OVRRUN FRMERR BRK PRERR Rx DATA
UTX 15 14 13 12 11 10 9
$4040Ð
407C
8 7 6 5 4 3
Tx DATA
2 1 0
UCR1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
$4080 TxFL[1:0] TRDIETXEN RxFL[1:0] RRDYIE RxEN IREN TXEIE RTSDIE SNDBRK DOZE UEN
UCR2
$4082
15 14 13 12
IRTS CTSC CTSD
11 10 9 8 7 6 5 4
PRENPROE STPB WS CLKSRC
3 2 1 0
UBRGR 15 14 13 12 11 10 9
$4084
USR 15 14 13 12 11 10
$4086 TXE RTSS TRDY
9
RRDY
UTS 15 14
$4088
13 12 11
FRCPERR LOOP
10
LOOPIR
8
8
7 6 5
CD[11:0]
7 6 5
RTSD
4 3 2 1 0
4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
8 7 6 5 4 3 0 UPCR 15 14 13 12 11 10 9
$408A
UDDR 15 14 13 12 11 10 9
$408C
UPDR 15 14 13 12 11 10 9
$408E
8
8
7
7
6
6
5
5
4
4
3
3
2 1
PC[3:0]
2 1
PDC[3:0]
2 1
PD[3:0]
0
0
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UART Registers
11.4.1 UART Control Registers
URX
Bit 15 14 13 12
UART Receive Register
11 10 9 8 7 6
CHARRDY ERR OVRRUN FRMERR BRK PRERR
RESET 0 0 0 0 0 0 0 0 Ñ Ñ
5 4 3
Rx DATA
Ñ Ñ
$0020_4000
2 1 Bit 0
Ñ Ñ Ñ Ñ
The 16-entry receive buffer FIFO is accessed through the URX register at address
$0020_4000. This register is actually mapped to 16 word addresses from $0020_4000 to
$0020_403C to support LDM instructions. At reset, the flag bits in the most significant byte are cleared, and the least significant byte, which holds the received character, contains random data.
Table 11-4. URX Description
Description Name Settings
CHARRDY
Bit 15
ERR
Bit 14
OVRRUN
Bit 13
Character ReadyÑ Set when the complete character has been received and error conditions have been evaluated. Cleared when the register is read.
0 = Character not ready (default).
1 = Character ready.
Error DetectedÑ Set when any of the error conditions indicated in bits 13Ð10 is present.
Cleared when the register is read.
0 = No error detected (default).
1 = Error detected.
Receiver OverrunÑ Set when incoming data is ignored because the URX FIFO is full. An overrun error indicates that MCU software is not keeping up with the receiver. Under normal conditions, this bit should never be set. Cleared when the register is read.
0 = No overrun (default).
1 = Overrun error.
FRMERR
Bit 12
BRK
Bit 11
PRERR
Bit 10
Rx DATA
Bits 7Ð0
Frame ErrorÑ Set when a received character is missing a stop bit, indicating that the data may be corrupted. Cleared when the register is read.
0 = No framing error detected (default).
1 = Framing error detected for this character.
BREAK DetectÑ Set when all bits in the frame, including stop bits, are zero, indicating that the current character is a BREAK. FRMERR is also set. If odd parity is employed, PRERR is also set.
BRK is cleared when the register is read.
0 = BREAK not detected (default).
1 = BREAK detected for this character.
Parity ErrorÑ Set when parity is enabled and the calculated parity in the received character does not match the received parity bit, indicating that the data may be corrupted. PRERR is never set when parity is disabled. Cleared when the register is read.
0 = No parity error (default).
1 = Parity error detected for this character.
Received DataÑ This field contains the character in a received frame. In 7-bit mode, bit 7 is always zero.
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UART Registers
UTX
11
UART Transmit Register
10 9 8 7 6
$0020_4040
2 1 Bit 0 Bit 15 14 13 12 5 4 3
Tx DATA
Ñ Ñ RESET 0 0 0 0 0 0 0 0 Ñ Ñ Ñ Ñ Ñ Ñ
The 16-entry transmit buffer FIFO is accessed through the UTX register at address
$0020_4040. This register is actually mapped to 16 word addresses from $0020_4040 to
$0020_407C to support STM instructions. Reading one of these registers returns zeros in bits 15Ð8 and random data in bits 7Ð0.
Name
Tx DATA
Bits 7Ð0
Table 11-5. UTX Description
Description Settings
Transmit DataÑ This field contains data to be transmitted to the far-end device. Writing to this register initiates transmission of a new character. Data is transmitted LSB first. In 7-bit mode, bit 7 is ignored. Tx DATA should only be written when the TRDY bit in USR is set, indicating that UTX can accept more data.
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UART Registers
UCR1
15 14 13 12
UART Control Register 1
11 10 9 8 7 6 5 4
TxFL[1:0] TRDYIE TXEN RxFL[1:0] RRDYIE RxEN IREN TXEIE RTSDIE SNDBRK
RESET 0 0 0 0 0 0 0 0 0 0 0 0
3
$0020_4080
2 1 Bit 0
0 0
DOZE UEN
0 0
Name
Table 11-6. UCR1 Description
Description Settings
TXFL[1:0]
Bits 15Ð14
TRDYIE
Bit 13
Transmit FIFO Interrupt Trigger LevelÑ These bits determine the number of available registers in UTX required to indicate to the MCU that space is available to write data to be transmitted. When the number of available registers rises above this threshold, the TRDY bit in USR is set and a maskable interrupt can be generated
00 = One FIFO slot (default).
01 = Four FIFO slots.
10 = Eight FIFO slots.
11 = Fourteen FIFO slots.
Transmitter Ready Interrupt EnableÑ Setting this bit enables an interrupt when the space available in UTX reaches the threshold determined by TxFL[1:0].
0 = Interrupt disabled (default).
1 = Interrupt enabled.
TXEN
Bit 12
RXFL[1:0]
Bits 11Ð10
RRDYIE
Bit 9
Note: Either the EUTX bit in the NIER or the
EFUTX bit in the FIER must also be set in order to generate this interrupt (see
Transmitter EnableÑ Setting this bit enables the
UART transmitter. If TXEN is cleared during a transmission, the transmitter is immediately disabled and the TxD pin is pulled high. The UTX cannot be written while TXEN is cleared.
0 = Transmitter disabled (default).
1 = Transmitter enabled.
Receive FIFO Interrupt Trigger LevelÑ These bits determine the number of received characters in URX required to indicate to the MCU that the
URX should be read. When the number of registers containing received data rises above this threshold, the RRDY bit in USR is set and a maskable interrupt can be generated.
00 = One FIFO slot (default).
01 = Four FIFO slots.
10 = Eight FIFO slots.
11 = Fourteen FIFO slots.
Receiver Ready Interrupt EnableÑ Setting this bit enables an interrupt when the number of received characters in UTX reaches the threshold determined by RxFL[1:0].
0 = Interrupt disabled (default).
1 = Interrupt enabled.
Note: Either the EURX bit in the NIER or the
EFURX bit in the FIER must also be set in order to generate this interrupt (see
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UART Registers
Name
RXEN
Bit 8
IREN
Bit 7
TXEIE
Bit 6
Table 11-6. UCR1 Description (Continued)
Description Settings
Receiver EnableÑ Setting this bit enables the
UART transmitter.
Note: The receiver requires a valid one-to-zero transition to accept a valid character, and will not recognize BREAK characters if the RxD line is at a logic low when the receiver is enabled.
0 = Receiver disabled (default).
1 = Receiver enabled.
Infrared Interface EnableÑ Setting this bit enables the IrDA infrared interface, configuring the RxD and TxD pins to operate as described in
0 = Normal NRZ (default).
1 = IrDA.
Transmitter Empty Interrupt EnableÑ Setting this bit enables an interrupt when all data in UTX has been transmitted.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
RTSDIE
Bit 5
Note: Either the EUTX bit in the NIER or the
EFUTX bit in the FIER must also be set in order to generate this interrupt (see
RTS Delta Interrupt EnableÑ Setting this bit enables an interrupt when the RTS pin changes state.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
SNDBRK
Bit 4
DOZE
Bit 1
UEN
Bit 0
Note: Either the EURTS bit in the NIER or the
EFRTS bit in the FIER must also be set in order to generate this interrupt (see
Send BREAKÑ Setting this forces the transmitter to send BREAK characters, effectively pulling the
TxD pin low until SNDBRK is cleared. SNDBRK cannot be set unless TXEN and UEN are both set.
0 = Normal transmission (default).
1 = BREAK characters transmitted.
UART DOZE Mode 0 = UART ignores DOZE mode (default).
1 = UART stops in DOZE mode.
UART EnableÑ This bit must be set to enable the
UART. If UEN is cleared during a transmission, the transmitter stops immediately and pulls TxD to logic one.
0 = UART disabled (default).
1 = UART enabled.
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UART Registers
UCR2
Bit 15 14 13 12
IRTS CTSC CTSD
RESET 0 0 0 0
11
UART Control Register 2
10 9 8 7 6 5 4
PREN PROE STPB CHSZ CLKSRC
0 0 0 0 0 0 0 0
3
0
$0020_4082
2 1 Bit 0
0 0 0
Name
Table 11-7. UCR2 Description
Description Settings
IRTS
Bit 14
CTSC
Bit 13
CTSD
Bit 12
PREN
Bit 8
Ignore RTS PinÑ Setting this bit configures the
UART to ignore the RTS pin, enabling it to transmit at any time. When IRTS is cleared, the
UART must wait for RTS to assert before it can transmit.
0 = RTS qualifies data transmission (default).
1 = RTS ignored.
CTS Pin ControlÑ This bit determines whether hardware or software controls the CTS pin. When
CTSC is set, the receiver controls CTS, automatically deasserting it when URX is full.
When CTSC is cleared, the CTS pin is driven by the CTSD bit.
0 = CTSD bit controls CTS (default).
1 = Receiver control CTS.
0 = CTS driven high (default).
1 = CTS driven low.
CTS DriverÑ This bit drives the CTS pin when
CTSC is cleared. Setting this bit asserts CTS, meaning that it is driven low; clearing CTSD deasserts (pulls high) CTS. When CTSC is set this bit has no effect.
Parity EnableÑ Controls the parity generator in the transmitter and the parity checker in the receiver.
0 = Parity disabled (default).
1 = Parity enabled.
0 = Even parity (default).
1 = Odd parity.
PROE
Bit 7
STPB
Bit 6
CHSZ
Bit 5
CLKSRC
Bit 4
Parity Odd/EvenÑ Determines the functionality of the parity generator and checker. This bit has no effect if PREN is cleared.
Stop BitsÑ Determines the number of stop bits transmitted. The STPB bit has no effect on the receiver, which expects one or more stop bits.
Character SizeÑ Determines the number of character bits transmitted and expected.
Clock SourceÑ Determines the source of the
16x transmit and receive clock. This bit should not be changed during a transmission.
0 = One stop bit (default).
1 = Two stop bits.
0 = 8 character bits (default).
1 = 7 character bits.
0 = CKIH divided by UBRGR (default).
1 = IRQ7/DTR pin.
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UART Registers
UBRGR
Bit 15 14
RESET 0 0
13
0
12
UART Bit Rate Generator Register
11 10 9 8 7 6 5
0 0 0 0 0 0
CD[11:0]
0 0
4
0
Table 11-8. UBRGR Description
Description
3
0
Settings
$0020_4084
2 1 Bit 0
0 0 0
Name
CD[11:0]
Bits 11Ð0
Clock DividerÑ If the CLKSRC bit in UCR2 is cleared, CKIH is divided by a number determined by this field to generate the 16x bit clock. The actual divisor is equal to the value in CD[11:0] plus one, i.e., a value of $000 yields a divisor of 1, and $FFF yields a divisor of 4096.
USR
Bit 15 14 13
TXE RTSS TRDY
RESET 1 0 1
12 11
UART Status Register
10 9 8 7 6
0 0
RRDY
0 0 0 0
5
RTSD
0
4 3
$0020_4086
2 1 Bit 0
0 0 0 0 0
All bits are read-only, and writes have no effect, with the exception of RTSD, which is cleared by writing it with one.
0
Name
TXE
Bit 15
RTSS
Bit 14
TRDY
Bit 13
RRDY
Bit 9
RTSD
Bit 15
Table 11-9. USR Description
Description Settings
Transmitter EmptyÑ Set when all data in UTX
FIFO has been sent. Cleared by a write to UTX.
0 = UTX or transmit buffer contains unsent data
(default).
1 = UTX and transmit buffer empty.
RTS Pin StatusÑ Indicates the current status of the RTS pin. When the USR is read, a ÒsnapshotÓ of the RTS pin is taken immediately before this bit is presented to the data bus.
Transmitter ReadyÑ Set when the number of unsent characters in UTX FIFO falls below the threshold determined by the TxFL bits in UCR1.
Cleared when the MCU writes enough data to fill the UTX above the threshold.
Receiver ReadyÑ Set when the number of characters in URX FIFO exceeds the threshold determined by the RxFL bits in UCR1. Cleared when the MCU reads enough data to bring the number of unread characters in URX below the threshold.
RTS DeltaÑ Set when the RTS pin changes state. Cleared by writing the bit with one.
0 = Number of unsent characters is above the threshold (default).
1 = Number of unsent characters is below the threshold.
0 = Number of unread characters is below the threshold (default).
1 = Number of unread characters is above the threshold.
0 = RTS has not changed state since RTSD was last cleared (default).
1 = RTS has changed state.
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UART Registers
UTS
Bit 15 14 13 12
FRCPERR LOOP
0 0
11
UART Test Register
10 9 8 7 6
0
LOOPIR
0 0 0 0 0
5 4 3
$0020_4088
2 1 Bit 0
RESET 0 0 0 0 0 0 0 0
This register is provided for test purposes and is not intended for use in normal operation.
Table 11-10. UTS Description
Description Name Settings
FRCPERR
Bit 13
LOOP
Bit 12
LOOPIR
Bit 10
Force Parity ErrorÑ If parity is enabled, the transmitter is forced to generate a parity error as long as this bit is set.
Loop Tx and RxÑ Setting this bit connects the receiver to the transmitter. The RxD pin is ignored.
0 = No intentional parity errors generated
(default).
1 = Parity errors generated.
0 = Normal operation (default).
1 = Receiver connected to transmitter.
Loop Tx and Rx for Infrared InterfaceÑ Setting this bit connects the infrared receiver to the infrared transmitter.
0 = Normal IR operation (default).
1 = IR Receiver connected to IR transmitter.
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UART Registers
11.4.2 GPIO Registers
Four of the UART pins can function as GPIO, governed by the following control registers.
UPCR
Bit 15 14 13 12
UART Port Control Register
11 10 9 8 7 6 5
RESET 0 0 0 0 0 0 0 0 0 0 0
Table 11-11. UPCR Description
Description Name
UPC[3:0]
Bits 3Ð0
Pin ConfigurationÑ Each bit determines whether its associated pin functions as UART or
GPIO.
0 = GPIO (default).
1 = UART
4
0
$0020_408A
2 1 Bit 0 3
UPC3
(CTS)
UPC2
(RTS)
UPC1
(TxD)
UPC0
(RxD)
0 0 0 0
Settings
UDDR
Bit 15 14
RESET 0
Name
UDD[3:0]
Bits 3Ð0
13 12
UART Data Direction Register
11 10 9 8 7 6 5 4
0
$0020_408C
2 1 Bit 0 3
UDD3
(CTS)
UDD2
(RTS)
UDD1
(TxD)
UDD0
(RxD)
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 11-12. UDDR Description
Description
UART Data DirectionÑ Each of these bits determines the data direction of the associated pin if it is configured as GPIO.
0 = Input (default).
1 = Output.
Settings
UPDR
Bit 15 14
RESET 0
Name
UPD[3:0]
Bits 3Ð0
0
13
0
12
0
11
0
UART Port Data Register
10
0
9
0
8
0
7
0
6
0
5
0
4
0
$0020_408E
2 1 Bit 0 3
UPD3
(CTS)
UPD2
(RTS)
UPD1
(TxD)
UPD0
(RxD)
Ñ Ñ Ñ Ñ
Table 11-13. UPDR Description
Description
UART Port GPIO Data [3:0]Ñ Each of these bits contains data for the corresponding UART pin if it is configured as GPIO. Writes to UPDR are stored in an internal latch, and driven on any port pin configured as an output. Reads of this register return the value sensed on input pins and the latched data driven on outputs
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Chapter 12
Smart Card Port
The Smart Card Port (SCP) is a serial communication channel designed to obtain user information such as identification. It is a customized UART with additional features for the SCP interface, as specified by ISO 7816-3 and GSM 11.11. Typically, a DSP56652 application uses this port to obtain subscriber information, and a smart card containing
this information is referred to as a Subscriber Interface Module (SIM). Figure 12-1
presents a block diagram of the SCP.
SCP Clock, Transmitter, Receiver
SMTX
SMRX
SMER
SCP
Interrupt
Control
SIM_CLK
SCDPE
Port Interface and
Auto Power Down Logic
(internal) (internal)
SMPC
(internal)
SIMDATA SIMCLK
Data Clock
SENSE PWR_EN
Power Switch
SIMRESET
Sense
Smart Card
V
CC
Reset
Figure 12-1. Smart Card Port Interface
Systems that do not require the SCP can configure the port as GPIO.
12.1 SCP Architecture
This section gives an overview of the SCP pins, data communication, and auto power-down circuitry.
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SCP Architecture
12.1.1 SCP Pins
The SCP provides the following five pins to connect to a smart card:
¥ SIMDATA Ñ a bidirectional pin on which transmit and receive data are multiplexed.
¥ SIMCLK Ñ an output providing the clock signal to the smart card.
¥ SENSE Ñ an input indicating if a smart card is inserted in the interface.
¥ SIMRESET Ñ an output that resets the smart card logic.
¥ PWR_EN Ñ an output that enables an external power supply for the smart card.
The five pins can function as GPIO if the SCP function is not required. Because SCP operation requires all five pins, they cannot be configured for GPIO individually.
12.1.2 Data Communication
The SCP contains a quad-buffered receiver FIFO and a double-buffered transmitter. A single register serves both as a write buffer for transmitted data and a read buffer for received data. Reading the register clears an entry in the receive FIFO, and writing the register enters a new character to be transmitted. Three flags and optional interrupts are provided for FIFO not empty, FIFO, full, and FIFO overflow. The transmitter provides two flags and optional interrupts for character transmitted and TX buffer empty.
The SCP employs an asynchronous serial protocol containing one start bit, eight data bits, a parity bit and two stop bits. The polarity of the parity bit can established either by programming a register or, in the initial Character mode, by hardware at the beginning of each communication session. Both the card and the port can indicate receiving a corrupted frame (no stop bit) by issuing a NACK signal (pulling the SIMDATA pin low during the stop bit period). The SCP can also issue a NACK to the card when its receive buffer overflows to avoid losing further data, when it receives incorrect parity, and when it receives incorrect protocol data in Initial Character mode. Flags and optional interrupts are provided for the three NACK signals. The receiver also has flags and optional interrupts to indicate parity error, frame error, and receiver overrun.
The SCP generates a primary data clock, SIM_CLK, which is further divided to generate the bit rate. SIM_CLK also drives the SIMCLK pin, which can be synchronously pulled low by software.
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SCP Operation
12.1.3 Power Up/Down
A transition on the SENSE pin triggers both power up and power down sequences. Power up is done under software control, while power down can be controlled either by software or hardware.
12.2 SCP Operation
This section describes SCP activation and deactivation, clock generation, data transactions, and low power mode operation. A summary of the various SCP interrupts is also provided.
12.2.1 Activation/Deactivation Control
The smart card power up and power down sequences are specified in ISO 7816-3 and
GSM 11.11. The signals and control bits provided by the DSP56652 to implement these
sequences are illustrated in Figure 12-2 and described below.
Edge
Detector
SMSC
Set
Clear
Interrupt
Flipflop
Level Detect
SMSCIE
SENSE
SMPC
Interrupt
SIM_CLK
SCCLK_CLR
SCDPE_CLR
SCCLK
Clock
Enable
SIMCLK
MCU_CLK
APDE
SCP Automatic
Power Down
Logic
SCRS_CLR
SCDPE
SCRS
SIMDATA
SIMRESET
SCPE_CLR
SCPE
PWR_EN
SCP Control Bits
Figure 12-2. SCP: Port Interface and Auto Power Down Logic
When the port is enabled, the SENSE input detects insertion and removal of the smart card, initiating SCP activation and deactivation. Inserting the card pulls the SENSE pin low, and removing the card pulls the pin high. The SENSE pin state is reflected in the
SCSP bit in the SCP Status Register (SCPSR). A rising or falling edge on the SENSE pin sets the SMSC flag in the SCPSR, and can generate an interrupt if the SMSCIE bit in the
SCP Interrupt Enable Register (SCPIER) is set.
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SCP Operation
The power up sequence specified in ISO 7816 is implemented by the DSP56652 as follows:
1. The SIMRESET pin is asserted (pulled low) by clearing the SCRS bit in the Smart
Card Activation Control. Register (SCACR).
2. The smart card is powered up. The SCPE bit in the SCACR can be set to turn on an external power supply for the card.
3. The SIMDATA pin is put in the reception mode (tri-stated) by setting the SCDPE bit in the SCACR.
4. The SCP drives a stable, glitch-free clock (SIM_CLK) on the SIMCLK pin by setting the SCCLK bit in the SCACR.
5. SIMRESET is deasserted by clearing the SCSR bit.
The power down sequence specified in ISO 7816 is implemented by the DSP56652 as follows:
1. SIMRESET is asserted by setting the SCRS bit.
2. SIMCLK is turned off (pulled low) by clearing the SCCLK bit.
3. SIMDATA transitions from tristate to low by clearing the SCDPE bit.
4. SIM V
CC
is powered off. The SCPE bit is cleared if it was used to activate an external power supply.
The power down sequence can be performed in hardware by setting the APDE bit in the
SCACR. The deactivation sequence is initiated by a rising edge on the SENSE pin so that the sequence can be completed before the card has moved far enough to lose connections with the contacts. The SCACR control bits in the above power down sequence are adjusted automatically.
12.2.2 Clock Generation
SCP clock operation is illustrated in Figure 12-3 on page 12-5. The SCP generates its
primary data clock, SIM_CLK, by dividing CKIH by four or five, depending on the state of the CKSEL bit in the Smart Card Port Control Register (SCPCR). To determine the bit rate, SIM_CLK is further divided by 372 (normal mode) or 64 (speed enhancement mode), controlled by the SIBR bit in the SCPCR.
SIM_CLK is also gated to the smart card through the SIMCLK pin. The pin can be pulled low to save power by clearing the SCCLK bit in the SCACR.
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SCP Operation
12.2.3 Data Transactions
This section describes the SCP data format, reception, and transmission. A summary of
NACK timing is also included. Data paths are shown in Figure 12-3.
100K
(internal)
RXDS
Data
Recovery
11-Bit RX
Shift Register
H P 7 6 5 4 3 2 1 0 L
RX Enable
(Low Power)
NACK Gen Par. Check
ICM Detect
RX FIFO(4)
TX Enable
(Low Power)
Transmitter
Control Logic
CKIH
Ö 4 or
Ö 5
SIM_CLK
Ö 64
Ö 372
Baud
Generator
CKSEL
SIBR
TX Buffer
Parity
Generator
11-Bit TX
Shift Register
H P 7 6 5 4 3 2 1 0 L
Figure 12-3. SCP: Clocks and Data
SCDPE
SCCLK
TXDS
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SCP Operation
12.2.3.1 Data Format
The SCP data format and protocol are compatible with ISO 7816. The data format is fixed at one start bit, eight data bits, one parity bit, and two stop bits. Either receiver can overlay a NACK during the stop bit period to indicate an error by pulling the SIMDATA pin low.
The SCP generates the NACK in hardware to save software overhead.
Odd/even parity is determined by the SCPT bit in the SCPCR. This bit can be explicitly written or adjusted automatically by the first smart card transmission after the card is inserted. In the latter mode, referred to as the initial character mode, the first character sent by the smart card is either $03 to indicate odd parity, or $3B to indicate even parity, and the parity bit in the frame is set. The initial character mode is selected by setting the SCIC bit in the SCPCR.
12.2.3.2 SIMDATA Pin
The SIMDATA pin serves as both transmitter and receiver for the SCP. The transmitter and receiver are enabled by the SCTE and SCRE pins respectively in the SCPCR. To avoid contention on the pin, only one of these bits should be set at a given time. If both bits are cleared, the clock input to the baud generator is disabled. The first transaction after the smart card is inserted is always from card to SCP, so it is recommended that SCRE be set and SCTE cleared as part of initialization and after the card is removed.
12.2.3.3 Data Reception
When the smart card is inserted and the power up sequence is complete, the SCP puts the
SIMDATA pin in tristate mode to receive the first transmission from the card. The pin is initially at a logic one. If the pin goes to a logic low, and the receiver detects a qualified start bit, it proceeds to decode the succeeding transitions on the SIMDATA pin, monitoring for eight data bits, two stop bits, and correct parity. When a complete character is decoded, the data is written to the next available space in the four-character receive
FIFO. The MCU reads the data at the top of the FIFO by reading the SCP Data Register
(SCPDR), and the FIFO location is cleared.
Two receive conditions can be flagged in the SCPSR:
1. If the FIFO is empty when the first character is received, the SCFN bit is set. An interrupt is generated if the SCFNIE bit in the SCPIER is set.
2. If the received character fills the FIFO, the SCFF bit is set. An interrupt is generated if the SCFFIE bit in the SCPIER is set.
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SCP Operation
Three receive error conditions can also be flagged in the SCPSR:
1. A parity error is flagged by setting the SCPE bit. If the NKPE bit in the SCPCR is set, a NACK is sent to the smart card.
2. A frame error is flagged if the stop bit is not received by setting the SCFE bit.
3. If the FIFO is full when another character is received, the SCOE flag is set to indicate an overrun. If the NKOVR bit in the SCPCR is set, a NACK is sent to the smart card. The new character is not transferred to the FIFO and is overwritten if another character is received before the FIFO is read.
Any of the three error conditions generates an interrupt if the SCREIE bit in the SCPIER is set.
12.2.3.4 Data Transmission
To send a character, the MCU should clear the SCRE bit and set the SCTE bit to enable transmission. The MCU then writes to the SCPDR, the data is stored in a transmit buffer, and the SCP transmits the data to the card over the SIMDATA pin. The SCP outputs a start bit, eight character bits (least significant bit first), a parity bit, and two stop bits. If the smart card detects a parity error in the transmission it sends a NACK back to the SCP, the
SCP alerts the MCU of the failure by setting the TXNK bit in the SCPSR, and the MCU must retry the transmission by writing the same data to SCPDR. When a frame has been transmitted, the transmit buffer is cleared and the SCTC flag in the SCPSR is set; if the
SCTCIE bit in the SCPIER has been set, an interrupt is generated. Although a transmission in progress will complete if the transmitter is disabled, it is recommended that software waits until SCTC is set before clearing the SCTE bit.
12.2.3.5 NACK Timing
The following is a summary of the timing for NACK signals as specified in ISO 7816. The unit of time used by the specification is the Elementary Time Unit, or etu, which is defined as one bit time.
A NACK pulse is generated at 10.5 etuÕs after the start bit. The width of the NACK pulse is 1 to 2 etuÕs. The NACK should be sampled at 11 etuÕs after the start bit. If a NACK pulse is received, the character should be retransmitted a minimum of 2 etuÕs after the detection of the error. The start of the repeated character should be a minimum of 2 etuÕs
after the detection of the error bit. Figure 12-4 shows timing of the data format.
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SCP Operation
12 etu min
Start
LSB
Without parity error
Byte i
MSB
P Guard Start period
Even Parity Bit
Byte i + 1
Start
11 etu
Byte i
NACK sample time
2 min
P
Error
Signal
Start
Retransmission
Byte i
With parity error
10.5 etu
NACK: 1 min, 2 max etuÕs
(Z) A Z Z A Z Z Z
A A A
A A (Z)
Initial Character from SCP etu = Elementary Time Unit
Figure 12-4. SCP Data Formats
12.2.4 Low Power Modes
If the DOZE bit in the SCPCR register is set when the MCU enters DOZE mode, the SCP completes the current transmit/receive transaction, then gates off the receive and transmit clocks. However, the clocks to the Automatic Power Down and the SENSE debouncer circuits remain enabled to allow the SCP to initiate an automatic power down if the smart card is removed during DOZE mode. All state machines and registers retain their current values. When exiting DOZE mode the SCP reenables all its clocks, and resumes operation with its previously retained state. If the DOZE bit in the SCPCR is cleared, the SCP continues full operation in DOZE mode.
When the MCU enters STOP mode, the SCP gates off the CKIH clock and freezes all state machines and registers. Software must complete all transmit/receive transactions and power down the SCP before entering STOP mode. When exiting the Stop mode, the SCP reenables all its clocks, and resumes operation with its previously retained state.
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SCP Operation
12.2.5 Interrupts
The SCP generates two interrupts to the MCU:
¥ SMPC is generated when the smart card position is changed (i.e., inserted or removed).
¥ SCP indicates all other SCP interrupt conditions generated by transmission, reception and errors. Error interrupts have priority over transmit and receive interrupts. Receive interrupts are not cleared until the SCPDR is read.
Figure 12-5 illustrates the sources and conditions that generate the various SCP interrupts.
Parity Error
Frame Error
Overrun
Transmit Complete
Rx FIFO Not Empty
Rx FIFO Full
SMSC
SMSCIE
SCPE
SCFE
SCOE
SCREIE
SCTC
SCTCIE
Tx
SCFN
SCFNIE
SCFF
SCFFIE
Rx
Figure 12-5. SCP Interrupts
Error
SMPC
Interrupt
SCP
Interrupt
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SCP Registers
12.3 SCP Registers
Table 12-1 is a summary of the SCP control and GPIO registers, including the acronym,
bit names, and address (least-significant halfword) of each register. The most-significant halfword of all register addresses is $0020.
Table 12-1. SCP Register Summary
SCPCR 15 14 13 12 11 10
$B000
9 8 7 6 5 4 3 2 1 0
CKSEL NKOVR DOZE SIBR SCSRSCPTSCIC NKPE SCTESCRE
SCACR 15 14 13 12 11 10 9 8 7 6 5
$B002
4 3 2 1 0
SCCLK SCRS SCDPE SCPE APDE
SCPIER 15 14 13 12 11 10 9 8 7 6 5
$B004
4 3 2 1 0
SCTCIE SCFNIE SCFFIE SCREIE SMSCIE
SCPSR 15 14 13 12 11 10 9
$B006
8 7 6 5 4 3 2 1 0
SCFF SCFN SCTY SCTC TXNK SCPE SCFE SCOE SMSC SCSP
SCPDR
$B008
15 14 13 12 11 10 9 8 7 6 5 4 3
SCPD[7:0]
2 1 0
SCPPCR 15 14 13 12 11 10 9
$B00A SMEN
8 7
PDIR[4:0]
6 5 4 3 2
PDAT[4:0]
1 0
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SCP Registers
12.3.1 SCP Control Registers
Name
CKSEL
Bit 9
NKOVR
Bit 8
DOZE
Bit 7
SIBR
Bit 6
SCSR
Bit 5
SCPCR
SCPT
Bit 4
SCIC
Bit 3
NKPE
Bit 2
SCTE
Bit 1
SCRE
Bit 0
Bit 15 14
RESET 0 0
13
0
12
0
11
SCP Control Register
10 9 8 7 6 5 4 3
$0020_B000
2 1 Bit 0
CKSEL NKOVR DOZE SIBR SCSR SCPT SCIC NKPE SCTE SCRE
0 0 0 0 0 0 0 0 0 0 0 0
Table 12-2. SCPCR Description
Description Settings
Clock SelectÑ Determines if the CKIH divisor that generates SIM_CLK is 4 or 5.
NACK on Receiver OverrunÑ Enables overrun checking and reporting.
DOZE ModeÑ Controls SCP operation in DOZE mode.
SIM Baud RateÑ Determines the SIM_CLK divisor to generate the SIM baud clock.
0 = CKIH divided by 5 (default).
1 = CKIH divided by 4.
0 = NACK not generated
1 = NACK is generated on overrun error.
0 = SCP ignores DOZE mode (default).
1 = SCP stops in DOZE mode.
0 = Baud rate = SIM_CLK Ö 372 (default).
1 = Baud rate = SIM_CLK Ö 64.
SCP System ResetÑ Setting this bit resets the SCPSR and state machines. Other registers are not affected. If the SCSR bit is set while a character is being sent or received, the transmission is completed before reset occurs.
SCP Parity TypeÑ Selects odd or even parity. In initial character mode, hardware adjusts this bit automatically
0 = Even parity (default).
1 = Odd parity.
SCP Initial Character ModeÑ Setting this bit implements initial character mode, in which parity is determined by the first character sent by the
card after it is inserted (see page 12-6).
0 = Parity determined by writing SCPT bit
(default).
1 = Parity determined by initial character from card.
NACK on Parity ErrorÑ Determines if a NACK signal is sent (SIMDATA pin pulled low) if a parity error is detected. This affects both the SCP and the smart card.
0 = No NACK sent (default).
1 = NACK sent on parity error.
SCP Transmit EnableÑ Setting this bit allows data written to the transmit buffer to be loaded to the transmit shift register and shifted out on the
SIMDATA pin. A transmission in progress when
SCTE is cleared is completed before the transmitter is disabled.
0 = Disabled (default).
1 = Enabled.
SCP Receive EnableÑ Setting this bit allows data received on the SIMDATA pin to be shifted into the receive shift register and loaded to the receive FIFO. A reception in progress when
SCRE is cleared is completed before the receiver is disabled.
0 = Disabled (default).
1 = Enabled.
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SCP Registers
SCACR
Name
SCCLK
Bit 4
SCRS
Bit 3
SCPE
Bit 1
APDE
Bit 0
Bit 15 14
RESET 0
SCDPE
Bit 2
0
13
0
Smart Card Activation Control Register
12 11 10 9 8 7 6 5 4 3
$0020_B002
2 1 Bit 0
SCCLK SCRS SCDPE SCPE APDE
0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-3. SCACR Description
Description Settings
Smart Card ClockÑ Setting this bit drives
SIM_CLK to the smart card on the SIMCLK pin.
Cleared by software or automatically after the card is removed if the APDE bit is set.
0 = SIMCLK pulled low (default).
1 = SIMCLK driven by the SIM_CLK signal.
Smart Card ResetÑ This bit drives the
SIMRESET pin. It is controlled automatically after the card is removed if the APDE bit is set.
0 = SIMRESET pulled low (default).
1 = SIMRESET driven high.
Smart Card Data Pin EnableÑ Setting this bit allows the SIMDATA pin to function as a receiver or transmitter. It is cleared automatically after the card is removed if the APDE bit is set.
0 = SIMDATA pulled low (default).
1 = SIMDATA functions as SCP transmit or receive pin.
Smart Card Power EnableÑ This bit drives the
PWR_EN pin, which can switch on an external power supply to power the smart card. It is cleared automatically after the card is removed if the APDE bit is set.
0 = PWR_EN pulled low (default).
1 = PWR_EN driven high.
Auto Power Down EnableÑ Setting this bit allows hardware to control the SCP pins to perform the power down sequence automatically after the smart card is removed.
0 = Software performs power down sequence
(default).
1 = Hardware automatically performs power down sequence.
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SCP Registers
SCPIER
Bit 15 14 13 12
SCP Interrupt Enable Register
11 10 9 8 7 6 5 4 3 2
$0020_B004
1 Bit 0
SCTCIE SCFNIE SCFFIE SCREIE SMSCIE
0 0 0 0 0 0 0 0 0 0 0 0 RESET 0 0 0 0
Note: In addition to the individual interrupt enable bits in the SCPIER, the following
bits must also be set in order to generate the respective interrupts (see page 7-7):
SIM Sense ChangeÑeither ESMPD in the NIER or EFSMPD in the FIER
All other interruptsÑeither ESCP in the NIER or EFSCP in the FIER.
Name
SCTCIE
Bit 4
SCFNIE
Bit 3
SCFFIE
Bit 2
SCREIE
Bit 1
SMSCIE
Bit 0
Table 12-4. SCPIER Description
Description Settings
SCP Transmit Complete Interrupt EnableÑ Allows an interrupt to be generated when the SCTC bit in the SCPSR is set.
SCP Receive FIFO Not Empty Interrupt EnableÑ Allows an interrupt to be generated when the SCFN bit in the SCPSR is set.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
SCP Receive FIFO Full Interrupt EnableÑ Allows an interrupt to be generated when the SCFF bit in the SCPSR is set.
SCP Receive Error Interrupt EnableÑ Allows an interrupt to be generated when the SCPE, SCFE, or SCOE bit in the SCPSR is set.
SIM SENSE Change Interrupt EnableÑ Allows an interrupt to be generated when the SMSC bit in the SCPSR is set.
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SCP Registers
SCPSR
Name
SCFF
Bit 9
SCFN
Bit 8
SCTY
Bit 7
SCTC
Bit 6
TXNK
Bit 5
SCPE
Bit 4
SCFE
Bit 3
SCOE
Bit 2
Bit 15 14
RESET 0 0
13
0
12
0
11
0
SCP Status Register
10 9 8 7 6 5 4 3
$0020_B006
2 1 Bit 0
SCFF SCFN SCTY SCTC TXNK SCPE SCFE SCOE SMSC SCSP
0 0 0 1 1 0 0 0 0 0 Ñ
Table 12-5. SCPSR Description
Type
1 Description Settings
R/RDC SCP Receive FIFO FullÑ Set when all four receive FIFO characters are filled. Cleared by reading the SCPDR.
0 = FIFO can receive more data (default).
1 = FIFO full.
R/RDC SCP Receive FIFO Not EmptyÑ Set when the FIFO contains at least one character.
Cleared by reading the SCPDR.
0 = FIFO empty (default).
1 = FIFO not empty.
R/WDC SCP Transmit Register EmptyÑ Set when the transmit data register is empty, signalling the MCU that a character can be written to
SCPDR. Cleared by reading the SCPDR.
Normally, the MCU uses the SCTC bit rather than SCTY to determine when the next character can be sent.
R/WDC SCP Transmit CompleteÑ Set after transmitting the second stop bit of a frame
(one additional bit time later if a NACK is received). Cleared by writing the SCPDR.
0 = Transmit register not empty.
1 = Transmit register empty (default).
0 = Next transmission not complete.
1 = Transmission complete (default).
R/WDC NACK Received for Transmitted WordÑ
Set when a NACK is detected while transmitting a character. Cleared by writing the SCPDR or by hardware reset. TXNK is set simultaneously with SCTC.
0 = No NACK (default).
1 = NACK received.
R/1C
R/1C
R/1C
SCP Parity ErrorÑ Set when an incorrect parity bit has been detected in a received character. Cleared by writing with 1.
0 = No parity error (default).
1 = Parity error detected.
SCP Frame ErrorÑ Set when an expected stop bit in a received frame is sampled as a 0.
Cleared by writing with 1.
0 = No frame error (default).
1 = Frame error detected.
SCP Overrun ErrorÑ Set when a new character has been shifted in to the receive buffer and the RX FIFO is full. Cleared by writing with 1.
0 = No overrun error (default).
1 = Overrun error detected.
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SCP Registers
Table 12-5. SCPSR Description (Continued)
Name Type
1 Description Settings
SMSC
Bit 1
R/1C SIM Sense ChangeÑ Set simultaneously with the SMPC interrupt when the smart card
(SIM) is inserted or removed, generating a falling or rising edge on the SENSE pin.
Cleared by writing with 1.
0 = No change on SENSE pin (default).
1 = Edge on SENSE pin detected.
SCSP
Bit 0
R SCP SENSE PinÑ Reflects the current state of the SCP SENSE pin.
1.
R = Read only
R/RDC = Read/Read SCPDR to clear
R/WDC = Read/Write SCPDR to clear
R/1C = Read; write with 1 to clear (write with 0 ignored).
SCPDR
Bit 15 14
RESET 0
Name
SCPD[7:0]
Bits 7Ð0
0
13
0
SCP Data Register
10 9 8 7 6 12
0
11 5
0 0 0 0 Ñ Ñ Ñ
Table 12-6. SCPDR Description
4 3
SCPD[7:0]
Ñ Ñ
$0020_B008
2
Ñ
1
Ñ
Bit 0
Ñ
Description
SCP Data BufferÑ This field is used both to transmit and receive SCP data. Writing to the SCPDR enters a new character in the transmit buffer; reading the SCPDR register reads the character at the top of the RX FIFO.
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SCP Registers
12.3.2 GPIO
The five SCP pins can function as GPIO. GPIO functions are governed by the SCPPCR register. The data direction and port GPIO data fields correspond to the SCP pins as
Table 12-7. SCP Pin GPIO Bit Assignments
GPIO Bit #
9, 4
8, 3
7, 2
6, 1
5, 0
SCP Pin
PWR_EN
SIMRESET
SIMDATA
SENSE
SIMCLK
SCPPCR
Bit 15 14
SMEN
RESET 0 0
Name
SMEN
Bit 15
SCPDD[4:0]
Bits 9Ð5
SCPPD[4:0]
Bits 4Ð0
13
0
12
0
11
SCP Port Control Register
10 9 8 7 6 5
0 0 0 0
SCPDD[4:0]
0 0 0
Table 12-8. SCPPCR Description
4
Ñ
3
$0020_B00A
2 1
Ñ
SCPPD[4:0]
Ñ Ñ
Bit 0
Ñ
Description Settings
SCP Port EnableÑ Determines if all five smart card pins function as SCP pins or GPIO.
SCP Data DirectionÑ Each of these bits determines the data direction of the associated pin if it is configured as GPIO.
0 = GPIO (default).
1 = SCP.
0 = Input (default).
1 = Output.
SCP Port GPIO Data [4:0]Ñ Each of these bits contains data for the corresponding SCP pin if it is configured as GPIO. Writes to these bits are stored in an internal latch, and driven on any port pin configured as an output. Reads of these bits return the value sensed on input pins and the latched data driven on outputs
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Chapter 13
Keypad Port
The keypad port (KP) is a 16-bit peripheral designed to ease the software burden of scanning a keypad matrix. It works with any sized matrix up to eight rows by eight columns. With appropriate software support, keypad logic can detect, debounce, and decode one or two keys pressed simultaneously. A key press generates an interrupt that can bring the MCU out of low power modes.
The KP is designed for a keypad matrix that shorts intersecting row and column lines when a key is depressed. It is not intended for use with other switch configurations.
13.1 Keypad Operation
This section describes KP pin configuration, software polling required to determine a
valid keypress, low power operation, and noise suppression circuitry. Figure 13-1 is a
block diagram of the keypad port.
Data
KDR(15:8) pull-up/Data Direction
Control
KDDR(15:8)
KPCR(15:8)
Open Drain/Totem Pole
Controls
Column
Pins
Row
Pins
Status
KPSR
Keypad Matrix
Up To 8 ´ 8
Noise
Filter To Interrupt
Controller
Data
KDDR[7:0] pull-up/Data Direction
Control
Row Enable
Control
Figure 13-1. Keypad Port Block Diagram
CKIL
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Keypad Operation
13.1.1 Pin Configuration
The KP provides 16 pins to support any keypad configuration up to eight rows and eight columns. Five of these pins, ROW7ÐROW 5 and COL7ÐCOL6, are multiplexed with other functions and require specific settings in the General-Purpose Configuration
Register for keypad operation. (Refer to Table 4-13 on page 4-18.) Any pins not used for
the keypad are available as GPIO pins.
13.1.1.1 Column Pins
Each column pin intended for keypad operation must be configured as an output by setting the corresponding KCD bit in the Keypad Port Data Direction Register (KDDR), and for keypad rather than GPIO operation by setting the corresponding KCO bit in the Keypad
Port Control Register (KPCR). Column pins configured for keypad operation are open drain with on-board pull-up resistors; column pins configured as GPIO outputs have totem pole drivers with the pull-up resistors disabled. These configurations are summarized in
Table 13-1. Keypad Port pull-up Resistor Control
KDDR[15:8]
0
1
1
KPCR[15:8] x
0
1
Pin Function
Input
OutputÑtotem pole
OutputÑopen drain pull-up Resistors
Enabled
Disabled
Enabled
13.1.1.2 Row Pins
Row pins intended for keypad operation must be configured as inputs by clearing the corresponding KRD bits in the KDDR, and for keypad operation (rather than GPIO) by setting the corresponding KRE bits in the KPCR. When pulled low, each row pin configured for keypad operation sets the KPKD bit in the Keypad Status Register (KPSR) and generates an interrupt. Row pins configured as GPIO do not set the status flag or generate an interrupt when they are pulled low. The KPKD bit is cleared by reading the
KPSR, then writing the KPKD bit with 1.
A discrete switch can be connected to any row input pin that is not part of the keypad matrix. The second terminal of the discrete switch is connected to ground. If the pin is configured as an input and for keypad operation, hardware detects closure of the switch and generates an interrupt if the corresponding row pin is configured for keypad operation.
Care should be taken not to configure a row pin for both KP operation and as an output. In this configuration a keypad interrupt is generated if the associated data bit in the Keypad
Data Register (KPDR) is written with zero, pulling the pin low.
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Keypad Operation
13.1.2 Keypad Matrix Polling
The keypad interrupt service routine typically includes a keypad polling loop to determine which key is pressed. This loop walks a 0 across each of the keypad columns by clearing the corresponding KCO bit, and reads the row values in the KPDR at each step. The process is repeated several times in succession, and the results of each pass compared with those from the previous pass. When several consecutive scans yield the same key closures, a valid key press has been detected. Software can then determine which switch is pressed and pass the value up to the next higher software layer.
13.1.3 Standby and Low Power Operation
The keypad does not require software intervention until a keypress is detected. Software can put the keypad in a standby state between keypresses to conserve power by clearing the KCO bits in the KPCR. Clearing the KCO bits turns off the open-drain mode in the corresponding column outputs, converting them to totem pole drivers, and disconnects the pull-up resistors, reducing standby current. The outputs are forced low by clearing the corresponding bits in the KPDR. Row inputs are left enabled. The MCU can then attend to other tasks or enter a low power mode.
The keypad port interrupts the MCU when a key is pressed, waking it up if it is in a low power mode. The MCU re-enables the open drain drivers, sets all the column strobes high, and runs the keypad polling routine to determine which key is pressed. Care should be taken to enable the open drain drivers before driving the columns high to avoid shorting power to ground through two or more switches.
13.1.4 Noise Suppression on Keypad Inputs
The noise suppression circuit illustrated in Figure 13-2 qualifies keypad closure signals to
prevent false keypad interrupts. The circuit is a four-state synchronizer driven by CKIL. A
KP interrupt is not generated until all four synchronizer stages have latched a valid key assertion, effectively filtering out any noise less than four clock cycles in duration. The interrupt signal is an S-R latch output that remains asserted until cleared by software.
Once cleared, the interrupt and its reflection in the KPSR cannot be set again until a period of no key closure is detected. In this way, the hardware prevents multiple interrupts for the same key press with no software intervention.
Because the keypad interrupt signal is driven by the noise suppression circuit, CKIL must remain powered in low power modes for which the keypad is a wake-up source.
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Keypad Port Registers
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Keypad
Matrix
NAND
D Q
FF
D Q
FF
D Q
FF
D Q
FF
CKIL
S
R Clear Status Flag
Figure 13-2. Glitch Suppressor Functional Diagram
To Interrupt
Controller
13.2 Keypad Port Registers
Table 13-2 is a summary of the KP control and GPIO registers, including the acronym, bit
names, and address (least-significant halfword) of each register. The most-significant halfword of all register addresses is $0020. All registers except KPSR are byte-addressable, with column bits in the most significant byte, and row bits in the least significant byte.
Table 13-2. Keypad Port Register Summary
KPCR 15 14 13 12 11 10 9
$A000 KCO[7:0]
8 7 6 5 4 3
KRE[7:0]
8 7 6 KPSR 15 14 13 12 11 10 9
$A002
KDDR 15 14 13 12 11 10 9
$A004 KCDD[7:0]
KPDR 15 14 13 12 11 10 9
$A006 KCD[7:0]
8
8
7
7
6
6
2 1 0
5 4 3 2
5 4 3
KRDD[7:0]
2
1 0
KPKD
1 0
5 4 3
KRD[7:0]
2 1 0
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Keypad Port Registers
KPCR
Bit 15 14
RESET 0
Name
KCO[7:0]
Bits 15Ð8
KRE[7:0]
Bits 7Ð0
0
13
0
12
Keypad Port Control Register
11
KCO[7:0]
10 9 8 7 6 5
0 0 0 0 0 0 0 0
Table 13-3. KPCR Description
Description
4 3
KRE[7:0]
0 0
$0020_A000
2
0
1
0
Settings
Keypad Column Strobe Open Drain
EnableÑ Each bit determines if the corresponding pin functions as a keypad column pin (strobe operationÑopen-drain output in normal operation, totem pole output in low power and standby modes) or GPIO (totem pole output only).
0 = GPIO (default).
1 = KPÑopen-drain output in normal operation.
Keypad Row Interrupt EnableÑ Each bit determines if the corresponding row pin functions as KP (generates an interrupt if pulled low) or GPIO
(no interrupt).
0 = GPIOÑinterrupt disabled (default).
1 = KPÑinterrupt enabled.
Bit 0
0
Note: Either the EKPD bit in the NIER or the
EFKPD bit in the FIER must also be set in order to generate the keypad interrupts
KPSR
Bit 15 14 13 12 11
Keypad Status Register
10 9 8 7 6 5 4 3
$0020_A002
2 1 Bit 0
0 0
KPKD
0 RESET 0 0 0 0 0 0 0 0 0 0 0
Table 13-4. Generic Description
Description Name Type
1
KPKD
Bit 0
R/1C Keypad Keypress DetectÑ This bit reflects the keypad interrupt status. It is set when a valid key closure has been detected, and cleared by reading the KPSR, then writing
KPKD with 1.
1.
R/1C = Read, or write with 1 to clear (write with 0 ignored).
0 0
Settings
0 = No valid keypress detected (default).
1 = Valid keypress detected.
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Keypad Port Registers
KDDR
Bit 15 14
RESET 0 0
13
0
12
Keypad Data Direction Register
11
KCDD[7:0]
10 9 8 7 6 5
0 0 0 0 0 0 0 0
Table 13-5. KDDR Description
Description
4 3
KRDD[7:0]
0 0
Name
KCDD[7:0]
Bits 15Ð8
Keypad Column Pin Data Direction
KRDD[7:0]
Bits 7Ð0
Keypad Row Pin Data Direction
Each of these bits determines the data direction of the associated pin. Valid data should be written to the KPDR before any of these bits are configured as outputs.
0 = Input (default).
1 = Output
Settings
$0020_A004
2 1 Bit 0
0 0 0
KPDR
Bit 15 14
RESET Ñ
Name
KCD[7:0]
Bits 15Ð8
KRD[7:0]
Bits 7Ð0
Ñ
13
Ñ
12
KCD[7:0]
Keypad Port Data Register
11 10 9 8 7 6 5
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Table 13-6. KPDR Description
Description
Keypad Column Data
Keypad Row Data
4 3
KRD[7:0]
Ñ Ñ
$0020_A006
2
Ñ
1
Ñ
Bit 0
Ñ
Each of these bits contains data for the corresponding keypad pin.
Writes to KPDR are stored in an internal latch, and driven on any port pin configured as an output. Reads of this register return the value sensed on input pins and the latched data driven on outputs.
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Chapter 14
Serial Audio and Baseband Ports
The Serial Audio Port (SAP) and the Baseband Port (BBP) are both DSP peripherals based on the synchronous serial interface (SSI) included in several other Motorola DSP devices. Each port supports full-duplex serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola SSI. Features common to both the SAP and the BBP include the following:
¥ Independent transmit and receive sections that can operate with separate
(asynchronous) or shared (synchronous) internal/external clocks and frame syncs
¥ TDM operation with either one slot per frame (normal mode) or up to 32 time slots per frame (network mode).
¥ Programmable word length (8, 12, or 16 bits).
¥ Program options for frame synchronization and clock generation
Features unique to one port include the following:
¥ The SAP contains a bit rate multiplier (BRM) to convert a 16.8 MHz input to a
16.834 MHz clock that can generate standard codec clock rates.
¥ The SAP includes a general-purpose timer.
¥ The BBP contains transmit and receive frame counters.
In addition, any or all of the pins in each port can be configured as GPIO.
Figure 14-1 and Figure 14-2 are block diagrams of the SAP and BBP respectively.
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CKIH
DSP_CLK
BRM
BRM_CLK
BRM MUX
SAPCRA
GDB
SAPCRB
SAPCRC
SAPTSR
SAPSR
SAPML
SAPCNT
RCLK
RX Shift Register
SAPRX
SRDA
STDA
TCLK
TX Shift Register
SAPTX
Interrupts
BRGCLK
DSP_CLK
Clock/Frame Sync Generators, Bit Rate Multiplier,
Control Logic, and Port Control
Figure 14-1. SAP Block Diagram
BBPCRA
BBPCRB
BBPCRC
BBPTSR
BBPSR
GDB
SC0A
SC1A
SC2A
SCKA
BBPRMR
RX Counter
BBPTMR
TX Counter
RCLK
RX Shift Register
BBPRX
SRDB
STDB
TCLK
TX Shift Register
BBPTX
Interrupts
Clock/Frame Sync Generators,
Control Logic, and Port Control
Figure 14-2. BBP Block Diagram
SC0B
SC1B
SC2B
SCKB
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Transmit and Receive Clocks
14.1 Data and Control Pins
Each of the ports contains six pins. The names and functions of these pins are summarized
SAP Pin
SC0A
SC1A
SC2A
SCKA
SRDA
STDA
SC0B
SC1B
SC2B
SCKB
SRDB
STDB
Table 14-1. SAP and BBP Pins
Function
BBP Pin
Asynchronous Mode Synchronous Mode
Receiver Clock
Receiver Frame Sync
Transmitter Frame Sync
Serial Flag 0
Serial Flag 1
Tx and Rx Frame Sync
Transmitter Clock Tx and Rx Clock
Serial Receive Data Pin
Serial Transmit Data Pin
The functions of the serial clock pin (SCK) and serial control pins (SC0Ð2) for each port depend on whether the port clock and frame sync signals operate independently
(asynchronous mode) or are common (synchronous mode). Signal directions (input or output) for these four pins are determined by the Serial Control Pin Direction SCD[2:0] and Serial Clock Pin Direction (SCKD) bits in Control Register C for each port (SAPCRC and BBPCRC). Pins that are not used for SAP or BBP operation can be configured as
GPIO. Pin functions are further described in the following sections:
¥
Receive and transmit clocksÑSection 14.2 on page 14-3.
¥
Data transmission and receptionÑSection 14.4 on page 14-9.
¥
Serial flagsÑSection 14.3.4 on page 14-8.
14.2 Transmit and Receive Clocks
Several options are provided to configure the SAP and BBP transmit and receive bit clocks, including clock sources (internal or external), frequency, polarity, and BRM (SAP only).
14.2.1 Clock Sources
The transmit and receive clock source(s) can be either external or internal. For an external clock source, the pins functioning as clocks are configured as inputs. For an internal clock source, clock pins are configured as outputs. The BBP internal clock is derived from
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Transmit and Receive Clocks
DSP_CLK; the SAP internal clock is derived from either DSP_CLK or the Bit Rate
Multiplier clock (BRM_CLK), as determined by the BRM bit in the SAP Control Register
C (SAPCRC). Clock sources and pins are governed by SAPCRC/BBPCRC control bits
SYN (which selects synchronous or asynchronous mode), SCKD, and SCD0, as shown in
SYN SCKD SCD0
Table 14-2. SAP/BBP Clock Sources
Receive
Clock Source
Receive
Clock Out
Transmit Clock
Source
Transmit
Clock Out
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1 x x
Asynchronous Mode
External, SC0A/B
Internal
External, SC0A/B
Internal
Ñ
SC0A/B
Ñ
SC0A/B
Synchronous Mode
External, SCKA/B
Internal
Ñ
SCKA/B
External, SCKA/B
External, SCKA/B
Internal
Internal
External, SCKA/B
Internal
Ñ
Ñ
SCKA/B
SCKA/B
Ñ
SCKA/B
Note: Although an external serial clock can be independent of and asynchronous to the DSP system clock, its frequency must be less than or equal to one-third the
DSP_CLK frequency.
14.2.2 Clock Frequency
The frequency of the internally-generated bit clock is determined by the source clock, an optional divide-by-8 prescaler, and a programmable prescale modulus, as shown in the following equation:
Bit clock frequency =
¾¾¾¾¾¾¾¾¾
2
´
(2ÐPSR)
3 ´
(PM+1) where BRGCLK =DSP_CLK (BBP)
DSP_CLK or BRM_CLK (SAP)
PSR = Prescaler (PSR) bit in Control Register A
(SAPCRA or BBPCRA)
PM = Value of the Prescale Modulus (PM[7:0]) bits in
SAPCRA or BBPCRA.
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Transmit and Receive Clocks
The minimum frequency is generated with the prescaler on (PSR=0) and the maximum prescale modulus (PM[7:0]=255), yielding
Bit clock frequency =
2
BRGCLK
´
(2)
3 ´
(256)
= BRGCLK
4096
The combination of PSR=1 and PM[7:0]=0 is reserved, so the maximum frequency is generated with PSR=1 and PM[7:0]=1, yielding
Bit clock frequency =
2
BRGCLK
´
(1)
3 ´
(2)
= BRGCLK
4
If the bit clock is supplied externally, the maximum allowed frequency is DSP_CLK
¸
3.
14.2.3 Clock Polarity
The Clock Polarity (CKP) bit in the SAPCRC or BBPCRC determines the clock edge on which data and frame sync are clocked out and latched in. When the CKP bit is cleared, data and frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock. When the CKP bit is set, data and frame sync are clocked out on the falling edge of the transmit bit clock and latched in on the rising edge of the receive bit clock.
14.2.4 Bit Rate Multiplier (SAP Only)
The BRM provides a way for systems with a CKIH of 16.8 MHz to generate a SAP bit clock with the standard codec frequency of 2.048 MHz. The BRM applies a 512/525 multiplier to DSP_CLK to generate a 16.384 MHz BRM_CLK from a 16.8 MHz input. To generate a 2.048 MHz bit clock, perform the following steps:
1. Set the BRM bit in the SAPCRC to select BRM_CLK rather than DSP_CLK as the bit rate clock source BRGCLK.
2. Set the PSR bit in SAPCRA to disable the prescaler.
3. Write $03 to the PM[7:0] bits in the SAPCRA to divide the 16.384 MHz BRGCLK by four.
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TDM Options
14.3 TDM Options
Several facets of SAP and BBP TDM operation can be controlled, including synchronous or asynchronous mode, frame configuration, frame sync parameters, serial I/O flags, and interrupts.
14.3.1 Synchronous and Asynchronous Modes
The transmit and receive sections for each port can operate either synchronously or asynchronously, as determined by the Synchronous Mode (SYN) bit in the SAPCRC or
BBPCRC. In asynchronous mode, there are separate, independent signals and pins for the transmit clock, receive clock, transmit frame sync (TFS) and receive frame sync (RFS).
The synchronous mode has a common transmit and receive clock and a common transmit
and receive frame syncs. Pin assignments for these signals are listed in Table 14-1 on page 14-3.
14.3.2 Frame Configuration
Each port can be configured for one time slot per frame (normal mode) or multiple time slots per frame (network mode). Each of these modes is periodic. A non-periodic on-demand mode is also provided. The mode is determined by Operation Mode (MOD) bit in the SAPCRC or BBPCRC and the Frame Rate Divider Control (DC[4:0]) bits in the
SAPCRA or BBPCRA, as shown in Table 14-3
MOD
0
1
1
Table 14-3. Frame Configuration
DC[4:0] Value
0Ð31
1Ð31
0
Mode
Normal
Network
On-Demand
DC[4:0] Meaning
(Word transfer rate) Ð 1
(Number of time slots) Ð 1
Ñ
14.3.2.1 Normal Mode
Normal mode is typically used to transfer data to or from a single device. There can be multiple (up to 32) Òtime slotsÓ per frame, according to the DC[4:0] bits, but data is transferred and received only in the first time slot. Thus, in normal mode, DC[4:0] effectively determine the word transfer rate.
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TDM Options
14.3.2.2 Network Mode
Network mode is typically used in TDM systems employing multiple devices. Two to 32 time slots can be selected with the DC[4:0] bits, and data is transferred and received in each time slot.
14.3.2.3 On-Demand Mode
On-demand mode is selected by adjusting the MOD bit for network mode and clearing
DC[4:0]. In this mode, frame sync is not periodic but is generated only when data is available to transmit. The TFS must be internal (output), and the RFS must be external
(input). Therefore, either synchronous or asynchronous mode can be used in simplex operation, but full-duplex operation requires asynchronous mode. On-demand mode is useful for interfacing to a codec that requires a continuous clock.
14.3.3 Frame Sync
The frame sync frequency for each port is
¾¾¾¾¾¾¾¾
WL
´
(DC + 1) where bit clock = the transmit or receive bit clock frequency derived in
WL = Binary value of the word length (8, 12, or 16) as specified by the
WL[1:0]) bits in SAPCRA or BBPCRA.
DC = Binary value of the DC[4:0] bits in SAPCRA or BBPCRA.
The following RFS and TFS parameters can be adjusted by bits in SAPCRC or BBPCRC:
¥ DurationÑThe sync signals can be either one bit long or one word long by adjusting the Frame Sync Length (FSL[1:0]) bits. In asynchronous mode, the sync signals can be the same or different lengths.
¥ DirectionÑThe signals can be outputs or inputs according to SCD[2:1]
¥ TimingÑWord-length frame syncs can be asserted at the start of a frame or on the last bit of the previous frame by adjusting the Frame Sync Relative timing (FSR) bit.
¥ PolarityÑThe sync signals can be active-high or active-low based on the Frame
Sync Polarity (FSP) bit.
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TDM Options
14.3.4 Serial I/O Flags
In synchronous mode, the SC0x and SC1x pins are available as Serial I/O Flags. Flag I/O is typically used in codec systems to select among multiple devices for addressing. Flag values can change state for each transmitted or received word. The DSP56652 provides double-buffered control and status bits for the flags to keep them synchronized with the transmit and receive registers. Each flag can be configured as an input or output according to the corresponding SCD bit in the SAPCRC or BBPCRC.
If a flag pin is configured as an input, its state is reflected in the Input Flag (IF0 or IF1) bit in the port Status Register (SAPSR or BBPSR). The pin is latched during reception of the first received bit after an RFS, and the corresponding IF bit is set when the contents of the portÕs receive shift register are transferred to the SAPRX or BBPRX. Latching the flag input pin allows the signal to change state without affecting the flag state until the first bit of the next received word.
When configured as an output, the flag pin reflects the state of the Output Flag (OF0 or
OF1) bit in Control Register B (SAPCRB or BBPCRB). When one of these bits is changed, the value is latched the next time the contents of SAPTX or BBPTX are transferred to the portÕs transmit shift register. The corresponding flag pin changes state at the start of the following frame (normal mode) or time slot (network mode), and remains stable until the first bit of the following word is transmitted. Use the following sequence for setting output flags when transmitting data:
1. Wait for the TDE bit to be set, indicating the TXB register is empty.
2. Write the OF0 and OF1 bits flags.
3. Write the transmit data to the TXB register.
For each port, the two flags operate independently but can be used together for multiple serial device selection. They can be used unencoded to select one or two codecs, or can be decoded externally to select up to four codecs.
14.3.5 TDM Interrupts
In network mode, interrupts can be generated at the end of the last slot in a transmit or receive frame. The interrupts are enabled by the Receive Last Slot Interrupt (RLIE) and
Transmit Last Slot Interrupt (TLIE) bits in the SAPCRB or BBPCRB.
The other four TDM interruptsÑReceive, Receive Error, Transmit, and Transmit ErrorÑ
can occur in any TDM mode. These interrupts are described in Section 14.4.
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Data Transmission and Reception
14.4 Data Transmission and Reception
Each port provides configuration options for data transmission and reception, as well as data format.
14.4.1 Data Transmission
The transmission sequence varies somewhat between normal, network, and on-demand modes.
14.4.1.1 Normal Mode Transmission
The following steps illustrate a typical transmission sequence in normal mode:
1. Write the first transmit data word to the portÕs Transmit Register (SAPTX or
BBPTX). This clears the Transmit Data Register Empty (TDE) bit in the SAPSR or
BBPSR.
2. Set the Transmit Enable (TE) bit in the SAPCRB or BBPCRB.
3. At the next TFS, the Transmit Register data is copied to the Transmit Shift
Register, the transmitter is enabled, and the TDE bit is set. The Transmit Register retains the current data until it is written again. If the Transmit Interrupt Enable
(TIE) bit in the SAPCRB or BBPCRB is set, an interrupt is generated. At this point, a new value is normally written to the Transmit Register, clearing TDE.
4. Data is shifted out from the shift register to the STDx pin, clocked by the transmit bit clock.
5. The cycle repeats from step 3.
If the TDE bit is set when step 3 occurs, indicating that new data has not been written to the Transmit Register, the Transmit Underflow Error (TUE) bit in the SAPSR or BBPSR is set. If the Transmit Error Interrupt Enable (TEIE) bit in the SAPCRB or BBPCRB is set, an interrupt is generated. The previously sent data, which has remained in the Transmit
Register, is again copied to the shift register and transmitted out.
Note: If the TE bit is cleared during a transmission, the SAP or BBP completes the transmission of the current data in the transmit shift register before disabling the transmitter. TE should not be cleared until the TDE bit is set, indicating that the current data has been transferred from the transmit register to the transmit shift register. When the transmitter is disabled, the STDx pin is tri-stated, and any data present in the SAPTX or BBPTX is not transmitted. Data can be written to a Transmit Register when the TE bit is cleared, but is not copied to the shift register until the TE bit is set.
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Data Transmission and Reception
14.4.1.2 Network Mode Transmission
The following steps illustrate a typical transmission sequence in network mode:
1. Write the Transmit Register with the first transmit data word. If no data is to be sent for the first time slot, write to the Time Slot register (SAPTSR or BBPTSR) instead to avoid an underrun error. The content written to the Time Slot Register is irrelevant and ignored.
2. Set the TE bit.
3. If the Transmit Register has been written, the data is copied to the transmit shift register at the next TFS for the first time slot in a frame. For other time slots, the copy takes place at the beginning of the next time slot. The Transmit Register retains the current data until it is written again.
4. The TDE bit is set. If the TIE bit is set, an interrupt is generated. At this point, the
Transmit Register or Time Slot Register is written, depending on the following circumstances: f. If data is to be transmitted in the next time slot, that data is written to the
Transmit Register.
g. If the next time slot is idle but subsequent time slots are to be used, the Time
Slot Register is written to avoid a transmit underrun error.
Either of these writes clears TDE.
5. If the shift register contains data, the data is shifted out to the STDx pin, clocked by the transmit bit clock. If the shift register is empty (data was written to the Time
Slot Register rather than the Transmit Register), the STDx pin is tri-stated for that time slot.
6. If data is to be sent for any subsequent time slots in the frame, or if this is the last time slot in the frame, the cycle repeats from step 3.
7. If no further data is to be sent in this frame, the first time slot of the next frame can be set up by writing either the Transmit Register (with data for the first time slot) or the Time Slot Register. After transmission of the last data word is completed, the
TE bit can be toggled (cleared and then reset) . This action disables the transmitter
(after the last bit has been shifted out of the transmit shift register) and the STDx pin remains in the high-impedance state until the beginning of the next frame. At the next frame sync, the next frame begins at step 3.
At step 3, if neither the Transmit Register nor the Time Slot Register have been written since step 3 of the previous cycle, the TUE bit is set and an interrupt is generated if enabled as described in Normal mode.
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Data Transmission and Reception
In addition to interrupts for receive and transmit, special network mode interrupts are provided to indicate the last slot.
14.4.1.3 On-Demand Mode
A typical transmission sequence in on-demand mode is as follows:
1. Set the TE bit in the SAPCRB or BBPCRB.
2. Write transmit data to the portÕs Transmit Register.
3. The Transmit Register data is copied to the Transmit Shift Register. The Transmit
Register retains the current data until it is written again.
4. The TDE bit is set, and an interrupt is generated if the TIE bit in is set.
5. Data is immediately shifted out from the shift register to the STDx pin, clocked by the transmit bit clock.
6. The cycle repeats from step 2, but not at any particular time. If the Transmit
Register is written before the current time slot has expired, step 5 will not occur
(and the Transmit Register will not accept another word) until the current time slot expires.
Although the SAP transmitter is double-buffered, only one word can be written to the
Transmit Register, even when the transmit shift register is empty. Transmit underruns are impossible for on-demand transmission and are disabled.
14.4.2 Data Reception
Data reception is enabled by setting the Receive Enable (RE) pin in SAPCRB or
BBPCRB, which allows or inhibits transfer from the shift register to the Receive Register.
Data is received on the SRDA or SRDB pin, clocked into the receive shift register by the receive transmit clock. When the number of bits received equals the expected word length
(as selected by the WL bits in SAPCRA or BBPCRA), the shift register contents are transferred to the Receive Register (SAPRX or BBPRX), and the Receive Data Register
Full (RDF) bit in the SAPSR or BBPSR is set. If the Receive Interrupt Enable (RIE) bit in
SAPCRB or BBPCRB is set, an interrupt is generated. Reading the receive register clears the RDF bit. If the received word is the first word in a frame, the Receive Frame Sync
(RFS) bit in the SAPSR or BBPSR is set.
If RDF is set when the shift register is full, indicating that the previous received word has not been read, the Receive Overrun Error (ROE) bit in the SAPSR or BBPSR is set, and an interrupt is generated if the Receive Error Interrupt Enable (REIE) bit in the SAPCRB or
BBPCRB has been set. The newer data is lost.
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Software Reset
14.4.3 Data Formats
Data words can be 8, 12, or 16 bits long. Word length is determined by the WL[1:0] bits in the SAPCRA or BBPCRA.
The shift registers in the SAP and BBP are bidirectional to accommodate data formats that specify MSB first (such as those used by codecs) and LSB first (such as those used by
AES-EBU digital audio). Selection of MSB or LSB first is determined by the SHFD bit in the SAPCRC or BBPCRC.
14.5 Software Reset
Either port can be reset without disturbing the rest of the system by clearing the PC[5:0] bits in the Port Control Register (SAPPCR or BBPPCR). This action stops all serial activity and resets the status bits; the contents of SAPCRA, SAPCRB, and SAPCRC are not affected. The port remains in reset while all pins are programmed as GPIO, and becomes active (i.e., functions as the SAP or BBP) only if at least one of the pins is programmed as a SAP or BBP pin.
Note: To ensure proper operation of the interface, the DSP program must reset the
SAP or BBP before changing any of its control registers except for the
SAPCRB or BBPCRB.
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Frame Counters (BBP Only)
14.6 General-Purpose Timer (SAP Only)
The SAP provides a general-purpose timer that can be used for debugging. The timer is enabled by the TCE bit in the SAPCRB. The following two registers control timer operation:
¥ The SAP Timer Counter (SAPCNT) is a counter that is decremented by a clock running at a frequency of (DSP_CLK
¸
2048). When it decrements to zero, a timer counter rollover interrupt is issued.
¥ The SAP Timer Modulus Register (SAPMR) contains a modulus value that is loaded into the SAPCNT register when TCE is set and each time the counter rolls over.
Note: Although this timer is technically not involved in SAP operation, the SAP must be enabled by setting the PEN bit and at least one of the PC[5:0] bits in the SAP
Port Control Register (SAPPCR) to enable the timer.
14.7 Frame Counters (BBP Only)
The BBP provides two counters that can be used to count transmit and receive frames.
Setting the TCE bit in BBPCRB enables the transmit frame counter and loads it with the value in the BBP Transmit Counter Modulus Register (BBPTMR). The counter is decremented by transmit frame sync. When the counter rolls over, it is again loaded with
BBPTMR, and an interrupt is generated if the TCIE bit in BBPCRB is set.
Setting the RCE bit in BBPCRB enables the receive frame counter and loads it with the value in the BBP Receive Counter Modulus Register (BBPRMR). The counter is decremented by receive frame sync. When the counter rolls over, it is again loaded with
BBPRMR, and an interrupt is generated if the RCIE bit in BBPCRB is set.
Note: Although these counters are technically not involved in BBP operation, the
BBP must be enabled by setting the PEN bit and at least one of the PC[5:0] bits in the BBP Port Control Register (BBPPCR) to enable the counters.
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Interrupts
14.8 Interrupts
Table 14-4 presents a summary of the possible interrupts the DSP can generate for each
port , ordered from highest to lowest priority (assuming they are all assigned the same interrupt priority level), along with their corresponding status and interrupt enable bits, if any.
Table 14-4. SAP and BBP Interrupts
Interrupt
SAP Receive Data with Overrun Error
SAP Receive Data
SAP Receive Last Slot
SAP Transmit Data with Underrun Error
SAP Transmit Last Slot
SAP Transmit Data
SAP Timer Counter Rollover
SAPCRB Interrupt
Enable Bit
REIE
RIE
RLIE
TEIE
TLIE
TIE
TCIE
BBP Receive Data with Overrun Error
BBP Receive Data
BBP Receive Last Slot
BBP Receive Frame Counter
BBP Transmit Data with Underrun Error
BBP Transmit Last Slot
BBP Transmit Data
BBP Transmit Frame Counter
BBPCRB Interrupt
Enable Bit
REIE
RIE
RLIE
RCIE
TEIE
TLIE
TIE
TCIE
SAPSR Status Bit
ROE
RDF
Ñ
TUE
Ñ
TDE
Ñ
BBPSR Status Bit
TUE
Ñ
TDE
Ñ
ROE
RDF
Ñ
Ñ
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SAP and BBP Control Registers
14.9 SAP and BBP Control Registers
Table 14-5 and Table 14-6 are summaries of the SAP and BBP control registers
respectively, including the acronym, bit names, and address of each register.
Table 14-5. Serial Audio Port Register Summary
SAPCNT 15 14 13 12 11 10 9
X:$FFB4
8 7
LV[15:0]
6 5 4 3 2 1 0
SAPMR 15 14 13 12 11 10 9
X:$FFB5
SAPCRA 15 14 13 12 11 10 9
X:$FFB6 PSR WL[1:0] DC[4:0]
8 7
LV[15:0]
8 7
6 5 4 3 2 1 0
6 5 4 3
PM[7:0]
4 3
2 1 0
SAPCRB 15 14 13 12 11 10 9 8
X:$FFB7 REIE TEIE RLIE TLIE RIE TIE RE TE
SAPCRC 15 14 13 12 11 10 9
X:$FFB8 FSP FSR FSL[1:0]
8 7
7
6
6 5
5
BRM SHFD CKP SCKD
4 3
SCD[2:0]
2
2
1
TCE OF[1:0]
1
0
0
MOD SYN
SAPSR
X:$FFB9
15 14 13 12 11 10 9
SAPRX 15 14 13 12 11 10 9
X:$FFBA
8
8
7 6 5 4 3 2 1 0
RDF TDE ROE TUE RFS TFS IF[1:0]
7
Receive Word
6 5 4 3 2 1 0
5 4 3 2 1 0 SAPTSR 15 14 13 12 11 10 9
X:$FFBB
SAPPDR
X:$FFBD
15 14 13 12 11 10 9
8 7
(Dummy)
6
SAPTX 15 14 13 12 11 10 9
X:$FFBC
8 7
Transmit Word
6
8 7 6
SAPDDR
X:$FFBE
15 14 13 12 11 10 9
SAPPCR 15 14 13 12 11 10 9
X:$FFBF
8
8
7
7
PEN
6
6
5
5
5
5
4
4
4
4
3
3
PD[5:0]
3 2
PDC[5:0]
3
2
2
2
PC[5:0]
1
1
1
1
0
0
0
0
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SAP and BBP Control Registers
Table 14-6. Baseband Port Register Summary
BBPRMR 15 14 13 12 11 10 9
X:$FFA4
8 7
LV[15:0]
6 5 4 3 2 1 0
BBPTMR 15 14 13 12 11 10 9
X:$FFA5
BBPCRA 15 14 13 12 11 10 9
X:$FFA6 PSR WL[1:0] DC[4:0]
BBPCRB Bit 15 14 13 12 11 10 9
BBPCRC
X:$FFA8
15 14
FSP FSR
13 12
FSL[1:0]
11 10 9 8
8 7
LV[15:0]
8 7
8 7
6
6
6
5
5
5
4
4
X:$FFA7 REIE TEIE RLIE TLIE RIE TIE RE TE RCIE TCIE RCE TCE
3
4 3
PM[7:0]
3
2
2
2
1
1
0
0
1 0
OF[1:0]
7 6 5 4 3 2 1 0
SHFD CKP SCKD SCD[2:0] MOD SYN
BBPSR
X:$FFA9
15 14 13 12 11 10 9
BBPRX 15 14 13 12 11 10 9
X:$FFAA
8
8
7 6 5 4 3 2 1 0
RDF TDE ROE TUE RFS TFS IF[1:0]
7
Receive Word
6 5 4 3 2 1 0
5 4 3 2 1 0 BBPTSR 15 14 13 12 11 10 9
X:$FFAB
BBPPDR
X:$FFAD
15 14 13 12 11 10 9
8 7
(Dummy)
6
BBPTX 15 14 13 12 11 10 9
X:$FFAC
8 7
Transmit Word
6
8 7 6
BBPDDR
X:$FFAE
15 14 13 12 11 10 9
BBPPCR 15 14 13 12 11 10 9
X:$FFAF
8
8
7
7
PEN
6
6
5
5
5
5
4
4
4
4
3
3
PD[5:0]
3 2
PDC[5:0]
3
2
2
2
PC[5:0]
1
1
1
1
0
0
0
0
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SAP and BBP Control Registers
14.9.1 SAP and BBP Control Registers
SAPCNT
Bit 15 14 13 12 11
SAP Timer Counter
10 9 8 7 6
Ñ Ñ
SAP Timer Count
Ñ Ñ Ñ RESET Ñ Ñ Ñ Ñ Ñ
This read-only register holds the value of the SAP timer.
5
Ñ
4
Ñ
3
Ñ
2
Ñ
X:$FFB4
1 Bit 0
Ñ Ñ
BBPRMR
Bit 15 14 13
BBP Receive Counter Modulus Register
12 11 10 9 8 7 6 5 4
0 0 0
BBP Receive Counter Load Value
0 0 0 0 0 0
3 2
X:$FFA4
1 Bit 0
RESET 0 0 0 0 0 0 0
This register contains the value that is loaded in the BBP receive frame counter register when the counter is enabled and when the counter rolls over.
SAPMR
Bit 15 14 13 12
SAP Timer Modulus Register
11 10 9 8 7 6 5
0 0 0
SAP Timer Load Value
0 0 0 0
4 3 2
X:$FFB5
1 Bit 0
RESET 0 0 0 0 0 0 0 0 0
This register contains the value that is loaded in the SAPCNT register when the timer is enabled and when the timer rolls over.
BBPTMR
Bit 15 14 13
0
BBP Transmit Counter Modulus Register
12 11 10 9 8 7 6 5 4
0 0 0
BBP Transmit Counter Load Value
0 0 0 0 0 0
3 2
X:$FFA5
1 Bit 0
RESET 0 0 0 0 0 0
This register contains the value that is loaded in the BBP transmit frame counter register when the counter is enabled and when the counter rolls over.
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SAP and BBP Control Registers
SAPCRA
BBPCRA
Bit 15 14
Name
PSR
Bit 15
PM[7:0]
Bits 7Ð0
PSR
RESET 0
WL[1:0]
Bits 14Ð13
DC[4:0]
Bits 12Ð8
0
13
WL[1:0]
0
12
0
11
SAP Control Register A
BBP Control Register A
10 9 8 7 6
0
DC[4:0]
0 0 0 0 0
5
0
4
PM[7:0]
3
0 0
Table 14-7. SAP/BBP CRA Description
Description Settings
2
X:$FFB6
X:$FFA6
1 Bit 0
0 0 0
Bit Clock PrescalerÑ Setting this bit bypasses the divide-by-eight prescaler to the bit rate generator.
Note: The combination of PSR = 1 and
PM[7:0] = $00 is reserved and may cause synchronization problems if used.
0 = Prescale applied (default).
1 = No prescale.
Word LengthÑ These bits select the word length for transmitted and received data.
00 = 8 bits per word (default).
01 = 12 bits per word.
10 = 16 bits per word.
11 = Reserved.
Frame Rate Divider ControlÑ These bits in conjunction with the MOD bit in the SAPCRC or
BBPCRC configure the transmit and receive frames. Refer to Table 14-3 on page 14-6. In network
mode, value of this field plus one equals the number of slots per frame. In normal mode, the value of this field is the number of dummy Òtime slotsÓ, effectively determining the word transfer rate.
Prescale ModulusÑ These bits along with the PSR bit determine the bit clock frequency. Refer to
Note: The combination of PSR = 1 and PM[7:0] = $00 is reserved and may cause synchronization problems if used.
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SAP and BBP Control Registers
SAPCRB
Bit 15 14 13 12 11
SAP Control Register B
10 9 8 7 6
REIE TEIE RLIE TLIE RIE TIE RE TE
RESET 0 0 0 0 0 0 0 0 0 0
5
0
4
0
3
0
2
X:$FFB7
1 Bit 0
TCE OF1 OF0
0 0 0
BBPCRB
Bit 15 14 13 12 11
BBP Control Register B
10 9 8 7 6
REIE TEIE RLIE TLIE RIE TIE RE
5 4
TE RCIE TCIE RCE TCE
RESET 0 0 0 0 0 0 0 0 0 0 0 0
3 2
X:$FFA7
1 Bit 0
OF1 OF0
0 0 0 0
Note: In addition to setting the interrupt enable bits in the SAPCRB or BBPCRB, the
SAPPL or BBPPL field respectively in the IPRP must be written with a
non-zero value to generate the respective interrupts (see page 7-14).
Name
REIE
Bit 15
TEIE
Bit 14
RLIE
Bit 13
TLIE
Bit 12
RIE
Bit 11
TIE
Bit 10
RE
Bit 9
Table 14-8. SAP/BBP CRB Description
Description Settings
Receive Error Interrupt EnableÑ Setting this bit enables an interrupt when a receive overflow error occurs.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
Transmit Error Interrupt EnableÑ Setting this bit enables an interrupt when a transmit underflow error occurs.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
Receive Last Slot Interrupt EnableÑ In network mode, setting this bit enables an interrupt at the end of the last receive time slot in a frame. RLIE has no effect in other modes.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
Transmit Last Slot Interrupt EnableÑ In network mode, setting this bit enables an interrupt at the beginning of the last transmit time slot in a frame. TLIE has no effect in other modes.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
Receive Interrupt EnableÑ Setting this bit enables an interrupt when the receive register receives the last bit of a word and transfers the contents to the Receive Register.
Transmit Interrupt EnableÑ Setting this bit enables an interrupt when the contents of the
Transmit Register are transferred to the transmit shift register.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
Receive EnableÑ Enables the SAP or BBP receiver by allowing data transfer from the receive shift register to the Receive Register.
0 = Receiver disabled (default).
1 = Receiver enabled.
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SAP and BBP Control Registers
Table 14-8. SAP/BBP CRB Description
Description Settings Name
TE
Bit 8
RCIE (BBP).
Bit 7
Transmit EnableÑ Enables the SAP or BBP transmitter by allowing data transfer from the
Transmit Register to the transmit shift register.
Note: The TE bit does not affect the generation of frame sync or output flags.
0 = Transmitter disabled (default).
1 = Transmitter enabled.
BBP Receive Counter Interrupt EnableÑ
Setting this bit enables an interrupt when the BBP receive counter rolls over.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
TCIE (BBP).
Bit 6
RCE (BBP).
Bit 5
TCE (BBP).
Bit 4
TCE (SAP).
Bit 2
OF1
Bit 1
OF0
Bit 0
BBP Transmit Counter Interrupt EnableÑ
Setting this bit enables an interrupt when the BBP transmit counter rolls over.
0 = Interrupt disabled (default).
1 = Interrupt enabled.
BBP Receive Counter EnableÑ Enables the
BBP receive frame sync counter.
BBP Transmit Counter EnableÑ Enables the
BBP transmit frame sync counter.
0 = Counter disabled (default).
1 = Counter enabled.
0 = Counter disabled (default).
1 = Counter enabled.
SAP Timer Count EnableÑ Enables the SAP general-purpose timer.
0 = Timer disabled (default).
1 = Timer enabled.
Output Flag 1Ñ In synchronous mode (SYN bit in the SAPCRC or BBPCRC is set), this bit drives serial output flag 1 on the SC1x pin if it is configured as an output (SCD1 bit in the SAPCRC or
BBPCRC is set).
Output Flag 0Ñ In synchronous mode (SYN bit in the SAPCRC or BBPCRC is set), this bit drives serial output flag 0 on the SC0x pin if it is configured as an output (SCD0 bit in the SAPCRC or
BBPCRC is set).
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SAP and BBP Control Registers
SCKD
Bit 5
SCD2
Bit 4
SCD1
Bit 3
SCD0
Bit 2
MOD
Bit 1
SYN
Bit 0
SAPCRC
BBPCRC
Bit 15 14
FSP FSR
RESET 0 0
Name
FSP
Bit 15
FSR
Bit 14
FSL[1:0]
Bits 13Ð12
BRM (SAP).
Reserved
(BBP).
Bit 8
SHFD
Bit 7
CKP
Bit 6
13 12
FSL[1:0]
0 0
11
0
SAP Control Register C
BBP Control Register C
10
0
9
0
8
BRM* SHFD CKP SCKD SCD2 SCD1 SCD0 MOD SYN
0
7
0
6
0
5
0
4
0
3
0
Table 14-9. SAP/BBP CRC Description
Description Settings
2
0
X:$FFB8
X:$FFA8
1
0
Bit 0
0
Frame Sync PolarityÑ Determines if frame sync is active-high or active-low.
0 = Active-high (default).
1 = Active-low.
Frame Sync Relative TimingÑ Determines if frame sync is asserted at the last bit or the previous frame or the first bit of the current frame.
This bit is effective for word-length frame sync only.
0 = First bit of current frame (default).
1 = Last bit of previous frame.
Frame Sync LengthÑ These bits determine the duration (word-length or bit-length) for both transmit and receive frame sync.
Bit Rate Multiplier (SAP only)Ñ clock prescaler.
Selects either
DSP_CLK or BRM_CLK as the input to the bit
00 = TFS and RFS are word-length (default).
01 = TFS is bit-length; RFS is word-length.
10 = TFS and RFS are bit-length.
11 = TFS is word-length; RFS is bit-length.
0 = DSP_CLK (default).
1 = BRM_CLK.
Shift DirectionÑ Determines if data is sent and received MSB first or LSB first.
Clock PolarityÑ Determines the bit clock edge on which frame sync is asserted and data is shifted.
Serial Clock Pin DirectionÑ Determines if the
SCKx pin is an output or an input.
Serial Control Pin 2 DirectionÑ Determines if the SC2x pin is an output or an input.
Serial Control Pin 1 DirectionÑ Determines if the SC1x pin is an output or an input.
Serial Control Pin 0 DirectionÑ Determines if the SC0x pin is an output or an input.
Normal/Network Mode Select
Synchronous/Asynchronous Select
0 = MSB first (default).
1 = LSB first.
0 = TransmitÑbit clock rising edge
ReceiveÑbit clock falling edge (default).
1 = TransmitÑbit clock falling edge
ReceiveÑbit clock rising edge.
0 = Input (default).
1 = Output.
0 = Input (default).
1 = Output.
0 = Input (default).
1 = Output.
0 = Input (default).
1 = Output.
0 = Normal mode (default).
1 = Network mode.
0 = Asynchronous mode (default).
1 = Synchronous mode .
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SAP and BBP Control Registers
SAPSR
BBPSR
Bit 15 14 13 12 11
SAP Status Register A
BBP Status Register A
10 9 8 7 6 5 4 3 2
X:$FFB9
X:$FFA9
1
RDF TDE ROE TUE RFS TFS IF1
Bit 0
IF0
0 0 0 0 0 1 0 0 0 0 0 0 RESET 0 0 0 0
The SAPSR and BBPSR are 8-bit, read-only registers.
Name
RDF
Bit 7
TDE
Bit 6
ROE
Bit 5
TUE
Bit 4
RFS
Bit 3
TFS
Bit 2
IF1
Bit 1
IF0
Bit 0
Table 14-10. SAP/BBP Status Register Description
Description Settings
Receive Data Register FullÑ Set when the contents of the receive shift register are transferred to the Receive Register. Cleared by reading the Receive Register.
0 = No new data received (default).
1 = New data in Receive Register.
Transmit Data Register EmptyÑ Set when the contents of the Transmit Register are transferred to the transmit shift register. Cleared by a write to the Receive Register or the Time Slot Register.
0 = Last transmit word has not yet been copied to transmit shift register.
1 = Last transmit word has been copied to transmit shift register (default).
Receiver Overrun ErrorÑ Set when the last bit of a word is shifted into the receive shift register and RDF is set, meaning that the previous received word has not been read. Cleared by reading the Status Register, then the Receive
Register.
0 = No receive error (default).
1 = Receiver overrun error has occurred.
Transmitter Underrun ErrorÑ Set when the transmit shift register is empty and a time slot occurs, meaning that the Transmit Register has not been written since the last transmission.
Cleared by reading the Status Register, then writing the Transmit Register or the Time Slot
Register.
0 = No transmit error (default).
1 = Transmitter underrun error has occurred.
Receive Frame SyncÑ This bit reflects the status of the receive frame sync signal, whether generated internally or received externally. In normal mode, RFS is always set. In network mode,
RFS is set only during the first time slot of the receive frame, and remains set for the duration of the word reception, regardless of the state of the FSL bit in the SAPCRC or BBPCRC.
Transmit Frame SyncÑ This bit reflects the status of the transmit frame sync signal, whether generated internally or received externally. In normal mode, TFS is always set. In network mode,
TFS is set only during the first time slot of the transmit frame, and remains set for the duration of the word transmission, regardless of the state of the FSL bit in the SAPCRC or BBPCRC.
Input Flag 1Ñ In synchronous mode, this bit reflects the state of Input Flag 1, which is driven on the SC1x pin.
Input Flag 0Ñ In synchronous mode, this bit reflects the state of Input Flag 0, which is driven on the SC0x pin.
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SAP and BBP Control Registers
SAPRX
BBPRX
Bit 15 14 13 12
SAP Receive Data Register
BBP Receive Data Register
11 10 9 8 7 6 5
Ñ Ñ Ñ
Receive Word
Ñ Ñ Ñ Ñ
4 3 2
X:$FFBA
X:$FFAA
1 Bit 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
This read-only register accepts data from the receive shift register after the last bit of a receive word is shifted in. If the word length is less than 16 bits, the data is shifted into the most significant bits.
SAPTSR
BBPTSR
Bit 15 14 13 12 11
SAP Time Slot Register
BBP Time Slot Register
10 9 8 7 6
Ñ Ñ Ñ
(Dummy)
Ñ Ñ Ñ
5 4 3 2
X:$FFBB
X:$FFAB
1 Bit 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
This dummy write-only register is written to avoid a transmit underrun error for a time slot for which no data is to be transmitted.
SAPTX
BBPTX
Bit 15 14 13 12
SAP Transmit Data Register
BBP Transmit Data Register
11 10 9 8 7 6 5
Ñ Ñ Ñ
Transmit Word
Ñ Ñ Ñ Ñ
4 3 2
X:$FFBC
X:$FFAC
1 Bit 0
RESET Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
This write-only register loads its data into the transmit shift register. If the word length is less than 16 bits, writes to this register should occupy the most significant bits.
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SAP and BBP Control Registers
14.9.2 GPIO Registers
SAPPDR SAP Port Data Register
Bit 15 14 13 12 11 10 9 8 7 6 5 4
RESET 0 0 0 0 0 0 0 0 0 0
1
X:$FFBD
Bit 0 3 2
SAPPD5
(STDA)
SAPPD4
(SRDA)
SAPPD3
(SCKA)
SAPPD2
(SC2A)
SAPPD1
(SC1A)
SAPPD0
(SC0A)
0 0 0 0 0 0
BBPPDR BBP Port Data Register
Bit 15 14 13 12 11 10 9 8 7 6 5 4
5
RESET 0 0 0 0 0 0 0 0 0 0
1
X:$FFAD
Bit 0 3 2
BBPPD5
(STDB)
BBPPD4
(SRDB)
BBPPD3
(SCKB)
BBPPD2
(SC2B)
BBPPD1
(SC1B)
BBPPD0
(SC0B)
0 0 0 0 0 0
Name
Table 14-11. SAP/BBP PDR Description
Description Settings
SAPPD[5:0]
BBPPD[5:0]
Bits 5Ð0
Port DataÑ Each of these bits contains data for the corresponding pin if it is configured as GPIO.
A write to one of these registers is stored in an internal latch, and driven on any port pin configured as an output. Reads of these registers return the value sensed on input pins and the latched data driven on outputs
SAPDDR SAP Data Direction Register
Bit 15 14 13 12 11 10 9 8 7 6 5 4
RESET 0 0 0 0 0 0 0 0 0 0
1
X:$FFBE
Bit 0 3 2
SAPDD5
(STDA)
SAPDD4
(SRDA)
SAPDD3
(SCKA)
SAPDD2
(SC2A)
SAPDD1
(SC1A)
SAPDD0
(SC0A)
0 0 0 0 0 0
BBPDDR BBP Data Direction Register
Bit 15 14 13 12 11 10 9 8 7 6 5 4
5
RESET 0 0 0 0 0 0 0 0 0 0
1
X:$FFAE
Bit 0 3 2
BBPDD5
(STDB)
BBPDD4
(SRDB)
BBPDD3
(SCKB)
BBPDD2
(SC2B)
BBPDD1
(SC1B)
BBPDD0
(SC0B)
0 0 0 0 0 0
Name
Table 14-12. SAP/BBP DDR Description
Description Settings
SAPDD[5:0]
BBPDD[5:0]
Bits 5Ð0
Data DirectionÑ Each of these bits determines the data direction of the associated pin if it is configured as GPIO.
0 = Input (default).
1 = Output.
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SAP and BBP Control Registers
SAPPCR
Bit 15 14 13 12 11 10
SAP Port Control Register
9 8 7 6 5 4
RESET 0 0 0 0 0 0 0 0
PEN
0 0
1
X:$FFBF
Bit 0 3 2
SAPPC5
(STDA)
SAPPC4
(SRDA)
SAPPC3
(SCKA)
SAPPC2
(SC2A)
SAPPC1
(SC1A)
SAPPC0
(SC0A)
0 0 0 0 0 0
BBPPCR
Bit 15 14 13 12 11 10
BBP Port Control Register
9 8 7 6 5 4
5
RESET 0 0 0 0 0 0 0 0
PEN
0 0
1
X:$FFAF
Bit 0 3 2
BBPPC5
(STDB)
BBPPC4
(SRDB)
BBPPC3
(SCKB)
BBPPC2
(SC2B)
BBPPC1
(SC1B)
BBPPC0
(SC0B)
0 0 0 0 0 0
Name
Table 14-13. SAP/BBP PCR Description
Description Settings
PEN
Bit 7
SAPPC[5:0]
BBPPC[5:0]
Bits 5Ð0
Port EnableÑ Setting this bit enables all SAP or
BBP pins to function as defined by all other register settings. When PEN is cleared, all port pins are tri-stated.
Pin ConfigurationÑ Each bit determines whether its associated pin functions as a peripheral (SAP or BBP) or GPIO.
0 = All pins tri-stated.
1 = All pins function as configured.
0 = GPIO (default).
1 = SAP or BBP.
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SAP and BBP Control Registers
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Chapter 15
JTAG Port
The DSP56652 includes two Joint Test Action Group (JTAG) Test Access Port (TAP) controllers that are compatible with the IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
The block diagram of these two TAPs is shown in
All JTAG testing functions in the DSP56652 are performed by the DSP TAP controller.
The JTAG-specific functions required by IEEE 1149.1 are not included in the MCU TAP controller, which is bypassed in JTAG compliance mode. The MCU TAP controller is only active in MCU OnCE emulation mode, in which the two controllers are enabled and connected serially. MCU OnCE operation is described in the MMC2001 Reference
Manual . DSP OnCE operation is described in the DSP56600 Family Manual .
This chapter describes aspects of the JTAG implementation that are specific to the
DSP56600 core, including items which the IEEE standard requires to be defined and additional information specific to the DSP core implementation. For internal details and applications of the standard, refer to the IEEE 1149.1 document.
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TCK
TRST
TMS
TDI
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MCU_DEBUG
TAP_STATE
MCU_ONCE_ENABLE
TST_LOGIC_RESET
MCU_ONCE_ENABLE
TDI
MCU OnCE TAP and Mode Select
MODE TDO
MCU_TDO
MCU_DE
0
1
TDI MUX
TDI
DSP OnCE and chip-level
JTAG TAP
TDO
DSP_TDO
R
S
JTAG/OnCE
TDO
DSP_DE
Figure 15-1. DSP56652 JTAG Block Diagram
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DSP56600 Core JTAG Operation
15.1 DSP56600 Core JTAG Operation
The DSP56600 core JTAG TAP includes six signal pins, a 16-state controller, an instruction register, and three test data registers. The test logic employs a static logic design and is independent of the device system logic. A block diagram of the DSP56600
core implementation of JTAG is shown in Figure 15-2.
TDI
Boundary Scan Register (BSR)
Bypass
ID Register
OnCE Logic
2
Decoder
3 2 1
4-Bit Instruction Register
0 TDO
TMS
TCK
TRST
TAP
Ctrl
Figure 15-2. DSP56600 Core JTAG Block Diagram
15.1.1 JTAG Pins
As described in the IEEE 1149.1 document, the JTAG port requires a minimum of four pins to support the TDI, TDO, TCK, and TMS signals. The DSP TAP also provides TRST
and DSP_DE pins. The pin functions are described in Table 15-1.
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DSP56600 Core JTAG Operation
Table 15-1. DSP JTAG Pins
Description Pin
TCK
TMS
TDI
TDO
Test ClockÑAn input that is used to synchronize the test logic. The TCK pin has an internal pullup resistor.
Test Mode SelectÑAn input that is used to sequence the test controllerÕs state machine. TMS is sampled on the rising edge of TCK and includes an internal pullup resistor.
Test Data InputÑSerial test instruction and data are received through the Test Data Input (TDI) pin.
TDI is sampled on the rising edge of TCK and includes an internal pullup resistor.
Test Data OutputÑThe serial output for test instructions and data. TDO is three-stateable and is actively driven in the Shift-IR and Shift-DR controller states. TDO changes on the falling edge of TCK.
TRST Test ResetÑAn input that is used to asynchronously initialize the test controller and select the
JTAG-compliant mode of operation. The TRST pin has an internal pullup resistor.
DSP_DE Test Data OutputÑA bidirectional pin used as an input to asynchronously initialize the test controller.
15.1.2 DSP TAP Controller
The DSP TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is a synchronous state machine that controls the operation of the JTAG
logic. A diagram of the TAP controller state machine is shown in Figure 15-3. The value
shown adjacent to each arc represents the value of the TMS signal sampled on the rising edge of TCK signal. For a description of the TAP controller states, refer to the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture.
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DSP56600 Core JTAG Operation
1
Test-Logic-Reset
0
Run-Test/Idle
0
1
0
1
Select-DR-Scan
0
Capture-DR
0
Shift-DR
1
Exit1-DR
0
Pause-DR
Exit2-DR
1
1
Update-DR
1 0
1
0
1
0
0
1
Select-IR-Scan
0
Capture-IR
0
Shift-IR
1
Exit1-IR
Pause-IR
0
1
Exit2-IR
1
Update-IR
1
0
1
0
1
0
Figure 15-3. TAP Controller State Machine
15.1.3 Instruction Register
The DSP JTAG implementation includes a 4-bit instruction register without parity
consisting of a shift register with four parallel outputs. Figure 15-4 shows the Instruction
Register configuration.
B3 B2 B1 B0
Figure 15-4. JTAG Instruction Register
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DSP56600 Core JTAG Operation
15.1.3.1 Instruction Register Operation
Data is transferred from the shift register to the parallel outputs during the Update-IR controller state. The four bits are used to decode the eight unique instructions shown in
0
0
B3
0
0
0
0
0
0
1
Table 15-2. JTAG Instructions
Code
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
1000Ð1110
1 1
Instruction
0
1
B0
0
1
0
1
0
1
1
EXTEST ÑPerform external testing for circuit-board electrical continuity using boundary scan operations.
SAMPLE/PRELOAD ÑSample the DSP56652 device system pins during operation and transparently shift out the result in the BSR. Preload values to output pins prior to invoking the EXTEST instruction.
IDCODE ÑQuery identification information (manufacturer, part number and version) from an DSP core-based device.
ENABLE_MCU_ONCE ÑProvide a means of accessing the MCU OnCE controller and circuits to control a target system.
HI-Z ÑDisable the output drive to pins during circuit-board testing.
CLAMP ÑForce test data onto the outputs of the device while replacing its boundary-scan register in the serial data path with a single bit register.
ENABLE_DSP_ONCE ÑProvide a means of accessing the DSP OnCE controller and circuits to control a target system.
DSP_DEBUG_REQUEST ÑProvide a means of entering the DSP into Debug Mode of operation.
Reserved for future use. Decoded as BYPASS.
BYPASS ÑBypass the DSP56652 chip for a given circuit-board test by effectively reducing the BSR to a single cell.
In the Test-Logic-Reset controller state the Instruction Register is reset to b0010, which is equivalent to the IDCODE instruction.
In the Capture-IR controller state, the two least significant bits of the instruction shift register are parallel-loaded with b01 as required by the standard. The two most significant bits are loaded with the values of the core status bits OS1 and OS0 from the OnCE controller.
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DSP56600 Core JTAG Operation
15.1.3.2 Instruction Descriptions
The DSP core JTAG implementation includes the three mandatory public instructions
(EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the optional CLAMP instruction defined by IEEE 1149.1.
The public instruction HIGHZ provides the capability for disabling all device output drivers. The public instruction
ENABLE_DSP_ONCE enables the JTAG port to communicate with the DSP OnCE circuitry. The public instruction DSP_DEBUG_REQUEST enables the JTAG port to force the DSP core into Debug mode.
15.1.3.2.1 EXTEST (B[3:0]=0000)
The external test (EXTEST) instruction selects the BSR and gives the test logic control of the I/O pins. EXTEST also asserts internal reset for the DSP56652 core system logic to force a predictable internal state while performing external boundary scan operations.
By using the TAP controller, the Instruction Register is capable of:
¥ Scanning user-defined values into the output buffers
¥ Capturing values presented to input pins
¥ Controlling the direction of bidirectional pins
¥ Controlling the output drive of tri-stateable output pins
For more details on the function and use of EXTEST, refer to IEEE 1149.1.
15.1.3.2.2 SAMPLE/PRELOAD (B[3:0]=0001)
The SAMPLE/PRELOAD instruction selects the BSR and the system logic controls the
I/O pins. The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a means to obtain a snapshot of system data and control signals. The snapshot occurs on the rising edge of TCK in the Capture-DR controller state. The data can be observed by shifting it transparently through the BSR.
Note: Since there is no internal synchronization between the JTAG clock (TCK) and the system clock (CLK), the user must provide some form of external synchronization to achieve meaningful results.
The second function of SAMPLE/PRELOAD is to initialize the BSR output cells prior to selection of EXTEST. This initialization ensures that known data appears on the outputs when entering the EXTEST instruction.
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15.1.3.2.3 IDCODE (B[3:0]=0010)
The IDCODE instruction selects the ID register, and the system logic controls the I/O pins. This instruction is provided as a public instruction to allow the manufacturer, part number and version of a component to be determined through the TAP. The ID register is
described in Section 15.2.3 on page 15-10.
Since the bypass register loads a logic 0 at the start of a scan cycle, whereas the ID register loads a logic 1 into its least significant bit, examination of the first bit of data shifted out of a component during a test data scan sequence immediately following exit from
Test-Logic-Reset controller state shows whether such a register is included in the design.
When the IDCODE instruction is selected, the operation of the test logic has no effect on the operation of the on-chip system logic as required by the IEEE 1149.1 standard.
15.1.3.2.4 ENABLE_MCU_ONCE (B[3:0]=0011)
The ENABLE_MCU_ONCE instruction is not included in the IEEE 1149.1 standard. It is provided as a public instruction to allow the user to perform system debug functions.
When the ENABLE_MCU_ONCE instruction is decoded the DSP JTAG controller is set to the BYPASS mode. This is the only function performed by the DSP controller. OnCE operation in the MCU is controlled by the MCUÕs OnCE TAP.
15.1.3.2.5 HIGHZ (B[3:0]=0100)
When the HIGHZ instruction is invoked, all output drivers, including the two-state drivers, are turned off (i.e., put in the high impedance state), and the Bypass Register is selected. The HIGHZ instruction also asserts internal reset for the DSP56652 core system logic to force a predictable internal state while performing external boundary scan operations. In this mode, all internal pullup resistors on all the pins (except the TMS, TDI, and TRST pins) are disabled.
15.1.3.2.6 CLAMP (B[3:0]=0101)
The CLAMP instruction selects the 1-bit Bypass Register as the serial path between TDI and TDO while allowing signals driven from the component pins to be determined from the BSR. During testing of ICs on PCB, it may be necessary to place static guarding values on signals that control operation of logic not involved in the test. If the EXTEST instruction were used for this purpose, the boundary-scan register would be selected and the required guarding signals would be loaded as part of the complete serial data stream shifted in, both at the start of the test and each time a new test pattern is entered. The
CLAMP instruction results in substantially faster testing than the EXTEST instruction because it allows guarding values to be applied using the BSR of the appropriate ICs while selecting their bypass registers. Data in the boundary scan cell remains unchanged until a new instruction is shifted in or the JTAG state machine is set to its reset state. The
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DSP56600 Core JTAG Operation
CLAMP instruction also asserts internal reset for the DSP56652 core system logic to force a predictable internal state while performing external boundary scan operations.
15.1.3.2.7 ENABLE_DSP_ONCE (B[3:0]=0110)
The ENABLE_DSP_ONCE instruction is not included in the IEEE 1149.1 standard. It is provided as a public instruction to allow the user to perform system debug functions.
When the ENABLE_DSP_ONCE instruction is decoded, the TDI and TDO pins are connected directly to the DSP OnCE registers. The particular DSP OnCE register connected between TDI and TDO at a given time is selected by the DSP OnCE controller depending on the DSP OnCE instruction being currently executed. All communication with the DSP OnCE controller is done through the Select-DR-Scan path of the JTAG TAP controller.
15.1.3.2.8 DSP_DEBUG_REQUEST (B[3:0]=0111)
The DSP_DEBUG_REQUEST instruction is not included in the IEEE 1149.1 standard. It is provided as a public instruction to allow the user to generate a debug request signal to the DSP core. When the DSP_DEBUG_REQUEST instruction is decoded, the TDI and
TDO pins are connected to the Instruction Registers. When the TAP is in the Capture-IR state, the OnCE status bits are captured in the Instruction shift register. Thus, the external
JTAG controller must continue to shift in the DSP_DEBUG_REQUEST instruction while polling the status bits that are shifted out until Debug mode is entered and acknowledged by the combination 11 on OS[1:0]. After the acknowledgment of Debug mode is received, the external JTAG controller must issue the ENABLE_DSP_ONCE instruction to allow the user to perform system debug functions.
15.1.3.2.9 BYPASS (B[3:0]=1xxx)
The BYPASS instruction selects the single-bit Bypass Register and restores control of the
I/O pins to system logic. This creates a shift-register path from TDI through the Bypass
Register to TDO, circumventing the BSR. This instruction is used to enhance test efficiency when a component other than the DSP56652 becomes the device under test.
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Test Registers
15.2 Test Registers
The DSP core implementation includes three test registersÑa Boundary Scan Register
(BSR), a 1-bit Bypass Register, and a 32-bit Identification Register (ID).
15.2.1 Boundary Scan Register (BSR)
The Boundary Scan Register (BSR) in the DSP core JTAG implementation contains bits for all device signal and clock pins and associated control signals. In addition, the BSR contains a data direction control bit for each bidirectional pin. Boundary scan bit definitions are provided in the Boundary Scan Description Language (BSDL) listing in
Appendix C.
Note: As a compliance enable pin, MCU_DE is not included in the BSR definition.
15.2.2 Bypass Register
The Bypass Register allows the serial data path to circumvent the DSP BSR. It is activated by the HIGHZ, CLAMP, and BYPASS instructions. When the Bypass Register is selected, the shift-register stage is set to a logic zero on the rising edge of TCK in the
Capture-DR controller state. Therefore, the first bit to be shifted out after selecting the
Bypass Register is always a logic zero. A drawing of the Bypass Register is shown in
Shift DR
From TDI
0
G1
1
Mux
1
D
C
To TDO
CLOCKDR
Figure 15-5. JTAG Bypass Register
15.2.3 Identification Register
The ID register contains the manufacturer, part number and version of the DSP56652. It is read by invoking the IDCODE command. It can be used to determine the manufacturer of a component on a board when multiple sourcing is used. Conforming to the IEEE 1149.1 standard in this way allows a system diagnostic controller to determine the type of component in each location through blind interrogation. This information is also available for factory process monitoring and for failure mode analysis of assembled boards.
MotorolaÕs Manufacturer Identity is b00000001110. The Customer Part Number consists of two parts: Motorola Design Center Number (bits 27:22) and a sequence number (bits
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DSP56652 JTAG Port Restrictions
21:12). The sequence number is divided into two parts: Core Number (bits 21:17) and
Chip Derivative Number (bits 16:12). Motorola Semiconductor Israel (MSIL) Design
Center Number is b000110 and DSP Core Number is b00010. Figure 15-6 shows the ID
register configuration.
31 28 27
Version Number
22 21 17 16
Customer Part Number
12 11
Manufacturer Identity Number
1 0
Design Center Number Core Number Derivative Number
0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1
Figure 15-6. JTAG ID Register
15.3 DSP56652 JTAG Port Restrictions
This section describes operation restrictions regarding the DSP56652 JTAG port in normal, test, and low-power modes.
15.3.1 Normal Operation
¥ JTAG transparencyÑ To ensure that the JTAG test logic is kept transparent to the system logic in normal operation, the JTAG TAP controller must be initialized and kept in the Test-Logic-Reset controller state. The controller can be forced into
Test-Logic-Reset by asserting TRST externally at power-up reset. The controller will remain in this state as long as TMS is not driven low.
¥ Connecting the TCK pinÑ The TCK pin does not have an on-board pullup resistor, and should be tied to a logic high or low during normal operation.
15.3.2 Test Modes
¥ Signal contention in circuit-board testingÑ The control afforded by the output enable signals using the BSR and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. The user must avoid situations in which the DSP56652 output drivers are enabled into actively driven networks.
¥ Executing the EXTEST instructionÑ The EXTEST instruction can be performed only after power-up or regular hardware reset while EXTAL is provided. Then during the execution of EXTEST, EXTAL can remain inactive.
15.3.3 STOP Mode
¥ Entering STOPÑ The TAP controller must be in the Test-Logic-Reset state to enter and remain in STOP mode.
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MCU TAP Controller
¥ Minimizing power consumptionÑ The TMS and TDI pins include on-chip pullup resistors. In STOP mode, these two pins should remain either unconnected or connected to V
CC to achieve minimal power consumption. Also, the TCK input is not blocked in STOP mode and should be externally connected to V
CC
or ground.
15.4 MCU TAP Controller
The MCU contains a TAP controller to provide MCU OnCE support. It is bypassed in
JTAG-compliant mode. The MCU OnCE operating mode can be selected in two ways:
¥ Assertion of the MCU_DE line while the TAP controllers are in the
Test-Logic-Reset state and the TRST input is deasserted.
¥ Shifting the ENABLE_MCU_ONCE command into the DSP TAP controller.
In the MCU OnCE mode, the MCU and DSP TAP controllers are serially linked. The TDI pin drives the MCU TAP controller TDI input, and the MCU TAP controller TDO output drives the DSP TAP controller TDI input. The combined Instruction Registers (IRs) and
Data Registers (DRÕs) of the two controllers are connected, effectively allowing both to be read or written from a single serial input stream. The TMS, TRST, and TCK inputs of the two controllers are connected together, forcing an identical sequence of state transitions to occur within the individual TAP controllers.
To return from the MCU OnCE configuration to JTAG-compliant mode, deassert the
MCU_DE signal and assert TRST.
15.4.1 Entering MCU OnCE Mode via JTAG Control
Table 15-3 shows the TMS sequencing for entering MCU OnCE mode from
JTAG-compliant mode by shifting the ENABLE_MCU_ONCE command into the DSP
TAP controller.
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MCU TAP Controller
Step g h e f j i c d a b k l
TMS
0
0
0
0
0
1
1
1
1
0
1
0
Table 15-3. Entering MCU OnCE Mode
JTAG State OnCE Note
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Shift-IR
Shift-IR
Shift-IR
Exit1-IR
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Capture DSP core status bits
The 4 bits of the JTAG
ENABLE_MCU_ONCE instruction (0b0011) are shifted into the DSP instruction register
Update-IR
Run-Test/Idle
OnCE Enabled
OnCE Enabled
At this point, the IR section of the DSP is ready to be loaded. The MCU TAP controller shadow logic is ready to reset the
JTAG/OnCE signal.
MCU OnCE mode is enabled.
MCU OnCE mode is enabled.
Note: When the MCU OnCE mode is enabled, the JTAG IR becomes the concatenation of the DSP IR (4 bits) and the MCU IR (8 bits). Subsequent shifts into the JTAG IR should be 12 bits in length.
15.4.2 Release from Debug Mode for DSP and MCU
Table 15-4 shows the TMS sequencing for simultaneously releasing the MCU and DSP
from Debug mode, assuming all internal states have been restored to both cores.
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MCU TAP Controller x y z z s t u v v w
Step o p m n q r k l j i g h e f c d a b
Table 15-4. Releasing the MCU and DSP from Debug Modes
OnCE Note TMS
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
1
JTAG State
Shift-IR
Shift-IR
Shift-IR
Shift-IR
Shift-IR
Shift-IR
Shift-IR
Shift-IR
Shift-IR
Exit1-IR
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Shift-IR
Shift-IR
Update-IR
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Idle
Capture DSP core status bits
The 4 bits of the JTAG
ENABLE_DSP_ONCE instruction
(0b0110) are shifted into the combined
DSP + MCU instruction register
The remaining 8 bits of the MCU OnCE instruction Òread no register selected + go + exitÓ (0b11101100) are shifted into the combined DSP + MCU IR
At this point, both IR sections are ready to be loaded, the MCU with Òread no register selected + go + exitÓ, the DSP with ÒEnable DSP OnCEÓ
OnCE is enabled for the DSP (already enabled for the MCU)
1
0
0
Select-DR-Scan
Capture-DR
Shift-DR
Idle
Idle
Idle
0
..................................................................
Shift-DR Idle
0 Shift-DR Idle
The 8 bits of the DSP OnCE command
Òread no register selected + go + exitÓ
(0b11111111) are shifted in
A single bit of bypass data corresponding to the MCU portion of the combined DR is shifted in
1
1
Exit1-DR
Update-DR
Idle
Idle Following this update, both OnCE control blocks release their respective cores
0
0
Run-Test/Idle
................................................
Idle
Run-Test/Idle Idle
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Appendix A
DSP56652 DSP Bootloader
The DSP56652 DSP Bootloader is a small program residing in the DSP program ROM that is executed when the DSP exits the reset state. The purpose of the bootloader is to provide MCU-DSP communication to enable the MCU to download a DSP program to the
DSP program RAM through the MCU-DSP Interface (MDI). This appendix describes the various protocols available in the bootloader to communicate with the DSP56652 and how a protocol is selected. It also provides a listing of the bootloader program.
A.1 Boot Modes
The user can select one of the following three protocols, or modes, to use to download code for the DSP:
¥ Mode A: Normal MDI boot mode implements a protocol incorporating MDI shared memory and messaging registers that enables the user to upload and download data to or from any address in program, X, or Y memory, test the
512-byte program RAM, and start the DSP from any address in program memory.
¥ Mode B: MDI shared memory boot mode allows only downloading to program
RAM using only the MDI shared memory to transfer data. The DSP program must start from program RAM address $0000. Some synchronization between the MCU and DSP is required.
¥ Mode C: MDI messaging unit boot mode allows only downloading to program
RAM using only the MDI messaging unit registers to transfer data. The DSP program must start from program RAM address $0000. No MCU-DSP synchronization is required.
The bootloader reads the SAP STDA pin and the BBP STDB pin (configured as GP inputs
at reset) to determine the boot mode, as shown Table A-1 on page A-2. The user must
supply pull-up and/or pull-down resisters to STDA and STDB to ensure that the DSP enters the desired mode.
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STDA
Table A-1. DSP56652 Boot Modes
STDB Boot Mode
1
0
1
0
0
0
1
1
Mode A: Normal MDI boot mode.
Mode B: MDI shared memory boot mode.
Mode C: MDI messaging unit boot mode.
Reserved for Motorola test modes
A.2 Mode A: Normal MDI Boot
The normal boot mode uses MDI communication between the DSP and MCU to implement the following functions:
¥ Download to the DSP program, X, or Y RAM.
¥ Upload from the DSP program, X, or Y memories (RAM or ROM).
¥ Run diagnostic tests on the DSP 0.5K program RAM.
¥ Start the DSP at a given program address (jump to a given address)
After entering the normal boot mode, the DSP waits until a message has arrived from the
MCU. When it receives a message, the DSP performs the necessary actions and in most cases returns an acknowledgment message to the MCU. The DSP remains in the normal boot mode, waiting for and executing MCU messages, until the MCU requests the DSP to exit the boot mode and start the userÕs application.
A.2.1 Short and Long Messages
The normal boot mode uses both the MDI messaging unit registers and the MDI shared memory for message transfers. Shorter messages are conveyed in one or both messaging unit registers
1
. For longer messages (such as downloading a program to the DSP),
MDI_R0 is used to point to the rest of the message in the MDI shared memory.
The format for short messages is shown in Figure A-1 on page A-3. The most significant
bit of MDI_R0 is used to indicate whether the message is a short message (S=1) or a long message (S=0). The eight least significant bits of MDI_R0 hold the message opcode. Bits
A-2
1.For simplicity, the messaging unit registers (MTR0, MTR1, MRR0, and MRR1 for the MCU transmit and receive registers, respectively; DTR0, DTR1, DRR0, and DRR1 for the DSP transmit and receive registers, respectively) are referred to as MDI_R0 and MDI_R1.
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Mode A: Normal MDI Boot
8Ð13 can contain message information if needed. If the short message uses the MDI_R1 register as well, the DW bit (bit 14) in MDI_R0 should be set.
MDI_R0
15 14
S=1 DW
13 information
MDI Messaging Unit Registers
8 7 message opcode
0
MDI_R1 information (if used, set DW=1)
Figure A-1. Short Message Format
The format for long messages is shown in Figure A-2. The long message is indicated by
clearing the S bit in MDI_R0.
The ten least significant bits of MDI_R0 indicate an offset address into the MDI shared memory. Note that this field is 10 bits wide so that it can point to an offset anywhere in the
1-Kword MDI shared memory space. The first entry in the MDI shared memory at the indicated offset location is the message opcode. This is followed by as many information words as necessary.
MDI_R0
15
S=0
14
MCU address
MCU_MDI_BASE+2*offset unused
10
MDI Messaging Unit Registers
9 mdi_offset
MDI Shared Memory message opcode information
¥
¥¥ information
Figure A-2. Long Message Format
0
DSP address
DSP_MDI_BASE+offset
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A.2.2 Message Descriptions
Table A-2 summarizes the messages that the bootloader supports. Initially, the bootloader
is in an idle loop awaiting a message from the MCU. When it receives a message, the DSP processes and executes the command, then sends an acknowledgment message back to the
MCU. The only exception to this procedure is the start_application.request message, for which there is no acknowledgment message. If the DSP receives a message it does not recognize, it returns a special invalid opcode response.
Message From
MCU to DSP memory_write.request
memory_read.request
memory_check.request
start_application.request
(invalid message)
Table A-2. Message Summary
Message
Opcode
Number
Long or
Short
1
2
3
4 other long long long long either
Acknowledgment Message
From DSP to MCU
Message
Opcode
Number
Long or
Short memory_write.response
memory_read.response
memory_check.response
(none) invalid_opcode.response
1
2
3
NA
4 short long long
NA short
The following sections describe the structure of each message.
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Mode A: Normal MDI Boot
A.2.2.1 memory_write.request
memory_write.request
is a long message from the MCU to the DSP used to write to the
DSP program or data RAM. The structure of this message is shown in Figure A-3. The
first entry in MDI memory is the message opcode. The second entry contains the number of words to write to DSP memory. The third entry contains two fields, XYP and source address offset. The XYP field, which occupies the upper two bits of the entry, determines
which memory space to access, as shown in Table A-3. The source address offset occupies
the lowest ten bits of the third entry and indicates the location in the MDI memory space of the data to be written to the DSP. The last entry of the message contains the DSP destination address to which the data is to be written. In most cases, the source address offset points to the word following the destination address, i.e., source_address_offset = mdi_offset + 4. However, the protocol allows for the data to be located anywhere in the
MDI shared memory space.
MDI_R0
15
S=0
14 13
MCU address
MCU_MDI_BASE+2*offset unused
XYP unused
10
MDI Messaging Unit Registers
9 mdi_offset
MDI Shared Memory memory_write.request
# of DSP words to write source_address_offset destination address
0
DSP address
DSP_MDI_BASE+offset
MCU_MDI_BASE+
2*source_address_offset
DSP_MDI_BASE+ source_address_offset data
¥
¥¥ data
Figure A-3. Format of memory_write.request Message
XYP
00
01
10
Table A-3. XYP Field
DSP Memory Space
X
Y
P
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A.2.2.2 memory_write.response
memory_write.response
is a short message from the DSP to the MCU in response to a
memory_write.request message. The format of this message is shown in Figure A-4. Note
that the MDI_R1 register is not used. A RET field of 0 indicates a successful memory_write.request; if the RET field is 1, the memory_write.request failed. Thus, since memory_write.response opcode is $1, the MCU should expect the DSP to respond to a successful memory write with MDI_R0 = $8001.
MDI_R0
15 14
S=1 DW=0
13
MDI Messaging Unit Registers
8 7
RET (0=success, 1=failure) memory_write.response
MDI_R1 not used
Figure A-4. Format of message_write.response Message
0
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Mode A: Normal MDI Boot
A.2.2.3 memory_read.request
memory_read.request
is a long message from the MCU to the DSP requesting an upload of
data from the program, X, or Y data space. The format of this message is shown in Figure
A-5. The next entry in MDI memory following the
memory_read.request
opcode is the number of DSP words to read. The third entry contains two fields, XYP and destination address offset. The XYP field determines which memory space of the read, as shown in
Figure A-3 on page A-5. The destination address offset contains the location in MDI
shared memory at which the DSP stores the data it reads. The last entry, source address, indicates the address in DSP program, X, or Y memory space of the data to be read.
The choice of destination address offset is arbitrary, but care should be taken to ensure that the DSP does not overwrite any of the words in the original message.
Figure A-5. Format of memory_read.request Message
14 13 10
MDI Messaging Unit Registers
9
MDI_R0
15
S=0
MCU address
MCU_MDI_BASE+2*offset unused
MDI Shared Memory mdi_offset
0
DSP address
DSP_MDI_BASE+offset memory_read.request
# of DSP words to read
XYP unused dest_address_offset source address
MCU_MDI_BASE+
2*dest_address_offset
DSP_MDI_BASE+ dest_address_offset
DSP uses this location for its long reply message
¥
¥¥
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A.2.2.4 memory_read.response
memory_read.response is a long message from the DSP to the MCU in response to a memory_read.request
message. The format of this long message is shown in Figure A-6.
Note that this long message is located in MDI shared memory at the location defined by the destination address field of the memory_read.request
message.
The entry following the memory_write.request
opcode in MDI memory is the return codeÑ$0000 indicates success, and $0001 indicates failure. Failure can only result from the invalid value of 11b to the XYP field in the memory_read.request
message. If the return code indicates a failure, the DSP does not write the remaining entries in the message. The third entry in the memory_read.response message is the number of DSP words read. The fourth entry contains two fields. The upper two bits indicate the memory
space accessed according to Table A-3 on page A-5. The lower ten bits indicate the
location in MDI shared memory where the DSP has stored the read data. In all cases, the bootloader defines the destination address offset to point to the word following the source address. Therefore, dest_address_offset = mdi_offset + 5. The last entry, source address, indicates the DSP program, X, or Y space address from which the data has been read.
MDI_R0
15
S=0
14 13
MCU address
MCU_MDI_BASE+2*offset unused
XYP
10
MDI Messaging Unit Registers
9
MDI Shared Memory mdi_offset memory_read.response(2) return code (0=success, 1=invalid memory space specified)
# of DSP words read unused dest_address_offset source address
0
DSP address
DSP_MDI_BASE+offset
MCU_MDI_BASE+
2*dest_address_offset
DSP_MDI_BASE+ dest_address_offset data
¥
¥¥ data
Figure A-6. Format of memory_read.response Message
A.2.2.5 memory_check.request
memory_check.request is a long message from the MCU to the DSP requesting a test of the DSP 0.5k program RAM.
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Mode A: Normal MDI Boot
Note: Although this protocol supports provisions to test all of the memory spaces, the bootloader only implements testing of the 0.5k program RAM space.
The format of this message is shown in Figure A-7. The entry following the opcode in
shared memory contains two fields. The upper three bits specify the RAM space to be tested (always Ò100Ó for the bootloader), and the lower ten bits specify the MDI address the at which DSP stores its long reply message.
Normally, the return address offset points to the next word, so that return_address_offset = mdi_offset + 2. However, the protocol allows for the long reply message to be located anywhere in MDI memory.
MDI_R0
15
S=0
14 13
MCU address
MCU_MDI_BASE+2*offset
12 unused unused
10
MDI Messaging Unit Registers
9 mdi_offset
MDI Shared Memory memory_check.request
result_address_offset RAM
MCU_MDI_BASE+
2*dest_address_offset
DSP uses this location for its long reply message
0
DSP address
DSP_MDI_BASE+offset
DSP_MDI_BASE+ dest_address_offset
Figure A-7. Format of memory_check.request Message
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A.2.2.6 memory_check.response
memory_check.response
is a long message from the DSP to the MCU in response to a memory_check.request
message. The format of this message is shown in Figure A-8. Note
that this message resides in MDI shared memory location specified in the result_address_offset field of the memory_check.request
message.
The entry in MDI shared memory following the memory_check.response
opcode is the return codeÑ$0000 indicates success, and $0001 indicates failure. The following entry is the failure address if the memory check has failed, and zero if the check is successful.
MDI_R0
15
S=0
14
MCU address
MCU_MDI_BASE+2*offset unused
10
MDI Messaging Unit Registers
9 mdi_offset
MDI Shared Memory memory_check.request
return code (0=success, 1=failure)
(failure address if failure, 0 otherwise)
0
DSP address
DSP_MDI_BASE+offset
Figure A-8. Format of memory_check.request Message
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Mode A: Normal MDI Boot
A.2.2.7 start_application.request
start_application.request
is a long message from the MCU to the DSP requesting the
DSP to leave the boot mode and begin executing the user program The format of this
message is shown in Figure A-9. The entry following the
start_application.request
opcode in MDI shared memory is the starting address of the user program in program memory. When the DSP receives this message, it jumps to the specified program address location and begins executing code at that location. The DSP does not generate a response to this message.
MDI_R0
15
S=0
14
MCU address
MCU_MDI_BASE+2*offset unused
10
MDI Messaging Unit Registers
9 mdi_offset
MDI Shared Memory start_application.request
starting address
0
DSP address
DSP_MDI_BASE+offset
Figure A-9. Format of start_application.request Message
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A.2.2.8 invalid_opcode.response
invalid_opcode.response
is a short message from the DSP to the MCU in response to any
unrecognized message opcode. The format of this message is shown in Figure A-10. The
RET field in MDI_R0 is used to indicate the length of the unrecognized message (0 = long, 1 = short). The unrecognized opcode is returned in the MDI_R1 register.
MDI_R0
15 14
S=1 DW=1
13
MDI Messaging Unit Registers
8 7
RET (0=long, 1=short) invalid_opcode.response
MDI_R1 bad opcode
Figure A-10. Format of invalid_opcode.response Message
0
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Mode A: Normal MDI Boot
A.2.3 Comments on Normal Boot Mode Usage
This section describes several items to keep in mind when using the normal boot mode.
1.
Downloads and uploads of DSP program memory require two words in the
MDI shared memory space because DSP program words are 24 bits wide. The most significant portion (upper 8 bits) should always we stored in the lower memory address, followed by the least significant (lower 16 bits) in the next higher memory
address, as illustrated in Figure A-11.
23 16 15 0
DSP
Program Word
7 0
MDI Word at Lower Address
15 0
MDI Word at Lower Address
Figure A-11. Mapping of DSP Program Memory words to MDI message words
2.
MDI shared memory size is only 1 Kword.
Data transfers larger than 1 Kword must be split into multiple uploads or downloads.
3.
The DSP does not perform any error checking.
MCU software is responsible for ensuring that addresses are within the MDI memory space.
4.
Writing MDI_R0 should be the final step taken to initiate a message.
This action affects bits in the MDI status register that the DSP bootloader program polls to determines when a new message has been received in MDI_R0.
5.
Ensure that the response to a message does not overwrite that message.
Each
MCU message that invokes a long message reply from the DSP defines the offset in MDI shared memory where the DSP stores the response. Care should be taken so that no portion of the reply overwrites any portion of the original message. The
DSP may need to access the original message while it is writing its response message.
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A.2.4 Example of Program Download and Execution
Example A-1 provides a short outline in pseudo-C code for downloading and starting a
program in normal boot mode. In this example, all long messages start at the beginning of
MDI shared memory, the DSP program exists in a long array called dsp_program[]
,
the program length is contained in a variable called program_length , and the program starting address is dsp_program_address .
Example A-1. Normal Boot unsigned short *mdimem = (unsigned short *)MDI_MEM_ADDR; unsigned short *MTR0 = (unsigned short *)MDI_MTR0; volatile unsigned short *MRR0 = (unsigned short *)MDI_MRR0; volatile unsigned short *MSR = (unsigned short *)MDI_MSR;
/* prepare to download to the DSP */
/* write long message info in shared mem */
*mdimem++ = memory_write.request;
*mdimem++ = program_length;
*mdimem++ = (%10<<14) + 4; /* %10: download to P memory */
/* 4: data starts following
this header information */
*mdimem++ = dsp_program_address;
/* write dsp program to MDI most significant part first */ for(i=0; i<program_length; i++)
{
*mdimem++ = (unsigned short)(dsp_program[i]>>16);
*mdimem++ = (unsigned short)dsp_program[i];
}
/* initiate this long message by writing to MTR0 register */
*MTR0 = 0; /* msb=0 -> long message */
/* lsbs=0 -> offset = 0 */
/* wait for acknowledgement from DSP by polling the MRF0 bit in MSR */ while(MSR&MRF0==0)
;
/* read and test the short message memory_write.response*/ if(MRR0 != $8001) exit(1); /* DSP write error */
/* start the DSP application */
/* reset the mdi memory pointer to beginning of mdi */
*mdimem = (unsigned short *)MDI_MEM_ADDR;
/* write the long message header */
*mdimem++ = start_application.request;
*mdimem++ = dsp_program_address;
/* initiate the long message by writing to MTR0 reg */
*MTR0 = 0; /* msb=0 -> long message */
/* lsbs=0 -> offset = 0 */
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Mode B: Shared Memory Boot
A.3 Mode B: Shared Memory Boot
The shared memory boot mode can be used if all that is required is to fill the lower 0.5K
DSP program RAM and begin execution at DSP program address P:$0000. The MDI memory values are undefined at reset, so this boot mode requires a bit of MCU-DSP synchronization prior downloading the code. The first two 16-bit words in the shared MDI memory space are reserved for synchronization messages. To download DSP code in the boot mode, the MCU must take the following steps:
1. Download up to 511 DSP program words to the MDI memory starting at the third
MDI memory location. Note that the most signification portion is stored first.
2. Write synchronization word 1 ($1234) to MDI shared memory location 0.
3. Wait for the DSP to acknowledge this by writing confirmation word 1 ($abcd) to
MDI shared memory location 1.
4. Write synchronization word 2 ($5678) to MDI shared memory location 0.
5. Wait for the DSP to acknowledge this by writing confirmation word 2 ($cdef) to
MDI shared memory location 1.
6. The DSP should now be reading the program from the MDI memory locations and jump to P:$0000 after the last word has been read.
These steps are demonstrated in the pseudo-C program in Example A-2.
Example A-2. Shared Memory Boot unsigned short *mdimem = (unsigned short *)MDI_MEM_ADDR+2; volatile unsigned short *mdimem0 = (unsigned short *)MDI_MEM_ADDR; volatile unsigned short *mdimem1 = (unsigned short *)MDI_MEM_ADDR+1;
/* write 511 dsp program words starting at MDI memory offset 2 */
/* -- write msb portion first */ for(i=0; i<511; i++)
{
*mdimem++ = (unsigned short)(dsp_program[i]>>16);
*mdimem++ = (unsigned short)dsp_program[i];
}
/* write syn message 1 */
*mdimem0 = $1234;
/* wait for confirm message 1 */ while(*mdimem1 != $abcd)
;
/* write sync message 2 */
*mdimem0 = $5678;
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Mode C: Messaging Unit Boot
/* wait for confirm message 2 */ while(*mdimem1 != $cdef)
;
A.4 Mode C: Messaging Unit Boot
The messing unit memory boot mode can also be used if all that is required is to fill the lower 0.5k DSP program RAM and begin execution at DSP program address P:$0000.
This mode uses the MDI messaging unit registers so there is no need for additional synchronization logic. In this mode, the MCU should write a maximum of 511 DSP program words, one at a time, to the two messaging unit registers. The most significant portion of each word should be written to MDI_R0 and the least significant portion to
MDI_R1. The DSP reads MDI_R0 first, so the MCU should write MDI_R0 first. Also, the MCU should poll the transmit empty bits in the MDI status register to ensure that the
DSP has read each register before a new value is written.
Example A-2 is pseudo-C program of a boot using the MDI messaging unit.
Example A-3. Messaging Unit Boot unsigned short *mtr0 = (unsigned short *)MDI_MTR0; unsigned short *mtr1 = (unsigned short *)MDI_MTR1; volatile unsigned short *msr = (unsigned short *)MDI_MSR;
/* write 511 dsp program words starting at MDI memory offset 2 */
/* -- write msb portion first */ for(i=0; i<511; i++)
{ while(*msr&MSR_MTE0==0)
;
*mtr0 = (unsigned short)(dsp_program[i]>>16); while(*msr&MSR_MTE1 == 0)
;
*mtr1 = (unsigned short)dsp_program[i];
}
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Bootstrap Program
A.5 Bootstrap Program
The following bootstrap source code is programmed into the DSP56652 at the factory.
Use this listing to develop external ROM programming for DSP56652 applications.
Note: When compiling source code, the correct X I/O equate and interrupt equate files
(specified by ioequ.asm and intequ.asm) must be used. Listings for these files are provided in Appendix B.
;----------------------------------------------------------------------------
;
; DSP BOOT LOADER CODE FOR 56652
;
; Boot mode is determined from reading the STDA, STDB pins:
; STDA STDB
; ---- ----
; 1 1 boot mode A, normal boot mode
; 0 1 boot mode B, shared memory boot mode
; 1 0 boot mode C, messaging unit boot mode
; 0 0 reserved for SPS test modes
;
;---------------------------------------------------------------------------section
; long message header long_header
BOOTSTRAP
;
;;;;;;;;;;;; BOOT MODE A MESSAGE EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;;;
; equ $4000
; message opcodes mem_write mem_read equ $0001 equ $0002 mem_check equ $0003 start_app inval_opc equ $0004 equ $0004
; long read/write memory codes (bits 14,15) mem_x equ $0000 ;%00 mem_y mem_p equ $4000 equ $8000
;%01
;%10 mem_invalid equ $C000 ;%11
; long memory check mem space codes (bits 13,14,15) pram512 equ $8000 ;%100
; response messages success fail equ fail_inv_mem equ equ 0
1
2
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Bootstrap Program
; short response messages write_success equ (1<<15)+(success<<8)+mem_write write_fail inval_long_msg inval_short_msg equ equ
(1<<15)+(fail<<8)+mem_write
$C000+inval_opc equ $C100+inval_opc
;
;;;;;;;;;;;; BOOT MODE B EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;;;
; prot_B_sig_0 prot_B_sig_1 prot_B_conf_0 prot_B_conf_1 equ equ $5678 equ
$1234
$abcd equ $cdef
;
;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;;
;
; bus switch
BPMRH equ
BPMRL
BPMRG equ equ
; MDI
MDI_base equ
DRR0
DRR1
DTR0
DTR1
DSR
DCR
; DSR bits
DF0
DF1
DF2
DRF1
DRF0
DTE1
DTE0 equ equ equ equ equ equ equ equ equ equ equ equ equ
$FFF2; bus switch program memory register high
$FFF3; bus switch program memory register low
$FFF4; bus switch program memory register (24bits)
$1C00; base dp ram address
$FF8F; dsp receive register 0
$FF8E; dsp receive register 1
$FF8D; dsp transmit register 0
$FF8C; dsp transmit register 1
$FF8B; dsp status register
$FF8A; dsp control register
0 ; DSR flag 0
1 ; DSR flag 1
2 ; DSR flag 2
12 ; DSR receive reg 1 full
13 ; DSR receive reg 0 full
14 ; DSR transmit reg 1 empty
15 ; DSR transmit reg 0 empty
; SAP/portA and BBP/portB
PCRA equ $FFBF; SAP GPIO control register
PRRA
PDRA equ equ
$FFBE; SAP GPIO data direction register
$FFBD; SAP GPIO data register
STDA
PCRB
PRRB
PDRB
STDB equ equ equ equ equ
5
5
; used as port A gpio pin #5
$FFAF; BBP GPIO control register
$FFAE; BBP GPIO data direction register
$FFAD; BBP GPIO data register
; used as port B gpio pin #5
;************************************************************************
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Bootstrap Program
; Begining of code
;************************************************************************ org P:$800 ; bootloader begins at start of ROM
START
; configured SAP and BBP as gpio inputs move #<$80,r0 movep movep r0,x:PCRA; gpio, PEN bit set, others cleared r0,x:PCRB; gpio, PEN bit set, others cleared move movep movep nop
#0,x0 x0,x:PRRA; gpio inputs x0,x:PRRB; gpio inputs
; STDA STDB
; ---- ----
; 1 1 boot mode A, normal boot
; 0 1 boot mode B, jump to user ROM
; 1 0 boot mode C, messaging unit boot
; 0 0 SPS modes jset jset
#STDA,x:PDRA,START_BOOT
#STDB,x:PDRB,START_BOOT
; else, continue with SPS code
;************************************************************************
; SPS MODES
;
; Approx 325 words of Program ROM are reserved for SPS test modes
; at this location
;************************************************************************
; code for SPS test modes resides here
;************************************************************************
; boot modes A, B, C
;************************************************************************
START_BOOT
; if we got here, STDA or STDB must have been set jclr #STDA,x:PDRA,START_BOOT_MODE_B jclr #STDB,x:PDRB,START_BOOT_MODE_C
; else, both set, continue with BOOT_MODE_A
;************************************************************************
; BOOT MODE A ÒNORMALÓ MoDE
;************************************************************************
START_BOOT_MODE_A
_wait jclr #DRF0,x:DSR,_wait; wait till DRR0 is full
; read message from DRR0 movep x:DRR0,x0
; short or long message?
jclr #15,x0,long_message
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Bootstrap Program
; else itÕs a short message
; handle short messages short_message
; there are currently no allowed short messages
; return an invalid message indication move jmp
#>inval_short_msg,x1
<invalid_message long_message
; handle long messages
; retrieve long message opcode move x0,a and add move move
#$03FF,a; save only lower 10 bits (offset)
#MDI_base,a; add MDI base address a1,r0 x:(r0)+,x0; x0=long message opcode
; which long message is it? move x0,a cmp jeq
#mem_write,a
<memory_write cmp jeq cmp jeq cmp jeq
#mem_read,a
<memory_read
#start_app,a
<start_application
#mem_check,a
<memory_check
; if it didnÕt match any of these, itÕs invalid long message move #>inval_long_msg,x1 invalid_message
; return a invalid message indication
_wait1
_wait2 jclr jclr
#DTE0,x:DSR,_wait1; donÕt clobber a previous message
#DTE1,x:DSR,_wait2; donÕt clobber a previous message movep movep jmp x0,x:DTR1 x1,x:DTR0
; put invalid data in DTR1
; invalid_opcode.indication in DTR0
<START_BOOT_MODE_A; and return to start
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; start memory_write.request
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; memory_write jsr jmp
<download_from_mcore
<START_BOOT_MODE_A
;--------------------------------------------------------
; download_from_mcore
; This subroutine is used to perform
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Bootstrap Program
; memory downloads from the M.CORE to the DSP.
;
; Inputs:
; r0 -- points to MDI memory, 1 location
; past memory_write.request
;
; Registers Used :
; R M N A B X Y
; 0 c - c c c c -
; 1 c - c c - - -
; 2 - - - c -
; 3 - - -
; 4 - - -
; 5 - - - c = changed
; 6 - - -
; 7 - - -
;-------------------------------------------------------xdef download_from_mcore download_from_mcore
; retrieve number of ÒwordsÓ to process move x:(r0)+,n0; n0=#words
; retrieve memory space/MDI address move x:(r0)+,x0 move and x0,a
#$03FF,a; keep lower 10 bits add move
#MDI_base,a a1,r1 ; r1=MDI memory address
; retrieve DSP memory address move x:(r0),r0; r0=DSP memory address
; which memory space?
move x0,a and cmp
#$C000,a; keep only upper 2 bits
#mem_x,a jeq cmp jeq cmp
<mem_write_x
#mem_y,a
<mem_write_y
#mem_p,a jeq <mem_write_p
; if it didnÕt match, itÕs invalid move jmp
#write_fail,b0
<mem_write_return mem_write_x do move move
_end jmp mem_write_y n0,_end x:(r1)+,x0 x0,x:(r0)+
<mem_write_success
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Bootstrap Program
_end do move move jmp n0,_end x:(r1)+,x0 x0,y:(r0)+
<mem_write_success mem_write_p move move do movep movep movep nop
_end
(r1)+
#3,n1
; point to low word first n0,_end x:(r1)-,x:BPMRL ; read data in big-endian x:(r1)+n1,x:BPMRH ; format. This looks odd, x:<<BPMRG,p:(r0)+ ; but itÕs faster and more
; efficient
; continue with mem_write_success mem_write_success
; return memory_write.confirm short message with SUCCESS move #write_success,b0 mem_write_return
; return memory_write.confirm short message with FAIL
_wait jclr movep
#DTE0,x:DSR,_wait; make sure DTR0 is not full b0,x:DTR0 rts
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; end of memory_write.request
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; start memory_read.request
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; memory_read jsr jmp
<upload_to_mcore
<START_BOOT_MODE_A
;--------------------------------------------------------
; upload_to_mcore
; This subroutine is used to perform
; memory uploads from the DSP to the M.CORE.
;
; Inputs:
; r0 -- points to MDI memory, 1 location
; past memory_read.request
;
; Registers Used :
; R M N A B X Y
; 0 c - c c c - -
; 1 c - c c c - -
; 2 - - - c c
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Bootstrap Program
; 3 - - -
; 4 - - -
; 5 - - - c = changed
; 6 - - -
; 7 - - -
;-------------------------------------------------------xdef upload_to_mcore upload_to_mcore
; retrieve number of ÒwordsÓ to process move x:(r0)+,n0; n0=#words
; retrieve memory space/MDI address move x:(r0)+,x0 move and x0,a
#$03FF,a; keep lower 10 bits
; save MDI offset to n1 move add move a1,n1
#MDI_base,a a1,r1 ; r1=MDI memory address
; retrieve DSP memory address move x:(r0),r0; r0=DSP memory address
; write 1st header word move #mem_read,b0 move b0,x:(r1)+; memory_read.indication-long move move move add move move cmp jeq
; which memory space?
move x0,a and cmp
#$C000,a; keep only upper 2 bits
#mem_invalid,a jeq <mem_read_fail
; if it gets here, itÕs a valid memory space
; write (successful) MDI header info move #success,b0 b0,x:(r1)+; return code (success | fail) n0,x:(r1)+; # words x0,b
#5,b ; new MDI address is offset by 5 b1,x:(r1)+; memory space & MDI address r0,x:(r1)+; DSP source address
#mem_x,a
<mem_read_x
; old memory space & MDI address cmp jeq
#mem_y,a
<mem_read_y
; only option left is mem_read_p jmp <mem_read_p mem_read_x do move move
_loop jmp n0,_loop x:(r0)+,x0 x0,x:(r1)+
<mem_read_return
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Bootstrap Program mem_read_y do move move
_loop jmp mem_read_p
_loop do movep movep movep jmp n0,_loop y:(r0)+,x0 x0,x:(r1)+
<mem_read_return n0,_loop p:(r0)+,x:<<BPMRG x:BPMRH,x:(r1)+; store p data in x:BPMRL,x:(r1)+; big-endian format
<mem_read_return mem_read_fail
; write (unsuccessful) MDI header info move move
#fail,b0 b0,x:(r1)+; return code (fail) mem_read_return
; form long message return (same for both success and failure) move or n1,a ; MDI address for long
#long_header,a
_wait jclr movep
#DTE0,x:DSR,_wait; donÕt clobber a previous message a1,x:DTR0 rts
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; end of memory_read.request
;
; start Ò512pramÓ memory_check.request
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; memory_check
; retrieve memory_type and address move x:(r0),x1 move and x1,a1
#$03FF,a; save only lower 10 bits (offset) move add move move a1,n1 ; save offset, needed for return
#MDI_base,a; add MDI base address a1,r1 ; return mdi address
#mem_check,b0; write memory_check.confirm
move move and cmp b0,x:(r1)+ ; as header x1,a
#$e000,a; keep upper 3 bits
#pram512,a jeq <pram_check
; else, itÕs not a valid memory space move #fail_inv_mem,b0; return code - fail invalid memory
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Bootstrap Program move jmp
;
; Òcheck 512 word p-ram spaceÓ
; b0,x:(r1)
<mem_check_return pram_check move #PATTERNS,r3 ; r3 points to p: test patterns do
; up(wB)
#NUM_PATTERNS/4,_loop_o movem p:(r3)+,n4; get BackGround Pattern (high word) movem p:(r3)+,n3; get BackGround Pattern (low word) movep movep n4,x:BPMRH n3,x:BPMRL move #0,r0 rep #512 movep
; r0 points to start of Memory
; fill Memory with BG Pattern: up(wB) x:BPMRG,p:(r0)+
; up(rB,wD,rD) clr clr move a b
#0,r0
;
Motorola do move move movep move movep movep cmp nop brkne movep movep nop movep move movep movep movep move move cmp movem p:(r3)+,n6; get Data Pattern (high word) movem p:(r3)+,n5; get Data Pattern (low word) movep movep n6,x:BPMRH n5,x:BPMRL
#512,_loop_i ; test all locations n3,a0 ; BG Pattern value to A n4,a1 p:(r0),x:BPMRG; read BackGround Pattern -> BPMRG
#$ABCD,n2 ; change gdb ????
x:BPMRL,b0 x:BPMRH,b1 a,b ; was the Memory data as expected???
n5,x:BPMRL n6,x:BPMRH
; restore low byte of DATA from n5
; restore high byte of DATA from n6 x:BPMRG,p:(r0) ; write Data to Memory
#$ABCD,n2 ; change gdb p:(r0),x:BPMRG; read Data Pattern -> BPMRG x:BPMRL,b0 ; read Data Pattern -> B x:BPMRH,b1 n5,a0 n6,a1
; restore low byte of DATA from n5
; restore high byte of DATA from n6 a,b ; was the Memory data as expected???
DSP56652 DSP Bootloader
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Bootstrap Program
_loop_i nop brkne move nop nop brkne nop nop nop
(r0)+
_loop_o move move tne move move
#success,r2
#fail,r4 r4,r2 r2,x:(r1)+ ; write success/fail r0,x:(r1)+ ; write address mem_check_return
; form long message return (same for both success and failure) move or n1,a
#long_header,a
; n1 = offset
_wait jclr movep
#DTE0,x:DSR,_wait; donÕt clobber a previous message a1,x:DTR0 jmp <START_BOOT_MODE_A
; the following patterns are used by boot mode A mem_check.request
BADDR M,8 ; place on modulo boundary for burnin mode
PATTERNS dc dc dc dc
$0055; background pattern high word
$5555 ; background pattern low word
$00AA; data pattern high word
$AAAA; data pattern low word dc dc dc dc
NUM_PATTERNSequ*-PATTERNS
$00CC; background pattern high word
$CCCC ; background pattern low word
$0033; data pattern high word
$3333; data pattern low word
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; end of memory_check.request
;
; start start_application.request
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; start_application move jmp x:(r0),r0 r0
;************************************************************************
; BOOT MODE B Shared memory Mode
;************************************************************************
A-26 DSP56652 UserÕs Manual
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Bootstrap Program
START_BOOT_MODE_B move #MDI_base,r0
; look for protocol_B_signature_0
_wait0 move cmp jne x:(r0),a
#>prot_B_sig_0,a
<_wait0
; reply with protocol_B_confirm_0 move #>prot_B_conf_0,x0 move x0,x:(r0+1)
; look for protocol_B_signature_1
_wait1 move cmp jne x:(r0),a
#prot_B_sig_1,a
<_wait1
; reply with protocol_B_confirm_1 move #prot_B_conf_1,x0 move x0,x:(r0+1)
_end
; okay, do the download move lea
#0,r1 ; start of p: memory to download
(r0+3),r0; MDI_base+3 move do
#3,n0
#511,_end movep movep movep nop x:(r0)-,x:BPMRL ; read data in x:(r0)+n0,x:BPMRH ; big-endian format x:<<BPMRG,p:(r1)+ jmp <0
;************************************************************************
; BOOT MODE C Message Unit Mode
;************************************************************************
START_BOOT_MODE_C
_wait0 move do jclr movep
#0,r0
#511,_loop
#DRF0,x:DSR,_wait0; wait till DRR0 is full x:DRR0,a1
_wait1 jclr movep movep movep nop movep nop
#DRF1,x:DSR,_wait1; wait till DRR1 is full x:DRR1,a0 a0,x:<<BPMRL a1,x:<<BPMRH x:<<BPMRG,p:(r0)+; write to pram512
_loop jmp <0 endsec end
Motorola DSP56652 DSP Bootloader
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A-27
Bootstrap Program
Freescale Semiconductor, Inc.
A-28 DSP56652 UserÕs Manual
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Appendix B
Equates and Header Files
This appendix provides the equates for both the MCU and DSP in the DSP56652, as well as a C include file for the MCU. If code for external bootstrap loading is developed, a file containing this listing called ioequ.asm should be included in the bootstrap executable.
B.1 MCU Equates
//====================================================================
//====================================================================
//
// DSP56651/DSP56652 M.CORE Assembly equates
//
// Revision History:
// 1.0: may 28,
//
1998
//====================================================================
//====================================================================
// 16kb on-chip rom
.equ
mcu_rom_base_address, 0x00000000
.equ
mcu_rom_size,
// 2kb on-chip ram
0x00004000
.equ
mcu_ram_base_address, 0x00100000
.equ
mcu_ram_size, 0x00000800
// peripheral space
.equ
mcu_peripherals_base_address,0x00200000
// 0x00300000 through 0x3fffffff is reserved
// external memory
.equ
.equ
.equ
.equ
.equ
.equ
cs0_base_address, cs1_base_address, cs2_base_address, cs3_base_address, cs4_base_address, cs5_base_address,
0x40000000
0x41000000
0x42000000
0x43000000
0x44000000
0x45000000
// 0x46000000 through 0xffffffff is reserved
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MCU Equates
//====================================================================
// MCU-DSP Interface (MDI) equates
//====================================================================
// general definitions
.equ
mdi_registers_base_address, 0x00202ff0
.equ
mdi_memory_base_address, 0x00202000
// registers of the messaging unit
.equ
mdi_mcvr, 0x2 // MCU-side Command Vector Register
.equ
mdi_mcr,
.equ
mdi_msr,
0x4 // MCU-side Control Register
0x6 // MCU-side Status Register
.equ
mdi_mtr1, 0x8 // MCU-side Transmit Register 1
.equ
mdi_mtr0, 0xa // MCU-side Transmit Register 0
.equ
mdi_mrr1, 0xc // MCU-side Recieve Register 1
.equ
mdi_mrr0, 0xe // MCU-side Receive Register 0
// bits of the MCU-side Command Vector register (MCVR)
.equ
mdi_mcvr_mnmi, 0x0 // MCU-command Non-Maskable Interrupt
.equ
mdi_mcvr_mc, 0x8 // MCU-Command active bit
// bits of the MCU-side Control Register (MCR)
.equ
mdi_mcr_mdf0, 0x0 // MCU to DSP Flag 0
.equ
mdi_mcr_mdf1, 0x1 // MCU to DSP Flag 1
.equ
mdi_mcr_mdf2, 0x2 // MCU to DSP Flag 2
.equ
mdi_mcr_mdir, 0x6 // MDI software Reset
.equ
mdi_mcr_dhr, 0x7 // DSP Hardware Reset
.equ
mdi_mcr_mgie1, 0xa // MCU General Interrupt 0 enable
.equ
mdi_mcr_mgie0, 0xb // MCU General Interrupt 1 enable
.equ
mdi_mcr_mtie1, 0xc // MCU transmit Interrupt 1 enable
.equ
mdi_mcr_mtie0, 0xd // MCU transmit Interrupt 0 enable
.equ
mdi_mcr_mrie1, 0xe // MCU Receive Interrupt 1 enable
.equ
mdi_mcr_mrie0, 0xf // MCU Receive Interrupt 0 enable
// bits of the MCU-side Status Register (MSR)
.equ
mdi_msr_mf0, 0x0 // MCU-side Flag 0
.equ
mdi_msr_mf1,
.equ
mdi_msr_mf2,
0x1 // MCU-side Flag 1
0x2 // MCU-side Flag 2
.equ
mdi_msr_mep,
.equ
mdi_msr_dpm,
0x4 // MCU-side Event Pending
0x5 // DSP power mode
.equ
mdi_msr_msmp, 0x6 // MCU Shared Memory access pending
.equ
mdi_msr_drs, 0x7 // DSP Reset State
.equ
mdi_msr_dws, 0x8 // DSP Wake from Stop
.equ
mdi_msr_mtir, 0x9 // MCU Protocol Timer wake DSP from stop & IRQ
.equ
mdi_msr_mgip1, 0xa // MCU General Interrupt 1 pending
.equ
mdi_msr_mgip0, 0xb // MCU General Interrupt 0 pending
.equ
mdi_msr_mte1, 0xc // MCU transmit register 1 empty
.equ
mdi_msr_mte0, 0xd // MCU transmit register 0 empty
.equ
mdi_msr_mrf1, 0xe // MCU Receive register 1 full
.equ
mdi_msr_mrf0, 0xf // MCU Receive register 0 full
//====================================================================
// Protocol timer (prot) equates
B-2 DSP56652 UserÕs Manual
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MCU Equates
//====================================================================
// general definitions
.equ
prot_memory_base_address,
.equ
prot_programable_registers_base_address,
.equ
prot_testmode_registers_base_address,
0x00203000
0x00203800
0x00203c00
// programable registers of the protocol timer
.equ
prot_tctr, 0x0 //Timer control register, old name
.equ
prot_ptcr, 0x0 //Timer control register, NEW NAME
.equ
prot_tier, 0x2 //timer interrupt enable register, old name
.equ
prot_ptier, 0x2 //timer interrupt enable register, NEW NAME
.equ
prot_tstr, 0x4 //timer status register, old name
.equ
prot_ptsr, 0x4 //timer status register, NEW NAME
.equ
prot_tevr, 0x6 //timer event register, old name
.equ
prot_ptevr, 0x6 //timer event register, NEW NAME
.equ
prot_tipr, 0x8 //time interval _prescaler_, old name
.equ
prot_timl, 0x8 //time interval _modulus latch_, NEW NAME
.equ
prot_ctic, 0xa //Channel time interval counter
.equ
prot_ctipr, 0xc //Channel time interval _preload register_, old name
.equ
prot_ctiml, 0xc //Channel time interval _modulus latch_, NEW NAME
.equ
prot_cfc, 0xe //Channel frames counter
.equ
prot_cfpr, 0x10 //Channel frames _preload register_, old name
.equ
prot_cfml, 0x10 //Channel frames _modulus latch_, NEW NAME
.equ
prot_rsc, 0x12 //Reference slot counter
.equ
prot_rspr, 0x14 //Reference slot _preload register_, old name
.equ
prot_rsml, 0x14 //Reference slot _modulus latch_, NEW NAME
.equ
prot_pdpar, 0x16 //Port D functionalty register, old name
.equ
prot_ptpcr, 0x16 //Protocol Timer Port Control Register, NEW NAME
.equ
prot_pddr, 0x18 //Port D directivity register, old name
.equ
prot_ptddr, 0x18 //Protocol Timer Data Direction Register, NEW NAME
.equ
prot_pddat, 0x1a //Port D data Register, old name
.equ
prot_ptpdr, 0x1a //Protocol Timer Port Data Register, NEW NAME
.equ
prot_ftptr, 0x1c //Frame tables pointers
.equ
prot_rtptr, 0x1e //Receive/Transmit Macro tables pointers, old name
.equ
prot_mtptr, 0x1e //Macro table pointers, NEW NAME
.equ
prot_ftbar, 0x20 //Frame tables base address register
.equ
prot_rtbar, 0x22 //Rx/Tx Macro tables base address register, old name
.equ
prot_mtbar, 0x22 //Macro table base address register, NEW NAME
.equ
prot_dtptr, 0x24 //Delay tables pointers.
// bits of the Timer Control Register (TCTR)(old names)
.equ
prot_tctr_te, 0x0 // timer enable bit.
.equ
prot_tctr_time, 0x1 // timer immidiate enable bit.
.equ
prot_tctr_mter, 0x2 // macro termination bit
.equ
prot_tctr_tdzd, 0x3 // Timer doze disable.
.equ
prot_tctr_spbp, 0x4 // slot prescaler by-pass bit
.equ
prot_tctr_hltr, 0x5 // halt request bit
.equ
prot_tctr_cfce, 0x8 // cfc counter enable bit
.equ
prot_tctr_rsce, 0x9 // rsc counter enable bit
// bits of the Protocol Timer Control Register (PTCR)(NEW NAMES)
.equ
prot_ptcr_te, 0x0 // timer enable bit.
.equ
prot_ptcr_time, 0x1 // timer immidiate enable bit.
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MCU Equates
.equ
prot_ptcr_mter, 0x2 // macro termination bit
.equ
prot_ptcr_tdzd, 0x3 // Timer doze disable.
.equ
prot_ptcr_spbp, 0x4 // slot prescaler by-pass bit
.equ
prot_ptcr_hltr, 0x5 // halt request bit
.equ
prot_ptcr_cfce, 0x8 // cfc counter enable bit
.equ
prot_ptcr_rsce, 0x9 // rsc counter enable bit
// bits of the Timer Interrupt Enable Register (TIER)(old names)
.equ
prot_ptier_cfie ,0x0 // channel frame interrupt enable bit
.equ
prot_ptier_cfnie ,0x1 // channel frame number intpt enable bit
.equ
prot_ptier_rsnie ,0x2 // reference slot number intpt enable bit
.equ
prot_ptier_mcie0 ,0x4 // MCU interrupt 0 enable bit
.equ
prot_ptier_mcie1 ,0x5 // MCU interrupt 1 enable bit
.equ
prot_ptier_mcie2 ,0x6 // MCU interrupt 2 enable bit
.equ
prot_ptier_dsie ,0x9 // DSP interrupt enable bit
.equ
prot_ptier_dvie ,0xa // DSP vector interrupt enable bit
.equ
prot_ptier_thie ,0xb // Timer haltinterrupt enable bit
.equ
prot_ptier_terie ,0xc // Timer error interrupt enable bit
// bits of the Protocol Timer Interrupt Enable Register (PTIER)(NEW NAMES)
.equ
prot_tier_cfie , 0x0 // channel frame interrupt enable bit
.equ
prot_tier_cfnie ,0x1 // channel frame number intpt enable bit
.equ
prot_tier_rsnie ,0x2 // reference slot number intpt enable bit
.equ
prot_tier_mcie0 ,0x4 // MCU interrupt 0 enable bit
.equ
prot_tier_mcie1 ,0x5 // MCU interrupt 1 enable bit
.equ
prot_tier_mcie2 ,0x6 // MCU interrupt 2 enable bit
.equ
prot_tier_dsie , 0x9 // DSP interrupt enable bit
.equ
prot_tier_dvie , 0xa // DSP vector interrupt enable bit
.equ
prot_tier_thie , 0xb // Timer haltinterrupt enable bit
.equ
prot_tier_terie ,0xc // Timer error interrupt enable bit
// bits of the Timer Status Register (TSTR)(old names)
.equ
prot_tstr_cfi , 0x0 // channel frame interrupt bit
.equ
prot_tstr_cfni , 0x1 // channel frame number interrupt bit
.equ
prot_tstr_rsni , 0x2 // reference slot number interrupt bit
.equ
prot_tstr_mcui0 ,0x4 // MCU interrupt 0 bit
.equ
prot_tstr_mcui1 ,0x5 // MCU interrupt 1 bit
.equ
prot_tstr_mcui2 ,0x6 // MCU interrupt 2 bit
.equ
prot_tstr_dsi , 0x9 // DSP interrupt bit
.equ
prot_tstr_dvi , 0xa // DSP vector interrupt bit
.equ
prot_tstr_thi , 0xb // Timer haltinterrupt bit
.equ
prot_tstr_teri , 0xc // Timer error interrupt bit
// bits of the Protocol Timer Status Register (PTSR)(NEW NAMES)
.equ
prot_ptsr_cfi , 0x0 // channel frame interrupt bit
.equ
prot_ptsr_cfni , 0x1 // channel frame number interrupt bit
.equ
prot_ptsr_rsni , 0x2 // reference slot number interrupt bit
.equ
prot_ptsr_mcui0 ,0x4 // MCU interrupt 0 bit
.equ
prot_ptsr_mcui1 ,0x5 // MCU interrupt 1 bit
.equ
prot_ptsr_mcui2 ,0x6 // MCU interrupt 2 bit
.equ
prot_ptsr_dsi , 0x9 // DSP interrupt bit
.equ
prot_ptsr_dvi , 0xa // DSP vector interrupt bit
.equ
prot_ptsr_thi , 0xb // Timer haltinterrupt bit
.equ
prot_ptsr_teri , 0xc // Timer error interrupt bit
B-4 DSP56652 UserÕs Manual
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MCU Equates
// bits of the Timer Event Register (TEVR)(old names)
.equ
prot_tevr_act , 0x0 // active table indicator bit
.equ
prot_tevr_rxma , 0x1 // active Rx macro indicator bit
.equ
prot_tevr_txma , 0x2 // active Tx macro indicator bit
.equ
prot_tevr_thip , 0x3 // timer halt in progress indicator bit
// bits of the Protocol Timer Event Register (PTEVR)(NEW NAMES)
.equ
prot_ptevr_act , 0x0 // active table indicator bit
.equ
prot_ptevr_rxma ,0x1 // active Rx macro indicator bit
.equ
prot_ptevr_txma ,0x2 // active Tx macro indicator bit
.equ
prot_ptevr_thip ,0x3 // timer halt in progress indicator bit
// bits of the Time Interval Preload Register (TIPR)(old names)
.equ
prot_tipr_tipv_0 ,0x0 // TIPR value-bit 0
.equ
prot_tipr_tipv_1 ,0x1 // TIPR value-bit 1
.equ
prot_tipr_tipv_2 ,0x2 // TIPR value-bit 2
.equ
prot_tipr_tipv_3 ,0x3 // TIPR value-bit 3
.equ
prot_tipr_tipv_4 ,0x4 // TIPR value-bit 4
.equ
prot_tipr_tipv_5 ,0x5 // TIPR value-bit 5
.equ
prot_tipr_tipv_6 ,0x6 // TIPR value-bit 6
.equ
prot_tipr_tipv_7 ,0x7 // TIPR value-bit 7
.equ
prot_tipr_tipv_8 ,0x8 // TIPR value-bit 8
// bits of the Time Interval Modulus Register (TIMR)(NEW NAMES)
.equ
prot_timl_timv_0 ,0x0 // timl value-bit 0
.equ
prot_timl_timv_1 ,0x1 // timl value-bit 1
.equ
prot_timl_timv_2 ,0x2 // timl value-bit 2
.equ
prot_timl_timv_3 ,0x3 // timl value-bit 3
.equ
prot_timl_timv_4 ,0x4 // timl value-bit 4
.equ
prot_timl_timv_5 ,0x5 // timl value-bit 5
.equ
prot_timl_timv_6 ,0x6 // timl value-bit 6
.equ
prot_timl_timv_7 ,0x7 // timl value-bit 7
.equ
prot_timl_timv_8 ,0x8 // timl value-bit 8
// bits of the Channel Time Interval Counter (CTIC)
.equ
prot_ctic_ctiv_0, 0x0 // CTIC value-bit 0
.equ
prot_ctic_ctiv_1,
.equ
prot_ctic_ctiv_2,
0x1 // CTIC value-bit 1
0x2 // CTIC value-bit 2
.equ
prot_ctic_ctiv_3,
.equ
prot_ctic_ctiv_4,
.equ
prot_ctic_ctiv_5,
.equ
prot_ctic_ctiv_6,
0x3 // CTIC value-bit 3
0x4 // CTIC value-bit 4
0x5 // CTIC value-bit 5
0x6 // CTIC value-bit 6
.equ
prot_ctic_ctiv_7,
.equ
prot_ctic_ctiv_8,
.equ
prot_ctic_ctiv_9,
.equ
prot_ctic_ctiv_10,
.equ
prot_ctic_ctiv_11,
.equ
prot_ctic_ctiv_12,
.equ
prot_ctic_ctiv_13,
0x7 // CTIC value-bit 7
0x8 // CTIC value-bit 8
0x9 // CTIC value-bit 9
0xa // CTIC value-bit 10
0xb // CTIC value-bit 11
0xc // CTIC value-bit 12
0xd // CTIC value-bit 13
// bits of the Channel Time Interval Preload Register (CTIPR)(old names)
.equ
prot_ctipr_ctipv_0, 0x0 // CTIPR value-bit 0
.equ
prot_ctipr_ctipv_1, 0x1 // CTIPR value-bit 1
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MCU Equates
.equ
prot_ctipr_ctipv_2,
.equ
prot_ctipr_ctipv_3,
.equ
prot_ctipr_ctipv_4,
.equ
prot_ctipr_ctipv_5,
.equ
prot_ctipr_ctipv_6,
.equ
prot_ctipr_ctipv_7,
.equ
prot_ctipr_ctipv_8,
.equ
prot_ctipr_ctipv_9,
.equ
prot_ctipr_ctipv_10,
.equ
prot_ctipr_ctipv_11,
.equ
prot_ctipr_ctipv_12,
.equ
prot_ctipr_ctipv_13,
0x2 // CTIPR value-bit 2
0x3 // CTIPR value-bit 3
0x4 // CTIPR value-bit 4
0x5 // CTIPR value-bit 5
0x6 // CTIPR value-bit 6
0x7 // CTIPR value-bit 7
0x8 // CTIPR value-bit 8
0x9 // CTIPR value-bit 9
0xa // CTIPR value-bit 10
0xb // CTIPR value-bit 11
0xc // CTIPR value-bit 12
0xd // CTIPR value-bit 13
// bits of the Channel Time Interval Modulus Register (CTIMR)(NEW NAMES)
.equ
prot_ctiml_ctimv_0, 0x0 // ctiml value-bit 0
.equ
prot_ctiml_ctimv_1,
.equ
prot_ctiml_ctimv_2,
0x1 // ctiml value-bit 1
0x2 // ctiml value-bit 2
.equ
prot_ctiml_ctimv_3,
.equ
prot_ctiml_ctimv_4,
.equ
prot_ctiml_ctimv_5,
.equ
prot_ctiml_ctimv_6,
0x3 // ctiml value-bit 3
0x4 // ctiml value-bit 4
0x5 // ctiml value-bit 5
0x6 // ctiml value-bit 6
.equ
prot_ctiml_ctimv_7,
.equ
prot_ctiml_ctimv_8,
.equ
prot_ctiml_ctimv_9,
.equ
prot_ctiml_ctimv_10,
.equ
prot_ctiml_ctimv_11,
.equ
prot_ctiml_ctimv_12,
.equ
prot_ctiml_ctimv_13,
0x7 // ctiml value-bit 7
0x8 // ctiml value-bit 8
0x9 // ctiml value-bit 9
0xa // ctiml value-bit 10
0xb // ctiml value-bit 11
0xc // ctiml value-bit 12
0xd // ctiml value-bit 13
// bits of the Channel Frame Counter (CFC)
.equ
prot_cfc_cfcv_0, 0x0 //CFC value-bit 0
.equ
prot_cfc_cfcv_1,
.equ
prot_cfc_cfcv_2,
0x1 //CFC value-bit 1
0x2 //CFC value-bit 2
.equ
prot_cfc_cfcv_3,
.equ
prot_cfc_cfcv_4,
.equ
prot_cfc_cfcv_5,
.equ
prot_cfc_cfcv_6,
.equ
prot_cfc_cfcv_7,
.equ
prot_cfc_cfcv_8,
0x3 //CFC value-bit 3
0x4 //CFC value-bit 4
0x5 //CFC value-bit 5
0x6 //CFC value-bit 6
0x7 //CFC value-bit 7
0x8 //CFC value-bit 8
// bits of the Channel Frame Preload Register (CFPR)(old names)
.equ
prot_cfpr_cfpv_0, 0x0 //CFPR value- bit 1
.equ
prot_cfpr_cfpv_1,
.equ
prot_cfpr_cfpv_2,
0x1 //CFPR value- bit 2
0x2 //CFPR value- bit 3
.equ
prot_cfpr_cfpv_3,
.equ
prot_cfpr_cfpv_4,
.equ
prot_cfpr_cfpv_5,
.equ
prot_cfpr_cfpv_6,
.equ
prot_cfpr_cfpv_7,
.equ
prot_cfpr_cfpv_8,
0x3 //CFPR value- bit 4
0x4 //CFPR value- bit 5
0x5 //CFPR value- bit 6
0x6 //CFPR value- bit 7
0x7 //CFPR value- bit 8
0x8 //CFPR value- bit 9
// bits of the Channel Frame Modulus Register (CFMR)(NEW NAMES)
.equ
prot_cfml_cfmv_0, 0x0 //cfml value- bit 1
.equ
prot_cfml_cfmv_1, 0x1 //cfml value- bit 2
B-6 DSP56652 UserÕs Manual
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Freescale Semiconductor, Inc.
MCU Equates
.equ
prot_cfml_cfmv_2,
.equ
prot_cfml_cfmv_3,
.equ
prot_cfml_cfmv_4,
.equ
prot_cfml_cfmv_5,
.equ
prot_cfml_cfmv_6,
.equ
prot_cfml_cfmv_7,
.equ
prot_cfml_cfmv_8,
0x2 //cfml value- bit 3
0x3 //cfml value- bit 4
0x4 //cfml value- bit 5
0x5 //cfml value- bit 6
0x6 //cfml value- bit 7
0x7 //cfml value- bit 8
0x8 //cfml value- bit 9
// bits of the Reference Slot Counter (RSC)
.equ
prot_rsc_rscv_0, 0x0 //RSC value-bit 0
.equ
prot_rsc_rscv_1,
.equ
prot_rsc_rscv_2,
0x1 //RSC value-bit 1
0x2 //RSC value-bit 2
.equ
prot_rsc_rscv_3,
.equ
prot_rsc_rscv_4,
.equ
prot_rsc_rscv_5,
.equ
prot_rsc_rscv_6,
.equ
prot_rsc_rscv_7,
0x3 //RSC value-bit 3
0x4 //RSC value-bit 4
0x5 //RSC value-bit 5
0x6 //RSC value-bit 6
0x7 //RSC value-bit 7
// bits of the Reference Slot Preload Register (RSPR) (old names)
.equ
prot_rspr_rspv_0, 0x0 //RSPR value -bit 0
.equ
prot_rspr_rspv_1,
.equ
prot_rspr_rspv_2,
0x1 //RSPR value -bit 1
0x2 //RSPR value -bit 2
.equ
prot_rspr_rspv_3,
.equ
prot_rspr_rspv_4,
.equ
prot_rspr_rspv_5,
.equ
prot_rspr_rspv_6,
.equ
prot_rspr_rspv_7,
0x3 //RSPR value -bit 3
0x4 //RSPR value -bit 4
0x5 //RSPR value -bit 5
0x6 //RSPR value -bit 6
0x7 //RSPR value -bit 7
// bits of the Reference Slot Modulus Register (RSMR) (NEW NAMES)
.equ
prot_rsml_rsmv_0, 0x0 //rsml value -bit 0
.equ
prot_rsml_rsmv_1,
.equ
prot_rsml_rsmv_2,
0x1 //rsml value -bit 1
0x2 //rsml value -bit 2
.equ
prot_rsml_rsmv_3,
.equ
prot_rsml_rsmv_4,
.equ
prot_rsml_rsmv_5,
.equ
prot_rsml_rsmv_6,
.equ
prot_rsml_rsmv_7,
0x3 //rsml value -bit 3
0x4 //rsml value -bit 4
0x5 //rsml value -bit 5
0x6 //rsml value -bit 6
0x7 //rsml value -bit 7
// bits of the Port D Pin Assignment Register (PDPAR) (old names)
.equ
prot_pdpar_pdgpc_0,0x0 //Select the function of pin 0 in port D
.equ
prot_pdpar_pdgpc_1,0x1 //Select the function of pin 1 in port D
.equ
prot_pdpar_pdgpc_2,0x2 //Select the function of pin 2 in port D
.equ
prot_pdpar_pdgpc_3,0x3 //Select the function of pin 3 in port D
.equ
prot_pdpar_pdgpc_4,0x4 //Select the function of pin 4 in port D
.equ
prot_pdpar_pdgpc_5,0x5 //Select the function of pin 5 in port D
.equ
prot_pdpar_pdgpc_6,0x6 //Select the function of pin 6 in port D
.equ
prot_pdpar_pdgpc_7,0x7 //Select the function of pin 7 in port D
// bits of the Protocol Timer Port Control Register (PTPCR) (NEW NAMES)
.equ
prot_ptpcr_ptpc_0,0x0 //Select the function of pin 0 in port D
.equ
prot_ptpcr_ptpc_1,0x1 //Select the function of pin 1 in port D
.equ
prot_ptpcr_ptpc_2,0x2 //Select the function of pin 2 in port D
.equ
prot_ptpcr_ptpc_3,0x3 //Select the function of pin 3 in port D
.equ
prot_ptpcr_ptpc_4,0x4 //Select the function of pin 4 in port D
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B-7
Freescale Semiconductor, Inc.
MCU Equates
.equ
prot_ptpcr_ptpc_5,0x5 //Select the function of pin 5 in port D
.equ
prot_ptpcr_ptpc_6,0x6 //Select the function of pin 6 in port D
.equ
prot_ptpcr_ptpc_7,0x7 //Select the function of pin 7 in port D
// bits of the Port D Direction Register Register (PDDR) (old names)
.equ
prot_pddr_pddr_0,0x0 //Select the direction of pin 0 in port D
.equ
prot_pddr_pddr_1,0x1 //Select the direction of pin 1 in port D
.equ
prot_pddr_pddr_2,0x2 //Select the direction of pin 2 in port D
.equ
prot_pddr_pddr_3,0x3 //Select the direction of pin 3 in port D
.equ
prot_pddr_pddr_4,0x4 //Select the direction of pin 4 in port D
.equ
prot_pddr_pddr_5,0x5 //Select the direction of pin 5 in port D
.equ
prot_pddr_pddr_6,0x6 //Select the direction of pin 6 in port D
.equ
prot_pddr_pddr_7,0x7 //Select the direction of pin 7 in port D
// bits of the Protocol Timer Data Direction Register (PTDDR) (NEW NAMES)
.equ
prot_ptddr_ptdd_0,0x0 //Select the direction of pin 0 in port D
.equ
prot_ptddr_ptdd_1,0x1 //Select the direction of pin 1 in port D
.equ
prot_ptddr_ptdd_2,0x2 //Select the direction of pin 2 in port D
.equ
prot_ptddr_ptdd_3,0x3 //Select the direction of pin 3 in port D
.equ
prot_ptddr_ptdd_4,0x4 //Select the direction of pin 4 in port D
.equ
prot_ptddr_ptdd_5,0x5 //Select the direction of pin 5 in port D
.equ
prot_ptddr_ptdd_6,0x6 //Select the direction of pin 6 in port D
.equ
prot_ptddr_ptdd_7,0x7 //Select the direction of pin 7 in port D
// bits of the Port D Data Register (PDDAT) (old names)
.equ
prot_pddat_pddat_0, 0x0 //Port D Data- pin 0
.equ
prot_pddat_pddat_1,
.equ
prot_pddat_pddat_2,
0x1 //Port D Data- pin 1
0x2 //Port D Data- pin 2
.equ
prot_pddat_pddat_3,
.equ
prot_pddat_pddat_4,
.equ
prot_pddat_pddat_5,
.equ
prot_pddat_pddat_6,
.equ
prot_pddat_pddat_7,
0x3 //Port D Data- pin 3
0x4 //Port D Data- pin 4
0x5 //Port D Data- pin 5
0x6 //Port D Data- pin 6
0x7 //Port D Data- pin 7
// bits of the Protocol Timer Port Data Register (PTPDR) (NEW NAMES)
.equ
prot_ptpdr_ptpd_0, 0x0 //Port D Data- pin 0
.equ
prot_ptpdr_ptpd_1,
.equ
prot_ptpdr_ptpd_2,
0x1 //Port D Data- pin 1
0x2 //Port D Data- pin 2
.equ
prot_ptpdr_ptpd_3,
.equ
prot_ptpdr_ptpd_4,
.equ
prot_ptpdr_ptpd_5,
.equ
prot_ptpdr_ptpd_6,
.equ
prot_ptpdr_ptpd_7,
0x3 //Port D Data- pin 3
0x4 //Port D Data- pin 4
0x5 //Port D Data- pin 5
0x6 //Port D Data- pin 6
0x7 //Port D Data- pin 7
// bits of the Frame Table Pointer (FTPTR)
.equ
prot_ftptr_ftptr_0, 0x0 //Frame table pointer-bit0
.equ
prot_ftptr_ftptr_1,
.equ
prot_ftptr_ftptr_2,
0x1 //Frame table pointer-bit1
0x2 //Frame table pointer-bit2
.equ
prot_ftptr_ftptr_3,
.equ
prot_ftptr_ftptr_4,
.equ
prot_ftptr_ftptr_5,
.equ
prot_ftptr_ftptr_6,
0x3 //Frame table pointer-bit3
0x4 //Frame table pointer-bit4
0x5 //Frame table pointer-bit5
0x6 //Frame table pointer-bit6
// bits of the Receive/Transmit macro Table Pointer (RTPTR)(old names)
B-8 DSP56652 UserÕs Manual
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Freescale Semiconductor, Inc.
MCU Equates
.equ
prot_rtptr_rxptr_0,
.equ
prot_rtptr_rxptr_1,
.equ
prot_rtptr_rxptr_2,
.equ
prot_rtptr_rxptr_3,
.equ
prot_rtptr_rxptr_4,
.equ
prot_rtptr_rxptr_5,
.equ
prot_rtptr_rxptr_6,
.equ
prot_rtptr_txptr_0,
.equ
prot_rtptr_txptr_1,
.equ
prot_rtptr_txptr_2,
.equ
prot_rtptr_txptr_3,
.equ
prot_rtptr_txptr_4,
.equ
prot_rtptr_txptr_5,
.equ
prot_rtptr_txptr_6,
0x0 //Receive macro pointer-bit 0
0x1 //Receive macro pointer-bit 1
0x2 //Receive macro pointer-bit 2
0x3 //Receive macro pointer-bit 3
0x4 //Receive macro pointer-bit 4
0x5 //Receive macro pointer-bit 5
0x6 //Receive macro pointer-bit 6
0x8 //Transmit macro pointer-bit 0
0x9 //Transmit macro pointer-bit 1
0xa //Transmit macro pointer-bit 2
0xb //Transmit macro pointer-bit 3
0xc //Transmit macro pointer-bit 4
0xd //Transmit macro pointer-bit 5
0xe //Transmit macro pointer-bit 6
// bits of the Macro Table Pointer (RTPTR)(NEW NAMES)
.equ
prot_mtptr_rxptr_0, 0x0 //Receive macro pointer-bit 0
.equ
prot_mtptr_rxptr_1,
.equ
prot_mtptr_rxptr_2,
0x1 //Receive macro pointer-bit 1
0x2 //Receive macro pointer-bit 2
.equ
prot_mtptr_rxptr_3,
.equ
prot_mtptr_rxptr_4,
.equ
prot_mtptr_rxptr_5,
.equ
prot_mtptr_rxptr_6,
0x3 //Receive macro pointer-bit 3
0x4 //Receive macro pointer-bit 4
0x5 //Receive macro pointer-bit 5
0x6 //Receive macro pointer-bit 6
.equ
prot_mtptr_txptr_0,
.equ
prot_mtptr_txptr_1,
.equ
prot_mtptr_txptr_2,
.equ
prot_mtptr_txptr_3,
.equ
prot_mtptr_txptr_4,
.equ
prot_mtptr_txptr_5,
.equ
prot_mtptr_txptr_6,
0x8 //Transmit macro pointer-bit 0
0x9 //Transmit macro pointer-bit 1
0xa //Transmit macro pointer-bit 2
0xb //Transmit macro pointer-bit 3
0xc //Transmit macro pointer-bit 4
0xd //Transmit macro pointer-bit 5
0xe //Transmit macro pointer-bit 6
// bits of the Frame Table Base Address Register (FTBAR)
.equ
prot_ftbar_ftba0_0, 0x0 //Frame table 0 base address-bit 0
.equ
prot_ftbar_ftba0_1,
.equ
prot_ftbar_ftba0_2,
0x1 //Frame table 0 base address-bit 1
0x2 //Frame table 0 base address-bit 2
.equ
prot_ftbar_ftba0_3,
.equ
prot_ftbar_ftba0_4,
.equ
prot_ftbar_ftba0_5,
.equ
prot_ftbar_ftba0_6,
0x3 //Frame table 0 base address-bit 3
0x4 //Frame table 0 base address-bit 4
0x5 //Frame table 0 base address-bit 5
0x6 //Frame table 0 base address-bit 6
.equ
prot_ftbar_ftba1_0,
.equ
prot_ftbar_ftba1_1,
.equ
prot_ftbar_ftba1_2,
.equ
prot_ftbar_ftba1_3,
.equ
prot_ftbar_ftba1_4,
.equ
prot_ftbar_ftba1_5,
.equ
prot_ftbar_ftba1_6,
0x8 //Frame table 1 base address-bit 0
0x9 //Frame table 1 base address-bit 1
0xa //Frame table 1 base address-bit 2
0xb //Frame table 1 base address-bit 3
0xc //Frame table 1 base address-bit 4
0xd //Frame table 1 base address-bit 5
0xe //Frame table 1 base address-bit 6
// bits of the Receive/Transmit Base Address Register (RTBAR) (old names)
.equ
prot_rtbar_rxba_0, 0x0 //Receive macro base address-bit 0
.equ
prot_rtbar_rxba_1,
.equ
prot_rtbar_rxba_2,
0x1 //Receive macro base address-bit 1
0x2 //Receive macro base address-bit 2
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Freescale Semiconductor, Inc.
MCU Equates
.equ
prot_rtbar_rxba_3,
.equ
prot_rtbar_rxba_4,
.equ
prot_rtbar_rxba_5,
.equ
prot_rtbar_rxba_6,
.equ
prot_rtbar_txba_0,
.equ
prot_rtbar_txba_1,
.equ
prot_rtbar_txba_2,
.equ
prot_rtbar_txba_3,
.equ
prot_rtbar_txba_4,
.equ
prot_rtbar_txba_5,
.equ
prot_rtbar_txba_6,
0x3 //Receive macro base address-bit 3
0x4 //Receive macro base address-bit 4
0x5 //Receive macro base address-bit 5
0x6 //Receive macro base address-bit 6
0x8 //Transmit macro base address-bit 0
0x9 //Transmit macro base address-bit 1
0xa //Transmit macro base address-bit 2
0xb //Transmit macro base address-bit 3
0xc //Transmit macro base address-bit 4
0xd //Transmit macro base address-bit 5
0xe //Transmit macro base address-bit 6
// bits of the Macro Table Base Address Register (MTBAR) (NEW NAMES)
.equ
prot_mtbar_rxba_0, 0x0 //Receive macro base address-bit 0
.equ
prot_mtbar_rxba_1,
.equ
prot_mtbar_rxba_2,
0x1 //Receive macro base address-bit 1
0x2 //Receive macro base address-bit 2
.equ
prot_mtbar_rxba_3,
.equ
prot_mtbar_rxba_4,
.equ
prot_mtbar_rxba_5,
.equ
prot_mtbar_rxba_6,
0x3 //Receive macro base address-bit 3
0x4 //Receive macro base address-bit 4
0x5 //Receive macro base address-bit 5
0x6 //Receive macro base address-bit 6
.equ
prot_mtbar_txba_0,
.equ
prot_mtbar_txba_1,
.equ
prot_mtbar_txba_2,
.equ
prot_mtbar_txba_3,
.equ
prot_mtbar_txba_4,
.equ
prot_mtbar_txba_5,
.equ
prot_mtbar_txba_6,
0x8 //Transmit macro base address-bit 0
0x9 //Transmit macro base address-bit 1
0xa //Transmit macro base address-bit 2
0xb //Transmit macro base address-bit 3
0xc //Transmit macro base address-bit 4
0xd //Transmit macro base address-bit 5
0xe //Transmit macro base address-bit 6
// bits of the Delay Table Pointer (DTPTR)
.equ
prot_dtptr_rdptr_0, 0x0 //Receive delay pointer-bit 0
.equ
prot_dtptr_rdptr_1,
.equ
prot_dtptr_rdptr_2,
0x1 //Receive delay pointer-bit 1
0x2 //Receive delay pointer-bit 2
.equ
prot_dtptr_rdba_0,
.equ
prot_dtptr_rdba_1,
.equ
prot_dtptr_rdba_2,
.equ
prot_dtptr_rdba_3,
0x3 //Receive delay base address-bit 0
0x4 //Receive delay base address-bit 1
0x5 //Receive delay base address-bit 2
0x6 //Receive delay base address-bit 3
.equ
prot_dtptr_tdptr_0,
.equ
prot_dtptr_tdptr_1,
.equ
prot_dtptr_tdptr_2,
.equ
prot_dtptr_tdba_0,
.equ
prot_dtptr_tdba_1,
.equ
prot_dtptr_tdba_2,
.equ
prot_dtptr_tdba_3,
0x8 //Transmit delay pointer-bit 0
0x9 //Transmit delay pointer-bit 1
0xa //Transmit delay pointer-bit 2
0xb //Transmit delay base address-bit 0
0xc //Transmit delay base address-bit 1
0xd //Transmit delay base address-bit 2
0xe //Transmit delay base address-bit 3
//====================================================================
// UART equates
//====================================================================
B-10 DSP56652 UserÕs Manual
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Freescale Semiconductor, Inc.
// general definitions
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
.equ
urx, urx_20, utx, utx_60, ucr1, ucr2, ubrg, usr, uts, upcr, uddr, updr,
0x00204000
0x00204020
0x00204040
0x00204060
0x00204080
0x00204082
0x00204084
0x00204086
0x00204088
0x0020408a
0x0020408c
0x0020408e
// bits of UART control register 1 (UCR1)
.equ
ucr1_uarten, 0x0 // old name
.equ
ucr1_uen,
.equ
ucr1_doze,
0x0 // NEW NAME
0x1
.equ
ucr1_sndbrk,
.equ
ucr1_rtsden,
.equ
ucr1_rtsdie,
.equ
ucr1_txmptyen,
0x4
0x5 // old name
0x5 // NEW NAME
0x6 // old name
.equ
ucr1_txeie,
.equ
ucr1_iren,
.equ
ucr1_rxen,
.equ
ucr1_rrdyen,
.equ
ucr1_rrdyie,
.equ
ucr1_rxfl0,
.equ
ucr1_rxfl1,
.equ
ucr1_txen,
.equ
ucr1_trdyen,
.equ
ucr1_trdyie,
.equ
ucr1_txfl0,
.equ
ucr1_txfl1,
0x6 // NEW NAME
0x7
0x8
0x9 // old name
0x9 // NEW NAME
0xa
0xb
0xc
0xd // old name
0xd // NEW NAME
0xe
0xf
// bits of UART control register 2 (UCR2)
.equ
ucr2_clksrc, 0x4
.equ
ucr2_ws,
.equ
ucr2_chsz,
0x5 // old name
0x5 // NEW NAME
.equ
ucr2_stpb,
.equ
ucr2_proe,
.equ
ucr2_pren,
.equ
ucr2_cts,
0x6
0x7
0x8
0xc // old name
.equ
ucr2_ctsd,
.equ
ucr2_CTSC,
.equ
ucr2_irts,
0xc // NEW NAME
0xD
0xe
// bits of UART status register (USR)
.equ
usr_rtsd, 0x5
.equ
usr_rrdy,
.equ
usr_trdy,
0x9
0xd
.equ
usr_rtss,
.equ
usr_txmpty,
0xe
0xf // old name
Motorola Equates and Header Files
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MCU Equates
B-11
Freescale Semiconductor, Inc.
MCU Equates
.equ
usr_txe, 0xf // NEW NAME
// bits of the UART receiver register (URX)
.equ
urx_prerr, 0xa
.equ
urx_brk,
.equ
urx_frmerr,
0xb
0xc
.equ
urx_ovrrun,
.equ
urx_err,
.equ
urx_charrdy,
0xd
0xe
0xf
// bits of the UART test register (UTS)
.equ
uts_loopir, 0xa
.equ
uts_loop,
.equ
uts_frcperr,
0xc
0xd
// bits of the UART port control register (UPCR), old names
.equ
upcr_pc0, 0x0
.equ
upcr_pc1,
.equ
upcr_pc2,
.equ
upcr_pc3,
0x1
0x2
0x3
// bits of the UART port control register (UPCR), NEW NAMES
.equ
upcr_upc0, 0x0
.equ
upcr_upc1,
.equ
upcr_upc2,
.equ
upcr_upc3,
0x1
0x2
0x3
// bits of the UART data direction register (UDDR), old names
.equ
uddr_pdc0, 0x0
.equ
uddr_pdc1,
.equ
uddr_pdc2,
.equ
uddr_pdc3,
0x1
0x2
0x3
// bits of the UART data direction register (UDDR), NEW NAMES
.equ
uddr_udd0, 0x0
.equ
uddr_udd1,
.equ
uddr_udd2,
.equ
uddr_udd3,
0x1
0x2
0x3
// bits of the UART port data register (UPDR), old names
.equ
updr_pd0, 0x0
.equ
updr_pd1,
.equ
updr_pd2,
.equ
updr_pd3,
0x1
0x2
0x3
// bits of the UART port data register (UPDR), NEW NAMES
.equ
updr_upd0, 0x0
.equ
updr_upd1,
.equ
updr_upd2,
.equ
updr_upd3,
0x1
0x2
0x3
//====================================================================
// QSPI equates
B-12 DSP56652 UserÕs Manual
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Freescale Semiconductor, Inc.
//====================================================================
// QSPI BASE ADDRESS
.equ
qspi_base_address, 0x00205000
// control ram, split into 16-byte sections
.equ
qspi_control_ram0_base_address, 0x00205000
.equ
qspi_control_ram1_base_address,
.equ
qspi_control_ram2_base_address,
0x00205010
0x00205020
.equ
qspi_control_ram3_base_address,
.equ
qspi_control_ram4_base_address,
.equ
qspi_control_ram5_base_address,
.equ
qspi_control_ram6_base_address,
.equ
qspi_control_ram7_base_address,
0x00205030
0x00205040
0x00205050
0x00205060
0x00205070
// data ram, split into 16-byte sections
.equ
qspi_data_ram0_base_address, 0x00205400
.equ
qspi_data_ram1_base_address,
.equ
qspi_data_ram2_base_address,
0x00205410
0x00205420
.equ
qspi_data_ram3_base_address,
.equ
qspi_data_ram4_base_address,
.equ
qspi_data_ram5_base_address,
.equ
qspi_data_ram6_base_address,
.equ
qspi_data_ram7_base_address,
0x00205430
0x00205440
0x00205450
0x00205460
0x00205470
// control register base addresses
.equ
qspi_regs_base_address,
.equ
qspi_spsr_base_address,
.equ
qspi_trig_base_address,
0x00205f00
0x00205f10
0x00205ff8
// QSPI REGISTERS ADDRESS relatitve to qspi_regs_base_address
.equ
qspi_qpcr, 0x00
.equ
qspi_qddr,
.equ
qspi_qpdr,
0x02
0x04
.equ
qspi_spcr,
.equ
qspi_qcr0,
.equ
qspi_qcr1,
.equ
qspi_qcr2,
0x06
0x08
0x0a
0x0c
.equ
qspi_qcr3,
.equ
qspi_spsr,
.equ
qspi_sccr0,
.equ
qspi_sccr1,
.equ
qspi_sccr2,
.equ
qspi_sccr3,
.equ
qspi_sccr4,
0x0e
0x10
0x12
0x14
0x16
0x18
0x1a
// QSPI REGISTERS ADDRESS relatitve to qspi_trig_base_address
.equ
qspi_trigger0, 0x00
.equ
qspi_trigger1, 0x02
.equ
qspi_trigger2, 0x04
.equ
qspi_trigger3, 0x06
//BYTE ACCESS,
.equ
qspi_qpcrb, relative to qspi_regs_base_address
0x00
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MCU Equates
B-13
Freescale Semiconductor, Inc.
MCU Equates
.equ
qspi_qddrb,
.equ
qspi_qpdrb,
.equ
qspi_spcrb,
.equ
qspi_qcr0b,
.equ
qspi_qcr1b,
.equ
qspi_qcr2b,
.equ
qspi_qcr3b,
0x02
0x04
0x06
0x08
0x0a
0x0c
0x0e
//BYTE ACCESS,
.equ
qspi_spsrb,
.equ
qspi_sccr0b,
.equ
qspi_sccr1b, relative to qspi_spsr_base_address
0x00
0x02
0x04
.equ
qspi_sccr2b,
.equ
qspi_sccr3b,
.equ
qspi_sccr4b,
0x06
0x08
0x0a
//BYTE ACCESS, relative to qspi_trig_base_address
.equ
qspi_trigger0b, 0x00
.equ
qspi_trigger1b, 0x02
.equ
qspi_trigger2b, 0x04
.equ
qspi_trigger3b, 0x06 old names // QSPI QPCR BITS
.equ
qspi_qpcr_pc0, 0
.equ
qspi_qpcr_pc1, 1
.equ
qspi_qpcr_pc2, 2
.equ
qspi_qpcr_pc3, 3
.equ
qspi_qpcr_pc4, 4
.equ
qspi_qpcr_pc5, 5
.equ
qspi_qpcr_pc6, 6
.equ
qspi_qpcr_pc7, 7
NEW NAMES // QSPI QPCR BITS
.equ
qspi_qpcr_qpc0, 0
.equ
qspi_qpcr_qpc1, 1
.equ
qspi_qpcr_qpc2, 2
.equ
qspi_qpcr_qpc3, 3
.equ
qspi_qpcr_qpc4, 4
.equ
qspi_qpcr_qpc5, 5
.equ
qspi_qpcr_qpc6, 6
.equ
qspi_qpcr_qpc7, 7
// QSPI QDDR BITS
.equ
qspi_qddr_pd0, 0
.equ
qspi_qddr_pd1, 1
.equ
qspi_qddr_pd2, 2
.equ
qspi_qddr_pd3, 3
.equ
qspi_qddr_pd4, 4
.equ
qspi_qddr_pd5, 5
.equ
qspi_qddr_pd6, 6
.equ
qspi_qddr_pd7, 7
// QSPI QDDR BITS
.equ
qspi_qddr_qdd0, 0 old names
NEW NAMES
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MCU Equates
.equ
qspi_qddr_qdd1, 1
.equ
qspi_qddr_qdd2, 2
.equ
qspi_qddr_qdd3, 3
.equ
qspi_qddr_qdd4, 4
.equ
qspi_qddr_qdd5, 5
.equ
qspi_qddr_qdd6, 6
.equ
qspi_qddr_qdd7, 7
// QSPI QPDR BITS // QSPI QDDR BITS old names
.equ
qspi_qpdr_d0, 0
.equ
qspi_qpdr_d1,
.equ
qspi_qpdr_d2,
1
2
.equ
qspi_qpdr_d3,
.equ
qspi_qpdr_d4,
.equ
qspi_qpdr_d5,
.equ
qspi_qpdr_d6,
.equ
qspi_qpdr_d7,
3
4
5
6
7
// QSPI QPDR BITS // QSPI QDDR BITS NEW NAMES
.equ
qspi_qpdr_qpd0, 0
.equ
qspi_qpdr_qpd1, 1
.equ
qspi_qpdr_qpd2, 2
.equ
qspi_qpdr_qpd3, 3
.equ
qspi_qpdr_qpd4, 4
.equ
qspi_qpdr_qpd5, 5
.equ
qspi_qpdr_qpd6, 6
.equ
qspi_qpdr_qpd7, 7
// QSPI SPCR BITS
.equ
qspi_spcr_qspe, 0
.equ
qspi_spcr_doze, 1
.equ
qspi_spcr_halt, 2
.equ
qspi_spcr_wie, 4
.equ
qspi_spcr_trcie, 5
.equ
qspi_spcr_hltie, 6
.equ
qspi_spcr_qe0, 7
.equ
qspi_spcr_qe1, 8
.equ
qspi_spcr_qe2, 9
.equ
qspi_spcr_qe3, 10
.equ
qspi_spcr_cspol0,11
.equ
qspi_spcr_cspol1,12
.equ
qspi_spcr_cspol2,13
.equ
qspi_spcr_cspol3,14
.equ
qspi_spcr_cspol4,15
// QSPI QCRn BITS
.equ
qspi_qcrn_qpn, 0x3f // queue pointer n bits mask
.equ
qspi_qcrn_hmdn, 14
.equ
qspi_qcrn_len, 15
// QSPI QCR1 BITS
.equ
qspi_qcr1_trcnt, 0x3c0 // trigger counter mask for queue 1
// QSPI SPSR BITS
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Freescale Semiconductor, Inc.
MCU Equates
.equ
qspi_spsr_eot0, 0
.equ
qspi_spsr_eot1, 1
.equ
qspi_spsr_eot2, 2
.equ
qspi_spsr_eot3, 3
.equ
qspi_spsr_qpwf, 4
.equ
qspi_spsr_trc, 5
.equ
qspi_spsr_halta, 6
.equ
qspi_spsr_qa0, 8
.equ
qspi_spsr_qa1, 9
.equ
qspi_spsr_qa2, 10
.equ
qspi_spsr_qa3, 11
.equ
qspi_spsr_qx0, 12
.equ
qspi_spsr_qx1, 13
.equ
qspi_spsr_qx2, 14
.equ
qspi_spsr_qx3, 15
// QSPI SCCRn BITS
.equ
qspi_sccrn_sckdfn,0x7f // sckdfn bits mask
.equ
qspi_sccrn_csckdn,0x380 // csckdn bits mask
.equ
qspi_sccrn_datrn,0x1c00 // datrn bits mask
.equ
qspi_sccrn_lsbfn,13
.equ
qspi_sccrn_ckpoln,14
.equ
qspi_sccrn_cphan,15
//====================================================================
// Timer/PWM
//====================================================================
// base address
.equ
tpwm_base_addr, 0x00206000 //MCU Timer base address
// register addresses relative to base
.equ
tpwm_tpwcr, 0x0
.equ
tpwm_tpwmr,
.equ
tpwm_tpwsr,
0x2
0x4
.equ
tpwm_twir,
.equ
tpwm_tocr1,
.equ
tpwm_tocr3,
.equ
tpwm_tocr4,
0x6
0x8
0xa
0xc
.equ
tpwm_ticr1,
.equ
tpwm_ticr2,
.equ
tpwm_pwor,
.equ
tpwm_tcr,
.equ
tpwm_tcnt,
.equ
tpwm_pwcr,
.equ
tpwm_pwml,
.equ
tpwm_pwcnr,
.equ
tpwm_pwcnt,
0xe
0x10
0x12
0x14 // old name
0x14 // NEW NAME
0x16 // old name
0x16 // NEW NAME
0x18 // old name
0x18 // NEW NAME
//tpwcr bits
.equ
tpwm_tpwcr_pwdbg,
.equ
tpwm_tpwcr_tdbg,
.equ
tpwm_tpwcr_pwd,
.equ
tpwm_tpwcr_pwe,
11 //TPWCR pwdbg bit
10 //TPWCR tdbg bit
9 //TPWCR pwd bit
8 //TPWCR pwe bit
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.equ
tpwm_tpwcr_td,
.equ
tpwm_tpwcr_te,
.equ
tpwm_tpwcr_pspw2,
.equ
tpwm_tpwcr_pspw1,
.equ
tpwm_tpwcr_pspw0,
.equ
tpwm_tpwcr_pst2,
.equ
tpwm_tpwcr_pst1,
.equ
tpwm_tpwcr_pst0,
//tpwmr bits
.equ
tpwm_tpwmr_pwc,
.equ
tpwm_tpwmr_pwp,
.equ
tpwm_tpwmr_fo4,
.equ
tpwm_tpwmr_fo3,
.equ
tpwm_tpwmr_fo1,
.equ
tpwm_tpwmr_im21,
.equ
tpwm_tpwmr_im20,
.equ
tpwm_tpwmr_im11,
.equ
tpwm_tpwmr_im10,
.equ
tpwm_tpwmr_om41,
.equ
tpwm_tpwmr_om40,
.equ
tpwm_tpwmr_om31,
.equ
tpwm_tpwmr_om30,
.equ
tpwm_tpwmr_om11,
.equ
tpwm_tpwmr_om10,
//tpwsr bits
.equ
tpwm_tpwsr_pwo,
.equ
tpwm_tpwsr_tov,
.equ
tpwm_tpwsr_pwf,
.equ
tpwm_tpwsr_if2,
.equ
tpwm_tpwsr_if1,
.equ
tpwm_tpwsr_of4,
.equ
tpwm_tpwsr_of3,
.equ
tpwm_tpwsr_of1,
//twir bits
.equ
tpwm_twir_pwoie,
.equ
tpwm_twir_tovie,
.equ
tpwm_twir_pwfie,
.equ
tpwm_twir_if2ie,
.equ
tpwm_twir_if1ie,
.equ
tpwm_twir_of4ie,
.equ
tpwm_twir_of3ie,
.equ
tpwm_twir_of1ie,
7 //TPWCR td bit
6 //TPWCR te bit
5 //TPWCR pspw2 bit
4 //TPWCR pspw1 bit
3 //TPWCR pspw0 bit
2 //TPWCR pst2 bit
1 //TPWCR pst1 bit
0 //TPWCR pst0 bit
14 //TPWMR pwc bit
13 //TPWMR pwp bit
12 //TPWMR fo4 bit
11 //TPWMR fo3 bit
10 //TPWMR fo1 bit
9 //TPWMR im21 bit
8 //TPWMR im20 bit
7 //TPWMR im11 bit
6 //TPWMR im10 bit
5 //TPWMR om41 bit
4 //TPWMR om40 bit
3 //TPWMR om31 bit
2 //TPWMR om30 bit
1 //TPWMR om11 bit
0 //TPWMR om10 bit
7 //TPWSR pwo bit
6 //TPWSR tov bit
5 //TPWSR pwf bit
4 //TPWSR if2 bit
3 //TPWSR if1 bit
2 //TPWSR of4 bit
1 //TPWSR of3 bit
0 //TPWSR of1 bit
7 //TWIR pwoie bit
6 //TWIR tovie bit
5 //TWIR pwfie bit
4 //TWIR if2ie bit
3 //TWIR if1ie bit
2 //TWIR of4ie bit
1 //TWIR of3ie bit
0 //TWIR of1ie bit
//====================================================================
// ckctl, rsr, emddr, emdr, and gpcr registers
//====================================================================
// register addresses
.equ
ckctl,
.equ
rsr,
0x0020c000
0x0020c400
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MCU Equates
B-17
Freescale Semiconductor, Inc.
MCU Equates
.equ
emddr,
.equ
emdr,
.equ
gpcr,
// bits of CKCTL
.equ
ckctl_ckihd,
.equ
ckctl_mcs,
.equ
ckctl_mcd0,
.equ
ckctl_mcd1,
.equ
ckctl_mcd2,
.equ
ckctl_ckos,
.equ
ckctl_ckoe,
.equ
ckctl_ckohe,
.equ
ckctl_dcs,
// bits of RSR
.equ
rsr_exr,
.equ
rsr_wdr,
// bits of EMDDR
.equ
emddr_emdd0,
.equ
emddr_emdd1,
.equ
emddr_emdd2,
.equ
emddr_emdd3,
.equ
emddr_emdd4,
.equ
emddr_emdd5,
// bits of EMDR
.equ
emdr_emd0,
.equ
emdr_emd1,
.equ
emdr_emd2,
.equ
emdr_emd3,
.equ
emdr_emd4,
.equ
emdr_emd5,
// bits of GPCR
.equ
gpcr_gpc0,
.equ
gpcr_gpc1,
.equ
gpcr_gpc2,
.equ
gpcr_gpc3,
.equ
gpcr_gpc4,
.equ
gpcr_gpc5,
.equ
gpcr_gpc6,
.equ
gpcr_gpc7,
0x0020c800
0x0020c802
0x0020cc00
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x0
0x1
0x2
0x3
0x4
0x5
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
//====================================================================
// Keypad Port
//====================================================================
B-18
.equ
kpp_base_address, 0x0020a000 // Module Base Address
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.equ
kpp_kpcr,
.equ
kpp_kpsr,
.equ
kpp_kddr,
.equ
kpp_kpdr,
Freescale Semiconductor, Inc.
MCU Equates
0x0 // Port Control Register
0x2 // Port Status Register
0x4 // Data direction Register
0x6 // Data value Register
//====================================================================
// Subscriber Interface Module (SmartCard Port)
//====================================================================
// old names
.equ
scp_base_address,0x0020b000// Module Base Address
.equ
scp_simcr,
.equ
scp_siacr,
.equ
scp_siicr,
.equ
scp_simsr,
.equ
scp_simdr,
.equ
scp_sipcr,
0x0
0x2
0x4
0x6
0x8
0xa
// SIM Control Register
// SIM Activation Control Register
// SIM Interrupt Control Register
// SIM Status Register
// SIM Tx and Rx Data Register
// SIM Pins Control Register
// NEW NAMES
.equ
scp_base_address,0x0020b000// Module Base Address
.equ
scp_scpcr,
.equ
scp_scacr,
.equ
scp_scpier,
.equ
scp_scpsr,
.equ
scp_scpdr,
.equ
scp_scppcr,
0x0
0x2
0x4
0x6
0x8
0xa
// SCP Control Register
// SCP Activation Control Register
// SCP Interrupt Control Register
// SCP Status Register
// SCP Tx and Rx Data Register
// SCP Pins Control Register
//====================================================================
// External Interrupts
//====================================================================
.equ
wext_base_address,0x00209000 // Module Base Address
.equ
wext_eppar,
.equ
wext_epddr,
.equ
wext_epdr,
.equ
wext_epfr,
0x0 // Edge Port Pin Assignment Register
0x2 // Edge Port Data Direction Register
0x4 // Edge Port Data Register
0x6 // Edge Port Flag Register
//====================================================================
// EIM
//====================================================================
.equ
eim_registers_base_address,0x00201000 // eim base address
// register addresses relative to base address
.equ
eim_cs0_control_reg, 0x0
.equ
eim_cs1_control_reg,
.equ
eim_cs2_control_reg,
.equ
eim_cs3_control_reg,
0x4
0x8
0xc
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Freescale Semiconductor, Inc.
MCU Equates
.equ
eim_cs4_control_reg,
.equ
eim_cs5_control_reg,
0x10
0x14
.equ
eim_configuration_reg, 0x18
// Bits definitions for the EIM CS configuration registers
.equ
eim_cs_csen, 0x0 // Chip select enable
.equ
eim_cs_pa,
.equ
eim_cs_wp,
0x1
0x2
// Output value for CS0 only when csen = 0
// Write Protec
.equ
eim_cs_sp,
.equ
eim_cs_dsz,
.equ
eim_cs_ebc,
.equ
eim_cs_wen,
0x3
0x4
0x6
0x7
// Supervisor Protect
// Data Port Size
// Enable Byte Control
// Determines when EB0-1 outputs are
.equ
.equ
.equ
.equ
.equ
eim_cs_oea, eim_cs_csa, eim_cs_edc, eim_cs_wws, eim_cs_wsc,
0x8
0x9
0xa
0xb
0xc
negated during a write cycle.
// Determines when OE is asserted during a
read cycle.
// Chip Select Assert
// Extra Dead Cycle
// Write Wait-State
//Wait-State Control
// EIM configuration register bits definitions
.equ
eim_cr_shen,
.equ
eim_cr_hdb,
0x0
0x2
.equ
eim_cr_sprom,
.equ
eim_cr_spram,
.equ
eim_cr_spiper,
.equ
eim_cr_epen,
0x3
0x4
0x5
0x6
//====================================================================
// Peripheral Interrupt Controller
//====================================================================
.equ
pic_base_address, 0x00200000
.equ
pic_isr ,
.equ
pic_normal_enable,
.equ
pic_fast_enable ,
.equ
pic_normal_pending,
.equ
pic_fast_pending,
.equ
pic_control ,
0x0
0x4
0x8
0xc
0x10
0x14
// Bits in the PIC registers
.equ
pic_sw0 ,
.equ
pic_sw1 ,
.equ
pic_sw2 ,
.equ
pic_int0 ,
.equ
pic_int1 ,
.equ
pic_int2 ,
.equ
pic_int3 ,
.equ
pic_int4 ,
.equ
pic_int5 ,
.equ
pic_int6 ,
.equ
pic_int7 ,
.equ
pic_urts ,
.equ
pic_kpd ,
0x0
0x1
0x2
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
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.equ
pic_pit ,
.equ
pic_tpw ,
.equ
pic_sim ,
.equ
pic_mdi ,
.equ
pic_qspi ,
.equ
pic_prot ,
.equ
pic_prot0 ,
.equ
pic_prot1 ,
.equ
pic_prot2 ,
.equ
pic_utx ,
.equ
pic_smpdint ,
.equ
pic_smpd ,
.equ
pic_urx ,
0x10
0x11
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x13 // old name
0x13 // NEW NAME
0x1f
//====================================================================
// Watchdog Timer
//====================================================================
.equ
wdt_base_address, 0x00208000
.equ
wdt_wcr,
.equ
wdt_wsr,
0x0
0x2
//====================================================================
// Periodic Interrupt Timer
//====================================================================
.equ
pit_base_address, 0x00207000
.equ
pit_itcsr,
.equ
pit_itdr,
.equ
pit_itadr,
0x0 // old names
0x2
0x4
.equ
pit_pitcsr,
.equ
pit_pitml,
.equ
pit_pitcnt,
0x0 // NEW NAMES
0x2
0x4
//====================================================================
// PSR bits
//====================================================================
.equ
psr_tc , 0xc
.equ
psr_sc ,
.equ
psr_mm ,
.equ
psr_ee ,
.equ
psr_ic ,
0xa
0x9
0x8
0x7
.equ
psr_ie ,
.equ
psr_fe ,
.equ
psr_af ,
.equ
psr_c ,
0x6
0x4
0x1
0x0
MCU Equates
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B-21
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MCU Include File
B.2 MCU Include File
/*
* DSP56651/DSP56652 C include file for M.CORE
*
* Revision History:
* 1.0: may 28,
*/
1998
#ifndef _REDCAP_H_
#define _REDCAP_H_
/* *********************
REDCAP MCU MEMORY MAP
********************* */
/* On-chip ROM: 16 KB starting at location 0 */
#define REDCAP_MCU_ROM_BASE 0x00000000
#define REDCAP_MCU_ROM_SIZE 0x00004000
/* On-chip RAM: 2KB starting at specified location */
#define REDCAP_MCU_RAM_BASE 0x00100000
#define REDCAP_MCU_RAM_SIZE x00000800
/* On-chip peripherals - base addresses */
#define REDCAP_MCU_PIC 0x00200000 /* Interrupt Controller */
#define REDCAP_MCU_EIM 0x00201000 /* External Interface Module */
#define REDCAP_MCU_MDI 0x00202000 /* MCU-DSP Interface */
#define REDCAP_MCU_PROT 0x00203000 /* Protocol Timer */
#define REDCAP_MCU_UART 0x00204000 /* UART */
#define REDCAP_MCU_QSPI 0x00205000 /* Queued SPI */
#define REDCAP_MCU_PWM 0x00206000 /* PWM/Input Capture Timers */
#define REDCAP_MCU_PIT 0x00207000 /* Periodic Interrupt Timer */
#define REDCAP_MCU_WDT 0x00208000 /* Watchdog Timer */
#define REDCAP_MCU_INTPINS 0x00209000 /* Interrupt Pins Control */
#define REDCAP_MCU_KPP 0x0020A000 /* Keypad Port */
#define REDCAP_MCU_SCP 0x0020B000 /* Smart Card Port */
#define REDCAP_MCU_CKCTL 0x0020C000 /* Clock Control Register */
#define REDCAP_MCU_RSR 0x0020C400 /* Reset Source Register */
#define REDCAP_MCU_EMULPORT 0x0020C800 /* Emulation Port Control */
#define REDCAP_MCU_GPCR 0x0020CC00 /* General Port Control */
/* Reserved 0x00300000 through 03fffffff */
/* External memory associated with chip Selects */
#define REDCAP_MCU_CS0_BASE 0x40000000 /* Chip Select 0 */
#define REDCAP_MCU_CS0_SIZE 0x01000000
#define REDCAP_MCU_CS1_BASE 0x41000000 /* Chip Select 1 */
#define REDCAP_MCU_CS1_SIZE 0x01000000
#define REDCAP_MCU_CS2_BASE 0x42000000 /* Chip Select 2 */
#define REDCAP_MCU_CS2_SIZE 0x01000000
#define REDCAP_MCU_CS3_BASE 0x43000000 /* Chip Select 3 */
#define REDCAP_MCU_CS3_SIZE 0x01000000
#define REDCAP_MCU_CS4_BASE 0x44000000 /* Chip Select 4 */
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MCU Include File
#define REDCAP_MCU_CS4_SIZE 0x01000000
#define REDCAP_MCU_CS5_BASE 0x45000000 /* Chip Select 5 */
#define REDCAP_MCU_CS5_SIZE 0x01000000
/* *****************************
REDCAP Clock Control Register
example usage:
unsigned short *clock = (unsigned short *)REDCAP_MCU_CKCTL;
***************************** */
#define REDCAP_CKCTL_CKIHD 0x0001
#define REDCAP_CKCTL_MCS 0x0002
#define REDCAP_CKCTL_MCD_1 0x0000
#define REDCAP_CKCTL_MCD_2 0x0004
#define REDCAP_CKCTL_MCD_4 0x0008
#define REDCAP_CKCTL_MCD_8 0x000C
#define REDCAP_CKCTL_MCD_16 0x0010
#define REDCAP_CKCTL_CKOS 0x0020
#define REDCAP_CKCTL_CKOE 0x0040
#define REDCAP_CKCTL_CKOHE 0x0080
#define REDCAP_CKCTL_DCS 0x0100
/* *********************
REDCAP Reset Source Register
example usage:
unsigned short *reset_source= (unsigned short *)REDCAP_MCU_RSR;
********************* */
#define REDCAP_RSR_EXR 0x0001
#define REDCAP_RSR_WDR 0x0002
/* *********************
REDCAP Emulation Port Control
example usage:
struct redcap_emulport *em_port= (struct redcap_emulport*)REDCAP_MCU_EMPORT;
********************* */
#ifdef _ASSEM
#define EMU_DIR 0
#define EMU_DATA 2
#else struct redcap_emulport {
unsigned short emddr; /* em port data direction register */
volatile unsigned short emdr; /* em port data register */
};
#endif
/* *********************
REDCAP General Port Control
example usage:
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unsigned short *gpcr= (unsigned short *)REDCAP_MCU_GPCR;
********************* */
/* *********************
REDCAP External Interface Module
example usage:
struct redcap_eim *eim= (struct redcap_eim*)REDCAP_MCU_EIM;
********************* */
#ifdef _ASSEM
#define EIM_CS0CR 0x0
#define EIM_CS1CR 0x4
#define EIM_CS2CR 0x8
#define EIM_CS3CR 0xc
#define EIM_CS4CR 0x10
#define EIM_CS5CR 0x14
#define EIM_CR 0x18
#else struct redcap_eim {
unsigned long cs0cr; /* chip select 0 control register */
unsigned long cs1cr; /* chip select 0 control register */
unsigned long cs2cr; /* chip select 0 control register */
unsigned long cs3cr; /* chip select 0 control register */
unsigned long cs4cr; /* chip select 0 control register */
unsigned long cs5cr; /* chip select 0 control register */
unsigned long eimcr; /* eim configuration register */
};
#endif
/* *********************
REDCAP Interrupt controller
example usage:
struct redcap_pic *pic= (struct redcap_pic *)REDCAP_MCU_PIC;
********************* */
#ifdef _ASSEM
#define PIC_ISR 0x00
#define PIC_NIER 0x04
#define PIC_FIER 0x08
#define PIC_NIPR 0x0C
#define PIC_FIPR 0x10
#define PIC_ICR 0x14
#else struct redcap_pic {
volatile unsigned long isr; /* interrupt source register*/
unsigned long nier; /* normal interrupt enable register*/
unsigned long fier; /* fast interrupt enable register*/
volatile unsigned long nipr; /* normal interrupt pending register*/
volatile unsigned long fipr; /* fast interrupt pending register*/
unsigned long icr; /* interrupt control register*/
};
#endif
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MCU Include File
/* Bit masks which apply to isr, nier, nipr, fier, and fipr. */
#define REDCAP_INT_URX 0x80000000
#define REDCAP_INT_SMPD 0x40000000
#define REDCAP_INT_UTX 0x20000000
#define REDCAP_INT_PT2 0x10000000
#define REDCAP_INT_PT1 0x08000000
#define REDCAP_INT_PT0 0x04000000
#define REDCAP_INT_PTM 0x02000000
#define REDCAP_INT_QSPI 0x01000000
#define REDCAP_INT_MDI 0x00800000
#define REDCAP_INT_SIM 0x00400000
#define REDCAP_INT_TPW 0x00020000
#define REDCAP_INT_PIT 0x00010000
#define REDCAP_INT_KPD 0x00004000
#define REDCAP_INT_URTS 0x00002000
#define REDCAP_INT_INT7 0x00001000
#define REDCAP_INT_INT6 0x00000800
#define REDCAP_INT_INT5 0x00000400
#define REDCAP_INT_INT4 0x00000200
#define REDCAP_INT_INT3 0x00000100
#define REDCAP_INT_INT2 0x00000080
#define REDCAP_INT_INT1 0x00000040
#define REDCAP_INT_INT0 0x00000020
#define REDCAP_INT_S2 0x00000004
#define REDCAP_INT_S1 0x00000002
#define REDCAP_INT_S0 0x00000001
/* icr manipulation */
#define REDCAP_ICR_ENABLE 0x00008000
#define REDCAP_ICR_MAKE_SRC(x) (((x)&0x1f)<<7)
#define REDCAP_ICR_MAKE_VECTOR(x) ((x)&0x7f)
#define REDCAP_ICR_GET_SRC(x) (((x)>>7)&0x1f)
#define REDCAP_ICR_GET_VECTOR(x) ((x)&0x7f)
/* ****************************************************************
REDCAP MCU-DSP Interface
example usage:
unsigned short *mdi_shared = (unsigned short *)MDI_SHARED_BASE;
struct redcap_mdi_regs *mdi_regs = (struct redcap_mdi_regs*)MDI_REG_BASE;
********************************************************************** */
/* Shared memory */
#define MDI_SHARED_BASE (REDCAP_MCU_MDI+0x000)
/* Registers are at the end of the 1K space */
#define MDI_REG_BASE (REDCAP_MCU_MDI+0xFF2)
#ifdef _ASSEM
#define MDI_MCVR 0x2
#define MDI_MCR 0x4
#define MDI_MSR 0x6
#define MDI_MTR1 0x8
#define MDI_MTR0 0xa
#define MDI_MRR1 0xc
#define MDI_MRR0 0xe
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#else struct redcap_mdi_regs {
volatile unsigned short mcvr; /* command vector register,volatile MC bit */
volatile unsigned short mcr; /* control register,volatile MDIR bit */
volatile unsigned short msr; /* status register*/
unsigned short mtr1; /* transmit register 1 */
unsigned short mtr0; /* transmit register 0*/
volatile unsigned short mrr1; /* receive register 1 - read-only */
volatile unsigned short mrr0; /* receive register 0 - read-only */
};
#endif
/* mcvr register bits */
#define MCVR_MNMI 0x0001
#define MCVR_MCV0 0x0002
#define MCVR_MCV1 0x0004
#define MCVR_MCV2 0x0008
#define MCVR_MCV3 0x0010
#define MCVR_MCV4 0x0020
#define MCVR_MCV5 0x0040
#define MCVR_MCV6 0x0080
#define MCVR_MC 0x0100
/* mcr register bits */
#define MCR_MF0 0x0001
#define MCR_MF1 0x0002
#define MCR_MF2 0x0004
#define MCR_MDIR 0x0040
#define MCR_DHR 0x0080
#define MCR_MGIE1 0x0400
#define MCR_MGIE0 0x0800
#define MCR_MTIE1 0x1000
#define MCR_MTIE0 0x2000
#define MCR_MRIE1 0x4000
#define MCR_MRIE0 0x8000
/* msr register bits */
#define MSR_MF0 0x0001
#define MSR_MF1 0x0002
#define MSR_MF2 0x0004
#define MSR_MEP 0x0010
#define MSR_DPM 0x0020
#define MSR_MSMP 0x0040
#define MSR_DRS 0x0080
#define MSR_DWS 0x0100
#define MSR_MGIP1 0x0400
#define MSR_MGIP2 0x0800
#define MSR_MTE1 0x1000
#define MSR_MTE0 0x2000
#define MSR_MRF1 0x4000
#define MSR_MRF0 0x8000
/****************************
REDCAP Keypad Port (KPP).
example usage:
struct redcap_kppb *kppb= (struct redcap_kppb *)REDCAP_MCU_KPP;
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**************************** */
#ifdef _ASSEM
#define KPP_KPCR 0x0
#define KPP_KPSR 0x2
#define KPP_KDDR 0x4
#define KPP_KPDR 0x6
#else
/* this structure uses halfwords */ struct redcap_kpp {
unsigned short kpcr; /* keypad control reg*/
volatile unsigned short kpsr; /* keypad status reg */
unsigned short kddr; /* keypad data dir reg */
volatile unsigned short kpdr; /* keypad data reg */
};
/* this structure uses byte addressing */ struct redcap_kppb {
unsigned char kpcr_col; /* keypad control reg - cols*/
unsigned char kpcr_row; /* keypad control reg - rows*/
unsigned char reserved; /* byte not used*/
volatile unsigned char kpsr; /* keypad status reg */
unsigned char kddr_col; /* keypad data dir reg - cols*/
unsigned char kddr_row; /* keypad data dir reg - rows*/
volatile unsigned char kpdr_col; /* keypad data reg - cols*/
volatile unsigned char kpdr_row; /* keypad data reg - rows*/
};
#endif
/* kpsr register bits */
#define KPSR_KPKD 0x0001
/******************************
* REDCAP Timer/PWM (TPWM).
example usage:
struct redcap_tpwm *twpm= (struct redcap_tpwm*)REDCAP_MCU_TPWM;
***************************** */
#ifdef _ASSEM
#define TPWM_TPWCR 0x00
#define TPWM_TPWMR 0x02
#define TPWM_TPWSR 0x04
#define TPWM_TWIR 0x06
#define TPWM_TOCR1 0x08
#define TPWM_TOCR3 0x0A
#define TPWM_TOCR4 0x0C
#define TPWM_TICR1 0x0E
#define TPWM_TICR2 0x10
#define TPWM_PWOR 0x12
#define TPWM_TCR 0x14
#define TPWM_PWCR 0x16
#define TPWM_PWCNR 0x18
#else struct redcap_tpwm {
unsigned short tpwcr; /* control reg*/
unsigned short tpwmr; /* mode reg */
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volatile unsigned short tpwsr; /* status reg*/
unsigned short twir; /* interrupts enable reg */
unsigned short tocr1; /* timer output compare 1*/
unsigned short tocr3; /* timer output compare 3*/
unsigned short tocr4; /* timer output compare 4*/
volatile unsigned short ticr1; /* timer input capture 1,read-only*/
volatile unsigned short ticr2; /* input capture 2*/
unsigned short pwor; /* pwm output compare */
volatile unsigned short tcr; /* timer counter register,read-only*/
unsigned short pwcr; /* pwm count register*/
volatile unsigned short pwcnr; /* pwm counter register,read-only*/
};
#endif
/* tpwcr register bits */
#define TPWCR_TE 0x0040
/* tpwmsr register bits */
#define TPWSR_OF1 0x0001
/* ********************************
REDCAP Periodic Interrupt Timer
example usage:
struct redcap_pit *pit= (struct redcap_pit *)REDCAP_MCU_PIT;
******************************** */
#ifdef _ASSEM
#define PIT_ITCSR 0
#define PIT_ITDR 2
#define PIT_ITADR 4
#else struct redcap_pit{
volatile unsigned short itcsr; /* control and status register */
unsigned short itdr; /* data register (determines modulo) */
volatile unsigned short itadr; /* alternate data register,read-only */
};
#endif
/* ********************************
REDCAP Watchdog Timer
example usage:
struct redcap_wdt *wdt= (struct redcap_wdt *)REDCAP_MCU_WDT;
******************************** */
#ifdef _ASSEM
#define WDT_WCR 0
#define WDT_WSR 2
#else struct redcap_wdt{
unsigned short wcr; /* watchdog control register */
unsigned short wsr; /* watchdog service register */
};
#endif
/* ********************************
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REDCAP Interrupt Pins
example usage:
struct redcap_intpins *intpins= (struct redcap_intpins *)REDCAP_MCU_INTPINS;
******************************** */
#ifdef _ASSEM
#define INTPINS_EPPAR 0
#define INTPINS_EPDDR 2
#define INTPINS_EPDR 4
#define INTPINS_EPFR 6
#else struct redcap_intpins{
unsigned short eppar; /* pin assignment register */
unsigned short epddr; /* data direction register */
volatile unsigned short epdr; /* data register */
volatile unsigned short epfr; /* flag register */
};
#endif
/* ********************************
REDCAP Smart Cart Port
example usage:
struct redcap_scp *scp= (struct redcap_scp *)REDCAP_MCU_SCP;
******************************** */
#ifdef _ASSEM
#define SCP_SIMCR 0x0
#define SCP_SIACR 0x2
#define SCP_SIICR 0x4
#define SCP_SIMSR 0x6
#define SCP_SIMDR 0x8
#deinfe SCP_SIPCR 0xA
#else struct redcap_intpins{
unsigned short simcr; /* control register */
unsigned short siacr; /* activation control register */
unsigned short siicr; /* interrupt control register */
volatile unsigned short simsr; /* status register */
volatile unsigned short simdr; /* transmit and receive data register */
volatile unsigned short sipcr; /* pins control register */
};
#endif
/* ********************************
REDCAP UART
note: rx and tx registers are "short" (halfwords) but are lie on
"long" (word) boundaries to support the use of ldm/stm instructions.
example usage:
unsigned long *uart_rx_data = (unsigned long *)UART_R_REG;
unsigned long *uart_tx_data = (unsigned long *)UART_T_REG;
struct redcap_uart_ctrl *uart_ctrl= (struct redcap_uart_ctrl *)UART_C_REG;
******************************** */
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/* receive data registers */
#define UART_R_REG (REDCAP_MCU_UART+0x00)
/* transmit data registers */
#define UART_T_REG (REDCAP_MCU_UART+0x40)
/* Control Registers */
#define UART_C_REG (REDCAP_MCU_UART+0x80)
#ifdef _ASSEM
#define UART_UCR1 0x0
#define UART_UCR2 0x2
#define UART_UBRG 0x4
#define UART_USR 0x6
#define UART_UTS 0x8
#define UART_UPCR 0xa
#define UART_UDDR 0xc
#define UART_UPDR 0xe
#else struct redcap_uart_ctrl{
unsigned short ucr1; /* control register 1 */
unsigned short ucr2; /* control register 2 */
unsigned short ubrg; /* baud-rate-generator register */
volatile unsigned short usr; /* status register */
unsigned short uts; /* test register */
unsigned short upcr; /* port control register */
unsigned short uddr; /* port data direction register */
volatile unsigned short updr; /* port data register */
};
#endif
/* ********************************
REDCAP QSPI
example usage:
unsigned short *qspi_control_ram = (unsigned short *)QSPI_C_RAM;
unsigned short *qspi_data_ram = (unsigned short *)QSPI_D_RAM;
struct redcap_qspi_c_reg *qspi_ctrl = (struct redcap_qspi_c_reg*)QSPI_C_REG;
struct redcap_qspi_t_reg *qspi_trigs = (struct redcap_qspi_t_reg*)QSPIDCAP_T_REG;
******************************** */
/* control ram */
#define QSPI_C_RAM (REDCAP_MCU_QSPI+0x000)
/* data ram */
#define QSPI_D_RAM (REDCAP_MCU_QSPI+0x400)
/* Control Registers */
#define QSPI_C_REG (REDCAP_MCU_UART+0xf00)
/* Manual Trigger Registers */
#define QSPI_T_REG (REDCAP_MCU_UART+0xff8)
#ifdef _ASSEM
/* control registers */
#define QSPI_QPCR 0x00
#define QSPI_QDDR 0x02
#define QSPI_QPDR 0x04
#define QSPI_SPCR 0x06
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#define QSPI_QCR0 0x08
#define QSPI_QCR1 0x0a
#define QSPI_QCR2 0x0c
#define QSPI_QCR3 0x0e
#define QSPI_SPSR 0x10
#define QSPI_SCCR0 0x12
#define QSPI_SCCR1 0x14
#define QSPI_SCCR2 0x16
#define QSPI_SCCR3 0x18
#define QSPI_SCCR4 0x1a
/* trigger registers */
#define QSPI_TRIG0 0x0
#define QSPI_TRIG1 0x2
#define QSPI_TRIG2 0x4
#define QSPI_TRIG3 0x6
#else struct redcap_qspi_c_reg{
unsigned short qpcr; /* port control register */
unsigned short qddr; /* port data direction register */
volatile unsigned short qpdr /* port data register */
unsigned short spcr; /* spi control register */
volatile unsigned short qcr0; /* queue control register 0 */
volatile unsigned short qcr1; /* queue control register 1 */
volatile unsigned short qcr2; /* queue control register 2 */
volatile unsigned short qcr3; /* queue control register 3 */
volatile unsigned short spsr; /* spi status register */
unsigned short sccr0; /* serial channel control register 0 */
unsigned short sccr1; /* serial channel control register 1 */
unsigned short sccr2; /* serial channel control register 2 */
unsigned short sccr3; /* serial channel control register 3 */
unsigned short sccr4; /* serial channel control register 4 */
}; struct redcap_qspi_t_reg{
unsigned short trig0; /* trigger for queue 0 */
unsigned short trig1; /* trigger for queue 1 */
unsigned short trig2; /* trigger for queue 2 */
unsigned short trig3; /* trigger for queue 3 */
};
#endif
/* ********************************
REDCAP Protocol Timer
example usage:
unsigned short *event_table = (unsigned short *)PROT_ET_BASE;
struct redcap_prot_ctrl *prot_ctrl = (struct redcap_prot_ctrl *)PROT_C_REG_BASE;
******************************** */
/* event table base address */
#define PROT_ET_BASE (REDCAP_MCU_PROT+0x000)
/* control registers base address*/
#define PROT_C_REG_BASE (REDCAP_MCU_PROT+0x800)
#ifdef _ASSEM
#define PROT_TCTR 0x00
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#define PROT_TIER 0x02
#define PROT_TSTR 0x04
#define PROT_TEVR 0x06
#define PROT_TIPR 0x08
#define PROT_CTIC 0x0A
#define PROT_CTIPR 0x0C
#define PROT_CFC 0x0E
#define PROT_CFPR 0x10
#define PROT_RSC 0x12
#define PROT_RSPR 0x14
#define PROT_PDPAR 0x16
#define PROT_PDDR 0x18
#define PROT_PDDAT 0x1A
#define PROT_FTPTR 0x1C
#define PROT_RTPTR 0x1E
#define PROT_FTBAR 0x20
#define PROT_RTBAR 0x22
#define PROT_DTPTR 0x24
#else struct redcap_prot_ctrl{
unsigned short tctr; /* timer control register */
unsigned short tier; /* timer interrupt enable register */
volatile unsigned short tstr; /* timer status register */
volatile unsigned short tevr; /* timer event register */
unsigned short tipr; /* time interval prescaler register */
volatile unsigned short ctic; /* channel time internal counter */
unsigned short ctipr; /* channel time interval preload regiser */
volatile unsigned short cfc; /* channel frame counter */
unsigned short cfpr; /* channel frame preload register */
volatile unsigned short rsc; /* reference slot counter */
unsigned short rspr; /* reference slot preload register */
unsigned short pdpar; /* port d pin assignment register */
unsigned short pddr; /* port d direction register */
volatile unsigned short pddat; /* port d data register */
volatile unsigned short ftptr; /* frame table pointer register */
volatile unsigned short rtptr; /* receive/transmit macro tables pointer register*/
unsigned short ftbar; /* frame table base address register */
unsigned short rtbar; /* receive/tranmit macro tables base address register */
volatile unsigned short dtptr; /* delay table pointer register */
};
#endif
#endif
B.3 DSP Equates
;***************************************************************
; DSP Equates for DSP56651/DSP56652
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;
; Revision History:
; 1.0: may 28 1998
;***************************************************************
; Register Addresses for IPR register
M_IPRC EQU $FFFF ; Interrupt Priority Register Core
M_IPRP EQU $FFFE ; Interrupt Priority Register Peripheral
; Register Addresses of PLL
M_PCTL0 EQU $FFFD ; PLL Control Register 0
M_PCTL1 EQU $FFFC ; PLL Control Register 1
; PLL Control Register 0 (PCTL0)
M_MF EQU $0FFF ; Multiplication Factor Bits Mask (MF0-MF11)
M_PD EQU $F000 ; PreDivider Factor Bits Mask (PD3-PD0)
M_PD03 EQU $F000 ; PreDivider Factor Bits Mask (PD3-PD0)
; PLL Control Register 1 (PCTL1)
M_PD46 EQU $0E00 ; PreDivider Factor Bits Mask (PD6-PD4)
M_DF EQU $7 ; Division Factor Bits Mask (DF0-DF2)
M_XTLR EQU 3 ; XTAL Range select bit
M_XTLD EQU 4 ; XTAL Disable Bit
M_PSTP EQU 5 ; STOP Processing State Bit
M_PEN EQU 6 ; PLL Enable Bit
M_PCOD EQU 7 ; PLL Clock Output Disable Bit
; Register Addresses Of BIU
M_BCR EQU $FFFA ; Bus Control Register <-- not used in this device
M_IDR EQU $FFF9 ; ID Register
; Register Addresses Of PATCH
M_PA0 EQU $FFF8 ; Patch Address Register 0
M_PA1 EQU $FFF7 ; Patch Address Register 1
M_PA2 EQU $FFF6 ; Patch Address Register 2
M_PA3 EQU $FFF5 ; Patch Address Register 3
; Register Addresses Of BPMR
M_BPMRG EQU $FFF4 ; BPMRG Register
M_BPMRL EQU $FFF3 ; BPMRL Register
M_BPMRH EQU $FFF2 ; BPMRH Register
;------------------------------------------------------------------------
;
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; EQUATES for SR and OMR
;
;------------------------------------------------------------------------
; control and status bits in SR
M_C EQU 0 ; Carry
M_V EQU 1 ; Overflow
M_Z EQU 2 ; Zero
M_N EQU 3 ; Negative
M_U EQU 4 ; Unnormalized
M_E EQU 5 ; Extension
M_L EQU 6 ; Limit
M_S EQU 7 ; Scaling Bit
M_I0 EQU 8 ; Interupt Mask Bit 0
M_I1 EQU 9 ; Interupt Mask Bit 1
M_S0 EQU 10 ; Scaling Mode Bit 0
M_S1 EQU 11 ; Scaling Mode Bit 1
M_FV EQU 12 ; DO-Forever Flag
M_SM EQU 13 ; Arithmetic Saturation
M_RM EQU 14 ; Rounding Mode
M_LF EQU 15 ; DO-Loop Flag
; control and status bits in OMR
M_MA EQU 0 ; Operating Mode A
M_MB EQU 1 ; Operating Mode B
M_MC EQU 2 ; Operating Mode C
M_MD EQU 3 ; Operating Mode D
M_EBD EQU 4 ; External Bus Disable bit in OMR
M_PCD EQU 5 ; PC relative logic disable
M_SD EQU 6 ; Stop Delay
M_XYS EQU 8 ; Stack Extention space select
M_EUN EQU 9 ; Extended Stack Underflow Flag
M_EOV EQU 10 ; Extended Stack Overflow Flag
M_WRP EQU 11 ; Extended Stack Wrap Flag
M_SEN EQU 12 ; Stack Extended Enable
M_ATE EQU 15 ; Address Tracing Enable bit in OMR.
;------------------------------------------------------------------------
;
; EQUATES for MDI
;
;------------------------------------------------------------------------
MDI_SHARED_MEMORY_BASE equ $1c00
MDI_IO_BASE equ $ff80
MDR_IRQ_BASE equ $60
; WMDI DSP-side registers
DRR0 equ MDI_IO_BASE+$f ;DSP-side receive register 0
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DSP Equates
DRR1 equ MDI_IO_BASE+$e ;DSP-side receive register 1
DTR0 equ MDI_IO_BASE+$d ;DSP-side transmit register 0
DTR1 equ MDI_IO_BASE+$c ;DSP-side transmit register 1
DSR equ MDI_IO_BASE+$b ;DSP-side status register
DCR equ MDI_IO_BASE+$a ;DSP-side control register
; WMDI DSP-side Status Register (DSR) bits
DF0 equ 0 ;DSP-side Flag 0
DF1 equ 1 ;DSP-side Flag 1
DF2 equ 2 ;DSP-side Flag 2
DEP equ 4 ;DSP Event Pending
MPM0 equ 5 ;MCU Power Mode bit 0
MPM1 equ 6 ;MCU Power Mode bit 1
DWSC equ 7 ;DSP Wake from Stop interrupt Clear
MCP equ 8 ;MCU Command Pending
DTIC equ 9 ;DSP Protocol Timer Interrupt clear
DGIR1 equ 10 ;DSP General Interrupt Request 1 bit
DGIR0 equ 11 ;DSP General Interrupt Request 0 bit
DRF1 equ 12 ;DSP Receive register 1 Full
DRF0 equ 13 ;DSP Receive register 0 Full
DTE1 equ 14 ;DSP Transmit register 1 Empty
DTE0 equ 15 ;DSP Transmit register 0 Empty
; WMDI DSP-side Control Register (DCR) bits
DMF0 equ 0 ;DSP-side MCU messaging flag 0
DMF1 equ 1 ;DSP-side MCU messaging flag 1
DMF2 equ 2 ;DSP-side MCU messaging flag 2
MCIE equ 8 ;MCU Command Interrupt Enable
DRIE1 equ 12 ;DSP Recieve 1 Interrupt Enable
DRIE0 equ 13 ;DSP Recieve 0 Interrupt Enable
DTIE1 equ 14 ;DSP Transmit 1 Interrupt Enable
DTIE0 equ 15 ;DSP Transmit 0 Interrupt Enable
;------------------------------------------------------------------------
;
; EQUATES for Base Band Port (BBP)
;
;------------------------------------------------------------------------
;
; Register Addresses of BBP
BBP_PCRB EQU $FFAF ; BBP Port Control Register
BBP_PRRB EQU $FFAE ; BBP GPIO Direction Register
BBP_PDRB EQU $FFAD ; BBP GPIO Data Register
BBP_TXB EQU $FFAC ; BBP Transmit Data Register
BBP_TSRB EQU $FFAB ; BBP Time Slot Register
BBP_RXB EQU $FFAA ; BBP Receive Data Register
BBP_SSISRB EQU $FFA9 ; BBP Status Register
BBP_CRCB EQU $FFA8 ; BBP Control Register C
BBP_CRBB EQU $FFA7 ; BBP Control Register B
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BBP_CRAB EQU $FFA6 ; BBP Control Register A
BBP_TCRB EQU $FFA5 ; BBP Tran. Frame Preload counter
BBP_RCRB EQU $FFA4 ; BBP Rec. Frame Preload counter
; BBP Control Register A Bit Flags
BBP_PSR EQU 15 ; Prescaler Range
BBP_DC EQU $1F00 ; Frame Rate Divider Control Mask (DC0-DC7)
BBP_WL EQU $6000 ; Word Length Control Mask (WL0-WL7)
; BBP Control register B Bit Flags
BBP_OF EQU $3 ; Serial Output Flag Mask
BBP_OF0 EQU 0 ; Serial Output Flag 0
BBP_OF1 EQU 1 ; Serial Output Flag 1
BBP_TCE EQU 4 ; BBP Tr Frame Cnt enable
BBP_RCE EQU 5 ; BBP Rc Frame Cnt enable
BBP_TCIE EQU 6 ; BBP Tr Frame RO enable
BBP_RCIE EQU 7 ; BBP Rc Frame RO enable
BBP_TE EQU 8 ; BBP Transmit Enable
BBP_RE EQU 9 ; BBP Receive Enable
BBP_TIE EQU 10 ; BBP Transmit Interrupt Enable
BBP_RIE EQU 11 ; BBP Receive Interrupt Enable
BBP_TLIE EQU 12 ; BBP Transmit Last Slot Interrupt Enable
BBP_RLIE EQU 13 ; BBP Receive Last Slot Interrupt Enable
BBP_TEIE EQU 14 ; BBP Transmit Error Interrupt Enable
BBP_REIE EQU 15 ; BBP Receive Error Interrupt Enable
; BBP Control Register C Bit Flags
BBP_SYN EQU 0 ; Sync/Async Control
BBP_MOD EQU 1 ; BBP Mode Select
BBP_SCD EQU $1C ; Serial Control Direction Mask
BBP_SCD0 EQU 2 ; Serial Control 0 Direction
BBP_SCD1 EQU 3 ; Serial Control 1 Direction
BBP_SCD2 EQU 4 ; Serial Control 2 Direction
BBP_SCKD EQU 5 ; Clock Source Direction
BBP_CKP EQU 6 ; Clock Polarity
BBP_SHFD EQU 7 ; Shift Direction
BBP_FSL EQU $3000 ; Frame Sync Length Mask (FSL0-FSL1)
BBP_FSL0 EQU 12 ; Frame Sync Length 0
BBP_FSL1 EQU 13 ; Frame Sync Length 1
BBP_FSR EQU 14 ; Frame Sync Relative Timing
BBP_FSP EQU 15 ; Frame Sync Polarity
; BBP Status Register Bit Flags
BBP_IF EQU $3 ; Serial Input Flag Mask
BBP_IF0 EQU 0 ; Serial Input Flag 0
BBP_IF1 EQU 1 ; Serial Input Flag 1
BBP_TFS EQU 2 ; Transmit Frame Sync Flag
BBP_RFS EQU 3 ; Receive Frame Sync Flag
BBP_TUE EQU 4 ; Transmitter Underrun Error FLag
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DSP Equates
BBP_ROE EQU 5 ; Receiver Overrun Error Flag
BBP_TDE EQU 6 ; Transmit Data Register Empty
BBP_RDF EQU 7 ; Receive Data Register Full
;------------------------------------------------------------------------
;
; EQUATES for Serial Audio Port (SAP)
;
;------------------------------------------------------------------------
; Register Addresses Of SAP
SAP_PCRA EQU $FFBF ; SAP Port Control Register
SAP_PRRA EQU $FFBE ; SAP GPIO Direction Register
SAP_PDRA EQU $FFBD ; SAP GPIO Data Register
SAP_TXA EQU $FFBC ; SAP Transmit Data Register
SAP_TSRA EQU $FFBB ; SAP Time Slot Register
SAP_RXA EQU $FFBA ; SAP Receive Data Register
SAP_SSISRA EQU $FFB9 ; SAP Status Register
SAP_CRCA EQU $FFB8 ; SAP Control Register C
SAP_CRBA EQU $FFB7 ; SAP Control Register B
SAP_CRAA EQU $FFB6 ; SAP Control Register A
SAP_TCLR EQU $FFB5 ; SAP Timer Preload register
SAP_TCRA EQU $FFB4 ; SAP Timer count register
; SAP Control Register A Bit Flags
SAP_PSR EQU 15 ; Prescaler Range
SAP_DC EQU $1F00 ; Frame Rate Divider Control Mask (DC0-DC7)
SAP_WL EQU $6000 ; Word Length Control Mask (WL0-WL7)
; SAP Control register B Bit Flags
SAP_OF EQU $3 ; Serial Output Flag Mask
SAP_OF0 EQU 0 ; Serial Output Flag 0
SAP_OF1 EQU 1 ; Serial Output Flag 1
SAP_TCE EQU 2 ; SAP Timer enable
SAP_TE EQU 8 ; SAP Transmit Enable
SAP_RE EQU 9 ; SAP Receive Enable
SAP_TIE EQU 10 ; SAP Transmit Interrupt Enable
SAP_RIE EQU 11 ; SAP Receive Interrupt Enable
SAP_TLIE EQU 12 ; SAP Transmit Last Slot Interrupt Enable
SAP_RLIE EQU 13 ; SAP Receive Last Slot Interrupt Enable
SAP_TEIE EQU 14 ; SAP Transmit Error Interrupt Enable
SAP_REIE EQU 15 ; SAP Receive Error Interrupt Enable
; SAP Control Register C Bit Flags
SAP_SYN EQU 0 ; Sync/Async Control
SAP_MOD EQU 1 ; SAP Mode Select
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DSP Equates
SAP_SCD EQU $1C ; Serial Control Direction Mask
SAP_SCD0 EQU 2 ; Serial Control 0 Direction
SAP_SCD1 EQU 3 ; Serial Control 1 Direction
SAP_SCD2 EQU 4 ; Serial Control 2 Direction
SAP_SCKD EQU 5 ; Clock Source Direction
SAP_CKP EQU 6 ; Clock Polarity
SAP_SHFD EQU 7 ; Shift Direction
SAP_BRM EQU 8 ; Binary Rate Multiplier (BRM) enable
SAP_FSL EQU $3000 ; Frame Sync Length Mask (FSL0-FSL1)
SAP_FSL0 EQU 12 ; Frame Sync Length 0
SAP_FSL1 EQU 13 ; Frame Sync Length 1
SAP_FSR EQU 14 ; Frame Sync Relative Timing
SAP_FSP EQU 15 ; Frame Sync Polarity
; SAP Status Register Bit Flags
SAP_IF EQU $3 ; Serial Input Flag Mask
SAP_IF0 EQU 0 ; Serial Input Flag 0
SAP_IF1 EQU 1 ; Serial Input Flag 1
SAP_TFS EQU 2 ; Transmit Frame Sync Flag
SAP_RFS EQU 3 ; Receive Frame Sync Flag
SAP_TUE EQU 4 ; Transmitter Underrun Error FLag
SAP_ROE EQU 5 ; Receiver Overrun Error Flag
SAP_TDE EQU 6 ; Transmit Data Register Empty
SAP_RDF EQU 7 ; Receive Data Register Full
;------------------------------------------------------------------------
;
; EQUATES for Exception Processing
;
;------------------------------------------------------------------------
if @DEF(I_VEC)
; leave user definition as it is.
else
I_VEC equ $0
endif
;------------------------------------------------------------------------
; Non-Maskable interrupts
;------------------------------------------------------------------------
I_RESET EQU I_VEC+$00 ; Hardware RESET
I_STACK EQU I_VEC+$02 ; Stack Error
I_ILL EQU I_VEC+$04 ; Illegal Instruction
I_DBG EQU I_VEC+$06 ; Debug Request
I_TRAP EQU I_VEC+$08 ; Trap
;------------------------------------------------------------------------
; Interrupt Request Pins
;------------------------------------------------------------------------
I_IRQA EQU I_VEC+$10 ; IRQA
I_IRQB EQU I_VEC+$12 ; IRQB - from DSP_IRQ pin
I_IRQC EQU I_VEC+$14 ; IRQC - from MDI wake up from stop
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DSP Equates
I_IRQD EQU I_VEC+$16 ; IRQD - from Protocol Timer wake from stop
;------------------------------------------------------------------------
; Protocol Timer Interrupts
;------------------------------------------------------------------------
I_PT_CVR0 EQU I_VEC+$20 ; Protocol Timer CVR0
I_PT_CVR1 EQU I_VEC+$22 ; Protocol Timer CVR1
I_PT_CVR2 EQU I_VEC+$24 ; Protocol Timer CVR2
I_PT_CVR3 EQU I_VEC+$26 ; Protocol Timer CVR3
I_PT_CVR4 EQU I_VEC+$28 ; Protocol Timer CVR4
I_PT_CVR5 EQU I_VEC+$2A ; Protocol Timer CVR5
I_PT_CVR6 EQU I_VEC+$2C ; Protocol Timer CVR6
I_PT_CVR7 EQU I_VEC+$2E ; Protocol Timer CVR7
I_PT_CVR8 EQU I_VEC+$30 ; Protocol Timer CVR8
I_PT_CVR9 EQU I_VEC+$32 ; Protocol Timer CVR9
I_PT_CVR10 EQU I_VEC+$34 ; Protocol Timer CVR10
I_PT_CVR11 EQU I_VEC+$36 ; Protocol Timer CVR11
I_PT_CVR12 EQU I_VEC+$38 ; Protocol Timer CVR12
I_PT_CVR13 EQU I_VEC+$3A ; Protocol Timer CVR13
I_PT_CVR14 EQU I_VEC+$3C ; Protocol Timer CVR14
I_PT_CVR15 EQU I_VEC+$3E ; Protocol Timer CVR15
;------------------------------------------------------------------------
; SAP Interrupts
;------------------------------------------------------------------------
I_SAP_RD EQU I_VEC+$40 ; SAP Receive Data
I_SAP_RDE EQU I_VEC+$42 ; SAP Receive Data With Exception Status
I_SAP_RLS EQU I_VEC+$44 ; SAP Receive last slot
I_SAP_TD EQU I_VEC+$46 ; SAP Transmit data
I_SAP_TDE EQU I_VEC+$48 ; SAP Transmit Data With Exception Status
I_SAP_TLS EQU I_VEC+$4A ; SAP Transmit last slot
I_SAP_TRO EQU I_VEC+$4C ; SAP Timer counter roll-over
;------------------------------------------------------------------------
; BBP Interrupts
;------------------------------------------------------------------------
I_BBP_RD EQU I_VEC+$50 ; BBP Receive Data
I_BBP_RDE EQU I_VEC+$52 ; BBP Receive Data With Exception Status
I_BBP_RLS EQU I_VEC+$54 ; BBP Receive last slot
I_BBP_RRO EQU I_VEC+$56 ; BBP Receive Frame rolls over
I_BBP_TD EQU I_VEC+$58 ; BBP Transmit data
I_BBP_TDE EQU I_VEC+$5A ; BBP Transmit Data With Exception Status
I_BBP_TLS EQU I_VEC+$5C ; BBP Transmit last slot
I_BBP_TRO EQU I_VEC+$5E ; BBP Transmit Frame rolls over
;------------------------------------------------------------------------
; MDI DSP-side interrupts
;------------------------------------------------------------------------
I_MDI_MCU EQU I_VEC+$60 ; MDI MCU default command vector
I_MDI_RR0 EQU I_VEC+$62 ; MDI Receive Register 0 interrupt
I_MDI_RR1 EQU I_VEC+$64 ; MDI Receive Register 1 interrupt
I_MDI_TR0 EQU I_VEC+$66 ; MDI Transmit Register 0 interrupt
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DSP Equates
I_MDI_TR1 EQU I_VEC+$68 ; MDI Transmit Register 1 interrupt
;------------------------------------------------------------------------
; INTERRUPT ENDING ADDRESS
;------------------------------------------------------------------------
I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space
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Appendix C
Boundary Scan Register
This appendix provides detailed information on the Boundary Scan Register (BSR), including bit descriptions and the Boundary Scan Description Language (BSDL) listing for the DSP56652 in the 196-pin Plastic Ball Grid Array (PBGA) package.
C.1 BSR Bit Definitions
Table C-1 is a list of the BSR bit definitions.
Motorola Boundary Scan Register
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BSR Bit Definitions
Pin Name
INT4
INT4
INT3
INT3
INT2
INT2
INT1
INT1
ROW0
ROW0
INT7
INT7
INT6
INT6
INT5
INT5
ROW4
ROW4
ROW3
ROW3
ROW2
ROW2
ROW1
ROW1
DSP_DE
DSP_DE
ROW7
ROW7
ROW6
ROW6
ROW5
ROW5
INT0
INT0
COLUMN7
COLUMN7
COLUMN6
COLUMN6
COLUMN5
COLUMN5
Bit #
28
29
30
31
24
25
26
27
20
21
22
23
16
17
18
19
36
37
38
39
32
33
34
35
12
13
14
15
8
9
10
11
6
7
4
5
2
3
0
1
Table C-1. BSR Bit Definitions
Pin Type
input/output
input/output
-
-
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
Cell Type control data control data control data control data control data control data control control control data control data control data control data control data control data control data control data control data control data control data control data control data
Bit #
68
69
70
71
64
65
66
67
60
61
62
63
56
57
58
59
76
77
78
79
72
73
74
75
52
53
54
55
48
49
50
51
44
45
46
47
40
41
42
43
Pin Name
SENSE
SENSE
SIMDATA
SIMDATA
PWR_EN
PWR_EN
SIMCLK
SIMCLK
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
COLUMN4
COLUMN4
COLUMN3
COLUMN3
COLUMN2
COLUMN2
COLUMN1
COLUMN1
COLUMN0
COLUMN0
STO
RESET_IN
RESET_OUT
BMODE
SIMRESET
SIMRESET
DATA[15:8]
DATA[7:0]
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
Cell Type data data data data data data data data control data control data control data control data control control data data data data data data control data data data data data control data control data control data control data control data
Pin Type
input/output
input/output
input/output
input/output input/output input/output input/output input/output input/output input/output input/output input/output
input/output
input/output
input/output
input/output
input/output output input output input
input/output
-
input/output input/output input/output input/output input/output input/output
C-2 DSP56652 UserÕs Manual
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BSR Bit Definitions
Pin Name
EB1
ADDR0
ADDR1
ADDR2
ADDR3
ADDR[7:0]
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
CS1
CS0
R/W
OE
CKO
CKOH
CKIL
EB0
DATA1
DATA0
CS5
CS4
CS3
CS2
R/W
EB0,EB1
ADDR14
ADDR15
ADDR[19:8]
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
Bit #
108
109
110
111
104
105
106
107
100
101
102
103
96
97
98
99
116
117
118
119
112
113
114
115
92
96
94
95
88
89
90
91
84
85
86
87
80
81
82
83
Table C-1. BSR Bit Definitions
Pin Type input/output input/output input/output input/output input/output
input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output output output output output
-
output output input/output output output output input input/output input/output input/output
input/output input/output input/output input/output output
Cell Type data data data data data data data data data data data data data control data data data data control data data data data data data data data data data data data data data data data data data data control control
Bit #
148
149
150
151
144
145
146
147
140
141
142
143
136
137
138
139
156
157
158
159
152
153
154
155
132
133
134
135
128
129
130
131
124
125
126
127
120
121
122
123
Pin Name
SPICS1
SPICS0
SPICS0
SCK
SCK
MISO
MISO
MOSI
TOUT7
SPICS4
SPICS4
SPICS3
SPICS3
SPICS2
SPICS2
SPICS1
TOUT3
TOUT4
TOUT4
TOUT5
TOUT5
TOUT6
TOUT6
TOUT7
ADDR21
TOUT0
TOUT0
TOUT1
TOUT1
TOUT2
TOUT2
TOUT3
MOSI
DSP_IRQ
SCKB
SCKB
SCB0
SCB0
SCB1
SCB1
Cell Type data control data control data control data control data control data control data control data control data data control data control data control data data control data control data control data control data control data control data control data control
Pin Type input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output input
input/output
input/output
input/output
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Boundary Scan Description Language
Pin Name
SCA1
SCA1
SCA0
SCA0
SCKA
SCKA
SRDA
SRDA
SCB2
SCB2
SRDB
SRDB
STDB
STDB
SCA2
SCA2
STDA
STDA
PSTAT3
Bit #
172
173
174
175
168
169
170
171
164
165
166
167
160
161
162
163
176
177
178
Table C-1. BSR Bit Definitions
Pin Type
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
-
Cell Type control data control data control data control data control data control data control data control data control data control
Bit #
191
192
193
194
187
188
189
190
183
184
185
186
179
180
181
182
195
196
197
Pin Name
SIZ1
SIZ0
SIZ0
CTS
CTS
RTS
RTS
RX
PSTAT3
PSTAT2
PSTAT2
PSTAT1
PSTAT1
PSTAT0
PSTAT0
SIZ1
RX
TX
TX
Pin Type input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
input/output
Cell Type data control data control data control data control data control data control data control data control data control data
C.2 Boundary Scan Description Language
The following is a listing of the DSP56652 Boundary Scan Description Language.
-- M O T O R O L A S S D T J T A G S O F T W A R E
-- BSDL File Generated: Sun Feb 23 11:09:20 1997
--
-- Revision History:
-entity DSP56652 is
generic (PHYSICAL_PIN_MAP : string := "PBGA196");
port ( TRST_B: in bit;
TCK: in bit;
TMS: in bit;
TDI: in bit;
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Boundary Scan Description Language
TDO: out bit;
ADDR: inout bit_vector(0 to 19);
DATA: inout bit_vector(0 to 15);
RW_B: inout bit;
EB_B: inout bit_vector(0 to 1);
OE_B: buffer bit;
INT: inout bit_vector(0 to 7);
DSP_IRQ_B: in bit;
CS_B: buffer bit_vector(0 to 4);
CKIH: linkage bit;
CKIL: in bit;
CKO: buffer bit;
CKOH: buffer bit;
BMODE: in bit;
RESET_OUT_B: buffer bit;
RESET_IN_B: in bit;
STO: buffer bit;
MUX_CTL: linkage bit;
PCAP: linkage bit;
PVCC: linkage bit;
PGND: linkage bit;
P1GND: linkage bit;
SIZ: inout bit_vector(0 to 1);
PSTAT: inout bit_vector(0 to 3);
MCU_DE_B: linkage bit;
DSP_DE_B: inout bit;
TEST: linkage bit;
COLUMN: inout bit_vector(0 to 7);
ROW: inout bit_vector(0 to 7);
TX: inout bit;
RX: inout bit;
RTS_B: inout bit;
CTS_B: inout bit;
TOUT: inout bit_vector(0 to 7);
STDA: inout bit;
SRDA: inout bit;
SCKA: inout bit;
SCA: inout bit_vector(0 to 2);
STDB: inout bit;
SRDB: inout bit;
SCKB: inout bit;
SCB: inout bit_vector(0 to 2);
MOSI: inout bit;
MISO: inout bit;
SCK: inout bit;
SPICS: inout bit_vector(0 to 4);
SIMCLK: inout bit;
SENSE: inout bit;
SIMDATA: inout bit;
SIMRESET_B: inout bit;
PWR_EN: inout bit;
AVDD: linkage bit_vector(0 to 1);
AGND: linkage bit_vector(0 to 1);
CVDD: linkage bit;
CGND: linkage bit;
DVDD: linkage bit;
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Boundary Scan Description Language
DGND: linkage bit;
EVDD: linkage bit;
EGND: linkage bit;
FVDD: linkage bit;
FGND: linkage bit;
GVDD: linkage bit_vector(0 to 1);
GGND: linkage bit_vector(0 to 1);
HVDD: linkage bit;
HGND: linkage bit;
KVDD: linkage bit;
KGND: linkage bit;
BVDD: linkage bit;
BGND: linkage bit;
QVCC: linkage bit_vector(0 to 3);
QVCCH: linkage bit_vector(0 to 3);
QGND: linkage bit_vector(0 to 3);
CS5: buffer bit;
RESERVED: linkage bit;
ADDR20: buffer bit;
ADDR21: buffer bit);
use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56652: entity is
"STD_1149_1_1993"; -- complies with Std. 1149.1a-1993
attribute PIN_MAP of DSP56652 : entity is PHYSICAL_PIN_MAP; constant PBGA196 : PIN_MAP_STRING :=
"ADDR20: A2, " &
"TOUT: (A3, C4, B4, A4, D5, C5, A5, B5), " &
"SPICS: (E7, B6, E6, D6, A6), " &
"HGND: A7, " &
"QVCCH: (A8, G12, H5, P7), " &
"DSP_IRQ_B: A9, " &
"SRDB: A10, " &
"EGND: A11, " &
"SRDA: A12, " &
"STDA: A13, " &
"AGND: (B1, G2), " &
"ADDR: (G1, H3, G5, G4, G3, F5, F4, F2, E1, F3, E4, E3, E2,
D1, D4, D2, D3, C2, B2, C3), " &
"ADDR21: B3, " &
"QVCC: (B7, H1, J14, M8), " &
"MOSI: B8, " &
"SCB: (E9, D9, B9), " &
"SCA: (B10, C10, D10), " &
"SCKA: B11, " &
"PSTAT: (C13, B13, B12, C11), " &
"KGND: B14, " &
"AVDD: (C1, F1), " &
"HVDD: C6, " &
"QGND: (C7, H12, J2, N8), " &
"SCKB: C8, " &
"STDB: C9, " &
"KVDD: C12, " &
"SIZ: (D12, C14), " &
"SCK: D7, " &
C-6 DSP56652 UserÕs Manual
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Boundary Scan Description Language
"MISO: D8, " &
"EVDD: D11, " &
"MUX_CTL: D13, " &
"CTS_B: D14, " &
"RESERVED: E8, " &
"RTS_B: E11, " &
"RX: E12, " &
"TEST: E13, " &
"TX: E14, " &
"TDO: F10, " &
"TCK: F11, " &
"DSP_DE_B: F12, " &
"TDI: F13, " &
"TRST_B: F14, " &
"MCU_DE_B: G10, " &
"ROW: (K14, J13, J11, J10, H13, H14, G13, G11), " &
"TMS: G14, " &
"EB_B: (H4, H2), " &
"GGND: (H10, L13), " &
"GVDD: (H11, L11), " &
"FGND: J1, " &
"CKIH: J3, " &
"CKOH: J4, " &
"CKIL: J5, " &
"INT: (L12, N14, M14, L14, K13, K12, K11, J12), " &
"CKO: K1, " &
"FVDD: K2, " &
"OE_B: K3, " &
"RW_B: K4, " &
"DATA: (N3, M4, P2, P3, N4, L4, P4, N5, M6, P5, N6, L6, K6,
M7, P6, N7), " &
"PWR_EN: K7, " &
"BGND: K8, " &
"PVCC: K9, " &
"CS_B: (L1, L2, M2, N1, M3), " &
"CVDD: L3, " &
"DGND: L5, " &
"SIMCLK: L7, " &
"BVDD: L8, " &
"PCAP: L9, " &
"RESET_IN_B: L10, " &
"CGND: M1, " &
"DVDD: M5, " &
"SIMDATA: M9, " &
"RESET_OUT_B: M10, " &
"COLUMN: (N11, M11, P12, N12, P13, M12, N13, M13), " &
"CS5: N2, " &
"SIMRESET_B: N9, " &
"P1GND: N10, " &
"SENSE: P8, " &
"PGND: P9, " &
"BMODE: P10, " &
"STO: P11 ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
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Boundary Scan Description Language
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_RESET of TRST_B : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of DSP56652 : entity is 4;
attribute INSTRUCTION_OPCODE of DSP56652 : entity is
"EXTEST (0000)," &
"SAMPLE (0001)," &
"IDCODE (0010)," &
"CLAMP (0101)," &
"HIGHZ (0100)," &
"ENABLE_MCU_ONCE (0011)," &
"ENABLE_DSP_ONCE (0110)," &
"DSP_DEBUG_REQUEST (0111)," &
"BYPASS (1111, 1000, 1001, 1010, 1011, 1100, 1101, 1110)";
attribute INSTRUCTION_CAPTURE of DSP56652 : entity is "0001";
attribute IDCODE_REGISTER of DSP56652 : entity is
"0000" & -- version
"000110" & -- manufacturer's use
"0001000010" & -- sequence number
"00000001110" & -- manufacturer identity
"1"; -- 1149.1 requirement
attribute REGISTER_ACCESS of DSP56652 : entity is
"BYPASS (ENABLE_MCU_ONCE,ENABLE_DSP_ONCE,DSP_DEBUG_REQUEST)" ;
attribute BOUNDARY_LENGTH of DSP56652 : entity is 198;
attribute BOUNDARY_REGISTER of DSP56652 : entity is
-- num cell port func safe [ccell dis rslt]
"0 (BC_1, *, control, 1)," &
"1 (BC_6, DSP_DE_B, bidir, X, 0, 1, Z)," &
"2 (BC_1, *, control, 1)," &
"3 (BC_6, ROW(7), bidir, X, 2, 1, Z)," &
"4 (BC_1, *, control, 1)," &
"5 (BC_6, ROW(6), bidir, X, 4, 1, Z)," &
"6 (BC_1, *, control, 1)," &
"7 (BC_6, ROW(5), bidir, X, 6, 1, Z)," &
"8 (BC_1, *, control, 1)," &
"9 (BC_6, ROW(4), bidir, X, 8, 1, Z)," &
"10 (BC_1, *, control, 1)," &
"11 (BC_6, ROW(3), bidir, X, 10, 1, Z)," &
"12 (BC_1, *, control, 1)," &
"13 (BC_6, ROW(2), bidir, X, 12, 1, Z)," &
"14 (BC_1, *, control, 1)," &
"15 (BC_6, ROW(1), bidir, X, 14, 1, Z)," &
"16 (BC_1, *, control, 1)," &
"17 (BC_6, ROW(0), bidir, X, 16, 1, Z)," &
"18 (BC_1, *, control, 1)," &
"19 (BC_6, INT(7), bidir, X, 18, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"20 (BC_1, *, control, 1)," &
"21 (BC_6, INT(6), bidir, X, 20, 1, Z)," &
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Boundary Scan Description Language
"22 (BC_1, *, control, 1)," &
"23 (BC_6, INT(5), bidir, X, 22, 1, Z)," &
"24 (BC_1, *, control, 1)," &
"25 (BC_6, INT(4), bidir, X, 24, 1, Z)," &
"26 (BC_1, *, control, 1)," &
"27 (BC_6, INT(3), bidir, X, 26, 1, Z)," &
"28 (BC_1, *, control, 1)," &
"29 (BC_6, INT(2), bidir, X, 28, 1, Z)," &
"30 (BC_1, *, control, 1)," &
"31 (BC_6, INT(1), bidir, X, 30, 1, Z)," &
"32 (BC_1, *, control, 1)," &
"33 (BC_6, INT(0), bidir, X, 32, 1, Z)," &
"34 (BC_1, *, control, 1)," &
"35 (BC_6, COLUMN(7), bidir, X, 34, 1, Z)," &
"36 (BC_1, *, control, 1)," &
"37 (BC_6, COLUMN(6), bidir, X, 36, 1, Z)," &
"38 (BC_1, *, control, 1)," &
"39 (BC_6, COLUMN(5), bidir, X, 38, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"40 (BC_1, *, control, 1)," &
"41 (BC_6, COLUMN(4), bidir, X, 40, 1, Z)," &
"42 (BC_1, *, control, 1)," &
"43 (BC_6, COLUMN(3), bidir, X, 42, 1, Z)," &
"44 (BC_1, *, control, 1)," &
"45 (BC_6, COLUMN(2), bidir, X, 44, 1, Z)," &
"46 (BC_1, *, control, 1)," &
"47 (BC_6, COLUMN(1), bidir, X, 46, 1, Z)," &
"48 (BC_1, *, control, 1)," &
"49 (BC_6, COLUMN(0), bidir, X, 48, 1, Z)," &
"50 (BC_1, STO, output2, X)," &
"51 (BC_1, RESET_IN_B, input, 0)," &
"52 (BC_1, RESET_OUT_B, output2, X)," &
"53 (BC_1, BMODE, input, X)," &
"54 (BC_1, *, control, 1)," &
"55 (BC_6, SIMRESET_B, bidir, X, 54, 1, Z)," &
"56 (BC_1, *, control, 1)," &
"57 (BC_6, SENSE, bidir, X, 56, 1, Z)," &
"58 (BC_1, *, control, 1)," &
"59 (BC_6, SIMDATA, bidir, X, 58, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"60 (BC_1, *, control, 1)," &
"61 (BC_6, PWR_EN, bidir, X, 60, 1, Z)," &
"62 (BC_1, *, control, 1)," &
"63 (BC_6, SIMCLK, bidir, X, 62, 1, Z)," &
"64 (BC_6, DATA(15), bidir, X, 72, 1, Z)," &
"65 (BC_6, DATA(14), bidir, X, 72, 1, Z)," &
"66 (BC_6, DATA(13), bidir, X, 72, 1, Z)," &
"67 (BC_6, DATA(12), bidir, X, 72, 1, Z)," &
"68 (BC_6, DATA(11), bidir, X, 72, 1, Z)," &
"69 (BC_6, DATA(10), bidir, X, 72, 1, Z)," &
"70 (BC_6, DATA(9), bidir, X, 72, 1, Z)," &
"71 (BC_6, DATA(8), bidir, X, 72, 1, Z)," &
"72 (BC_1, *, control, 1)," &
"73 (BC_1, *, control, 1)," &
"74 (BC_6, DATA(7), bidir, X, 73, 1, Z)," &
"75 (BC_6, DATA(6), bidir, X, 73, 1, Z)," &
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Boundary Scan Description Language
"76 (BC_6, DATA(5), bidir, X, 73, 1, Z)," &
"77 (BC_6, DATA(4), bidir, X, 73, 1, Z)," &
"78 (BC_6, DATA(3), bidir, X, 73, 1, Z)," &
"79 (BC_6, DATA(2), bidir, X, 73, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"80 (BC_6, DATA(1), bidir, X, 73, 1, Z)," &
"81 (BC_6, DATA(0), bidir, X, 73, 1, Z)," &
"82 (BC_1, CS5, output2, X)," &
"83 (BC_1, CS_B(4), output2, X)," &
"84 (BC_1, CS_B(3), output2, X)," &
"85 (BC_1, CS_B(2), output2, X)," &
"86 (BC_1, *, control, 1)," &
"87 (BC_1, *, control, 1)," &
"88 (BC_1, CS_B(1), output2, X)," &
"89 (BC_1, CS_B(0), output2, X)," &
"90 (BC_6, RW_B, bidir, X, 86, 1, Z)," &
"91 (BC_1, OE_B, output2, X)," &
"92 (BC_1, CKO, output2, X)," &
"93 (BC_1, CKOH, output2, X)," &
"94 (BC_1, CKIL, input, 0)," &
"95 (BC_6, EB_B(0), bidir, X, 87, 1, Z)," &
"96 (BC_6, EB_B(1), bidir, X, 87, 1, Z)," &
"97 (BC_6, ADDR(0), bidir, X, 101, 1, Z)," &
"98 (BC_6, ADDR(1), bidir, X, 101, 1, Z)," &
"99 (BC_6, ADDR(2), bidir, X, 101, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"100 (BC_6, ADDR(3), bidir, X, 101, 1, Z)," &
"101 (BC_1, *, control, 1)," &
"102 (BC_6, ADDR(4), bidir, X, 101, 1, Z)," &
"103 (BC_6, ADDR(5), bidir, X, 101, 1, Z)," &
"104 (BC_6, ADDR(6), bidir, X, 101, 1, Z)," &
"105 (BC_6, ADDR(7), bidir, X, 101, 1, Z)," &
"106 (BC_6, ADDR(8), bidir, X, 114, 1, Z)," &
"107 (BC_6, ADDR(9), bidir, X, 114, 1, Z)," &
"108 (BC_6, ADDR(10), bidir, X, 114, 1, Z)," &
"109 (BC_6, ADDR(11), bidir, X, 114, 1, Z)," &
"110 (BC_6, ADDR(12), bidir, X, 114, 1, Z)," &
"111 (BC_6, ADDR(13), bidir, X, 114, 1, Z)," &
"112 (BC_6, ADDR(14), bidir, X, 114, 1, Z)," &
"113 (BC_6, ADDR(15), bidir, X, 114, 1, Z)," &
"114 (BC_1, *, control, 1)," &
"115 (BC_6, ADDR(16), bidir, X, 114, 1, Z)," &
"116 (BC_6, ADDR(17), bidir, X, 114, 1, Z)," &
"117 (BC_6, ADDR(18), bidir, X, 114, 1, Z)," &
"118 (BC_6, ADDR(19), bidir, X, 114, 1, Z)," &
"119 (BC_1, ADDR20, output2, X)," &
-- num cell port func safe [ccell dis rslt]
"120 (BC_1, ADDR21, output2, X)," &
"121 (BC_1, *, control, 1)," &
"122 (BC_6, TOUT(0), bidir, X, 121, 1, Z)," &
"123 (BC_1, *, control, 1)," &
"124 (BC_6, TOUT(1), bidir, X, 123, 1, Z)," &
"125 (BC_1, *, control, 1)," &
"126 (BC_6, TOUT(2), bidir, X, 125, 1, Z)," &
"127 (BC_1, *, control, 1)," &
"128 (BC_6, TOUT(3), bidir, X, 127, 1, Z)," &
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Boundary Scan Description Language
"129 (BC_1, *, control, 1)," &
"130 (BC_6, TOUT(4), bidir, X, 129, 1, Z)," &
"131 (BC_1, *, control, 1)," &
"132 (BC_6, TOUT(5), bidir, X, 131, 1, Z)," &
"133 (BC_1, *, control, 1)," &
"134 (BC_6, TOUT(6), bidir, X, 133, 1, Z)," &
"135 (BC_1, *, control, 1)," &
"136 (BC_6, TOUT(7), bidir, X, 135, 1, Z)," &
"137 (BC_1, *, control, 1)," &
"138 (BC_6, SPICS(4), bidir, X, 137, 1, Z)," &
"139 (BC_1, *, control, 1)," &
"140 (BC_6, SPICS(3), bidir, X, 139, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"141 (BC_1, *, control, 1)," &
"142 (BC_6, SPICS(2), bidir, X, 141, 1, Z)," &
"143 (BC_1, *, control, 1)," &
"144 (BC_6, SPICS(1), bidir, X, 143, 1, Z)," &
"145 (BC_1, *, control, 1)," &
"146 (BC_6, SPICS(0), bidir, X, 145, 1, Z)," &
"147 (BC_1, *, control, 1)," &
"148 (BC_6, SCK, bidir, X, 147, 1, Z)," &
"149 (BC_1, *, control, 1)," &
"150 (BC_6, MISO, bidir, X, 149, 1, Z)," &
"151 (BC_1, *, control, 1)," &
"152 (BC_6, MOSI, bidir, X, 151, 1, Z)," &
"153 (BC_1, DSP_IRQ_B, input, X)," &
"154 (BC_1, *, control, 1)," &
"155 (BC_6, SCKB, bidir, X, 154, 1, Z)," &
"156 (BC_1, *, control, 1)," &
"157 (BC_6, SCB(0), bidir, X, 156, 1, Z)," &
"158 (BC_1, *, control, 1)," &
"159 (BC_6, SCB(1), bidir, X, 158, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"160 (BC_1, *, control, 1)," &
"161 (BC_6, SCB(2), bidir, X, 160, 1, Z)," &
"162 (BC_1, *, control, 1)," &
"163 (BC_6, SRDB, bidir, X, 162, 1, Z)," &
"164 (BC_1, *, control, 1)," &
"165 (BC_6, STDB, bidir, X, 164, 1, Z)," &
"166 (BC_1, *, control, 1)," &
"167 (BC_6, SCA(2), bidir, X, 166, 1, Z)," &
"168 (BC_1, *, control, 1)," &
"169 (BC_6, SCA(1), bidir, X, 168, 1, Z)," &
"170 (BC_1, *, control, 1)," &
"171 (BC_6, SCA(0), bidir, X, 170, 1, Z)," &
"172 (BC_1, *, control, 1)," &
"173 (BC_6, SCKA, bidir, X, 172, 1, Z)," &
"174 (BC_1, *, control, 1)," &
"175 (BC_6, SRDA, bidir, X, 174, 1, Z)," &
"176 (BC_1, *, control, 1)," &
"177 (BC_6, STDA, bidir, X, 176, 1, Z)," &
"178 (BC_1, *, control, 1)," &
"179 (BC_6, PSTAT(3), bidir, X, 178, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"180 (BC_1, *, control, 1)," &
"181 (BC_6, PSTAT(2), bidir, X, 180, 1, Z)," &
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Boundary Scan Description Language
"182 (BC_1, *, control, 1)," &
"183 (BC_6, PSTAT(1), bidir, X, 182, 1, Z)," &
"184 (BC_1, *, control, 1)," &
"185 (BC_6, PSTAT(0), bidir, X, 184, 1, Z)," &
"186 (BC_1, *, control, 1)," &
"187 (BC_6, SIZ(1), bidir, X, 186, 1, Z)," &
"188 (BC_1, *, control, 1)," &
"189 (BC_6, SIZ(0), bidir, X, 188, 1, Z)," &
"190 (BC_1, *, control, 1)," &
"191 (BC_6, CTS_B, bidir, X, 190, 1, Z)," &
"192 (BC_1, *, control, 1)," &
"193 (BC_6, RTS_B, bidir, X, 192, 1, Z)," &
"194 (BC_1, *, control, 1)," &
"195 (BC_6, RX, bidir, X, 194, 1, Z)," &
"196 (BC_1, *, control, 1)," &
"197 (BC_6, TX, bidir, X, 196, 1, Z)" ; end DSP56652;
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Appendix D
ProgrammerÕs Reference
This appendix provides a set of reference tables to simplify programming the DSP56652.
The tables include the following:
¥ Instruction set summaries for both the MCU and DSP.
¥ I/O memory maps listing the configuration registers in numerical order.
¥ A register index providing an alphabetical list of registers and the page numbers in this manual where they are described.
¥ A list of acronym and bit name changes from previous 56000 and M
·
CORE family devices.
D.1 MCU Instruction Reference Tables
summary table. For complete MCU instruction set details, see Section 3 of the MCU
Reference Manual (MCORERM/AD).
Mnemonic
ABS
ADDC
ADDI
ADDU
AND
ANDI
ANDN
ASR
Table D-1. MCU Instruction Set Summary
Instruction Syntax
ABS RX
ADDC RX,RY
ADDI RX,OIMM5
ADDU RX,RY
AND RX,RY
ANDI RX,IMM5
ANDN RX,RY
ASR RX,RY
Opcode
0000 0001 1110 rrrr
0000 0110 ssss rrrr
0010 000i iiii rrrr
0001 1100 ssss rrrr
0001 0110 ssss rrrr
0010 0011 0000 rrrr
0001 1111 ssss rrrr
0001 1010 ssss rrrr
C Bit
Unaffected
C ¬ carryout
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
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MCU Instruction Reference Tables
BR
BREV
BSETI
BSR
BT
BTSTI
ASRI
BCLRI
BF
BGENI
BGENR
BKPT
BMASKI
Mnemonic
ASRC
CLRF
CLRT
CMPHS
CMPLT
CMPLTI
CMPNE
CMPNEI
DECF
DECGT
DECLT
DECNE
DECT
Table D-1. MCU Instruction Set Summary (Continued)
Instruction Syntax
ASRC RX
ASRI RX,IMM5
BCLRI RX,IMM5
BF LABEL
BGENI RX,IMM5
BGENR RX,RY
BKPT
BMASKI RX,IMM5
BR LABEL
BREV RX
BSETI RX,IMM5
BSR LABEL
BT LABEL
BTSTI RX,IMM5
CLRF RX
CLRT RX
CMPHS RX,RY
CMPLT RX,RY
CMPLTI RX,OIMM5
CMPNE RX,RY
CMPNEI RX,IMM5
DECF RX
DECGT RX
DECLT RX
DECNE RX
DECT RX
Opcode
0011 1010 0000 rrrr
0011 101i iiii rrrr
0011 000i iiii rrrr
1110 1ddd dddd dddd
0011 0010 0111 rrrr
0001 0011 ssss rrrr
0000 0000 0000 0000
0010 0011 0000 rrrr
1111 0ddd dddd dddd
0000 0000 1111 rrrr
0011 010i iiii rrrr
1111 1ddd dddd dddd
1110 0ddd dddd dddd
0011 011i iiii rrrr
0000 0001 1101 rrrr
0000 0001 1100 rrrr
0000 1100 ssss rrrr
0000 1101 ssss rrrr
0010 001i iiii rrrr
0000 1111 ssss rrrr
0010 101i iiii rrrr
0000 0000 1001 rrrr
0000 0001 1010 rrrr
0000 0001 1000 rrrr
0000 0001 1011 rrrr
0000 0000 1000 rrrr
C Bit
RX copied into C bit before shifting
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected n/a
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Set to value of RX pointed to by IMM5
Unaffected
Unaffected
Set as a result of comparison
Set as a result of comparison
Set as a result of comparison
Set as a result of comparison
Set as a result of comparison
Unaffected
Set if RX > 0, else bit is cleared
Set if RX < 0, else bit is cleared
Set if RX ¹ 0, else bit is cleared
Unaffected
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MCU Instruction Reference Tables
LSRI
MFCR
MOV
MOVF
MOVI
MOVT
Mnemonic
DIVS
DIVU
DOZE
FF1
INCF
INCT
IXH
IXW
JMP
JMPI
JSR
JSRI
LD.[BHW]
LDM
LDQ
LOOPT
LRW
LSL
LSLC
LSLI
LSR
LSRC
Table D-1. MCU Instruction Set Summary (Continued)
Instruction Syntax
DIVS RX,R1
DIVU RX,R1
DOZE
FF1 RX,R1
INCF RX
INCT RX
IXH RX,RY
IXW RX,RY
JMP RX
JMPI [LABEL]
JSR RX
JSRI [LABEL]
LD.[B, H, W] RZ, (RX,DISP)
[LD, LDB, LDH, LDW] RZ,(RX,DISP)
LDM RFÐR15,(R0)
LDQ R4ÐR7,(RX)
LOOPT RY,LABEL
Opcode
0011 0010 0001 rrrr
0010 0011 0001 rrrr
0000 0000 0000 0110
0000 0000 1110 rrrr
0000 0000 1011 rrrr
0000 0000 1010 rrrr
0001 1101 ssss rrrr
0001 0101 ssss rrrr
0000 0000 1100 rrrr
0111 0000 dddd dddd
0000 0000 1101 rrrr
0111 1111 dddd dddd
1000 zzzz iiii rrrr
0000 0000 0110 rrrr
0000 0000 0100 rrrr
0000 0100 ssss bbbb
C Bit
Undefined
Undefined
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
LRW RZ,LABEL
LSL RX,RY
LSLC RX
LSLI RX,IMM5
LSR RX,RY
LSRC RX
LSRI RX,IMM5
MFCR RX,CRY
MOV RX,RY
MOVF RX,RY
MOVI RX,IMM7
MOVT RX,RY
0111 zzzz dddd dddd
0001 1011 ssss rrrr
0011 1100 0000 rrrr
0011 110i iiii rrrr
0000 1011 ssss rrrr
0011 1110 0000 rrrr
0011 111i iiii rrrr
0001 000c cccc rrrr
0001 0010 ssss rrrr
0000 1010 ssss rrrr
0110 0iii iiii rrrr
0000 0010 ssss rrrr
Unaffected
Unaffected
Set if signed result in
RY > 0, else bit is cleared
Unaffected
Unaffected
Copy RX[31] into C before shifting
Unaffected
Unaffected
Copy RX0 into C before shifting
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
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MCU Instruction Reference Tables
STM
STOP
STQ
SUBC
SUBI
SUBU
MULT
MVC
MVCV
NOT
OR
RFI
ROTLI
RSUB
RSUBI
RTE
SEXTB
SEXTH
ST.[BHW]
Mnemonic
MTCR
SYNC
TRAP
TST
TSTNBZ
WAIT
XOR
XSR
XTRB0
Table D-1. MCU Instruction Set Summary (Continued)
Instruction Syntax
MTCR RX, CRY
MULT RX,RY
MVC RX
MVCV RX
NOT RX
OR RX,RY
RFI
ROTLI RX,IMM5
RSUB RX,RY
RSUBI RX,IMM5
RTE
SEXTB RX
SEXTH RX
ST.[B, H, W] RZ, (RX,DISP)
[ST, STB, STH, STW] RZ,(RX,DISP)
STM RFÐR15,(R0)
STOP
STQ R4ÐR7,(RX)
SUBC RX,RY
SUBI RX,IMM5
SUBU RX,RY
SUB RX,RY
SYNC
TRAP #TRAP_NUMBER
TST RX,RY
Opcode
0001 100c cccc rrrr
0000 0011 ssss rrrr
0000 0000 0001 rrrr
0000 0000 0011 rrrr
0000 0001 1111 rrrr
0001 1110 ssss rrrr
0000 0000 0000 0011
0011 100i iiii rrrr
0001 0100 ssss rrrr
0010 100i iiii rrrr
0000 0000 0000 0010
0000 0001 0101 rrrr
0000 0001 0111 rrrr
1001 zzzz iiii rrrr
0000 0000 0111 rrrr
0000 0000 0000 0100
0000 0000 0101 rrrr
0000 0111 ssss rrrr
0010 010i iiii rrrr
0000 0101 ssss rrrr
0000 0000 0000 0001
0000 0000 0000 10ii
0000 1110 ssss rrrr
C Bit
Unaffected unless CR0
(PSR) specified
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected n/a
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
C ¬ carryout
Unaffected
Unaffected
TSTNBZ RX
WAIT
XOR RX,RY
XSR RX
XTRB0 R1,RX
0000 0001 1001 rrrr
0000 0000 0000 0101
0001 0111 ssss rrrr
0011 1000 0000 rrrr
0000 0001 0011 rrrr
Unaffected
Unaffected
Set if (RX & RY) ¹ 0, else bit is cleared
Set to result of test n/a
Unaffected
Set to original value of
RX[0]
Set if result ¹ 0, else bit is cleared
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MCU Instruction Reference Tables
Mnemonic
XTRB1
XTRB2
XTRB3
ZEXTB
ZEXTH
Table D-1. MCU Instruction Set Summary (Continued)
Instruction Syntax
XTRB1 R1,RX
XTRB2 R1,RX
XTRB3 R1,RX
ZEXTB RX
ZEXTH RX
Opcode
0000 0001 001 0 rrrr
0000 0001 0001 rrrr
0000 0001 0000 rrrr
0000 0001 0100 rrrr
0000 0001 0110 rrrr
C Bit
Set if result ¹ 0, else bit is cleared
Set if result ¹ 0, else bit is cleared
Set if result ¹ 0, else bit is cleared
Unaffected
Unaffected
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MCU Instruction Reference Tables
Symbol
DISP
B
H
W
RF
R4ÐR7
CRY
RX
RY
RZ
IMM5
OIMM5
IMM7
LABEL
R1
Table D-2. MCU Instruction Syntax Notation
Description
Source or destination register R0 Ð R15
Source or destination register R0ÐR15
Source or destination register R0ÐR15 (range may be restricted)
5-bit immediate value
5-bit immediate value offset (incremented) by 1
7-bit immediate value
Register R1
Displacement specified
Byte (8 bits)
Half-word (16 bits)
Word (32 bits)
Register First (any register from R1 to R14; R0 and R15 are invalid)
The four registers R4ÐR7
Source control register CR0ÐCR31
Table D-3. MCU Instruction Opcode Notation
Symbol Description rrrr ssss zzzz ffff cccc iii ... i xx ... x
RX field
RY field
RZ field
Rfirst field
Control register specifier
One of several immediate fields
Undefined fields
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DSP Instruction Reference Tables
D.2 DSP Instruction Reference Tables
Table D-4 provide a brief summary of the instruction set for the DSP core. Table D-5,
Table D-6, and Table D-7 list the abbreviations used in the instruction set summary table.
For complete DSP instruction set details, see Appendix A of the DSP56600 Family
Manual (DSP56600FM/AD).
Mnemonic
ABS
ADC
ADD
ADDL
ADDR
AND
AND
ANDI
ASL
ASR
Bcc
BCHG
BCLR
BRA
Table D-4. DSP Instruction Set Summary
Syntax
ABS D
ADC S,D
ADD S,D
ADD #iiiiii,D
ADD #iii,D
ADDL S,D
ADDR S,D
AND S,D
AND #iiiiii,D
AND #iii,D
ANDI EE
ASL S,D
ASL #ii,S,D
ASL sss,S,D
ASR S,D
ASR sss,S,D
ASR #ii,S,D
Bcc (PC + Rn)
Bcc (PC + aa)
BCHG #bbbb , S:<aa>
BCHG #bbbb , S:<ea>
BCHG #bbbb , S:<pp>
BCHG #bbbb , S:<qq>
BCHG #bbbb, DDDDDD
BCLR #bbbb , S:<pp>
BCLR #bbbb , S:<ea>
BCLR #bbbb , S:<aa>
BCLR #bbbb , S:<qq>
BCLR #bbbb , DDDDDD
BRA (PC + Rn)
BRA (PC + aa)
P T
2
1
2
1
3
1
1
Ñ
Ñ
Ñ
Ñ
4
4
1
1
Ñ 2
Ñ 2 + U + A
Ñ
Ñ
2
2
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
2
2
Ñ 2 + U + A
Ñ 2
2
2
4
4
P
Ñ
Ñ
P
P
Ñ
Ñ
Ñ
Ñ
Ñ
P
P
P
P
P
CCR
S L E U N Z V C
* * *
* * *
* * *
* * *
* * *
* * *
* * *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* ?
* *
*
*
* Ñ
*
*
*
*
*
*
*
*
* Ñ Ñ Ñ ?
?
0 Ñ
* Ñ Ñ Ñ ?
?
0 Ñ
* Ñ Ñ Ñ ?
?
0 Ñ
?
?
?
?
?
?
?
?
* * *
* * *
* * *
* * *
*
*
*
*
*
*
*
*
*
*
*
*
?
?
?
0
?
?
?
?
* * *
* * *
*
*
*
*
* 0 ?
* 0 ?
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
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DSP Instruction Reference Tables
Mnemonic
Table D-4. DSP Instruction Set Summary (Continued)
Syntax P T
BRKcc
BScc
BSET
BSR
BTST
CLB
CLR
CMPM
CMPU
DEBUG DEBUG
DEBUGcc DEBUGcc
DEC
DIV
DMAC
DO
DO S:<aa>,aaaa
DO FOREVER DO FOREVER , (aaaa)
ENDDO
EOR
EXTRACT
BRKcc Ñ
BScc (PC + Rn) Ñ
BScc (PC + aa)
BSET #bbbb,S:<pp>
Ñ
Ñ
BSET #bbbb, S:<ea>
BSET #bbbb, S:<aa>
BSET #bbbb , DDDDDD
BSET #bbbb , S:<qq>
5
4
4
2
Ñ 2 + U + A
Ñ 2
Ñ
Ñ
2
2
BSR (PC + Rn)
BSR (PC + aa)
BTST #bbbb,S:<pp>
BTST #bbb ,S:<ea>
BTST #bbbb,S:<aa>
BTST #bbbb , DDDDDD
BTST #bbbb,S:<qq>
CLB S,D
CLR D
Ñ
Ñ
Ñ 2
Ñ 2 + U + A
Ñ
Ñ
Ñ
Ñ
4
4
2
2
2
1
CMP #iiiiii,D
CMP #iii,D
CMPM S1,S2
CMPU ggg,D
DEC
DIV
DMAC S1,S2,D (ss,su,uu)
DO #xxx,aaaa
DO DDDDDD,aaaa
DO S:<ea>,aaaa
ENDDO
EOR S,D
EOR #iiiiii,D
EOR #iii,D
EXTRACT SSS,s,D
EXTRACT #iiii,s,D
P
Ñ
Ñ
Ñ
P
P
Ñ
Ñ
Ñ
Ñ
N
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
P
Ñ
Ñ
Ñ
Ñ
2
1
1
2
2
1
1
5
1
1
1
1
5
5
5 + U
5
4
1
CCR
S L E U N Z V C
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ ?
* * Ñ Ñ Ñ Ñ Ñ ?
* * Ñ Ñ Ñ Ñ Ñ ?
* * Ñ Ñ Ñ Ñ Ñ ?
* * Ñ Ñ Ñ Ñ Ñ ?
Ñ Ñ Ñ Ñ ?
?
0 Ñ
* * 0 1 0 1 0 Ñ
* * * * * * * *
* * *
* * *
*
*
*
*
*
*
*
*
*
*
* * * * *
Ñ Ñ Ñ Ñ *
* * *
?
0 *
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ * * * * * * *
Ñ ?
Ñ Ñ Ñ Ñ ?
?
Ñ * * * * * * Ñ
?
?
Ñ Ñ Ñ Ñ Ñ Ñ
?
?
Ñ Ñ Ñ Ñ Ñ Ñ
?
?
Ñ Ñ Ñ Ñ Ñ Ñ
?
?
Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ ?
?
0 Ñ
* * Ñ Ñ ?
?
0 Ñ
* * Ñ Ñ ?
?
0 Ñ
Ñ Ñ *
Ñ Ñ *
*
*
*
*
*
*
0 0
0 0
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DSP Instruction Reference Tables
Table D-4. DSP Instruction Set Summary (Continued)
CCR
Mnemonic Syntax P T
S L E U N Z V C
EXTRACTU EXTRACTU SSS,s,D
EXTRACTU #iiii,s,D
IFcc
IFcc(.U)
Ñ
Ñ
IFcc Ñ
IFcc(.U) Ñ
ILLEGAL
INC
INSERT
ILLEGAL
INC D
INSERT SSS,qqq,D
INSERT #iiii,qqq,D
Ñ
Ñ
Ñ
Ñ
Jcc
JCLR
JMP
JScc
JSCLR
Jcc aa
Jcc ea
JCLR #bbbb,S:<ea>,aaaa
JCLR #bbbb,S:<pp>,aaaa
JCLR #bbbb ,S:<aa>,aaaa
JCLR #bbbb,DDDDDD,aaaa
JCLR #bbbb, S:<qq>,aaaa
JMP aa
JMP ea
JScc aa
JScc ea
JSCLR #bbbb,S:<pp>,aaaa
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
1
2
1
1
2
5
1
4
4
4 + U
4
4
3
4
4
Ñ Ñ *
Ñ Ñ *
*
*
*
*
*
*
0 0
0 0
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
?
?
?
?
?
?
?
?
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ * *
Ñ Ñ *
Ñ Ñ *
*
*
*
*
*
*
*
*
*
*
0
0
*
0
0
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
*
*
*
Ñ
*
*
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ 3 + U + A Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ 4 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ
Ñ
4
4
Ñ
*
Ñ
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
JSET
JSCLR #bbbb , S:<ea>,aaaa
JSCLR #bbbb , S:<aa>,aaaa
JSCLR #bbbb, DDDDDD,aaaa
JSCLR #bbbb , S:<qq>,aaaa
JSET #bbbb , S:<pp>,aaaa
JSET #bbbb , S:<ea>,aaaa
JSET #bbbb , S:<aa>,aaaa
JSET #bbbb, DDDDDD,aaaa
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
4 + U
4
4
4
4
4 + U
4
4
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
JSR
JSSET
LRA
JSET #bbbb , S:<qq>,aaaa
JSR aa
JSR ea
JSSET #bbbb,S:<pp>,aaaa
JSSET #bbbb,S:<ea>,aaaa
JSSET #bbbb,S:<aa>,aaaa
JSSET #bbbb, DDDDDD,aaaa
JSSET #bbbb,S:<qq>,aaaa
LRA (PC + Rn) ® 0DDDDD
LRA (PC + aaaa) ® 0DDDDD
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
4
3
* * Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ 3 + U + A Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ 4 * * Ñ Ñ Ñ Ñ Ñ Ñ
Ñ
Ñ
4 + U
4
4
4
3
3
*
*
*
*
Ñ
Ñ
*
*
*
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
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DSP Instruction Reference Tables
Mnemonic
LSL
LSR
LSL D
LSL sss,D
LSL #ii,D
LSR D
LUA, LEA
MAC
LSR #ii,D
LSR sss,D
LUA ea ® 0DDDDD
LUA (Rn + aa) ® 01DDDD
MAC ± 2**s,QQ,d
MAC S1,S2,D
MAC (su,uu) MAC S1,S2,D
MACI
MACR
MACRI
MACI ± #iiiiii,QQ,D
MACR ± 2**s,QQ,d
MACRI ± #iiiiii,QQ,D
MAX MAX A,B
MAXM MAXM A,B
MERGE
MOVE
MERGE SSS,D
No Parallel Data Move (DALU)
MOVE #xx ® DDDDD
MOVE ddddd ® DDDDD
U move
MOVE S:<ea>,DDDDD
MOVEC
MOVEC
MOVE S:<aa>,DDDDD
MOVE S:<Rn + aa>,DDDD
MOVE S:<Rn + aaaa>,DDDDDD
MOVE d ® X Y:<ea>,YY
MOVE X:<ea>,XX & d ® Y
MOVE A ® X:<ea> X0 A
MOVE B ® X:<ea> X0 B
MOVE Y0 ® A A Y:<ea>
MOVE Y0 ® B B Y:<ea>
MOVE L:<ea>,LLL
MOVE L:<aa>,LLL
MOVE X:<ea>,XX & Y:<ea>,YY
MOVEC #xx ® 1DDDDD
MOVEC S:<ea>,1DDDDD
MOVEC S:<aa>,1DDDDD
MOVEC DDDDDD, 1ddddd
Table D-4. DSP Instruction Set Summary (Continued)
Syntax P T
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
P
Ñ
Ñ
P
1
1
Ñ
Ñ
P
P
Ñ
Ñ
N
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
N
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
1
1+U+A+I
1
2
3
1+U+A+I
1+U+A+I
1 + U
Ñ
Ñ
1 + U
1 + U
Ñ 1 + U
Ñ 1 + U + A
1
1
1
1
1
1
1
2
1
2
1
1
3
3
1
1
1
1
1
1+U+A+I
1
1
CCR
S L E U N Z V C
* * Ñ Ñ ?
?
0 ?
* * Ñ Ñ ?
?
0 ?
* * Ñ Ñ ?
?
0 ?
* * Ñ Ñ ?
?
0 ?
* * Ñ Ñ ?
?
0 ?
* * Ñ Ñ ?
?
0 ?
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
* * *
* * *
Ñ * *
Ñ * *
*
*
*
*
*
*
*
*
*
*
*
*
* Ñ
* Ñ
* Ñ
* Ñ
* * *
Ñ * *
*
*
*
*
*
*
* Ñ
* Ñ
* * Ñ Ñ Ñ Ñ Ñ ?
* * Ñ Ñ Ñ Ñ Ñ ?
Ñ Ñ Ñ Ñ ?
?
0 Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
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DSP Instruction Reference Tables
Mnemonic
MOVEM
MOVEP
MOVEM P:<ea>,DDDDDD
MOVEM P:<aa>,DDDDDD
MOVEP S:<pp>,s:<ea>
MOVEP S:<pp>,P:<ea>
MOVEP S:<pp>,DDDDDD
MOVEP X:<qq>,s:<ea>
MOVEP Y:<qq>,s:<ea>
MOVEP X:<qq>,DDDDDD
MOVEP Y:<qq>,DDDDDD
MOVEP S:<qq>,P:<ea>
MPY MPY ± 2**s,QQ,d
MPY(su,uu) MPY S1,S2,D (su,uu)
MPYI
MPYR
MPYRI
NEG
MPYI ± #iiiiii,QQ,D
MPYR ± 2**s,QQ,d
MPYRI ± #iiiiii,QQ,D
NEG D
NOP
NORMF
NOT
OR
ORI
REP
NOP
NORMF SSS,D
NOT D
OR SD
OR #iiiiii,D
OR #iii,D
ORI EE
REP #xxx
RESET
RND
ROL
ROR
RTI
RTS
SBC
STOP
SUB
SUBL
REP DDDDDD
REP S:<ea>
REP S:<aa>
RESET
RND D
ROL D
ROR D
RTI
RTS
SBC S,D
STOP
SUB S,D
SUB #iiiiii,D
SUB #iii,D
SUBL S,D
Table D-4. DSP Instruction Set Summary (Continued)
Syntax P T
Ñ
Ñ
P
Ñ
P
Ñ
P
P
P
P
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
P
P
Ñ 6 + U + A
Ñ 6
Ñ 2 + U + A
Ñ 6 + U + A
Ñ 1
Ñ 2 + U + A
Ñ 2 + U + A
Ñ 1
Ñ
Ñ
Ñ
P
Ñ 1
Ñ 6 + U + A
Ñ
Ñ
1
1
2
1
2
1
1
5
5 + U
5
7
3
5
2
1
3
3
10
2
1
CCR
S L E U N Z V C
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
* * *
Ñ * *
*
*
Ñ * *
* * *
Ñ * *
* * *
*
*
*
*
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
*
*
*
*
*
*
?
?
?
?
?
?
?
?
*
*
*
*
Ñ
Ñ
*
*
*
*
*
*
*
*
Ñ
Ñ
Ñ
Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ * * * * * ?
Ñ
* * Ñ Ñ ?
?
0 Ñ
* * Ñ Ñ ?
?
0 Ñ
* * Ñ Ñ ?
?
0 Ñ
* * Ñ Ñ ?
?
0 Ñ
?
?
?
?
?
?
?
?
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
* * Ñ Ñ Ñ Ñ Ñ Ñ
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
* * * * * * * Ñ
* * Ñ Ñ ?
?
0 ?
* * Ñ Ñ ?
?
0 ?
?
?
?
?
?
?
?
?
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
* * * * * * * *
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
* * * * * * * *
* * *
* * *
* * *
*
*
*
*
*
*
*
*
*
*
*
?
*
*
*
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DSP Instruction Reference Tables
Mnemonic
SUBR
Tcc
TFR
TRAP
TRAPcc
TST
VSL
WAIT
Table D-4. DSP Instruction Set Summary (Continued)
Syntax
SUBR S,D
Tcc JJJ ® D ttt TTT
Tcc JJJ ® D
Tcc ttt ® TTT
TFR S,D
TRAP
TRAPcc
TST S
VSL S,i,L:ea
WAIT
CCR
P T
S L E U N Z V C
P
Ñ
Ñ
P
P
Ñ
Ñ
Ñ
1
1
1
9
9
*
Ñ
Ñ
Ñ
*
Ñ
Ñ
*
*
Ñ
Ñ
Ñ
*
Ñ
Ñ
*
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
*
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
*
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
*
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
*
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
0
*
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ 1 + U + A Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
Ñ 10 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
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DSP Instruction Reference Tables
Table D-5. Program Word and Timing Symbols
Description and Symbols Column
P
T
Parallel Move
P Parallel Move
N
Ñ
No Parallel Move
Not Applicable
Instruction Clock Cycle Counts (Add one cycle for each symbol in column)
U Pre-Update
A
I
Long Absolute
Long Immediate
Symbol
Z
V
U
N
C
S
L
E
Table D-6. Condition Code Register (CCR) Symbols
Description
Scaling bit indicating data growth is detected
Limit bit indicating arithmetic overflow and/or data limiting
Extension bit indicating if the integer portion is in use
Unnormalized bit indicating if the result is unnormalized
Negative bit indicating if Bit 35 (or 31) of the result is set
Zero bit indicating if the result equals 0
Overflow bit indicating if arithmetic overflow has occurred in the result
Carry bit indicating if a carry or borrow occurred in the result
Notation
1
U
?
*
Ñ
0
Table D-7. Condition Code Register Notation
Description
Bit is set or cleared according to the standard definition by the result of the operation
Bit is not affected by the operation
Bit is always cleared by the operation
Bit is always set by the operation
Undefined
Bit is set or cleared according to the special computation definition by the result of the operation
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MCU Internal I/O Memory Map
D.3 MCU Internal I/O Memory Map
Table D-8 lists the MCU I/O registers in address numerical order. Unlisted addresses are
reserved.
Address
Table D-8. MCU Internal I/O Memory Map
Register Name Reset Value
$0020_0000
$0020_0004
$0020_0008
$0020_000C
$0020_0010
$0020_0014
$0020_1000
$0020_1004
$0020_1008
$0020_100C
$0020_1010
$0020_1014
$0020_1018
$0020_2FF2
$0020_2FF4
$0020_2FF6
$0020_2FF8
$0020_2FFA
$0020_2FFC
$0020_2FFE
MCVR
MCR
MSR
MTR1
MTR0
MRR1
MRR0
CS0
CS1
CS2
CS3
CS4
CS5
EIMCR
ISR
NIER
FIER
NIPR
FIPR
ICR
Interrupts
1
Interrupt Source Register
Normal Interrupt Enable Register
Fast Interrupt Enable Register
Normal Interrupt Pending Register
Fast Interrupt Pending Register
Interrupt Control Register
External Interface Module (EIM)
1
Chip Select 0 Register
Chip Select 1 Register
Chip Select 2 Register
Chip Select 3 Register
Chip Select 4 Register
Chip Select 5 Register
EIM Configuration Register
MCU-DSP Interface (MDI)
MCU-Side Command Vector Register
MCU-Side Control Register
MCU-Side Status Register
MCU Transmit Register 1
MCU Transmit Register 0
MCU Receive Register 1
MCU Receive Register 0
$0060
$0000
$3080
$0000
$0000
$0000
$0000
$F861
$uuuu
$uuuu
$uuuu
$uuuu
$uuuu
$0038
$0007
$0000
$0000
$0000
$0000
$0000
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MCU Internal I/O Memory Map
$0020_3800
$0020_3802
$0020_3804
$0020_3806
$0020_3808
$0020_380A
$0020_380C
$0020_380E
$0020_3810
$0020_3812
$0020_3814
$0020_3816
$0020_3818
$0020_381A
$0020_381C
$0020_381E
$0020_3820
$0020_3822
$0020_3824
CFC
CFMR
RSC
RSMR
PTPCR
PTDDR
PTPDR
FTPTR
PTCR
PTIER
PTSR
PTEVR
TIMR
CTIC
CTIMR
MTPTR
FTBAR
MTBAR
DTPTR
Table D-8. MCU Internal I/O Memory Map (Continued)
Address Register Name Reset Value
Protocol Timer (PT)
PT Control Register
PT Interrupt Enable Register
PT Status Register
PT Event Register
Time Interval Modulus Register
Channel Time Interval Counter
Channel Time Interval Modulus Register
Channel Frame Counter
Channel Frame Modulus Register
Reference Slot Counter
Reference Slot Modulus Register
PT Port Control Register
PT Data Direction Register
PT Port Data Register
Frame Table Pointer
Macro Table Pointer
Frame Tables Base Address Register
Macro Tables Base Address Register
Delay Table Pointer
UART
UART Receiver Register
2 $00uu $0020_4000 to
$0020_403C
URX
$0020_4040 to
$0020_407C
UTX
$0020_4080 UCR1
$0020_4082
$0020_4084
$0020_4086
UCR2
UBRGR
USR
UART Transmitter Register
3
UART Control Register 1
UART Control Register 2
UART Bit Rate Generator Register
UART Status Register
$0000
$0000
$0000
$0000
$0000
$0000
$uuuu
$uuuu
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$uuuu
$uuuu
$uuuu
$uuuu
$00uu
$0000
$0000
$0000
$A000
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Freescale Semiconductor, Inc.
MCU Internal I/O Memory Map
Table D-8. MCU Internal I/O Memory Map (Continued)
Address Register Name Reset Value
$0020_4088
$0020_408A
$0020_408C
$0020_408E
UTS
UPCR
UDDR
UPDR
UART Test Register
UART Port Control Register
UART Data Direction Register
UART Port Data Register
Queued Serial Peripheral Interface (QSPI)
$0020_5000 to $0020_507F
$0020_5400 to $0020_547F
$0020_5F00 QPCR
$0020_5F02
$0020_5F04
$0020_5F06
$0020_5F08
QDDR
QPDR
SPCR
QCR0
$0020_5F0A
$0020_5F0C
$0020_5F0E
$0020_5F10
$0020_5F12
$0020_5F14
$0020_5F16
$0020_5F18
$0020_5F1A
$0020_5FF8
$0020_5FFA
$0020_5FFC
$0020_5FFE
QCR1
QCR2
QCR3
SPSR
SCCR0
SCCR1
SCCR2
SCCR3
SCCR4
QSPI Control RAM
QSPI Data RAM
QSPI Port Control Register
QSPI Data Direction Register
QSPI Port Data Register
Serial Port Control Register
Queue Control Register 0
Queue Control Register 1
Queue Control Register 2
Queue Control Register 3
Serial Port Status Register
Serial Channel Control Register 0
Serial Channel Control Register 1
Serial Channel Control Register 2
Serial Channel Control Register 3
Serial Channel Control Register 4
MCU Trigger for Queue 0
MCU Trigger for Queue 1
MCU Trigger for Queue 2
MCU Trigger for Queue 3
General-Purpose Timer and Pulse Width Modulator (PWM)
$0020_6000
$0020_6002
TPWCR
TPWMR
Timers and PWM Control Register
Timers and PWM Mode Register
$0000
$0000
$0000
$000u
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$0000 uuuu uuuu
$0000
$0000
$0000
$0000
$0000
D-16 DSP56652 UserÕs Manual
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Freescale Semiconductor, Inc.
MCU Internal I/O Memory Map
Table D-8. MCU Internal I/O Memory Map (Continued)
Address Register Name Reset Value
$0020_6004
$0020_6006
$0020_6008
$0020_600A
$0020_600C
$0020_600E
$0020_6010
$0020_6012
$0020_6014
$0020_6016
$0020_6018
$0020_7000
$0020_7002
$0020_7004
$0020_8000
$0020_8002
$0020_9000
$0020_9002
$0020_9004
$0020_9006
$0020_A000
$0020_A002
$0020_A004
$0020_A006
TPWSR
TPWIR
TOCR1
TOCR3
TOCR4
TICR1
TICR2
PWOR
TCNT
PWMR
PWCNT
PITCSR
PITMR
PITCNT
WCR
WSR
EPPAR
EPDDR
EPDDR
EPFR
KPCR
KPSR
KDDR
KPDR
Timers and PWM Status Register
Timers and PWM Interrupts Enable Register
Timer 1 Output Compare Register
Timer 3 Output Compare Register
Timer 4 Output Compare Register
Timer 1 Input Capture Register
Timer 2 Input Capture Register
PWM Output Compare Register
Timer Counter
PWM Modulus Register
PWM Counter
Periodic Interrupt Timer (PIT)
PIT Control and Status Register
PIT Modulus Register
PIT Counter
Watchdog Timer
Watchdog Control Register
Watchdog Service Register
Edge Port (EP)
Edge Port Pin Assignment Register
Edge Port Data Direction Register
Edge Port Data Register
Edge Port Flag Register
Keypad Port (KP)
Keypad Control Register
Keypad Status Register
Keypad Data Direction Register
Keypad Data Register
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$0000
$FFFF
$uuuu
$0000
$0000
$0000
$0000
$00uu
$0000
$0000
$0000
$0000
$uuuu
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MCU Internal I/O Memory Map
Table D-8. MCU Internal I/O Memory Map (Continued)
Address Register Name Reset Value
$0020_B000
$0020_B002
$0020_B004
$0020_B006
$0020_B008
$0020_B00A
SCPCR
SCACR
SCPIER
SCPSR
SCPDR
SCPPCR
Smart Card Port (SCP)
SCP Control Register
Smart Card Activation Control Register
SCP Interrupt Enable Register
SCP Status Register
SCP Data Register
SCP Port Control Register
MCU Core
$0020_C000
$0020_C400
$0020_C800
$0020_C802
CKCTL
RSR
EMDDR
EMDR
Clock Control Register
Reset Source Register
Emulation Port
Emulation Port Control Register
Emulation Port Data Register
I/O Multiplexing
$0000
$0000
$00uu
$0020_CC00 GPCR General Port Control Register $0000
1.
These registers are 32 bits wide.
2.
These 16-bit registers are mapped on 32-bit boundaries to support the LDM instruction.
3.
These 16-bit registers are mapped on 32-bit boundaries to support the STM instruction.
$0000
$0000
$0000
$00Cu
$0000
$000u
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DSP Internal I/O Memory Map
D.4 DSP Internal I/O Memory Map
Table D-9 lists the DSP I/O registers in address numerical order.
Address
Table D-9. DSP Internal I/O Memory Map
Register Name
X:$FF8A
X:$FF8B
X:$FF8C
X:$FF8D
X:$FF8E
X:$FF8F
X:$FFA4
X:$FFA5
X:$FFA6
X:$FFA7
X:$FFA8
X:$FFA9
X:$FFAA
X:$FFAB
X:$FFAC
X:$FFAD
X:$FFAE
X:$FFAF
X:$FFB4
X:$FFB5
X:$FFB6
X:$FFB7
DCR
DSR
DTR1
DTR0
DRR1
DRR0
BBPRMR
BBPTMR
BBPCRA
BBPCRB
BBPCRC
BBPSR
BBPRX
BBPTSR
BBPTX
BBPPDR
BBPDDR
BBPPCR
SAPCNT
SAPMR
SAPCRC
SAPCRB
MCU-DSP Interface (MDI)
DSP-Side Control Register
DSP-Side Status Register
DSP Transmit Register 1
DSP Transmit Register 0
DSP Receive Register1
DSP Receive Register 0
Baseband Port (BBP)
BBP Receive Counter Modulus Register
BBP Transmit Counter Modulus Register
BBP Control Register A
BBP Control Register B
BBP Control Register C
BBP Status Register
BBP Receive Data Register
BBP Time Slot Register
BBP Transmit Data Register
BBP Port Data Register
BBP GPIO Direction Register
BBP Port Control Register
Serial Audio Port (SAP)
SAP Timer Counter
SAP Timer Modulus Register
SAP Control Register A
SAP Control Register B
Reset Value
$0
$0
$0
$0
$0
$40
$FFFF
$0
$0
$0
$0
$0
$0
$C000
$0
$0
$0
$0
$0
$0
$0
$0
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Freescale Semiconductor, Inc.
DSP Internal I/O Memory Map
Table D-9. DSP Internal I/O Memory Map (Continued)
Address Register Name Reset Value
X:$FFB8
X:$FFB9
X:$FFBA
X:$FFBB
X:$FFBC
X:$FFBD
X:$FFBE
X:$FFBF
SAPCRA
SAPSR
SAPRX
SAPTSR
SAPTX
SAPPDR
SAPDDR
SAPPCR
SAP Control Register C
SAP Status Register
SAP Receive Data Register
SAP Time Slot Register
SAP Transmit Data Register
SAP Port Data Register
SAP GPIO Data Direction Register
SAP Port Control Register
$0
$40
$FFFF
$0
$0
$0
$0
$0
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Freescale Semiconductor, Inc.
DSP Internal I/O Memory Map
Table D-9. DSP Internal I/O Memory Map (Continued)
Address Register Name Reset Value
X:$FFF5
X:$FFF6
X:$FFF7
X:$FFF8
X:$FFF9
X:$FFFB
X:$FFFC
X:$FFFD
X:$FFFE
X:$FFFF
PAR3
PAR2
PAR1
PAR0
IDR
OGDB
PCTL1
PCTL0
IPRP
IPRC
DSP Core
Patch 3 Register
Patch 2 Register
Patch 1 Register
Patch 0 Register
ID Register
OnCE GDB Register
PLL Control Register 1
PLL Control Register 0
Interrupt Priority RegisterÑPeripheral
Interrupt Priority RegisterÑCore
$uuuu
$uuuu
$uuuu
$uuuu
$0652
$0000
$0010
$0000
$0000
$0000
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Register Index
DCR
DRR0
DRR1
DSR
DTPTR
DTR0
DTR1
EIMCR
CS0
CS1
CS2
CS3
CS4
CS5
CTIC
CTIMR
EMDDR
EMDR
EPDDR
EPDR
BBPCRA
BBPCRB
BBPCRC
BBPDDR
BBPPCR
BBPPDR
BBPRMR
BBPRX
BBPSR
BBPTMR
BBPTSR
BBPTX
CFC
CFMR
CKCTL
D.5 Register Index
Table D-10 lists all DSP56652 registers in alphabetical order by acronym, and includes
the name, peripheral, address and description page number for each register.
Table D-10. Register Index
Register Name
BBP Control Register A
BBP Control Register B
BBP Control Register C
BBP GPIO Direction Register
BBP Port Control Register
BBP Port Data Register
BBP Receive Counter Modulus Register
BBP Receive Data Register
BBP Status Register
BBP Transmit Counter Modulus Register
BBP Time Slot Register
BBP Transmit Data Register
Channel Frame Counter
Channel Frame Modulus Register
Clock Control Register
Chip Select 0 Register
Chip Select 1 Register
Chip Select 2 Register
Chip Select 3 Register
Chip Select 4 Register
Chip Select 5 Register
Channel Time Interval Counter
Channel Time Interval Modulus Register
DSP-Side Control Register
DSP Receive Register 0
DSP Receive Register1
DSP-Side Status Register
Delay Table Pointer
DSP Transmit Register 0
DSP Transmit Register 1
EIM Configuration Register
Emulation Port Control Register
Emulation Port Data Register
Edge Port Data Direction Register
Edge Port Data Register
Peripheral Address
MDI
MDI
MDI
MDI
PT
MDI
MDI
EIM
EIM
EIM
EIM
EIM
EIM
EIM
PT
PT
Emulation
Emulation
EP
EP
BBP
BBP
BBP
BBP
BBP
BBP
BBP
X:$FFA6
X:$FFA7
X:$FFA8
X:$FFAE
X:$FFAF
X:$FFAD
X:$FFA4
BBP
BBP
BBP
BBP
X:$FFAA
X:$FFA9
X:$FFA5
X:$FFAB
BBP
PT
X:$FFAC
$0020_380E
PT $0020_3810
MCU Core $0020_C000
$0020_1000
$0020_1004
$0020_1008
$0020_100C
$0020_1010
$0020_1014
$0020_380A
$0020_380C
X:$FF8A
X:$FF8F
X:$FF8E
X:$FF8B
$0020_3824
X:$FF8D
X:$FF8C
$0020_1018
$0020_C800
$0020_C802
$0020_9002
$0020_9004
Page
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MTBAR
MTPTR
MTR0
MTR1
NIER
NIPR
OMR
PCTL0
KPCR
KPDR
KPSR
MCR
MCVR
MRR0
MRR1
MSR
PCTL1
PTPDR
PTDDR
PTPCR
PTCR
PTIER
PWCNT
PWMR
IDR
IPRC
IPRP
ISR
PITCNT
PITMR
PITCSR
KDDR
EPFR
EPPAR
FIER
FIPR
FTBAR
FTPTR
GPCR
ICR
Freescale Semiconductor, Inc.
Register Index
Table D-10. Register Index (Continued)
Register Name
Edge Port Flag Register
Edge Port Pin Assignment Register
Fast Interrupt Enable Register
Fast Interrupt Pending Register
Frame Tables Base Address Register
Frame Table Pointer
General Port Control Register
Interrupt Control Register
ID Register
Interrupt Priority RegisterÑCore
Interrupt Priority RegisterÑPeripheral
Interrupt Source Register
PIT Counter
PIT Modulus Register
PIT Control and Status Register
Keypad Data Direction Register
Keypad Control Register
Keypad Data Register
Keypad Status Register
MCU-Side Control Register
MCU-Side Command Vector Register
MCU Receive Register 0
MCU Receive Register 1
MCU-Side Status Register
Macro Tables Base Address Register
Macro Table Pointer
MCU Transmit Register 0
MCU Transmit Register 1
Normal Interrupt Enable Register
Normal Interrupt Pending Register
Operating Mode Register
PLL Control Register 0
PLL Control Register 1
PT Port Data Register
PT Data Direction Register
PT Port Control Register
PT Control Register
PT Interrupt Enable Register
PWM Counter Register
PWM Modulus Register
Peripheral
KP
KP
KP
MDI
MDI
MDI
MDI
MDI
PT
PT
MDI
MDI
Interrupts
Interrupts
DSP Core
DSP Core
EP
EP
Interrupts
Interrupts
PT
PT
I/O Mux
Interrupts
JTAG
Interrupts
Interrupts
Interrupts
Timers
Timers
Timers
KP
DSP Core
PT
PT
PT
PT
PT
Timers
Timers
Address
$0020_A000
$0020_A006
$0020_A002
$0020_2FF4
$0020_2FF2
$0020_2FFE
$0020_2FFC
$0020_2FF6
$0020_3822
$0020_381E
$0020_2FFA
$0020_2FF8
$0020_0004
$0020_000C
$0020_9006
$0020_9000
$0020_0008
$0020_0010
$0020_3820
$0020_381C
$0020_CC0
$0020_0014
X:$FFF9
X:$FFFF
X:$FFFE
$0020_0000
$0020_7004
$0020_7002
$0020_7000
$0020_A004
X:$FFFD
X:$FFFC
$0020_381A
$0020_3818
$0020_3816
$0020_3800
$0020_3802
$0020_6018
$0020_6016
Page
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Freescale Semiconductor, Inc.
Register Index
SCCR0
SCCR1
SCCR2
SCCR3
SCCR4
SCPCR
SCPDR
SCPIER
SAPMR
SAPPCR
SAPPDR
SAPRX
SAPSR
SAPTSR
SAPTX
SCACR
PWOR
QCR0
QCR1
QCR2
QCR3
QDDR
QPCR
QPDR
RSC
RSMR
RSR
SAPCNT
SAPCRA
SAPCRB
SAPCRC
SAPDDR
SCPPCR
SCPSR
SPCR
SPSR
TCNT
PTEVR
TICR1
TICR2
Table D-10. Register Index (Continued)
Register Name
PWM Output Compare Register
Queue Control Register 0
Queue Control Register 1
Queue Control Register 2
Queue Control Register 3
QSPI Data Direction Register
QSPI Port Control Register
QSPI Port Data Register
Reference Slot Counter
Reference Slot Modulus Register
Reset Source Register
SAP Timer Counter
SAP Control Register C
SAP Control Register B
SAP Control Register A
SAP GPIO Data Direction Register
SAP Timer Modulus Register
SAP Port Control Register
SAP Port Data Register
SAP Receive Data Register
SAP Status Register
SAP Time Slot Register
SAP Transmit Data Register
Smart Card Activation Control Register
Serial Channel Control Register 0
Serial Channel Control Register 1
Serial Channel Control Register 2
Serial Channel Control Register 3
Serial Channel Control Register 4
SCP Control Register
SCP Data Register
SCP Interrupt Enable Register
SCP Port Control Register
SCP Status Register
Serial Port Control Register
Serial Port Status Register
Timer Counter
PT Event Register
Timer 1 Input Capture Register
Timer 2 Input Capture Register
Peripheral Address
QSPI
QSPI
QSPI
QSPI
QSPI
SCP
SCP
SCP
SAP
SAP
SAP
SAP
SAP
SAP
SAP
SCP
SCP
SCP
QSPI
QSPI
Timers
PT
Timers
Timers
Timers
QSPI
QSPI
QSPI
QSPI
QSPI
QSPI
QSPI
$0020_6012
$0020_5F08
$0020_5F0A
$0020_5F0C
$0020_5F0E
$0020_5F02
$0020_5F00
$0020_5F04
PT
PT
$0020_3812
$0020_3814
MCU Core $0020_C400
SAP X:$FFB4
SAP
SAP
SAP
SAP
X:$FFB8
X:$FFB7
X:$FFB6
X:$FFBE
$0020_B00A
$0020_B006
$0020_5F06
$0020_5F10
$0020_6014
$0020_3806
$0020_600E
$0020_6010
X:$FFB5
X:$FFBF
X:$FFBD
X:$FFBA
X:$FFB9
X:$FFBB
X:$FFBC
$0020_B002
$0020_5F12
$0020_5F14
$0020_5F16
$0020_5F18
$0020_5F1A
$0020_B000
$0020_B008
$0020_B004
Page
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USR
UTS
UTX
WCR
WSR
PTSR
UBRGR
UCR1
UCR2
UDDR
UPCR
UPDR
URX
TIMR
TOCR1
TOCR3
TOCR4
TPWCR
TPWIR
TPWMR
TPWSR
Freescale Semiconductor, Inc.
Register Index
Table D-10. Register Index (Continued)
Register Name
Time Interval Modulus Register
Timer 1 Output Compare Register
Timer 3 Output Compare Register
Timer 4 Output Compare Register
Timers and PWM Control Register
Timers and PWM Interrupts Enable Register
Timers and PWM Mode Register
Timers and PWM Status Register
PT Status Register
UART But Rate Generator Register
UART Control Register 1
UART Control Register 2
UART Data Direction Register
UART Port Control Register
UART Port Data Register
UART Receive Registers
UART Status Register
UART Test Register
UART Transmit Registers
Watchdog Control Register
Watchdog Service Register
Peripheral
PT
UART
UART
UART
UART
UART
UART
UART
PT
Timers
Timers
Timers
Timers
Timers
Timers
Timers
UART
UART
UART
Timers
Timers
Address
$0020_3808
$0020_6008
$0020_600A
$0020_600C
$0020_6000
$0020_6006
$0020_6002
$0020_6004
$0020_3804
$0020_4084
$0020_4080
$0020_4082
$0020_408C
$0020_408A
$0020_408E
$0020_4000 to
$0020_403C
$0020_4086
$0020_4088
$0020_4040 to
$0020_407C
$0020_8000
$0020_8002
Page
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Acronym Changes
D.6 Acronym Changes
Some register and bit acronyms in the DSP56652 are different than those in previous
DSP56000 and M
·
CORE family devices. Table D-11 presents a summary of the changes.
Addresses containing X: are DSP X-memory addresses. All other addresses are the LSP of
MCU addresses; the MSP is $0020.
Function
Interrupts
Edge Port
QSPI
PIT
PWM
PT
Table D-11. DSP56652 Acronym Changes
Address
$6018
$3800
$3802
$3804
$3806
$3808
$380C
$3810
$3814
$3816
$3818
$381A
$381E
$3822
$5F00
$5F02
$5F04
$7000
$7002
$7004
$6014
$6016
$0000
$0000
$0004
$0008
$000C
$0010
X:$FFFE
$9000
Register
Original
PWCNR
TCTR
TIER
TSTR
TEVR
TIPR
CTIPR
CFPR
RSPR
PDPAR
PDDR
PDDAT
RTPTR
RTBAR
QPCR
QDDR
QPDR
ITCSR
ITDR
ITADR
TCR
PWCR
ISR
ISR
NIER
FIER
NIPR
FIPR
IPRP
EPPAR
New
Ð
Ð
TCNT
PWMR
PWCNT
PTCR
PTIER
PTSR
PTEVR
TIMR
Ð
Ð
Ð
Ð
Ð
PITCSR
PITMR
PITCNT
CTIMR
CFMR
RSMR
PTPCR
PTDDR
PTPDR
MTPTR
MTBAR
Bit #
30
28Ð25
8Ð0
13Ð0
8Ð0
7Ð0
7Ð0
7Ð0
7Ð0
7Ð6
7Ð0
7Ð0
7Ð0
7Ð0
Bit Name
Original New
SMPDINT SMPD
ÒL1Ó replaced with ÒPTÓ in all bit names
TIMPL[1:0]
EPPAR[7:0]
PC[7:0]
PD[7:0]
D[7:0]
PTPL[1:0]
EPPA[7:0]
QPC[7:0]
QDD[7:0]
QPD[7:0]
TIPV[8:0] TIMV[8:0]
CTIPV[13:0] CTIMV[13:0]
CFPV[8:0] CFMV[8:0]
RSPV[7:0]
PDGPC[7:0]
PDDR[7:0]
PDDAT[7:0]
RSMV[7:0]
PTPC[7:0]
PTDD[7:0]
PTPD[7:0]
D-26 DSP56652 UserÕs Manual
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Freescale Semiconductor, Inc.
Acronym Changes
Function
UART
Table D-11. DSP56652 Acronym Changes (Continued)
Address
$4080
Register
Original
UCR1
New
Ð
Bit #
$4082
$4086
$408A
$408C
$408E
UCR2
USR
UPCR
UDDR
UPDR
Ð
Ð
Ð
Ð
Ð
5
0
12
5
13
9
6
15
3Ð0
3Ð0
3Ð0
Bit Name
Original
TRDYEN
RRDYEN
TXMPTYEN
RTSDEN
UARTEN
CTS
WS
TXMPTY
PC[3:0]
PDC[3:0]
D[3:0]
New
TRDYIE
RRDYIE
TXEIE
RTSDIE
UEN
CTSD
CHSZ
TXE
UPC[3:0]
UDD[3:0]
UPD[3:0]
Motorola ProgrammerÕs Reference
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D-27
Freescale Semiconductor, Inc.
Acronym Changes
Function
SCP
Table D-11. DSP56652 Acronym Changes (Continued)
Address
$B000
Register
Original
SIMCR
New
SCPCR
Ð
Bit #
$B002
$B004
$B006
$B008
$B00A
SIACR
SIICR
SIMSR
SIMDR
SIPCR
SCACR
SCPIER
SCPSR
SCPDR
SCPPCR
0
7Ð0
9Ð5
4Ð0
2
1
4
3
6
5
8
7
0
9
2
1
4
3
1
0
3
2
0
4
2
1
4
3
9
8
5
Bit Name
Original
SIPE
SIFE
SIOV
SIIP
SIPD
SIMD[7:0]
PDIR[4:0]
PDAT[4:0]
SIFFI
SIRRI
SIPDI
SIFF
SIFN
SITY
SITC
SITK
VOLTSEL
OVRSINK
SISR
SIPT
SIIC
SINK
SITE
SIRE
SICK
SIRS
SIOE
SIVE
SIAP
SITCI
SIFNI
New
SCFFIE
SCRRIE
SCSCIE
SCFF
SCFN
SCTY
SCTC
TXNK
SCPE
SCFE
SCOE
SCSC
SCSP
SCPD[7:0]
SCPDD[4:0]
SCPPD[4:0]
CKSEL
NKOVR
SCSSR
SCPT
SCIC
NKPE
SCTE
SCRE
SCCLK
SCRS
SCDPE
SCPE
APDE
SCTCIE
SCFNIE
D-28 DSP56652 UserÕs Manual
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Freescale Semiconductor, Inc.
Acronym Changes
Function
SAP
BBP
X:$FFB4
X:$FFB5
X:$FFB6
X:$FFB7
X:$FFB8
X:$FFB9
X:$FFBA
X:$FFBB
X:$FFBC
X:$FFBD
X:$FFBE
X:$FFBF
X:$FFA4
X:$FFA5
X:$FFA6
X:$FFA7
X:$FFA8
X:$FFA9
X:$FFAA
X:$FFAB
X:$FFCC
X:$FFAD
X:$FFAE
X:$FFAF
Table D-11. DSP56652 Acronym Changes (Continued)
Address
Register
Original
TSRA
TXA
PDRA
PRRA
PCRA
RCRB
TCRB
CRAB
TCRA
TCLR
CRAA
CRBA
CRCA
SSISRA
RXA
CRBB
CRCB
SSISRB
RXB
TSRB
TXB
PDRB
PRRB
PCRB
New
BBPCRB
BBPCRC
BBPSR
BBPRX
BBPTSR
BBPTX
BBPPDR
BBPDDR
BBPPCR
SAPCNT
SAPMR
SAPCRA
SAPCRB
SAPCRC
SAPSR
SAPRX
SAPTSR
SAPTX
SAPPDR
SAPDDR
SAPPCR
BBPRMR
BBPTMR
BBPCRA
Bit #
5Ð0
5Ð0
5Ð0
5Ð0
5Ð0
5Ð0
Bit Name
Original New
PD[5:0]
PDC[5:0]
PC[5:0]
PD[5:0]
PDC[5:0]
PC[5:0]
SAPPD[5:0]
SAPDD[5:0]
SAPPC[5:0]
BBPPD[5:0]
BBPDD[5:0]
BBPPC[5:0]
Motorola ProgrammerÕs Reference
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D-29
Acronym Changes
Freescale Semiconductor, Inc.
D-30 DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Appendix E
ProgrammerÕs Data Sheets
These programmerÕs sheets are intended to simplify programming the various registers in the DSP56652. They can be photocopied and used to write in the binary bit values and the hexadecimal value for each register. The programmerÕs sheets are provided in the same order as the sections in this document. Sheets are also provided for certain registers that
are described in other documents. Table E-1 lists each programmerÕs sheet, the register
described in the sheet, and the page in this appendix where the sheet is located.
Functional Block
MCU Configuration
DSP Configuration
MDI
Acronym
MCR
MCVR
MSR
MRR0
MRR1
MTR0
MTR1
DCR
RSR
CKCTL
GPCR
PCTL0
PCTL1
OMR
PATCH
DSR
DRR0
DRR1
DTR0
DTR1
Table E-1. List of ProgrammerÕs Sheets
Register
Name
Reset Source Register
Clock Control Register
General Port Control Register
PLL Control Register 0
PLL Control Register 1
Operating Mode Register
Patch Registers
MCU-Side Control Register
MCU-Side Command Vector Register
MCU-Side Status Register
MCU Receive Register 0
MCU Receive Register 1
MCU Transmit Register 0
MCU Transmit Register 1
DSP-Side Control Register
DSP-Side Status Register
DSP Receive Register 0
DSP Receive Register1
DSP Transmit Register 0
DSP Transmit Register 1
Page
E-14
Motorola ProgrammerÕs Data Sheets
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E-1
Freescale Semiconductor, Inc.
E-2
Acronym
QCR1
QCR2
QCR3
SPSR
SCCR0
SCCR1
SCCR2
SCCR3
SCCR4
IPRP
IPRC
EPPAR
EPDDR
EPDDR
EPFR
SPCR
QCR0
CS0
CS1
CS2
CS3
CS4
CS5
EIMCR
EPDDR
EPDR
ISR
NIER
FIER
NIPR
FIPR
ICR
EIM
Interrupts
Edge Port
QSPI
Table E-1. List of ProgrammerÕs Sheets (Continued)
Functional Block
Emulation Port
Periodic Interrupt
Timer
QPCR
QDDR
QPDR
PITCSR
PITMR
PITCNT
Register
Name
Chip Select 0 Register
Chip Select 1 Register
Chip Select 2 Register
Chip Select 3 Register
Chip Select 4 Register
Chip Select 5 Register
EIM Configuration Register
Emulation Port Data Direction Register
Emulation Port Data Register
Interrupt Source Register
Normal Interrupt Enable Register
Fast Interrupt Enable Register
Normal Interrupt Pending Register
Fast Interrupt Pending Register
Interrupt Control Register
Interrupt Priority Register, Peripherals
Interrupt Priority Register, Core
Edge Port Pin Assignment Register
Edge Port Data Direction Register
Edge Port Data Register
Edge Port Flag Register
Serial Port Control Register
Queue Control Register 0
Queue Control Register 1
Queue Control Register 2
Queue Control Register 3
Serial Port Status Register
Serial Channel Control Register 0
Serial Channel Control Register 1
Serial Channel Control Register 2
Serial Channel Control Register 3
Serial Channel Control Register 4
QSPI Control RAM
QSPI Port Control Register
QSPI Data Direction Register
QSPI Port Data Register
PIT Control and Status Register
PIT Modulus Register
PIT Counter
Page
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Freescale Semiconductor, Inc.
Acronym
CFMR
RSC
RSMR
FTPTR
MTPTR
FTBAR
MTBAR
DTPTR
PTCR
PTIER
PTSR
PTEVR
TIMR
CTIC
CTIMR
CFC
PTPCR
PTDDR
PTPDR
WCR
WSR
TPWCR
TPWMR
TPWSR
TPWIR
TOCR1
TOCR3
TOCR4
TICR1
TICR2
PWOR
TCNT
PWMR
PWCNT
Table E-1. List of ProgrammerÕs Sheets (Continued)
Functional Block
Watchdog Timer
G-P Timer and
PWM
Protocol Timer
Register
Name
Watchdog Control Register
Watchdog Service Register
Timers and PWM Control Register
Timers and PWM Mode Register
Timers and PWM Status Register
Timers and PWM Interrupts Enable Register
Timer 1 Output Compare Register
Timer 3 Output Compare Register
Timer 4 Output Compare Register
Timer 1 Input Capture Register
Timer 2 Input Capture Register
PWM Output Compare Register
Timer Count Register
PWM Modulus Register
PWM Counter
PT Control Register
PT Interrupt Enable Register
PT Status Register
PT Event Register
Time Interval Modulus Register
Channel Time Interval Counter
Channel Time Interval Modulus Register
Channel Frame Counter
Channel Frame Modulus Register
Reference Slot Counter
Reference Slot Modulus Register
Frame Table Pointer
Macro Table Pointer
Frame Tables Base Address Register
Macro Tables Base Address Register
Delay Table Pointer
PT Port Control Register
PT Data Direction Register
PT Port Data Register
Page
Motorola ProgrammerÕs Data Sheets
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E-3
Freescale Semiconductor, Inc.
Acronym
SCPPCR
KPCR
KPSR
KPDDR
KPDR
SAPCNT
SAPMR
SAPCRC
SAPCRB
SAPCRA
SAPSR
SAPRX
SAPTSR
SAPTX
SAPPCR
SAPDDR
SAPPDR
URX
UTX
UCR1
UCR2
UBRGR
USR
UTS
UPCR
UDDR
UPDR
SCPCR
SCACR
SCPIER
SCPSR
SCPDR
Functional Block
UART
SCP
Keypad Port
Table E-1. List of ProgrammerÕs Sheets (Continued)
Serial Audio Port
Register
Name
UART Receiver Register
UART Transmitter Register
UART Control Register 1
UART Control Register 2
UART Bit Rate Generator Register
UART Status Register
UART Test Register
UART Port Control Register
UART Data Direction Register
UART Port Data Register
SCP Control Register
Smart Card Activation Control Register
SCP Interrupt Enable Register
SCP Status Register
SCP Data Register
SCP Port Control Register
Keypad Port Control Register
Keypad Status Register
Keypad Data Direction Register
Keypad Data Register
SAP Timer Counter
SAP Timer Modulus Register
SAP Control Register A
SAP Control Register B
SAP Control Register C
SAP Status Register
SAP Receive Data Register
SAP Time Slot Register
SAP Transmit Data Register
SAP Port Control Register
SAP GPIO Data Direction Register
SAP Port Data Register
Page
E-4 DSP56652 UserÕs Manual
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Freescale Semiconductor, Inc.
Table E-1. List of ProgrammerÕs Sheets (Continued)
Functional Block
Baseband Port
Acronym
BBPRMR
BBPTMR
BBPCRA
BBPCRB
BBPCRC
BBPSR
BBPRX
BBPTSR
BBPTX
BBPPCR
BBPDDR
BBPPDR
Register
Name
BBP Receive Counter Modulus Register
BBP Transmit Counter Modulus Register
BBP Control Register A
BBP Control Register B
BBP Control Register C
BBP Status Register
BBP Receive Data Register
BBP Time Slot Register
BBP Transmit Data Register
BBP Port Control Register
BBP GPIO Direction Register
BBP Port Data Register
Page
Motorola ProgrammerÕs Data Sheets
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E-5
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
MCU Core
15
*
0
RSR
Reset Source Register
Address = $0020_C400
Reset value depends on cause of reset
Read Only
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
9
*
0
CKCTL
Clock Control Register
Address = $0020_C000
Reset = $0000
Read/Write
CKOS
0
1
Description
MCU clock driven on CKO pin
DSP clock driven on CKO pin
CKOD
0
1
Description
CKO pin enabled
CKO pin disabled
CKOHD
0
1
Description
CKOH output buffer enabled
CKOH output buffer disabled
15
*
0
DCS
0
1
Description
CKIH provided to DSP core
CKIL provided to DSP core
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
8
*
0
EXR
0
1
WDR
0
1
7
*
0
Description
The last reset was not caused by an external reset (assertion of
RESET_IN pin)
The last reset was caused by
RESET_IN assertion
6
*
0
Description
The last reset was not caused by
Watchdog timer expiration
The last reset was caused by
Watchdog timer expiration
5
*
0
4
*
0
3
*
0
2
*
0
$0
1 0
WDR EXR
MCD[0:2]
000
001
010
Description
MCU clock division factor = 1
MCU clock division factor = 2
MCU clock division factor = 4
011
100
MCU clock division factor = 8
MCU clock division factor = 16
101-111 (Reserved)
MCS
0
1
Description
CKIL selected at multiplexer output
CKIH selected at multiplexer output
CKIHD
0
1
Description
CKIH input buffer enabled
CKIH input buffer disabled when
MCS bit cleared
9
*
0
8 7 6 5 4 3 2 1 0
DCS CKOHD CKOD CKOS MCD2 MCD1 MCD0 MCS CKIHD
* = Reserved,
E-6 DSP56652 UserÕs Manual
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Application:
MCU Core
GPCR
General Port Control Register
Address = $0020_CC00
Reset = $0000
Read/Write
GPC5
0
1
Description
Pin G13 functions as ROW6
Pin G13 functions as SC2A
DTR accessed by configuring as output in KDDR
GPC6
0
1
Description
Pin G11 functions as ROW7
Pin G11 functions as SCKA
GPC7
0
1
Description
Pin E11 functions as RTS
Pin E11 functions as IC2
STO bit value is reflected
Freescale Semiconductor, Inc.
Date:
Programmer:
GPC4
0
1
Description
Pin H14 functions as ROW5
Pin H14 functions as IC2
GPC3
0
1
Description
Pin M13 functions as COL7
Pin M13 functions as PWM
GPC2
0
1
Description
Pin N13 functions as COL6
Pin N13 functions as OC1
GPC1
0
1
Description
Pin J12 functions as INT7
Pin J12 functions as SRDA
DTR accessed by configuring as output in EPDDR
GPC0
0
1
Description
Pin K11 functions as INT6
Pin K11 functions as STDA
DSR accessed by configuring as output in EPDDR
15
STO
14
*
0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
7 6 5 4 3 2 1 0
GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0
$0
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-7
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
Predivider Factor
DSP Core
PCTL0
PLL Control Register 0
Address = X:$FFFD
Reset = $0000
Multiplication Factor
15
PD3
14
PD2
13
PD1
12
PD0
11
MF11
10
MF10
9
MF9
8
MF8
7
MF7
6
MF6
5
MF5
4
MF4
3
MF3
2
MF2
1 0
MF1 MF0
PEN
0
1
Description
PLL disabled
PLL enabled
Predivider Factor
PCTL1
PLL Control Register 1
Address = X:$FFFC
Reset = $0000
PSTP
0
1
Description
PLL disabled during STOP mode
PLL operates during STOP mode
Division Factor
E-8
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
PD6
10
PD5
9
PD4
8 7
* *
0 0
6 5
PEN PSTP
4 3
* *
0 0
2 1 0
DF2 DF1 DF0
* = Reserved,
DSP56652 UserÕs Manual
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Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
DSP Core
OMR
Operating Mode Register
Reset determined by hardware
Read/Write
Extended Stack
Underflow Flag
XYS
0
1
Description
Stack Extension mapped to X memory
Stack Extension mapped to Y memory
SD
0
1
Description
128 K clock cycle delay
16 clock cycle delay
SEN
0
1
Description
Stack Extension disabled
Stack Extension enabled
PCD
0
1
Description
PC relative instructions enabled
PC relative instructions disabled
ATE
0
1
Description
Address Trace disabled
Address Trace enabled
MB Description
Reflects state of DSP_IRQ at negation of RESET_IN
15
ATE
14
*
0
13
*
0
12 11 10 9 8
SEN WRP EOV EUN XYS
EOM Extended Operating Mode Register
* =
*
0
7 6
SD
5
PCD
4
*
0
3 2
* *
0 0
1
MB
COM Chip Operating Mode Register
0
*
1
Motorola ProgrammerÕs Data Sheets
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E-9
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
DSP Core
15
PAR15
14
PAR14
13
PAR13
12
PAR12
11
PAR11
10
PAR10
9
PAR9
PAR0
Patch Register 0
Address = X:$FFF8
Reset = $uuuu
8
PAR8
7
PAR7
6
PAR6
5
PAR5
4
PAR4
3
PAR3
2
PAR2
1 0
PAR1 PAR0
15
PAR15
14
PAR14
13
PAR13
12
PAR12
11
PAR11
10
PAR10
9
PAR9
PAR1
Patch Register 1
Address = X:$FFF7
Reset = $uuuu
8
PAR8
7
PAR7
6
PAR6
5
PAR5
4
PAR4
3
PAR3
2
PAR2
1 0
PAR1 PAR0
15
PAR15
14
PAR14
13
PAR13
12
PAR12
11
PAR11
10
PAR10
9
PAR9
PAR2
Patch Register 2
Address = X:$FFF6
Reset = $uuuu
8
PAR8
7
PAR7
6
PAR6
5
PAR5
4
PAR4
3
PAR3
2
PAR2
1 0
PAR1 PAR0
15
PAR15
14
PAR14
13
PAR13
12
PAR12
11
PAR11
10
PAR10
9
PAR9
PAR3
Patch Register 3
Address = X:$FFF5
Reset = $uuuu
8
PAR8
7
PAR7
6
PAR6
5
PAR5
4
PAR4
3
PAR3
2
PAR2
1 0
PAR1 PAR0
E-10 DSP56652 UserÕs Manual
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Application:
MRIE1
0
1
MRIE0
0
1
MTIE0
0
1
MCU MDI
MCR
MCU-Side Control Register
Address = $0020_2FF4
Reset = $0000
Read/Write
Description
Interrupt disabled
MCU Transmit Interrupt 0 enabled
Description
Interrupt disabled
MCU Receive Interrupt 1 enabled
Description
Interrupt disabled
MCU Receive Interrupt 0 enabled
Date:
Programmer:
MTIE1
0
1
MGIE1
0
1
MGIE0
0
1
DHR
0
1
MDIR
0
1
Description
Interrupt disabled
MCU Transmit Interrupt 1 enabled
Description
Interrupt disabled
MCU General Interrupt 1 enabled
Description
Interrupt disabled
MCU General Interrupt 0 enabled
Description
No reset issued
Resets DSP
Description
No reset issued
Resets MDI on MCU and DSP
MCU-to-DSP Flags
15
MRIE0
14
MRIE1
13
MTIE0
12
MTIE1
11
MGIE0
10
MGIE1 *
9
0
*
8
0
7
DHR
6
MDIR *
5
0
*
4
0
*
3
0
2
MDF2
1 0
MDF1 MDF0
MCVR
MCU-Side Command Vector Register
Address = $0020_2FF2
Reset = $0060
Read/Write
MC
0
1
Description
No interrupt issued
Sets MCP bit in DSR
Command Vector
Address
MNMI
0
1
Description
Command Interrupt is maskable
Command Interrupt is non-maskable
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8 7
MC MCV6
6 5
MCV5 MCV4
4 3
MCV3 MCV4
2 1 0
MCV1 MCV0 MNMI
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-11
Application:
MCU MDI
MSR
MCU-Side Status Register
Address = $0020_2FF6
Reset = $3080
Read/Write
MGIP0
0
1
Description
No interrupt pending
MCU General Interrupt 0 pending
MTE1
0
1
Description
MTR1 has data
MTR1 is empty
MTE0
0
1
Description
MTR0 has data
MTR0 is empty
MRF1
0
1
Description
MRR1 is empty
MRR1 has data
MRF0
0
1
Description
MRR0 is empty
MRR0 has data
Freescale Semiconductor, Inc.
Date:
Programmer:
MGIP1
0
1
Description
No interrupt pending
MCU General Interrupt 1 pending
MTIR
0
1
Description
No interrupt pending
Protocol Timer DSP Interrupt pending
DWS
0
1
Description
No interrupt pending
IRQC asserted to awaken DSP from
STOP mode
DRS
0
1
Description
DSP is not in RESET state
DSP currently in RESET state
MSMP
0
1
Description
No memory access pending
Shared memory access pending
DPM
0
1
Description
DSP is in Normal mode
DSP is in STOP mode
MEP
0
1
Description
No event pending
MCU-Side event pending
MCU-Side Flags
E-12
15
MRF0
14
MRF1
13
MTE0
12 11 10 9 8
MTE1 MGIP0 MGIP1 MTIR DWS
7
DRS
6 5
MSMP DPM
4
MEP
3
*
0
2
MF2
1
MF1
0
MF0
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
MCU MDI
15 data
14 data
13 data
12 data
11 data
10 data
MRR0
MCU Receive Register 0
Address = $0020_2FFE
Reset = $uuuu
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
MRR1
MCU Receive Register 1
Address = $0020_2FFC
Reset = $uuuu
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
MTR0
MCU Transmit Register 0
Address = $0020_2FFA
Reset = $uuuu
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
MTR1
MCU Transmit Register 1
Address = $0020_2FF8
Reset = $uuuu
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
Motorola ProgrammerÕs Data Sheets
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E-13
Application:
DSP MDI
DCR
DSP-Side Control Register
Address = X:$FF8A
Reset = $0000
Read/Write
Freescale Semiconductor, Inc.
Date:
Programmer:
DRIE0
0
1
Description
Interrupt disabled
DSP Receive Interrupt 0 enabled
DRIE1
0
1
Description
Interrupt disabled
DSP Receive Interrupt 1 enabled
DTIE1
0
1
Description
Interrupt disabled
DSP Transmit Interrupt 1 enabled MCIE
0
1
Description
Interrupt disabled
MCU Command Interrupt enabled
DTIE0
0
1
Description
Interrupt disabled
DSP Transmit Interrupt 0 enabled
DSP-to-MCU Flags
E-14
15
DTIE0
14 13
DTIE1 DRIE0
12
DRIE1
11
*
0
10
*
0
*
9
0
8
MCIE *
7
0
*
6
0
$0
*
5
0
* = Reserved,
*
4
0
*
3
0
2
DMF2
1
DMF1
0
DMF0
DSP56652 UserÕs Manual
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Motorola
Application:
DSP MDI
DSR
DSP-Side Status Register
Address = X:$FF8B
Reset = $C060
Read/Write
DGIR0
0
1
Description
No interrupt pending
MCU General Interrupt 0 pending
(MGIP0 is set)
DRF1
0
1
Description
DRR1 is empty
DRR1 has data
DRF0
0
1
Description
DRR0 is empty
DRR0 has data
DTE1
0
1
Description
DTR1 has data
DTR1 is empty
DTE0
0
1
Description
DTR0 has data
DTR0 is empty
Freescale Semiconductor, Inc.
Date:
Programmer:
DGIR1
0
1
Description
No interrupt pending
MCU General Interrupt 1 pending
(MGIP1 is set)
DTIC
1
Description
Signal to MCU to clear MTIR bit in
MSR (bit 9) (write-only)
MCP
0
1
Description
No interrupt pending
MCU-Side Command interrupt pending
DWSC
1
Description
Signal to MCU to clear DWS bit in
MSR (bit 8) (write-only)
MPM[0:1]
00
01
10
11
Description
MCU in STOP mode
MCU in WAIT mode
MCU in DOZE mode
MCU in Normal mode
DEP
0
1
Description
No event pending
DSP-Side event pending
DSP-Side Flags
15
DTE0
14
DTE1
13
DRF0
12 11 10 9 8
DRF1 DGIR0 DGIR1 DTIC MCP
7
DWSC
6 5
MPM1 MPM0
4
DEP *
0
3 2
DF2
1
DF1
0
DF0
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-15
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
15 data
DSP MDI
14 data
13 data
12 data
11 data
10 data
DRR0
DSP Receive Register 0
Address = X:$FF8F
Reset = $uuuu
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
DRR1
DSP Receive Register 1
Address = X:$FF8E
Reset = $uuuu
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
DTR0
DSP Transmit Register 0
Address = X:$FF8D
Reset = $uuuu
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
DTR1
DSP Transmit Register 1
Address = X:$FF8C
Reset = $uuuu
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
E-16 DSP56652 UserÕs Manual
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Motorola
Application:
EIM
CSCR0
Chip Select Register 0
Address = $0020_1000
Reset = $F861
Read/Write
OEA
0
1
Description
The OE signal is negated normally
The OE signal is asserted half a clock cycle later on read accesses
CSA
0
1
Description
The CS signal is asserted normally
The CS signal is asserted one cycle later on read and write accesses, and an extra cycle inserted between back-to-back cycles
EDC
0
1
Description
No delay occurs after a read cycle
One clock cycle is inserted after a read cycle
WWS
0
1
Description
Read and write WAIT states same
Write WAIT states = Read WAIT states + 1
WSC[0:3] Description
Binary value of number of external memory wait states
Freescale Semiconductor, Inc.
Date:
Programmer:
WEN
0
1
Description
The EB0Ð1 signals are negated normally
The EB0Ð1 signals are negated half a clock cycle earlier on write accesses
EBC
0
1
Description
Read and write accesses both assert EB0Ð1
Only write accesses can assert
EB0Ð1
DSZ1 DSZ0
0 0
0
1
1
1
0
1
Description
8-bit port on D[8:15] pins
8-bit port on D[0:7] pins
16-bit port on D[0:15] pins
(Reserved)
SP
0
1
Description
User mode accesses allowed
User mode accesses prohibited
WP
0
1
Description
Writes are allowed
Writes are prohibited
CSEN
0
1
Description
Chip Select function is disabled, and CS0 pin is an output
Chip Select function is enabled
31Ð16 15
WSC3
0
*
14
WSC2
13
WSC1
12 11 10 9 8
WSC0 WWS EDC CSA OEA
$0
7
WEN
* = Reserved,
6 5
EBC DSZ1
4
DSZ0
3
SP
2
WP
1
*
0
0
CSEN
Motorola ProgrammerÕs Data Sheets
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E-17
Application:
EIM
CSCR1
Chip Select Register 1
Address = $0020_1004
Reset = $uuuu
Read/Write
OEA
0
1
Description
The OE signal is negated normally
The OE signal is asserted half a clock cycle later on read accesses
CSA
0
1
Description
The CS signal is asserted normally
The CS signal is asserted one cycle later on read and write accesses, and an extra cycle inserted between back-to-back cycles
EDC
0
1
Description
No delay occurs after a read cycle
One clock cycle is inserted after a read cycle
WWS
0
1
Description
Read and write WAIT states same
Write WAIT states = Read WAIT states + 1
WSC[0:3] Description
Binary value of number of external memory wait states
Freescale Semiconductor, Inc.
Date:
Programmer:
WEN
0
1
Description
The EB0Ð1 signals are negated normally
The EB0Ð1 signals are negated half a clock cycle earlier on write accesses
EBC
0
1
Description
Read and write accesses both assert EB0Ð1
Only write accesses can assert
EB0Ð1
DSZ1 DSZ0
0 0
0
1
1
1
0
1
Description
8-bit port on D[8:15] pins
8-bit port on D[0:7] pins
16-bit port on D[0:15] pins
(Reserved)
SP
0
1
Description
User mode accesses allowed
User mode accesses prohibited
WP
0
1
Description
Writes are allowed
Writes are prohibited
CSEN
0
1
Description
Chip Select function is disabled, and CS0 pin is an output
Chip Select function is enabled
E-18
31Ð16
*
0
15
WSC3
14
WSC2
13
WSC1
12 11 10 9 8
WSC0 WWS EDC CSA OEA
$0
7
WEN
* = Reserved,
6 5
EBC DSZ1
4
DSZ0
3
SP
2
WP
1
*
0
0
CSEN
DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
WEN
0
1
EIM
CSCR2
Chip Select Register 2
Address = $0020_1008
Reset = $uuuu
Read/Write
Description
The EB0Ð1 signals are negated normally
The EB0Ð1 signals are negated half a clock cycle earlier on write accesses
OEA
0
1
CSA
0
1
Description
The OE signal is negated normally
The OE signal is asserted half a clock cycle later on read accesses
Description
The CS signal is asserted normally
The CS signal is asserted one cycle later on read and write accesses, and an extra cycle inserted between back-to-back cycles
EDC
0
1
WWS
0
1
Description
No delay occurs after a read cycle
One clock cycle is inserted after a read cycle
Description
Read and write WAIT states same
Write WAIT states = Read WAIT states + 1
WSC[0:3] Description
Binary value of number of external memory wait states
EBC
0
1
Description
Read and write accesses both assert EB0Ð1
Only write accesses can assert
EB0Ð1
DSZ1 DSZ0
0 0
0
1
1
1
0
1
Description
8-bit port on D[8:15] pins
8-bit port on D[0:7] pins
16-bit port on D[0:15] pins
(Reserved)
SP
0
1
Description
User mode accesses allowed
User mode accesses prohibited
WP
0
1
Description
Writes are allowed
Writes are prohibited
PA
0
1
Description
CS pin at logic high
CS pin at logic low
CSEN
0
1
Description
Chip Select function is disabled, and CS0 pin is an output
Chip Select function is enabled
31Ð16 15
WSC3
0
*
14
WSC2
13
WSC1
12 11 10 9 8
WSC0 WWS EDC CSA OEA
$0
7
WEN
* = Reserved,
6 5
EBC DSZ1
4
DSZ0
3
SP
2
WP
1
PA
0
CSEN
Motorola ProgrammerÕs Data Sheets
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E-19
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
WEN
0
1
EIM
CSCR3
Chip Select Register 3
Address = $0020_100C
Reset = $uuuu
Read/Write
Description
The EB0Ð1 signals are negated normally
The EB0Ð1 signals are negated half a clock cycle earlier on write accesses
OEA
0
1
CSA
0
1
Description
The OE signal is negated normally
The OE signal is asserted half a clock cycle later on read accesses
Description
The CS signal is asserted normally
The CS signal is asserted one cycle later on read and write accesses, and an extra cycle inserted between back-to-back cycles
EDC
0
1
WWS
0
1
Description
No delay occurs after a read cycle
One clock cycle is inserted after a read cycle
Description
Read and write WAIT states same
Write WAIT states = Read WAIT states + 1
WSC[0:3] Description
Binary value of number of external memory wait states
EBC
0
1
Description
Read and write accesses both assert EB0Ð1
Only write accesses can assert
EB0Ð1
DSZ1 DSZ0
0 0
0
1
1
1
0
1
Description
8-bit port on D[8:15] pins
8-bit port on D[0:7] pins
16-bit port on D[0:15] pins
(Reserved)
SP
0
1
Description
User mode accesses allowed
User mode accesses prohibited
WP
0
1
Description
Writes are allowed
Writes are prohibited
PA
0
1
Description
CS pin at logic high
CS pin at logic low
CSEN
0
1
Description
Chip Select function is disabled, and CS0 pin is an output
Chip Select function is enabled
31Ð16
*
0
15
WSC3
14
WSC2
13
WSC1
12 11 10 9 8
WSC0 WWS EDC CSA OEA
$0
7
WEN
* = Reserved,
6 5
EBC DSZ1
4
DSZ0
3
SP
2
WP
1
PA
0
CSEN
E-20 DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
WEN
0
1
EIM
CSCR4
Chip Select Register 4
Address = $0020_1010
Reset = $uuuu
Read/Write
Description
The EB0Ð1 signals are negated normally
The EB0Ð1 signals are negated half a clock cycle earlier on write accesses
OEA
0
1
CSA
0
1
Description
The OE signal is negated normally
The OE signal is asserted half a clock cycle later on read accesses
Description
The CS signal is asserted normally
The CS signal is asserted one cycle later on read and write accesses, and an extra cycle inserted between back-to-back cycles
EDC
0
1
WWS
0
1
Description
No delay occurs after a read cycle
One clock cycle is inserted after a read cycle
Description
Read and write WAIT states same
Write WAIT states = Read WAIT states + 1
WSC[0:3] Description
Binary value of number of external memory wait states
EBC
0
1
Description
Read and write accesses both assert EB0Ð1
Only write accesses can assert
EB0Ð1
DSZ1 DSZ0
0 0
0
1
1
1
0
1
Description
8-bit port on D[8:15] pins
8-bit port on D[0:7] pins
16-bit port on D[0:15] pins
(Reserved)
SP
0
1
Description
User mode accesses allowed
User mode accesses prohibited
WP
0
1
Description
Writes are allowed
Writes are prohibited
PA
0
1
Description
CS pin at logic high
CS pin at logic low
CSEN
0
1
Description
Chip Select function is disabled, and CS0 pin is an output
Chip Select function is enabled
31Ð16 15
WSC3
0
*
14
WSC2
13
WSC1
12 11 10 9 8
WSC0 WWS EDC CSA OEA
$0
7
WEN
* = Reserved,
6 5
EBC DSZ1
4
DSZ0
3
SP
2
WP
1
PA
0
CSEN
Motorola ProgrammerÕs Data Sheets
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E-21
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
WEN
0
1
EIM
CSCR5
Chip Select Register 5
Address = $0020_1014
Reset = $uuuu
Read/Write
Description
The EB0Ð1 signals are negated normally
The EB0Ð1 signals are negated half a clock cycle earlier on write accesses
OEA
0
1
CSA
0
1
Description
The OE signal is negated normally
The OE signal is asserted half a clock cycle later on read accesses
Description
The CS signal is asserted normally
The CS signal is asserted one cycle later on read and write accesses, and an extra cycle inserted between back-to-back cycles
EDC
0
1
WWS
0
1
Description
No delay occurs after a read cycle
One clock cycle is inserted after a read cycle
Description
Read and write WAIT states same
Write WAIT states = Read WAIT states + 1
WSC[0:3] Description
Binary value of number of external memory wait states
EBC
0
1
Description
Read and write accesses both assert EB0Ð1
Only write accesses can assert
EB0Ð1
DSZ1 DSZ0
0 0
0
1
1
1
0
1
Description
8-bit port on D[8:15] pins
8-bit port on D[0:7] pins
16-bit port on D[0:15] pins
(Reserved)
SP
0
1
Description
User mode accesses allowed
User mode accesses prohibited
WP
0
1
Description
Writes are allowed
Writes are prohibited
PA
0
1
Description
CS pin at logic high
CS pin at logic low
CSEN
0
1
Description
Chip Select function is disabled, and CS0 pin is an output
Chip Select function is enabled
31Ð16
*
0
15
WSC3
14
WSC2
13
WSC1
12 11 10 9 8
WSC0 WWS EDC CSA OEA
$0
7
WEN
* = Reserved,
6 5
EBC DSZ1
4
DSZ0
3
SP
2
WP
1
PA
0
CSEN
E-22 DSP56652 UserÕs Manual
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
EIM
EIMCR
EIM Configuration Register
Address = $0020_1018
Reset = $0038
Read/Write
SPRAM
0
1
Description
User mode access to internal RAM is allowed
User mode access to internal RAM is prohibited. Only Supervisor access is allowed
SPROM
0
1
Description
User mode access to internal ROM is allowed
User mode access to internal ROM is prohibited. Only Supervisor access is allowed
HDB
0
1
Description
Lower data bus D[0:15] driven externally
Upper data bus D[16:31] driven externally
SPIPER
0
1
Description
User mode access to peripherals is allowed
User mode access to internal peripherals is prohibited. Only
Supervisor access is allowed
SHEN1 SHEN0
0 0
0 1
1
1
0
1
Description
Show cycles disabled
Show cycles enabled, transfers during EDC/CSA idle cycles not visible externally
Show cycles enabled, all transfers visible (causes performance loss)
(Reserved)
EPEN
0
1
Description
Emulation port pins configured as
GPIO
Emulation port pins configured as
SIZ[0:1] and PSTAT[0:3]
31Ð16
0
*
$0
15
0
*
14
*
$0
13
0
*
12
0
*
11
*
0
10
*
0
9
*
0
8
*
0
$0
* = Reserved,
7
*
0
6 5 4 3
EPEN SPIPER SPRAM SPROM
2
HDB
1 0
SHEN1 SHEN0
Motorola ProgrammerÕs Data Sheets
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E-23
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
EIM
EMDDR
Emulation Port Data Direction Register
Address = $0020_C800
Reset = $0000
Read/Write
EMDDn
0
1
Description
Pin is GPIO input
Pin is GPIO output
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
9
0
*
8
0
*
7
0
*
6
0
5 4 3 2 1 0
EMDD5 EMDD4 EMDD3 EMDD2 EMDD1 EMDD0
EMDR
Emulation Port Data Register
Address = $0020_C802
Reset = $0000
Read/Write
Port Data Bits
E-24
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
*
0
8
*
0
7
*
0
$0
* = Reserved,
6
*
0
5
EMD5
4
EMD4
3
EMD3
2
EMD2
1
EMD1
0
EMD0
DSP56652 UserÕs Manual
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Motorola
Application:
MCU Interrupts
ISR
Upper Halfword
Interrupt Souce Register
Upper Halfword
Address = $0020_0000
Reset = $0000
Read/Write
PT1
0
1
Description
No interrupt request
Protocol Timer MCU1 interrupt request pending
PT2
0
1
UTX
0
1
Description
No interrupt request
Protocol Timer MCU2 interrupt request pending
Description
No interrupt request
UART Transmitter Ready interrupt request pending
SMPD
0
1
Description
No interrupt request
SIM Auto Power Down interrupt request pending
URX
0
1
Description
No interrupt request
UART Receiver Ready interrupt request pending
Freescale Semiconductor, Inc.
Date:
Programmer:
PT0
0
1
Description
No interrupt request
Protocol Timer MCU0 interrupt request pending
PTM
0
1
Description
No interrupt request
Protocol Timer interrupt request pending
QSPI
0
1
Description
No interrupt request
QSPI interrupt request pending
MDI
0
1
Description
No interrupt request
MDI interrupt request pending
SCP
0
1
Description
No interrupt request
SIM Card Tx, Rx, or Error interrupt request pending
TPW
0
1
Description
No interrupt request
General Purpose Timer/PWM interrupt request pending
PIT
0
1
Description
No interrupt request
Periodic Interrupt Timer interrupt request pending
31
URX
30
SMPD
29
UTX
28
PT2
27
PT1
26
PT0
25 24
PTM QSPI
23
MDI
22
SCP
21
*
0
20
*
0
19
*
0
18
*
0
17 16
TPW PIT
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-25
Application:
MCU Interrupts
ISR
Lower Halfword
Interrupt Souce Register
Lower Halfword
Address = $0020_0002
Reset = $0007
Read/Write
INT6
0
1
Description
No interrupt request
INT6 interrupt request pending
INT7
0
1
Description
No interrupt request
INT7 interrupt request pending
URTS
0
1
Description
No interrupt request
UART RTS Delta interrupt request pending
KPD
0
1
Description
No interrupt request
Keypad Interface interrupt request pending
Freescale Semiconductor, Inc.
Date:
Programmer:
INT5
0
1
Description
No interrupt request
INT5 interrupt request pending
INT4
0
1
Description
No interrupt request
INT4 interrupt request pending
INT3
0
1
Description
No interrupt request
INT3 interrupt request pending
INT2
0
1
Description
No interrupt request
INT2 interrupt request pending
INT1
0
1
Description
No interrupt request
INT1 interrupt request pending
INT0
0
1
Description
No interrupt request
INT0 interrupt request pending
Software Interrupt
E-26
15
*
0
14
KPD
13
URTS
12
INT7
11
INT6
10
INT5
9 8
INT4 INT3
7
INT2
6
INT1
5
INT0
4
*
0
3
*
0
2
S2
1
S1
0
S0
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Application:
MCU Interrupts
NIER
Upper Halfword
Normal Interrupt Enable Register
Upper Halfword
Address = $0020_0004
Reset = $0000
Read/Write
EPT1
0
1
Description
Interrupt source is masked
Protocol Timer MCU1 interrupt source enabled
EPT2
0
1
EUTX
0
1
Description
Interrupt source is masked
Protocol Timer MCU2 interrupt source enabled
Description
Interrupt source is masked
UART Transmitter Ready interrupt source enabled
ESMPD
0
1
Description
Interrupt source is masked
SIM Auto Power Down interrupt source enabled
EURX
0
1
Description
Interrupt source is masked
UART Receiver Ready interrupt source enabled
Freescale Semiconductor, Inc.
Date:
Programmer:
EPT0
0
1
Description
Interrupt source is masked
Protocol Timer MCU0 interrupt source enabled
EPTM
0
1
Description
Interrupt source is masked
Protocol Timer interrupt source enabled
EQSPI
0
1
Description
Interrupt source is masked
QSPI interrupt source enabled
EMDI
0
1
Description
Interrupt source is masked
MDI interrupt source enabled
ESCP
0
1
Description
Interrupt source is masked
SIM Card Tx, Rx, or Error interrupt source enabled
ETPW
0
1
Description
Interrupt source is masked
General Purpose Timer/PWM interrupt source enabled
EPIT
0
1
Description
Interrupt source is masked
Periodic Interrupt Timer interrupt source enabled
31
EURX
30
ESMPD
29
EUTX
28
EPT2
27
EPT1
26
EPT0
25 24
EPTM EQSPI
23
EMDI
22
ESCP
21
*
0
20
*
0
19
*
0
18
*
0
17 16
ETPW EPIT
NOTE:NIER can only be written as a 32-bit
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-27
Application:
MCU Interrupts
NIER
Lower Halfword
Normal Interrupt Enable Register
Lower Halfword
Reset = $0000
Read/Write
EINT5
0
1
Description
Interrupt source is masked
INT5 interrupt source enabled
EINT6
0
1
Description
Interrupt source is masked
INT6 interrupt source enabled
EINT7
0
1
Description
Interrupt source is masked
INT7 interrupt source enabled
EURTS
0
1
Description
Interrupt source is masked
UART RTS Delta interrupt source enabled
EKPD
0
1
Description
Interrupt source is masked
Keypad Interface interrupt source enabled
Freescale Semiconductor, Inc.
Date:
Programmer:
EINT4
0
1
Description
Interrupt source is masked
INT4 interrupt source enabled
EINT3
0
1
Description
Interrupt source is masked
INT3 interrupt source enabled
EINT2
0
1
Description
Interrupt source is masked
INT2 interrupt source enabled
EINT1
0
1
Description
Interrupt source is masked
INT1 interrupt source enabled
ES1
0
1
ES0
0
1
EINT0
0
1
Description
Interrupt source is masked
INT0 interrupt source enabled
ES2
0
1
Description
Interrupt source is masked
Software Interrupt 2 source enabled
Description
Interrupt source is masked
Software Interrupt 1 source enabled
Description
Interrupt source is masked
Software Interrupt 0 source enabled
E-28
15
*
0
14
EKPD
13
EURTS
12
EINT7
11
EINT6
10
EINT5
9 8
EINT4 EINT3
7
EINT2
6
EINT1
5
EINT0
4
*
0
3
*
0
2
ES2
1 0
ES1 ES0
NOTE:NIER can only be written as a 32-bit
* = Reserved,
DSP56652 UserÕs Manual
For More Information On This Product,
Go to: www.freescale.com
Motorola
Application:
MCU Interrupts
FIER
Upper Halfword
Fast Interrupt Enable Register
Upper Halfword
Address = $0020_0008
Reset = $0000
Read/Write
EFPT1
0
1
Description
Interrupt source is masked
Protocol Timer MCU1 interrupt source enabled
EFPT2
0
1
Description
Interrupt source is masked
Protocol Timer MCU2 interrupt source enabled
EFUTX
0
1
Description
Interrupt source is masked
UART Transmitter Ready interrupt source enabled
EFSMPD
0
1
Description
Interrupt source is masked
SIM Auto Power Down interrupt source enabled
EFURX
0
1
Description
Interrupt source is masked
UART Receiver Ready interrupt source enabled
Freescale Semiconductor, Inc.
Date:
Programmer:
EFPT0
0
1
Description
Interrupt source is masked
Protocol Timer MCU0 interrupt source enabled
EFPTM
0
1
Description
Interrupt source is masked
Protocol Timer interrupt source enabled
EFQSPI
0
1
Description
Interrupt source is masked
QSPI interrupt source enabled
EFMDI
0
1
Description
Interrupt source is masked
MDI interrupt source enabled
EFSCP
0
1
Description
Interrupt source is masked
SIM Card Tx, Rx, or Error interrupt source enabled
EFTPW
0
1
Description
Interrupt source is masked
General Purpose Timer/PWM interrupt source enabled
EFPIT
0
1
Description
Interrupt source is masked
Periodic Interrupt Timer interrupt source enabled
31 30 29
EFURX EFSMPD EFUTX
28
EFPT2
27
EFPT1
26
EFPT0
25 24
EFPTM EFQSPI
23
EFMDI
22
EFSCP
21
*
0
20
*
0
19
*
0
18
*
0
17 16
EFTPW EFPIT
NOTE:FIER can only be written as a 32-bit
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-29
Application:
MCU Interrupts
FIER
Lower Halfword
Fast Interrupt Enable Register
Lower Halfword
Reset = $0000
Read/Write
EFINT5
0
1
Description
Interrupt source is masked
INT5 interrupt source enabled
EFINT6
0
1
Description
Interrupt source is masked
INT6 interrupt source enabled
EFINT7
0
1
Description
Interrupt source is masked
INT7 interrupt source enabled
EFURTS
0
1
Description
Interrupt source is masked
UART RTS Delta interrupt source enabled
EFKPD
0
1
Description
Interrupt source is masked
Keypad Interface interrupt source enabled
Freescale Semiconductor, Inc.
Date:
Programmer:
EFINT4
0
1
Description
Interrupt source is masked
INT4 interrupt source enabled
EFINT3
0
1
Description
Interrupt source is masked
INT3 interrupt source enabled
EFINT2
0
1
Description
Interrupt source is masked
INT2 interrupt source enabled
EFINT1
0
1
Description
Interrupt source is masked
INT1 interrupt source enabled
EFINT0
0
1
Description
Interrupt source is masked
INT0 interrupt source enabled
EFS2
0
1
Description
Interrupt source is masked
Software Interrupt 2 source enabled
EFS1
0
1
Description
Interrupt source is masked
Software Interrupt 1 source enabled
EFS0
0
1
Description
Interrupt source is masked
Software Interrupt 0 source enabled
E-30
15
*
0
14 13 12 11 10 9 8 7 6 5
EFKPD EFURTS EFINT7 EFINT6 EFINT5 EFINT4 EFINT3 EFINT2 EFINT1 EFINT0
4
*
0
3
*
0
2
EFS2
1 0
EFS1 EFS0
NOTE:FIER can only be written as a 32-bit
* = Reserved,
DSP56652 UserÕs Manual
For More Information On This Product,
Go to: www.freescale.com
Motorola
Application:
MCU Interrupts
NIPR
Upper Halfword
Normal Interrupt Pending Register
Upper Halfword
Address = $0020_000C
Reset = $0000
Read/Write
NPT1
0
1
Description
No interrupt pending
Protocol Timer MCU1 interrupt request pending
NPT2
0
1
Description
No interrupt pending
Protocol Timer MCU2 interrupt request pending
NUTX
0
1
Description
No interrupt pending
UART Transmitter Ready interrupt request pending
NSMPD
0
1
Description
No interrupt pending
SIM Auto Power Down interrupt request pending
NURX
0
1
Description
No interrupt pending
UART Receiver Ready interrupt request pending
Freescale Semiconductor, Inc.
Date:
Programmer:
NPT0
0
1
Description
No interrupt pending
Protocol Timer MCU0 interrupt request pending
NPTM
0
1
Description
No interrupt pending
Protocol Timer interrupt request pending
NQSPI
0
1
Description
No interrupt pending
QSPI interrupt request pending
NMDI
0
1
Description
No interrupt pending
MDI interrupt request pending
NSCP
0
1
Description
No interrupt pending
SIM Card Tx, Rx, or Error interrupt request pending
NTPW
0
1
Description
No interrupt pending
General Purpose Timer/PWM interrupt request pending
NPIT
0
1
Description
No interrupt pending
Periodic Interrupt Timer interrupt request pending
31
NURX
30
NSMPD
29
NUTX
28
NPT2
27
NPT1
26
NPT0
25 24
NPTM NQSPI
23
NMDI
22
NSCP
21
*
0
20
*
0
19
*
0
18
*
0
17 16
NTPW NPIT
NOTE:NIPR can only be written as a 32-bit
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-31
Application:
MCU Interrupts
NIPR
Lower Halfword
Normal Interrupt Pending Register
Lower Halfword
Address = $0020_000E
Reset = $0000
Read/Write
NINT5
0
1
Description
No interrupt pending
INT5 interrupt request pending
NINT6
0
1
Description
No interrupt pending
INT6 interrupt request pending
NINT7
0
1
Description
No interrupt pending
INT7 interrupt request pending
NURTS
0
1
Description
No interrupt pending
UART RTS Delta interrupt request pending
NKPD
0
1
Description
No interrupt pending
Keypad Interface interrupt request pending
Freescale Semiconductor, Inc.
Date:
Programmer:
NINT4
0
1
Description
No interrupt pending
INT4 interrupt request pending
NINT3
0
1
Description
No interrupt pending
INT3 interrupt request pending
NINT2
0
1
Description
No interrupt pending
INT2 interrupt request pending
NINT1
0
1
Description
No interrupt pending
INT1 interrupt request pending
NS1
0
1
NS0
0
1
NINT0
0
1
Description
No interrupt pending
INT0 interrupt request pending
NS2
0
1
Description
No interrupt pending
Software Interrupt 2 request pending
Description
No interrupt pending
Software Interrupt 1 request pending
Description
No interrupt pending
Software Interrupt 0 request pending
E-32
15
*
0
14
NKPD
13
NURTS
12
NINT7
11
NINT6
10
NINT5
9 8
NINT4 NINT3
7
NINT2
6
NINT1
5
NINT0
4
*
0
3
*
0
2
NS2
1 0
NS1 NS0
NOTE:NIPR can only be written as a 32-bit
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Application:
MCU Interrupts
FIPR
Upper Halfword
Fast Interrupt Pending Register
Upper Halfword
Address = $0020_0010
Reset = $0000
Read/Write
FPT1
0
1
Description
No interrupt pending
Protocol Timer MCU1 interrupt request pending
FPT2
0
1
FUTX
0
1
Description
No interrupt pending
Protocol Timer MCU2 interrupt request pending
Description
No interrupt pending
UART Transmitter Ready interrupt request pending
FSMPD
0
1
Description
No interrupt pending
SIM Auto Power Down interrupt request pending
FURX
0
1
Description
No interrupt pending
UART Receiver Ready interrupt request pending
Freescale Semiconductor, Inc.
Date:
Programmer:
FPT0
0
1
Description
No interrupt pending
Protocol Timer MCU0 interrupt request pending
FPTM
0
1
Description
No interrupt pending
Protocol Timer interrupt request pending
FQSPI
0
1
Description
No interrupt pending
QSPI interrupt request pending
FMDI
0
1
Description
No interrupt pending
MDI interrupt request pending
FSCP
0
1
Description
No interrupt pending
SIM Card Tx, Rx, or Error interrupt request pending
FTPW
0
1
Description
No interrupt pending
General Purpose Timer/PWM interrupt request pending
FPIT
0
1
Description
No interrupt pending
Periodic Interrupt Timer interrupt request pending
31
FURX
30
FSMPD
29
FUTX
28
FPT2
27
FPT1
26
FPT0
25 24
FPTM FQSPI
23
FMDI
22
FSCP
21
*
0
20
*
0
19
*
0
18
*
0
17 16
FTPW FPIT
NOTE:FIPR can only be written as a 32-bit
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-33
Application:
MCU Interrupts
FIPR
Lower Halfword
Fast Interrupt Pending Register
Lower Halfword
Address = $0020_0012
Reset = $0000
Read/Write
FINT5
0
1
Description
No interrupt pending
INT5 interrupt request pending
FINT6
0
1
Description
No interrupt pending
INT6 interrupt request pending
FINT7
0
1
Description
No interrupt pending
INT7 interrupt request pending
FURTS
0
1
Description
No interrupt pending
UART RTS Delta interrupt request pending
FKPD
0
1
Description
No interrupt pending
Keypad Interface interrupt request pending
Freescale Semiconductor, Inc.
Date:
Programmer:
FINT4
0
1
Description
No interrupt pending
INT4 interrupt request pending
FINT3
0
1
Description
No interrupt pending
INT3 interrupt request pending
FINT2
0
1
Description
No interrupt pending
INT2 interrupt request pending
FINT1
0
1
Description
No interrupt pending
INT1 interrupt request pending
FS1
0
1
FS0
0
1
FINT0
0
1
Description
No interrupt pending
INT0 interrupt request pending
FS2
0
1
Description
No interrupt pending
Software Interrupt 2 request pending
Description
No interrupt pending
Software Interrupt 1 request pending
Description
No interrupt pending
Software Interrupt 0 request pending
E-34
15
*
0
14
FKPD
13
FURTS
12
FINT7
11
FINT6
10
FINT5
9 8
FINT4 FINT3
7
FINT2
6
FINT1
5
FINT0
4
*
0
3
*
0
2
FS2
1 0
FS1 FS0
NOTE:FIPR can only be written as a 32-bit
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
31
*
0
MCU Interrupts
ICR
Upper Halfword
Interrupt Control Register
Upper Halfword
Address = $0020_0014
Reset = $0000
Read/Write
Accessible Only in Supervisor Mode
30
*
0
$0
29
*
0
28
*
0
27
*
0
26
*
0
$0
25
*
0
24
*
0
23
*
0
22
*
0
$0
21
*
0
20
*
0
19
*
0
18
*
0
$0
17
*
0
16
*
0
ICR
Lower Halfword
Interrupt Control Register
Lower Halfword
Reset = $0000
Read/Write
Accessible Only in Supervisor Mode
EN
0
1
Description
Priority hardware disabled
Priority hardware disabled
Source Number
Vector Number
15
EN
14
*
0
13
*
0
12
*
0
11
SRC4
10
SRC3
9
SRC2
8 7
SRC1 SRC0
6 5
VEC6 VEC5
4 3
VEC4 VEC3
2 1 0
VEC2 VEC1 VEC0
NOTE:ICR can only be written as a 32-bit * = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-35
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
DSP Interrupts
IPRP
Interrupt Priority Register, Peripheral
Address = X:$FFFE
Reset = $0000
Read/Write
PL1
0
0
1
1
PL0
0
1
0
1
SAP IPL
Mode
Interrupts disabled
Interrupts enabled, IPL = 0
Interrupts enabled, IPL = 1
Interrupts enabled, IPL = 2
PL1
0
0
1
1
Protocol Timer IPL
PL0 Mode
0
1
Interrupts disabled
Interrupts enabled, IPL = 0
0
1
Interrupts enabled, IPL = 1
Interrupts enabled, IPL = 2
PL1
0
0
1
1
PL0
0
1
0
1
BBP IPL
Mode
Interrupts disabled
Interrupts enabled, IPL = 0
Interrupts enabled, IPL = 1
Interrupts enabled, IPL = 2
PL1
0
0
1
1
PL0
0
1
0
1
MDI IPL
Mode
Interrupts disabled
Interrupts enabled, IPL = 0
Interrupts enabled, IPL = 1
Interrupts enabled, IPL = 2
PL1
0
0
1
1
MCU Default Command IPL
PL0 Mode
0
1
Interrupts disabled
Interrupts enabled, IPL = 0
0
1
Interrupts enabled, IPL = 1
Interrupts enabled, IPL = 2
E-36
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9 8 7 6 5 4 3 2 1 0
MDIPL1 MDIPL0 PTPL1 PTPL0 SAPPL1 SAPPL0 BBPPL1 BBPPL0 MDCPL1 MDCPL0
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
DSP Interrupts
IPRC
Interrupt Priority Register, Core
Address = X:$FFFF
Reset = $0000
Read/Write
1
1
0
1
1
IBTM IBPL1 IBPL0
0 0 0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
0
1
1
1
0
1
1
IATM IAPL1 IAPL0
0 0 0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
0
1
IRQ B Mode
IRQ B disabled, no IPL
IRQ B enabled, IPL = 0
IRQ B enabled, IPL = 1
IRQ B enabled, IPL = 2
IRQ B disabled, no IPL
IRQ B enabled, IPL = 0
IRQ B enabled, IPL = 1
IRQ B enabled, IPL = 2
IRQ A Mode
IRQ A disabled, no IPL
IRQ A enabled, IPL = 0
IRQ A enabled, IPL = 1
IRQ A enabled, IPL = 2
IRQ A disabled, no IPL
IRQ A enabled, IPL = 0
IRQ A enabled, IPL = 1
IRQ A enabled, IPL = 2
Trigger Mode
Level-sensitive
Level-sensitive
Level-sensitive
Level-sensitive
Edge-sensitive
Edge-sensitive
Edge-sensitive
Edge-sensitive
Trigger Mode
Level-sensitive
Level-sensitive
Level-sensitive
Level-sensitive
Edge-sensitive
Edge-sensitive
Edge-sensitive
Edge-sensitive
1
1
0
1
1
IDTM IDPL1 IDPL0
0 0 0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
0
1
1
1
0
1
1
ICTM ICPL1 ICPL0
0 0 0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
0
1
IRQ C Mode
IRQ C disabled, no IPL
IRQ C enabled, IPL = 0
IRQ C enabled, IPL = 1
IRQ C enabled, IPL = 2
IRQ C disabled, no IPL
IRQ C enabled, IPL = 0
IRQ C enabled, IPL = 1
IRQ C enabled, IPL = 2
IRQ D Mode
IRQ D disabled, no IPL
IRQ D enabled, IPL = 0
IRQ D enabled, IPL = 1
IRQ D enabled, IPL = 2
IRQ D disabled, no IPL
IRQ D enabled, IPL = 0
IRQ D enabled, IPL = 1
IRQ D enabled, IPL = 2
Trigger Mode
Level-sensitive
Level-sensitive
Level-sensitive
Level-sensitive
Edge-sensitive
Edge-sensitive
Edge-sensitive
Edge-sensitive
Trigger Mode
Level-sensitive
Level-sensitive
Level-sensitive
Level-sensitive
Edge-sensitive
Edge-sensitive
Edge-sensitive
Edge-sensitive
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
IDTM
10
IDPL1
9
IDPL0
8 7 6 5 4 3 2 1 0
ICTM ICPL1 ICPL0 IBTM IBPL1 IBPL0 IATM IAPL1 IAPL0
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-37
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
Edge Port
EPPAR
Edge Port Pin Assignment Register
Address = $0020_9000
Reset = $0000
Read/Write
15
EPPA7
14 13
EPPA6
12 11
EPPA5
10 9
EPPA4
8
EPPAn
00
01
10
11
Description
Pin INTn is level-sensitive
Pin INTn defined as rising-edge detect
Pin INTn defined as falling-edge detect
Pin INTn defined as both rising- and falling-edge detect
7
EPPA3
6 5
EPPA2
4 3
EPPA1
2 1
EPPA0
0
E-38
15
*
0
15
*
0
15
*
0
EPDDR
Edge Port Data Direction Register
Address = $0020_9002
Reset = $0000
Read/Write
14
*
0
13
*
0
12
*
0
11
*
0
10
*
0
$0 $0
9
*
0
14
*
0
EPDR
Edge Port Data Register
Address = $0020_9004
Reset = $00uu
Read/Write
13
*
0
12
*
0
11
*
0
$0
10
*
0
$0
*
9
0
*
8
0
EPDDn
0
1
Pin is input
Description
Pin is output
8
*
0
7
EPDD7
6 5
EPDD6 EPDD5
4 3
EPDD4 EPDD3
2 1 0
EPDD2 EPDD1 EPDD0
Port Data Bits
7
EPD7
6
EPD6
5
EPD5
4
EPD4
3
EPD3
2
EPD2
1 0
EPD1 EPD0
14
*
0
EPFR
Edge Port Flag Register
Address = $0020_9006
Reset = $0000
Read/Write
13
*
0
12
*
0
11
*
0
$0
Edge Port Flags
10
*
0
9
*
0
8
*
0
7
EPF7
$0
* = Reserved,
6
EPF6
5
EPF5
4
EPF4
3
EPF3
2
EPF2
1 0
EPF1 EPF0
DSP56652 UserÕs Manual
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Motorola
Application:
QSPI
SPCR
Serial Port Control Register
Address = $0020_5F06
Reset = $0000
Read/Write
TRCIE
0
1
Description
Trigger collisions do not cause hardware interrupts from QSPI to
MCU
Trigger collisions cause hardware interrupts from QSPI to MCU
HLTIE
0
1
Description
Hardware interrupts from QSPI to
MCU caused by HALTA flag are disabled
Hardware interrupts from QSPI to
MCU caused by HALTA flag are enabled
QEn
0
1
Description
Queue n triggering is inactive
Queue n triggering is active on
MCU or Protocol Timer triggers
CSPOLn
0
1
Description
SPICSn is active low
SPICSn is active high
Freescale Semiconductor, Inc.
Date:
Programmer:
WIE
0
1
Description
Queue wraparounds do not cause hardware interrupts from QSPI to
MCU
Queue wraparounds (QPWF flag set) cause hardware interrupts from
QSPI to MCU
TACE
0
1
Description
Trigger accumulation for Queue 1 is disabled
Trigger accumulation for Queue 1 is enabled. Queues 0, 2, and 3 are unaffected
HALT
0
1
Description
QSPI HALT is disabled
QSPI HALT is requested
DOZE
0
1
Description
QSPI ignores DOZE mode
DOZE mode causes QSPI to halt at end of executing queue
QSPE
0
1
Description
QSPI disabled
QSPI enabled
15 14 13 12 11
CSPOL4 CSPOL3 CSPOL2 CSPOL1 CSPOL0
10
QE3
9
QE2
8
QE1
7 6 5 4 3 2 1 0
QE0 HLTIE TRCIE WIE TACE HALT DOZE QSPE
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E-39
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
LE0
0
1
QSPI
QCR0
Queue Control Register 0
Address = $0020_5F08
Reset = $0000
Read/Write
Description
Queue 0 reloading disabled
Queue 0 reloading enabled
HMD0
0
1
Description
Queue 0 halts only at end of queue
Queue 0 halts on any sub-queue boundary
Queue 0 Pointer
15
LE0
14
HMD0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
9
0
*
8
0
*
7
0
*
6
0
5
QP05
4 3
QP04 QP03
2 1 0
QP02 QP01 QP00
QCR1
Queue Control Register 1
Address = $0020_5F0A
Reset = $0000
Read/Write
LE1
0
1
Description
Queue 1 reloading disabled
Queue 1 reloading enabled
HMD1
0
1
Description
Queue 1 halts only at end of queue
Queue 1 halts on any sub-queue boundary
Trigger Counter
Queue 1 Pointer
E-40
15
LE1
14
HMD1
13
*
0
12
*
0
11
*
0
10
*
0
9 8 7 6
TRCNT3 TRCNT2 TRCNT1 TRCNT0
5
QP15
4 3
QP14 QP13
2 1 0
QP12 QP11 QP10
* = Reserved,
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
QSPI
QCR2
Queue Control Register 2
Address = $0020_5F0C
Reset = $0000
Read/Write
LE2
0
1
Description
Queue 2 reloading disabled
Queue 2 reloading enabled
HMD2
0
1
Description
Queue 2 halts only at end of queue
Queue 2 halts on any sub-queue boundary
Queue 2 Pointer
15
LE2
14
HMD2
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
0
9 8
*
0
*
0
7 6
*
0
5
QP25
4 3
QP24 QP23
2 1 0
QP22 QP21 QP20
QCR3
Queue Control Register 3
Address = $0020_5F0E
Reset = $0000
Read/Write
LE3
0
1
Description
Queue 3 reloading disabled
Queue 3 reloading enabled
HMD3
0
1
Description
Queue 3 halts only at end of queue
Queue 3 halts on any sub-queue boundary
Queue 3 Pointer
15
LE3
14
HMD3
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
*
0
7
$0
* = Reserved,
6
*
0
5
QP35
4 3
QP34 QP33
2 1 0
QP32 QP31 QP30
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E-41
Application:
QSPI
SPSR
Serial Port Status Register
Address = $0020_5F10
Reset = $0000
Read/Write
QA2
0
1
QA3
0
1
QX0
0
1
QX1
0
1
QX2
0
1
QX3
0
1
Description
Queue 2 is not active
Queue 2 is active
Description
Queue 3 is not active
Queue 3 is active
Description
Queue 0 is not executing
Queue 0 is executing
Description
Queue 1 is not executing
Queue 1 is executing
Description
Queue 2 is not executing
Queue 2 is executing
Description
Queue 3 is not executing
Queue 3 is executing
Freescale Semiconductor, Inc.
Date:
Programmer:
EOT3
0
1
EOT2
0
1
EOT1
0
1
EOT0
0
1
QA1
0
1
QA0
0
1
Description
Queue 1 is not active
Queue 1 is active
Description
Queue 0 is not active
Queue 0 is active
HALTA
0
1
Description
QSPI has not halted
QSPI has halted
TRC
0
1
QPWF
0
1
Description
Trigger collision has not occurred
Trigger collision has occurred
Description
Queue pointer has not wrapped around
Queue pointer has wrapped around
Description
Queue 3 transfer not complete
Queue 3 transfer complete
Description
Queue 2 transfer not complete
Queue 2 transfer complete
Description
Queue 1 transfer not complete
Queue 1 transfer complete
Description
Queue 0 transfer not complete
Queue 0 transfer complete
E-42
15
QX3
14
QX2
13
QX1
12
QX0
11
QA3
10
QA2
9 8
QA1 QA0
7
*
0
6
HALTA
5
TRC
4
QPWF
3
EOT3
2
EOT2
1 0
EOT1 EOT0
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
QSPI
SCCR0
Serial Channel Control Register 0
Address = $0020_5F12
Reset = $0000
Read/Write
DATR0[0:2]
000
001
010
011
100
101
110
111
Delay After Transfer
1 SCK cycle delay
2 SCK cycles delay
4 SCK cycles delay
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
LSBF0
0
1
Description
Data transferred MSB first
Data transferred LSB first
CKPOL0
0
1
Description
SCK inactive at logic 1
SCK inactive at logic 0
CPHA0
0
1
Description
Data changes on first SCK transition
Data latches on first SCK transition
CSCKDF0[0:2] Assertion to Activation Delay
000 1 SCK cycle delay
001
010
2 SCK cycles delay
4 SCK cycles delay
011
100
101
110
111
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
MCU_CLK
SCK =
2¥{3(SCKFD0[6]+1)¥(SCKDF0[0:5]+1)}
All values for SCKDF0[0:6] are valid.
Sample values are shown.
SCKDF0[0:6]
000_0000
000_0001
000_0111
100_0000
000_0100
100_1011
111_1110
111_1111
Description
SCK = MCU_CLK Ö 2
SCK = MCU_CLK Ö 4
SCK = MCU_CLK Ö 16
SCK = MCU_CLK Ö 8
SCK = MCU_CLK Ö 10
SCK = MCU_CLK Ö 96
SCK = MCU_CLK Ö 504
SCK = MCU_CLK Ö 1
15 14 13
CAPHA0 CKPOL0 LSBF0
12 11 10 9 8 7 6 5 4 3 2 1 0
DATR02 DATR01 DATR00 CSCKD02 CSCKD01 CSCKD00 SCKDF06 SCKDF05 SCKDF04 SCKDF03 SCKDF02 SCKDF01 SCKDF00
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E-43
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
QSPI
SCCR1
Serial Channel Control Register 1
Address = $0020_5F14
Reset = $0000
Read/Write
DATR1[0:2]
000
001
010
011
100
101
110
111
Delay After Transfer
1 SCK cycle delay
2 SCK cycles delay
4 SCK cycles delay
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
LSBF1
0
1
Description
Data transferred MSB first
Data transferred LSB first
CKPOL1
0
1
Description
SCK inactive at logic 1
SCK inactive at logic 0
CPHA1
0
1
Description
Data changes on first SCK transition
Data latches on first SCK transition
CSCKDF1[0:2] Assertion to Activation Delay
000 1 SCK cycle delay
001
010
2 SCK cycles delay
4 SCK cycles delay
011
100
101
110
111
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
MCU_CLK
SCK =
2¥{3(SCKFD1[6]+1)¥(SCKDF1[0:5]+1)}
All values for SCKDF1[0:6] are valid.
Sample values are shown.
SCKDF1[0:6]
000_0000
000_0001
000_0111
100_0000
000_0100
100_1011
111_1110
111_1111
Description
SCK = MCU_CLK Ö 2
SCK = MCU_CLK Ö 4
SCK = MCU_CLK Ö 16
SCK = MCU_CLK Ö 8
SCK = MCU_CLK Ö 10
SCK = MCU_CLK Ö 96
SCK = MCU_CLK Ö 504
SCK = MCU_CLK Ö 1
15 14
CAPHA1 CKPOL1
13
LSBF1
12 11 10 9 8 7 6 5 4 3 2 1 0
DATR12 DATR11 DATR10 CSCKD12 CSCKD11 CSCKD10 SCKDF16 SCKDF15 SCKDF14 SCKDF13 SCKDF12 SCKDF11 SCKDF10
E-44 DSP56652 UserÕs Manual
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
QSPI
SCCR2
Serial Channel Control Register 2
Address = $0020_5F16
Reset = $0000
Read/Write
DATR2[0:2]
000
001
010
011
100
101
110
111
Delay After Transfer
1 SCK cycle delay
2 SCK cycles delay
4 SCK cycles delay
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
LSBF2
0
1
Description
Data transferred MSB first
Data transferred LSB first
CKPOL2
0
1
Description
SCK inactive at logic 1
SCK inactive at logic 0
CPHA2
0
1
Description
Data changes on first SCK transition
Data latches on first SCK transition
CSCKDF2[0:2] Assertion to Activation Delay
000 1 SCK cycle delay
001
010
2 SCK cycles delay
4 SCK cycles delay
011
100
101
110
111
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
MCU_CLK
SCK =
2¥{3(SCKFD2[6]+1)¥(SCKDF2[0:5]+1)}
All values for SCKDF2[0:6] are valid.
Sample values are shown.
SCKDF2[0:6]
000_0000
000_0001
000_0111
100_0000
000_0100
100_1011
111_1110
111_1111
Description
SCK = MCU_CLK Ö 2
SCK = MCU_CLK Ö 4
SCK = MCU_CLK Ö 16
SCK = MCU_CLK Ö 8
SCK = MCU_CLK Ö 10
SCK = MCU_CLK Ö 96
SCK = MCU_CLK Ö 504
SCK = MCU_CLK Ö 1
15 14 13
CAPHA2 CKPOL2 LSBF2
12 11 10 9 8 7 6 5 4 3 2 1 0
DATR22 DATR21 DATR20 CSCKD22 CSCKD21 CSCKD20 SCKDF26 SCKDF25 SCKDF24 SCKDF23 SCKDF22 SCKDF21 SCKDF20
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E-45
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
QSPI
SCCR3
Serial Channel Control Register 3
Address = $0020_5F18
Reset = $0000
Read/Write
DATR3[0:2]
000
001
010
011
100
101
110
111
Delay After Transfer
1 SCK cycle delay
2 SCK cycles delay
4 SCK cycles delay
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
LSBF3
0
1
Description
Data transferred MSB first
Data transferred LSB first
CKPOL3
0
1
Description
SCK inactive at logic 1
SCK inactive at logic 0
CPHA3
0
1
Description
Data changes on first SCK transition
Data latches on first SCK transition
CSCKDF3[0:2] Assertion to Activation Delay
000 1 SCK cycle delay
001
010
2 SCK cycles delay
4 SCK cycles delay
011
100
101
110
111
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
MCU_CLK
SCK =
2¥{3(SCKFD3[6]+1)¥(SCKDF3[0:5]+1)}
All values for SCKDF3[0:6] are valid.
Sample values are shown.
SCKDF3[0:6]
000_0000
000_0001
000_0111
100_0000
000_0100
100_1011
111_1110
111_1111
Description
SCK = MCU_CLK Ö 2
SCK = MCU_CLK Ö 4
SCK = MCU_CLK Ö 16
SCK = MCU_CLK Ö 8
SCK = MCU_CLK Ö 10
SCK = MCU_CLK Ö 96
SCK = MCU_CLK Ö 504
SCK = MCU_CLK Ö 1
15 14
CAPHA3 CKPOL3
13
LSBF3
12 11 10 9 8 7 6 5 4 3 2 1 0
DATR32 DATR31 DATR30 CSCKD32 CSCKD31 CSCKD30 SCKDF36 SCKDF35 SCKDF34 SCKDF33 SCKDF32 SCKDF31 SCKDF30
E-46 DSP56652 UserÕs Manual
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
QSPI
SCCR4
Serial Channel Control Register 4
Address = $0020_5F1A
Reset = $0000
Read/Write
DATR4[0:2]
000
001
010
011
100
101
110
111
Delay After Transfer
1 SCK cycle delay
2 SCK cycles delay
4 SCK cycles delay
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
LSBF4
0
1
Description
Data transferred MSB first
Data transferred LSB first
CKPOL4
0
1
Description
SCK inactive at logic 1
SCK inactive at logic 0
CPHA4
0
1
Description
Data changes on first SCK transition
Data latches on first SCK transition
CSCKDF4[0:2] Assertion to Activation Delay
000 1 SCK cycle delay
001
010
2 SCK cycles delay
4 SCK cycles delay
011
100
101
110
111
8 SCK cycles delay
16 SCK cycles delay
32 SCK cycles delay
64 SCK cycles delay
128 SCK cycles delay
MCU_CLK
SCK =
2¥{3(SCKFD4[6]+1)¥(SCKDF4[0:5]+1)}
All values for SCKDF4[0:6] are valid.
Sample values are shown.
SCKDF4[0:6]
000_0000
000_0001
000_0111
100_0000
000_0100
100_1011
111_1110
111_1111
Description
SCK = MCU_CLK Ö 2
SCK = MCU_CLK Ö 4
SCK = MCU_CLK Ö 16
SCK = MCU_CLK Ö 8
SCK = MCU_CLK Ö 10
SCK = MCU_CLK Ö 96
SCK = MCU_CLK Ö 504
SCK = MCU_CLK Ö 1
15 14 13
CAPHA4 CKPOL4 LSBF4
12 11 10 9 8 7 6 5 4 3 2 1 0
DATR42 DATR41 DATR40 CSCKD42 CSCKD41 CSCKD40 SCKDF46 SCKDF45 SCKDF44 SCKDF43 SCKDF42 SCKDF41 SCKDF40
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E-47
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
QSPI
Control RAM
Control RAM
Address = $0020_5000 to 507F
Reset = $0000
Read/Write
CONT
0
1
Description
Deactivate chip select
Keep chip select active
PAUSE
0
1
Description
Not a queue boundary
Queue boundary
RE
0
1
Description
Receive disabled
Receive enabled
PCS[0:2]
000
001
010
011
100
101
110
111
Delay After Transfer
SPIC0 activated
SPIC1 activated
SPIC2 activated
SPIC3 activated
SPIC4 activated
NOPÐNo SPIC line activated
EOTIEÐEnd-of-transfer interrupt enabled
EOQÐEnd of queue
BYTE
0
1
16-bit data
Description
8-bit data
E-48
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
*
0
8
*
0
7
*
0
$0
* = Reserved,
6 5 4 3 2 1 0
BYTE RE PAUSE CONT PCS2 PCS1 PCS0
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Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
QSPI
QPCR
QSPI Port Control Register
Address = $0020_5F00
Reset = $0000
Read/Write
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
0
9
QPCn
0
1
Description
Pin is GPIO pin
Pin is QSPI pin
8
*
0
7 6 5 4 3 2 1 0
QPC7 QPC6 QPC5 QPC4 QPC3 QPC2 QPC1 QPC0
(SCK) (MOSI) (MISO) (CS4) (CS3) (CS2) (CS1) (CS0)
QDDR
QSPI Data Direction Register
Address = $0020_5F02
Reset = $0000
Read/Write
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
9
0
QDDn
0
1
Pin is input
Description
Pin is outut
*
8
0
7
QDD7
6 5 4 3 2 1 0
QDD6 QDD5 QDD4 QDD3 QDD2 QDD1 QDD0
QPDR
QSPI Port Data Register
Address = $0020_5F04
Reset = $00uu
Read/Write
Port Data Bits
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
7
QPD7
6 5 4 3 2 1 0
QPD6 QPD5 QPD4 QPD3 QPD2 QPD1 QPD0
$0
* = Reserved,
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E-49
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
OVW
0
1
PIT
PITCSR
PIT Control and Status Register
Address = $0020_7000
Reset = $0000
Read/Write
Description
Write to modulus latch does not overwrite PITCNT
Write to modulus latch immediately overwrites PITCNT
ITIE
0
1
ITIF
0
1
Description
PIT interrupt disabled
PIT interrupt enabled
Description
PITCNT has not reached zero
PITCNT has rolled over
RLD
0
1
Description
Counter rolls over to $FFFF
Counter rolls over to PITMR value
15
*
0
DBG
0
1
Description
PIT not affected by Debug mode
PIT halted by Debug mode
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
9
*
0
8
*
0
7
*
0
6
*
0
5 4 3 2 1
DBG OVW ITIE ITIF RLD
15 data
14 data
13 data
12 data
11 data
10 data
9 data
PITMR
PIT Modulus Register
Address = $0020_7002
Reset = $FFFF
Read/Write
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
0
*
0
E-50
15 data
14 data
13 data
12 data
11 data
10 data
9 data
PITCNT
PIT Counter
Address = $0020_7004
Reset = $uuuu
Read/Write
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
* = Reserved,
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
Watchdog Timer
WCR
Watchdog Control Register
Address = $0020_8000
Reset = $0000
Read/Write
WDE
0
1
Description
Watchdog Timer is disabled
Watchdog Timer is enabled
Watchdog Time-Out
WDBG
0
1
Description
Watchdog Timer not affected by
Debug mode
Watchdog Timer disabled in Debug mode
WDZE
0
1
Description
Watchdog Timer not affected by
DOZE mode
Watchdog Timer disabled in
DOZE mode
15
WT5
14
WT4
13
WT3
12
WT2
11
WT1
10
WT0 *
9
0
*
8
0
*
7
0
*
6
0
$0
*
5
0
*
4
0
*
3
0
2 1
WDE WDBG
0
WDZE
WSR
Watchdog Service Register
Address = $0020_8002
Reset = $0000
Read/Write
15
WS15
14
WS14
13
WS13
12
WS12
11
WS11
10
WS10
9
WS9
8
WS8
7
WS7
6
WS6
5
WS5
4
WS4
3
WS3
2
WS2
1 0
WS1 WS0
* = Reserved,
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E-51
Application:
PWM
TPWCR
Timers and PWM Control Register
Address = $0020_6000
Reset = $0000
Read/Write
PWE
0
1
Description
PWM counter is disabled
PWM counter is enabled
PWD
0
1
Description
PWM counter is enabled in DOZE mode
PWM counter is disabled in DOZE mode
TDBG
0
1
Description
Timer stops in Debug mode
Timer runs in Debug mode
PWDBG
0
1
Description
PWM counter stops during Debug mode
PWM counter runs during Debug mode
Freescale Semiconductor, Inc.
Date:
Programmer:
TD
0
1
Description
Timers are enabled in DOZE mode
Timers are disabled in DOZE mode
TE
0
1
Description
Timers are disabled
Timers are enabled
PSPW[0:2]
000
001
010
011
100
101
110
111
Description
PWM prescaler factor = 1
PWM prescaler factor = 2
PWM prescaler factor = 4
PWM prescaler factor = 8
PWM prescaler factor = 16
PWM prescaler factor = 32
PWM prescaler factor = 64
PWM prescaler factor = 128
PST[0:2]
000
001
010
011
100
101
110
111
Description
Timer prescaler factor = 1
Timer prescaler factor = 2
Timer prescaler factor = 4
Timer prescaler factor = 8
Timer prescaler factor = 16
Timer prescaler factor = 32
Timer prescaler factor = 64
Timer prescaler factor = 128
E-52
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
PWDBG
10
TDBG
9
PWD
8
PWE
7
TD
6 5 4 3 2 1 0
TE PSPW2 PSPW1 PSPW0 PST2 PST1 PST0
* = Reserved,
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
PWM
TPWMR
Timers and PWM Mode Register
Address = $0020_6002
Reset = $0000
Read/Write
FO3 Description
(Not pinned out)
FO4 Description
(Not pinned out)
PWP
0
1
Description
PWM pin active high
PWM pin active low
PWC
0
1
Description
PWM disconnected from PWM pin
PWM connected to PWM pin
FO1 Description
Writing a 1 to this bit forces the
Output Compare 1 function
IM2[0:1]
00
01
10
11
Description
Capture disabled
Capture on rising edge only
Capture on falling edge only
Capture on any edge
IM1[0:1]
00
01
10
11
Description
Capture disabled
Capture on rising edge only
Capture on falling edge only
Capture on any edge
OM1[0:1]
00
01
10
11
Description
Timer disconnected from pin
Toggle output pin
Clear output pin
Set output pin
15
*
0
14 13 12 11 10 9 8
PWC PWP FO4 FO3 FO1 IM21 IM20
7 6
IM11 IM10 *
0
5 4
*
0
*
0
3 2
*
0
1 0
OM11 OM10
* = Reserved,
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E-53
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
PWM
TPWSR
Timers and PWM Status Register
Address = $0020_6004
Reset = $0000
Read/Write
IF2
0
1
Description
Timer 2 Input Capture has not occurred
Timer 2 Input Capture has occurred
PWF
0
1
Description
PWM compare has not occurred
PWM compare has occurred
TOV
0
1
Description
TCNT overflow has not occurred
TCNT overflow has occurred
PWO
0
1
Description
PWCNT rollover has not occurred
PWCNT rollover has occurred
IF1
0
1
Description
Timer 1 Input Capture has not occurred
Timer 1 Input Capture has occurred
OF4
0
1
Description
Timer 4 Output Compare has not occurred
Timer 4 Output Compare has occurred
OF3
0
1
Description
Timer 3 Output Compare has not occurred
Timer 3 Output Compare has occurred
OF1
0
1
Description
Timer 1 Output Compare has not occurred
Timer 1 Output Compare has occurred
E-54
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
*
0
8
*
0
7
PWO
$0
* = Reserved,
6 5 4
TOV PWF IF2
3
IF1
2 1 0
OF4 OF3 OF1
DSP56652 UserÕs Manual
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
PWM
TPWIR
Timers and PWM Interrupt Register
Address = $0020_6006
Reset = $0000
Read/Write
IF2IE
0
1
Description
Interrupt disabled
Timer 2 Input Capture interrupt enabled
PWFIE
0
1
Description
Interrupt disabled
PWM Output Compare interrupt enabled
TOVIE
0
1
Description
Interrupt disabled
TCNT overflow interrupt enabled
PWOIE
0
1
Description
Interrupt disabled
PWCNT rollover interrupt enabled
IF1IE
0
1
Description
Interrupt disabled
Timer 1 Input Capture interrupt enabled
OF4IE
0
1
Description
Interrupt disabled
Timer 4 Output Compare interrupt enabled
OF3IE
0
1
Description
Interrupt disabled
Timer 3 Output Compare interrupt enabled
OF1IE
0
1
Description
Interrupt disabled
Timer 1 Output Compare interrupt enabled
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
7
PWOIE
6 5 4 3 2 1 0
TOVIE PWFIE IF2IE IF1IE OF4IE OF3IE OF1IE
$0
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-55
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
15 data
14 data
TOCR1
PWM
Timer 1 Output Compare Register
Address = $0020_6008
Reset = $0000
Read/Write
8 7 13 12 11 10 9 6 5 data data data data data data data data data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10
TOCR3
Timer 3 Output Compare Register
Address = $0020_600A
Reset = $0000
9
Read/Write
8 7 6 5 data data data data data data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10
TOCR4
Timer 4 Output Compare Register
Address = $0020_600C
Reset = $0000
9
Read/Write
8 7 6 5 data data data data data data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
TICR1
Timer 1 Input Capture Register
Address = $0020_600E
Reset = $0000
9
Read/Write
8 7 6 5 data data data data data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
TICR2
Timer 2 Input Capture Register
9
Address = $0020_6010
Reset = $0000
Read/Write
8 7 6 5 data data data data data
4 data
3 data
2 data
1 0 data data
E-56 DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
15 data
14 data
PWM
13 data
12 data
11 data
10 data
PWOR
PWM Output Compare Register
Address = $0020_6012
Reset = $0000
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
TCNT
Timer Count Register
Address = $0020_6014
Reset = $0000
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
PWMR
PWM Modulus Register
Address = $0020_6016
Reset = $0000
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
15 data
14 data
13 data
12 data
11 data
10 data
PWCNT
PWM Count Register
Address = $0020_6018
Reset = $0000
Read/Write
9 data
8 data
7 data
6 data
5 data
4 data
3 data
2 data
1 0 data data
Motorola ProgrammerÕs Data Sheets
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E-57
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
Protocol Timer
PTCR
PT Control Register
Address = $0020_3800
Reset = $0000
Read/Write
SPBP
0
1
Description
Reference Slot Prescaler Counter
(RSPC) drives RSC
RSPC bypassed, TICK drives RSC
HLTR
0
1
Description
Timer HALT not requested
Timer HALT requested
CFCE
0
1
Description
Channel Frame Counter disabled
Channel Frame Counter enabled
RSCE
0
1
Description
Reference Slot Counter disabled
Reference Slot Counter enabled
TDZD
0
1
Description
Protocol Timer ignores DOZE mode
Protocol Timer stops during DOZE mode
MTER
0
1
Description
Active macro execution continues to end of macro
Active macro execution halts immediately when HLTR bit is set or
ÔEnd_of_frame_haltÕ received
TIME
0
1
Description
Protocol Timer event disabled until
CFE occurs
Protocol Timer event executes immediately after TE assertion or
HALT state is exited
TE
0
1
Description
Protocol Timer disabled
Protocol Timer enabled
E-58
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
RSCE
8
CFCE
7
*
0
* = Reserved,
6
*
0
5 4 3 2 1 0
HLTR SPBP TDZD MTER TIME TE
DSP56652 UserÕs Manual
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Motorola
Application:
Protocol Timer
PTIER
PT Interrupt Enable Register
Address = $0020_3802
Reset = $0000
Read/Write
DSIE
0
1
Description
Interrupt disabled
DSP Interrupt enabled
DVIE
0
1
Description
Interrupt disabled
DSP Vector Interrupt enabled
THIE
0
1
Description
Interrupt disabled
Timer HALT Interrupt enabled
TERIE
0
1
Description
Interrupt disabled
Timer Error Interrupt enabled
Freescale Semiconductor, Inc.
Date:
Programmer:
MCIE2
0
1
Description
Interrupt disabled
MCU Interrupt 2 enabled
MCIE1
0
1
Description
Interrupt disabled
MCU Interrupt 1 enabled
MCIE0
0
1
Description
Interrupt disabled
MCU Interrupt 0 enabled
RSNIE
0
1
Description
Interrupt disabled
Reference Slot Interrupt enabled
CFNIE
0
1
Description
Interrupt disabled
Channel Frame Number Interrupt enabled
CFIE
0
1
Description
Interrupt disabled
Channel Frame Interrupt enabled
15
*
0
14
*
0
13
*
0
12
TERIE
11
THIE
10
DVIE
9
DSIE
8
*
0
*
0
7 6
MCIE2
5 4
MCIE1 MCIE0 *
0
3 2 1 0
RSNIE CFNIE CFIE
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-59
Application:
Protocol Timer
PTSR
PT Status Register
Address = $0020_3804
Reset = $0000
Read/Write
DVI
0
1
Description
Interrupt has not occurred
DSP Vector Interrupt event has occurred
THS
0
1
Description
Timer is not in HALT state
Timer is in HALT state
EOFE
0
1
Description
No error
End of Frame Error has occurred
MBUE
0
1
Description
No error
Macro Being Used Error has occurred
PCE
0
1
Description
No error
Pin Contention Error has occurred
Freescale Semiconductor, Inc.
Date:
Programmer:
DSPI
0
1
Description
Interrupt has not occurred
DSP Interrupt event has occurred
MCUI2
0
1
Description
Interrupt has not occurred
MCU Interrupt 2 event has occurred
MCUI1
0
1
Description
Interrupt has not occurred
MCU Interrupt 1 event has occurred
MCUI0
0
1
Description
Interrupt has not occurred
MCU Interrupt 0 event has occurred
RSNI
0
1
Description
Interrupt has not occurred
Reference Slot Number Interrupt has occurred
CFNI
0
1
Description
Interrupt has not occurred
Channel Frame Number Interrupt event has occurred
CFI
0
1
Description
Interrupt has not occurred
Channel Frame Interrupt event has occurred
E-60
15
*
0
14
PCE
13
MBUE
12
EOFE
11
THS
10
DVI
9
DSPI
8
*
0
7
*
0
6
MCUI2
5 4
MCUI1 MCUI0
3
*
0
2 1 0
RSNI CFNI CFI
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
Protocol Timer
PTEVR
PT Event Register
Address = $0020_3806
Reset = $0000
Read/Write
TXMA
0
1
Description
Macro not active
Transmit macro is active
RXMA
0
1
Description
Macro not active
Receive macro is active
ACT
0
1
Description
Frame Table 0 active
Frame Table 1 active
15
*
0
15
*
0
THIP
0
1
Description
Timer not halted
Timer HALT in progress
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
9
0
TIMR
Time Interval Modulus Register
Address = $0020_3808
Reset = $0000
Read/Write
*
8
0
*
7
0
*
6
0
$0
*
5
0
*
4
0
3
THIP
2 1 0
TXMA RXMA ACT
Timer Interval Modulus
Value
*
0
9 8 7
TIMV8 TIMV7
6 5
TIMV6 TIMV5
4 3
TIMV4 TIMV3
2 1 0
TIMV2 TIMV1 TIMV0
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
CTIC
Channel Time Interval Counter
Address = $0020_380A
Reset = $0000
Read/Write
10
*
0
Channel Time Interval
Value
14
*
0
13 12 11 10
CTIV13 CTIV12 CTIV11 CTIV10
9
CTIV9
8 7
CTIV8 CTIV7
6 5
CTIV6 CTIV5
4 3
CTIV4 CTIV3
2 1 0
CTIV2 CTIV1 CTIV0
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-61
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
Protocol Timer
CTIMR
Channel Time Interval Modulus Register
Address = $0020_380C
Reset = $0000
Read/Write
Channel Time Interval
Modulus Value
15
*
0
14
*
0
13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTIMV13 CTIMV12 CTIMV11 CTIMV10 CTIMV9 CTIMV8 CTIMV7 CTIMV6 CTIMV5 CTIMV4 CTIMV3 CTIMV2 CTIMV1 CTIMV0
CFC
Channel Frame Counter
Address = $0020_380E
Reset = $0000
Read/Write
Channel Frame Count
Value
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
*
0
8 7
CFCV8 CFCV7
6 5
CFCV6 CFCV5
4 3
CFCV4 CFCV3
2 1 0
CFCV2 CFCV1 CFCV0
E-62
CFMR
Channel Frame Modulus Register
Address = $0020_3810
Reset = $0000
Read/Write
Channel Frame Modulus
Value
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
*
0
8 7 6 5 4 3 2 1 0
CFMV8 CFMV7 CFMV6 CFMV5 CFMV4 CFMV3 CFMV2 CFMV1 CFMV0
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
Protocol Timer
RSC
Reference Slot Counter
Address = $0020_3812
Reset = $0000
Read/Write
Reference Slot Count
Value
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
9
0
*
8
0
7
RSCV7
6 5
RSCV6 RSCV5
4 3
RSCV4 RSCV3
2 1 0
RSCV2 RSCV1 RSCV0
Reference Slot Modulus
Value
RSMR
Reference Slot Modulus Register
Address = $0020_3814
Reset = $0000
Read/Write
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
7 6 5 4 3 2 1 0
RSMV7 RSMV6 RSMV5 RSMV4 RSMV3 RSMV2 RSMV1 RSMV0
$0
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-63
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
Protocol Timer
FTPTR
Frame Table Pointer
Address = $0020_381C
Reset = $00uu
Read/Write
Frame Table Pointer
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
9
0
*
8
0
*
7
0
6 5 4 3 2 1 0
FTPTR6 FTPTR5 FTPTR4 FTPTR3 FTPTR2 FTPTR1 FTPTR0
MTPTR
Macro Table Pointer
Address = $0020_381E
Reset = $uuuu
Read/Write
Transmit Macro Table
Pointer
Receive Macro Table
Pointer
E-64
15
*
0
14 13 12 11 10 9 8
TxPTR6 TxPTR5 TxPTR4 TxPTR3 TxPTR2 TxPTR1 TxPTR0
7
*
0
6 5 4 3 2 1 0
RxPTR6 RxPTR5 RxPTR4 RxPTR3 RxPTR2 RxPTR1 RxPTR0
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
Protocol Timer
FTBAR
Frame Table Base Address Register
Address = $0020_3820
Reset = $uuuu
Read/Write
Second Frame Table
First Frame Table
15
*
0
14 13 12 11 10 9 8
FTBA16 FTBA15 FTBA14 FTBA13 FTBA12 FTBA11 FTBA10 *
0
7 6 5
FTBA6 FTBA5
4 3
FTBA4 FTBA3
2 1 0
FTBA2 FTBA1 FTBA0
MTBAR
Macro Table Base Address Register
Address = $0020_3822
Reset = $uuuu
Read/Write
Transmit Base Address
Receive Base Address
15
*
0
14
TxBA6
13
TxBA5
12
TxBA4
11
TxBA3
10
TxBA2
9
TxBA1
8
TxBA0 *
7
0
6 5
RxBA6 RxBA5
4 3
RxBA4 RxBA3
2 1 0
RxBA2 RxBA1 RxBA0
DTPTR
Delay Table Pointer
Address = $0020_3824
Reset = $uuuu
Read/Write
Transmit Delay Base
Transmit Delay Table
Receive Delay Base
Receive Delay Table
15
*
0
14
TDBA3
13
TDBA2
12
TDBA1
11 10 9 8
TDBA0 TDPTR2 TDPTR1 TDPTR0 *
0
7 6 5
RDBA3 RDBA2
4 3 2 1 0
RDBA1 RDBA0 RDPTR2 RDPTR1 RDPTR0
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-65
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
E-66
Protocol Timer
PTPCR
PT Port Control Register
Address = $0020_3816
Reset = $0000
Read/Write
PTPCn
0
1
Description
Pin is GPIO output
Pin is Protocol Timer output
15
*
0
14
* *
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
9
*
0
8
*
0
7
PTPC7
6 5
PTPC6 PTPC5
4 3
PTPC4 PTPC3
2 1 0
PTPC2 PTPC1 PTPC0
PTDDR
PT Data Direction Register
Address = $0020_3818
Reset = $0000
Read/Write
PTDDn
0
1
Description
Pin is input (when GPIO)
Pin is output (when GPIO)
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
9
*
0
8
*
0
7
PTDD7
6 5
PTDD6 PTDD5
4 3
PTDD4 PTDD3
2 1 0
PTDD2 PTDD1 PTDD0
PTPDR
PT Port Data Register
Address = $0020_381A
Reset = $00uu
Read/Write
Port Data Bits
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
*
0
8
*
0
7 6 5 4 3 2 1 0
PTDAT7 PTDAT6 PTDAT5 PTDAT4 PTDAT3 PTDAT2 PTDAT1 PTDAT0
$0
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Application:
UART
URX
UART Receive Register
Address = $0020_4000 to 403C
Reset = $00uu
Read/Write
ERR
0
1
Description
No error detected in bits 13Ð10
Error detected
CHARRDY
0
1
Description
Character not ready
Character ready
Freescale Semiconductor, Inc.
Date:
Programmer:
OVRRUN
0
1
Description
No FIFO overrun
URX FIFO overrun detected
FRMERR
0
1
Description
No framing error detected
Character has a framing error
BRK
0
1
Description
Character is not a BREAK
Character is a BREAK
PRERR
0
1
Description
No parity error detected
Parity error detected
Rx Data
15
CHARRDY
14
ERR
13 12
OVRRUN FRMERR
11
BRK
10
PRERR *
0
9 8
*
0
7 data
6 data
5 data
4 data
3 data
2 1 0 data data data
UTX
UART Transmit Register
Address = $0020_4040 to 407C
Reset = $uuuu
Read/Write
Tx Data
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
7 data
$0
* = Reserved,
6 5 data data
4 3 data data
2 1 0 data data data
Motorola ProgrammerÕs Data Sheets
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E-67
Application:
UART
UCR1
UART Control Register 1
Address = $0020_4080
Reset = $0000
Read/Write
RXFL[0:1]
00
01
10
11
Description
Interrupt if RX FIFO contains 1 or more characters
Interrupt if RX FIFO contains 4 or more characters
Interrupt if RX FIFO contains 8 or more characters
Interrupt if RX FIFO contains 14 or more characters
TXEN
0
1
Description
Transmitter disabled
Transmitter enabled
TRDYIE
0
1
Description
Interrupt disabled
Transmitter Ready Interrupt enabled
TXFL[0:1]
00
01
10
11
Description
Interrupt if TX FIFO has slot for 1 or more characters
Interrupt if TX FIFO has slot for 4 or more characters
Interrupt if TX FIFO has slot for 8 or more characters
Interrupt if TX FIFO has slot for 14 or more characters
Freescale Semiconductor, Inc.
Date:
Programmer:
RRDYIE
0
1
Description
Interrupt disabled
Receiver Ready Interrupt enabled
RXEN
0
1
Description
Receiver disabled
Receiver enabled
IREN
0
1
Description
Infrared interface (IrDA) disabled
Infrared interface (IrDA) enabled
TXEIE
0
1
Description
Interrupt disabled
Transmitter Empty Interrupt enabled
RTSDIE
0
1
Description
RTS interrupt disabled
RTS interrupt enabled
SNDBRK
0
1
Description
(Bit is cleared)
Send continuous BREAK
DOZE
0
1
Description
UART enabled during DOZE mode
UART disabled during DOZE mode
UEN
0
1
Description
UART disabled
UART enabled
E-68
15
TXFL1
14
TXFL0
13
TRDYIE
12 11 10 9 8
TXEN RXFL1 RXFL0 RRDYIE RXEN
7
IREN
6 5 4
TXEIE RTSDIE SNDBRK
3
*
0
2
*
0
1
DOZE
0
UEN
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Application:
UART
UCR2
UART Control Register 2
Address = $0020_4082
Reset = $0000
Read/Write
CTSD
0
1
Description
CTS pin is inactive (high)
CTS pin is active (low)
CTSC
0
1
Description
CTS pin controlled by CTSD
CTS pin controlled by receiver
IRTS
0
1
Description
Transmit only when RTS pin is asserted
RTS pin is ignored
Freescale Semiconductor, Inc.
Date:
Programmer:
PREN
0
1
Description
Parity disabled
Parity enabled
PROE
0
1
Description
Even parity
Odd parity
STPB
0
1
1 Stop bit
2 Stop bits
Description
CHSZ
0
1
Description
7-bit characters
8-bit characters
CLKSRC
0
1
Description
Bit clock generated from 16x bit clock generator
Bit clock derived from IRQ7/DTR pin (input)
15
*
0
14
IRTS
13
CTSC
12
CTSD
11
*
0
10
*
0
*
0
9 8
PREN
7
PROE
6
STPB
5
CHSZ
4
CLKSRC *
0
3 2
*
0
$0
*
0
1
UBRGR
UART Bit Rate Generator Register
Address = $0020_4084
Reset = $0000
Read/Write
Clock Divider Bits
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
CD11
10
CD10
9
CD9
8
CD8
7
CD7
6 5
CD6 CD5
4 3
CD4 CD3
2 1 0
CD2 CD1 CD0
* = Reserved,
0
*
0
Motorola ProgrammerÕs Data Sheets
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E-69
Freescale Semiconductor, Inc.
Application:
UART
USR
UART Status Register
Address = $0020_4086
Reset = $A000
Read Only
TXE
0
1
Description
Unsent transmit data
All transmit data has been sent
Date:
Programmer:
RTSS
0
1
Description
RTS pin is high (inactive)
RTS pin is low (active)
TRDY
0
1
Description
Unsent characters above TXFL[0:1]
Unsent characters below TXFL[0:1]
RRDY
0
1
Description
Unread characters below RXFL[0:1]
Unread characters above RXFL[0:1]
RTSD
0
1
Description
RTS pin has not changed state
RTS pin has changed state
15
TXE
14
RTSS
13
TRDY
12
*
0
11
*
0
10
*
0
9
RRDY *
8
0
*
7
0
*
6
0
5
RTSD *
4
0
*
3
0
*
2
0
$0
*
1
0
*
0
0
UTS
UART Test Register
Address = $0020_4088
Reset = $0000
Read/Write
FRCPERR
0
1
Description
No intentional parity errors generated
Intentional parity error generated
NOTE: This register is included for test
LOOP
0
1
Description
Normal operation
Receiver connected to transmitter
15
*
0
14
*
0
13
FRCPERR
12
LOOP
11
*
0
10
LOOPIR
9
*
0
8
*
0
7
*
0
LOOPIR
0
1
Description
Normal IR operation
IR Receiver connected to IR transmitter
6
*
0
$0
5
*
0
4
*
0
3
*
0
2
*
0
$0
1
*
0
0
*
0
* = Reserved,
E-70 DSP56652 UserÕs Manual
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
UART
UPCR
UART Port Control Register
Address = $0020_408A
Reset = $0000
Read/Write
UPCn
0
1
Description
Pin is GPIO pin
Pin is UART pin
15
*
0
14
* *
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
0
9 8
*
0
*
0
7 6
*
0
$0
*
0
5 4
*
0
3
UPC3
2 1 0
UPC2 UPC1 UPC0
UDDR
UART Data Direction Register
Address = $0020_408C
Reset = $0000
Read/Write
UDDn
0
1
Description
Pin is input (when GPIO)
Pin is output (when GPIO)
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
0
9 8
*
0
*
0
7 6
*
0
$0
*
0
5 4
*
0
3
UDD3
2 1 0
UDD2 UDD1 UDD0
UPDR
UART Port Data Register
Address = $0020_408E
Reset = $000u
Read/Write
Port Data Bits
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
*
0
7
$0
* = Reserved,
6
*
0
$0
*
0
5 4
*
0
3
UPD3
2 1 0
UPD2 UPD1 UPD0
Motorola ProgrammerÕs Data Sheets
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E-71
Application:
SCP
SCPCR
SCP Control Register
Address = $0020_B000
Reset = $0000
Read/Write
SIBR
0
1
Description
Baud rate = SIM_CLK Ö 372
Baud rate = SIM_CLK Ö 64
DOZE
0
1
Description
SCP ignores DOZE mode
SCP halts in DOZE mode
NKOVR
0
1
Description
No NACK on overrun error
NACK generated on overrun error
CLKSEL
0
1
Description
SIM_CLK = CKIH Ö 5
SIM_CLK = CKIH Ö 4
Freescale Semiconductor, Inc.
Date:
Programmer:
SCSR
0
1
Description
(bit is cleared)
Reset SIM
SCPT
0
1
Description
Even parity
Odd parity
SCIC
0
1
Description
Parity determined by SIPT bit
Parity determined by smart card
NKPE
0
1
Description
No NACK on parity error
NACK generated on parity error
SCTE
0
1
Description
Transmitter disabled
Transmitter enabled
SCRE
0
1
Description
Receiver disabled
Receiver enabled
E-72
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9 8 7
CLKSEL NKOVR DOZE
6
SIBR
5 4
SCSR SCPT
3
SCIC
2 1 0
NKPE SCTE SCRE
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
SCP
SCACR
Smart Card Activation Control Register
Address = $0020_B002
Reset = $0000
Read/Write
SCRS
0
1
Description
SIMRESET pin asserted
SIMRESET pin deasserted
SCCLK
0
1
Description
SIMCLK pin disabled
SIMCLK pin enabled
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
0
9
SCDPE
0
1
Description
SIMDATA pin disabled
SIMDATA pin enabled
SCPE
0
1
APDE
0
1
Description
PWR_EN pin disabled
PWR_EN pin enabled
Description
Auto power-down disabled
Auto power-down enabled
8
*
0
*
0
7 6
*
0
*
0
5 4 3 2 1
SCCLK SCRS SCDPE SCPE
0
APDE
SCPIER
SCP Interrupt Enable Register
Address = $0020_B004
Reset = $0000
Read/Write
SCFNIE
0
1
Description
Interrupt disabled
Enable interrupt for data reception
SCTCIE
0
1
Description
Interrupt disabled
Enable interrupt for transmission complete
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
*
0
7
$0
* = Reserved,
6
*
0
SCFFIE
0
1
Description
Interrupt disabled
Enable interrupt for receive FIFO full
SCRRIE
0
1
Description
Interrupt disabled
Enable interrupt for receive error
SCSCIE
0
1
Description
Interrupt disabled
Enable interrupt for card sense change
*
0
5 4 3 2 1 0
SCTCIE SCFNIE SCFFIE SCRRIE SCSCIE
Motorola ProgrammerÕs Data Sheets
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E-73
Application:
SCP
Freescale Semiconductor, Inc.
SCPSR
SCP Status Register
Address = $0020_B006
Reset = $00C01
Read/Write
SCTC
1
Description
Transmit complete
SCTY
1
Description
TX data buffer is empty
SCFN
1
Description
Receive FIFO not empty
Date:
Programmer:
TXNK
1
Description
NACK detected
SCPE
1
Description
Parity error detected
SCFE
1
Description
Frame error detected
SCOE
1
Description
Overrun error detected
SCSC
1
Description
SENSE pin has changed state
SCSP
0
1
Description
SENSE pin low
SENSE pin high
SCFF
1
Description
Receive FIFO full
E-74
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
SCFF
8 7
SCFN SCTY
6
SCTC
5 4
TXNK SCPE
3
SCFE
2 1 0
SCOE SCSC SCSP
NOTE: Reset value of bit 0 depends on * = Reserved,
DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
SCP
15
*
0
SCPDR
SCP Data Register
Address = $0020_B008
Reset = $00uu
Read/Write
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
9
0
SCP Data Bits
*
8
0
7
SCPD7
6 5
SCPD6 SCPD5
4 3
SCPD4 SCPD3
2 1 0
SCPD2 SCPD1 SCPD0
SCPPCR
SCP Port Control Register
Address = $0020_B00A
Reset = $00uu
Read/Write
SMEN
0
1
Description
Pins function as GPIO
Pins function as SCP
SCPDDn
0
1
Description
Pin is an input when configured as
GPIO
Pin is an output when configured as GPIO
Port Data Bits
15
SMEN
14
*
0
13
*
0
12
*
0
11
*
0
10
*
0
9 8 7 6 5 4 3 2 1 0
SCPDD4 SCPDD3 SCPDD2 SCPDD1 SCPDD0 SCPPD4 SCPPD3 SCPPD2 SCPPD1 SCPPD0
* = Reserved,
Motorola ProgrammerÕs Data Sheets
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E-75
Application:
KP
KPCR
Keypad Port Control Register
Address = $0020_A000
Reset = $0000
Read/Write
Freescale Semiconductor, Inc.
Date:
Programmer:
KCOn
0
1
Description
Column strobe output n is totem-pole drive
Column strobe output n is open-drain
KREn
0
1
Description
Row n is not included in key press detect
Row n is included in key press detect
15
KCO7
14 13 12 11 10
KCO6 KCO5 KCO4 KCO3 KCO2
9
KCO1
8
KCO0
7
KRE7
6 5
KRE6 KRE5
4 3
KRE4 KRE3
2 1 0
KRE2 KRE1 KRE0
KPSR
Keypad Status Register
Address = $0020_A002
Reset = $0000
Read/Write
KPKD
0
1
Description
No keypad press detected
Keypad press detected
E-76
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
*
0
8
*
0
7
*
0
$0
* = Reserved,
6
*
0
$0
5
*
0
4
*
0
3
*
0
2
*
0
1
*
0
0
KPKD
DSP56652 UserÕs Manual
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
KP
KDDR
Keypad Data Direction Register
Address = $0020_A004
Reset = $0000
Read/Write
KCDDn
0
1
Description
Column strobe n pin is an input
Column strobe n pin is an output
KRDDn
0
1
Description
Row n pin is an input
Row n pin is an output
15
KCDD7
14 13 12 11 10 9
KCDD6 KCDD5 KCDD4 KCDD3 KCDD2 KCDD1
8 7
KCDD0 KRDD7
6 5
KRDD6 KRDD5
4 3
KRDD4 KRDD3
2 1 0
KRDD2 KRDD1 KRDD0
KPDR
Keypad Data Register
Address = $0020_A006
Reset = $0000
Read/Write
Column Data Bits
Row Data Bits
15
KCD7
14 13 12 11 10
KCD6 KCD5 KCD4 KCD3 KCD2
9
KCD1
8
KCD0
7
KRD7
6 5
KRD6 KRD5
4 3
KRD4 KRD3
2 1 0
KRD2 KRD1 KRD0
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E-77
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
15
SAP
SAPCNT
SAP Timer Counter Register
Address = X:$FFB4
Reset = $0000
Read/Write
14 13 12 11 10 9
SAP Timer Count
8 7 6 5 4 3 2 1 0
15
SAPMR
SAP Timer Modulus Register
Address = X:$FFB5
Reset = $0000
Read/Write
14 13 12 11 10 9
SAP Timer Modulus
8 7 6 5 4 3 2 1 0
PSR
0
1
SAPCRA
SAP Control Register A
Address = X:$FFB6
Reset = $0000
Read/Write
Description
No prescale
Prescale applied
Prescale Modulus
WL1 WL0
0 0
0
1
1
1
0
1
Description
8 bits per word
12 bits per word
16 bits per word
(Reserved)
Frame Rate Divider
15
PM7
14 13 12 11 10
PM6 PM5 PM4 PM3 PM2
9
PM1
8
PM0
7
PSR
6 5
WL1 WL0
4 3
DC4 DC3
2 1 0
DC2 DC1 DC0
E-78 DSP56652 UserÕs Manual
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Motorola
Application:
SAP
Freescale Semiconductor, Inc.
SAPCRB
SAP Control Register B
Address = X:$FFB7
Reset = $0000
Read/Write
RLIE
0
1
Description
Disable interrupt
Enable interrupt for last receive time slot
TEIE
0
1
Description
Disable interrupt
Enable interrupt for transmit error
REIE
0
1
Description
Disable interrupt
Enable interrupt for receive error
Date:
Programmer:
TLIE
0
1
Description
Disable interrupt
Enable interrupt for last transmit time slot
RIE
0
1
Description
Disable interrupt
Enable interrupt when a word is received
TIE
0
1
Description
Transmit Interrupt disabled
Transmit Interrupt enabled
RE
0
1
Description
Receiver disabled
Receiver enabled
TE
0
1
Description
Transmitter disabled
Transmitter enabled
TCE
0
1
Description
Timer disabled
Enable SAP timer
Serial Output Flags
15
REIE
14
TEIE
13
RLIE
12
TLIE
11
RIE
10
TIE
9
RE
8
TE *
0
7 6
*
0
$0
*
0
5
* = Reserved,
4
*
0
*
0
3 2 1 0
TCE OF1 OF0
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E-79
Application:
SAP
SAPCRC
SAP Control Register C
Address = X:$FFB8
Reset = $0000
Read/Write
SHFD
0
1
Description
Data shifted out MSB first
Data shifted out LSB first
BRM
0
1
Description
SAP clock source is DSP_CLK
SAP clock source is BRM_CLK
FSL1 FSL0
0 0
0
1
1
1
0
1
Description
WL bit clock for both TX and RX
1-bit clock for TX
WL bit clock for RX
1-bit clock for both TX and RX
WL bit clock for TX
1-bit clock for RX
FSR
0
1
FSP
0
1
Description
Frame sync occurs with first bit of current frame
Frame sync occurs with last bit of previous frame
Description
Positive frame sync
Negative frame sync
Freescale Semiconductor, Inc.
Date:
Programmer:
CKP
0
1
Description
Transmit Ð bit clock rising edge
Receive Ð bit clock falling edge
(default)
Transmit Ð bit clock falling edge
Receive Ð bit clock rising edge
SCKD
0
1
Description
External clock source
Internal clock source
SCD2
0
1
Description
SCD2 pin is input
SCD2 pin is output
SCD1
0
1
Description
SCD1 pin is input
SCD1 pin is output
SCD0
0
1
Description
SCD0 pin is input
SCD0 pin is output
MOD
0
1
SYN
0
1
Description
Normal mode
Network mode
Description
Asynchronous mode
Synchronous mode
E-80
15
FSP
14
FSR
13
FSL1
12
FSL0
11
*
0
10
*
0
9
*
0
8
BRM
7 6 5 4 3
SHFD CKP SCKD SCD2 SCD1
2 1 0
SCD0 MOD SYN
* = Reserved,
DSP56652 UserÕs Manual
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Motorola
Application:
SAP
SAPSR
SAP Status Register
Address = X:$FFB9
Reset = $0000
Read/Write
Freescale Semiconductor, Inc.
Date:
Programmer:
TUE
1
Description
TX underrun occurred
TFS
1
Description
TX frame sync occurred
ROE
1
Description
RX overrun occurred
RFS
1
Description
RX frame sync occurred
TDE
1
Description
TX data register empty
Serial Input Flags
RDF
1
Description
RX data register has data
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
7
RDF
$0
* = Reserved,
6
TDE
5 4
ROE TUE
3
RFS
2
TFS
1
IF1
0
IF0
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E-81
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
SAP
SAPRX
SAP Receive Data Register
Address = X:$FFBA
Reset = $0000
Read/Write
15 14 13 12 11
High Byte
10 9 8 7 6 5 4 3
Low Byte
2 1 0
SAPTSR
SAP Time Slot Register
Address = X:$FFBB
Reset = $0000
Read/Write
15 14 13 12 11 10 9 8 7 6 5
Dummy Register, Written During Inactive Time Slots
4 3 2 1 0
SAPTX
SAP Transmit Data Register
Address = X:$FFBC
Reset = $0000
Read/Write
15 14 13 12 11
High Byte
10 9 8 7 6 5 4 3
Low Byte
2 1 0
E-82 DSP56652 UserÕs Manual
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Motorola
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
15
*
0
SAP
SAPPDR
SAP Port Data Register
Address = X:$FFBD
Reset = $0000
Read/Write
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
9
0
Port Data Bits
*
8
0
*
7
0
*
6
0
5 4 3 2 1 0
SAPPD5 SAPPD4 SAPPD3 SAPPD2 SAPPD1 SAPPD0
SAPPCR
SAP Port Control Register
Address = X:$FFBF
Reset = $0000
Read/Write
PEN
0
1
Description
Port pins are tri-stated
Port pins enabled
SAPPCn
0
1
Description
Pin configured as GPIO
Pin configured as SAP
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
0
9 8
*
0
7
PEN
6
*
0
5 4 3 2 1 0
SAPPC5 SAPPC4 SAPPC3 SAPPC2 SAPPC1 SAPPC0
(STDA) (SRDA) (SCKA) (SC2A) (SC1A) (SC0A)
SAPDDR
SAP Data Direction Register
Address = X:$FFBE
Reset = $0000
Read/Write
SAPDDn
0
1
Pin is input
Description
Pin is output
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
*
0
9 8
*
0
*
0
7
$0
* = Reserved,
6
*
0
5 4 3 2 1 0
SAPDD5 SAPDD4 SAPDD3 SAPDD2 SAPDD1 SAPDD0
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E-83
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
BBP
BBPRMR
BBP Receive Counter Modulus Register
Address = X:$FFA4
Reset = $0000
Read/Write
15 14 13 12 11 10 9
Receive Counter Modulus
8 7 6 5 4 3 2 1 0
BBPTMR
BBP Transmit Counter Modulus Register
Address = X:$FFA5
Reset = $0000
Read/Write
15 14 13 12 11 10 9
Transmit Counter
8 7 6 5 4 3 2 1 0
PSR
0
1
BBPCRA
BBP Control Register A
Address = X:$FFA6
Reset = $0000
Read/Write
Description
No prescale
Prescale applied
Prescale Modulus
WL1 WL0
0 0
0
1
1
1
0
1
Description
8 bits per word
12 bits per word
16 bits per word
(Reserved)
Frame Rate Divider
15
PM7
14 13 12 11 10
PM6 PM5 PM4 PM3 PM2
9
PM1
8
PM0
7
PSR
6 5
WL1 WL0
4 3
DC4 DC3
2 1 0
DC2 DC1 DC0
E-84 DSP56652 UserÕs Manual
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Motorola
Application:
RIE
0
1
BBP
BBPCRB
BBP Control Register B
Address = X:$FFA7
Reset = $0000
Read/Write
Description
Disable interrupt
Enable interrupt when a word is received
TLIE
0
1
Description
Disable interrupt
Enable interrupt for last transmit time slot
RLIE
0
1
Description
Disable interrupt
Enable interrupt for last receive time slot
TEIE
0
1
Description
Disable interrupt
Enable interrupt for transmit error
REIE
0
1
Description
Disable interrupt
Enable interrupt for receive error
Freescale Semiconductor, Inc.
Date:
Programmer:
TIE
0
1
Description
Transmit Interrupt disabled
Transmit Interrupt enabled
RE
0
1
Description
Receive disabled
Receive enabled
TE
0
1
Description
Transmit disabled
Transmit enabled
RCIE
0
1
Description
Disable interrupt
Enable receive interrupt
TCIE
0
1
Description
Disable interrupt
Enable transmit interrupt
RCE
0
1
Description
Counter disabled
Enable receive counter
TCE
0
1
Description
Counter disabled
Enable transmit counter
Serial Output Flags
15
REIE
14
TEIE
13
RLIE
12
TLIE
11
RIE
10
TIE
9
RE
8
TE
7
RCIE
6
TCIE
5
RCE
4
TCE *
3
0
*
2
0
1 0
OF1 OF0
* = Reserved,
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E-85
Freescale Semiconductor, Inc.
E-86 DSP56652 UserÕs Manual
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Motorola
Application:
BBP
BBPCRC
BBP Control Register C
Address = X:$FFA8
Reset = $0000
Read/Write
SHFD
0
1
Description
Data shifted out MSB first
Data shifted out LSB first
FSL1 FSL0
0 0
0
1
1
1
0
1
Description
WL bit clock for both TX and RX
1-bit clock for TX
WL bit clock for RX
1-bit clock for both TX and RX
WL bit clock for TX
1-bit clock for RX
FSR
0
1
Description
Frame sync occurs with first bit of current frame
Frame sync occurs with last bit of previous frame
FSP
0
1
Description
Positive frame sync
Negative frame sync
Freescale Semiconductor, Inc.
Date:
Programmer:
CKP
0
1
Description
Transmit Ð bit clock rising edge
Receive Ð bit clock falling edge
(default)
Transmit Ð bit clock falling edge
Receive Ð bit clock rising edge
SCKD
0
1
Description
External clock source
Internal clock source
SCD2
0
1
Description
SCD2 pin is input
SCD2 pin is output
SCD1
0
1
Description
SCD1 pin is input
SCD1 pin is output
SCD0
0
1
Description
SCD0 pin is input
SCD0 pin is output
MOD
0
1
SYN
0
1
Description
Normal mode
Network mode
Description
Asynchronous mode
Synchronous mode
15
FSP
14
FSR
13
FSL1
12
FSL0
11
*
0
10
*
0
*
0
9 8
*
0
7 6 5 4 3
SHFD CKP SCKD SCD2 SCD1
$0
* = Reserved,
2 1 0
SCD0 MOD SYN
Motorola ProgrammerÕs Data Sheets
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E-87
Application:
BBP
BBPSR
BBP Status Register
Address = X:$FFA9
Reset = $0000
Read/Write
Freescale Semiconductor, Inc.
Date:
Programmer:
TUE
1
Description
TX underrun occurred
TFS
1
Description
TX frame sync occurred
ROE
1
Description
RX overrun occurred
RFS
1
Description
RX frame sync occurred
TDE
1
Description
TX data register empty
Serial Input Flags
RDF
1
Description
RX data register has data
E-88
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
*
0
8
*
0
7
RDF
$0
* = Reserved,
6
TDE
5 4
ROE TUE
3
RFS
2
TFS
1
IF1
0
IF0
DSP56652 UserÕs Manual
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Motorola
Application:
Freescale Semiconductor, Inc.
Date:
Programmer:
BBP
BBPRX
BBP Receive Data Register
Address = X:$FFAA
Reset = $0000
Read/Write
15 14 13 12 11
High Byte
10 9 8 7 6 5 4 3
Low Byte
2 1 0
BBPTSR
BBP Time Slot Register
Address = X:$FFAB
Reset = $0000
Read/Write
15 14 13 12 11 10 9 8 7 6 5
Dummy Register, Written During Inactive Time Slots
4 3 2 1 0
BBPTX
BBP Transmit Data Register
Address = X:$FFAC
Reset = $0000
Read/Write
15 14 13 12 11
High Byte
10 9 8 7 6 5 4 3
Low Byte
2 1 0
Motorola ProgrammerÕs Data Sheets
For More Information On This Product,
Go to: www.freescale.com
E-89
Freescale Semiconductor, Inc.
Application: Date:
Programmer:
15
*
0
BBP
BBPPDR
BBP Port Data Register
Address = X:$FFAD
Reset = $0000
Read/Write
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
*
9
0
Port Data Bits
*
8
0
*
7
0
*
6
0
5 4 3 2 1 0
BBPPD5 BBPPD4 BBPPD3 BBPPD2 BBPPD1 BBPPD0
BBPPCR
BBP Port Control Register
Address = X:$FFAF
Reset = $0000
Read/Write
PEN
0
1
Description
Port pins are tri-stated
Port pins enabled
BBPPCn
0
1
Description
Pin configured as GPIO
Pin configured as SAP
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
$0
9
*
0
8
*
0
7
PEN
6
*
0
5 4 3 2 1 0
BBPPC5 BBPPC4 BBPPC3 BBPPC2 BBPPC1 BBPPC0
(STDA) (SRDA) (SCKA) (SC2A) (SC1A) (SC0A)
BBPDDR
BBP Data Direction Register
Address = X:$FFAE
Reset = $0000
Read/Write
BBPDDn
0
1
Pin is input
Description
Pin is output
15
*
0
14
*
0
$0
13
*
0
12
*
0
11
*
0
10
*
0
9
*
0
8
*
0
7
*
0
$0
* = Reserved,
6
*
0
5 4 3 2 1 0
BBPDD5 BBPDD4 BBPDD3 BBPDD2 BBPDD1 BBPDD0
E-90 DSP56652 UserÕs Manual
For More Information On This Product,
Go to: www.freescale.com
Motorola
Freescale Semiconductor, Inc.
Motorola ProgrammerÕs Data Sheets
For More Information On This Product,
Go to: www.freescale.com
E-91
Freescale Semiconductor, Inc.
E-92 DSP56652 UserÕs Manual
For More Information On This Product,
Go to: www.freescale.com
Motorola
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