AMS AS7024 Datasheet
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AS7024
Biosensors
General Description
The AS7024 device provides a flexible analog front end for light sensing applications. The photodiode input circuit can be configured in different ways to guarantee best tradeoff between speed and sensitivity for a large number of different sensing applications.
AS7024 is targeted for wearables (fitness band, smart watch).
and
Content Guide appear at end of
datasheet.
Key Benefits and Features
The benefits and features of AS7024, Biosensors are listed below:
Figure 1:
Added Value of Using AS7024
Benefits
•
Allows smallest application size e.g. narrow HRM measurement band
•
Good HRM measurement quality
•
Additional information for end user
•
Long operating time
•
Works reliably with ambient light
Features
•
Single device integrated optical solution
•
Low noise analog optical front end
•
Analog electrical front end (e.g. for temperature sensing using a NTC or galvanic skin resistivity
(GSR))
•
Hardware sequencer to offload processor
•
Adjustable LED driver with current control
•
Synchronous demodulator
ams Datasheet
[v1-04] 2018-Sep-11
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Figure 2:
Application Schematic AS7024
AS7024 −
General Description
Applications
The device is suitable for optical sensor platform.
VD1
VBAT
ECG_INP
ECG_INN
ECG_REF
SDA
SCL
INT
2.7V-5.5V
VDD
V_LDO
GND
VD3
LDO
LED1 LED4
Optical barrier
I2C, Optical &
Electrical
Frontend,
ECG Amp.
Ref
IR
VD4
ENABLE
GPIO3
GPIO2
GPIO1
GPIO0
SIGREF
AGND
Optical barrier
LED2
AS7024
VD2
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AS7024 −
Pin Assignments
Pin Assignments
Optical Module Pinout:
This drawing is not to scale
Figure 3:
AS7024 Optical Module Pinout (Top View)
VD1 1
VD3 2
GND 3
ECG_INP 4
ECG_INN 5
ECG_REF 6
ENABLE 7
INT 8
SCL 9
SDA 10
LED
1
Sensor
LED
4
LED
2
20 VD4
19 VD2
18 SIGREF
17 AGND
16 V_LDO
15 GPIO3
14 GPIO2
13 GPIO1
12 GPIO0
11 VDD
Figure 4:
Pin Description
Pin No.
3
4
1
2
5
6
7
8
9
Pin Name
VD1
VD3
GND
ECG_INP
ECG_INN
ECG_REF
ENABLE
INT
SCL
Description
Supply voltage for LED D1
Connection to current sink 3
Power supply ground. All voltages are referenced to GND.
ECG amplifier positive input
ECG amplifier negative input
ECG amplifier reference output
Enable input for AS7024. Active high. Setting this input to low resets all internal registers and the AS7024 enters power down mode. Setting it high allows operation of the AS7024.
If ENABLE is not used (AS7024 always enabled), connect to VDD.
Open drain interrupt output pin. Active low.
I²C serial clock input terminal – the device does not use clock stretching therefore SCL is only an input terminal.
ams Datasheet
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AS7024 −
Pin Assignments
Pin No.
10
11
12
13
14
15
16
17
18
19
20
Pin Name
SDA
VDD
GPIO0
GPIO1
GPIO2
GPIO3
V_LDO
AGND
SIGREF
VD2
VD4
Description
I²C serial data I/O terminal – open drain.
Supply voltage. Connect a 2.2
μ
F capacitor to GND.
General purpose input/output
General purpose input/output
General purpose input/output
General purpose input/output
1.9V output voltage. Connect 2.2
μ
F capacitor to GND
(e.g. 0402 sized capacitor GRM153R60J225ME95 or 0201 sized
GRM033R60J225ME47 from Murata – needs to have >1
μ
F with 1.0V voltage bias); do not load externally
Analog ground. Connect to low noise GND
Analog reference output. Connect 2.2
μ
F capacitor to GND
(e.g. 0402 sized capacitor GRM153R60J225ME95 or 0201 sized
GRM033R60J225ME47 from Murata – needs to have >1
μ
F specified for 1.0V voltage bias); do not load externally
The typical operating voltage on this pin is 0.6V (sigref_en=1)
Supply voltage for LED D2
Supply voltage for LED D4
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AS7024 −
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in
is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 5:
Absolute Maximum Ratings
Symbol
VDD
V
IN
V
IN-OTHER
Parameter Min Max
Supply Voltage to Ground
Input Pin Voltage to Ground pins GPIO0/1/2/3
Electrical Parameters
6V
-0.3
VDD+0.3V
max. 6V
Input Pin Voltage to Ground pins SCL/SDA/INT/ENABLE and
VD1/VD2/VD3/VD4
-0.3
5.5
Units
V
V
V
V
VD1/2/3/4_
INTERNAL
Voltage between internal pin of
VD1-VD4 to VDD
VDD+0.3V
V
V
Comments
Diode to VDD
No internal diode to VDD or V_LDO
Internal diode between current source (internal node at anode of the LED if the pin has a LED otherwise VD1/2/3/4 pin) and VDD
Diode to VDD
V
V
IN-LDO
IN-LDO_
DIODE
V
GND-AGND
Input Pin Voltage to Ground for pin V_LDO
Input Pin Voltage to Ground pins for ECG_INP/ECG_
INN/ECG_REF/SIGREF
Analog to power ground voltage difference
-0.3
-0.3
-0.3
VDD+0.3V
max. 6V
V_LDO+0.3V
max. 6V
+0.3
V Diode to V_LDO
I
SCR
Input Current (latch-up immunity)
-100 100
V mA
JEDEC JESD78
Connect specified capacitor on SIGREF and
V_LDO during latchup test
ESD
HBM
Electrostatic Discharge HBM
Electrostatic Discharge
±2.0
kV JS-001-2014
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AS7024 −
Absolute Maximum R atings
Symbol
T
STRG
Parameter Min Max Units
Temperature Ranges and Storage Conditions
Storage Temperature Range -40 85 °C
T
BODY
Package Body Temperature 260
Comments
°C
IPC/JEDEC J-STD-020
The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC
J-STD-020
“Moisture/Reflow
Sensitivity Classification for
Non-hermetic Solid State
Surface Mount Devices.”
RH
NC
MSL
Relative Humidity
(non-condensing)
Moisture Sensitivity Level
5
3
85 %
Maximum floor life time of
168h
Note(s):
1. All optical customer designs shall be reviewed by
ams
before production.
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ams Datasheet
[v1-04] 2018-Sep-11
AS7024 −
Electrical Characteristics
Electrical Characteristics
All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical
Quality Control) methods.
VDD=2.7 to 5.5V, typ. values are at T
AMB
=25°C (unless otherwise specified).
Figure 6:
Operating Conditions
Symbol
VDD
T
AMB
Parameter
Supply voltage
Operating free-air temperature
Conditions Min Typ Max Unit
2.7
3.8
5.5
V
−30 70 °C
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AS7024 −
Electrical Characteristics
Symbol Parameter
IDD Supply current
VOL
VOH
VIH
GPIO0-3, INT, SDA output low voltage
GPIO0-3 output high voltage
GPIO0-3, SCL, SDA,
ENABLE input high voltage
Conditions
ENABLE=VDD, ldo_en=0; osc_en=0; internal LDO operating in low power mode – only I²C communication possible, no blocks shall be enabled
ENABLE=VDD, ldo_en=1; osc_en=0; internal LDO operating and bandgap running – I²C communication possible, analog blocks can be enabled
ENABLE=VDD, ldo_en=1, osc_en=1; internal LDO operating and bandgap and oscillator running – I²C communication possible, analog blocks can be enabled
SIGREF buffer (sigref_en=1) transimpedance amplifier
(pd_amp_en=1)
Optical front end operating (one channel)
Gain stage (ofe1_gain_en=1 or ofe2_gain_en=1)
ADC sampling at 20Hz with 64μs settling time
ECG amplifier and frontend (need
SIGREF enabled)
ECG leakage compensation (ecg_ low_leakage_en=1), low pass filter, high pass filter and gain stage
Power down, no I²C communication possible
ENABLE=GND
With 3 mA load
With 6 mA load
Min Typ Max Unit
0
0
22
32
86
52
110
200
75
4.5
151
0.5
0.4
0.8
μA
μA
μA
μA
μA
μA
μA
μA
190 μA
μA
μA
V
With 3 mA load 2.3
VDD V
1.25
V
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ams Datasheet
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AS7024 −
Electrical Characteristics
Symbol
VIL
ILEAK1
ILEAK2
Parameter
GPIO0-3, SCL, SDA,
ENABLE input low voltage
GPIO0-3, SCL, SDA,
ENABLE, INT
VD1, VD23 pins
E_f2M
Tolerance of internal
2MHz oscillator
ILEAK_
ECG
ECG pins leakage current
V
NOISE_
ECG
Integrated noise
CMRR
ECG
Common mode rejection ratio
Conditions Min Typ Max Unit
0.54
V
0ºC to 70ºC, VDD<5.0V
-30ºC to 70ºC
ECG Amplifier and Filter
Lab evaluation shows <±20nA maximum leakage current. Not production tested.
ADC sampling at 400Hz; low pass filter set to 40Hz, PPG channel operating in parallel
Measured at 50Hz and 100Hz
−1
−1
-2
-4
±1
20
73
1
1
+2
+2
μA
μA
%
% nA
μV dB
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AS7024 −
Electrical Characteristics
Symbol Parameter Conditions
LED
I
LED
VF
LED
λp
I
LED1/2/3/4
Allowed operating LED current range
Forward voltage
Peak wavelength at
I
LED
=20mA
LED output current range
Tolerance
1/10 duty cycle @ 1 kHz
Green LED, add compliance voltage of LED driver, ILED=10mA, add compliance voltage of LED driver (V_Dmin) to obtain minimum voltage on the pin to drive the current at T
AMB
=25ºC
IR LED, ILED=20mA
Green LED
IR LED
LED Driver
LED current is adjustable with 10 bits – registers curr1/2/3/4
At 35mA output current
(currX[9:0]=166h, X=1…4),
VDD<5.0V
V_Dmin
V_Dmax
Output voltage compliance
Output voltage maximum
Min Typ Max Unit
0
0
-7
3.1
1.4
527
940
0.3
50
100
3.3
100
7
5.5
mA
V nm mA
%
V
V
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AS7024 −
Electrical Characteristics
Symbol
Re
PD1-4
Id
Ios
Parameter
Irradiance responsivity photodiode PD1…PD4
Irradiance responsivity photodiode B
Dark current
Extrapolated offset current
Conditions
Photodiode
λ
P
=525nm,
4 photodiodes used pd1/2/3/4=1, gain_g=4x, gain_en=1, pd_ampres = 7MΩ
λ
P
=940nm, gain_g=4x, gain_en=1, pd_ampres=7MΩ
E e
=0, T
AMB
=25°C
T
AMB
=25°C
ADC
Vref
INL
DNL
SNR
THD
Tconv
Vin
ADC reference voltage
Resolution
Relative accuracy
Differential
Offset error
Gain error
Signal-to-noise ratio
Total harmonic distortion
Conversion rate
Input voltage range
T
AMB
=25°C
Fsample = 1kHz, Fsignal=100Hz
Fsample = 1kHz, Fsignal=100Hz
14 bit resolution
Min Typ Max Unit
0
−1
-8
-8
14
-8
0
45.9
0.3
1.6
V
Bit
8 LSB
1.5
80
-70
1
1
8
8
50
Vref mV/
(μW
/cm
2
) nA nA
LSB
LSB
LSB dB dB ksps
V
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AS7024 −
Electrical Characteristics
Symbol
f
SCLK t
BUF t
HD:STA t
LOW t
HIGH t
SU:STA t
HD:DAT t
SU:DAT t
R t
F t
SU:STO
C
B
C
I/O
Parameter Conditions
I²C Mode Timings
SCL Clock Frequency
Bus Free Time Between a STOP and START
Condition
Hold Time (Repeated)
START Condition
LOW Period of SCL Clock
HIGH Period of SCL
Clock
Setup Time for a
Repeated START
Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Setup Time for STOP
Condition
Capacitive Load for Each
Bus Line
CB — total capacitance of one bus line in pF
I/O pin Capacitance
(SDA, SCL)
Min Typ Max Unit
0
1.3
0.6
1.3
0.6
0.6
0
100
20
20
0.6
400
0.9
300
300
400
10 kHz
μs
μs
μs
μs
μs
μs ns ns ns
μs pF pF
Note(s):
1. GPIO0-3 configured to draw minimum current (software dependent).
2. The design of AS7024 is done in a way that it does not affect other I²C communication on SCL/SDA even if AS7024 is in power down.
3. Specified only typical value for DNL to reduce production test time.
4. After this period, the first clock pulse is generated.
5. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL.
6. A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
= to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max + t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
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AS7024 −
Electrical Characteristics
Figure 7:
I²C Mode Timing Diagram
I²C Mode Timing Diagram:
This figure shows the different timings required for I²C communication.
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AS7024 −
Detailed Description
Detailed Description
Optical Analog Front End
Figure 8:
Optical Analog Front End
pd1 pd2 pd3 pd4 pd_i0 pd_i1 any LED on?
pdoffx pdoffx_ledon
TIA pd_ampres pd_ampcap pd_amp_en aa_freq
200Hz gain_sd h/l vth
Clip Det
Prefilter
Clip Det h/l vth
Synchronous Demodulator1,2 + BP Filter + Gain Stages ofe1_en, ofe2_en ofe1/2_sd_byp ofe1/2_hp_byp
* ofe1/2_sd_bw ofe1/2_hp_freq ofe1/2_hp_en ofe1/2
_gain_g sd1 tia sd2 ofe1 ofe2 pregain
ADC
FiFo fifol, fifoh
Sequencer
LEDs
Two green LEDs are used with anode on pin VD1 and VD2. A IR
LED is connected with anode to pin VD4. VD3 allows direct access to the current sink 3.
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AS7024 −
Detailed Description
Figure 9:
LED Drivers
LED-Driver
The LED-driver outputs can be controlled manually or by the built in sequencer. See
Optical Front End Operating Modes
ledX_en man_mode man_sw_ledX
Sequencer
VD1
D1 max. compliance
VD2
D2
VD3 VD4
*
D3 D4
S
SET
Q
R
CL R
Q
write ‘1’ to register irq_led_supply_low ledX_supply
_low and irq_led_ supply_low currX ledX_mode
X=1
X=2
X=3
X=4
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AS7024 −
Detailed Description
LED Configuration Registers
Figure 10:
LED_CFG Register
Field
6
5:4
3
2
1
0
Name
sigref_en sigref_voltage led4_en led3_en led2_en led1_en
Rst Type
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
0x10: LED_CFG
Description
Signal reference: Is required for all analog blocks
(except PD_Amp or light-to-frequency operation)
0 … Disable signal reference
1 … Enable signal reference
Voltage setting of SIGREF – datasheet parameters are guaranteed only for default value of 0.6V.
Setting
0
1
2
IMAX
0.6V (default)
0.7V
0.8V
0.9V
3
0 … Disables LED4 output source.
1 … Enables LED4 output source.
0 … Disables LED3 output source.
1 … Enables LED3 output source.
0 … Disables LED2 output source.
1 … Enables LED2 output source.
0 … Disables LED1 output source.
1 … Enables LED1 output source.
The LED_CURR defines the LED output current. Warning: it is recommended to configure the current only when the output is not active, as there is no latch implemented to keep the 10 bits consistent. New values are applied directly and immediately.
Figure 11:
LED1_CURRL Register
Field
7:6
Name
curr1[1:0] 0 RW
0x12: LED1_CURRL
Rst Type Description
LED1 output current lower 2 bits
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AS7024 −
Detailed Description
Figure 12:
LED1_CURRH Register
Field
7:0
Name
curr1[9:2] 0 RW
0x13: LED1_CURRH
Rst Type Description
LED1 output current upper 8 bits
Coding for curr1[9:0]:
000h … 786μA
001h … 883μA (1 LSB=97μA)
002h … 980μA
166h … 35mA
3FFh … 100mA
Figure 13:
LED2_CURRL Register
Field
7:6
Name
curr2[1:0]
Figure 14:
LED2_CURRH Register
Field
7:0
0 RW
0x14: LED2_CURRL
Rst Type Description
LED2 output current lower 2 bits
Name
curr2[9:2] 0 RW
0x15: LED2_CURRH
Rst Type Description
LED2 output current upper 8 bits
Coding for curr2[9:0]:
000h … 786μA
001h … 883μA (1 LSB=97μA)
002h … 980μA
166h … 35mA
3FFh … 100mA
Figure 15:
LED3_CURRL Register
Field
7:6
Name
curr3[1:0] 0 RW
0x16: LED3_CURRL
Rst Type Description
LED3 output current lower 2 bits
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AS7024 −
Detailed Description
Figure 16:
LED3_CURRH Register
Field
7:0
Name
curr3[9:2] 0 RW
0x17: LED3_CURRH
Rst Type Description
LED3 output current upper 8 bits
Coding for curr3[9:0]:
000h … 786μA
001h … 883μA (1 LSB=97μA)
002h … 980μA
166h … 35mA
3FFh … 100mA
Figure 17:
LED4_CURRL Register
Field
7:6
Name
curr4[1:0]
Figure 18:
LED4_CURRH Register
0 RW
0x18: LED4_CURRL
Rst Type Description
LED4 output current lower 2 bits
Field
7:0
Name
curr4[9:2] 0 RW
0x19: LED4_CURRH
Rst Type Description
LED4 output current upper 8 bits
Coding for curr4[9:0]:
000h … 786μA
001h … 883μA (1 LSB=97μA)
002h … 980μA
166h … 35mA
3FFh … 100mA
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AS7024 −
Detailed Description
Figure 19:
LED12_MODE Register
Field
7
6:4
3
Name
man_sw_led2
led2_mode man_sw_led1
0
0
0
RW
RW
RW
0x2c: LED12_MODE
Rst Type Description
0 … LED output D2 disabled. (High impedance)
1 … LED output D2 enabled
LED2 mode
Setting Behavior
0
1
2
3
Always OFF
Always ON when sequencer is active
Controlled by sequencer
Controlled by sequencer, only ON in even iterations: 0, 2, 4 etc.
4
5
Controlled by sequencer, only ON in odd iterations: 1, 3, 5 etc.
Controlled by sequencer, only ON in every fourth iteration, starting at 1: 1, 5, 9 etc.
6
Controlled by sequencer: secondary LED timing
Do not use 7
0 … LED output D1 disabled. (High impedance)
1 … LED output D1 enable
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AS7024 −
Detailed Description
Field
2:0
Name
led1_mode
0x2c: LED12_MODE
Rst Type
LED1 mode
Setting
0
1
2
0 RW
3
4
5
6
7
Description
Behavior
Always OFF
Always ON when sequencer is active
Controlled by sequencer
Controlled by sequencer, only ON in even iterations: 0, 2, 4 etc.
Controlled by sequencer, only ON in odd iterations: 1, 3, 5 etc.
Controlled by sequencer, only ON in every fourth iteration, starting at 0: 0, 4, 8 etc.
Controlled by sequencer: secondary LED timing
Do not use
Note(s):
1. Function enabled only in manual mode
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AS7024 −
Detailed Description
Figure 20:
LED34_MODE Register
Field
7
Name
man_sw_
Rst
0
6:4 led4_mode 0
3 man_sw_
0
RW
RW
RW
0x2d: LED34_MODE
Type Description
0 … LED output D4 disabled. (High impedance)
1 … LED output D4 enabled
LED4 mode
Setting
0
1
2
3
Behavior
Always OFF
Always ON when sequencer is active
Controlled by sequencer
Controlled by sequencer, only ON in even iterations: 0, 2, 4 etc.
4
5
6
7
Controlled by sequencer, only ON in odd iterations: 1, 3, 5 etc.
Controlled by sequencer, only ON in every fourth iteration, starting at 3: 3, 7, 11 etc.
Controlled by sequencer: secondary LED timing
Do not use
0 … LED output D3 disabled. (High impedance)
1 … LED output D3 enabled
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AS7024 −
Detailed Description
Field Name
2:0 led3_mode
Rst
0 RW
0x2d: LED34_MODE
Type Description
LED3 mode
Setting
0
1
2
3
Behavior
Always OFF
Always ON when sequencer is active
Controlled by sequencer
Controlled by sequencer, only ON in even iterations: 0, 2, 4 etc.
4
5
6
7
Controlled by sequencer, only ON in odd iterations: 1, 3, 5 etc.
Controlled by sequencer, only ON in every fourth iteration, starting at 2: 2, 6, 10 etc.
Controlled by sequencer: secondary LED timing
Do not use
Note(s):
1. Function enabled only in manual mode
The MAN_SEQ_CFG register is used to configure the operation of the optical front end.
Figure 21:
MAN_SEQ_CFG Register
Field
7
6
5
4
Name
man_mode man_sw_ sdmult man_sw_ sdpol man_sw_itg
0x2e: MAN_SEQ_CFG
Rst Type
0
0
0
0
RW
RW
RW
RW
Description
0 … Enables Sequencer
1 … Enables Manual control of optical front end
If man_mode=1
0 … Disables synchronous demodulator multiplication
1 … Enables synchronous demodulator multiplication
If man_mode=1
0 … Negative polarity in synchronous demodulator multiplication
1 … Positive polarity in synchronous demodulator multiplication
If man_mode=1
0 … All integrator capacitors are shorted. Integrator is reset
1 … Integrator capacitors are charging up. Integrator is running
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AS7024 −
Detailed Description
Field
3:1
0
Name
diode_ctrl seq_en
0x2e: MAN_SEQ_CFG
Rst Type
0
0
RW
RW
Description
Connection of Photodiodes PD1, PD2, PD3, PD4 to the photodiode amplifier.
0 … PD1-PD4 are connected
1 … PD1 synchronous to LED1, PD2 sync/to LED2, PD3 sync/to
LED3, PD4 sync/to LED4
2 … PD1 synchronous to LED1, PD2 sync/to LED1, PD3 sync/to
LED2, PD4 sync/to LED2
3 … PD1 synchronous to LED1, PD2 sync/to LED1, PD3 sync/to
LED4, PD4 sync/to LED4
4 … SPO2 mode *(obsolete): (negedge(sdm1) or negedge(sdp1)) -
PD1=0 PD2=0 PD3=1 PD4=1; (negedge(sdm2) or negedge(sdp2)) -
PD1=1 PD2=1 PD3=0 PD4=0
Note that PD_CFG.pdX takes precedence - to turn OFF one photo diode, the respective bit has to be de-asserted in the PD_CFG register.
PD_
CFG.pdX
diode_ ctrl
Photo
Diode1
Photo
Diode2
Photo
Diode3
Photo
Diode4
0
1
1
1 xx
0
1
2
1
1
3
4
1 5..7
0 … Disables sequencer
1 … Enables sequencer
OFF
ON
LED1
LED1
LED1
OFF
ON
LED2
LED1
LED1
OFF
ON
LED3
LED2
LED4
SPO2 mode (obsolete)
Do not use
OFF
ON
LED4
LED2
LED4
Figure 22:
LEDSTATUS Register
Field
1
0
3
2
Name
led4_supply_low led3_supply_low led2_supply_low led1_supply_low
Rst
0
0
0
0
RO
RO
RO
RO
0xa2: LEDSTATUS
Type Description
If this bit is asserted, LED4 voltage has been too low.
If this bit is asserted, LED3 voltage has been too low.
If this bit is asserted, LED2 voltage has been too low.
If this bit is asserted, LED1 voltage has been too low.
ams Datasheet
[v1-04] 2018-Sep-11
An asserted bit can be cleared by writing a '1' to the irq_led_ supply_low bit.
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Figure 23:
Photodiode Selection
AS7024 −
Detailed Description
Photodiode Selection
In order to have flexible arrangement of the use photodiodes,
PD1-PD4 can be individually connected to the photodiode amplifier input. The optional offset current allows cancellation of constant light sources like sunlight. In case of an external photodiode or any other sensor with (low) current output, the pins GPIO0 and GPIO1 can be used as input.
Additionally the sequencer can control the diodes – see diode_ ctrl described in register MAN_SEQ_CFG.
GPIO0 pd1 pd2 pd3 pd4 pd_i0 pd_i1 any LED on?
pdoffx pdoffx_ledon to TIA
(Trans-Impedance-Amplifier)
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ams Datasheet
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AS7024 −
Detailed Description
Photodiode Registers
The PD_CFG register is used to configure the input to the photo amplifier.
Figure 24:
PD_CFG Register
Field
5
Name
pd4
4
3
2
1
0 pd3 pd2 pd1 pd_i1 pd_i0
Rst
0
0
0
0
0
0
Type
RW
RW
RW
RW
RW
RW
0x1a: PD_CFG
Description
0 … Photodiode PD4 is disconnected from photo amplifier
1 … Photodiode PD4 is connected to photo amplifier
(as defined in diode_ctrl)
0 … Photodiode PD3 is disconnected from photo amplifier
1 … Photodiode PD3 is connected to photo amplifier
(as defined in diode_ctrl)
0 … Photodiode PD2 is disconnected from photo amplifier
1 … Photodiode PD2 is connected to photo amplifier
(as defined in diode_ctrl)
0 … Photodiode PD1 is disconnected from photo amplifier
1 … Photodiode PD1 is connected to photo amplifier
(as defined in diode_ctrl)
0… Photodiode B (see Photodiode Characteristics
) disconnected from TIA input
1… Photodiode B (see Photodiode Characteristics
) connected to TIA input; set ltf1_sel=0 and ltf2_sel=0.
0 … GPIO0-input is disconnected from photo amplifier
1 … GPIO0-input is connected to photo amplifier; set gpio_a[0]=1.
ams Datasheet
[v1-04] 2018-Sep-11
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AS7024 −
Detailed Description
Figure 25:
PDOFFX_LEDOFF Register
Field
7:0
Name
pdoffx_ ledoff
Rst
0
0x1b: PDOFFX_LEDOFF
Type
RW
Description
Input offset current if all LEDs are OFF (all sw_led* sequencer outputs are zero)
Ioffset = pdoffx_ledoff*10nA
0 … Offset source is turned OFF
Figure 26:
PDOFFX_LEDON Register
Field
7:0
Name
pdoffx_ ledon
Rst
0
0x1c: PDOFFX_LEDON
Type
RW
Description
Input offset current if at least one LED is ON (one or more sw_led* sequencer outputs are non-zero)
Ioffset = pdoffx_ledon*10nA
0 … Offset source is turned OFF
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ams Datasheet
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AS7024 −
Detailed Description
Photodiode Characteristics
Figure 27:
Photodiode Arrangement – Orientation as in
LED
1
LED
4
1mm
PD1
A B
PD3
PD4 PD2
1mm
Sensor
LED
2
For operation and characteristics of photodiode ‘A’ and photodiode ‘B’ see
ams Datasheet
[v1-04] 2018-Sep-11
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AS7024 −
Detailed Description
Figure 28:
Photodiode Sensitivity (solid green and black) and LED Emission Spectrum (dotted green and dotted black)
80%
60%
120%
100%
AS7024 PD1-PD4
AS7024 Photodiode B
Green LED
IR LED 940nm
NREL Sun normlized
40%
20%
0%
300 400 500 600 700
Wavelength (nm)
800 900 1000 1100
Note(s):
1. All 4 photodiodes used pd1/2/3/4=1;perpendicular; perpendicular light source and no diffuser used on AS7024; due to the difference in photodiode size the absolute response for Photodiode B (0.01mm
2
) is much lower compared to PD1-PD4 (0.8mm
2
).
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ams Datasheet
[v1-04] 2018-Sep-11
AS7024 −
Detailed Description
Photodiode Trans-Impedance Amplifier (TIA)
The photodiode amplifier can be configured in three different modes:
•
Photocurrent to frequency converter – see
Light-to-Frequency Mode Registers
•
Photocurrent to voltage converter
•
Photocurrent integrator
Figure 29:
Trans-Impedance-Amplifier (TIA)
pd_ampres pd_ampcap from photodiodes pd_amp_en man_mode man_sw_itg
Sequencer to synchronous demodulator
The integration time t
INT
is defined either by the sequencer
(man_mode=0) of manually through the bit sw_itg if man_mode=1.
ams Datasheet
[v1-04] 2018-Sep-11
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AS7024 −
Detailed Description
Use following settings for the programming of the TIA:
Figure 30:
TIA Programming Settings pd_ampres pd12341
1
2
3
4
5
6
7
3 …4
1 …2
3 …4
1
1 …4
1 …4
1 …4
1 …2
2 …4
1 …2
3 …4
5
0
0
0
1 …4
1 …4
1 …4
1 …4
pd_ampcap pd_ampcomp pd_ampvo
13
7
1
1
5
2
1
0
3
2
0
3
1
0
2
1
0
2
Low Bandwidth Mode
31 3
Integrating Mode (pd_ampres=0)
10
20
30
3
3
3
15
15
15
15
15
15
15
15
15
15
15
Gain
1V/μA
2V/μA
3V/μA
5V/μA
7V/μA
10V/μA
15V/μA
7V/μA
1V/pQ
1/2V/pQ
1/3V/pQ
Note(s):
1. pd1234: number of active photodiodes (for example, pd1=1, pd2=0, pd3=1, pd4=0 -> pd1234=2).
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ams Datasheet
[v1-04] 2018-Sep-11
AS7024 −
Detailed Description
Photodiode TIA Registers
Figure 31:
PD_AMPRCCFG Register
Field Name
7:5 pd_ampres
4:0 pd_ampcap
Rst
0
0
0x1d: PD_AMPRCCFG
Type
RW
RW
Description
Feedback resistor
Setting
0
Resistance
No resistor in feedback of amplifier – photocurrent integrator
3
4
1
2
1MΩ
2MΩ
3MΩ
5MΩ
5
6
7
Feedback capacitor
7MΩ
10MΩ
15MΩ
The PD_AMPCFG register is used to configure the operating mode of the photoamplifier.
Figure 32:
PD_AMPCFG Register
Field
7
6
5:2
1:0
Name
pd_amp_en pd_amp_ auto pd_ampvo pd_ ampcomp
Rst
0
0
15
3
0x1e: PD_AMPCFG
Type
RW
RW
RW
RW
Description
0 … Activates power down mode of photo-amplifier
1 … Enables photo-amplifier (direct or automatic pd_ amp_auto mode) also set en_bias_ofe=1
0 … Normal TIA mode
1 … Enable TIA only when seq_itg is set (i.e. controlled by sequencer itg setting) also set en_bias_ofe=1
OpAmp offset. Can be used to limit signal in darkness and to shorten rise times
OpAmp compensation, depending on gain and number of used photo diodes Capacitor = pd_ampcap*0.1pF
ams Datasheet
[v1-04] 2018-Sep-11
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AS7024 −
Detailed Description
Figure 33:
PD_THRESHCFG Register
Field
7:4
3:0
Name
pd_ clipdetect_ h_thresh pd_ clipdetect_ l_thresh
Rst
0
0
0x1f: PD_THRESHCFG
Type
RW
RW
Description
If the voltage on the output of the TIA exceed this threshold the irq_clipdetect interrupt is asserted. The threshold is defined as
0 … 1824mV
1 … 1748mV
2 … 1672mV
3 … 1596mV
4 … 1520mV
5 … 1444mV
6 … 1368mV
7 … 1292mV
8 … 1216mV
9 … 1140mV
10 … 1064mV
11… 988mV
12 … 912mV
13 … 836mV
14 … 760mV
15 … 684mV
If the voltage on the output of the TIA falls below this threshold the irq_clipdetect interrupt is asserted. The threshold is defined as
0 … 67mV
1 … 143mV
2 … 219mV
3 … 295mV
4 … 371mV
5 … 447mV
6 … 523mV
7 … 599mV
8 … 675mV
9 … 751mV
10 … 827mV
11 … 903mV
12 … 979mV
13 … 1055mV
14 … 1131mV
15 … 1207mV
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ams Datasheet
[v1-04] 2018-Sep-11
AS7024 −
Detailed Description
Voltage Mode of the Photodiode Amplifier
The output voltage of the photodiode amplifier is depending on the feedback component:
(EQ1)
Feedback resistor:
U out
= I photo
⋅
R fb
(EQ2)
Feedback capacitor:
U out
= I photo
⋅ t
----------
C fb
Note(s):
The integration time t
INT
is defined either by the sequencer (man_mode=0) of manually through the bit sw_itg if man_mode=1.
For the synchronous demodulator only use the resistive feedback.
Figure 34:
Difference Between Resistive and Capacitive Feedback ams Datasheet
[v1-04] 2018-Sep-11
With reference to
,
• Green:
Capacitive Integration
• Green Dotted:
Effective Value from Capacitive Mode
• Blue:
Resistive Feedback
• Red:
Light Intensity
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AS7024 −
Detailed Description
Optical Front End Operating Modes
Once the photodiode amplifier is configured the measurement can be done in two different ways. Either the LED-outputs, the photodiode amplifier and the ADC are controlled manually by means of register bits, or they are controlled by a built in sequencer.
Manual Operation of the Optical Frontend:
The optical front end can be manually controlled via the register man_mode=1
Figure 35:
Manual Operation of the Optical Frontend and LED
GPIO0
GPIO1 pd1 pd2 pd3 pd4 any LED on?
pdoffx pdoffx_ledon pd_ampres pd_ampcap pd_amp_en pdi_0 pdi_1 man_sw_itg adc_channel_mask_tia is set?
ADC
Start conversion: seq_en=1
End of conversion: seq_en returns to 0
Note(s):
1. Applies only If man_mode=1
For manual operation of the LEDs and its current sinks see
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AS7024 −
Detailed Description
Sequencer
In order to synchronize the LED-currents, the integration time and the ADC-sampling time, a built in sampling Sequencers can be used. The sequencer generates the 8 bit-timings based on a
1μs clock which can be pre-scaled with seq_div. The results of the analog to digital conversion are automatically stored in a pipeline buffer or in register adc_data and the ADC FIFO.
The timings can be programmed with following registers (apply for man_mode=0):
Figure 36:
Sequencer Control Registers Overview
Register
seq_div seq_count seq_start seq_period seq_led_start seq_led_stop seq_secled_start seq_secled_stop seq_itg_start seq_itg_stop seq_sdp1_start seq_sdp1_stop seq_sdm1_start seq_sdm1_stop seq_sdp2_start seq_sdp2_stop seq_sdm2_start seq_sdm2_stop seq_adc
Description
Divider of the 1μs input clock for all sequencer timings
Number of measurements in one sequence
Writing 1 starts the sequencer, 0 stops the sequencer
Time of one measurement cycle
Start time of the LED drivers within one cycle
Stop time of the LED drivers within one cycle
Start time of the secondary LED drivers within one cycle (used for SpO2)
Stop time of the secondary LED drivers within one cycle (used for SpO2)
Start time of the integrator
Stop time of the integrator
Start time of the synchronous demodulator’s 1 positive multiplication
Stop time of the synchronous demodulator’s 1 positive multiplication
Start time of the synchronous demodulator’s 1 negative multiplication
Stop time of the synchronous demodulator’s 1 negative multiplication
Start time of the synchronous demodulator’s 2 positive multiplication
Stop time of the synchronous demodulator’s 2 positive multiplication
Start time of the synchronous demodulator’s 2 negative multiplication
Stop time of the synchronous demodulator’s 2 negative multiplication
Sampling position of the ADC
ams Datasheet
[v1-04] 2018-Sep-11
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AS7024 −
Detailed Description
Register
seq_adc2tia, seq_ adc3tia sd_subs, sd_subs_ always ulp
Description
If the TIA channel is selected allow a second (and third) conversion within this cycle.
Synchronous demodulator subsampling ratio between sequencer frequency and
ADC sampling frequency.
Ultra low power bit for the sequencer. If this bit is set and sd_subs>0, it disables the LED pulses and powers off the TIA in all sequences but the one where the TIA is sampled. This bit can be used to optimize the power consumption of the LEDs
.
The sequencer setup caused a timing error on ADC conversion.
irq_adc_timing_error
Note(s):
1. The lowest data value of all registers except seq_count and seq_div is 1.
2. This bit is located in register ADC_CFGB bit 1.
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ams Datasheet
[v1-04] 2018-Sep-11
AS7024 −
Detailed Description
Figure 37:
Block Diagram of Sequencer
pdoffx pd1 pd2 pd3 pd4 pdi_0 pdi_1 pd_ampres pd_ampcap pd_amp_en
TIA
Synchronous Demodulator sd_en
* aa_freq
200Hz sd_byp sd_bw hp_freq hp_en hp_byp
High Pass Filter
-1 +1 gain_g gain_en gain_byp
Gain Stage
ADC seq_itg_start seq_itg_stop clk register diode_ctrl led_x_mode x=1...4
seq_led_start seq_led_stop clk
S
SET
Q
R
CL R
Q
S SET
Q
R
CL R
Q
seq_sdp_start seq_sdp_stop clk seq_sdm1_start seq_sdm1_stop clk seq_sdm2_start
S SET
Q
+1 -1
R
CL R
Q
S SET
Q
R
CL R
Q
S
SET
Q
seq_sdm2_stop
R
CL R
Q
clk
Synchronous Demodulator control seq_div
1µs div sd_subs seq_adc_inc seq_adc
+ z
-1 clk init seq_adc_frac_inc seq_adc_frac
+ z
-1 init clk*16
Sequencer div
ADC control
Counter
0...seq_period-1 clk
Run/Reset
Run / Stop
Logic seq_count cycles seq_start
ams Datasheet
[v1-04] 2018-Sep-11
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AS7024 −
Detailed Description
Sequencer Registers
Figure 38:
SEQ_CNT Register
Field
7:0
Name
seq_count
Rst
0
0x30: SEQ_CNT
Type
RW
Description
Number of measurements in one sequence.
If seq_count = 0x0 the sequencer is running continuously if started by seq_start=1 or seq_start_sync=1.
This register is reset by disabling/enabling of seq_start=0
(but not by osc_off=1)
The SEQ_DIV register sets the input divider for the main clock.
Figure 39:
SEQ_DIV Register
Field
7:0
Name
seq_div
Rst
0 RW
0x31: SEQ_DIV
Type Description
Divider value
Sequencer time increment tclk = ( seq_div + 1 ) * 1us
Figure 40:
SEQ_START Register
Field
1
0
Name
seq_start_ sync seq_start
Rst
0
0
0x32: SEQ_START
Type
R_PUSH
R_PUSH
Description
Similar to seq_start, but the sequencer will wait for overflow of the frequency divider that feeds all the switched-cap filters. This means 1) that it could take anything between 0 and 8ms before the sequencer actually starts. And 2) That the generated frequencies are in phase with the sequencer. For this to have any effect, the sequencer period should be selected with the selected frequencies (sd_bw, hp_freq) in mind.
Writing 1 starts the sequencer(s) in the according to the configuration and upon rising edge of seq_start ADC selects first channel.
Writing 0 stops the sequencer(s).
In manual mode, writing 1 starts one ADC conversion but does not initialize the ADC channel selection. Reading returns 1 if the sequencer is running (sequencer mode), respectively if the ADC is converting (manual mode)
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AS7024 −
Detailed Description
With the SEQ_START register sets the configured sequencer can be started
Figure 41:
SEQ_PER Register
Field
7:0
Name
seq_period
Rst
0
0x33: SEQ_PER
Type
RW
Description
t_period
Sequencer period T = t_period * (seq_div+1) * 1us
The SEQ_PER register sets one measurement cycle of the sequencer.
Figure 42:
SEQ_LED_STA Register
Field
7:0
Name
seq_led_ start
Rst
0
0x34: SEQ_LED_STA
Type
RW LED start time
Description
The SEQ_LED register sets the LED drive timing. Data is stored as 16-bit value.
Figure 43:
SEQ_LED_STO Register
Field
7:0
Name
seq_led_ stop
Rst
0
0x35: SEQ_LED_STO
Type
RW LED stop time
Description
Figure 44:
SEQ_SECLED_STA Register
Field
7:0
Name
seq_secled_ start
Rst
0
0x36: SEQ_SECLED_STA
Type Description
RW Secondary LED start time
ams Datasheet
[v1-04] 2018-Sep-11
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AS7024 −
Detailed Description
The SEQ_LED register sets the secondary LED drive timing which is used in ledX_mode 6 only. Data is stored as 16-bit value.
Figure 45:
SEQ_SECLED_STO Register
Field
7:0
Name
seq_secled_ stop
Rst
0x37: SEQ_SECLED_STO
Type Description
0 RW Secondary LED stop time
Figure 46:
SEQ_ITG_STA Register
Field
7:0
Name
seq_itg_ start
Rst
1
0x38: SEQ_ITG_STA
Type
RW
Description
Integrator start time (start time=1 and stop time=0 means that it's - by default - always ON) Turning OFF the integrator actually means discharge the capacitor. This is only useful in capacitive integration mode, without the synchronous demodulator.
The SEQ_ITG register sets the photoamplifier integration time.
Data is stored as 16-bit value.
Figure 47:
SEQ_ITG_STO Register
Field
7:0
Name
seq_itg_ stop
Figure 48:
SEQ_SDP1_STA Register
Rst
0
0x39: SEQ_ITG_STO
Type
RW Integrator stop time
Description
Field
7:0
Name
seq_sdp1_ start
Rst
0
0x3a: SEQ_SDP1_STA
Type
RW
Description
Positive multiplication start time 1
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AS7024 −
Detailed Description
The SEQ_SDP register sets the synchronous demodulator positive multiplication time. Data is stored as 16-bit value.
Figure 49:
SEQ_SDP1_STO Register
Field
7:0
Name
seq_sdp1_ stop
Figure 50:
SEQ_SDP2_STA Register
Rst
0
0x3b: SEQ_SDP1_STO
Type
RW
Description
Positive multiplication stop time 1
Field
7:0
Name
seq_sdp2_ start
Rst
0
0x3c: SEQ_SDP2_STA
Type
RW
Description
Positive multiplication start time 2
The SEQ_SDP register sets the synchronous demodulator positive multiplication time. Data is stored as 16-bit value
Figure 51:
SEQ_SDP2_STO Register
Field
7:0
Name
seq_sdp2_ stop
Figure 52:
SEQ_SDM1_STA Register
Rst
0
0x3d: SEQ_SDP2_STO
Type
RW
Description
Positive multiplication stop time 2
Field
7:0
Name
seq_sdm1_ start
Rst
0
0x3e: SEQ_SDM1_STA
Type
RW
Description
Negative multiplication start time 1
The SEQ_SDM1 register sets the synchronous demodulator negative multiplication time 1. Data is stored as 16-bit value
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[v1-04] 2018-Sep-11
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AS7024 −
Detailed Description
Figure 53:
SEQ_SDM1_STO Register
Field
7:0
Name
seq_sdm1_ stop
Figure 54:
SEQ_SDM2_STA Register
Rst
0
0x3f: SEQ_SDM1_STO
Type
RW
Description
Negative multiplication stop time 1
Field
7:0
Name
seq_sdm2_ start
Rst
0
0x40: SEQ_SDM2_STA
Type
RW
Description
Negative multiplication start time 2
The SEQ_SDM2 register sets the synchronous demodulator negative multiplication time 2. Data is stored as 16-bit value
Figure 55:
SEQ_SDM2_STO Register
Field
7:0
Name
seq_sdm2_ stop
Figure 56:
SEQ_ADC Register
Rst
0
0x41: SEQ_SDM2_STO
Type Description
RW Negative multiplication stop time 2
Field
7:0
Name
seq_adc
Rst
0
0x42: SEQ_ADC
Type
RW
Description
ADC sampling time
The ADC conversion needs to be finished before the sequencer period ends otherwise ADC samples can be lost.
The SEQ_ADC register defines the time when the ADC starts sampling during each measurement cycle.
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Detailed Description
Figure 57:
SEQ_ADC2TIA Register
Field Name
7:0 seq_adc2tia
Rst
0
0x43: SEQ_ADC2TIA
Type
RW
Description
ADC second sampling time for TIA: If this time is non-zero, an ADC conversion is started at the given cycle, but only if adc_sel is currently selecting TIA. For all other channels, there is only a single ADC conversion executed in the sequencer period.
Warning: If non-zero, seq_adc must be non-zero as well, and seq_adc2tia bigger than seq_adc. The difference must be high enough so that the second ADC conversion is started after the first ADC conversion has finished.
Also, if the seq_adc2tia features is used, there is the additional restriction that the second ADC conversion has to be finished before the end of the sequencer period.
Figure 58:
SEQ_ADC3TIA Register
Field Name
7:0 seq_adc3tia
Rst
0
0x44: SEQ_ADC3TIA
Type
RW
Description
ADC third sampling time for TIA: same as seq_adc2tia.
Also must make sure to not overlap ADC conversions!
Also, adc3tia must be after adc2tia
Figure 59:
SD_SUBS Register
Field
7:0
Name
sd_subs
Rst
0
0x45: SD_SUBS
Type
RW
Description
Synchronous demodulator subsampling ratio between sequencer frequency and ADC sampling frequency.
ADC-Fsample = Sequencyer_Frequency/(sd_subs+1)
When setting to 0, then in every sequencer iteration the
ADC will run.
When setting to 1, then the first sequencer iteration will not trigger the ADC, but the second one will.
Setting to N will make N iterations without ADC, followed by one iteration with the ADC measurement executed.
It is recommended to use the ADC interrupt in this case and not the sequencer interrupt.
Also see sd_subs_always which significantly affects this mechanism.
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[v1-04] 2018-Sep-11
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Detailed Description
Figure 60:
SEQ_CFG Register
Field
0
Name
sd_subs_ always
Rst
0
Figure 61:
SEQ_ERR Register
Field Name
7 irq_adc_ timing_error
Rst
0
0x47: SEQ_ERR
Type
SS_WC
Description
The ADC was started by the sequencer (or manually) while it was still converting. This does not flag an interrupt but when playing with the sequencer settings we suggest to check this flag to make sure that there is no problem with the sequencer programming
Figure 62:
CYC_COUNTER Register
0x46: SEQ_CFG
Type
RW
Description
If this bit is asserted, all sequencer periods are subject to subsampling as defined in SD_SUBS.
If this bit is zero, then only the first period of an "ADC cycle" is duplicated sd_subs times, all other periods are regular.
One "ADC cycle" is the time from the sequence in which adc_sel is pointing to the "smallest" adc channel up and including the sequence of the "largest" adc channel.
Field
7:0
Name
cycle_ counter
Rst
0
0x60: CYC_COUNTER
Type
RO
Description
Current cycle counter value
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Detailed Description
The SEQ_COUNTER register shows the current value of the sequence counter and period counter
Figure 63:
SEQ_COUNTER Register
Field
7:0
Name
sequence_ counter
Figure 64:
SUBS_COUNTER Register
Rst
0
Field
7:0
Name
subs_ counter
0x61: SEQ_COUNTER
Type
RO
Description
Current sequence counter value
Rst
0
0x62: SUBS_COUNTER
Type Description
RO Current subsampling counter value
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Optical Signal Conditioning
AS7024 −
Detailed Description
Figure 65:
Optical Signal Conditioning
from TIA aa_freq
200Hz gain_sd sd_clipdetect_h/l_thresh
Clip Det irq_clipdetect
Prefilter
Synchronous Demodulator1,2 + BP Filter + Gain Stages ofe1_en, ofe2_en ofe1/2_sd_byp ofe1/2_hp_byp ofe_gs_aa
* ofe1/2_sd_bw ofe1/2_hp_freq ofe1/2_hp_en ofe1/2
_gain_g
Clip Det
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ADC
FiFo
Synchronous Demodulator
Two optional synchronous demodulators can be used to detect small optical signals in the presence of large unwanted noise
(ambient light). Since the detector synchronizes to the LED frequency, the demodulator can only be used of the measurement sequencer is running.
It includes input filer (high pass at 200Hz, adjustable low pass) and an 2nd order adjustable output low pass. The demodulator itself multiplies the signal by +1 / 0 / -1 with a timing which is controlled by the sequencer.
Note(s):
The optical signal conditioning stage need sigref_ en=1 for operation.
High Pass Filter
Two optional high pass filter can be used to remove unwanted
DC-components from the signal and allows further amplification. In order to guarantee fast settling times of the filter, four cutoff frequencies can be chosen.
Gain Stage
Two optional gain stage can be used to amplify the signal after the DC-component has been removed.
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AS7024 −
Detailed Description
Optical Signal Conditioning Registers
Figure 66:
OFE_CFGA Register
Field
7
6
5
Name
ofe2_en ofe1_en en_bias_ofe
Rst
0
0
0
4:3
2:0 aa_freq gain_sd
0
0
0x50: OFE_CFGA
Type
RW
RW
RW
RW
RW
Description
Enable OFE2
Enable OFE1
Enable bias for OFE and TIA
Anti-aliasing filter cut-OFF frequency
Setting
0
1
2
Signal
10kHz
20kHz
40kHz
60kHz 3
SD gain
Setting
0
1
2
3
4
5
6
7
Nominal Gain
1
2
4
8
16
32
64 reserved
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AS7024 −
Detailed Description
Figure 67:
OFE_CFGB Register
Field Name
7:4 sd_ clipdetect_ h_thresh
3:0 sd_ clipdetect_ l_thresh
Rst
0
0
0x51: OFE_CFGB
Type
RW
RW
Description
If the voltage on the output of the gain_sd stage (input of synchronous demodulator) exceed this threshold the irq_ clipdetect interrupt is asserted. The threshold is defined as:
0 … 1824mV
1 … 1748mV
2 … 1672mV
3 … 1596mV
4 … 1520mV
5 … 1444mV
6 … 1368mV
7 … 1292mV
8 … 1216mV
9 … 1140mV
10 … 1064mV
11 … 988mV
12 … 912mV
13 … 836mV
14 … 760mV
15 … 684mV
If the voltage on the output of the gain_sd stage (input of synchronous demodulator) falls below this threshold the irq_clipdetect interrupt is asserted. The threshold is defined as:
0 … 67mV
1 … 143mV
2 … 219mV
3 … 295mV
4 … 371mV
5 … 447mV
6 … 523mV
7 … 599mV
8 … 675mV
9 … 751mV
10 … 827mV
11 … 903mV
12 … 979mV
13 … 1055mV
14 … 1131mV
15 … 1207mV
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Detailed Description
Figure 68:
OFE_CFGC Register
Field
6
5
4
3
2
1
0
Name
prefilter_aa_ byp prefilter_ hp_byp prefilter_ gain_byp prefilter_ bypass_en prefilter_aa_ en prefilter_ hp_en prefilter_ gain_en
Rst
0
0
0
0
0
0
0
Figure 69:
OFE_CFGD Register
Field Name
1:0 ofe_gs_aa
0x52: OFE_CFGC
Type
RW
RW
RW
RW
RW
RW
RW
Description
0 … Anti aliasing filter (aa_filter) is used
1 … Bypass anti aliasing filter
0 … Use 200Hz high pass filter
1 … Bypass 200Hz high pass filter
0 … Use gain_sd stage
1 … Bypass gain_sd stage
0 … Use prefilter unless any of the above register is set
1 … Bypass complete prefilter
0 … Anti aliasing filter (aa_filter) is OFF
1 … Anti aliasing filter is ON
0 … 200Hz high pass filter is OFF
1 … 200Hz high pass filter is ON
0 … gain_sd stage is OFF
1 … gain_sd stage is ON
Rst
0
0x53: OFE_CFGD
Type
RW
OFE anti aliasing
Setting
0
1
2
3
Description
Nominal Gain
Bypass fc=100Hz fc=300Hz fc=826Hz
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AS7024 −
Detailed Description
Figure 70:
OFE1_CFGA Register
Field
7
6
5
4
3
2
1
0
Name
ofe1_sd_pol_init ofe1_sd_en ofe1_hp_en ofe1_gain_en ofe1_sd_byp ofe1_hp_byp ofe1_gain_byp ofe1_sd_hld
0x54: OFE1_CFGA
Rst Type
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Description
The low level driver shall ensure that this register is 0 if one of the seq_sdm pulses is first, and is 1 if the seq_sdp is first within a sequence.
0 … Power down of the Synchronous demodulator
1 … Enable Synchronous demodulator
0 … Power down of the high pass filter
1 … Enable high pass filter
0 … Power down of the Gain stage
1 … Enable Gain stage
0 … Synchronous demodulator is used
1 … Synchronous demodulator is bypassed
0 … HP filter is used
1 … HP filter is bypassed
0 … Gain stage is used
1 … Gain stage is bypassed
SD hold
0 … Output of synchronous demodulator is forced to
SIGREF if not set to +1 or -1
1… Output of synchronous demodulator is tristated if not set to +1 or -1
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Detailed Description
Figure 71:
OFE1_CFGB Register
Field
6:4
3:2
Name
ofe1_gain_g ofe1_sd_bw
1:0 ofe1_hp_freq
Rst
0
0
0
0x55: OFE1_CFGB
Type
RW
RW
RW
Description
Gain
Setting Gain
1 0
1 2
4 2
3 8
16 4
5 32
64 6
7 Do not use
Synchronous demodulator low pass filter.
Setting
0
Frequency
10Hz
1
2
20Hz
40Hz
3
High pass filter cutoff frequency
80Hz
Setting
0
1
2
3
Cutoff Frequency
0.33Hz
1.32Hz
5.28Hz
10.56Hz
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AS7024 −
Detailed Description
Figure 72:
OFE2_CFGA Register
Field
7
6
5
4
3
2
1
0
Name
ofe2_sd_pol_init ofe2_sd_en ofe2_hp_en ofe2_gain_en ofe2_sd_byp ofe2_hp_byp ofe2_gain_byp ofe2_sd_hld
Rst
0
0
0
0
0
0
0
0
0x58: OFE2_CFGA
Type
RW
RW
RW
RW
RW
RW
RW
RW
Description
The low level driver shall ensure that this register is 0 if one of the seq_sdm pulses is first, and is 1 if the seq_sdp is first within a sequence.
0 … Power down of the synchronous demodulator
1 … Enable synchronous demodulator
0 … Power down of the high pass filter
1 … Enable high pass filter
0 … Power down of the Gain stage
1 … Enable Gain stage
0 … Synchronous demodulator is used
1 … Synchronous demodulator is bypassed
0 … HP filter is used
1 … HP filter is bypassed
0 … Gain stage is used
1 … Gain stage is bypassed
SD hold
0 … Output of synchronous demodulator is forced to
SIGREF if not set to +1 or -1
1 … Output of synchronous demodulator is tristated if not set to +1 or -1
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Detailed Description
Figure 73:
OFE2_CFGB Register
Field
6:4
3:2
1:0
Name
ofe2_gain_g ofe2_sd_bw ofe2_hp_freq
Rst
0
0
0
0x59: OFE2_CFGB
Type
RW
RW
RW
Description
Gain
Setting Gain
1 0
1 2
4 2
3 8
16 4
5 32
64 6
7 Do not use
Synchronous demodulator low pass filter.
Setting
0
Frequency
10Hz
1
2
20Hz
40Hz
3
High pass filter cutoff frequency
80Hz
Setting
0
1
2
3
Cutoff Frequency
0.33Hz
1.32Hz
5.28Hz
10.56Hz
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AS7024 −
Detailed Description
Figure 74:
Light-to-Frequency Mode Internal Circuit
Light-to-Frequency Mode
The LTF (light-to-frequency, or FM, frequency mode) mode.
1
2
3
4
A
B
I -> f conversion
Counter ltf_enable
Timer &
Capture
LTF 0
LTF 1 ltf_data0
16 bits ltf_data1
16 bits ltf_gain ltf0_sel, lft1_sel itime
Note: Do not use diodes which are connected to the TIA (register pd_a, pd_b, pd1...4) at the same time when ltf_en is enabled on the same diode
Note(s):
1. Do not use diodes which are connected to the TIA (register pd_a, pd_b, pd1...4) at the same time when Itf_en is enabled on the same diode.
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Detailed Description
Light-to-Frequency Mode Registers
Figure 75:
LTFDATA0_L Register
Field Name
7:0 ltfdata0[7:0]
Rst
0
Figure 76:
LTFDATA0_H Register
Field
7:0
Name
ltfdata0[15:8]
Rst
0
Figure 77:
LTFDATA1_L Register
0x21: LTFDATA0_H
Type
RO
Description
LTF result channel 0 high byte
Field Name
7:0 ltfdata1[7:0]
Rst
0
0x22: LTFDATA1_L
Type
RO
Description
LTF result channel 1 low byte. Software must make sure that the LTF integration is not running when accessing the LTFDATA registers. If buffering is required, consider using FIFO mode.
Figure 78:
LTFDATA1_H Register
0x20: LTFDATA0_L
Type
RO
Description
LTF result channel 0 low byte. Software must make sure that the LTF integration is not running when accessing the LTFDATA registers. These are the direct counter registers, they are not latched. If buffering is required, consider using FIFO mode.
Field
7:0
Name
ltfdata1[15:8]
Rst
0
0x23: LTFDATA1_H
Type
RO
Description
LTF result channel 1 high byte
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AS7024 −
Detailed Description
Figure 79:
ITIME Register
Field Name
7:0 itime
Rst
0
Type
RW
0x24: ITIME
Description
LTF integration time. MODCLK is 2/3MHz (666.67kHz).
One LSB of itime is 3.072ms (2048 MODCLK cycles).
0=3.072ms
...
255=786.432ms
Using the itime_unit register (see below), the unit of itime can be reduced by 2, 4, or 8. This shorter integration times can be selected (required for flicker detection), but it can also be used to increase the resolution of itime. For example, if 50ms integration time are desired, the best value for regular itime would be 15 (=16 periods=49.152ms). However, but setting itime_unit=2
(LSB=768
μ s), one can select 64 (=65 periods=49.9ms)
Warning: selecting an integration time smaller than
3.072ms will reduce the resolution of the conversion, as the maximum ltfdata value is not 1024 (10 bits) anymore, but 512 (9 bits) in case of 1.536ms integration time, 256 (8 bits) for 768
μ s and 128 (7 bits) for 384
μ s
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Detailed Description
Figure 80:
LTF_CONFIG Register
Field
7
1
0
Name
infinite_ itime
6
5:4 az_disable_ auto reserved ltf_fifo_ mode ltf_enable
Rst
0
0
0
0
0
0x25: LTF_CONFIG
Type
RW
RW
RW
RW
RW
Description
If this is asserted, then integration does not stop. The
ITIME setting is ignored. Use with watch the ltfdata counters. (Warning: must be filtered in software to prevent inconsistent upper/lower byte). It's implemented as a count disable on the integration counter, so when resetting bit to 0 again, the itime counter will continue and results can be read afterwards through the regular mechanisms (ltfdata or FIFO) This is intended for very long integration times - as the timing is controlled by software/I²C, accuracy fully depends on the system and
I²C master.
0: Run autozero on both channels every time FM mode is activated for the first time after ENAB is being asserted.
1: Do not run autozero automatically. Autozero can only be activated manually (AZ_CONTROL)
Reserved – leave at 0.
Run LTF integrations back to back, the LTF modulator is running continuously (the modulators are not reset between integrations cycles).
After each integration, the result gets written to the FIFO.
The FIFO is being filled automatically, FIFO threshold interrupt is flagged as configured.
The first item read from the FIFO is from channel 0, the next one from channel 1, etc.
Note that there is no ltf_done interrupt triggered after each integration. A FIFO threshold of 1 can be used to generate an interrupt for each result. irq_ltf_enab should be kept asserted to avoid missing an ltf_sat interrupt.
Do not enable ADC/sequencer FIFO mode and ltf_fifo_ mode at the same time, corrupted data would be the result.
Make sure to empty the FIFO in time, if the FIFO is full, new data is not being stored in the FIFO. Source of data read from the FIFO after an overflow condition is undefined (can be from channel 0 or channel 1)
Stop the procedure by clearing this bit.
This bit must be asserted for any LTF function (powers up the LTF clock tree)
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AS7024 −
Detailed Description
Figure 81:
LTF_SEL Register
Field Name
6:4
2:0 ltf1_sel ltf0_sel
Rst
2
0
RW
RW
0x26: LTF_SEL
Type Description
Select the sensor diode for LTF1
Setting Source
0
1
A
A/16
4
5
2
3
B
B/16
PD1
PD2
6
7
PD3
PD4
Select the sensor diode for LTF0
Setting Source
2
3
0
1
A
A/16
B
B/16
6
7
4
5
PD1
PD2
PD3
PD4
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Detailed Description
Figure 82:
LTF_GAIN Register
Field Name
5:4 itime_unit
3:0 ltf_gain
Rst
0
0
0x27: LTF_GAIN
Type
RW
RW
Description
Select the itime unit. See itime register description.
Setting Behavior
0
1
2
3
Normal, time LSB=3.072ms
/2, LSB=1.536ms
/4, time LSB=768
μ s
/8, time LSB=384
μ s
Select the gain
Setting Gain
0.25
0
1 0.5
1 2
3 2
4 4
5 8
16 6
7 32
64 8
9-15 Reserved – do not use
Figure 83:
LTF_CONTROL Register
Field
0
Name
ltf_start
Rst
0
0x28: LTF_CONTROL
Type
R_PUSH
Description
Writing 1 starts the counter, and it will run for the specified time (itime). Afterwards it stops automatically and interrupt is flagged.
writing 0 to the counter stops it as well.
reading the value returns whether the counter is running.
If ltf_fifo_mode is non-zero, then FM conversions are done continuously until a 0 is written to this bit again.
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Detailed Description
Figure 84:
AZ_CONTROL Register
Field
1
Name
az_enable_1
Rst
0
0x29: AZ_CONTROL
Type Description
RW_SM
Writing a '1' to this register starts the AZ engine for channel 1. This is usually not necessary, as AZ is executed automatically before the first LTF integration (unless az_ disable_auto is set) The bit is cleared to '0' automatically when the AZ has finished. You cannot write a '0' to this register.
RW_SM The same as az_enable_1, but for channel 0.
0 az_enable_0
Figure 85:
OFFSET0 Register
0
Field
7:0
Name
offset0[7:0]
Rst
0
0x2a: OFFSET0
Type
RW_SM
Description
This register holds the value of the offset on the channel 0
OpAmp. It can be overwritten, and it gets overwritten by the auto-zero mechanism. The value is in sign/magnitude encoding.
The value is ±127, sign/magnitude
Figure 86:
OFFSET1 Register
Field
7:0
Name
offset1[7:0]
Rst
0
0x2b: OFFSET1
Type
RW_SM
Description
This register holds the value of the offset on the channel 1
OpAmp. It can be overwritten, and it gets overwritten by the auto-zero mechanism. The value is in sign/magnitude encoding.
The value is ± 127, sign/magnitude
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Detailed Description
Electrical Analog Front End
The electrical analog front end consists of three identical signal paths with independent settings of bias condition, gain and offset.
Figure 87:
Electrical Analog Front End Internal Circuit
GPIO0
GPIO1
GPIO2
GPIO3
ECG_REF
SIGREF afe_enab_dac_buf dac1_value dac2_value
1.9V
DAC
1
0 sigref_on_dac_buf afe_enab_dac gpio_dac
T-gates:
50Ω gpio_r_bias
160kΩ
T-gates:
10kΩ
Note:
gpio_gst_in measure_dac
Resistor / T-gates resistance values are given as indication - don’t rely on absolute values
T-gates:
50kΩ afe_enab_gainstage on
Vref=1.6V
ADC
50kΩ
AGND
SIGREF don’t use
1
0
2
3 gst_ref
128kΩ gst_gain
0 … 1x
1 … 2x
AGND
2 … 4x
3 … 8x
4 … 16x
5 … 32x
6 … 64x
7 … don’t use
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AS7024 −
Detailed Description
DAC Switching
Figure 88:
Electrical Analog Front End DAC Level Switching
Example with dac_mode=1
V
DAC dac2_value dac1_value dac1_value sequencer seq_adc start period seq_adc
ADC convert start ADC convert start seq_adc t [not to scale]
ADC convert
If register dac_mode is not zero, the DAC switches its codes between dac1_value and dac2_value on the beginning of every/every 2nd/every 4th sequencer cycle where the ADC is converting the electrical frontend channel. ADC conversions of any other channel do not switch the DAC.
Input Pins
Four general purpose pins and ECG_REF can be used either as configurable GPIO pin or as analog input pins for the electrical analog front end. The analog inputs can be configured to setup different amplifier topologies.
EAF (Electrical Analog Frontend) Registers
Figure 89:
AFE_CFG Register
2
1
0
Field
3
Name
afe_enab afe_enab_ dac afe_enab_ dac_buf afe_enab_ gainstage
Rst
0
0
0
0
0x70: AFE_CFG
Type
RW
RW
RW
RW
Description
0 … EAF bias deactivated
1 … EAF bias activated (need to be set for any functions of the EAF are used).
0 … DAC inside the EAF OFF
1 … DAC inside the EAF ON
0 … DAC buffer ON
1 … DAC buffer OFF
0 … Gain stage in EAF OFF
1 … Gain stage in EAF ON
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Detailed Description
The AFE_CFG register is used to configure the analog frontend.
Figure 90:
EAF_GST Register
Field Name
7:5 gpio_gst_in
4:3
2:0 gst_ref gst_gain
Rst
0
0
0
0x80: EAF_GST
Type
RW
RW
RW
Description
5
6
7
3
4
1
2
Gain stage input selection
Setting
0
Meaning
Not connected
1
2
GPIO0
GPIO1
3
4
GPIO2
GPIO3
5
Gain stage reference voltage
ECG_REF
Setting
0
1
2
3
Gain stage gain
Setting
0
Meaning
AGND
DAC buffer
SIGREF
Reserved
Meaning
1
2
4
8
16
32
64
Reserved
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Detailed Description
The EAF register is used to configure the electrical frontend
Figure 91:
EAF_BIAS Register
Field
7:5
Name
gpio_r_bias
Rst
0
0x81: EAF_BIAS
Type
RW
Resistive biasing
Setting
0
1
4
5
2
3
Description
Meaning
No resistive biasing
Resistive biasing on GPIO0
Resistive biasing on GPIO1
Resistive biasing on GPIO2
Resistive biasing on GPIO3
Resistive biasing on ECG_REF
Figure 92:
EAF_DAC Register
Field
4
Name
sigref_on_dac_buf
Rst
0
3
2:0 measure_dac gpio_dac
0
0
0x82: EAF_DAC
Type
RW
RW
RW
Description
If asserted, connect SIGREF to DAC buffer.
If this bit is asserted, the DAC output is connected to the gain stage input (independent of gpio_gst_in selection, therefore the DAC output is measurable on the GPIO pin)
DAC on GPIO
Setting
0
1
Meaning
No DAC biasing
DAC on GPIO0
DAC on GPIO1
4
5
2
3 DAC on GPIO2
DAC on GPIO3
DAC on ECG_REF
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Detailed Description
Figure 93:
EAF_DAC1_L Register
Field
7:6
Name
dac1_ value[1:0]
Rst
0
0x83: EAF_DAC1_L
Type
RW DAC value 1 (2LSB)
Description
The EAF_DAC1/2_L/H registers is used to configure the dac value. See register dac_mode for selection of dac register 1 or 2.
Figure 94:
EAF_DAC1_H Register
Field
7:0
Name
dac1_ value[9:2]
Rst
0
0x84: EAF_DAC1_H
Type
RW
Description
DAC value 1 (upper 8 bits)
10 bit value:
0x000 … 0V
0x3FF … 1.9V
Figure 95:
EAF_DAC2_L Register
Field
7:6
Name
dac2_ value[1:0]
Figure 96:
EAF_DAC2_H Register
Rst
0
0x85: EAF_DAC2_L
Type
RW DAC value 2 (2LSB)
Description
Field
7:0
Name
dac2_ value[9:2]
Rst
0
0x86: EAF_DAC2_H
Type
RW
Description
DAC value 2 (upper 8 bits)
10 bit value:
0x000 … 0V
0x3FF … 1.9V
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Detailed Description
Figure 97:
EAF_DAC_CFG Register
Field Name
1:0 dac_mode
Rst
0
0x87: EAF_DAC_CFG
Type
RW
Description
DAC mode The EAF has a DAC that can be switched out on GPIOs.
dac_mode 0 uses statically dac1_value, the other modes switch dynamically between the two values.
The system switches from one value to the next always at the beginning of a sequence in which the ADC will sample the AFE channel.
Setting
0
Meaning
1-1-1-1-1-1-1-1-1-1-1-
1
2
3
1-2-1-2-1-2-1-2-1-2-1-
1-1-2-2-1-1-2-2-1-1-2-
1-1-1-1-2-2-2-2-1-1-1-
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Detailed Description
Possible Configurations of Every Amplifier Stage
Figure 98:
Non Inverting Amplifier with Offset and Input Voltage
Divider (Temperature Sensor) ams Datasheet
[v1-04] 2018-Sep-11
Figure 99:
Non Inverting Amplifier with Current Source and Offset
(Temperature Sensor)
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Detailed Description
Figure 100:
Non Inverting Amplifier with Current Source and Reference
Path (Temperature Sensor)
Figure 101:
Non Inverting Amplifier High Impedance, GND Referenced
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Detailed Description
Figure 102:
Non Inverting Amplifier with DC-Blocking, Referenced to
V_ADCRef/2 ams Datasheet
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Figure 103:
Non Inverting Amplifier with DC-Blocking and Fast Settling
Time, Referenced to ADCRef /2
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Detailed Description
ECG Amplifier
Figure 104:
ECG Amplifier Internal Circuit
2x10MΩ
ECG_REF
1µF
SIGREF
ECG_INP ecg_low_leakage_en for diode leakage reduction on ECG_INP and ECG_INN
Leads off detect ecg_ref_en to electrical frontend
SIGREF ecg_lp ecg_lp_en ecg_en
Instrumentation amplifier gain=5 ecg_lp_byp ecg_hp_byp ecg_gain_byp ecg_hp_freq ecg_hp_en ecg_gain_g ecg_gain_en
The ECG (electro cardiogram) amplifier is a high impedance, low noise instrumentation amplifier with analog circuitry to bandpass filter the signal and amplify it before converting it with the ADC.
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Detailed Description
Figure 105:
ECG Lead OFF Detection Internal Circuit
ECG Lead OFF Detection
ECG_INP ecg_leadsdet_curr
20nA/100nA/500nA/1μA on ecg_leadsdet_en ecg_low_leakage_en to ADC channel ecgi ecg_leadsdet_sync_adc updates ecg_leadsdet_pol
2x10MΩ
ECG_REF
GND ecg_leadsdet_en
If ecg_leaddet_sync_adc is set, the leads detect current is reversed by toggling ecg_leadset_pol on every start of a sequencer period, where an ADC conversion of ECG_INP is performed.
This concept allows the measurement of the connected resistor and capacitor between the electrodes.
ecg_leadsdet_sync_adc=1
I
ECG_INP
V
ECG_INP seq_adc sequencer start period ADC convert start seq_adc
ADC convert start seq_adc
ADC convert
The ECG lead OFF detection can be used for detection if the user actually touches the leads. It is a circuitry to measure the capacitor and/or resistance between the two lead inputs ECG_
INP and ECG_INN.
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Detailed Description
ECG Registers
Figure 106:
ECG_CFGA Register
2
1
4
3
0
Field
7
6
5
Name
ecg_en not used ecg_lp_en ecg_hp_en ecg_gain_ en ecg_lp_byp ecg_hp_byp ecg_gain_ byp
Rst
0
NA
0
0
0
0
0
0
0x5c: ECG_CFGA
Type
RW
NA
RW
RW
RW
RW
RW
RW
Description
Enable ECG instrumentation amplifier
Do not rely on the content of this register
0 … LP filter disabled
1 … LP filter enabled
0 … Power down of the high pass filter
1 … Enable high pass filter
0 … Power down of the Gain stage
1 … Enable Gain stage
0 … LP stage is used
1 … LP stage is bypassed
0 … HP filter is used
1 … HP filter is bypassed
0 … Gain stage is used
1 … Gain stage is bypassed
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Detailed Description
Figure 107:
ECG_CFGB Register
Field Name
6:5 ecg_lp_freq
2:0 ecg_gain_g
Rst
0
4:3 ecg_hp_freq 0
0
0x5d: ECG_CFGB
Type
RW
RW
RW
Description
Gain
Setting
0
1
4
5
2
3
6
7
ECG low pass filter.
Setting
0
1
2
3
Frequency
40Hz
80Hz
160Hz
320Hz
High pass filter cutoff frequency
Setting Filter Frequency Cutoff Frequency
2
3
0
1
122Hz
488Hz
1953Hz
3906Hz
0.33Hz
1.32Hz
5.28Hz
10.56Hz
Gain
1
2
4
8
16
32
64
128
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Detailed Description
Figure 108:
ECG_CFGC Register
Field
1
0
Name
ecg_low_ leakage_en ecg_ref_en
Rst
0
0
0x5e: ECG_CFGC
Type
RW
RW
Description
Enable ECG leakage compensation
ECG Reference Feedback Amplifier Enable
Figure 109:
ECG_CFGD Register
Field
4
3
2:1
0
Name
ecg_leadsdet_ sync_adc ecg_leadsdet_pol ecg_leadsdet_curr ecg_leadsdet_en
Rst
0
0
0
0
0x5f: ECG_CFGD
Type
RW
RW_SM
RW
RW
Description
ECG Leads Detection Automatic Update. If this is asserted, then ecg_leadsdet_pol is inverted automatically at the start of a sequence (at count=2) if in this sequence the ADC will convert the ECGi channel.
ECG Leads Detection Polarity. Can be written to manually if ecg_leadsdet_sync_adc is clear, otherwise it is automatically toggled.
ECG Leads Detection Current
Setting Current
0
1
20nA
100nA
2
3
ECG Leads Detection Enable
500nA
1μA
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Detailed Description
Figure 110:
ADC Internal Circuit and Multiplexer
ADC and FIFO
The ADC is a 14bit successive-approximation register (SAR) type. It supports 14bit with conversion time up to 50ksps.
The ADC is started by the sequencer and its timing or in manual mode (man_mode=1) by setting seq_start=1 (seq_start stays
‘1’ as long as the conversion runs). The AS7024 can be configured to trigger an interrupt upon end of conversion.
Start from top and cycle through channels where adc_channel_mask_...=1 (first channel selected seq_start 0->1)
Pre-
Filter adc_channel_mask_tia adc_channel_mask_ofe1/ sd1/ofe2/sd2
OFE
TIA adc_channel_mask_temp vtemp
GPIOs
ECG_
REF
4
Electrical
Frontend
GPIO3
GPIO2 adc_channel_mask_afe adc_channel_mask_pregain adc_channel_mask_ecgo from ECG adc_channel_mask_ecgi adc_channel_mask_gpio3 adc_channel_mask_gpio2
V_LDO
Vref=1.6V
ADC
ADC_DATAH/L
AGND
FiFo
64x16 bit entries
For best accuracy, the ADC can be optionally calibrated.
Note(s):
If GPIO2 or GPIO3 is used as ADC input, there is no anti-aliasing filter in front of the ADC (needs to be added externally).
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Detailed Description
ADC Threshold
At the output of the ADC converter a digital threshold can be enabled. If the output of the ADC exceeds the threshold adc_threshold, it triggers an interrupt. This mechanism can be used to identify if an object is in proximity of the sensor and then to interrupt the host. In cases where no object is detected, the host can be sleeping therefore reducing power consumption of the system.
For detailed description of the threshold calculation see the register ADC_THRESHOLD and ADC_THRESHOLD_CFG description.
ADC Registers
Figure 111:
ADC_THRESHOLD Register
Field
7:0
Name
adc_threshold
Rst
0xff
0x68: ADC_THRESHOLD
Type Description
RW
If the ADC returns a value above adc_threshold (not equal), then the adc_threshold interrupt can be triggered. Note that when comparing, only the upper 8 bits are compared, the lower 6 bits are ignored. A value of 0xff can therefore never trigger the interrupt.
Figure 112:
ADC_THRESHOLD_CFG Register
Field
1
0
Name
adc_thresh_ differential adc_thresh_ tiaonly
Rst
0x69: ADC_THRESHOLD_CFG
Type Description
0
0
RW
RW
If adc_thresh_tiaonly is asserted and any of seq_adc[23]tia is non-zero, meaning that there are two or three ADC TIA measurements in one sequencer period, then the second is subtracted from the first, and the
difference
is being compared to the adc_threshold.
Normally, the adc_threshold works regardless of the adc channel.
If this bit is set, then the threshold is only checked if the adc channel is TIA.
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Figure 113:
ADC_CFGA Register
Field
3:1
0
Name
adc_multi_n adc_multimode
Rst
0
0
0x88: ADC_CFGA
Type
RW
RW
Description
Defines number of samples that are taken in multimode
(adc_multimode =1)
Setting
Number of Samples per ADC
Conversion Command
2
3
0
1
2
4
8
16
6
7
4
5
32
48
64
96
0 … If ADC is started one sample is measured
1 … If ADC is started multiple samples are stored in sequence in the FIFO. The number of samples is defined with "adc_multi_n".
Note(s):
1. If the ADC is triggered with the sequencer, the very first ADC conversion after seq_en=1 stores the number of samples according to above table. All subsequent samples use one sample less (e.g. 7 instead of 8).
The ADC_CFGA,B,C register is used to configure the ADC operation.
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Detailed Description
Figure 114:
ADC_CFGB Register
Field
5:3
2
1
0
Name
adc_clock adc_calibration ulp adc_en
Rst
0
0
0
0
0x89: ADC_CFGB
Type
RW
RW
RW
RW
Description
ADC clock divider: The ADC clock is freely configurable.
Setting Periods μs kHz
0
1
2
4
1
2
1000
500
4
5
2
3
6
8
10
12
3
4
5
6
333
250
200
167
6
7
14
16
7
8
143
125
To activate the optional self calibration, this bit must be asserted, and an ADC “conversion” has to be started in manual mode (man_mode=1) by asserting seq_start.
Ultra low power bit for the sequencer. If this bit is set and sd_subs>0, it disables the LED pulses and powers off the
TIA in all sequences but the one where the TIA is sampled.
0 … Reset ADC
1 … Enable ADC
Warning: In reset state the ADC clears its calibration data.
Re-calibration is necessary next time it is enabled again.
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Detailed Description
Figure 115:
ADC_CFGC Register
Field
4
3
2:0
Name
adc_selfpd adc_discharge adc_settling_ time
Rst
1
1
0
0x8a: ADC_CFGC
Type
RW
RW
RW
Description
4
5
2
3
6
7
1 … Power down the ADC when not converting; use this to conserve power, but set adc_settling_time to minimum
64us to permit settling of the ADC reference buffer.
0 … Always enable ADC
0: Suppress ADC capacitor discharging – use with caution
1: Discharge ADC capacitor before tracking
If asserted, the capacitor is discharged before the tracking phase. If zero, the discharge phase is suppressed and the tracking phase is started one cycle earlier.
ADC settling time: Use with synchronous demodulator. It defines the number of ADC clock cycles the sampling window is kept open additionally.
If the gain stage in the optical frontend is used (gain_ byp=0), set this to minimum 8
μ s. If adc_selfpd=1, set this to minimum 64
μ s.
Setting Periods
μs
(@500kHz)
μs
(@250kHz)
0
1
0
4
0
8
0
16
8
16
32
64
128
256
16
32
64
128
256
512
32
64
128
256
512
1ms
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Detailed Description
Figure 116:
ADC_CHANNEL_MASK_L Register
Field
7
6
5
4
3
2
1
0
Name
adc_channel_ mask_pregain adc_channel_ mask_afe adc_channel_ mask_temp adc_channel_ mask_sd2 adc_channel_ mask_ofe2 adc_channel_ mask_sd1 adc_channel_ mask_ofe1 adc_channel_ mask_tia
0x8b: ADC_CHANNEL_MASK_L
Rst Type Description
0 RW Pregain channel selection
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Electrical front end
Temperature measurement
Synchronous modulator 2 output just before the gain stage
Synchronous modulator 2 output after the gain stage
Synchronous modulator 1 output just before the gain stage
Synchronous modulator 1 output after the gain stage
Transimpedance amplifier output
The adc channel is chosen automatically from the bits within the adc_channel_mask_* set. It starts from right and finishes left (LSB->MSB) and wraps back from the most significant asserted bit to the least significant of the asserted bits. After every ADC conversion it switches to the next enabled channel,
(except around the adc2tia/adc3tia cases). See register description FIFOH and FIFOL for encoding of the first channel in the data stream.
This applies to both, manual mode and sequencer mode. In sequencer mode, it starts with the smallest channel when the sequencer is being started. In manual mode, the adc_sel is reset with every write to either ADC_CHANNEL_MASK_L or
ADC_CHANNEL_MASK_H
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Detailed Description
Figure 117:
ADC_CHANNEL_MASK_H Register
Field
3
2
1
0
Name
adc_channel_ mask_gpio2 adc_channel_ mask_gpio3 adc_channel_ mask_ecgi adc_channel_ mask_ecgo
Rst
0x8c: ADC_CHANNEL_MASK_H
Type Description
0
0
RW
RW
GPIO2 input – set gpio2_a=1 and
Write 0x47 to register 0xC6
Write 0x0C to register 0xC2
Write 0x0C to register 0xC3
GPIO3 input – set gpio3_a=1 and
Write 0x47 to register 0xC6
Write 0x0C to register 0xC2
Write 0x0C to register 0xC3
0 RW ECG amplifier input – use for leads off detection
0 RW ECG amplifier output – amplified ECG signal
Figure 118:
ADC_DATA_L Register
Field
7:0
Name
adc_data[7:0]
Rst
0
0x8e: ADC_DATA_L
Type
RO
Description
Current ADC output: low byte.
The ADC_DATA register shows the current raw output of the
ADC
Figure 119:
ADC_DATA_H Register
Field
5:0
Name
adc_data[13:8]
Rst
0
0x8f: ADC_DATA_H
Type
RO
Description
Current ADC output: high byte warning: there is no latch mechanism implemented to guarantee consistency if the
ADC is possibly running when reading this register, then the data can be corrupted - use the FIFO to guarantee data consistency.
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Detailed Description
FIFO Registers
Figure 120:
FIFO_CFG Register
Field
5:0
Name
fifo_threshold
Rst
19 RW
0x78: FIFO_CFG
Type Description
FIFO threshold. The fifo_threshold interrupt is flagged if there are more than this many entries in the FIFO.
0 … Interrupt with 1 (16bit) entry in FIFO
63 … Interrupt when FIFO is full but one; note that the
FIFO is 64 entries deep
Figure 121:
FIFO_CNTRL Register
Field
0
Name
fifo_clear
Rst
0
0x79: FIFO_CNTRL
Type
PUSH1
Description
Write a 1 here to clear the FIFO can be useful when switching from one sequencer mode to another to make sure that there are no old FIFO entries left
Figure 122:
FIFOSTATUS Register
Field
7
6:0
Name
fifooverflow fifolevel
Rst
0
0
0xa3: FIFOSTATUS
Type
RO
RO
Description
FIFO overflow indicator
FIFO fill level (0 …64)
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Figure 123:
FIFOL Register
Field
7:0
Name
fifol
Rst
0
0xfe: FIFOL
Type
PUSHPOP Low byte of FIFO
Description
FIFOL can be read out with single reads (2 consecutive I²C addresses have to be read to get one FIFO entry) or with block-read (up to 2 x fifo_depth values can be read in a single block-read)
Upon reading of FIFOH, it automatically advances the internal read pointer and decreases FIFO level.
If reading beyond end of FIFO, data will return 00h. There is no underrun flag, this is not an error condition.
Use ams SDK functions to read from the FIFO register to keep the reading in synchronization with the ADC channel selection.
If synchronization is no concern use [fifoh[7:0] : fifol[7:2]] as ADC result as the ADC data is multiplied by x4 before it is pushed in to the FIFO. FIFOl[0] is used as an ADC first channel indication.
The first channel indication bit toggles upon every new entry unless the first ADC channel is transmitted. Then toggling can be stopped for up to 5 FIFO entries and the very first stopping indicates the first ADC channel. To allow encoding of any number of ADC channels, the first ADC channel encoding is dropped from time to time.
Figure 124:
FIFOH Register
Field
7:0
Name
fifoh
Rst
0
0xff: FIFOH
Type
PUSHPOP High byte of FIFO
Description
See
Interrupts for the actual FIFO interrupt.
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Figure 125:
GPIO Internal Circuit
GPIO0...3
VDD gpio_o enabled if gpio_e=1 gpio_i enabled if gpio_a=0 to analog
GND pullup/pulldown controlled by gpio_p
AS7024 −
Detailed Description
Digital Interface
Power Management
After setting the pin ENABLE=1 the AS7024 registers can be accessed by the I²C interface. Before enabling any additional function (current source, TIA, ADC…) set the bit ldo_en=1 to set the internal LDO to normal mode.
For operating the ADC or the sequencer enable the oscillator by setting osc_en=1.
GPIO Pins
Each of the GPIO pins can be digitally controlled and is capable of adding a pullup and/or pulldown:
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Interrupts
An interrupt output pin INT can be used to interrupt the host.
Following interrupt sources are possible
irq_adc:
End of ADC conversion
irq_sequencer:
End of sequencer sequence reached.
irq_ltf:
A light-to-frequency conversion is finished.
irq_adc_threshold:
ADC threshold triggered – see
.
irq_fifothreshold:
FIFO almost full (as defined in register fifo_threshold)
irq_fifooverflow:
FIFO overflow (error condition, data is lost)
irq_clipdetect:
TIA output and/or SD output exceeded threshold– see details in CLIPSTATUS
irq_led_supply_low:
led supply low comparator triggered – see details in LEDSTATUS
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AS7024 −
Detailed Description
Depending on the setting in register INTENAB each of the above interrupt source can assert INT output pin (active low).
I²C
The AS7024 includes an I²C slave using an I²C address of 0x30
(7-bit format; R/W bit has to be added) respectively 60h (8-bit format for writing) and 61h (8-bit format for reading). It expects external pullup resistors.
I²C Serial Control Interface
I²C Feature List
Fast mode (400kHz) and standard mode (100kHz) support
7+1-bit addressing mode
Write formats: Single-Byte-Write, Page-Write
Read formats: Current-Address-Read, Random-Read,
Sequential-Read
SDA input delay and SCL spike filtering by integrated
RC-components
I²C Protocol
Figure 126:
I²C Symbol Definition
Symbol
S
Sr
DW
DR
WA
A
N reg_data data (n)
P
WA++
Definition
Start condition after stop
Repeated start
Device address for write
Device address for read
Word address
Acknowledge
No Acknowledge
Register data/write
Register data/read
Stop condition
Increment word address internally
I²C Symbol Definition:
Shows the symbols used in the following mode descriptions.
RW
R
R
R
W
R
R
R
R
W
R
R
Note
1 bit
1 bit
0110 0000b (60h)
0110 0001b (61h)
8 bit
1 bit
1 bit
8 bit
8 bit
1 bit
During acknowledge
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Detailed Description
I²C Write Access
Byte Write and Page Write formats are used to write data to the slave.
Figure 127:
I²C Byte Write
S DW A WA A reg_data A P write register
WA++
I²C Byte Write:
Shows the format of an I²C byte write access.
Figure 128:
I²C Page Write
S DW A WA A reg_data 1 A reg_data 2 A write register
WA++ write register
WA++
...
reg_data n A P write register
WA++
I²C Page Write:
Shows the format of an I²C page write access.
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated
START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally.
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Detailed Description
I²C Read Access
Random, Sequential and Current Address Read are used to read data from the slave.
Figure 129:
I²C Random Read
S DW A WA A Sr DR A read register
WA++ data N P
WA++
I²C Random Read:
Shows the format of an I²C random read access.
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
Figure 130:
I²C Sequential Read
S DW A WA A Sr DR A read register
WA++ data N P
WA++
I²C Sequential Read:
Shows the format of an I²C sequential read access.
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Detailed Description
Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
Figure 131:
I²C Current Address Read
S DW A WA A Sr DR A read register
WA++ data N P
WA++
I²C Current Address Read:
Shows the format of an I²C current address read access.
To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to
Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to
Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition.
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Detailed Description
Power, GPIO, ID and Interrupt Registers
Figure 132:
CONTROL Register
Field
1
0
Name
osc_en ldo_en
Rst
0
0
RW
RW
0x00: CONTROL
Type Description
Enable the oscillator. The oscillator must be enabled for any analog block (ADC, sequencer, optical frontend, sequencer); not mandatory for current sinks or ECG amplfier
If the EN input is not asserted, the chip is in reset If asserted, I²C transactions are possible. Upon assertion of ldo_en, the reference and the LDO are enabled The LDO must be enabled for anything but plain I²C register read/write
Figure 133:
GPIO_A Register
Field
3
2
1
0
Name
gpio3_a gpio2_a gpio1_a gpio0_a
Rst
0
0
0
0
Type
RW
RW
RW
RW
0x08: GPIO_A
Description
1=Put GPIO3 in analog mode; set this bit when used for an analog function e.g. the electrical frontend.
If set execute following I²C commands (otherwise an internal pulldown will be enabled) in this sequence:
Write 0x47 to register 0xC6
Write 0x0C to register 0xC2
Write 0x0C to register 0xC3
1=Put GPIO2 in analog mode
If set execute following I²C commands (otherwise an internal pulldown will be enabled) in this sequence:
Write 0x47 to register 0xC6
Write 0x0C to register 0xC2
Write 0x0C to register 0xC3
Note(s):
1. No further I²C commands are required (different to GPIO2/3).
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Detailed Description
Figure 134:
GPIO_E Register
Field
1
0
3
2
Figure 135:
GPIO_O Register
Name
gpio3_e gpio2_e gpio1_e gpio0_e
Rst
0
0
0
0
Type
RW
RW
RW
RW
0x09: GPIO_E
Description
GPIO3 output enabled if set
GPIO2 output enabled if set
GPIO1 output enabled if set
GPIO0 output enabled if set
Field
1
0
3
2
Figure 136:
GPIO_I Register
Name
gpio3_o gpio2_o gpio1_o gpio0_o
Rst
0
0
0
0
RW
RW
RW
RW
Type
0x0a: GPIO_O
Description
If gpio3_e=1, gpio3_o defines the output state of GPIO3
If gpio2_e=1, gpio2_o defines the output state of GPIO2
If gpio1_e=1, gpio1_o defines the output state of GPIO1
If gpio0_e=1, gpio0_o defines the output state of GPIO0
Field
1
0
3
2
Name
gpio3_i gpio2_i gpio1_i gpio0_i
Rst
0
0
0
0
Type
RO
RO
RO
RO
0x0b: GPIO_I
Description
The digital value sensed on GPIO3
The digital value sensed on GPIO2
The digital value sensed on GPIO1
The digital value sensed on GPIO0
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Detailed Description
Figure 137:
GPIO_P Register
Field
3
2
1
0
Field
7
Name
gpio3_pd
6
3
2
5
4
1
0 gpio3_pu gpio2_pd gpio2_pu gpio1_pd gpio1_pu gpio0_pd gpio0_pu
Figure 138:
GPIO_SR Register
0
0
0
0
0
0
Rst
0
0
RW
RW
RW
RW
RW
RW
Type
RW
RW
0x0c: GPIO_P
Description
GPIO3 pulldown configuration
0: No pulldown on GPIO3
1: Pulldown to GND on GPIO3
GPIO3 pullup configuration
0: No pullup on GPIO3
1: Pullup to VDD on GPIO3
GPIO2 pulldown configuration
GPIO2 pullup configuration
GPIO1 pulldown configuration
GPIO1 pullup configuration
GPIO0 pulldown configuration
GPIO0 pullup configuration
Name
gpio3_sr gpio2_sr gpio1_sr gpio0_sr
0
0
0
Rst
0
Type
RW
RW
RW
RW
0x0d: GPIO_SR
Description
GPIO3 slew rate configuration
0: Default slew rate
1: Increased slew rate
GPIO2 slew rate configuration
GPIO1 slew rate configuration
GPIO0 slew rate configuration
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Detailed Description
Figure 139:
SUBID Register
Field
7:3
2:0
Name
subid
Revision
Rst
NA
NA
Type
RO
RO
0x91: SUBID
Description
Defines product version. Do not rely on bits defined as ‘X’.
1XXXXb
Reserved. Do no use and do not rely that the content stays the same for each device.
Internal information: At least one bit is set on subid.
Figure 140:
ID Register
Field
7:2
1:0
Name
id id_reserved
Rst
0
0
Type
RO
RO
0x92: ID
Description
Part Number Identification.
Value Meaning
AS7024 110011
Reserved. Do no use and do not rely that the content stays the same for each device.
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Detailed Description
Figure 141:
STATUS Register
Type
0xa0: STATUS
6
5
4
2
1
0
Field
7
3
Name
irq_led_supply_ low irq_clipdetect irq_fifooverflow irq_fifothreshold irq_adc_ threshold irq_ltf irq_sequencer irq_adc
Rst
0
0
0
0
0
0
0
0
R_PUSH1 Check LEDSTATUS
Description
R_PUSH1 Check CLIPSTATUS
R_PUSH1 FIFO overflow (error condition, new data is lost)
R_PUSH1 FIFO is almost full (as defined in fifo_threshold, usually 3/4)
R_PUSH1
The ADC value was above the programmed adc_threshold register setting
R_PUSH1 LTF measurement is done. check LTFSTATUS (or ignore it)
R_PUSH1 All configured sequencer iterations have finished
R_PUSH1 ADC has finished
The STATUS register shows the current state of the interface.
Some bits in here can trigger an interrupt.
An asserted bit can be cleared by writing a '1' to it - in case of irq_led_supply_low and irq_clipdetect, this also clears the underlying condition in the CLIPSTATUS and LEDSTATUS registers.
The FIFO threshold interrupt cannot be cleared directly, but only by lowering the FIFO level. The FIFO overflow interrupt is sticky and must be cleared explicitly.
Figure 142:
CLIPSTATUS Register
Field
3
Name
pd_clipdetect_l
Rst
0
2
1
0 pd_clipdetect_h sd_clipdetect_l sd_clipdetect_h
0
0
0
0xa1: CLIPSTATUS
Type
RO
RO
RO
RO
Description
If this bit is asserted, photo diode amplifer has been below the lower threshold
If this bit is asserted, photo diode amplifer has been above the upper threshold
If this bit is asserted, photo diode amplifer has been below the lower threshold
If this bit is asserted, photo diode amplifer has been above the upper threshold
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Detailed Description
An asserted bit can be cleared by writing a '1' to the irq_ clipdetect.
Figure 143:
LEDSTATUS Register
Field
1
0
3
2
Name
led4_supply_low led3_supply_low led2_supply_low led1_supply_low
Rst
0
0
0
0
RO
RO
RO
RO
0xa2: LEDSTATUS
Type Description
If this bit is asserted, LED4 voltage has been too low.
If this bit is asserted, LED3 voltage has been too low.
If this bit is asserted, LED2 voltage has been too low.
If this bit is asserted, LED1 voltage has been too low.
An asserted bit can be cleared by writing a '1' to the irq_led_ supply_low bit.
Figure 144:
INTENAB Register
Field
7
6
5
4
3
2
1
0
Name
irq_led_supply_ low_enab irq_clipdetect_ enab irq_fifooverflow_ enab irq_ fifothreshold_ enab irq_adc_ threshold_enab irq_ltf_enab irq_sequencer_ enab irq_adc_enab
Rst
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Type
RW
0xa8: INTENAB
Description
1 … Enable led supply low interrupt
1 … Enable clipdetect interrupt
1 … Enable fifooverflow interrupt
1 … Enable fifothreshold interrupt
1 … Enable irq_adc_threshold as an interrupt source
1 … Enable LTF as an interrupt source
1 … Enable irq_sequencer as an interrupt source
1 … Enable irq_adc as an interrupt source
Each of the STATUS register bits can cause an interrupt (register
INTR) if the respective bit is asserted in the INTENAB register.
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Detailed Description
Figure 145:
INTR Register
Field
7
6
5
4
3
2
1
0
Name
irq_led_supply_ low_intr irq_clipdetect_ intr irq_fifooverflow_ intr irq_ fifothreshold_intr irq_adc_ threshold_intr irq_ltf_intr irq_sequencer_ intr irq_adc_intr
Rst
0
0
0
0
0
0
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
0xa9: INTR
Description
The INTR registers shows the bit or bits that are responsible for an asserted interrupt. Effectively, these bits are OR-ed together to drive the interrupt pin INT low (open drain output).
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AS7024 −
Application Information
Application Information
The following figure shows the complete integration of the
AS7024 in a mobile optical measurement system for HRM, SpO2,
GSR (galvanic skin resistivity) and skin temperature using an
NTC.
The device can be powered directly by a LiIon battery as it has its own power management. Nevertheless the I²C interface can be powered by 1.8V circuitry.
Figure 146:
Optical HRM Measurement System for Wrist-Based Application
LED Supply
VD1
VBAT
ECG_INP
ECG_INN
ECG_REF
SDA
SCL
INT
VDD
V_LDO
GND
LDO
Optical barrier
I2C, Optical &
Electrical
Frontend,
ECG Amp.
Ref
VD4
VBAT
VDD
ENABLE
GPIO3
GPIO2
GPIO1
GPIO0
ON=0,OFF=1
NTC
SIGREF
AGND connect
VD3 unused current sinks to GND
AS7024
VD2
LED
Supply
VBAT
Accelerometer
Host
Processor to ENABLE for on/off
PMIC
+Charger
VBAT
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Package Drawings & Markings
Package Drawings & Markings
Figure 147:
Package Drawing
RoHS
Green
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AS7024 −
Ordering & Contac t Information
Ordering & Contact Information
Figure 148:
Ordering Information
Ordering Code
AS7024-AB
Type
AS7024
Marking
NA
Delivery Form Delivery Quantity
Tape and Reel 5000 pcs/reel
Buy our products or get free samples online at: www.ams.com/Products
Technical Support is available at: www.ams.com/Technical-Support
Provide feedback about this document at: www.ams.com/Document-Feedback
For further information and requests, e-mail us at: [email protected]
For sales offices, distributors and representatives, please visit: www.ams.com/Contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS:
The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br):
ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information:
The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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Copyrights & Disclaimer
AS7024 −
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
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Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Product Status
Pre-Development
Pre-Production
Production
Discontinued
Definition
Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice
Information in this datasheet is based on products in the design, validation or qualification phase of development.
The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice
Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade
Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and should not be used for new designs
ams Datasheet
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Revision Information
Revision Information
Changes from 1-03 (2017-Sep-27) to current revision 1-04 (2018-Sep-11)
Removed “Confidential” from footer
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Page
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Content Guide
Content Guide
ams Datasheet
[v1-04] 2018-Sep-11
1 General Description
1 Key Benefits and Features
2 Applications
3 Pin Assignments
5 Absolute Maximum Ratings
7 Electrical Characteristics
14 Detailed Description
14 Optical Analog Front End
16 LED Configuration Registers
25 Photodiode Registers
29 Photodiode Trans-Impedance Amplifier (TIA)
31 Photodiode TIA Registers
33 Voltage Mode of the Photodiode Amplifier
34 Optical Front End Operating Modes
34 Manual Operation of the Optical Frontend:
46 Optical Signal Conditioning
47 Optical Signal Conditioning Registers
54 Light-to-Frequency Mode
55 Light-to-Frequency Mode Registers
61 Electrical Analog Front End
62 EAF (Electrical Analog Frontend) Registers
67 Possible Configurations of Every Amplifier Stage
70 ECG Amplifier
75 ADC and FIFO
76 ADC Threshold
84 Digital Interface
86 I²C Write Access
87 I²C Read Access
89 Power, GPIO, ID and Interrupt Registers
96 Application Information
97 Package Drawings & Markings
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Content Guide
98 Ordering & Contact Information
99 RoHS Compliant & ams Green Statement
100 Copyrights & Disclaimer
101 Document Status
102 Revision Information
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