AMS AS7341 Light Sensor Datasheet
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Datasheet
DS000504
AS7341
11-Channel Multi-Spectral Digital Sensor
v3-00
• 2020-Jun-25
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AS7341
Content Guide
Content Guide
General Description ....................... 3
Key Benefits & Features .............................. 3
Applications .................................................. 4
Block Diagram .............................................. 4
Ordering Information ..................... 5
Pin Assignment ............................. 6
Pin Diagram .................................................. 6
Pin Description ............................................. 6
Absolute Maximum Ratings .......... 7
Electrical Characteristics .............. 8
Optical Characteristics .................. 9
Characteristics ............................. 16
Functional Description ................ 17
Channel Architecture .................................. 18
Sensor Array .............................................. 19
GPIO/INT .................................................... 19
SMUX ......................................................... 19
Integration Mode ........................................ 20
I²C Interface .................................. 22
I²C Address ................................................ 22
I²C Write Transaction ................................. 22
I²C Read Transaction ................................. 23
Timing Characteristics ............................... 23
Timing Diagrams ........................................ 24
10 Register Description ................... 25
Register Overview ...................................... 25
Detailed Register Description .................... 27
11 Application Information .............. 59
Schematic .................................................. 59
PCB Pad Layout......................................... 60
Application Optical Requirements .............. 61
12 Package Drawings & Markings ... 62
Tape & Reel Information ............. 63
14 Soldering & Storage Information 65
Storage Information ................................... 66
15 Revision Information ................... 67
Legal Information ........................ 68
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AS7341
General Description
1 General Description
The ams AS7341 is an 11-channel spectrometer enabling new consumer, commercial and laboratory applications including spectral identification, reflection and absorption for color matching, fluid or reagent analysis, passive ambient light measurement and color calibration. The spectral response is defined by individual channels covering approximately 350nm to 1000nm with 8 channels centered in the visible spectrum (VIS), plus one near-infrared (NIR) and a clear channel. The NIR channel in combination with the other VIS channels may provide information of surrounding ambient light conditions, including light source detection. Light source detection can be assisted by an integrated flicker channel that can automatically flag ambient light flicker at 50/60Hz as well as buffer data for externally calculating other flicker frequencies up to 2kHz.
AS7341 integrates high-precision optical filters onto standard CMOS silicon via nano-optic deposited interference filter technology. A built-in aperture controls the light entering the sensor array to increase accuracy. A programmable digital GPIO and LED current controller enable light source and trigger control, as well as enabling expandability for an added external photodiode. Device control and spectral data access is implemented through a serial I²C interface. The device is available in an ultralow profile package with dimensions of 3.1mm x 2mm x 1mm.
1.1 Key Benefits & Features
The benefits and features of AS7341, 11-Channel Multi-Spectral Digital Sensor , are listed below:
Figure 1: Added Value of Using AS7341
Benefits Features
Precision color, spectral composition and distribution measurments
Low power consumption and efficient I²C communication
Integrated ambient light flicker detection on chip and light source detection through NIR channel
8 optical channels distributed over the visible spectral range + clear and NIR channels realized via silicon nano-optic interference filter deposition technologies
●
1.8VDD operation, max 300µA
●
Configurable sleep mode to <5µA
●
Interrupt-driven device
●
Dedicated channel
●
Independently configurable timing and gain
●
Automatic gain adjustment
●
50Hz and 60Hz flicker detection flags
Electronic shutter/trigger and synch control
External photodiodes to expand detection range
GPIO can be used as external trigger input or light source synchronization output
GPIO can be used as input for external photodiodes including mid-IR range
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AS7341
General Description
1.2 Applications
●
High-precision reflective color point and spectral measurements
●
Fluid color, turbidity or reagent based constituent analysis
●
Spectral power distribution and passive ambient CCT measurement for home and building automation
●
High-end display color management
1.3 Block Diagram
The functional blocks of this device are shown below:
Figure 2 : Functional Blocks of AS7341
MCU
1.8V
1.8V
VDD
PGND
GND
AS7341
SCL
SDA
INT
8CH VIS
NIR/CLE AR
350-100 0nm sensor
GPIO
LDR e.g.:
Flash LED light in light source reflective surface
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2 Ordering Information
Ordering Code
AS7341-DLGT
AS7341-DLGM
Package
OLGA-8
OLGA-8
Delivery Form
Tape & Reel 13-inch
Tape & Reel 7-inch
AS7341
Ordering Information
Delivery Quantity
5000 pcs/reel
500 pcs/reel
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3 Pin Assignment
AS7341
Pin Assignment
3.1 Pin Diagram
Figure 3: Pin Assignment of AS7341 (TOP VIEW)
VDD
1
8
SDA
SCL
2
AS7341
TOP VIEW
GND
3
7
INT
6
GPIO
LDR
4 5
PGND
3.2 Pin Description
Figure 4: Pin Description of AS7341
7
8
Pin Number
3
4
1
2
5
6
Pin Name
VDD
SCL
GND
LDR
PGND
GPIO
INT
SDA
(1) Explanation of abbreviations:
DI Digital Input
D_I/O Digital Input/Output
DO_OD Digital Output, open drain
P
A_I/O
Power pin
Analog pin
Pin Type
(1)
P
DI
P
A_I/O
P
DI
DO_OD
D_I/O
Description
Positive supply terminal
Serial interface clock signal line for I
2
C interface
Ground. All voltages referenced to GND
LED current sink input
Ground. All voltages referenced to GND
General purpose input/output
Interrupt. Open drain output. Connect pull up resistor to
1.8V.
Serial interface data signal line for I
2
C interface
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AS7341
Absolute Maximum Ratings
4 Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages with respect to GND/PGND. Device parameters are guaranteed at V
DD
=1.8V and T
A
=25°C unless otherwise noted.
Figure 5
Absolute Maximum Ratings of AS7341
Symbol Parameter Min Max Unit Comments
Electrical Parameters
V
DD
/ V
GND
Supply Voltage to Ground
V
ANA_MAX
Analog Pins
V
DIG_MAX
Digital Pins
I
SCR
Input Current (latch-up immunity)
Output Terminal Current I
O
Electrostatic Discharge
ESD
HBM
Electrostatic Discharge HBM
ESD
CDM
Electrostatic Discharge CDM
Temperature Ranges and Storage Conditions
T
A
T
STRG
T
BODY
RH
NC
Operating Ambient Temperature
Storage Temperature Range
Package Body Temperature
Relative Humidity (noncondensing)
-0.3
-0.3
-0.3
-1
-30
-40
5
± 100
± 2000
± 500
2.2
3.6
3.6
20
85
85
260
85
V
V
V mA mA
V
V
°C
°C
°C
%
Applicable for pin VDD
Applicable for pin LDR
Applicable for pins
SCL,SDA and INT
JEDEC JESD78D Nov
2011
JS-001-2014
JEDEC JESD22-C101F
IPC/JEDEC J-STD-020
(1)
MSL
(1)
Moisture Sensitivity Level 3
Maximum floor life time of
168h
The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for Pbfree leaded packages is “Matte Tin” (100% Sn)
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AS7341
Electrical Characteristics
5 Electrical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. All voltages with respect to GND/PGND. Device parameters are guaranteed at VDD=1.8V and T
A
=25°C unless otherwise noted.
Figure 6:
Electrical Characteristics of AS7341
Symbol Parameter Conditions Min Typ Max Unit
V
T
DD
A
Supply Voltage
Operating free-air temperature
(1)
Power Consumption
1.7
-30
1.8
25
2.0
70
V
°C
V
DD
=1.8V; T
A
=25°C
Active mode
(3)
210 300 µA
I
DD
Supply Current
(2)
V
DD
=1.8V; T
A
=25°C
Idle mode
(4)
V
DD
=1.8V; T
A
=25°C
Sleep mode
(5)
Digital pins
V
IH
SCL,SDA input high voltage
V
V
C
IL
OL
I
SCL,SDA input low voltage
INT, SDA output low voltage
Input pin capacitance
6mA sink current
1.26
35
0.7
60
5
0.54
0.4
µA
µA
V
V
V
10 pF
I leak
Leakage current into
SCL,SDA,INT pins
-5 5 µA
GPIO
C
(1)
(2)
(3)
(4)
(5)
LOAD
Maximum capacitive load GPIO
20 pF
While the device is operational across the temperature range, functionality will vary with temperature.
Supply current values are shown at the VDD pin and do not include current through pin LDR.
Active state occurs during active integration. (PON = “1” ; SP_EN = “1”) If wait is enabled (WEN = “1”), supply current is lower during the wait period
Idle state occurs when PON = “1” and all functions are disabled
Sleep state occurs when PON = “0” and I
2
C bus is idle. If I
2
C traffic is active device automatically enters idle mode.
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AS7341
Optical Characteristics
6 Optical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. All voltages with respect to GND/PGND. Device parameters are guaranteed at VDD=1.8V and T
A
=25°C unless otherwise noted.
Figure 7:
AS7341 Optical Channel Summary
Channel
F5
F6
F7
F8
F1
F2
F3
F4
NIR (Near IR)
Clear
FD (Flicker Detection)
Center Wavelength
[nm] typical
415
445
480
515
555
590
630
680
910
Si response/non filtered
Si response/non filtered
Full Width Half Maximum
[nm] typical
39
40
50
52
26
30
36
39 n/a n/a n/a
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AS7341
Optical Characteristics
Figure 8:
Optical Characteristics of Channel F1, AGAIN: 64x, Integration Time: 27.8ms
Symbol Parameter Conditions Min Typ Max Unit
R e_F1
LED: warm white 2700K
(3)
Ee = 107.67
μW/cm
2
Irradiance responsivity channel F1
(2)
Center wavelength
(1)
LED: 420nm
(3)
Ee = 57 µW/cm²
AGAIN = 512x tint = 100ms
55
3200 counts counts
λ p
405 415 425 nm
(1)
(2)
(3)
FWHM
Full width half maximum
(1)
26
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Typical LED Spectra Used in Final Test of AS7341
nm
Figure 9:
Optical Characteristics of Channel F2, AGAIN: 64x, Integration Time: 27.8ms
Symbol Parameter Conditions Min Typ Max Unit
R e_F2
Irradiance responsivity channel F2
(2)
LED: warm white 2700K
(3)
Ee = 107.67
μW/cm
2
110 counts
λ p
Center wavelength
(1)
435 445 455 nm
(1)
(2)
(3)
FWHM Full width half maximum
(1)
30
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Typical LED Spectra Used in Final Test of AS7341
nm
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AS7341
Optical Characteristics
Figure 10:
Optical Characteristics of Channel F3, AGAIN: 64x, Integration Time: 27.8ms
Symbol Parameter Conditions Min Typ Max Unit
R e_F3
Irradiance responsivity channel F3
(2)
LED: warm white 2700K
(3)
Ee = 107.67
μW/cm
2
210 counts
λ p
Center wavelength
(1)
470 480 490 nm
(1)
(2)
(3)
FWHM Full width half maximum
(1)
36
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Typical LED Spectra Used in Final Test of AS7341
nm
Figure 11:
Optical Characteristics of Channel F4, AGAIN: 64x, Integration Time: 27.8ms
Symbol Parameter Conditions Min Typ Max Unit
R e_F4
Irradiance responsivity channel F4
(2)
LED: warm white 2700K
(3)
Ee = 107.67
μW/cm
2
390 counts
λ p
Center wavelength
(1)
505 515 525 nm
(1)
(2)
(3)
FWHM
Full width half maximum
(1)
39
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Typical LED Spectra Used in Final Test of AS7341
nm
Figure 12:
Optical Characteristics of Channel F5, AGAIN: 64x, Integration Time: 27.8ms
Symbol Parameter Conditions Min Typ Max Unit
R e_F5
Irradiance Responsivity channel F5
(2)
LED: warm white 2700K
(3)
Ee = 107.67
μW/cm
2
590 counts
λ p
Center wavelength
(1)
545 555
(1)
(2)
(3)
FWHM Full width half maximum
(1)
39
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Typical LED Spectra Used in Final Test of AS7341
565 nm nm
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AS7341
Optical Characteristics
Figure 13:
Optical Characteristics of Channel F6, AGAIN: 64x, Integration Time: 27.8ms
Symbol Parameter Conditions Min Typ Max Unit
R e_F6
Irradiance responsivity channel F6
(2)
LED: warm white 2700K
(3)
Ee = 107.67
μW/cm
2
840 counts
λ p
Center wavelength
(1)
580 590 600 nm
(1)
(2)
(3)
FWHM Full width half maximum
(1)
40
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Typical LED Spectra Used in Final Test of AS7341
nm
Figure 14:
Optical Characteristics of Channel F7, AGAIN: 64x, Integration Time: 27.8ms
Symbol Parameter Conditions Min Typ Max Unit
R e_F7
Irradiance responsivity channel F7
(2)
LED: warm white
2700K
(3)
Ee = 107.67
μW/cm²
1350
λ p
Center wavelength
(1)
620 630 640
(1)
(2)
(3)
FWHM Full width half maximum
(1)
50
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Typical LED Spectra Used in Final Test of AS7341
counts nm nm
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AS7341
Optical Characteristics
Figure 15:
Optical Characteristics of Channel F8, AGAIN: 64x, Integration Time: 27.8ms
Symbol Parameter Conditions Min Typ Max
R e_F8
Irradiance responsivity channel F8
(2)
LED: warm white
2700K
(3)
Ee = 107.67
μW/cm²
1070
λ p
Center wavelength
(1)
670 680 690
(1)
(2)
(3)
FWHM
Full width half maximum
(1)
52
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Typical LED Spectra Used in Final Test of AS7341
Figure 16:
Typical LED Spectra Used in Final Test of AS7341
0,6
0,5
0,4
0,3
0,2
0,1
0
1
0,9
0,8
0,7
350 450 950 1050 550 650 750 wavelength [nm]
850
LED 420nm
LED 940nm warm white
2700K
Unit
counts nm nm
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AS7341
Optical Characteristics
Figure 17:
Optical Characteristics of AS7341, AGAIN: 64x, Integration Time: 27.8ms (unless otherwise noted)
t t
Symbol
R
R e_CLEAR e_NIR
Dark
Gain ratio
ADC noise
(3) int
_2
(2)
ASTEP
(6)
R e_FLICKER
Dark
_1
(1)(6)
Parameter
Irradiance responsivity channel
CLEAR
Irradiance responsivity channel
FLICKER
Irradiance responsivity channel
NIR
Dark ADC 0-4 count value
Dark ADC 5 count value
Optical gain ratios, relative to 64x gain setting
Typical integration time
(4)
Integration time step size
Conditions
LED: warm white
2700K
(5)
Ee = 107.67
μW/cm
2
LED: warm white
2700K
(5)
Ee = 52.32
μW/cm
2
LED: warm white
2700K
(5)
Ee = 107.67
μW/cm
2
LED: 940nm
(5)
Ee = 98 µW/cm²
AGAIN = 128x tint = 100ms
Ee = 0μW/cm
2
AGAIN: 512x
Integration time: 98ms
Ee = 0μW/cm
2
AGAIN: 512x
Integration time: 98ms
AGAIN: 0.5x
AGAIN: 1x
AGAIN: 2x
AGAIN: 4x
AGAIN: 8x
AGAIN: 16x
AGAIN: 32x
AGAIN: 64x
AGAIN: 128x
AGAIN: 256x
AGAIN: 512x
AGAIN: 16x
Integration time: 10ms
ASTEP = 599
ATIME = 29
ASTEP = 999
Min Typ
1750
6810
112
5135
0
0
0.007 0.008 0.009
0.0145 0.016 0.0175
0.03 0.032 0.034
0.062 0.065 0.068
0.119 0.125 0.131
0.237 0.25 0.263
0.47 0.5
1
0.53
1.8
3.75
7.25
2
3.95
7.75
2.1
4.25
8.25
0.005
% full scale
50 ms
2.78
Max
3
5
Unit
counts counts counts counts counts ms
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AS7341
Optical Characteristics
Symbol Parameter Conditions Min Typ Max
(1)
(2)
(3)
(4)
(5) h ca
(6)
Half cone angle On the sensor 40
The typical 3-sigma distribution is between 0 and 1 counts for AGAIN setting of 16x.
The gain ratios are calculated relative to the response with integration time: 27.8ms and AGAIN: 64x.
ADC noise is calculated as the standard deviation of 1000 data samples divided by full scale.
Integration time, in milliseconds, is equal to: (ATIME + 1) x (ASTEP + 1) x 2.78µs
Typical LED Spectra Used in Final Test of AS7341
Register 0xD6 / AZ_CONFIG is set to “1” – auto zero done before every integration cycle
Unit
deg
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AS7341
Typical Operating Characteristics
7 Typical Operating Characteristics
Figure 18:
Normalized Spectral Responsivity
F1
F7
1
0,9
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0
350
F2
F8
F3
Clear
F4
NIR
450 550 650 750 wavelength [nm]
Figure 19:
Measured Spectral Responsivity Relative to F8
(1)
850
F5
F l i c k e r
950
F6
1050
F1_256x
F5_256x
Clear_512x
F2_256x
F6_256x
NIR_64x
F3_256x
F7_256x
F l i c k e r_64x
F4_256x
F8_256x
1,2
1
0,8
0,6
0,4
0,2
(1)
0
350 390 430 470 510 550 590 630 670 710 750 790 830 870 910 950 990 1030 wavelength [nm]
Fx_256x…AGAIN = 256x, diffuser mounted on top of package surface
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AS7341
Functional Description
8 Functional Description
Upon power-up (POR), the device initializes. During initialization
(typically 200μs), the device will deterministically send NAK on I²C and cannot accept I²C transactions. All communication with the device must be delayed and all outputs from the device must be ignored including interrupts. After initialization, the device enters the SLEEP state. In this operational state, the internal oscillator and other circuitry are not active, resulting in ultra-low power consumption. If an I²C transaction occurs during this state, the I²C core wakes up temporarily to service the communication. Once the Power ON bit,
“PON”, is enabled, the device enters the IDLE state in which the internal oscillator and attendant circuitry are active, but power consumption remains low. Whenever the spectral measurement is enabled (SP_EN
= “1”) the device enters the ACTIVE state. If the spectral measurement is disabled
(SP_EN
= “0”) the device returns to the IDLE state. The figure below describes a simplified state diagram and the typical supply currents in each state.
If Sleep after Interrupt is enabled
(SAI = “1” in register 0xAC), the state machine will enter SLEEP when an interrupt occurs. Entering SLEEP does not automatically change any of the register settings
(e.g. PON bit is still high, but the normal operational state is over-ridden by SLEEP state). SLEEP state is terminated when the SAI_ACTIVE bit is cleared (the status bit is in register 0xA7 and the clear status bit is in register 0xFA).
Figure 20: Simplified State Diagram
Power On
VDD > VDD_POR
SLEEP
IDD = 0.7µA (typ)
PON = „1"
IDLE
IDD = 35µA (typ)
SPM = „1"
ACTIVE
Spectral/Flicker
IDD = 115µA (typ)
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AS7341
Functional Description
8.1 Channel Architecture
The device features 6 independent optical channels with a dedicated 16-bit light-to-frequency converter. Gain and integration time of the 6 channels can be adjusted with the I2C interface. A wait time can be programed to automatically set a delay between two consecutive spectral measurements and to reduce overall power consumption. The other available channels can be accessed by a multiplexer (SMUX) connecting them to one of the internal ADCs.
Figure 21: Simplified Block Diagram
VDD
GND
PGND
GPIO
LDR
LED
6 x 16bit LTF ADC
CH0 ADC
CH1 ADC
CH2 ADC
CH3 ADC
CH4 ADC
CH5 ADC
CH0 data
CH5 data regist er
CH0 Data
CH1 Data
CH2 Data
CH3 Data
CH4 Data
CH5 Data
OTP
I2C
Interface interrupt handling
RCosc
SCL
SDA
INT
8 x VIS F1-F8
4x4 PD array
NIR/CLEAR/FLICKER
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AS7341
Functional Description
8.2 Sensor Array
The device features a 4x4-photodiode array. On top and below the photodiode array there are two photodiodes with dedicated functions such as flicker detection (
“FLICKER”) and near- infrared response (
“NIR”). A clear channel (“C”) – photodiode without filter – is provided at the left and right bottom corner. Each of the filter pairs can be mapped to one of the six internal ADCs (CH0
– CH5).
Figure 22:
Sensor Array
520µm
F L I C K E R
C
F1
F6
F4
F7
F3
F8
F2
F5
F5
F2
F8
F3
F7
F4
F6
F1
C NIR
8.3 GPIO/INT
The GPIO can be either used as input for external photodiodes or as synchronization input to start/stop the spectral measurement. (SYNS/SYND mode).The interrupt output pin INT can also be used to indicate the status (READY/BUSY) of the spectral measurement in mode SYNS and SYND.
8.4 SMUX
AS7341 integrates a sensor multiplexer (SMUX) that enables high-flexibility photodiode channel mapping to the six available ADCs. The 6 ADC limit requires that any measurement that includes more than six of the 8 VIS + 3 specialty channels will require 2 integration cycles. In all cases, after power-up, the SMUX needs to be configured before any spectral measurement is started. ams provides reference code and an application note on how to configure the SMUX. When flicker detection (FD) is used, the flicker diode needs to be configured to ADC5.
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AS7341
Functional Description
8.5 Integration Mode
The device features three modes to perform a spectral measurement. The integration mode
(INT_MODE) can be configured in register 0x70 (CONFIG). For auto zero configuration refer to register 0xD6.
Figure 23:
Integration Mode Description
Mode Description Synchronization Integration Time Registers
SPM (spectral measurement, no sync)
INT_MODE = 0x0
SYNS (spectral measurement, start sync)
INT_MODE = 0x1
Default setting:
Integration is started with bit SP_EN
= “1”. Integration Time is set by register ATIME and ASTEP.
Integration with external start:
Integration is started with rising/falling edge on pin GPIO.
Integration Time is set by register
ATIME and ASTEP.
SYND (spectral measurement, start/stop sync)
INT_MODE = 0x3
Integration with external start and stop:
Integration is controlled via rising/falling edge on pin GPIO and register EDGE. If the number of edges on pin GPIO is reached, integration time is stopped. Actual integration time can be read out in register “ITIME”.
No
Yes (start)
Yes (start/stop)
Figure 24 :
SPM Mode
ATIME [7:0]
ASTEP [15:0]
ATIME [7:0]
ASTEP [15:0]
SP_EN
= “1”
INT_MODE = 0x0
ATIME [7:0]
ASTEP [15:0]
WTIME [7:0]
SP_EN
= “1”
INT_MODE = 0x1
ATIME [7:0]
ASTEP [15:0]
WTIME [7:0]
Rising/falling edge on pin GPIO and register EDGE[7:0]
SP_EN
= “1”
INT_MODE = 0x3
EDGE[7:0]
ITIME[23:0]
STATE
Start
I2C write enable register
WTIME
ATIME x ASTEP
IDLE
AUTO
ZERO
INTEGRATION
RES-
ULT
WAIT auto re-start
INTEGRATION
RES-
ULT
INT
I2C read data registers I2C read data registers
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Functional Description
Figure 25 :
SYNS Mode
Start
STATE IDLE
AUTO
ZERO
SYNC
(GPIO)
READY_BUSYX
(INT)
WTIME
ATIME x ASTEP
INTEGRATION
RES-
ULT
I2C read data registers
Figure 26 :
SYND Mode
Start
STATE
IDLE
AUTO
ZERO
SYNC
(GPIO)
1st
READY_BUSYX
(INT)
2nd
EDGE = 0x4
ITIME
INTEGRATION
3rd 4th
RES-
ULT
5th
I2C read data registers
Start
WAIT
Start
IDLE INTEGRATION
INTEGRATION
1st 2nd 3rd 4th
RES-
ULT
I2C read data registers
RES-
ULT
5th
I2C read data registers
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I²C Interface
9 I²C Interface
The device uses I²C serial communication protocol for communication. The device supports 7-bit chip addressing and both standard and full-speed clock frequency modes. Read and Write transactions comply with the standard set by Philips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e. valid even after the master issues a
STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme for reading and writing. In general, it is recommended to use I²C bursts whenever possible, especially in this case when accessing two bytes of one logical entity. When reading these fields, the low byte must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read immediately afterwards. When writing to these fields, the low byte must be written first, immediately followed by the high byte. Reading or writing to these registers without following these requirements will cause errors.
9.1 I²C Address
Figure 27:
AS7341 I
2
C Slave Address
Device
AS7341
I
2
C Address
0x39
9.2 I²C Write Transaction
A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE,
DATA BYTE(S), and STOP (P). Following each byte (9TH clock pulse) the slave places an
ACKNOWLEDGE/NOT- ACKNOWLEDGE (A/N) on the bus. If the slave transmits N, the master may issue a STOP.
Figure 28:
I
2
C Byte Write
S DW A WA A reg_data A P
WA++
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I²C Interface
9.3 I²C Read Transaction
A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS,
RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP.
Figure 29:
I
2
C Read
S DW A WA A Sr DR A data N P
RA++
9.4 Timing Characteristics
Figure 30:
I²C Timing Characteristics
Symbol
f
SCL t
BUF t
HS;STA t
SU;STA t
SU;STO t
LOW t
HIGH t
HD;DAT t
SU;DAT t
F t
R
Parameter
I²C clock frequency
Bus free time between start and stop condition
Hold time after (repeated) start condition.
After this period, the first clock is generated.
Repeated start condition setup time
Stop condition setup time
SCL clock low period
SCL clock high period
Data hold time
Data setup time
Clock/data fall time
Clock/data rise time
Min Typ Max Unit
400 kHz
1.3
0.6
0.6
0.6
1.3
0.6
0
100
300
300
µs
µs
µs
µs
µs
µs ns ns ns ns
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9.5 Timing Diagrams
Figure 31:
I²C Slave Timing Diagram
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I²C Interface
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Register Description
10 Register Description
The device is controlled and monitored by registers accessed through the I²C serial interface. These registers provide device control functions and can be read to determine device status and acquire device data.
The register set is summarized below. The values of all registers and fields that are listed as reserved or are not listed must not be changed at any time. Two-byte fields are always latched with the low byte followed by the high byte. The
“Name” column illustrates the purpose of each register by highlighting the function associated to each bit. The bits are shown from MSB (D7) to LSB (D0). GRAY fields are reserved and their values must not be changed at any time.
In order to access registers from 0x60 to 0x74 bit REG_BANK in register CFG0 (0xA9) needs to be set to “1”.
10.1 Register Overview
Figure 32:
Register Overview
Addr Name
0x60 ASTATUS
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
CH0_DATA
ITIME
CH1_DATA
CH2_DATA
CH3_DATA
CH4_DATA
CH5_DATA
0x70 CONFIG
0x71 STAT
0x72 EDGE
<D7>
ASAT_
STATUS
<D6> <D5> <D4> <D3> <D2> <D1> <D0>
AGAIN_STATUS [3:0]
CH0_DATA_L [7:0]
CH0_DATA_H [7:0]
ITIME_L [7:0]
ITIME_M [7:0]
ITIME_H [7:0]
CH1_DATA_L [7:0]
CH1_DATA_H [7:0]
CH2_DATA_L [7:0]
CH2_DATA_H [7:0]
CH3_DATA_L [7:0]
CH3_DATA_H [7:0]
CH4_DATA_L [7:0]
CH4_DATA_H [7:0]
CH5_DATA_L [7:0]
CH5_DATA_H [7:0]
LED_SEL INT_SEL
SYNC_EDGE [7:0]
INT_MODE[1:0]
WAIT_SYNC READY
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Register Description
Addr Name
0x73 GPIO
0x74 LED
0x80 ENABLE
0x81 ATIME
0x83 WTIME
0x84
SP_TH_L
0x85
0x86
SP_TH_H
0x87
0x90 AUXID
0x91 REVID
0x92 ID
0x93 STATUS
0x94 ASTATUS
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
CH0_DATA
CH1_DATA
CH2_DATA
CH3_DATA
CH4_DATA
CH5_DATA
0xA3 STATUS 2
0xA4 STATUS 3
0xA6 STATUS 5
0xA7 STATUS 6
0xA9 CFG 0
0xAA CFG 1
0xAC CFG 3
0xAF CFG 6
0xB1 CFG 8
<D7>
LED_ACT
<D6> <D5>
FDEN
<D4> <D3> <D2>
LED_DRIVE [6:0]
SMUXEN WEN
ATIME [7:0]
WTIME [7:0]
SP_TH_L_LSB [7:0]
SP_TH_L_MSB [7:0]
SP_TH_H_LSB [7:0]
SP_TH_H_MSB [7:0]
AUXID [7:0]
REVID [7:0]
ID [7:0]
AINT FINT
<D1>
PD_GPIO
SP_EN
ASAT
ASAT_
STATU
S
CINT
AGAIN_STATUS [3:0]
FIFO_
OV
AVALI
D
FIFO_TH [7:6]
CH0_DATA_L [7:0]
CH0_DATA_H [7:0]
CH1_DATA_L [7:0]
CH1_DATA_H [7:0]
CH2_DATA_L [7:0]
CH2_DATA_H [7:0]
CH3_DATA_L [7:0]
CH3_DATA_H [7:0]
CH4_DATA_L [7:0]
CH4_DATA_H [7:0]
CH5_DATA_L [7:0]
CH5_DATA_H [7:0]
ASAT_
DIG
ASAT_
ANA
FDSAT
_ANA
INT_SP_
H
OVTEMP
LOW_
POWER
INT_SP_L
FD_TRIG
SINT_FD
SP_TRIG
SAI_
ACT
REG_
BANK
WLONG
SAI
SMUX_
CMD[4:3]
FD_AGC
AGAIN[4:0]
SP_AGC
<D0>
PD_INT
PON
SINT
FDSAT_
DIG
INT_BUS
Y
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AS7341
Register Description
Addr Name
0xB2 CFG 9
0xB3 CFG 10
0xB5 CFG 12
0xBD PERS
0xBE GPIO 2
0xCA
0xCB
ASTEP
0xCF
AGC_GAIN_M
AX
0xD6 AZ_CONFIG
0xD8 FD_TIME 1
0xDA FD_TIME 2
0xD7 FD_CFG0
0xDB FD_STATUS
0xF9 INTENAB
0xFA CONTROL
0xFC FIFO_MAP
0xFD FIFO_LVL
0xFE
0xFF
FDATA
<D7>
SIEN
_FD
AGC_H [7:6]
<D6> <D5> <D4>
AGC_L[7:6]
SIEN
_SMUX
<D3>
GPIO_
INV
ASTEP [7:0]
ASTEP [15:8]
AGC_FD_GAIN_MAX [7:4]
<D2> <D1>
FD_PERS [2:0]
SP_TH_CH [2:0]
APERS [3:0]
GPIO_
IN
GPIO_
OUT
GPIO_
IN
AGC_AGAIN_MAX [3:0]
AT_NTH_ITERATION [7:0]
FD_TIME [7:0]
FD_GAIN [7:3] FD_TIME [10:8]
FD_
FIFO
ASIEN
FD_
VALID
FD_
SAT
FD_
120HZ_
VALID
SP_IEN
FD_
100Hz_
VALID
FIEN
AZ_SP_
MAN
FIFO_WRITE_CH5_DATA
– FIFO_WRITE_CH0_DATA [6:1]
FIFO_LVL [7:0]
FDATA [7:0]
FDATA [15:8]
FD_
120Hz
CIEN
FIFO_
CLR
<D0>
FD_
100Hz
SIEN
CLEAR_
SAI_ACT
ASTATU
S
10.2 Detailed Register Description
For easier readability, the detailed register description is done in groups of registers related to dedicated device functions. This is not necessarily related to its register address.
Explanation of register access abbreviations:
RW = read or write
R = read only
W = write only
SC = self-clearing after access
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Register Description
10.2.1 Enable and Configuration Register
The following registers are needed to power up and configure the device. To operate the device set bit
PON = “1” first (register 0x80) after that configure the device and enable interrupts before setting
SP_EN
= “1”. Changing configuration while SP_EN = “1” may result in invalid results. Register
CONFIG (0x70) is used to set the INT_MODE (SYNS,SYND).
ENABLE Register (Address 0x80)
Figure 33:
ENABLE Register
6
5
2
1
Addr: 0x80
Bit
7
Bit Name
reserved
4
3
0
FDEN reserved
SMUXEN
WEN reserved
SP_EN
PON
ENABLE
Default
0
0
0
0
0
0
0
0
Access Bit Description
RW
RW
RW
RW
RW
RW
RW
RW reserved
Flicker Detection Enable.
0: Flicker Detection disabled
1: Flicker Detection enabled reserved
SMUX Enable.
1: Starts SMUX command
Note: this bit gets cleared automatically as soon as
SMUX operation is finished
Wait Enable.
0: Wait time between two consecutive spectral measurements disabled
1: Wait time between two consecutive spectral measurements enabled reserved
Spectral Measurement Enable.
0: Spectral Measurement Disabled
1: Spectral Measurement Enabled
Power ON.
0: AS7341 disabled
1: AS7341 enabled
Note: When bit is set, internal oscillator is activated, allowing timers and ADC channels to operate.
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Register Description
CONFIG Register (Address 0x70)
Figure 34:
CONFIG Register
Addr: 0x70
Bit
7:4
Bit Name
reserved
3
2
1:0
LED_SEL
INT_SEL
INT_MODE
CONFIG
Default
0
0
0
0
Access Bit Description
RW
RW
RW
RW reserved
LED control.
0: External LED not controlled by AS7341
1: Register LED controls LED connected to pin LDR
Note: register 0x74
1: Sync signal applied on output pin INT
Ambient light sensing mode:
0: SPM mode (spectral measurement, normal mode)
1: SYNS mode
2: reserved
3: SYND mode
Note: in SYND mode it is recommended to use register 0x60 to 0x6F to read out spectral data.
GPIO Register (Address 0x73)
Figure 35:
GPIO Register
Addr: 0x73
Bit
7:2
1
0
Bit Name
reserved
PD_GPIO
PD_INT
GPIO
Default
0
0
0
Access
RW
RW
RW
Bit Description
reserved
1: Photo diode connected to pin GPIO
1: Photo diode connected to pin INT
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GPIO 2 Register (Address 0xBE)
Figure 36:
GPIO2 Register
2
1
Addr: 0xBE
Bit
7:4
3
Bit Name
reserved
GPIO_INV
GPIO_IN_EN
GPIO_OUT
0
1
GPIO 2
Default
0
0
0 GPIO_IN 0
AS7341
Register Description
Access Bit Description
RW
RW
RW
R reserved
GPIO Invert.
If set, the GPIO output is inverted.
GPIO Input Enable.
If set, the GPIO pin accepts a non-floating input.
GPIO Output.
If set, the output state of the GPIO is active directly.
GPIO Input.
Indicates the status of the GPIO input if
GPIO_IN_EN is set.
LED Register (Address 0x74)
Figure 37:
LED Register
Addr: 0x74
Bit Bit Name
LED
Default
7 LED_ACT 0
6:0 LED_DRIVE 000 0100
Access Bit Description
RW
RW
LED control.
0: External LED connected to pin LDR off
1: External LED connected to pin LDR on
LED driving strength.
000 0000: 4mA
000 0001: 6mA
000 0010: 8mA
000 0011: 10mA
000 0100:
12mA
……
111 1110: 256mA
111 1111: 258mA
Note: Bit LED_SEL (register 0x70) needs to be set to “1” to control LED connected to pin LDR.
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INTENAB Register (Address 0xF9)
Figure 38:
INTENAB Register
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7
2
1
Addr: 0xF9
Bit Bit Name
6:4
3
0
ASIEN reserved
SP_IEN
F_IEN reserved
SIEN
AS7341
Register Description
INTENAB
Default
0
0
0
0
Access Bit Description
RW
RW
RW
RW
Spectral and Flicker Detect Saturation Interrupt
Enable.
When asserted permits saturation interrupts to be generated. reserved
Spectral Interrupt Enable.
When asserted permits interrupts to be generated, subject to the spectral thresholds and persistence filter. Bit is mirrored in the ENABLE register.
FIFO Buffer Interrupt Enable.
When asserted permits interrupt to be generated when FIFO_LVL exceeds the FIFO threshold condition. reserved
System Interrupt Enable.
When asserted permits system interrupts to be generated. Indicates that flicker detection status has changed or SMUX operation has finished.
CONTROL Register (Address 0xFA)
Figure 39:
CONTROL Register
Addr: 0xFA
Bit
7:3
Bit Name
reserved
2 SP_MAN_AZ
1
0
FIFO_CLR
CLEAR_SAI_ACT
CONTROL
Default
0
0
0
0
Access Bit Description
RW
RW
RW reserved
Spectral Engine Manual Autozero.
Starts a manual autozero of the spectral engines.
Set SP_EN = 0 before starting a manual autozero for it to work.
FIFO Buffer Clear.
Clears all FIFO data, FINT, FIFO_OV, and
FIFO_LVL.
Clear Sleep-After-Interrupt Active.
Clears SAI_ACTIVE, ends sleep, and restarts device operation.
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Register Description
10.2.2 ADC Timing Configuration / Integration Time
The integration time in INT
_MODE = “00” and “01” (SPM/SYNS) is set using the ATIME (0x81) and
ASTEP (0xCA, 0xCB) registers. The integration time, in milliseconds, is equal to:
Equation 1: Setting the integration time
𝑡 𝑖𝑛𝑡
= (𝐴𝑇𝐼𝑀𝐸 + 1) × (𝐴𝑆𝑇𝐸𝑃 + 1) × 2.78µ𝑠
The reset value for ASTEP is 999 (2.78ms) and the recommended configuration for these two registers is ASTEP = 599 and ATIME = 29, which results in an integration time of 50ms. It is not allowed that both settings
–ATIME and ASTEP – are set to “0”.
The integration time also defines the full-scale ADC value, which is equal to:
Equation 2: ADC full scale value
(1)
𝐴𝐷𝐶 𝑓𝑢𝑙𝑙𝑠𝑐𝑎𝑙𝑒
= (𝐴𝑇𝐼𝑀𝐸 + 1) × (𝐴𝑆𝑇𝐸𝑃 + 1)
ATIME Register (Address 0x81)
Figure 40:
ATIME Register
Addr: 0x81 ATIME
Bit Bit Name Default Access Bit Description
7:0
(1)
ATIME 0x00 RW
Integration time.
Sets the number of integration steps from 1 to 256.
Value Integration Time
0 ASTEP n ASTEP x (n+1)
255 256 x ASTEP
The maximum ADC count is 65535. Any ATIME/ASTEP field setting resulting in higher ADCfullscale values would result in a full-scale of 65535.
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ASTEP Register (Address 0xCA, 0xCB)
Figure 41:
ASTEP Register
Addr: 0xCA, 0xCB
Bit Bit Name
ASTEP
Default
7:0
15:8
ASTEP 0xCA
ASTEP 0xCB
999
AS7341
Register Description
Access Bit Description
RW
Integration time step size.
Sets the integration time per step in increments of
2.78µs. The default value is 999.
VALUE
0 n
STEP SIZE
2.78µs
2.78µs x (n+1)
599
999
17999
65534
65535
1.67ms
2.78ms
50ms
182ms reserved, do not use
WTIME Register (Address 0x83)
If wait is enabled (WEN = “1” register 0x80), each new measurement is started based on WTIME. It is necessary for WTIME to be sufficiently long for spectral integration and any other functions to be completed within the period. The device will warn the user if the timing is configured incorrectly. If
WTIME is too short, then SP
_TRIG in register STATUS6 (ADDR: 0xA7) will be set to “1”.
Figure 42:
WTIME Register
Addr: 0x83
Bit Bit Name
7:0 WTIME
WTIME
Default
0x00
Access Bit Description
RW
Spectral Measurement Wait time.
8-bit value to specify the delay between two consecutive spectral measurements.
Value Wait Cycles Wait Time
0x00
0x01 n
0xff
1
2 n
256
2.78ms
5.56ms
2.78ms x (n+1)
711ms
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Register Description
ITIME Register (Address 0x63, 0x64, 0x65)
The register ITIME can be used to read-out the actual integration time in INT
_MODE = “11” (SYND).
In SYND mode the integration time is defined by the register “EDGE” and the device is running integration until the number of falling edges on pin GPIO is reached.
Equation 3: Calculating the integration time in SYND mode
𝑡 𝑖𝑛𝑡
= 𝐼𝑇𝐼𝑀𝐸 × 2.78µ𝑠
Figure 43:
ITIME_L Register
Addr: 0x63
Bit
7:0
Bit Name
ITIME_L
ITIME_L
Default
0
Access Bit Description
R Integration time in integration mode SYND
Figure 44:
ITIME_M Register
Addr: 0x64
Bit
15:8
Bit Name
ITIME_M
ITIME_M
Default
0
Access Bit Description
R Integration time in integration mode SYND
Figure 45:
ITIME_H Register
Addr: 0x65
Bit
23:16
Bit Name
ITIME_H
ITIME_H
Default
0
Access Bit Description
R Integration time in integration mode SYND
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EDGE Register (Address 0x72)
Figure 46:
EDGE Register
Addr: 0x72
Bit Bit Name
7:0 SYNC_EDGE
EDGE
Default
0
Access
RW
Bit Description
AS7341
Register Description
Number of falling SYNC-edges between start and stop of integration in mode SYND
Number of edges = SYNC_EDGE + 1
FD_TIME Register (Address 0xD8, 0xDA)
The register FD Time 1 and FD Time 2 can be used to configure the integration time and gain (ADC 5) of the flicker detection independently from the other ADCs. The FD_TIME register is an 11-bit register with the MSB in register 0xDA (bit 10:8) and the LSB in register 0xD8 (bit 7:0). The bit FDEN (register
0x80) must be set to “1” in order to use the FD_TIME registers. If the bit FDEN is not set, ADC5 runs automatically with the same gain and integration time as ADC0 to ADC4.
Equation 4: Calculating the flicker detection integration time
𝑡 𝑖𝑛𝑡_𝐹𝐷
= 𝐹𝐷_𝑇𝐼𝑀𝐸 × 2.78µ𝑠
Figure 47:
FD Time Register
Addr: 0xD8
Bit
7:0
Bit Name
FD_TIME [7:0]
FD_TIME_1
Default
0
Access Bit Description
RW
LSB of flicker detection integration time
Note: must not be changed during FDEN = 1 and
PON = 1.
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AS7341
Register Description
Figure 48:
FD Time Register
Addr: 0xDA
Bit Bit Name
7:3 FD_GAIN
2:0 FD_TIME [10:8]
FD_TIME_2
Default
9
0
Access Bit Description
R/W
RW
Flicker Detection gain setting (ADC5)
2
3
4
VALUE
0
1
2x
4x
8x
GAIN
0.5x
1x
7
8
5
6
16x
32x
64x
128x
9
10
256x
512x
MSB of flicker detection integration time
Note: must not be changed during FDEN = 1 and
PON = 1.
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Register Description
10.2.3 ADC Configuration (gai n, AGC…)
The following registers provide configuration for the 6 integrated ADCs (CH0 to CH5). It is possible to adjust the gain, configure and enable the automatic gain control (AGC) and setup the auto zero compensation for the engines.
CFG1 Register (Address 0xAA)
Figure 49:
CFG1 Register
Addr: 0xAA
Bit
7:5
Bit Name
reserved
CFG1
Default
0
4:0 AGAIN 9
Access Bit Description
RW
5
6
3
4
7
0
1
2
8
9
10 reserved
Spectral engines gain setting.
Sets the spectral sensitivity.
VALUE GAIN
128x
256x
512x
0.5x
1x
2x
4x
8x
16x
32x
64x
CFG10 Register (Address 0xB3)
Figure 50:
CFG10 Register
Addr: 0xB3
Bit Bit Name
CFG10
Default
7:6 AGC_H 3
Access Bit Description
RW
AGC High Hysteresis.
Sets the data threshold at which AGAIN is reduced when spectral AGC mode is enabled. The threshold is automatically calculated internally as a percentage of full-scale. Note that full-scale is equal to (ATIME +
1) x (ASTEP + 1).
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Addr: 0xB3
Bit Bit Name
5:4 AGC_L
3 reserved
2:0 FD_PERS
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AS7341
Register Description
CFG10
Default
3
0
2
Access Bit Description
RW
RW
VALUE
0
SIGNAL
50%
1
2
62.5%
75%
3 87.5%
AGC Low Hysteresis.
Sets the data threshold at which AGAIN is increased when spectral AGC mode is enabled. The threshold is automatically calculated internally as a percentage of full-scale. Note that full-scale is equal to (ATIME +
1) x (ASTEP + 1).
VALUE SIGNAL
0
1
2
12.5%
25%
37.5%
50% 3 reserved
Flicker Detect Persistence.
Sets the number of consecutive flicker detect results that must be different before the flicker detect status will be changed. Flicker detection interrupts on SINT are affected by this setting. Flicker detect persistence is equal to 2
(𝐹𝐷
𝑃𝐸𝑅𝑆
−1)
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AS7341
Register Description
AZ_CONFIG Register (Address 0xD6)
The following register configures how often the spectral engine offsets are reset (auto zero) to compensate for changes of the device temperature. The typical time auto zero needs to be completed is 15ms.
Figure 51:
AZ_CONFIG Register
Addr: 0xD6
Bit
7:0
AZ_CONFIG
Bit Name Default Access Bit Description
AZ_NTH_ITERATION 255 RW
1
2
…
254
255
AUTOZERO FREQUENCY.
Sets the frequency at which the device performs auto zero of the spectral engines.
Note: If FD
EN = “1” auto zero is also done for ADC 5.
The flicker detection measurement will be interrupted and restarted in this case.
VALUE
0
AUTOZERO FREQUENCY
Never (not recommended)
Every integration cycle
Every 2 cycles
Every
“AZ_NTH_ITERATION” cycle
Every 254 cycles
Only before first measurement cycle
AGC_GAIN_MAX Register (Address 0xCF)
Figure 52:
AGC_GAIN_MAX Register
Addr: 0xCF
Bit
7:4
3:0
Bit Name
AGC_FD_GAIN_MAX 9
AGC_AGAIN_MAX
AGC_GAIN_MAX
Default
9
Access Bit Description
RW
RW
Flicker Detection AGC Gain Max.
Sets the maximum gain for flicker detection to
2
𝐴𝐺𝐶_𝐹𝐷_𝐺𝐼𝐴𝑁_𝑀𝐴𝑋
Default value is 9 (256x). The range can be set from
0 (0.5x) to 10 (512x).
AGC Gain Max.
Sets the maximum gain for AGC engine to
2
𝐴𝐺𝐶_𝐹𝐷_𝐺𝐼𝐴𝑁_𝑀𝐴𝑋
Default value is 9 (256x). The range can be set from
0 (0.5x) to 10 (512x).
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CFG8 Register (Address 0xB1)
Figure 53:
CFG8 Register
Addr: 0xB1
Bit Bit Name
CFG8
Default
7:6
2
1
0
5:4
3
FIFO_TH reserved
FD_AGC
SP_AGC reserved reserved
2
0
1
0
0
0
AS7341
Register Description
Access Bit Description
R/W
RW
RW
FIFO Threshold.
Sets a threshold on the FIFO level that triggers the first FIFO buffer interrupt (FINT).
VALUE
0
1
FIFO_LVL
1
4
2
3 reserved
Flicker Detect AGC Enable
.
If set, device uses automatic gain control for the flicker detect engine to maximize flicker signal and avoid saturation.
Spectral AGC enable.
If asserted, device uses automatic gain control for the spectral engines to maximize signal while avoiding saturation. reserved reserved
8
16
10.2.4 Device Identification
The following registers provided device identification. Device ID, revision ID and auxiliary ID are read only.
AUXID Register (Address 0x90)
Figure 54:
AUXID Register
Addr: 0x90
Bit
7:4
3:0
Bit Name
reserved
AUXID
AUXID
Default
000
Access Bit Description
R reserved
Auxiliary identification
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REVID Register (Address 0x91)
Figure 55:
REVID Register
Addr: 0x91
Bit
7:3
2:0
Bit Name
reserved
REV_ID
REVID
Default
000
Access
R
Bit Description
AS7341
Register Description reserved
Revision number identification
ID Register (Address 0x92)
Figure 56:
ID Register
Addr: 0x92
Bit Bit Name
7:2
1:0
ID reserved
ID
Default
001001
Access Bit Description
R
Part number Identification
Value 001001 reserved
10.2.5 Spectral Interrupt Configuration
The spectral interrupt threshold registers provide 16-bit values to be used as the high and low thresholds for comparison to the 16-bit CH0_DATA values (ADC CH0). If SP_IEN (register 0xF9) is enabled and CH0_DATA is not between the two thresholds for the number of consecutive measurements specified in APERS (register 0xBD) an interrupt is set.
SP_TH_L_LSB Register (Address 0x84)
Figure 57:
SP_TH_L_LSB Register
Addr: 0x84
Bit
7:0
Bit Name
SP_TH_L_LSB
SP_TH_L_LSB
Default
0x00
Access Bit Description
RW
Spectral low threshold LSB
This register provides the low byte of the low interrupt threshold (CH0).
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SP_TH_L_MSB Register (Address 0x85)
Figure 58:
SP_TH_L_MSB Register
Addr: 0x85
Bit Bit Name
7:0 SP_TH_L_MSB
AS7341
Register Description
SP_TH_L_MSB
Default
0x00
Access Bit Description
RW
Spectral low threshold MSB
This register provides the high byte of the low interrupt threshold (CH0).
Both SP_TH_L registers are combined to a 16-bit threshold. If the value captured by channel 0 is below the low threshold and the APERS value is reached the bit SP_IEN is set and an interrupt is generated.
There is an 8-bit data latch implemented that stores the written low byte until the high byte is written.
Both bytes will be applied at the same time to avoid an invalid threshold.
Note: The LSB register cannot be changed without writing to the MSB register. It is recommended to write to SP_TH_L_LSB and SP_TH_L_MSB within one I
2
C command.
SP_TH_H_LSB Register (Address 0x86)
Figure 59:
SP_TH_H_LSB Register
Addr: 0x86
Bit
7:0
Bit Name
SP_TH_H_LSB
SP_TH_H_LSB
Default
0x00
Access Bit Description
RW
Spectral high threshold LSB
This register provides the low byte of the high interrupt threshold (CH0).
SP _TH_H_MSB Register (Address 0x87)
Figure 60:
SP _TH_H_MSB Register
Addr: 0x87
Bit
7:0
Bit Name
SP_TH_H_MSB
SP _TH_H_MSB
Default
0x00
Access Bit Description
RW
Spectral high threshold MSB
This register provides the high byte of the high interrupt threshold (CH0).
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AS7341
Register Description
Addr: 0x87
Bit
CFG12 Register (Address 0xB5)
Figure 61:
CFG12 Register
Addr: 0xB5
Bit
7:3
Bit Name
reserved
CFG12
Default
0
2:0
Bit Name
SP_TH_CH
SP _TH_H_MSB
Default Access Bit Description
Both SP_TH_H registers are combined to a 16-bit threshold. If the value captured by channel 0 is above the high threshold and the APERS value is reached the bit SP_IEN is set and an interrupt is generated.
0
Access Bit Description
RW
2
3
0
1
4 reserved
Spectral Threshold Channel.
Sets the channel used for interrupts, persistence and the AGC, if enabled, to determine device status and gain settings.
VALUE CHANNEL
CH0
CH1
CH2
CH3
CH4
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Register Description
10.2.6 Device Status Register
The following register provide status of the device and indicate details about saturation, interrupts, over temperature, device execution and ambient light flicker detection.
STAT Register (Address 0x71)
Figure 62:
STAT Register
Addr: 0x71
Bit
7:2
1
Bit Name
reserved
WAIT_SYNC
0 READY
STAT
Default
0
0
0
Access Bit Description
RW
R
R reserved
1: Device waits for sync pulse on GPIO to start integration (SYNS / SYND INT_mode)
0: Spectral measurement status is busy
1: Spectral measurement status is ready
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Register Description
STATUS Register (Address 0x93)
The primary status register for AS7341 indicates if there are saturation or interrupt events that need to be handled by the user. This register is selfclearing, meaning that writing a “1” to any bit in the register clears that status bit. In this way, the user should read the STATUS register, handle all indicated event(s) and then write the register value back to STATUS to clear the handled events.
Writing “0” will not clear those bits if they have a value of “1”, which means that new events that occurred since the last read of the STATUS register will not be accidentally cleared.
Figure 63:
STATUS Register
Addr: 0x93
Bit Bit Name
7
1
0
6:4
3
2
ASAT reserved
AINT
FINT
C_INT
SINT
0
0
STATUS
Default
0
0
0
0
Access Bit Description
R, SC
R
R, SC
R, SC
R, SC
R, SC
Spectral and Flicker Detect saturation.
If ASIEN is set, indicates Spectral saturation. Check
STATUS2 register to distinguish between analog or digital saturation. reserved
Spectral Channel Interrupt.
If SP_IEN is set, indicates that a spectral event that met the programmed thresholds and persistence
(APERS) occurred.
FIFO Buffer Interrupt.
If FIEN is set, indicates that the FIFO_LVL fulfills the threshold condition. If cleared by writing 1, the interrupt will be asserted again as more data is collected. To fully clear this interrupt, all data must be read from the FIFO buffer.
Calibration Interrupt.
System Interrupt.
If SIEN is set, indicates that system interrupt is set.
Refer to Status5 register
.
STATUS 2 Register (Address 0xA3)
Figure 64:
STATUS 2 Register
Addr: 0xA3
Bit
7
Bit Name
reserved
6
5
AVALID reserved
STATUS 2
Default
0
0
0
Access Bit Description
R reserved
Spectral Valid
.
Indicates that the spectral measurement has been completed reserved
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AS7341
Register Description
Addr: 0xA3
Bit
4
3
2
1
0
Bit Name
ASAT_DIGITAL
ASAT_ANALOG reserved
FDSAT_ANALOG
FDSAT_DIGITAL
STATUS 2
Default
0
0
0
0
0
Access Bit Description
R
R
R
R
R
Digital saturation
.
Indicates that the maximum counter value has been reached. Maximum counter value depends on integration time set in the ATIME register.
Analog saturation
.
Indicates that the intensity of ambient light has exceeded the maximum integration level for the spectral analog circuit. reserved
Flicker detect analog saturation
.
Indicates that the intensity of ambient light has exceeded the maximum integration level for the analog circuit for flicker detection.
Flicker detect digital saturation
.
Indicates that the maximum counter value has been reached during flicker detection.
STATUS 3 Register (Address 0xA4)
Figure 65:
STATUS 3 Register
Addr: 0xA4
Bit
7:6
5
4
3:0
Bit Name
reserved
INT_SP_H
INT_SP_L reserved
STATUS 3
Default
0
0
0
0
Access Bit Description
R
R reserved
Spectral interrupt high.
Indicates that a spectral interrupt occurred because the data exceeded the high threshold.
Spectral interrupt low
.
Indicates that a spectral interrupt occurred because the data is below the low threshold. reserved
STATUS 5 Register (Address 0xA6)
Figure 66:
STATUS 5 Register
Addr: 0xA6
Bit
7:4
Bit Name
reserved
STATUS 5
Default
0
Access Bit Description
reserved
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AS7341
Register Description
Addr: 0xA6
Bit
3
2
1:0
Bit Name
SINT_FD
SINT_SMUX reserved
STATUS 5
Default
0
0
0
Access Bit Description
R
R
Flicker Detect interrupt.
If SIEN_FD is set, indicates that the FD_STATUS register status has changed
SMUX operation interrupt.
Indicates that SMUX command execution has finished. reserved
7
4
3
2
STATUS 6 Register (Address 0xA7)
Figure 67:
STATUS 6 Register
Addr: 0xA7
Bit Bit Name
6
5
1
0
FIFO_OV reserved
OVTEMP
FD_TRIG reserved
SP_TRIG
SAI_ACTIVE
INT_BUSY
STATUS 6
Default
0
0
0
0
0
0
0
0
Access Bit Description
R
R
R
R
R
R
R
FIFO Buffer Overflow.
Indicates that the FIFO buffer overflowed and information has been lost. Bit is automatically cleared when the FIFO buffer is read reserved
Over Temperature Detected.
Indicates the device temperature is too high. Write 1 to clear this bit.
Flicker Detect Trigger Error.
Indicates that there is a timing error that prevents flicker detect from working correctly. reserved
Spectral Trigger Error.
Indicates that there is a timing error. The WTIME is too short for the selected ATIME.
Sleep after Interrupt Active.
Indicates that the device is in SLEEP due to an interrupt. To exit SLEEP mode, clear this bit.
Initialization Busy.
Indicates that the device is initializing. This bit will remain 1 for about 300μs after power on. Do not interact with the device until initialization is complete.
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FD_STATUS Register (Address 0xDB)
Figure 68:
FD STATUS Register
AS7341
Register Description
Addr: 0xDB
Bit
7:6
5
FD_STATUS
Bit Name
reserved
FD_MEASUREMENT_
VALID
0
Default
4
3
2
1
0
FD_SATURATION_
DETECTED
0
FD_120HZ_FLICKER_
VALID
0
FD_100HZ_FLICKER_
VALID
0
FD_120HZ_FLICKER 0
FD_100HZ_FLICKER 0
Access Bit Description
R
R
R
R
R
R reserved
Flicker Detection Measurement Valid.
Indicates that flicker detection measurement is complete. Write 1 to this bit to clear this field.
Flicker Saturation Detected.
Indicates that saturation occurred during the last flicker detection measurement, and the result may not be valid. Write 1 to this bit to clear this field.
Flicker Detection 120Hz Flicker Valid.
Indicates that the 120Hz flicker detection calculation is valid. Write 1 to this bit to clear this field.
Flicker Detection 100Hz Flicker Valid.
Indicates that the 100Hz flicker detection calculation is valid. Write 1 to this bit to clear this field.
Flicker Detected at 120Hz.
Indicates if an ambient light source is flickering at
120Hz.
Flicker Detected at 100Hz.
Indicates if an ambient light source is flickering at
100Hz.
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AS7341
Register Description
10.2.7 Spectral Data and Status
The ASTATUS register is mapped to register address 0x60 and 0x94. It provides saturation and gain status associated to each set of spectral data. Reading the ASTATUS register (0x60 or 0x94) latches all 12 spectral data bytes to that status read. Reading these bytes consecutively (0x60 to 0x6F or 0x94 to 0xA0) ensures that the data is concurrent. All spectral data are stored as 16-bit values. If flicker detection is enabled, spectral channel five (CH5 ADC) is used for the flicker detection function and
CH5_DATA will read “0”. The ASTATUS and spectral data registers are read only.
In SPM or SYNS mode, it is recommended to use the ASTATUS register 0x94 and spectral data register 0x94 to 0xA0. In SYND mode, it is possible to use register 0x60 to 0x6F for easier implementation.
ASTATUS Register (Address 0x60 or 0x94)
Figure 69:
ASTATUS Register
Addr: 0x60 and 0x94
Bit
7
6:4
3:0
Bit Name
ASAT_STATUS reserved
AGAIN_STATUS
ASTATUS
Default
0
0
0
Access Bit Description
R, SC
R
R, SC
Saturation Status.
Indicates if the latched data is affected by analog or digital saturation. reserved
Gain Status.
Indicates the gain applied for the spectral data latched to this ASTATUS read. The gain from this status read is required to calculate spectral results if
AGC is enabled.
CH0_DATA Register (Address 0x95/0x96)
Figure 70:
CH0_DATA_L Register
Addr: 0x95
Bit
7:0
Bit Name
CH0_DATA_L
CH0_DATA_L
Default
0
Access Bit Description
R CH0 ADC data
– low byte
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Figure 71:
CH0_DATA_H Register
Addr: 0x96
Bit
7:0
Bit Name
CH0_DATA_H
CH0_DATA_H
Default
0
Access Bit Description
R CH0 ADC data
– high byte
CH1_DATA Register (Address 0x97/0x98)
Figure 72:
CH1_DATA_L Register
Addr: 0x97
Bit
7:0
Bit Name
CH1_DATA_L
CH1_DATA_L
Default
0
Access Bit Description
R CH1 ADC data
– low byte
Figure 73:
CH1_DATA_H Register
Addr: 0x98
Bit
7:0
Bit Name
CH1_DATA_H
CH1_DATA_H
Default
0
Access Bit Description
R CH1 ADC data
– high byte
AS7341
Register Description
CH2_DATA Register (Address 0x99/0x9A)
Figure 74:
CH2_DATA_L Register
Addr: 0x99
Bit
7:0
Bit Name
CH2_DATA_L
CH2_DATA_L
Default
0
Access Bit Description
R CH2 ADC data
– low byte
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Figure 75:
CH2_DATA_H Register
Addr: 0x9A
Bit
7:0
Bit Name
CH2_DATA_H
CH2_DATA_H
Default
0
Access Bit Description
R CH2 ADC data
– high byte
CH3_DATA Register (Address 0x9B/0x9C)
Figure 76:
CH3_DATA_L Register
Addr: 0x9B
Bit
7:0
Bit Name
CH3_DATA_L
CH3_DATA_L
Default
0
Access Bit Description
R CH3 ADC data
– low byte
Figure 77:
CH3_DATA_H Register
Addr: 0x9C
Bit
7:0
Bit Name
CH3_DATA_H
CH3_DATA_H
Default
0
Access Bit Description
R CH3 ADC data
– high byte
AS7341
Register Description
CH4_DATA Register (Address 0x9D/0x9E)
Figure 78:
CH4_DATA_L Register
Addr: 0x9D
Bit
7:0
Bit Name
CH4_DATA_L
CH4_DATA_L
Default
0
Access Bit Description
R CH4 ADC data
– low byte
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Figure 79:
CH4_DATA_H Register
Addr: 0x9E
Bit
7:0
Bit Name
CH4_DATA_H
CH4_DATA_H
Default
0
Access Bit Description
R CH4 ADC data
– high byte
CH5_DATA Register (Address 0x9F/0xA0)
Figure 80:
CH5_DATA_L Register
Addr: 0x9F
Bit
7:0
Bit Name
CH5_DATA_L
CH5_DATA_L
Default
0
Access Bit Description
R CH5 ADC data
– low byte
Figure 81:
CH5_DATA_H Register
Addr: 0xA0
Bit
7:0
Bit Name
CH5_DATA_H
CH5_DATA_H
Default
0
Access Bit Description
R CH5 ADC data
– high byte
AS7341
Register Description
10.2.8 Miscellaneous Configuration
CFG0 Register (Address 0xA9)
Figure 82:
CFG 0 Register
Addr: 0xA9
Bit
7:6
Bit Name
reserved
CFG0
Default
0
5 LOW_POWER 0
Access Bit Description
RW reserved
Low Power Idle.
When asserted, the device will automatically run in a low power mode whenever all functions are in wait states or disabled.
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AS7341
Register Description
Addr: 0xA9
Bit
4
3
2
1:0
Bit Name
REG_BANK reserved
WLONG reserved
CFG3 Register (Address 0xAC)
Figure 83:
CFG 3 Register
Addr: 0xAC
Bit
7:5
Bit Name
reserved
CFG3
Default
0
4
3:0
SAI reserved
0
0
0
CFG0
Default
0
Access Bit Description
RW
RW
Register Bank Access
0: Register access to register 0x80 and above
1: Register access to register 0x60 to 0x74
Note: Bit needs to be set to access registers 0x60 to
0x74. If registers 0x80 and above needs to be accessed bit needs to be set to “0”. reserved
Trigger Long.
Increases the WTIME setting by a factor of 16. reserved
0
0xC
Access Bit Description
RW reserved
Sleep after interrupt.
If set, the oscillator is turned off whenever an interrupt is active. SAI_ACTIVE is set in this event.
To activate the oscillator again, clear all interrupts and clear the SAI_ACTIVE bit. reserved
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CFG6 Register (Address 0xAF)
Figure 84:
CFG 6 Register
Addr: 0xAF
Bit Bit Name
CFG6
Default
4:3 SMUX_CMD 2
AS7341
Register Description
Access Bit Description
RW
SMUX command.
Selects the SMUX command to execute when setting SMUXEN gets set. Do not change during ongoing SMUX operation.
VALUE
0
SMUX_CMD
ROM code initialization of SMUX
1
2
3
Read SMUX configuration to RAM from SMUX chain
Write SMUX configuration from
RAM to SMUX chain
Reserved, do not use
CFG9 Register (Address 0xB2)
Figure 85:
CFG 9 Register
5
4
3:0
Addr: 0xB2
Bit
7
Bit Name
reserved
6 SIEN_FD reserved
SIEN_SMUX reserved
0
CFG9
Default
0
0
Access Bit Description
RW
RW reserved
System Interrupt Flicker Detection.
Enables system interrupt when flicker detection status change has occurred. reserved
System Interrupt SMUX Operation.
Enables system interrupt when SMUX command has finished reserved
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PERS Register (Address 0xBD)
Figure 86:
PERS Register
Addr: 0xBD
Bit
7:4
Bit Name
reserved
PERS
Default
0
3:0 APERS 0
AS7341
Register Description
Access Bit Description
RW
4
5
…
14
15
1
2
3 reserved
Spectral Interrupt Persistence.
Defines a filter for the number of consecutive occurrences that spectral data must remain outside the threshold range between SP_TH_L and
SP_TH_H before an interrupt is generated. The spectral data channel used for the persistence filter is set by SP_TH_CHANNEL. Any sample that is inside the threshold range resets the counter to 0.
VALUE CHANNEL
0
2
3
Every spectral cycle generates an interrupt
1
5
10
5 x (APERS
– 3)
55
60
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AS7341
Register Description
10.2.9 FIFO Buffer Data and Status
The FIFO buffer is used to poll spectral data with fewer I²C read and write transactions. The FIFO buffer is 256 bytes of RAM containing 128 two-byte datasets. If the FIFO overflows (i.e. 129 datasets before host reads data from the FIFO buffer), an overflow flag will be set and new data will be lost.
The Host acquires data by reading addresses: 0xFE
– 0xFF. The register address pointer automatically wraps from 0xFF to 0xFE as data are read. Data can be read one byte at a time or in blocks, (there is no block-read length limit). When reading single bytes, the internal FIFO read pointer and the FIFO Buffer Level, FIFO_LVL, are updated each time register 0xFF is read. For block-reads, the internal FIFO read pointer and the FIFO Buffer Level, FIFO_LVL update for each two-byte entry. If the FIFO continues to be accessed after FIFO_LVL = 0, the device will return 0 for all data. The FINT interrupt indicates when there is valid data in the FIFO buffer. The amount of unread data is indicated by the FIFO_LVL.
FIFO_MAP Register (Address 0xFC)
Figure 87:
FIFO_MAP Register
Addr: 0xFC
Bit
7
6
5
4
3
2
1
0
Bit Name
reserved
FIFO_MAP
Default
0
FIFO_WRITE_CH5_DATA 0
FIFO_WRITE_CH4_DATA 0
FIFO_WRITE_CH3_DATA 0
FIFO_WRITE_CH2_DATA 0
FIFO_WRITE_CH1_DATA 0
FIFO_WRITE_CH0_DATA 0
FIFO_WRITE_ASTATUS 0
Access Bit Description
RW
RW
RW
RW
RW
RW
RW reserved
FIFO write CH5 Data.
If set, CH5 data is written to the FIFO Buffer. (two bytes per sample)
Note: If flicker detection is enabled, this bit is ignored. Refer to register 0xD7 for FDEN=”1”.
FIFO write CH4 Data.
If set, CH4 data is written to the FIFO Buffer. (two bytes per sample)
FIFO write CH3 Data.
If set, CH3 data is written to the FIFO Buffer. (two bytes per sample)
FIFO write CH2 Data.
If set, CH2 data is written to the FIFO Buffer. (two bytes per sample)
FIFO write CH1 Data.
If set, CH1 data is written to the FIFO Buffer. (two bytes per sample)
FIFO write CH0 Data.
If set, CH0 data is written to the FIFO Buffer. (two bytes per sample)
FIFO write Status.
If set, ASTATUS (one byte per sample) is written to the FIFO Buffer.
In case SP_AGC_ENABLE = 1, ASTATUS should be written to FIFO buffer.
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FIFO_CFG0 Register (Address 0xD7)
Figure 88:
FIFO_CFG0 Register
Addr: 0xD7
Bit Bit Name
7
6:0
FIFO_WRITE_FD reserved
AS7341
Register Description
FIFO_CFG0
Default
0
0100001
Access Bit Description
R/W
FIFO write Flicker Detection
If set flicker raw data is written into FIFO (two bytes per sample)
Note: This bit is ignored if flicker detection is disabled. Refer to register 0xFC for FDEN=”0”.
Reserved, do not change
FIFO_LVL Register (Address 0xFD)
Figure 89:
FIFO_LVL Register
Addr: 0xFD
Bit Bit Name
7:0 FIFO_LVL
FIFO_LVL
Default
0
Access Bit Description
R
FIFO Buffer Level.
Indicates the number of entries (each are 2 bytes) available in the FIFO buffer waiting for readout. The
FIFO RAM is 256byte, the FIFO_LVL range is from 0 entries to 128 entries.
FDATA Register (Address 0xFE and 0xFF)
Figure 90:
FDATA Register
Addr: 0xFE
Bit
7:0
Bit Name
FDATA
FDATA
Default
0
Access Bit Description
R FIFO Buffer Data
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Figure 91:
FDATA Register
Addr: 0xFF
Bit
15:8
Bit Name
FDATA
Document Feedback
FDATA
Default
0
Access Bit Description
R FIFO Buffer Data
AS7341
Register Description
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AS7341
Application Information
11 Application Information
Figure 92 shows an example how AS7341 can be utilized to interface to an external InGaAs
photodiode. GPIO2 is mapped to an internal ADC.
11.1 Schematic
Figure 92:
Application Example with External InGaAs Detector
MCU
2.7V–5.5V
Filter tuning
VCC
EN
LX
AS1340
FB
GND
25-40V
1.8V
1.8V
VDD
PGND
GND
AS7341
SCL
SDA
INT
8CH VIS
NIR/CLE AR
350-100 0nm sensor
GPIO
LDR
Temperature supervision ligh t in
UP-MIR
InGaAS-Anode light source
InGaAs sensor
1.55
–1.85µm NIR
C13272-02 light in reflective surface
LOW-MIR
CASE
InGaAS-Cathode
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11.2 PCB Pad Layout
Figure 93:
Recommended PCB Pad Layout
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AS7341
Application Information
(1)
(2)
(3)
All dimensions are in millimeters.
Dimension tolerances are 0.05mm unless otherwise noted.
This drawing is subject to change without notice.
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AS7341
Application Information
11.3 Application Optical Requirements
For optimal performance, an achromatic diffuser shall be placed above the device aperture. The recommended solution is a bulk diffuser that meets the minimum recommended scattering characteristic shown below. For more details refer to the optical design guide or contact ams.
Figure 94:
Diffuser Characteristics
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12 Package Drawings & Markings
Figure 95:
OLGA8 Package Outline Drawing
AS7341
Package Drawings & Markings
(1)
(2)
(3)
(4)
RoHS
All dimensions are in millimeters. Angles in degrees.
Dimensioning and tolerance conform to ASME Y14.5M-1994.
This package contains no lead (Pb).
This drawing is subject to change without notice.
Green
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13 Tape & Reel Information
Figure 96:
AS7341 OLGA8 Tape Dimensions
AS7341
Tape & Reel Information
(1)
(2)
All dimensions are in millimeters. Angles in degrees.
This drawing is subject to change without notice.
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Figure 97:
AS7341 OLGA8 Reel Dimensions
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AS7341
Tape & Reel Information
(1)
(2)
All dimensions are in millimeters. Angles in degrees.
This drawing is subject to change without notice.
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AS7341
Soldering & Storage Information
14 Soldering & Storage Information
Figure 98:
Solder Reflow Profile Graph
Figure 99:
Solder Reflow Profile
Parameter
Average temperature gradient in preheating
Soak time
Time above 217 °C (T1)
Time above 230 °C (T2)
Time above T peak
– 10 °C (T3)
Peak temperature in reflow
Temperature gradient in cooling
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Reference
t soak t
1 t
2 t
3
T peak
Device
2.5 °C/s
2 to 3 minutes
Max 60 s
Max 50 s
Max 10 s
260 °C
Max −5 °C/s
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Soldering & Storage Information
14.1 Storage Information
14.1.1 Moisture Sensitivity
Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package.
To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use.
14.1.2 Shelf Life
The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions:
●
●
●
Shelf Life: 12 months
Ambient Temperature: <40°C
Relative Humidity: <90%
Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity
Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region.
14.1.3 Floor Life
The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
●
●
●
Floor Life: 168 hours
Ambient Temperature: <30°C
Relative Humidity: <60%
If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing.
14.1.4 Rebaking Instructions
When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.
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Revision Information
15 Revision Information
Document Status
Product Preview
Product Status Definition
Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice
Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice
Datasheet Production
Datasheet
(discontinued)
Discontinued
Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade
Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs
Changes from previous version to current revision v3-00 Page
-added figure 7 6
●
●
-fixed typos and document maintenance ALL
Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
Correction of typographical errors is not explicitly mentioned.
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AS7341
Legal Information
16 Legal Information
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved.
The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams
AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additi onal processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
RoHS Compliant & ams Green Statement
RoHS Compliant:
The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br/Cl):
ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material).
Important Information:
The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Please visit our website at www.ams.com
Buy our products or get free samples online at www.ams.com/Products
Technical Support is available at www.ams.com/Technical-Support
Provide feedback about this document at www.ams.com/Document-Feedback
For sales offices, distributors and representatives go to www.ams.com/Contact
For further information and requests, e-mail us at [email protected]
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