AMS AS3418 Audio Datasheet

Datasheet

DS000507

AS3418

Low Noise ANC Solution

v4-00

• 2020-Jan-23

Document Feedback

AS3418

Content Guide

Content Guide

3

3.1

3.2

4

5

6

6.1

6.2

6.3

6.4

6.5

6.6

6.7

1

1.1

1.2

1.3

2

General Description ....................... 3

Key Benefits & Features .............................. 3

Applications .................................................. 4

Block Diagram .............................................. 4

Ordering Information ..................... 5

Pin Assignment ............................. 6

Pin Diagram .................................................. 6

Pin Description ............................................. 6

Absolute Maximum Ratings .......... 9

Electrical Characteristics ............ 10

Functional Description ................ 12

Audio Line Input ......................................... 12

Microphone Inputs ...................................... 13

Microphone Supply .................................... 19

Headphone Amplifier .................................. 21

Music Bypass Switch ................................. 25

Operational Amplifier .................................. 28

System ....................................................... 30

7

7.1

7.2

8

6.8

Operation Modes ....................................... 33

6.9

V

NEG

Charge Pump .................................... 38

6.10

EEPROM .................................................... 39

6.11

Production Trimming Interface ................... 41

6.12

I

2

C Interface ............................................... 42

Register Description ................... 47

Register Overview ...................................... 47

Detailed Register Description .................... 49

Application Information .............. 70

8.1

8.2

9

Schematic .................................................. 70

External Components ................................ 72

Package Drawings & Markings ... 74

10

11

Revision Information ................... 76

Legal Information ........................ 77

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 2

Document Feedback

AS3418

General Description

1 General Description

The AS3418 speaker driver with Ambient Noise Cancelling function for headsets, headphones or ear pieces. They are intended to improve quality of e.g. music listening, a phone conversation etc. by reducing background ambient noise.

The fully analog implementation allows the lowest power consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP implementations.

The device is designed to be easily applied to existing architectures.

An internal EEPROM can be optionally used to store the microphones gain calibration settings. The

AS3418 can be used in different configurations for best trade-off of noise cancellation, required filtering functions and mechanical designs.

The AS3418 targeting feed-forward topology is used to effectively reduce frequencies typically up to 2-

3 kHz. The typical bandwidth for a feed-forward system is from 20Hz up to 3 kHz which is lower than the feed-forward systems.

The filter loop for the system is determined by measurements, for each specific headset individually, and depends very much on mechanical designs. The gain and phase compensation filter network is implemented with cheap resistors and capacitors for lowest system costs.

1.1 Key Benefits & Features

The benefits and features of AS3418, Low Noise ANC Solution , are listed below:

Figure 1:

Added Value of Using AS3418

Benefits

Low Noise Floor

Integrated Music Bypass Switch

Smallest ANC form factor

Reprogrammable ANC settings

Features

Low Noise Amplifiers

Depletion mode transistors for passive music bypass

WL-CSP package 2.645mm x 2.545mm; 0.4mm pitch

EEPROM Memory for system settings

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 3

1.2 Applications

●

Ear Pieces

●

Headsets

●

Hands-Free Kits

●

Mobile Phones

●

Voice Communicating Devices

Document Feedback

AS3418

General Description

1.3 Block Diagram

The functional blocks of this device are shown below:

Figure 2 :

Functional Blocks of AS3418

Music Input

Left ANC

Microphone

V

MIC

C

MICL

R

MICL

Right ANC

Microphone

V

MIC

C

MICR

R

MICR

TRSDA

TRSCL

LINR

BPR

MICR

MICL

BPL

LINL

C

ACL

C

ACR

MUTE

EEPROM

MUTE

C

FLY

Left ANC Filter

C

VNEG

V

NEG

Charge Pump

VBAT

C

VBAT

V

BAT

Music Bypass

AS3418

ANC

Processing

HPL

AGND

HPR

ILED

Music Bypass

I2C

On/Off/Monitor/PBO

V

MIC

C

MICS

MSUP

C

MSUP

Right ANC Filter

Button Control or

I2C Communication

V

BAT

Speaker Left

Speaker Right

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 4

Document Feedback

2 Ordering Information

Ordering Code

AS3418-EWLT

AS3418-EWLM

Package

WL-CSP

WL-CSP

Marking

AS3418

AS3418

AS3418

Ordering Information

Delivery Form Delivery Quantity

Tape & Reel

Tape & Reel

6500 pcs/reel

500 pcs/reel

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 5

Document Feedback

3 Pin Assignment

AS3418

Pin Assignment

3.1 Pin Diagram

Figure 3 :

Pin Assignment AS3418

A1

IOP1R

A2

QMICR

A3

MICR

A4

VNEG

A5

GND

B1

BPR

C1

VNEG

D1

BPL

B2

HPR

C2

QOP1R

D2

HPL

B3

MICACR

C3

QOP1L

B4

CPN

C4

CPP

D3

MICACL

D4

TRSDA

B5

LINR

C5

ANC/

CSDA

D5

AGND

E1

IOP1L

E2

QMICL

E3

MICL

E4

MICS

E5

MSUP

A6

VBAT

B6

LINL

C6

MODE/

CSCL

D6

TRSCL

E6

ILED

3.2 Pin Description

Figure 4:

Pin Description of AS3418

Pin Number Pin Name Pin Type

(1)

A1

A2

A3

IOP1R

QMICR

MICR

ANA IN

ANA OUT

ANA IN

A4 VNEG SUP OUT

Description

ANC filter OPAMP1 input - right channel.

ANC microphone preamplifier output - right channel.

ANC microphone preamplifier input - right channel.

V

NEG

charge pump output terminal. This output provides the negative amplifier supply voltage for all

OPAMPs and the headphone amplifier.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 6

Document Feedback

AS3418

Pin Assignment


A5

A6

B1

B2

B3

B4

B5

B6

C1

C2

C3

C4

C5

C6

D1

D2

D3

D4

D5

D6

E1

GND

VBAT

BPR

HPR

MICACR

CPN

LINR

LINL

VNEG

QOP1R

QOP1L

CPP

ANC/

CSDA

MODE/

CSCL

BPL

HPL

MICACL

TRSDA

AGND

TRSCL

IOP1L

ANA IN

SUP IN

ANA IN

(1)

ANA OUT

ANA OUT

ANA OUT

ANA IN

ANA IN

SUP OUT

ANA OUT

ANA OUT

ANA OUT

DIG IN/OUT

DIG IN

ANA IN

ANA OUT

ANA OUT

ANA IN

ANA IN

ANA IN

ANA IN

Description

V

NEG

charge pump ground terminal.

Positive supply terminal of AS3418.

Right audio bypass switch input. This pin features a music bypass function for the right audio channel in off mode operation in order to replace and external analog switch.

Headphone amplifier output - right channel.

Microphone preamplifier AC coupling ground terminal. This pin requires a typ. 10µF capacitor connected to AGND pin.

V

NEG

charge pump negative terminal for flying capacitor

Line input - right channel.

Line input - left channel.

V

NEG

charge pump output terminal. This output provides the negative amplifier supply voltage for all

OPAMPs and the headphone amplifier.

ANC filter OPAMP1 output - right channel

ANC filter OPAMP1 output - left channel

V

NEG

charge pump positive terminal for flying capacitor

Serial interface data signal line for I

2

C interface and alternatively ANC control to enable/disable ANC.

Serial Interface clock signal line for I

2

C interface and alternatively control pin for power up/down and

Monitor mode.

Left audio bypass switch input. This pin features a music bypass function for the left audio channel in off mode operation in order to replace and external analog switch.

Headphone amplifier output - left channel.

Microphone preamplifier AC coupling ground terminal. This pin requires a typ. 10µF capacitor connected to AGND pin.

Data input for production trimming. Can be connected to LINL pin to enable production trimming via 3.5mm audio jack.

Analog reference ground. Do not connect this pin to power or digital ground plane.

Clock input for production trimming. Can be connected to LINR pin to enable production trimming via 3.5mm audio jack.

ANC filter OPAMP1 input - left channel

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 7

Document Feedback

AS3418

Pin Assignment


(1)

Description

E2

E3

E4

E5

QMICL

MICL

MICS

MSUP

ANA OUT

ANA IN

SUP OUT

SUP IN/OUT

ANC microphone preamplifier output - left channel

ANC microphone preamplifier input - left channel

Microphone Supply output to source analog ECM via a bias resistor or MEMs microphones. This pin needs an output blocking capacitor with 4.7µF.

In default configuration a charge pump output that provides the power for the low noise microphone supply LDO. The internal charge pump can also be disabled the MSUP serves as a supply input terminal to source the low noise microphone supply

LDO.

E6

(1)

ILED ANA IN

Current sink input for on-indication LED. The

Cathode of an LED can be directly connected to this terminal without the need of an external current limitation resistor.

Explanation of abbreviations:

ANA IN Analog Input

ANA OUT

DIG IN

SUP IN/OUT

SUP IN

SUP OUT

Analog Output

Digital Input

Supply input or supply output pad

Supply input terminal

Supply output terminal

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 8

Document Feedback

AS3418

Absolute Maximum Ratings

4 Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 5

Absolute Maximum Ratings of AS3418

Symbol Parameter Min Max Unit Comments

Electrical Parameters

V

SUP_MAX

Supply Voltage to Ground

V

GND_MAX

V

NEG_MAX

V

CP_MAX

V

HP_MAX

V

ANA_MAX

V

CON_MAX

V

OTHER_MAX

Ground Terminals

Negative Terminals

Charge Pump Terminals

Headphone Pins

Analog Pins

Control Pins

Other Pins

-0.5

-0.5

-2.0

V

NEG

- 0.5

V

NEG

- 0.5

V

NEG

- 0.5

V

NEG

- 0.5

V

NEG

- 0.5

2

+0.5

0.5

V

POS

+ 0.5

V

POS

+ 0.5

V

POS

+ 0.5

5

5

V

V

V

V

V

V

V

V

Applicable for pin VBAT

Applicable for pin AGND and GND

Applicable for pin VNEG

Applicable for pins CPN and CPP

Applicable for pins HPR and HPL

Applicable for pins LINL,

LINR, MICL/R, HPR, HPL,

QMICL/R, IOP1x, QOP1x,

CPP, CPN, TRSCL, BPR,

TRSDA, BPL, MICACL and MICACR

Applicable for pins

ANC/CSDA and

MODE/CSCL

Applicable for pins MICS and MICFB

I

SCR

Input Current (latch-up immunity)

Electrostatic Discharge

ESD

HBM

Electrostatic Discharge HBM

Temperature Ranges and Storage Conditions

± 100

± 2000 mA

V

Class II JEDEC JESD78D

Norm: JS-001-2014

T

J

T

STRG

T

BODY

Operating Junction Temperature

Storage Temperature Range

Package Body Temperature

- 55

85

125

260

°C

°C

°C IPC/JEDEC J-STD-020

(1)

RH

NC

Relative Humidity (noncondensing)

5 85 %

MSL

(1)

Moisture Sensitivity Level 1 Unlimited floor lifetime

The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020

“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for Pbfree leaded packages is “Matte Tin” (100% Sn)

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 9

Document Feedback

AS3418

Electrical Characteristics

5 Electrical Characteristics

V

BAT

= 1.4V to 1.8V, T

A

= -20ºC to 85ºC. Typical values are at V

BAT

= 1.6V, T

A

= 25ºC, unless otherwise specified. All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods.

Figure 6:

Electrical Characteristics of AS3418

Symbol Parameter Conditions

T

A

Ambient Temperature

Range

Supply Voltages

GND

V

BAT

V

NEG

V

ANALOG

Reference Ground

Battery Supply Voltage

Charge Pump Voltage

Normal Operation

V

DELTA

Difference of Ground

Supplies GND, AGND

To achieve good performance, the negative supply terminals should be connected to a low impedance ground plane.

Other Pins

V

MICS

Microphone Supply Voltage Applicable to MICS pin

Analog Pins

MICACL, MICACR,LINR, LINL, HPR,

HPL, QMICL, QMICR, IOP1x, and

QOP1x

V

V

CONTROL

CP

Control Pins

Charge Pump Pins

Applicable to MODE/CSCL and

ANC/CSDA pins

Applicable to CPN and CPP pins

V

TRIM

Application Trim Pins Applicable to TRSCL and TRSDA pins

V

BYP

V

MIC

Microphone Inputs

Block Power Requirements

I

OFF

Off mode current

I

SYS

I

MIC

Bypass Pins

Reference supply current

Microphone gain stage current

Applicable to BPR and BPL pins

Applicable to MICL and MICR pins.

MODE/CSCL pin low, device switched off

V

BAT

= 1.8V; Bias generation, oscillator,

POR and V

NEG

V

BAT

= 1.4V; Bias generation, oscillator,

POR and V

NEG

V

BAT

= 1.8V; no signal, stereo, High quality mode

V

BAT

= 1.8V; no signal, stereo, ECO mode

V

BAT

= 1.4V; no signal, stereo, High quality mode

Min Typ Max Unit

-20 85 °C

0

1.4

-1.8

1.6

-0.1

0

V

NEG

0

V

NEG

V

NEG

-

0.3 or -1.8

V

NEG

-

0.3 or -1.8

V

NEG

0.1 V

1

1.45

5

1

0.97

0.68

0.92

0

1.8

-1.2

V

V

V

3.6 V

V

BAT

V

3.7 V

V

BAT

V

BAT

+0.5 or 1.8

V

BAT

+0.5 or 1.8

V

BAT

V

V

V

V mA mA mA

µA mA mA

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 10

Document Feedback

AS3418

Electrical Characteristics


I

HP

I

OP1

Headphone stage current

ANC Filter OPAMP current

V

BAT

= 1.4V; no signal, stereo, ECO mode

V

BAT

= 1.8V; no signal, high quality mode

V

BAT

= 1.8V; no signal, ECO mode

V

BAT

= 1.4V; no signal, high quality mode

V

BAT


V

BAT

= 1.8V; OP1L and OP1R enabled,

High quality mode

V

BAT


ECO mode

V

BAT


High quality mode

I

MICS

I

MICS_CP

Microphone low noise LDO supply current

Microphone supply charge pump current

V

BAT


ECO mode

V

BAT

= 1.8V; no load; high quality mode

V

BAT

= 1.4V; no load; high quality mode

V

BAT

= 1.8V; no load; ECO mode

V

BAT

= 1.4V; no load; ECO mode

V

BAT

= 1.8V; no load

V

BAT

= 1.4V; no load

Typical System Power Consumption

P

FF

Typical power consumption feed forward application in high quality mode configuration

V

BAT

= 1.8V; OP1L, OP1R enabled,

250µA microphone load; all amplifiers in high quality mode

V

BAT


250µA microphone load; all amplifiers in high quality mode

P

FF_ECO

Typical power consumption feed forward application in

ECO mode configuration

V

BAT


250µA microphone load; all amplifiers in

ECO mode

V

BAT


250µA microphone load; all amplifiers in

ECO mode


0.63

2.9

2.4

2.78

2.32

1

0.7

0.95

0.65

0.69

0.67

0.33

0.32

0.3

0.26

15

10.7

12.4

8.8 mA mA mA mA mA mA mA mA mA mW mW mW mW mA mA mA mA mA mA

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 11

Document Feedback

6 Functional Description

This section provides a detailed description of the device related components.

AS3418

Functional Description

6.1 Audio Line Input

The chip features one stereo line input for music playback. In monitor mode the line inputs can also be muted in order to interrupt the music playback and increase speech intelligibility.

Figure 7:

Stereo Line Input

Music Left

C

LIN

LINL

R

LIN

MUTE to left headphone amplifier

Music Right

C

LIN

LINR

R

LIN

MUTE to right headphone amplifier

If there is a high pass function desired in an application, to block very low frequencies that could harm the speaker or eliminate little offset voltages, a series capacitor C

LIN

can support this function. The

implementation is shown in Figure 7. The correct capacitor value for the desired cut-off frequency can

be calculated with the following formula:

Equation 1:

𝐶

𝐿𝐼𝑁

1

=

2 ∗ 𝜋 ∗ 𝑅

𝐿𝐼𝑁

∗ 𝑓 𝑐𝑢𝑡−𝑜𝑓𝑓

A typical cut-off frequency in an audio application is 20Hz. With an input impedance RLIN of typ. 1k

Ω and a desired cut off frequency of 20Hz the input capacitor should be bigger than 8µF. Therefore a typical value of 10µF is recommended.

6.1.1 Parameter

V

BAT

=1.65V, T

A

= 25ºC unless otherwise specified.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 12

Document Feedback

Figure 8:

Parameter of Line Input

Symbol Parameter

V

LIN

R

LIN

A

MUTE

Input Signal Level

Input Impedance

Mute Attenuation

Conditions

AS3418



V

BAT

*

0.9

100

1

V

BAT

V

PEAK k

Ω dB

6.2 Microphone Inputs

The AS3418 offers two low noise microphone inputs with full digital control and a dedicated DC offset cancellation pin for each microphone input. In total each gain stage offers up to 63 gain steps of 0.5dB resulting in a gain range from 0dB to +31dB. The microphone gain is stored digitally during production, in an EEPROM memory on the ANC chip. Besides the standard microphone gain register for left and right channel, the chip features also four additional microphone gain registers for Monitor- and

Playback Only operation mode. Thus, in Monitor/Playback Only mode, a completely different gain setting for left and right microphone can be selected to implement voice filter functions in order to amplify the speech band for better intelligibility.

Figure 9:

Stereo Microphone Inputs

MICL

MUTE

DISCHARGE

AGC

QMICL

MICACL

MICACR

DISCHARGE

MICR

AGC

QMICR

MUTE

To avoid unwanted start-up pop noise, a soft-start function is implemented for an automatic gain ramping of the device. In case of an overload condition on the microphone input (e.g. high sound pressure level) there is also an automatic gain control (AGC) function available which reduces the gain to a moderate level. For some designs it might be useful to switch off this feature. Especially in feedback systems infrasound can cause an overload condition of the microphone preamplifier that results in low frequency noise which can be avoided by disabling the AGC.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 13

6.2.1

Document Feedback

AS3418


Input Capacitor Selection

The microphone preamplifier needs a bias resistor (R

Bias

) per channel as well as DC blocking capacitors (C

MIC

). The capacitors C

AC

are DC blocking capacitors to avoid DC amplification of the noninverting microphone preamplifier. This capacitor has an influence on the frequency response because the internal feedback resistors create a high pass filter. The typical application circuit is shown in

Figure 10 with all necessary components.

Figure 10:

Microphone Capacitor Selection Circuit

MICS

R

BIAS

C

MIC

MICL

MUTE

ANC Microphone R

MICIN

C

AC

MICACL

DISCHARGE

R2

R1

AGC

QMICL

MICACR

ANC Microphone

C

MIC

MICS

R

BIAS

C

AC

R

MICIN

MICR

DISCHARGE

MUTE

R1

R2

AGC

QMICR

The corner frequency of this high pass filter is defined with the capacitor C

AC

and the gain of the

headphone amplifier. Figure 11 shows an overview of typical cut-off frequencies with different

microphone gain settings.

Figure 11:

Microphone Cut-Off Frequency Overview

Microphone Gain

0dB

3dB

6dB

9dB

12dB

15dB

R

1

22.2k

Ω

15716Ω

11126Ω

7877Ω

5576Ω

3948Ω

R

2

0

Ω

6484Ω

11074Ω

14323Ω

16623Ω

18252Ω

f cut-off

1.7Hz

1.9Hz

2.2Hz

2.7Hz

3.5Hz

4.5Hz

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 14

Document Feedback

AS3418


Microphone Gain

18dB

21dB

24dB

27dB

30dB

R

1

2795Ω

1979Ω

1400Ω

992Ω

702Ω

R

2

19405Ω

20221Ω

20800Ω

21208Ω

21498Ω

f cut-off

6.1Hz

8.4Hz

11.5Hz

16.3Hz

22.7Hz

It is important when doing the ANC filter simulations to include all microphone filter components to incorporate the

gain and phase influence

of these components. In the cut-off frequency overview, capacitor C

AC

was defined as 10µF which results in a rather low cut-off frequency for best ANC filter design. If a different capacitor value is desired in the application, the following formula defines the transfer function of the high pass circuit of the microphone preamplifier:

Equation 2:

|𝐴| =

√4 ∗ 𝐶

2

𝐴𝐶

∗ 𝑓

√4 ∗ 𝐶

2

𝐴𝐶

2

∗ (𝑅

∗ 𝑓

2

1

+ 𝑅

2

∗ 𝑅

2

1

) 2

∗ 𝜋

2

+ 1

∗ 𝜋

2

+ 1

The simplified transfer function does not include the high pass filter defined by CMIC and RMICIN.

With the recommended values of 2.2µF for CMIC and 22kΩ for RMICIN this filter can be neglected because of the very low cut-off frequency of 1.5Hz. The cut-off frequency for this filter can be calculated with the following formula:

Equation 3:

𝑓 𝑐𝑢𝑡−𝑜𝑓𝑓

=

1

2 ∗ 𝜋 ∗ 𝑅

𝑀𝐼𝐶𝐼𝑁

∗ 𝐶

𝑀𝐼𝐶

The simulated frequency response for the microphone preamplifier with the recommended component

values is shown in Figure 12.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 15

Document Feedback

Figure 12 :

Simulated Microphone Frequency Response

AS3418


35

30

25

20

15

10

5

0

-5

10

30dB

24dB

18dB

12dB

6dB

0dB

100 f [Hz]

1k 10k

In applications with PCB space limitations it is also possible to remove the capacitors C

AC

and connect

MICACL and MICACR pins directly to AGND. In this configuration AC coupling of the QMICR and

QMICL signals is recommended.

6.2.2 Parameter

V

BAT

=1.8V, T

A

= 25ºC , C

AC

=10µF, C

MIC

=4.7µF and R

MICIN

=2.2kΩ unless otherwise specified.

Figure 13:

Microphone Parameter

Symbol

V

MICIN_0

V

MICIN_0

Typical maximum

Input Signal Level

SNR

Parameter

Signal to Noise

Ratio

Conditions

Preamplifier gain=0dB, THD <

0.1%

Preamplifier gain=20dB, THD <

0.1%

0dB gain, High quality mode,

AGC disabled


AGC disabled


AGC disabled

0dB gain, ECO mode, AGC disabled



1050

110

119

109

106

117

108 mV mV dB dB dB dB dB

RMS

RMS

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 16

Document Feedback

AS3418



V

NOISE-A

I

A

MIC

MIC

Conditions

A-weighted output noise floor


0dB gain, 20Hz

– 20kHz bandwidth, high quality

10dB gain, 20Hz


20dB gain, 20Hz


0dB gain, 20Hz

– 20kHz bandwidth, ECO mode

10dB gain, 20Hz


20dB gain, 20Hz


Block Current

Consumption

Programmable

Gain

Gain Step Size

Gain Step Precision

V

BAT

= 1.8V; no signal, stereo, normal mode

V

BAT

= 1.8V; no signal, stereo,

ECO mode

V

BAT

= 1.4V; no signal, stereo, normal mode

V

BAT

= 1.4V; no signal, stereo,

ECO mode


105 dB

0

1.3

4.5

13.7

1.4

5

15.7

1

0.7

0.9

0.6

0.5

31

0.2

µV

µV

µV

µV

µV

µV mA mA mA mA dB dB dB

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 17

Document Feedback

Figure 14 :

Microphone Frequency Response (MICACx grounded; C

MIC

=10µF)

35

30

25

20

15

10

5

0

-5

10

30dB

20dB

10dB

0dB

100 1k f [Hz]

10k

Figure 15:

Microphone THD+N vs. V input

High Quality Mode (A-weighted)

100k

1

AS3418


0,1

0,01

0,001

0,0001

10

Vinput [mV]

100

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 18

Document Feedback

Figure 16:

Microphone THD+N vs. V input

ECO Mode (A-weighted)

1

0,1

0,01

0,001

0,0001

10

Vinput [mV]

100

AS3418


6.3 Microphone Supply

The AS3418 features an integrated microphone supply voltage regulator and a charge pump to source the microphone LDO even with a 1.4V chip supply voltage in order to increase the sensitivity of the microphone. The microphone supply charge pump is in default configuration enabled and can be controlled in ANC and Monitor operation mode with register

ANCMON_MICS_CP_ON

bit. For PBO operation mode there is a dedicated control bit

PBO_MICS_CP_ON

.

The output of the charge pump is directly connected to an internal microphone supply ultra-low noise voltage regulator. This low dropout (LDO) regulator is in default configuration enabled and can be controlled with

ANCMON_MICS_ON

bit. The default output voltage of the regulator is 2.9V. If there is a lower output voltage desired in an application the voltage level can be changed via register

MICS_V_SEL

register.

If the AS3418 is connected to a 1.5V battery the input voltage will of course drop during operation because the battery is discharging during operation. In order to make sure the microphone supply

LDO has enough headroom to regulate properly the device features an automatic output voltage adjustment feature. This function makes sure the voltage regulator has enough headroom and adjusts the output voltage of the LDO accordingly.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 19

Document Feedback

AS3418


Figure 17:

Microphone Supply

to microphone

BIAS resistors

MICS

ANCMON_

MICS_ON

M ICS_V_SEL<3:0>

M ICS_V_LEV<3:0>

LDO

ANCM ON_MICS_CP_BYP_EN

MIC

Charge

Pump

ANCMON_MICS_CP_ON

VBAT

C

MICS

C

MSUP

The microphone supply charge pump is also used to switch off the integrated music bypass switch of the AS3418 in active mode. Therefore, during normal operation the microphone supply must not be switched off if the BPL and BPR pins are in use.

6.3.1 Parameter

V

BAT

=1.8V, T

A

= 25ºC, C

MSUP

= 4.7µF and C

MICS

= 4.7µF unless otherwise specified.

Figure 18:

Microphone Supply Parameter

I


V

V

V

MICS

MSUP

Noise-A

MICS

Conditions

Microphone supply

LDO output voltage

V

BAT

= 1.8V; no load; charge pump activated

V

BAT

=1.4V; no load; charge pump activated

Microphone supply charge pump output voltage

V

BAT

= 1.8V; no load; MICS voltage regulator off

V

BAT

= 1.4V; no load; MICS voltage regulator off

Microphone Supply

Noise at MICS output

High quality mode enabled; 1mA load; A-weighted

High quality mode disabled;

1mA load; A-weighted

Current consumption low noise voltage regulator

V

BAT

= 1.8V; no load;

HIQ_EN_MICS_LDO

= 1

V

BAT

= 1.4V; no load;

HIQ_EN_MICS_LDO

= 1


2.9

2.5

3.15

2.7

1.7

2.2

0.69

0.67

V

V

V

V

µV

µV mA mA

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 20

Document Feedback

I

I

Symbol

MICS_CP

OUT

Parameter

Current consumption microphone supply charge pump

Output current

Conditions

V

BAT

= 1.8V; no load;

HIQ_EN_MICS_LDO

= 0

V

BAT

= 1.4V; no load;

HIQ_EN_MICS_LDO

= 0

V

BAT

= 1.8V; MICS voltage regulator off; no load

V

BAT

= 1.8V; MICS voltage regulator off; 1mA load

V

BAT

= 1.4V; MICS voltage regulator off; no load

V

BAT

= 1.4V; MICS voltage regulator off; 1mA load

Charge pump activated

Figure 19:

Microphone Supply Load Characteristic

AS3418



0.33 mA

0.32

0.3

3.5

0.26

3.33

2 mA mA mA mA mA mA

3

2

1

0

1

VBAT=1,4V

VBAT=1.8V

2

I load

[mA]

3 4

6.4 Headphone Amplifier

The headphone amplifier is a true ground output using V

NEG

as negative supply. It is designed to feature an output power of 2x34mW @ 32

Ωload. For higher output requirements, the headphone amplifier is also capable of operating in bridged mode. In this mode the left output is carrying the

inverted signal of the right output shown in Figure 21. With a V

BAT

voltage of 1.8V, a maximum output power of 100mW can be achieved. This is necessary for over- and on ear headsets with higher output power requirements. The amplifier itself features various input sources. The line input signal is directly connected to the headphone amplifier. The input multiplexer supports three different input signals

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 21

Document Feedback

AS3418

Functional Description which can be configured according in the

ANC_HPH_MUX, MON_HPH_MUX

and

PBO_HPH_MUX

registers independently for each operation mode

. The “Open” setting is being used to disable the active noise cancelling function.

Figure 20:

Headphone Amplifier Single Ended

LINR

XXX_HPH_MUX

QMICR

QOP1R open

1kΩ

R

LI N

1kΩ

LINE_MUTE

AGND

LINL

QMICL

QOP1L open

R

LI N

1kΩ

LINE_MUTE

XXX_HPH_MUX

1kΩ

Figure 21:

Headphone Amplifier Differential

LINR

XXX_HPH_MUX

QMICL

QOP1L open

1k

R

LI N

1k

LINE_MUTE

AGND

1kΩ

1kΩ

1k

HPR

HPL

HPR

HPL

1k 1k

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 22

6.4.1

Document Feedback

Parameter

V

BAT

=1.8V, TA= 25ºC, unless otherwise specified.

Figure 22:

Microphone Supply Parameter

AS3418


I

Symbol

R

C

P

P

P

L_HP

L_HP

HP

BRIDGE

HPH

SRRHP

SNR

Parameter Conditions

Load Impedance

Stereo Operation Mode

Mono Operation Mode

Load Capacitance Per channel

V

BAT

= 1.8V; 32

Ω load;

THD<0.1%

Nominal Output

Power Stereo Mode

Nominal Output

Power Differential

Mode

V

BAT

= 1.4V; 32

Ω load;

THD<0.1%

V

BAT

= 1.8V; 16

Ω load;

THD<0.1%

V

BAT

= 1.4V; 16

Ω load;

THD<0.1%

V

BAT

= 1.8V; 32

Ω load;

THD<0.1%

V

BAT

= 1.4V; 32

Ω load;

THD<0.1%

Supply Current

V

BAT

= 1.8V; no input signal, normal mode

V

BAT

= 1.8V; no input signal,

ECO mode

V

BAT

= 1.4V; no input signal, normal mode

V

BAT


Power Supply

Rejection Ratio

1kHz

Signal to Noise

Ratio

High Quality Mode, Line Input -

> HPH stereo in phase test signal; 32Ω load; V

BAT

= 1.8V;

A-weighted

High Quality Mode, Line Input -

> HPH stereo out of phase test signal; 32

Ω load; V

BAT

= 1.8V;

A-weighted

ECO Mode, Line Input -> HPH stereo in phase test signal;

32Ω load; V

BAT

= 1.8V; Aweighted

16

32

Min Typ

32

35

20

55

30

130

75

2.9

2.4

2.8

2.3

100

117

117.5

114

Max Unit

Ω

Ω

100 pF mW mW mW mW mW mW mA mA mA mA dB dB dB dB

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 23

Document Feedback

AS3418



ECO Mode, Line Input -> HPH stereo out of phase test signal;

32Ω load; V

BAT

= 1.8V; Aweighted

A

CHANNEL

Channel Separation 32

Ω load

V

NOISE-A

A-Weighted Output

Noise Floor

High Quality Mode; 32Ω load;

HP_MUX

= nc; LINx connected to ground

ECO Mode; 32Ω load;

HP_MUX

= nc; LINx connected to ground

Min Typ

114.5

93

1.5

2.1

Max Unit

dB dB

µV

µV

Figure 23:

Headphone THD+N vs. Output Power 32Ω

Stereo

– High Quality Mode

1

Vbat = 1.8V

Vbat = 1.4V

0,1

Figure 24:

Headphone THD+N vs. Output Power 32

Ω

Stereo

– ECO Mode

1

0,1

Vbat = 1.8 ECO

Vbat = 1.4V ECO

0,01

0,001

1

Pout [mW]

10

0,01

100

0,001

1

Pout [mW]

10 100

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 24

Document Feedback

Figure 25:


Stereo

– High Quality Mode

1

Vbat = 1.8V

Vbat = 1.4V

0,1

AS3418


Figure 26:

Headphone THD+N vs. Output Power 1

6Ω

Stereo

– ECO Mode

1

Vbat = 1.8 ECO

Vbat = 1.4V ECO

0,1

0,01

0,001

1

Pout [mW]

10

Figure 27:


MONO

– High Quality Mode (1.8//1.4V)

1

Vbat = 1.8V

Vbat = 1.4V

100

0,01

1

Pout [mW]

10

Figure 28:


MONO

–ECO Mode (1.8//1.4V)

1

Vbat = 1.8 ECO

Vbat = 1.4V ECO

100

0,1 0,1

0,01

1 10

Pout [mW]

100 1k

0,01

1 10

Pout [mW]

100 1k

6.5 Music Bypass Switch

If the AS3418 is switched off, the device features a unique feature, which are integrated music bypass switches. These switches can be used to replace a mechanical switch to bypass the music signal in

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 25

Document Feedback

AS3418


off mode or if the headset runs out of battery. Figure 29 shows the basic music playback path of the

AS3418 with a full battery. In this mode the line input signal is feed to the headphone amplifier. The integrated bypass switches are automatically disabled in this operation mode.

Figure 29:

Bypass Mode Inactive

100%

BPL

Music Bypass

3.5mm audio jack

LINL

AGND

LINR

HPL

HPR

BPR

Music Bypass

Figure 30 shows the AS3418 in off mode with an empty battery. This is basically the same use case

as no battery at all. In this mode the internal bypass switch becomes active. The headphone amplifier is not powered because the headset has run out of battery and the bypass switch becomes active.

Thus the music signal coming from the 3.5mm audio jack is routed through the ANC chip, without any power source connected to the device, to the speakers. The integrated bypass switch works even without any battery connected to the device. It helps to reduce BOM costs and PCB area. Furthermore it facilitates new industrial designs to ANC solutions.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 26

Figure 30:

Bypass Mode Active

Document Feedback

AS3418


BPL

Music Bypass

0%

3.5mm audio jack

LINL

AGND

LINR

BPR

HPL

HPR

Music Bypass

6.5.1 Parameter

V

BAT

=0V, T

A

= 25ºC, unless otherwise specified.

Figure 31:

Bypass Switch Parameter


R

SWITCH

Switch resistance Power down

THD

Total Harmonic

Distortion

0dBV input signal, 32

Ω load

0dBV input signal, 16

Ω load


1.2

-85

-79

Ω dB dB

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 27

Document Feedback

Figure 32 :

Bypass THD+N vs. Output Power 32Ω Load

0,1

32 Ohm

0,01

0,001

AS3418


0,0001

1

Pout [mW]

10 100

6.6 Operational Amplifier

The AS3418 offers one general purpose operational amplifier for feed-forward ANC. The amplifier is used to develop the gain- and phase compensation filter for the ANC signal path.

Figure 33:

Operational Amplifier

OP1L

QOP1L

AGND

OP1R

QOP1R

6.6.1 Parameter

V

BAT

=1.8V, T

A

= 25ºC, R input

= R

FB

= 1kΩ unless otherwise specified.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 28

Document Feedback

AS3418


Figure 34:

Operational Amplifier Parameter


V

IN

SNR

Input Signal Level Gain=0dB

10k



load



Gain = 0dB

(1)

,

V

BAT

=1.8V,

High Quality Mode

Signal to Noise

Ratio

10k



load



Gain = 0dB

(1)

,

V

BAT

=1.4V

High Quality Mode

10k



load



Gain = 0dB

(1)

,

V

BAT

=1.8V,

ECO Mode

10k



load



Gain = 0dB

(1)

,

V

BAT

=1.4V,

ECO Mode

I

OP1

Block Current

Consumption

V

BAT

= 1.8V; OP1L and

OP1R enabled; normal mode

V

BAT

= 1.8V; OP1L and

OP1R enabled; ECO mode

V

BAT

= 1.4V; OP1L and

OP1R enabled; normal mode

V

BAT

= 1.4V; OP1L and

OP1R enabled; ECO mode

High Quality Mode

V

NOISE-A

Input Referred

Noise Floor A-

Weighted

ECO Mode

V

C

OFFSET

L

DC offset voltage

Load Capacitance

Gain=0dB

R

L

Load Impedance

A

(1)

LOOP

Open Loop Gain

100MHz

SNR figure measured with 20dB gain to minimize audio analyzer noise floor

1


0.9*V

BAT

V

BAT

V

PEAK

114.5

111.4

113.3

110

1

0.7

0.95

0.65

2.2

2.6

120 dB dB dB dB mA mA mA mA

µV

µV

500 µV

100 pF kΩ dB

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 29

Document Feedback

Figure 35 :

Operational Amplifier Frequency Response

1

0,8

0,6

0,4

0,2

0

-0,2

-0,4

-0,6

-0,8

-1

10

ECO Mode

HighQ Mode

100 1k f [Hz]

Figure 36 :

OPAMP THD+N vs. Frequency

1

HighQ Mode

ECO Mode

0,1

10k 100k

AS3418


0,01

0,001

0,0001

10 100 1k f [Hz]

10k 100k

6.7 System

This chapter describes the power up and power down conditions of AS3418. Furthermore the Start-up sequence of the device is also described in more detail.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 30

6.7.1

Document Feedback

AS3418


Figure 37:

Power Up Conditions

#

1

2 I

Source

MODE/CSCL pin

2

C start condition

Description

Depending on the operation mode the power up/down pin

MODE/CSCL pin behaves differently:

Slider Mode: Mode pin has to be driven high turn on the device. Since the timing can be programmed the value depends also on

POWER_UP_BUT_TIME

register setting. With default configuration of


register typ. button press time is ~16ms.

Full Slider Mode: Mode pin has to be driven high turn on the device.

Since the timing can be programmed the value depends also on





Push Button Mode: Mode pin has to be driven high turn on the device.

Since the timing can be programmed the value depends also on





In I

2

C mode, an I

2

C start condition turns on the device. For this startup function

I2C_MODE

bit must be set in the EEPROM register.

The chip automatically powers down if one of the following conditions arises:

Figure 38:

Power Down Conditions

2

3

#

1

Source Description

I

MODE/CSCL pin

2

C power down command

Depending on the operation mode the power MODE/CSCL pin behaves differently:

Slider Mode: Mode pin has to be driven low for min. 10ms to turn off the device

Full Slider Mode: Mode pin has to be driven low for min. 10ms to turn off the device

Push Button Mode: Mode pin has to be high for the time defined in

PWR_DOWN_BUT_TIME

register to turn off the device.

Power down by serial interface is initiated by clearing the

PWR_HOLD

bit. (Please mind that the

I2C_MODE

bit has to be set before clearing the

PWR_HOLD

bit to enable the I

2

C power down mode)

V

NEG

over current Power down if V

NEG

is higher than the V

NEG

off-threshold.

Start-Up Sequence

The AS3418 has a defined startup sequence. Once the AS3418 MODE pin is pulled high, the device

initiates the automatic startup sequence shown in Figure 39 or Figure 40 depending on the operation

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 31

Document Feedback

AS3418

Functional Description mode. In case the

I2C_MODE

bit is set the device behaves differently during startup compared to normal operation with external slide switch or push button.

Figure 39:

Normal Start-Up Sequence

VBAT

MODE/CSCL

VOL/CSDA

BIAS & OSC ON

VNEG OK

START EEPROM DOWNLOAD

EEPROM READY

Enable MICS charge pump (MSUP)

Enable OPAMPs and MIC Amplifiers

MICS LDO Chargepump OK

MICS LDO OK

Enable Line Zero Cross Comparator

Right Zero Cross Detect

Left Zero Cross Detect

Enable Right Music Bypass

Enable Left Music Bypass

Enable Headphone Right

Enable Headphone Left

Configure HPH_MUX

PWRUP COMPLETE

Fade in MIC Gain

Operating State

Time Axis

0

~10ms

~1ms min. 1.4V

min. 70% V

BAT don‘t care not connected b‘11‘

11

PWR_UP_BUT_TIME

(5ms-2500ms)

MUTE

OFF

~5ms

~40µs masking

~ ~

31ms timeout

ANC_HPH_MUX<1:0>

FADE IN MIC GAIN

START_RAMP_TIME

ANC_MICx_GAIN<6:0>

ANC Operation typ. 52 t

[ms]

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 32

Document Feedback

AS3418


Figure 40:

I

2

C Start-Up Sequence

VBAT

MODE/CSCL

VOL/CSDA

BIAS & OSC ON

VNEG OK

START EEPROM DOWNLOAD

EEPROM READY

I2C_MODE

PWR_HOLD

Enable MICS charge pump (MSUP)

Enable OPAMPs and MIC Amplifiers

MICS LDO Chargepump OK

MICS LDO OK

Enable Line Zero Cross Comparator

Right Zero Cross Detect

Left Zero Cross Detect

Enable Right Music Bypass

Enable Left Music Bypass

Enable Headphone Right

Enable Headphone Left

Configure HPH_MUX

PWRUP COMPLETE

Fade in MIC Gain

Operating State

Time Axis

0 min. 70% V

BAT

PWRUP_HOLD = 1

PWRUP_HOLD = 1 min. 1.4V

~10ms

~1ms

I2C_TIMEOUT = 8ms

~5ms

~40µs masking not connected b‘11‘

11

MUTE

OFF

~ ~

31ms timeout

ANC_HPH_MUX<1:0>

FADE IN MIC GAIN

START_RAMP_TIME

ANC_MICx_GAIN<6:0>

ANC Operation typ. 55 t

[ms]

6.8 Operation Modes

If the AS3418 is in stand-alone mode (no I

2

C control), the device can work in different operation

modes. An overview of the different operation modes is shown in Figure 41.

Figure 41:

Operation Modes

MODE

OFF

ANC

Description

Chip is turned off.

Chip is turned on and active noise cancellation is enabled.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 33

Document Feedback

AS3418


6.8.1

MODE

MONITOR

PBO

Description

In Monitor Mode, a different (normally higher) microphone preamplifier gain can be configured to get an amplification of the ambient noise. To get rid of the low pass filtering needed for the noise cancellation, the headphone input multiplexer can be set to a different (normally to MIC) source to increase speech intelligibility. In addition, the Line Input signal can be muted for further improved intelligibility. If the device is operated in I

2

C mode, it is also possible to enter the monitor mode by setting the

MON_MODE_EN

bit in register 0x03.

The Playback Only mode is a special mode that disables the noise cancelling function and just keeps e.g. line input amplifier or headphone amplifier active.

Certainly this operation mode can also be used as an alternative Monitor or ANC mode with different gain settings.

With the AS3418 design engineers have different options to enter the described operation modes

shown in Figure 41. In addition to the different user interface modes described in the following three

chapters, it is also important to configure the device accordingly. Figure 42 shows the required register

configuration settings to enable the different AS3418 control modes.

Figure 42:

User Interface Control Modes

MODE

Button Mode

Slider Mode

Full Slider Mode

Do not use

Register UI_MODE<1:0>

1

1

0

0

0

1

0

1

Full Slider Mode

Full Slider Mode enables the AS3418 to be connected to two slide switches for Power, ANC and

Monitor Mode control. To enable this operation mode register

UI_MODE

has to be set to ‘d2’. The

typical connection of the slide switches is shown in Figure 43.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 34

Document Feedback

AS3418


Figure 43:

Full Slider Mode

V

BAT

22kΩ

MODE/CSCL

ANC/CSDA

Control Logic

S1

22kΩ 1MΩ

S2

OFF ON MON ANC PBO

In Full Slider Mode the MODE/CSCL pin can detect three different input levels to distinguish between the different operating modes On, Off and Monitor mode. The timing diagram with all relevant

information is shown in Figure 44.

Figure 44:

Full Slider Timing Diagram

Operation Mode

OFF MONITOR OFF ON

>=1.65V

ON

V

BAT

MODE/CSCL Pin

45% - 55% V

BAT

> PWR_UP_BUT_TIME > MON_TIME

> SHUTDOWN_DELAY > MON_TIME

6.8.2 Slider Mode

Slider Mode is similar to Full Slider Mode with the only difference that it is possible to use a push button (S3) to enable and disable the Monitor Mode. In order to enable this operation mode, register

UI_MODE

has to be set to ‘d1’. The typical connection of the slide switches and push button is shown

in Figure 45.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 35

Document Feedback

AS3418


Figure 45:

Slider Mode

V

BAT

22kΩ

MODE/CSCL

ANC/CSDA

Control Logic

S1

S3

22kΩ

S2

ON OFF

MONITOR ANC PBO

The advantage of this mode compared to Full Slider Mode is the automatic hold function of the

Monitor Mode. Once the push button S3 is pressed, the device enters monitor mode. This mode stays active until the user pushes the button again.

Figure 46:

Slider Mode Timing Diagram

Operation Mode

OFF MONITOR OFF ON

>=1.65V

ON

V

BAT

MODE/CSCL Pin

45% - 55% V

BAT

> PWR_UP_BUT_TIME > MON_TIME > MON_TIME

<0.3V

> SHUTDOWN_DELAY

6.8.3 Push Button Mode

Push Button mode allows the user to control the device with a single normally open (NO) push button.

A simple key press (>

PWR_UP_BUT_TIME)

powers up the AS3418. Once the device is running, a long key press (>


) the device down. The device features two configuration registers (

PWR_UP_BUT_TIME

and


) that allows the user to re-configure the power up- and power down button press time. Monitor Mode can be activated with a second, short key press. To avoid unwanted change of operation mode it is also possible to configure the button press time (

MON_TIME

) to enter monitor mode. A timing diagram of this function is shown in Figure

48. If the monitor mode function is not desired, it is possible to deactivate the monitor mode by

clearing the bit

MON_EN

in register 0x0F. The typical connection of the push button to the AS3418 is

shown in Figure 47.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 36

Document Feedback

AS3418


Figure 47:

Push Button Mode

V

BAT

MODE/CSCL

ANC/CSDA

Control Logic

S4

22k

S2

ON/OFF/MONITOR

Figure 48:

Push Button Timing Diagram

Operation Mode

OFF

>65% V

BAT

MODE/CSCL Pin

<35% V

BAT

ANC

> PWR_UP_BUT_TIME

ANC PBO

> MON_TIME

MONITOR

> MON_TIME

ANC OFF

>PWR_DOWN_BUT_TIME

6.8.4 Playback Only Mode

The active noise cancelling feature of the AS3418 can also be disabled with the ANC/CSDA pin. The

ANC/CSDA pin has to be pulled high to enable the ANC function during startup (ANC MODE). If the pin is connected to ground, the chip enters playback only mode (PBO MODE) in which the ANC function can be disabled or an alternative monitor/ANC mode is configured. The functional blocks in this operation mode can be controlled in registers

PBO_MODE0

and

PBO_MODE1

. Typically only the line input amplifiers and the headphone amplifier are enabled in the playback only mode. If this function is not desired you just need to pull the pin high with an external

22kΩ resistor.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 37

Document Feedback

Figure 49:

Playback Only Mode Timing Diagram

Operation Mode

ANC ON

Playback Only Mode

>65% V

BAT

ANC/CSDA Pin

<35% V

BAT

200-400ms

AS3418


ANC ON

200-400ms

6.9 V

NEG

Charge Pump

The V

NEG

charge pump uses one external 2.2µF ceramic capacitor (C

FLY

) to generate a negative supply voltage out of the input voltage to supply all audio related blocks. This allows a true-ground headphone output with no need of external DC-decoupling capacitors.

Figure 50:

V

NEG

Charge Pump

C

FLY

C

VBAT

V

BAT

VBAT

Charge Pump

Connection to audio blocks

VNEG

C

VNEG

V

NEG

The charge pump typically requires an input capacitor C

VBAT

with 4.7µF, an output capacitor C

VNEG

with a capacity of typ. 10µF and a flying capacitor C

FLY

with 2.2µF.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 38

6.9.1

Document Feedback

Parameter

V

BAT

=1.8V, T

A

= 25ºC, unless otherwise specified.

Figure 51:

V

NEG

Charge Pump Parameter


V

IN

V

OUT

C

C

C

VBAT

VNEG

FLY

Input Voltage

Output Voltage

VBAT input capacitor

VNEG output capacitor

Flying capacitor

Conditions

V

BAT

V

NEG

Effective capacitive value



AS3418



1.4 1.6 1.8 V

-1.8 -1 V

1.6 4.7 5.46 µF

3.4 10 12 µF

0.97 2.2 2.86 µF

6.10 EEPROM

The AS3418 features an integrated EEPROM that stores the system configuration data like microphone gain settings and configuration of the different operation modes during power down operation mode. Because the EEPROM is not bit addressable the AS3418 has an additional register bank in parallel to the EEPROM that is loaded with the EEPROM content during startup of the device.

Each time AS3418 is powered up the EEPROM content is loaded to the register bank (0x00

– 0x1D) to configure the AS3418 according to the application requirements. The registers can be accessed via the I

2

C interface for embedded applications and system evaluation purpose. For non-embedded systems were no MCU is in place to configure the device there are two dedicated production trimming signal lines available that allow access to the AS3418 registers and upload/download function of the

EEPROM.

Figure 52:

Register Access

MODE/CSCL

ANC/CSDA

WRITE

READ

AS3418 Register

0x00 – 0x1D

TRSDA

TRSCL

WRITE

READ

EEPROM

Memory

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 39

Document Feedback

AS3418


The EEPROM supports three operation modes:

●

Upload Operation

- The Upload function copies the register content of register 0x01

– 0x1D and stores it permanently to the EEPROM.

●

Download Operation

- The Download function copies the permanently stored EEPROM content to the registers of AS3418 and overwrites the existing register content with the

EEPROM values like it happens during startup of the device.

●

TEST UPLOAD

- The Test Upload function is a feature to trigger a test EEPROM upload.

During this test the device does not write the EEPROM settings, instead it just tries if it would be possible to write the EEPROM successfully. It is recommended to perform this test each time before a real EEPROM upload is triggered.

6.10.1 EEPROM Download Function

In order to trigger an EEPROM Download function (copy EEPROM content to AS3418 system registers) the

EEPROM_DOWNLOAD

bit has to be set in register 0x34. Once the bit is set via I

2

C interface or the production trimming interface the

EE_READY

bit in register 0x01 can be checked if the download of the EEPROM content is finished. As long as the

EE_READY

bit is zero the download process is ongoing. Once the bit is set the download process is completed. A flow chart of the

download is shown in Figure 53.

Figure 53:

EEPROM Download Flow Chart

Set bit

EEPROM_DOWNLOAD

in register 0x34

Check

EE_READY

bit in register 0x01

EE_READY = 1

EEPROM Download complete

EE_READY = 0

6.10.2 EEPROM Upload Function

An EEPROM Upload function can be simply triggered by setting the

EEPROM_UPLOAD

bit in register

0x34. Once the bit is set, the

EE_READY

bit has to be monitored to check the status of the EEPROM.

If the Upload function is completed the

EE_READY

bit is set and the next step in the upload sequence is to check the

EE_WR_OK

bit in the same register 0x01. If the upload process was successfully completed the bit is set to ‘1’. In case the upload failed the bit is set to ‘0’. The flow chart for the

EEPROM Upload sequence is shown in Figure 54.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 40

Document Feedback

AS3418


Figure 54:

EEPROM Upload Flow Chart

Set bit

EEPROM_UPLOAD

in register 0x34

Check

EE_READY


EE_READY = 0

EE_READY = 1

Check

EE_WR_OK


EE_WR_OK = 0

EEPROM Upload failed

EE_WR_OK = 1

EEPROM Upload complete

6.10.3 EEPROM Upload Test Function

Before an EEPROM Upload function is started it is recommended to do first an Upload Test. During this test the device does not write the EEPROM settings, instead it just tries if it would be possible to write the EEPROM successfully. It is checked if the power supply is sufficient to trigger a real

EEPROM Upload.

Figure 55:

EEPROM Upload Test Function

Set bit

EEPROM_UPLOAD_TEST

in register 0x34

Check

EE_READY


EE_READY = 1

Check

EE_WR_OK


EE_WR_OK = 1

EEPROM Upload Test complete

EE_READY = 0

EE_WR_OK = 0

EEPROM Upload Test failed

The sequence for the Upload test function is similar to the real Upload. The only difference is that the

EEPROM_UPLOAD_TEST

bit has to be set to start the upload test instead of the

EEPROM_UPLOAD

bit. The flow chart for the Upload test sequence is shown in Figure 55.

6.11 Production Trimming Interface

In addition to option programming the AS3418 via I2C interface, the AS3418 features a second unique trimming mechanism. This very special mode enables the analog music inputs of the AS3418 to become a digital production trimming input.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 41

Document Feedback

AS3418


Figure 56:

Production Trim Box

LINL

Application Trim Box

TRSDA

TRSCL

MUTE

EEPROM to HPH

AS3418

LINR to HPH

MUTE

With this new system, there is no need for mechanical potentiometers any more. Up to now, operators in production used to use screw drivers to fine tune the ANC performance of each headset. The disadvantage of this is reliability and cost of potentiometers. Additionally, operators are not always precise in their work, thus yielding inconsistent results. With the production trimming system from ams there are no mechanical potentiometers required. The operator connects a 3.5mm audio jack to a trimming box and this box enables the audio input of the headset to become the ANC tuning input.

This new feature also helps industrial designers of headset because there are no more considerations concerning leakage holes for the old mechanical trimming. Thus, the headset can be fully assembled and ready for the ANC test system at the end of the manufacturing process. The trim box can be easily controlled with an USB interface so it is also possible to create fully automated trimming systems. For further details please contact our local sales office; they can provide you with source code examples and application notes.

6.12 I

2

C Interface

In order to configure the device using the evaluation software or a MCU the AS3418 features a serial

two wire interface. The I²C address for the device can be found in Figure 57.

Figure 57:

I

2

C Slave Address

7 bit I2C address

0x47

8 Bit read address

0x8F

8 Bit write address

0x8E

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 42

Document Feedback

6.12.1 Protocol

Figure 58:

I2C Serial Interface Symbol Definition

Symbol

S

Sr

DW

DR

WA

A

N reg_data data (n)

P

WA++

Definition

Start condition after stop

Repeated start

Device address for write

Device address for read

Word address

Acknowledge

No Acknowledge

Register data/write

Register data/read

Stop condition

Increment word address internally

AS3418 (=slave) transmits data

AS3418 (=slave) receives data

Figure 59:

Byte Write

RW

R

W

R

R

R

R

R

R

W

R

R

AS3418


Note

1 bit

1 bit

1000 1110b (8Eh)

1000 1111b (8Fh)

8 bit

1 bit

1 bit

8 bit

8 bit

1 bit during acknowledge

S DW A WA A reg_data A P

WA++

Figure 60:

Page Write

S DW A WA A reg_data 1 A reg_data 2 A ...

reg_data n A P

WA++ WA++ WA++

Byte Write and Page Write formats are used to write data to the slave. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free).

The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes to subsequent address locations.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 43

Document Feedback

AS3418


For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1 st

register byte transmitted from the slave. In Read

Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally.

Figure 61:

Random Read

S DW A WA A Sr DR A data N P

RA++

Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master.

The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address.

In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.

Figure 62:

Sequential Read

S DW A WA A Sr DR A reg_data 1 A reg_data 2 A

RA++ RA++

...

reg_data n N P

RA++

Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. Different from the Random Read, for a sequential read, the transferred register-data bytes are responded with an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and then generate the STOP condition.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 44

Document Feedback

AS3418


Figure 63:

Current Address Read

S DR A data A reg_data 2 A ...

reg_data n N P

RA++ RA++ RA++

To keep the access time as short as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes have to be responded with an acknowledge from the master. For termination of the transmission, the master sends a notacknowledge following the last data byte and a subsequent STOP condition.

6.12.2 Parameter

VBAT =1.8V, T

A

=25ºC, unless otherwise specified.

Figure 64:

I

2

C Serial Timing

TS T

SU

T

H

T

HD

MODE/CSCL

T

L

T

PD

ANC/CSDA

1-7

Start

Condition

Address R/W

9

ACK

1-7

Data

9

ACK

Figure 65:

I

2

C Serial Interface Parameter


V

V

CSL

CSH

HYST

Conditions

CSCL, CSDA Low

Input Level

CSCL, CSDA High

Input Level

CSCL, CSDA Input

Hysteresis

(max 30% V

BAT

)

CSCL, CSDA (min 70% V

BAT

)

1-7

Data

9

ACK Stop

Condition


0 - 0.42 V

1.16 -

450

V mV

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 45

Document Feedback

AS3418



V

T

T

T

T

TS

T

OL

Tsp

H

L

SU

HD

PD

Conditions

CSDA Low Output

Level at 3mA

Spike insensitivity

Clock high time max. 400kHz clock speed

Clock low time max. 400kHz clock speed

CSDA has to change Tsetup before rising edge of CSCL

No hold time needed for CSDA relative to rising edge of CSCL

CSDA H hold time relative to

CSDA edge for start/stop/rep_start

CSDA prop delay relative to low going edge of CSCL

Min

-

Max

0.4

50

500

100 -

500

250 -

0

Typ

-

-

200 -

50

-

-

-

Unit

V ns ns ns ns ns ns ns

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 46

Document Feedback

7 Register Description

AS3418

Register Description

7.1 Register Overview

Figure 66:

Register Overview

Addr Name

System Registers

0x00 ID

0x01

0x02

0x03

0x04

0x05

0x06

0x07

SYSTEM_STATUS

MODE_REG0

MODE_REG1

MICS_VOLTAGE

PUSH_DELAY

ON_DELAY

HIQ_MODE_REG

<D7> <D6> <D5> <D4> <D3>

0x08

0x09

LED_MON

LED_ANC

ANC Mode Control Registers

0x0A ANC_MODE_REG

0x0B

ANC_MIC_LEFT_GAI

N

-

0x0C

ANC_MIC_RIGHT_G

AIN

Monitor Mode Control Registers

-

ANC_HPH_MUX<1

:0>

LIN_MU

TE

-

ANC_MIC_LEFT_GAIN<6:0>

ANC_MIC_RIGHT_GAIN<6:0>

0x0D MONITOR_MODE0

MON_E

N

0

-

MON_LI

N_MUT

E

MON_M

IX_EN

0

0x0E MONITOR_MODE1 - - MON_TIME<1:0> -

-

<D2>

0

-

<D1>

DESIGN_VERSION<3:0> CHIP_ID<3:0>

- - -

EE_WR

_TEST_

OK

EE_RE

ADY

LOBAT

PWRUP

_COMP

LETE

PWR_H

OLD

NO_LO

BAT_O

FF

EN_ZE

RO_CR

OSS

DELAY

_HPH_

MUX

UI_MODE<1:0>

MICS_

DC_EN

HPH_M

ODE

I2C_MO

DE

PBO_M

ODE_E

N

MON_M

ODE_E

N

-

ANCMO

N_MIC

S_CP_

BYP_E

N

ANCMO

N_MIC

S_CP_

ON

ANCMO

N_MIC

S_LDO

_ON

ANCMO

N_MIC_

ON

ANCMO

N_HPH

_ON

MICS_L

DO_CV

_MODE

-

-

T<1:0>

-

-

MICS_L

DO_CD

_MODE

-

-

-

HIQ_ECO_PRESE

PWR_DOWN_BUT_TIME<2:0

>

LDO_BOOST<2:0>

- -

HIQ_EN

_MICS_

LDO

- -

PBO_LED_MODE<

1:0>

MICS_V_SEL<3:0>

PWR_UP_BUT_TIME<2:0>

HIQ_EN

_HPH

MON_LED_MODE<2:0>

-

ANC_LED_MODE<

1:0>

ON_DELAY<2:0>

HIQ_EN

_MIC

HIQ_EN

_OPAM

P

MON_ILED<1:0>

ANC_ILED<1:0>

ANC_O

P1L_O

N

N

MON_O

P1L_O

<D0>

ANC_O

P1R_O

N

MON_O

P1R_O

N

MON_HPH_MUX<

1:0>

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 47

Document Feedback

AS3418


Addr Name <D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0>

0x0F

0x10

MON_MIC_LEFT_GA

IN

MON_MIC_RIGHT_G

AIN

PBO Mode Control Registers

0x11

0x12

PBO_MODE0

PBO_MODE1 -

PBO_E

N

-

HPH_O

N/DIS_

BYPAS

S

PBO_LI

N_MUT

E

PBO_M

ICS_CP

_BYP_

EN

PBO_M

IX_EN

O_ON

PBO_M

ICS_LD

-

PBO_M

ICS_CP

_ON

-

PBO_M

IC_ON

PBO_O

P1L_O

N

PBO_HPH_MUX

<1:0>

PBO_O

P1R_O

N

0x13

PBO_MIC_LEFT_GAI

N

0x14

PBO_MIC_RIGHT_G

AIN

AGC Control Registers

-

-

PBO_MIC_LEFT_GAIN<6:0>

PBO_MIC_RIGHT_GAIN<6:0>

0x15 AGC_CONTROL0

ZERO_

CROSS

_EN

AGC_ATTACK_LE

VEL<1:0>

0x16

AGC_ATTACK_RELE

ASE_TIME

AGC_RELEASE_TIME<3:0>

0x17

0x18

AGC_HOLD

AGC_START_TIME

Operation Mode Control Register

ZERO_TIMEOUT<3:0>

- - -

AGC_RELEASE_L

EVEL<1:0>

- -

AGC_M

UTE_E

N

NEG_A

TT_EN

AGC_ATTACK_TIME<3:0>

HOLD_TIME<3:0>

AGC_E

N

START_RAMP_TIME<2:0>

0x1A

MODE_SWITCH_CO

NTROL

-

-

-

MON_MIC_LEFT_GAIN<6:0>

MON_MIC_RIGHT_GAIN<6:0>

SHUTDOWN_DEL

AY<1:0>

-

MODE_SWITCH_D

ELAY<1:0>

GAIN_J

UMP_U

P_EN

GAIN_J

UMP_D

OWN_E

N

EEPROM Control Register

0x34 EEPROM_CONTROL - - - - -

EEPRO

M_UPL

OAD_T

EST

EEPRO

M_UPL

OAD

EEPRO

M_DO

WNLOA

D

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 48

Document Feedback

AS3418


7.2 Detailed Register Description

7.2.1 System Registers

Figure 67:

ID Register Description

Addr: 0x00

Bit Bit Name

7:4

DESIGN_VER

SION

3:0 CHIP_ID

ID

Default Access Bit Description

0110

0001

R

R

Design version number to identify the design version of the AS3418.

0110: Chip Version 3.0

This register represents the chip ID number of

AS3418.

0001: AS3418

Figure 68:

SYSTEM_STATUS Register Description

Addr: 0x01

Bit Bit Name

4

3

1

0

EE_WR_TEST

_OK

EE_READY

PWRUP_COM

PLETE

PWR_HOLD

SYSTEM_STATUS


-

-

1

1

R

R

R

R/W

This register reports if an EEPROM upload test was successfully finished. This bit is also used for the

EEPROM-Program-Test (together with

EEPROM_UPLOAD_TEST

), where a “dummy-write” can be initialized to check the power-supply

0: EEPROM upload TEST failed

1: EEPROM upload TEST successful

This registers indicates the status after a read/write command of the EEPROM.

0: EEPROM busy

1: EEPROM ready

This bit indicates the Power-Up sequencer status of

AS3418. The signal goes high after all amplifiers are enabled but before the microphone signal is faded in.

0: Power-up sequence incomplete

1: Power-up sequence completed

This bit allows an MCU, using the I

2

C interface, to power down the AS3418. A start condition on the I

2

C interface will wake up the device again. This function

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 49

Document Feedback

AS3418


Addr: 0x01

Bit Bit Name

SYSTEM_STATUS


works only if the

I2C_MODE

bit is set. In case

I2C_MODE

is low, the register content is ignored.

0: Power up hold is cleared and chip powers down

1: Device remains powered on

Figure 69:

MODE_REG0 Register Description

Addr: 0x02 MODE_REG0

Bit

6

5

4:3

2

1

Bit Name

EN_ZERO_C

ROSS

DELAY_HPH_

MUX

UI_MODE

MICS_DC_EN

HPH_MODE


1

0

01

1

0

R/W

R/W

R/W

R/W

R/W

This bit activates zero cross detection while switching between music bypass switch and headphone amplifier.

0: Zero cross detection is disabled.

1: Zero cross detection is enabled.

This register controls the startup delay setting before the

ANC_HPH_MUX

setting is applied to the system.

This function can help to reduce pop noise during startup of the device especially if there are components with long charging times involved. This bit is only valid during initial startup.

0: Headphone MUX delay disabled

1: Headphone MUX delay enabled

This register defines the user interface operation mode of AS3418. For a detailed description of the different user interface modes please refer to chapter

Operation Modes.

00: Push Button Operation Mode

01: Slider Operation Mode

10: Full Slider Operation

11: Do not use

This bit enables the internal microphone supply discharge function if the microphone supply is switched off. The MICS_LDO pin is discharged within

~

10ms.

0: MICS_LDO discharge disabled

1: MICS_LDO discharge enabled

This register controls the operation mode of the headphone amplifier. The headphone amplifier supports single ended mode and differential mode. In differential output mode the right audio signal path is the active input signal for the headphone amplifier.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 50

Document Feedback

AS3418



Bit

0

Bit Name

I2C_MODE


0 R/W

0: Stereo single ended mode

1: Mono differential mode

All registers can be read and written by the I

2

C interface independent on the level of

I2C_MODE

bit but

I2C_MODE

controls whether the main modes of

AS3418 (MON/ANC/PBO/ON/OFF) are controlled by the

MON_MODE_EN

,

PBO_MODE_EN

bits and

SYSTEM_STATUS

registers or by the buttons and switches. Once the bit is set and the system powers up because there’s an I

2

C start condition applied to the CSCL and CSDA pins, the user has to write the

PWR_HOLD

bit within

SHUTDOWN_DELAY

, otherwise AS3418 powers down again.

This can be done either over the CSDA/CSCL or over the application trimming interface.

0: I

2

C mode control functions disabled

1: I

2

C mode control functions enabled

Figure 70:

MODE_REG1 Register Description


Bit

7

6

4

Bit Name

PBO_MODE_

EN

MON_MODE_

EN

ANCMON_MI

CS_BYP_EN


0

0

0

R/W

R/W

R/W

In case

I2C_MODE

bit is not set, the register content is ignored but can be read and written. In case

I2C_MODE

bit is set, this bit controls the operation mode of AS3418 (ANC, MON, PBO). In case the

PBO_MODE_EN

is 1,

MON_MODE_EN

has to be 0.

0: ANC Mode

1: PBO Mode

In case

I2C_MODE

bit is not set, the register content is ignored but can be read and written. In case

I2C_MODE

bit is set, this bit controls the operation mode of AS3418 (ANC, MON, PBO). In case the

PBO_MODE_EN

is 1,

MON_MODE_EN

has to be 0.

0: ANC Mode

1: MON Mode

This bit enables the automatic VBAT to MICS bypass function when the microphone supply charge pump is switched off. This function has to be activated in case the microphone supply voltage regulator is supplied externally via MICS_CP pin.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 51

Document Feedback

AS3418



Bit

3

2

1

0

Bit Name

ANCMON_MI

CS_CP_ON

ANCMON_MI

CS_LDO_ON

ANCMON_MI

C_ON

ANCMON_HP

H_ON


0: MIC charge pump bypass function disabled

1: MIC charge pump bypass function enabled

1 R/W

This bit controls the microphone supply charge pump. The microphone charge pump has a second function besides the bias voltage generation for microphones. It is also used to disable the integrated music bypass switch if the AS3418 is active. In case the integrated bypass switch is used in an application this bit must not be set to ‘0’.

0: Microphone supply charge pump disabled

1: Microphone supply charge pump enabled

WARNING: Microphone supply is also used for disabling the Bypass switch. If Microphone supply is disabled an external supply is required.

1

1

1

R/W

R/W

R/W

This bit controls the microphone supply. In case this bit is set to ‘1’ the microphone supply voltage regulator (MICS output pin) is powered up.

0: Microphone supply switched off

1: Microphone supply switched on

This bit powers up the microphone preamplifier.

0: Microphone preamplifier disabled

1: Microphone preamplifier enabled

This bit allows the user to power down headphone amplifier in case it is not used in the final application in order to save system power.

0: Headphone amplifier disabled

1: Headphone amplifier enabled

Figure 71:

MICS_VOLTAGE Register Description

Addr: 0x04 MICS_VOLTAGE

Bit

7

6

Bit Name

MICS_LDO_C

V_MODE

MICS_LDO_C

D_MODE


-

-

R

R

Signals if the MICS_LDO is in constant voltage mode.

1: Constant voltage mode active

0: Constant voltage mode inactive

Signals if the microphone supply is in constant drop mode

1: Constant drop mode active

0: Constant drop mode inactive

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 52

Document Feedback

AS3418


Addr: 0x04 MICS_VOLTAGE

Bit

3:0

Bit Name

MICS_V_SEL


1011 R/W

This register controls the output voltage of the integrated microphone supply regulator.

0000: 1.6V

0001: 1.7V

0010: 1.8V

0011: 1.9V

0100: 2.0V

0101: 2.1V

0110: 2.2V

0111: 2.3V

1000: 2.4V

1001: 2.5V

1010: 2.6V

1011: 2.7V(default)

1100: 2.8V

1101: 2.9V

1110: Do not use

…

1111: Do not use

Figure 72:

PUSH_DELAY Register Description

Addr: 0x05 PUSH_DELAY

Bit

5:3

Bit Name

PWR_DOWN_

BUT_TIME


111 R/W

This register controls the hold time for the push button in order to power down the AS3418.

Depending on the register setting the power down push button time can be programmed accordingly.

This delay is applied for button, slider and full slider mode.

000: 5ms

001: 500ms

010: 1000ms

011: 1500ms

100: 2000ms

101: 2500ms

110: 2500ms

111: 2500ms

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 53

Document Feedback

AS3418


Addr: 0x05

Bit

2:0

Bit Name

PWR_UP_BU

T_TIME

PUSH_DELAY


000 R/W

This register controls the hold time for the push button in order to power up the AS3418. Depending on the register setting the power up push button time can be programmed accordingly. This delay is applied for button, slider and full slider mode.

000: 5ms

001: 500ms

010: 1000ms

011: 1500ms

100: 2000ms

101: 2500ms

110: 2500ms

111: 2500ms

Figure 73:

ON_DELAY Register Description

Addr: 0x06 ON_DELAY

Bit

5:3

2:0

Bit Name

LDO_BOOST

ON_DELAY


001

000

R/W

R/W

This register controls the pre-charge time of the microphone supply LDO. LDO_BOOST is effective not only during startup but also whenever the LDO is enabled after startup.

000: 0ms

001: 150ms

010: 400ms

011: 600ms

100: 800ms

101: 1000ms

110: 1200ms

111: 1500ms

This register controls the power on delay setting. If this register is set, the device powers up but stays in a Mute mode with the integrated bypass switches deactivated to block unwanted noise at the line input.

000: 0ms

001: 200ms

010: 400ms

011: 600ms

100: 800ms

101: 1200ms

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 54

Document Feedback

AS3418


Addr: 0x06 ON_DELAY

Bit Bit Name Default Access Bit Description

110: 1600ms

111: 2000ms

Figure 74:

ECO_MODE_REG Register Description

Addr: 0x07 ECO_MODE_REG

Bit

7:6

3

2

1

0

Bit Name

HIQ_ECO_PR

ESET

HIQ_EN_MIC

S_LDO

HIQ_EN_HPH

HIQ_EN_MIC

HIQ_EN_OPA

MP


00

1

1

1

1

R/W

R/W

R/W

R/W

R/W

This register allows the device to achieve best offset performance. Depending on the quality settings of headphone amplifier, microphone pre-amplifier and

OP1 the correct preset from the table below has to be configured to ensure lowest offset values.

00: HPH->HIQ; MIC->HIQ; OP1->HIQ

01: HPH->HIQ; MIC->ECO; OP1->ECO

10: HPH->HIQ; MIC->HIQ; OP1->ECO

11: HPH->ECO; MIC->ECO; OP1->ECO

This bit enables the high quality mode of the microphone LDO.

0: High quality function disabled

1: High quality function enabled

This bit enables the high quality mode of the headphone amplifier.



This bit enables the high quality mode of the microphone amplifier.



This bit enables the high quality mode of the operational amplifier amplifiers for ANC filter design.



Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 55

Document Feedback

AS3418


Figure 75:

LED_MON Register Description

Addr: 0x08 LED_MON

Bit

4:2

1:0

Bit Name

MON_LED_M

ODE

MON_ILED


000

00

R/W

R/W

This register controls blinking time of LED in MON mode.

000: LED always on

001: 80ms PWM active / 80ms off







This register controls the integrated LED driver current sink of the AS3418 in Monitor operation mode.

00: ILED current sink switched off

01: 25% duty cycle (4µs on/ 14µs off)



Figure 76:

LED_ANC Register Description

Addr: 0x09

Bit Bit Name

6:5

PBO_LED_M

ODE

3:2

ANC_LED_M

ODE

LED_ANC


00

00

R/W

R/W

Defines the blinking scheme if PBO mode is active.

Please note that PBO mode has not an individual

LED control register. Therefore this setting uses hardcoded 25% PWM duty cycle for brightness.

00: LED always off

01: Blinking scheme as in ANC mode

10: Blinking scheme as in MON mode

11: LED always on (=PWM always active)

This register controls the different LED effects for

ANC mode with various on/off times as well as different flash frequencies.

00: LED always on

01: 80ms on / 1s off

10: 80ms on / 1.5s off

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 56

Document Feedback

AS3418


7.2.2

Addr: 0x09

Bit Bit Name

1:0 ANC_ILED

LED_ANC


11: 80ms on / 2.5s off

00 R/W

This register controls the integrated LED driver current sink of the AS3418 in ANC operation mode.

The typical PWM frequency is 1/18µs=55.6kHz.

00: ILED current sink switched off




ANC Mode Control Registers

Figure 77:

ANC_MODE_REG Register Description

Addr: 0x0A ANC_MODE_REG

Bit

7:6

5

1

0

Bit Name

ANC_HPH_M

UX

LIN_MUTE

ANC_OP1L_O

N

ANC_OP1R_

ON


11

0

0

0

R/W

R/W

R/W

R/W

This register selects the ANC input source for the headphone amplifier in ANC mode. Depending on the register, setting different outputs are routed to the headphone amplifier input. It is also possible to disconnect all ANC input sources which is sometimes desired in monitor mode.

00: QMIC outputs are connected to HPH input

01: OP1 outputs are connected to HPH input

10: Do not use this setting

11: Nothing connected to HPH input except line input in case it is enabled.

This bit mutes the line input signal. If the bit is set the line input signal is disconnected from the headphone amplifier in ANC operation mode.

0: Line input signal enabled

1: Line input signal muted

This register enables the left channel of OPAMP 1 in

ANC operation mode.

0: Left OP1 is switched off

1: Left OP1 is switched on

This register enables the right channel of OPAMP 1 in ANC operation mode.

0: Right OP1 is switched off

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 57

Document Feedback

AS3418


Addr: 0x0A ANC_MODE_REG


1: Right OP1 is switched on

Figure 78:

ANC_MIC_LEFT_GAIN Register Description

Addr: 0x0B ANC_MIC_LEFT_GAIN

Bit

6:0

Bit Name

ANC_MIC_LE

FT_GAIN


101

0111

R/W

Volume settings for left microphone input, adjustable in 63 steps of 0.5dB for ANC operation mode.

000 0000: 0dB

000 0001: 0.5dB gain

000 0010: 1.0dB gain

000 0011: 1.5dB gain

…

011 1110: 31dB gain

011 1111: Do not use

101 0111: MUTE (Mute code if NEG_ATT_EN bit

set)


not set)

Figure 79:

ANC_MIC_RIGHT_GAIN Register Description

Addr: 0x0C

Bit Bit Name

6:0

ANC_MIC_RI

GHT_GAIN

ANC_MIC_RIGHT_GAIN


101

0111

R/W

Volume settings for right microphone input, adjustable in 63 steps of 0.5dB for ANC operation mode.

000 0000: 0dB

000 0001: 0.5dB gain

000 0010: 1.0dB gain

000 0011: 1.5dB gain

…

011 1110: 31dB gain



set)

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 58

Document Feedback

AS3418


7.2.3

Addr: 0x0C

Bit Bit Name

ANC_MIC_RIGHT_GAIN



not set)

Monitor Mode Control Registers

Figure 80:

MONITOR_MODE0 Register Description

Addr: 0x0D MONITOR_MODE0

Bit

7

5

1

0

Bit Name

MON_ EN

MON_LIN_MU

TE

MON_OP1L_

ON

MON_OP1R_

ON


1

1

0

0

R/W

R/W

R/W

R/W

This bit disables the monitor mode function in all operation modes.

0: Monitor mode disabled

1: Monitor mode enabled

This bit enables mute function for the line input in monitor more.

0: Line input enabled in Monitor mode

1: Line input muted in Monitor mode

This register enables the left channel of OPAMP 1 in

MON operation mode.



This register enables the right channel of OPAMP 1 in MON operation mode.



Figure 81:

MONITOR_MODE1 Register Description

Addr: 0x0E MONITOR_MODE1

Bit

5:4

Bit Name

MON_TIME<1:

0>


00 R/W

Time needed to press the monitor switch until monitor mode is activated.

00: 25ms

01: 200ms

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 59

Document Feedback

AS3418


Addr: 0x0E MONITOR_MODE1

Bit Bit Name

1:0

MON_HPH_M

UX<1:0>


00 R/W

10: 400ms

11: 600ms

This register selects the ANC input source for the headphone amplifier in Monitor mode. Depending on the register setting different outputs are routed to the headphone amplifier input. It is also possible to disconnect all ANC input sources which is sometimes desired in monitor mode.

00: QMIC outputs are connected to HPH input


10: Do not use (reserved for OP2)

11: QMIC, OP1 are disconnected from HPH

Figure 82:

MON_MIC_LEFT_GAIN Register Description

Addr: 0x0F MON_MIC_LEFT_GAIN

Bit Bit Name

6:0

MON_MIC_LE

FT_GAIN


101

0111

R/W

Volume settings for left microphone input, adjustable in 63 steps of 0.5dB for Monitor operation mode.

000 0000: 0dB

000 0001: 0.5dB gain

000 0010: 1.0dB gain

000 0011: 1.5dB gain

…

011 1110: 31dB gain



set)


not set)

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 60

7.2.4

Document Feedback

Figure 83:

MON_MIC_RIGHT_GAIN Register Description

AS3418


Addr: 0x10

Bit Bit Name

6:0

MON_MIC_RI

GHT_GAIN

MON_MIC_RIGHT_GAIN


101

0111

R/W

Volume settings for right microphone input, adjustable in 63 steps of 0.5dB for Monitor operation mode.

000 0000: 0dB

000 0001: 0.5dB gain

000 0010: 1.0dB gain

000 0011: 1.5dB gain

…

011 1110: 31dB gain

011 1111: do not use


set)


not set)

PBO Mode Control Registers

Figure 84:

PBO_MODE0 Register Description

Addr: 0x11 PBO_MODE0

Bit

7

5

1

Bit Name

PBO_EN

PBO_LIN_MU

TE

PBO_OP1L_O

N


1

0

0

R/W

R/W

R/W

This bit disables the Playback Only mode function in all modes. No external pull up resistor is required on

ANC / CSDA pin if this bit is set to ‘0’.

0: Playback only mode disabled

1: Playback only mode enabled

This bit mutes the line input in Playback Only operation mode.

0: Line input enabled

1: Line input muted

This register enables the left channel of OPAMP 1 in playback only mode.



Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 61

Document Feedback

AS3418



Bit

0

Bit Name

PBO_OP1R_

ON


0 R/W

This register enables the right channel of OPAMP 1 in playback only mode.



Figure 85:

PBO_MODE1 Register Description


Bit

6

5

4

3

2

1:0

Bit Name

HPH_ON/DIS_

BYPASS

PBO_MICS_C

P_BYP_EN

PBO_MICS_L

DO_ON

PBO_MICS_C

P_ON

PBO_MIC_ON

PBO_HPH_M

UX


0

0

1

1

0

11

R/W

R/W

R/W

R/W

R/W

R/W

This register disables the headphone amplifier in

Playback Only mode and enables the integrated music bypass switch.

0: Headphone amplifier disabled/ Bypass enabled

1: Headphone amplifier enabled

This bit disables the automatic charge pump bypass function if the microphone supply charge pump is in off mode.

0: Charge Pump bypass disabled

1: Charge Pump bypass enabled

This bit enables the microphone LDO in Playback

Only operation mode.

0: Microphone Supply voltage LDO regulator disabled

1: Microphone Supply voltage LDO regulator enabled

This bit controls the microphone supply charge pump. Please mind that disabling the charge pump automatically activates the integrated music bypass switch.

0: Microphone supply charge pump disabled

1: Microphone supply charge pump enabled

This register controls the microphone preamplifier in

Playback Only operation mode.

0: Microphone preamplifier disabled

1: Microphone preamplifier enabled

This register selects the input source of the headphone amplifier in Playback Only operation mode. Depending on register setting the microphone

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 62

Document Feedback

AS3418


Addr: 0x12

Bit Bit Name

PBO_MODE1


preamplifier or OPAMP1 can be connected to the headphone amplifier input.

00: QMIC outputs are connected to HPH input


10: Do not use

11: Nothing connected to HPH input except line input.

Figure 86:

PBO_MIC_LEFT_GAIN Register Description

Addr: 0x13 PBO_MIC_LEFT_GAIN

Bit

6:0

Bit Name

PBO_MIC_LE

FT_GAIN


101

0111

R/W

Volume settings for left microphone input, adjustable in 63 steps of 0.5dB for PBO operation mode.

000 0000: 0dB

000 0001: 0.5dB gain

000 0010: 1.0dB gain

000 0011: 1.5dB gain

…

011 1110: 31dB gain



set)


not set)

Figure 87:

PBO_MIC_RIGHT_GAIN Register Description

Addr: 0x14

Bit Bit Name

6:0

PBO_MIC_RI

GHT_GAIN

PBO_MIC_RIGHT_GAIN


101

0111

R/W

Volume settings for right microphone input, adjustable in 63 steps of 0.5dB for PBO operation mode.

000 0000: 0dB

000 0001: 0.5dB gain

000 0010: 1.0dB gain

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 63

Document Feedback

AS3418


7.2.5

Addr: 0x14

Bit Bit Name

PBO_MIC_RIGHT_GAIN


000 0011: 1.5dB gain

…

011 1110: 31dB gain



set)


not set)

AGC Control Registers

Figure 88:

AGC_CONTROL0 Register Description

Addr: 0x15 AGC_CONTROL0

Bit

7

6:5

ATTACK_LEV

EL

4:3

RELEASE_LE

VEL

2

Bit Name

ZERO_CROS

S_EN

AGC_MUTE_

EN


0

0

00

0

R/W

R/W

R/W

R/W

This register disables the zero cross detection function of the AGC.

0: Zero cross detection disabled

1: Zero cross detection enabled

This register controls the attack level threshold voltage of the AGC.

00: 0.277*

V

BAT

attack level

01: 0.333* V

BAT

attack level

10: 0.395* V

BAT

attack level

11: 0.463* V

BAT

attack level

This register controls the release level threshold voltage of the AGC.

00: 0.200* V

BAT

release level

01: 0.250* V

BAT

release level

10: 0.304* V

BAT

release level

11: 0.364* V

BAT

release level

This bit enables the mute function for the automatic gain control.

0: AGC mute function disabled

1: AGC mute function enabled

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 64

Document Feedback

AS3418


Addr: 0x15 AGC_CONTROL0

Bit

1

0

Bit Name

NEG_ATTEN_

EN

AGC_EN


0

0

R/W

R/W

This bit enables negative the negative gain option for the microphone preamplifier in case of a microphone overload condition. The gain can go down to -40dB.

In case the

AGC_MUTE_EN

bit is not. If the

AGC_MUTE_EN

bit is set the preamplifier goes to -

40dB and eventually mutes the output.

0: Negative attenuation disabled

1: Negative attenuation enabled

This bit enables/disabled the automatic gain control function of AS3418. This setting is valid for ANC,

Monitor and PBO operation mode.

0: AGC disabled

1: AGC enabled

Figure 89:

AGC_ATTACK_RELEASE_TIME Register Description

Addr: 0x16 AGC_ATTACK_RELEASE_TIME

Bit

7:4

3:0

Bit Name

AGC_RELEAS

E_TIME

AGC_ATTACK

_TIME


0001

0000

R/W

R/W

This register controls the AGC release time.

0000: 0ms

0001: 0.5ms

0010: 1ms

0011: 2ms

0100: 4ms

0101: 8ms

0110: 10ms

0111: 12ms

1000: 16ms

1001: 20ms

1010: 24ms

1011: 28ms

1100: 32ms

1101: 64ms

1110: 128ms

1111: 256ms

This register controls the AGC attack time.

0000: 0.5µs

0001: 1µs

0010: 2µs

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 65

Document Feedback

AS3418


Addr: 0x16 AGC_ATTACK_RELEASE_TIME


0011: 4µs

0100: 8µs

0101: 12µs

0110: 16µs

0111: 24µs

1000: 32µs

1001: 64µs

1010: 128µs

1011: 256µs

1100: 512µs

1101: 1000µs

1110: 2000µs

1111: 4000µs

Figure 90:

AGC_HOLD Register Description

Addr: 0x17 AGC_HOLD

Bit

7:4

3:0

Bit Name

ZERO_TIMEO

UT

HOLD_TIME


0000

0000

R/W

R/W

This register controls the timeout of the zero cross detection.

0000: 0 (no timeout)

0001: 20ms

0010: 40ms

0011: 80ms

0100: 120ms

0101: 160ms

0110: 240ms

0111: 320ms

1000: 400ms

1001: 480ms

1010: 560ms

1011: 640ms

1100: 800ms

1101: 960ms

1110: 1120ms

1111: 1280ms

This register controls the AGC hold time.

0000: 0 (no hold time)

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 66

Document Feedback

AS3418


Addr: 0x17 AGC_HOLD


0001: 20ms

0010: 40ms

0011: 80ms

0100: 120ms

0101: 160ms

0110: 240ms

0111: 320ms

1000: 400ms

1001: 480ms

1010: 560ms

1011: 640ms

1100: 800ms

1101: 960ms

1110: 1120ms

1111: 1280ms

Figure 91:

AGC_START_TIME Register Description

Addr: 0x18 AGC_START_TIME

Bit Bit Name

2:0

START_RAM

P_TIME<2:0>


000 R/W

This register controls the AGC gain ramp up step time only during startup of the device.

000: 1ms/step

001: 2ms/step

010: 4ms/step

011: 8ms/step

100: 16ms/step

101: 32ms/step

110: 64ms/step

111: 128ms/step

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 67

7.2.6

Document Feedback

AS3418


Operation Mode Control Register

Figure 92:

MODE_SWITCH_CONTROL Register Description

Addr: 0x1A MODE_SWITCH_CONTROL

Bit

6:5

SHUTDOWN_

DELAY

3:2

1

0

Bit Name

MODE_SWIT

CH_DELAY

GAIN_JUMP_

UP_EN

GAIN_JUMP_

DOWN_EN


00

11

0

0

R/W

R/W

R/W

R/W

This register controls the shutdown delay function of

AS3418.

00: 10ms(default after reset)

01: 80ms

10: 200ms

11: 400ms

Defines the time switching from ANC to PBO and

PBO to MONITOR operation mode. During this mode switching delay the headphone amplifier multiplexer is not connected to any source.

00: 5ms

01: 100ms

10: 200ms

11: 400ms

This bit is independent of

AGC_EN

bit. The gain after a gain register write is not immediately set but is stepped up from old to new value if it is lower than the old gain setting. Gain change will follow

AGC_RELEASE_TIME

register setting.

0: Gain Jump up disabled

1: The gain is immediately set after a gain register write if it is higher than the old gain setting

This bit is independent of

AGC_EN

bit. The gain after a gain register write is not immediately set but is stepped down from old to new value if it’s lower than the old gain setting. Gain change will follow

AGC_ATTACK_TIME

register setting.

0: Gain Jump down disabled

1: Gain jump down enabled

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 68

7.2.7

Document Feedback

AS3418


EEPROM Control Registers

Figure 93:

EEPROM_CONTROL Register Description

Addr: 0x34 EEPROM_CONTROL

Bit

2

1

0

Bit Name

EEPROM_UP

LOAD_TEST

EEPROM_UP

LOAD

EEPROM_DO

WNLOAD


0

0

0

R/W

R/W

R/W

The register bit supports an EEPROM upload test function which simulates an EEPROM write without executing the actual write in order to check if the supply voltage is high enough for proper EEPROM programming. Once the bit is set, the test is started automatically and cleared after the test in finished.

The result, if the test was positive, can be read out in register

EE_WR_TEST_OK

.

0: EEPROM upload test disabled

1: EEPROM upload test started

This register triggers the EEPROM upload function which copies all register content of AS3418 to the

AS3418 to store it permanently to the device. Once the upload is completed the bit is cleared automatically. The success of the EEPROM upload can be read out in register

EE_READY

.

0: EEPROM upload function disabled

1: EEPROM upload function started

This register triggers the EEPROM download function which copies all EEPROM content to the

AS3418 configuration regsiters. Once the download is completed the bit is cleared automatically. The success of the EEPROM download can be read out in register

EE_READY

.

0: EEPROM upload function disabled

1: EEPROM upload function started

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 69

Document Feedback

AS3418

Application Information

8 Application Information

The following chapters provide application specific information like schematic examples and a summary of external components.

8.1 Schematic

Figure 94 shows an example of a Feed Forward ANC headset in Push Button operation mode.

Figure 94:

Push Button Operation Mode

– Application Example

Left

ANC

Filter

Left ANC MIC

MICS

R1

2k2

MIC1

AGND

C3

1uF

AGND

R2

2k2

U2

Right ANC MIC

L 3

Music Line Input

R

GND

2

1

AGND AGND AGND

MIC2

MICS

R6

2k2

C13 1uF

AGND

R3

150

R4

150

AGND

R7

2k2

C7

C8

AGND

C4

10uF

4.7µF

4.7µF

D4

D6

B5

B1

A3

E3

D1

B6

MICL

BPL

LINL

TRSDA

TRSCL

LINR

BPR

MICR

C11

10uF

AGND

AS3418

WL-CSP

VN EG

GND

U1

CPN

CPP

VBAT

HPL

AGND

HPR

MSUP

MICS

D2

D5

B2

E5

E4

B4

C4

A6

C1

10µF

VN EG

GND

C2

2.2µF

C6

2.2µF

MICS

C9

4.7µF

VBAT

GND

C5

4.7µF

AGND

R5

VBAT

10k

C12

GND

4.7µF

Right

ANC

Filter

AGND

VBAT

S1

Push Button

On / Off / Monitor

Speaker Left

Speaker Right

Figure 95 shows an application example of a Feed Forward ANC headset in Slider operation mode.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 70

Document Feedback

Figure 95:

Slider Operation Mode


AS3418


Left

ANC

Filter

Left ANC MIC

MICS

R1

2k2

MIC1

AGND

C3 1uF

AGND

R2

2k2

U2

L 3

Music Line Input

R

GND

2

1

R3

150

R4

150

AGND AGND AGND

Right ANC MIC

MIC2

MICS

R6

2k2

C13 1uF

AGND

AGND

R7

2k2

C7

C8

AGND

C4

10uF

4.7µF

4.7µF

D4

D6

B5

B1

A3

E3

D1

B6

MICL

BPL

LINL

TRSDA

TRSCL

LINR

BPR

MICR

C11

10uF

AGND

AS3418

WL-CSP

VN EG

GND

U1

CPN

CPP

VBAT

HPL

AGND

HPR

MSUP

MICS

B4

C4

A6

D2

D5

B2

E5

E4

C1

10µF

VN EG

GND

C2

2.2µF

C6

2.2µF

MICS

C9

4.7µF

VBAT

GND

C5

4.7µF

AGND

R5

VBAT

10k

C12

GND

4.7µF

Right

ANC

Filter

AGND

R8

22k

VBAT

S2

ON OFF

GND

S3

GND

R9

Figure 96 shows an application example of a Feed Forward ANC headset in Full Slider operation

mode.

Speaker Left

Speaker Right

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 71

Document Feedback

Figure 96:

Full Slider Operation Mode


Left ANC MIC

MIC1

MICS

R1

2k2

C3

AGND

1uF

AGND

R2

2k2

U2

L 3

Music Line Input

R

GND

2

1

R3

150

R4

150

AGND AGND AGND

Right ANC MIC

MIC2

MICS

R6

2k2

C13 1uF

AGND

AGND

R7

2k2

AS3418


Left

ANC

Filter

C7

C8

AGND

C4

10uF

4.7µF

4.7µF

D4

D6

B5

B1

A3

E3

D1

B6

MICL

BPL

LINL

TRSDA

TRSCL

LINR

BPR

MICR

C11

10uF

AGND

AS3418

WL-CSP

VN EG

GND

U1

CPN

CPP

VBAT

HPL

AGND

HPR

MSUP

MICS

D2

D5

B2

E5

E4

B4

C4

A6

C1

10µF

VN EG

GND

C2

2.2µF

C6

2.2µF

MICS

C9

4.7µF

VBAT

GND

C5

4.7µF

AGND

R5

VBAT

10k

C12

GND

4.7µF

Right

ANC

Filter

AGND

R8

22k

VBAT

GND

R9

22k

GND

R10

1M

OFF ON MON

Speaker Left

Speaker Right

8.2 External Components

This chapter provides detailed information about recommended external components.

Figure 97:

Useful Caption


Temp.

Characteristic

Min.

Rated

Voltage

Max.

Tolerance

Min. Nominal

Capacitance /

Resistance

Capacitors

C

VBAT

C

FLY

Input Capacitor

VNEG charge pump flying capacitor

Y5R; X5R

Y5R; X5R

C

ACR

, C

ACL

AC coupling capacitor Y5R; X5R

C

VNEG

Output Capacitor Y5R; X5R

4V

4V

4V

4V

±20%

±20%

±10%

±20%

1.6µF

0.97µF

5.6µF

3.4µF

Recommended typ.

Component Value

4.7µF

2.2µF

10µF

10µF

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 72

Document Feedback

AS3418



Temp.

Characteristic

Min.

Rated

Voltage

Max.

Tolerance

Min. Nominal

Capacitance /

Resistance

C

C

C

MICL

, C

MICR

C

MICS

MSUP

FILTER

Output Capacitor microphone supply

Output Capacitor microphone charge pump

AC coupling capacitor; value depends on

ANC filter design

ANC filter related capacitors

Y5R; X5R

Y5R; X5R

Y5R; X5R

Y5R; X5R

4V ±20%

±20%

±10%

±10%

0.94µF

0.94µF

-

-

Recommended typ.

Component Value

4.7µF

4.7µF

-

-

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 73

Document Feedback

9 Package Drawings & Markings

Figure 98:

WL-CSP Package Outline Drawing

40 c cc

AS3418

Package Drawings & Markings

80

450

±15 400 ±15 400

0 160

0 250

±15 400

±15 400

450

(1)

(2)

(3)

(4)

RoHS

Green

All dimensions are in µm. Angles in degrees.

Dimensioning and tolerancing conform to ASME Y14.5M-1994.

This package contains no lead (Pb).

This drawing is subject to change without notice.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 74

Figure 99:

Package Marking/Code

Document Feedback

AS3418

Package Drawings & Markings

AS3418

XXXXX

XXXXX Encoded Tracecode

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 75

Document Feedback

AS3418

Revision Information

10 Revision Information

Document Status

Product Preview

Product Status Definition

Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice

Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice

Datasheet Production

Datasheet

(discontinued)

Discontinued

Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade

Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs

Changes from previous version to current revision v4-00 Page

●

●

Figure 94 update of ball number of pin QOP1L



70

71

72

Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.

Correction of typographical errors is not explicitly mentioned.

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 76

Document Feedback

AS3418

Legal Information

11 Legal Information

Copyrights & Disclaimer

Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved.

The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.

Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of

Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams

AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing b y ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.

RoHS Compliant & ams Green Statement

RoHS Compliant:

The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.

ams Green (RoHS compliant and no Sb/Br/Cl):

ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material).

Important Information:

The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Headquarters

ams AG

Tobelbader Strasse 30

8141 Premstaetten

Austria, Europe

Tel: +43 (0) 3136 500 0

Please visit our website at www.ams.com

Buy our products or get free samples online at www.ams.com/Products

Technical Support is available at www.ams.com/Technical-Support

Provide feedback about this document at www.ams.com/Document-Feedback

For sales offices, distributors and representatives go to www.ams.com/Contact

For further information and requests, e-mail us at [email protected]

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

77

│ 77

AMS AS3418 Audio Datasheet

Datasheet

Low Noise ANC Solution

Content Guide

1 General Description

2 Ordering Information

3 Pin Assignment

4 Absolute Maximum Ratings

5 Electrical Characteristics

6 Functional Description

Control Logic

Control Logic

Control Logic

Charge Pump

Application Trim Box

7 Register Description

8 Application Information

9 Package Drawings & Markings

Green

10 Revision Information

11 Legal Information

Related manuals

Table of contents

AMS AS3418 Audio Datasheet

Datasheet

Low Noise ANC Solution

Content Guide

1 General Description

2 Ordering Information

3 Pin Assignment

4 Absolute Maximum Ratings

5 Electrical Characteristics

6 Functional Description

Control Logic

Control Logic

Control Logic

Charge Pump

Application Trim Box

7 Register Description

8 Application Information

9 Package Drawings & Markings

Green

10 Revision Information

11 Legal Information

Related manuals

AMS

AS3412

AMS

AS3502

AMS

AS3420

Converters.TV

USB Audio Center

AMS

AS3422

Variobot

tinobo-Steuereinheit

NXP

NE58633BS

AMS

AS3661

Table of contents