AMS AS3422 Audio Datasheet
Oglas
Oglas
AS3421/22
Low Power Ambient Noise-Cancelling Speaker Driver
1 General Description
The AS3421/22 are speaker driver with Ambient Noise Cancelling function for headsets, headphones or ear pieces. It is intended to improve quality of e.g. music listening, a phone conversation etc. by reducing background ambient noise.
The fully analog implementation allows the lowest power consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP implementations. The device is designed to be easily applied to existing architectures.
An internal OTP-ROM can be optionally used to store the microphone gain calibration settings as well as all application specific settings.
The AS3421/22 can be used in different configurations for best trade-off of noise cancellation, required filtering functions and mechanical designs.
The simpler feed-forward topology is used to effectively reduce frequencies typically up to 2-3kHz. The feed-back topology with either 1 or 2 filtering stages has it strengths especially at very low frequencies. The typical bandwidth for feedback system is from 20Hz up to 1kHz which is a little bit lower than with feed forward systems.
The filter loop for both systems is determined by measurements, for each specific headset individually, and depends very much on mechanical designs. The gain and phase compensation filter network is implemented with cheap resistors and capacitors for lowest system costs.
AS3421/22 features also an audio playback only mode which allows the user to easily switch between ANC on and off mode. In ANC off mode unused blocks are automatically switch off to guaranty lowest power consumption in each operating mode.
2 Key Features
Microphone Input
128 gain steps @ 0.375dB and MUTE with AGC
Differential, low noise microphone amplifier
Single ended or differential mode
Improved supply for electret microphone
MIC gain OTP programmable
High Efficiency Headphone Amplifier
2x23mW, 0.1% THD+N @ 32
, 1.5V supply,
100dB SNR
Bridged mode for e.g. 300
loads
Click and pop less start-up and mode switching
Line Input
Volume control via serial interface or push buttons
64 steps @ 0.75dB and MUTE, pop-free gain setting
Fully differential stereo line inputs
ANC processing
Feed-forward cancellation
Feed-back cancellation with filter loop transfer function definable via simple RC components
Simple in production SW calibration
12-30dB noise reduction (headset dependent)
10-3000Hz wide frequency active noise attenuation (headset dependent)
Monitor Function
For assisted hearing, i.e. to monitor announcements
Fixed (OTP prog.) ambient sound amplification to compensate headphone passive attenuation
Incremental Functions
ANC with or without music on the receiving path
Music Playback mode for lowest power consumption
OTP ROM for automatic trimming during production (4 times programmable)
Performance Parameter
7mA @ 1.5V stereo ANC; <1µA quiescent
Extended PSRR for 217Hz
Increased TDMA noise immunity
Interfaces
2-wire serial control mode & volume inputs
Calibration via Line-In or 2-wire serial interface
Fixed 1.0-1.8V supply with internal CP
Package
AS3421 QFN24 [4x4mm] 0.5mm pitch
AS3422 QFN32 [5x5mm] 0.5mm pitch
3 Applications
The devices are ideal for wireless devices like stereo Bluetooth headsets as well as stereo wireless headsets.
www.ams.com/ANC Revision 1.10
1 - 61
AS3421/22
Datasheet - A p p l i c a t i o n s
Figure 1. AS3421 Feed Forward ANC Block Diagram
Figure 2. AS3422 Feed-Back Block Diagram
www.ams.com/ANC Revision 1.10
2 - 61
AS3421/22
Datasheet - C o n t e n t s
4 Contents
1 General Description .................................................................................................................................................................. 1
2 Key Features ............................................................................................................................................................................ 1
3 Applications .............................................................................................................................................................................. 1
4 Contents ................................................................................................................................................................................... 3
5 Pin Assignments ....................................................................................................................................................................... 4
5.1 Pin Descriptions ............................................................................................................................................................. 5
6 Absolute Maximum Ratings ...................................................................................................................................................... 6
7 Electrical Characteristics .......................................................................................................................................................... 7
8 Typical Operating Characteristics ............................................................................................................................................. 9
9 Detailed Description ............................................................................................................................................................... 12
9.1 Audio Line Input ........................................................................................................................................................... 12
9.2 Microphone Input ......................................................................................................................................................... 13
9.3 Headphone Output ...................................................................................................................................................... 15
9.4 Operational Amplifier ................................................................................................................................................... 16
9.5 SYSTEM ...................................................................................................................................................................... 18
9.6 VNEG Charge Pump ................................................................................................................................................... 21
9.7 OTP Memory & Internal Registers ............................................................................................................................... 21
9.8 2-Wire-Serial Control Interface .................................................................................................................................... 24
10 Register Description ............................................................................................................................................................. 28
11 Application Information ......................................................................................................................................................... 44
11.1 AS3422 Feedback Application Examples .................................................................................................................. 44
11.2 AS3421 Feed Forward Application Examples ........................................................................................................... 48
11.3 Layout Recommendation .......................................................................................................................................... 52
11.4 Bill of Materials ......................................................................................................................................................... 53
11.5 PCB Footprint Recommendation ............................................................................................................................... 54
12 Package Drawings and Marking ........................................................................................................................................... 56
Ordering Information ....................................................................................................................................................................60
www.ams.com/ANC Revision 1.10
3 - 61
AS3421/22
Datasheet - P i n A s s i g n m e n t s
5 Pin Assignments
Note:
Pin assignment may change in preliminary data sheets.
Figure 3. Pin Assignments (Top View)
CAUTION:
Exposed pad must be connect to VNEG
www.ams.com/ANC Revision 1.10
4 - 61
AS3421/22
Datasheet - P i n A s s i g n m e n t s
MODE_CSCL
QOP2R
VSS
HPL
HPVSS
HPR
HPVDD
VBAT
CPP
MICL
MICS
MICR
QMICR
QLINR
IOP1R
QOP1R
IOP2R
GND
CPN
VNEG
QOP2L
IOP2L
QOP1L
VNEG
5.1 Pin Descriptions
Note:
Pin description may change in preliminary data sheets.
Table 1. Pin Description for AS3421 AS3422
Pin Name
IOP1L
QLINL
QMICL
AGND
LINL_N
LINL_P
LINR_P
LINR_N
3
4
1
2
Pin Number
AS3421 AS3422
24 1
2
5
6
7
8
5
6
3
4
Type
ANA IN
ANA OUT
ANA OUT
ANA IN
ANA IN
ANA IN
ANA IN
ANA IN
ANC_CSDA 7 9 MIXED IO
8
9
10
11
12
13
14
15
20
21
22
16
17
18
19
23
25
10
23
24
25
26
19
20
21
22
15
16
17
18
11
12
13
14
31
32
33
27
28
29
30
DIG IN
ANA OUT
SUP IN
ANA OUT
SUP IN
ANA OUT
SUP IN
SUP IN
ANA OUT
ANA IN
ANA OUT
ANA IN
ANA OUT
ANA OUT
ANA IN
ANA IN
ANA IN
GND
ANA OUT
SUP IO
ANA OUT
ANA IN
ANA OUT
SUP IN
Description
Filter OpAmp1 Input Left Channel
Line In Gain Stage Output Left Channel
MIC Gain Stage Output Right Channel
Analog Reference
Negative Line In pin of Left Channel
Positive Line In pin of Left Channel
Positive Line In pin of Right Channel
Negative Line In pin of Right Channel
Serial Interface Data
ANC Pin (Enable/Disable ANC function)
Mode Pin (Power Up/Down, Monitor)
Serial Interface Clock
Microphone In Left Channel
Microphone Supply
Microphone Input Right Channel
MIC Gain Stage Output Right Channel
Line In Gain Stage Output Right Channel
FilterOpAmp1 Input Right Channel
Filter OpAmp1 Output Right Channel
Filter OpAmp2 Input Right Channel
Filter OpAmp2 Output Right Channel
VSS supply terminal
Headphone Output Left Channel
Headphone amplifier VSS supply terminal
Headphone Output Right Channel
Headphone VDD Supply
Positive supply terminal of IC
VNEG ChargePump Flying Capacitor Positive Terminal
VNEG ChargePump Negative Supply
VNEG ChargePump Flying Capacitor Negative Terminal
VNEG ChargePump Output
Filter OpAmp2 Output Left Channel
Filter OpAmp2 Input Left Channel
Filter OpAmp1 Output Right Channel
Exposed Pad: Connect to VNEG www.ams.com/ANC Revision 1.10
5 - 61
AS3421/22
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
6 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 7 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions.
Table 2. Absolute Maximum Ratings
Min Max Units Parameter
Reference Ground
Supply terminals
Ground terminals
Negative terminals
Voltage difference at VSS terminals
Pins with protection to VBAT
Pins with protection to HPVDD other pins
Input Current (latch-up immunity)
Continuous Power Dissipation (T
A
= +70ºC)
-0.5
-0.5
-2.0
-0.5
VNEG
-0.5
VSS
-0.5
VSS
-0.5
-100
2.0
0.5
0.5
0.5
5.0
VBAT+0.5
5.0
HPVDD+0.5
5
100
V
V
V
V
V
V mA
Comments
Defined as in GND
Applicable for pin VBAT, HPVDD
Applicable for pins AGND
Applicable for pins VNEG, VSS, HPVSS
Applicable for pins VSS, HPVSS
Applicable for pins CPP, CPN
Applicable for pins LINL_P/N, LINR_P/N, MICL/
R, HPR, HPL, QMICL/R, QLINL/R, IOPx, QOPx
Applicable for pins MICS, ANC_CSDA,
MODE_CSCL
Norm: JEDEC 17
Continuous Power Dissipation
200 mW
P
T
1
for QFN16/24/32 package
Electrostatic Discharge
Electrostatic Discharge HBM
+/-2 kV Norm: JEDEC JESD22-A114C
Temperature Ranges and Storage Conditions
Junction Temperature
Storage Temperature Range
Humidity non-condensing
Moisture Sensitive Level
Package Body Temperature
-55
5
3
+110
+125
85
260
ºC
ºC
%
ºC
Represents a max. floor life time of 168h
The reflow peak soldering temperature (body temperature) specified is in accordance with
IPC/
JEDEC J-STD-020“Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State
Surface Mount Devices”.
1. Depending on actual PCB layout and PCB used www.ams.com/ANC Revision 1.10
6 - 61
AS3421/22
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
7 Electrical Characteristics
VBAT = 1.0V to 1.8V, T
A
= -20ºC to +85ºC. Typical values are at VBAT = 1.5V, T
A
= +25ºC, unless otherwise specified. All limits are guaranteed.
The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods.
Table 3. Electrical Characteristics
Symbol
T
A
Supply Voltages
GND
Parameter
Ambient Temperature Range
Reference Ground
Condition Min
-20
Max
+85
Unit
°C
VBAT,
HPVDD
VNEG
VSS
Battery Supply Voltage
ChargePump Voltage
Analog neg. Supply Voltages
HPVSS, VSS, VNEG normal operation with MODE pin high
Two wire interface operation
0
1.0
1.4
-1.8
-1.8
0
1.8
1.8
-0.7
-0.7
V
V
V
V
V
V
DELTA
-
Difference of Ground Supplies
GND, AGND
To achieve good performance, the negative supply terminals should be connected to low impedance ground plane.
-0.1
0.1
V
V
DELTA
--
Difference of Negative Supplies
VSS, VNEG, HPVSS
Difference of Positive Supplies
Charge pump output or external supply
VBAT-HPVDD
-0.1
-0.25
0.1
0.25
V
V
V
DELTA
+
Other pins
V
MICS
Microphone Supply Voltage
0 3.6
V
V
V
V
HPVDD
VBAT
V
CONTROL
TRIM
Pins with diode to HPVDD
Pins with diode to VBAT
Control Pins
Line Input & Application Trim Pins
MICS
MICL/R, HPR, HPL, QMICL/R, QLINL/R,
IOPx, QOPx
CPP, CPN
MODE_CSCL, ANC_CSDA
LINL_P, LINL_N, LINR_P, LINR_N
VSS
VNEG
VSS
VNEG -0.5
or -1.8
3.6
VBAT
3.7
HPVDD +0.5
or 1.8
V
V
V
V
Condition
VBAT<0.8V
VBAT<0.6V
Min Typ Max
20
10
Unit
µA
µA
Symbol Parameter
I leak
Leakage current
Block Power Requirements @ 1.5V VBAT
I
OFF
Off mode current
I
SYS
Reference supply current
LineIn gain stage current I
LIN
I
MIC
I
HP
Mic gain stage current
Headphone stage current
MICS charge pump current I
MICS
I
MIN
I
OP1
I
OP2
Minimal supply current
OP1 supply current
OP2 supply current
MODE pin low, device switched off
Bias generation, oscillator, ADC6, VNEG no signal, stereo no signal, stereo no signal no load
Sum of all above blocks no load no load
30
4.6
0.64
0.64
1
0.25
0.5
2.10
1.70
µA mA mA mA
µA mA mA mA mA www.ams.com/ANC Revision 1.10
7 - 61
AS3421/22
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Symbol
I
MICB
I
PB
Parameter
Microphone bias current
Low Power Playback Mode
Condition
200µA per microphone via charge pump
V
BAT
= 1.8V
V
BAT
= 1.5V
V
BAT
= 1.0V
Min Typ
0.9
2,8
2,5
2
Max Unit
mA mA mA mA www.ams.com/ANC Revision 1.10
8 - 61
AS3421/22
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
8 Typical Operating Characteristics
V
BAT
= +1.5V, C
1
=100nF, C
2
=10µF, C
3
=1µF, C
6
=100nF, C unless otherwise specified.
5
=10µF, C
13
=10µF, C
12
=2.2µF, C14=2.2µF T
A
= +25ºC and HP_MUX_OTP set to ‘3’
Figure 4. THD+N vs. Pout; Line to HPH; 16
single ended stereo Figure 5. THD+N vs. Pout; Line to HPH; 32
single ended stereo
10 10
1V
1.5V
1.8V
1V
1.5V
1.8V
1
1
0,1
0,1
0,01
1 10
Pout [mW]
Figure 6. THD+N vs. f; Line to HPH; 1mW load per channel
100
1,5
1
16 Ohm
32 Ohm
Pout
0,01
1
16 Ohm
32 Ohm
Pout
10
Pout [mW]
Figure 7. THD+N vs. f; Line to HPH; 10mW load per channel
1
100
15
1,0
10
0,1
0,1
0,01
0,5
0,01
5
0,001
10 100 f [Hz]
1k
Figure 8. THD+N vs. f; 20mW and 30mW per channel
10k
0,0
1
0,1
0,01
0,001
10 www.ams.com/ANC
30
20
10
100 f [Hz]
1k
THD+N 16 Ohm
THD+N 32 Ohm
Pout 16 Ohm
Pout 32 Ohm
10k
0
0,001
10 100 f [Hz]
1k 10k
Figure 9. Frequency Response 30mW@16
; Line to HPH
0,5
0,4
0,3
0,2
0,1
0
-0,1
-0,2
-0,3
-0,4
-0,5
10 100 f [Hz]
1k 10k
0
Revision 1.10
9 - 61
AS3421 AS3422
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 10. Frequency Response 20mW@32
; Line to HPH
0,5
0,4
0,3
0,2
0,1
0
-0,1
-0,2
-0,3
-0,4
-0,5
10 100 1k 10k f [Hz]
Figure 11. Microphone Supply FFT
0
-20
-40
-60
-80
-100
-120
-140
-160
10 100 f [Hz]
1k 10k
Figure 12. V
NEG
CP Voltage vs. CP load current with different
V
BAT
supply voltages
0
-0,5
1.8V
1.5V
1.0V
Figure 13. V
NEG
Efficiency vs.I
VNEG
with different V
BAT
supply voltages
0
1.8V
1.5V
1.0V
-0,5
-1
-1
-1,5
-1,5
-2
0 25 50 75 100 125 150 175 200
I
VNEG
[mA]
Figure 14. V
MIC_OUT
vs. I
MIC_OUT
4
3,5
3
2,5
2
1,5
1
0,5
0
0 200 400
I
MIC_OUT
[µA]
600
VBAT = 1.8V
VBAT = 1.5V
800 www.austriamicrosystems.com
Revision 1.10
-2
0 25 50 75 100 125 150 175 200
I
VNEG
[mA]
10 - 61
AS3421/22
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 15. Typical Performance Data, Feed Forward configuration with an over the ear headset
Feed Forward Topology - Over the Ear Headset
10
5
0
-5
-10
-15
-20
-25
-30
10 100 1000 f [Hz]
10000
Figure 16. Typical Performance Data, Feedback configuration with an on ear headset
Feedback Topology - On Ear Headset
-10
-15
0
-5
10
5
-20
-25
-30
10 100 f [Hz]
1000 10000 www.ams.com/ANC Revision 1.10
11 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
9 Detailed Description
This section provides a detailed description of the device related components.
9.1 Audio Line Input
The chip features one line input. The blocks can work in mono differential or in stereo single ended mode.
In addition to the 12.5-25k
input impedance, LineIn has a termination resistor of 10k
which is also effective during MUTE to charge eventually given input capacitors.
9.1.1 Gain Stage
The Line In gain stage is designed to have 63 gain steps of 0.75dB with a max gain of 0dB plus MUTE per default. By setting the bit Line Gain
+3dB in register 0x33 the gain range can be changed from -46.5dB....0dB to -43.5dB ....+3dB.
In default, the gain will be ramped up from MUTE to 0dB during startup. There is a possibility to make the playback volume user controlled by the
VOL pin with an ADC converted VOL voltage or UP/DOWN buttons. If the device is configured to control the line input volume via push-buttons the device ramps the gain from -46.5dB to 0dB if no button is pressed. If a user presses a button while ramping up the ramping mechanism will be stopped automatically.
In monitor mode, the gain stage can be set to an fixed default attenuation level for reducing the loudness of the music. To avoid unwanted pop noise in this special mode the internal state machine support very smooth gain fading to avoid unwanted acoustic effects.
Figure 17. Fully Differential Stereo Line Inputs
9.1.2 Parameter
VBAT=1.5V, T
A
= 25ºC, unless otherwise specified.
Table 4. Line Input Parameter
Symbol Parameter
V
LIN
Input Signal Level
R
LIN
Δ
RLIN
C
LIN
A
LIN
A
LINMUTE
Input Impedance
Input Impedance Tolerance
Input Capacitance
Programmable Gain
Gain Steps
Gain Step Accuracy
Mute Attenuation
Condition
0dB gain (12.5k // 10k)
-46.5dB gain (25k // 10k)
MUTE
Discrete logarithmic gain steps
Min Typ
0.6*
VBAT
5.6
7.2
10
±30
5
-46.5
0.75
0.5
100
Max
VBAT
+0
Unit
V
PEAK dB dB dB dB k Ω k Ω k Ω
% pF www.ams.com/ANC Revision 1.10
12 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 4. Line Input Parameter (Continued)
Symbol Parameter
Δ
ALIN
V
ATTACK
V
DECAY t
ATTACK t
DECAY
Gain Ramp Rate
Limiter Activation Level
Limiter Release Level
Limiter Attack Time
Limiter Decay Time
Condition
Button Mode, Tinit=400ms
Monitor Mode
HPL/R start of neg. clipping
HPL/R
Min Typ
80
8
VNEG
+0.3
4
8
Max Unit
ms/step
V
PEAK
V
PEAK
µs ms
9.2 Microphone Input
The AFE offers two microphone inputs and one low noise microphone voltage supply (microphone bias). The inputs can be switched to single ended or differential mode.
Figure 18. Microphone Input
MICR
AGND
MICL stereo mode
QMICR
MICR
AGND
QMICL
MICL
QMICR
AGND mono differential mode
QMICL
9.2.1 Gain Stage & Limiter
The Mic Gain Stage has programmable Gain within -11.25dB…+36dB in 128 steps of 0.375dB.
As soft-start function is implemented for an automatic gain ramping implemented with steps of 4ms to fade in the audio at the end of the start-up sequence.
A limiter automatically attenuates high input signals. The AGC has 127 steps with 0.375dB with a dynamic range of the full gain stage. In some design it is necessary to switch of the AGC functionality. This can be done in register 0x17 by setting bit ‘1’.
In monitor mode, the gain stage can be set to an fixed (normally higher) gain level or be controlled by the VOL pin.
9.2.2 Microphone Supply
The MICS charge pump is providing a proper microphone supply voltage for low supply voltage supply. The integrated microphone supply supports basically 3 different modes.
The first mode, also called SWITCH-MODE, for 1.8V supply is to have a direct connection with an integrated switch from VBAT to MICS. The microphone supply pin of AS3421/22 is in this mode directly connected to V
BAT
. For some applications a 1.8V microphone supply is high enough to operate a microphone properly. This mode is more commonly used in devices with a fixed power supply like in Bluetooth headsets.
The internal microphone charge pump is switched off in this mode. This can help also reducing the external filter capacitors for the microphone supply. Please mind that the sensitivity of your microphone can be reduced in this mode.
www.ams.com/ANC Revision 1.10
13 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
The second mode, with the name CHAREGPUMP_MODE, is the most commonly used mode which is per default enabled. In this mode the internal charge pump is enabled. The charge pump doubles the supply voltage of AS3421/22 with a high output impedance of the charge pump in order to make external passive filters more effective. If doubling the supply voltage is not enough the microphone supply can be switched to a special regulated mode which increases the output voltage but with a little bit higher output noise. This setting can be found in register 0x35.
The third mode is the OFF MODE. This mode allows the user to switch of the microphone supply if not needed (e.g. playback without ANC)
9.2.3 Parameter
VBAT=1.5V, T
A
= 25ºC unless otherwise specified.
Table 5. Microphone Input Parameter
Symbol
V
MICIN
0
V
MICIN
1
V
MICIN
2
R
MICIN
Parameter
Input Signal Level
Input Impedance
Δ
MICIN
Input Impedance Tolerance
C
MICIN
A
MIC
Input Capacitance
Programmable Gain
Gain Steps
Gain Step Precision
Δ
AMIC
V
ATTACK
V
DECAY
Gain Ramp Rate
Limiter Activation Level
Limiter Release Level
A
MICLIMIT t
ATTACK
Limiter Gain Overdrive
Limiter Attack Time t
DECAY-DEB
Limiter Decay Debouncing Time t
DECAY
Limiter Decay Time
Condition
A
MIC
= 24dB
A
MIC
= 30dB
A
MIC
= 36dB
MICP to AGND
Discrete logarithmic gain steps
Tinit=64ms
V
PEAK
related to VBAT or VNEG
127 @ 0.375dB
Min
-11.25
Typ
40
20
10
7.5
-7
+33
5
0.375
0.15
4
0.67
0.4
36
5
64
4
Max
+36
Unit
mV
P mV
P mV
P k
% pF dB dB dB ms/step
1
1 dB
µs/step ms ms/step
V
MICS
I
MICS
R
OUT_CP
I
MIC_MIN
I
MIC_MAX
Microphone Output Voltage
Microphone Supply Current
CP Output Resistance
Microphone Output Current
Microphone Output Current no output load no output load
400µA load
Recommended minimum microphone output current @ Vbat = 1.5V
Recommended minimum microphone output current @ Vbat = 1.8V
Recommended maximum microphone output current @Vbat = 1.5V
Recommended maximum microphone output current @Vbat = 1.8V
2.7
30
900
170
300
500
700
µA
µA
V
µA
µA
µA www.ams.com/ANC Revision 1.10
14 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
9.3 Headphone Output
The headphone output is a true ground output using VNEG as negative supply, designed to provide the audio signal with 2x12mW @ 16
-64
, which are typical values for headphones. It is also capable to operate in bridged mode for higher impedance (e.g. 300
headphone. In this mode the left output is carrying the inverted signal of the right output shown in Figure 20 .
Figure 19. Headphone Output Single Ended Mode
HPVDD
QMicR
QOP1R
QOP2R open
LineInR HPR
AGND
HPL
LineInL open
QOP2L
QOP1L
QMicL
LineIn gain stage
Pop
Click
Control
HPVSS
Figure 20. Headphone Output Differential Mode
9.3.1 Input Multiplexer
The signal from the line-input gain stage gets summed at the input of the headphone stage with the microphone gain stage output, the first filter opamp output or the second filter opamp output. The microphone gain stage output is used per default. It is also possible to playback without
ANC by only using the line-input gain stage with no other signal on the multiplexer.
For the monitor mode, the setting of this input multiplexer can be changed to another source, normally to the microphone.
9.3.2 No-Pop Function
The No-Pop startup of the headphone stage takes 60ms to 120ms dependent on the supply voltage.
9.3.3 No-Clip Function
The headphone output stage gets monitored by comparator stages which detect if the output signal starts to clip.
This signal is used to reduce the LineIn gain to avoid distortion of the output signal. A hystereses avoids jumping between 2 gain steps for a signal with constant amplitude.
www.ams.com/ANC Revision 1.10
15 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
9.3.4 Over-Current Protection
The over-current protection has a threshold of 150-200mA and a debouncing time of 8µs. The stage is forced to OFF mode in an over-current situation. After this, the headphone stage tries to power up again every 8ms as long as the over-current situation still exists or the stage is turned off manually.
9.3.5 Parameter
VBAT=1.5V, T
A
= 25ºC, unless otherwise specified.
Table 6. Headphone Output Parameter
Symbol
R
L_HP
C
L_HP
Parameter
Load Impedance
Load Capacitance
P
HP
P
SRRHP
Nominal Output Power
Power Supply Rejection Ratio
Condition
Stereo mode
Min
16
Typ
Stereo mode
RL=64
RL=32
RL=16
12
24
34
200Hz-20kHz, 720mVpp, RL=16 Ω 90
Max
100
Unit
pF mW mW mW dB
9.4 Operational Amplifier
While AS3421 offers only one operational amplifier for feed-forward ANC, AS3422 features an additional operational amplifier stage to support feed-back ANC or any other additional needed filtering.
Both operational amplifiers stages can be activated and used individually. While OP1 stage is always configured as inverting amplifier, OP2 stage can be also switched to a non-inverting mode with an adjustable gain of 0...+10.5dB.
Figure 21. Operational Amplifiers
IOP1R
AGND
IOP1L
OP1
QOP1R
QOP1L
0..10.5dB
IOP2R
QOP2R
IOP2R
AGND
AGND
IOP2L
OP2 inverting mode
QOP2L
IOP2L
AGND 0..10.5dB
OP2 non-inverting mode
QOP2R
QOP2L www.ams.com/ANC Revision 1.10
16 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
9.4.1 Parameter
VBAT=1.5V, T
A
= 25ºC, unless otherwise specified.
Table 7. Headphone Output Parameter
Symbol
R
L_OP
C
L_OP
GBW
OP
V
OS_OP
V
EIN_HP
Parameter
Load Impedance
Load Capacitance
Gain Band Width
Offset Voltage
Equivalent Input Noise
Condition
Single ended
Single ended
200Hz-20kHz
Min
1
Typ
4.3
2.6
Max
100
6
Unit
k
pF
MHz mV
µV www.ams.com/ANC Revision 1.10
17 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
9.5 SYSTEM
The system block handles the power up and power down sequencing, as well as, the mode switching.
9.5.1 Power Up/Down Conditions
The chip powers up when one of the following conditions is true:
Table 8. Power UP Conditions
#
1
2
Source
MODE_CSCL pin
I2C start
Description
In stand-alone mode, MODE pin has to be driven high to turn on the device
In I2C mode, a I2C start condition turns on the device
The chip automatically shuts off if one of the following conditions arises:
Table 9. Power DOWN Conditions
# Source
3
4
1
2
MODE pin
SERIF
Low Battery
VNEG CP OVC
Description
Power down by driving MODE_CSCL pin to low
Power down by SERIF writing 0h to register 20h bit <0>
Power down if VBAT is lower than the supervisor off-threshold
Power down if VNEG is higher than the VNEG off-threshold
9.5.2 Start-up Sequence
The start-up sequence depends on the used mode.
In stand-alone mode the sequence runs automatically, in I2C mode(I2C MODE bit has to be pre-trimmed) the sequence runs till a defined state and waits then for an I2C command. Either the automatic sequence is started by setting the CONT_PWRUP bit in addition to the PWR_HOLD bit. If only the PWR_HOLD is set all enable bits for headphone, microphone, etc have to be set manually.
Figure 22. Stand-Alone Mode Start-Up Sequence
www.ams.com/ANC Revision 1.10
18 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 23. I2C Mode Start-Up Sequence
The total start-up time (including fade-in of the gain stages) can be reduced to 600ms by OTP setting.
9.5.3 MODE_CSCL Switching
When the chip is in stand-alone mode (no I2C control), the mode can be switched with different levels on the MODE pin.
Table 10. MODE_CSCL Operation Modes
MODE
OFF
ANC
MONITOR
MODE_CSCL pin
LOW (VSS)
HIGH (VBAT)
VBAT/2
Description
Chip is turned off
Chip is turned on and active noise cancellation is active
Chip is turned on and monitor mode is active
In Monitor mode, a different (normally higher) microphone preamplifier gain can be chosen to get an amplification of the surrounding noise. This volume can be either fixed or be controlled by the
VOL input.
To get rid of the low pass filtering needed for the noise cancellation, the headphone input multiplexer can be set to a different (normally to MIC) source.
In addition, the LineIn gain can be lowered to reduce the loudness of the music currently played back.
In I2C mode, the monitor mode can be activated be setting the corresponding bit in the system register.
www.ams.com/ANC Revision 1.10
19 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
9.5.4 ANC_CSDA Switching
For Bluetooth applications it is sometimes a requirement to switch off the ANC function while listening to music or having a phone call. Because the fully differential audio outputs of the Bluetooth chip are directly connected to the line input of the AS3421/22 it is not possible to simply switch off the ANC chip to do music playback without ANC.In order to avoid an expensive bypass path with mechanical or electrical switches the
AS3421/22 features a special low power audio playback mode. In this mode the device enters a low power mode where the ANC function is disabled and the blocks which are not necessary in this mode are automatically switched off to safe system power. This audio playback mode can be entered by simply pulling the ANC_SCDA pin to low.
Figure 24. ANC / CSDA Switching
An example how to implement this feature is shown in Figure 24 . In default operation (ANC enabled) the ANC_CSDA pin is pulled high. If the device should enter the low power playback mode the pin is pulled low with the switch S1. Once the pin is pulled low the device enters after
200ms the playback mode. As long as the pin is low the device stays in the playback only mode. If the feature is for some reason not required it can also be disabled by setting the bit NO_PB_MODE_OTP in register 0x33. Once this bit is set to ‘1’ the status of pin ANC_CSDA has no influence on the device any more.
Besides the low power playback mode the ANC_CSDA pin supports also volume control via push buttons. In order to enable this feature the corresponding bit VOL_BUTTON_MODE_OTP is register 0x33 has to be set to ‘1’. Once this bit is set, the device can not support the low power playback mode via ANC_CSDA pin any more. An example on how to connect the push buttons for volume control is shown in Figure 24 with the push buttons S2 and S3.
Table 11. ANC_CSDA Operation Modes
NO_PB_MODE_OTP
Bit
0
0
0
1
X
X
X
VOL_BUTTON_MODE_OTP
Bit
0
0
0
0
1
1
1
ANC_CSDA
Pin
Description
high
Normal ANC operation high -> low Device enters low power playback mode low -> high Device returns to normal ANC operation
X
Normal ANC operation. No influence on operation via
ANC_CSDA pin.
high
Volume Control Mode via Button - Volume up
High Imp.
Volume Control Mode via Button - No Volume change low
Volume Control Mode via Button - Volume down www.ams.com/ANC Revision 1.10
20 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
9.6 VNEG Charge Pump
The VNEG charge pump uses one external 1uF capacitor to generate a negative supply voltage out of the battery input voltage to supply all audio related blocks. This allows a true-ground headphone output with no more need of external dc-decoupling capacitors.
9.6.1 Parameter
VBAT=1.5V, T
A
= 25ºC, unless otherwise specified.
Table 12. Headphone Output Parameter
Symbol
V
IN
V
OUT
C
EXT
Parameter
Input voltage
Output voltage
External flying capacitor
Condition
VBAT
VNEG
Min
1.0
-0.7
Typ
1.5
-1.5
1
Max
1.8
-1.8
Unit
V
V
µF
9.7 OTP Memory & Internal Registers
The OTP memory consists of OTP register and the OTP fuses.The OTP register can be written as often as wanted but will lose the content on power off. The OTP fuses are intended to store basic chip configurations as well as the microphone gain settings to optimize the ANC performance and get rid of sensitivity variations of different microphones. Burning the fuses can only be done once and is a permanent change, which means the fuses keep the content even if the chip is powered down. This AS3421/22 offers 4 register set for storing the microphone gain making it possible to change the gain 3 times for re-calibration or other purposes.
When the chip is controlled by a microcontroller via I2C, the OTP memory don’t has to be used. The chip configuration can be stored in the flash memory of the Bluetooth- or wireless chipset.
9.7.1 Register & OTP Memory Configuration
Figure 25 is showing the principal register interaction.
Figure 25. Register Access
OTP WRITE
OTP Register
10h...16h; 30h...35h
OTP READ normal I2C write normal I2C read
0xB, 0xC, 0x21
BURN
LOAD
OTP
Fuses
OTP path is default but can be switched by register setting
Registers 0x8, 0x9, 0xA, 0xB, 0xC and 0x21 have only effect when the corresponding “REG_ON” bit is set, otherwise the chip operates with the
OTP Register settings which are loaded from the OTP fuses at every start-up.
All registers settings can be changed several times, but will loose the content on power off. When using the I2C mode, the chip configuration has to be loaded from the micro controller after every start-up. In stand alone mode the OTP fuses have to be programmed for a permanent change of the chip configuration.
A single OTP cell can be programmed only once. Per default, the cell is “0”; a programmed cell will contain a “1”. While it is not possible to reset a programmed bit from “1” to “0”, multiple OTP writes are possible, but only additional unprogrammed “0”-bits can be programmed to “1”.
Independent of the OTP programming, it is possible to overwrite the OTP register temporarily with an OTP write command at any time. This setting will be cleared and overwritten with the hard programmed OTP settings at each power-up sequence or by a LOAD operation.
www.ams.com/ANC Revision 1.10
21 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
The OTP memory can be accessed in the following ways:
LOAD Operation.
The LOAD operation reads the OTP fuses and loads the contents into the OTP register. A LOAD operation is automatically executed after each power-on-reset.
WRITE Operation.
The WRITE operation allows a temporary modification of the OTP register. It does not program the OTP. This operation can be invoked multiple times and will remain set while the chip is supplied with power and while the OTP register is not modified with another
WRITE or LOAD operation.
READ Operation.
The READ operation reads the contents of the OTP register, for example to verify a WRITE command or to read the OTP memory after a LOAD command.
BURN Operation.
The BURN operation programs the contents of the OTP register permanently into the OTP fuses. Don’t use old or nearly empty batteries for burning the fuses.
Attention:
If you once burn the OTP_LOCK bit, no further programming, e.g. setting additional “0” to “1”, of the OTP can be done.
For production, the OTP_LOCK bit must be set to avoid an unwanted change of the OTP content during the lifetime of the product.
9.7.2 OTP Fuse Burning
As many wireless applications like Bluetooth single chip solutions support programmable solutions as well as ROM versions it is in ROM versions necessary to store microphone gain compensation data and the general ANC configuration inside the ANC chip because there is not other way to configure the ANC chip during startup. In order to guaranty successful trimming of AS3421/22 it is necessary to provide a decent environment for the trimming process. In Figure 26 a principal block diagram is shown for trimming the AS3421/22 properly in production.
Figure 26. Block Diagram for Production Environment
The most important block is the external power supply. Usually it is possible to trim the AS3421/22 with a single supply voltage of min. 1.7V in laboratory environment but as soon as it comes to mass production we highly recommend buffering also V
NEG
supply of the chip. As highlighted in the block diagram it is mandatory to get a voltage difference between V
POS
and V
NEG
of min. 3.4V to guaranty proper trimming of the device. no current sink capability, therefore it is possible to buffer it external with a negative power supply. The V
NEG voltage applied to V
NEG
pin must be lower than the voltage created with the charge pump. This means if the typical V
NEG
output voltage is -1.5V you can easily apply externally -
1.7V. The charge pump switches then automatically into skip mode.
Important for applying an external buffer and switching on the ANC device is the timing in order to avoid latch up on the ANC device.
The timing diagram in Figure 2 shows clearly that it is important that there is a certain delay between VBAT and the MODE /CSCL pin necessary. This delay is mandatory in order to guaranty that the device starts up properly. In case AS350x is used the delay between VBAT and MODE/CSCL is not necessary. The MODE /CSCL pin powers the ANC device up and the whole sequence to power up the internal charge pump of AS34x0 and
AS350x takes approximately 1ms. Once VNEG is settled the external VNEG buffer (e.g. power supply) can be enabled in order to support the charge pump especially during the trim process which can now be started.
www.ams.com/ANC Revision 1.10
22 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 27. Timing Diagram for V
NEG
Buffering
To guaranty a successful trimming process it is important to follow exactly the predefined trimming sequence shown in Figure 28 .
As a first step it is important to do a register dump of all OTP registers. This register backup in your system memory is a backup of all register setting and is necessary for the verification after the trim process to make sure that all bits are trimmed correctly. Once the register dump has been done it is important to check the OTP_LOCK in register 0x35. This register indicates if the device is already trimmed or not. In case this bit is set to ‘1’ there is no more trimming possible. The device has obviously already been trimmed before. In case the bit is ‘0’ there is initial or further trimming of the device possible. You enter the trim mode and start the trimming process. Once the trimming is done the most important step is comparing the values trimmed to the device with the original register dump we did right before we started with the actual trimming process. If the verification was successful we know that all bits have been trimmed correctly to AS3501/AS3502. What is important to mention is that the AS3502 and AS3501 have a couple of test bits inside which are per default set to ‘1’. We do not recommend overwriting these bytes.
Furthermore it is important to know that it is not possible to change bits once they are trimmed. With AS3501 and AS3502 it is possible to trim the device again if the MAIN_LOCK bit is not set to ‘1’. What is not possible is, is changing a bit from ‘1’ back to zero. If an additional trimming is done it is only possible to change bits from ‘0’ to ‘1’. An example would be the following. A register contains a value of 0x41. If the MAIN_LOCK bit is not set to ‘1’ you can basically re-trim the part but it doesn’t work to change the value from 0x41 to 0x40. What is possible would be a change from 0x41 to 0x43. It is important that all necessary bits are trimmed exactly like in the block diagram shown in
Figure 28
. The internal state machine needs the MAIN_LOCK bit as well as the ALTx_LOCK bits to determine the right microphone register at start-up of the device. If the
MAIN_LOCK bit and the ALTx_LOCK bits are not set correctly the result can be malfunction of the device. for detailed implementation of the I2C trimming there is also an application note available which describes the whole process in more detail and includes also some code examples.
www.ams.com/ANC Revision 1.10
23 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 28. OTP Burning Process
enter
“Application Trimm” mode
ANC pre burning measurements
MAIN_LOCK set?
N write, burn OTP fuses
30-35h, 16-17h
Set MAIN_LOCK and
SEQ_LOCK
Y
ALT1_LOCK set?
N
MIC trimm #2 write, burn OTP fuses
10-11h
Set ALT1_LOCK
Y
ALT2_LOCK set?
N
MIC trimm #3 write, burn OTP fuses
12-13h
Set ALT2_LOCK
Y
ALT3_LOCK set?
N
MIC trimm #4 write, burn OTP fuses
14-15h
Set ALT3_LOCK
Y trimm verification verification
OK?
Y leave
“Application Trim” mode
N
ANC post burning measurements leave
“Application Trimm” mode verification
OK?
Y
Device trimming succeeded
N
Device trimming failed leave
“Application Trimm” mode
No further MIC trimming possible
9.8 2-Wire-Serial Control Interface
There is an I2C slave block implemented to have access to 64 byte of setting information.
The I2C address is: Adr_Group8 - audio processors
8Eh_write
8Fh_read
9.8.1 Protocol
Table 13. 2-Wire Serial Symbol Definition
Symbol
S
Sr
DW
DR
WA
A
N reg_data data (n)
Definition
Start condition after stop
Repeated start
Device address for write
Device address for read
Word address
Acknowledge
No Acknowledge
Register data/write
Register data/read
R
R
R
W
W
RW
R
R
R
R
Note
1 bit
1 bit
1000 1110b (8Eh)
1000 1111b (8Fh)
8 bit
1 bit
1 bit
8 bit
8 bit www.ams.com/ANC Revision 1.10
24 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 13. 2-Wire Serial Symbol Definition
Symbol
P
WA++
Definition
Stop condition
Increment word address internally
AS3421 AS3422 (=slave) receives data
AS3421 AS3422 (=slave) transmits data
Figure 29. Byte Write
RW
R
R
Note
1 bit during acknowledge
S DW A WA A reg_data A P write register
WA++
Figure 30. Page Write
S DW A WA A reg_data 1 A reg_data 2 A write register
WA++ write register
WA++
...
reg_data n A P write register
WA++
Byte Write and Page Write formats are used to write data to the slave.
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The devicewrite address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally.
www.ams.com/ANC Revision 1.10
25 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 31. Random Read
S DW A WA A Sr DR A read register
WA++ data N P
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
Figure 32. Sequential Read
S DW A WA A Sr DR A read register
WA++ data A reg_data 2 read register
WA++
A read register
WA++
...
reg_data n N P
Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the
Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
Figure 33. Current Address Read
S DR A read register
WA++ data A reg_data 2 read register
WA++
A read register
WA++
...
reg_data n N P
To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer.
The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition.
www.ams.com/ANC Revision 1.10
26 - 61
AS3421/22
Datasheet - D e t a i l e d D e s c r i p t i o n
9.8.2 Parameter
Figure 34. 2-Wire Serial Timing
TS T
SU
T
H
CSDA
CSCL
1-7
Start
Condition
Address R/W
9
ACK
T
HD
T
L
1-7
Data
9
ACK
T
PD
1-7
Data
9
ACK Stop
Condition
VBAT >=1.4V
1
, T
A
=25ºC, unless otherwise specified.
Table 14. 2-Wire Serial Parameter
Symbol
V
CSL
V
CSH
HYST
V
OL
Tsp
T
H
T
L
Parameter
CSCL, CSDA Low Input Level
CSCL, CSDA High Input Level
CSCL, CSDA Input Hysteresis
CSDA Low Output Level
Spike insensitivity
Clock high time
Clock low time
T
T
T
SU
HD
TS
PD
Condition
(max 30%VBAT)
CSCL, CSDA (min 70%VBAT) at 3mA max. 400kHz clock speed max. 400kHz clock speed
CSDA has to change Tsetup before rising edge of CSCL
No hold time needed for CSDA relative to rising edge of CSCL
CSDA H hold time relative to CSDA edge for start/stop/rep_start
CSDA prop delay relative to low going edge of
CSCL
Min
0
0.98
200
-
50
500
500
250
0
200
-
-
-
50
Typ
-
-
450
-
100
-
-
-
Max
0.42
800
0.4
-
Unit
V ns ns ns
V mV
V ns ns ns ns
1. Serial interface operates down to VBAT = 1.0V but with 100kHz clock speed and degraded parameters. www.ams.com/ANC Revision 1.10
27 - 61
10 Register Description
Table 15. I2C Register Overview
Addr Name
Audio Registers
00-07h reserved
08h
09h
0Ah
0Bh
0Ch
MIC_L
MIC_R
LINE_IN
GP_OP_L
GP_OP_R
b7 b6 b5 b4 b3 b2 b1
MIC_MODE
0: StereoSingleEnd
1: MonoDiff
MIC_REG_ON
0: use reg 30h & 31h
1: use reg 08h & 09h
LIN_REG_ON
0: use reg 33h and VOL pin
1: use reg 0Ah
HP_MUX<1:0>
0: MIC; 1: OP1;
2: OP2; 3: open
OP_REG_ON
0: use reg 34h
1: use reg 0Bh & 0Ch
MICL_VOL<6:0>
Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
MICR_VOL<6:0>
Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
LIN_GAIN_+3dB
0: 0dB max. Line Gain
1: +3dB max. Line Gain
HP_MODE
0: StereoSingleEnd
1: MonoDiff
LIN_VOL<5:0>
0: MUTE;
0x01..0x3F: Gain from LINR/L to QLINR/L or Mixer = -46.5dB...+0dB; 63 steps of 0.75dB with LIN_GAIN_+3dB bit set to ‘0’
0x01..0x3F: Gain from LINR/L to QLINR/L or Mixer = -43.5dB...+3dB; 63 steps of 0.75dB with LIN_GAIN_+3dB bit set to ‘1’
OP2L<3:0>
0: OP2L inverting mode;
0x1..0xF: OP2L non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB
OP2R<3:0>
0: OP2R inverting mode;
0x1..0xF: OP2R non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB
OP2L_ON
OP2R_ON
0Dh-0Fh reserved
18h-1Fh reserved
System Register
20h SYSTEM REG3F_ON MONITOR_ON CONT_PWRUP
21h PWR_SET
Design_Version<3:0> 1001
PWR_REG_ON
0: use reg 0x35
1: use reg 0x21h
HP_ON MIC_ON LIN_ON MICS_CP_ON
LOW_BAT
PWRUP_
COMPLETE
22h-2Fh reserved
b0
OP1L_ON
OP1R_ON
PWR_HOLD
MICS_ON
Table 15. I2C Register Overview
Addr
OTP Register
Name
10h
11h
12h
13h
14h
15h
16h
17h
30h
31h
32h
33h
34h
35h
3Eh
3Fh
ANC_L2
ANC_R2
ANC_L3
ANC_R3
ANC_L4
ANC_R4
MICS_CNTR
PWRUP
ANC_L
ANC_R
MIC_MON
AUDIO_SET
GP_OP
OTP_SYS
CONFIG_1
CONFIG_2
b7 b6 b5 b4 b3 b2 b1 b0
TEST_BIT_5
ALT1_LOCK
TEST_BIT_6
ALT2_LOCK
TEST_BIT_7
ALT3_LOCK
SEQ_LOCK
TEST_BIT_1
TEST_BIT_2
MON_MODE
0: fixed volume
1: adj. volume
NO_PB_MODE_OTP
0: PB mode enabled
1: PB mode disabled
HP_MUX_OTP<1:0>
0: MIC; 1: OP1;
2: OP2; 3: -
MAIN_LOCK
0: write reg 30h.. 35h
1: lock reg 30h..35h
MICL_VOL_OTP2<6:0>
Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
MICR_VOL_OTP2<6:0>
Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
MICL_VOL_OTP3<6:0>
Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
MICR_VOL_OTP3<6:0>
Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
MICL_VOL_OTP4<6:0>
Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
MICR_VOL_OTP4<6:0>
Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
LowBat + 100mV DEL_ ANC_MUX
FAST_START<4:0>
0: ~900ms; 0Eh: ~600ms
MICL_VOL_OTP<6:0>
Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
MICR_VOL_OTP<6:0>
Gain from MICR to QMICR or Mixer =MUTE, -11.25dB...+36dB; 127 steps of 0.375dB
LIN_AGC_OFF MIC_AGC_OFF
MIC_MON_OTP<6:0>
Gain from MICl/R to QMICL/R or Mixer = MUTE, -5.625dB...+41.6dB; 0.375dB steps, if MON_MODE is set to 0
Gain from MICl/R to QMICL/R or Mixer = MUTE, -5.625dB...+41.6dB; 0.375dB steps, adjustable by VOL pin if MON_MODE is set to 1
VOL_BUTTON_
MODE_OTP
0: Volume Mode disabled
1: Volume Mode enabled
LINE_GAIN_+3dB
OTP
0: 0dB max. Line Gain
1: +3dB max. Line Gain
MIC_MODE_
OTP
0: StereoSingleEnd
1: MonoDiff
HP_MODE_
OTP
0: StereoSingleEnd
1: MonoDiff
LIN_MON_ATTEN<2:0>
0: no attenuation;
1..6: LIN_VOL<6:0> shift by -6dB...-36dB
7: MUTE
TEST_BIT_3
OP2_OTP<3:0>
0: OP2 inverting mode;
0x1..0xF: OP2 non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB
MON_HP_MUX<1:0>
0: MIC; 1: OP1;
2: OP2; 3: -
EXTBURNCLK
CP_MODE
0: Low noise, low voltage
1: High output voltage;
OP2_ON_OTP
MICS_CP_OFF
OP1_ON_OTP
I2C_MODE
TM34 BURNSW TM_REG34-35 TM_REG30-33
OTP_MODE<1:0>
0: READ; 1: LOAD;
2: WRITE; 3: BURN
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 16. MIC_L Register
Name
MIC_L
Bit
7
6:0
Offset: 08h
Bit Name
MIC_MODE
MICL_VOL<6:0>
Base
2-wire serial
Left Microphone Input Register
Default
00h
Configures the gain for the left microphone input and defines the microphone operation mode. This register is reset at POR.
Default
0
Access
R/W
000 0000 R/W
Bit Description
Selects the microphone input mode
0: single ended stereo mode
1: mono differential mode
Volume settings for left microphone input, adjustable in 127 steps of
0.375dB
00 0000: MUTE
00 0001: -11.25 dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625 dB gain
11 1111: 36 dB gain
Table 17. MIC_R Register
Name
MIC_R
Bit
7
6:0
Offset: 09h
Bit Name
MIC_REG_ON
MICR_VOL<6:0>
Base
2-wire serial
Default
00h
Right Microphone Input Register
Configures the gain for the right microphone input and enables register 08h & 09h. This register is reset at
POR.
Default
0
000 0000
Access
R/W
R/W
Bit Description
Defines which registers are used for the microphone settings.
0: settings of register 30h and 31h are used
1: settings of register 08h and 09h are used
Volume settings for right microphone input, adjustable in 127 steps of
0.375dB
00 0000: MUTE
00 0001: -11.25B gain
00 0010: -10.875 dB gain
..
11 1110: 35.625 dB gain
11 1111: 36 dB gain www.ams.com/ANC Revision 1.10
30 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 18. LINE_IN Register
Bit
7
6
5:0
Offset: 0Ah
Name
LINE_IN
Bit Name
LIN_REG_ON
LINE_GAIN_+3dB
LIN_VOL<5:0>
Base
2-wire serial
Line Input Register
Default
00h
Configures the attenuation for the line input, defines the line input operation mode and enables register
0Ah. This register is reset at POR.
Default
0
Access
R/W
0
00 0000
R/W
R/W
Bit Description
Defines which source is used for the line input settings.
0: settings of register 33h and VOL pin are used
1: register 0Ah is used
Selects the line input operating gain range. If this bit is set the gain range of the line input amplifiers is shifted by +3dB.
0: Line Input gain range from -46.5dB...0dB
1: Line Input gain range from -43.5dB...+3dB
Volume settings for line input, adjustable in 63 steps of 0.75dB. the following gain settings are valid if LINE_GAIN_+3dB bit is set to ‘0’.
00 0000: MUTE
00 0001:-46.5dB gain
00 0010:-45.75dB gain
..
11 1110:-0.75dB gain
11 1111:.0 dB gain
Volume settings for line input, adjustable in 63 steps of 0.75dB. the following gain settings are valid if LINE_GAIN_+3dB bit is set to ‘1’.
00 0000: MUTE
00 0001:-43.5dB gain
00 0010:-42.75dB gain
..
11 1110:+2.25dB gain
11 1111:+3 dB gain
Table 19. GP_OP_L Register
Name
GP_OP_L
Bit
7:6
5:2
Offset: 0Bh
Bit Name
HP_MUX<1:0>
OP2L<3:0>
Base Default
2-wire serial
Left General Purpose Operational Amplifier Register
00h
Enables the left opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This register is reset at POR.
Default
00
Access
R/W
0000 R/W
Bit Description
Multiplexes the analog audio signal to HP amp
00: MIC: selects QMICL/R output
01: OP1: selects QOP1L/R outputs
10:OP2: selects QOP2L/R output
11: open: no signal mixed together with the line input signal
Mode and volume settings for left OP2, adjustable in 15 steps of 0.75dB
0000: OP2L in inverting mode
0001: 0 dB gain, OP2L in non inverting mode
0001: 0.75 dB gain, non inverting
..,
1110: 9.75dB gain, non inverting
1111:.10.5 dB gain, non inverting www.ams.com/ANC Revision 1.10
31 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 19. GP_OP_L Register
Name
GP_OP_L
Bit
1
0
Offset: 0Bh
Bit Name
OP2L_ON
OP1L_ON
Base
2-wire serial
Default
00h
Left General Purpose Operational Amplifier Register
Enables the left opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This register is reset at POR.
Default
0
Access
R/W
Bit Description
0 R/W
Enables left OP 2
0: left OP2 is switched off
1: left OP2 is enabled
Enables left OP 1
0: left OP1 is switched off
1: left OP1 is enabled
Table 20. GP_OP_R Register
Name
GP_OP_R
Bit
7
6
5:2
1
0
Offset: 0Ch
Bit Name
OP_REG_ON
HP_MODE
OP2R<3:0>
OP2R_ON
OP1R_ON
Base Default
2-wire serial 00h
Right General Purpose Operational Amplifier Register
Enables the right opamp stages, defines opamp 2 mode and gain and sets the HP mode. This register is reset at POR.
Default
0
Access
R/W
0
0000
0
0
R/W
R/W
R/W
R/W
Bit Description
Defines which register is used for the opamp and HP settings.
0: settings of register 33h and 34h are used
1: register 0B and 0Ch are used
Selects the line input mode
0: single ended stereo mode
1: mono differential mode
Mode and volume settings for right OP2, adjustable in 15 steps of 0.75dB
0000: OP2R in inverting mode
0001: 0 dB gain, OP2R in non inverting mode
0001: 0.75 dB gain, non inverting
..,
1110: 9.75dB gain, non inverting
1111:.10.5 dB gain, non inverting
Enables right OP 2
0: right OP2 is switched off
1: right OP2 is enabled
Enables right OP 1
0: right OP1 is switched off
1: right OP1 is enabled www.ams.com/ANC Revision 1.10
32 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 21. SYSTEM Register
Bit
7:4
3
2
1
0
Offset: 20h
Name
SYSTEM
Bit Name
Design_Version<3:0>
TESTREG_ON
MONITOR_ON
CONT_PWRUP
PWR_HOLD
Base
2-wire serial
SYSTEM Register
Default
31h
This register is reset at a POR.
Default
1001
Access
R
0
0
0
1
R/W
R/W
R/W
R/W
Bit Description
AFE number to identify the design version
1001: for chip version 1v1
0: normal operation
1: enables writing to test register 3Eh & 3Fh to configure the OTP and set the access mode.
Enables the monitor mode
0: normal operation
1: monitor mode enabled
Continues the automatic power-up sequence when using the I2C mode
0: chip stops the power-up sequence after the supplies are stable, switching on individual blocks has to be done via I2C commands
1: automatic power-up sequence is continued
0: power up hold is cleared and AFE will power down
1: is automatically set to on after power on
Table 22. PWR_SET Register
Bit
7
6
5
4
3
Name
PWR_SET
Offset: 21h
Bit Name
PWR_REG_ON
LOW_BAT
PWRUP_COMPLETE
HP_ON
MIC_ON
Base
2-wire serial
Default
0x11 1111b (stand alone mode)
0x00 0000b (I2C mode)
Power Setting Register
Please be aware that writing to this register will enable/disable the corresponding blocks, while reading gets the actual status. It is not possible to read back e.g ILED settings. This register is reset at POR.
Default
0
Access
R/W x x
0 x
0 x
R
R
W
R
W
R
Bit Description
Defines which register is used for the power settings.
0: all blocks stay on as defined in the start-up sequence
1: register 21h is used
VBAT supervisor status
0: VBAT is above brown out level
1: BVDD has reached brown out level
Power-Up sequencer status
0: power-up sequence incomplete
1: power-up sequence completed
0: switches HP stage off
1: switches HP stage on
0: HP stage not powered
1: normal operation
0: switches microphone stage off
1: switches microphone stage on
0: microphone stage not powered
1: normal operation www.ams.com/ANC Revision 1.10
33 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 22. PWR_SET Register
Name
PWR_SET
Bit
2
1
0
Offset: 21h
Bit Name
LIN_ON
MICS_CP_ON
MICS_ON
Base
2-wire serial
Default
0x11 1111b (stand alone mode)
0x00 0000b (I2C mode)
Power Setting Register
Please be aware that writing to this register will enable/disable the corresponding blocks, while reading gets the actual status. It is not possible to read back e.g ILED settings. This register is reset at POR.
Default
0
Access
W x
0 x
0 x
R
W
R
W
R
Bit Description
0: switches line input stage off
1: switches line input stage on
0: line input stage not powered
1: normal operation
0: switches microphone supply charge pump off
1: switches microphone supply charge pump on
0: microphone supply charge pump not powered
1: normal operation
0: switches microphone supply off
1: switches microphone supply on
0: microphone supply not enabled
1: normal operation www.ams.com/ANC Revision 1.10
34 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 23. ANC_L2 Register
Name
ANC_L2
Bit
7
6:0
Offset: 10h
Bit Name
TEST_BIT_5
MICL_VOL_OTP2
<6:0>
Base Default
2-wire serial 80h (OTP)
Left OTP Microphone Input Register (2nd OTP option)
Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
1
000 0000
Access
R
R/W
Bit Description
for testing purpose only
Volume settings for left microphone input, adjustable in 127 steps of
0.375dB
00 0000: MUTE
00 0001: -11.25dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625dB gain
11 1111: 36 dB gain
Table 24. ANC_R2 Register
Name
ANC_R2
Bit
7
6:0
Offset: 11h
Bit Name
ALT1_LOCK
MICR_VOL_OTP2
<6:0>
Base
2-wire serial
Default
00h (OTP)
Right OTP Microphone Input Register (2nd OTP option)
Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
0
000 0000
Access
R/W
R/W
Bit Description
0: additional bits can be fused inside register 10h & 11h
1: OTP fusing for register 10h & 11h gets locked, no more changes can be done.
Volume settings for right microphone input, adjustable in 127 steps of
0.375dB
00 0000: MUTE
00 0001: -11.25dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625dB gain
11 1111: 36 dB gain www.ams.com/ANC Revision 1.10
35 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 25. ANC_L3 Register
Name
ANC_L3
Bit
7
6:0
Offset: 12h
Bit Name
TEST_BIT_6
MICL_VOL_OTP3
<6:0>
Base Default
2-wire serial 80h (OTP)
Left OTP Microphone Input Register (3rd OTP option)
Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
1
000 0000
Access
R
R/W
Bit Description
for testing purpose only
Volume settings for left microphone input, adjustable in 127 steps of
0.375dB
00 0000: MUTE
00 0001: -11.25dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625dB gain
11 1111: 36 dB gain
Table 26. ANC_R3 Register
Name
ANC_R3
Bit
7
6:0
Offset: 13h
Bit Name
ALT2_LOCK
MICR_VOL_OTP3
<6:0>
Base
2-wire serial
Default
00h (OTP)
Right OTP Microphone Input Register (3rd OTP option)
Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
0
000 0000
Access
R/W
R/W
Bit Description
0: additional bits can be fused inside register 12h & 13h
1: OTP fusing for register 12h & 13h gets locked, no more changes can be done.
Volume settings for right microphone input, adjustable in 127 steps of
0.375dB
00 0000: MUTE
00 0001: -11.25dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625dB gain
11 1111: 36 dB gain www.ams.com/ANC Revision 1.10
36 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 27. ANC_L4 Register
Name
ANC_L4
Bit
7
6:0
Offset: 14h
Bit Name
TEST_BIT_7
MICL_VOL_OTP4
<6:0>
Base Default
2-wire serial 80h (OTP)
Left OTP Microphone Input Register (4th OTP option)
Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
1
000 0000
Access
R
R/W
Bit Description
for testing purpose only
Volume settings for left microphone input, adjustable in 127 steps of
0.375dB
00 0000: MUTE
00 0001: -11.25dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625dB gain
11 1111: 36 dB gain
Table 28. ANC_R4 Register
Name
ANC_R4
Bit
7
6:0
Offset: 15h
Bit Name
ALT3_LOCK
MICR_VOL_OTP4
<6:0>
Base
2-wire serial
Default
00h (OTP)
Right OTP Microphone Input Register (4th OTP option)
Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
0
000 0000
Access
R/W
R/W
Bit Description
0: additional bits can be fused inside register 14h & 15h
1: OTP fusing for register 14h & 15h gets locked, no more changes can be done.
Volume settings for right microphone input, adjustable in 127 steps of
0.375dB
00 0000: MUTE
00 0001: -11.25dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625dB gain
11 1111: 36 dB gain www.ams.com/ANC Revision 1.10
37 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 29. MICS_CNTR Register
Name
MICS_CNTR
Bit
3
0
Offset: 16h
Bit Name
LowBat
DEL_ ANC_MUX
Base
2-wire serial
Microphone Supply Regsiter
Configures the low battery threshold value
Default
0
0
Access
R/W
R/W
Bit Description
Default
00h (OTP)
0: default LowBat value
1: 100mV increase of LowBat threshold
0: default startup timing of AS3421/22
1: HP_MUX_OTP is set to OTP value 0.8s after device startup
Table 30. PWRUP_CNTR Register
Bit
7
6:2
1
0
Name
PWRUP_CNTR
Offset: 17h
Base
2-wire serial
Default
00h (OTP)
PowerUp Control Register
Configures chip start-up speed. This is a special register, writing needs to be enabled by writing 10b to
Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Bit Name
SEQ_LOCK
Default
0
Access
R/W
FAST_START
<4:0>
LIN_AGC_OFF
MIC_AGC_OFF
0 0000
0
0
R/W
R/W
R/W
Bit Description
0: additional bits can be fused inside register 16h & 17h
1: OTP fusing for register 16h & 17h gets locked, no more changes can be done.
0h: ~900ms start-up time
0Eh: ~600ms start-up time
0: Line Input AGC enabled
1: Line Input AGC switched off
0:Microphone Input AGC enabled
1: Microphone Input AGC switched off
Table 31. ANC_L Register
Name
ANC_L
Bit
7
6:0
Offset: 30h
Bit Name
TEST_BIT_1
MICL_VOL_OTP
<6:0>
Base
2-wire serial
Default
80h (OTP)
Left OTP Microphone Input Register
Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
1
000 0000
Access
R
R/W
Bit Description
for testing purpose only
Volume settings for left microphone input, adjustable in 127 steps of 0.375dB
00 0000: MUTE
00 0001: -11.25dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625dB gain
11 1111: 36 dB gain www.ams.com/ANC Revision 1.10
38 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 32. ANC_R Register
Name
ANC_R
Bit
7
6:0
Offset: 31h
Bit Name
TEST_BIT_2
MICR_VOL_OTP
<6:0>
Base
2-wire serial
Default
80h (OTP)
Right OTP Microphone Input Register
Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
1
000 0000
Access
R
R/W
Bit Description
for testing purpose only
Volume settings for right microphone input, adjustable in 127 steps of
0.375dB
00 0000: MUTE
00 0001: -11.25dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625dB gain
11 1111: 36 dB gain www.ams.com/ANC Revision 1.10
39 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 33. MIC_MON Register
Name
MIC_MON
Bit
7
6:0
Offset: 32h
Bit Name
MON_MODE
MIC_MON_OTP
<6:0>
Base
2-wire serial
OPT Microphone Monitor Mode Register
Default
00h (OTP)
Configures the gain for the microphone input in monitor mode. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
0
Access
R/W
000 0000 R/W
Bit Description
0: monitor mode is working with fixed microphone gain
1: monitor mode uses adjustable gain via the VOL pin
Volume settings for microphone input during monitor mode, adjustable in
127 steps of 0.375dB. If MON_MODE bit is set to 1 the gain can be further adjusted via the VOL pin.
00 0000: MUTE
00 0001: -11.25dB gain
00 0010: -10.875 dB gain
..
11 1110: 35.625dB gain
11 1111: 36 dB gain
Table 34. AUDIO_SET Register
Bit
7
6
5
4
Name
AUDIO_SET
Offset: 33h
Bit Name
NO_PB_MODE
VOL_BUTTON_MODE
LINE_GAIN_+3dB_OTP
MIC_MODE_OTP
Base
2-wire serial
Default
00h (OTP)
OPT Audio Setting Register
Configures the audio settings. This is a special register, writing needs to be enabled by writing 10b to Reg
3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
0
Access
R/W
0
0
0
R/W
R/W
R/W
Bit Description
This bit defines if the low power music playback mode is enabled or not. In case the bit is set to ‘0’, music playback mode can be entered by pulling the
ANC_CSDA pin low. In case the bit is set to ‘1’ the music playback mode is disabled. Pulling the ANC_CSDA pin low has no influence.
0: Music playback mode enabled
1: Music playback mode disabled
If bit is set to ‘1’ the ANC_CSDA pin allows the user to control the line input gain via push-buttons. If bit is set to ‘0’, the volume control is disabled.
Please mind that if VOL_BUTTON_MODE bit is set to ‘1’ entering music playback mode via ANC_CSDA pin is not possible any more.
0: Volume mode via push-button disabled
1: Volume mode via push-button enabled
Selects the line input operating gain range. If this bit is set the gain range of the line input amplifiers is shifted by +3dB.
0: Line Input gain range from -46.5dB...0dB
1: Line Input gain range from -43.5dB...+3dB
0: microphone input stage operating in single ended mode
1: normal operating in mono balanced www.ams.com/ANC Revision 1.10
40 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 34. AUDIO_SET Register
Name
AUDIO_SET
Bit
3
2:0
Offset: 33h
Bit Name
HP_MODE_OTP
LIN_MON_ATTEN
<6:0>
Base
2-wire serial
Default
00h (OTP)
OPT Audio Setting Register
Configures the audio settings. This is a special register, writing needs to be enabled by writing 10b to Reg
3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
0
000
Access
R/W
R/W
Bit Description
0: headphone stage operating in single ended mode
1: normal operating in mono balanced
Volume settings for line input during monitor mode, adjustable in 7 steps of
6dB and mute.
000: 0dB gain
001: -6dB gain
..
110: -36dB gain
111: MUTE www.ams.com/ANC Revision 1.10
41 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 35. GP_OP Register
Bit
7:6
5:2
1
0
Offset: 34h
Name
GP_OP
Bit Name
HP_MUX_OTP<1:0>
OP2_OTP<3:0>
OP2_ON
OPL_ON
Base Default
2-wire serial 00h (OTP)
OTP General Purpose Operational Amplifier Register
Enables the opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at
POR and gets loaded with the OTP fuse contents.
Default
00
Access
R/W
0000
0
0
R/W
R/W
R/W
Bit Description
Multiplexes the analog audio signal to HP amp
00: MIC: selects QMICL/R output
01:OP1: selects QOP1L/R outputs
10:OP2: selects QOP2L/R output
11: open: no signal mixed together with the line input signal
Mode and volume settings for OP2, adjustable in 15 steps of 0.75dB
0000: OP2L in inverting mode
0001: 0 dB gain, OP2L in non inverting mode
0001: 0.75 dB gain, non inverting
..,
1110: 9.75dB gain, non inverting
1111:.10.5 dB gain, non inverting
0: OP2 is switched off
1: left OP2 is enabled
0: OP1 is switched off
1: OP1 is enabled
Table 36. OTP_SYS Register
Name
OTP_SYS
Bit
7
6
5:4
2
1
0
Offset: 35h
Bit Name
MAIN_LOCK
TEST_BIT_3
MON_HP_MUX
<1:0>
CP_MODE_OTP
MICS_CP_OFF
I2C
Base
2-wire serial
Default
40h (OTP)
OTP System Settings Register
Defines several system settings for OTP operation. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
0
Access
R/W
1
00
0
0
0
R
R/W
R/W
R/W
R/W
Bit Description
0: additional bits can be fused inside the OTP
1: OTP fusing gets locked, no more changes can be done for testing purpose only
Multiplexes the analog audio signal to HP amp in monitor mode
00: MIC: selects QMICL/R output
01: OP1: selects QOP1L/R outputs
10:OP2: selects QOP2L/R output
11: open: no signal mixed together with the line input signal
This bit controls the operating mode of the microphone supply charge pump.
0: Standard low noise operation
1: Increased output voltage
0: MICS charge pump is enabled
1: MICS charge pump is switched off
0: I2C and stand alone mode start-up possible
1: chip starts-up in I2C mode only www.ams.com/ANC Revision 1.10
42 - 61
AS3421/22
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 37. CONFIG_1 Register
Name
CONFIG_1
Bit
7:4
3
2:0
Offset: 3Eh
Bit Name
-
EXTBURNCLK
-
Base
2-wire serial
OTP Configuration Register
Default
00h
Controls the clock configuration. This is a special register, writing needs to be enabled by writing 9h to
Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents.
Bit Description Default
0000
0
Access
n/a n/a
0: ext. clock for OTP burning disabled
1: ext. clock for OTP burning enabled
000 n/a
Table 38. CONFIG_2 Register
Name
CONFIG_2
Bit
7:6
5
4
3
2
1:0
Offset: 3Fh
Bit Name
-
TM34
BURNSW
TM_REG34-35
TM_REG30-33
OTP_MODE<1:0>
Base
2-wire serial
Default
00h
OTP Access Configuration Register
Controls the OTP access. This is a special register, writing needs to be enabled by writing 9h to Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents.
Default
000
0
Access
n/a n/a
Bit Description
0
0
0
00 n/a n/a n/a
R/W
This Register defines the Register bank selection for Register
TM_REG34-35 and TMREG30-33. Depending on TM34 you can select either between Register bank 14h-17h and 10h-13h enabled or 30h-33h and
34h-37h enabled.
0: test mode Registers 14h-17h and 10h-13h disabled
test mode Registers 30h-33h and 34h-37h enabled
1: test mode Registers 14h-17h and 10h-13h enabled
test mode Registers 30h-33h and 34h-37h disabled
0: BURN switch from LINL to VNEG is disabled
1: BURN switch from LINL to VNEG is enabled
0: test mode for Register 34h-35h disabled test mode for Register 14h-17h disabled
1: test mode for Register 34h-35h enabled
test mode for Register 14h-17h enabled
0: test mode for Register 30h-33h disabled test mode for Register 10h-13h disabled
1: test mode for Register 30h-33h enabled
test mode for Register 10h-13h enabled
Controls the OTP access
00: READ
01: LOAD
10: WRITE
11: BURN www.ams.com/ANC Revision 1.10
43 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
11 Application Information
11.1 AS3422 Feedback Application Examples
Figure 35. AS3422 Feedback Application Example with Bluetooth I2C Control
www.ams.com/ANC Revision 1.10
44 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 36. AS3422 Feedback Application Example with Bluetooth ROM Version (No I2C Control)
www.ams.com/ANC Revision 1.10
45 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 37. AS3422 Schematic - Stereo Bluetooth Feedback Application with I2C Control
30
29
31
28
27
25
26
33
32
L
L
2L IOP
QOP2
QOP1
VNEG
VNEG
CPN
GND
CPP
VBAT
13
12
14
10
11
9
16
15
R
1R IOP
QLIN
R
S
L
R
MIC
MIC
MIC
CSCL
QMIC
CSDA uF 4.7
uF 4.7
10uF
C14
C13
C12 www.ams.com/ANC Revision 1.10
46 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 38. AS3422 Schematic - Stereo Bluetooth Feedback Application with ROM Version (No I2C Control)
L
L
2L IOP
QOP2
QOP1
VNEG
VNEG
CPN
GND
CPP
VBAT
31
30
29
28
27
26
25
33
32
R
R
1R IOP
QLIN
QMIC
S
L
R
MIC
MIC
MIC
CSCL
CSDA
15
14
16
13
12
10
11
9
4.7uF
10uF
4.7uF
4 C1
C13
2 C1
1 1
1 2 www.ams.com/ANC Revision 1.10
47 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
11.2 AS3421 Feed Forward Application Examples
Figure 39. AS3421 Feed-Forward Application Example with Bluetooth I2C Control
www.ams.com/ANC Revision 1.10
48 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 40. AS3421 Feed-Forward Application Example with Bluetooth ROM Version (No I2C Control)
www.ams.com/ANC Revision 1.10
49 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 41. AS3421 Schematic - Stereo Feed-Forward Bluetooth Application with I2C Control
22
21
20
19
24
23
25
AD
L
1L IOP
QOP1
EX_P
VNEG
CPN
GND
CPP
L SC _C
R
S
L
R MIC
MIC
MIC
MODE
QMIC
ANC_CSDA
11
10
12
8
7
9 uF 4.7
uF 4.7
10μF
C14
C13
C12 www.ams.com/ANC Revision 1.10
50 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 42. AS3421 Schematic - Stereo Feed-Forward Bluetooth Application ROM Version (No I2C Control)
24
23
25
22
21
20
19
L
1L IOP
QOP1
VNEG
CPN
GND
CPP
EX_PAD
CL
A SD
CS
R
S
L
R
MIC
MIC
MIC
MODE_
QMIC
ANC_C
8
7
9
10
12
11
4.7uF
10μF
4.7uF
4 C1
C13
2 C1
1 1
1 2 www.ams.com/ANC Revision 1.10
51 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
11.3 Layout Recommendation
Whereever you have audio circuits mixed with power management layout of the blocks is a critical issue. The AS3421/22 has an integrated charge pump which operates at a frequency of 1Mhz. If the layout of the PCB is not done properly the charge pump can directly influence the audio performance of the device. Therefore it is very important to make sure that the layout of the charge pump is done properly.
The layout recommendation shown in Figure 43 below shows an example placement of the components of the charge pump. The reference designators of the components used in the example refer to the schematic shown in Figure 37 . It can be seen clearly that the ground pins of all capacitors as well as the ground pin of AS3422 are placed closely. This compact placement of the components help to minimize high frequency cross over currents all over the PCB and therefore helps to improve the audio quality. A dedicated ground plane on the top (red) layer minimizes the resistance between the ground pads of the components. The ground plane (GND) is then connected to the analog ground (AGND) at a single point which is indicated with three vias in the example.
Figure 43. AS3422 CP Layout Recommendation
IA connection to analog round plane (AGND)
If the physical alignment of the components allows it, it is also recommended to connect the charge pump ground plane on top layer directly to the battery ground terminal of your device. The analogue- (AGND) and charge pump ground plane (GND) are then connected together directly at the battery terminal. This concept is also know as star shaped ground concept shown in Figure 44 below.
Figure 44. AS3422 Star Shaped Ground Concept
Charge pump ground (GND) and analog ground (AGND) are directly connected together at negative battery terminal.
www.ams.com/ANC Revision 1.10
52 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
The layout examples showed in the examples before are based on AS3422. The AS3421 has of course a smaller package than AS3422, therefore the alignment of the charge pump components is different. A layout recommendation for AS3421 is shown in Figure 45 below.
Figure 45. AS3421 CP Layout Recommendation
VIA connection to analog round plane (AGND)
11.4 Bill of Materials
The following section shows the Bill of Materials which is necessary to operate the device. The necessary R-C filter networks which are necessary for gain- and phase compensation are excluded. These components very much depend on the acoustic design of each headset. Both devices basically need 17 external component for standard operation without the necessary filter components. The reference designator of the components shown in Table 39 refer to the schematics shown in Figure 37 and Figure 41 .
Table 39. AS3421/22 Bill of Materials
8
9
10
11
12
Sum
6
7
4
5
2
3
1
POS Reference
U1
U2
C3, C15
Value/Name
AS3421
Description
Stereo Bluetooth ANC headphone driver circuit
AS1363-AD Low Drop Voltage Regulator
1µF Charge Pump flying capacitor; +/- 10% tolerance and LDO support
C1, C6 100nF
C7, C8, C9, C10 220nF
C13
C12, C14
10µF
4.7uF
PMU Blocking capacitors; +/- 10% tolerance
Audio DC coupling capacitors; +/- 10% tolerance
Microphone supply filter capacitor; +/- 10% tolerance
Microphone DC coupling capacitors; +/-5% tolerance
R5, R6
C2, C5
R7
R8
R3, R4
2k2
10µF
15k
47k
10k
Microphone bias resistors; +/- 5%tolerance
PMU Blocking capacitors; +/- 10% tolerance
Voltage Regulator feedback resistor
Voltage Regulator feedback resistor
Two wire interface pull up resistors; +/- 10% tolerance
1
1
2
2
2
21
1
2
2
4
1
1
2
Count
www.ams.com/ANC Revision 1.10
53 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
11.5 PCB Footprint Recommendation
Figure 46. AS3421 PCB Footprint Recommendation
Pin 1
www.ams.com/ANC
Pin 1
Pin 1
RECOMMENDED LAND PATTERN
OW COMPONENT DENSITY
TOP VIEW
Silk Screen
RECOMMENDED LAND PATTERN
MEDIUM COMPONENT DENSITY
TOP VIEW
Silk Screen
Revision 1.10
RECOMMENDED LAND PATTERN
HIGH COMPONENT DENSITY
TOP VIEW
Silk Screen
54 - 61
AS3421/22
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 47. AS3422 PCB Footprint Recommendation
Pin 1
www.ams.com/ANC
Pin 1
Pin 1
RECOMMENDED LAND PATTERN
OW COMPONENT DENSITY
TOP VIEW
Silk Screen
RECOMMENDED LAND PATTERN
MEDIUM COMPONENT DENSITY
TOP VIEW
Silk Screen
Revision 1.10
RECOMMENDED LAND PATTERN
HIGH COMPONENT DENSITY
TOP VIEW
Silk Screen
55 - 61
AS3421/22
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g
12 Package Drawings and Marking
Figure 48. QFN Marking
Table 40. Package Code YYWWIZZ
YY
last two digits of the year
WW
manufacturing week
X
plant identifier
ZZ
free choice / traceability code www.ams.com/ANC Revision 1.10
56 - 61
AS3421/22
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g
Figure 49. AS3421, 24-pin QFN 0.5mm Pitch
www.ams.com/ANC Revision 1.10
57 - 61
AS3421/22
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g
Figure 50. AS2322 32-pin QFN 0.5mm Pitch
www.ams.com/ANC Revision 1.10
58 - 61
AS3421/22
Datasheet - R e v i s i o n H i s t o r y
Revision History
Revision
1.00
1.10
Date
25.6.2012
08.04.2013
Owner
hgt hgt
Description
initial release
Updated package marking to new logo, changed Exposed Pad comments
Note:
Typos may not be explicitly mentioned under revision history.
www.ams.com/ANC Revision 1.10
59 - 61
AS3421/22
Datasheet - O r d e r i n g I n f o r m a t i o n
13 Ordering Information
The devices are available as the standard products shown in Table 41 .
Table 41. Ordering Information
Ordering Code Description
AS3421-EQFP
AS3421-EQFP-500
AS3422-EQFP
AS3422-EQFP-500
Low Power Ambient Noise-Cancelling Speaker Driver
Low Power Ambient Noise-Cancelling Speaker Driver
Low Power Ambient Noise-Cancelling Speaker Driver
Low Power Ambient Noise-Cancelling Speaker Driver
Delivery Form
Tape & Reel dry pack
Tape & Reel dry pack
Tape & Reel dry pack
Tape & Reel dry pack
Package
QFN 24 [4.0x4.0x0.85mm] 0.5mm pitch
QFN 24 [4.0x4.0x0.85mm] 0.5mm pitch
QFN 32 [5.0x5.0x0.85mm] 0.5mm pitch
QFN 32 [5.0x5.0x0.85mm] 0.5mm pitch
Note:
All products are RoHS compliant and ams green.
Buy our products or get free samples online at ICdirect: http://www.ams.com/ICdirect
For further information and requests, please contact us mailto:[email protected]
or find your local distributor at http://www.ams.com/distributor www.ams.com/ANC Revision 1.10
60 - 61
AS3421/22
Datasheet - C o p y r i g h t s
Copyrights
Copyright © 1997-2013, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
Contact Information
Headquarters
ams AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit: http://www.ams.com/contact www.ams.com/ANC Revision 1.10
61 - 61
Preuzimanje
Javna poveznica ažurirana
Javna poveznica na vaš razgovor je ažurirana. You may view and manage your chat links after registration here.
Javna poveznica dokumenta
Oglas
