AMS AS5510 Position Sensor Datasheet
AMS AS5510 is a state-of-the-art linear Hall sensor with I²C output, ideal for measuring absolute position of lateral movement. It operates in a wide magnetic range and offers high-resolution output with 10-bit resolution. The AS5510 is suitable for various applications, including position sensing, servo drive feedback, camera lens control, and closed-loop position control.
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General Description
AS5510
Linear Hall Sensor with I²C Output
The AS5510 is a Linear Hall Sensor with 10 bit resolution and I²C interface. It can measure absolute position of lateral movement of a simple 2-pole magnet. Depending on the magnet size, a lateral stroke of 0.5~2mm can be measured with air gaps around 1.0mm. To conserve power, the AS5510 may be switched to a power down state when it is not used. It is available in a WLCSP and SOIC8 package and qualified for an ambient temperature range from -30°C to 85°C.
and
Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS5510, Linear Hall sensor with I²C output are listed below:
Figure 1:
Added Value of Using AS5510
Benefits
Highest reliability and durability
Ideal for battery powered devices
Easy to use
High-resolution output
Operates in wide magnetic range
Smallest form factor
Features
Contactless position measurement
Power down mode
Simple configuration over the I
2
C interface
10bit resolution
Programmable sensitivity
Available in two different packages: WLCSP & SOIC8
Applications
The AS5510 is ideal for:
• Position sensing
• Servo drive feedback
• Camera lens control
• Closed loop position control.
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[v1-07] 2015-Feb-27
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AS5510 −
General Description
Block Diagram
The functional blocks of this device for reference are shown below:
Figure 2:
AS5510 Block Diagram
Front
End
Offset
Compensation
Buffer & Filter
ADC 10 bit
Biasing &
Reference
Factory Gain Trim
Test
DSP
I
2
C
SDA SCL ADR VDD VSS
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AS5510 −
Pin Assignment
Pin Assignment
Pin Configuration of AS5510 in
WLCSP Package(Top view):
The AS5510 is available in a 6-pin Chip
Scale Package with a ball pitch of
400μm.
The AS5510 pin assignments are described below.
Figure 3:
Pin Diagram for WLCSP Package
Pin A1 indicator
A
1
VSS
2
ADR
3
VDD
B
SDA SCL Test
Pin Configuration of AS5510 in SOIC8
Package(Top view):
Package drawing not to scale.
Figure 4:
Pin Diagram for SOIC8 Package
NC
VSS
ADR
VDD
1
2
3
4
8
7
6
5
NC
SCL
SDA
TEST
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AS5510 −
Pin Assignment
Figure 5:
Pin Description
Pin
Name
NC
VSS
Pin Number
WLCSP SOIC8
-
A1
1
2
ADR
VDD
Test
SDA
SCL
NC
A2
A3
B3
B1
B2
-
3
4
5
6
7
8
Pin Type Description
-
Supply pin
Digital input
Supply pin
Not Connected
Negative supply pin, analog and digital ground
I²C address selection pin
Connect to either VSS (56h) or VDD (57h)
Positive supply pin. A capacitor of 100nF should be connected to this pin and VSS
Digital input/output
Test pin, must be connected to VSS during operation
Digital input / Digital output open drain
I²C data I/O, 20mA driving capability
Digital input
-
I²C clock
Not Connected
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AS5510 −
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed in
may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 6:
Absolute Maximum Ratings
Parameter
DC supply voltage at pin VDD
Input pin voltage
Input current (latchup immunity)
Electrostatic discharge
Storage temperature
Body temperature (Lead-free package) for WLCSP
Body temperature (Lead-free package) for SOIC8
Relative Humidity non-condensing
Moisture Sensitivity Level for WLCSP
Moisture Sensitivity Level for SOIC8
Min Max Units
-0.3
5
-0.3
VDD+0.3
-100 100
±2
-55 125
V
V mA kV
°C
Comments
Norm: JEDEC 78
Norm: MIL 883 E method 3015
T
Body
260
260
°C
The reflow peak soldering temperature
(body temperature) specified is in accordance with IPC/ JEDEC J-STD-020
“Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid
State Surface Mount Devices”.
5 85 %
1
3
Represents a max. floor life time of unlimited
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Electrical Characteristics
Electrical Characteristics
Figure 7:
Operating Conditions
Symbol
VDD
I supp
I pd
T amb
Parameter
Supply voltage at pin VDD
Supply current
Power down current
Ambient temperature
Conditions
@ 25°C ambient temperature
Min Typ Max Units
2.5
3.6
-30
3
3.5
25
85
V mA
μ
A
°C
Figure 8:
Electrical Characteristics ADR Input
Symbol
V
IH
V
IL
I
LEAK
Parameter
High level input voltage
Low level input voltage
Input leakage current
DC Characteristics for Digital Inputs and
Outputs
CMOS Input: ADR
Operating conditions: T amb
= -30°C to 85°C, VDD = 2.5V to 3.6V
(3V operation) unless otherwise noted.
Min
0.7 * VDD
0
-1
Typ Max
VDD
0.3 * VDD
1
Units
V
V
μ
A
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AS5510 −
Electrical Characteristics
CMOS I²C: SDA, SCL
Operating conditions: Tamb = -30°C to 85°C, VDD = 2.5V to 3.6V
(3V operation) unless otherwise noted.
Figure 9:
Electrical Characteristics I²C
Symbol
V
IL
V
IH
V hys
V
OL
I
OL t of t
SP
I i
C
B
C
I/O
Parameter
LOW-level input voltage
HIGH-level input voltage
Hysteresis of Schmitt Trigger inputs
LOW-level output voltage
(open-drain or open-collector) at
3mA sink current
LOW-level output current
Output fall time from V
IHmax
to
V
ILmax
Pulse width of spikes that must be suppressed by the input filter
Input current at each I/O pin
Total capacitive load for each bus line
Conditions
VDD > 2.5V
VDD > 2.5V
VOL = 0.4V
Min
-0.5
0.7 * VDD
0.05 * VDD
Max
0.3 * VDD
VDD +0.5V
Units
V
V
V
20
-10
0.4V
+10
550
10
V mA ns ns
μ
A pF pF
Note(s) and/or Footnote(s):
1. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be considered for bus timing.
2. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
3. I/O pins of Fast-mode and Fast-mode plus devices must not obstruct the SDA and SCL lines if VDD is switched OFF.
4. Special purpose devices such as multiplexers and switches may exceed this capacitance due to the fact that they connect multiple paths together.
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AS5510 −
Electrical Characteristics
Electrical and Magnetic Specifications
Figure 10:
Electrical and Magnetic Specifications
Symbol
RES
Bin
Parameter
Resolution
Offset inp
t
PwrUp
Initial Power up time from cold start
t
PwrOn
Conditions
Default Setting
Magnetic Input Range
Configurable via I²C or factory trimming option
This time is needed for the first power-up of the device until the offset compensation is finished;
Includes readout of the PPROM fuses
Time after switching from power-down mode into active mode until the offset compensation is finished
250
Typ
10
±50
±25
±12.5
±18.75
Max Units
0.45
bit mT mT mT mT mT
3 %
1.5
ms
μ s
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AS5510 −
Electrical Characteristics
Symbol
f
S t delay
Noise inp f
S t delay
Noise inp
Parameter Conditions
ADC sampling frequency
System propagation delay
Input related noise
After offset compensation finished
Equivalent to 8 * rms
Slow Mode (I²C command option)
ADC sampling frequency
System propagation delay
Input related noise
Fast Mode (Default setting)
After offset compensation finished
Equivalent to 8 * rms
Typ Max
50
20
0.8
Units
KHz
μ s mTpp
12.5
50
0.5
KHz
μ s mTpp
Note(s) and/or Footnote(s):
1. Offset inp
= 0.35mT residual offset + 0.1mT earth magnetic field.
2. Linearity error = lin
– error
= 1 –
adc
– out maxB
–
2
×
adc
–
---------------
2
adc
–
– adc
–
) out zeroB
)
×
100
3. This time is needed for the first power-up of the device until the offset compensation is finished; Includes readout of the PPROM fuses; It depends on the sensitivity setting.
4. Time after switching from power-down mode into active mode until the offset compensation is finished.
5. Input related Noise (Noise
Inp
) is the repeatability of the measurement.
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Detailed Description
Detailed Description
Figure 11:
Linear Position Sensor AS5510 + Magnet
magnet
N S
AS5510
SOIC8
PCB
PCB
N magnet
S
AS5510
WLCSP
Linear Position Sensor AS5510 + Magnet:
The AS5510 can measure the absolute position of lateral movement in combination with a diametrical two pole magnet.
Typical Application
The typical application circuit of AS5510 is shown below:
Figure 12:
Typical Application Circuit
VDD
VSS
AS5510
#1
I²C ADDR = 56h
SCL
SDA
ADR
Test
VDD =
2.5 ~ 3.6V
100nF
VDD
VDD
VDD
VSS
AS5510
#2
I²C ADDR = 57h
SCL
SDA
ADR
Test
VDD
Microcontroller
SCL
SDA
I²C interface
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AS5510 −
Detailed Description
I²C Interface
The AS5510 includes an I²C slave according to the NXP specification UM10204.
• 7-bit slave address
101011x
, the last address bit x is set by the ADR pin (0 or 1)
• Random/Sequential Read
• Byte/Page Write
• Fast-mode plus with 20mA SDA drive strength
• Internal hold time of 120ns for SDA signal is included
(Start/Stop detection)
Not implemented:
• 10-bit Slave Address
• Clock Stretching
• General Call Address
• General Call – Software Reset
• Read of Device ID
The communication from the AS5510 includes:
• Reading the magnetic field strength in 10-bit data
• Reading the status bits
Note(s):
The I²C address of the chip is selected by hardware (pin
ADR). Depending on the state of this pin, the I²C address is either:
• Pin ADR = LOW
I²C address = 1010110b(56h)
• Pin ADR = HIGH
I²C address = 1010111b(57h)
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AS5510 −
Detailed Description
I²C Interface Data
Operating conditions: Tamb = -30 to 85°C, VDD=2.5 to 3.6V (3V operation) unless otherwise noted.
Figure 13:
I²C Timings
Symbol
f
SCLK t
BUF t
HD.STA
t
LOW t
HIGH t
SU.STA
t
HD.DAT
t
SU.DAT
t
R t
F t
SU.STO
Parameter
SCL clock frequency
Bus free time; time between STOP and START condition
Hold time; (repeated) START condition
LOW period of SCL clock
HIGH period of SCL clock
Setup time for a repeated START condition
Data hold time
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Setup time for STOP condition
Min
50
0.26
0.5
0.26
0.5
0.26
0.26
Typ Max
1
0.45
120
120
Units
ns ns
μ s
μ s
μ s
μ s
μ s
MHz
μ s
μ s ns
Note(s) and/or Footnote(s):
1. After this time the first clock is generated.
2. A device must internally provide a hold time of at least 120ns (Fast-mode Plus) for the SDA signal (referred to the V
IHmin
of the SCL) to bridge the undefined region of the falling edge of SCL.
3. A fast-mode device can be used in standard-mode system, but the requirement t
SU.DAT
= 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
Rmax
+ T
SU.DAT
= 1000 + 250 = 1250ns before the SCL line is released.
4. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be considered for bus timing.
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AS5510 −
Detailed Description
Figure 14:
I²C Timing Diagram
SDA t buf t
LOW t
R
SCL
Stop Start t
HD.STA
t
HD.DAT
t
HIGH t
F
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HD.STA
t
SU.DAT
t
SU.STA
Repeated
Start t
SU.STO
I²C Modes
The AS5510 supports the I²C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions must control the bus.
The AS5510 operates as a slave on the I²C bus. Within the bus specifications a standard mode (100 kHz maximum clock rate) a fast mode (400 kHz maximum clock rate) and fast mode plus
(1MHz maximum clock rate) are defined. The AS5510 works in all three modes. Connections to the bus are made through the open-drain I/O lines SDA and the input SCL. Clock stretching is not included.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as start or stop signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy
Both data and clock lines remain HIGH.
Start Data Transfer
A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.
Stop Data Transfer
A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
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Detailed Description
Data Valid
The state of the data line represents valid data when, after a
START condition, the data line is stable for the duration of the
HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a
START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge bit after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of READ access to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
Figure 15:
Data Read (Write Pointer, Then Read) - Slave Receive and Transmit
SDA
SCL
Start
Condition
MSB
Slave Address
LSB R/W ACK
Repeated if more Bytes are transferred
ACK
1 2 ...
6 7 8 9 1 ...
7 8 9
Stop Condition or
Repeated Start Condition
Depending upon the state of the R/W bit, two types of data transfer are possible:
Data transfer from a Master Transmitter to a Slave
Receiver.
The first byte transmitted by the master is the slave address, followed by R/W = 0. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. If the slave does not understand the command or data it sends a “not acknowledge”. Data is transferred with the most significant bit
(MSB) first.
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AS5510 −
Detailed Description
Data transfer from a Slave Transmitter to a Master
Receiver.
The master transmits the first byte (the slave address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte.
At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first.
The AS5510 can operate in the following two modes:
Slave Receiver Mode (Write Mode)
Serial data and clock are received through SDA and SCL. Each byte is followed by an acknowledge bit (or by a not acknowledge depending on the address-pointer pointing to a valid position). START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see
). The slave address byte is the first byte received after the START condition. The slave address byte contains the 7-bit AS5510 address. The 7-bit slave address is followed by the direction bit (R/W), which, for a write, is 0.
After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA. After the AS5510 acknowledges the slave address + write bit, the master transmits a register address to the AS5510. This sets the address pointer on the AS5510. If the address is a valid readable address the AS5510 answers by sending an acknowledge. If the address-pointer points to an invalid position a “not acknowledge” is sent. The master may then transmit zero or more bytes of data. In case of the address pointer pointing to an invalid address the received data are not stored. The address pointer will increment after each byte transferred independent from the address being valid. If the address-pointer reaches a valid position again, the AS5510 answers with an acknowledge and stores the data. The master generates a STOP condition to terminate the data write.
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AS5510 −
Detailed Description
Figure 16:
Data Write - Slave Receiver Mode
S
<Slave address>
1010110
<Word address (n)> <Data(n)>
0 A XXXXXXXX A XXXXXXXX A
<Data(n+1)>
XXXXXXXX A
S – Start
A – Acknowledge (ACK)
P – Stop
Data transferred: X+1 Bytes + Acknowledge
<Data(n+X)>
XXXXXXXX NA P
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AS5510 −
Detailed Description
Slave Transmitter Mode (Read Mode)
The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on
SDA by the AS5510 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (
Figure 17 and Figure 18 ). The slave address
byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit AS5510 address. The 7-bit slave address is followed by the direction bit
(R/W), which, for a read, is 1. After receiving and decoding the slave address byte the device outputs an acknowledge on the
SDA line. The AS5510 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The AS5510 must receive a “not acknowledge” to end a read.
Figure 17:
Data Read (from Current Pointer Location) - Slave Transmitter Mode
S
<Slave address>
1010110 1 A
S – Start
A – Acknowledge (ACK)
NA – Not Acknowledge (NACK)
P – Stop
<Data(n)>
XXXXXXXX A
<Data(n+1)>
XXXXXXXX A
Data transferred: X+1 Bytes + Acknowledge
<Data(n+2)>
XXXXXXXX
Note: Last data byte is followed by NACK
A
<Data(n+X)>
XXXXXXXX NA P
Figure 18:
Data Read (Write Pointer, Then Read) - Slave Receive and Transmit
S
<Slave address>
1010110
<Word Address (n)>
0 A XXXXXXXX A Sr
<Slave Address>
1010110 1
S – Start
SA – Repeated Start
A – Acknowledge (ACK)
NA – Not Acknowledge (NACK)
P – Stop
A
Data transferred: X+1 Bytes + Acknowledge
<Data(n)>
XXXXXXXX
Note: Last data byte is followed by NACK
A
<Data(n+1)>
XXXXXXXX A
<Data(n+X)>
XXXXXXXX NA P
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AS5510 −
Detailed Description
Automatic Increment of Address Pointer
The AS5510 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent from the address being valid or not.
Invalid Addresses
If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible. The address pointer is increased after each byte.
Reading
When reading from a wrong address, the AS5510 slave returns all zero. The address pointer is increased after each byte.
Sequential read over the whole address range is possible including address overflow.
Write
A write to a wrong address is not acknowledged by the AS5510 slave, although the address pointer is increased. When the address pointer points to a valid address again, a successful write accessed is acknowledged. Page write over the whole address range is possible including address overflow.
SDA, SCL Input Filters
Input filters for SDA and SCL inputs are included to suppress noise spikes of less than 50ns. Furthermore the SDA line is delayed by 120ns to provide an internal hold time for Start/Stop detection to bridge the undefined region of the falling edge of
SCL. The delay needs to be smaller than tHD.STA 260ns. For
Standard-mode and Fast-mode an internal hold time of 300ns is required, which is not covered by the AS5510 slave.
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AS5510 −
Register Description
Register Description
Figure 19:
Register Map
Register
Address
00h
7
D7
01h
02h
03h
04h
0Bh
6
D6
Offs7 Offs6
5
D5
Offs5
4
D4
Offs4
Bit
3
D3
OCF
Offs3
2 1
D2
Parity
(even)
Fast(0)
Slow mode (1)
Offs2
D1
D9
Polarity(0)
Offs1
Offs9
Sens 1
0
D0
D8
PD(0)
Offs0
Offs8
Sens 0
Access
Type
R
R
R/W
R/W
R/W
R/W
Note(s) and/or Footnote(s):
1. Blank or not listed fields may contain factory settings. To change a configuration, read out the register, modify only the desired bits and write the new configuration.
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AS5510 −
Register Description
Figure 20:
Register Description
Register Address
00h, 01h
01h
01h
02h
02h
02h
03h, 04h
0Bh
Name Description
D9 to D0
Parity
OCF
PD
10 Bit ADC output value that corresponds to the magnetic field input
Even parity bit calculated from D9 to D0
Offset compensation loop status
0 = Offset compensation loop in use
1 = Offset compensation loop has finished
Power down mode
0 = Normal operation (Default)
1 = Power Down mode.
Polarity
Fast / Slow mode
Output signal polarity
0 = Normal polarity (Default)
1 = Reversed polarity (reversed magnet)
0 = Fast mode (Default)
1 = Slow mode. Enables averaging of the output values (reduced noise, better repeatability slower sampling frequency. See
Electrical and Magnetic Specifications
Offs9 to Offs0
Sensitivity
Contains the offset compensation value. For read access only.
Don't modify the register values.
Sensitivity setting
0h = Input range ± 50mT
Sensitivity = 97.66μT/LSB (Default)
1h = Input range ± 25mT
Sensitivity = 48.83μT/LSB
2h = Input range ± 12.5mT
Sensitivity = 24.41μT/LSB
3h = Input range ± 18.75mT
Sensitivity = 36.62μT/LSB
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AS5510 −
Package Drawings & Markings
Package Drawings & Markings
WLCSP Package
The WLCSP package drawings and markings are shown below:
Figure 21:
Package Dimensions (WLCSP)
Top View
Device number
Side View
Bottom View
Green
RoHS
Note(s) and/or Footnote(s):
1. ccc Coplanarity
2. All dimensions in
μ m
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Pack age Drawings & Mark ings
Figure 22:
Recommended Footprint
X x0 x1 x1 x0
D y0 y1
Y y0
Package Dimensions
Symbol
y0 y1
D
X x0 x1
Y
Typ
1460
330
400
1100
350
400
270
Unit
μ m
μ m
μ m
μ m
μ m
μ m
μ m
Figure 23:
Package Marking (WLCSP)
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Figure 24:
Package Code XXXX
XXXX
Tracecode
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AS5510 −
Package Drawings & Markings
SOIC8 Package
The SOIC8 package drawings and markings are shown below:
Figure 25:
Package Dimensions SOIC8
Symbol Min Nom Max
R
R1 h
Θ
Θ
1
Θ
2 aaa
L1
L2 e
L
E
E1 c
D
A
A1
A2 b bbb ccc ddd eee fff ggg
N
0.07
0.07
0.25
0º
-
0.40
-
-
0.17
-
-
-
-
0.10
1.25
0.31
-
-
-
-
-
-
-
5º
0º
1.27 BSC
-
1.04 REF
0.25 BSC
-
-
-
-
-
-
-
-
-
4.90 BSC
6.00 BSC
3.90 BSC
0.10
0.25
0.10
0.15
-
-
0.10
0.20
0.15
8
-
-
0.50
8º
-
1.27
-
-
0.25
-
-
-
1.75
0.25
-
0.51
-
-
-
-
-
15º
-
-
-
Green
RoHS ams Datasheet
[v1-07] 2015-Feb-27
Page 23
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Figure 26:
Package Marking (SOIC8)
AS5510 −
Pack age Drawings & Mark ings
Figure 27:
Package Code XXX@
XXX
Tracecode
@
Sublot Identifier
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ams Datasheet
[v1-07] 2015-Feb-27
AS5510 −
Ordering & Contact Information
Ordering & Contact Information
The devices are available as the standard products shown in the figure below.
Figure 28:
Ordering Information
Ordering Code
AS5510-DWLT
AS5510-DWLM
AS5510-DSOT
AS5510-DSOM
Package
6pin WL-CSP 1.4x1.1mm
6pin WL-CSP 1.4x1.1mm
8pin SOIC
8pin SOIC
Marking Delivery Form Delivery Quantity
AS5510
AS5510
AS5510
AS5510
Tape & Reel
Mini Reel
Tape & Reel
Mini Reel
12.000pcs
1000pcs
2.500pcs
500pcs
D
→
Temperature Range: -30°C to 85°C
WL
→
Package: WL-CSP Wafer Level - Chip Scale Package
SO
→
Package: SOIC 8
T
→
Delivery Form: Tape & Reel
M
→
Delivery Form: Mini Reel
Buy our products or get free samples online at: www.ams.com/ICdirect
Technical Support is available at: www.ams.com/Technical-Support
Provide feedback about this document at: www.ams.com/Document-Feedback
For further information and requests, e-mail us at: [email protected]
For sales offices, distributors and representatives, please visit: www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
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Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
ams Datasheet
[v1-07] 2015-Feb-27
Page 25
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AS5510 −
RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS:
The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br):
ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information:
The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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ams Datasheet
[v1-07] 2015-Feb-27
AS5510 −
Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141
Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing inits General Terms of
Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
ams Datasheet
[v1-07] 2015-Feb-27
Page 27
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AS5510 −
Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Product Status
Pre-Development
Pre-Production
Production
Discontinued
Definition
Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice
Information in this datasheet is based on products in the design, validation or qualification phase of development.
The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice
Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade
Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and should not be used for new designs
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ams Datasheet
[v1-07] 2015-Feb-27
AS5510 −
Revision Information
Revision Information
Changes from 1-06 (2014-Oct-30) to current revision 1-07 (2015-Feb-27)
Updated Figure 19
Updated Figure 20
Note(s) and/or Footnote(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Page
ams Datasheet
[v1-07] 2015-Feb-27
Page 29
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Content Guide
AS5510 −
Content Guide
1 General Description
1 Key Benefits & Features
1 Applications
2 Block Diagram
3 Pin Assignment
5 Absolute Maximum Ratings
6 Electrical Characteristics
6 DC Characteristics for Digital Inputs and Outputs
6 CMOS Input: ADR
7 CMOS I²C: SDA, SCL
8 Electrical and Magnetic Specifications
10 Detailed Description
10 Typical Application
11 I²C Interface
12 I²C Interface Data
13 I²C Modes
13 Bus Not Busy
13 Start Data Transfer
13 Stop Data Transfer
13 Data Valid
14 Acknowledge
14 Data transfer from a Master Transmitter to a
Slave Receiver.
14 Data transfer from a Slave Transmitter to a
Master Receiver.
15 Slave Receiver Mode (Write Mode)
16 Slave Transmitter Mode (Read Mode)
17 Automatic increment of Address Pointer
17 Invalid Addresses
17 Reading
17 Write
17 SDA, SCL Input Filters
18 Register Description
20 Package Drawings & Markings
20 WLCSP Package
22 SOIC8 Package
24 Ordering & Contact Information
25 RoHS Compliant & ams Green Statement
26 Copyrights & Disclaimer
27 Document Status
28 Revision Information
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ams Datasheet
[v1-07] 2015-Feb-27
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