The AS621x IC family is a high accuracy temperature sensor system that communicates via a 2-wire digital bus with other devices. It consists of a Si bandgap temperature sensor, an ADC and a digital signal processor.

The family consists of 3 different variants (AS6212, AS6214 and AS6218). The difference between these variants is the temperature accuracy:

Figure 1:

AS621x Variants

Variant

AS6212

AS6214

AS6218

Temperature Accuracy Remark

±0.2°C

±0.4°C

±0.8°C between -10°C to 65°C between 0°C to 65°C between 0°C to 65°C

The high temperature accuracy (shown in Figure 1) and an ultra-low power consumption (low

operation and quiescent current) makes the AS621x ideally suited for mobile/battery powered applications.

The AS621x is an easy to integrate and use solution, featuring a factory-calibrated sensor, integrated linearization and the possibility to use 8 different I²C addresses, enabling to use eight AS621x devices on one bus.

Additionally the AS621x temperature sensor system features an alert functionality, which triggers e.g. an interrupt to protect devices from excessive temperatures.

1.1 Key Benefits & Features

The benefits and features of AS621x are listed below:

Figure 2:

Added Value of Using AS621x

Benefits

High Measurement Accuracy

Features

± 0.2 °C ( -10°C to 65 °C, for AS6212)

± 0.3 °C (from -40°C to -10°C and from 65°C to

85°C, for AS6212)

± 0.5 °C (for remaining temperature span, for

AS6212)

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Benefits

Low Power Consumption

Supply Voltage Range

Small PCB Footprint

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AS621x

General Description

Features

6 µA @ Operation (typical, @ 4 Hz)

0.1 µA @ Standby (typical)

1.71

– 3.6 V (0 °C to 125 °C)

1.5 mm x 1 mm (WLCSP)

1.2 Applications

●

Electronic Equipment

●

Tablets

Convertibles

Laptop

●

Personal Computers

●

Wearables

●

HVAC

1.3 Block Diagram

The functional blocks of this device are shown below:

Figure 3 :

Functional Blocks of AS621x

In Figure 3 the functional blocks are depicted. The sensing element for sensing the temperature is a Si

bipolar transistor. The analog signal of the sensing element is converted into a digital signal by the A/D converter and the signal is further processed by a digital signal processor and written into the registers. The registers can be accessed via the serial bus interface (I²C bus).

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2 Ordering Information

Ordering Code

AS6212-AWLT-S

AS6212-AWLT-L

AS6214-AWLT-S

AS6214-AWLT-L

AS6218-AWLT-S

AS6218-AWLT-L

Package

WLCSP

Marking

AS6212

AS6214

AS6218

AS621x

Ordering Information

Delivery Form Delivery Quantity

Tape & Reel

500 pcs/reel

5000 pcs/reel

500 pcs/reel

5000 pcs/reel

500 pcs/reel

5000 pcs/reel

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3 Pin Assignment

3.1 Pin Diagram

Figure 4:

Pin Assignment WLCSP

AS621x

Pin Assignment

In Figure 4 the pin assignment of the WLCSP package is shown. The viewing side is from the top. The

A1 pin is also marked with a point on the top side

3.2 Pin Description

Figure 5:

Pin Description of AS621x (WLCSP)

Pin Number Pin Name

VSS

ALERT/ADD1

SCL

VDD

ADD0

Pin Type

(1)

DIO_SOD

DI_S

Description

Ground Pin

Alert output and address select1

Serial Interface Clock

Positive Supply Voltage

Address select 0

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AS621x

Pin Assignment

Pin Number Pin Name Pin Type

(1)

Description

(1)

SDA DIO_SOD Serial Interface Data

Explanation of abbreviations:

S Supply

DI_S Digital Schmitt Trigger Input

DIO_SOD Digital Schmitt Trigger Input / Open Drain Output

In Figure 5 the pins of AS621x are described. External pull up resistors (to VDD) are necessary for the

pins

“SDA” and “SCL”.

The pin “ADD0” must not be left unconnected (refer to section 6.3.3 for further details).

The pin “ALERT/ADD1” is used to set the I²C address and has the additional functionality of triggering an interrupt. In case this ALERT functionality is used, a pull up resistor (to VDD) is necessary. If this functionality is not used it must be connected to VSS or SCL, depending on the selected I²C address

(refer to section 6.3.3 for further details). It must not be left unconnected.

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AS621x

Absolute Maximum Ratings

4 Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 6

Absolute Maximum Ratings of AS621x

Symbol Parameter Min Max Unit Comments

Electrical Parameters

/ V

VDIO

Supply Voltage to VSS

IO Pin voltage

I_SCR

Input Current (latch up immunity)

Electrostatic Discharge

ESD

HBM

Electrostatic Discharge HBM

Temperature Ranges and Storage Conditions

Operating Ambient Temperature T

STRG

BODY

Operating Junction Temperature

Storage Temperature Range

HNC

Package Body Temperature

Relative Humidity (noncondensing)

-0.3

-100

-40

-55

±2000

100

125

260

V mA

°C

Reference to VSS

According to JESD78D

MIL_STD_833J-3015.9

IPC/JEDEC J-STD-020

(1)

MSL

(1)

Moisture Sensitivity Level 1 Unlimited floor life time

The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020

“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.”

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5 Operating Conditions

AS621x

Operating Conditions

The AS621x is a complete sensor system that has an integrated sensing element, the analog frontend, the A/D converter and the digital signal processing part.

The digital signal processing part consists of the signal processor, the registers and the serial bus interface.

5.1 Analog System Parameters

Figure 7:

Analog System Parameters of AS621x

Parameter

Supply Voltage

Current Consumption

(4 conversions /s)

Symbol

VDD

Temperature Range T

Standby Current

Consumption

IDD

Min

1.71

2.0

-40

Typ

3.0

0.1

0.3

Resolution

Conversion Time

Conversion Rate

0.25

Supply Voltage Rise

Time

Supply Voltage Slew

Rate

TRise_VDD

SR_VDD 50

In Figure 7 an overview of the analog system parameters is given.

Max

3.6

125

0.4

9.0

0.35

1.35

5.5

10.7

Unit

°C

µA

Bits ms

Conv/s

CR[1:0]=00

CR[1:0]=01

CR[1:0]=10

CR[1:0]=11 ms mV/ms

Note

T= 0°C to 125°C

T= -40°C to 125°C

T= -40°C to 65°C

T= 65°C to 125°C

T= -40°C to 65°C

Serial bus inactive

T= 65°C to 125°C

Serial bus inactive from 0.1V to 1.6V from 0.1V to 1.6V

The current consumption for less than 4 conversions per second is lower than the values given in

Figure 7.

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Figure 8:

Temperature Accuracy Values of AS621x

AS621x

Operating Conditions

Variant

AS6212

AS6214

AS6218

Symbol Min

T_ERR

-0.3

-0.2

-0.3

-0.5

-1.0

-0.4

-1.0

-0.8

-1.0

Typ Max

0.3

0.2

0.3

0.5

1.0

0.4

1.0

0.8

1.0

Unit

°C

Note

T= -40°C to -10°C

T= -10°C to 65°C

T= 65°C to 85°C

T= 85°C to 125°C

T= -40°C to 0°C

T= 0°C to 65°C

T= 65°C to 125°C

T= -40°C to 0°C

T= 0°C to 65°C

T= 65°C to 125°C

In Figure 8 the different accuracy values of AS621x are shown. These values are representative for a



distribution. All accuracy values are valid for the complete supply voltage range given in Figure 7.

5.2 Digital System Parameters

Figure 9:

Digital System Parameters of AS621x

Parameter Symbol Pins Min Max Unit Note

High level input voltage

Low level input voltage

Hysteresis voltage

V_IH

V_IL

V_HYST

SCL, ADD0 0.7 * VDD

SCL, ADD0

0.3 * VDD V

SCL,ADD0,

SDA,Alert

200 1200 mV

Input leakage current I_LEAK

Low level output voltage V_OL

High level input voltage

Low level input voltage

V_IH

V_IL

Low level output voltage V_OL

Tristate leakage current I_OZ

SCL;ADD0 -1

Alert

SDA

0.7 * VDD

-10

VSS+0.4

µA

0.3*VDD V

µA

V_IL=0.0V

I_OL=3mA to VSS

In Figure 9 an overview of the digital system parameters is given.

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6 Register Description

6.1 Register Overview

Figure 10 :

Register Map with Serial Interface

AS621x

In Figure 10 the registers that the device contains are shown.

With the use of the index register, it is possible to address the specific register. The index register is

an 8-bit register, where only bits 0 and 1 are used as shown in Figure 11 and all other bits are set to 0

and read only

6.1.1 Index Register

Figure 11:

Index Register

Bit

Bit Name

Address Bit

Reserved

Default

Access

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AS621x

Figure 12:

Register Map

Address Symbol Register Description

0x0

0x1

0x2

0x3

TVAL

CONFIG

TLOW

THIGH

Temperature Register

Configuration Register

LOW

HIGH

Contains the temperature value

Configuration settings of the temperature sensor

Low temperature threshold value

High temperature threshold value

The first 2 bit addresses in the index register define the access to the registers shown in Figure 12.

This means that in order to access the different registers, the index register must be set accordingly.

With the exception of the TVAL register (which contains the temperature value data), all registers are read/write accessible.

6.2 Detailed Register Description

6.2.1 Configuration Register (Address 0x1)

Figure 13:

CONFIGURATION Register

Addr: 0x1

Bit

Bit Name

Reserved

CR[0]

CR[1]

POL

CF[0]

CF[1]

Reserved

Default

Access Bit Description

Reserved

Alert Bit (AL)

Conversion RATE (CR)

Sleep Mode (SM)

Interrupt Mode (IM)

Polarity (POL)

Consecutive Faults (CF)

Reserved

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AS621x

Addr: 0x1

Bit

Bit Name

Reserved

Default

Access

Bit Description

Reserved

Single Shot

The configuration register is a 16-bit register which defines the operation modes of the device. Any read/write operation processes the MSB byte first.

In Figure 13 the configuration register is shown. The bits 0-4 and 13-14 are not to be used and are set

to read only. The explanation of the other bits are detailed in the following sections.

6.2.2 Alert Bit

The alert bit can be used to easily compare the current temperature reading to the thresholds that can be set in the TLWO and THIGH registers.

If the polarity bit is set to 0, the AL bit is read as 1 until the converted temperature value exceeds the defined value in the high temperature threshold register THIGH for the number of defined consecutive faults (bits CF). Such an event causes the AL bit to toggle to 0 and the value is kept until the converted temperature value falls below the defined value in the low temperature threshold register

TLOW for the number of defined consecutive faults. If this condition is met, the AL bit is reset to 1.

The polarity bit (POL) defines the active state of the alert bit as depicted in the following figure.

The alert bit has the same setting as the alert output as long as the device is configured for the comparator mode.

Figure 14:

State Diagram of the Alert Bit

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6.2.3

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AS621x

Conversion Rate Bits

The conversion rate bits define the number of executed temperature conversions per time unit.

Additional readouts of the temperature register between conversions are possible but not recommended because the value is changed only after a conversion is finished.

Values of 125ms, 250ms, 1s and 4s for a conversion can be configured while the default rate is set to

4 conversions per second. The following table summarizes the different configuration settings:

Figure 15:

Conversion Rate Configuration

Conversion Rate Bits

Bit 6

Conversion Rate

Figure 16:

Conversion Sequence

6.2.4 Sleep Mode

The sleep mode is activated by setting the bit SM in the configuration register to 1. This shuts the device down immediately and reduces the power consumption to a minimum value.

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6.2.5

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AS621x

The serial interface is the only active circuitry in the sleep mode in order to provide access to the digital registers.

Entering the sleep mode will take some time (120 ms maximum) and the first conversion after the

sleep mode has been entered takes longer than the values specified in Figure 7. It is therefore

recommended when entering sleep mode to trigger a single shot conversion at the same time. After

150 ms (max), the device has then entered the sleep mode and subsequent conversion times are as

specified in Figure 7.

After resetting the SM bit to 0, the device enters the continuous conversion mode.

Figure 17:

Sleep Mode Configuration

Sleep Mode Bit

Operation Mode

Continuous Conversion Mode

Sleep Mode

Interrupt Mode

The interrupt mode bit defines whether the device operates in the temperature comparator mode or the interrupt mode. This defines the operation of the ALERT output as described in the polarity section bit.

Figure 18:

Interrupt Mode Configuration

Interrupt Mode Bit Configuration Mode

Comparator Mode

Interrupt Mode

The comparator mode is characterized that if the temperature value exceeds the THIGH value, the alert output is changed (e.g. from high to low if the polarity bit is set to 0 and vice versa). The alert output stays in that condition until the measured temperature drops below the defined TLOW value.

The interrupt mode is characterized that it changes the alert output as soon as the measured temperature crosses the THIGH or TLOW value threshold.

The alert bit has the same setting as the alert output if the device is set to comparator mode.

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Figure 19:

Alert Output Functionality

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AS621x

6.2.6 Polarity Bit

The polarity bit configures the polarity of the ALERT output. If the polarity bit is cleared, the ALERT output is low active while it becomes high active if the polarity bit is set to ‘1’.

Figure 20:

Polarity Bit Configuration

Polarity Bit

ALERT Output

Active low

Active high

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6.2.7

6.2.8

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AS621x

Consecutive Faults

A fault condition persists if the measured temperature either exceeds the configured value in register

THIGH or falls below the defined value in register TLOW. As a result, the ALERT pin indicates the fault condition if a defined number of consecutive temperature readings meets this fault condition. The number of consecutive faults are defined with two bits (12 and 11) and prevent a false alert if environmental temperature noise is present. The register configuration is shown in the following table.

Figure 21:

Consecutive Faults Bit Settings

Consecutive Fault Bits

Bit 13

Bit 12

Consecutive Faults (N)

Single Shot Conversion

The device features a single shot measurement mode if the device is in sleep mode (SM=1). By setting the “Single Shot-bit” to 1, a single temperature conversion is started and the SS-bit can be read as 1 during the active conversion operation. Once the conversion is completed, the device enters the sleep mode again and the SS-bit is set to 0. The single shot conversion allows very low power consumption since a temperature conversion is executed on demand only. This allows a user defined timing of the temperature conversions to be executed and is used if the consecutive operation mode is not required.

The first conversion triggered in this mode has a longer conversion time. In the section 6.2.4 Sleep

Mode it is detailed together with the recommendation to trigger the first conversion simultaneously with

entering the sleep mode.

As the device exhibits a very short conversion time, the effective conversion rate can be increased by setting the single shot bit repetitively after a conversion has finished. However, it has to be ensured that the additional power is limited, otherwise self-heating effects have to be considered.

Figure 22:

Single Shot Conversion Bit Settings

Single Shot Bit Conversion

No conversion ongoing/ conversion finished

Start single shot conversion / conversion ongoing

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6.2.9

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AS621x

High and Low Limit Registers

If the comparator mode is configured (IM=0), the ALERT output becomes active if the temperature equals or exceeds the defined value in register THIGH for the configured number of consecutive faults (N). This configuration is defined by the field CF in the configuration register. The ALERT output remains assigned until the converted temperature value equals or falls below the defined value in register TLOW for the same number of consecutive fault cycles.

If the interrupt mode is configured (IM=1), the ALERT output becomes active if the temperature equals or exceeds the defined value in register THIGH for the configured number of consecutive fault cycles.

It remains active until a read operation is executed on any register. The ALERT output is also cleared if the device is set into sleep mode by setting bit SM in the configuration register.

Once the ALERT output is cleared, it is activated again only if the temperature value falls below the configured value in register TLOW. It remains active unless a read operation has taken place.

This sequence is repeated unless the device is set into the comparator mode. This reset command clears the interrupt mode bit and consequently puts the device into the comparator mode.

The sequential behavior is summarized in the following Figure 23.

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Figure 23:

Alert Operation Modes

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AS621x

Comparator Mode

ALERT output cleared

≤ TLOW for

N consecutive cycles

≥ THIGH for

N consecutive cycles

ALERT output active

General Reset

Command

IM=0 IM=1

Read operation or

Set to sleep mode

ALERT output active

Interrupt Mode

ALERT output cleared

≥ THIGH for

N consecutive cycles

ALERT output active

≤ TLOW for

N consecutive cycles

ALERT output cleared

Read operation or

Set to sleep mode

The following table defines the content of the registers TLOW and THIGH. For data transmission, the

MSB byte is transmitted first, followed by the LSB byte. The data format for representing the threshold temperatures is equal to the temperature register (TVAL). After a power-up, the registers are initialized with the following default values:

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Figure 24:

Default Values for THIGH and TLOW

AS621x

Register

TLOW

THIGH

Temperature

75 °C

80 °C

Binary Value

0010 0101 1000 0000

0010 1000 0000 0000

The following table defines the register bits of the THIGH and TLOW register.

Figure 25:

Register Bit Settings for THIGH/TLOW

Addr: 0x2 / 0x3

Bit

TLOW Register

L10

L11

L12

L13

L14

L15

THIGH Register

H10

H11

H12

H13

H14

H15

Access

Permanently set to 0

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6.2.10 Temperature Register (Address 0x0)

Figure 26:

Temperature Value Register

AS621x

Addr: 0x0

Bit

Bit Name

T10

T11

T12

T13

T14

T15

The temperature register contains the digitally converted temperature value and can be read by setting the index pointer to the TVAL register (0x0).

Two consecutive bytes must be read to obtain the complete temperature value. The MSB byte (Bits 15 to 8) is transmitted upon the first read access and the LSB byte (Bits 7 to 0) is transmitted after the second read access.

A temperature value is represented as a two complement value in order to cover also negative values.

After power-up, the temperature value is read as 0°C until the first conversion has been completed.

One LSB corresponds to 0.0078125°C (=1/128 °C).

The binary values can be calculated according to the following formulas:

Positive values: |Value| / LSB

Negative values: Complement (|Value| / LSB ) + 1

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AS621x

Example 75°C:

75°𝐶/0.0078125°𝐶 = 9600 = 𝐵𝑖𝑛𝑎𝑟𝑦 0010 0101 1000 0000 = 𝐻𝑒𝑥 2580

Example -40°C:

|−40°𝐶|/0.0078125 °𝐶 + 1 = 5120 + 1 = 𝐵𝑖𝑛𝑎𝑟𝑦 0001 0100 0000 0000 + 1 = 1110 1100 0000 0000 =

𝐻𝑒𝑥 EC00

Figure 27:

Temperature Conversion Examples

Temperature (°C)

100.0

75.0

50.0

25.0

0.125

0.0078125

0.0

-0.0078125

-0.125

-25.0

-40.0

Digital Output (Binary)

0011 0010 0000 0000

0010 0101 1000 0000

0001 1001 0000 0000

0000 1100 1000 0000

0000 0000 0001 0000

0000 0000 0000 0001

0000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 0000

1111 0011 1000 0000

1110 1100 0000 0000

Digital Output (Hex)

3200

2580

1900

0C80

0010

0001

0000

FFFF

FFF0

F380

EC00

6.3 Serial Interface

The device employs a standard I²C-serial bus.

6.3.1 Bus Description

A data transfer must be invoked by a master device (e.g. microcontroller) which defines the access to the slave device. The master device defines and generates the serial clock (SCL) and the start/stop conditions.

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AS621x

In order to address a specific device, a START condition has to be generated by the master device by pulling the data line (SDA) from a logic high level to a logic low level while the serial clock signal (SCL) is kept at high level.

After the start condition, the slave address byte is transmitted which is completed with a ninth bit which indicates a read (bit=’1’) or a write operation (bit=’0’) respectively. All slaves read the data on the rising edge of the clock. An acknowledge signal is generated by the addressed slave during the ninth clock pulse. This acknowledge signal is produced by pulling the pin SDA to a low level by the selected slave.

Subsequently, the byte data transfer is started and finished by an acknowledge bit. A change in the data signal (SDA) while the clock signal (SCL) is high causes a START or STOP condition. Hence, it must be ensured such a condition is prevented during a data transfer phase.

After completing the data transfer, the master generates a STOP condition by pulling the data line

(SDA) from low level to high level while the clock signal (SCL) is kept at high level.

6.3.2 Data Interface

A bus connection is created by connecting the open drain input/output lines SDA and SCL to the two wire bus. The inputs of SDA and SCL feature Schmitt-trigger inputs as well as low pass filters in order to suppress noise on the bus line. This improves the robustness against spikes on the two wire interface.

Both fast transmission mode (1kHz to 400kHz) and high-speed transmission mode (1kHz to 3.4MHz) are employed to cover different bus speed settings.

Any data transfer transmits the MSB first and the LSB as last bit.

6.3.3 Bus Address

A slave address consists of seven bits, followed by a data direction bit (read/write operation). The slave address can be selected from 8 different address settings by connecting the pin ADD0 and

ADD1 to an appropriate signal as summarized in Figure 28.

The ADD0 and the ADD1 pin must not be left unconnected.

The address selection with ADD1 is depending on the usage of the ALERT function (described in

chapter 6.3.8). In case the ALERT functionality is used, it must be connected via a pull up resistor to

VDD. In case the ALERT functionality is not used, the pin must be connected to either SCL or VSS

(refer to Figure 28 for details).

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6.3.4

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AS621x

Figure 28:

I²C Address Select Configuration

ALERT / ADD1

Connection

SCL

VSS

Pull up to VDD

VSS

VDD

SDA

SCL

VSS

VDD

SDA

SCL

VSS

VDD

SDA

SCL

ADD0 Connection

Alert

Functionality

Enabled

Yes

Device Address

(bin)

100 0100

100 0101

100 0110

100 0111

100 1000

100 1001

100 1010

100 1011

100 1000

100 1001

100 1010

100 1011

Device Address

(hex)

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x48

0x49

0x4A

0x4B

Read/Write Operation

In order to access an internal data register, the index register must be written in advance. This register contains the actual register address and selects the appropriate register for an access. A typical transfer consists of the transmission of the slave address with a write operation indication, followed by the transmission of the register address and is finalized with the actual register content data transfer.

This implies that every write operation to the temperature sensor device requires a value for the index register prior to the transmission of the actual register data.

The index register defines the register address for both the write and read operation. Consequently, if a read operation is executed, the register address is taken from the index register which was defined from the last write operation.

If a different register needs to be read, the index register has to be written in advance to define the new register address. This is accomplished by transmitting the slave address with a low R/W bit, followed by the new content of the index register. Subsequently, the master provokes a START condition on the bus and transmits the slave address with a high R/W bit in order to initiate a read operation.

Since the index register always keeps its last value, reads can be executed repetitively on the same register.

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Similarly to the byte transfer where the MSB is transmitted first, the transfer of a 16-bit word is executed by a two byte transfer whereas the MSB byte is always transmitted first.

6.3.5 Slave Operation

The device employs a slave functionality only (slave transmitter and slave receiver) and cannot be operated as a bus master. Consequently, the device never actively drives the SCL line.

6.3.6 Slave Receiver Mode

Any transmission is invoked by the master device by transmitting the slave address with a low R/W bit.

Subsequently, the slave device acknowledges the reception of the valid address by pulling the ninth bit to a low level. Following to acknowledge, the master transmits the content of the index register.

This transfer is again acknowledged by the slave device. The next data byte(s) are written to the actual data register which is selected by the index register while each transfer is acknowledged upon a completed transfer by the slave device. A data transfer can be finished if the master transmits a

START or a STOP condition on the bus.

6.3.7 Slave Transmitter

The master transmits the slave address with a high R/W bit. In turn, the slave acknowledges a valid slave address. Subsequently, the slave transmits the MSB byte of the actual selected data register by the index register. After the MSB byte transmission, acknowledge is sent by the master. Afterwards, the LSB byte is transmitted by the slave which is also acknowledged by the master after the completed transmission. The data transfer can be terminated by the master by transmitting a Not-

Acknowledge after the transmitted slave data or by invoking a START or a STOP condition on the bus.

6.3.8 Alert Function

If the device is configured for an interrupt mode operation (IM=1), the ALERT output can be used as an alert signal.

If the polarity bit is set to ‘0’ (POL=’0’), the alert condition bit is set to ‘0’ in case the temperature has exceeded the configured value in register THIGH. Accordingly, the alert condition bit is set to ‘1’ if the temperature has fallen below the configured value in register TLOW.

If the polarity bit is set to ‘1’ (POL=’1’), the alert condition bit is inverted. The following table summarizes the status of the alert condition bit with different alert conditions and polarity configurations.

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6.3.9

Figure 29:

Alert Condition Bit

Polarity Bit

Alert Condition

T ≥ THIGH

T ≤ TLOW

T ≥ THIGH

T ≤ TLOW

Alert Condition Bit (AC-Bit)

High Speed Mode

The bus operation is limited to 400kHz unless a high speed command is issued by the master device as the first byte after a START condition. This switches the bus to a high speed operation which allows data transfer frequencies up to 3.4MHz. Such a command is not acknowledged by the slave but the input filter time constants on the serial interface (SDA and SCL) are adapted to allow the higher transfer rate.

After a high speed command, the slave address is transmitted by the master in order to invoke a data transfer. The bus keeps operating at the higher operating frequency until the master issues a STOP condition on the serial bus. Upon the reception of the STOP condition by the slave, the input filters are switched to their initial time constants which allow lower transfer rates only.

6.3.10 General Call

A general call is issued by the master by transmitting the general call address (000 0000) with a low

R/W bit. When this command is issued on the bus, the device acknowledges this command. The device also acknowledges the second byte but ignores the data. Subsequent bytes sent by the master during the general call are not acknowledged.

6.3.11 Start Byte

When the master transmits address

000 0000 and a high R/W bit (“START byte”) the device acknowledges the address. The device then send the MSB data byte and LSB data byte, where the data corresponds to the content of the register whose address has been last written to. After reset this corresponds to the temperature register.

6.3.12 Timeout Function

The serial interface of the slave device is reset if the clock signal SCL is kept low for typ. 30ms. Such a condition results in a release of the data line by the slave in case it has been pulled to low level. The slave remains inactive after a timeout and waits for a new START command invoked by the bus master. In order to prevent a timeout, the bus transfer rate must be higher than 1kHz.

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6.3.13 Bus Conditions

The following conditions occur on the serial bus which is compatible to the I²C-Bus.

Bus Idle

The signals SDA and SCL are not actively driven and pulled to a high level by an external pull-up resistor.

Start Data Transfer

A transition of the SDA input from high to low level while the SCL signal is kept at high level results in a START condition. Such a START condition must precede any data transfer.

Stop Data Transfer

A transition of the SDA input from low to high level while the SCL signal is kept at high level results in a STOP condition. Any data transfer is finished by generating a STOP or START condition.

Data Transfer

The master device defines the number of data bytes between a START and STOP condition and there is no limitation in the amount of data to be transmitted.

If it is desired to read only a single MSB byte without the LSB byte, a termination of the data transfer can be provoked by issuing a START or STOP condition on the bus.

Acknowledge

It is mandatory for each slave device to respond with acknowledge if the device is addressed by the master. Acknowledge is indicated by pulling down the data line (SDA) while the clock signal (SCL) is high in the acknowledge clock phase. In order to avoid an unwanted START or STOP condition on the bus, setup and hold times must be met.

The master can signal an end of data transmission by transmitting a Not-Acknowledge on the last transmitted data byte by keeping the acknowledge bit at high level.

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6.3.14 Timing Characteristics

Figure 30:

Serial Interface Timing Diagram

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Figure 31:

Bus Timing Specifications

Parameter Symbol Fast Mode

Min

SCL clock frequency

Bus free time between STOP and START condition

Hold time after repeated

START condition

Repeated START condition setup time

Data in hold time

Data out hold time

(1)

Data setup time

SCL clock low period t t t f

SCL

BUF

HDSTA

SUSTA t

HDDAT t

DH t

SUDAT t

LOW

0.001

600

100

1300

0.4 0.001

160

100

160

SCL clock high period

Clock/Data fall time t

HIGH t

600

300

Clock/Data rise time t

300

Clock/Data rise time for

SCL

≤100 kHz

(1) t

1000

The device will hold the SDA line high for 100 ns during the falling edge of the SCL.

Max

High Speed Mode Unit

Min Max

3.4

MHz ns ns ns ns ns ns ns ns ns ns ns

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6.3.15 Timing Diagrams

The following timing diagrams depict the different bus operation modes and data transmission:

Figure 32:

Timing Diagram for Word Write

Frame 1 : Slave Address Byte Frame 2 : Index Register Byte

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SCL

SDA

1 0 0

A3 A2

R / W

Start by master

Values are defined by ALERT/ADD1 pin setting

Values are defined by

ADD 0 pin setting

Acknowledge by slave

0 0 0 0 0 0 IX 1 IX 0

Acknowledge by slave

Frame 3 : MSB Data Byte

1 2 3 4 5 6 7 8 9

Frame 4 : LSB Data Byte

1 2 3 4 5 6 7 8 9

SCL

( Continued )

SDA

( Continued )

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

Acknowledge by slave

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

Acknowledge by slave

Stop by master

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Figure 33:

Timing Diagram for Word Read

Frame 1 : Slave Address Byte Frame 2 : Index Register Byte

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SCL

SDA

1 0 0 A3

R / W 0 0 0 0 0 0 IX 1 IX 0

Start by master

Values are defined by ALERT/ADD1 pin setting

Values are defined by

ADD 0 pin setting

Acknowledge by slave

Frame 3 : Slave Address Byte

1 2 3 4 5 6 7 8 9

SCL

( Continued )

Acknowledge by slave

Stop by master

Frame 4 : Register MSB Data Byte

1 2 3 4 5 6 7 8 9

SDA

( Continued )

Start by master

1 0 0

A3 A2

R / W

Acknowledge by slave

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

Acknowledge by master

Frame 5 : Register LSB Data Byte

1 2 3 4 5 6 7 8 9

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

Acknowledge by master

Stop by master

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7 Application Information

Figure 34:

Application Example

VDD

Microcontroller

(Bus Master)

AS621x

Application Information

Pull-up resistors

Address Select 0

VDD

10nF

SDA

ADD0

VDD

Slave

SCL

ADD1/

ALERT

VSS

Address Select 1

In Figure 34 the connections of the AS621x temperature sensors to a microcontroller and the supply

voltage are shown.

The AS621x is connected to a microcontroller via an I²C bus (SDA and SCL only). Additionally the

Alert output can also be used for temperature monitoring (e.g. using the interrupt mode, refer to IM bit

settings), an example is given in Figure 34 where the Alert output is connected to microcontroller.

The I²C address of the AS621x can be selected by connecting the ADD0 and ADD1 to different pins

(refer to Figure 28 for details). These pins must not be left unconnected.

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7.1 External Components

Figure 35:

Schematic with External Components

AS621x

Application Information

VDD

SCL

SDA

Pull-up resistors

Address Select 0

SDA

ADD0

VDD

10nF

Slave

SCL

ADD1/

ALERT

VSS

Address Select 1

Alert

Figure 36:

Values for External Components

Parameter

Decoupling capacitor

Pull up resistors

Min

Typ

Unit

nF k

In Figure 35 and Figure 36 the schematics and the recommended values for external components are

shown.

The decoupling capacitor for the supply should have a value of at least 10 nF.

In order to use the alert functionality, the ALERT/ADD1 pin must be connected via a pull up resistor to

VDD.

For the serial interface, pull up resistors to VDD are mandatory.

The pull up resistors on the serial interface and the interrupt depend on the bus capacitance and on the clock speed.

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8 Package Drawings & Markings

AS621x

Package Drawings & Markings

Figure 37:

WLCSP Outline Drawing

Ref. Min Nom Max

Y ax dx ay dy d

Thickness

(with balls before reflow)

1475 1495

1005 1025

347.5

1515

1045

400

312.5

400

250

600

RoHS

Green

(1)

(2)

(3)

(4)

All dimensions are in micrometers. Angles in degrees.

Dimensioning and tolerance conform to ASME Y14.5M-1994.

This package contains no lead (Pb).

This drawing is subject to change without notice.

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Figure 38:

WLCSP Package Marking/Code for AS6212



XXXX

AS6212

XXXX Tracecode

Figure 40:

WLCSP Package Marking/Code for AS6218



XXXX

AS6218

Figure 39:

WLCSP Package Marking/Code for AS6214



XXXX

AS6214

XXXX Tracecode

AS621x

Package Drawings & Markings

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9 Revision Information

AS621x

Revision Information

Document Status

Product Preview

Product Status Definition

Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice

Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice

Datasheet Production

Datasheet

(discontinued)

Discontinued

Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade

Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs

Changes from previous version (v1-00) to current revision v2-00 Page

Figure 7: Updated conversion time

Updated conversion time reference

Added clarification for time to enter sleep mode 15

●

Added reference for longer first conversion in sleep mode 17

Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.

Correction of typographical errors is not explicitly mentioned.

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10 Legal Information

AS621x

Legal Information

Copyrights & Disclaimer

The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.

Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of

Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams

AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.

RoHS Compliant & ams Green Statement

RoHS Compliant:

The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.

ams Green (RoHS compliant and no Sb/Br/Cl):

ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material).

Important Information:

The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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Tel: +43 (0) 3136 500 0

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Datasheet

Digital Temperature Sensor

Content Guide

1 General Description

1.1 Key Benefits & Features

1.2 Applications

1.3 Block Diagram

2 Ordering Information

3 Pin Assignment

3.1 Pin Diagram

3.2 Pin Description

4 Absolute Maximum Ratings

5 Operating Conditions

5.1 Analog System Parameters

5.2 Digital System Parameters

6 Register Description

6.1 Register Overview

6.2 Detailed Register Description

6.3 Serial Interface

7 Application Information

7.1 External Components

8 Package Drawings & Markings

Green

9 Revision Information

10 Legal Information

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