AMS AS8510 Sensor Interface Datasheet
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AS8510
Data Acquisition Device for Battery Sensors
1 General Description
The AS8510 is a virtually offset free, low noise, two channel measurement device. It is tailored to accurately measure battery current from mA range up to kA range in conjunction with a 100 µ
Ω shunt resistor in series with the battery rail. Through the second measurement channel it enables capture of, either battery voltage synchronous with the current measurement, or, measure the analog output of an internal or external temperature sensor. Both channels are matched and can either measure small signals up to ±160 mV versus ground, through programmable gain amplifier or larger signals in the 0 to 1V range without the amplifier.
After analog to digital conversion and digital filtering, the resulting
16-bit digital words are accessible through 4-wire standard serial interface.The device includes a number of additional features explained in the next section.
2 Key Features
3.3V supply voltage
Two High resolution 16 bit Σ−Δ A/D converters
Programmable sampling to enable data throughputs from less than 1Hz to 8kHz
Zero Offset for both channels
Independent control of data rate on both channels
Precision, low noise, programmable gain amplifiers for both channels with gains 5, 25, 40, 100 to support wide dynamic ranges.
Figure 1. AS8510 Block Diagram
AVDD
REF
Option for multiplexing either one differential input, or two single ended inputs or the internal temperature sensor on one channel
Programmable current source for external temperature sensor connectable to any of the inputs
High precision and high stability 1.2V reference voltage source
Digital signal processing with filter options for both channels
Four operating modes providing
- Continuous data acquisition (or)
- Periodic single-shot acquisition, (or)
- Continuous acquisition on threshold crossing of programmed current levels (or)
- A combination of the above
On chip high-precision 4MHz RC oscillator or option for external clock
-40ºC to +125ºC ambient operation
AEC - Q100 automotive qualified
Internal chip ID for full traceability
SSOP-20 pin package
3 Applications
The AS8510 is ideal for shunt based batteries sensor. For high-side current sensing, the input signal may be conditioned using
ams
device AS8525 before applying to this device.
DVDD
ETR
ETS
VBAT_IN
VBAT_GND
Internal Temperature Sensor
Prog-Cur
Source
MUX and
Chopper
PGA
Bandgap Reference
16-bit Sigma-Delta ADC
AS8510
Oscillators
FIR / MA
MEN
CHOP_CLK
INT
CLK
RSHH
RSHL
Chopper PGA 16-bit Sigma-Delta ADC
AVSS
Analog Common Mode
VCM
Serial Interface
SCLK CS SDI SDO DVSS www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - C o n t e n t s
Contents
1 General Description
2 Key Features
3 Applications
4 Pin Assignments
5 Absolute Maximum Ratings
6 Electrical Characteristics
6.2 DC/AC Characteristics for Digital Inputs and Outputs
6.3 Detailed System and Block Specifications
6.4 Current Measurement Ranges (across 100µOhm shunt resistor)
7 Detailed Description
7.1 Current Measurement Channel
7.2 Voltage/Temperature Measurement Channel
7.3 Digital Implementation of Measurement Path
7.8 4-Wire Serial Port Interface
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AS8510
Datasheet - C o n t e n t s
7.10 Low Side Current Measurement Application
8 Package Drawings and Markings
9 Ordering Information
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AS8510
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
ETR
ETS
VBAT_IN
VBAT_GND
RSHH
RSHL
REF
VCM
AVDD
AVSS
9
10
7
8
5
6
1
2
3
4
AS8510
18
17
16
15
20
19
12
11
14
13
INT
CLK
SDI
MEN
CHOP_CLK
DVDD
DVSS
SDO
SCLK
CS
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Number
1
2
Pin Name
RSHH
RSHL
3 REF
4
9
10
11
12
13
7
8
5
6
VCM
AVDD
AVSS
ETR
ETS
VBAT_IN
VBAT_GND
CS
SCLK
SDO
Pin Type
Analog input
Analog output
Supply pad
Description
Positive Differential input for current channel
Negative differential input for current channel
Internal reference voltage to sigma-delta ADC; connect 100nF to
AVSS from this pin.
Common Mode voltage to the internal measurement path; connect 100nF to AVSS from this pin.
+3.3V Analog Power-supply
0V Power-supply analog
Voltage channel single ended input
Analog input
Battery voltage (high) input
Battery voltage (low) input
Digital input with pull-up Chip select with an internal pull-up resistor (SPI Interface)
Digital input
Clock signal (SPI Interface)
Digital output
Serial Data Input (SPI Interface) www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - P i n A s s i g n m e n t s
Table 1. Pin Descriptions
Pin Number
14
15
Pin Name
DVSS
DVDD
16 CHOP_CLK
17
18
19
20
MEN
SDI
CLK
INT
Pin Type
Supply pad
Digital output
Digital input
Digital I/O
Digital output
Description
0V Digital Ground
+3.3V Digital Supply
Chop Clock used in High side measurements to synchronize external chopper.
(As an example, when AS8525 is used to condition the input signal to the input range of AS8510, the chop clock is used by
AS8525.)
Digital output issued during the Standby Mode (SBM) to signal the short duration of data sampling. This signal is useful in the case of a High Side Measurement application.
(For example: This signal is used by AS8525 device to wake-up and enable the measurement path.)
Data signal (SPI Interface)
By default this pin is the internal clock output which can be used by a Microcontroller. The internal clock may also be disabled as an output by programming Register 08. To use an external Clock,
Register 08 has to be programmed.
Active High Interrupt to indicate data is ready www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2
may cause permanent damage to the device. These are stress ratings only. Functional operation of the
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Electrical Parameters
DC supply voltage (AVDD and DVDD)
Min
-0.3
Max Units
V
Notes
Input voltage (V
IN
) -0.3
5
AVDD + 0.3
DVDD + 0.3
V
Input current (latchup immunity)
(I
SCR
)
Electrostatic Discharge
Electrostatic discharge (ESD) all pins
Continuous Power Dissipation
-100 100
±2 mA kV
AEC - Q100 - 004
AEC - Q100 - 002
Total power dissipation
(all supplies and outputs) (P t
)
50 mW
SSOP20 in still air, soldered on JEDEC standard board @ 125º ambient, static operation with no time limit
Temperature Ranges and Storage Conditions
Storage temperature (T
STRG
)
Junction temperature (T
J
)
Thermal resistance (R thJC
)
-50 125
130
80
260
ºC
ºC
K/W
ºC
JEDEC standard test board, 0 air velocity
Norm: IPC/JEDEC J-STD-020
1
Package body temperature (T
BODY
)
Moisture Sensitive level (MSL)
Humidity non-condensing 5
3
85 %
1. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Non-hermetic Solid State Surface Mount Devices”.
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
6.1 Operating Conditions
Table 3. Operating Conditions
Symbol
AVDD
AVSS
A - D
DVDD
DVSS
T
AMB
I
SUPP
Parameter
Positive analog supply voltage
0V Ground
Difference in analog and digital supplies
Positive digital supply
0V Digital Ground
Ambient temperature
Supply current f
CLK
System clock frequency
1
1. Nominal clock frequency from external or internal oscillator.
Conditions Min
3.0
0
2.97
0
-40
6.2 DC/AC Characteristics for Digital Inputs and Outputs
All pull-up and pull-down have been implemented with active devices. SDO has been measured with 10pF load.
Table 4. INT
Symbol
I
LEAK
V
OH
V
OL
I
O
Parameter
Tri-state leakage current
High level output voltage
Low level output voltage
Output Current
Conditions Min
-1
2.5
Typ
Table 5. CS Input
Symbol
V
IH
V
IL
I
LEAK
Ipu
Parameter
High level input voltage
Low level input voltage
Input leakage current
Pull up current
Conditions
CS pulled to DV
DD
= 3.3V
Min
2.0
-1
-150
Typ
Table 6. SDI
Symbol
V
IH
V
IL
I
LEAK
Parameter
High level input voltage
Low level input voltage
Input leakage current
Conditions Min
2.0
-1
Typ
Max
3.6
0
0.1
3.63
0
125
5.5
4.096
Max
+1
0.4
4
Max
Max
0.8
+1
0.8
+1
-15
Units
V
V
V
V
V
ºC mA
MHz
Units
V
V
µA
Units
µA
V
V mA
Units
V
V
µA
µA www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 7. SDO Output
Symbol
V
OH
V
OL
I o
Parameter
High level output voltage
Low level output voltage
Output Current
Table 8. CHOP_CLK Output
Symbol
V
OH
V
OL
I o
Parameter
High level output voltage
Low level output voltage
Output Current
Table 9. CLK I/O with Input Schmitt Trigger and Output Buffer
Symbol
V
IH
V
IL
I
LEAK
I
PD
I o
V
OH
V
OL
Parameter
High level input voltage
Low level input voltage
Input leakage current
Pull down current
Output Current
High level output voltage
Low level output voltage
Table 10. SCLK with Input Schmitt Trigger
Symbol
V
IH
V
IL
I
LEAK
Parameter
High level input voltage
Low level input voltage
Input leakage current
Table 11. MEN Output
Symbol
V
OH
V
OL
I
O
Parameter
High level output voltage
Low level output voltage
Output Current
Conditions
Isource = 8mA
Isink = 8mA
Conditions
Conditions
DV
DD
DV
DD
= 3.3V
= 3.3V
CLK pulled to DVSS
Conditions
DV
DV
DD
DD
= 3.3V
= 3.3V
Conditions
Min
2.5
Typ Max
0.4
8
Units
V
V mA
Min
2.5
Typ Max
0.4
4
Units
V
V mA
-1
10
2.5
Min
2.4
Typ
1.0
+1
100
4
Max
0.4
Units
V
V
µA
µA mA
V
V
Min
2.4
-1
Typ Max
1.0
+1
Units
V
V
µA
Min
2.5
Typ Max
0.4
2
Units
V
V mA www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.3 Detailed System and Block Specifications
6.3.1 Electrical System Specifications
Table 12. Electrical System Specifications
Symbol
IDD
NOM
Parameter
Current consumption normal mode
IDD
SBM
Current consumption standby mode
Min Typ
3
40
Max
5.5
6.4
Current Measurement Ranges (across 100
µ
Ohm shunt resistor)
Table 13. Current Measurement Ranges
Symbol
I70
I200
I400
I1500
Parameter
I max
[A]
V sh
[mV]
Input current range of 70A in NOM ±77 ±8.1
Input current range of 200A in NOM
Input current range of 400A in NOM
±235
±400
±24.7
±42
Input current range of 1500A in NOM +2076/-1523 +218/-160
PGA
Gain
Nominal
100
40
25
5
1. V
INADC
= V sh
* Gain, gain deviations to be considered according to
and
.
2. AVDD, DVDD of 3.3V with ±5% variation.
Units
mA
µA
Notes
Average of NORMAL Mode Power consumption over a period of 10sec when the device is in STANDBY Mode
Data Rate
(f
OUT
)
@ 1 kHz
@ 1 kHz
@ 1 kHz
@ 1 kHz
V
INADC
1
[mV]
890
1088
1137
1204
PSR
2
[dB]
60
60
60
60
The maximum current range can be calculated by the equation:
I max
= (VREF min
– V
OSDRIFT
*Gn*e)/(Gn *e*R
SHUNT
)
Where
VREF min
is minimum ADC reference voltage for the anticipated temperature range e.g.1220mV
V
OSDRIFT
is the maximum input referred PGA offset (e.g. 3 mV)
Gn is the nominal gain as selected (G1 to G4) e is maximum gain tolerance (1,1)
R
SHUNT
is the maximum shunt resistance
Exceeding this maximum current range will lead first to non-linearity and finally to clamping.
Note:
The Data Rate at the output can be calculated according to the formula:
fsout=2*fchop /R2 (R2 is down sampling ratio taking values 1, 2, 4 up to 32768 as powers of 2)
Table 14. Valid Combinations of the Chopper Clock, Oversampling Clock and Decimation Ratios
Over Sampling Frequency Chopper Frequency
1.024MHz
2.048MHz
2kHz
2kHz
2.048MHz
2.048MHz
2kHz
4kHz
Decimation Ratio
64
64
128
64 www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.4.1 Differential Input Amplifier for Current Channel
Table 15. Differential Input Amplifier for Current Channel
V
Symbol
IN
_AMP
Parameter
Input voltage range
I
IN
_AMP
Input current
1, 11
Conditions
RSHH and RSHL
RSHH and RSHL@ +160mV input voltage at 125ºC with PGA
ICM
G = G1
G = G2
G = G3
G = G4 e f
P
_AMP
Absolute input voltage range
2
Gain1
3, 4, 9
Gain2
3, 4, 9
Gain3
3, 4, 9
Gain4
3, 4, 9
Gain deviation
Pole frequency
4, 5
I10
I200
I400
I1500 i = 1, 2, 3, 4
ε T1
V
OSDRIFT
V os
V os_ch
V
Ndin
THD
Gain drift with temperature
6
Offset drift with temperature
7, 10
Input referred offset
7, 10
Noise density
4, 8
Total harmonic distortion
-20ºC to +65ºC
Gain 5, 25, referenced to room temperature
@65ºC
After trim at -20ºC
Chopping enabled
For 150 Hz input signal
Min
-160
-50
0.9 * Gi
15
Typ
2
-160
+300
100
40
25
5
350
0
25
70
Max
+160
50
1.1 * Gi
±0.3
Units
mV nA mV kHz
%
2700
420
µV
µV
LSB nV/
√
Hz dB
Notes:
1. Leakage test accuracy is limited by tester resource accuracy and tester hardware.
2. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
3. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are programmed independently.
4. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaranteed by design.
5. Pole frequency of input amplifier changes with GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other ranges. This parameter is not measured in production.
6. Based on device evaluation. Not tested.
7. These offsets are cancelled if chopping enabled (default).
8. Noise density calculated by taking system bandwidth as 150Hz.
9. Refer to Measurement Ranges shown in Table 13
.
10. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
11. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of protection diode.
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
G = G1
G = G2
G = G3
G = G4 e f
P
_AMP
V
NDIN
THD
6.4.2 Differential Input Amplifier for Voltage Channel
Table 16. Differential Input Amplifier for Voltage Channel
Symbol Parameter
V
IN_
AMP
Input voltage range
1, 10
I
IN_
AMP
Input current
2, 10
Conditions
VBAT_IN, ETR, ETS @ +160mV input voltage at 125ºC with PGA
ICM
Absolute input voltage range
3
Gain1
4, 5
Gain2
4, 5
Gain3
4, 5
Gain4
4, 5
Gain deviation
Pole frequency
5, 6
Noise density
5, 7
Total harmonic distortion i = 1, 2, 3, 4
ε
T
1
V
OS
V os_ch
V
OSDRIFT
Gain drift with temperature
8
Input referred offset
9
Offset drift with temperature
9
For 150Hz input signal
-20ºC to +65ºC
Gain 5, 25, referenced to room temperature
After trim at -20ºC
Chopping enabled
@65ºC
Min
-160
-50
0.9 * Gi
15
Typ
2
-160
+300
100
40
25
5
25
70
0
350
Max
+160
50
1.1 * Gi
±0.3
420
2700 kHz nV/ √ Hz dB
%
µV
LSB
µV
Units
mV nA mV
Notes:
1. Input for the voltage channel can be as high as 1220mV, in this high input case PGA will be bypassed.
2. Leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to condensing moisture.
3. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
4. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are programmed independently.
5. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaranteed by design.
6. Pole frequency of input amplifier changes with changing the GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other ranges. This parameter is not measured in production.
7. Noise density calculated by taking system bandwidth as 150Hz.
8. Based on device evaluation. Not tested.
9. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
10. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of protection diode.
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.4.3 Sigma Delta Analog to Digital Converter
Table 17. Sigma Delta Analog to Digital Converter
Symbol Parameter
V
VREF
INADC
R1
Reference voltage
6
Input range
1
Oversampling ratio/Decimation Ratio
2 f ovs
Oversampling frequency
3
RES
BW
S/N
Number of bits
Bandwidth
4
Signal to noise ratio
5
Conditions
At V ref
= 1.22V
Min
0
64
1
Typ
1.225
Max
128
1024/
2048
±1.22
128
16
500
90
Units
V
V kHz bits
Hz dB
Notes:
1. Production test at ±800mV. Maximum V
IN
can be 1.22V with VREF=1.225V.
2. Programmable. It is defined with respect to the first decimator in the ΣΔ ADC.
3. Programmable: Internal clock is 1024/2048 kHz; external clock max is 8192 kHz.
4. Dependent on fovs, R1 and R2. The bandwidth is calculated according to the formula:
BW=fovs/(2*R1*R2); the sampling frequency at the output of the A/D converter is 2*BW.
5. Defined at maximum input signal, BW=500 Hz (1Hz to 500 Hz), fovs=1024 kHz, R1=64, fchop=2 kHz and R2=2.
6. Reference voltage might be forced from external.
6.4.4 Bandgap Reference Voltage
Table 18. Bandgap Reference Voltage
Symbol Parameter
V
V
REF
TRIM
REF
ACC
Reference Voltage after trim
1, 2
Reference Voltage Initial Accuracy
1, 2
V
REF
DRIFT
PSRR
REF
SUT
AVDD
SUT
PD
R
NDVREF
V
NDVREF
CL
VREF
ESR
VREF
Reference Voltage Temperature drift
PSR @ dc
Start Up Time with supply ramp
3
Start Up Time from power down
3
Output resistance of band gap
Bandgap reference thermal noise density
3
Output Capacitor (Ceramic)
Conditions
Trim at 65ºC
At 65ºC
Temperature range
-20 to 65 ºC
Temperature range
-40 to 125 ºC
Min
0.02
Typ
1.225
+0.4/
-0.6
80
5
500
100
Max
±3.5
±0.4
Units
V mV
%
% dB ms
1 ms
1000
Ω
300 nV/ √ Hz nF
1
Ω
Notes:
1. Accuracy at 65ºC.
2. No DC current is allowed from this pin.
3. This is a design parameter and not production tested.
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.4.5 Internal (Programmable) Current Source for External Temperature Measurement
Table 19. External Temperature Measurement
Symbol Parameter
I
I
CURON
CUROFF
5-bit current source enabled
1
5-bit current source disabled
Conditions
5-bit programmable current source
Limited by leakage
Min
0
T
K
_
CS
Temperature coefficient of current source
2
V
MAXETR
V
MAXETRMOD
V
MAXETS
V
MAXETSMOD
Voltage on pin ETR
3
Max voltage on pin ETR when PGA is bypassed
4
Voltage on pin ETS for resistor sensor
3
Max. Voltage on pin ETS when PGA is bypassed
5
Typ
270
10
1000
Max
320
1000/G
1.22
1000/G
1.22
V
V
V
Units
µA nA ppm
/ ºK mV
Notes:
1. Current value can be programmed in steps of 8 μ A from 0 to 256 μ A with a process error of 30%.
2. Temperature coefficient is not important since external temperature measurement is a 2 step measurement. The value specified is guaranteed by design and will not be tested in production.
3. Maximum voltage on pin ETR (reference) can be calculated by given formula, where G is the gain of PGA (G=100).
4. Maximum voltage on pin ETR, if PGA is bypassed.
5. Maximum voltage on pin ETS, if PGA is bypassed.
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.4.6 CMREF Circuit (VCM)
Table 20. CMREF Circuit
Symbol
V
VCM
C
L
Parameter
Output voltage
Load capacitance
Min
1.6
6.4.7 Internal AVDD Power-on Reset
Table 21. Internal AVDD Power-on Reset
Symbol
V
PORHIA
Parameter
Power On Reset Threshold t
PORA
I
PORA
POR time - The duration from Power ON till the time, internal Power On Reset signal goes HIGH
1
Current consumption in POR block
2
Min
2.2
1
1. POR pulse is always longer than t
PORA
whatever the slope of the supply.
2. I
PORA
can not be switched off.
6.4.8 Internal DVDD Power-on Reset
Table 22. Internal DVDD Power-on Reset
Symbol
V
PORHID
Parameter
Power On Reset Threshold
V
HYST t
PORD
I
PORD
Hysteresis
1
POR time - The duration from Power ON till the time, internal Power On Reset signal goes
HIGH
2
Current
3
1. V
PORLO
= V
PORHI
- V
HYST where V
PORLO is the lower threshold of POR.
2. V
PORLO
= V
PORHI
- V
HYST where V
PORLO is the lower threshold of POR.
3. I
PORD
can not be switched off.
Min
2.2
0.2
1
6.4.9 Low Speed Oscillator
Table 23. Low Speed Oscillator
Symbol
f
LS f
LS
_
ACC
I
LS
Parameter
Frequency
Accuracy
Supply current
Min
Typ
1.7
100
Typ
2.4
1.5
1.5
Typ
262.144
± 7
5
Typ
2.4
0.25
Max
1.8
Max
2.6
Max
Max
2.7
0.4
Units
V nF
Units
kHz
%
µA
Units
V
V
µs
µA
Units
V
µs
µA www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.4.10 High Speed Oscillator
Table 24. High Speed Oscillator
Symbol
f
HS f
HSACC
I
HS
Parameter
Frequency
Accuracy
1, 2
Supply current
Min Typ
4.096
±4
300
Notes:
1. Accuracy after trimming.
2. Accuracy for limited temperature range of -20 to 65 ºC.
6.4.11 External Clock
Table 25. External Clock
Symbol Parameter
f
CLKEXT
Clock frequency
DIV
CLKEXT
DC
CLKEXT
Clock division factor
Duty Cycle of external clock
Conditions
to be programmed in Register 08
CLK_REG through the serial bus SPI.
Min
40
Max Units
MHz
%
µA
Typ
2048/
4096/
8192
2/4/8
Max Units
kHz
60 %
6.4.12 Internal Temperature Sensor
Table 26. Internal Temperature Sensor
Symbol
T
INTRNG
Δ
TIN
Parameter
Temperature sensor range
Temperature measurement accuracy
T
INTSLP
T
INT
65
G
5
Temperature sensor slope
Temperature sensor output at gain 5
Conditions Min
-40
Typ
3
Guaranteed by design; at PGA gain 5 which is the recommended Gain for internal temperature measurement.
27
40660 41807
Max
125
Units
ºC
ºC
Digits/C
43012 Digits
6.5 System Specifications
Table 27. System Specifications
Symbol
I
S
At
Ph
Parameter
Channel to channel isolation
1
Difference in channel to channel attenuation @600Hz
1, 2
Difference in phase shift between the two channels @600Hz
1, 2
System Measurement Error Budget for Voltage and Current Channel.
Min Typ Max
-90
3
5
Units
dB dB
Deg www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Temperature Range: -20ºC to +65ºC; Output data rate is 1kHz, V
CC
= 3.3V, chopping enabled.
Table 28. System Measurement Error Budget for Gains 5 and 25
Symbol Parameter
System measurement error
3, 4
Conditions
Err
Voltage channel signal path measurement error
5
Measurement error due to PGA gain drift
Measurement error due to V
REF
drift
From device evaluation
Measurement error due to non-linearity of PGA Tested by distortion measurements
Min Typ
±0.5
Notes:
1. These specifications are defined by taking one channel as reference and measured on the other channel.
2. Guaranteed by design.
3. System measurement error due to noise, individual block parameter drifts and non linearity. Based on evaluation, not tested.
4. System error due to offset is neglected because of chopper architecture.
5. PGA is by-passed.
Max
±0.8
±0.5
±0.3
±0.4
±0.025
Units
%
%
%
% www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
System Error Compensation Function:
For battery voltage measurement it is recommended to by-pass the PGA. This eliminates PGA gain drift as an error source, thus error for the VBAT/VBAT_GND differential signal path is determined by VREF drift with temperature. The typical characteristic of VREF versus temperature extracted from 3 production lots is shown in
. This function could be used to improve accuracy by an error correction method utilizing the internal temperature sensor. In this case ADC raw data readings need to be corrected with a temperature dependent factor by the software in the external micro controller. This factor is given by a generic compensation function and can be applied to all IC’s because VREF is production trimmed to minimize linear coefficient of VREF over temperature.
Figure 3. Reference Error Compensation Function
1.0001
1
0.9999
0.9998
0.9997
0.9996
0.9995
0.9994
0.9993
0.9992
F
Comp
= −3.9658e−007 T
2
+ 2.0407e−005 T + 0.99974
Polynom Fit
Measured points
−10 0 10 20 30
Temperature [°C]
40 50 60 70
Generic compensation factor the ADC output need to be multiplied with:
F comp
= (A*T^2 + B*T + C)
Where:
F comp
is the compensation factor for VREF drift over temperature normalized to 1 at 25°C
T is Temperature reading from calibrated internal temperature sensor in [°C]
A: -4E-7
B: 2E-5
C: 0,9997
The compensated ADC value = raw ADC value * F comp
If PGA is by-passed and an external precision reference is applied, the signal path measurement error is basically determined by the drift due to temperature and ageing of the external reference.
Current channel error contributions for a single temperature end of line calibrated system are shunt resistance, PGA gain and VREF changes with temperature. The drift of a shunt resistor made from Manganin alloy and VREF drift with temperature are non-linear and show 2 nd
order
if thermally coupled to the AS8510. Over all error can be further reduced by an error correction method in external micro controller by matching typical VREF(T) curvature to R shunt
(T) curvature with the help of the internal temperature sensor.
Total final current channel system error calculated from quadratic summing of error contributions from Isabellenhuette shunt PPAP data and
AS8510 safe launch data over 21000 units is ±0.5%.
Temperature sensor system considerations:
Internal temperature sensor can be used to measure the ambient temperature because there is just 13 mW of AS8510 power dissipation in normal mode. This results in internal self-heating of less than 1°C.
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
The AS8510 consists of two independent high resolution 16-bit SD analog to digital conversion channels. The measurement path of these two channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filter for simultaneous measurement of Current and Voltage/Temperature.
The two measurement channels, namely the Current and Voltage/Temperature measurement channels have identical data path.
The input signal is amplified in the Programmable Gain Amplifier (PGA) with any of the selected gains of 1, 5, 25, 40 and 100 facilitating measurement of a wide range of Current, voltage and temperature levels. Gain Settings for different input ranges and any associated restrictions are explained in the
Offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. By default the chopper/de-chopper is ON in the measurement path. It may be disabled by programming the appropriate register.
The amplified input signal is converted into a single-bit pulse-density modulated stream by the Σ Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. The decimation ratios of 64, 128 may be selected in the first filter stage. For reducing data rate further, the second stage decimation can be used.
An optional FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
7.1 Current Measurement Channel
The voltage across a Shunt Resistor, connected in series with the Battery negative terminal, forms the input signal to the Current Measurement channel. RSHH and RSHL are the Current measurement input pins. Offset in the input signal is nullified with the use of a chopper and a dechopper at appropriate stages in the data path. The programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and
100 enables measurement of current ranges from ±1A to ±1500A. The sampled input signal is converted into a single-bit pulse-density modulated stream by the Σ Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data equivalent to the input current signal. The programmable input sampling rate and the decimation ratio determine the output data rates. The data path can be programmed to provide 1Hz to 2 kHz rates in the various modes available. An optional FIR filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
After enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles.
7.2 Voltage/Temperature Measurement Channel
The other two parameters of the Battery for measurement are Voltage and its Temperature. The second channel accepts signals from four independent sources through a Multiplexer as listed below:
An attenuated battery voltage obtained through appropriate external resistor divider, (or)
A signal from the external temperature sensor, (or)
A signal from external reference, (or)
A signal from the internal temperature sensor.
Apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the Current measurement channel.
RSHH and RSHL are the Current measurement input pins
The Battery Voltage which can go up to 18V is attenuated through a Resistor Divider externally and is applied to the Voltage Channel. For
Automotive Battery measurement, the Gain of the PGA should be restricted to 5 and 25. The latency for the first result from the voltage measurement channel is two conversion cycles.
A second option on this measurement channel is to measure Temperature. Internally generated constant current is pumped through the
Temperature Sensor with positive temperature coefficient, and, a high- precision resistor. The voltages across the sensor and the resistor form the inputs to the measurement channel one at a time. The difference between the two voltages which is independent of the magnitude of the current is used to determine the temperature accurately. The Voltage across the sensor is applied between the ETS and VSS pins and, the voltage across the high-precision resistor is applied between ETR and VSS. External Temperature measurement involves the acquisition of two signals one after the other using the same constant current source. The latency for the first result from the temperature measurement channel is two conversion cycles.
A third option on the measurement channel is to measure the internal temperature. Hence, one of the three options for measurement of Battery
Voltage, External Temperature and, internal temperature may be carried out by selection of appropriate inputs through the internal multiplexer selection.
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.3 Digital Implementation of Measurement Path
Figure 4. Block Diagram of Digital Implementation
MOD_IN
MOD_CLK
f
mod
R1
R2
FIR_MA_SEL
CIC1
64 / 128
f
mod
/ R1
Dechopper
f
chop
* 2
CIC2
f
chop
* 2 / R2
FIR/MA
f
chop
* 2 / R2
DATAOUT
R1
f chop
R1 = First decimation ratio (64 or 128)
R2 = Second decimation ratio (1 to 32768)
CHP_CLK
CLK DIVISION
BLOCK
MOD_CLK
density modulated output (MOD_IN) from the second order sigma delta modulator along with the oversampling frequency clock (MOD_CLK).
The MOD_CLK directly goes to a clock division block, which generates chopper clock (CHOP_CLK). The CHOP_CLK can be one of 2kHz or
first phase, the R1 down sampling rate can be obtained by selecting either 64 or 128 in Registers DECREG_R1_I, DECREG_R1_V in
.
The 16-bit CIC1 output is dechopped with respect to CHOP_CLK. The output of Dechopper is passed through the CIC2 filter with a decimation ratio of 1to 32768 in steps of power of 2. This output is then processed through a FIR or Moving Average (MA) filter. FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. MA filter is used to provide averaged output and the number of samples for averaging can be any integer value from 1, 3, 7 or 15.
7.4 Modes of Operation
The device operates in four different modes, namely,
Normal Mode 1 (NOM1),
Normal Mode 2 (NOM2),
Standby Mode 1 (SBY1), and,
Standby Mode 2 (SBY2).
The Normal Modes are full-power modes with the exception that in Normal Mode 2, sampling is normally at a programmed lower frequency and is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel.
The Standby Modes are lower power modes. Sampling is normally at a very low frequency interval. In Standby Mode 2, data sampling can be carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it generates interrupt on the INT pin.
The device enters into the “Stop” state on Power On. This is a state where in the data path is inactive and can be entered into from any of the
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 5. State Transition Diagram
RESET
OTP_INT
Wait for otp_load
Completes in 32 cycles of lp_clk stop star t
1.5msec &
NORM
STOP
Analog Stablization period
Wait for 1.5msec
A_STB
NORM
Wait for x number of conversions
SBM_ON
sto p
NO
RM
TT1
_tim eou t
SBM
SBM_OFF
Wait for TT1 timeout
NORM or stop
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Note:
1. Device soft reset can be written in any of the following states STOP, A_STB, SBM_ON, SBM_OFF by writing “0” into D[7] of the RESET
_REG (Address 0X09).
2. Measurement path of soft reset should be written in any the states, STOP, SBM_OFF by writing “0” into D[6] of the RESET _REG (Address
0X09).
3. When soft reset is used for the measurement path or for the device, external clock needs to be disabled if the system clock is external clock in the application.
7.4.1 Normal Mode 1 (NOM1)
On Power-on-reset of the device, AS8510 goes into STOP State.
through the serial port SPI. Data Rate of voltage and current channels can be independently programmed and both the channels generate interrupts for every output available from ADC. The interrupt signal is generated on the INT pin. The width of the interrupt pulse is eight cycles of l p_clk
. The data is stable up to the next interrupt. If the data rate is different for the two channels, the interrupt rate would follow the higher rate among the two channels. Data update can be known by reading the status register. The functionality is explained in the waveform shown in
Figure 6. Normal Mode 1
I
DATA
I
Sampling with f1
V,T
DATA
V,T
Sampling with f2
STOP START
Current Channel
DATA Register
Voltage Channel
DATA Register
INT at f1 rate from current channel
Interrupt from the current channel is at f1 rate which is integer multiple of f2 rate from voltage channel t t
T
INT
7.4.2 Normal Mode 2 (NOM2)
NOM2 differs from NOM1 in such a way that it allows for a relaxed data rate at a period of T
MC
by programming the corresponding register as long as the amplitude of current is less than a programmed threshold I
THC
. However, when, the measured input signal exceeds the programmed threshold, the data rate is changed to the rate of NOM1 mode.
Transition to NOM2 occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in
Table 33 is set to 1 and mode control bits to
01 through SPI. In this mode the data rate should be programmed with the time of T
MC
. An interrupt signal is generated on INT at the rate of T
MC secs with a pulse width of eight cycles of l p_clk
. The data is stable up to the next interrupt. The data sample is compared against the programmed threshold and when it is exceeded, the data sampling rate is changed to provide data at the data rate of NOM1 mode. However, as soon as the data sample amplitude falls below the programmed threshold, the sampling rate is restored to provide data at the rate of T
MC
. The functionality is illustrated in the waveform
.
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 7. Normal Mode 2
I
I
DD
I
THS
T
MC
V,I,T
T
MC
V,I,T V,I,T
I < I
THS
V,I,T V,I,T
Sampling with f t
I > I
THS
INT
T INT
7.4.3 Standby Mode1 (SBM1)
The low-power Standby Mode can be entered only through the STOP state. Transition to SBM1 mode occurs when the “START BIT” D0 of Mode
with the time of Ta. An interrupt signal is generated on INT at the rate of Ta secs., and with a pulse width of eight cycles of l p_clk
. The data is stable up to the next interrupt. The functionality is illustrated in Figure. During the period of Ta, only one data sample is made available and, during the rest of the period, the device is maintained in STOP state to reduce power consumption. The microcontroller which receives the data on the Interrupt, is also expected to be processing the data for a short time as shown clearly in the
to ensure the overall low-power consumption of the data acquisition and processing system.
Figure 8. Standby Mode 1
I
DD
MCU MCU
ADC
MCU
V, I, T
V, I, T t
T a
sec.
Start SBM1
Channel
DATA Register
INT
DATA – A0
T conv
T a
sec.
DATA – A1
T conv
T a
sec.
DATA – A2
T conv
DATA – A3
T
INT www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.4.4 Standby Mode2 (SBM2)
Standby Mode 2 is an extension of the Standby Mode1 to achieve even a lower power in the data acquisition system by providing interrupt to the microcontroller only when the data sample exceeds the set current threshold. The Standby Mode can be entered only through the STOP state.
Transition to SBM2 mode occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in
is set to “1” and Mode Control
Bits D7,D6 to “1,1” through SPI. In this mode the date rate is programmable with the time of Ta in the Ta control registers B, C. The data sample is made available and an interrupt signal is generated on INT pin only when the input signal exceeds the threshold set in Current Threshold
Figure 9. Standby Mode 2
I
DD
|I| > I Threshold I
MCU
I
ADC t
Start SBM2
Channel
DATA Register
INT
T a
sec.
DATA – A0
T conv
T a
sec.
DATA – A1
T conv
T a
sec.
DATA – A2
T conv
DATA – A3
T
INT
7.5 Reference-Voltage
Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement.
7.6 Oscillators
A High-speed oscillator (HS) generates the oversampling clock. For internal state machine and Interrupt generation, a low-speed Oscillator (LS) is also available.
7.7 Power-On Reset
The AS8510 has PORs, APOR and DPOR on analog and digital power supplies respectively. On PORs of both supplies, initialization sequence
happens and the system status is shown in state diagram (see Figure 5)
.
As shown in the state diagram, the system is in RESET state until DPOR output goes to logic HIGH and subsequently until APOR output goes to logic HIGH. Once analog power supply is available, the system goes into OTP_INT state and loads the default values into the control and data registers and goes into STOP state. If analog POR, APOR goes low at any time, the system goes into RESET state. In the STOP state, the
AS8510 can be programmed and by giving start command it starts working following the state machine.
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.8 4-Wire Serial Port Interface
The SPI interface is used as interface between the AS8510 and an external micro-controller to configure the device and access the status information. The micro-controller begins communication with the SPI which is configured as a slave. The SPI protocol is simple and the length of each frame is an integer multiple of bytes except when a transmission is started. Each frame has 1 command bit, 7 address/configuration bits, and one or more data bytes. The edge of CS and the level of SCLK during the start of a SPI transaction, determine the edge on which the data is transferred from the SPI and the edge on which the data is sampled by the slave.
describes the setting of the transfer and sampling edges of SCLK.
shows the falling edge and rising edge for data transfer and data sampling respectively, when SCLK is HIGH on the falling edge of CS.
Table 29. CS and SCLK
CS
FALL
FALL
ANY
SCLK
LOW
HIGH
ANY
Description
Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock.
Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock.
Serial data transfer edge is unchanged.
Figure 10. Protocol for Serial Data Write with Length = 1
CS
SCLK
SDI
SDO
0
A6
A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Transfer edge Sampling edge
Data D7 – D0 is moved to Address A4..A0 here
7.8.1 SPI Frame
A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of bytes. Command is coded on the 1 first bit, while address is given on LSB 7 bits
.
Table 30. Command Bits
Command Bits
C0 A6 A5
Register Address or Transmission Configuration
A4 A3 A2 A1 A0
Table 31. Command Bits
C0
0
1
Command
WRITE
READ
<A6:A0>
ADDRESS
ADDRESS
Description
Writes data byte on the given starting address.
Read data byte from the given starting address.
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Datasheet - D e t a i l e d D e s c r i p t i o n
If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling), the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.
7.8.2 Write Command
For write command, C0=0. After the command code C0 is transferred, the address of register to be written is provided from MSB to LSB.
Subsequently one or more data bytes can be transferred from MSB to LSB. For each data byte following the first one, used address is the incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge. The
SPI slave samples it on the next clock edge. These edges are determined by the level of SCLK as shown in
are examples of write command without and with address self-increment.
Figure 11. Protocol for Serial Data Write with Length = 1
CS
SCLK
SDI
SDO
0
A6
A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Data D7 – D0 is moved to Address A4..A0 here
Figure 12. Protocol for Serial Data Write with Length = 4
CS
SCLK
SDI
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDO
Data D7-D0 is moved to Address
A4-A0 here
Data D7-D0 is moved to Address
A4-A0 +1 here
Data D7-D0 is moved to Address
A4-A0 +2 here
Data D7-D0 is moved to Address
A4-A0 +3 here
Data D7-D0 is moved to Address
A4-A0 +4 here www.ams.com/AS8510 Revision 3.8
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CS
SCLK
SDI
SDO
AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.8.3 Read Command
For Read command C0=1. After the command code C0, the address of register to be read is provided from MSB to LSB. Then one or more data bytes can be transferred from the SPI slave to the master, always from MSB to LSB. To transfer more bytes from consecutive addresses, SPI master keeps CS signal LOW and SPI clock active as long as it desires to read data from the slave. Each bit of the command and address of the frame is to be driven by the SPI master on the SPI clock transfer edge where SPI slave samples it on the next SPI clock edge.
Each bit of the data section of the frame is driven by the SPI slave on the SPI clock transfer edge and SPI master samples it on the next SPI
clock edge. These edges are determined as per Table 29
and examples of read command without and with address self-increment.
Figure 13. Protocol for Serial Data Read with Length = 1
1
A6
A5 A4 A3 A2 A1 A0
D7 D6 D5
Data D7 – D0 at
Address A4..A0 is read here
D4 D3 D2 D1 D0
Figure 14. Protocol for Serial Data Read with Length = 4
CS
SCLK
SDI
1
A
6
A
5
A
4
A
3
A
2
A
1
A
0
SDO
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Data D7-D0 at
Address A4-A0 is read here
Data D7-D0 at
Address A4-A0 +1 is read here
Data D7-D0 at
Address A4-A0 +2 is read here
Data D7-D0 at
Address A4-A0 +3 is read here
Data D7-D0 at
Address A4-A0 +4 is read here www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.8.4 Timing
In the following timing waveforms and parameters are exposed.
Figure 15. Write Timing for Writing
CS
SCLK
SDI t
CPS
t
CPHD
CLK polarity t
SCLKH
t
SCLKL
t
DIS
t
DIH
DATAI
SDO
DATAI
...
...
t
CSH
...
DATAI
...
Figure 16. Read Timing for Reading
CS
SCLK
SDI
DATAI
SDO t
SCLKH t
SCLKL
DATAI
DATAO (D7 ) t
DOD
DATAO (D0 ) t
DOHZ www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.8.5 SPI Interface Timing
Table 32. SPI Interface Timing
Symbol
General
BR
SPI
T
SCLKH
T
SCLKL
Write timing
Parameter
Bit rate
Clock high time
Clock low time
Conditions
t t t
DIS t
DIH
CPS
CPHD
Data in setup time
Data in hold time
T
CSH
Read timing
t
DOD
CS hold time
Data out delay t
DOHZ
Data out to high impedance delay
Time for the SPI to release the SDO bus
Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity)
Clock setup time
(CLK polarity)
Clock hold time
(CLK polarity)
Setup time of SCLK with respect to CS falling edge
Hold time of SCLK with respect to CS falling edge
Min
400
400
20
20
20
20
20
Typ Max Units
1
80
80 ns ns ns
Mbps ns ns ns ns ns ns www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.9 Control Register
This section describes the control registers used in AS8510. Registers can be broadly classified into the following categories.
Data access registers
Status Registers
Digital signal path control registers
Digital Control registers
Analog Control Registers
Table 33. Control Registers
Addr in
HEX
Register Name
Data Access Registers
00
01
DREG_I1
(ADC Data Register for Current)
DREG_I2
(ADC Data Register for Current)
02
DREG_V1
(ADC Data Register for Voltage)
03
DREG_V2
(ADC Data Register for Voltage)
Status Registers
POR Value R/W
0000_0000
0000_0000
0000_0000
0000_0000
R
R
R
R
D[7:0]
D[7:0]
D[7:0]
D[7:0]
04 STATUS_REG 0000_0000 R
D[3]
D[2]
D[1]
D[0]
D[7]
D[6]
D[5]
D[4]
8-bit Control / Status Data
Denotes the Current ADC MSB Byte (ADC_I[15:8])
Denotes the Current ADC LSB Byte (ADC_I[7:0])
Denotes the Voltage ADC MSB Byte (ADC_V[15:8])
Denotes the Voltage ADC LSB Byte (ADC_V[7:0])
NOM1/NOM2 Data Ready
NOM2 Threshold Crossover
SBM1 Data Ready
SBM2 Threshold Crossover
APOR status
Data from current channel updated
Data from voltage channel updated
Reserved www.ams.com/AS8510 Revision 3.8
29 - 48
AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
Register Name POR Value
Digital Signal Path Control Registers for Current Channel
R/W
05 DEC_REG_R1_I
8-bit Control / Status Data
0100_ 0101 R/W
D[7]
D[6:5]
D[4:1]
D[0]
This bit selects decimation rate is used for current channel. Default is 0 (Down Sampling Rate is 64)
0
1
Down Sampling Rate is 64
Down Sampling Rate is 128
These two bits select division ratio of oversampling frequency clock MOD_CLK to be used as chopper clock, CHOP_CLK.
Default is “10” (divide by 512)
10
11
00
01
Chopper Clock Always High
Divide by 256
Divide by 512
Divide by 1024
These four bits select the decimation ratio of second
CIC stage. Default is “0010” (equal to 4)
0100
0101
0110
0111
0000 1
0001 2
0010
0011
4
8
16
32
64
128
1000
1001
1010
1011
256
512
1024
2048
1100
1101
1110
1111
4096
8192
16384
32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
0
1
Unmask
Mask www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
Register Name
06 DEC_REG_R2_I
POR Value R/W
1100_0101 R/W
D[7]
D[6]
D[5]
D[4]
D[3:2]
D[1:0]
8-bit Control / Status Data
I-Channel Enable, Default 1=enable
V-Channel Enable, Default 1=enable
0
1
Interrupt polarity
Active high
Active low
. Interrupt Mask Control for Current Channel Data
Ready Interrupt on INT pin (Default is 0)
0
1
Unmasked
Masked
These two bits select the source of output 16-bit data in
Normal mode from Current channel. Default is 01
10
11
00
01
FIR / MA Output
CIC2 Output
Dechop/Demod Output
CIC1 Output
These two bits select the source of output 16-bit data in
SBM mode from Current channel. Default is 01
10
11
00
01
FIR / MA Output
CIC2 Output
Dechop/Demod Output
CIC1 Output www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
Register Name
07 FIR CTL_REG_I
POR Value R/W
0000_0100 R/W
D[7]
D[6:3]
D[2:1]
D[0]
8-bit Control / Status Data
0000
0001
0011
0111
This bit selects FIR / MA Filter in Current channel.
Default is 0 (FIR)
0
1
FIR
MA Filter
These bits select the number of data samples for averaging in MA filter in Current channel.
Default is 0000 (bypass) bypass
1
3
7
1111 15
These two bits select the Measurement Path architecture in both Current and Voltage channels.
Default is 10 (Dechopper after CIC)
00
01
10
11
Demodulator after CIC1
Demodulator before CIC1
Dechopper after CIC1
(preferred and suggested)
Demodulator before CIC1 with settled sample
Reserved. Default 0. Do not change www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
08
09
Register Name
Digital Control Registers
CLK_REG
(Clock Control Register)
RESET_REG
(Reset Control Register)
POR Value R/W 8-bit Control / Status Data
0010_0000 R/W
1100_0000 R/W
D[7:6]
D[5:4]
D[3:2]
Oversampling frequency clock selection. Default is 00
(high speed (HS) internal Clock)
00
01
Internal HS Clock with No Clock Output
Internal HS Clock with Clock Output
10 External Clock
These two bits select the division ratio for HS clock/ external clock. Default is 10 (division by 4)
10
11
00
01
No division
Divide by 2
Divide by 4
Divide by 8
These two bits select the division ratio of HS clock, by which it should be divided before providing it on CLK pin. Default is 00 (No Division)
10
11
00
01
No Division
Divide by 2
Divide by 4
Divide by 8
D[1] 0
This bit selects the division ratio of LS clock
LS _CLK undivided (Low Speed clock)
1 LS _CLK divide by 2
Reserved D[0]
D[7]
D[6]
Entire device can be soft reset by writing “0” into this register bit. This bit will take a default 1 value on coming out of Reset
Measurement Path can be soft reset by writing “0” into this register bit. This bit will take a default 1 value after
Measurement Path is reset.
D[5:0] Reserved www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
0A
0B
0C
0D
0E
Register Name
MOD_CTL_REG
(Mode Control Registers)
MOD_Ta_REG1
(Ta Control Register)
MOD_Ta_REG2
(Ta Control Register)
MOD_I
TH
_REG1
(Current Threshold Register)
MOD_I
TH
_REG2
(Current Threshold Register)
POR Value R/W
0000_0000
1000_0000
0000_0000
0000_0000
0000_0000
R/W
R/W
R/W
R/W
8-bit Control / Status Data
D[7:6]
D[5:3]
D[2]
D[1]
D[0]
D[7]
D[6:0]
D[7:0]
D[7:0]
These two bits select the operating mode of the Device.
Default is 00 (Normal Mode 1)
00
01
Normal Mode 1
Normal Mode 2
10
11
Standby Mode 1
Standby Mode 2
These three bits select the number of cycles to be ignored before comparison with the set threshold in
Standy Mode. Default is 000 (3 cycles of data)
000
001
010
011
3 cycles of data
4 cycles of data
5 cycles of data
6cycles of data
100
101
110
111
7 cycles of data
8 cycles of data
9 cycles of data
10 cycles of data
This bit controls the CHOP_CLK availability on
CHOP_CLK pin.
Default is 0
0
1
Disabled
Enabled
Enabling the MEN pin to indicate transition from
Standby to Normal Mode.
0
1
Disabled
Enabled
This bit is used to take the device from STOP state to any of the Modes based on D[7:6] selection of this register.
0
1
Retain in STOP state
Enables transition to Normal or Standby
Modes.
0
1
Unit of Ta in SBM1/SBM2. Default is 1
Unit is in milliseconds
Unit is in seconds
MSB value of Ta
Unit of Ta in SBM1/SBM2
LSB value of Ta
MSB bits of 16 bits SBM2 threshold register
D[7:0] LSB bits of 16 bits SBM2 threshold register www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
13
14
Register Name
0F
(T
MOD_T
MC
_REG1
MC
Control Registers)
10
(T
MOD_T
MC
_REG2
MC
Control Register)
NOM_I
TH
_REG1 11
12 NOM_I
TH
_REG2
Analog Control Registers
PGA_CTL_REG
(PGA Control Registers)
POR Value R/W
0000_0000 R/W
0000_0000 R/W
0000_0000 R/W
0000_0000 R/W
D[7:0]
D[7:0]
D[7:0]
D[7:0]
8-bit Control / Status Data
MSB value of number of data samples to be dropped from ADC before sending Interrupt in NOM2
LSB value of number of data samples to be dropped from ADC before sending Interrupt in NOM2
Eight MSB bits of NOM2 current threshold register
Eight LSB bits of NOM2 current threshold register
0101_0000 R/W
D[7:6]
D[5:4]
D[3:0]
Setting of Gain G of Current Channel PGA. Default is
01 (G = 25)
00
01
5
25
10
11
40
100
Setting of Gain G in Voltage channel. Default is 01 (G =
25)
10
11
00
01
40
100
Reserved
5
25
PD_CTL_REG_1
(Power Down Control Register)
1100_1111 R/W
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
1
0
1
0
1
0
1
0
1
0
1
Disable Chopper clock to Current channel
Enable Chopper clock to Current channel
Disable Chopper clock to Voltage channel
Enable Chopper clock to Voltage channel
Reserved
Reserved
Disable Current channel PGA
Enable Current channel PGA
Disable Current channel
ΣΔ
Modulator
Enable Current channel
ΣΔ
Modulator
Disable Voltage channel PGA
Enable Voltage channel PGA
Disable Voltage channel
ΣΔ
Modulator
Enable Voltage channel
ΣΔ
Modulator www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
Register Name
15
POR Value R/W
D[7]
D[6]
D[5]
D[4]
PD_CTL_REG_2
(Power Down Control Register)
1111_0011 R/W
D[3]
16
PD_CTL_REG_3
(Power Down Control Register)
1111_1000
D[2]
D[1]
D[0]
D[7]
D[6]
D[2]
D[1]
D[0]
D[5]
D[4]
D[3]
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
8-bit Control / Status Data
Disable CIC1 of both channels
Enable CIC1 of both channels
Disable CIC2 of both channels
Enable CIC2 of both channels
Disable Dechopper in both channels
Enable Dechopper in both channels
Disable FIR in both channels
Enable FIR in both channels
Do not bypass PGA in Current Channel
Default 0
Bypass PGA in Current Channel
Do not bypass PGA in Voltage Channel
Default 0
Bypass PGA in Voltage Channel
Disable Current Channel Chopper
Enable Current Channel Chopper
Disable Voltage Channel Chopper
Enable Voltage Channel Chopper
Disable Common Mode Reference
Enable Common Mode Reference
Disable Internal Current Source
Enable Internal Current Source
Disable Internal temperature sensor
Enable Internal temperature sensor
Reserved. (Default 1) Do not change
Reserved. (Default 1) Do not change
Data Output in binary numbering system
Data Output in 2’s complement numbering system
Reserved. (Default 0) Do not change
Reserved www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
17
18
19
44
Register Name
ACH_CTL_REG
(Analog Channel Selection
Register)
ISC_CTL_REG
(Current Source Setting Register)
OTP_EN_REG
STATUS_REG_2
POR Value R/W
0000_0000
0000_0000 R/W
0000_0000 R/W
0000_0000
R/W
R
8-bit Control / Status Data
D[7:6]
D[5]
These bits specify the selection of voltage/temperature in Voltage Channel
Default is 00 (Voltage Channel)
00
01
Voltage Channel
External Temperature Channel ETR
10
11
External Temperature Channel ETS
Internal Temperature Channel
Reserved. (Default 0) Do not change
Internal current source switch enable. Default is 0
D[2:0]
D[7]
D[6:0]
D[7]
D[6]
D[5:0]
D[4]
Note:
D4 bit is used for Enabling current source to the channel selected by bits D[7,6] of this register.
0
1
Disabled
Enabled
Enable/disable Internal current source to RSHH pin of
Current channel
D[3]
0
1
Disabled
Enabled
Enable/disable current source switch to RSHL pin of
Current channel
D[2]
0
1
Disabled
Enabled
D[1:0] Reserved
These three bits specify the selection of magnitude of current from the Internal current source. Default is
00000 (0µA).
D[7:3]
00000
00001
00010
00100
01000
10000
11111
0µA
8.5µA
17µA
34.5µA
68µA
135µA
270µA
Reserved
1 Reserved (default = 1) Do not change
Reserved
Status indicating data saturation in Current channel
Status indicating data saturation in Voltage channel
Reserved www.ams.com/AS8510 Revision 3.8
37 - 48
AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
Register Name POR Value
Digital Signal path control registers for Voltage Channel
R/W
45 DEC_REG_R1_V
8-bit Control / Status Data
0100_ 0101 R/W
D[7]
D[6:5]
D[4:1]
D[0]
10
11
00
01
Selection of Decimation ratio for Voltage/Temperature channel.
Default is 0 (Down Sampling Rate is 64)
0
1
Down Sampling Rate is 64
Down Sampling Rate is 128
Division of oversampling clock, which is used as
Chopper Clock. Default is 10 (divide by 512)
Chopper Clock Always High
Divide by 256
Divide by 512
Divide by 1024
0011
0100
0101
0110
Decimation ratio of CIC2. Default is 0010 (4)
0000 1
0001
0010
2
4
8
16
32
64
1011
1100
1101
1110
0111
1000
1001
1010
128
256
512
1024
2048
4096
8192
16384
1111 32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
0
1
Unmasked
Masked www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 33. Control Registers
Addr in
HEX
46
47
Register Name
DEC_REG_R2_V
FIR CTL_REG_V
POR Value R/W
0000_0100
0000_0000
R/W
R/W
8-bit Control / Status Data
D[7:5]
D[4]
Reserved
Interrupt Mask Control for Voltage channel data Ready
Interrupt on INT pin (Default is 0)
0
1
Unmasked
Masked
These two bits select the source of output 16-bit data in
Normal mode from Voltage channel. Default is 01
D[3:2]
D[1:0]
10
11
00
01
FIR / MA Output
CIC2 Output
Dechop/Demod Output
CIC Output
Reserved
This bit selects FIR / MA Filter in Voltage channel.
Default is 0 (FIR)
D[7]
D[6:3]
0
1
FIR
MA Filter
These bits select the number of data samples for averaging in MA filter in Voltage channel.
Default is 0000 (bypass)
0000 bypass
0001 1
0011
0111
3
7
1111
D[2:0] Reserved
15
Note:
All the registers from address 0x19 to 0x2C are read-only.
There is an OTP test lock bit set by factory which locks the write access to all the test registers from 0x1A to 0x2C.
www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.9.1 Standby Mode - Power Consumption
In Standby Mode 1 there is a timer based accurate measurement every Ta seconds. The device itself stays in idle-mode as long as it does not get a different command from the SPI interface. Internal oscillator frequency is typically foscint=262 kHz to reduce power consumption as long as the timer runs. After every time out of Ta secs, it performs accurate measurement of current, voltage/ temperature. Data ready is signaled to microcontroller through an interrupt signal on INT and goes into STOP state.
In the SBM the following equations hold:
T sbm1
= Ta= 10s (default value is 10secs); the power consumption is valid for this setting. This is the period of the repetition rate in SBM 1 and SBM2.
T sett
≈ 2ms (depending on external capacitors). This is the time required by the analog part to settle when the new measuring period is started. Any measurements performed during T sett
produce invalid results.
T1 = 3ms (by default setting, every third measurement is sent to microcontroller in the SBM mode 1) is the time needed to perform the first measurement.
T meas
=T sett
+T1 is the total active time needed to get a valid result.
DR
SBM
= T meas
/T sbm
≈ 5ms/10s. This is the ratio of repetition time versus the active time (Device in NOM mode).
Power consumption = (DR
SBM
*NOM mode power consumption) + ((10s-5ms)/10s)*Stop mode power consumption)
7.9.2 Initialization Sequence at Power ON
Figure 17. AS8510 Device Initialization Sequence at Power ON
V
PORHID
/V
PORHIA
DVDD/AVDD
POR_N
INT
CHOP_CLK
Channel Data
Register
Start
ADC
1.5mS
500µS
Configure
Device
D1
T
ADC
D2
D3 D4
D1 D2
D3 D4
D1 D2
D3 D4
0x0000
DATA1
T
DATA_STATUS_RD
T
DATA_VALID
T
DATA_INVALID
DATA2
Device initialization starts if the DVDD and AVDD supplies are switched ON and DVDD > V
PORHID
. The duration period of Initialization is 500 μ sec and during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and activation should be carried out only after the initialization period.
On ADC start, device enters into analog stabilization state and takes 1.5msec for oscillator and Reference to settle. After this 1.5msec period, the first interrupt will occur after a time period of T
ADC
.
T
DATA
_
STATUS
_
RD
is the time period during which the micro-controller should complete reading of data and status from the device. If reading is carried out beyond this time period, then, ADC performance will degrade for next sample generation. Status register gets cleared automatically only when micro-controller reads this register. Data in the channel registers is changed after T
DATA
_
VALID
duration. Ensure that data channel registers and status registers are not read during the T
DATA
_
INVALID duration.
www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Example:
Configuration registers are set as follows:
CLK_REG = 8’b0010_0000
DEC_REG_R1_I = 0100_0101
DEC_REG_R2_I = 1100_0101
FIR_CTL_REG_I = 0000_0100
ADC is configured to a data rate of 1KHz, CHOP_CLK to 2KHz, and Modulator clock to 1MHz, Decimation ratio of CIC1 = 64, and Decimation
T
DATA
_
STATUS
_
RD
= 100 μ sec
(T
DATA
_
STATUS
_
RD
= (1/mod_clk) * R1 * [((mod_clk/(2*chop_clk))*(1/R1)) - 2.5)
T
DATA
_
INVALID
= 8 μ sec
T
ADC
= 1msec
T
DATA
_
VALID
= T
ADC
- T
DATA
_
INVALID
= 1msec - 8 μ sec
CHOP_CLK and POR_N are internal signals of the device.
DATA
_
STATUS
_
RD
and
T
ADC
.
Table 34. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1
Modulator Clock
1.024MHz
2.048MHz
Chopper Frequency
CHOP_CLK
2KHz
2KHz
Decimation Ratio R1
64
64
T
DATA
_
STATUS
_
RD
1usec * 64 * [4 - 2.5] = 96usec
0.5usec * 64 * [8 - 2.5] = 176usec
T
ADC
R2/(2*CHOP_CLK) for R2=4
1mSec
1mSec
2.048MHz
2KHz 128
0.5usec * 128 * [4 - 2.5] = 96usec
1mSec
2.048MHz
4KHz 64
0.5usec * 64 * [4 - 2.5] = 48usec
0.5mSec
7.9.3 Soft-reset of Device Using Bit D[7] of Reset Register 0x09
It is possible to soft-reset the device by writing “0” into D[7] bit of Reset Register at 0x09. On applying soft-reset, the device enters into initialization state and D[6] bit changes back to “1”. The duration period of Initialization is 500 μ sec, and, during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and
soft-reset.
www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 18. AS8510 Device Initialization Sequence at Soft-reset
Start
ADC
1.5mS
INT
D4
D1 D2
D3 D4
CHOP_CLK
Channel Data
Register
DATA-N
T
DATA_STATUS_RD
T
DATA_VALID
D1
500µS
Soft Reset
Using D7
Re-Configure
Device
DATA-N+1
T
DATA_INVALID
0x0000
D1 D2 D
3
D4 D1 D2 D3 D4 D1 D2 D3 D4
DATA1
T
DATA_STATUS_RD
T
DATA_VALID
T
DATA_INVALID
DATA2
7.9.4 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09
Measurement path also can be reset by using D[6] bit of Reset Register at 0x09. On applying soft-reset only signal measurement path registers will be reset. For applying this reset, device should be in STOP state. If the device is working with external clock, at the time of soft-reset the clock needs to be disabled.
7.9.5 Reconfiguring Gain Setting of PGA
Only PGA gain settings can be changed dynamically while ADC conversions are in progress. When PGA gain settings are changed, the first sample from the ADC is invalid. Ignore the first interrupt after the gain re-configuration. Valid data starts from the second interrupt onwards.
Figure 19. AS8510 - Re-configuration of Gain Setting of PGA
Read Channel data in this slot
T
DATA_STATUS_RD
Gain Re-Configuration can be carried out in this slot, skip next interrupt and Channel Data.
INT
CHOP_CLK
Channel Data
Register
D4
D1 D2
D3 D4
D1
DATA-N
T
DATA_STATUS_RD
T
DATA_VALID
T
DATA_INVALID
DATA-N+1
D2
D3 D4
D1 D2
T
DATA_STATUS_RD
DATA1
T
DATA_VALID
D3
VALID
DATA
D4
D1
T
DATA_INVALID
D2
DATA2
D3 D4 www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.9.6 Configuring the Device During Normal Mode
Following registers can be programmed dynamically when the device is in operational mode (Normal mode).
ACH_CTL_REG address is 0x17 for channel selection on the voltage measurement path
PGA_CTL_REG address is 0x13 for gain setting
PD_CTL_REG2 address is 0x15 for PGA Bypass
ISC_CTL_REG address is 0x18 for current source programmability
During the operation (Normal mode) of the device, if any of the registers need to be programmed or changed other than the above mentioned registers, then it is required to STOP the device by writing into MOD_CTL_REG “STOP” bit and configure the device as per the requirements and start the device.
7.10 Low Side Current Measurement Application
Figure 20. Application Diagram
100nF
100nF
+12V
481 R
R
RSHH
RSHL
REF
VCM
3.3V
1µF
AVDD
AVSS
ETR
ETS
VBAT_IN
VBAT_GND
AS8510
20 pin
(SSOP20)
INT
CLK
SDI
MEN
CHOP_CLK
DVDD
DVSS
SDO
SCLK
CS
3.3V
+
12V
Battery
-
100 µohm
Load
µC
Note
: On ETR connect constant resistor (temp co = 0)
On ETS connect Temperature sensor (use sensor resistor more than 10K)
1µF www.ams.com/AS8510 Revision 3.8
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AS8510
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
8 Package Drawings and Markings
The product is available in a 20-pin SSOP package.
Figure 21. Drawings and Dimensions
AS8510 @
YYWWMZZ
18320
Symbol Min
L1
L2 e
L
R
θ
N c
D
E
E1
A
A1
A2 b
-
0.55
-
-
0.09
0º
0.09
6.90
7.40
5.00
-
0.05
1.65
0.22
Nom
0.65 BSC
0.75
1.25 REF
0.25 BSC
-
4º
20
-
7.20
7.80
5.30
-
-
1.75
-
Max
-
0.95
-
-
-
8º
0.25
7.50
8.20
5.60
2.00
-
1.85
0.38
Notes:
1. Dimensions & tolerancing conform to
ASME Y14.5M-1994
.
2. All dimensions are in millimeters. Angles are in degrees.
www.ams.com/AS8510 Revision 3.8
RoHS
Green
44 - 48
AS8510
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Marking: @YYWWMZZ.
@ YY WW
Sublot Identifier Last two digits of the current year Manufacturing Week
8.1 Recommended PCB Footprint
Figure 22. PCB Footprint
M
Assembly Plant Identifier
ZZ
Letters of free choice
Recommended Footprint Data
Symbol
A
D
E
B
C
mm
9.02
6.16
0.46
0.65
6.31
www.ams.com/AS8510 Revision 3.8
45 - 48
AS8510
Datasheet - R e v i s i o n H i s t o r y
Revision History
Revision
1.1
1.2
1.3
2.0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Date
Jun 22, 2009
Dec 02, 2009
Dec 08, 2009
Feb 19, 2010
June 01, 2010
Oct 29, 2010
Nov 02, 2010
Nov 14, 2010
Nov 26, 2010
Dec 03, 2010
Mar 01, 2011
Aug 05, 2011
Dec 31, 2012
Feb 07, 2013
Feb 27, 2014
Description
Initial version
Updated the datasheet according to 1.8 specification
Following modifications carried out in
1) Deleted Max value for parameter ‘Temperature upper limit’
2) Added Footnote 2
3) Added new parameter ‘Temperature Sensor Output (without gain calibration)
with PGA information
Updated Voltage Measurement
Updated V
REF and V
IN
values in
REF
Inserted new
Table 28 - System Measurement Error Budget
Changed the pin name AGND to VCM
Current source added in the block diagram
Added application diagram
Updated Electrical Characteristics on page 7
Updated Detailed System and Block Specifications on page 9
Updated Standby Mode - Power Consumption on page 40
Updates carried out across the datasheet
Updated Ref Voltage Offset in
Added sections 7.9.2, 7.9.3, 7.9.5
Formatted figures 17, 18 in portrait mode. Index modified from page 39
Added
Configuring the Device During Normal Mode on page 43
Updated General Description , Key Features , Applications ,
, Differential Input Amplifier for Current Channel
Amplifier for Voltage Channel ,
Sigma Delta Analog to Digital Converter , Bandgap
System Measurement Error Budget for Gains 5 and 25
. Deleted Voltage Measurement.
Updated ordering table
Additional information added to System Specifications
section.
, description of Figure 4 , note of
,
and its description.
Note:
Typos may not be explicitly mentioned under revision history.
www.ams.com/AS8510 Revision 3.8
46 - 48
AS8510
Datasheet - O r d e r i n g I n f o r m a t i o n
9 Ordering Information
The devices are available as the standard products shown in Table 35 .
Table 35. Ordering Information
Ordering Code
AS8510-ASSP
AS8510-ASSM
Description
Data Acquisition Device for Battery Sensors
Data Acquisition Device for Battery Sensors
Delivery Form
Tape and Reel (2000 pcs)
Tape and Reel (500 pcs)
Note:
All products are RoHS compliant and ams green.
Buy our products or get free samples online at www.ams.com/ICdirect
Technical Support is available at www.ams.com/Technical-Support
For further information and requests, e-mail us at [email protected]
For sales offices, distributors and representatives, please visit www.ams.com/contact
Package
20-pin SSOP
20-pin SSOP www.ams.com/AS8510 Revision 3.8
47 - 48
AS8510
Datasheet - C o p y r i g h t s & D i s c l a i m e r
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
Contact Information:
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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