AMS AS8515 Datasheet
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AS8515
Data Acquisition System with Power Management and LIN Transceiver for 12V Battery Sensor Applications
1 General Description
Internal temperature sensor
Synchronous acquisition for both ADC channels
The AS8515 is designed for simultaneous measurement of shunt current sensor signal and battery voltage by two independent ADC channels. Both channels can measure small signals up to ±219 mV versus ground through programmable gain amplifier or larger signals in the 1V range without amplifier. After analog to digital conversion and digital filtering, the resulting digital values are accessible through
4-wire serial interface. The device is powered directly from the battery through LDO and provides a 3.3V supply for an external microcontroller. For communication with the next level ECU, the device offers a LIN 2.1 transceiver. Measurement of battery voltage is supported through resistive attenuator with disable for power saving in standby.
Reference-voltage source (high precision and high stability)
Offset auto zero architecture on both channels
Current monitoring comparator with interrupt signal generation and µC clock enable. Timer with 2 related outputs for single shot sampling of current and voltage channel in low power mode.
Precision on chip RC oscillator or external clock. Low slew, low
EMC clock output which can be used by external microcontroller which is enabled respectively disabled by mode control through SPI and interrupt from current monitor in low power mode.
The device is a stacked die system providing a high voltage CMOS
IC for power management and transceiver functions as a
Top die
and low voltage sensor interface functions as a
Bottom die
inside a 32-pin MLF (5x5 mm) package.
The integrated circuit can execute measurements with internal and external sensors and sources for the voltage channel and with external sensor for the current channel.
External Sensors:
Current measurement via Shunt resistor (4 ranges)
Battery voltage (internal voltage divider to battery)
ETR and ETS for external temperature sensor (with switchable current source)
2 Key Features
A precision voltage attenuator with power down facility
LIN 2.1 transceiver
Power-On Reset with programmable reset timeout and brownout detection through factory setting
A window Watchdog function in the normal mode and a timeout
Watchdog in the device standby mode as a factory option
Load dump protection (42V) for all battery supplied pins and
Enable pin
Internal reverse polarity protection (up to -27V) for all batterysensing pins, and LIN bus pin
Over temperature warning & shutdown functions
Two independent high resolution A/D converters with programmable over sampling ratio
Programmable sampling rate up to 4kHz throughput
Programmable gain, low noise amplifier for current channel with gain stages 5, 25, 40, 100
Internal Sensors:
On chip temperature sensor
Internal current sources for functional test of measurement path and the connection of shunt resistor
3 Applications
The AS8515 is suitable for battery sensors, having shunt current sensor at minus pole. For lead acid, Li-Ion batteries up to 18V nominal, 42V over voltage capability.
The device is also ideal as a general purpose sensor interface for automotive LIN slaves.
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AS8515
Datasheet (discontinued) - A p p l i c a t i o n s
Figure 1. AS8515 Block Diagram
VSUP
RSHH
RSHL
VSENSE
VSENSE_IN
VSENSE_GND
LIN
POR_VSUP
LDO
VCC
AS8515
POR_VCC
MEN DVDD
AVDD
Voltage Channel
Multiplexer,
Current Source
To voltage
Channel ADC
Low
Precision
Clock Logic
High
Precision
Clock
CHOP_CLK
CLK
PGA
Current Channel ADC
DEC
Temperature
Sensor
PGA
Voltage Channel ADC
DEC
LIN
SPI,
Diagnosis,
WWD
Reference
Generator
, ator,
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AS8515
Datasheet (discontinued) - C o n t e n t s
Contents
5
8
8
10
11
12
12
12
13
13
14
16
17
18
19
20
21
24
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Datasheet (discontinued) - C o n t e n t s
26
28
28
29
29
29
29
30
33
36
8.9.1 Current Measurement Ranges (across 100µ
Ω (±5%) shunt resistor)...................................................................................... 36
44
48
12 Ordering Information.............................................................................................................................................................
64
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AS8515
Datasheet (discontinued) - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
RSHH
32
EN
31
RESET
30
Rx
29
Tx
28
CST
27
INT
26 25
RSHL 1
VREF
2
VCM
3
AVDD
4
AVSS
5
ETR
6
ETS
7
VSENSE_IN
8
AS8515
9
VSENSE_GND
10
LIN
11 12 13
VSS
VSENSE VSUP
14 15
VCC
16
CSB
24 CLK
23 SDI
22
MEN
21
CHOP_CLK
20 DVDD
19
DVSS
18 SDO
17
SCLK
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name
RSHL
Pin Number
1
VREF 2
3 VCM
AVDD
1
AVSS
2
4
5
Pin Type
Analog input
Analog output
Analog output
Analog input
Power supply
Description
Negative differential input for current channel
Internal reference voltage to Sigma Delta ADC;
Connect 100nF to AVSS from this pin.
Common mode voltage to the internal measurement path;
Connect 100nF to AVSS from this pin.
+3.3V Power-supply; Supplied by LDO output (VCC) in
Top die
;
Should be shorted to pin 21 (VCC) externally.
0V Power-supply Ground analog www.ams.com
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Datasheet (discontinued) - P i n A s s i g n m e n t s
Table 1. Pin Descriptions
Pin Name
ETR
ETS
VSENSE_IN
VSENSE_GND
LIN
VSENSE
VSUP
-
CSB
SCLK
SDO
DVSS
CHOP_CLK
MEN
SDI
CLK
-
INT
CST
Tx
Rx
RESET
EN
RSHH
Pin Number
6
7
8
9
10
11
12
20
21
13
14
15
16
17
18
19
22
23
24
25
26
27
28
29
30
31
32
Pin Type
Analog input
Analog I/O
Analog input
Analog I/O
Power supply
Analog input
Power supply
-
Analog output
Digital input
Digital input
Digital output
Power supply
Analog input
Digital output
Digital I/O
Digital input
Digital I/O
-
Digital output
Digital input
Digital input
Digital output
Digital output
Digital input
Analog input
-
Description
Voltage channel single ended input
Battery voltage attenuator output and voltage channel input
Input signal for voltage channel (low)
LIN BUS
0V Power-supply Ground analog
-
Battery voltage input
Connect 100nF to VSS from this pin.
Supply input from battery (through external reverse polarity protection device)
Regulated 3.3V output supply for loads up to 50mA
Chip select for
Bottom die
Clock signal SPI
Data signal SDO
0V Power-supply digital
+3.3V Power-supply; Supplied by LDO output (VCC) in
Top die
;
Should be shorted to pin 21(VCC) externally.
Chopper clock
Digital output for
Bottom die
in SBM mode
3
and input for
Top die
Data signal SDI
Internal/External digital clock signal
Interrupt not: Wake-up, digital interrupt, ready flag 2
Chip select for
Top die
LIN transceiver transmit pin
LIN transceiver receive pin
Reset output (open drain)
Enable input
Positive differential input for current channel
1. Pin #4, pin #20 and pin #15 needs to be shorted externally on the board. Pin #21 is the LDO output that supplies pin #4 and pin #20.
2. Pin #5, pin #11 and pin #19 needs to be shorted externally on the board as they are the grounds.
3. Use as output port only.
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Datasheet (discontinued) - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2
may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
Electrical Characteristics on page 8 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
Electrical Parameters
VSUP
VSENSE
Parameter
Supply voltages
Battery voltage inputs
AVDD,
DVDD
EN
DC supply voltage
Enable input
Min
-0.3
-27
-0.3
-0.3
Typ Max
42
42
5
42
Units
V
V
V
V
Comments
VCC Regulated output supplies -0.3
5 V
VCC generated by than 5V on board level as it has to be connected with
Top die
must not be larger
Bottom die
AVDD and AVCC
LIN LIN bus
Analog & digital inputs and outputs
Input current (latch-up immunity)
Electrostatic Discharge
-27
-0.3
-100
40
5
100
V
V mA Norm: AEC-Q100-004
ESD
Electrostatic discharge
Norm: AEC-Q100-002
±6
±4
±2 kV kV kV
LIN, VSS
VSUP, VSENSE
All other pins
Continuous Power Dissipation
P tot
1
Total operating power dissipation
(all supplies and outputs)
0.375
W
MLF-32 in still air, soldered on JEDEC standard board @125º ambient, static operation = no time limit
Temperature Ranges and Storage Conditions
R
Θ
T stg
T
J
Package thermal resistance
Storage temperature
Junction temperature
-55
34 40
150
130
ºC/W
ºC
ºC
T
BODY
Package body temperature 260 ºC
The reflow peak soldering temperature (body temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin (100% Sn).
MSL
Humidity non-condensing
Moisture Sensitive Level
5
3
85 %
Represents a maximum floor time of 168h
1. Total power dissipation cannot exceed 0.375W to avoid increase in junction temperature, i.e. greater than 130ºC. VCC LDO can supply current externally, which is not greater than 17mA at 18V VSUP and 20mA at 16V VSUP.
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Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
Unless otherwise noted in this specification, all defined tolerances of parameters are assured over the whole operation conditions range and also over lifetime.
6.1 Operating Conditions
Table 3. Operating Conditions
Symbol
V
SUP
V
SENSE
AVDD
AVSS
DVDD
DVSS
LIN
EN
VCC
T
AMB
I
SUP
1
Parameter
Supply voltages
Battery voltage input
Positive supply voltage
Negative supply voltage
Positive digital supply voltage
Negative digital supply voltage
LIN bus
Enable input
Regulated output supply
Ambient temperature
Supply current f
CLK
System clock frequency
Min
4.3
4.5
3.15
0
3.15
0
0
0
3.15
-40
Typ
18
18
3.45
115
27
Max
18
18
3.45
V
3.45
V
ºC
V
V
V
V mA
Unit
V
V
V
Note
Referring to DVSS, Typical ± 10%
Maximum junction temperature (T
J
) is 130ºC
8.192
MHz
When external clock is selected, internal clock will be 4.096 MHz
1. Total power dissipation cannot exceed 0.375W to avoid increase in junction temperature, i.e. greater than 130ºC. VCC LDO can supply current externally, which is not greater than 17mA at 18V VSUP and 20mA at 16V VSUP.
6.2 DC/AC Characteristics for Digital Inputs and Outputs
All pull-up, pull-downs have been implemented with active devices. SDO have been measured with 10pF load.
INT Output.
Table 4. INT
Symbol
V
OH
V
OL
I
O
Parameter
High level output voltage
Low level output voltage
Output current
Condition Min
2.5
CST, CSB, TxD.
Table 5. CST, CSB
Symbol
V
IH
V
IL
I
LEAK
I
PU
Parameter
High level input voltage
Low level input voltage
Input leakage current
Pull-up current
Condition
Pulled to GND
Min
0.8*VCC
-1
-150
Typ Max
0.4
4
Typ Max
0.2*VCC
+1
-10
Unit
V
V
µA
µA
Unit
V
V mA www.ams.com
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Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
SDI, SCLK.
Table 6. SDI, SCLK
Symbol
V
IH
V
IL
I
LEAK
Parameter
High level input voltage
Low level input voltage
Input leakage current
SDO Output.
Table 7. SDO
Symbol
V
OH
V
OL
I
O
Parameter
High level output voltage
Low level output voltage
Output current
CHOP_CLK Output.
Table 8. CHOP_CLK
Symbol
V
OH
V
OL
I
O
Parameter
High level output voltage
Low level output voltage
Output current
EN Input.
Table 9. EN
Symbol
V
IH
V
IL
I
LEAK
I pd_en
Parameter
High level input voltage
Low level input voltage
Input leakage current
Pull-down current
CLK I/O.
Table 10. CLK I/O
Symbol
V
IH
V
IL
I
LEAK
I
PD_EN
I
O
V
OH
V
OL
Parameter
High level input voltage
Low level input voltage
Input leakage current
Pull-down current
Output current
High level output voltage
Low level output voltage
Condition
Condition
Min
0.8*VCC
Typ
-1
Max
0.2*VCC
+1
Unit
V
V
µA
Min
2.5
Typ Max
0.4
4
Unit
V
V mA
Conditions Min
2.5
Typ Max
0.4
4
Units
V
V mA
Conditions
EN = VSS
Pulled up to VCC
Condition
Min
0.8*VCC
Typ
-1
30
Max
0.2*VCC
+1
100
Units
V
V
µA
µA
Min
2.4
-1
10
2.5
Typ Max
1
+1
100
4
0.4
Unit
V
V
µA
µA mA
V
V www.ams.com
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Datasheet (discontinued) - E l e c t r i c a l C h a r a c t e r i s t i c s
MEN Output.
Table 11. MEN
Symbol
V
OH
V
OL
I
O
Rx Output.
Table 12. Rx
Symbol
V
OH
V
OL
I
O
I pu_reset
RESET Output.
Table 13. RESET
Symbol
V
OH
V
OL
I
O
6.3 System Specifications
Table 14. System Specifications
Symbol Parameter
Ivsupnom
Ivsupstdby
Parameter
High level output voltage
Low level output voltage
Output current
Parameter
High level output voltage
Low level output voltage
Output Current
Pull-up current
Parameter
High level output voltage
Low level output voltage
Output current
Current consumption in normal mode
Current consumption standby
Conditions
Conditions
Pulled down to VSS
Conditions
Open Drain Pull-down
Min
2.5
Min
VCC-0.5
-30
Min
2.5
Condition
No load on VCC, LIN bus in dominant state
No load on VCC,
LIN bus in recessive state
Min
Typ
Typ Max
VSS+0.4
1
-100
Units
V
V mA
µA
Typ
Typ
80
Max
0.4
2
Max
0.4
8
Max
7
Units
V
V mA
Units
V
V mA
Unit
mA
µA
Note:
Stand by mode power consumption is sum of stop mode power consumption and average of normal mode power consumption over a period of 2s (NOM1 time of device is low in Standby mode).
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Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
7 AS8515 Top Die Overview
The AS8515
Top die
consists of a resistive divider, a low dropout regulator, and a LIN bus transceiver. Additionally integrated are a RESET unit with a power-on-reset delay, programmable window watchdog and timeout watchdog timers as a factory programming option. It also includes a watchdog timeout on LIN Tx node to indicate if the Microcontroller is stuck in a loop and the LIN bus remains in dominant time for more than the necessary time.
7.1 Voltage Attenuator
A resistive divider is used as a battery voltage attenuator. Like the amplifier, the attenuator can be enabled or disabled through SPI, and in the device standby mode, we additionally need logic high on MEN pin for enabling. Internal reverse polarity protection is provided for VSENSE pin.
Figure 3. Attenuator Implementation
VSENSE
PD
VSENSE_IN
VSENSE_GND
7.2 Voltage Regulators (LDO)
The device has a low-dropout voltage regulator named LDO, 3.3V voltage outputs. The output of the LDO is VCC. The regulator is always ON except when the device enters the over-temperature shutdown.
The regulator has in-built short-circuit current limitation feature. The regulator can be temporarily shut down for hard reset of the external circuitry by configuring the device to temporary shutdown mode through SPI.
The LDO power-up happens when the POR-VSUP event occurs (RESET_VSUP_N switching from low to high). The LDO will be switched off if there is an under voltage on VCC, that is, when RESET_VCC_N switches back to low.
7.3 LIN Transceiver
The device has a LIN transceiver with slew-controlled bus driver for controlling the electromagnetic emissions from the LIN bus. Further, the slew rate is independent of the bus load. The transmitter relays the data from the LIN controller (Tx pin) to the bus (LIN pin), and the receiver provides the data on the bus to the controller (Rx pin). The transceiver conforms to the LIN 2.1 standard.
The LIN transceiver has a timeout watchdog for Tx. After the timeout, the LIN bus will be released to the recessive state from the dominant state.
The bus driver has an in-built short-circuit current limitation facility to protect the device from damage when there is a short between the bus and the supply. In addition to the data receiver, there is a low-power receiver active in the device standby mode which received a wake-up event from the LIN bus to bring the device to normal mode.
7.4 Temperature Monitor/Limiter
The temperature limiter circuit powers down the device when the junction temperature exceeds 170°C (nominal). It also issues an overtemperature warning at 160°C (nominal). The device is powered up again when the junction temperature falls below 140°C (nominal). The overtemperature warning flag is also cleared at this temperature.
The temperature limiter circuit can be optionally disabled through SPI.
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7.5 VSUP Under-voltage Reset
When VSUP drops below VSUVR_ON, the RESET_VSUP_N switches back to low level. This is treated as a master reset and will have the highest priority over all other signals. In this case, the regulators, LIN transceiver, and all other blocks are shut off, and the device comes to a complete stop. The device returns to the normal mode when VSUP rises over VSUVR_OFF again irrespective of the mode it was in prior to this under-voltage condition.
7.6 Reset
RESET module generates an active-low reset signal for the external circuitry supplied by VCC. The behavior of the reset output is depicted in
detail in the subsequent sections.
The reset period can be one-time programmed to 4, 16 and 32 ms with a default value of 8 ms.
Figure 4. Reset Functionality
VSUP
VCC
VUVR_OFF
VUVR_ON t
Res
RESET
T>Tj T<Tj t
rr
t
Res
Start-up
Over-temp
Shutdown
t<t
rr
Glitch in
VSUP
t
Res
t
Res
t
Res
VSUP UV
Reset by
Watchdog
SC Current
Limitation Active
7.7 VCC Under-voltage Reset
When VCC drops below VUVR_ON, the RESET_VCC_N switches back to low level. This event generates a reset output. The reset output is released again only a reset period (t
Res
) later after VCC rises above VUVR_OFF. If the time difference between the VCC falling below VUVR_ON and rising above VUVR_OFF is less than t rr
, there will be no reset output. The reset output is affected in the conditions like over-temperature shutdown and temporary shutdown only through VCC under voltage. www.ams.com
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7.8 Window Watchdog (WWD)
The Window Watchdog ensures that the Microcontroller is properly functioning in the normal mode of the device. The Watchdog is started after a reset and the Microcontroller needs to send a trigger in the window of WD_TSV (service time). If the trigger occurs early, in the period WD_TCL, or after WD_TSV, a reset output is generated.
The Microcontroller can access the trigger bit for the watchdog through SPI. The WWD can be enabled and the window times can be programmed through factory setting and enabled as a factory option.
Figure 5. Window Watchdog Functionality
Trigger via SPI
Period
Non-Service time (WD_TCL)
50 %
Trigger restart period
Service time (WD_TSV)
100 %
Last trigger
Wrong trigger
(RESET generation)
Earliest point for correct trigger
(No RESET)
Correct trigger
(No RESET)
Latest point for correct trigger
(No RESET)
Wrong trigger
(RESET generation)
7.9 Timeout Watchdog (TWD)
The Timeout Watchdog ensures that the Microcontroller is in proper functional state in the device standby mode. The Watchdog timer will be started upon a rising edge on INT and will generate a reset output if the Microcontroller doesn’t send a trigger before the timeout.
The Microcontroller can access the trigger bit for the watchdog through SPI. The TWD can be enabled by factory setting and the timeout interval can be programmed through SPI.
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7.10 Modes of Operation
The AS8515
Top die
provides the following four main operating modes:
Normal Mode
Standby Mode
Temporary Shutdown Mode
Thermal Shutdown Mode
The LIN transceiver can be programmed to operate with lower slew in the normal mode. See
for a detailed state transition diagram. Soft states like “TxWD Wait”, “Standby Wait”, and other wait states have also been included in the state diagram for completeness.
Figure 6. Finite State Machine Model of AS8515 Top Die
OVTEMP
! temp170
INIT0
por_vsup
OTP LOAD
otp_load temp170 temp170
Temp Shut
128msec shutd
Temp own
RESET TIMEOUT
reset timeout
! por_vcc || wwdtimeout temp170 temp170 temp170 temp170 w m
STANDBY
Rwake / local wake
STANDBY WAIT
Standby & otp_mode
Sta ndb y & ode
~ot p_m
! sta ndb y
! por_vcc || stdby_timeout rw ak e_ wa it / loc al_ wa it
! por_vcc || wwdtimeout
Te m p s hu tdo wn
! por_vcc || stdby_timeout
NORMAL
TXWD WAIT
test_en
RX=0
RX=0 otp_e n
WAIT_TEST
WAIT_OTP www.ams.com
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Table 15. Transition Table
Transition
From Mode
Normal Mode
To Mode
Temporary
Shutdown
Over-
Temperature
Normal (LW)
LIN
X
Interface
Rx
Stand-By X-RS X-H
1
Tx
H
X
X
X
2
EN
H-L
H
X
L-H
Reg.
0x05
D0
Flags
Rwake U
VSENSE
OT
L
H
L
X
X
X
L X
X
X
X
X
U
VCC
Comments
inactive inactive inactive set set set inactive inactive
Tx is high for
T
STNDY_trigger
The Control Bit is set through the 4-Wire SPI interface
Temperature monitor output asserted
(covered by scan)
Normal (RW) X
H
X L set X
Standby Mode
Temporary
Shutdown
Over-
Temperature
Normal
RS
RS
H
H
X
L
L
X
H
L
L
X
X
X
X
X
X inactive set inactive set set clear
The Control bit is set through the 4-Wire SPI interface
Temperature monitor output asserted
(covered by scan)
Internal 128ms timer expired
Temporary
Shutdown
Mode
Overtemperature
Mode
All States
Normal
Power Off
X X
X
X
X
X
L
X
X
X
X
L-H
clear
X clear
X
Temperature monitor output de-asserted
(covered by scan)
1. Effect of transition
2. Cause for transition
Note:
L = Low state, H = High state, OT = Over temperature Reset, U
VCC
= Under-voltage VCC, U
VSENSE
= Under-voltage VSENSE,
Rwake = Remote wake, X = don’t care.
7.10.1 Normal Mode
This is the mode after the power-up. In this mode, voltage regulator, LIN transceiver, window Watchdog is all active. The resistive divider can be enabled through SPI. LIN transceiver is capable of sending the Tx data from microcontroller to the LIN bus at a maximum rate of 20Kbps.
7.10.2 Standby Mode
Standby Mode is a functional low power mode and is entered by pulling EN to ground. The LIN transceiver, resistive divider, window watchdog, and Tx timeout watchdog circuits are disabled. But, it is possible to selectively enable the voltage and current measurement paths in this mode using an externally generated measurement enable (MEN) signal on the MEN pin. The timeout Watchdog can be enabled in this mode to make sure that the Microcontroller is active.
7.10.3 Temporary Shutdown Mode
In this mode, the regulator is powered down and the VCC is pulled down. This provides an alternative way to reset those components powered by AS8515. The feature has to be enabled by the factory programming option and can be invoked through SPI. The LIN transceiver along with the LIN wake-up circuits are powered down. No remote wake functionality possible. LIN bus enters into recessive state. The system goes out of this mode to normal mode after the timeout of an internal timer.
7.10.4 Thermal Shutdown Mode
If the junction temperature T
J
is higher than T sd
, the device will be switched into the thermal shutdown mode. The regulator and the transceiver are completely disabled. Only the over-temperature monitor is active. As soon as the temperature returns back to T
RET
, the system enters normal mode.
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Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
7.11 Initialization
When the power supply is switched on, when VSUP > VSUVR_OFF, RESET_VSUP_N becomes high. This starts the regulator LDO with 3.3V and Vuvr_off option of 2.75V. When VCC > Vuvr_off (2.75V), active-low PORN_2_OTP is generated. The rising edge of PORN_2_OTP loads contents of fuse onto the factory setting latch after load access time T
Load
. LOAD_OTP_IN_PREREG signal loads contents of factory setting latch onto a register. This register provides the actual settings of LDO, Vuvr_off and Reset Timeout period T
Res
. This is done as the factory setting block is powered by the VCC. If VCC > Vuvr_off (phase 2), Reset timeout is restarted. RESET signal is de-asserted after Reset Timeout period T
Res
(phase 2) and then device enters into normal mode. The circuit also needs to initialize correctly for very slow ramp rates on VSUP (of the order of 0.5V/min).
Figure 7. Initialization Sequence
VSUP_POR_Threshold
VSUP
RESET_VSUP_N
LDO Off
Device Settings
PHASE 1
LDO On
VCC Por Threshold = 2.75V
LDO setting = 3.3V
Reset Timeout = 4msec
VCC_POR_Threshold
VCC
RESET_VCC_N
PORN_2_OT
P
LOAD_OTP_IN_PREREG
6 Cycles of
RC-Oscillator
RESET
PHASE 2
LDO On
VCC Por Threshold = from OTP Block
LDO setting = from OTP Block
Reset Timeout = from OTP Block
LDO settings to 5 V
LDO settings to 3.3 V
If Phase 1 POR threshold != Phase 2 POR threshold
Tres = Reset Timeout from OTP Block
If Phase 1 POR threshold == Phase 2 POR threshold
Tres = Reset Timeout from OTP Block
Table 16. VSUP>Vsuvr_on and VCC<Vuvr_on
Block
TRANSCEIVER=Enabled (disabled only during initial VSUP ramp-up)
LDO=Enabled (disabled only during initial ramp-up)
RESET BLOCK=Enabled
RESISTIVE DIVIDER=Enabled
Output Signal
LIN=high-z, Rx=follows VCC…
VCC=low…
RESET=high-z…
VSENSE=high…, VSENSE_DIV=enabled www.ams.com
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AS8515
Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
Table 17. VSUP<Vsuvr_on
Block
TRANSCEIVER=Disabled
LDO=Disabled
RESET BLOCK=Disabled
RESISTIVE DIVIDER=Disabled
Output Signal
LIN=high-z, Rx=high-z…
VCC=low
RESET=high-z
VSENSE=high, VSENSE_DIV=low
7.12 Wake-up
When the device enters standby mode, it can be brought back to the normal mode. A dominant state on the BUS for duration of t
WAKE
will result in the device wake-up which is termed as remote wake.
7.12.1 Remote Wake-up Event
In all low power modes of
Top die
, low power BUS receiver is ON. If BUS is in dominant state for longer than t
WAKE
then, remote wake is sensed on the BUS and REMOTE_WAKE_flag is set. Indication of wake-up is given to µC by setting a bit in interrupt register and giving interrupt on INTN pin.
Figure 8. Remote Wake-up Event
BUS
REMOTE_WAKE_flag
>T wake
Remote wake detected
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AS8515
Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
7.13 LIN BUS Transceiver
The AS8515 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed by a de-bouncing unit.
7.13.1 Transmit Mode
During transmission the data at the pin Tx will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit.
Transmitting will be interrupted in the following cases:
Thermal Shutdown active
Master Reset (VSUP < Vsuvr_on)
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS>VSUP). No additional termination resistor is necessary to use the
AS8515 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1k Ω resistor in series with a diode to VSENSE.
7.13.2 Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin Rx. Short spikes on the bus signal are suppressed by the implemented debouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely observed.
Figure 9. Receive Mode Impulse Diagram
BUS
60%
50%
40%
V thr_max
V thr_hys
V thr_cnt
V thr_min t < t deb_BUS
Rx
t < t deb_BUS www.ams.com
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AS8515
Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
7.14 Rx and Tx Interface
7.14.1 Input Tx
The 3.3V input Tx controls directly the BUS level. LIN Transmitter acts like a slew-controlled level shifter. A dominant state (low) on Tx leads to the LIN bus being pulled low (dominant state) too. The Tx pin has an internal active pull up connected to VCC. This guarantees that an open Tx pin generates a recessive BUS level.
Figure 10. Tx Interface
MCU
VCC
VCC
I
PU_TxD
Tx
RC-Filter
(10ns)
AS8515
7.14.2 Output Rx
The received BUS signal will be output to the Rx pin:
BUS < Vthr_cnt – 0.5 * Vthr_hys
→
Rx = low
BUS > Vthr_cnt + 0.5 * Vthr_hys → Rx = high
This output is a push-pull driver between VCC and GND with an output current of 1mA
Figure 11. Rx Interface
AS8515
VCC
Rx
MCU
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AS8515
Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
7.15 MODE Input EN
The AS8515
Top die
is switched from normal mode to the standby mode with a falling edge on EN and keeping Tx high for T
STNDY_trigger time.
Device is switched from standby mode to normal mode with a rising edge at the EN pin. The mode change for
Top die
with a falling edge on EN can be done independently from the state of the transceiver bus. This ensures the direct control of device to enter into standby mode by microcontroller using EN pin.
Figure 12. EN Pin Functionality
EN
Tx
T tx_su
Normal Mode
T
STNDY_trigger
T tx_hd
Standby/Sleep
Mode
Normal
Mode
The EN input has an internal active pull down to secure that if this pin is not connected, a low level will be generated.
Figure 13. Enable Interface
V
BAT
C
IN
+
EN
VSUP
LIN
VSS
VSENSE
VCC
RESET
Tx
Rx
C
LOAD
+
+3.3V
MCU
If the application doesn’t need the low-power modes of the device, a direct connection of EN to VCC is possible. In this case the
Top die
operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via VSUP signal as shown below.
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AS8515
Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
Figure 14. EN Connection for Permanent Normal Mode
V BAT
C IN
+
EN
VSUP
LIN
VSS
VCC
RESET
Tx
Rx
C
LOAD
+
+3.3V
MCU
7.16 Top Die Block Specifications
This section provides specification of design related key parameters.
7.16.1 Voltage Attenuator
Table 18. Voltage Attenuator
Symbol
RDIV
VSENSE
ε p,RDIV
Parameter
Division ratio
Input voltage range/
Battery voltage range
Ratio error
ε dt1,RDIV
ε dt2,RDIV
ε dv1,RDIV
ε dv2,RDIV
Ratio drift
(with reference to Temperature)
Ratio drift
(with reference to VSENSE)
Condition
At room temperature, VSENSE=12V
Temperature: -25 to +65º @VSENSE=12V
Maximum values will be added after device evaluation (to be guaranteed by evaluation)
Temperature: -40 to +125º @VSENSE=12V
Maximum values will be added after device evaluation (to be guaranteed by evaluation)
VSENSE: 11V to 13V @Temperature=27º
Maximum values will be added after device evaluation (to be guaranteed by evaluation)
VSENSE: 6V to 18V @Temperature=27º
Maximum values will be added after device evaluation (to be guaranteed by evaluation)
Min
4.5
Typ
21
12
±0.05
±0.2
±0.05
±0.2
Max
18
±1
Unit
V/V
V
%
%
% www.ams.com
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AS8515
Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
7.16.2 Voltage Regulator (LDO)
Table 19. Voltage Regulator
Symbol
V
SUP
VCC
I
LOAD
ICC_SH dVCC1
Parameter
Input Supply Voltage
Output Voltage Range
LDO Load Current
Output Short Circuit Current
Line Regulation
Load Regulation LOREG
CL1
ESR1
CL2
ESR2
CSUP1E
ESR1_CSUP
CSUP2C
ESR2_CSUP
Output Capacitor 1 LDO
Output Capacitor 2 LDO
Input capacitor (Electrolytic)
Input capacitor (Ceramic)
7.16.3 VCC Power-on-Reset
Table 20. VCC
Symbol
Vuvr_off
Vuvr_on
Vhyst_vcc
Parameter
VCC under-voltage threshold OFF
VCC under voltage threshold ON
Hysteresis of under-voltage threshold on/off VCC
7.16.4 VSUP Power-on-Reset
Table 21. VSUP
Symbol Parameter
Vsuvr_off
Vsuvr_on
VSUP under-voltage threshold OFF
VSUP under-voltage threshold ON
Vhyst_VSUP Hysteresis of VSUP under-voltage
Condition
Normal mode
Δ VCC / Δ VSUP for VSUP range
Δ VCC / Δ ICCn
(0.5mA < I
LOAD
< 50mA)
Electrolytic
Ceramic
For EMC suppression
Condition
Rising edge of VCC
Falling edge of VCC
Condition
Rising edge of VSUP
Falling edge of VSUP
Min
4.3
3.15
2.2
1
100
0.02
22
1
100
0.02
Typ
12
3.3
1
1
100
10
10
10
220
220
1
Max
18
3.45
45
250
8 mV/mA
W
μ F
Ω nF
Ω
μ F
Ω nF
Unit
V
V mA mA mV/V
Min
2.55
2.3
0.1
Typ
0.25
Max
2.95
2.7
0.4
Unit
V
V
V
Min
4.8
3.5
1.1
Typ
5.1
3.8
Max
5.4
4.1
1.5
Unit
V
V
V www.ams.com
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Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
7.16.5 Window Watchdog Timer
Table 22. WWD
Symbol
WD_TCL
WD_TSV
WD_TCL1
WD_TSV1
WD_TCL2
WD_TSV2
WD_TCL3
WD_TSV3
WD_TCL4
WD_TSV4
WD_TCL5
WD_TSV5
Factory setting 1
Factory setting 2
Factory setting 3
Factory setting 4
Factory setting 5
Factory setting 6
Parameter
WWD non-service time
WWD Service time
WWD non-service time
WWD Service time
WWD non-service time
WWD Service time
WWD non-service time
WWD Service time
WWD non-service time
WWD Service time
WWD non-service time
WWD Service time
Condition
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
7.16.6 LIN Transceiver
DC Electrical Characteristics.
Table 23. Driver
Symbol Parameter
I bus_lim
Pull-up resistor
I
LIN_V
OL bus_leak_rec
Condition
Current limitation in dominant state
LIN = VSUP_max
Output Voltage BUS (dominant state),
I
LIN
= 40mA
(short-circuit condition tested at V
OL
=2.5V)
Normal mode
(recessive BUS level on Tx pin)
Driver OFF; 7.3V < VSUP < 18;
8V < V
BAT
< 18,
VSUP < VBUS < 1.08 * VSUP
(to be tested at VBUS = 18V)
Table 24. Receiver
I
I
Symbol
bus_leak_dom
I bus_no_GND bus_no_bat
Parameter Condition
Input Leakage current at receiver
Driver OFF;
VBUS = 0V; VSUP = 12V; VCC = 3.3V
VSS = VSUP; VSUP = 12V;
0V < VBUS < 18V, VCC = 3.3V
(to be tested at VBUS = 18V)
VSUP = VSS; 0V < VBUS < 18V,
VCC = VSS
(to be tested at VBUS = 18V)
V bus_dom
V bus_rec
V bus_cnt
V hys
V bus_cnt
= (V th_dom
+ V th_rec
)/2
1
V hys
= (V th_dom
– V th_rec
)
1. V th_dom
: Receiver threshold of the recessive to dominant LIN bus edge
V th_rec
: Receiver threshold of the dominant to recessive LIN bus edge
Min
40
20
Min
-1
-1
0.6
0.475
0.05
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Revision 1.1
Min Typ
0-100
100-200
0-80
80-160
0-60
60-120
0-200
200-400
0-160
160-320
0-120
120-240
Max
Typ
120
40
Typ
Max
200
2
60
20
Max
1
V
K Ω
µA mA
100 µA
0.4
VSUP
VSUP
0.525
VSUP
0.175
VSUP
23 - 65 ms ms ms ms ms ms ms ms ms
Unit
ms ms ms
Unit
mA
Unit
mA
AS8515
Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
AC Electrical Characteristics.
LIN Driver, Bus load conditions (C
BUS
; R
BUS
): 1nF; 1k Ω / 6, 8nF; 660 Ω / 10nF; 500 Ω
Table 25. LIN Driver
Symbol Parameter
D1
D2
D3
D4 t dLR t dHR t
RS t
WAKE t sln t nsl t rec_deb
C int
(worst case 20Kbps transmission)
(worst case 20kbps transmission)
(worst case 10.4kbps transmission)
(worst case 10.4kbps transmission)
Condition
V th_rec
(max)
= 0.744 x V
SUP
;
V th_d om
(max)
= 0.581 x V
SUP
;
V
SUP
= 6.0V...18V; t bit
= 50µs;
D1 = t bus_rec(min)
/ (2 x t bit
)
V th_rec
(min)
= 0.422 x V
SUP
;
V th_d om
(min)
= 0.284 x V
SUP
;
V
SUP
= 6V...18V; t bit
= 50µs;
D2 = t bus_rec(max)
/ (2 x t bit
)
V th_rec
(max)
= 0.778 x V
SUP
;
V th_d om
(max)
= 0.616 x V
SUP
;
V
SUP
= 6.0V...18V; t bit
= 96µs;
D3 = t bus_rec(min)
/ (2 x t bit
)
V th_rec
(min)
= 0.389 x V
SUP
;
V th_d om
(min)
= 0.251 x V
SUP
;
V
SUP
= 6V...18V; t bit
= 96µs;
D4 = tb us_rec(max)
/ (2 x t bit
)
VCC = 3.3V;
Propagation delay bus dominant to Rx LOW
VCC = 3.3V;
Propagation delay bus dominant to Rx HIGH
Receiver delay symmetry
Dominant time for wake-up via LIN bus
Transition from standby mode to normal mode (clock frequency is 128KHz ±25%)
Transition from normal mode to standby mode (clock frequency is 128KHz ±25%)
Receiver de-bounce time
Internal capacitance of the LIN node configured as a slave with a 180pF cap on the LIN bus
Min
0.396
0.417
-2
30
0.6
7.17 Timing Diagrams
Figure 15. Timing Diagram for Propagation Delays
Typ
220
4
6
Max
0.581
0.59
Unit
6
6
2
150
3
250
µs
µs
µs
µs
Clock cycles
Clock cycles
µs pF
TxD
V
BUS
50%
t
df_TXD
BUS
95%
50%
100
%
t
dr_TXD
50%
5%
RxD
50%
0%
t
df_RXD
t
dr_RXD www.ams.com
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AS8515
Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
Figure 16. Timing Diagram for Duty Cycle According to LIN 2.1 and J2602
t
Bit
t
Bit
TxD
V
SUP
BUS
100
%
t
x_dom_max
t
x_dom_min
t
x_rec_min
t
dom(max)
t
dom(min)
58.1%
61.6%
28.4%
25.1%
V
SS
0%
t
x_rec_max
74.4%
77.8%
42.2%
38.9%
t
rec(min)
t
rec(max)
58.1%
61.6%
28.4%
25.1%
TxD
LIN
Vth_rec(max)
Vth_dom(max)
Vth_rec(min)
Vth_dom(min) t bit t bit t bus_dom(max) t bus_rec(min) t bus_dom(min) t bus_rec(max) www.ams.com
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Datasheet (discontinued) - A S 8 5 1 5 To p D i e O v e r v i e w
7.17.1 Tx Timeout Watchdog
Table 26. Tx Timeout Watchdog
Symbol
t lin_wdog
Parameter
Timeout period for the dominant state
Conditions Min
0.5
Typ
1
Max
2
Units
s
7.17.2 Temperature Limiter
Table 27. Temperature Limiter
Symbol
T sd
T otset
T ret
Parameter
Shut down temperature
Over-temperature warning
Return temperature
Conditions
Junction temperature
Min
155
142
125
Typ
170
157
140
Max
185
172
155
Units
ºC
ºC
ºC
7.18 Top Die Registers
The serial interface can be used for communication between AS8515 and an external microcontroller. The device is only a slave and the microcontroller has to initiate the communication. The device can be configured by writing into the control registers and the diagnostic information can be read out from the diagnostic registers. Pin CST is used as chip select for SPI communication.
A total of 32 registers, each of 8-bits which include configuration, diagnostic, and backup are available. The registers can be accessed using the
4-wire serial interface.
provides a description of all AS8515
Top die
registers.
Table 28. AS8515 Top Die Registers
Address Register Name Default Value R/W
Configuration and Control Registers
0x00
0x01
0x02
Reserved
Reserved
Reserved
Description
0x03
0x04
0x05
0x06
Device
Configuration
Register
Device Control
Register
On
POR_VSUP
0000_0001
Temporary
Shutdown
Register
Window Watch
Dog Trigger
Register
On
POR_VCC
0000_1100
On
POR_VCC
0000_0000
On
POR_VCC
0000_0000
R/W
R/W
R/W
W
D0 Reserved
D1 Voltage Attenuator Enable Bit.
0 Disabled, 1 Enabled
D2 Enable/Disable Over Temperature Monitor
0 Disabled, 1 Enabled
D3 Enable/Disable LIN Transceiver
0 Disabled, 1 Enabled
D4 Reserved
D5-D7 Reserved
D0 High-slew / Low-slew control
1 High-slew, 0 Low-slew
D1-D7 Reserved
D0 Temporary shutdown control bit
1 Enter temporary shutdown
D1-D7 Reserved
D0 Window Watchdog trigger bit
D1 Timeout Watchdog trigger bit
Upon a trigger, the bit will be cleared within 2 internal clock cycles.
D2-D7 Reserved
0x07
0x0A
0x0B
Reserved
Reserved
Reserved www.ams.com
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Table 28. AS8515 Top Die Registers
Address Register Name Default Value R/W
0x0C
0x0D
Reserved
Reserved
0x0E
Watchdog Timer
Control Register
On
POR_VCC
0000_0000
Description
R/W
D0 Timer resolution
0 1 second, 1 32 seconds
D1-D7 Timeout period.
If D0=1, then timeout period = D[7:1]*64*0.512 seconds, else timeout period
= D[7:1]*0.512 seconds
0x0F Reserved
Diagnostic Registers
0x08
0x09
Diagnostic
Register-1
Diagnostic
Register-2
On
0000_0011
On
POR_VSUP
POR_VSUP
0000_0000
R
R
D7-D0 = DR[7:0], 8-LSB bits of the 24-bit Diagnostic Register.
D0 POR-VSUP
Set when VSUP < Vsuvr_on, cleared after µC read
D1 Under voltage VCC (UVVCC)
Set when VCC < Vuvr_on, cleared after µC read
D2 Over-temperature Reset (OTEMP170)
Set when temp > T sd
, cleared after µC read
D3 Over-temperature warning (OTEMP160)
Set when temp > T otset
, cleared after µC read
D4 Overvoltage VSENSE (OVVSENSE)
Set when VSUP > Vovthh, cleared after µC read
D5 Reserved
D6 Remote wakeup (RWAKE)
Set on remote wakeup event on LIN Bus, cleared after µC read
D7 Set on failure of window Watchdog trigger, cleared after µC read
D7-D0 = DR[15:8], Next 8-LSB bits of the 24-bit Diagnostic Register.
D0 Tx timeout of 1sec (TXTIMEOUT)
Set on Tx low > 1sec, cleared after µC read
D1 TEMPSHUT
This bit is set on entering temporary shutdown state and cleared after µC read.
D2 Set on failure of timeout Watchdog trigger, cleared after µC read
D3 Load Dump Flag
D7-D4 Reserved www.ams.com
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AS8515
Datasheet (discontinued) - A S 8 5 1 5 B o t t o m D i e O v e r v i e w
8 AS8515 Bottom Die Overview
The AS8515
Bottom die
consists of two independent high resolution 16-bit SD analog to digital conversion channels. The measurement path of these two channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filter for simultaneous measurement of Current and Voltage/Temperature.
The two measurement channels, namely the Current and Voltage/Temperature measurement channels have identical data path.
The input signal is amplified in the Programmable Gain Amplifier (PGA) with any of the selected gains of 1, 5, 25, 40 and 100 facilitating measurement of a wide range of Current, voltage and temperature levels. Gain Settings for different input ranges and any associated restrictions are explained in the
Offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. By default the chopper/de-chopper is ON in the measurement path. It may be disabled by programming the appropriate register.
The amplified input signal is converted into a single-bit pulse-density modulated stream by the Σ Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. The decimation ratios of 64, 128 may be selected in the first filter stage. For reducing data rate further, the second stage decimation can be used.
An optional FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
8.1 Current Measurement Channel
The voltage across a Shunt Resistor, connected in series with the Battery negative terminal, forms the input signal to the Current Measurement channel. RSHH and RSHL are the Current measurement input pins. Offset in the input signal is nullified with the use of a chopper and a dechopper at appropriate stages in the data path. The programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and
100 enables measurement of current ranges from ±1A to ±1500A on a 100µ Ω shunt. The sampled input signal is converted into a single-bit pulse-density modulated stream by the Σ Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16bit data equivalent to the input current signal. The programmable input sampling rate and the decimation ratio determine the output data rates.
The data path can be programmed to provide sub 1Hz to 4kHz rates in the various modes available. An optional FIR filter specifically designed for 1KHz sample rate is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
After enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles.
8.2 Voltage/Temperature Measurement Channel
The other two parameters of the Battery for measurement are Voltage and its Temperature. The second channel accepts signals from four independent sources through a Multiplexer as listed below:
An attenuator battery voltage obtained through internal resistor divider from
Top die
, (or)
A signal from the external temperature sensor, (or)
A signal from external reference, (or)
A signal from the internal temperature sensor.
Apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the Current measurement channel.
RSHH and RSHL are the Current measurement input pins.
The Battery Voltage which can go up to 18V is attenuated through a Resistor Divider externally and is applied to the Voltage Channel. For
Automotive Battery measurement, the PGA is to be bypassed to connect battery voltage attenuated by a factor of 21 directly to the ADC input.
The latency for the first result from the voltage measurement channel is two conversion cycles.
A second option on this measurement channel is to measure Temperature. Internally generated constant current is pumped through the
Temperature Sensor with positive temperature coefficient, and, a high- precision resistor. The voltages across the sensor and the resistor form the inputs to the measurement channel one at a time. The difference between the two voltages which is independent of the magnitude of the current is used to determine the temperature accurately. The voltage across the sensor is applied between the ETS and VSS pins and, the voltage across the high-precision resistor is applied between ETR and VSS. External temperature measurement involves the acquisition of two signals one after the other using the same constant current source. The latency for the first result from the temperature measurement channel is two conversion cycles.
A third option on the measurement channel is to measure the internal temperature. Hence, one of the three options for measurement of Battery
Voltage, External Temperature and, internal temperature may be carried out by selection of appropriate inputs through the internal multiplexer selection.
ETR and ETS inputs can optionally be used to measure other signal sources like external resistive attenuators for battery voltages different to
12V nominal.
ETR and ETS are single ended inputs and referenced to AVSS. Voltage drop on internal bond wire causes ~100 digits of offset with systematic temperature dependency of another 50 LSB’s over temperature.
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8.3 Digital Implementation of Measurement Path
Figure 17. Block Diagram of Digital Implementation
MOD_I
N
MOD_CLK
f
mod
R1
CIC1
64 / 128
R2
FIR_MA_SEL
f
mod
/ R1
Dechopper
f
chop
* 2
CIC2
f
chop
* 2 / R2
FIR / MA
f
chop
* 2 / R2
DATAOUT
R1
f chop
R1 = First decimation ratio (64 or 128)
R2 = Second decimation ratio (1 to 32768)
CHP_CLK
CLK DIVISION
BLOCK
MOD_CLK
shows the digital implementation of the decimator and filter to process the 1-bit output of the Modulator. This block receives a 1-bit pulse density modulated output (MOD_IN) from the second order sigma delta modulator along with the oversampling frequency clock
(MOD_CLK). The MOD_CLK directly goes to a clock division block, which generates chopper clock (CHOP_CLK). The CHOP_CLK can be one of 2kHz or 4kHz selected by Register CLK_REG in
Table 49 . The MOD_CLK can be either 1MHz or 2MHz. The Decimation is a two phase
process. In the first phase, the R1 down sampling rate can be obtained by selecting either 64 or 128 in Registers DECREG_R1_I,
. The 16-bit CIC1 output is dechopped with respect to CHOP_CLK. The output of Dechopper is passed through the
CIC2 filter with a decimation ratio of 1to 32768 in steps of power of 2. This output is then processed through a FIR or Moving Average (MA) filter.
FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. MA filter is used to provide averaged output and the number of samples for averaging can be any integer value from 1 to 15.
8.4 Reference-Voltage
Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement.
8.5 Oscillators
A High-speed oscillator (HS) generates the oversampling clock. For internal state machine and Interrupt generation, a low-speed Oscillator (LS) is also available.
8.6 Power-On Reset
The AS8515 has PORs, APOR and DPOR on analog and digital power supplies respectively. On PORs of both supplies, initialization sequence
happens and the system status is shown in state diagram (see Figure 18)
.
As shown in the state diagram, the system is in RESET state until DPOR output goes to logic HIGH and subsequently until APOR output goes to logic HIGH. Once analog power supply is available, the system goes into OTP_INT state and loads the default values into the control and data registers and goes into STOP state. If analog POR, APOR goes low at any time, the system goes into RESET state. In the STOP state, the
AS8515 can be programmed and by giving start command it starts working following the state machine.
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8.7 Modes of Operation
The device operates in four different modes, namely,
Normal Mode 1 (NOM1)
Normal Mode 2 (NOM2)
Standby Mode 1 (SBM1)
Standby Mode 2 (SBM2)
The Normal Modes are full-power modes with the exception that in Normal Mode 2, sampling is normally at a programmed lower frequency and is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel.
The Standby Modes are lower power modes. Sampling is normally at a very low frequency interval. In Standby Mode 2, data sampling can be carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it generates interrupt on the INT pin.
The device enters into the “Stop” state on Power On. This is a state where in the data path is inactive and can be entered into from any of the
Figure 18. Finite State Machine Model of AS8515 Bottom Die
RESET
OTP_INT
Wait for otp_load
Completes in 32 cycles of lp_clk stop star t
1.5msec &
NORM
STOP
Analog Stablization period
Wait for 1.5msec
A_STB
NORM
Wait for x number of conversions
SBM_ON
sto p
NO
RM
TT1
_tim eou t
SBM
SBM_OFF
Wait for TT1 timeout
NORM or stop
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Figure Notes:
1. Device soft reset can be written in any of the following states STOP, A_STB, SBM_ON, SBM_OFF by writing “0” into D[7] of the RESET
_REG (Address 0X09).
2. Measurement path of soft reset should be written in any the states, STOP, SBM_OFF by writing “0” into D[6] of the RESET _REG (Address
0X09).
3. When soft reset is used for the measurement path or for the device, external clock needs to be disabled if the system clock is external clock in the application.
8.7.1 Normal Mode 1 (NOM1)
On Power-on-reset of the device, AS8515 goes into STOP State.
is set to “1” through the serial port SPI. Data Rate of voltage and current channels can be independently programmed and both the channels generate l interrupts for every output available from ADC. The interrupt signal is generated on the INT pin. The width of the interrupt pulse is eight cycles of p_clk
. The data is stable up to the next interrupt. If the data rate is different for the two channels, the interrupt rate would follow the higher rate among the two channels. Data update can be known by reading the status register. The functionality is explained in the waveform shown in
. When the device is configured to NORMAL Mode1 from any mode the configuration should be through the STOP state only.
Figure 19. Normal Mode 1
I
DATA
I
Sampling with f1
V,T
DATA
V,T
Sampling with f2
STOP
START
Current Channel
DATA Register
Voltage Channel
DATA Register
INT at f1 rate from current channel
Interrupt from the current channel is at f1 rate which is integer multiple of f2 rate from voltage channel t t
T
INT
8.7.2 Normal Mode 2 (NOM2)
NOM2 differs from NOM1 in such a way that it allows for a relaxed data rate at a period of T
MC
by programming the corresponding register as long as the amplitude of current is less than a programmed threshold I
THC
. However, when, the measured input signal exceeds the programmed threshold, the data rate is changed to the rate of NOM1 mode.
Transition to NOM2 occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in
Table 49 is set to 1 and mode control bits to
01 through SPI. In this mode the data rate should be programmed with the time of T
MC
. An interrupt signal is generated on INT at the rate of T
MC secs with a pulse width of eight cycles of l p_clk
. The data is stable up to the next interrupt. The data sample is compared against the programmed threshold and when it is exceeded, the data sampling rate is changed to provide data at the data rate of NOM1 mode. However, as soon as the data sample amplitude falls below the programmed threshold, the sampling rate is restored to provide data at the rate of T
MC
. The functionality is illustrated in the waveform
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Figure 20. Normal Mode 2
I
I
DD
I
THS
T
MC
V,I,T
T
MC
V,I,T V,I,T
I < I
THS
V,I,T V,I,T
Sampling with f t
I > I
THS
INT
T INT
8.7.3 Standby Mode1 (SBM1)
The low-power Standby Mode can be entered only through the STOP state. Transition to SBM1 mode occurs when the “START BIT” D0 of Mode
Control register MOD_CTL_REG in Table 49
is set to “1” and Mode Control Bits to “10” through SPI. In this mode the date rate is programmable with the time of Ta. An interrupt signal is generated on INT at the rate of Ta seconds, and with a pulse width of eight cycles of l p_clk
. The data is stable up to the next interrupt. The functionality is illustrated in Figure. During the period of Ta, only one data sample is made available and, during the rest of the period, the device is maintained in STOP state to reduce power consumption. The microcontroller which receives the data on the Interrupt, is also expected to be processing the data for a short time as shown clearly in the
Figure 21 to ensure the overall low-power
consumption of the data acquisition and processing system.
Figure 21. Standby Mode 1
I
DD
MCU MCU
ADC
MCU
V, I, T
V, I, T t
T a
sec.
Start SBM1
Channel
DATA Register
INT
DATA – A0
T conv
T a
sec.
DATA – A1
T conv
T a
sec.
DATA – A2
T conv
DATA – A3
T
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8.7.4 Standby Mode2 (SBM2)
Standby Mode 2 is an extension of the Standby Mode1 to achieve even a lower power in the data acquisition system by providing interrupt to the microcontroller only when the data sample exceeds the set current threshold. The Standby Mode can be entered only through the STOP state.
Transition to SBM2 mode occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in
is set to “1” and Mode Control
Bits D7,D6 to “1,1” through SPI. In this mode the date rate is programmable with the time of Ta in the Ta control registers B, C. The data sample is made available and an interrupt signal is generated on INT pin only when the input signal exceeds the threshold set in Current Threshold
Registers D,E. It should be noted here that the data is stable for Ta seconds. The functionality is illustrated in
Figure 22. Standby Mode 2
I
DD
|I| > I Threshold I
MCU
I
ADC t
Start SBM2
Channel
DATA Register
INT
T a
sec.
DATA – A0
T conv
T a
sec.
DATA – A1
T conv
T a
sec.
DATA – A2
T conv
DATA – A3
T
INT
8.8 Initialization Sequence at Power ON
Figure 23. Bottom Die Device Initialization Sequence at Power ON
V
PORHID
/V
PORHIA
DVDD/AVDD
POR_N
INT
CHOP_CLK
Channel Data
Register
Start
ADC 1.5mS
500µS
Configure
Device
D1
T
ADC
D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4
0x0000
DATA1
T
DATA_STATUS_RD
T
DATA_VALID
T
DATA_INVALID
DATA2
Device initialization starts if the DVDD and AVDD supplies are switched ON and DVDD > V
PORHID
. The duration period of Initialization is 500 μ sec and during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and activation should be carried out only after the initialization period.
On ADC start, device enters into analog stabilization state and takes 1.5msec for oscillator and Reference to settle. After this 1.5msec period, the first interrupt will occur after a time period of T
ADC
.
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T
DATA
_
STATUS
_
RD
is the time period during which the micro-controller should complete reading of data and status from the device. If reading is carried out beyond this time period, then, ADC performance will degrade for next sample generation. Status register gets cleared automatically only when micro-controller reads this register. Data in the channel registers is changed after T
DATA
_
VALID
duration. Ensure that data channel registers and status registers are not read during the T
DATA
_
INVALID duration.
Example:
Configuration registers are set as follows:
CLK_REG = 8’b0010_0000
DEC_REG_R1_I = 0100_0101
DEC_REG_R2_I = 1100_0101
FIR_CTL_REG_I = 0000_0100
ADC is configured to a data rate of 1KHz, CHOP_CLK to 2KHz, and Modulator clock to 1MHz, Decimation ratio of CIC1 = 64, and Decimation
T
DATA
_
STATUS
_
RD
= 100
μ sec
(T
DATA
_
STATUS
_
RD
= (1/mod_clk) * R1 * [((mod_clk/(2*chop_clk))*(1/R1)) - 2.5)
T
DATA
_
INVALID
= 8 μ sec
T
ADC
= 1msec
T
DATA
_
VALID
= T
ADC
- T
DATA
_
INVALID
= 1msec - 8 μ sec
CHOP_CLK and POR_N are internal signals of the device.
DATA
_
STATUS
_
RD
and
T
ADC
.
Table 29. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1
Modulator Clock
1.024MHz
2.048MHz
Chopper Frequency
CHOP_CLK
2KHz
2KHz
Decimation Ratio R1
64
64
T
DATA
_
STATUS
_
RD
1usec * 64 * [4 - 2.5] = 96usec
0.5usec * 64 * [8 - 2.5] = 176usec
T
ADC
R2/(2*CHOP_CLK) for R2=4
1mSec
1mSec
2.048MHz
2KHz 128
0.5usec * 128 * [4 - 2.5] = 96usec
1mSec
2.048MHz
4KHz 64
0.5usec * 64 * [4 - 2.5] = 48usec
0.5mSec
8.8.1 Soft-reset of Device Using Bit D[7] of Reset Register 0x09
It is possible to soft-reset the device by writing “0” into D[7] bit of Reset Register at 0x09. On applying soft-reset, the device enters into initialization state and D[6] bit changes back to “1”. The duration period of Initialization is 500 μ sec, and, during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and
activation should be carried out only after the initialization period. See Figure 24
for the timing details of the sequence of device initialization on soft-reset.
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Figure 24. Bottom Die Device Initialization Sequence at Soft-reset
Start
ADC
1.5mS
INT
D4 D1 D2 D3 D4
CHOP_CLK
Channel Data
Register
DATA-N
T
DATA_STATUS_RD
T
DATA_VALID
D1
500µS
Soft Reset
Using D7
Re-Configure
Device
DATA-N+1
T
DATA_INVALID
0x0000
D1 D2
D
3
D4
D1 D2
D3 D4
D1 D2
D3 D4
DATA1
T
DATA_STATUS_RD
T
DATA_VALID
T
DATA_INVALID
DATA2
8.8.2 Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09
Measurement path also can be reset by using D[6] bit of Reset Register at 0x09. On applying soft-reset only signal measurement path registers will be reset. For applying this reset, device should be in STOP state. If the device is working with external clock, at the time of soft-reset the clock needs to be disabled.
8.8.3 Reconfiguring Gain Setting of PGA
Only PGA gain settings can be changed dynamically while ADC conversions are in progress. When PGA gain settings are changed, the first sample from the ADC is invalid. Ignore the first interrupt after the gain re-configuration. Valid data starts from the second interrupt onwards.
Figure 25. Bottom Die - Re-configuration of Gain Setting of PGA
Read Channel data in this slot
T
DATA_STATUS_RD
Gain Re-Configuration can be carried out in this slot, skip next interrupt and Channel Data.
INT
CHOP_CLK
Channel Data
Register
D4
D1 D2
D3 D4
D1
DATA-N
T
DATA_STATUS_RD
T
DATA_VALID
T
DATA_INVALID
DATA-N+1
D2
D3 D4
D1 D2
T
DATA_STATUS_RD
DATA1
T
DATA_VALID
D3
VALID
DATA
D4 D1
T
DATA_INVALID
D2
DATA2
D3 D4
8.8.4 Configuring the Device During Normal Mode
Following registers can be programmed dynamically when the device is in operational mode (Normal mode).
ACH_CTL_REG address is 0x17 for channel selection on the voltage measurement path
PGA_CTL_REG address is 0x13 for gain setting
PD_CTL_REG2 address is 0x15 for PGA Bypass
ISC_CTL_REG address is 0x18 for current source programmability
During the operation (Normal mode) of the device, if any of the registers need to be programmed or changed other than the above mentioned registers, then it is required to STOP the device by writing into MOD_CTL_REG “STOP” bit and configure the device as per the requirements and start the device.
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8.8.5 Standby Mode - Power Consumption
In Standby Mode 1 there is a timer based accurate measurement every Ta seconds. The device itself stays in idle-mode as long as it does not get a different command from the SPI interface. Internal oscillator frequency is typically foscint=262 kHz to reduce power consumption as long as the timer runs. After every time out of Ta seconds, it performs accurate measurement of current, voltage/ temperature. Data ready is signaled to microcontroller through an interrupt signal on INT and goes into STOP state.
In the SBM the following equations hold:
T sbm1
= Ta= 10s (default value is 10secs); the power consumption is valid for this setting. This is the period of the repetition rate in SBM 1 and SBM2.
T sett
≈ 2ms (depending on external capacitors). This is the time required by the analog part to settle when the new measuring period is started. Any measurements performed during T sett
produce invalid results.
T1 = 3ms (by default setting, every third measurement is sent to microcontroller in the SBM mode 1) is the time needed to perform the first measurement.
T meas
=T sett
+T1 is the total active time needed to get a valid result.
DR
SBM
= T meas
/T sbm
≈ 5ms/10s. This is the ratio of repetition time versus the active time (Device in NOM mode).
Power consumption = (DR
SBM
*NOM mode power consumption) + ((10s-5ms)/10s)*Stop mode power consumption)
8.9 Bottom Die Block Specifications
This section provides specification of design related key parameters.
8.9.1 Current Measurement Ranges (across 100µ
Ω
(±5%) shunt resistor)
Table 30. Current Measurement Ranges
Symbol
I70
I200
I400
I1500
Parameter
I max
[A]
V sh
[mV]
Input current range of 70A in NOM
Input current range of 200A in NOM
±77
±235
±8.1
±24.7
Input current range of 400A in NOM ±400 ±42
Input current range of 1500A in NOM +2076/-1523 +218/-160
PGA
Gain
Nominal
100
40
25
5
Data Rate
(f
OUT
)
@ 1 kHz
@ 1 kHz
@ 1 kHz
@ 1 kHz
V
INADC
1
[mV]
890
1088
1137
1204
PSR
2
[dB]
60
60
60
60
1. V
INADC
= V sh
* Gain, gain deviations to be considered according to
and
.
2. AVDD, DVDD of 3.3V with ±5% variation.
Note:
The Data Rate at the output can be calculated according to the formula:
fsout=2*fchop /R2 (R2 is down sampling ratio taking values 1, 2, 4 up to 32768 as powers of 2)
Table 31. Valid Combinations of the Chopper Clock, Oversampling Clock and Decimation Ratios
Over Sampling Frequency Chopper Frequency
1.024MHz
2.048MHz
2kHz
2kHz
2.048MHz
2.048MHz
2kHz
4kHz
Decimation Ratio
64
64
128
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Differential Input Amplifier for Current Channel.
Table 32. Differential Input Amplifier for Current Channel
Symbol
V
IN
_AMP
Parameter
Input voltage range
I
IN
_AMP
Input current
1, 11
ICM
G = G1
G = G2
G = G3
G = G4 e f
P
_AMP
Absolute input voltage range
2
Gain1
3, 4, 9
Gain2
3, 4, 9
Gain3
3, 4, 9
Gain4
3, 4, 9
Gain deviation
Pole frequency
4, 5
Conditions
RSHH and RSHL
RSHH and RSHL@ +160mV input voltage at 125ºC with PGA
I10
I200
I400
I1500 i = 1, 2, 3, 4
ε
T1
Gain drift with temperature
6
-20ºC to +65ºC
Gain 5, 25, referenced to room temperature
V
OSDRIFT
V os
V os_ch
V
Ndin
THD
Offset drift with temperature
7, 10
Input referred offset
7, 10
Noise density
4, 8
Total harmonic distortion
After trim at -20deg
Chopping enabled
For 150 Hz input signal
Min
-160
-50
0.9 * Gi
15
Typ
2
-160
+300
100
40
25
5
350
0
25
70
Max
+160
50
1.1 * Gi
±0.5
350
Units
mV nA mV kHz
%
µV
µV
LSB nV/ √ Hz dB
Notes:
1. Leakage test accuracy is limited by tester resource accuracy and tester hardware.
2. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
3. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are programmed independently.
4. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaranteed by design.
5. Pole frequency of input amplifier changes with GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other ranges. This parameter is not measured in production.
6. Based on device evaluation. Not tested.
7. These offsets are cancelled if chopping enabled (default).
8. Noise density calculated by taking system bandwidth as 150Hz.
9. Refer to Measurement Ranges shown in Table 30
.
10. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
11. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of protection diode.
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G = G1
G = G2
G = G3
G = G4 e f
P
_AMP
V
NDIN
THD
Differential Input Amplifier for Voltage Channel.
Table 33. Differential Input Amplifier for Voltage Channel
Symbol
V
IN_
AMP
Parameter
Input voltage range
1, 10
I
IN_RES
Input resistance
2, 10
Conditions
VBAT_IN, ETR, ETS @ +160mV input voltage at 125ºC with PGA
ICM
Absolute input voltage range
3
Gain1
4, 5
Gain2
4, 5
Gain3
4, 5
Gain4
4, 5
Gain deviation
Pole frequency
5, 6
Noise density
5, 7
Total harmonic distortion i = 1, 2, 3, 4
ε
T
1
V
OS
V os_ch
V
OSDRIFT
Gain drift with temperature
8
Input referred offset
9
Offset drift with temperature
9
For 150Hz input signal
-20ºC to +65ºC
Gain 5, 25, referenced to room temperature
After trim at -20ºC
Chopping enabled
Min
-160
0.9 * Gi
15
Typ
12.5
-160
+300
100
40
25
5
25
70
0
350
Max
+160
1.1 * Gi
±0.5
350 kHz nV/ √ Hz dB
%
µV
LSB
µV
Units
mV k Ω mV
Notes:
1. Input for the voltage channel can be as high as 1220mV, in this high input case PGA will be bypassed.
2. Leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to condensing moisture.
3. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
4. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are programmed independently.
5. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaranteed by design.
6. Pole frequency of input amplifier changes with changing the GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other ranges. This parameter is not measured in production.
7. Noise density calculated by taking system bandwidth as 150Hz.
8. Based on device evaluation. Not tested.
9. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
10. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of protection diode.
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Sigma Delta Analog to Digital Converter.
Table 34. Sigma Delta Analog to Digital Converter
Symbol Parameter
V
V
REF
INADC
R1
Reference voltage
6
Input range
1
Oversampling ratio/Decimation Ratio
2 f
OVS
Oversampling frequency
3
RES
BW
S/N
Number of bits
Bandwidth
4
Signal to noise ratio
5
Conditions
At V
REF
= 1.22V
Min
0
64
1
Typ
1.225
128
1024/
2048
90
Max
±1.22
128
16
500
Units
V
V
Notes:
1. Production test at ±800mV. Maximum V
IN
can be 1.22V with VREF=1.225V.
2. Programmable. It is defined with respect to the first decimator in the ΣΔ ADC.
3. Programmable: Internal clock is 1024/2048 kHz; external clock max is 8192 kHz.
4. Dependent on fovs, R1 and R2. The bandwidth is calculated according to the formula:
BW=fovs/(2*R1*R2); the sampling frequency at the output of the A/D converter is 2*BW.
5. Defined at maximum input signal, BW=500 Hz (1Hz to 500 Hz), fovs=1024 kHz, R1=64, fchop=2 kHz and R2=2.
6. Reference voltage might be forced from external.
Bandgap Reference Voltage.
Table 35. Bandgap Reference Voltage
Symbol Parameter
V
REFTRIM
V
REFACC
Reference Voltage after trim
1, 2, 3
Reference Voltage Initial Accuracy
1, 2, 3
V
REF
DRIFT
PSRR
REF
SUT
AVDD
SUT
PD
R
NDVREF
V
NDVREF
CL
VREF
ESR
VREF
Reference Voltage Temperature drift
PSR @ dc
Start Up Time with supply ramp
4
Start Up Time from power down
4
Output resistance of band gap
Bandgap reference thermal noise density
4
Output Capacitor (Ceramic)
Conditions
Trim at 65ºC
At 65ºC (0 Hour data)
Temperature range
-20ºC to 65ºC
Temperature range
-40ºC to 125ºC
Min
0.02
Typ
1.225
+0.4/
-0.6
80
5
500
100
Max
±6.5
±0.4
Units
V mV
%
% dB ms
1 ms
1000
Ω
300 nV/ √ Hz nF
1 Ω
Notes:
1. Accuracy at 65ºC. No DC current is allowed from this pin.
2. Specification does not include solder shift and life time drift.
3. Please refer Figure 26 for typical life time drift based on system level measurements.
4. This is a design parameter and not production tested.
kHz bits
Hz dB www.ams.com
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Figure 26. Typical System-level V
REF
Drift
AS8515
www.ams.com
1.2265
1.2260
1.2255
1.2250
1.2245
1.2240
1.2235
1.2230
0 50 100 150 200 250
System Level Operating Time in Normal mode at 115ºC ambient [h]
300
DUT1
DUT2
DUT3
DUT4
0.10%
-0.10%
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Internal (Programmable) Current Source for External Temperature Measurement.
Table 36. External Temperature Measurement
Symbol
I
CURON
I
CUROFF
Parameter
5-bit current source enabled
1
5-bit current source disabled
Conditions
5-bit programmable current source
Limited by leakage
T
K
_
CS
Temperature coefficient of current source
2
V
MAXETR
V
MAXETRMOD
V
MAXETS
V
MAXETSMOD
Voltage on pin ETR
3
Max voltage on pin ETR when PGA is bypassed
4
Voltage on pin ETS for resistor sensor
3
Max. Voltage on pin ETS when PGA is bypassed
5
Min
0
Typ
270
10
1000
Max
320
1000/G
1.22
1000/G
1.22
Units
µA nA ppm
/ ºK mV
V
V
V
Notes:
1. Current value can be programmed through stop mode in steps of 8 μ A from 0 to 256 μ A with a process error of 30%.
2. Temperature coefficient is not important since external temperature measurement is a 2 step measurement. The value specified is guaranteed by design and will not be tested in production.
3. Maximum voltage on pin ETR (reference) can be calculated by given formula, where G is the gain of PGA (G=100).
4. Maximum voltage on pin ETR, if PGA is bypassed.
5. Maximum voltage on pin ETS, if PGA is bypassed.
CMREF Circuit (VCM).
Table 37. CMREF Circuit
Symbol
V
VCM
C
L
Parameter
Output voltage
Load capacitance
Min
1.6
Typ
1.7
100
Max
1.8
Units
V nF
Internal AVDD Power-on Reset.
Table 38. Internal AVDD Power-on Reset
Symbol
V
PORHIA
Parameter
Power On Reset Threshold t
PORA
I
PORA
POR time - The duration from Power ON till the time, internal Power On Reset signal goes HIGH
1
Current consumption in POR block
2
1
1. POR pulse is always longer than t
PORA
whatever the slope of the supply.
2. I
PORA
can not be switched off.
Min
2.2
Typ
2.4
1.5
Max
2.6
Units
V
µs
µA www.ams.com
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Internal DVDD Power-on Reset.
Table 39. Internal DVDD Power-on Reset
Symbol
V
PORHID
Parameter
Power On Reset Threshold
V
HYST t
PORD
I
PORD
Hysteresis
1
POR time - The duration from Power ON till the time, internal Power On Reset signal goes
HIGH
2
Current
3
1. V
PORLO
= V
PORHI
- V
HYST where V
PORLO is the lower threshold of POR.
2. V
PORLO
= V
PORHI
- V
HYST where V
PORLO is the lower threshold of POR.
3. I
PORD
can not be switched off.
Low Speed Oscillator.
Table 40. Low Speed Oscillator
Symbol
f
LS f
LS
_
ACC
I
LS
High Speed Oscillator.
Table 41. High Speed Oscillator
Symbol
f
HS f
HSACC
I
HS
Parameter
Frequency
Accuracy
Supply current
Notes:
1. Accuracy after trimming.
External Clock.
Table 42. External Clock
Symbol Parameter
Parameter
Frequency
Accuracy
1
Supply current f
CLKEXT
Clock frequency
Min
2.2
0.2
Min
1
Min
Conditions
DIV
CLKEXT
DC
CLKEXT
Clock division factor
Duty Cycle of external clock
1.5
Typ
262.144
± 7
5
Typ
4.096
±4
300 to be programmed in Register 08
CLK_REG through the serial bus SPI.
Typ
2.4
0.25
Min
40
Max
2.7
0.4
Max Units
kHz
%
µA
Max Units
MHz
%
µA
Typ
2048/
4096/
8192
2/4/8
Max Units
kHz
60 %
Units
V
V
µs
µA www.ams.com
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Internal Temperature Sensor.
Table 43. Internal Temperature Sensor
Symbol
T
INTRNG
Δ
TIN
T
INTSLP
T
INT
65
G
5
Parameter
Temperature sensor range
Temperature measurement accuracy
Temperature sensor slope
Temperature sensor output at gain 5
Conditions Min
-40
Typ
3
Guaranteed by design; at PGA gain 5 which is the recommended Gain for internal temperature measurement.
27
40660 41807
8.9.2 System Specifications
Table 44. System Specifications
Symbol
I
S
At
Ph
Parameter
Channel to channel isolation
1
Difference in channel to channel attenuation
@600Hz
1, 2
Difference in phase shift between the two channels @600Hz
1, 2
Min Typ
System Measurement Error Budget for Voltage and Current Channel.
Temperature Range: -20ºC to +65ºC; Output data rate is 1kHz, V
CC
= 3.3V, chopping enabled.
Table 45. System Measurement Error Budget for Gains 5 and 25
Symbol
Err
Parameter
System measurement error
3, 4
Conditions
Measurement error due to PGA gain drift
Measurement error due to V
REF
drift
From device evaluation
Measurement error due to non-linearity of PG Tested by distortion measurements
Min
Max
-90
3
5
Typ
±0.6
Max
125
Units
ºC
ºC
Digits/C
43012 Digits
Units
dB dB
Deg
Max
1
±0.5
±0.4
±0.025
Units
%
%
%
%
Notes:
1. These specifications are defined by taking one channel as reference and measured on the other channel.
2. Guaranteed by design.
3. System measurement error due to noise, individual block parameter drifts and non linearity. Based on evaluation, not tested.
4. System error due to offset is neglected because of chopper architecture.
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Datasheet (discontinued) - 4 - W i r e S P I I n t e r f a c e
9 4-Wire SPI Interface
The SPI interface can also be used as interface between the AS8515 and an external micro-controller to configure the device and access the status information. Micro-controller begins communication with the SPI configured as a slave. The SPI protocol is very simple and the length of each frame is an integer multiple of byte except when a transmission is started. Basically each frame has 1 command bits, 5 address/ configuration bits, 1 or more data bytes. SPI clock polarity settings depend on the value of the SCLK on the CS falling edge. This setting is done on each start of the SPI transaction. During the transaction SPI clock polarity will be fixed to the settings done. On the CS falling edge the values on SCLK signal decide setting of the active SPI clock edge for data transfer
Table 46. CS and SCLK
CS
1
SCLK Description
FALL
FALL
ANY
LOW
HIGH
ANY
Serial data transferred on rising edge of SPI clock.
Sampled at falling edge of SPI clock.
Serial data transferred on falling edge of SPI clock.
Sampled at rising edge of SPI clock.
Serial data transfer edge is unchanged.
1. Pin CST is used to program top device and pin CSB is used to program bottom device.
9.1 SPI Timing Parameters
Table 47. 4-Wire Serial Port Interface
Symbol
General
BR
SPI
T
SCLKH
T
SCLKL
Write Timing
t
DIS t
DIH
T
CSH
Read Timing
Parameter
Bit rate
Clock high time
Clock low time
Data in setup time
Data in hold time
CS hold time
Conditions
t
DOD
Data out delay t
DOHZ
Data out to high impedance delay Time for the SPI to release the SDO bus
Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity)
t t
CPS
CPHD
Clock setup time
(CLK polarity)
Clock hold time
(CLK polarity)
Setup time of SCLK with respect to
CS falling edge
Hold time of SCLK with respect to
CS falling edge
Min
2
2
20
10
20
20
20
Typ Max
250
80
80
Units
ns ns ns ns ns
Kbps
µs
µs ns ns www.ams.com
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9.1.1 SPI Frame
A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of
bytes. Command is coded on the 1 first bit, while address is given on LSB 5 bits (see Table 48)
.
Table 48. Command Bits
C0
Command Bits
Reserved Reserved A4
Register Address or Transmission Configuration
A3 A2 A1 A0
C0
0
1
Command
WRITE
READ
<A4:A0>
ADDRESS
ADDRESS
Description
Writes data byte on the given starting address
Reads data byte from the given starting address
If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling), the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.
9.1.2 Write Command
For Write command C0 = 0.
After the command code C0 and two reserved bits, the address of register to be written has to be provided from the MSB to the LSB. Then one or more data bytes can be transferred, always from the MSB to the LSB. For each data byte following the first one, used address is the incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge and the SPI slave on the next SPI clock edge samples it. These edges are selected as per clock polarity settings. In the following figures two examples of write command (without and with address self-increment.
Figure 27. Protocol for Serial Data Write with Length = 1
CS
SCLK
SDI
SDO
0
RES1 RES0
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Transfer edge Sampling edge
Data D7 – D0 is moved to
Address A4..A0 here www.ams.com
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Figure 28. Protocol for Serial Data Write with Length = 4
CS
SCLK
SDI
0
RE
S1
RE
S0
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDO
Data D7-D0 is moved to Address
A4-A0 here
Data D7-D0 is moved to Address
A4-A0 +1 here
Data D7-D0 is moved to Address
A4-A0 +2 here
Data D7-D0 is moved to Address
A4-A0 +3 here
Data D7-D0 is moved to Address
A4-A0 +4 here
9.1.3 Read Command
For Read command C0=1.
After the command code C0 and two reserved bits, the address of register to be read has to be provided from the MSB to the LSB. Then one or more data bytes can be transferred from the SPI slave to the master, always from the MSB to the LSB. To transfer more bytes from consecutive addresses, SPI master has to keep active the SPI CS signal and the SPI clock as long as it desires to read data from the slave. Each bit of the command and address sections of the frame have to be driven by the SPI master on the SPI clock transfer edge and the SPI slave on the next
SPI clock edge samples it. Each bit of the data section of the frame has to be driven by the SPI slave on the SPI clock transfer edge and the SPI master on the next SPI clock edge samples it. These edges are selected as per clock polarity settings. In the following figures, two examples of read command (without and with address self-increment) have been shown.
Figure 29. Protocol for Serial Data Read with Length = 1
CS
SCLK
SDI
SDO
1 RES1 RES0 A4 A3 A2 A1 A0
Transfer edge
D7 D6 D5 D4 D3 D2 D1 D0
Sampling edge
Data D7 – D0 at Address A4..A0 is read here
Transfer edge Sampling edge www.ams.com
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Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Figure 30. Protocol for Serial Data Read with Length = 4
CS
SCLK
SDI
1
RE
S1
RE
S0
A
4
A
3
A
2
A
1
A
0
SDO
D
7 6
D D
5 4
D D
3 2
D D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1 0
D
7
D
6
D
5
D
4
D D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4 3
D D
2 1
D
0
D
7
D
6
D
5
D D
4
D
3
D
2
D
1
D
0
Data D7-D0 at
Address A4-A0 is read here
Data D7-D0 at
Address A4-A0 +1 is read here
Data D7-D0 at
Address A4-A0 +2 is read here
Data D7-D0 at
Address A4-A0 +3 is read here
Data D7-D0 at
Address A4-A0 +4 is read here
9.1.4 Timing
In the following figures timing waveforms and parameters are exposed.
Figure 31. Timing for Writing
CS
SCLK
SDI t CPS tCPHD
CLK polarity tSCLKH tSCLKL tDIS t DIH
DATAI
SDO
DATAI
...
...
t CSH
...
DATAI
...
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Revision 1.1
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AS8515
Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Figure 32. Timing for Reading
CS tSCLKH tSCLKL
SCLK
SDI DATAI DATAI tDOD tDOHZ
SDO DATAO (D7) DATAO (D0)
9.2 Bottom Die Registers
This section describes the control registers used in AS8515
Bottom die
. Registers can be broadly classified into the following categories.
Data access registers
Status Registers
Digital signal path control registers
Digital Control registers
Analog Control Registers
Table 49. Control Registers
Addr in
HEX
Register Name
Data Access Registers
00
01
DREG_I1
(ADC Data Register for Current)
DREG_I2
(ADC Data Register for Current)
02
03
DREG_V1
(ADC Data Register for Voltage)
DREG_V2
(ADC Data Register for Voltage)
POR Value R/W
0000_0000
0000_0000
0000_0000
0000_0000
R
R
R
R
D[7:0]
D[7:0]
D[7:0]
D[7:0]
8-bit Control / Status Data
Denotes the Current ADC MSB Byte (ADC_I[15:8])
Denotes the Current ADC LSB Byte (ADC_I[7:0])
Denotes the Voltage ADC MSB Byte (ADC_V[15:8])
Denotes the Voltage ADC LSB Byte (ADC_V[7:0]) www.ams.com
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Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Status Registers
Register Name POR Value R/W
04 STATUS_REG 0000_0000 R
D[3]
D[2]
D[1]
D[0]
D[7]
D[6]
D[5]
D[4]
8-bit Control / Status Data
NOM1/NOM2 Data Ready
NOM2 Threshold Crossover
SBM1 Data Ready
SBM2 Threshold Crossover
APOR status
Data from current channel updated
Data from voltage channel updated
Reserved www.ams.com
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Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name POR Value
Digital Signal Path Control Registers for Current Channel
R/W
05 DEC_REG_R1_I
8-bit Control / Status Data
0100_ 0101 R/W
D[7]
D[6:5]
D[4:1]
D[0]
This bit selects decimation rate is used for current channel. Default is 0 (Down Sampling Rate is 64)
0
1
Down Sampling Rate is 64
Down Sampling Rate is 128
These two bits select division ratio of oversampling frequency clock MOD_CLK to be used as chopper clock, CHOP_CLK.
Default is “10” (divide by 512)
00
01
10
11
Chopper Clock Always High
Divide by 256
Divide by 512
Divide by 1024
These four bits select the decimation ratio of second
CIC stage. Default is “0010” (equal to 4)
0100
0101
0110
0111
0000 1
0001 2
0010
0011
4
8
16
32
64
128
1000
1001
1010
1011
256
512
1024
2048
1100
1101
1110
1111
4096
8192
16384
32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
0
1
Unmask
Mask www.ams.com
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Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
06 DEC_REG_R2_I
POR Value R/W
1100_0101 R/W
D[7]
D[6]
D[5]
D[4]
D[3:2]
D[1:0]
8-bit Control / Status Data
I-Channel Enable, Default 1=enable
V-Channel Enable, Default 1=enable
0
1
Interrupt polarity
Active high
Active low
. Interrupt Mask Control for Current Channel Data
Ready Interrupt on INT pin (Default is 0)
0
1
Unmasked
Masked
These two bits select the source of output 16-bit data in
Normal mode from Current channel. Default is 01
00
01
10
11
FIR / MA Output
CIC2 Output
Dechop/Demod Output
CIC1 Output
These two bits select the source of output 16-bit data in
SBM mode from Current channel. Default is 01
00
01
10
11
FIR / MA Output
CIC2 Output
Dechop/Demod Output
CIC1 Output www.ams.com
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Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
07 FIR CTL_REG_I
POR Value R/W
0000_0100 R/W
D[7]
D[6:3]
D[2:1]
D[0]
8-bit Control / Status Data
0000
0001
0011
0111
This bit selects FIR / MA Filter in Current channel.
Default is 0 (FIR)
0
1
FIR
MA Filter
These bits select the number of data samples for averaging in MA filter in Current channel.
Default is 0000 (bypass) bypass
1
3
7
1111 15
These two bits select the Measurement Path architecture in both Current and Voltage channels.
Default is 10 (Dechopper after CIC)
00
01
10
11
Demodulator after CIC1
Demodulator before CIC1
Dechopper after CIC1
(preferred and suggested)
Demodulator before CIC1 with settled sample
Reserved. Default 0. Do not change www.ams.com
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Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
08
09
Register Name
Digital Control Registers
CLK_REG
(Clock Control Register)
RESET_REG
(Reset Control Register)
POR Value R/W 8-bit Control / Status Data
0010_0000 R/W
1100_0000 R/W
D[7:6]
D[5:4]
D[3:2]
Oversampling frequency clock selection. Default is 00
(high speed (HS) internal Clock)
00
01
Internal HS Clock with No Clock Output
Internal HS Clock with Clock Output
10 External Clock
These two bits select the division ratio for HS clock/ external clock. Default is 10 (division by 4)
00
01
10
11
No division
Divide by 2
Divide by 4
Divide by 8
These two bits select the division ratio of HS clock, by which it should be divided before providing it on CLK pin. Default is 00 (No Division)
00
01
10
11
No Division
Divide by 2
Divide by 4
Divide by 8
D[1] 0
This bit selects the division ratio of LS clock
LS _CLK undivided (Low Speed clock)
1 LS _CLK divide by 2
Reserved D[0]
D[7]
D[6]
Entire device can be soft reset by writing “0” into this register bit. This bit will take a default 1 value on coming out of Reset
Measurement Path can be soft reset by writing “0” into this register bit. This bit will take a default 1 value after
Measurement Path is reset.
D[5:0] Reserved www.ams.com
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Table 49. Control Registers
Addr in
HEX
0A
0B
0C
0D
0E
Register Name
MOD_CTL_REG
(Mode Control Registers)
MOD_Ta_REG1
(Ta Control Register)
MOD_Ta_REG2
(Ta Control Register)
MOD_I
TH
_REG1
(Current Threshold Register)
MOD_I
TH
_REG2
(Current Threshold Register)
POR Value R/W
0000_0000
1000_0000
0000_0000
0000_0000
0000_0000
R/W
R/W
R/W
R/W
8-bit Control / Status Data
D[7:6]
D[5:3]
D[2]
D[1]
D[0]
D[7]
D[6:0]
D[7:0]
These two bits select the operating mode of the Device.
Default is 00 (Normal Mode 1)
00
01
Normal Mode 1
Normal Mode 2
10
11
Standby Mode 1
Standby Mode 2
These three bits select the number of cycles to be ignored before comparison with the set threshold in
Standy Mode. Default is 000 (3 cycles of data)
000
001
010
011
3 cycles of data
4 cycles of data
5 cycles of data
6cycles of data
100
101
110
111
7 cycles of data
8 cycles of data
9 cycles of data
10 cycles of data
This bit controls the CHOP_CLK availability on
CHOP_CLK pin.
Default is 0
0
1
Disabled
Enabled
Enabling the MEN pin to indicate transition from
Standby to Normal Mode.
0
1
Disabled
Enabled
This bit is used to take the device from STOP state to any of the Modes based on D[7:6] selection of this register.
0
1
Retain in STOP state
Enables transition to Normal or Standby
Modes.
0
1
Unit of Ta in SBM1/SBM2. Default is 1
Unit is in milliseconds
Unit is in seconds
MSB value of Ta
Unit of Ta in SBM1/SBM2
LSB value of Ta
D[7:0] MSB bits of 16 bits SBM2 threshold register
D[7:0] LSB bits of 16 bits SBM2 threshold register www.ams.com
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Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
13
14
Register Name
0F
10
(T
MOD_T
MC
_REG1
MC
Control Registers)
(T
MOD_T
MC
_REG2
MC
Control Register)
NOM_I
TH
_REG1 11
12 NOM_I
TH
_REG2
Analog Control Registers
PGA_CTL_REG
(PGA Control Registers)
POR Value R/W
0000_0000 R/W
0000_0000 R/W
0000_0000 R/W
0000_0000 R/W
D[7:0]
D[7:0]
D[7:0]
D[7:0]
8-bit Control / Status Data
MSB value of number of data samples to be dropped from ADC before sending Interrupt in NOM2
LSB value of number of data samples to be dropped from ADC before sending Interrupt in NOM2
Eight MSB bits of NOM2 current threshold register
Eight LSB bits of NOM2 current threshold register
0101_0000 R/W
D[7:6]
D[5:4]
D[3:0]
Setting of Gain G of Current Channel PGA. Default is
01 (G = 25)
00
01
5
25
10
11
40
100
Setting of Gain G in Voltage channel. Default is 01 (G =
25)
00
01
10
11
40
100
Reserved
5
25
PD_CTL_REG_1
(Power Down Control Register)
1100_1111 R/W
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
1
0
1
0
1
0
1
0
1
0
1
Disable Chopper clock to Current channel
Enable Chopper clock to Current channel
Disable Chopper clock to Voltage channel
Enable Chopper clock to Voltage channel
Reserved
Reserved
Disable Current channel PGA
Enable Current channel PGA
Disable Current channel
ΣΔ
Modulator
Enable Current channel
ΣΔ
Modulator
Disable Voltage channel PGA
Enable Voltage channel PGA
Disable Voltage channel
ΣΔ
Modulator
Enable Voltage channel
ΣΔ
Modulator www.ams.com
Revision 1.1
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AS8515
Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
15
POR Value R/W
D[7]
D[6]
D[5]
D[4]
PD_CTL_REG_2
(Power Down Control Register)
1111_0011 R/W
D[3]
16
PD_CTL_REG_3
(Power Down Control Register)
1111_1000
D[1]
D[0]
D[7]
D[6]
D[2]
D[1]
D[0]
D[5]
D[4]
D[3]
D[2]
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8-bit Control / Status Data
Disable CIC1 of both channels
Enable CIC1 of both channels
Disable CIC2 of both channels
Enable CIC2 of both channels
Disable Dechopper in both channels
Enable Dechopper in both channels
Disable FIR in both channels
Enable FIR in both channels
Do not bypass PGA in Current Channel
Default 0
Bypass PGA in Current Channel
Do not bypass PGA in Voltage Channel
Default 0
Bypass PGA in Voltage Channel
Note:
For Automotive Battery measurement, ensure that the PGA is bypassed to connect battery voltage
(attenuated by factor of 21) directly to the
ADC input.
Disable Current Channel Chopper
Enable Current Channel Chopper
Disable Voltage Channel Chopper
Enable Voltage Channel Chopper
Disable Common Mode Reference
Enable Common Mode Reference
Disable Internal Current Source
Enable Internal Current Source
Disable Internal temperature sensor
Enable Internal temperature sensor
Reserved. (Default 1) Do not change
Reserved. (Default 1) Do not change
Data Output in binary numbering system
Data Output in 2’s complement numbering system
Reserved. (Default 0) Do not change
Reserved www.ams.com
Revision 1.1
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AS8515
Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
17
18
19
44
Register Name
ACH_CTL_REG
(Analog Channel Selection
Register)
ISC_CTL_REG
(Current Source Setting Register)
OTP_EN_REG
STATUS_REG_2
POR Value R/W
0000_0000
0000_0000
0000_0000
0000_0000
R/W
R/W
R/W
R
8-bit Control / Status Data
D[7:6]
D[5]
These bits specify the selection of voltage/temperature in Voltage Channel
Default is 00 (Voltage Channel)
00
01
Voltage Channel
External Temperature Channel ETR
10
11
External Temperature Channel ETS
Internal Temperature Channel
Reserved. (Default 0) Do not change
Internal current source switch enable. Default is 0
D[2:0]
D[7]
D[6:0]
D[7]
D[6]
D[5:0]
D[4]
Note:
D4 bit is used for Enabling current source to the channel selected by bits D[7,6] of this register.
0
1
Disabled
Enabled
Enable/disable Internal current source to RSHH pin of
Current channel
D[3]
0
1
Disabled
Enabled
Enable/disable current source switch to RSHL pin of
Current channel
D[2]
0
1
Disabled
Enabled
D[1:0] Reserved
These three bits specify the selection of magnitude of current from the Internal current source. Default is
00000 (0µA).
D[7:3]
00000
00001
00010
00100
01000
10000
11111
0µA
8.5µA
17µA
34.5µA
68µA
135µA
270µA
Reserved
1 Reserved (default = 1) Do not change
Reserved
Status indicating data saturation in Current channel
Status indicating data saturation in Voltage channel
Reserved www.ams.com
Revision 1.1
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AS8515
Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name POR Value
Digital Signal path control registers for Voltage Channel
R/W
45 DEC_REG_R1_V
8-bit Control / Status Data
0100_ 0101 R/W
D[7]
D[6:5]
D[4:1]
D[0]
00
01
10
11
Selection of Decimation ratio for Voltage/Temperature channel.
Default is 0 (Down Sampling Rate is 64)
0
1
Down Sampling Rate is 64
Down Sampling Rate is 128
Division of oversampling clock, which is used as
Chopper Clock. Default is 10 (divide by 512)
Chopper Clock Always High
Divide by 256
Divide by 512
Divide by 1024
0011
0100
0101
0110
Decimation ratio of CIC2. Default is 0010 (4)
0000 1
0001
0010
2
4
8
16
32
64
1011
1100
1101
1110
0111
1000
1001
1010
128
256
512
1024
2048
4096
8192
16384
1111 32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
0
1
Unmasked
Masked www.ams.com
Revision 1.1
58 - 65
AS8515
Datasheet (discontinued) - 4 -W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
46
47
Register Name
DEC_REG_R2_V
FIR CTL_REG_V
POR Value R/W
0000_0100
0000_0000
R/W
R/W
8-bit Control / Status Data
D[7:5]
D[4]
Reserved
Interrupt Mask Control for Voltage channel data Ready
Interrupt on INT pin (Default is 0)
0
1
Unmasked
Masked
These two bits select the source of output 16-bit data in
Normal mode from Voltage channel. Default is 01
D[3:2]
D[1:0]
00
01
10
11
FIR / MA Output
CIC2 Output
Dechop/Demod Output
CIC Output
Reserved
This bit selects FIR / MA Filter in Voltage channel.
Default is 0 (FIR)
D[7]
D[6:3]
0
1
FIR
MA Filter
These bits select the number of data samples for averaging in MA filter in Voltage channel.
Default is 0000 (bypass)
0000 bypass
0001 1
0011
0111
3
7
1111
D[2:0] Reserved
15
Note:
All the registers from address 0x19 to 0x2C are read-only.
www.ams.com
Revision 1.1
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AS8515
Datasheet (discontinued) - A p p l i c a t i o n I n f o rm a t i o n
10 Application Information
Figure 33. Application Diagram
100nF
100nF
1
32
RSHH
2
VREF
3
VCM
4
3.3V
5
AVDD
AVSS
6
ETR
7
ETS
VSENSE_IN
8
9
10
31
11
30
12
29
AS8515
13
28
14
27 26 25
24
23
SDI
22
15
MEN
21
CHOP_CLK
DVDD
20
19
3.3V
DVSS
18
SDO
17
CSB
16
200nF
Optional
22µF
VBAT
SUP
Diode
µC
+
12V
Battery
-
100µohm
Load
Note:
VSENSE_IN, VSENSE_GND, MEN, and CHOP_CLK should be left unconnected.
Note:
Keep the differential input signal lines short, symmetric, and as close as possible. Use of PCB shielding layers is recommended, but consider Eddy currents for fast changes in shunt current and related parasitic signal / ground shift generation.
www.ams.com
Revision 1.1
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AS8515
Datasheet (discontinued) - P a c k a g e D r a w i n g s a n d M a r ki n g s
11 Package Drawings and Markings
The devices are available in a 32-pin MLF (5x5 mm) package.
Figure 34. Package Drawings and Dimensions
AS8515
YYWWVZZ
@
www.ams.com
Revision 1.1
RoHS
Green
61 - 65
AS8515
Datasheet (discontinued) - P a c k a g e D r a w i n g s a n d M a r ki n g s
Symbol
A
A1
A2
A3
L
θ b
D
E e
D1
E1
Min
0.80
0
-
0.30
0º
0.18
Nom
0.90
0.02
0.65
0.20 REF
0.40
-
0.25
5.00 BSC
5.00 BSC
0.50 BSC
4.75 BSC
4.75 BSC
Max
1.00
0.05
1.00
0.50
14º
0.30
Notes:
1. Dimensions and tolerancing conform to
ASME Y14.5M -1994
.
2. All dimensions are in millimeters. Angles are in degrees.
3. Bilateral coplanarity zone applies to the exposed pad as well as the terminal.
4. Radius on terminal is optional.
5. N is the total number of terminals.
Marking: YYWWVZZ.
YY
Last two digits of the manufacturing year
WW
Manufacturing Week
V
Plant Identifier
Symbol
D2
E2 aaa bbb ccc ddd eee fff
N
Min
3.40
3.40
-
-
-
-
-
-
ZZ
Traceability Code
0.10
0.05
0.08
0.10
32
Nom
3.50
3.50
0.15
0.10
@
Sublot identifier
Max
3.60
3.60
-
-
-
-
-
www.ams.com
Revision 1.1
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AS8515
Datasheet (discontinued) - R e vi si o n H i s t o r y
Revision History
Revision
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.0
1.1
Date
Dec 16, 2011
Jan 25, 2012
Mar 07, 2012
Aug 14, 2012
Nov 22, 2012
Mar 22, 2013
Jul 26, 2013
Jul 31, 2013
Nov 18, 2016
Jun 23, 2017
Owner Description
zmo/mbr Initial draft zmo
Updated table information on
Pins 10, 11 updated in the file (Pin Assignments,
)
Updated power dissipation info in Absolute Maximum Ratings (page 7)
zmo/mbr zmo mbr mbr
Updated Operating Conditions, Electrical Characteristics, Ordering
,
,
.
and
updated.
and notes to
, updated information in
Updated AS8515 Block Diagram
.
Updated Block Diagram Figure 1 and max. value of V
REFACC in
Update of document status
Update of Ordering Information (page 64)
section by adding NRND statement
Note:
Typos may not be explicitly mentioned under revision history.
www.ams.com
Revision 1.1
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AS8515
Datasheet (discontinued) - O r d e r i n g I n f o r m a t i o n
12 Ordering Information
The devices are available as the standard products shown in Table 50
.
Table 50. Ordering Information
Ordering Code
AS8515-ZMFP
AS8515-ZMFM
Description
Data acquisition system with power management and LIN transceiver
Delivery Form
Tape & Reel (5000 pcs)
Tape & Reel (500 pcs)
Not Recommended for New Designs!
ams AG is discontinuing production of this device. Final lifetime buy order must be placed by DECEMBER 31, 2017.
Package
32-pin MLF (5x5 mm)
Note:
All products are RoHS compliant and
ams Green
.
Buy our products or get free samples online at www.ams.com/ICdirect
Technical Support is available at www.ams.com/Technical-Support
Provide feedback about this document at: www.ams.com/Document-Feedback
For further information and requests, e-mail us at [email protected]
For sales offices, distributors and representatives, please visit www.ams.com/contact www.ams.com
Revision 1.1
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AS8515
Datasheet (discontinued) - C o p yr i g h t s & D i s c l a i m e r
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
Contact Information:
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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