AMS AS8525 Sensor Interface Datasheet
โฆษณา
โฆษณา
AS8525
LIN Transceiver with Voltage Regulators, Programmable Gain High
Side Amplifier, and Voltage Attenuator
1 General Description
The AS8525 is a companion IC for automotive battery sensor systems for both low-side and high-side current sensing applications.
The device provides two regulated 3.3V supplies from the battery supply, attenuated battery voltage in differential form, and amplified version of a high-side current-sense element’s voltage with a translated common-mode voltage. The device also communicates the system output to a LIN bus.
AS8525 is designed in a high-voltage 0.35µm CMOS process and packaged on QFN-32.
2 Key Features
Operating voltage 4.3V to 18V, max. 42V for 500 ms
Two linear low-drop voltage regulators: VCC = 3.3V with 50mA drive capability
Typical 50µA quiescent current in standby mode
Typical 35µA quiescent current in sleep mode
Precision voltage attenuator with power down facility
- 0.05% ratio drift accuracy and disable
Precision fully-differential programmable gain amplifier (PGA)
- High-voltage to low-voltage common-mode translation
- Gain steps 5, 25, 50, 100
LIN bus transceiver
- Load independent slew control conforming to LIN 2.1
- Short circuit protection
- TX time out fail safe feature
- Over temperature warning and shut down
Power-On Reset with OTP adjustable reset timeout and brownout detection
Over temperature warning & shutdown functions
Operating modes: Normal, Standby, Sleep, Temporary shut down
Microcontroller 4-wire interface
RC oscillator and programmable timer
Optional window watchdog in normal mode and time-out watchdog in standby mode
8 backup registers to store MCU data during VCC shut down
Load dump protection for all battery supplied pins, LIN bus pin and Enable pin
Internal reverse polarity protection (up to -27V) for all batterysensing pins and LIN bus pin
Chip ID for traceability
-40ºC to 115ºC ambient operating temperature
32-pin QFN (5x5) package
3 Applications
The AS8525 is suitable for LIN networked 14V battery sensor slaves for current measurement in positive battery power rail (high side) or in minus rail (PGA is left un-used in that case).
The device is also ideal for general purpose system basis chip for actuator LIN slaves with battery voltage sensing and actuator high side current sensing.
www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - A p p l i c a t i o n s
Figure 1. AS8525 Block Diagram
VSUP
EN
INT
MEN
ALDO
POR-
VSUP
Temp
Limiter
Mode
Control
LIN Wakeup
AS8525
POR-
VCC
Window
Watchdog
Timeout
Watchdog
RESET
Signal Path
Mode Control
OTP Memory
Receiver
VSUP
Control
Registers
Diagnostic
Registers
Backup Registers
VBG_IN
VSUP2
HRSHL
HRSHH
CLK
-
+
VBAT
VSS1
RX
TX
Slew
Control
Transmitter
LIN Transceiver
VCMREF
Generator
CHP
PGA with common-mode translation
AVCC
-
+
G
-
+
Attenuator
CS
SCLK
SDO
SDI
LIN
AVCC
VCC
VSS2
RESET
LRSHH
LRSHL
VBAT_DIV
VBAT_DIVN
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AS8525
Datasheet - C o n t e n t s
Contents
5
8
9
16
17
17
17
18
18
18
18
19
19
19
20
21
23
24
24
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AS8525
Datasheet - C o n t e n t s
25
26
28
31
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AS8525
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
1
VBAT
2
HRSHH
3
VSUP2
4
HRSHL
5
6
VBAT_DIV
7
VBAT_DIVN
8
32 31 30 29 28 27 26 25
AS8525
(QFN-32)
24
VCC
23 AVCC
22
TX
21
RX
20
CS
19 SDO
18
SCLK
17 SDI
9 10 11 12 13 14 15 16
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name
NC
VBAT
HRSHH
VSUP2
HRSHL
NC
VBAT_DIV
VBAT_DIVN
LRSHL
LRSHH
Pin Number
1
2
3
6
7
4
5
8
9
10 www.ams.com/AS8525
Pin Type
Analog Input
Supply
Analog Input
Analog Output
Description
Not connected
Battery voltage input
Battery-side connection to high-side current-sense element
Supply input for the high-side amplifier
Load-side connection to high-side current-sense element
Not connected
Attenuated battery voltage output (differential)
Gained current-sense element voltage output with translated common-mode voltage (differential)
Revision 2.8
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AS8525
Datasheet - P i n A s s i g n m e n t s
AVCC
VCC
EN
VSUP
LIN
NC
VSS1
VSS2
NC
Table 1. Pin Descriptions
Pin Name
VBG_IN
NC
INT
MEN
CLK
RESET
SDI
SCLK
SDO
CS
RX
TX
Pin Number
11
12
13
18
19
20
21
22
14
15
16
17
23
31
32
28
29
30
24
25
26
27
Pin Type
Analog Input
Description
Low noise Bandgap reference voltage input
Digital Input
Not connected
Reference input for time-out Watchdog in the device standby mode
Digital I/O with Pull-Down Enable input for analog signal paths in the device standby mode
Digital Input with Pull-Down Chopper clock input
Digital Output Reset output (active low)
Serial data in
Digital Input
Serial clock
Digital Output / Tristate Serial data out
Digital Input with Pull-Up Chip select
LIN transceiver receive pin
Digital I/O with Pull-Up
LIN transceiver transmit pin
Regulated 3.3V regulated output supply-2 for loads up to 50mA
Supply
Note:
The OTP selection option is common for VCC & AVCC
Regulated 3.3V regulated output supply-1 for loads up to 50mA
Digital Input with Pull-Down Enable input
Supply
Supply input from battery (through external reverse polarity protection device)
Analog Input / Output
Ground
LIN bus
Not connected
Ground
Ground (VCC and AVCC are generated with reference to this ground)
Not connected www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2
may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
Electrical Characteristics on page 8 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
VSUP
VSUP2
VBAT,
HRSHH,
HRSHL
EN
VCC,
AVCC
LIN
Parameter
Supply voltages
Battery voltage inputs
Enable input
Regulated output supplies
I scr
Min
-0.3
-27
-27
-0.3
-0.3
LIN bus
Analog & digital inputs and outputs
-27
-0.3
Input current (latchup immunity) -100
Typ Max
42
42
42
42
7
40
7
100
Units
V
V
V
V
V
V mA
Comments
Maximum allowed potential difference between any two pins in the set HRSHH,
HRSHL and VSUP2 is 0.3V
ESD
P
T tot
R o stg
2
Electrostatic discharge
Norm: AEC-Q100
Total operating power outputs)
1 dissipation (all supplies and
Package thermal resistance
Storage temperature -55
±2
±4
±8
±6
±0.5
±0.1
25
500
150 kV mW
ºC/W
ºC
Norm: AEC-Q100
For VCC, AVCC, TX, RX, Reset, CS, SCLK,
SDO, SDI, EN, VBAT_DIV, VBAT_DIVN,
LRSHH, LRSHL, VBG_IN, CLK, INT, MEN,
VSUP2, HRSHH and HRSHL
VSUP, VBAT
Short of VSUP2, HRSHH and HRSHL
(shorted by shunt)
LIN to VSS1, HBM Model
LIN to VSS1, IEC6100-4-2
LIN to VSS1, CDM
LIN to VSS1, MM
QFN 32 in still air, soldered on JEDEC standard board @115º ambient, static operation = no time limit
T body
Package body temperature 260 ºC
The reflow peak soldering temperature
(body temperature) is specified according to
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-hermetic
Solid State Surface Mount Devices.” The lead finish for Pb-free leaded packages is
“Matte Tin” (100% Sn)
RH
NC
MSL
Relative humidity
(non-condensing)
Moisture sensitivity level
5
3
85 %
Represents a maximum floor time of 168h
1. ESD Human Body model: R=1500 Ω and C=150pF
2. Total power dissipation cannot exceed 0.500W to avoid increase in junction temperature, i.e. greater than 130ºC. VCC LDO can supply current externally, which is not greater than 15mA at 18V VSUP and 18mA at 16V VSUP. AVCC LDO can supply current externally, which is not greater than 10mA at 18V VSUP and 12mA at 16V VSUP.
www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
Table 3. Operating Conditions
Symbol Parameter
VSUP
Supply voltages
Conditions
Regulators after power-on reset
Regulators for power-on reset
Min
4.3
6
4.5
Typ Max
18
Units
V
VSUP2
VBAT,
HRSHH,
HRSHL
Δ VHiSide
LIN
EN
VCC,
AVCC
Δ VCC
VBG_IN
T
AMB
I sup
Battery voltage inputs 4.5
Difference between any two pins in the set HRSHH, HRSHL and VSUP2
LIN bus
Enable input
Regulated output supplies
Difference in regulated supplies
Bandgap reference input
Analog & digital inputs and outputs
Ambient temperature
Supply Current
Maximum junction temperature (T
J
)=130ºC -40
Though the two regulators are individually capable of 50mA, the total current is limited.
0
0
0
0
0
18
18
±0.2
18
18
3.6
±0.2
1.32
3.6
115
65
V
V
6.1 Characteristics of Digital Inputs and Outputs
All pull-up, pull-downs have been implemented with active devices. RX, SDO, RESET have been measured with 100pF load.
Table 4. Characteristics of Digital Inputs and Outputs
Parameter Conditions Min Typ Symbol
EN Input
V
IH
V
IL
I
LEAK
I pd_en
TX, CS, INT Inputs
V
IH
V
IL
I
LEAK
Ipu
CLK, MEN Inputs
V
IH
V
IL
I
LEAK
I pd_spi
SDI, SCLK
V
IH
V
IL
I
LEAK
High level input voltage
Low level input voltage
Input leakage current
Pull down current
High level input voltage
Low level input voltage
Input leakage current
Pull up current
High level input voltage
Low level input voltage
Input leakage current
Pull down current
High level input voltage
Low level input voltage
Input leakage current
EN=VSS
EN=VCC
TX=VCC
TX,CS, INTN pulled down to VSS
CLK, MEN pulled up to VCC
0.8*VCC
-1
30
0.8*VCC
-1
-30
0.8*VCC
-1
30
0.8*VCC
-1
Max
0.2*VCC
+1
100
0.2*VCC
+1
-100
0.2*VCC
+1
100
0.2*VCC
+1
Units
V
V
µA
µA
µA
µA
V
V
V
V
µA
V
V
µA
µA
V
V
V
V
V
V
V
ºC mA www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. Characteristics of Digital Inputs and Outputs (Continued)
Symbol
RX Output
V
OH
Parameter
High level output voltage
V
OL
V
OL
Low level output voltage
I pu_reset
SDO, RESET Output
V
OH
Pull-up current
High level output voltage
Low level output voltage
Conditions
I
OUT
= 1mA, VSUP ≥ 6V
Pulled down to VSS
VSUP ≥ 6V
Min
6.2 Detailed System and Block Specifications
Table 5. System Specifications
Symbol Parameter
Ivsupnom
Conditions
No load on VCC, AVCC, LIN bus in recessive state, Current sense channel ON
Current consumption normal mode
Ivbatnom
Ivsup2nom
Ivsupstdby
Current sense channel ON
No load on VCC, AVCC, LIN bus in recessive state
Ivsupsleep
Ivbatoff
Ivsup2off
Current consumption standby / sleep mode
Voltage sense channel OFF
Current sense channel OFF
Min
Typ Max Units
VSS+0.
4
-100
V
V
µA
VSS+0.
4
V
V
Typ
850
60
600
40
30
Max Units
µA
µA
2
5 www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.2.1 Programmable Gain Amplifier (PGA)
Table 6. Programmable Gain Amplifier (PGA)
Parameter Symbol
G1
G2
G3
G4
Gain
Conditions
DC gain
V
V
V
IN_AMP
ICM_AMP
OCM_AMP
ε
ε p1,G p2,G
Input signal range
Input common-mode voltage
Output common-mode voltage
Gain error
V(HRSHH)-V(HRSHL)
Gx represents typical gain value (x=1,2,3,4) after Offset trimming
V(HRSHH), VSUP2
When AVCC=3.3V
Only for information
Temperature: -40 to 115ºC
@ VSUP2 = 12V
Post system calibration for G1 and G2, referenced to room temperature
1
At room temperature
V(HRSHH), VUSP2 = 4,5V
Without system calibration
T
Settle_AMP
Time for settling to within 0.05% final value
Includes the settling of chopper
V
V
V
V f
THD
V
-3dB AMP
NDin_AMP
C
AMP
L_AMP
BG_AMP
NDBG_AMP
OSin_AMP
OSinT_AMP
3-dB bandwidth
Input referred thermal noise density
(rms)
Total harmonic distortion
Load capacitance
Bandgap reference voltage
Bandgap reference thermal noise density
Input referred offset before trimming
Input referred offset after trimming
G1
G2
G3
G4
This excludes 1/f noise
Guaranteed by design
Till 500Hz single-ended sinusoidal inputs
(after offset trimming).
Guaranteed by design
Single ended (Includes the capacitance presented by the pad and pin of the host chip)
External low noise reference
When noise bandwidth < signal bandwidth, take it as 200nV/ Hz (Noise Bandwidth /
Signal Bandwidth)
Refers to the standalone amplifier without chopper stabilization
Refers to the standalone amplifier without chopper stabilization;
Only at room temperature
Min
4.5
1.5
650
250
150
75
70
1.176
1. This parameter is based on device evaluation and not production tested.
Typ
5
25
50
100
Max
12
1.65
±0.18*5/
Gx
18
1.8
Units
V/V
V
V
V
35
1.2
±0.5
±5
45 nV/ √ Hz dB
100 pF
1.224
200
V nV/ √ Hz
±37.5
mV
±1.5
%
%
µs kHz mV www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.2.2 VCMREF Generator
Table 7. VCMREF Generator
Symbol Parameter
V
CMREF_AMP
Common-mode reference voltage
6.2.3 Voltage Attenuator
Table 8. Voltage Attenuator
Symbol Parameter
RDIV
V
BAT
ε p,RDIV
ε dt1,RDIV
Division ratio
Input voltage range/
Battery voltage range
Ratio error
Ratio drift
(w.r.t Temperature)
ε dt2,RDIV
6.2.4 Voltage Regulators (LDO & ALDO)
Table 9. Voltage Regulators (LDO & ALDO)
Symbol
VSUP
VCC
AVCC
Parameter
Input Supply Voltage
Output Voltage Range
I
LOAD
ICC_SH dVCC1
LDO Load Current
ALDO Load Current
Output Short Circuit Current
Line Regulation
LOREG Load Regulation
CL1
ESR1
CL2
ESR2
CL1
ESR1
CL2
ESR2
Output Capacitor1 LDO
Output Capacitor2 LDO
Output Capacitor1 ALDO
Output Capacitor2 ALDO
Conditions
When AVCC=3.3V
Conditions
Factory option
At room temperature, V
BAT
=12V
Temperature: -25 to 65ºC
@VBAT = 12V
Temperature: -40 to 115ºC
@VBAT = 12V
Conditions
Normal mode
Δ VCC / Δ VSUP for VSUP range
Δ VCC / Δ ICCn
(0.5mA < I
LOAD
< 50mA)
Electrolytic
Ceramic
Electrolytic
Ceramic
Min
1.55
Typ
1.65
Max
1.75
Units
V
Min
4.5
Typ
481
21
12
Max
±0.05
0.1
18
±1
0.1
0.2
Units
V/V
V
%
%
Min
4.3
3.15
0.01
2.2
1
100
0.02
2.2
1
100
0.02
Typ
12
3.3
Units
V
V mA mA mA mV/V mV/mA
Ω nF
Ω
µF
Ω nF
Ω
µF
50
50
250
8
1
10
10
220
1
5
10
220
1
Max
18
3.45
www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.2.5 LIN Transceiver
Table 10. DC Electrical Characteristics
Parameter Symbol
Driver
I bus_lim
I
LIN_V
OL bus_leak_rec
Pull-up resistor
Conditions
Current limitation in Dominant State LIN=VSUP_max
Output Voltage BUS (dominant state), I
LIN
(short-circuit condition tested at V
OL
=40mA
=2.5V)
Normal mode (recessive BUS level on TX pin)
Driver OFF; 7.3V < VSUP < 18;
8V < VBUS < 18, VSUP < VBUS < 1.08 * VSUP
(to be tested at VBUS=18V)
Receiver
I
I bus_leak_dom bus_no_GND
Input Leakage current at receiver
Driver OFF; Vbus=0V; VSUP=12V; VCC=3.3V
VSS=VSUP;
VSUP=12V; 0V < VBUS < 18V, VCC=3.3V
(to be tested at VBUS=18V)
VSUP=VSS; 0V < VBUS < 18V, VCC=VSS
(to be tested at VBUS=18V)
I bus_no_bat
V bus_dom
V bus_rec
V bus_cnt
V hys
V bus_cnt
= (V th_dom
+ V th_rec
)/2
1
V hys
= (V th_dom
– V th_rec
)
1
1. V th_dom
: Receiver threshold of the recessive to dominant LIN bus edge,
V th_rec
: Receiver threshold of the dominant to recessive LIN bus edge
Table 11. AC Electrical Characteristics
Symbol Conditions
LIN Driver, Bus load conditions (C
BUS
; R
BUS
): 1nF; 1k
Ω
/ 6.8nF; 660
Ω
/ 10nF; 500
Ω
D1
Worst case 20Kbps transmission
V th_rec (max)
= 0.744 x VSUP;
V th_dom (max)
= 0.581 x VSUP;
VSUP = 6.0V...18V; t bit
D1 = t bus_rec (min)
= 50
/ (2 x t bit
μ
) s;
OTP selection = High Slew Mode
D2
Worst case 20kbps transmission
D3
Worst case 10.4kbps transmission
V th_rec (min)
= 0.422 x VSUP;
V th_dom (min)
= 0.284 x VSUP;
VSUP = 6V...18V; t bit
D2 = t bus_rec (max)
= 50
/ (2 x t
μ bit
) s;
OTP selection = High Slew Mode
V th_rec (max)
= 0.778 x VSUP;
V th_dom (max)
= 0.616 x VSUP;
VSUP = 6.0V...18V; t bit
= 96 μ s;
D3 = t bus_rec (min)
/ (2 x t bit
)
OTP selection = Low Slew Mode
Min
0.396
0.417
Min
40
20
-1
-1
0.6
0.475
0.05
Typ
Typ
120
40
Max
Max
0.581
20
1
200
2
60
Units
mA mA
100 µA
0.4
VSUP
VSUP
0.525
VSUP
0.175
VSUP
Units
mA
V k
Ω
µA www.ams.com/AS8525 Revision 2.8
12 - 38
AS8525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 11. AC Electrical Characteristics (Continued)
Symbol
D4
Worst case 10.4kbps transmission
Conditions
V th_rec (min)
= 0.389 x VSUP;
V th_dom (min)
= 0.251 x VSUP;
VSUP = 6V...18V; t bit
D4 = t bus_rec (max)
= 96
/ (2 x t
μ bit
) s;
OTP selection = Low Slew Mode
VCC= 3.3V; Propagation delay bus dominant to RX LOW t t dLR t dHR t
RS t wake t t sln nsl rec_deb
C int
VCC= 3.3V; Propagation delay bus dominant to RX HIGH
Receiver Delay symmetry
Wake-up delay time
Transition from standby mode to normal mode
(clock frequency is 128kHz ±25%)
Transition from standby mode to normal mode
(clock frequency is 128kHz ±25%)
Receiver De-bounce time
Internal capacitance of the LIN node
6.2.6 TX Timeout Watchdog
Table 12. TX Timeout Watchdog
Symbol
t lin_wdog
Parameter
Time out period for the dominant state
Conditions
6.2.7 Temperature Limiter
Table 13. Temperature Limiter
Symbol
T sd
T otset
T ret
Parameter
Shut down temperature
Over-temperature warning
Return temperature
Conditions
Junction temperature
Junction temperature
Junction temperature
Min
-2
30
0.6
Min
0.5
Min
155
142
125
Typ
4
6
Typ
1
Typ
170
157
140
Max
0.59
1
250
6
6
2
150
Max
2
Max
185
172
155
Units
µs
µs
µs
µs
Clock cycles
Clock cycles
µs pF
Units
s
Units
ºC
ºC
ºC www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.2.8 Other Modules
Table 14. Other Modules
Symbol Parameter
Vuvr_off VCC under-voltage threshold off (default)
Vuvr_on VCC under-voltage threshold on (default)
Vuvr1_off
VCC under voltage threshold off (factory option)
Vuvr1_on
Vuvr2_off
VCC under voltage threshold on (factory option)
VCC under voltage threshold off (factory option)
Vuvr2_on
Vuvr3_off
Vuvr3_on
Vhyst_vcc
VCC under voltage threshold on (factory option)
VCC under-voltage threshold off (factory option)
VCC under voltage threshold on (factory option)
Hysteresis of under-voltage threshold on/ off VCC t rr
Vsuvr_off
Glitch filter on VCC under-voltage detection
VSUP under-voltage threshold off
Vsuvr_on
WD_TCL
VSUP under-voltage threshold on
WWD non-service time (factory option)
WD_TSV WWD Service time (factory option)
WD_TCL1 WWD non-service time (factory option)
WD_TSV1 WWD Service time (factory option)
WD_TCL2 WWD non-service time (factory option)
WD_TSV2 WWD Service time (factory option)
WD_TCL3 WWD non-service time (factory option)
WD_TSV3 WWD Service time (factory option)
WD_TCL4 WWD non-service time (factory option)
WD_TSV4 WWD Service time (factory option)
WD_TCL5 WWD non-service time (factory option)
WD_TSV5
WD_T t
Res
T shd
WWD Service time (factory option)
TWD service time
Reset period
Temporary shutdown reset active time
Conditions
Rising edge of VCC
Falling edge of VCC
Rising edge of VCC
Falling edge of VCC
Rising edge of VCC
Falling edge of VCC
Rising edge of VCC
Falling edge of VCC
For all OTP options
See Reset Functionality (page 18)
Rising edge of VSUP
Falling edge of VSUP
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
RESET will be generated
RESET will not be generated
T is configured through SPI
Min = -25% and Max = +50%
Min
2.55
2.3
3.0
2.75
Typ
3.5
3.25
4.0
3.75
3.9
3.65
4.4
4.15
0.1
0.25
0.4
4
5.1
0-75
3.8
0-100 0-125
75-150 100-200 125-250
0-60 0-80 0-100
60-120 80-160 100-200
0-45 0-60 0-75
45-90 60-120 75-150
0-150 0-200 0-250
150-300 200-400 250-500
0-120 0-160 0-200
120-240 160-320 200-400
0-90 0-120 0-150
90-180 120-240 150-300
0.75*T T 1.25*T
6
0.1
8 12
1
Max
2.95
2.7
3.4
3.15
Units
V
V
V
V
V
V
V
V
V
µs ms ms ms ms ms ms ms ms ms s
V
V ms ms ms ms s www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.2.9 4-Wire Serial Port Interface
Table 15. 4-Wire Serial Port Interface
Symbol
General
Parameter Conditions
BR
SPI
T
SCLKH
T
SCLKL
Write Timing
t
DIS t
DIH
T
CSH
Read Timing
t
DOD
Bit rate
Clock high time
Clock low time
Data in setup time
Data in hold time
CS hold time
Data out delay t
DOHZ
Data out to high impedance delay Time for the SPI to release the SDO bus
Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity)
t t
CPS
CPHD
Clock setup time
(CLK polarity)
Clock hold time
(CLK polarity)
Setup time of SCLK with respect to CS falling edge
Hold time of SCLK with respect to CS falling edge
T
STNDY_trigger
TX high time from EN falling edge To enter into Sleep/Standby mode
Min
2
2
20
20
10
20
20
5
Typ Max Units
250 Kbps
µs
µs
80
80 ns ns ns ns ns ns ns cycles www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.3 Timing Diagrams
Figure 3. Timing Diagrams for Propagation Delays
TxD
V
BUS
50%
BUS t
df_TXD
95%
50%
100%
RxD
50%
0%
t
df_RXD
5%
t
dr_TXD
t
dr_RXD
50%
Figure 4. Timing Diagram for Duty Cycle According to LIN 2.1 and J2602
t bit t bit
TXD
t bus_dom(max) t bus_rec(min)
LIN
Vth_rec(max)
Vth_dom(max)
Vth_rec(min)
Vth_dom(min) t bus_dom(min) t bus_rec(max) www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
The following modules are described in detail under this section:
Programmable-Gain Amplifier (PGA) / Current-Sense Amplifier (CSA)
Voltage Attenuator
Voltage Regulators (LDO & ALDO)
LIN Transceiver
Temperature Monitor/Limiter
VSUP Under-Voltage Reset
RESET
VCC Under-Voltage Reset
Window Watchdog (WWD)
Timeout Watchdog (TWD)
7.1 Programmable-Gain Amplifier (PGA) / Current-Sense Amplifier (CSA)
The current-sense amplifier primarily serves the purpose of shifting the common-mode level of the signal from around the battery voltage to a low voltage which is nominally half the regulated supply voltage. The input to the amplifier can be optionally chopped for offset and low-frequency noise mitigation. As the name indicates, it also provides a programmable gain for the measurement of different battery current ranges which can be programmed through SPI.
7.2 Voltage Attenuator
A resistive divider is used as a battery voltage attenuator. Like the amplifier, the attenuator can be enabled or disabled through SPI, and in the device standby mode, we additionally need logic high on MEN pin for enabling. Internal reverse polarity protection is provided for VBAT pin.
Figure 5. Attenuator Implementation
VBAT
PD
VBAT_DIV
VBAT_DIVN
7.3 Voltage Regulators (LDO & ALDO)
The device has two low-dropout voltage regulators, named LDO and ALDO, with one-time programmable 3.3V voltage output. The output of the
LDO is VCC and that of the ALDO is AVCC. The regulated voltage choice is common to both the regulators. The regulators are always ON except when the device enters the sleep mode or over-temperature shutdown.
The two regulators have inbuilt short-circuit current limitation feature.
The regulators can be temporarily shut down for hard reset of the external circuitry by configuring the device to temporary shutdown mode through SPI.
The LDO power-up happens when the POR-VSUP event occurs (RESET_VSUP_N switching from low to high), and the ALDO powers up when
POR-VCC event occurs (RESET_VCC_N switching from low to high). The start-up sequence is the same even after a temporary shutdown phase. The ALDO will be switched off if there is an under-voltage on VCC, that is, when RESET_VCC_N switches back to low.
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AS8525
Datasheet - D e t a i l e d D e s c r i p t i o n
7.4 LIN Transceiver
The device has a LIN transceiver with slew-controlled bus driver for controlling the electromagnetic emissions from the LIN bus. Further, the slew rate is independent of the bus load. The transmitter relays the data from the LIN controller (TX pin) to the bus (LIN pin), and the receiver provides the data on the bus to the controller (RX pin). The transceiver conforms to the LIN 2.1 standard.
The LIN transceiver has a timeout watchdog for TX. After the timeout, the LIN bus will be released to the recessive state from the dominant state.
The bus driver has an inbuilt short-circuit current limitation facility to protect the device from damage when there is a short between the bus and the supply.
In addition to the data receiver, there is a low-power receiver active in the device standby/sleep mode which received a wake-up event from the bus to bring the device to normal mode.
7.5 Temperature Monitor / Limiter
The temperature limiter circuit powers down the device when the junction temperature exceeds 170°C (nominal). It also issues an overtemperature warning at 160°C (nominal). The device is powered up again when the junction temperature falls below 140°C (nominal). The overtemperature warning flag is also cleared at this temperature.
The temperature limiter circuit can be optionally disabled through SPI.
7.6 VSUP Under-Voltage Reset
When VSUP drops below VSUVR_ON, the RESET_VSUP_N switches back to low level. This is treated as a master reset and will have the highest priority over all other signals. In this case, the regulators, LIN transceiver, and all other blocks are shut off, and the device comes to a complete stop. The device returns to the normal mode when VSUP rises over VSUVR_OFF again irrespective of the mode it was in prior to this under-voltage condition.
7.7 RESET
RESET module generates an active-low reset signal for the external circuitry supplied by VCC. The behavior of the reset output is depicted in
detail in the subsequent sections.
The reset period can be one-time programmed to 4, 16, and 32 ms with a default value of 8 ms.
Figure 6. Reset Functionality
VSUP
VCC
VUVR_OFF
VUVR_ON t
Res
RESET
T>Tj T<Tj t
rr
t
Res
Start-up
Over-temp
Shutdown
t<t
rr
Glitch in
VSUP
t
Res
t
Res
t
Res
VSUP UV
Reset by
Watchdog
SC Current
Limitation Active www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - D e t a i l e d D e s c r i p t i o n
7.8 VCC Under-Voltage Reset
When VCC drops below VUVR_ON, the RESET_VCC_N switches back to low level. This event generates a reset output. The reset output is released again only a reset period (t
Res
) later after VCC rises above VUVR_OFF. If the time difference between the VCC falling below VUVR_ON and rising above VUVR_OFF is less than t rr
, there will be no reset output. The reset output is affected in the conditions like over-temperature shutdown and temporary shutdown only through VCC under-voltage.
VCC under-voltage reset thresholds (VUVR_ON and VUVR_OFF) can be chosen by OTP.
7.9 Window Watchdog (WWD)
The Window Watchdog ensures that the Microcontroller is properly functioning in the normal mode of the device. The Watchdog is started after a reset and the Microcontroller needs to send a trigger in the window of WD_TSV (service time). If the trigger occurs early, in the period WD_TCL, or after WD_TSV, a reset output is generated.
The Microcontroller can access the trigger bit for the watchdog through SPI. The WWD can be enabled and the window times can be programmed through OTP bits.
Figure 7. Window Watchdog Functionality
Trigger via SPI
Period
Non-Service time (WD_TCL)
50 %
Trigger restart period
Service time (WD_TSV)
100 %
Last trigger
Wrong trigger
(RESET generation)
Earliest point for correct trigger
(No RESET)
Correct trigger
(No RESET)
Latest point for correct trigger
(No RESET)
Wrong trigger
(RESET generation)
7.10 Timeout Watchdog (TWD)
The Timeout Watchdog ensures that the Microcontroller is in proper functional state in the device standby mode. The Watchdog timer will be started upon a rising edge on INT and will generate a reset output if the Microcontroller doesn’t send a trigger before the timeout.
The Microcontroller can access the trigger bit for the watchdog through SPI. The TWD can be enabled by OTP and the timeout interval can be programmed through SPI.
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
The AS8525 chip consists of a programmable gain amplifier, a resistive divider, two low drop-out regulators, and a LIN bus transceiver.
Additionally integrated are a RESET unit with a power-on-reset delay and programmable window watchdog and timeout watchdog timers. It also includes a watchdog time-out on LIN TX node to indicate if the Microcontroller is stuck in a loop and the LIN bus remains in dominant time for more than the necessary time.
8.1 Operating Modes and States
The device provides four main operating modes ‘normal’, ‘sleep/stand-by’ (programmed by OTP), “temporary shutdown” and ‘thermal shutdown’.
The LIN transceiver can be programmed to operate with lower slew in the normal mode. A detailed state transition table is shown in the following
8.1.1 Normal Mode
This is the mode after the power-up. In this mode, voltage regulators, LIN transceiver, window Watchdog are all active. The PGA and resistive divider can be enabled through SPI. LIN transceiver is capable of sending the TX data from micro-controller to the LIN bus at a maximum rate of
20Kbps.
8.1.2 Standby Mode
Standby mode is a functional low-power mode and is entered by pulling EN to ground. The LIN transceiver, PGA, resistive divider, window watchdog, and TX timeout watchdog circuits are disabled. But, it is possible to selectively enable the voltage and current measurement paths in this mode using an externally generated measurement enable (MEN) signal on the MEN pin. The timeout Watchdog can be enabled in this mode to make sure that the Microcontroller is active.
8.1.3 Sleep Mode
Sleep mode is the current saving mode. The voltage regulators are disabled in this mode. Also, the PGA, resistive divider, LIN transceiver, and the reset and Watchdog units are switched off. The LIN wake-up circuit and oscillator are active. Wake-up is possible only through remote wakeup through LIN pin pulling it to dominant state for 100us.
8.1.4 Temporary Shutdown Mode
In this mode, the regulators are powered down and the VCC, AVCC are pulled down. This provides an alternative way to reset those components powered by AS8525. The feature has to be enabled by an OTP bit and can be invoked through SPI. The LIN transceiver along with the LIN wake-up circuit is powered down. No remote wake-up functionality is possible. LIN bus enters into recessive state. The system goes out of this mode to normal mode after the timeout of an internal timer.
8.1.5 Thermal Shutdown Mode
If the junction temperature T
J
is higher than T sd
, the device will be switched into the thermal shutdown mode. The regulators and the transceiver are completely disabled. Only the over-temperature monitor is active. As soon as the temperature returns back to T ret
, the system enters normal mode.
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.2 State Transition Diagram
The complete functional state machine of AS8525 is shown in this section. Soft states like “TXWD Wait” and “Standby Wait”, and other wait states have also been included here for completeness.
Figure 8. Finite State Machine Model of AS8525
! temp160
INIT0
por_vsup
OTP LOAD OVTEMP
temp160 temp160 temp160 temp160 temp160 temp160 otp_load
Temp Shut
SLEEP
128msec
RESET
TIMEOUT
Tem p rwake
Standby & sleep reset timeout
! por_vcc || wwdtimeout
NORMAL
p m wn do ut sh utdow n
STANDBY
STANDBY
WAIT
! sta ndb y stan dby
! por_vcc sh utd ow n
Te m p rw ake
_w ait
! por_vcc
! por_vcc || wwdtimeout
TXWD WAIT
temp160
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Table 16. Transition Table
Transition
From mode
Normal Mode
Stand-By Mode
Temporary
Shutdown
Mode
Over-
Temperature
Mode
To mode
Stand-By
Sleep
Over-
1
Temporary
Shutdown
Over-
Temperature
2-Wire Interface
2-Wire Interface
(This is a testing condition only)
Normal Mode
Temporary
Shutdown
Over-
Temperature
Normal (LW)
Normal (RW)
Temporary
Shutdown
Temperature
Normal
Normal
Normal
Sleep Mode
3
Over-
Temperature
Power Off All States
1. Chosen by OTP option
2. Effect of Transition
3. Cause for Transition
LIN
X-RS
RX
X-H
2
TX
H
3
X-RS
X-H
2
H
3
EN
H-L
3
H-L
3
X-RS
X-RS
X
X
X-RS
X-H
2
X-RS
X-H
2
X
X
RS
RS
RS-X
RS-X
RS-X
RS
X
Interface
X-H
X-H
X
X
H-X
2
H-X
2
H
H
2
2
H-X
H-X
H-X
H
X
2
2
2
2
2
2
X
X
H-L
3
H-L
3
X
X
X
X
H
H
H
X
X
X
X
X
H
X
H
X
X
L-H
3
X
L
L
X
X
X
X
X
Reg.
0x05
D0
L
L
H
3
L
L
L
H
L
L
L
3
H
3
L
L
L
L
L
X
Flags rwake Uvbat
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OT inactive inactive inactive inactive set set set set inactive inactive inactive inactive inactive set
Uvcc set set
Comments
TX is high for
T
STNDY_trigger
TX is high for
T
STNDY_trigger
1
The Control Bit is set through the 4-Wire SPI interface
Temperature monitor output asserted
(covered by scan)
TX goes High to low within T tx_SP_trigger
Window.
Completion of 2-Wire
Read/Write command
Completion of 2-Wire
Write command to 0x05
Temperature monitor output asserted
(covered by scan) inactive inactive set
X
X
X
X set
X
X
X
X
X
X
X
X
X
L-H
3 inactive inactive Remote Wake up Event inactive set
The Control Bit is set through the 4-Wire SPI interface set set
Temperature monitor output asserted
(covered by scan) inactive clear
Internal 128ms timer expired clear inactive set clear clear hold
Temperature monitor output de-asserted
(covered by scan)
Remote Wake up Event occurred on LIN
Temperature monitor output asserted
(covered by scan)
X X www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Note:
L = low state, H = high state, OT = Over-temperature Reset, Uvcc = Under-voltage VCC, Uvbat = Under-voltage VBAT, rwake =remote wake, X = don’t care.
8.3 Initialization
When the power supply is switched on, when VSUP > VSUVR_OFF, RESET_VSUP_N becomes high. This starts the regulator LDO with 3.3V and Vuvr_off option of 2.75V. When VCC > Vuvr_off (2.75V), active-low PORN_2_OTP is generated and the regulator ALDO is turned on with
3.3V. The rising edge of PORN_2_OTP loads contents of fuse onto the OTP latch after load access time T
Load
. LOAD_OTP_IN_PREREG signal loads contents of OTP latch onto a register. This register provides the actual settings of LDO (and ALDO), Vuvr_off and Reset Timeout period
T
Res
. This is done as the OTP block is powered by the VCC. If VCC > Vuvr_off (phase 2), Reset timeout is restarted. RESET signal is deasserted after Reset Timeout period T
Res
(phase 2) and then device enters into normal mode. The circuit also needs to initialize correctly for very slow ramp rates on VSUP (of the order of 0.5V/min).
Figure 9. Initialization Sequence for AS8525
VSUP_POR_Threshold
VSUP
RESET_VSUP_N
Device
Settings
LDO Off
PHASE 1
LDO On
VCC Por Threshold = 2.75V
LDO setting = 3.3V
Reset Timeout = 4msec
VCC_POR_Threshold
VCC
AVCC
RESET_VCC_N
PORN_2_OTP
LOAD_OTP_IN_
PREREG
6 Cycles of
RC-Oscillator
RESET
PHASE 2
LDO On
VCC Por Threshold = from OTP Block
LDO setting = 3.3V
Reset Timeout = from OTP Block
LDO settings to 3.3 V
LDO settings to 3.3 V
If Phase 1 POR threshold != Phase 2 POR threshold
Tres = Reset Timeout from OTP Block
If Phase 1 POR threshold == Phase 2 POR threshold
Tres = Reset Timeout from OTP Block
Table 17. VSUP>Vsuvr_on and VCC<Vuvr_on
Block
TRANSCEIVER=Enabled (disabled only during initial VSUP ramp-up)
LDO=Enabled (disabled only during initial ramp-up)
RELAY DRIVER=Enabled
RESET BLOCK=Enabled
RESISTIVE DIVIDER=Enabled www.ams.com/AS8525 Revision 2.8
Output Signal
LIN=high-z, RX=follows VCC…
VCC=low…
LDRIVE1=high… LDRIVE2=high…
RESET=high-z…
VBAT=high…, VBAT_DIV=enabled
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Table 18. VSUP<Vsuvr_on
Block
TRANSCEIVER=Disabled
LDO=Disabled
RELAY DRIVER=Disabled
RESET BLOCK=Disabled
RESISTIVE DIVIDER=Disabled
Output Signal
LIN=high-z, RX=high-z…
VCC=low
LDRIVE1=high LDRIVE2=high
RESET=high-z
VBAT=high, VBAT_DIV=low
8.4 Wake-Up
When the device enters sleep/standby mode, it can be brought back to the normal mode with the BUS interface. A dominant state on the BUS for t wake
will result in the device wakeup.
8.5 LIN BUS Transceiver
The AS8525 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed by a de-bouncing unit.
8.5.1 Transmit Mode
During transmission the data at the pin TX will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit.
Transmitting will be interrupted in the following cases:
Sleep mode
Thermal Shutdown active
Master Reset (VSUP < Vsuvr_on)
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS>VSUP). No additional termination resistor is necessary to use the
AS8525 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1k Ω resistor in series with a diode to VBAT.
8.5.2 Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin RX. Short spikes on the bus signal are suppressed by the implemented debouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely observed.
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 10. Receive Mode Impulse Diagram
BUS
60%
50%
40%
V thr_max
V thr_hys
V thr_min
V thr_cnt t < t deb_BUS
RX t < t deb_BUS
8.6 RX and TX Interface
8.6.1 Input TX
The Tx input controls directly the BUS level. LIN Transmitter acts like a slew-controlled level shifter. A dominant state (low) on TX leads to the
LIN bus being pulled low (dominant state) too. The TX pin has an internal active pull up connected to VCC. This guarantees that an open TX pin generates a recessive BUS level.
Figure 11. TX Interface
MCU
VCC
VCC
AS8525
RC-Filter
(10ns)
I
PU_TXD
TX
8.6.2 Output RX
The received BUS signal will be output to the RX pin:
BUS < Vthr_cnt – 0.5 * Vthr_hys → RX = low
BUS > Vthr_cnt + 0.5 * Vthr_hys → RX = high
This output is a push-pull driver between VCC and GND with an output current of 1mA.
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 12. RX Interface
AS8525
VCC
RX
MCU
8.7 MODE Input EN
The AS8525 is switched from normal mode to the standby/sleep mode with a falling edge on EN and keeping TX high for T
STNDY_trigger
time.
Device is switched from standby mode to normal mode with a rising edge at the EN pin. The mode change for AS8525 with a falling edge on EN can be done independently from the state of the transceiver bus. The device enters into Serial port mode by forcing EN low and driving TX high to low within T tx_SP_trigger
time after EN forced to low. This ensures the direct control of device to enter into standby/sleep mode by microcontroller using EN pin.
Figure 13. EN Pin Functionality
EN
TX
T tx_su
Normal
Mode
T
STNDY_trigger
T tx_hd
Standby/Sleep
Mode
T tx_su
Normal
Mode
Entry into
Serial Port
Mode
T en_ENSCLK
RD
WR LEN1 LEN0 A4
T tx_SP_trigger
Serial Port
Mode
D3 D2 D1
D0
Normal
Mode
The EN input has an internal active pull down to secure that if this pin is not connected, a low level will be generated.
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 14. Enable Interface
V
BAT
C
IN
+
EN
VSUP
LIN
VSS
VBAT
VCC
RESET
TX
RX
C
LOAD
+
+3.3V
MCU
If the application doesn’t need the low-power modes of the device, a direct connection of EN to VCC is possible. In this case the AS8525 operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via VSUP signal as shown below.
Figure 15. EN Connection for Permanent Normal Mode
V
BAT
C
IN
+
EN
VSUP
LIN
VSS
VCC
RESET
TX
RX
C
LOAD
+
+3.3V
MCU
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.8 4-Wire SPI Interface
SPI interface is essentially used for programming the gain of the PGA, to enable the PGA and resistive attenuator in the standby mode, to temporarily shutdown the LDOs, etc. The SPI interface can also be used as interface between the AS8525 and an external micro-controller to configure the device and access the status information. The interface is a slave and then only the microcontroller can start the communication.
The SPI protocol is very simple and the length of each frame is an integer multiple of byte except when a transmission is started. Basically each frame has 1 command bits, 5 address/configuration bits, 1 or more data bytes. SPI clock polarity settings depend on the value of the SCLK on the CS falling edge. This setting is done on each start of the SPI transaction. During the transaction SPI clock polarity will be fixed to the settings done. On the CS falling edge the values on SCLK signal decide setting of the active SPI clock edge for data transfer (see Table below).
Table 19. CS and SCLK
CS SCLK
FALL
FALL
ANY
LOW
HIGH
ANY
Description
Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock.
Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock.
Serial data transfer edge is unchanged.
8.8.1 SPI Frame
A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of bytes. Command is coded on the 1 first bit, while address is given on LSB 5 bits (see table below).
Table 20. Command Bits
C0
Command Bits
Reserved Reserved A4
Register Address or Transmission Configuration
A3 A2 A1 A0
C0
0
1
Command
WRITE
READ
<A4:A0>
ADDRESS
ADDRESS
Description
Writes data byte on the given starting address.
Reads data byte from the given starting address.
If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling), the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.
8.8.2 Write Command
For Write command C0 = 0.
After the command code C0 and two reserved bits, the address of register to be written has to be provided from the MSB to the LSB. Then one or more data bytes can be transferred, always from the MSB to the LSB. For each data byte following the first one, used address is the incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge and the SPI slave on the next SPI clock edge samples it. These edges are selected as per clock polarity settings. In the following figures two examples of write command (without and with address self-increment.
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 16. Protocol for Serial Data Write with Length = 1
CS
SCLK
SDI
SDO
0
RES1 RES0
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Transfer edge Sampling edge
Data D7 – D0 is moved to Address A4..A0 here
Figure 17. Protocol for Serial Data Write with Length = 4
CS
SCLK
SDI
0
S
0
R
E
S
1
R
E
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDO
Data D7-D0 is moved to Address
A4-A0 here
Data D7-D0 is moved to Address
A4-A0 +1 here
Data D7-D0 is moved to Address
A4-A0 +2 here
Data D7-D0 is moved to Address
A4-A0 +3 here
Data D7-D0 is moved to Address
A4-A0 +4 here
8.8.3 Read Command
For Read command C0=1.
After the command code C0 and two reserved bits, the address of register to be read has to be provided from the MSB to the LSB. Then one or more data bytes can be transferred from the SPI slave to the master, always from the MSB to the LSB. To transfer more bytes from consecutive addresses, SPI master has to keep active the SPI CS signal and the SPI clock as long as it desires to read data from the slave. Each bit of the command and address sections of the frame have to be driven by the SPI master on the SPI clock transfer edge and the SPI slave on the next
SPI clock edge samples it. Each bit of the data section of the frame has to be driven by the SPI slave on the SPI clock transfer edge and the SPI master on the next SPI clock edge samples it. These edges are selected as per clock polarity settings. In the following figures, two examples of read command (without and with address self-increment) have been shown.
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 18. Protocol for Serial Data Read with Length = 1
CS
SCLK
SDI
SDO
1 RES1
RES
0
A4 A3 A2 A1 A0
Transfer edge
D7 D6 D5 D4 D3 D2 D1 D0
Sampling edge
Data D7 – D0 at
Address A4..A0 is read here
Transfer edge Sampling edge
Figure 19. Protocol for Serial Data Read with Length = 4
CS
SCLK
SDI
1
S
1
R
E
S
0
R
E
A
4
A
3
A
2
A
1
A
0
SDO
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Data D7-D0 at
Address A4-A0 is read here
Data D7-D0 at
Address A4-A0 +1 is read here
Data D7-D0 at
Address A4-A0 +2 is read here
Data D7-D0 at
Address A4-A0 +3 is read here
Data D7-D0 at
Address A4-A0 +4 is read here
8.8.4 Timing
In the following figures timing waveforms and parameters are exposed.
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 20. Timing for Writing
CS
SCLK
SDI t
CPS t
CPHD
CLK polarity t
SCLKH t
SCLKL t
DIS t
DIH
DATAI
SDO
Figure 21. Timing for Reading
DATAI
...
...
t CSH
...
DATAI
...
CS
SCLK
SDI DATAI
SDO t
SCLKH t
SCLKL
DATAI
DATAO (D7) t
DOD
DATAO (D0) t
DOHZ
8.9 Configuration and Diagnostic Registers
The serial interface can be used for communication between AS8525 and an external microcontroller. The device is only a slave and the microcontroller has to initiate the communication. The device can be configured by writing into the control registers and the diagnostic information can be read out from the diagnostic registers.
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.9.1 Register Definitions
A total of 32 registers, each of 8-bits which include configuration, diagnostic, and backup are available. The registers can be accessed using the
2-wire or the 4-wire serial interface. Table 21 provides a description of all registers.
Table 21. Registers
Addr Register Name Default Value RD/WR
Configuration and Control Registers
0x00
Reserved
0x01
Reserved
0 x 02
Reserved
Description
0 x 03
0 x 04
0 x 05
0 x 06
Device
Configuration
Register
Device Control
Register
On POR_VSUP
0000_0001
Temporary
Shutdown
Register
Window Watch
Dog Trigger
Register
On POR_VCC
0000_1100
On POR_VCC
0000_0000
On POR_VCC
0000_0000
RD/WR
RD/WR
RD/WR
WR
D0
Reserved
D1
Reserved
D2
Enable/Disable Over-Temperature Monitor. (0-Disabled, 1-Enabled)
D3
Enable/Disable LIN Transceiver. (0-Disabled, 1-Enabled)
D4- D7
Reserved
D0
High Slew / Low Slew control.
1 High Slew mode
0 Low Slew Mode
D1- D7
Reserved
D0
Temporary shutdown control bit
1 Enter temporary shutdown
D1- D7
Reserved
D0
Window Watchdog Trigger
D1
Timeout Watchdog trigger bit
Upon a trigger, the bit will be cleared within 2 internal clock cycles.
D2- D7
Reserved
0 x 07
Reserved
0x0A
Signal Path
Control Register
On POR_VCC
0000_0000
RD/WR
D0
Reserved
D1
Enable/Disable current channel chopper (0 Disabled, 1 Enabled)
D2
Reserved
D3
Reserved
D4
Enable/Disable voltage attenuator (0 Disabled, 1 Enabled)
D5
Enable/Disable PGA (0 Disabled, 1 Enabled)
D6-D7
PGA gain selection
10 00 Gain-5, 01 Gain-25, 10 Gain-50, 11 Gain-100
0x0B Reserved
0x0C Reserved
0x0D Reserved
0x0E
Watchdog Timer
Control Register
On POR_VCC
0000_0000
RD/WR
D0
Timer resolution
0 1 second, 1 32 seconds
D1-D7
Timeout period
If D0=1, then timeout period = D[7:1]*64*0.512 seconds, else timeout period =
D[7:1]*0.512 seconds
0x0F Reserved www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Table 21. Registers
Addr Register Name Default Value RD/WR
Backup Registers
Description
8 backup registers
These registers can be used by MCU to backup any system configuration before sending the device to sleep mode.
0x10
………
0x17
Backup-0
……………
Backup-7
On POR_VSUP
0000_0000
RD/WR
If Test Control Register D[5] =1, Backup-0 to Backup-3 are used for testing connectivity between OTP and digital modules.
Backup-0 = OTP[25:32]
Backup-1 = OTP[33:40]
Backup-2 = OTP[41:47]
Backup-3 = OTP[48:49]
Diagnostic Registers
0 x 08
0 x 09
Diagnostic
Register 1
Diagnostic
Register 2
On POR_VSUP
0000_0011
On POR_VSUP
0000_0000
RD
RD
D7-D0 = DR[7:0]
8-LSB bits of the 24-bit Diagnostic Register.
D0
POR-VSUP (set when VSUP < Vsuvr_on, cleared after µC read)
D1
UVVCC Under-voltage VCC (set when VCC < Vuvr_on, cleared after µC read)
D2
OTEMP160 Over-temperature Reset. (set when temp > T sd read)
, cleared after µC
D3
OTEMP140 Over-temperature warning (set when temp > T otset
, cleared after
µC read)
D4
OVVBAT Overvoltage VBAT. (set when VSUP > Vovthh, cleared after µC read)
D5
Reserved
D6
RWAKE Remote Wakeup. (set on Remote Wakeup event on LIN Bus, cleared after µC read)
D7
WWDT Window watchdog timeout. (set on failure of Window watchdog timeout, cleared after µC read)
D7-.D0 = DR[15:8]
Next 8 LSB bits of the 24 bit Diagnostic Register.
D0
TXTIMEOUT Tx timeout of 1sec. (set on TX low > 1sec, cleared after µC read)
D1
(TEMPSHUT) This bit is set on entering into temporary shutdown state and cleared after µC read.
D2
Set on failure of timeout Watchdog trigger, cleared after µC read
D7- D3
Reserved www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - P a c ka g e D r a w i n g s a n d M a rk i n g s
9 Package Drawings and Markings
The devices are available in a 32-pin QFN (5x5) package.
Figure 22. 32-pin QFN (5x5) Package
AS8525
YYWWIZZ
11L @
E2
D1
E1 aaa e
D2
D
E
Symbol
A
A1
A2
A3
L
Θ b bbb ccc ddd eee fff
N
-
-
-
-
-
-
Min
0.80
0
-
0.35
0º
0.18
3.40
3.40
Nom
0.90
0.02
0.65
0.20 REF
0.40
-
0.25
5.00 BSC
5.00 BSC
0.50 BSC
3.50
3.50
4.75 BSC
4.75 BSC
0.15
0.10
0.10
0.05
0.08
0.10
32
Max
1.00
0.05
1.00
0.45
14º
0.30
3.60
3.60
-
-
-
-
-
-
Green
RoHS
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AS8525
Datasheet - P a c ka g e D r a w i n g s a n d M a rk i n g s
Marking Info:
1st line is AS8525 - Product Name
2nd Line is YYWWIZZ - Date Code
3rd line is 2 numbers and 1 letter in a row in top down order of factory option designators. e.g. 11L in Fig. 22 3rd line stands for attenuator ratio=21, Window Watchdog disabled.
3rd line @ at the right: sublot identifier
Marking for default option:
AS8525
YYWWIZZ
@
For other factory options please contact ams sales force for quotation, marking and order code.
Notes:
1. Dimensioning and tolerancing conform to
ASME Y14.5M-1994
.
2. All dimensions are in millimeters, angle is in degrees.
3. Coplanarity applies to the exposed heat slug as well as the terminal.
4. Radius on terminal is optional.
5. N is the total number of terminals.
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AS8525
Datasheet - R e v i s i o n H i s t o r y
Revision History
Revision
0.1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Date
Oct 20, 2008
Nov 02, 2009
Oct 11, 2012
Nov 23, 2012
Dec 31, 2012
Mar 14, 2013
Apr 17, 2013
Apr 19, 2013
May 17, 2013
Dec 22, 2014
Jan 13, 2015
Jan 19, 2015
Jan 28, 2015
Mar 16, 2015
Description
Initial revision
Updated the entire datasheet according to spec 2.1
Removed LDO 5V option, added Section 6.1 Characteristics of Digital Inputs and Outputs
Updated Section 6.2.1 Programmable Gain Amplifier (PGA)
Updated ordering table.
Removed 5V LDO option, Removed SCLK & SDI pins and added Marking Information to Section 9.
Updated
& Section 6.2.3 Voltage Attenuator
Updated Marking Information to Section 9
Updated T
AMB
to 115ºC, Footnote added to P tot in
Added note to
Updated
Updated marking code
- gain error & modified marking code
and Ordering Information section
Updated marking for default option
Note:
Typos may not be explicitly mentioned under revision history.
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AS8525
Datasheet - O r d e r i n g I n f o rm a t i o n
10 Ordering Information
The devices are available as the standard products shown in Table 22
.
Table 22. Ordering Information
Ordering Code
AS8525-AQFP
1
Description
High Side current sensor companion IC
High Side current sensor companion IC
AS8525-AQFM
AS8525-AQFP-21
2
High Side current sensor companion IC
High Side current sensor companion IC
1. For default version (attenuator ratio 481)
2. Device version for attenuator ratio 21
Delivery Form
Tape and Reel (4000 pcs)
Tape and Reel (500 pcs)
Tape and Reel (4000 pcs)
Tape and Reel (500 pcs)
Note:
All products are RoHS compliant and ams green.
Buy our products or get free samples online at www.ams.com/ICdirect
Technical Support is available at www.ams.com/Technical-Support
Provide feedback about this document at: www.ams.com/Document-Feedback
For further information and requests, e-mail us at [email protected]
For sales offices, distributors and representatives, please visit www.ams.com/contact
Package
32-pin QFN (5x5)
32-pin QFN (5x5)
32-pin QFN (5x5)
32-pin QFN (5x5) www.ams.com/AS8525 Revision 2.8
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AS8525
Datasheet - C o p y r i g h t s & D i sc l a i m e r
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
Contact Information:
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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