NXP TEA2209T Active Bridge Rectifier Controller new User Guide
NXP TEA2209T is an active bridge rectifier controller that offers significant efficiency improvements by eliminating forward conduction losses found in traditional diode bridges. It directly drives four external MOSFETs, reducing power consumption and improving THD. With integrated X-capacitor discharge and self-supplying features, this IC is ideal for high-efficiency power supplies in adapters, servers, telecom, PCs, and TVs.
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UM11493
TEA2209DB1584 active bridge rectifier controller demo board
Rev. 1 — 29 January 2021 User manual
Document information
Information Content
Keywords
Abstract
TEA2209T, TEA2209DB1584, active bridge rectifier controller, X-capacitor discharge, self-supplying, high efficiency, traditional diode bridge, power supply, demo board
The TEA2209T is an active bridge rectifier controller replacing the traditional diode bridge. Using the TEA2209T with low-ohmic high-voltage external
MOSFETs significantly improves the efficiency of the power converter as the typical rectifier diode-forward conduction losses are eliminated. In addition, the TEA2209T includes an X-capacitor discharge function. To reduce power consumption at a standby condition, an external signal via the COMP pin can disable the TEA2209T. This user manual describes how the TEA2209DB1584 demo board can be used to replace the traditional diode bridge. This demo board contains a TEA2209T and four low-ohmic high-voltage MOSFETs.
NXP Semiconductors
Revision history
Rev Date
v.1
20210129
Description
Initial version
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1 Introduction
Note:
This product has not undergone formal EU EMC assessment. As a component used in a research environment, it is the responsibility of the user to ensure that the finished assembly does not cause undue interference when used. It cannot be CE marked unless assessed.
WARNING
Lethal voltage and fire ignition hazard
The non-insulated high voltages that are present when operating this product, constitute a risk of electric shock, personal injury, death and/ or ignition of fire. This product is intended for evaluation purposes only.
It shall be operated in a designated test area by personnel qualified according to local requirements and labor laws to work with noninsulated mains voltages and high-voltage circuits. This product shall never be operated unattended.
This user manual describes the TEA2209DB1584 demo board. It provides a functional description, supported with instructions on how to connect the board to obtain the best results and performance.
The TEA2209T is a product of a new generation of active bridge rectifier controllers replacing the traditional diode bridge.
Using the TEA2209T with low-ohmic high-voltage external MOSFETs significantly improves the efficiency of the power converter as the typical rectifier diode-forward conduction losses are eliminated. Efficiency can improve up to about 1.4 % at 90 V (AC) mains voltage.
The TEA2209T is intended for power supplies with a boost-type power-factor controller as a first stage. The second stage can be a resonant controller, a flyback controller, or any other controller topology. It can be used in all power supplies requiring high efficiency such as adapters, server and telecom power supplies, desktop PCs, all-in-all PC power supplies, and television power supplies.
L
1
VCCHL 2
GATEHL
3
HVS
4
GATELL
VCC
GND
COMP_POL
7
8
5
6
Figure 1. Pin configuration diagram (SO16)
IC
aaa-038079
16
VR
15 HVS
14
GATEHR
13
VCCHR
12 R
11
HVS
10 GATELR
9 COMP
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1.1 Features
•
Elimination of forward conduction losses of the diode rectifier bridge
•
Very low IC power consumption (2 mW)
•
Integrated high-voltage level shifters
•
Directly drives four rectifier MOSFETs
•
Very low external part count
•
Integrated X-capacitor discharge (2 mA)
•
Self-supplying
•
Full-wave drive improving total harmonic distortion (THD)
•
Undervoltage lockout (UVLO) for high-side and low-side drivers
•
Drain-source overvoltage protection for all external power MOSFETs
•
Gate pull-down currents at start-up for all external power MOSFETs
•
Disable function for all external power FETs
2 Safety warning
This demo board is connected to the mains voltage. Avoid touching the board while it is connected to the mains voltage and when it is in operation. An isolated housing is obligatory when used in uncontrolled, non-laboratory environments. Galvanic isolation from the mains phase using a fixed or variable transformer is always recommended.
019aab173
a. Isolated
Figure 2. Isolation symbols
b. Not isolated
019aab174
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3 Board photographs
The TEA2209DB1584 demo board consists of the TEA2209T in an SO16 package with four MOSFETs (600 V; 28 mΩ).
Figure 3 shows the front side of demo board.
Figure 3. TEA2209DB1584 demo board photograph
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4 TEA2209DB1584 demo board setup
The TEA2209DB1584 demo board contains four 600 V/28 mΩ MOSFETs. It makes the board suitable for universal AC input and output power applications of several hundreds of Watts. The TEA2209DB1584 demo board contains four leads that can easily replace a traditional diode bridge. The outer two leads are connected to positive and negative rectified voltages. The inner two leads are connected to AC mains lines. These four leads
are pin-to-pin with typical bridge rectifier diodes pins. Figure 4
describes the difference between bridge diodes and active bridge configurations.
TEA2209T
aaa-036471 aaa-039044
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a. Diode bridge b. Active bridge
Figure 4. Diode bridge configuration versus TEA2209DB1584 demo board typical configuration
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Figure 5 shows an example of the TEA2209DB1584 demo board mounted on an NXP
Semiconductors TEA2016DB1519 demo board.
Figure 5. TEA2209DB1584 demo board added to 240 W resonant adapter board
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5 Operation
The TEA2209T is a controller IC for an active bridge rectifier. It can directly drive the four
MOSFETs in an active bridge. Figure 6
shows a typical configuration. As the output is a rectified sine wave, a boost-type power-factor circuit must follow the application.
VR
VCCHL VCCHR
200 nF
GATEHL
VCC
LEVEL
SHIFT
VCC
LEVEL
SHIFT
GATEHR
200 nF
L R
CONTROL
GATELL GATELR
COMP
1.3 V
VR
SUPPLY
+
XCAP DISCH
COMP_POL GND
VCC
2.2 µF
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enable
aaa-038080
Figure 6. Typical configuration
The control circuit of the TEA2209T senses the polarity of the mains voltage between pins L and R. Depending on the polarity, either GATELL or GATELR is switched on. The comparator in the control circuit, which compares the L and R voltages, has thresholds of
250 mV and −250 mV depending on the slope polarity. If the difference voltage between
L and R is less than 250 mV both GATELL and GATELR are low.
The gate drivers are high-current rail-to-rail MOS output drivers. An on-chip supply circuit which draws current from either L or R generates the gate driver voltage. After a zerocrossing of the mains voltage, the supply capacitor C level V reg
VCC
is charged to the regulation
. Then the discharge state is entered. The resulting power dissipation from the mains voltage is about 1 mW excluding gate charge losses of the external power
MOSFETs. These gate charge losses typically add 1 mW of dissipation.
At start-up, the supply capacitor is first charged to the V start
voltage and enters the startup state. After a next zero-crossing of the mains voltage, the supply capacitor is charged to V reg
in the charging state. When the voltage at the supply capacitor exceeds V dis
, the gate driver outputs are enabled. When all drivers are active, the MOSFETs take over the role of the diodes which, compared to a passive diode rectifier bridge, results in lower power loss.
When the mains voltage is disconnected, the internal bias current in the discharge state discharges the supply capacitor. When the voltage at pin VCC drops to below V dis
, the Xcapacitor discharge state is entered, which draws 2 mA of current from VR to discharge the X-capacitor. The waiting time t d
until X-capacitor discharge starts is:
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Using a typical value of 2.2 μF for C
VCC
yields about 0.24 s. While VR discharges the
X-capacitor, the mains can be reconnected. In that case, the charge mode is entered again.
Figure 7 describes the start-up, the normal operation, and the power-off of the
TEA2209T.
(1) mains discount
L-R t d
VR
VCC
V reg
V dis
V startup
GATELL
GATEHR
GATELR
GATEHL
Figure 7. TEA2209T signals (start-up, normal operation and power-off)
aaa-038081
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6 Performance
6.1 Test facilities
•
Oscilloscope: AgilentTechnologiesDSOX3034T
•
AC power source: Chroma 61504
•
Electronic load: Chroma 63600-2
•
Digital power meter: WT210
•
Power board: TEA2016DB1519
6.2 Test setup
To measure the system performance the TEA2209DB1584 is mounted on the TEA2016DB1519. The diode bridge rectifier, BD101, is removed from the
TEA2016DB1519 and replaced by the TEA2209DB1584.
test setup.
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Figure 8. TEA2209T test setup on TEA2016DB1519
When the MOSFET pin open test for active bridge is required, add a diode in parallel to each active bridge MOSFET.
To enable or disable active bridge operation via the COMP pin, the TEA2209T supports an external signal. This COMP pin is connected to digital high/low signal output from the
MCU or the PFC gate signal throughout RC filter. When the PFC gate signal is used, the
PFC gate pin can be connected to the TEA2209DB1584 directly, because the RC filter is already implemented. When a digital high/low signal is input, remove the C4 capacitor on the TEA2209DB1584 to avoid additional delay time.
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6.3 Design guideline for COMP and COMP_POL
The TEA2209T can disable gate drivers using an external signal. The external signal is connected to the COMP pin. Depending on the COMP_POL selection, either a high level
or a low level on the COMP pin disables gate operation. Table 1
shows the functionality of COMP and COMP_POL. When COMP pin voltage exceeds 1.3 V, the COMP level is
HIGH. When the COMP pin voltage is lower than 0.95 V, the COMP level is LOW.
Table 1. COMP and COMP_POL functionality
COMP_POL = VCC
COMP HIGH
COMP LOW
All gate drivers are disabled
All gate drivers are enabled
COMP_POL = GND
All gate drivers are enabled
All gate drivers are disabled
Disabling all gate drivers is helpful to reduce power loss and increase efficiency at a lowload condition. A signal from a microprocessor can disable gate drivers. When there is no microprocessor on the system, the PFC gate signal can be used to disable the
gate drivers at light load throughout the external circuit. Figure 9
shows an application example with PFC gate signal. The PFC gate duty-ratio, the PFC gate level, and the external resistor divider determine the COMP level. When PFC operates in burst mode,
COMP level has ripple according to burst mode frequency. Whenever the ripple exceeds
1.3 V threshold, gate drivers are enabled. Section 6.5
shows the test waveform.
VBOOST
VR
VCCHL VCCHR
VCC VCC
200 nF
GATEHL
LEVEL
SHIFT
LEVEL
SHIFT
GATEHR
200 nF
L R
CONTROL
V (AC)
GATELL GATELR mains filter
COMP
1.3 V
VR
SUPPLY
+
XCAP DISCH
COMP_POL GND
VCC
2.2 µF
PFC
CONTROL boost-type pFC
CCOMP_low
RCOMP_low
RCOMP_high
aaa-038084
Figure 9. Application diagram example with PFC gate signal
The TEA2209DB1584 implements an external RC filter with R
R
COMP_low
= 180 kΩ, C
COMP_high
= 2.2 μF and 1N4148. To adjust the output power level which disables gate drivers, change R
TEA2016DB1519.
COMP_high
COMP_high
. As reducing R
= 18 kΩ,
COMP_high
value, gate drivers can be disabled at lower power levels.
gives the test result with the
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6.4 Start-up sequence
After AC mains voltage is applied, the body diodes of the MOSFET rectifiers are connected until the TEA2209T is enabled. The internal self-bias circuit from the rectified mains voltage, VR, supplies the VCC.
Depending on the output load condition, the COMP pin voltage may vary. At 264 V (AC) and a no-load condition, the TEA2209T is disabled. At 90 V (AC) and a no-load condition, however, the COMP pin level is high enough to enable the TEA2209T when PFC gate signals are available.
When the 3.3 V (DC) external source level to enable the TEA2209T is connected to the
COMP pin, TEA2209T is enabled when VCC has reached the V start
level. As mentioned in
, the C4 capacitor is removed from the TEA2209DB1584 demo board.
and
Figure 13 show the start-up sequences when an external 3.3 V (DC)
source is connected to COMP pin.
CH1: AC mains (300 V/div)
CH2: VCC (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 200 ms/div a. 90 V (AC)
CH1: AC mains (300 V/div)
CH2: VCC (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 200 ms/div b. 264 V (AC)
Figure 10. Start-up sequence at no load; PFC gate signal connected to COMP pin
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CH1: AC mains (300 V/div)
CH2: VCC (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 100 ms/div a. 90 V (AC)
CH1: AC mains (300 V/div)
CH2: VCC (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 100 ms/div b. 264 V (AC)
Figure 11. Start-up sequence at 240 W load; PFC gate signal connected to COMP pin
CH1: AC mains (300 V/div)
CH2: VCC (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (2 V/div)
Time: 20 ms/div a. 90 V (AC)
CH1: AC mains (300 V/div)
CH2: VCC (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (2 V/div)
Time: 20 ms/div b. 264 V (AC)
Figure 12. Start-up sequence at no load; 3.3 V (DC) connected to COMP pin
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CH1: AC mains (300 V/div)
CH2: VCC (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (2 V/div)
Time: 20 ms/div a. 90 V (AC)
CH1: AC mains (300 V/div)
CH2: VCC (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (2 V/div)
Time: 20 ms/div b. 264 V (AC)
Figure 13. Start-up sequence at 240 W load; 3.3 V (DC) connected to COMP pin
6.5 Normal operation
6.5.1 Connecting the PFC gate signal to the COMP pin
When the voltage between L and R is higher than 250 mV, the GATEHL and GATELR are enabled. When the voltage between L and R is below −250 mV, the GATEHR and
GATELL are enabled. Depending the +250 mV and −250 mV detection thresholds, dead time occurs between the gates. At no load, the PFC of the TEA2016 operates in burst mode. Because the on-time of the PFC gate and the switching period in burst mode are long at 90 V (AC) and no load, the TEA2209T is enabled in every PFC burst period.
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CH1: AC mains (300 V/div)
CH2: PFC gate from TEA2016 (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 5 s/div and 100 ms/div a. 90 V (AC)
CH1: AC mains (300 V/div)
CH2: PFC gate from TEA2016 (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 100 ms/div b. 264 V (AC)
Figure 14. Normal operation at no load; the PFC gate signal is connected to the COMP pin
CH1: AC mains (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 20 ms/div and 10 μs/div a. Dead time while GATELR is enabled
CH1: AC mains (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 20 ms/div and 10 μs/div b. Dead time while GATELL is enabled
Figure 15. Normal operation at 90 V (AC)/240 W load; the PFC gate signal is connected to the COMP pin
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CH1: AC mains (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 20 ms/div and 10 μs/div a. Dead time while GATELR is enabled
CH1: AC mains (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 20 ms/div and 10 μs/div b. Dead time while GATELL is enabled
Figure 16. Normal operation at 264 V (AC)/240 W load; the PFC gate signal is connected to the COMP pin
6.5.2 Connecting the external DC signal to the COMP pin
When the COMP level exceeds 1.3 V, the TEA2209T is enabled. Before enabling the first gate signal after TEA2209 is enabled, it can have a maximum of around a half mains cycle delay time because of the MOSFET drain-source overvoltage protection. As soon as COMP level is below 0.95 V, the TEA2209T is disabled.
CH1: AC mains (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (5 V/div)
CH4: COMP (2 V/div)
Time: 20 ms/div a. 90 V (AC)
Figure 17. COMP level increase at no load condition
CH1: AC mains (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (5 V/div)
CH4: COMP (2 V/div)
Time: 20 ms/div b. 264 V (AC)
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CH1: AC mains (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (5 V/div)
CH4: COMP (2 V/div)
Time: 20 ms/div a. 90 V (AC)
Figure 18. COMP level decrease at no load condition
CH1: AC mains (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (5 V/div)
CH4: COMP (2 V/div)
Time: 20 ms/div b. 264 V (AC)
6.6 Output dynamic load condition operation
Output dynamic load is applied between 240 W and a no-load condition. The dynamic load period is 14 ms. Regardless of the output load condition, the gates operate well in alignment with the mains polarity without shoot-through. Because the output dynamic load frequency is lower than the RC filter design on the COMP pin, the COMP level is still the DC level. The COMP level is in accordance with the average output load.
CH1: AC mains (300 V/div)
CH2: Output load (20 A/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 20 ms/div a. 90 V (AC)
CH1: AC mains (300 V/div)
CH2: Output load (20 A/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 20 ms/div b. 264 V (AC)
Figure 19. Dynamic load operation; the PFC gate is connected to the COMP pin
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6.7 Efficiency test result and R
DSon
selection
The efficiency test result includes power losses of bridge rectifiers and other power stages, such as PFC and LLC. However, throughout the active bridge incorporated in the
TEA2209T an efficiency improvement compared a diode bridge can be seen. Depending on the different R varies.
DSon
values of the active bridge MOSFET, the efficiency improvement
η
(%)
94
93
92
91
90
89
88
87
86
(1)
(2)
aaa-037226
85
0 50 100 150 200 250
P o
(W)
300
(1) Active bridge with the TEA2209T
(2) Diode bridge
Figure 20. Efficiency comparison between diode and active bridge at 115 V (AC)
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shows the comparison between different MOSFET R
DSon
values and the number of diodes in parallel at 115 V (AC). To see the improvement achieved with the active bridge with a MOSFET at its worst condition, the efficiency is calculated at a junction temperature of 125 °C. The efficiency improvement can reduce the temperature on the bridge rectifier. It helps to increase power density.
η
(%)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
aaa-037227
0
200 300 400 500 600 700 800 900
Po (W)
1x10
3
Efficiency drop comparison calculation based on 115 V (AC) input and a die temperature of
125 °C (bridge diode bridge: GSIB15A60;15 A; 600 V; 20 A 600 V).
(1) One diode bridge (eff_drop_Diode_125deg_onePoVin_rms)
(2) Two diode bridges parallel (eff_drop_Diode_125deg_twoPoVin_rms)
(3) Three diode bridges parallel (eff_drop_Diode_125deg_threePoVin_rms)
(4) Active bridge with MOSFET R
DSon
(5) Active bridge with MOSFET R
DSon
= 30 mΩ (eff_drop_Active_125degPo0.030, 2, Vin_rms)
= 25 mΩ (eff_drop_Active_125degPo0.025, 2, Vin_rms)
(6) Active bridge with MOSFET R
(7) Active bridge with MOSFET R
DSon
DSon
(8) Active bridge with MOSFET R
DSon
= 20 mΩ (eff_drop_Active_125degPo0.02, 2, Vin_rms)
= 15 mΩ (eff_drop_Active_125degPo0.015, 2, Vin_rms)
= 10 mΩ (eff_drop_Active_125degPo0.01, 2, Vin_rms)
Figure 21. Efficiency improvement based on different R
DSon
values at 115 V (AC)
Example:
When an R
DSon bridge, is 1.2 %.
of 0.015 Ω is used on a MOSFET for a 500 W design, the efficiency improvement that can be achieved, when compared to a single diode for a diode
6.8 Standby power consumption test result and design guidelines
6.8.1 Recommended setting for low standby power consumption
When active bridge is enabled, the rectified AC mains voltage is a full-wave rectified waveform even at no-load condition. Although a full wave rectified waveform achieves a better THD performance, it can make an additional current path on capacitors (which are placed on the rectified mains voltage). The result is extra power losses on these capacitors because of ESR. To minimize standby power consumption, disable the
TEA2209T via COMP pin. To disable the TEA2209T at a no-load condition, either the external DC level or the PFC gate signal can be selected. When the PFC gate signal is used, an external RC filter can adjust a power level which disables the TEA2209T.
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Table 2. Standby power consumption
115 V (AC) and no load (mW) 230 V (AC) and no load (mW)
Standby power consumption of
TEA2209DB1584 standalone
(COMP = low)
3.8
7.4
Standby power consumption with TEA2016DB1519
33 52
6.8.2 Enable and disable power levels; PFC gate connected to COMP pin
When the COMP pin is connected to PFC gate throughout external RC filter, the COMP level is increased as increasing output power level.
Table 3 shows enable and disable
power levels with PFC gate connection.
Table 3. Enable and disable power levels; the PFC gate is connected to the COMP pin
90 V (AC) 115 V (AC) 230 V (AC) 264 V (AC)
TEA2209T enable power level
2.0 W 2.5 W 7.4 W 21.6 W
TEA2209T
disable power level
1.8 W 2.4 W 7.2 W 13.2 W
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6.9 AC power-off sequence and X-capacitor discharge test
If the X-capacitor discharge function is activated, the discharge current flows from VR to
Ground via the internal path of the IC. After AC mains is disconnected, the VCC capacitor is discharged. While VCC is discharged to V not enabled. This delay time (t d dis
, the X-capacitor discharge current is
) can be adjusted with different VCC capacitors. After
VCC is decreased to V mains voltage.
dis
, the X-capacitor discharge current is enabled. It takes 370 ms to discharge the 940 nF the X-capacitor and the 1470 nF capacitor on the rectified AC
CH1: AC mains voltage (300 V/div)
CH2: VCC (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 200 ms/div
Figure 22. X-capacitor discharge test at 264 V (AC) and a no-load condition; the PFC gate is connected to the COMP pin
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6.10 AC mains transition test
When the AC mains voltage is changed from high mains to low mains, or vice versa, no shoot-through occurs. The active bridge operates normally.
CH1: AC mains voltage (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 50 ms/div and 5 ms/div a. Mains change from 90 V (AC) to 264 V (AC)
CH1: AC mains voltage (300 V/div)
CH2: GATELR (5 V/div)
CH3: GATELL (10 V/div)
CH4: COMP (5 V/div)
Time: 50 ms/div and 5 ms/div b. Mains change from 264 V (AC) to 90 V (AC)
Figure 23. AC mains voltage transition test at a 240 W load; the PFC gate is connected to the COMP pin
6.11 Surge test result
To test the system surge, the TEA2209DB1584 is mounted on the TEA2016DB1519. In
addition, one MOV, 14D511, is added between two AC mains lines. Figure 24 shows the
MOV position. Surge test can pass up to 5 kV without damage, which is same test result as with the diode bridge.
Additionally, to increase power capability, the R107 and R108 resistors on the
TEA2016DB1519 are changed to a metal-alloy type. The power rating of the R106 is also increased.
F101
SS-5H-4A-APH
E103
AWG15
L
E104
AWG15
N
L
N earth wire
E101
AWG18 earth
PE
E102 mounting hole earth casing
EARTH
4AT/300 V (AC)
14D511
CX101
470 nF
310 V (AC)
GDT1 n.m.
DSP-201M
1
2
GDT3 n.m.
DSP-201M
GDT2
2051-20
4
LF102
6.8 mH
3
GDT4 n.m.
2051-20
CX102
470 nF
310 V (AC)
SNS_MAINS_R
4
PG0
3
2
BD101
GBU806 on heat sink
HS101
1
C103
1 µF
450 V n.m.
aaa-039076
Figure 24. Circuit diagram which adding MOV 14D511 on the AC mains lines
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Table 4. Surge test result, EN61000-4-5
Surge voltage (V) Surge degree
1000 0 deg, 90 deg, 180 deg, 270 deg
2000
3000
4000
5000
0 deg, 90 deg, 180 deg, 270 deg
0 deg, 90 deg, 180 deg, 270 deg
0 deg, 90 deg, 180 deg, 270 deg
0 deg, 90 deg, 180 deg, 270 deg
Test result
pass without damage pass without damage pass without damage pass without damage pass without damage
7 Schematic
VR
R1
Q1
IPT60R028G7
R3
Q3
IPT60R028G7
C3
2.2 F
R2
Q2
IPT60R028G7
C1
220 nF
L
VCCHL
GATEHL
HVS
GATELL
VCC
GND
COMP_POL
U1
3
4
1
2
5
6
7
8
TEA2209T
16
15
14
13
12
11
10
9
VR
HVS
GATEHR
VCCHR
R
HVS
GATELR
COMP
C2
220 nF
R5 n.m.
R10
MCU
R6
R7
18 k
R8
R9
180 k
C4
2.2 F
R4
Q4
IPT60R028G7
D1
GATE
1N4148
GND
L
Figure 25. Schematic diagram
N
aaa-039077
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8 Bill of materials (BOM)
Table 5. Bill of materials (BOM)
Part reference Values and description
C1; C2 capacitor; 220 nF; 10 %; 50 V; X7R;
0603
C3; C4
Q1; Q2; Q3; Q4
R1; R2; R3; R4; R6;
R8; R10
-
Part number
-
Manufacturer
capacitor; 2.2 μF; 10 %; 25 V; X7R;
0805
MOSFET-N; 600 V; 75 A resistor; jumper; 0 Ω;100 mW; 0603 -
IPT60R028G7 Infineon
-
R5
R7
R9
D1
U1 resistor; not mounted; jumper;
0 Ω;100 mW; 0603 resistor; jumper; 18 kΩ; 100 mW;
0603 resistor; jumper; 180 kΩ; 100 mW;
0603 diode; fast switching; SOD123 active bridge rectifier controller
-
-
-
1N4148W
TEA2209T
-
-
-
Diodes
NXP
Semiconductors
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9 Layout
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TEA2209DB1584 active bridge rectifier controller demo board
a. Front view layout and assembly
UM11493
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b. Back view layout and assembly
Figure 26. TEA2209DB1584 demo board layout
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10 Abbreviations
Table 6. Abbreviations
Acronym
MOSFET
UVLO
THD
PCB
11 References
[1]
TEA2209T data sheet
Description
metal-oxide semiconductor field-effect transistor undervoltage lockout total harmonic distortion printed-circuit board
— Active bridge rectifier controller; 2020, NXP Semiconductors
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12 Legal information
12.1 Definitions
Draft
— A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information.
12.2 Disclaimers
Limited warranty and liability
— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes
— NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
Suitability for use
— NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
Applications
— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
Export control
— This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
Evaluation products
— This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose.
Translations
— A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
Security
— Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability.
Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team
(PSIRT) (reachable at [email protected]) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.
12.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
GreenChip
— is a trademark of NXP B.V.
NXP
— wordmark and logo are trademarks of NXP B.V.
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Contents
Introduction ......................................................... 3
Features .............................................................4
Safety warning .................................................... 4
Board photographs .............................................5
TEA2209DB1584 demo board setup ..................6
Operation ............................................................. 8
Performance ...................................................... 10
Test facilities .................................................... 10
Test setup ........................................................ 10
Design guideline for COMP and COMP_
POL ..................................................................12
Start-up sequence ........................................... 13
Normal operation ............................................. 15
Connecting the PFC gate signal to the
COMP pin ........................................................15
Connecting the external DC signal to the
COMP pin ........................................................17
Output dynamic load condition operation .........18
Efficiency test result and RDSon selection ...... 19
Recommended setting for low standby power consumption ..........................................20
AC mains transition test .................................. 23
Surge test result .............................................. 23
Schematic .......................................................... 24
Bill of materials (BOM) ..................................... 25
Layout .................................................................26
Abbreviations .................................................... 27
References .........................................................27
Legal information ..............................................28
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 29 January 2021
Document identifier: UM11493
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