NXP PN5190 NFC Frontend supporting challenging RF environment Data Sheet

NXP PN5190 is a high-power NFC frontend IC that supports contactless communication at 13.56 MHz. It is a highly integrated device that includes an RF transceiver, a host interface, and a power management unit. The PN5190 is compliant with the NFC Forum specifications and supports all major NFC protocols, including ISO/IEC 14443-A, ISO/IEC 14443-B, FeliCa, and ISO/IEC 15693. It also supports peer-to-peer communication and can be used in a variety of applications, including payment, physical access, and eGov.

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PN5190

NFC frontend

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1 General description

This document describes the functionality and electrical specification of the high-power

NFC-IC PN5190B1, silicon version B1, using firmware or V2.0 or higher.

Additional documents supporting a design-in of the PN5190B1 are available from NXP, this additional design-in information is not part of this document.

The PN5190B1 supports highly innovative and unique features which do not require any host controller interaction. These features include dynamic power control (DPC), adaptive waveform control (AWC), and fully automatic EMD error handling.

The independence of real-time host controller interactions makes this product a good fit for systems which operate a pre-emptive multitasking OS like Linux or Android.

In this document, the term „MIFARE card“ refers to a contactless card using an IC out of the MIFARE Classic, MIFARE Plus, MIFARE Ultralight or MIFARE DESFire product family.

NXP Semiconductors PN5190

NFC frontend

2 Features and benefits

2.1 RF functionality

• As a highly integrated high performance full NFC Forum-compliant frontend IC for contactless communication at 13.56 MHz, this NFC frontend IC utilizes an outstanding modulation and demodulation concept completely integrated for relevant 13.56 MHz based contactless communication methods and protocols.

PN5190B1 supports communication with all products of the MIFARE product-based card family including MIFARE Ultralight, MIFARE Classic 1K/4K, MIFARE DESFire

EV1/EV2 and MIFARE Plus cards CRYPTO implemented in hardware for R/W of all

NXP MIFARE product-based cards (includes intellectual-property licensing rights for

NXP ISO/IEC 14443-A, Innovatron ISO/IEC 14443-B, and NXP MIFARE products).

The PN5190B1 frontend IC supports the following RF operating modes:

2.1.1 ISO/IEC14443-A

• Reader/writer mode supporting ISO/IEC 14443-A R/W up to 848 kBit/s

2.1.2 ISO/IEC14443-B

• Reader/writer mode supporting ISO/IEC 14443-B up to 848 kBit/s

2.1.3 FeliCa

• Reader/writer mode supporting FeliCa 212 kBit/s and 424 kBit/s(without crypto)

2.1.4 Tag type reading

• Supports reading of all NFC tag types (type 1, type 2, type 3, type 4A and type 4B, type

2.1.5 MIFARE card reading

• Reader/writer communication mode for the MIFARE card family including MIFARE

Classic

2.1.6 ISO/IEC 15693

• Reader/writer mode supporting ISO/IEC 15693 (ICODE)

• Proprietary data rates based on ISO/IEC15693 with 106 kbit and 212 kbit/s (for NXP

NTAG 5 communication)

2.1.7 Peer to peer

• P2P Active 106 kbit/s TO 424 kbit/s, Initiator and Target

• Proprietary passive communication for type A up to 848 kbit/s

• Functionality according to ISO/IEC 21481 (NFC-IP-2)

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2.2 Host interface

• One host interface based on SPI is implemented:

– SPI interface with data rates up to 15 Mbit/s with MOSI, MISO, NSS and SCK signals

– Interrupt request line to inform host controller on events

– Independent TX and RX buffer for RF data with size of 1024 bytes each

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3 Applications

• Payment

• Physical access

• eGov

PN5190

NFC frontend

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4 Firmware versions

Firmware versions covered by this data sheet:

Version 2.0:

• This version cannot be replaced by FW versions using smaller version numbers (e.g.

replacing FW2.0 by FW1.9 is not possible)

• This FW version is not available on volume production devices, but can be installed by the user

Before using this firmware in Peer to Peer target mode, for better communication stability the EEPROM address 0x292 (default A6E813C 0 ) shall be initialized with the value (A6E813C 1 - 0x292:0xC1 0x203: 0x13 0x294:0xE8 0x295:0xA6). This setting has no influence on reader or card emulation modes.

Version 2.1:

• This version is functionally equivalent to Version FW2.0 but offers updated EEPROM

Settings compared to FW2.0

• This version cannot be replaced by FW versions using smaller version numbers (e.g.

replacing FW2.1 by FW1.9 is not possible)

• This FW version is installed by default on volume production devices of PN5190 B1

• This FW and all upcoming FW versions will use the EEPROM Setting at address 0x292

= A6E813C 1 to configure the Peer to Peer target mode for better communication stability.

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5 Quick reference data

Table 1. Quick reference data

Symbol Parameter

VDD

(VBAT)

VDD pd

(VDDIO) supply voltage on pin VBAT

(analog and digital supply) supply voltage on pin VDDIO

(supply for host interface and

GPIO's) power-down current

I stb

ULPCD

IDD

(PA)

(VDDPA) amb stg j_max

Conditions

VBAT ≥ VDDIO

1.8 V supply

3.3 V supply

Min

2.4

1.62

2.4

standby current average ultra-low-power card detection current supply current on pin VDDPA

Transmitter output power ambient operating temperature

VDD

(VDDPA)

= VDD

(VDDIO)

=VDD

(VDD)

3.0 V; hard powerdown state; pin VEN set LOW,

T amb

= 25 °C, External supply by

VDDIO

T amb

= 25 °C

T amb

= 25 °C, VDD(VDDPA) =

VDD(VDDIO) =VDD(VDD) 3.0

V, 330 ms Polling interval, 50 R antenna matching supplied via VUP_TX (TX_LDO active) supplied without DC-DC and

TXLDO active supplied via VUP_TX (TX_LDO active) supplied without DC-DC and

TXLDO active in still air with exposed pins soldered on a 4 layer JEDEC PCB, in still air with exposed pins soldered on a 4 layer JEDEC PCB,

HVQFN40 Package TX current =

120 mA @ VDDPA=3.6 V storage temperature maximum junction temperature no supply voltage applied

-40

-55

Typ

Max

5.5

1.98

3.6

105

Unit

μA

110 μA

μA

350

400

2.0

2.3

+85 °C

+105 °C mA

+150 °C

+125 °C

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6 Ordering information

Table 2. Ordering information

Type number Package

Name

PN5190B1HN/C121Y HVQFN40R

PN5190B1HN/C121E HVQFN40R

PN5190B1EV/C121Y VFBGA64

PN5190B1EV/C121E VFBGA64

Description

Plastic thermal enhanced very thin quad flat package; no leads;

40 terminals + 1 central ground; body 5 x 5 x 1.0 mm; delivered in one reel,

MSL=3. Minimum order quantity = 6000 pcs

The ending Y in the product name is indicating the packing

"reel"

Initialized with FW 2.1

Plastic thermal enhanced very thin quad flat package; no leads;

40 terminals + 1 central ground; body 5 x 5 x 1.0 mm; delivered in one tray, bakeable,

MSL=3. Minimum order quantity = 490 pcs

The ending E in the product name is indicating the packing

"single tray"

Initialized with FW 2.1

Plastic thin fine-pitch ball grid array package; 64 balls, body 4.5

x 4.5 x 0.9 mm, delivered on reel 13", MSL = 3. Minimum order quantity = 4000 pcs

The ending Y in the product name is indicating the packing

"reel"

Initialized with FW 2.1

Plastic thin fine-pitch ball grid array package; 64 balls, body 4.5

x 4.5 x 0.9 mm, delivered in one tray, MSL = 3. Minimum order quantity = 490 pcs

The ending E in the product name is indicating the packing

"single tray"

Initialized with FW 2.1

Version

SOT2062-1

SOT1307-2

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7 Block diagram with VFBGA64 connections

optional 2.4 V.... 6.0 V supply (no DC-DC used)

3.3 V supply (with DC-DC used)

1.8 V or 3.3 V pad supply (connect to host)

220 nF

1 µH

1 220 nF

µ F

PN5190

NFC frontend

IRQ

SPI_MISO

SPI_MOSI

SPI_NSS

SPI_SCK

VEN

XTAL1

XTAL2

INTERFACE

CLK/PLL

VSS_PMU

VSS_DIG

VSS_NFC

DAC

DC-DC

ANALOG/DIGITAL

TX_LDO

TRANSMITTER

TXVCM

RECEIVER

MUX

220 nF

TX1

VMID

TX2

VSS/PA

RXp

RXn

220 nF

AUX1

AUX2

AUX3/VTUNE0

PRD0

PRD1

220 nF 100 nF 220 nF host interfaces clock and reset ground connections power supply out for stabilizing capacitors out for stabilizing capacitors antenna connection digital/analog l/O

Figure 1. Block diagram aaa-029370

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8 Pinning information

8.1 Pin description VFBGA64 ball A1 index area

1 2 3 4 5 6 7 8

Figure 2. Pin configuration for VFBGA64 aaa-035352

Transparent top view

Table 3. Pin description VFBGA64

Pin

Number

Symbol Type

Host Interface

E6 ATX_A Output

Description PN5190

SPI slave data output

ATX_B

ATX_C

ATX_D

IRQ

XTAL1

XTAL2

VEN

Input

Output

Input

Output

Input

Description PN76 family (planned pinning of upcoming device)

SPI clock input

SPI slave select input

SPI slave data input

Host communication/ event interrupt signal

Crystal / system clock input

Clock output (amplifier inverted signal output) for crystal

Hardware reset, low active (independent from V

VDDIO

)

UART RX / I³C SDA / SPI MISO / I

SDA

UART CTS / I³C SCL / SPI SCK / I 2

SCL

UART RTS / I

C Adr Bit 0 / SPI NSS / I

Adr Bit 0 / USB D+

UART TX / I

C Adr Bit 1 / SPI MOSI / I

Adr Bit 1 / USB D-

Host communication / event interrupt signal

Crystal / system clock input

Clock output (amplifier inverted signal output) for crystal

Hardware reset, low active (independent from V

VDDIO

)

Supply pins

H2 VSS_PA Transmitter ground Transmitter ground

VSS_PLL

VSS_PWR

Supply

GND

Supply

GND

Supply

GND

PLL ground (low noise)

DC-DC boost ground

PLL ground (low noise)

DC-DC boost ground

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Table 3. Pin description VFBGA64

...continued

Pin

Number

Symbol Type Description PN5190

D3 VSS_REF Supply

GND

PMU ground

B2, E3 VSS_SUB Substrate ground

C3 VSS_PMU

Supply

GND

Supply

GND

PMU ground

F4 VSS_DIG Supply

GND

Digital ground

VSS_NFC

VBAT

Supply

GND

Supply

NFC ground

System supply, used to supply the analog and digital blocks, memory and internal voltage references

VDDIO

VDDPA

VUP_TX

VDDBOOST

BOOST_LX

VBATPWR

Supply

Output

Supply

Description PN76 family (planned pinning of upcoming device)

PMU ground

Substrate ground

PMU ground

Digital ground

NFC ground

System supply, used to supply the analog and digital blocks, memory and internal voltage references

IO pads power supply

Transmitter supply

IO pads power supply

Transmitter supply

Input supply voltage for transmitter LDO Input supply voltage for transmitter LDO

DC-DC boost supply DC-DC boost supply

Boost inductance loopback, to be connected to boost inductor

To be connected to boost inductor and transmitter power supply

Boost inductance loopback, to be connected to boost inductor

To be connected to boost inductor and transmitter power supply

Outputs for stabilizing cap

A4 VDDNV Output

VREF

VDDC

TXVCM

TXVCASC

VMID

Output

Non-volatile memory power supply, to be connected to ground via 220 nF blocking cap

High quiescent reference voltage, to be connected to ground via 100 nF blocking cap

Power supply for Digital Core, to be connected to ground via 220 nF blocking cap

Transmitter voltage common mode, to be connected to ground via 220 nF blocking cap

TX decoupling cap, to be connected to

VDDPA

Stabilizing capacitor connection output, to be connected to electrical symmetry point of antenna (typically antenna ground) by 100 nF blocking cap

Non-volatile memory power supply, to be connected to ground via 220 nF blocking cap

High quiescent reference voltage, to be connected to ground via 100 nF blocking cap

Power supply for Digital Core, to be connected to ground via 220 nF blocking cap

Transmitter voltage common mode, to be connected to ground via 220 nF blocking cap

TX decoupling cap, to be connected to

VDDPA

Stabilizing capacitor connection output, to be connected to electrical symmetry point of antenna (typically antenna ground) by 100 nF blocking cap

RF Debug signals

G7 AUX_1

F7 AUX_2

Output

Test bus 1

Test bus 2

Test bus 1

Test bus 2

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Table 3. Pin description VFBGA64

...continued

Pin

Number

Symbol Type Description PN5190

H8 AUX_3 /

VTUNE0

Output Test bus 3 / VTUNE0 (Digital to analog output 0)

Antenna connections

RXP

RXN

TX1

TX2

Input

Output

Analog/Digital inputs & outputs

VTUNE1

GPIO0

GPIO1

Output

Input/

Output

Input/

Output

Receiver input "Positive"

Receiver input "Negative"

Antenna driver output 1

Antenna driver output 2

Digital to analog output 1 (not available on HVQFN40)

General Purpose In/Out 0

General Purpose Output 1

GPIO2

GPIO3

Input/

Output

Input/

Output

General Purpose Output 2

General Purpose Output 3

If PN5190 is using the ULPCD, GPIO3 cannot be used for any other purpose than aborting the ULPCD.

Security Feature

B4 PRD1 Input/

Output

Package removal detection, internally connected to PRD2 (not available on

HVQFN40)

G4 PRD2 Input/

Output

Package removal detection, internally connected to PRD1 (not available on

HVQFN40)

Pins connected on PN76 family only

A5 PVDD_OUT Output PN5190: Do not connect

A6 I2CM_SDA Do not connect

DWL_REQ

GPIO5

Input/Out put

Input

Input/Out put

Do not connect

I2CM_SCL

SWDIO

TEST

ISO_INT_

AUX

Input

Input/Out put

Do not connect

Internal test pin. Do not connect

Do not connect

Description PN76 family (planned pinning of upcoming device)

Test bus 3 / VTUNE0 (Digital to analog output 0)

Receiver input "Positive"

Receiver input "Negative"

Antenna driver output 1

Antenna driver output 2

Digital to analog output 1 (DAC 1)

General Purpose I/O 0

General Purpose I/O 1

General Purpose I/O 2

General Purpose I/O 3

If PN76 is using the ULPCD, GPIO3 cannot be used for any other purpose than aborting the ULPCD.

Package removal detection, internally connected to PRD2

Package removal detection, internally connected to PRD1

PVDD LDO output

C master SDA

Download request (optional)

General Purpose I/O 5

C master SCL

Single Wire Debug Interface Data

Internal test pin. Do not connect.

Auxiliary Card Interrupt

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Table 3. Pin description VFBGA64

...continued

Pin

Number

Symbol Type Description PN5190

C5 GPIO4 Input/Out put

Do not connect

C6 Input Do not connect

HOST_IF_

SEL1

HOST_IF_

SEL0

Input Do not connect

SWD_CLK Input

USB_VBUS Supply

Do not connect

D4 Do not connect ISO_IO_AUX Input/Out put

AD1

ISO_CLK_

AUX

Input

SPIM_MOSI Input

SPIM_MISO Output

SPIM_SCLK Input

SPIM_NSS Input

Do not connect

Description PN76 family (planned pinning of upcoming device)

General Purpose I/O 5

Host interface select 1

Host interface select 0

Single Wire Debug Interface Clock

USB VBUS supply

Auxiliary Card I/O

Analog/Digital Converter Input 1

Auxiliary Card Clock

SPI master MOSI

SPI master MISO

SPI master clock

SPI master NSS

For good RF performance, all blocking capacitors shall be placed on the same side of the

PCB, traces from pin to capacitor shall be as short as possible.

All Supply GND connections shall be connected by low-ohmic connections on the PCB.

PN76 is a planned product, the pin allocation is provided for information only. This product PN76 will assign functionality to n.c. pins of the PN5190.

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8.2 Pin description HVQFN40 terminal 1 index area

PN5190 central heatsink connect to GND

Transparent top view

Figure 3. Pin configuration for HVQFN40 (SOT2062-1)

Table 4. Pin description HVQFN40

Pin

Number

Symbol Type

BOOST_LX

VDDBOOST

Output

Supply

VSS_REF

VREF

Supply GND

Output

VBAT

VUP_TX

TXVCASC

VSS

VDDPA

TXVCM

TX1

VSS_PA

TX2

RXN

RXP

VMID

Supply

Output

Supply GND

Supply

Output

Supply GND

Output

Input

Output

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Description PN5190

Boost inductance loopback, to be connected to boost inductor pin 1

Boosted supply voltage output

PMU ground

High quiescent reference voltage, to be connected to ground via 100 nF blocking cap

System supply, used to supply the analog and digital blocks, memory and internal voltage references

Input supply voltage for transmitter LDO

TX decoupling cap, to be connected to VDDPA

Ground

Transmitter supply

Transmitter voltage common mode, to be connected to ground via 220 nF blocking cap

Antenna driver output 1

Transmitter ground

Antenna driver output 2

Receiver Input "Negative"

Receiver input "Positive"

Stabilizing capacitor connection output, to be connected to electrical symmetry point of antenna (typically antenna ground)

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Table 4. Pin description HVQFN40

...continued

Pin

Number

Symbol Type Description PN5190

17 VSS Supply GND Ground

XTAL1

XTAL2

Input

Output

Crystal / System clock input

Clock output (amplifier inverted signal output) for crystal

VTUNE1

AUX_1

AUX_2

AUX_3 /

VTUNE0

Output

Digital to analog output 0

Test bus 1

Test bus 2

Test bus 3 / VTUNE0 Digital to analog output 1

ATX_A

ATX_B

ATX_C

ATX_D

IRQ

VDDIO

GPIO3

GPIO2

GPIO1

GPIO0 n.c.

VSS

VDDC

VEN

VDDNV

VBATPWR

VSS_PWR

Input

Output

Input

Output

Supply

Output

Supply GND

Output

Input

Output

Supply

Supply GND

SPI slave data output

SPI clock input

SPI slave select input

SPI slave data input

Host communication/ event Interrupt signal

IO pads power supply

General Purpose Out 3

General Purpose Out 2

General Purpose Out 1

General Purpose Out 0

Ground

Power supply for Digital Core, to be connected to ground via 220 nF blocking cap

Hardware reset, low active (independent from V

PVDD

)

Non-volatile memory power supply, to be connected to ground via 220 nF blocking cap

To be connected to boost inductor pin 2 and transmitter power supply

DC-DC boost ground

For best performance, all blocking capacitors shall be placed on the same side of the

PCB, traces from pin to capacitor shall be as short as possible.

Compared to the BGA package, all ground connections named VSS are connected on the leadframe of the package. Therefore general VSS pins do exist, pins are not distinguished by function like on the BGA package type e.g. VSS_PMU. The exceptions are the pins VSS_PWR, VSS_PA and VSS_REF.

All Supply GND connections shall be connected by low-ohmic connections on the PCB.

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9 Functional description

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9.1 Functional overview

The PN5190B1 is an NFC frontend with high transmitter output power. It implements the RF functionality like an antenna driving and receiver circuitry and all the low-level functionality to realize an NFC Forum and EMVCo compliant reader.

Connection to host controller

The PN5190B1 connects to a host microcontroller with a fast SPI interface (15 Mbit/s) for configuration, NFC data exchange and high-level NFC protocol implementation. An optimized TLV-based framing is supported to reduce the command handling overhead on the host controller and to reduce command-response latencies. Multiple commands are allowed to be sent within a single frame and processed in sequential order. This reduces the handshake overhead for a transaction significantly and by this shortens the overall time of a transaction.

Clock supply

The PN5190B1 uses an external 27.12 MHz crystal as clock source for generating the RF field and its internal digital logic. Alternatively, an internal PLL allows using an accurate external clock source of either 24 MHz, 32 MHz and 48 MHz (configured in

EEPROM register CLK_INPUT_FREQ, 0012h)). This allows saving the 27.12 MHz crystal in systems which implement one of the mentioned clock frequencies.

Integrated DC-DC

The integrated DC-DC allows a single supply voltage while delivering maximum RF output power. Dependent on the application target either a direct transmitter supply or a transmitter supply by the integrated DC-DC can be chosen. The usage of the integrated DC-DC is the preferred choice for a stable RF performance, even in case of a de-charged battery. Optimized usage of a battery charge can be achieved by directly connecting the transmitters to the supply. The DC-DC is controlled by the Dynamic Power

Control 2.0 to keep the power dissipation of the chip minimized in antenna loading cases which require a reduction of the RF output power.

The DC-DC is a step-up converter and is able to deliver an output voltage from approx.

2.8 V up to 6.0 V. The targeted output voltage can be configured by software.

The DC-DC clock is synchronized with the clock of the receiver - this avoids the typical performance reduction by DC-DC noise which can be seen in systems using external

DC-DCs.

Transmitter LDO (VDDPALDO)

The Transmitter output drivers are supplied by a transmitter LDO which reduces external noise and is used for the DPC functionality to lower the supply voltage of the transmitters.

The high granularity of 100 mV for setting the VDDPALDO output voltage together with a sophisticated control loop and true current measurement ensures that a DPC regulation is not accidentally treated as received data.

Low-power card detection

The low-power card detection (LPCD) allows saving battery charge during polling for

NFC counterparts like cards and mobile phones. In general, the low-power card detection provides a functionality, which allows to power down the reader for a certain amount of time to safe energy. After some time, the reader becomes active again to poll for cards. If

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PN5190

NFC frontend no card is detected, the reader can go back to the power down state. During the polling time, a host controller can be set to a power-saving mode. An interrupt request from the

PN5190B1 allows waking up the host controller in case an antenna detuning by a card or cell phone had been detected.

Two modes for the low-power card detection are available:

• LPCD (software based) which allows maximum detection range. For detecting a card presence, I/Q channel information is used.

• ULPCD (hardware based) which offers maximum current savings. For detecting a card presence, only the amplitude information is used.

Dynamic power control 2.0

The next generation Dynamic Power Control (DPC2.0) with true transmitter current measurement works autonomous without host interaction. Avoiding additional host controller processing load is important for time critical applications like payment. A fast control response time of less than 1 ms allows using optimized antenna matchings.

Adaptive wave shape control

The Adaptive Wave Shape Control (AWC) helps to keep the waveshapes within specification limits, even in case of antenna detuning. This simplifies the time-consuming antenna matching procedure and does not require any matching compromises to be taken.

Receiver signal level control

The receiver signal chain consists of an automatic controller RF input attenuator and a true Baseband Amplifier (BBA). This feature delivers an outstanding communication range with tags, labels, cards and mobile phones.

RF Debugging

Comprehensive and innovative debug features are implemented to support the NFC reader development even for difficult and non-standard compliant cards and mobile phones. An Integrated Chip scope allows performing a non-intrusive debugging of receiver signals without the need of connecting additional wires to the chip. Capturing of chip-internal signals is done by configuring flexible trigger conditions, sampled internal data is stored in RAM memory, transferred by SPI to a host microcontroller and visualized on a PC by the NFC Cockpit development tool. A virtual comfort interface (VCOM) is supported by the NFC cockpit tool, which allows to use the NFC cockpit together with any host microcontroller. Analog debug signals (AUX1, AUX2) are available as well and allow the connection of an Oscilloscope for analog and digital signal debugging.

The receiver signal processing is optimized to cope with noisy environments. This is beneficial, especially in case a TFT display or DC-DCs are part of the NFC system.

Automatic EMD error handling

An automatic EMD handling performed without host interaction relaxes the timing requirements on the Host Controller. Automatic EMD error handling according to ISO/

IEC14443 and EMVCo 3.0 is supported. In addition, the EMD error handling is widely configurable, which allows adaptions in case of future possible specification changes.

Automatic antenna tuning

Two analog outputs are available to connect variable capacitors for automatic antenna tuning (AAT). The automatic antenna tuning allows compensating for production tolerances or changing environments like surrounding metal. This is especially beneficial

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NFC frontend for applications which make use of OEM NFC Modules which are finally used in an unknown environment. The automatic antenna tuning is performed command triggered.

Firmware update

The PN5190B1 supports a secure update of the implemented firmware. The secure firmware download mode is using a dedicated command set, but a framing which is not different from the standard host interface commands used for NFC operation of the device. In Secure Firmware update mode, the PN5190B1 requires no dedicated physical handling of the SPI interface lines. The firmware download does not require any additional hardware pin to be handled, instead the download mode is activated by a command, followed by a hardware reset. After booting from reset, the PN5190B1 will be in download mode.

Register configuration

Internal registers of the PN5190B1 store volatile configuration data and accessible by the host interface. The internal registers are reset to configurable initial values in case of powerON, hardware-reset and standby.

The configuration for dedicated RF protocols and antenna-dependent configuration is defined in non-volatile memory. This configuration is typically done only once during production, and is performed by a command issued from the host microcontroller.

EEPROM configuration

Non-Volatile EEPROM memory of the PN5190B1 is used to store configuration data that needs to be preserved in case the PN5190B1 is not connected to any supply voltage.

The configuration for dedicated RF protocols and antenna-dependent configuration is defined in this non-volatile memory and copied to volatile registers by a host interface command. In addition, other configuration data which needs to be preserved during power supply disconnect is stored in this EEPROM memory as well. Examples for this are configurations for DPC, LPCD and ULPCD configurations.

RF configuration

The PN5190B1 allows a fast RF protocol selection based on the command

Load_RF_configuraton and pre-defined user configuration data in non-volatile memory

(EEPROM).

On the one hand, the configuration of modulation-related parameters can be done (e.f.

selection of ISO/IEC14443-A), on the other hand antenna-specific parameters can be configured.

For more information see

[1]

PN5190B1

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9.2 Endianness

The endianness describes the order of bytes or bits within a binary representation of a value in the memory, which can be a register or EEPROM.

"Array size" defines the number of elements of "type size". Type size can be uint8 (8 bit), uint16 (16 bit) or uint32 (32 bit).

The location of byte sized data (8 bit) with an array size of 2 is as follows:

Value hex: 0x1234 address x: 12 address x+1: 34

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The location of word sized data (16 bit) is as follows:

Value hex: 0x1234 address x: 34 address x+1: 12

The location of word sized data (16 bit) in an array size of 2 is as follows:

The placement of the array is large endian, the placement of nibbles of the variable is small endian.

Value hex: 0xAABBCCDD address x: BB address x+1: AA address x+2: DD address x+3: CC

The location of double word sized data (32 bit) is as follows:

Value hex: 0xAABBCCDD address x: DD address x+1: CC address x+2: BB address x+3: AA

Byte sized data (8 bit) with an array size of 2

Data: 0x1234

Word sized data (16 bit) with an array size of 1

Data: 0x1234

Word sized data (16 bit) with an array size of 2

Data: 0xAABBCCDD

Data in Memory

Address

X+1

Data in Memory

Address

X+1

Data in Memory

Address

X+1

DD CC

X+2 X+3

PN5190B1

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Dword sized data (32 bit)

Data: 0xAABBCCDD

Data in Memory

Address

X+1

BB AA

X+2 X+3 aaa-036897

Figure 4. Endianness examples

Data from the EEPROM is read in little endian format - LSB first. This means that the byte at the lower address is read first.

9.3 Initial calibration

The PN5190B1 requires a calibration before the RF field is switched on for the first time.

The calibration sequence is the following:

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Power state

Power OFF

PMU OFF

ULP standby

Hard power down

Write EEPROM CfgNovCal (0xC83) – 0x00

Write REGISTER TX_NOV_CALIBRATE_AND_STORE_VAL (addr: 0x5d) - 0x01

Write EEPROM CfgNovCal (0xC83) – 0x02

9.4 System power states

The PN5190B1 can operate in different power states. The functionality and current consumption is dependent on the actual system power state.

Power states can be changed by the level on the pin VEN and by connecting/ disconnecting the power supply of VBAT.

In addition, state changes are triggered possible by host commands.

Disconnecting and connecting the power supply on VBAT restarts the PN5190B1 always in Active State after releasing the pin VEN (transition low to high).

A transition of low to high on pin VEN restarts the PN5190B1 always in Active State.

The following power states are supported:

Description

The NFC system (supply pin VBAT, RF transmitter) is not supplied by a battery/system PMU. Other domains might be supplied (for example, IO pad interface on pin VDDIO).

Device is not functional

The NFC system is disabled by the host via a low signal on pin VEN. No internal clocks of the PN5190B1 are active. Wake-up events to change

PMU OFF state: Power reset on pin VBAT, VEN rising edge, RX ULPCD detect, ULP abort signal on PIN3

The host can set the PN5190B1 into Ultra-low power card detection state

(ULP Standby state) via programming of the ULPCD bit.

In the ULP Standby state, the PN5190B1 is able to activate the transmitter and receiver after defined time (expiry of wake-up timer) to detect the card.

If a card is not detected, the transmitter and receiver is deactivated and the wake-up timer restarted. Power consumption of ULP Standby mode is much lower than Hard Power Down State and Standby State. Only the wake-up timer is active during ULP Standby state

Wake-up events: Power reset on pin VBAT, VEN rising edge, Card detected.

Variant 1: Configurable wake-up timer allows system to boot into active

Variant 2: Configurable wake-up timer allows checking regularly for a card in the field.

The NFC system is disabled by the Host system via the reset/enable signal on VEN or by detecting an external condition (for example, battery voltage monitor). The power dissipation is reduced to a minimum. No power dissipation or leakage is expected on the different interfaces. Lowpower resources are enabled (VDDC_LP, VHV_LP, LQ_REF, LQ-BIAS).

LFO clock is available. PCRM is supplied and is running in low-power state. I/Os are supplied by VDDC_HP. Wake-up events: Power reset on pin VBAT, VEN rising edge, RX ULP detect

typical current consumption

5 µA

Variant 1: 5 µA

Variant2: 22 µA

40 µA

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Power state

Standby

Suspend

Active

Description

The NFC system can switch after a specific time of inactivity automatically into a low-power mode to minimize power dissipation. The state of external interfaces is maintained properly. PMU operates in low-power state. Wakeup counter clock is available. PCRM is supplied and running in low-power mode. I/Os are supplied by VDDC_LP. PMU FSM in PCRM manages the transition in power state. Wake-up sources: Activity on host IF, SWPM communication, ULPDET, LPDET, wake-up counter, power loss on VDDIO,

GPIO, RxPROT, No High Temp on TX and so on.

All power sources are available. LFO and HFO clocks are available.

CPU subsystem clock sources are gated, except for the LFO. I/O's are available.

The PN5190B1 is able to process internal or external events or data. All external power supply sources and the external clock need to be available, and all internal clocks are active.

typical current consumption

45 µA

2.5 mA

20 mA (system without RF current)

9.5 Power supply

The device allows to configure different power supply options for the transmitter power amplifier. To make use of them, a combination of external connections and chip internal configurations needs to be done. The following supply options are available:

• Internal VDDPA configuration: The TX power amplifier is supplied by the internal voltage regulator (VDDPALDO). In this configuration the DPC, current measurement and overcurrent protection is available. In addition, the VDDPALDO is adding an improved rejection of noise on the supply lines.

• Direct VDDPA configuration: This configuration is recommended for applications which require highest efficiency, like battery supplied devices. In this configuration, a battery can be connected directly to the transmitter supply avoiding the voltage drop of approximately 0.3 V caused by the VDDPALDO. A clean supply voltage without noise is required to achieve a good RF performance.

In this configuration the DPC, current measurement and overcurrent protection is not available.

9.5.1 System power supply overview

The PN5190B1 is using three different supplies each for the following functional blocks:

1. Supply for the host interface and GPIO's (VDDIO)

2. Supply for the analog and digital blocks (VBAT/VBAT_PWR)

3. Supply of the RF drivers (VDDPA), DC-DC (VBAT_PWR) and VDDPALDO (VUP)

The functionality of the GPIO's, Host Interface and internal analog and digital blocks is independent from the supply of the RF Driver. This allows to configure a dedicated transmitter supply configuration at any time. Care shall be taken to switch on the RF field only after the transmitter-related power supply had been configured according to the external physical supply connections (VDDPA, VBAT_PWR, VUP).

The power supply configuration is configured in EEPROM and therefore will not get lost in case of power supply loss or reset of the chip. Typically, this configuration is only performed once during the production of a reader.

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RF field shall not be turned on without setting the correct power supply configuration in the EEPROM.

Note: The Voltage on pin VDDIO must always be smaller or equal to the Voltage on pin

VBAT.

9.5.2 Connecting blocking capacitors

Some pins are connected to blocking supply capacitors. PCB traces to these capacitors need to be as short as possible, and a low-ohmic grounding of the GND-side of the capacitors is required for optimized RF performance.

PN5190B1

Product data sheet

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0.22 F

TXVCASC VDDPA

VDDC

0.22 F

VDDNV

0.22 F

VREF

100 nF

TXVCM

VMID

0.22 F

100 nF aaa-035230

Figure 5. Blocking capacitors

9.5.3 Transmitter power supply

The PN5190B1 is configured by EEPROM for the different power supply options.

The following registers are used to configure the power supply of the transmitter:

DCDC_PWR_CONFIG (0004h) - Enables/disables and configures the DC-DC according to the external supply connections.

DCDC_DELAY_TO_ON (0008h) -

DCDC_DELAY_TO_OFF (0009h) -

VDDPALDO_CONFIG (address 000Ch) - Enables/disables and configures the

TXPALDO.

VDDPALDO_VDDPA_HIGH (address 0010h) - out voltage when DC-DC or external power source is used as supply.

VDDPALDO_VDDPA_LOW (address 0011h) - out voltage when VBAT is used as supply.

VDDPALDO_VDDPA_MAX_RDR (address 0012h) - maximum voltage to be set in reader mode used by DPC.

VDDPALDO_VDDPA_MAX_CARD (address 0013h) - VDDPA maximum voltage to be set in card mode used by DPC.

No specific registers are required to configure the pad supply (VDDIO) or the supply for the analog and digital blocks (VUP).

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9.5.3.1 VDDPALDO transmitter supply

VDDPALDO supplied VDDPA configuration: The TX power amplifier is supplied by the internal voltage regulator (VDDPALDO).

In this configuration the DPC, current measurement and overcurrent protection is available. In addition, the VDDPALDO is adding an improved rejection of noise on the supply lines.

A decoupling cap is required on VDDPA pin.

Pad supply

(1.8 V or 2.4 to 3.6 V)

IOs

Battery/EXT supply/

USB supply

Connectto

VBAT/VBATPWR supply or External supply

Cvup_tx

VBAT/VBATPWR

Cvbat

VUP_TX

VDDPA

Cvddpa

VDDPALDO

DRIVER

(a) Internal VDDPA configuration aaa-035233

Figure 6. Transmitter supply

9.5.3.2 Direct transmitter supply

Direct VDDPA configuration:

VDDPALDO must be configured OFF by SW configuration. VUP_TX and VDDPA connected to VBAT/VBATPWR.

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Pad supply

(1.8 V or 2.4 to 3.6 V)

Battery/EXT supply/

USB supply

Cvbat

VBAT/VBATPWR

VUP_TX

IOs

Cvddpa

VDDPA

VDDPALDO

(OFF)

DRIVER

(a) Direct VDDPA configuration aaa-035232

Figure 7. Direct transmitter supply

9.5.3.3 DC-DC (boost) supply

BOOST inductor

(1 H)

VBAT

2.4-5.5 V

BOOST capacitor

(20 F)

VDDBOOST

Decoupling caps

VBAT

Decoupling caps

VUP

VDDPA

Decoupling caps

Figure 8. Transmitter supply by DC-DC

9.5.3.4 Configuration example 1: VDDPALDO transmitter supply - DC-DC active

VBAT is connected to VBATPWR.

aaa-035231

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Battery/EXT supply

(2.4 to 5.5 V)

Battery/EXT supply

(2.4 to 4.8 V)

VBAT

VBATPWR

Cvbatpwr

Cvbat

Cvddboost

Vbat Supply

[VBAT]

DCDC Supply

[VBATPWR]

BOOST_LX

VDDBOOST

VUP

DCDC

(SMPS_BOOST)

Cvup

TXLDO

(VDDPA_LDO)

Cvddpa Ctxvcasc

VDDPA

TXVCASC DRIVER

(TX_PA) aaa-035225

Figure 9. DC-DC active

9.5.3.5 Configuration example 2: VDDPALDO transmitter supply - DC-DC bypassed

VBAT is connected to VBATPWR.

Battery/EXT supply

(2.4 to 4.8 V)

VBAT

Vbat Supply

[VBAT]

Battery/EXT supply

(2.4 to 4.8 V)

VBATPWR

Cvbatpwr

Cvbat

DCDC Supply

[VBATPWR]

BOOST_LX DCDC

(SMPS_BOOST) bypass

Cvddboost

VDDBOOST

VUP

Cvup

TXLDO

(VDDPA_LDO)

VDDPA

Cvddpa Ctxvcasc

TXVCASC DRIVER

(TX_PA) aaa-035226

Figure 10. DC-DC bypassed (in DCDC_PWR_CONFIG)

9.5.3.6 Configuration example 3: VDDPALDO transmitter supply connected to VBAT - no

DC-DC

VBAT is connected to VBATPWR.

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Battery/EXT supply/

USB supply

(2.4 to 5.5 V)

Battery/EXT supply/

USB supply

(2.4 to 5.5 V)

VBAT

VBATPWR

Cvbatpwr

Cvbat

Vbat Supply

[VBAT]

DCDC Supply

[VBATPWR]

BOOST_LX

VDDBOOST

VUP

DCDC

(SMPS_BOOST)

Cvup

TXLDO

(VDDPA_LDO)

Cvddpa Ctxvcasc

VDDPA

TXVCASC DRIVER

(TX_PA) aaa-035229

Figure 11. No DC-DC used

9.5.3.7 Configuration example 4: VDDPALDO supplied independent from VBAT - no DC-DC

VBAT is connected to VBATPWR.

VBAT

Vbat Supply

[VBAT]

Battery/EXT supply/

USB supply

(2.4 to 5.5 V)

Battery/EXT supply/

USB supply

(2.4 to VBAT)

VBATPWR

Cvbatpwr

Cvbat

DCDC Supply

[VBATPWR]

BOOST_LX DCDC

(SMPS_BOOST)

EXT supply

(2.4 to 6.0 V)

VDDBOOST

VUP

Cvup

TXLDO

(VDDPA_LDO)

VDDPA

Cvddpa Ctxvcasc

TXVCASC DRIVER

(TX_PA) aaa-035228

Figure 12. No DC-DC used

9.5.3.8 Configuration example 5: VDDPALDO not used - no DC-DC

VBAT is connected to VBATPWR.

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Battery/EXT supply/

USB supply

(2.4 to 5.5 V)

Battery/EXT supply/

USB supply

(2.4 to 5.5 V)

VBAT

VBATPWR

Cvbatpwr

Cvbat

Cvddpa Ctxvcasc

Vbat Supply

[VBAT]

DCDC Supply

[VBATPWR]

BOOST_LX

VDDBOOST

VUP

DCDC

(SMPS_BOOST)

VDDPA

TXVCASC

TXLDO

(VDDPA_LDO)

DRIVER

(TX_PA)

PN5190

NFC frontend aaa-035227

Figure 13. No DC-DC used - no VDDPALDO

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9.5.3.9 Supply voltage range for transmitter supply configuration examples

Table 5. Supply voltage range

Supply Config1:

VDDPALDO transmitter supply - DC-DC active

VBAT 2.8 V … 4.8 V

VBATPWR 2.8 V ... 4.8 V

VUP 3.1 V … 6.0 V

VDDPA VUP-0.3V drop of

VDDPALDO. max 5.7 V

Config2:

VDDPALDO transmitter supply -

DC-DC bypassed

2.8 V … 4.8 V

2.8 V … 6.0 V

VBATPWR - 0.5 V voltage drop

Config3:

VDDPALDO transmitter supply connected to VBAT - no DC-

2.4 V … 5.5 V

2.4 V ... 6.0 V internally connected to

VDDPALDO

Config4:

VDDPALDO supplied independent from

VBAT - no DC-DC

Config5:

VDDPALDO not used - no DC-DC

2.4 V … 5.5 V

2.4 V ... 5.5 V

2.4 V … 6.0 V internally connected to

VDDPALDO

2.4 V … 5.5 V

9.6 Clock generation

The device supports the operation with two clock options, which is configured in EEprom address CLK_INPUT_FREQ (0012h).

One option is clocking by a crystal (default), the other a clocking by an external clock input frequency.

It is important to consider additional phase noise introduced e.g. by clock drivers in the design. Phase noise of the external clock will have an impact on the RF performance which can be achieved.

READER IC

XTAL1 XTAL2

27.12 MHz

001aam308

Figure 14. Clocking by crystal

PN5190B1

Product data sheet

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9.7 External interfaces

The PN5190B1 requires the connection of a power supply, and a clock source like crystal or external clock and a host microcontroller connected by the SPI interface for operation.

Additional connections of the package require the connection of stabilizing capacitors and ground.

The RF interface connects transmitter and receiver to the EMC filter of a connected antenna matching network. Additional connections are available for the GPIO's (on

PN5190B1 only outputs are implemented) and 2x DAC functionality (analog outputs).

The GPIO's implement internal Pull-up/Pull-down resistors. The output of the GPIO's can be configured in the pad configuration PAD_CONFIG (0052h).

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[2]

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9.8 Transmitter overcurrent and temperature protection

The PN5190B1 implements different mechanisms to protect the chip against damage.

On the one hand, an overcurrent protection exists which shuts down the Transmitter

Driver in case of a out of spec current. This can be enabled in TXPALDO_CONFIG

(000Ch), bit 11: overcurrent enable (0: disable, 1: enable)

On the other hand, an internal temperature sensor allows to monitor the temperature of the chip. This is configured in the register TEMP_WARNING (0048h). Three temperatures can be configured: 114 °C, 2:125 °C, 3:130 °C. GPIO1 is used to indicate this temperature warning to a connected host.

This is a safety feature only. A design shall not functionally rely on this feature since the operating conditions will be violated if the overcurrent detection becomes active.

9.9 Loading a dedicated RF configuration

The PN5190B1 allows an efficient selection of a dedicated RF protocol.

The selection of one RF protocol is done by sending a command to the PN5190B1. This instruction is used to load the RF configuration from EEPROM into registers.

It is possible to configure RF technology, mode (target/initiator) and baud rate.

Configurations can be loaded separately for the receiver (RX configuration) and transmitter (TX configuration).

The Command used for loading a dedicated RF protocol is

LOAD_RF_CONFIGURATION (0Dh).

9.10 Dynamic power control (DPC)

The DPC is used for a special antenna tuning, called "symmetric antenna tuning". For an

"asymmetric antenna tuning", the DPC is not required.

However, even for "asymmetric antenna tuning" with high output power needs, it might turn out that the RF field is too strong in close proximity of the antenna to be compliant with ISO/IEC14443 requirements. In this case, the DPC can be used as well to reduce the RF output power dependent on the distance of the card from the reader antenna.

The DPC works very well with a tuning called "symmetric tuning". With symmetric tuning, a detuning of the antenna is causing a reduction of the antenna impedance. This low antenna impedance might lead to a current which is too high for the targeted application.

The DPC allows to limit the transmitter current even under antenna detuning conditions.

DPC is useful:

• To achieve EMVCo analog compliancy

• To achieve NFC Forum and ISO/IEC 14443 compliancy (e.g. NFC Forum Power

Transfer Maximum, ISO/IEC 14443 Field Emission Maximum)

• To improve interoperability

The Dynamic Power Control (DPC 2.0) allows controlling the transmitter driver voltage in

100 mV steps dependent on the actual transmitter current.

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2 Please refer to the Errata sheet if the device is used with FW2.0 or FW2.1.

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A lookup table is used to configure the transmitter output voltage and by this control the

RF output power.

Features of the Dynamic power control (DPC 2.0):

• True current measurement provides maximum information for the regulation loop

• The transmitter current can be limited and additionally reduced according to detected transmitter current condition / antenna detuning condition

• DPC works autonomous without host interaction causing no additional processing load on the host

• Fastest response time of 1 ms for regulation

• Used for adaptive waveshape control (AWC)

• Used for adaptive RX sensitivity control (ARC)

The DPC is able to operate in two modes:

1. Current limiting mode

2. Current limiting + Current reduction mode

The DPC is configured in the EEPROM, this configuration is used after startup. This avoids that the host needs to configure the chip after each reset or power-off.

The following EEPROM registers are most relevant for the DPC configuration:

0xF8: DPC_Config: Enables/Disables the DPC (enable: 0x39, disable: 0x00)

0xF9: DPC_TargetCurrent: Unloaded VDDPA target current in mA, the target current +/-

Hysteresis is limiting the current for the DPC.

• The DPC_TargetCurrent is the current which can be measured for the selected antenna impedance and transmitter supply voltage in unloaded condition. This is the current the system is designed to operate at.

0xFB: DPC_Hysteresis: Absolute difference to current target current in mA that triggers a DPC update event.

• The configuration of the hysteresis ensures, that the DPC is not regulating if small changes of the transmitter current occur due to external disturbances. A typical value for the DPC_Hysteresis is e.g. 20 mA.

0x8B: DPC_Lookup_Table: configures the current reduction

The DPC_LOOKUP_TABLE allows in addition to the limitation of the current, to configure

• an additional current reduction on top of the current limitation, achieved by further lowering the transmitter supply voltage

• a relative change of modulated amplitude level

• and a relative change of falling and raising edge time constant for ASK10% and

ASK100% modulations

This lookup table is initialized with 0x00 for devices delivered from the factory. (The customer development board is already initialized with useful data in EEPROM which work well with the antenna of the board).

The 0x00 entry in the DPC_LOOKUP_TABLE means that no additional function then the current limitation takes place for the DPC.

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In order to achieve a limitation of the current even in the case of an antenna impedance that is lowered, the Transmitter supply voltage is reduced accordingly.

This transmitter supply voltage reduction is now used as index for the

DPC_LOOKUP_TABLE.

For a specific transmitter supply voltage, it is possible to further reduce the current below the value of DPC_TargetCurrent or to configure parameters for waveshaping and modulation. All these entries are relative values, granularity of the entries dependent on the transmitter supply voltage is 0.1 V, resulting in 42 table entries.

The DPC updates the content of the following register dependent on the antenna load / lookup table configuration:

0x30 - DGRM_RSSI

DPC Configuration Table with PowerReduction for Hmax

AWC Configuration Table

Unloaded PCD Shaping

Configuration

ARC Configuration Table

IVDDPA

DPC

VDDPA

Loading strength information

VDDPA/VBOOST

Configuration

AWC

FW- based TX edge pattern generation

Load dependent offset reconfig

Falling/rising edges: Time Constant

Modulation index

Level output stream

TX Signal Scalling

Only if VDDPA scaling not possible any more

CLIF Signal Shaping

ARC

Load dependent receiver settings

CLIF Receiver Gain and

Threshold Configuration

Host IF accessible configuration

Technology dependent

Figure 15. System overview: DPC, AWC and ARC aaa-038384

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DPC

VDDPA Voltage

VDDPA LUT

VDDPA Voltage Entry 0

VDDPA Voltage Entry 1

VDDPA Voltage Entry 2

VDDPA Voltage Entry 3

VDDPA Voltage Entry 4

VDDPA index

(0,1,2,3,4)

Configure protocol and datarate

Type A-106

Type A-212

Type A-424

Type A-848

Type B-106

Type B-212

Type B-424

Type B-848

Type F-212

Type F-424

15693 26K

15693 53K

15693 106K

15693 212K

180003m3 SC424-Man2

180003m3 SC424-Man4

180003m3 SC848-Man2

180003m3 SC848-Man4

Receiver settings

Figure 16. System overview: DPC, AWC and ARC

Type A-424

ARC settings 0

ARC settings 1

ARC settings 2

ARC settings 3

ARC settings 4

Receiver settings configuration aaa-038526

Next DPC algorithm check

RF field envelope:

DPC algorithm: t

DPC,RegulationDone

Current

Meas

New

VDDPA t

DPC,CurrMeas,GuardTime t

DPC,VDDPAReconfig t

DPC,Updateinterval

Update PCD

Shaping

Current

Meas

Update VDDPA

Figure 17. System overview: DPC, AWC and ARC aaa-038399

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Measured current I

VDDPA,mcas

not in target current range

Estimate load impedance Z

LDO_VDDPA_VOUT_SEL

L,estimated n

and l

based ON

VDDPA,mcas

Determine new LDO_VDDPA_VOUT_SEL target current and est. load Impedance Z n+1

based on

L,estimated

Find last active entry in reconfiguration table (index: new VDDPA configuration)

Reconfiguration changes new target current?

yes

Determine new LDO_VDDPA_VOUT_SEL n+1 new target current and est. load Impedance Z

based on

L,estimated

Find last active entry in reconfiguration table (index: new VDDPA configuration)

Apply VDDPA voltage change LDO_VDDPA_VOUT_SEL n+1

Apply PCD shaping for active technology based on unloaded configuration and AWC re-config no

DPC update completed aaa-038400

Figure 18. System overview: DPC, AWC and ARC

9.10.1 DPC algorithm

The DPC algorithm is controlling the transmitter current. It is using the following states:

1. Current measurement: Performs VDDPA current measurement

2. New VDDPA: Determine new VDDPA configuration based on measured current

VDDPA New (for target current of Itarget) = VDDPA Voltage / VDDPA current * Itarget

3. Update VDDPA: Perform output power update

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4. Update PCD Shaping: Apply AWC configuration updates for active technology

5. Update RX sensitivity parameter only for short duration

Reconfiguration table includes Relative changes of target current and of waveform parameters adaption for all VDDPA voltage configurations. The VDDPA configuration is implicitly defined by the row index. The first row refers to LDO_VDDPA_VOUT_SEL=0

(represents 1V5).

EXAMPLE:

Unloaded configuration After Field ON:

VDDPA max set to 42 (5.7 V) ·Target current set to 280 mA

Technology B106: amp_mod=200

Falling edge time constant=rising edge time constant=3

Table 6. DPC_LOOKUP_TABLE element, defining the configuration for one dedicated VDDPA voltage

Function Bit Description

ENTRY 0 31:0 This is the entry for 1.5 V.

Target current reduction

AWC amp mod change

31:23

23:16

ENTRY 0 -LSB - byte 0

Voltage step between DPC entries = 100 mV. Voltage offset start = 1.5 V bEntry_00 =

1V5 ... bEntry_42 = 5V7

Bits[7:0] = Target current reduction in mA (unsigned)

ENTRY 0 - byte 1

Bits[7:0] = Relative change of modulated amplitude level (signed)

AWC edge time constant for ASK100

15:8

AWC falling edge time constant for ASK10

7:0

ENTRY 0 - byte 2

Bits[3:0] = ASK100, Relative change of falling edge time constant (signed)

Bits[7:4] = ASK100, Relative change of rising edge time constant (signed)

ENTRY 0 -MSB - byte 4

Bits[3:0] = ASK10, Relative change of falling edge time constant (signed)

Bits[7:4] = ASK10, Relative change of rising edge time constant (signed)

Loaded configuration After Field ON:

DPC regulates from unloaded VDDPA configuration 42 to 31. Consequently, new configuration to be applied based on index entry 31.

Target current stays at 280 mA.

Technology B106: amp_mod=205, falling edge time constant=2, rising edge time constant=0

9.10.2 DPC characteristics

Table 7. Dynamic power control characteristics

Symbol Parameter Conditions

Minimum hysteresis configured in EEPROM DPC_HYSTERESIS

(address 079h)

Depends on application target current

Min

ApplicationTargetCurrent

* 0.0609 + 2 mA

Typ

Max Unit mA

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Table 7. Dynamic power control characteristics

...continued

Symbol Parameter Conditions

Max target current configured in EEPROM

DPC_TARGET_CURRENT

(077h)

Hysteresis as configured in

DPC_HYSTERESIS

(address 079h)

Min

Typ Max

350-

Hysteresis

Unit mA

9.11 Adaptive waveshape control (AWC)

Depending on the level of detected detuning of the antenna, wave shaping related register settings can be automatically updated.

Two different waveshaping mechanisms can be used:

1. Firmware based shaping (1,2,3)

2. Lookup table based shaping (4,5,6)

The Firmware based shaping allows to correct rise times and overshoot with linear transition shapes.

The lookup table based shaping allows maximum flexibility and enables to configure almost any possible correction.

Example: rising edge

RF amplitude

3 transition

2 unmodulated modulated

4, 5, 6

Edge type

1 = linear

2 = 2x linear

3 = 3x linear

4, 5, 6 = any shape (look up table) up to 16/fc t aaa-037863

Figure 19. Waveshaping transitions (example falling edge)

The shaping related register settings are stored in a lookup table located in EEPROM, and selected dependent on the actual detected detuning condition.

Each lookup table entry allows the configuration not only of a dedicated wave shaping configuration for the corresponding detuning condition. But allows in addition to configure the wave shaping individually dependent on the actual protocol which is active.

Features of the Adaptive Waveshape Control:

• No external components required

• No need to compromise antenna matching to meet waveshape requirements

• Waveshapes automatically adapted according to detected detuning condition

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• RF standards define envelope timing and residual carrier parameters required for compliance and interoperability.

The device supports the design of compliant antennas by allowing to actively shaping the style of edge transition for falling and rising edges. The shaping of modulation edges is achieved by selecting one from three edge transition styles:

1. Linear transition between two amplitude levels

2. Two linear transition´s between amplitude levels and

3. Three linear transitions between amplitude levels.

The type of the transition is selected in the EEPROM registers EDGE_TYPE_(protocol), and can be defined independent for each RF protocol and data rate - for both falling and rising edge.

The EEPROM registers EDGE_STYLE_(protocol) define the time constant "s" of falling/ rising edge (depends on edge style).

The EEPROM registers EDGE_LENGTH_(protocol) define the total length of the edge pattern.

The figures below illustrate the edge type for the falling edge.

amplitude

CW level a

MOD k=-(a-b)/s level b start of edge pattern time constant s length of edge pattern l end of edge pattern

Figure 20. One linear transition (example falling edge) time aaa-035963

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CW level a

MOD k1=-2(a-b)/(3s) k2=k1/2 level b time constant s length of edge pattern l start of edge pattern end of edge pattern

Figure 21. Two linear transitions (example falling edge) time aaa-035964 amplitude

CW level a

MOD k1=-2(a-b)/(3s) k2=k1/2 k3=k2/2 level b time constant s s/2 length of edge pattern l start of edge pattern end of edge pattern time aaa-035965

Figure 22. Three linear transitions (example falling edge)

The transition patterns are used as implicit pre-distortion to compensate effects of TX loading circuitry (e.g. resonant circuitry parameters) to the emitted RF envelope.

9.12 Adaptive receiver control (ARC)

Depending on the level of detected antenna detuning, receiver-related register settings can be automatically updated. The receiver-related registers which are allowed to be dynamically controlled are:

DGRM_RSSI_REG (30h) ->DGRM_SIGNAL_DETECT_TH_OVR_VAL

SIGPRO_RM_TECH_REG (22h) ->RM_MF_GAIN,

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The adaptive receiver control settings override the default RM_MF_GAIN and

DGRM_SIGNAL_DETECT_TH_OVR_VAL settings configured by the command

LOAD_RF_CONFIGURATION (0Dh).

The ARC algorithm is called when VDDPA voltage changes after DPC. There are two lookup tables used in ARC algorithm i.e VDDPA lookup and ARC lookup. In case of a VDDPA change, an EEPROM lookup (at current protocol and baud rate) is performed. The receiver-related settings i.e RM_MF_GAIN,

DGRM_SIGNAL_DETECT_TH_OVR_VAL and IIR_ENABLE are read from EEPROM lookup table and configured in registers.

VDDPA lookup table:

VDDPA lookup table define maximum five voltage ranges. Number of VDDPA voltage ranges used in ARC algorithm is configured in bArcConfig[2:0]. VDDPA voltage output from DPC algorithm is input to VDDPA lookup. VDDPA lookup returns

VDDPA_range_index (i.e 0,1,2,3,4).

Table 8. ARC_VDDPA (0139Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

13D ARC VDDPA

Setting

7:0 Byte[4] = ARC_VDDPA_0: ARC_VDDPA_3 > VDDPA < ARC_VDDPA_4

13C 7:0 Byte[3] = ARC_VDDPA_0: ARC_VDDPA_2 > VDDPA < ARC_VDDPA_3

13B

13A

139

7:0

Byte[2] = ARC_VDDPA_0: ARC_VDDPA_1 > VDDPA < ARC_VDDPA_2

Byte[1] = ARC_VDDPA_0: ARC_VDDPA_0 > VDDPA < ARC_VDDPA_1

Byte[0] = ARC_VDDPA_0: 1.5 > VDDPA < ARC_VDDPA_0

ARC lookup table:

VDDPA index and RF protocol/datarates are input to ARC lookup. There are five

Receiver settings entries for each protocol and data rates. ARC algorithm select one out of five entries (at current protocol and baud rate) based on VDDPA_range_index.

Following table show ARC settings for Type A-106.

Table 9. ARC_RM_A106 (address 013Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

146 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT,

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 9. ARC_RM_A106 (address 013Eh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

144 RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT,

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

142

140

RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT,

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT,

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

13E RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: For ISO14443-A: In case ARC is disabled, it requires DPC_

SIGNAL_DETECT_TH_OVR_VAL larger than 0x50 (with MF_GAIN = 2 (default))

Note: For ISO14443-A: In case Bit[15] is configured to 0, it requires DPC_

SIGNAL_DETECT_TH_OVR_VAL larger than 0x50 (with MF_GAIN = 2 (default)) if the

ARC is enabled.

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9.13 Timer

The PN5190B1 implements three different types of timers: 2 general-purpose timers

(only general-purpose Timer0 is accessible by the user, Timer1 is used by the PN5190B1 as FDT Timer), 1 wake-up timer and 1 low frequency timer.

General-purpose timer

The PN5190B1 implements two 20-bit wide general-purpose timers - Timer0 and Timer1.

Timer0 can be configured by 2 registers each (TIMER0_CONFIG, TIMER0_RELOAD).

Timer 1 is typically used for as FDT and EMD timer configuration. Configuration can be done from the host but the associated IRQ is handled by the firmware of the PN5190B1.

The Timer1 events are consumed by the PN5190B1 FW and respective Time-out status is included as part of the command response.

The general-purpose Timer0 and the FTD Timer1 have a max count of 1.048.575.

The register TIMER0_CONFIG, TIMER0_RELOAD configure if either the 13.56 MHz clock of the RF interface is used as Timer input, or if a divided clock frequency is used as input. These registers configure as well the start conditions for the timer.

The following clock frequencies can be selected for the pre-scaler:

000b - 6.78 MHz counter

001b - 3.39 MHz counter

010b - 1.70 MHz counter

011b - 848 kHz counter

100b - 424 kHz counter

101b - 212 kHz counter

110b - 106 kHz counter

111b - 53 kHz counter

Wake-up timer

The PN5190B1 implements one 10-bit wide wake-up timer.

Max count of the wake-up timer is 1023, inout clock is the LFO CLK = 380 kHz. The max timeout is 269 ms.

The wake-up time is configured via the SWITCH_MODE_STANDBY /

SWITCH_MODE_LPCD commands. There is no dedicated register available for this timer. The PN5190B1 enters the standby state by the switch mode command

SWITCH_MODE_STANDBY/ SWITCH_MODE_LPCD. The counter value is part of the command and has to be sent as one configuration parameter. The 2-byte parameter value for the standby counter is indicating the counting time in milliseconds. The value needs to be provided in little-endian format.

Low frequency timer

The wakeup-counter for the ULPCD mode has a width of 12bits.

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The input clock for this timer is 1 kHz. ULPCD uses the ULP_STANDBY command, and for this the wake-up timer is feed by the 1 kHz clock. Count down value (12 bits counter;

ULFO CLK / 4096 = 0.244 Hz i.e. 1 ms per bit).

The max timeout is 4.096 s.

Timer for contactless interface

In addition to the timers above, to guarantee correct protocol timing, a guard period timer is implemented for the RF_EXCHANGE command in reception and transmission mode

(TX_WAIT, RX_WAIT counting).

No configuration of this timer is available for the user, setup and counting is managed completely by the hardware. Therefore this timer is not indicated in the timer overview.

13.56 MHz

Timer start configuration

T0_PRESCALE_SEL

PRESCALER

Internally configured

PRESCALER

User timer 0

20 Bit

FDT timer 1

20 Bit

Internally configured

Wakeup-timer (configured by command)

10 Bit

Timer events

380 kHz

1 kHz

Low frequency timer (configured by command)

12 Bit aaa-036459

Figure 23. Timer overview

9.14 Low-power card detection

The low-power card detection (LPCD) and ultra-low power card detection (ULPCD) are an energy-saving card polling configuration for the PN5190B1. During LPCD, a host microcontroller can be set into power-saving mode, as no host controller interaction is required.

A low frequency timer is implemented to drive a wake-up counter, which triggers a periodic activation of the antenna drivers to emit a short pulse which allows to detect a detuning of the antenna. In case of a detected antenna detuning, the system is woken up from power-saving mode. It sends an interrupt signal to the connected host microcontroller to wake up the host microcontroller from power-saving mode and to indicate a change of the antenna detuning condition.

There is no trimming for the Low Frequency Timer required.

The SWITCH_MODE instruction allows entering the LPCD mode with a given standby duration value.

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SWITCH_MODE_LPCD

(ULPCD)

Configure measurement interval, threshold

Enter Ultra low power card detection mode and perform card detection task at configured time intervals

Abs(ref-measured) < threshold

Event signaling card detection

Figure 24. LPCD configuration and card detection loop

Active Mode

Low power mode aaa-038408

9.14.1 Low-power card detection (LPCD)

The low-power card detection (LPCD) is an energy-saving card polling configuration for the PN5190B1. During LPCD, a host microcontroller can be set into power-saving mode, as no host controller interaction is required. The host microcontroller is woken up from power-saving mode by an IRQ send by the PN5190B1.

The LPCD mode offers highest sensitivity at the cost of slightly higher current consumption compared to the ULPCD mode.

A low frequency oscillator (there is no trimming for the low frequency oscillator required) is implemented to drive a wake-up counter, which triggers a periodic activation of the antenna drivers to emit a short RF pulse. This RF pulse allows to detect a detuning of the antenna by presence of conductive objects in proximity of the antenna (card, cell phone, metal).

In case of a detected antenna detuning, the system wakes up from power-saving mode. It sends an interrupt signal to the connected host microcontroller to wake up the host microcontroller from power-saving mode and to indicate a change of the antenna detuning condition.

A low frequency oscillator (LFO) is implemented to drive a wake-up counter, waking-up

PN5190B1 from standby mode. This allows implementation of low-power card detection polling loop at application level.

The host microcontroller can then perform a card polling sequence to verify if the technology of the object causing the antenna detuning is supported by the system.

The SWITCH_MODE instruction allows entering the LPCD mode with a given standby duration value.

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SWITCH_MODE_LPCD

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Enter standby with wakeup counter configured

Field ON and perform measurement of ADC_I and

ADC_Q values no

Abs(Ref value - Measured value) > Threshold yes

Event signalling card detection

Active Mode

Low power mode aaa-038409

Figure 25. LPCD configuration

The LPCD mode is entered by the host interface command SWITCH_MODE_LPCD

(23h), and terminated by the command SWITCH_MODE_NORMAL (20h). In addition, terminating the LPCD mode is possible by toggling a GPIO, by a reset (VEN) of the

PN5190B1 or a signal of the RF Level detector.

Before entering the LPCD mode, ADC_I and ADC_Q reference value needs to be determined. This is done during the so called calibration.

LPCD calibration phase a) An initial calibration measurement is performed to set up the RX chain parameters namely HFATT, DCO_DAC_I_CTRL and DCO_DAC_Q_CTRL values.

b) The next measurement is done using the RX chain parameters that are set up, to arrive at the ADC_I and ADC_Q values which are used as reference values. All following

LPCD measurements are done relative to the LPCD calibration measurement.

The LPCD loop itself works in two phases:

First the standby phase is controlled by the wake-up counter (timing defined in the instruction), which defines the duration of the standby of the PN5190B1.

Second phase is the detection-phase. The RF field is switched on for a defined time

(EEPROM configuration) and then the ADC_I and ADC_Q values are compared to a reference value.

• If the ADC_I and ADC_Q values exceed the reference value, a LPCD_IRQ is raised to the host. The register configurations done by the host to support a dedicated RF protocol are not restored after wake-up command. The host has to configure the NFC frontend for a dedicated protocol operation to allow a polling for a card.

• If the ADC_I and ADC_Q values do not exceed the thresholds of the reference value, no LPC_IRQ is raised and the IC is set to the first phase (standby mode) again.

These two phases are executed in a loop until:

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- Card / metal is detected (LPCD_IRQ is raised).

- Reset occurs, which resets all the system configurations. The LPCD is also terminated in this case.

- NSS on host interface

- RF Level Detected

- GPIO toggle

As feature, the GPIO1 (general-purpose input/output) pin can be enabled to wake up an external DC-DC from power down for the VDDPA supply. The GPO1 allows setting to high before the transmitter is switched on. This allows the wake-up of an external DC-DC from power down. The GPO1 can be set to low after the RF field is switched off to set an external DC-DC into power-down mode. The time of toggling the GPO in relation to the

RF-on and RF-off timings can be configured in EEPROM addresses 0xXX and 0xXX.

The behavior of the generated field is different dependent on the activation state of the

DPC function:

• If the DPC feature is not active, the ISO/IEC14443 type A 106 kbit/s settings are used during the sensing time.

• If the DPC is active, the RF_ON command is executed. The RF field is switched on as soon as the timer configured by the SWITCH_MODE command elapses. The RF field is switched on for a duration as defined for an activated DPC. The timer for the

LPCD_FIELD_ON_TIME starts to count as soon as the RF_ON command terminates.

Table 10. Low-Power Card Detection: relevant EEPROM configuration

EEPROM address

Name Description

0492 LPCD_AVG_SAMPLES Defines how many samples of the I and Q values are used for the averaging.

Used to optimize the system to achieve highest detection sensitivity versus false alarms.

0494 LPCD_RSSI_TARGET

0496 LPCD_RSSI_HYST

Value to be used as the RSSI target in the calibration phase to arrive at the RX chain parameters.

This parameter is used to arrive at an optimal target voltage level at RXP.

Value to be used as the RSSI hysteresis in the calibration phase to arrive at the

RX chain parameters.

This is used to avoid oscillations while arriving at the target voltage level at RXP.

049E LPCD_THRESHOLD

04B5

0013

LPCD_VDDPA

XTAL_CHECK_DELAY

If the difference between the measured value of I/Q and the reference value for I/

Q is greater than the threshold on either channels, then a card is detected.

VDDPA voltage when DC-DC (internal or external) or external power source is used to feed TXLDO

Interval which is used to check if XTAL is ready (unit is 256/fc, e.g. ~18.8 us).

For fastest startup this time, a check is performed at a time slightly higher than the expected startup time of the crystal.

9.14.2 Semi-autonomous mode (LPCD)

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LPCD semi-autonomous mode

The LPCD can be invoked by the host in the semi-autonomous mode wherein the ADC_I and ADC_Q values that are measured is returned back to the host.

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In this mode, standby is not entered and the difference between the measured and reference values are not checked against the threshold. Nevertheless, the host may check the measured values against a reference and threshold to detect a card and also put the PN5190B1 in standby mode between measurements, using the

SWITCH_MODE_STANDBY command.

This mode is especially useful to find optimized settings for the LPCD, since it does not offer no significant current saving.

Table 11. Low-Power Card Detection - semi-autonomous mode: relevant REGISTERS

REGISTER address

Name Description

0050 LPCD_CALIBRATE_CTRL Writing to this register triggers the LPCD calibration with the LPCD

RSSI_HYSTERESIS and LPCD RSSI_TARGET values. After calibration is completed calibration status is available in LPCD_

CALIBRATE_STATUS. If the calibration is successful, the I/Q channel values can be read from register IQ_CHANNEL_VALS

0051

0053

IQ_CHANNEL_VALS

LPCD_CALIBRATE_STATUS

Actual I/Q channel value

1: if successful - a new calibration clears this value

9.15 Automatic EMD error handling

The PN5190B1 supports a configurable EMD handling according to the ISO14443 or

EMVCo standard. To support further extensions or changes of these standards, the EMD block is configurable.

After being configured, the PN5190B1 restarts both the receiver and a timeout timer automatically without host interaction in case of a detected EMD event.

Features of the Automatic EMD Error Handling:

• No real-time constraints

• Less processing load on the host processor

• Configurable, anticipating future specification changes

In addition to the EMD error handling according to ISO14443 and EMVCo, the

PN5190B1 implements special features for FeliCa

preamble processing.

Registers CLIF_RX_EMD_1_CONFIG(0x47) and CLIF_RX_EMD_0_CONFIG(0x48) hold the configurations for the EMD configurations for ISO/IEC14443, and NFC Forum.

EMVCo EMD configuration is supported in the register EMVCO_EMD_CONTROL (0x3).

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9.16 Autocoll (card emulation)

The Autocoll state machine performs the time critical activation for Type-A PICC and for

NFC-Forum Active and Passive Target activation (card emulation mode).

The PICC state machine supports three configurations:

• Autocoll mode0: Autocoll mode is left when no RF field is present

• Autocoll mode1: Autocoll mode is left when one technology is activated by an external reader. During RFoff, the chip enters standby mode automatically

• Autocoll mode2: Autocoll mode is left when one technology is activated by an external reader. During RFoff, the chip does not enter standby mode.

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At start-up, the Autocoll state machine automatically performs a LOAD_RF_CONFIG with the General Target Mode Settings. When a technology is detected during activation, the Autocoll state machine performs an additional LOAD_RF_CONFIG with the corresponding technology.

The card configuration for the activation is stored in EEPROM. If RandomUID is enabled

(EEPROM configuration), a random UID is generated after each RF-off.

For all active target modes, the own RF field is automatically switched on after the initiator has switched off its own filed.

entry

IDLE

Frame received no ReqA/WupA yes no

SensF received and Passive

Target F enabled yes no

Frame received and no error yes

Active Mode enabled

Yes and

Autocoll_state_a** == HALT

Passive Target A enabled?

ISO14443-3A PICC state machine

Yes and

Autocoll_state_a** == IDLE

HALT no

Any CL

Error

READY*

ACTIVE*

READY

ACTIVE

SC = 0xFFFF or

EE-Value yes

SensFReq received

Send SensF response any other frame received no

Passive Target A106

IRQ line is asserted

Load Protocol PICC-A106 done

RX_IRQ and

CARD_ACTIVATED_IRQ are set

Figure 26. Autocall state machine

Passive Target F212/424*

IRQ line is asserted

Load Protocol PICC-F212 or PICC-F424 done

RX_IRQ and

CARD_ACTIVATED_IRQ are set

Active Target A106/F212/F424*

Load Protocol AT106/AT212/

*the determined baudrate can be found in the SIGPRO_CONFIG register

** Autocoll_state_a is defined in the register SYSTEM_CONFIG

IRQ line is asserted

AT424 done

RX_IRQ is set aaa-020625

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9.17 RF-level detection

The PN5190B1 implements an RF level detector (RFLD) and an NFC level detector

(NFCLD) which allows to detect the presence of an external RF field.

RF Level Detector:

During low-power card detection (LPCD), the RF level detector (RFLD) acts as wake-up source from power-saving mode.

During ultra low-power card detection (ULPCD), a specific ultra low-power RF level detector is used as RF level detector(RFLD). This can be enabled as wake-up source.

The purpose of the RFLD function is to detect any signal at 13.56 MHz in order to wake up the PN5190B1 from power-saving mode.

NFC Level Detector:

The NFC Level detector (NFCLD) is used during full power mode. The NFCLD function is required by NFC Forum to support the "RF collision avoidance".

The sensitivity of the NFCLD sensor can be configured by EEPROM register to meet the

NFC Forum requirements.

It can be used as well in card mode to detect an external field.

9.18 Antenna tuning with variable capacitors

The PN5190B1. allows the tuning of the connected antenna based on variable capacitors.

Variable capacitors are devices which allow to change their capacity dependent on a supplied control voltage. Typically, these capacitors are used as serial and parallel capacitors in an antenna matching network.

The PN5190B1 allows to measure a detuning of the connected antenna caused e.g. by surrounding metal and correct the actual detuning by applying an appropriate control voltage on 2 analog outputs.

To correct a potential detuning of the connected antenna, a phase measurement needs to be performed. The following sequence is required to read out the phase information:

Step 1: Disable DPC

Step 2: Perform Type A-106 load protocol

Step 3: Set the VDDPA Voltage as 𝑉 _𝑉((𝑑 𝑝𝑝 𝑎

Step 4: Perform RF ON

Step 5: Read out RXM phase

Step 6: Perform RF OFF

Step 7: Enable DPC

For reading the RXM phase, refer to the related application note. Based on the phase information, a host is able to calculate the DAC output voltages to correct a detuning.

The antenna tuning requires the DPC to be disabled, and is typically not suitable for dynamic tuning e.g. during card communication.

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VC1

Tx1 L0 Rs Ra

C2 VC2

Ca La

GND

Tx2

C2 VC2

EMC Filter

VC1 Matching Network

Figure 27. Antenna connection using variable capacitors

Antenna Coil aaa-041704

9.19 RF debug signals

The following signals are available for debugging purposes:

The test signals are selected by sending a command string to the

PN5190B1. The commands CONFIGURE_ TESTBUS_DIGITAL (12h) and

CONFIGURE_TESTBUS_ANALOG (13h) are used to configure the dedicated signal on an output pin.

If used, ADC-Q needs to be routed always to AUX1, ADC-I needs to be routed always to AUX2

The analog test signals are analog representation of an internal digital value. The internal digital signal is converted by an 8-bit wide DAC to the analog signal.

This overview indicates the signals which are available for debugging purposes

(indicated by numbers):

RxP

IIR

HF-

Attenuator

COMBINER

SYNC

FILTER

DECODER

Data

RxN

Figure 28. Receiver block diagram

IIR

Table 12. DEBUG SIGNALS

Signal REGISTER Description

ADC Data I Channel (1) obs_clif_ tbcontrol_ patchbox0

SIGNAL

NAME adc_ data_i_i

BITS

9:2 Unfiltered I channel signal aaa-037146 upper 7 bit of the 10 bit signed unfiltered I channel signal including sign (bit9)

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Table 12. DEBUG SIGNALS

...continued

Signal REGISTER SIGNAL

NAME

BITS Description

ADC Data Q Channel (2)

Preprocessor Out I

Channel (3)

Preprocessor Out Q

Channel (4)

Output MF S0 (5)

Output MF S1 (6)

Output Synchronization

Filter (7) clif_status

PN5190B1

Product data sheet

COMPANY PUBLIC obs_clif_ tbcontrol_ patchbox1 obs_clif_ tbcontrol_ patchbox2 obs_clif_ tbcontrol_ patchbox3 obs_clif_sigpro_ rm0 obs_clif_sigpro_ rm1 obs_clif_sigpro_ rm2 obs_clif_sigpro_ rm3 obs_clif_sigpro_ rm4 obs_clif_sigpro_ rm5 obs_clif_sigpro_ rm6 obs_clif_sigpro_ rm7 obs_clif_sigpro_ rm8 obs_clif_sigpro_ rm9 adc_ data_q_i rm_cor_ adc_i_o rm_cor_ adc_q_o mf_pt_ s0_d mf_pt_ s1_d sync_filt_ out

9; 6:0

9:2

9; 6:0

14:8

7:0

14:8

7:0

14:8

7:0

14:8

7:0

14:8

7:0

Unfiltered I channel signal lower 7 bit of the 10 bit signed unfiltered I channel signal including sign (bit9)

Unfiltered Q channel signal upper 7 bit of the 10 bit signed unfiltered Q channel signal including sign (bit9)

Unfiltered Q channel signal lower 7 bit of the 10 bit signed unfiltered Q channel signal including sign (bit9)

Pre-processed ADC data I channel upper 7bit of 15bit signed pre-processed ADC data I channel, after IIR Filter and down-sampling including sign (bit14) bit 15: RFU

Pre-processed ADC data I channel lower 8bit of 15bit signed pre-processed ADC data I channel, after IIR Filter and down-sampling

Pre-processed ADC data I channel upper 7bit of 15bit signed pre-processed ADC data Q channel, after IIR Filter and down-sampling including sign (bit14) bit 15: RFU

Pre-processed ADC data I channel lower 8bit of 15bit signed pre-processed ADC data Q channel, after IIR Filter and down-sampling

Delayed matched filter S0 output, after CH combiner upper 7 bit of the 15 bit signed delayed matched filter

S0 output, after Channel combiner including sign

(bit14) bit 15: RFU (ignore)

Delayed matched filter S0 output, after CH combiner lower 8 bit of the 15 bit signed delayed matched filter

S0 output, after Channel combiner

Delayed matched filter S1 output, after CH combiner upper 7 bit of the 15 bit signed delayed matched filter S1 output, after Channel combiner including sign (bit14) bit 15: RFU (ignore) Remark: S1 is not relevant for type A 106

Delayed matched filter S1 output, after CH combiner lower 8 bit of the 15 bit signed delayed matched filter

S1 output, after Channel combiner Remark: S1 is not relevant for type A 106

Synchronization filter output upper 7 bit of the 15 bit signed synchronization filter output including sign (bit14) bit 15: RFU (ignore)

Synchronization filter output lower 8 bit of the 15 bit signed synchronization filter output transceive_state 7:5

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Table 12. DEBUG SIGNALS

...continued

Signal clif_transceive

REGISTER rx_cl_error tx_envelope rx_enevelope svalid sdata rx_start_receive rx_over_ok rx_over_term rx_resume sgp_msg_busy fig_reset_sigpro fig_reset_rxdec cfg_sw_reset_ sigpro

SIGNAL

NAME

BITS

Table 13. TRIGGER SIGNALS

TRIGGER REGISTER

TX Active

RX Enable obs_clif_txenc1

RX collision detected obs_clif_sigpro_ rm15 obs_clif_sigpro_ rm14

SIGNAL

NAME

BITS tx_active_o 1 rx_enable_o 1 rm_scoll_o 1

Description

Description high level indicates transmission of data Remark: Falling edge can be used to trigger on end of transmission.

high level indicates that the reception is ongoing Remark: can be used to trigger on the start /end of reception high-level pulse indicates that the collision is detected during reception

PN5190B1

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9.20 Secure firmware update

The PN5190B1 supports a secure update of the implemented firmware.

The secure firmware download mode is using dedicated commands, but does not require a dedicated physical handling of the SPI interface lines.

The secure firmware download mode is entered by setting a register in non-volatile memory followed by a trigger of the VEN pin.

The firmware binary file which is used to update the PN5190B1 is protected with an RSA signature and AES encryption.

The key length of the RSA is 2048 bits, the public exponent supports any 32-bit integer value.

A pre-computed Montgomery format of signature is used, and the signature hash computation is based on SHA256 algorithm.

This prevents a download of any other software which is not released by NXP.

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An anti-tearing function is implemented in order to detect supply voltage removal or memory fault.

During the secure firmware download, the NFC operation is not available, only the command set defined for the secure firmware download is valid.

Updating the PN5190B1 with the default firmware binaries programs the memories for user configuration with default values. Any previous user configuration will be overwritten. The user has to take care to restore the data of these memories after a secure firmware update.

If this is not intended, special firmware versions are available which do not overwrite the configuration. If the standard firmware file is named e.g. FW 2.00 , the name of the firmware which does not overwrite existing settings is then FW 2.F0.

(The "F" is indicating the non overwrite version)

The PN5190B1 checks if the new major version number is equal or higher than the current one. In case the major version number of the new firmware to be installed is smaller than the already installed version number of the firmware, the secure firmware update is rejected. Downgrading major firmware versions is therefore not possible.

Upgrading and therefore increasing major firmware versions is always possible.

In case of any failure or exception during the download (e.g. caused by a communication error or power-off), the PN5190B1 remains in the secure firmware download mode until a full firmware update sequence has been performed successfully.

Features of the automatic secure firmware update:

• Works without download request pin

• No special implementation of SPI interface handling

• Maximum integrity: Only encrypted and signed firmware images download possible

• Updating the firmware overwrites existing all previous EEPROM configurations.

9.21 SPI host interface

The interface of the PN5190B1 to a host microcontroller is based on a SPI interface.

The maximum SPI speed is 15 Mbit/s and fixed to CPOL = 0 and CPHA = 0. Only a halfduplex data transfer is supported. There is no chaining allowed, meaning that the whole instruction has to be sent or the whole receive buffer has to be read out. The whole transmit buffer shall be written at once as well. No NSS assertion is allowed during data transfer.

The SPI host interface is designed to support the typical interface supply voltages of 1.8

V and 3.3 V of CPUs. A dedicated supply input which defines the host interface supply voltage independent from other supplies is available (pin VDDIO).

There is no external pull-up / pull-down resistor required, the SPI pads are automatically configured by the PN5190B1.

Only a voltage of 1.8 V or 3.3 V is supported, but no voltage in the range of 1.95 V to 2.4

Note: The Voltage on pin VDDIO must always be smaller or equal to the Voltage on pin

VBAT.

Master in slave out (MISO)

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The MISO line is configured as an output in a slave device. It is used to transfer data from the slave to the master, with the most significant bit sent first. The MISO signal is put into 3-state mode when NSS is high.

Master out slave in (MOSI)

The MOSI line is configured as an input in a slave device. It is used to transfer data from the master to a slave, with the most significant bit sent first.

Serial clock (SCK)

The serial clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines.

Not slave select (NSS)

The slave select input (NSS) line is used to select a slave device. It shall be set to low before any data transaction starts and must stay low during the transaction.

9.22 Host interface commands

9.22.1 Logical command layer

PN5190B1 has two main modes of operation to communicate with the host controller:

1. TLV-Command response-based communication

2. HDLL-Based communication, used when device is triggered to enter the “download mode”, to update its firmware.

The description of the transport layer in the next chapters is limited to TLV-based command-response communication.

For more information see

[3]

9.22.1.1 Logical frame definition

A SPI frame starts with the falling edge of NSS and ends with the rising edge of NSS.

SPI is per physical definition full duplex but PN5190B1 uses SPI in a half-duplex mode.

SPI mode is limited to CPOL 0 and CPHA 0 with a max clock speed of 15 MHz.

Every SPI frame is composed of a 1-byte header and n-bytes of body.

9.22.1.2 Logical flow definition

The HOST always sends as a first byte the flow indication byte whether it wants to write or read data from the PN5190B1.

In case of a read request and no data is available, the response contains 0xFF.

The data after the flow indication byte is one or several messages.

For every NSS assertion, the first byte is always a HEADER (flow indication byte), it can be either 0x7F/0xFF with respect to write/read operation.

9.22.1.3 Logical message type definition

A host controller communicates with PN5190B1 using messages which are transported within SPI frames.

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There are three different message types:

• Command

• Response

• Event

Commands are only sent from host controller to PN5190B1 responses.

Events are only sent from PN5190B1 to host controller.

Allowed sequences and rules:

• Command is always acknowledged by a response

• Host Controller is not allowed to send another command before receiving a response to a previous command, except in concatenation

• Events may be sent asynchronously at any time (NOT interleaved within a command/ response pair)

• EVENT messages are never combined with the RESPONSE messages within one frame.

9.22.1.4 Logical message format

Type (T) => 1 byte

Bit[7] Message Type

0: COMMAND or RESPONSE message

1: EVENT message

Bit[6:0]: Instruction Code

Length (L) => 2 bytes (large endian format)

Length of the message body

Value (V) => N bytes

Value/data of the TLV (Command Parameters / Response data) based on Length field

(Large endian format)

9.22.1.5 Split frame definition

COMMAND message must be sent in one SPI frame RESPONSE and EVENT messages can be read in multiple SPI frames, e.g., to read out the length byte.

RESPONSE and EVENT messages can be read in single SPI frame but delayed by NO-

CLOCK in between, e.g., to read out the length byte.

9.22.2 Host interface command list

PN5190B1 command/response list

Table 14. Host interface commands

Command code PN5180 legacy command

0x00 Yes

Command

WRITE_REGISTER

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0x21

0x22

0x23

0x24

0x25

0x0E

0x0F

0x10

0x11

0x12

0x09

0x0A

0x0B

0x0C

0x0D

0x04

0x05

0x06

0x07

0x08

Table 14. Host interface commands

...continued

Command code PN5180 legacy command

Command

0x01 Yes WRITE_REGISTER_OR_MASK

0x02

0x03

Yes

WRITE_REGISTER_AND_MASK

WRITE_REGISTER_MULTIPLE

Yes

READ_REGISTER

READ_REGISTER_MULTIPLE

WRITE_EEPROM

READ_EEPROM

TRANSMIT_RF_DATA

0x13

0x14

0x15

0x16

0x17 - 0x19

0x1A

0x1B-0x1F

0x20

Yes

RETRIEVE_RF_DATA

EXCHANGE_RF_DATA

MFC_AUTHENTICATE

EPC_GEN2_INVENTORY

LOAD_RF_CONFIGURATION

UPDATE_RF_CONFIGURATION

GET_ RF_CONFIGURATION

RF_ON

RF_OFF

CONFIGURE_ TESTBUS_DIGITAL (not available for engineering samples)

CONFIGURE_TESTBUS_ANALOG (not available for engineering samples)

CTS_ENABLE

CTS_CONFIGURE

Yes

CTS_RETRIEVE_LOG

RFU

RECEIVE_RF_DATA

RFU

SWITCH_MODE_NORMAL

SWITCH_MODE_AUTOCOLL

SWITCH_MODE_STANDBY

SWITCH_MODE_LPCD

SWITCH_MODE_SUSPEND

SWITCH_MODE_DOWNLOAD

0x26

0x27

0x28 - 0x3F -

GET_DIE_ID

GET_VERSION

RFU

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Table 14. Host interface commands

...continued

Command code PN5180 legacy command

Command

0x40 RFU

0x41

0x41 - 0x50 -

No PRBS_TEST

RFU

9.22.3 Command WRITE_REGISTER (00h)

Description

This instruction is used to write a 32-bit value (little endian) to a logical register.

Conditions

The address of the register must exist and the register must either have the READ-

WRITE or WRITE-ONLY attribute.

Event

There are no events for this command.

Command

Table 15. WRITE_REGISTER

Payload Length

(byte)

Command code 1

Parameter 1

Response

Value/Description

0x00

Status

0x00: STATUS_SUCCESS

0x018: STATUS_INSTR_ERROR

9.22.4 Command WRITE_REGISTER_OR_MASK (01h)

Description

This instruction is used to modify the content of register using a logical OR operation.

The content of the register is read and a logical OR operation is performed with the provided mask. The modified content is written back to the register.

PN5190B1

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Conditions

The address of the register must exist and the register must either have the READ-

WRITE or WRITE-ONLY attribute.

Event

There are no events for this command.

Command

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Table 16. WRITE_REGISTER_OR_MASK

Payload Length

(byte)

Value/Description

Command code 1 0x01

Parameter 1

4 byte bitmask:

Bitmask used as operand for logical OR operation.

Response 1 Status

0x00: STATUS_SUCCESS

0x018: STATUS_INSTR_ERROR

9.22.5 Command WRITE_REGISTER_AND_MASK (02h)

Description

This instruction is used to modify the content of register using a logical AND operation.

The content of the register is read and a logical AND operation is performed with the provided mask. The modified content is written back to the register.

Conditions

The address of the register must exist and the register must either have the READ-

WRITE or WRITE-ONLY attribute.

Event

There are no events for this command.

Command

Table 17. WRITE_REGISTER_AND_MASK

Payload Length

(byte)

Value/Description

Command code 1 0x02

Parameter 1 Register address

Response 1

Bitmask

Bitmask used as operand for logical AND operation.

Status

0x00: STATUS_SUCCESS

0x018: STATUS_INSTR_ERROR

9.22.6 Command WRITE_REGISTER_MULTIPLE (03h)

Description

This instruction behaves like WRITE_REGISTER, WRITE_REGISTER_OR_MASK and

WRITE_REGISTER_AND_MASK with the possibility to combine them. In fact, it takes an array of register-type-value set and performs appropriate action. The type reflects the action which is either write register, logical OR operation on a register or logical AND operation on a register.

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Conditions

The respective logical address of the register within a set must exist. The register access attribute must allow execution of required action (type):

• Write action: READ-WRITE or WRITE-ONLY attribute

• OR mask action: READ-WRITE attribute

• AND mask action: READ-WRITE attribute

The size of the parameter array must be in the range from 1 – 43, inclusive. Field ‘Type’ must be in the range of 1 – 3, inclusive.

In case of an exception, the operation is not rolled-back, i.e. registers which have been modified until the exception occurs remain in modified state. Host has to take care to recover a defined state.

Event

There are no events for this command.

Command

Table 18. WRITE_REGISTER_MULTIPLE

Payload Length (byte) Value/Description

Command code

Parameter

6...258

(6 x 1….6 x 43)

0x03

Array of up to 43 {Register address element, Action element, Content element}

1 byte Register address element

Response 1

1 byte

4 bytes

Type

0x01: Write Register

0x02: Write Register OR Mask

0x03: Write Register AND Mask

Content element

32-bit register value which has to be written to register address, or 32bit bitmask used for logical operation with content available at register address

Status:

0x00: STATUS_SUCCESS

0x018: STATUS_INSTR_ERROR

9.22.7 Command READ_REGISTER (04h)

Description

This instruction is used to read a 32-bit value (little endian) to a register. The register content is present in the response, as 4 byte value.

Conditions

The address of the register must exist.

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The register must either have the READ-WRITE or WRITE-ONLY attribute.

Event

There are no events for this command.

Command

Table 19. READ_REGISTER

Payload Length

(byte)

Command code 1

Parameter 1

Response 1

Value/Description

0x04

Address of the register to be read out

Status

0x00: STATUS_SUCCESS

0x018: STATUS_INSTR_ERROR

32-bit register value which has been read out.

PN5190

NFC frontend

9.22.8 Command READ_REGISTER_MULTIPLE (05h)

Description

This instruction is used to read multiple logical registers at once. The result (content of each register) is provided in the response to the instruction. The register address itself is not included in the response. The order of the register contents within the response corresponds to the order of the register addresses provided within the instruction.

Conditions

All register addresses within the instruction must exist. The access attribute for each register must either be READ-WRITE or READ-ONLY. The size of ‘Register Address’ array must be in the range from 1 – 18, inclusive.

Event

There are no events for this command.

Command

Table 20. READ_REGISTER_MULTIPLE

Payload Length (byte) Value/Description

Command code 1 0x05

Parameter 1..18

Array of up to 18 elements {Register address element }

1 Register address element

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Table 20. READ_REGISTER_MULTIPLE

...continued

Payload Length (byte) Value/Description

Response 1 Status

0x00: no error

0x01: error

4...72

Array of up to 18 {Register content element}

4..72

9.22.9 Command WRITE_EEPROM (06h)

Description

The accessible area in EEPROM is 5119 bytes long and starts at EEPROM address 0.

This instruction is used to write one or more values to EEPROM. The field ‘Values’ contains the data to be written to EEPROM starting at the address given by field

‘EEPROM Address’. The data is written in sequential order.

This is a blocking command, the device is blocked during the write operation. This will take approximately 2.85 ms, termination of the EEPROM write (programming) is indicated by the response to the command.

Conditions

‘EEPROM Address’ field must be in the range from 0 – 5119, inclusive. Write operation must not go beyond EEPROM address 5119. Error response will be sent to the host if address exceeds 5119.

Event

There are no events for this command.

PN5190B1

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Command

Table 21. WRITE_EEPROM

Payload length

(byte)

Command code 1

Parameter 2

Response -

1..5119

Value/Description

0x06

EEPROM Address

Address in EEPROM from which write operation starts

{EEPROM Address}

Array of up to 5119 {EEPROM content element}

EEPROM content

1..5119 Byte Values which have to be written to EEPROM in sequential order

Status

0x00: no error

0x01: ERROR due to wrong address

0x02: PROGRAMM ERROR

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9.22.10 Command READ_EEPROM (07h)

Description

This instruction is used to read back data from EEPROM memory area. The field

‘EEPROM Address’ indicates the start address of the read operation. The response contains the data read from EEPROM.

Conditions

‘EEPROM Address’ field must be in the range from 0 – 5120, inclusive. Read operation must not go beyond EEPROM address 5120. Error response shall be sent to the host if the address exceeds 5120.

Event

There are no events for this command.

Command

Table 22. READ_EEPROM

Payload Length (byte) Value/Description

Command code 1 0x07

Parameter 2

Response

1...1024

Address in EEPROM from which read operation starts

(EEPROM Address)

Number of bytes to read from EEPROM

0x00: no error

0x01: error

Array of up to 1024 bytes {EEPROM content}

1 EEPROM content

9.22.11 Command TRANSMIT_RF_DATA (08h)

Description

This instruction is used to write data into the internal CLIF transmission buffer and start transmission. The size of this buffer is limited to 1024 bytes. After this instruction has been executed, an RF reception is started automatically.

The command returns immediately after Transmission is complete not waiting for the reception completion.

Conditions

The number of bytes within the ‘TX Data’ field must be in the range from 1 – 1024, inclusive.

The command must not be called during an ongoing RF transmission.

Event

There are no events for this command.

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Command

Table 23. TANSMIT_RF_DATA

Payload Length

(byte)

Command code 1

Value/Description

0x08

Parameter 1

1-1024

Number of valid bits in last Byte:

0x00: All bits of last byte are transmitted

0x01....0x07: Number of bits within last byte to be transmitted

TxData

Data which shall be used during next RF transmission

Response 1 Status

0x00 no error

0x01 error

0x02 RF Field is not switched on (if reader mode is active)

0x03 no RF Field present (if target mode is active)

9.22.12 Command RETRIEVE_RF_DATA (09h)

Description

This instruction is used to read data from the internal CLIF RX buffer, which contains the RF response data (if any) posted to it from the previous execution of

EXCHANGE_RF_DATA with option not to include the received data in the response or

TRANSMIT_RF_DATA command.

Conditions

Event

There are no events for this command.

Command

Table 24. RETRIEVE_RF_DATA

Payload Length

(byte)

Value/Description

Command code 1

Parameter 0

Response 1

0x09

Empty

1...1024

Status of the operation:

0x00: PN5190B1_STATUS_INSTR_SUCCESS

0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is present)

RX data which has been received during last successful RF reception expected from executing the commands EXCHANGE_

RF_DATA or TRANSMIT_RF_DATA

9.22.13 Command EXCHANGE_RF_DATA (0Ah)

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Description

The RF exchange function performs a transmission of the TX data and is waiting for the reception of any RX data.

The function returns in case of a reception (either erroneous or correct) or a timeout that happened. The timer is started with the END of TRANSMISSION and stopped with the

START of RECEPTION. The timeout value pre-configured in EEPROM will be used.

If transceiver_state is

• IDLE: the Exchange Data mode is entered.

• WAIT_RECEIVE: the transceiver state is reset to Exchange Data Mode in case of initiator bit is set

• WAIT_TRANSMIT: the transceiver state is reset to Exchange Data Mode in case initiator bit is NOT set

The field ‘Number of valid bits in last Byte’ indicates the exact data length to be transmitted. The command terminates after end of transmission and end of reception.

Conditions

Size of ‘TX Data’ field must be in the range from 0 – 1024, inclusive.

‘Number of valid bits in last Byte’ field must be in the range from 0 – 7.

The command must not be called during an ongoing RF transmission. Command shall ensure the right state of the Transceiver for transmitting the data.

Event

There are no events for this command.

Command

Table 25. EXCHANGE_RF_DATA

Payload Length

(byte)

Value/Description

Command code 1 0x0A

Parameter 1 Number of valid bits in last Byte:

0: All bits of last byte are transmitted

1-7: Number of bits within last byte to be transmitted

Response

0 - 1024

RF Exchange Config

Configuration of the RFExchange function.

TxData

Data which has to be sent out via CLIF using EXCHANGE_RF_

DATA command. Length = 0 – 1024 bytes

Status

0x00 no error

0x01 Timeout

0x10 RF Field is not switched on (if reader mode is active)

0x18 error (in payload)

RX_STATUS

If RX_STATUS is requested in RF Exchange Config parameter

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Table 25. EXCHANGE_RF_DATA

...continued

Payload Length

(byte)

Value/Description

4 RF_STATUS

If RF_STATUS is requested in RF Exchange Config parameter

1-1024

EVENT_STATUS

If EVENT_STATUS is requested in RF Exchange Config parameter

Rx_Data

RX data which has been received during last successful RF reception.

Table 26. EXCHANGE_RF_DATA Parameter RF Exchange Config: Bitmask

Bitmask / Bit position Description

B7 B6 B5 B4 B3 B2 B1 B0

X X X X

RFU

Include RX Data in response based on RX_STATUS, if bit set to 1b.

Include EVENT_STATUS register in response, if bit set to 1b.

Include RF_STATUS register in response, if bit is set to 1b.

X Include RX_STATUS register in response, if bit is set to 1b.

9.22.14 Command MFC_AUTHENTICATE (0Bh)

This command is used to perform a MIFARE Classic Authentication on an activated card.

It takes the key, card UID and the key type to authenticate at given block address. The response contains one byte indicating the authentication status.

Conditions

Field ‘Key’ must be 6 bytes long. Field ‘Key Type’ must contain the value 0x60 or 0x61.

Block address may contain any address from 0x00 – 0xFF, inclusive. Field ‘UID’ must be bytes long and should contain the 4 byte UID of the card. An ISO14443-3 MIFARE

Classic card should be put into state ACTIVE or ACTIVE* prior to execution of this instruction.

In case of a runtime error related to the authentication, the field ‘Authentication Status’ is set accordingly.

Event

There are no events for this command.

Command

Table 27. MFC_AUTHENTICATE

Payload Length

(byte)

Value/Description

Command code 1 0x0B

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Table 27. MFC_AUTHENTICATE

...continued

Payload Length

(byte)

Value/Description

Parameter 6 Key

Authentication key to be used.

1 KeyType

0x60: Key Type A

0x61: Key Type B

Response

Block Address

The address of the block for which the authentication has to be performed.

UID

UID of the card.

Status

0x00 no error (Authentication successful)

0x01 error (Authentication failed)

0x02 Timeout waiting for card response (card not present).

0x07 Authentication error: Indicates that MFC authentication failed (permission denied)

9.22.15 Command EPC_GEN2_INVENTORY (0Ch)

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This instruction is used to perform an inventory of ISO18000-3M3 tags. It implements an autonomous execution of several commands according to ISO18000-3M3 in order to guarantee the timings specified by that standard.

If present in payload of the instruction, first a "Select" command is executed followed by a "BeginRound" command. If there is a valid response in the first timeslot (no timeout, no collision), the instructions sends an ACK (acknowledge) and saves the received PC/XPC/

UII.

The instruction then performs an action according to the field ‘Timeslot Processed

Behavior’:

• if this field is set to 0 a NextSlot command is issued to handle the next timeslot. This is repeated until the internal buffer is full

• If this field is set to 1 the algorithm pauses

• If this field is set to 2 a Req_Rn command is issued if, and only if, there has been a valid tag response in this timeslot command.

Conditions

The field ‘Select Command Length’ must contain the length of the field ‘Select

Command’, which must be in the range from 1 – 39, inclusive. If ‘Select Command

Length’ is 0, the fields ‘Valid Bits in last Byte’ and ‘Select Command’ must not be present.

The field Bits in last Byte should contain the number of bits to be transmitted in the last byte of the ‘Select Command’ field. The value must be in the range from 1 – 7, inclusive.

If the value is 0, all bits from last byte from ‘Select Command’ field are transmitted. The field ‘Select Command’ should contain a Select command according to ISO18000-3M3 without trailing CRC-16c and must have the same length as indicated in field ‘Select

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Command Length’. Field ‘BeginRound Command’ should contain a BeginRound command according to ISO18000-3M3 without trailing CRC-5. The last 7 bits of the last byte of ‘BeginRound Command’ are ignored as the command has an actual length of 17 bits. ‘Timeslot Processed Behavior’ must contain a value from 0 – 2, inclusive.

Event

There are no events defined for this command.

Command

Table 28. EPC_GEN2_INVENTORY

Payload Length

(byte)

Value/Description

Command code 1 0x0C

Parameter 1

Resume Inventory:

00: Initial GEN2_INVENTORY

01: Resume the GEN2_INVENTORY command – the remaining fields below are empty (any payload is ignored)

Select Command Length

0x00 No Select command is set prior to BeginRound command.

‘Valid Bits in last Byte’ field and ‘Select command’ field shall not be present.

0x01...0x27: Length (1d...39d) of the ‘Select command’ field.

0...39

Valid Bits in last Byte

0: All bits of last byte of ‘Select command’ field are transmitted.

1-7: Number of bits to be transmitted in the last byte of ‘Select command’ field.

If present, this field contains the Select command (according to ISO18000-3, Table 47) which is sent prior to BeginRound command. CRC-16c will not be included.

Response

3-69

BeginRound Command

This field contains the BeginRound command (according to

ISO18000-3, Table 49). CRC-5 will not be included

Timeslot Processed Behavior

0x00: Response shall contain max. Number of timeslots which may fit in response buffer.

0x01: Response shall contain only one timeslot.

0x02: Response shall contain only one timeslot. If timeslot contains valid card response, also the card handle is included.

Status

0x00 no error

0x01 syntax error (no further bytes)

Timeslot array {Timeslot status element, Tag reply length element, Valid bits in last byte element}

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Table 28. EPC_GEN2_INVENTORY

...continued

Payload Length

(byte)

Value/Description

1 Timeslot status element

0x00: Tag response available. ‘Tag Reply Length’ field,

‘Valid bits in last byte’ field, and ‘Tag reply’ field present.

0x01: Tag response available.

0x02: No tag replied in timeslot. ‘Tag Reply Length’ field and ‘Valid bits in last byte’ field, shall be set to zero. ‘Tag reply’ field shall not be present.

0x03: Two or more tags responded in the timeslot.

(Collision). ‘Tag Reply Length’ field and ‘Valid bits in last byte’ field, shall be set to zero. ‘Tag reply’ field shall not be present.

Tag Reply Length element

0x00...0x42: Length of ‘Tag Reply’ field [0d...66d]. If Tag

Reply Length is 0x00, then the Tag Reply field is not present.

Valid bits in last byte element

0: All bits of last byte of ‘Tag reply’ field are valid.

1: Number of valid bits of last byte of ‘Tag reply’ field. If

Tag Reply Length is zero, the value of this byte shall be ignored.

0 or 2

Tag Reply n-bytes reply of the tag according to ISO18000-3_2010, Table

56.

Tag Handle

2 byte handle of the tag, in case field ‘Timeslot Status’ is set to

‘1’. Otherwise field not present

9.22.16 Command LOAD_RF_CONFIGURATION (0Dh)

Description

This instruction is used to load the RF configuration from E2PROM into registers. It is possible to configure RF technology, mode (target/initiator) and baud rate. Configurations can be loaded separately for the receiver (RX configuration) and transmitter (TX configuration). The value 0xFF has to be used if the existing configuration for either TX or

RX shall not be updated.

Conditions

Field ‘TX Configuration’ must be in the range from 0x0 – 0x2B, inclusive. If the value is

0xFF, TX configuration is not changed.

Field ‘RX Configuration’ must be in the range from 0x80 – 0xAB, inclusive. If the value is

0xFF, RX configuration is not changed.

A special configuration with TX Configuration = 0xFF and RX Configuration = 0xAC is used load the Boot-up registers one time. This special configuration is required to update the register configurations (both TX and RX) that are different from the IC reset values.

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Event

There are no events for this command.

Command

Table 29. LOAD_RF_CONFIGURATION

Payload Length

(byte)

Value/Description

Command code 1 0x0D

Parameter 1

TX Configuration (Transmitter)

0xFF: actual TX configuration not changed.

others: Corresponding TX configuration loaded.

RX Configuration (Receiver)

0xFF: actual RX configuration not changed.

others: Corresponding RX configuration loaded.

Response 1 Status of the operation:

0x00 STATUS_SUCCESS

0x08 STATUS_MEMORY_ERROR

0x18 STATUS_INSTR_ERROR

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9.22.16.1 Parameter for command LOAD_RF_CONFIGURATION

Table 30. TX Parameter for command LOAD_RF_CONFIGURATION

PCD

Setting

0x00

Protocol

ISO14443A alternate Speed

NFC-PI-106, NFC-AI-106 106

0x01

0x02

ISO14443A

ISO14443A -

212

424

0x08

0x09

0x0a

0x0b

0x0c

0x03

0x04

0x05

0x06

0x07

0x0d

0x0e

0x0f

ISO14443A

ISO14443B

FeliCa

ISO15693_ASK100

ISO15693_ASK10

ISO180003m3

848

106

212

424

848

NFC-PI-212, NFC-AI-212 212

NFC-PI-424, NFC-AI-424 424

TARI=18_

88us

Modulation

Miller

NRZ

1out4/ASK100

1out4/ASK10

ASK

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Table 30. TX Parameter for command LOAD_RF_CONFIGURATION

...continued

Setting

0x10

Protocol

ISO180003m3 alternate

PICC

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1a

0x1B

0x1C

0x1D

0x1E..0xFE

0xFF

ISO14443A-PICC

NFC-PT-212

NFC-PT-424

NFC-AT-106

NFC-AT-212

NFC-AT-424

GTM

Idle_RF_Config

No change

NFC-PT-106

Table 31. RX Parameter for command LOAD_RF_CONFIGURATION

Setting Protocol alternate

PCD 0x80 ISO14443A NFC-PI-106, NFC-

AI-106

0x81

0x82

0x83

0x84

0x85

ISO14443A

ISO14443B

0x86

0x87

0x88

0x89

0x8a

0x8b

ISO14443B

FeliCa

ISO15693

NFC-PI-212, NFC-

AI-212

NFC-PI-424, NFC-

AI-424

Speed

106

212

424

848

106

212

424

848

212

424

6P6

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All

212

424

106

212

424

106

212

424

848

Speed

TARI=9_

44us

Modulation

ASK

All

Manch SubC

BPSK

Modulation

Manch SubC

BPSK

Manch424

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Table 31. RX Parameter for command LOAD_RF_CONFIGURATION

...continued

0x8c

0x8d

ISO15693

0x8e

0x8f

0x90

0x91

ISO15693

ISO180003m3_

Manch424_4

ISO180003m3_

Manch424_2

ISO180003m3_

Manch848_4

0x92

PICC 0x93

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

ISO180003m3_

Manch848_2

ISO14443A-PICC NFC-PT-106

ISO14443A-PICC -

NFC-PT-212 -

NFC-PT-424

NFC-AT-106

NFC-AT-212 -

0x9B

0x9C

0x9D

0x9E

0x9F-0xFE

0xFF

NFC-AT-424

GTM

Idle_RF_Config

Boot no change

106

212

106

212

424

All

106

212

424

848

212

424

106

212

Manch424

Manch424/4 period

Manch424/2 period

Manch848/4 period

Manch848/2 period

All

Miller

9.22.17 Command UPDATE_RF_CONFIGURATION (0Eh)

Description

This instruction is used to update the RF configuration within the EEPROM. The instruction allows updating at register granularity value, i.e. not the complete register set needs to be updated.

Conditions

The size of the field array must be in the range from 1 – n, inclusive. The field array

‘Configuration’ must contain a set of elements for ‘RF Configuration’, ‘Register Address’ and ‘Value’. The field ‘RF configuration’ must be in the range from 0x00 – 0x2B for the

TX configuration and 0x80 – 0xAB for the RX configuration, inclusive. The address within field ‘Register Address’ must exist within the respective RF configuration. Field ‘Value’ should contain a value which has to be written into the given register and must be 4 bytes long.

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Event

There are no events for this command.

Command

Table 32. UPDATE_RF_CONFIGURATION

Payload Length

(byte)

Value/Description

Command code 1 0x0E

Parameter n Array of n { RF configuration element, Register address element,

Value element }

Response 1

RF configuration element

RF Configuration for which the register has to be changed.

4 Value element

Value which has to be written into the register

Status of the operation:

0x00 STATUS_SUCCESS

0x08 STATUS_MEMORY_ERROR

0x18 STATUS_INSTR_ERROR

9.22.18 Command GET_ RF_CONFIGURATION (0Fh)

Description

This instruction is used to read out an RF configuration. The register address-value-pairs are available in the response. In order to know how many pairs are to be expected, first size information can be retrieved from the first TLV, which indicates the total length of the payload.

Conditions

The field ‘RF configuration’ must be in the range from 0x0 – 0x2B for TX Configuration and 0x80 – 0xAB for the RX configuration, inclusive.

Event

There are no events for this command.

Command

Table 33. GET_RF_CONFIGURATION

Payload Length

(byte)

Value/Description

Command code 1

Parameter 1

0x1F

RF Configuration

RF Configuration for which the set of register value pairs have to be retrieved.

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Table 33. GET_RF_CONFIGURATION

...continued

Payload Length

(byte)

Value/Description

Response 1 Status of the operation:

0x00 STATUS_SUCCESS

0x18 STATUS_INSTR_ERROR n * 5 Array of n { Register address element, Register value element }; n defined by first TLV

1 Register Address element

4 Register value element

32-Bit register data content.

9.22.19 Command RF_ON (10h)

Description

This instruction is used to activate the transmitter output.

The RF_ON command shall be always sent with a guard time of at least 5.1 ms after a previous RF_OFF command.

Conditions

The transmitter needs to be supplied to allow the emission of an RF field.

Event

There are no events for this command.

Command

Table 34. RF_ON

Payload Length

(byte)

Command code 1

Parameter 1

Value/Description

Response 1

0x10

RF On

Bit 0 = 0: Use collision avoidance by RF Level detector

Bit 0 = 1: Disable collision avoidance by RF level detector

Bit 1 = 0 No P2P active

Bit 1 = 1 P2P active

Status

0x00 no error (RF field switched on)

0x01 error (wrong payload of command)

0x02 RF Field not switched on due to detected RF collision.

9.22.20 Command RF_OFF (11h)

Description

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This instruction is used to de-activate the transmitter output.

Conditions

No conditions are required to execute this command.

Event

There are no events for this command.

Command

Table 35. RF_OFF

Payload Length

(byte)

Command code 1

Parameter

Response

Value/Description

0x11

No payload

Status

0x00 no error (RF field switched off)

0x01 error (wrong payload of command)

9.22.21 Command CONFIGURE_ TESTBUS_DIGITAL (12h)

Description

This instruction is used to route digital test bus signals to the available test buses TB0

(Testbus_0) and TB1 (Testbus_1).

Conditions

No conditions are required to execute this command.

Event

There are no events for this command.

Command

Table 36. RF_OFF

Payload Length

(byte)

Command code 1

Parameter 1

Response

Value/Description

0x12

TB_SignalIndex

TB_BitIndex

TB_PadIndex

Status

0x00 no error

0x018 Instruction error

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9.22.22 Command CONFIGURE_TESTBUS_ANALOG (13h)

Description

This instruction is used activate analog debug signals to the available test signal out pads

AUX1, AUX2.

Conditions

No conditions are required to execute this command.

If used, ADC-Q needs to be routed always to AUX1, ADC-I needs to be routed always to AUX2

Event

There are no events for this command.

Command

Table 37. RF_OFF

Payload Length

(byte)

Command code 1

Parameter 1

Value/Description

Response

0x12

Config: Configurable bits

Combined_Mode Signal:

0 – ADCI/ADCQ

1 – pcrm_if_rssi

2-0xFF – Reserved

TB_SignalIndex0

Signal index of the analog signal

TB_SignalIndex1

Signal index of the analog signal

Shift_Index0

DAC0 input shift positions. Direction will be decided by bit_0 in

Config

Shift_Index1

DAC1 input shift positions. Direction will be decided by bit_1 in bConfig.

Mask0: DAC0 mask

Mask1: DAC1 mask

Status

0x00 no error

0x018 Instruction error

9.22.23 Command CTS_ENABLE (14h)

Description

This instruction is used to enable/disable the CTS feature.

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Conditions

Event

In case a trigger condition is fulfilled, an event will be raised:

Value/Description Payload

EVENT

Length

(byte)

Command

Table 38. CTS_ENABLE

Payload Length

(byte)

Command code 1

Parameter 1

00 … TRIGGER has occurred, data is ready for reception.

Value/Description

Response 1

0x14

Enable

0x00: Disable the CTS Logging Feature

0x01: Enable the CTS Logging Feature

0x02-0xFF: RFU

0x00 no error

0x01 error

9.22.24 Command CTS_CONFIGURE (15h)

Description

This instruction is used to configure the all the required CTS registers such as triggers, test bus registers, sampling configuration etc.

The captured data to be sent as part of the response to CTS_RETRIEVE_LOG command.

Event

There is no event for this instruction.

Command

Table 39. CTS_CONFIGURE

Payload Length

(byte)

Command code 1

Value/Description

0x15

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Table 39. CTS_CONFIGURE

...continued

Payload Length

(byte)

Value/Description

Parameter 1 PRE_TRIGGER_SHIFT

Defines the length of the after-trigger acquisition sequence in

256-bytes units.

0 means no shift; n means n*256 bytes block shift.

Note: Valid only if TRIGGER_MODE is “PRE” or “COMB” trigger mode

1 TRIGGER_MODE

Specifies Acquisition mode to be used.

0x00 - POST mode

0x01 - RFU

0x02 - PRE Mode

0x03 - 0xFF - Invalid

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Table 39. CTS_CONFIGURE

...continued

Payload Length

(byte)

Value/Description

1 RAM_PAGE_WIDTH

Specifies the amount of on-chip memory that is covered by an acquisition. Granularity is chosen by design as 256 Bytes (i.e. 64

32-bits words).

Valid values are as below:

0x00h - 256 bytes

0x01h - 512 bytes

0x02h - 768 bytes

0x03h - 1024 bytes

0x04h - 1280 bytes

0x05h - 1536 bytes

0x06h - 1792 bytes

0x07h - 2048 bytes

0x08h - 2304 bytes

0x09h - 2560 bytes

0x0Ah - 2816 bytes

0x0Bh - 3072 bytes

0x0Ch - 3328 bytes

0x0Dh - 3584 bytes

0x0Eh - 3840 bytes

0x0Fh - 4096 bytes

0x10h - 4352 bytes

0x11h - 4608 bytes

0x12h - 4864 bytes

0x13h - 5120 bytes

0x14h - 5376 bytes

0x15h - 5632 bytes

0x16h - 5888 bytes

0x17h - 6144 bytes

0x18h - 6400 bytes

0x19h - 6656 bytes

0x1Ah - 6912 bytes

0x1Bh - 7168 bytes

0x1Ch - 7424 bytes

0x1Dh - 7680 bytes

0x1Eh - 7936 bytes

0x1Fh - 8192 bytes

Note: if values provided is more than 0x1F, the value will be masked with 0x1F and resultant value will be considered.

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Table 39. CTS_CONFIGURE

...continued

Payload Length

(byte)

Value/Description

1 SAMPLE_CLK_DIV

The decimal value of this field specifies the clock rate division factor to be used during acquisition. CTS clock = 13.56 MHz /

2 SAMPLE_CLK_DIV

00 - 13560 kHz

01 - 6780 kHz

02 - 3390 kHz

03 - 1695 kHz

04 - 847.5 kHz

05 - 423.75 kHz

06 - 211.875 kHz

07 - 105.9375 kHz

08 - 52.96875 kHz

09 - 26.484375 kHz

10 - 13.2421875 kHz

11 - 6.62109375 kHz

12 - 3.310546875 kHz

13 - 1.6552734375 kHz

14 - 0.82763671875 kHz

15 - 0.413818359375 kHz

SAMPLE_BYTE_SEL

These bits are used to specify which bytes of the two 16bits input buses contribute to the interleave mechanism that generates data to be transferred to the on-chip memory. The meaning and usage of them is depending from the SAMPLE_

MODE_SEL values.

Note: Given value is always masked with 0x0F and then effective value is considered.

SAMPLE_MODE_SEL

Selects the sampling interleave mode as described by the CTS design specs. Decimal value 3 is reserved and will be treated as 0. Note: Given value is always masked with 0x03, and then effective value is considered.

TB0

Selects which test bus to be connected to TB0. Refer to list below (TB_Signal_Index value)

TB1

Selects which test bus to be connected to TB1. Refer to list below (TB_Signal_Index value)

TB2

Selects which test bus to be connected to TB2. Refer to list below (TB_Signal_Index value)

TB3

Selects which test bus to be connected to TB3. Refer to list below (TB_Signal_Index value)

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Table 39. CTS_CONFIGURE

...continued

Payload Length

(byte)

Value/Description

1 TTB_SELECT

Selects which TB to be connected to the trigger sources. Refer to list below (TB_Signal_Index value)

RFU

Send always 0x00000000

MISC_CONFIG

Trigger occurrences, polarity etc. Refer to (5) below for understanding of CTS configuration to use.

Response 1 0x00 no error

0x01 error

9.22.25 Command CTS_RETRIEVE_LOG (16h)

Description

This instruction retrieves the data log of the captured test bus data samples stored in the memory buffer.

CTS_RETREIVE_LOG is valid only if CTS_EVENT bit is set in the EVENT_STATUS register.

Event

There are no events for this command.

Command

Table 40. CTS_RETRIEVE_LOG

Payload Length

(byte)

Value/Description

Command code 1 0x16

Parameter 1

Response 1

ChunkSize

0x01-0xFF Contains the number of bytes of data expected.

Status of the operation

Expected values:

- STATUS_SUCCESS

- STATUS_INSTR_ERROR (No further data is present)

- STATUS_SUCCSES_CHAINING

1..n

CTSRequest

Captured Samples Data chunk. Maximum size is depended upon the ‘ChunkSize’ that has been provided as part of the command.

Total ChunkSize shall be available in the TLV header response.

9.22.26 Command RECEIVE_RF_DATA (1Ah)

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Description

This instruction waits for the command/data from the reader to be received. The instruction returns in case of a reception (either erroneous or correct) and is blocking or a timeout occurred. The timer is started with the END of TRANSMISSION and stopped with the START of RECEPTION. The default timeout value preconfigured in EEPROM shall be used.

Conditions

This instruction is valid only in “Card” mode or “Target” mode.

Error conditions for the reception are available in the register RX_STATUS_REG.

Event

There are no events for this command.

Command

Table 41. RECEIVE_RF_DATA

Payload Length

(byte)

Command code 1

Value/Description

0x1A

Parameter 1 7..4: RFU

3: Include RX Data in response based on RX_STATUS, if bit set

Response 1

1-1024

2: Include EVENT_STATUS register in response, if bit set

1: Include RF_STATUS register in response, if bit is set

0: Include RX_STATUS register in response, if bit is set

Status of the operation:

0x00: PN5190B1_STATUS_INSTR_SUCCESS

0x01: PN5190B1_STATUS_TIMEOUT

0x0A: PN5190B1_STATUS_NO_RF_FIELD

0x10: PN5190B1_STATUS_NO_EXTERNAL_RF_FIELD

0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is present)

If RX_STATUS is requested (little endian)

If RF_STATUS is requested (little endian)

If EVENT_STATUS is requested (little endian)

RX data which has been received during last successful RF reception.

9.22.27 Command SWITCH_MODE_NORMAL (20h)

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Description

The Switch Mode Normal command is used to terminate one of the modes Standby,

LPCD (not ULPCD) or Autocoll. The response indicates that the normal mode is entered.

Conditions

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Event

Table 42. EVT_SWITCH_MODE_NORMAL

Payload Length

(byte)

Value/Description

Event 1 Indicates that the normal mode is entered and PN5190B1 is able to receive new commands.

Command

Table 43. SWITCH_MODE_NORMAL

Payload Length

(byte)

Value/Description

Command code 1 0x20

Parameter 0 - (no payload)

Response 0 - (No data in response. Instead the EVT_SWITCH_MODE_

NORMAL is used to indicate the successful operation modeswitch)

9.22.28 Command SWITCH_MODE_AUTOCOLL (21h)

Description

The Switch Mode Autocoll automatically performs the card activation procedure in target mode.

Conditions

In case field ‘Mode’ is set to 2 (Autocoll): Field ‘RF Technologies’ (Table 21) must contain a bitmask indicating the RF Technologies to support during Autocoll, according to Table

22.

Field ‘Autocoll Mode’ must be in the range from 0 – 2, inclusive.

No instructions must be sent while being in this mode.

Termination of the command is indicated by an interrupt.

Event

The event notification is sent when the command has terminated and the normal mode is entered. Host shall read-out the response bytes based on the event value. Technology information is retrieved from the registers using the command READ_REGISTER or

READ_REGISTER_MULTIPLE.

Command

Table 44. EVT_SWITCH_MODE_AUTOCOLL

Payload Length

(byte)

Value/Description

Event 1 0X00 … PN5190B1 has been activated as a card

0X01 … No RF field or RF field has vanished

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Table 44. EVT_SWITCH_MODE_AUTOCOLL

...continued

Payload Length

(byte)

Value/Description

Autocoll_resp 0...n

0 … if previous field is 01

1..n bytes ATR_RES / ATS_RES as per ISO18092 / ISO1443-4

Table 45. SWITCH_MODE_AUTOCOLL

Payload Length

(byte)

Value/Description

Command code 1 0x21

Parameter 1 RF Technologies: Bitmask indicating the RF technology to listen for during Autocoll.

Response 1

Autocoll Mode

0x00: Autonomous mode not used i.e. Autocoll terminates when external RF field is not present.

Termination in case of

• NO RF FIELD or RF FIELD has disappeared

• PN5190B1 is ACTIVATED in TARGET mode

0x01Autonomous mode used.

When no RF field is present, Autocoll automatically enters standby mode. Once RF external RF field is detected, PN5190B

1 enters again Autocoll mode.

Termination in case of

• PN5190B1 is ACTIVATED in TARGET mode

0x02 Autonomous mode without standby used.

When no RF field is present, PN5190B1 waits until RF field is present before actually starting Autocoll algorithm. Standby is not used in this case.

Termination in case of

• PN5190B1 is ACTIVATED in TARGET mode

Status

0x00 no error

0x01 error (Switch mode has not been entered – due to wrong settings or due to standby prevention)

Table 46. RF Technologies parameter: Bitmask

Bitmask / Bit position Description

B7 B6 B5 B4 B3 B2 B1 B0

0 0 0 0 RFU

X listening for NFC-F Active is enabled

X listening for NFC-A Active is enabled listening for NFC-F is enabled

X listening for NFC-A is enabled

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9.22.29 Command SWITCH_MODE_STANDBY (22h)

Description

The Switch Mode Standby automatically sets the IC into standby mode.

Conditions

Event

The event notification is sent when the command has finished and the normal mode is entered.

Command

Table 47. EVT_SWITCH_MODE_STANDBY

Payload Length

(byte)

Value/Description

Event 1 Indicates wake-up source

0x01 … WUC

0x02 … RF Level Detector

0x03 … NSS low transition (HOSTIF activity)

Table 48. SWITCH_MODE_STANDBY

Payload Length

(byte)

Value/Description

Command code 1 0x22

Parameter 1 Wake-up Control

Bitmask controlling the wake-up source to be used.

Response

Counter Value

Used value for wake-up counter in msecs. Maximum supported value is 2690

Status

0x00 no error

0x01 error (Switch mode has not been entered – due to wrong settings or due to standby prevention)

Table 49. STANDBY control parameter: Bitmask

Bitmask / Bit position Description

B7 B6 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0

RFU

Wake-up on external RF field

X Wake-up on wake-up counter expired

9.22.30 Command SWITCH_MODE_LPCD (23h)

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Description

The Switch Mode LPCD performs a detuning detection on the antenna due to changing environment around the antenna. There are 2 different modes of LPCD. The HWbased solution offers a competitive power consumption with a reduced sensitivity. The

FW-based solution offers a higher sensitivity at the cost of a slightly increased power consumption. The configuration of the LPCD is done in the EEPROM register settings before the command is called.

Conditions

Before this command is issued, other configuration bits must be specified.

Event

The event notification is sent when the command has finished and the normal mode is entered.

Command

Table 50. EVT_SWITCH_MODE_LPCD

Payload Length

(byte)

Value/Description

Event 1 0x00: LPCD has detected a wake-up condition

Table 51. SWITCH_MODE_LPCD

Payload Length

(byte)

Value/Description

Command code 1 0x 23

Parameter 1

LPCD Type

0x00 Hardware-based ULPCD is used

0x01 Firmware-based LPCD is used

0x02-0xFF RFU

Counter Value

Used value for wake-up counter in msecs. Maximum supported value is 4096 (12 Bit), the counter input clock is 1 kHz

Response 1 Status

0x00 no error

0x01 error (Switch mode has not been entered – due to wrong settings)

9.22.31 Command SWITCH_MODE_DOWNLOAD (25h)

Description

The Switch Mode Download command enters the Firmware download mode.

Conditions

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The response signalizes that the command has been processed by the PN5190B1. After the response is read by the host and no error is indicated in the response, the download mode is entered.

Event

Command

Table 52. SWITCH_MODE_DOWNLOAD

Payload Length

(byte)

Value/Description

Command code 1 0x25

Parameter 0 - (SWITCH_MODE_DOWNLOAD command is called without any parameter)

Response 1 Status

0x00 no error

0x01 error (Switch mode has not been entered)

9.22.32 Command GET_DIE_ID (26h)

Description

This instruction is used to read-out the Die ID of the PN5190B1 chip.

Conditions

No conditions are required to execute this command.

Event

There are no events for this command.

Command

Table 53. GET_DIE_ID

Payload Length

(byte)

Command code 1

Parameter 0

Response 1

Value/Description

0x26

No payload

Status of the operation:

0x00: PN5190B1_STATUS_INSTR_SUCCESS

0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is present)

16 bytes DIE ID.

9.22.33 Command GET_VERSION (27h)

Description

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This instruction is used to read-out the HW version, ROM version and the FW version of the PN5190B1 chip.

Conditions

No conditions are required to execute this command.

Event

There are no events for this command.

Command

Table 54. GET_VERSION

Payload Length

(byte)

Command code 1

Parameter

Response

Value/Description

0x27

No payload

Status of the operation:

0x00: PN5190B1_STATUS_INSTR_SUCCESS

0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is present)

Hardware Version

ROM Code Version

Firmware version (used for secure firmware download)

Example:

Get Version with FW v2.0

[HOST] -> [0x00 0x04 0xE1 0x00 0x00 0x00 0x75 0x48]

[HOST] <- [0x00 0x08 STAT HW_V RO_V MODEL_ID FM1V FM2V RFU1 RFU2 CRC16] o/p : 00 08 00 51 02 00 00 02 00 00 7F 10

HW_Version = x51, ROM_Version = x02, MODEL_ID = x00, FirmwareVersion = 02.00

9.22.34 Command PRBS_TEST (41h)

Description

This instruction is used to generate the PRBS sequence for the different configurations of the reader mode protocols and bit-rates.

Conditions

This instruction is a blocking instruction and shall be terminated only with

SWITCH_MODE_NORMAL command.

Event

There are no events for this command.

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Command

Table 55. PRBS_TEST

Payload Length

(byte)

Command code 1

Parameter 1

Response

Value/Description

0x41 prbs_type

0x00: PRBS9 (default)

0x01: PRBS15

0x02-0xFF: RFU prbs_techno

0x00: ISO14443-A

0x01: ISO1443-B

0x02: FeliCa

0x03: ISO15693

0x04-0xFF: RFU prbs_baud

0x00: 106 kBit/s (default for type A,B,F)

0x01: 212 kBit/s

0x02: 424 kBit/s

0x03: 848 kBit/s

0x04: 26 kBit/s (default for ISO15693)

0x05-0xFF: RFU prbs_length

2 bytes indicating the prbs length of 1 byte up to 510 bytes data length of the transmission sequence

Status of the operation:

0x00: PN5190B1_STATUS_INSTR_SUCCESS

0x0A: PN5190B1_STATUS_NO_RF_FIELD

0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is present)

9.22.35 RESPONSE STATUS CODES

Table 56. RESPONSE STATUS CODES LIST

RESPONSE STATUS VALUE Value/Description

STATUS_SUCCESS 0x00 Indicates that operation completed successfully

STATUS_TIMEOUT 0x01 Indicates that the operation of the command resulted in timeout

0x02 Indicates that the operation of the command resulted in RF data integrity error STATUS_INTEGRITY_

ERROR

STATUS_RF_COLLISION_

ERROR

STATUS_RFU1

STATUS_INVALID_

COMMAND

0x03

0x04

0x05

Indicates that the operation of the command resulted in RF collision error

Indicates that the given command is invalid/not implemented

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Table 56. RESPONSE STATUS CODES LIST

...continued

RESPONSE STATUS VALUE Value/Description

STATUS_RFU2 0x06

STATUS_AUTH_ERROR 0x07

STATUS_MEMORY_

ERROR

0x08

Indicates that MFC authentication failed (permission denied)

Indicates that the operation of the command resulted in a programming error or internal memory error

STATUS_RFU4 0x09

STATUS_NO_RF_FIELD 0x0A

0x0B

0x0C

Indicates that there are no or error in internal RF field presence (applicable only if initiator/reader mode).

Indicates that invalid command frame length is received

STATUS_RFU5

STATUS_SYNTAX_

ERROR

STATUS_RESOURCE_

ERROR

STATUS_RFU6

STATUS_RFU7

0x0D

0x0E

0x0F

0x10

Indicates that an internal resource error occurred

STATUS_NO_

EXTERNAL_RF_FIELD

STATUS_RFU8

STATUS_USER_

CANCELLED

0x11

0x12

Indicates that no external RF field is present during the execution of the command (Applicable only in card/target mode)

Indicates that the present command in-progress is aborted

STATUS_PREVENT_

STANDBY

0x13

STATUS_RFU9 0x14

STATUS_CLOCK_ERROR 0x15

STATUS_RFU10 0x16

Indicates that chip is prevented to go into standby mode

Indicates that clock to the CLIF did not start

STATUS_PRBS_ERROR 0x17

STATUS_INSTR_ERROR 0x18

Indicates that the PRBS command returned an error

Indicates that operation of the command is failed (it may include, the error in instruction parameters, syntax error, error in operation itself, pre-requirements for the instruction is not met etc.…)

Indicates that access to internal memory is denied STATUS_ACCESS_

DENIED

STATUS_TX_FAILURE

STATUS_NO_ANTENNA

RFU

STATUS_INTERNAL_

ERROR

RFU

STATUS_SUCCSES_

CHAINING

0x19

0x1A

0x1B

0x1C-0x7E -

0x7F Indicates that the NVM operation failed

0x80-0xAE -

0xAF

Indicates that TX over RF is failed

Indicates that no antenna is connected/present

Indicates that furthermore data is pending to be read

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9.22.36 EVENTS INDICATED BY INTERRUPT

Normal events are indicated over IRQ.

These normal events can be either

• always enabled - Host is always notified

• controlled by Host – Host is notified if the respective Event Enable bit is set in the register (EVENT_ENABLE).

Low-level interrupts from the peripheral IPs including the CLIF are completely handled within the firmware and host will be notified only of the events listed in the events section.

The Firmware implements two event registers as RAM registers that can be written /

Read using WRITE_REGISTER / READ_REGISTER commands.

Two registers do exist to handle the events from a host microcontroller: EVENT_ENABLE and EVENT_STATUS:

• EVENT_ENABLE => register, enables/disables specific event notifications

• EVENT_STATUS => content of this register is part of the event message payload

Events are auto-cleared once the event message is read-out by the host.

Events are asynchronous in nature and are notified to the host if they are enabled within event register.

Following is the list of events available to the host as part of event message:

Table 57. IRQ EVENT LIST

BIT EVENT Value/Description

31..12

RFU

CTS_EVENT

IDLE_EVENT

LP_CALIBRATION_EVENT

LPCD_EVENT

AUTOCOLL_EVENT

TIMER0_EVENT

TX_OVERCURRENT_EVENT

RFON_DET_EVENT

RFOFF_DET_EVENT

STANDBY_PREV_EVENT

GENERAL_ERROR_EVENT

BOOT_EVENT

Always enabled

Note that no two events are clubbed except in case of errors. In case of errors during the operation, functional event (e.g. BOOT_EVENT, AUTOCALL_EVENT etc.) and

GENERAL_ERROR_EVENT will be set.

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9.22.37 EVENTS INDICATED ON GPIO

Temperature events are possible to be indicated by a GPIO to speed up the notification to a host.

The EEPROM register ENABLE_GPIO0_ON_OVERTEMP (0054h) allows enabling the indication of a temperature event on GPIO0.

No other event can be routed to a GPIO.

9.23 Register description

The default setting of a bit within a register is indicated by the "*". Value indicates the allowed range for the bits of a symbol.

9.23.1 Register overview

12h

13h

14h

15h

16h

17h

10h

11h

Table 58. Register Overview

Address (HEX) Address (decimal) Name

0h 0 SYSTEM_CONFIG

EVENT_ENABLE

EVENT_STATUS

EMVCO_EMD_CONTROL

FELICA_EMD_CONTROL

RX_STATUS

RX_STATUS_ERROR

CLIF_STATUS

TRANSCEIVE_CONTROL

TX_SYMBOL01_MOD

TX_SYMBOL1_DEF

TX_SYMBOL0_DEF

TX_SYMBOL23_MOD

TX_SYMBOL23_DEF

TX_SYMBOL_CONFIG

TX_FRAME_CONFIG

TX_DATA_MOD

TX_WAIT

TX_CRC_CONFIG

RFU

SS_TX_CONFIG

SS_TX1_RMCFG

SS_TX2_RMCFG

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56-58

65-66

43-44

3Dh

3Eh

3Fh

38-3A

40h

41h-42h

2Fh

30h

31h

32h

2B-2C

2Dh

23-24

Table 58. Register Overview

...continued

Address (HEX) Address (decimal) Name

18h

19h

RFU

SS_TX_TRANS_CFG

1A-1C

26-28

RFU

PUBLIC RESERVED

35-36

RFU

PUBLIC_RESERVED

SIGPRO_RM_PATTERN

PUBLIC RESERVED

RFU

PUBLIC RESERVED

RFU

RX_FRAME_LENGTH

RX_ERROR_CONFIG

RX_CTRL_STATUS

PUBLIC RESERVED

SIGPRO_IIR_CONFIG0

PUBLIC RESERVED

RFU

PUBLIC RESERVED

RFU

DGRM_RSSI

RX_CRC_CONFIG

RX_WAIT

PUBLIC RESERVED

RFU

RXM_CTRL

PUBLIC RESERVED

RFU

PUBLIC RESERVED

SS_TX1_CMCFG

SS_TX2_CMCFG

TIMER0_CONFIG

TIMER0_RELOAD

RFU

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Table 58. Register Overview

...continued

Address (HEX) Address (decimal) Name

44-46

68-70

PUBLIC RESERVED

RFU

47h

48h

EMD_1_CONFIG

EMD_0_CONFIG

73-79

RFU

LPCD_CALIBRATE_CTRL

IQ_CHANNEL_VALS

PAD_CONFIG

CALIBRATE_STATUS

TXLDO_VDDPA_CONFIG

GENERAL_ERROR_STATUS

TXLDO_VOUT_CURR

CLIF_DAC

PMU_ANA_SMPS_CTRL_REG

139

140

141

142

143

134

135

136

137

138

129

130

131

132

133

128

RXM_FREQ

RXM_RSSI

TEMP_SENSOR

TX_NOV_CALIBRATE

SS_TX1_RTRANS0

SS_TX1_RTRANS1

SS_TX1_RTRANS2

SS_TX1_RTRANS3

SS_TX1_RTRANS4

SS_TX1_RTRANS5

SS_TX1_RTRANS6

SS_TX1_RTRANS7

SS_TX1_RTRANS8

SS_TX1_RTRANS9

SS_TX1_RTRANS10

SS_TX1_RTRANS11

SS_TX1_RTRANS12

SS_TX1_RTRANS13

SS_TX1_RTRANS14

SS_TX1_RTRANS15

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9.23.2 SYSTEM_CONFIG (0000h)

Table 59. SYSTEM_CONFIG register (address 0000h) bit description

Bit Symbol Access Value Description

31:9

RFU

TX_NOV_CALIBRATION

RFU r/w r/w r/w

0*,1

0 -

One time calibration when the host writes a 1 into this register, a one time calibration will be performed.

Note:

The calibration is resulting a short RF-on. All the power configurations shall the configured before setting this bit.

6:5 15693_CHANGE_DATARATE r/w 0*,1

RFU

AUTOCOLL STATE A

SOFT RESET

MF CRYPTO ON r/w r/w r/w r/w

0*,1

15693_changedatarate

0 - RFU

1 - Change Data Rate to 53kB/sec

2 - Change Data Rate to 106kB/sec

3 - Change Data Rate to 212kB/sec

By default, the basic data rate of 26kB/sec will be loaded, switching to a different higher data rate requires this config register to be updated.

All relevant related registers will be updated automatically.

0: TypeA Card mode: Autocoll entry with IDLE state of the card

1: TypeA Card mode: Autocoll entry with HALT state of the card

Performs a soft reset of the system, all registers are set to default values

If set to 1 the MIFARE - crypto bit is generated for

MIFARE Classic en-/de-cryption

0 RFU r/w 0*,1 -

9.23.3 EVENT_ENABLE (0001h)

Table 60. EVENT_ENABLE register (address 0001h) bit description

Bit Symbol Access Value

31:8

RFU

CTS_EVENT_ENABLE r 0*,1

IDLE_EVENT_ENABLE

LP_CALIBRATION_EVENT_

ENABLE

LPCD_EVENT_ENABLE

AUTOCOLL_EVENT_ENABLE

TIMER0_EVENT_ENABLE r/w r/w

TEMP_ERROR_EVENT_ENABLE r/w

0*,1

Description

Enable the corresponding event

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Table 60. EVENT_ENABLE register (address 0001h) bit description

...continued

Bit Symbol Access Value Description

RFON_DET_EVENT_ENABLE

RFOFF_DET_EVENT_ENABLE r/w r/w

0*,1

Enable the corresponding event

STANDBY_PREV_EVENT_ENABLE r/w

GENERAL_ERROR_EVENT_

ENABLE

BOOT_EVENT_ENABLE r/w r/w

0*,1

Enable the corresponding event

9.23.4 EVENT_STATUS (0002h)

Table 61. EVENT_STATUS register (address 0002h) bit description

Bit Symbol Access Value

31:12

RFU

CTS_EVENT r 0*,1

IDLE_EVENT

LP_CALIBRATION_EVENT

LPCD_EVENT

AUTOCOLL_EVENT

TIMER0_EVENT

TEMP_ERROR_EVENT

RFON_DET_EVENT

RFOFF_DET_EVENT r/w r/w r/w r/w r/w

0*,1

2 STANDBY_PREV_EVENT

GENERAL_ERROR_EVENT

BOOT_EVENT r/w r/w r/w

0*,1

Description

Indicated the availability of CTS Event

Indicated the availability of IDLE event.

Indicated the availability of LP Calibration event

Indicated the availability of LPCD event.

Indicated the availability of Autocoll event

Indicated the availability of Timer0 event

Indicated the availability of Temp error

Indicated the availability of RF ON detected.

Indicated the availability of Standby Prevention reason.

Indicated the availability of General Error event.

Indicated the availability of Boot event.

9.23.5 EMVCO_EMD_CONTROL (0003h)

To activate the EMVCo EMD handling of the PN5190B1, the following bits of the register need to be set as follows:

0001b: EMVCO_EMD_ENABLE

1b: EMD_TRANSMISSION_ERROR_ABOVE_NOISE_THRESHOLD_IS_NO_EMD

0001b: EMD_NOISE_BYTES_THRESHOLD

Table 62. EMVCO_EMD_CONTROL register (address 0003h) bit description

Bit Symbol Access Value Description

31:12 RFU rw 0*,1 -

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Table 62. EMVCO_EMD_CONTROL register (address 0003h) bit description

...continued

Bit Symbol Access Value Description

11:10 EMD_RM_EMD_SENSITIVITY rw 0*,1

9:8 rw 0*,1

RM EMD SENSITIVITY value that will be applied to SIGPRO_RM_CONFIG,

At layer 4, when EMD is enabled, the value of EMD_RM_SENSITIVITY can be lowered to ensure robust EMD suppression, if during the layer 3 activation, the value of EMD_RM_

SENSITIVITY in the protocol area is set to a high value to ensure collision detection and resolution when multiple typeA cards are presented at close distance to the antenna.

Timer used for RF communication.

EMD_TRANSMISSION_TIMER_

USED

EMD_MISSING_CRC_IS_

PROTOCOL_ERROR_TYPE_B

EMD_MISSING_CRC_IS_

PROTOCOL_ERROR_TYPE_A rw rw

0*,1

Missing CRC treated as protocol error in » case of

Type B based communication P » case of Type B based communication

Missing CRC treated as protocol error in » case of

Type A based communication P » case of Type A based communication

5:2 EMD_NOISE_BYTES_THRESHOLD rw 0*,1

EMD_TRANSMISSION_ERROR_

ABOVE_NOISE_THRESHOLD_IS_

NO_EMD

EMVCO_EMD_ENABLE rw rw

0*,1

Defines the threshold under which transmission errors are treated as noise.

Note: CRC bytes are NOT included/counted!

Transmission errors with received byte length >=

EMD_NOISE_BYTES_THRESHOLD is never treated as EMD (can be used for versions below

EMVCo3.0)

EMD handling enabled

If this register is enabled by setting EMVCO_

EMD_ENABLE=1, the registers EMD_0_CONFIG and EMD_1_CONFIG is ignored for the EMVCO_

EMD function.

9.23.6 FELICA_EMD_CONTROL (0004h)

Table 63. FELICA_EMD_CONTROL register (address 0004h) bit description

Bit Symbol Access setting for

FeliCa

EMD

Value handling

Description

31:24 FELICA_EMD_RC_BYTE_

VALUE rw 0 0*,1 FeliCa RC byte value that needs to be received does not treat the frame as EMD

23:16 rw 0 0*,1

15:8

7:5

FELICA_EMD_LENGTH_BYTE_

MAX

FELICA_EMD_LENGTH_BYTE_

MIN

RESERVED rw rw

0*,1

0*,1 -

Maximum Length byte value that needs to be received does not treat the frame as EMD

Minimum Length byte value that needs to be received does not treat the frame as EMD

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Table 63. FELICA_EMD_CONTROL register (address 0004h) bit description

...continued

Bit Symbol Access setting for

FeliCa

EMD

Value handling

Description

4 rw 1 0*,1

FELICA_EMD_INTEGRITY_

ERR_CHECK_ENABLE

FELICA_EMD_PROTOCOL_

ERR_CHECK_ENABLE rw 1 0*,1

FeliCa EMD handling enabled when integrity error is set

FeliCa EMD handling enabled when protocol error is set

FELICA_EMD_RC_CHECK_

ENABLE

FELICA_EMD_LEN_CHECK_

ENABLE

FELICA_EMD_ENABLE rw rw rw

0*,1

FeliCa RC byte check enabled for FeliCa EMD handling

FeliCa Length byte check enabled for FeliCa

EMD handling

FeliCa EMD handling enabled

Recommended value for FeliCa EMD handling: 00FF0019h

9.23.7 RX_STATUS (0005h)

Table 64. RX_STATUS register (address 0005h) bit description

Bit Symbol Access Value

31:27

26:20

RFU

RX_COLL_POS r r

0*,1

19:17

16:13

12:0

RX_NUM_LAST_BITS

RX_NUM_FRAMES_RECEIVED r

RX_NUM_BYTES_RECEIVED r r 0*,1

0*,1

Description

Status indicating the bit position of the first collision detected in the data bit. The value is valid only when

RX_COLLISION_DETECTED==1. The value of the

RX_BIT_ALIGN is also taken into account (RX_

COLL_POS = physical bit position in the flow + RX_

BIT_ALIGN value).

Indicates the collision position in the first 8 bytes only. Can be used during the TypeA/ICODE/EPC anti-collision procedure.0x00 - first bit 0x01 - second bit...0x7F - 128th bit.

The status register is not updated by the collision detected on stop or parity bit.

Indicating the number of valid bits in the last byte received.

0: all bits are valid

1: 1 bit is valid

….

7: - 7 bits are valid

This is generally used during ISO/IEC14443 type A anti-collision

Indicates the number of frames received. The value is updated after every normal frame reception in RX_

MULTIPLE mode.

The value is valid only if the bit RX_MULTIPLE_

ENABLE==’1’.

Number of bytes received on the RF interface

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9.23.8 RX_STATUS_ERROR (0006h)

Table 65. RX_STATUS_ERROR register (address 0006h) bit description

Bit Symbol Access Value Description

31:30

RFU

EMD_DETECTED_IN_RXDEC r r/w

0*,1

EMD_DETECTED_IN_SIGPRO

EXT_RFOFF_DETECTED r/w r/w

0*,1

The high level indicates that the EMD was detected

(in the SigPro or in the RxDecoder or in both) during the reception.

The high level indicates that the EMD was detected on the Physical layer (in the SigPro) during the reception.

The high level indicates that the received frame length violated the configured minimum limit.

26 RX_FRAME_MAXLEN_VIOL r/w 0*,1

RX_FRAME_MINLEN_VIOL

RX_FRAME_LE_CRC

RX_NOT_FULL_BYTE r/w r/w r/w

0*,1

The high level indicates that the received frame length is less or equal to the expected CRC field length.

The high level indicates that the last received character in the frame has less than 8 bits.

The high level indicates that the last received character in the frame has 8 data bits but the expected parity bit is absent.

The high level indicates that the last received character in the frame has 8 data bits but the expected stop bit is absent.

RX_MISSING_PARBIT_

DETECTED

RX_MISSING_STOPBIT_

DETECTED

RX_COLLISION_PARBIT_

DETECTED

RX_COLLISION_STOPBIT_

DETECTED

RX_COLLISION_DETECTED

RX_STOP_ON_RXOVER

RX_STOP_ON_RFOFF

RX_STOP_ON_ERR r/w r/w r/w r/w r/w r/w r/w r/w

0*,1

The high level indicates that the collision was detected on the parity bit position.

The high level indicates that the collision was detected on the stop bit position.

The high level indicates that the collision was detected during the frame reception.

The high level indicates that the frame reception was stopped by SGP_MSG_RXOVER_* message reception.

The high level indicates that the collision was detected during the frame reception.

The high level indicates that the frame reception was stopped by SGP_MSG_RXOVER_* message reception.

The high level indicates that the frame reception was interrupted by external RF-field vanishing event.

The high level indicates that the frame reception was stopped by detected communication error event.

14 RX_STOP_ON_LEN r/w 0*,1 The high level indicates that the frame reception was normally stopped by byte counter expiration event. Relates to the protocols where the LEN field is used in the frame format (FeliCa RM/CM, FWEC

RM/CM).

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Table 65. RX_STATUS_ERROR register (address 0006h) bit description

...continued

Bit Symbol Access Value Description

13 RX_STOP_ON_INVPAR r/w 0*,1 The high level indicates that the frame reception was normally stopped by the inverted parity detection event. Relates to the TypeA RM 212-848 kbit/s modes. 12 RX_STOP_ON_PATTERN R 0h

The high level indicates that the frame reception was normally stopped by EOF pattern detection event. Relates to the TypeB RM/CM, B prime RM/

CM modes.

RX_STOP_ON_PATTERN

RX_STOP_ON_ANTICOLL

RX_CRC_ERROR r/w r/w r/w

0*,1

The high level indicates that the frame reception was normally stopped by EOF pattern detection event. Relates to the TypeB RM/CM, B prime RM/

CM modes.

The high level indicates that the frame reception was normally stopped by collision detected on data bit position. Relates to the bit-oriented frame reception in TypeA RM 106 kbit/s mode during the anti-collision procedure.

The high level indicates that the CRC error is detected in the received frame.

9 RX_LEN_ERROR r/w 0*,1

RX_SIGPRO_ERROR

RX_PARITY_ERROR

RX_STOPBIT_ERROR r/w r/w r/w

0*,1

The high level is set if the received frame is shorter than the length stated in the received frame LEN field OR if the LEN parameter in the received frame violates the configured [RX_FRAME_MINLEN:RX_

FRAME_MAX LEN] limits. Can assert only in the mode where the LEN field is used in the frame format (FeliCa RM/CM, FWEC RM/CM).

The high level indicates that the communication error/errors were detected during the frame reception on physical layer(in the SigPro).

The high level indicates that the parity error was detected during the frame reception.

The high level indicates that the stop bit error (‘0’ level instead of ‘1’ on the stop bit position) was detected during the frame reception.

RX_WRITE_ERROR

RX_BUFFER_OVFL_ERROR

RX_LATENCY_ERROR

RX_DATA_INTEGRITY_ERROR r/w r/w r/w r/w

0*,1

The high level indicates that the error acknowledge status was received on the CLIF-system interface during the received frame transmission to the

System RAM.

The high level indicates that the data payload length in the received frame exceeds the 28 bytes limit.

Relates to the PollReq procedure in the FeliCa RM mode only.

The high level indicates that the write request flow was corrupted due to traffic congestion on the system interface during the received frame transmission to the System RAM.

The high level indicates that the data integrity corruption (parity/CRC/etc error) was detected in the received frame.

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Table 65. RX_STATUS_ERROR register (address 0006h) bit description

...continued

Bit Symbol Access Value Description

1 RX_PROTOCOL_ERROR r/w 0*,1 The high level indicates that the protocol requirements violation (stop bit error, missing parity bit, not full byte received, etc) was detected in the received frame.

0 RX_CL_ERROR r/w 0*,1 The high level indicates that some protocol/data integrity erorr/errors were detected during the frame reception

9.23.9 CLIF_STATUS (0007h)

Table 66. CLIF_STATUS register (address 0007h) bit description

Bit Symbol Access Value

31:30 RFU r 0*,1

29 CRC_OK r 0*,1

22:12

RX_SC_DETECTED

RX_SOF_DETECTED

TX_RF_STATUS

RF_DET_STATUS

ADC_Q_CLIPPING

ADC_I_CLIPPING

RFU

TX_NO_DATA_ERROR r r r r r r r r

0*,1

Description

This bit indicates the status of the actual CRC calculation. If 1 the CRC is correct. meaning the

CRC register has the value 0 or the residue value if inverted CRC is used. Note: This flag should only be evaluated at the end of a communication

Status signal indicating that a subcarrier is detected.

Status signal indicating that a SOF has been detected.

If set to 1 this bit indicates that the drivers are turned on. meaning an RF-Field is created by the device itself.

If set to 1 this bit indicates that an external RF-Field is detected by the RF level detectors (after digital filtering)

Indicates that the Q-Channel ADC has clipped

(value 0 or 63), This bit is reset with Rx-reset

(enabling of receiver).

Indicates that the I-Channel ADC has clipped (value

0 or 63), This bit is reset with Rx-reset (enabling of receiver).

This error flag is set to 1. in case a transmission is started but no data is available (register

NumBytesToSend == 0).

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Table 66. CLIF_STATUS register (address 0007h) bit description

...continued

Bit Symbol Access Value Description

10:8 RF_ACTIVE_ERROR_CAUSE r 0*,1 This status flag indicates the cause of an NFC-

Active error.

Note: These bits are only valid when the RF_

ACTIVE_ERROR_IRQ is raised and will be cleared as soon as the bit TX_RF_ENABLE is set to 1. 0*

No Error. reset value 1 External field was detected on within TIDT timing 2 External field was detected on within TADT timing 3 No external field was detected within TADT timings 4 Peer did switch off

RF Field without but no RX event was raised (no data received) 5 - 7 Reserved.

7:6

RFU

RX_ENABLE r r 0*,1

0*,1

TX_ACTIVE

RX_ACTIVE r r 0*,1

0*,1

This bit indicates if the RxDecoder is enabled. If 1 the RxDecoder was enabled and is now ready for data reception

This bit indicates activity of the TxEncoder. If 1 a transmission is ongoing otherwise the TxEncoder is in idle state.

This bit indicates activity of the RxDecoder. If 1 a data reception is ongoing. otherwise the RxDecoder is in idle state.

2:0 RF_EXCHANGE_STATE r 0*,1 These registers hold the command bits

0* IDLE state

1 WaitTransmit state

2 Transmitting state

3 WaitReceive state

4 WaitForData state

5 Receiving state

6 LoopBack state

7 reserved

9.23.10 RF_EXCHANGE_CONTROL (0008h)

To meet the ISO14443A FDT with an accuracy of 1 carrier clock cycle, there is support implemented to synchronize the guard time pre-scaler to the modified Miller envelope pulses (end of pulse). For adjustment, there is a 7-bit wide configuration register -

TX_BITPHASE - which is allows to adjust the FDT in the range of 0 to 128 carrier clock cycles. As defined in the ISO14443 the adjustment is different, depending on the data bit value of the data stream. For correct bit grid calculation, the pre-scaler must be set to a value corresponding exactly to one etu - for 106 kbit/s this corresponds to 0x7F.

Otherwise the FdT will be incorrect.

Table 67. RF_EXCHANGE_CONTROL register (address 0008h) bit description

Bit Symbol Access Value Description

31:16

15:8

RFU

TX_BITPHASE r r/w

0*,1

Defines the number of 13.56 MHz cycles used for adjustment of TX_WAIT to meet the FDT. This is applicable for CardMode only.

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Table 67. RF_EXCHANGE_CONTROL register (address 0008h) bit description

...continued

Bit Symbol Access Value Description

7:3

1:0

RFU

RX_MULTIPLE_ENABLE

RFU r/w r/w r/w

0*,1

0*,1 -

If this bit is set to 1. the receiver is reactivated after the end of a reception.

9.23.11 TX_SYMBOL01_MOD (0009h)

Table 68. TX_SYMBOL01_MOD register (address 0009h) bit description

Bit Symbol Access Value Description

31:24 RFU rw 0*,1 -

23:16 TX_S01_MODWIDTH rw 0*,1

15:9

7:5

RFU

TX_S01_MILLER_ENABLE

TX_S01_INV_ENV

TX_S01_ENV_TYPE rw rw rw rw

0*,1

Specifies the length of a pulse for sending data of symbol 0/1. The length is given by the number of carrier clocks + 1.

If set to 1. pulse modulation is applied according to modified miller coding.

If set to 1. the output envelope is inverted.

Specifies the type of envelope used for transmission of data packets. The selected envelope type is applied to the pseudo bit stream. 000b Direct output

001b Manchester code 010b Manchester code with subcarrier 011b BPSK 100b RZ (pulse of half bit length at beginning of second half of bit) 101b RZ

(pulse of half bit length at beginning of bit) 110b

Manchester tupple 111b RFU.

2:0

TX_S01_SC_FREQ

TX_S01_BIT_FREQ rw rw

0*,1

Specifies the frequency of the subcarrier. 0 424 kHz 1

848 kHz

Specifies the frequency of the bit-stream.

000b -> 1.695 MHz.

001b -> Reserved.

010b -> 26 kHz.

011b -> 53 kHz.

100b -> 106 kHz.

101b -> 212 kHz.

110b -> 424 kHz.

111b -> 848 kHz.

9.23.12 TX_SYMBOL1_DEF (000Ah)

Table 69. TX_SYMBOL1_DEF register (address 000Ah) bit description

Bit Symbol Access Value Description

31:0 TX_SYMBOL1_DEF RW 0*,1 Pattern definition for Symbol1

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9.23.13 TX_SYMBOL0_DEF (000Bh)

Table 70. TX_SYMBOL0_DEF register (address 000Bh) bit description

Bit Symbol Access Value Description

31:0 TX_SYMBOL0_DEF RW 0*,1 Pattern definition for Symbol0

9.23.14 TX_SYMBOL23_MOD (000Ch)

Table 71. TX_SYMBOL23_MOD register (address 000Ch) bit description

Bit Symbol Access Value Description

31:24

23:16

15:9

RFU

TX_S23_MODWIDTH

RFU r r/w r/w

0*,1

0*,1 -

Specifies the length of a pulse for sending data of symbol 2/3. The length is given by the number of carrier clocks + 1.

8 TX_S23_MILLER_ENABLE r/w 0*,1

6:4

2:0

TX_S23_INV_ENV

TX_S23_ENV_TYPE

TX_S23_SC_FREQ

TX_S23_BIT_FREQ r/w r/w r/w r/w

0*,1

If set to 1 pulse modulation is applied according to modified miller coding

If set to 1 the output envelope is inverted.

Specifies the type of envelope used for transmission of data packets. The selected envelope type is applied to the pseudo bit stream. 000b Direct output

001b Manchester code 010b Manchester code with subcarrier 011b BPSK 100b RZ (pulse of half bit length at beginning of second half of bit) 101b RZ

(pulse of half bit length at beginning of bit) 110b

Manchester tupple 111b RFU

Specifies the frequency of the subcarrier. 0 424 kHz 1

848 kHz

Specifies the frequency of the bit-stream. 000b ->

1.695 MHz. 001b -> Reserved. 010b -> 26 kHz. 011b

-> 53 kHz. 100b -> 106 kHz. 101b -> 212 kHz. 110b -

> 424 kHz. 111b -> 848 kHz.

9.23.15 TX_SYMBOL23_DEF (000Dh)

Table 72. TX_SYMBOL23_DEF register (address 000Dh) bit description

Bit Symbol Access Value Description

31:24

23:16

RFU

TX_SYMBOL3_DEF r r/w

0*,1

Pattern definition for Symbol3

15:8

7:0

RFU

TX_SYMBOL2_DEF r/w r/w

0*,1

00000h* -

FFFFFh

Pattern definition for Symbol2

9.23.16 TX_SYMBOL_CONFIG (000Eh)

Table 73. TX_SYMBOL_CONFIG register (address 000Eh) bit description

Bit Symbol Access Value Description

31 RFU 0*,1 -

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Table 73. TX_SYMBOL_CONFIG register (address 000Eh) bit description

...continued

Bit Symbol Access Value Description

30:27

TX_SYMBOL1_BURST_LEN

TX_SYMBOL1_BURST_TYPE r/w r/w

00000h* -

FFFFFh

0*,1

Specifies the number of bits issued for symbol 1 burst. The 3 bits encode a range from 8 to 256 bit length: 0000b 8 bit 0001b 12 bit 0010b 16 bit 0011b

24 bit 0100b 32 bit 0101b 40 bit 0110b 48 bit 0111b

64 bit 1000b 80 bit 1001b 96 bit 1010b 112 bit 1011b

128 bit 1100b 160 bit 1101b 192 bit 1110b 224 bit

1111b 256 bit

Specifies the type of the burst of Symbol1 (logical zero / logical one)

22:19

15:13

12:10

9:5

4:0

TX_SYMBOL1_BURST_ONLY

TX_SYMBOL1_BURST_

ENABLE

RFU

TX_SYMBOL0_BURST_LEN

TX_SYMBOL0_BURST_TYPE

TX_SYMBOL0_BURST_ONLY

TX_SYMBOL0_BURST_

ENABLE

TX_SYMBOL3_LEN

TX_SYMBOL2_LEN

TX_SYMBOL1_LEN

TX_SYMBOL0_LEN r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w

0*,1

If set to 1. Symbol1 consists only of a burst and no symbol pattern

If set to 1. the burst of Symbol0 of the length defined in bit field SYMBOL1_BURST_LEN is enabled

Specifies the number of bits issued for symbol 0 burst. The 3 bits encode a range from 8 to 256 bit length: 0000b 8 bit 0001b 12 bit 0010b 16 bit 0011b

24 bit 0100b 32 bit 0101b 40 bit 0110b 48 bit 0111b

64 bit 1000b 80 bit 1001b 96 bit 1010b 112 bit 1011b

128 bit 1100b 160 bit 1101b 192 bit 1110b 224 bit

1111b 256 bit

Specifies the type of the burst of Symbol0 (logical zero / logical one)

If set to 1. Symbol0 consists only of a burst and no symbol pattern

If set to 1. the burst of Symbol0 of the length defined in bit field SYMBOL0_BURST_LEN is enabled

Specifies the number of valid bits of the symbol definition of Symbol3. The range is from 1 bit (value

0000) to 8 bit (value 111)

Specifies the number of valid bits of the symbol definition of Symbol2. The range is from 1 bit (value

0000) to 8 bit (value 111)

Specifies the number of valid bits of the symbol definition of Symbol1. The range is from 1 bit (value

0000) to 31 bits (value 11110)

Specifies the number of valid bits of the symbol definition of Symbol0. The range is from 1 bit (value

0000) to 31 bits (value 11110)

9.23.17 TX_FRAME_CONFIG (000Fh)

Table 74. TX_FRAME_CONFIG register (address 000Fh) bit description

Bit Symbol Access Value Description

31:19 RFU r 0*,1 -

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Table 74. TX_FRAME_CONFIG register (address 000Fh) bit description

...continued

Bit Symbol Access Value Description

18:16 TX_DATA_CODE_TYPE r/w 0*,1

15:13 TX_STOPBIT_TYPE r/w 0*,1

Specifies the type of encoding of data to be used

000b No special code 001b 1 out of 4 code [ICODE

SLI] 010b 1 out of 256 code [ICODE SLI] 011b Pulse interval encoding (PIE) [ICODE EPC-V2] 100b 2bit tupple code (intended only for test purpose) 101-111b

Reserved

Enables the stop bit (logic 1) and extra guard time

(logic 1). The value 0 disables transmission of stopbits. 000b no stop-bit. no EGT 001b stop-bit. no EGT

010b stop-bit + 1 EGT 011b stop-bit + 2 EGT 100b stop-bit + 3 EGT 101b stop-bit + 4 EGT 110b stop-bit

+ 5 EGT 111b stop-bit + 6 EGT

TX_STARTBIT_ENABLE

TX_MSB_FIRST

TX_PARITY_LAST_INV_

ENABLE

TX_PARITY_TYPE r/w r/w r/w r/w

0*,1

If set to 1. a start-bit (logic 0) will be sent

If set to 1. data bytes are interpreted MSB first for data transmission

If set to 1. the parity bit of last sent data byte is inverted

Defines the type of the parity bit 0 Even Parity is calculated 1 Odd parity is calculated

8 TX_PARITY_ENABLE r/w 0*,1

7:5

3:2

1:0

RFU

TX_DATA_ENABLE

TX_STOP_SYMBOL

TX_START_SYMBOL r r/w r/w r/w

0*,1

If set to 1. a parity bit is calculated and appended to each byte transmitted. If the Transmission Of Data

Is Enabled and TX_NUM_BYTES_2_SEND is zero.

then a NO_DATA_ERROR occurs.

If set to 1. transmission of data is enabled otherwise only symbols are transmitted.

Defines which pattern symbol is sent as frame stopsymbol 00b No symbol is sent 01b Symbol1 is sent

10b Symbol2 is sent 11b Symbol3 is sent

Defines which symbol pattern is sent as frame startsymbol 00b No symbol pattern is sent 01b Symbol0 is sent 10b Symbol1 is sent 11b Symbol2 is sent

9.23.18 TX_DATA_MOD (0010h)

Table 75. TX_DATA_MOD register (address 0010h) bit description

Bit Symbol Access Value Description

31:25 RFU r 0*,1 -

23:16

TX_ICODE_DATA_MODWIDTH_

ENABLE

TX_DATA_MODWIDTH r/w r/w

0*,1

Enables modulation width of icode data. Width of modulation is defined by the TX_DATA_MODWIDTH field. When 1, we should have TX_DATA_ENV_

TYPE=0 and TX_DATA_INV_ENV=0

Specifies the length of a pulse for sending data with miller pulse modulation enabled. The length is given by the number of carrier clocks + 1.

15:9 RFU r 0*,1 -

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Table 75. TX_DATA_MOD register (address 0010h) bit description

...continued

Bit Symbol Access Value Description

6:4

TX_DATA_MILLER_ENABLE

TX_DATA_INV_ENV

TX_DATA_ENV_TYPE r/w r/w r/w

0*,1

If set to 1 pulse modulation is applied according to modified miller coding

If set to 1 the output envelope is inverted

Specifies the type of envelope used for transmission of data packets. The selected envelope type is applied to the pseudo bit stream. 000b Direct output

001b Manchester code 010b Manchester code with subcarrier 011b BPSK 100b RZ (pulse of half bit length at beginning of second half of bit) 101b RZ

(pulse of half bit length at beginning of bit) 110b

Manchester tupple coding 111b RFU

2:0

TX_DATA_SC_FREQ

TX_DATA_BIT_FREQ r/w r/w

0*,1

Specifies the frequency of the subcarrier. 0 424 kHz 1

848 kHz

Specifies the frequency of the bit-stream. 000b ->

1.695 MHz. 001b -> Reserved. 010b -> 26 kHz. 011b

-> 53 kHz. 100b -> 106 kHz. 101b -> 212 kHz. 110b -

> 424 kHz. 111b -> 848 kHz.

9.23.19 TX_WAIT (0011h)

To guarantee correct protocol timing a guard period timer is implemented for the

RF_EXCHANGE command in reception and transmission mode.

These guard times are not available for Transmit or Receive command.

The guard time TX_WAIT is started after the end of a reception no matter if the frame is correct or erroneous.

It is not started in case the reception is restarted because of an EMD-event or in case the

RX_MULTIPLE_ENABLE bit is set to 1 the TX_WAIT.

In case the register flag TX_WAIT_RFON_ENABLE is set to 1 the guard time timer is started when the devices own RF-Field was switched on.

It is possible to disable the guard time tx_wait by setting the register TX_WAIT_VALUE to

00h.

TX_WAIT can be used for 2 different purposes:

1. It can be used to prevent start of transmission before a certain period has expired even if FW already finished data processing and set the START_SEND bit. This behavior is mainly intended for reader mode to guaranteed PICC to PCD frame delay time (FDT).

2. TX_WAIT time can be used to start the transmission at an exactly defined time.

Table 76. TX_CLIF_WAIT register (address 0011h) bit description

Bit Symbol Access Value Description

31:28

27:8

RFU

TX_WAIT_VALUE r r/w

0*,1

Defines the tx_wait timer reload value. Note: If set to 00000h the tx_wait timer guard time is disabled

Note: This bit is set by HW a protocol is detected in automatic mode detection

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Table 76. TX_CLIF_WAIT register (address 0011h) bit description

...continued

Bit Symbol Access Value Description

0 TX_WAIT_PRESCALER r/w 0*,1 Defines the prescaler reload value for the tx_wait timer. Note: This bit is set by HW a protocol is detected in automatic mode detection

9.23.20 TX_CRC_CONFIG (0012h)

Table 77. TX_CRC_CONFIG (address 0012h) bit description

Bit

31:16

Symbol

TX_CRC_PRESET_VALUE

Access r/w

Value Description

0*-FFFFh Arbitrary preset value for the TX-Encoder CRC calculation.

15:7

5:3

RFU

TX_CRC_BYTE2_ENABLE

TX_CRC_PRESET_SEL r/w r/w r/w

0*,1

Reserved

If set; the CRC is calculated from the second byte onwards (intended for HID). This option is used in the

TX-Encoder.

000-101b Preset values of the CRC register for the TX-Encoder.

For a CRC calculation using 5 bits, only the LSByte is used.

000b*

001b

010b

0000h, reset value

6363h

A671h

TX_CRC_TYPE

TX_CRC_INV

TX_CRC_ENABLE r/w r/w r/w

011b

100b

101b

110b

111b

0*,1

0*, 1

FFFFh

0012h

E012h

RFU

Use arbitrary preset value TX_CRC_PRESET_

VALUE

Controls the type of CRC calculation for the TX-

Encoder

16-bit CRC calculation, reset value

5-bit CRC calculation

Controls the sending of an inverted CRC value by the

TX-Encoder

Not inverted CRC checksum, reset value

Inverted CRC checksum

If set to one, the TX-Encoder computes and transmits a CRC.

9.23.21 SS_TX_CONFIG (00015h)

Table 78. SS_TX_CONFIG register (address 0015h) bit description

Bit Symbol Access Value Description

31:14 RFU r 0*,1 -

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Table 78. SS_TX_CONFIG register (address 0015h) bit description

...continued

Bit Symbol Access Value Description

13 TX2_USE_TX1_CONF r/w 0*,1

12:6 RFU r/w 0*,1 -

When 1, the tx1 configuration is used also for tx2: all

SS_TX2_* registers are discarded and configurations from corresponding SS_TX1_* register is used.

5:3

2:0

TX2_CLK_MODE_DEFAULT

TX1_CLK_MODE_DEFAULT r/w r/w

0*,1

TX2 clk mode without field (RM and CM)

TX1 clk mode without field (RM and CM)

9.23.22 SS_TX1_RMCFG (00016h)

Table 79. SS_TX1_RMCFG register (address 0016h) bit description

Bit Symbol Access Value Description

31:25

24:22

21:19

RFU

TX1_CLK_MODE_TRANS_RM

TX1_CLK_MODE_MOD_RM r r/w r/w

0*,1

TX1 clock mode in RM during transition

18:16 TX1_CLK_MODE_CW_RM r/w 0*,1

TX1 clock mode of modulated wave in RM

000: TX1=High-Z

001: TX1=VSS_PA

010 - 110: RFU

111: TX1 clocked normal operation

TX1 clock mode of modulated wave in RM

000: TX1=High-Z

001: TX1=VSS_PA

010 - 110: RFU

111: TX1 clocked normal operation

15:8

7:0

TX1_AMP_MOD_RM

TX1_AMP_CW_RM r/w r/w

0*,1

TX1 amplitude of modulated wave in RM ( 0x00 = 0% modulaton, 0xFF: 100% modulation)

TX1 amplitude of unmodulated wave in RM ( 0x00 =

0% signal, 0xFF: 100% signal)

9.23.23 SS_TX2_RMCFG (00017h)

These settings for TX_2 are only applied, if the bit 13 in TX_CONFIG

(TX2_USE_TX1_CONF is set to 0.

Table 80. SS_TX2_RMCFG register (address 0017h) bit description

Bit Symbol Access Value Description

31:25 RFU r 0*,1 -

24:22

21:19

TX2_CLK_MODE_TRANS_RM

TX2_CLK_MODE_MOD_RM r/w r/w

0*,1

TX2 clock mode in RM during transition

TX2 clock mode of modulated wave in RM

000: TX2=High-Z

001: TX2=VSS_PA

010 - 110: RFU

111: TX2 clocked normal operation

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Table 80. SS_TX2_RMCFG register (address 0017h) bit description

...continued

Bit Symbol Access Value Description

18:16 TX2_CLK_MODE_CW_RM r/w 0*,1 TX2 clock mode of modulated wave in RM

000: TX2=High-Z

001: TX2=VSS_PA

010 - 110: RFU

111: TX2 clocked normal operation

15:8

7:0

TX2_AMP_MOD_RM

TX2_AMP_CW_RM r/w r/w

0*,1

TX2 amplitude of modulated wave in RM ( 0x00 = 0% modulaton, 0xFF: 100% modulation)

TX2 amplitude of unmodulated wave in RM ( 0x00 =

0% signal, 0xFF: 100% signal)

9.23.24 SS_TX_TRANS_CFG (00019h)

Table 81. SS_TX_TRANS_CFG register (address 0019h) bit description

Bit Symbol Access Value Description

31:12 RFU -

11 TX2_SS_TRANS_RATE

10 TX1_SS_TRANS_RATE

TX2 shaping edge rate: 0: 1/fc, 1: 2/fc. 1/fc should be selected for CM.

TX1 shaping edge rate: 0: 1/fc, 1: 2/fc. 1/fc should be selected for CM

9:5 TX2_SS_TRANS_LENGTH TX2 shaping edge length: from 0 (disable) to 16. for

CM, only 0 or 4 values are valid

4:0 TX1_SS_TRANS_LENGTH TX1 shaping edge length: from 0 (disable) to 16. for

CM, only 0 or 4 values are valid

9.23.25 SIGPRO_RM_PATTERN (0020h)

Table 82. SIGPRO_RM_PATTERN register (address 0020h) bit description

Bit Symbol Access Value Description

31:16 RM_SYNC_PATTERN r/w 0*,1 Sync pattern for FeliCa. LSB transmitted last

11:0

RM_SYNC_PATTERN_EXT4

RM_SYNC_PATTERN_EXT2

RM_RECEIVE_TILL_END

RFU

RM_SOF_PATTERN r r/w r/w r/w r/w

0*,1

Extend FeliCa sync pattern with 16 leading 0s

Extend FeliCa sync pattern with 8 leading 0s

Do not stop the reception before RxDecoder sends a stop command.

SOF pattern for Type B. LSB transmitted last or Start

Byte pattern for NFC passive.

9.23.26 SIGPRO_RM_TECH (0022h)

Table 83. SIGPRO_RM_TECH register (address 0022h) bit description

Bit Symbol Access Value Description

31:17 RFU rw 0 -

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Table 83. SIGPRO_RM_TECH register (address 0022h) bit description

...continued

Bit Symbol Access Value Description

16:15 RM_MF_GAIN rw 0

14:0 RFU rw 0 -

Defines the gain of the Matched-Filters

00: Minimum Gain,

11: Maximum Gain

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9.23.27 RX_FRAME_LENGTH (0026h)

Table 84. RX_FRAME_LENGTH register (address 0026h) bit description

Bit Symbol Access Value Description

30:16

RFU

RX_FRAME_MAXLEN

RFU r r r/w

0*,1

0*,1 -

Maximal number of received [DATA + CRC] bits in the frame. The violation of the maximum length limit can be also configured as an Error/EMD condition.

If the max length violation is configured as error the frame reception is stopped in case of maximum length limit exceeding. Otherwise the reception is continued.0x0000 - 1 bit...0x7FFF - 32 kbit

14:0 RX_FRAME_MINLEN r/w 0*,1 Minimal number of received [DATA + CRC] bits in the frame. The violation of the minimum length limit can be also configured as an Error/EMD condition. The parameter also defines the number of received[DATA

+ CRC] bits before which any of the EOF patterns or

INVPAR stop condition events are ignored.0x0000 - 1 bit...0x7FFF - 32 kbit

9.23.28 RX_ERROR_CONFIG (0027h)

Table 85. RX_ERROR_CONFIG register (address 0027h) bit description

Bit Symbol Access Value Description

31:0 rw xxx NFC FORUM-compliant error handling yyy EMVCO-compliant error handling zzz compliant error handling

9.23.29 RX_CTRL_STATUS (0028h)

Table 86. RX_CTRL_STATUS register (address 0028h) bit description

Bit Symbol Access Value Description

31:9 RFU r dyn -

8:3 r dyn HF attenuator value

2:0

RXCTRL_HF_

ATT_VAL

RFU r dyn -

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9.23.30 SIGPRO_IIR_CONFIG0 (0002Ah)

Table 87. SIGPRO_IIR_CONFIG0 register (address 002Ah) bit description

Bit Symbol Access Value Description

31:1

RFU

IIR_ENABLE

Enable the IIR filter

28:23

22:17

16:7

6:0

9.23.31 DGRM_RSSI (0030h)

This register is updated dynamically by the firmware if the DPC is enabled.

Table 88. DGRM_RSSI register (address 0030h) bit description

Bit Symbol Access Value

31:30 RFU

29 DGRM_SIGNAL_DETECT_TH_

OVR r/w 0*,1

RFU

DGRM_RSSI_HYST

DGRM_RSSI_TARGET

DGRM_SIGNAL_DETECT_TH_

OVR_VAL r/w r/w r/w r/w

0*,1

Description

Enables the override of signal detect threshold.

Override value is set based on DGRM_SIGNAL_

DETECT_TH_OVR_VAL.

Hysteresis value for RSSI target

RSSI target value

Defines the override value for signal detect threshold when DGRM_SIGNAL_DETECT_TH_OVR is set.

These bits are modified dynamically by the ARC algorithm based on the DPC voltage.

Only if the ARC is disabled, the value written during

LOAD_RF_CONFIGURATION(0x0D) is retained throughout the RF Field session.

9.23.32 RX_CRC_CONFIG (0031h)

Table 89. RX_CRC_CONFIG register (address 0031h) bit description

Bit Symbol Access Value Description

31:16 RX_CRC_PRESET_VALUE r 0*,1

15:8

RFU

RX_FORCE_CRC_WRITE r/w r/w

0*,1

Arbitrary preset value for the Rx-Decoder CRC calculation.

6 RX_CRC_ALLOW_BITS r/w 0*,1

If set. the Rx-Decoder will send to the RAM the CRC bits as well.

If activated the frame with length =< CRC_length will be always sent to the System RAM as is, without

CRC bits removal.

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Table 89. RX_CRC_CONFIG register (address 0031h) bit description

...continued

Bit Symbol Access Value Description

5:3 RX_CRC_PRESET_SEL r/w 0*,1 Preset value of the CRC register for the Rx-Decoder.

For a CRC calculation using 5bits only the LSByte is used.

000b* 0000h reset value. Note that this configuration is set by the Mode detector for FeliCa.

001b 6363h Note that this configuration is set by the

Mode detector for ISO14443 type A.

010b A671h

011b FFFFh Note that this configuration is set by the

Mode detector for ISO14443 type B.

100b

0012h

101b E012h

110b RFU 111b Use arbitrary preset value RX_CRC_

PRESET_VALUE

RX_CRC_TYPE

RX_CRC_INV r/w r/w

0*,1

Controls the type of CRC calculation for the Rx-

Decoder 0* 16bit CRC calc

Controls the comparison of the CRC checksum for the Rx-Decoder

0*: Not inverted CRC value: 0000h reset value.

Note that this bit is cleared by the Mode detector for

ISO14443 type A and FeliCa.

1: Inverted CRC value: F0B8h Note that this bit is set by the Mode detector for ISO14443 type B

0 RX_CRC_ENABLE If set. the Rx-Decoder will check the CRC for correctness.

Note that this bit is set by the Mode Detector when

ISO14443 type B. or FeliCa (212 kBd or 424 kBd) is detected.

7:0

9.23.33 RX_WAIT (0032h)

To guarantee correct protocol timing a guard period timer is implemented for the

RF_EXCHANGE command in reception and transmission mode.

These guard times are not available for Transmit or Receive command.

The guard time RX_WAIT is started after the end of a transmission. The guard time

RX_WAIT can be disabled by setting the register RX_WAIT_VALUE to 00h meaning the receiver is immediately enabled.

Table 90. RX_WAIT register (address 0032h) bit description

Bit Symbol Access Value

31:28

27:8

RFU

RX_WAIT_VALUE r r/w

0*,1

RX_WAIT_PRESCALER r/w 0*,1

Description

Defines the rx_wait timer reload value. Note: If set to

00000h the rx_wait guard time is disabled

Defines the prescaler reload value for the rx_wait timer.

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9.23.34 RXM_CTRL (0035h)

Table 91. RXM_CTRL register (address 0035h) bit description

Bit Symbol Access Value

31:3

RFU

RXM_FRQ_CHECK_PCRM_

ENABLE r/w

1 RXM_FRQ_CHECK_CORDIC_

ENABLE r/w

0 RXM_ENABLE r/w

Description enable frequency check from PCRM enable precise frequency check from cordic phase

(+/- 1.7 MHz multiples) enable the all RxMeasure module

9.23.35 SS_TX1_CMCFG (0003Bh)

Table 92. SS_TX1_CMCFG register (address 003Bh) bit description

Bit Symbol Access Reset

Value

Description

31:22

21:19

RFU

TX1_CLK_MODE_MOD_CM rw rw

TX1 clock mode of modulated wave in CM

18:16

15:8

TX1_CLK_MODE_CW_CM

TX1_AMP_MOD_CM rw rw

TX1 clock mode of unmodulated wave in CM

TX1 clock mode of modulated wave in CM

7:0 TX1_AMP_CW_CM rw 0xFF TX1 clock mode of unmodulated wave in CM

9.23.36 SS_TX2_CMCFG (0003Ch)

Table 93. SS_TX2_CMCFG register (address 003Ch) bit description

Bit Symbol Access Reset

Value

Description

31:22

21:19

RFU

TX2_CLK_MODE_MOD_CM rw rw

TX2 clock mode of modulated wave in CM

18:16

15:8

7:0

TX2_CLK_MODE_CW_CM

TX2_AMP_MOD_CM

TX2_AMP_CW_CM rw rw rw

0xFF

TX2 clock mode of unmodulated wave in CM

TX2 clock mode of modulated wave in CM

TX2 clock mode of unmodulated wave in CM

9.23.37 TIMER0_CONFIG (003Dh)

Table 94. TIMER0_CONFIG register (address 003Dh) bit description

Bit Symbol Access Value Description

31:9 RFU r 0*,1 -

8 T0_START_NOW r/w 0*,1

RFU

T0_ONE_SHOT_MODE r r/w

0*,1

T0_START_EVENT: If set. the timer T0 is started immediately

When set to 1, the counter value does not reload again until the counter value has reached zero

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Table 94. TIMER0_CONFIG register (address 003Dh) bit description

...continued

Bit Symbol Access Value Description

5:3 T0_PRESCALE_SEL r/w 0*,1 Controls input frequency/period of the timer T0 when the prescaler is activated in T0_MODE_SEL.

000b - 6.78 MHz counter

001b - 3.39 MHz counter

010b - 1.70 MHz counter

011b - 848 kHz counter

100b - 424 kHz counter

101b - 212 kHz counter

110b - 106 kHz counter

111b - 53 kHz counter

T0_MODE_SEL

T0_RELOAD_ENABLE r/w r/w

0*,1

Configuration of the timer T0 clock.

0b - Prescaler is disabled: the timer frequency matches CLIF clock frequency (13.56 MHz).

1b - Prescaler is enabled: the timer operates on the prescaler signal frequency (chosen by T0_

PRESCALE_SEL).

If set to

0b - the timer T0 will stop on expiration. 0* After expiration the timer T0 will stop counting. i.e. remain zero. reset value.

1b - After expiration the timer T0 will reload its preset value and continue counting down.

0 T0_ENABLE r/w 0*,1 Enables the timer T0

9.23.38 TIMER0_RELOAD (003Eh)

Table 95. TIMER0_RELOAD register (address 003Eh) bit description

Bit Symbol Access Value Description

31:20

19:0

RFU

T0_RELOAD_VALUE r r/w

0*,1

Reload value of the timer T0.

9.23.39 TIMER1_CONFIG (003Fh)

Timer 1 is typically used for the FDT configuration. Configuration can be done from the host but the associated IRQ is handled by the firmware of the PN5190B1.

Table 96. TIMER1_CONFIG register (address 003Fh) bit description

Bit Symbol Access Value Description

31 RFU r 0*,1 -

30 T1_STOP_ON_RX_STARTED r/w 0*,1

T1_STOP_ON_TX_STARTED

T1_STOP_ON_RF_ON_EXT r/w r/w

0*,1

T1_STOP_EVENT: If set. the timer T1 is stopped when a data reception begins (1st bit is received).

T1_STOP_EVENT: If set. the timer T1 is stopped when a data transmission begins.

T1_STOP_EVENT: If set. the timer T1 is stopped when the external RF field is detected.

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Table 96. TIMER1_CONFIG register (address 003Fh) bit description

...continued

Bit Symbol Access Value Description

27 T1_STOP_ON_RF_OFF_EXT r/w 0*,1

26 T1_STOP_ON_RF_ON_INT r/w 0*,1

T1_STOP_EVENT: If set. the timer T1 is stopped when the external RF field vanishes.

T1_STOP_EVENT: If set. the timer T1 is stopped when the internal RF field is turned on.

23:18

T1_STOP_ON_RF_OFF_INT

T1_STOP_ON_RX_ENDED

RFU

T1_START_ON_RX_STARTED

T1_START_ON_RX_ENDED

T1_START_ON_TX_STARTED

T1_START_ON_TX_ENDED

T1_START_ON_RF_ON_EXT r r/w r/w r/w r/w r/w r/w r/w

0*,1

T1_STOP_EVENT: If set. the timer T1 is stopped when the internal RF field is turned off.

T1_STOP_EVENT: If set the timer T1 is stopped when an activity on RX is detected.

T1_START_EVENT: If set. the timer T1 is started when a data reception begins (1st bit is received).

T1_START_EVENT: If set. the timer T1 is started when a data reception ends.

T1_START_EVENT: If set. the timer T1 is started when a data transmission begins.

T1_START_EVENT: If set. the timer T1 is started when a data transmission ends.

T1_START_EVENT: If set. the timer T1 is started when the external RF field is detected.

12 T1_START_ON_RF_OFF_EXT r/w 0*,1

5:3

T1_START_ON_RF_ON_INT

T1_START_ON_RF_OFF_INT

T1_START_ON_TX_

FRAMESTEP

T1_START_NOW

RFU

T1_ONE_SHOT_MODE

T1_PRESCALE_SEL r r/w r/w r/w r/w r/w r/w

0*,1

T1_START_EVENT: If set. the timer T1 is started when the external RF field is not detected anymore.

T1_START_EVENT: If set. the timer T1 is started when an internal RF field is turned on.

T1_START_EVENT: If set. the timer T1 is started when an internal RF field is turned off.

T1_START_EVENT: If set. the timer T1 is started when an activity on Frame step is detected.

T1_START_EVENT: If set. the timer T1 is started immediately.

When set to 1, the counter value does not reload again until the counter value has reached zero

Controls input frequency/period of the timer T0 when the prescaler is activated in T1_MODE_SEL.

000b - 6.78 MHz counter

001b - 3.39 MHz counter

010b - 1.70 MHz counter

011b - 848 kHz counter

100b - 424 kHz counter

101b - 212 kHz counter

110b - 106 kHz counter

111b - 53 kHz counter

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Table 96. TIMER1_CONFIG register (address 003Fh) bit description

...continued

Bit Symbol Access Value Description

2 T1_MODE_SEL r/w 0*,1 If set. the timer T1 is started the prescaler for the timer T1 is enabled. 0* Prescaler is disabled: the timer frequency matches CLIF clock frequency (13.56

MHz). 1 Prescaler is enabled: the timer operates on the prescaler signal frequency (chosen by T1_

PRESCALE_SEL).

T1_RELOAD_ENABLE

T1_ENABLE r/w r/w

0*,1

If set to 0.the timer T1 will stop on expiration. 0* After expiration the timer T1 will stop counting. i.e. remain zero. reset value. 1 After expiration the timer T1 will reload its preset value and continue counting down.

Enables the timer T1

9.23.40 TIMER1_RELOAD (0040h)

Table 97. TIMER1_RELOAD register (address 0040h) bit description

Bit Symbol Access Value Description

31:20 RFU r 0*,1 -

19:0 T1_RELOAD_VALUE r/w 0*,1 Reload value of the timer T1.

9.23.41 EMD_1_CFG (0047h)

This register allows to configure the ISO14443 and NFC-Forum EMD handling.

This register shall not be modified in case EMVCO or FeliCa EMD is activated.

Table 98. EMD_1_CFG register (address 0047h) bit description

Bit Symbol AccessValue Value for ISO/

IEC14443

EMD handling

31:0 EMD_1_Configuration r/w 0000

FF03h

Value for NFC

Forum

EMD handling

0000

FF04h

Description

0000 FF03h EMD ISO

0000 FF04h EMD NFC Forum

9.23.42 EMD_0_CONFIG (0048h)

This register allows to configure the ISO14443 and NFC-Forum EMD handling.

This register shall not be modified in case EMVCO or FeliCa EMD is activated.

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Table 99. EMD_0_CONFIG register (address 0048h) bit description

Bit Symbol AccessValue Value for ISO/

IEC14443

EMD handling

Value for

NFC

Forum

EMD handling

Description

31:0 EMD_0_Configuration 176003

FFh

1F600

3FFh

Default value for ISO14443 and NFC Forum

9.23.43 LPCD_CALIBRATE_CTRL (00050h)

This register is used for LPCD semi autonomous mode. Writing to this register triggers the LPCD calibration with the RSSI_HYSTERESIS and RSSI_TARGET values as given in bits 23:16 and 15:0. After calibration is completed, calibration status is available in

LPCD_CALIBRATE_STATUS. If the calibration is successful, the I/Q channel values can be read from register IQ_CHANNEL_VALS (51h).

Table 100. LPCD_CALIBRATE_CTRL register (address 0050h) bit description

Bit Symbol Access Value Description

31:24

23:16

RFU

RSSI_HYSTERESIS r r/w

0*,1

Value to be set in DGRM_RSSI_HYST used for calibration

15:0 RSSI_TARGET r/w 0*,1 Value to be set in DGRM_RSSI_TARGET used for calibration

9.23.44 IQ_CHANNEL_VALS (00051h)

Table 101. IQ_CHANNEL_VALS register (address 0051h) bit description

Bit Symbol Access Value Description

31:16 Q_CHANNEL_VAL r Q Channel value

15:0 I_CHANNEL_VAL r I Channel value

9.23.45 PAD_CONFIG (0052h)

Table 102. PAD_CONFIG register (address 0052h) bit description

Bit Symbol Access Value Description

31:7

RFU

AUX3_OUTPUT_VAL

Output value for AUX3

0: Low

1: High

AUX2_OUTPUT_VAL

AUX1_OUTPUT_VAL

Output value for AUX2

0: Low

1: High

Output value for AUX1

0: Low

1: High

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Table 102. PAD_CONFIG register (address 0052h) bit description

...continued

Bit Symbol Access Value Description

3 GPIO3_OUTPUT_VAL RW

2 GPIO2_OUTPUT_VAL RW

Output value for GPIO3

0: Low

1: High

Output value for GPIO2

0: Low

1: High

GPIO1_OUTPUT_VAL

GPIO0_OUTPUT_VAL

Output value for GPIO1

0: Low

1: High

Output value for GPIO0

0: Low

1: High

On PN5190B1 only output functionality is available on GPIO's.

9.23.46 CALIBRATE_STATUS (00053h)

Table 103. CALIBRATE_STATUS register (address 0053h) bit description

Bit Symbol Access Value Description

31 LPCD_CALIBRATION_STATUS r Calibration Status

0 - Calibration Not Done,

1- Calibration Done

30:1

RFU

TXNOV_CALIBRATION_STATUS r -

Calibration Status

0 - Calibration Not Done,

1- Calibration Done

9.23.47 TXLDO_VDDPA_CONFIG (00054h)

If DPC is disabled, the VDDPA supply voltage can be set with this register. These register settings are overruled by the DPC.

This register does allow to read the actual VDDPA supply voltage independent from having the DPC enabled/disabled, this allows to read-out the actual transmitter supply voltage.

Table 104. TXLDO_VDDPA_CONFIG register (address 0054h) bit description

Bit Symbol Access Value Description

31:8 RFU rw -

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Table 104. TXLDO_VDDPA_CONFIG register (address 0054h) bit description

...continued

Bit Symbol Access Value Description

7:0 VDDPA CONFIG rw VDDPALDO output voltage

VDDPA_1V50 /* 0x00 */ VDDPA_1V60, /* 0x01 */

VDDPA_1V70, /* 0x02 */ VDDPA_1V80, /* 0x03 */

VDDPA_1V90, /* 0x04 */ VDDPA_2V00, /* 0x05 */

VDDPA_2V10, /* 0x06 */ VDDPA_2V20, /* 0x07 */

VDDPA_2V30, /* 0x08 */ VDDPA_2V40, /* 0x09 */

VDDPA_2V50, /* 0x0A */ VDDPA_2V60, /* 0x0B */

VDDPA_2V70, /* 0x0C */ VDDPA_2V80, /* 0x0D */

VDDPA_2V90, /* 0x0E */ VDDPA_3V00, /* 0x0F */

VDDPA_3V10, /* 0x10 */ VDDPA_3V20, /* 0x11 */

VDDPA_3V30, /* 0x12 */ VDDPA_3V40, /* 0x13 */

VDDPA_3V50, /* 0x14 */ VDDPA_3V60, /* 0x15 */

VDDPA_3V70, /* 0x16 */ VDDPA_3V80, /* 0x17 */

VDDPA_3V90, /* 0x18 */ VDDPA_4V00, /* 0x19 */

VDDPA_4V10, /* 0x1A */ VDDPA_4V20, /* 0x1B */

VDDPA_4V30, /* 0x1C */ VDDPA_4V40, /* 0x1D */

VDDPA_4V50, /* 0x1E */ VDDPA_4V60, /* 0x1F */

VDDPA_4V70, /* 0x20 */ VDDPA_4V80, /* 0x21 */

VDDPA_4V90, /* 0x22 */ VDDPA_5V00, /* 0x23 */

VDDPA_5V10, /* 0x24 */ VDDPA_5V20, /* 0x25 */

VDDPA_5V30, /* 0x26 */ VDDPA_5V40, /* 0x27 */

VDDPA_5V50, /* 0x28 */ VDDPA_5V60, /* 0x29 */

VDDPA_5V70, /* 0x2A */

9.23.48 GENERAL_ERROR_STATUS (0055h)

Table 105. GENERAL_ERROR_STATUS register (address 0055h) bit description

Bit Symbol Access Value Description

31:3

RFU

TXLDO_ERROR r r

0*,1

TXLDO does not start

CLOCK_ERROR

GPADC_ERROR r r 0*,1

0*,1

XTAL or PLL does not start

GPADC initialization fail

9.23.49 TXLDO_VOUT_CURR (0056h)

Table 106. TXLDO_VOUT_CURR register (address 0056h) bit description

Bit Symbol Access Value Description

31:24 RFU r -

23:8 TXLDO_CURRENT r Indicates the TXLDO Current, measured value is indicated in mA (1 bit = 1 mA)

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Table 106. TXLDO_VOUT_CURR register (address 0056h) bit description

...continued

Bit Symbol Access Value Description

7:0 VDDPA_VOUT r VDDPA output voltage

VDDPA_1V50 /* 0x00 */ VDDPA_1V60, /* 0x01 */

VDDPA_1V70, /* 0x02 */ VDDPA_1V80, /* 0x03 */

VDDPA_1V90, /* 0x04 */ VDDPA_2V00, /* 0x05 */

VDDPA_2V10, /* 0x06 */ VDDPA_2V20, /* 0x07 */

VDDPA_2V30, /* 0x08 */ VDDPA_2V40, /* 0x09 */

VDDPA_2V50, /* 0x0A */ VDDPA_2V60, /* 0x0B */

VDDPA_2V70, /* 0x0C */ VDDPA_2V80, /* 0x0D */

VDDPA_2V90, /* 0x0E */ VDDPA_3V00, /* 0x0F */

VDDPA_3V10, /* 0x10 */ VDDPA_3V20, /* 0x11 */

VDDPA_3V30, /* 0x12 */ VDDPA_3V40, /* 0x13 */

VDDPA_3V50, /* 0x14 */ VDDPA_3V60, /* 0x15 */

VDDPA_3V70, /* 0x16 */ VDDPA_3V80, /* 0x17 */

VDDPA_3V90, /* 0x18 */ VDDPA_4V00, /* 0x19 */

VDDPA_4V10, /* 0x1A */ VDDPA_4V20, /* 0x1B */

VDDPA_4V30, /* 0x1C */ VDDPA_4V40, /* 0x1D */

VDDPA_4V50, /* 0x1E */ VDDPA_4V60, /* 0x1F */

VDDPA_4V70, /* 0x20 */ VDDPA_4V80, /* 0x21 */

VDDPA_4V90, /* 0x22 */ VDDPA_5V00, /* 0x23 */

VDDPA_5V10, /* 0x24 */ VDDPA_5V20, /* 0x25 */

VDDPA_5V30, /* 0x26 */ VDDPA_5V40, /* 0x27 */

VDDPA_5V50, /* 0x28 */ VDDPA_5V60, /* 0x29 */

VDDPA_5V70, /* 0x2A */

9.23.50 CLIF_DAC (00057h)

This register allows to configure the output voltage of VTUNE1, VTUNE2.

Table 107. CLIF_DAC register (address 0057h) bit description

Bit Symbol Access Value

31:28

27:24

RFU

TUNING_DAC_2_RANGE

23:17

15:12

11:8

TUNING_DAC_2_VALUE

TUNING_DAC_2_PD

RFU

TUNING_DAC_1_RANGE

Description

Reference voltage of the DAC, allows to increase the resolution in case a limited output voltage is required.

For max output voltage, 0x000 need to be configured

(3.8 V) x111=2 V x110=3 V x100=3.45 V x000=3.8 V

Output voltage of DAC2 according to 1/128

*<TUNING_DAC_2_VALUE> * <Range in V>

0=DAC Turned off, 1=DAC enabled

Reference voltage of the DAC, allows to increase the resolution in case a limited output voltage is required.

For max output voltage, 0x000 need to be configured

(3.8 V) x111=2 V, x110=3 V x100=3.45 V x000=3.8 V

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Table 107. CLIF_DAC register (address 0057h) bit description

...continued

Bit Symbol Access Value Description

7:1

TUNING_DAC_1_VALUE

TUNING_DAC_1_PD

Output voltage of DAC1 according to 1/128 *

<TUNING_DAC_1_VALUE> * <Range in V>

0=DAC Turned off, 1=DAC enabled

9.23.51 PMU_ANA_SMPS_CTRL_REG (00058h)

Table 108. PMU_ANA_SMPS_CTRL_REG register (address 0058h) bit description

Bit Symbol Access Value Description

31:30 RFU -

29:27 SMPS_MAXDT_SEL SMPS max duty cycle value, valid when SMPS_

MAX_DTC_BYPASS is set

25:24

23:22

21:20

SMPS_MAXDT_SEL_BYPASS

SMPS_GM

SMPS_RSENSE

SMPS_SOFT_START

SMPS max duty cycle lookup table bypass

SMPS Gm setup

SMPS Rsense setup

SMPS Soft Start setup

19:17

16:14

13:12

11:10

9:7

6:1

SMPS_SAWTOOTHGEN

RFU

SMPS_PROT_UNDERSHOOT_

VTH

SMPS_REG_SPARE_0

SMPS_PID

SMPS_VDDBOOST_VOUT_SEL

SMPS_EN

SMPS Sawtooth generator setup

SMPS

SMPS PID filter setup

SMPS Output voltage selection

SMPS enable

9.23.52 RXM_FREQ (00059h)

Table 109. RXM_FREQ register (address 0059h) bit description

Bit Symbol Access Value

31 RXM_FREQ_REG_VALID r -

30:25

24:16

RFU

RXM_FREQ r r

15:9

0:8

RFU

RXM_PHASE r r

Description

CLIF_RXM_FREQ_REG fields are valid

frequence difference between the last two consecutive measures at 1.7 MHz (multiple of

13.56MHz/4096). Signed. 2-Complement coded

phase value

9.23.53 RXM_RSSI (0005Ah)

Table 110. RXM_RSSI register (address 005Ah) bit description

Bit Symbol Access Reset

Value

31 RFU r -

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Table 110. RXM_RSSI register (address 005Ah) bit description

...continued

Bit Symbol Access Reset

Value

Description

22 RXM_RSSI_FROZEN r The RSSI value is not currently updated

RXM_FRQ_OK

RXM_RSSI_REG_VALID r r

The carrier frequency detected is OK.

CLIF_RXM_RSSI_REG fields are valid

19:14

13:0

RXM_HFATT

RXM_RSSI r r

HFAtt latched with RSSI

RSSI value

9.23.54 TEMP_SENSOR (005Bh)

Table 111. TEMP_SENSOR register (address 005Bh) bit description

Bit Symbol Access Value Description

31:16

15-0

TEMP_SENSOR_DATA

0*,1

RFU

Indicates the current temperature of the chip in degree celsius.

This is the actual temperature data of the sensor which is used for the overheat protection.

Maximum temperature readable will be the maximum temperature threshold configured in EEPROM address 0x14.

9.23.55 TX_NOV_CALIBRATE (005Dh)

Table 112. TX_NOV_CALIBRATE register (address 005Dh) bit description

Bit Symbol Access Value Description

31:30 RFU RW 0*,1 -

0 TX_NOV_CALIBRATE_AND_

STORE_VAL

RW Calibrates the TX NOV and stores the resulting value in EEPROM

9.23.56 SS_TX1_RTRTRANS0 (00080h)

Table 113. SS_TX1_RTRTRANS0 register (address 0080h) bit description

Bit Symbol Access Value Description

31:24

23:16

TX1_SS_RTRANS3

TX1_SS_RTRANS2 rw rw

TX1 rising transition value 3

TX1 rising transition value 2

15:8

7:0

TX1_SS_RTRANS1

TX1_SS_RTRANS0 rw rw

TX1 rising transition value 1

TX1 rising transition value 0

9.23.57 SS_TX1_RTRTRANS1 (00081h)

Table 114. SS_TX1_RTRTRANS1 register (address 0081h) bit description

Bit Symbol Access Value Description

31:24 TX1_SS_RTRANS7 rw TX1 rising transition value 7

23:16 TX1_SS_RTRANS6 rw TX1 rising transition value 6

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Table 114. SS_TX1_RTRTRANS1 register (address 0081h) bit description

...continued

Bit Symbol Access Value Description

15:8

7:0

TX1_SS_RTRANS5

TX1_SS_RTRANS4 rw rw

TX1 rising transition value 5

TX1 rising transition value 4

9.23.58 SS_TX1_RTRTRANS2 (00082h)

Table 115. SS_TX1_RTRTRANS2 register (address 0082h) bit description

Bit Symbol Access Value Description

31:24 TX1_SS_RTRANS11 rw TX1 rising transition value 11

23:16

15:8

TX1_SS_RTRANS10

TX1_SS_RTRANS9 rw rw

TX1 rising transition value 10

TX1 rising transition value 9

7:0 TX1_SS_RTRANS8 rw TX1 rising transition value 8

9.23.59 SS_TX1_RTRTRANS3 (00083h)

Table 116. SS_TX1_RTRTRANS0 register (address 0080h) bit description

Bit Symbol Access Value Description

31:24 TX1_SS_RTRANS15 rw TX1 rising transition value 15

23:16

15:8

7:0

TX1_SS_RTRANS14

TX1_SS_RTRANS13

TX1_SS_RTRANS12 rw rw rw

TX1 rising transition value 14

TX1 rising transition value 13

TX1 rising transition value 12

9.23.60 SS_TX2_RTRTRANS0 (00084h)

Table 117. SS_TX2_RTRTRANS0 register (address 00804) bit description

Bit Symbol Access Value Description

31:24 TX2_SS_RTRANS3 rw TX2 rising transition value 3

23:16

15:8

TX2_SS_RTRANS2

TX2_SS_RTRANS1 rw rw

TX2 rising transition value 2

TX2 rising transition value 1

7:0 TX2_SS_RTRANS0 rw TX2 rising transition value 0

9.23.61 SS_TX2_RTRTRANS1 (00085h)

Table 118. SS_TX2_RTRTRANS1 register (address 0085h) bit description

Bit Symbol Access Value Description

31:24

23:16

TX2_SS_RTRANS7

TX2_SS_RTRANS6 rw rw

TX2 rising transition value 7

TX2 rising transition value 6

15:8

7:0

TX2_SS_RTRANS5

TX2_SS_RTRANS4 rw rw

TX2 rising transition value 5

TX2 rising transition value 4

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9.23.62 SS_TX2_RTRTRANS2 (00086h)

Table 119. SS_TX2_RTRTRANS2 register (address 0086h) bit description

Bit Symbol Access Value Description

31:24

23:16

TX2_SS_RTRANS11

TX2_SS_RTRANS10 rw rw

TX2 rising transition value 11

TX2 rising transition value 10

15:8

7:0

TX2_SS_RTRANS9

TX2_SS_RTRANS8 rw rw

TX2 rising transition value 9

TX2 rising transition value 8

9.23.63 SS_TX2_RTRTRANS3 (00087h)

Table 120. SS_TX2_RTRTRANS3 register (address 0087h) bit description

Bit Symbol Access Value Description

31:24 TX2_SS_RTRANS15 rw TX2 rising transition value 15

23:16 TX2_SS_RTRANS14 rw TX2 rising transition value 14

15:8

7:0

TX2_SS_RTRANS13

TX2_SS_RTRANS12 rw rw

TX2 rising transition value 13

TX2 rising transition value 12

9.23.64 SS_TX1_FTRTRANS0 (00088h)

Table 121. SS_TX1_FTRTRANS0 register (address 0088h) bit description

Bit Symbol Access Value Description

31:24

23:16

TX1_SS_FTRANS3

TX1_SS_FTRANS2 rw rw

TX1 falling transition value 3

TX1 falling transition value 2

15:8

7:0

TX1_SS_FTRANS1

TX1_SS_FTRANS0 rw rw

TX1 falling transition value 1

TX1 falling transition value 0

9.23.65 SS_TX1_FTRTRANS1 (00089h)

Table 122. SS_TX1_FTRTRANS1 register (address 0089h) bit description

Bit Symbol Access Value Description

31:24 TX1_SS_FTRANS7 rw TX1 falling transition value 7

23:16 TX1_SS_FTRANS6 rw TX1 falling transition value 6

15:8

7:0

TX1_SS_FTRANS5

TX1_SS_FTRANS4 rw rw

TX1 falling transition value 5

TX1 falling transition value 4

9.23.66 SS_TX1_FTRTRANS2 (0008Ah)

Table 123. SS_TX1_FTRTRANS2 register (address 008Ah) bit description

Bit Symbol Access Value Description

31:24

23:16

15:8

TX1_SS_FTRANS11

TX1_SS_FTRANS10

TX1_SS_FTRANS9 rw rw rw

TX1 rising transition value 11

TX1 rising transition value 10

TX1 rising transition value 9

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Table 123. SS_TX1_FTRTRANS2 register (address 008Ah) bit description

...continued

Bit Symbol Access Value Description

7:0 TX1_SS_FTRANS8 rw TX1 rising transition value 8

9.23.67 SS_TX1_FTRTRANS3 (0008Bh)

Table 124. SS_TX1_FTRTRANS3 register (address 008Bh) bit description

Bit Symbol Access Value Description

31:24

23:16

TX1_SS_FTRANS15

TX1_SS_FTRANS14 rw rw

TX1 rising transition value 15

TX1 rising transition value 14

15:8

7:0

TX1_SS_FTRANS13

TX1_SS_FTRANS12 rw rw

TX1 rising transition value 13

TX1 rising transition value 12

9.23.68 SS_TX2_FTRTRANS0 (0008Ch)

Table 125. SS_TX2_FTRTRANS0 register (address 008Ch) bit description

Bit Symbol Access Value Description

31:24 TX2_SS_FTRANS3 rw TX2 falling transition value 3

23:16 TX2_SS_FTRANS2 rw TX2 falling transition value 2

15:8

7:0

TX2_SS_FTRANS1

TX2_SS_FTRANS0 rw rw

TX2 falling transition value 1

TX2 falling transition value 0

9.23.69 SS_TX2_FTRTRANS1 (0008Dh)

Table 126. SS_TX2_FTRTRANS1 register (address 008Dh) bit description

Bit Symbol Access Value Description

31:24 TX2_SS_FTRANS7 rw TX2 falling transition value 7

23:16

15:8

7:0

TX2_SS_FTRANS6

TX2_SS_FTRANS5

TX2_SS_FTRANS4 rw rw rw

TX2 falling transition value 6

TX2 falling transition value 5

TX2 falling transition value 4

9.23.70 SS_TX2_FTRTRANS2 (0008Eh)

Table 127. SS_TX2_FTRTRANS2 register (address 008Eh) bit description

Bit Symbol Access Value Description

31:24 TX2_SS_FTRANS11 rw TX2 falling transition value 11

23:16

15:8

7:0

TX2_SS_FTRANS10

TX2_SS_FTRANS9

TX2_SS_FTRANS8 rw rw rw

TX2 falling transition value 10

TX2 falling transition value 9

TX2 falling transition value 8

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9.23.71 SS_TX2_FTRTRANS3 (0008Fh)

Table 128. SS_TX2_FTRTRANS3 register (address 008Fh) bit description

Bit Symbol Access Value Description

31:24

23:16

TX2_SS_FTRANS15

TX2_SS_FTRANS14 rw rw

TX2 falling transition value 15

TX2 falling transition value 14

15:8

7:0

TX2_SS_FTRANS13

TX2_SS_FTRANS12 rw rw

TX2 falling transition value 13

TX2 falling transition value 12

9.24 EEPROM configuration description

The settings done in EEPROM are used for basic configuration which does not change frequently. Typically it is performed once during trimming or configuration of a product.

The EEPROM has a limited number of erase/write cycles that can be performed. This means, that configurations that change frequently must be performed in standard registers which do not keep their value during reset and power-off.

This section describes the EEPROM configuration of the PN5190B1.

Writing to the EEPROM has to be performed with Read-Modify-Write for all memory addresses which contain RFU bits.

9.24.1 EEPROM configuration overview

Table 129. EEPROM CONFIGURATION REGISTER

Address

(HEX)

Name

0 DCDC_PWR_CONFIG

DCDC_CONFIG

TXLDO_CONFIG

TXLDO_VDDPA_HIGH

TXLDO_VDDPA_LOW

TXLDO_VDDPA_MAX_RDR

TXLDO_VDDPA_HIGH_MAX_CARD

BOOST_DEFAULT_VOLTAGE

XTAL_CONFIG

XTAL_TIMEOUT

CLK_INPUT_FREQ

XTAL_CHECK_DELAY

TEMP_WARNING

RFU

ENABLE_GPIO0_ON_OVERTEMP

RFU

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Table 129. EEPROM CONFIGURATION REGISTER

...continued

Address

(HEX)

Name

19 RFU

RFU

RESIDUAL_AMP_LEVEL_A106

EDGE_TYPE_A106

EDGE_STYLE_A106

EDGE_LENGTH_A106

RESIDUAL_AMP_LEVEL_A212

EDGE_TYPE_A212

EDGE_STYLE_A212

EDGE_LENGTH_A212

RESIDUAL_AMP_LEVEL_A424

EDGE_TYPE_A424

EDGE_STYLE_A424

EDGE_LENGTH_A424

RESIDUAL_AMP_LEVEL_A848

EDGE_TYPE_A848

EDGE_STYLE_A848

EDGE_LENGTH_A848

RESIDUAL_AMP_LEVEL_B106

EDGE_TYPE_B106

EDGE_STYLE_B106

EDGE_LENGTH_B106

RESIDUAL_AMP_LEVEL_B212

EDGE_TYPE_B212

EDGE_STYLE_B212

EDGE_LENGTH_B212

RESIDUAL_AMP_LEVEL_B424

EDGE_TYPE_B424

EDGE_STYLE_B424

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Table 129. EEPROM CONFIGURATION REGISTER

...continued

Address

(HEX)

Name

3D EDGE_LENGTH_B424

RESIDUAL_AMP_LEVEL_B848

EDGE_TYPE_A848

EDGE_STYLE_A848

EDGE_LENGTH_A848

RESIDUAL_AMP_LEVEL_F212

EDGE_TYPE_F212

EDGE_STYLE_F212

EDGE_LENGTH_F212

RESIDUAL_AMP_LEVEL_F424

EDGE_TYPE_F424

EDGE_STYLE_F424

EDGE_LENGTH_F424

RESIDUAL_AMP_LEVEL_V100_26

EDGE_TYPE_V100_26

EDGE_STYLE_V100_26

EDGE_LENGTH_V100_26

RESIDUAL_AMP_LEVEL_V100_53

EDGE_TYPE_V100_53

EDGE_STYLE_V100_53

EDGE_LENGTH_V100_53

RESIDUAL_AMP_LEVEL_V100_106

EDGE_TYPE_V100_106

EDGE_STYLE_V100_106

EDGE_LENGTH_V100_106

RESIDUAL_AMP_LEVEL_V100_212

EDGE_TYPE_V100_212

EDGE_STYLE_V100_212

EDGE_LENGTH_V100_212

RESIDUAL_AMP_LEVEL_V10_26

EDGE_TYPE_V10_26

EDGE_STYLE_V10_26

EDGE_LENGTH_V10_26

RESIDUAL_AMP_LEVEL_V10_53

EDGE_TYPE_V10_53

EDGE_STYLE_V10_53

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Table 129. EEPROM CONFIGURATION REGISTER

...continued

Address

(HEX)

Name

61 EDGE_LENGTH_V10_53

RESIDUAL_AMP_LEVEL_V10_106

EDGE_TYPE_V10_106

EDGE_STYLE_V10_106

EDGE_LENGTH_V10_106

RESIDUAL_AMP_LEVEL_V10_212

EDGE_TYPE_V10_212

EDGE_STYLE_V10_212

EDGE_LENGTH_V10_212

RESIDUAL_AMP_LEVEL_V10_212

EDGE_TYPE_V10_212

EDGE_STYLE_V10_212

EDGE_LENGTH_V10_212

RESIDUAL_AMP_LEVEL_180003m3_tari18p88

EDGE_TYPE_180003m3_tari18p88

EDGE_STYLE_180003m3_tari18p88

EDGE_LENGTH_180003m3_tari18p88

RESIDUAL_AMP_LEVEL_180003m3_tari9p44

EDGE_TYPE_180003m3_tari9p44

EDGE_STYLE_180003m3_tari9p44

EDGE_LENGTH_180003m3_tari9p44

RESIDUAL_AMP_LEVEL_B_PRIME_106

EDGE_TYPE_B_PRIME_106

EDGE_STYLE_B_PRIME_106

EDGE_LENGTH_B_PRIME_106

DPC_CONFIG

DPC_TARGET_CURRENT

DPC_HYSTERESIS_LOADING

RFU

DPC_HYSTERESIS_UNLOADING

DPC_TXLDOVDDPALow

DPC_TXGSN

DPC_RDON_Control

DPC_InitialRDOn_RFOn

RFU

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1FC

206

210

2B2

2B3

2B5

2B8

2B9

1CA

1D4

1DE

1E8

1F2

198

1A2

1AC

1B6

1C0

166

170

17A

184

18E

139

13E

148

152

15C

137

Table 129. EEPROM CONFIGURATION REGISTER

...continued

Address

(HEX)

Name

83 RFU

RFU

DPC_GUARD_TIME

DPC_ENABLE_DURING_FDT

DPC_GUARD_TIME_AFTER_RX

RFU

DPC_LOOKUP_TABLE

ARC_CONFIG

ARC_VDDPA

ARC_RM_A106

ARC_RM_A212

ARC_RM_A424

ARC_RM_A848

ARC_RM_B106

ARC_RM_B212

ARC_RM_B424

ARC_RM_B848

ARC_RM_F212

ARC_RM_F424

ARC_RM_V6p6

ARC_RM_V26

ARC_RM_V53

ARC_RM_V106

ARC_RM_V212

ARC_RM_18003m3_SC424_4MAN

ARC_RM_18003m3_SC848_2MAN

ARC_RM_18003m3_SC848_4MAN

ARC_RM_18003m3_SC848_2MAN

ARC_RM_AI106

ARC_RM_AI212

ARC_RM_AI424

RF_DEBOUNCE_TIMEOUT

SENSE_RES

NFC_ID1

SEL_RES

FELICA_POLL_RES

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4B5

4BF

4C2

4C6

4C7

492

494

496

49B

49E

2DC

2DE

2DF

2E0

3A2

Table 129. EEPROM CONFIGURATION REGISTER

...continued

Address

(HEX)

Name

2CB RANDOM_UID_ENABLE

2CC

2DA

MFC_AUTH_TIMEOUT

RSSI_TIMER

RSSI_TIMER_FIRST_PERIOD

RSSI_CTRL_00_AB

RSSI_NB_ENTRIES_AB

RSSI_THRESHOLD_PHASE_TABLE

TX_PARAM_ENTRY_TABLE

LPCD_AVG_SAMPLES

LPCD_RSSI_TARGET

LPCD_RSSI_HYST

RFU

LPCD_THRESHOLD

LPCD_VDDPA

ULPCD_VDDPA_CTRL

ULPCD_TIMING_CTRL

ULPCD_VOLTAGE_CTRL

RFU

4C9

4CA

4CB

4CC

559

ULPCD_RSSI_GUARD_TIME

ULPCD_RSSI_SAMPLE_CFG

ULPCD_THRESH_LVL

ULPCD_GPIO3

TXIRQ_GUARDTIME

55D

561

FDT_DEFAULTVAL

RXIRQ_GUARDTIME

562-6D2 RFU

6D3 NFCLD_RFLD_Valid

6D4-ABB RFU

ABC CurrentSensorTrimConfig

ABD-BD9 RFU

BDA

C03

C83

CORRECTION_ENTRY_TABLE

RTRANS_FRTANS_TABLE

CFG_NOV_CAL

C84

C85

C86

NOV_CAL_VAL1

NOV_CAL_VAL2

NOV_CAL_THRESHOLD

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Table 129. EEPROM CONFIGURATION REGISTER

...continued

Address

(HEX)

Name

C87 NOV_CAL_OFFSET1

C8B

C8F

NOV_CAL_OFFSET2

VDDPA_DISCHARGE

C9D ARC_RM_A106_FDT

CA8-CC4 RFU

CC5

CC9

CCD

Tx_Symbol23_Mod_Reg_BR_53

Tx_Data_Mod_Reg_BR_53

Tx_Symbol23_Mod_Reg_BR_106

CD1

CD5

CD9

CDDh-14

00h

Tx_Data_Mod_Reg_BR_106

Tx_Symbol23_Mod_Reg_BR_212

Tx_Data_Mod_Reg_BR_212

DO NOT TOUCH OR OVERWRITE, INTERNAL SETTINGS

9.24.2 DCDC_PWR_CONFIG (0000h)

Table 130. PWR_CONFIG (address 0000h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

0 DC-DC usage in card mode

7 0b: DC-DC is not powered and set to bypass

1b: DC-DC is powered and not bypassed

DC-DC usage in reader mode

6 0b: DC-DC is not powered and set to bypass

1b: DC-DC is powered and not bypassed

5 Do not touch, default value 01b RFU

VUP input voltage 4..0 0x00: Not connected or 0 V

0x01: VUP supplied by PN5190B1 itself (pin VUP_TX connected to VBAT/VBATPWR)

0x02: Internal DC-DC with fixed VDDBOOST

0x04: Internal DC-DC with auto by pass and variable boost w.r.t VDDPA (internal DPC controls VDDBOOST): DC-DC goes into pass through mode when the VDDPA goes below 3.3 V. When VDDPA is greater than 3.3 V, the DC-DC is configured to boost voltage in range of 3.3 V to 6 V.

0x05 - 0x09: RFU

0x10: external supply

9.24.3 DCDC_CONFIG (0001h)

Table 131. DCDC_CONFIG (address 0001h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1 DC-DC configuration

7:5 RFU

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Table 131. DCDC_CONFIG (address 0001h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

4 DC-DC passthrough feature is:

0: Not supported (Vout = 0v or +5v)

1: Supported (Vout = 0v, Vin or +5v)

3 Use of DC-DC for LPCD (attention: not ULPCD)

1: enabled

0: disabled

2:0 RFU

9.24.4 TXLDO_CONFIG (0002h)

Table 132. TXLDO_CONFIG (address 0002h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2 TXLDO

Configuration

31:12 RFU

11:10 RFU

9:4 TXLDO output voltage

VDDPA_1V50 /* 0x00 */

VDDPA_1V60, /* 0x01 */

VDDPA_1V70, /* 0x02 */ VDDPA_1V80, /* 0x03 */ VDDPA_1V90, /* 0x04 */ VDDPA_

2V00, /* 0x05 */ VDDPA_2V10, /* 0x06 */ VDDPA_2V20, /* 0x07 */ VDDPA_2V30, /*

0x08 */ VDDPA_2V40, /* 0x09 */ VDDPA_2V50, /* 0x0A */ VDDPA_2V60, /* 0x0B */

VDDPA_2V70, /* 0x0C */ VDDPA_2V80, /* 0x0D */ VDDPA_2V90, /* 0x0E */ VDDPA_

3V00, /* 0x0F */ VDDPA_3V10, /* 0x10 */ VDDPA_3V20, /* 0x11 */ VDDPA_3V30, /

* 0x12 */ VDDPA_3V40, /* 0x13 */ VDDPA_3V50, /* 0x14 */ VDDPA_3V60, /* 0x15 */

VDDPA_3V70, /* 0x16 */ VDDPA_3V80, /* 0x17 */ VDDPA_3V90, /* 0x18 */ VDDPA_

4V00, /* 0x19 */ VDDPA_4V10, /* 0x1A */ VDDPA_4V20, /* 0x1B */ VDDPA_4V30, /*

0x1C */ VDDPA_4V40, /* 0x1D */ VDDPA_4V50, /* 0x1E */ VDDPA_4V60, /* 0x1F */

VDDPA_4V70, /* 0x20 */ VDDPA_4V80, /* 0x21 */ VDDPA_4V90, /* 0x22 */ VDDPA_

5V00, /* 0x23 */ VDDPA_5V10, /* 0x24 */ VDDPA_5V20, /* 0x25 */ VDDPA_5V30, /

* 0x26 */ VDDPA_5V40, /* 0x27 */ VDDPA_5V50, /* 0x28 */ VDDPA_5V60, /* 0x29 */

VDDPA_5V70, /* 0x2A */

3:1 RFU

0 Enable TXLDO

0b: disabled - no voltage output of the TXLDO

1b: enabled - regulated output of the TXLDO according to bits 9:4

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9.24.5 TXLDO_VDDPA_HIGH (0006h)

Table 133. TXLDO_VDDPA_HIGH (address 0006h) EEPROM configuration bit description

Address

(hex)

Function

6 TXLDO output: initial voltage in case the DPC is used. Applies directly at the beginning of the RF-field-on before any DPC regulation takes place.

Bit Description

0x15: 3V60

0x16: 3V70

0x17: 3V80

0x18: 3V90

0x19: 4V00

0x1A: 4V10

0x1B: 4V20

0x1C: 4V30

0x1D: 4V40

0x1E: 4V50

0x1F: 4V60

0x20: 4V70

0x21: 4V80

0x22: 4V90

0x23: 5V00

0x24: 5V10

0x25: 5V20

0x26: 5V30

0x27: 5V40

0x28: 5V50

0x29: 5V60

0x2A: 5V70

7:0 0x00: 1V50

0x01: 1V60

0x02: 1V70

0x03: 1V80

0x04: 1V90

0x05: 2V00

0x06: 2V10

0x07: 2V20

0x08: 2V30

0x09: 2V40

0x0A: 2V50

0x0B: 2V60

0x0C: 2V70

0x0D: 2V80

0x0E: 2V90

0x0F: 3V00

0X10: 3V10

0x11: 3V20

0x12: 3V30

0x13: 3V40

0x14: 3V50

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9.24.6 TXLDO_VDDPA_LOW (0007h)

Table 134. TXLDO_VDDPA_LOW (address 0007h) EEPROM configuration bit description

Address

(hex)

Function

7 TXLDO output voltage in case the DPC is disabled and not used.

Bit Description

0x15: 3V60

0x16: 3V70

0x17: 3V80

0x18: 3V90

0x19: 4V00

0x1A: 4V10

0x1B: 4V20

0x1C: 4V30

0x1D: 4V40

0x1E: 4V50

0x1F: 4V60

0x20: 4V70

0x21: 4V80

0x22: 4V90

0x23: 5V00

0x24: 5V10

0x25: 5V20

0x26: 5V30

0x27: 5V40

0x28: 5V50

0x29: 5V60

0x2A: 5V70

7:0 0x00: 1V50

0x01: 1V60

0x02: 1V70

0x03: 1V80

0x04: 1V90

0x05: 2V00

0x06: 2V10

0x07: 2V20

0x08: 2V30

0x09: 2V40

0x0A: 2V50

0x0B: 2V60

0x0C: 2V70

0x0D: 2V80

0x0E: 2V90

0x0F: 3V00

0X10: 3V10

0x11: 3V20

0x12: 3V30

0x13: 3V40

0x14: 3V50

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9.24.7 TXLDO_VDDPA_MAX_RDR (0008h)

Table 135. TXLDO_VDDPA_MAX_RDR (address 0008h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

8 VDDPA maximum output voltage in case the DPC is enabled in reader mode

0x15: 3V60

0x16: 3V70

0x17: 3V80

0x18: 3V90

0x19: 4V00

0x1A: 4V10

0x1B: 4V20

0x1C: 4V30

0x1D: 4V40

0x1E: 4V50

0x1F: 4V60

0x20: 4V70

0x21: 4V80

0x22: 4V90

0x23: 5V00

0x24: 5V10

0x25: 5V20

0x26: 5V30

0x27: 5V40

0x28: 5V50

0x29: 5V60

0x2A: 5V70

7:0 0x00: 1V50

0x01: 1V60

0x02: 1V70

0x03: 1V80

0x04: 1V90

0x05: 2V00

0x06: 2V10

0x07: 2V20

0x08: 2V30

0x09: 2V40

0x0A: 2V50

0x0B: 2V60

0x0C: 2V70

0x0D: 2V80

0x0E: 2V90

0x0F: 3V00

0X10: 3V10

0x11: 3V20

0x12: 3V30

0x13: 3V40

0x14: 3V50

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9.24.8 TXLDO_VDDPA_MAX_CARD (0009h)

Table 136. TXLDO_VDDPA_MAX_CARD (address 0009h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

9 VDDPA maximum output voltage in case the APC is enabled in card mode

0x15: 3V60

0x16: 3V70

0x17: 3V80

0x18: 3V90

0x19: 4V00

0x1A: 4V10

0x1B: 4V20

0x1C: 4V30

0x1D: 4V40

0x1E: 4V50

0x1F: 4V60

0x20: 4V70

0x21: 4V80

0x22: 4V90

0x23: 5V00

0x24: 5V10

0x25: 5V20

0x26: 5V30

0x27: 5V40

0x28: 5V50

0x29: 5V60

0x2A: 5V70

7:0 0x00: 1V50

0x01: 1V60

0x02: 1V70

0x03: 1V80

0x04: 1V90

0x05: 2V00

0x06: 2V10

0x07: 2V20

0x08: 2V30

0x09: 2V40

0x0A: 2V50

0x0B: 2V60

0x0C: 2V70

0x0D: 2V80

0x0E: 2V90

0x0F: 3V00

0X10: 3V10

0x11: 3V20

0x12: 3V30

0x13: 3V40

0x14: 3V50

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9.24.9 BOOST_DEFAULT_VOLTAGE (000Ah)

Table 137. BOOST_DEFAULT_VOLTAGE (address 000Ah) EEPROM configuration bit description

Address

(hex)

Function Bit Description

0A DC-DC configuration

7:0 VDDBOOST output voltage in case of DC-DC with fixed VDDBOOST is enabled (PWR_

CONFIG)

0x00: 3.1 V

0x01: 3.2 V

0x02: 3.3 V

0x03: 3.4 V

0x04: 3.5 V

0x05: 3.6 V

0x06: 3.7 V

0x07: 3.8 V

0x08: 3.9 V

0x09: 4.0 V

0x0A: 4.1 V

0x0B: 4.2 V

0x0C: 4.3 V

0x0D: 4.4 V

0x0E: 4.5 V

0x0F: 4.6 V

0x10: 4.7 V

0x11: 4.8 V

0x12: 4.9 V

0x13: 5.0 V

0x14: 5.1 V

0x15: 5.2 V

0x16: 5.3 V

0x17: 5.4 V

0x18: 5.5 V

0x19: 5.6 V

0x1A: 5.7 V

0x1B: 5.8 V

0x1C: 5.9 V

0x1D: 6.0 V all other values: RFU

9.24.10 XTAL_CONFIG (0010h)

Table 138. XTAL_CONFIG (address 0010h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

10 Configuration for the XTAL startup procedure

7:1 RFU

0 Crystal recalibration start after wake-up from standby

1: enable

0: disable

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9.24.11 XTAL_TIMEOUT (0011h)

Table 139. XTAL_TIMEOUT (address 0011h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

11 Configuration for the XTAL startup procedure

7:0 Timeout for XTAL to be ready (in *128us), if the timeout happens, an XTAL error event will be raised.

This configuration does not speed up the boot time.

9.24.12 CLK_INPUT_FREQ (0012h)

Table 140. CLK_INPUT_FREQ (address 0012h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

12 Configuration for the PLL input clock frequency

7:4 RFU

3:0 0010b: 24 MHz

0011b: 32 MHz

0100b: 48 MHz

1000b: XTAL 27.12 MHz

All others: RFU

9.24.13 XTAL_CHECK_DELAY (0013h)

Correct Crystal clocking is detected by locking the crystal to the PLL. This allows the system to start quick independent from the crystal startup time. High-quality crystals will start up typically fast and allow by this optimized current consumption, e.g, during

ULPCD.

A user needs to find an optimized balance between retry numbers of checking for a proper locking and the interval for checking for a locked PLL.

This allows to configure a timeout value for locking the crystal to the PLL. The timeout value is defined by Retry_number x Interval . If the timeout is reached, a clock error is raised.

Table 141. XTAL_CHECK_DELAY (address 0013h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

13 Retry_number

Interval

7:5 Max Number of retries before a clock error is raised

4:0 Interval which is used to check if XTAL is ready (unit is 256/fc, e.g. ~18.8 us). This is the time to try to lock the PLL, a stable crystal clock is required for locking. If the PLL is not locked, a next retry to lock the PLL will be done after this interval.

This value can be used to optimize the startup time dependent on the crystal characteristics. This is important, e.g., for optimization of the LPCD and ULPCD.

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9.24.14 TEMP_WARNING (0014h)

Table 142. TEMP_WARNING (address 0014h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

14 CLIF & PMU temperature warning

7:6 PMU high threshold (0: disabled, 1:114degC, 2:125degC, 3:130degC)

5:4 PMU low threshold (0: disabled, 1:114degC, 2:125degC, 3:130degC)

3:2 high threshold (0: disabled, 1:114 °C, 2:125 °C, 3:130 °C) in case temp sensor is triggered, transmitter and VDDPALDO are shut down, system goes in low-power mode - default is 130 °C. This event is not indicated by an IRQ to the host, instead GPIO0 with configurable high/low polarity is used to indicate this critical event (Register PAD_CONFIG 0x4B).

To enable this event on GPIO0, the EEPROM register ENABLE_GPIO0_ON_

OVERTEMP (0054h) must be set.

1:0 low threshold (0: disabled, 1:114 °C, 2:125 °C, 3:130 °C) - in case temperature sensed is lower than threshold, system wakes up from low-power mode, a temp wake-up event is issued to the host - default is 114 °C. This event is not indicated by an IRQ to the host, instead GPIO0 with configurable high/low polarity is used to indicate this critical event

(Register PAD_CONFIG 0x52).

To enable this event on GPIO0, the EEPROM register ENABLE_GPIO0_ON_

OVERTEMP (0054h) must be set.

9.24.15 ENABLE_GPIO0_ON_OVERTEMP (0016h)

Table 143. ENABLE_GPIO0_ON_OVERTEMP (address 0016h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

16 RFU 7..1 -

Set/Clear GPIO0 during over temperature.

0 If set, the GPIO0 is used to indicate a temperature event.

The temperature warning levels are configured in the EEPROM Register TEMP_

WARNING (0048h).

9.24.16 RESIDUAL_AMPL_LEVEL_A106 (0022h)

Table 144. RESIDUAL_AMPL_LEVEL_A106 (address 0022h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0% carrier

FF: 100% carrier

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9.24.17 EDGE_TYPE_A106 (0023h)

Table 145. EDGE_TYPE_A106 (address 0023h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.18 EDGE_STYLE_A106 (0024h)

Table 146. EDGE_STYLE_A106 (address 0024h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

3 -

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

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9.24.19 EDGE_LENGTH_A106 (0025h)

Table 147. EDGE_LENGTH_A106 (address 0025h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.20 RESIDUAL_AMPL_LEVEL_A212 (0026h)

Table 148. RESIDUAL_AMPL_LEVEL_A212 (address 0026h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.21 EDGE_TYPE_A212 (0027h)

Table 149. EDGE_TYPE_A212 (address 0027h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

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Table 149. EDGE_TYPE_A212 (address 0027h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.22 EDGE_STYLE_A212 (0028h)

Table 150. EDGE_STYLE_A212 (address 0028h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU

Transmitter shaping configuration falling edge

7 -

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.23 EDGE_LENGTH_A212 (0029h)

Table 151. EDGE_LENGTH_A212 (address 0029h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

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9.24.24 RESIDUAL_AMPL_LEVEL_A424 (002Ah)

Table 152. RESIDUAL_AMPL_LEVEL_A424 (address 002Ah) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0% carrier

FF: 100% carrier

9.24.25 EDGE_TYPE_A424 (002Bh)

Table 153. EDGE_TYPE_A424 (address 002Bh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.26 EDGE_STYLE_A424 (002Ch)

Table 154. EDGE_STYLE_A424 (address 002Ch) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

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Table 154. EDGE_STYLE_A424 (address 002Ch) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.27 EDGE_LENGTH_A424 (002Dh)

Table 155. EDGE_LENGTH_A424 (address 002Ch) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.28 RESIDUAL_AMPL_LEVEL_A848 (002Eh)

Table 156. RESIDUAL_AMPL_LEVEL_A848 (address 002Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

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9.24.29 EDGE_TYPE_A848 (002Fh)

Table 157. EDGE_TYPE_A848 (address 002Fh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.30 EDGE_STYLE_A848 (0030h)

Table 158. EDGE_STYLE_A848 (address 0030h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

3 -

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

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9.24.31 EDGE_LENGTH_A848 (0031h)

Table 159. EDGE_LENGTH_A848 (address 0031h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.32 RESIDUAL_AMPL_LEVEL_B106 (0032h)

Table 160. RESIDUAL_AMPL_LEVEL_B106 (address 0032h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.33 EDGE_TYPE_B106 (0033h)

Table 161. EDGE_TYPE_B106 (address 0033h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

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Table 161. EDGE_TYPE_B106 (address 0033h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.34 EDGE_STYLE_B106 (0034h)

Table 162. EDGE_STYLE_B106 (address 0034h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU

Transmitter shaping configuration falling edge

7 -

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.35 EDGE_LENGTH_B106 (0035h)

Table 163. EDGE_LENGTH_B106 (address 0035h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

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9.24.36 RESIDUAL_AMPL_LEVEL_B212 (0036h)

Table 164. RESIDUAL_AMPL_LEVEL_B212 (address 0036h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.37 EDGE_TYPE_B212 (0037h)

Table 165. EDGE_TYPE_B212 (address 0037h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.38 EDGE_STYLE_B212 (0038h)

Table 166. EDGE_STYLE_B212 (address 0038h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

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Table 166. EDGE_STYLE_B212 (address 0038h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.39 EDGE_LENGTH_B212 (0039h)

Table 167. EDGE_LENGTH_B212 (address 0039h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.40 RESIDUAL_AMPL_LEVEL_B424 (003Ah)

Table 168. RESIDUAL_AMPL_LEVEL_B424 (address 003Ah) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

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9.24.41 EDGE_TYPE_B424 (003Bh)

Table 169. EDGE_TYPE_B424 (address 003Bh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.42 EDGE_STYLE_B424 (003Ch)

Table 170. EDGE_STYLE_B424 (address 003Ch) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1,2 or 3:

3 -

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

2:0 If EDGE_TYPE is 1,2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

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9.24.43 EDGE_LENGTH_B424 (003Dh)

Table 171. EDGE_LENGTH_B424 (address 003Dh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.44 RESIDUAL_AMPL_LEVEL_B848 (003Eh)

Table 172. RESIDUAL_AMPL_LEVEL_B848 (address 003Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.45 EDGE_TYPE_B848 (003Fh)

Table 173. EDGE_TYPE_B848 (address 003Fh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

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Table 173. EDGE_TYPE_B848 (address 003Fh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.46 EDGE_STYLE_B848 (0040h)

Table 174. EDGE_STYLE_B848 (address 0040h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU

Transmitter shaping configuration falling edge

7 -

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.47 EDGE_LENGTH_B848 (0041h)

Table 175. EDGE_LENGTH_B848 (address 0041h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

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9.24.48 RESIDUAL_AMPL_LEVEL_F212 (0042h)

Table 176. RESIDUAL_AMPL_LEVEL_F212 (address 0042h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.49 EDGE_TYPE_F212 (0043h)

Table 177. EDGE_TYPE_F212 (address 0043h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.50 EDGE_STYLE_F212 (0044h)

Table 178. EDGE_STYLE_F212 (address 0044h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

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Table 178. EDGE_STYLE_F212 (address 0044h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.51 EDGE_LENGTH_F212 (0045h)

Table 179. EDGE_LENGTH_F212 (address 0045h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.52 RESIDUAL_AMPL_LEVEL_F424 (0046h)

Table 180. RESIDUAL_AMPL_LEVEL_F424 (address 0046h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

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9.24.53 EDGE_TYPE_F424 (0047h)

Table 181. EDGE_TYPE_F424 (address 0047h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.54 EDGE_STYLE_F424 (0048h)

Table 182. EDGE_STYLE_F424 (address 0048h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

3 -

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

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9.24.55 EDGE_LENGTH_F424 (0049h)

Table 183. EDGE_LENGTH_F424 (address 0049h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.56 RESIDUAL_AMPL_LEVEL_V100_26 (004Ah)

Table 184. RESIDUAL_AMPL_LEVEL_V100_26 (address 004Ah) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.57 EDGE_TYPE_V100_26 (004Bh)

Table 185. EDGE_TYPE_V100_26 (address 004Bh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

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Table 185. EDGE_TYPE_V100_26 (address 004Bh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.58 EDGE_STYLE_V100_26 (004Ch)

Table 186. EDGE_STYLE_V100_26 (address 004Ch) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU

Transmitter shaping configuration falling edge

7 -

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.59 EDGE_LENGTH_V100_26 (004Dh)

Table 187. EDGE_LENGTH_V100_26 (address 004Dh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

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9.24.60 RESIDUAL_AMPL_LEVEL_V100_53 (004Eh)

Table 188. RESIDUAL_AMPL_LEVEL_V100_53 (address 004Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.61 EDGE_TYPE_V100_53 (004Fh)

Table 189. EDGE_TYPE_V100_53 (address 004Fh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.62 EDGE_STYLE_V100_53 (0050h)

Table 190. EDGE_STYLE_A106 (address 0050h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

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Table 190. EDGE_STYLE_A106 (address 0050h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.63 EDGE_LENGTH_V100_53 (0051h)

Table 191. EDGE_LENGTH_V100_53 (address 0051h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.64 RESIDUAL_AMPL_LEVEL_V100_106 (0052h)

Table 192. RESIDUAL_AMPL_LEVEL_V100_106 (address 0052h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

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9.24.65 EDGE_TYPE_V100_106 (0053h)

Table 193. EDGE_TYPE_V100_106 (address 0053h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.66 EDGE_STYLE_V100_106 (0054h)

Table 194. EDGE_STYLE_V100_106 (address 0054h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

3 -

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

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9.24.67 EDGE_LENGTH_V100_106 (0055h)

Table 195. EDGE_LENGTH_V100_106 (address 0055h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.68 RESIDUAL_AMPL_LEVEL_100_212 (0056h)

Table 196. RESIDUAL_AMPL_LEVEL_100_212 (address 0056h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.69 EDGE_TYPE_V100_212 (0057h)

Table 197. EDGE_TYPE_V100_212 (address 0057h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

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Table 197. EDGE_TYPE_V100_212 (address 0057h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.70 EDGE_STYLE_V100_212 (0058h)

Table 198. EDGE_STYLE_V100_212 (address 0058h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU

Transmitter shaping configuration falling edge

7 -

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.71 EDGE_LENGTH_V100_212 (0059h)

Table 199. EDGE_LENGTH_V100_212 (address 0059h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

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9.24.72 RESIDUAL_AMPL_LEVEL_V10_26 (005Ah)

Table 200. RESIDUAL_AMPL_LEVEL_V10_26 (address 005Ah) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.73 EDGE_TYPE_V10_26 (005Bh)

Table 201. EDGE_TYPE_V10_26 (address 005Bh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.74 EDGE_STYLE_V10_26 (005Ch)

Table 202. EDGE_STYLE_V10_26 (address 005Ch) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

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Table 202. EDGE_STYLE_V10_26 (address 005Ch) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.75 EDGE_LENGTH_V10_26 (005Dh)

Table 203. EDGE_LENGTH_V10_26 (address 005Dh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.76 RESIDUAL_AMPL_LEVEL_V10_53 (005Eh)

Table 204. RESIDUAL_AMPL_LEVEL_V10_53 (address 005Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

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9.24.77 EDGE_TYPE_V10_53 (005Fh)

Table 205. EDGE_TYPE_V10_53 (address 005Fh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.78 EDGE_STYLE_V10_53 (0060h)

Table 206. EDGE_STYLE_V10_53 (address 0060h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

3 -

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

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9.24.79 EDGE_LENGTH_V10_53 (0061h)

Table 207. EDGE_LENGTH_V10_53 (address 0061h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.80 RESIDUAL_AMPL_LEVEL_V10_106 (0062h)

Table 208. RESIDUAL_AMPL_LEVEL_V10_106 (address 0062h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.81 EDGE_TYPE_V10_106 (0063h)

Table 209. EDGE_TYPE_V10_106 (address 0063h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

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Table 209. EDGE_TYPE_V10_106 (address 0063h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.82 EDGE_STYLE_V10_106 (0064h)

Table 210. EDGE_STYLE_V100_212 (address 0064h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU

Transmitter shaping configuration falling edge

7 -

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.83 EDGE_LENGTH_V10_106 (0065h)

Table 211. EDGE_LENGTH_V10_106 (address 0065h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

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9.24.84 RESIDUAL_AMPL_LEVEL_V10_212 (0066h)

Table 212. RESIDUAL_AMPL_LEVEL_V10_212 (address 0066h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.85 EDGE_TYPE_V10_212 (0067h)

Table 213. EDGE_TYPE_V10_212 (address 0067h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.86 EDGE_STYLE_V10_212 (0068h)

Table 214. EDGE_STYLE_V10_212 (address 0068h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

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Table 214. EDGE_STYLE_V10_212 (address 0068h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.87 EDGE_LENGTH_V10_212 (0069h)

Table 215. EDGE_LENGTH_V100_212 (address 0069h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.88 RESIDUAL_AMPL_LEVEL_180003m3_tari18p88 (006Ah)

Table 216. RESIDUAL_AMPL_LEVEL_180003m3_tari18p88 (address 006Ah) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

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9.24.89 EDGE_TYPE_180003m3_tari18p88 (006Bh)

Table 217. EDGE_TYPE_180003m3_tari18p88 (address 006Bh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.90 EDGE_STYLE_180003m3_tari18p88 (006Ch)

Table 218. EDGE_STYLE_180003m3_tari18p88 (address 006Ch) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

3 -

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

PN5190B1

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9.24.91 EDGE_LENGTH_180003m3_tari18p88 (006Dh)

Table 219. EDGE_LENGTH_180003m3_tari18p88 (address 006Dh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.92 RESIDUAL_AMPL_LEVEL_180003m3_tari9p44 (006Eh)

Table 220. RESIDUAL_AMPL_LEVEL_180003m3_tari9p44 (address 006Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.93 EDGE_TYPE_180003m3_tari9p44 (006Fh)

Table 221. EDGE_TYPE_180003m3_tari9p44 (address 006Fh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

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Table 221. EDGE_TYPE_180003m3_tari9p44 (address 006Fh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.94 EDGE_STYLE_180003m3_tari9p44 (0070h)

Table 222. EDGE_STYLE_180003m3_tari9p44 (address 0070h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU

Transmitter shaping configuration falling edge

7 -

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.95 EDGE_LENGTH_180003m3_tari9p44 (0071h)

Table 223. EDGE_LENGTH_180003m3_tari9p44 (address 0071h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

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9.24.96 RESIDUAL_AMPL_LEVEL_B_PRIME_106 (0072h)

Table 224. RESIDUAL_AMPL_LEVEL_180003m3_tari18p88 (address 0072h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

22 Transmitter shaping configuration

7:0 Residual amplitude level

00: 0 % carrier

FF: 100 % carrier

9.24.97 EDGE_TYPE_B_PRIME_106 (0073h)

Table 225. EDGE_TYPE_B_PRIME_106 (address 0073h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

23 Transmitter shaping configuration

7:4 Definition of edge transition style of falling edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

3:0 Definition of edge transition style of rising edge

Defines style of edge transition:

Firmware based shaping:

1: linear transition between two amplitude levels

2: two linear transitions between amplitude levels

3: three linear transitions between amplitude levels Others: RFU

Lookup table based shaping:

4: lookup table-based transition, no automatic adaptation based on VDDPA

5: lookup table-based transition, automatic adaptation based on VDDPA including sCorrection

6: lookup table-based transition, automatic adaptation based on VDDPA but no sCorrection others: RFU

9.24.98 EDGE_STYLE_B_PRIME_106 (0074h)

Table 226. EDGE_STYLE_B_PRIME_106 (address 0074h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

24 RFU 7 -

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Table 226. EDGE_STYLE_B_PRIME_106 (address 0074h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

Transmitter shaping configuration falling edge

6:4 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of falling edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of falling edge (0,1,2,3)

RFU

Transmitter shaping configuration rising edge

3 -

2:0 If EDGE_TYPE is 1, 2 or 3:

Time constant configuration of rising edge (depends on edge style)

If EDGE_TYPE is 4,5,6:

This number is the lookup table which shall be used of rising edge (0,1,2,3)

9.24.99 EDGE_LENGTH_B_PRIME_106 (0075h)

Table 227. EDGE_LENGTH_B_PRIME_106 (address 0075h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

25 Transmitter shaping configuration

7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling edge at the same time)

0=disabled (1 transition state = one carrier cycle)

1=enabled (1 transition state = two carrier cycles)

6:5 RFU

4:0 Number of active transition states in rising and falling edge pattern (refers to both rising and falling edge at the same time)

9.24.100 DPC_CONFIG (0076h)

Table 228. DPC_CONFIG (address 0076h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

76 DPC Configuration 7:3 RFU

2 DPC in Active Target Mode:

0: disabled,

1: enabled

1 DPC in Active Initiator Mode:

0: disabled,

1: enabled

0 DPC in Reader/ Passive Initiator Mode:

0: disabled,

1: enabled

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9.24.101 DPC_TARGET_CURRENT (077h)

Table 229. DPC_TARGET_CURRENT (address 077h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

77 DPC Configuration 15:0 VDDPA target current in mA. The target current +/- hysteresis defines the limiting maximum current for the DPC.

This configuration shall not exceed 350 mA - hysteresis.

Note: The resulting current that is driven by the transmitter can be further reduced based on the current reduction lookup table entries.

9.24.102 DPC_HYSTERESIS_LOADING (079h)

The hysteresis (DPC_HYSTERESIS_LOADING, DPC_HYSTERESIS_UNLOADING) together with the target current (DPC_TARGET_CURRENT) defines the current limit, at which the DPC automatically decreases or increases the VDDPA.

The VDDPA is automatically reduced, as soon as the current exceeds the

DPC_TARGET_CURRENT + DPC_HYSTERESIS_LOADING, and the

VDDPA is automatically increased again, as soon as the current is below

DPC_TARGET_CURRENT – DPC_HYSTERESIS_UNLOADING.

Table 230. DPC_HYSTERESIS_LOADING (address 079h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

79 DPC Configuration 7:0 Absolute difference of measured transmitter current (target current incl. current reduction) in mA that triggers a DPC update event during loading.

Note: If the hysteresis is configured too small, it might cause an oscillation of the transmitted field.

Note: In most application, the default values work well and do not need to be modified.

9.24.103 DPC_HYSTERESIS_UNLOADING (07Ch)

The VDDPA is automatically reduced, as soon as the current exceeds the

DPC_TARGET_CURRENT + DPC_HYSTERESIS_LOADING, and the

VDDPA is automatically increased again, as soon as the current is below

DPC_TARGET_CURRENT – DPC_HYSTERESIS_UNLOADING.

Table 231. DPC_HYSTERESIS_UNLOADING (address 07Ch) EEPROM configuration bit description

Address

(hex)

Function Bit Description

7C DPC Configuration 7:0 Absolute difference of measured transmitter current (target current incl. current reduction) in mA that triggers a DPC update event during unloading.

Note: If the hysteresis is configured too small, it might cause an oscillation of the transmitted field.

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Note: In most application, the default values work well and do not need to be modified.

9.24.104 DPC_TXLDOVDDPALow (007Dh)

Table 232. DPC_TXLDOVDDPALow (address 007Dh) EEPROM configuration register bit description

Address

(hex)

Function Bit Description

7D DPC Configuration 7:0 VDDPA Low Limit for RDON

9.24.105 DPC_TXGSN (007Eh)

Table 233. DPC_TXGSN (address 007Eh) EEPROM configuration register bit description

Address

(hex)

Function Bit Description

7E DPC Configuration 7:0 for tx1_gsn < 20: resistance = 10 Ohm / (tx1_gsn + 1) for tx1_gsn >= 20: resistance = 0.5 Ohm

9.24.106 DPC_RDON_Control (007Fh)

Table 234. DPC_RDON_Control (address 007Fh) EEPROM configuration register bit description

Address

(hex)

Function Bit Description

7F DPC Configuration 7:0 00: Disabled

01: RdON Control

02-FF: RFU

9.24.107 DPC_InitialRDOn_RFOn (0080h)

Table 235. DPC_InitialRDOn_RFOn (address 0080h) EEPROM configuration register bit description

Address

(hex)

Function Bit Description

80 DPC Configuration 7:0 Initial GSP TX1/TX2 value during FieldON

9.24.108 DPC_GUARD_TIME (087h)

Table 236. DPC_GUARD_TIME (address 087h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

87 DPC guard time configuration

7:0 Guard time before TX and after RX. 1unit = 1us.

The DPC regulation is done once before TX and once after RX.

The guard time parameter is the time between DPC regulation completion and TX start.

The guard time parameter is the time between RX stop and DPC regulation start.

The guard time is always enabled for TX

Note: Recommendation is not to modify the default value.

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9.24.109 DPC_ENABLE_DURING_FDT (088h)

Table 237. DPC_ENABLE_DURING_FDT (address 088h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

88 DPC Configuration 7 DPC regulation enable during FDT

0: DPC disabled during FDT (debug purpose only)

1: DPC enabled during FDT (recommendation)

9.24.110 DPC_GUARD_TIME_AFTER_RX (089h)

Table 238. DPC_GUARD_TIME_AFTER_RX (address 089h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

RFU 7:1 -

DPC Configuration 0 Enable DPC guard time after RX

0: disable (debug purposes)

1: enable (recommended)

The guard time can be configured in register DPC_GUARD_TIME

Note: The guard time is always enabled for TX and cannot be disabled.

9.24.111 DPC_LOOKUP_TABLE (008Bh-0133h)

Table 239. DPC_LOOKUP_TABLE (008Bh-0133h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

08B

ENTRY 0

Target current reduction

31:0 This is the entry for 1.5 V

08C AWC amp mod change

31:23 ENTRY 0 -LSB - byte 0

Voltage step between DPC entries = 100 mV. Voltage offset start = 1.5 V bEntry_00 =

1V5 ... bEntry_42 = 5V7

Bits[7:0] = Target current reduction in mA (unsigned)

23:16 ENTRY 0 - byte 1

Bits[7:0] = Relative change of modulated amplitude level (signed)

08D AWC edge time constant for

ASK100

08E AWC falling edge time constant for

ASK10

15:8 ENTRY 0 - byte 2

Bits[3:0] = ASK100, Relative change of falling edge time constant (signed)

Bits[7:4] = ASK100, Relative change of rising edge time constant (signed)

7:0 ENTRY 0 -MSB - byte 4

Bits[3:0] = ASK10, Relative change of falling edge time constant (signed)

Bits[7:4] = ASK10, Relative change of rising edge time constant (signed)

08F

….

093

ENTRY 1

ENTRY 2

31:0 This is the entry for 1.6 V

….

31:0 This is the entry for 1.7 V

…..

….

0133 ENTRY 42

….

This is the entry for 5.6 V

31:0 This is the entry for 5.7 V

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9.24.112 ARC_CONFIG (0137h)

Table 240. ARC_CONFIG (address 0137h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

137 ARC Setting configuration

7 ARC algorithm enable

0: Disable

1: Enable

6:3 RFU

2:0 Number of entries in ARC table. (value between 0 to 4)

0: one entry

1: two entries

2: three entries

3: four entries

4: five entries

9.24.113 ARC_VDDPA (0139h)

Table 241. ARC_VDDPA (0139Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

13D VDDPA_4 7:0 Byte[4] = VDDPA range_index 4: if VDDPA voltage between VDDPA_3 to ARC_VDDPA_

13C VDDPA_3 7:0 Byte[3] = VDDPA_range_index 3: if VDDPA voltage between VDDPA_2 to ARC_VDDPA_

3 - 0.1

13B

13A

139

VDDPA_2

VDDPA_1

VDDPA_0

7:0 Byte[2] = VDDPA_range_index 2: if VDDPA voltage between VDDPA_1 to ARC_VDDPA_

2 - 0.1

7:0 Byte[1] = VDDPA_range_index 1: if VDDPA voltage between VDDPA_0 to (ARC_

VDDPA_1 - 0.1)

7:0 Byte[0] = VDDPA_range_index 0: if VDDPA voltage between 1.5 to (VDDPA_0 - 0.1)

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Note: VDDPA setting for Bytes 0...4:

0x00: 1V50

0x01: 1V60

0x02: 1V70

0x03: 1V80

0x04: 1V90

0x05: 2V00

0x06: 2V10

0x07: 2V20

0x08: 2V30

0x09: 2V40

0x0A: 2V50

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0x1B: 4V20

0x1C: 4V30

0x1D: 4V40

0x1E: 4V50

0x1F: 4V60

0x20: 4V70

0x21: 4V80

0x22: 4V90

0x23: 5V00

0x24: 5V10

0x25: 5V20

0x26: 5V30

0x27: 5V40

0x28: 5V50

0x29: 5V60

0x2A: 5V70

0x0B: 2V60

0x0C: 2V70

0x0D: 2V80

0x0E: 2V90

0x0F: 3V00

0X10: 3V10

0x11: 3V20

0x12: 3V30

0x13: 3V40

0x14: 3V50

0x15: 3V60

0x16: 3V70

0x17: 3V80

0x18: 3V90

0x19: 4V00

0x1A: 4V10

9.24.114 ARC_RM_A106 (013Eh)

This is the setting for type A-106.

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Table 242. ARC_RM_A106 (address 013Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

146 RM_RX_ARC_4 15:0 Bit[15]

This setting is only taken into account if bit 14 of address 13E is set.

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits

0..9 of table ARC_RM_A106 are used

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

144 RM_RX_ARC_3

142 RM_RX_ARC_2

15:0 Bit[15]

This setting is only taken into account if bit 14 of address 13E is set.

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits

0..9 of table ARC_RM_A106 are used

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

This setting is only taken into account if bit 14 of address 13E is set.

0: ARC settings always apply, bits 0...9 from the table ARC_RM_106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits

0..9 of table ARC_RM_A106 are used

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

140 RM_RX_ARC_1 15:0 Bit[15]

This setting is only taken into account if bit 14 of address 13E is set.

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits

0..9 of table ARC_RM_A106 are used

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 242. ARC_RM_A106 (address 013Eh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

13E RM_RX_ARC_0 15:0 Bit[15]

This setting is only taken into account if bit 14 of address 13E is set.

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits

0..9 of table ARC_RM_A106 are used

Bit [14]:

1: ARC enabled for this Tech and Baudrate.

0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

9.24.115 ARC_RM_A212 (0148h)

This is the setting for type A-212.

Table 243. ARC_RM_A212 (address 0148h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

150 RM_RX_ARC_4

14E RM_RX_ARC_3

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 243. ARC_RM_A212 (address 0148h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

14C RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

14A RM_RX_ARC_1

148 RM_RX_ARC_0

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.116 ARC_RM_A424 (0152h)

This is the setting for type A-424.

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Table 244. ARC_RM_A424 (address 0152h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

15A RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A424 are used, else settings will be used from LoadProtocol A424

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and

Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

158 RM_RX_ARC_3

156 RM_RX_ARC_2

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A424 are used, else settings will be used from LoadProtocol A424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A424 are used, else settings will be used from LoadProtocol A424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

154 RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A424 are used, else settings will be used from LoadProtocol A424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 244. ARC_RM_A424 (address 0152h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

152 RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.117 ARC_RM_A848 (015Ch)

This is the setting for type A-848.

Table 245. ARC_RM_A848 (address 015Ch) EEPROM configuration bit description

Address

(hex)

Function Bit Description

164 RM_RX_ARC_4 15:0

162 RM_RX_ARC_3 15:0

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A848 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A848 are used, else settings will be used from LoadProtocol A848

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A848 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A848 are used, else settings will be used from LoadProtocol A848

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 245. ARC_RM_A848 (address 015Ch) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

160 RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A848 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A848 are used, else settings will be used from LoadProtocol A848

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15E RM_RX_ARC_1 15:0

15C RM_RX_ARC_0 15:0

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A848 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A848 are used, else settings will be used from LoadProtocol A848

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.118 ARC_RM_B106 (0166h)

This is the setting for type B-106.

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Table 246. ARC_RM_B106 (address 0166h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

16E RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B106 are used, else settings will be used from LoadProtocol B106

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

16C RM_RX_ARC_3 15:0

16A RM_RX_ARC_2 15:0

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B106 are used, else settings will be used from LoadProtocol B106

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B106 are used, else settings will be used from LoadProtocol B106

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

168 RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B106 are used, else settings will be used from LoadProtocol B106

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 246. ARC_RM_B106 (address 0166h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

166 RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.119 ARC_RM_B212 (0170h)

This is the setting for type B-212.

Table 247. ARC_RM_B212 (address 0170h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

178 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B212 are used, else settings will be used from LoadProtocol B212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

176 RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B212 are used, else settings will be used from LoadProtocol B212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 247. ARC_RM_B212 (address 0170h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

174 RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B212 are used, else settings will be used from LoadProtocol B212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

172 RM_RX_ARC_1

170 RM_RX_ARC_0

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B212 are used, else settings will be used from LoadProtocol B212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and

Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.120 ARC_RM_B424 (017Ah)

This is the setting for type B-424.

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Table 248. ARC_RM_B424 (address 017Ah) EEPROM configuration bit description

Address

(hex)

Function Bit Description

182 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

180 RM_RX_ARC_3

17E RM_RX_ARC_2

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

17C RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 248. ARC_RM_B424 (address 017Ah) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

17A RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.121 ARC_RM_B848 (0184h)

This is the setting for type B-848.

Table 249. ARC_RM_B848 (address 0184h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

18C RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B848 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B848 are used, else settings will be used from LoadProtocol B848

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

18A RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B848 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B848 are used, else settings will be used from LoadProtocol B848

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 249. ARC_RM_B848 (address 0184h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

188 RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B848 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B848 are used, else settings will be used from LoadProtocol B848

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

186 RM_RX_ARC_1

184 RM_RX_ARC_0

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_B848 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_B848 are used, else settings will be used from LoadProtocol B848

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and

Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.122 ARC_RM_F212 (018Eh)

This is the setting for type F-212.

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Table 250. ARC_RM_F212 (address 018Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

196 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_F212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_F212 are used, else settings will be used from LoadProtocol F212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

194 RM_RX_ARC_3 15:0

192 RM_RX_ARC_2 15:0

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_F212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_F212 are used, else settings will be used from LoadProtocol F212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_F212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_F212 are used, else settings will be used from LoadProtocol F212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

190 RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_F212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_F212 are used, else settings will be used from LoadProtocol F212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 250. ARC_RM_F212 (address 018Eh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

18E RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.123 ARC_RM_F424 (0198h)

This is the setting for type F-424.

Table 251. ARC_RM_F424 (address 0198h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1A0 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_F424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_F424 are used, else settings will be used from LoadProtocol F424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

19E RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_F424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_F424 are used, else settings will be used from LoadProtocol F424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 251. ARC_RM_F424 (address 0198h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

19C RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_F424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_F424 are used, else settings will be used from LoadProtocol F424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

19A RM_RX_ARC_1 15:0

198 RM_RX_ARC_0 15:0

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_F424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_F424 are used, else settings will be used from LoadProtocol F424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.124 ARC_RM_V_6p6 (01A2h)

This is the setting for type A-106.

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Table 252. ARC_RM_V_6p6 (address 01A2h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1AA RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V6P6 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V6P6 are used, else settings will be used from LoadProtocol V6P6

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1A8 RM_RX_ARC_3 15:0

1A6 RM_RX_ARC_2 15:0

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V6P6 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V6P6 are used, else settings will be used from LoadProtocol V6P6

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V6P6 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V6P6 are used, else settings will be used from LoadProtocol V6P6

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1A4 RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V6P6 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V6P6 are used, else settings will be used from LoadProtocol V6P6

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 252. ARC_RM_V_6p6 (address 01A2h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

1A2 RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.125 ARC_RM_V_26 (01ACh)

This is the setting for type V 26.

Table 253. ARC_RM_V_26 (address 01ACh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1B4 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V26 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V26 are used, else settings will be used from LoadProtocol V26

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1B2 RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V26 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V26 are used, else settings will be used from LoadProtocol V26

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 253. ARC_RM_V_26 (address 01ACh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

1B0 RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V26 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V26 are used, else settings will be used from LoadProtocol V26

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1AE RM_RX_ARC_1 15:0

1AC RM_RX_ARC_0 15:0

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V26 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V26 are used, else settings will be used from LoadProtocol V26

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.126 ARC_RM_V53 (01B6h)

This is the setting for type V53.

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Table 254. ARC_RM_V53(address 01B6h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1BE RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V53 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V53 are used, else settings will be used from LoadProtocol V53

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1BC RM_RX_ARC_3

1BA RM_RX_ARC_2

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V53 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V53 are used, else settings will be used from LoadProtocol V53

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V53 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V53 are used, else settings will be used from LoadProtocol V53

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1B8 RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V53 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V53 are used, else settings will be used from LoadProtocol V53

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 254. ARC_RM_V53(address 01B6h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

1B6 RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.127 ARC_RM_V106 (01C0h)

This is the setting for type V106.

Table 255. ARC_RM_V106(address 01C0h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1C8 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1C6 RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 255. ARC_RM_V106(address 01C0h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

1C4 RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1C2 RM_RX_ARC_1 15:0

1C0 RM_RX_ARC_0 15:0

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings will be used from LoadProtocol A212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.128 ARC_RM_V212 (01CAh)

This is the setting for type V212.

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Table 256. ARC_RM_V212(address 01CAh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1D2 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V212 are used, else settings will be used from LoadProtocol V212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1D0 RM_RX_ARC_3

1CE RM_RX_ARC_2

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V212 are used, else settings will be used from LoadProtocol V212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V212 are used, else settings will be used from LoadProtocol V212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1CC RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_V212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_V212 are used, else settings will be used from LoadProtocol V212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 256. ARC_RM_V212(address 01CAh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

1CA RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.129 ARC_RM_180003m3_SC424_4Man (01D4h)

This is the setting for type 180003m3_SC424_4Man.

Table 257. ARC_RM_180003m3_SC424_4Man (address 01D4h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1DC RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_

4MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_4MAN are used, else settings will be used from LoadProtocol 180003M3_SC424_4MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1DA RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_

4MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_4MAN are used, else settings will be used from LoadProtocol 180003M3_SC424_4MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 257. ARC_RM_180003m3_SC424_4Man (address 01D4h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

1D8 RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_

4MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_4MAN are used, else settings will be used from LoadProtocol 180003M3_SC424_4MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1D6 RM_RX_ARC_1

1D4 RM_RX_ARC_0

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_

4MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_4MAN are used, else settings will be used from LoadProtocol 180003M3_SC424_4MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.130 ARC_RM_180003m3_SC424_2Man (01DEh)

This is the setting for type 180003m3_SC424_2Man.

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Table 258. ARC_RM_180003m3_SC424_2Man (address 01DEh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1E6 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_

2MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_2MAN are used, else settings will be used from LoadProtocol 180003M3_SC424_2MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1E4

1E2

1E0

RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_

2MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_2MAN are used, else settings will be used from LoadProtocol 180003M3_SC424_2MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_

2MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_2MAN are used, else settings will be used from LoadProtocol 180003M3_SC424_2MAN

Bits[14:9] = RFU

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_

2MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_2MAN are used, else settings will be used from LoadProtocol 180003M3_SC424_2MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 258. ARC_RM_180003m3_SC424_2Man (address 01DEh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

1DE RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and

Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.131 ARC_RM_180003m3_SC848_4Man (01E8h)

This is the setting for type 180003m3_SC848_4Man.

Table 259. ARC_RM_180003m3_SC848_4Man (address 01E8h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1F0 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_

4MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_4MAN are used, else settings will be used from LoadProtocol 180003M3_SC848_4MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1EE RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_

4MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_4MAN are used, else settings will be used from LoadProtocol 180003M3_SC848_4MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 259. ARC_RM_180003m3_SC848_4Man (address 01E8h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

1EC RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_

4MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_4MAN are used, else settings will be used from LoadProtocol 180003M3_SC848_4MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1EA RM_RX_ARC_1 15:0

1E8 RM_RX_ARC_0 15:0

Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_

4MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_4MAN are used, else settings will be used from LoadProtocol 180003M3_SC848_4MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.132 ARC_RM_180003m3_SC848_2Man (01F2h)

This is the setting for type 180003m3_SC848_2Man.

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Table 260. ARC_RM_180003m3_SC848_2Man (address 01F2h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1FA RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_

2MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_2MAN are used, else settings will be used from LoadProtocol 180003M3_SC848_2MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1F8 RM_RX_ARC_3

1F6

1F4

RM_RX_ARC_2

RM_RX_ARC_1

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_

2MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_2MAN are used, else settings will be used from LoadProtocol 180003M3_SC848_2MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_

2MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_2MAN are used, else settings will be used from LoadProtocol 180003M3_SC848_2MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_

2MAN are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_2MAN are used, else settings will be used from LoadProtocol 180003M3_SC848_2MAN

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 260. ARC_RM_180003m3_SC848_2Man (address 01F2h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

1F2 RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and

Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.133 ARC_RM_AI106 (01FCh)

This is the setting for type AI106.

Table 261. ARC_RM_AI106 (address 01FCh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

204 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI106 are used, else settings will be used from LoadProtocol AI106

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

202 RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI106 are used, else settings will be used from LoadProtocol AI106

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 261. ARC_RM_AI106 (address 01FCh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

200 RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI106 are used, else settings will be used from LoadProtocol AI106

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

1FE RM_RX_ARC_1

1FC RM_RX_ARC_0

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI106 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI106 are used, else settings will be used from LoadProtocol AI106

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.134 ARC_RM_AI212 (0206h)

This is the setting for type AI212.

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Table 262. ARC_RM_AI212 (0206h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

20E RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI212 are used, else settings will be used from LoadProtocol AI212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

20C RM_RX_ARC_3

20A RM_RX_ARC_2

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI212 are used, else settings will be used from LoadProtocol AI212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI212 are used, else settings will be used from LoadProtocol AI212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

208 RM_RX_ARC_1 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI212 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI212 are used, else settings will be used from LoadProtocol AI212

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 262. ARC_RM_AI212 (0206h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

206 RM_RX_ARC_0 15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.135 ARC_RM_AI424 (0210h)

This is the setting for type AI424.

Table 263. ARC_RM_AI424 (0210h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

218 RM_RX_ARC_4 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI424 are used, else settings will be used from LoadProtocol AI424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

216 RM_RX_ARC_3 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI424 are used, else settings will be used from LoadProtocol AI424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

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Table 263. ARC_RM_AI424 (0210h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

214 RM_RX_ARC_2 15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI424 are used, else settings will be used from LoadProtocol AI424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

212 RM_RX_ARC_1

210 RM_RX_ARC_0

15:0 Bit[15]

0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI424 are used

1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI424 are used, else settings will be used from LoadProtocol AI424

Bits[14:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]

0: ARC settings always apply

1: ARC settings applicable during FDT and DPC change

Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and

Baudrate

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.

9.24.136 RF_DEBOUNCE_TIMEOUT (02B2h)

Table 264. RF_DEBOUNCE_TIMEOUT (address 02B2h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2B2 DEBOUNCE_

TIMEOUT

7:0 Timeout used after the RF detection during the AUTOCOLL to detect if there is a glitch or continuous RF

Value is entered in micro seconds, each bit represents 1 micro second

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9.24.137 SENSE_RES (02B3h)

Table 265. SENSE_RES (address 02B3) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2B3 AUTOCOLL configuration

16:0 ATQA in order byte 0, byte 1

16:8

7:0

Byte1

Byte0

9.24.138 NFC_ID1 (02B5h)

Table 266. SIGNAL_SCALING_CONFIG (address 2B5h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2B5 AUTOCOLL configuration

If Random UID is disabled (EEPROM address 0x2CB), the content of these addresses is used to generate a Fixed UID.

The order is byte 0, Byte 1, Byte 2; Byte3 - which is the first NFCID1 byte - is fixed to

08h, the check byte is calculated automatically

23:16 Byte2

15:8 Byte1:

7:0 Byte0:

9.24.139 SEL_RES (02B8h)

Table 267. SEL_RES (address 2B8h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2B8 AUTOCOLL configuration

7:0 Response to Select: SAK

9.24.140 FELICA_POLL_RES (02B9h)

The FeliCa response is configured by 18 bytes.

Table 268. FELICA_POLL_RES (address 02B9) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2B9 AUTOCOLL configuration

15:0 FeliCa Polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad

+ 2 bytes system code)

47:0

63:0

NFCID2

PAD

15:0 system code

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9.24.141 RANDOM_UID_ENABLE (02CBh)

Table 269. RANDOM_UID_ENABLE (address 2CBh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2CB RFU

Random UID

Enable

7:1

0: Use UID stored in EEPROM

1: Randomly generate the UID in which the first byte is fixed and the remaining 3 bytes are random

A new random number is generated after each RF-OFF to RF-ON.

9.24.142 MFC_AUTH_TIMEOUT (02CCh)

Table 270. MFC_AUTH_TIMEOUT (address 2CCh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2CC RFU 15:0 Timeout value in micro seconds used for Auth1 & Auth2 stages during MIFARE

Classic Authenticate

9.24.143 RSSI_TIMER (02DAh)

Configuration for Card Emulation mode only.

Table 271. RSSI_TIMER (address 2DAh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2DA RSSI_TIMER 15:0 Default: 423

9.24.144 RSSI_TIMER_FIRST_PERIOD (02DCh)

Table 272. RSSI_TIMER_FIRST_PERIOD (address 2DCh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2DC RSSI 15:0 First period duration after Rffield ON. Unit is 128/fc (106 kHz) if set to 0 it means that feature is not used 0D2 => ~2 ms

9.24.145 RSSI_CTRL_00_AB (02DEh)

Table 273. RSSI_CTRL_00_AB (address 2DEh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2DE RSSI 7:6 Bits [6:7] = RFU

5:0 Bits [0:5] = (APC_ID_REF_AB) ID of APC_TX entry that is equiv to RSSI = 0 (for Type

AB)

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9.24.146 RSSI_NB_ENTRIES_AB (02DFh)

Table 274. RSSI_NB_ENTRIES_AB (address 2DFh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2DF RSSI 7:5 RFU

4:0 For Initial RF ON, CEA and CEB

Number of entries in RSSI lookup table (it refers to dwRssiEntryAB_01 to dwRssiEntryAB_X);

9.24.147 RSSI_THRESHOLD_PHASE_TABLE (02E0h)

Table 275. RSSI_THRESHOLD_PHASE_TABLE (address 2E0h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

2E0 wRssiThresholdF_01 15:0 bit[0:12] - RSSI Value bit[13:15] - RFU Note: dwRssiEntryAB_00 = 0 (not in EEPROM) Signed phase compensation with 1/4 degree resolution: 16 bits signed value (using complement of 2)

2E2 ArbPhaseF_01 15:0 wArbPhaseF_xx: Signed phase compensation with 1/4 degree resolution: 16 bits signed value (using complement of 2)

RssiThresholdF_02 15:0

ArbPhaseF_02 15:0

RssiThresholdF_03 15:0

ArbPhaseF_03 15:0

RssiThresholdF_04 15:0

ArbPhaseF_04 15:0

RssiThresholdF_05 15:0

ArbPhaseF_05 15:0

RssiThresholdF_06 15:0

ArbPhaseF_06 15:0

RssiThresholdF_07 15:0

ArbPhaseF_07 15:0

RssiThresholdF_08 15:0

ArbPhaseF_08 15:0

RssiThresholdF_09 15:0

ArbPhaseF_09 15:0

RssiThresholdF_0A 15:0

ArbPhaseF_0A 15:0

RssiThresholdF_0B 15:0

ArbPhaseF_0B 15:0

RssiThresholdF_0C 15:0

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Table 275. RSSI_THRESHOLD_PHASE_TABLE (address 2E0h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

ArbPhaseF_0C 15:0

RssiThresholdF_0D 15:0

ArbPhaseF_0D 15:0

RssiThresholdF_0E 15:0

ArbPhaseF_0E 15:0

RssiThresholdF_0F 15:0

ArbPhaseF_0F 15:0

RssiThresholdF_10 15:0

ArbPhaseF_10 15:0

RssiThresholdF_11 15:0

ArbPhaseF_11 15:0

RssiThresholdF_12 15:0

ArbPhaseF_12 15:0

RssiThresholdF_13 15:0

ArbPhaseF_13 15:0

RssiThresholdF_14 15:0

ArbPhaseF_14 15:0

RssiThresholdF_15 15:0

ArbPhaseF_15 15:0

RssiThresholdF_16 15:0

ArbPhaseF_16 15:0

RssiThresholdF_17 15:0

ArbPhaseF_17 15:0

RssiThresholdF_18 15:0

ArbPhaseF_18 15:0

9.24.148 TX_PARAM_ENTRY_TABLE (03A2h)

Table 276. TX_PARAM_ENTRY_TABLE (address 3A2h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

3A2 TxParamEntry_00_ID 7 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

5:0

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

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Table 276. TX_PARAM_ENTRY_TABLE (address 3A2h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description bTxParamEntry_00_Tx1 7:6 RFU

5:0 bTxParamEntry_00_Tx2 7:0

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2

3A5 TxParamEntry_01_ID 7

6 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

3A8 bTxParamEntry_02_Tx2 7:0

3AB TxParamEntry_03_ID 7

3AE

5:0 bTxParamEntry_01_Tx1 7:6

5:0 bTxParamEntry_01_Tx2 7:0

TxParamEntry_02_ID 7

5:0 bTxParamEntry_02_Tx1 7:6

5:0

5:0 bTxParamEntry_03_Tx1 7:6

5:0 bTxParamEntry_03_Tx2 7:0

TxParamEntry_04_ID 7

5:0

RFU

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

RFU

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

RFU

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

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Table 276. TX_PARAM_ENTRY_TABLE (address 3A2h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description bTxParamEntry_04_Tx1 7:6 RFU

5:0 bTxParamEntry_04_Tx2 7:0

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2

3B1 TxParamEntry_05_ID 7

6 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

3B4

3B7

3BA

5:0 bTxParamEntry_05_Tx1 7:6

5:0 bTxParamEntry_05_Tx2 7:0

TxParamEntry_06_ID 7

5:0 bTxParamEntry_06_Tx1 7:6

5:0 bTxParamEntry_06_Tx2 7:0

TxParamEntry_07_ID 7

5:0 bTxParamEntry_07_Tx1 7:6

5:0 bTxParamEntry_07_Tx2 7:0

TxParamEntry_08_ID 7

5:0

RFU

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

RFU

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

RFU

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

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Table 276. TX_PARAM_ENTRY_TABLE (address 3A2h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description bTxParamEntry_08_Tx1 7:6 RFU

5:0 bTxParamEntry_08_Tx2 7:0

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2

3BD TxParamEntry_09_ID 7

6 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

5:0 bTxParamEntry_09_Tx1 7:6

5:0 bTxParamEntry_09_Tx2 7:0

3C1 TxParamEntry_0A_ID 7

5:0 bTxParamEntry_0A_Tx1 7:6

5:0 bTxParamEntry_0A_Tx2 7:0

3C3 TxParamEntry_0B_ID 7

5:0 bTxParamEntry_0B_Tx1 7:6

5:0 bTxParamEntry_0B_Tx2 7:0

RFU

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

RFU

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2 bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):

0 - Dual driver,

1 - Single driver

BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):

0 - Disabled,

1 - Enabled

RFU

PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V

Scaling factor for TX1 and TX2

9.24.149 LPCD_AVG_SAMPLES (0492h)

Configuration for the Switch mode LPCD

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Table 277. LPCD_AVG_SAMPLES (address 0492h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

492 LPCD setting 7 Defining how many samples of the I and Q values are used for the averaging.

Average of samples in power of 2

0->1 sample

1->2 samples

2->4 samples

3->8 samples

4->16 samples

5-> 32 samples

9.24.150 LPCD_RSSI_TARGET (0494h)

Table 278. LPCD_RSSI_TARGET (address 0494h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

494 LPCD setting 7 Value to be set in register DGRM_RSSI_REG_DGRM_RSSI_TARGET

Typically the same values from the Type A106 LOAD_RF_CONFIGURATION(0x0D)

(DGRM_RSSI register) are used

9.24.151 LPCD_RSSI_HYST (0496h)

Table 279. LPCD_RSSI_HYST (address 0496h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

496 LPCD setting 7 Value to be set in CLIF_DGRM_RSSI_REG_DGRM_RSSI_HYST

Typically the same values from the Type A106 LOAD_RF_CONFIGURATION(0x0D)

(DGRM_RSSI register) are used

9.24.152 LPCD_CONFIG (0497h)

Table 280. LPCD_CONFIG (address 0497h) EEPROM configuration register bit description

Address

(hex)

Function Bit Description

49B RFU 15:6

Immediate RF OFF before TXLDO shutdown to save power 0 - Disable 1 - Enable

Acquisition channels:

2:0

VDDPA fast discharge 0 - Disable 1 - Enable

TX Drivers 0 - Enable Single driver 1 - Enable both drivers

0:1 = RFU

2 = Magnitude

3 = I and Q

4 =M, I and Q

5:7 = RFU

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9.24.153 LPCD_THRESHOLD_COARSE (049Ah)

Table 281. LPCD_THRESHOLD_COARSE (address 049Ah) EEPROM configuration bit description

Address

(hex)

Function Bit Description

49E LPCD Q channel threshold

LPCD I channel threshold

31:16

0:15

ADC LSB granularity of threshold depends on avg_samples_meas value

5: unit 1/32;

4: unit 1/16;

3: unit 1/8;

2: unit 1/4;

1: unit 1/2;

0: unit 1

ADC LSB granularity of threshold depends on avg_samples_meas value

5: unit 1/32;

4: unit 1/16;

3: unit 1/8;

2: unit 1/4;

1: unit 1/2;

0: unit 1

Note: If the difference between the measured value and the reference is greater than the threshold on either channels, then a card is detected.

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9.24.154 LPCD_VDDPA (04B5h)

Table 282. LPCD_VDDPA (address 04B5h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

4B5 VDDPA voltage during LPCD when DC-DC

(internal or external) or external power source is used to feed TXLDO

7:0 TXLDO output voltage:

0x00: 1V50

0x01: 1V60

0x02: 1V70

0x03: 1V80

0x04: 1V90

0x05: 2V00

0x06: 2V10

0x07: 2V20

0x08: 2V30

0x09: 2V40

0x0A: 2V50

0x0B: 2V60

0x0C: 2V70

0x0D: 2V80

0x0E: 2V90

0x0F: 3V00

0X10: 3V10

0x11: 3V20

0x12: 3V30

0x13: 3V40

0x14: 3V50

0x15: 3V60

0x16: 3V70

0x17: 3V80

0x18: 3V90

0x19: 4V00

0x1A: 4V10

0x1B: 4V20

0x1C: 4V30

0x1D: 4V40

0x1E: 4V50

0x1F: 4V60

0x20: 4V70

0x21: 4V80

0x22: 4V90

0x23: 5V00

0x24: 5V10

0x25: 5V20

0x26: 5V30

0x27: 5V40

0x28: 5V50

0x29: 5V60

0x2A: 5V70

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9.24.155 ULPCD_VDDPA_CTRL (04BFh)

Table 283. ULPCD_VDDPA_CTRL (address 4BFh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

RFU

LDO_VDDPA_

VOUT_SEL

15:9 -

3-8 TXLDO output voltage during ULPCD polling

VDDPA_1V50 /* 0x00 */

VDDPA_1V60, /* 0x01 */

VDDPA_1V70, /* 0x02 */

VDDPA_1V80, /* 0x03 */

VDDPA_1V90, /* 0x04 */

VDDPA_2V00, /* 0x05 */

VDDPA_2V10, /* 0x06 */

VDDPA_2V20, /* 0x07 */

VDDPA_2V30, /* 0x08 */

VDDPA_2V40, /* 0x09 */

VDDPA_2V50, /* 0x0A */

VDDPA_2V60, /* 0x0B */

VDDPA_2V70, /* 0x0C */

VDDPA_2V80, /* 0x0D */

VDDPA_2V90, /* 0x0E */

VDDPA_3V00, /* 0x0F */

VDDPA_3V10, /* 0x10 */

VDDPA_3V20, /* 0x11 */

VDDPA_3V30, /* 0x12 */

VDDPA_3V40, /* 0x13 */

VDDPA_3V50, /* 0x14 */

VDDPA_3V60, /* 0x15 */

VDDPA_3V70, /* 0x16 */

VDDPA_3V80, /* 0x17 */

VDDPA_3V90, /* 0x18 */

VDDPA_4V00, /* 0x19 */

VDDPA_4V10, /* 0x1A */

VDDPA_4V20, /* 0x1B */

VDDPA_4V30, /* 0x1C */

VDDPA_4V40, /* 0x1D */

VDDPA_4V50, /* 0x1E */

VDDPA_4V60, /* 0x1F */

VDDPA_4V70, /* 0x20 */

VDDPA_4V80, /* 0x21 */

VDDPA_4V90, /* 0x22 */

VDDPA_5V00, /* 0x23 */

VDDPA_5V10, /* 0x24 */

VDDPA_5V20, /* 0x25 */

VDDPA_5V30, /* 0x26 */

VDDPA_5V40, /* 0x27 */

VDDPA_5V50, /* 0x28 */

VDDPA_5V60, /* 0x29 */

VDDPA_5V70, /* 0x2A */

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Table 283. ULPCD_VDDPA_CTRL (address 4BFh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

4BF RFU 2:0 -

9.24.156 ULPCD_TIMING_CTRL (04C2h)

Table 284. ULPCD_TIMING_CTRL (address 4C2h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

4C2 RFON_GUARD_

TIME

7:4 RFON guard time: (RFON_GUARD_TIME + 2) * LFO-Freq (380 kHz)

Guard time: Time between RF-ON and first sampling of data

RFU 3:0 -

9.24.157 ULPCD_VOLTAGE_CTRL (04C6h)

Table 285. ULPCD_VOLTAGE_CTRL (address 4C6h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

4C6 ULPCD configuration

7:5 RFU

4:2 RFU

1 TX_SUPPLY by VUP_TX

0: VUP externally supplied (2.8 V to 6.0 V)

1: VUP supplied by PN5190B1 itself (pin VUP_TX connected to VBAT/VBATPWR)

0 RFU

9.24.158 ULPCD_RSSI_GUARD_TIME (04C9h)

Table 286. ULPCD_RSSI_GUARD_TIME (address 4C9h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

4C9 ULPCD RSSI sampling guard time

15 RFU

14:0 This is the time between consecutive RSSI samples:

Range: 0 - 127 in micro seconds

9.24.159 ULPCD_RSSI_SAMPLE_CFG (04CAh)

Table 287. ULPCD_RSSI_SAMPLE_CFG (address 4CAh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

4CA ULPCD configuration

15:0 Number of RSSI Samples which are internally averaged:

0: 4 samples,

1: 8 samples

2: 16 samples

3: 32 samples

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9.24.160 ULPCD_THRESH_LVL(04CBh)

Table 288. ULPCD_THRESH_LVL (address 4CBh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

4CB ULPCD configuration

15:0 RSSI Threshold level Range 0 - 31

If the difference between the measured RSSI value and the reference (which is derived during calibration) is greater than the threshold, then a card is detected.

9.24.161 ULPCD_GPIO3 (04CCh)

Table 289. ULPCD_GPIO3 (address 4CCh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

4CC RFU 7:1 -

4CC ULPCD GPIO3 configuration

0 GPIO3 abort polarity configuration. If PN5190B1 is using the ULPCD, GPIO3 cannot be used for any other purpose than aborting the ULPCD.

1: high-level abort ULPCD

0: low-level abort ULPCD

9.24.162 TXIRQ_GuardTime (0559h)

Table 290. FELICA_POLL_RES (address 0559) EEPROM configuration bit description

Address

(hex)

Function Bit Description

559 TXIRQ_

GuardTime

31:0 0 - Disabled

0x1-0xFFFFF (Enabled - 1 unit corresponds to 1 us) Maximum timeout of 1.048 s

9.24.163 FDT_default_val (055Dh)

Table 291. FDT_default_val (address 055D) EEPROM configuration bit description

Address

(hex)

Function Bit Description

55D FDT_default_val 31:0 0x00 - Disabled others - enabled (1 unit is 18.86us) Default fixed to 5.5 secs

9.24.164 RXIRQ_GuardTime (0561h)

Table 292. RXIRQ_GuardTime (address 0561h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

55D RXIRQ_

GuardTime

31:0 0x00 Disabled

0x1-0xFFFFF (Enabled - 1 unit corresponds to 1 us) Maximum timeout of 1.048 s

Default value = 0xF4240 (1 s)

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9.24.165 NFCLD_RFLD_Valid (006D3h)

Table 293. NFCLD_RFLD_Valid (address 06D3h) EEPROM configuration register bit description

Address

(hex)

Function Bit Description

6D3 RFU

RFLD_

CALIBRATE

7:1 -

0 This bit allows to calibrate the RFLD / NFCLD.

This calibration is required only once in the lifetime of the chip for increased RFLD /

NFCLD accuracy, independent from the value of this bit (0 or 1).

Clearing this bit (0) will calibrate the RFLD /RFLD during the next boot-up, precondition for the proper calibration is an unloaded condition and no external field applied.

After calibration this bit is set (1) and indicates that the RFLD /RFLD Threshold is a valid data.

9.24.166 CurrentSensorTrimConfig (0ABCh)

Table 294. CurrentSensorTrimConfig (address 0CACh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

ABC RFU 7:1 -

Current_Sensor_

Calib_Bypass

0 1: current sensor calibration offset is used by DPC;

0: Current sensor calibration offset is bypassed by DPC

Note: The default value should only be modified for debug purpose.

9.24.167 CORRECTION_ENTRY_TABLE (0BDAh)

Table 295. CORRECTION_ENTRY_TABLE (address 0BDAh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

0BDA sCorrection_Entry0 15:0 The correction that is applied when lookup table based shaping with scaling is enabled.

Range is -128 to +127, sCorrection_Entry0 corresponds to correction applied at VDDPA =

1V5,

Correction_Entry42 corresponds to correction applied at VDDPA =

5V7

For each entry:

BYTE 0: Bits[7:0] = define the correction which is applied for

ASK100

BYTE 1: Bits[15:8] = define the correction which is applied for

ASK10

BAF sCorrection_Entry1

BB1 sCorrection_Entry2

15:0

BB3 sCorrection_Entry3

BB5 sCorrection_Entry4

15:0

BB7 sCorrection_Entry5 15:0

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Table 295. CORRECTION_ENTRY_TABLE (address 0BDAh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

BB9 sCorrection_Entry6 15:0

BBB sCorrection_Entry7

BBD sCorrection_Entry8

15:0

BBF sCorrection_Entry9

BC1 sCorrection_Entry10

BC3 sCorrection_Entry11

BC5 sCorrection_Entry12

BC7 sCorrection_Entry13

15:0

BC9 sCorrection_Entry14

BCB sCorrection_Entry15

BCD sCorrection_Entry16

BCF sCorrection_Entry17

BD1 sCorrection_Entry18

BD3 sCorrection_Entry19

BD5 sCorrection_Entry20

BD7 sCorrection_Entry21

BD9 sCorrection_Entry22

BDB sCorrection_Entry23

15:0

BDD sCorrection_Entry24

BDF sCorrection_Entry25

BE1 sCorrection_Entry26

BE3 sCorrection_Entry27

BE5 sCorrection_Entry28

BE7 sCorrection_Entry29

BE9 sCorrection_Entry30

BEB sCorrection_Entry31

BED sCorrection_Entry32

BEF sCorrection_Entry33

BF1 sCorrection_Entry34

BF3 sCorrection_Entry35

BF5 sCorrection_Entry36

BF7 sCorrection_Entry37

BF9 sCorrection_Entry38

BFB sCorrection_Entry39

BFD sCorrection_Entry40

BFF sCorrection_Entry41

15:0

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Table 295. CORRECTION_ENTRY_TABLE (address 0BDAh) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

C01 sCorrection_Entry42 15:0

9.24.168 RTRANS_FTRANS_TABLE (0C03h)

Table 296. RTRANS_FTRANS_TABLE (address C03h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

C03 RTRANS0 31:0 These values apply in case EDGE_STYLE = 0 is configured for the rising edge

C07 RTRANS1 31:0 These values apply in case EDGE_STYLE = 0 is configured for the rising edge

C0B RTRANS2

C0F RTRANS3

C13 FTRANS0

C17 FTRANS1

C1B FTRANS2

31:0 These values apply in case EDGE_STYLE = 0 is configured for the rising edge

31:0 These values apply in case EDGE_STYLE = 0 is configured for the falling edge

C1F FTRANS3

C23 RTRANS0

C27 RTRANS1

C2B RTRANS2

C2F RTRANS03

C33 FTRANS0

C37 FTRANS1

C3B FTRANS2

C3F FTRANS3

C43 RTRANS0

31:0 These values apply in case EDGE_STYLE = 0 is configured for the falling edge

31:0 These values apply in case EDGE_STYLE = 1 is configured for the rising edge

31:0 These values apply in case EDGE_STYLE = 1 is configured for the falling edge

31:0 These values apply in case EDGE_STYLE = 2 is configured for the rising edge

C47 RTRANS1

C4B RTRANS2

C4F RTRANS03

C53 FTRANS0

C57 FTRANS1

C5B FTRANS2

C5F FTRANS3

C63 RTRANS0

C67 RTRANS1

C6B RTRANS2

C6F RTRANS03

C73 FTRANS0

C77 FTRANS1

31:0 These values apply in case EDGE_STYLE = 2 is configured for the rising edge

31:0 These values apply in case EDGE_STYLE = 2 is configured for the falling edge

31:0 These values apply in case EDGE_STYLE = 3 is configured for the rising edge

31:0 These values apply in case EDGE_STYLE = 3 is configured for the falling edge

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Table 296. RTRANS_FTRANS_TABLE (address C03h) EEPROM configuration bit description

...continued

Address

(hex)

Function Bit Description

C7B FTRANS2 31:0 These values apply in case EDGE_STYLE = 3 is configured for the falling edge

C7F FTRANS3 31:0 These values apply in case EDGE_STYLE = 3 is configured for the falling edge

This table applies only, if the transmitter shaping configuration is (EDGE_TYPE_xx) 4, 5, or 6.

Which of the entries RTRANS0..3 (rising transition) / FTRANS0..3 (falling transition) is applied, is defined by the EDGE_STYLE.

9.24.169 CFG_NOV_CAL (0C83h)

TX non-overlap feature - defines the non-overlap time of TX1, TX2.

Table 297. CFG_NOV_CAL (address 0083h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1 RFU 7:2 -

CALIBRATION_

TYPE

1:0 00 = No calibration performed, needs to be updated to 01 or 10 before the first RF on of the chip is performed

01 = Enable FW calibration after every cold boot

10 = Use calibration value coming from EEPROM NOV_CAL_VAL1, NOV_CAL_VAL2 (D efault)

11 = RFU

9.24.170 NOV_CAL_VAL1 (0C84h)

Table 298. NOV_CAL_VAL1 (address 0C84h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1 VddpaCalVal1 7 It defines the VDDPA value that FW will use to perform NOV calibration group #1.

value = 03h (1.8 V) value = 0Dh (2.8 V)

See "TxLdoVddpaHigh" parameter for list of voltage

9.24.171 NOV_CAL_VAL2 (0C85h)

Table 299. NOV_CAL_VAL2 (0C85h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1 VddpaCalVal2 7 It defines the VDDPA value that FW will use to perform NOV calibration group #2.

default value = 15h (3.6 V) default value = 24h (5.1 V)

See "TxLdoVddpaHigh" parameter for list of voltage

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9.24.172 NOV_CAL_THRESHOLD (0C86h)

Table 300. NOV_CAL_THRESHOLD (address 0C86h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1 CfgThreshold 7 It defines VDDPA threshold that FW will use to select Group #1 or Group #2 NOV offset values.

default value = 08h (2.3 V) default value = 16h (3.7 V)

See "TxLdoVddpaHigh" parameter for list of voltage

9.24.173 NOV_CAL_OFFSET1 (0C87h)

Table 301. NOV_CAL_OFFSET1 (address 0C87h) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1 UserOffsets1 7 It defines user static offsets applied if CfgNovCal[1:0] = 10b bits[04:00] Group #2 (CfgThreshold to VDDPA max), offset_3l bits[12:08] Group #2 (CfgThreshold to VDDPA max), offset_3l_p2 bits[20:16] Group #2 (CfgThreshold to VDDPA max), offset_2l<0> bits[28:24] Group #2 (CfgThreshold to VDDPA max), offset_2l<1>

9.24.174 NOV_CAL_OFFSET2 (0C8Bh)

Table 302. NOV_CAL_OFFSET1 (address 0C8Bh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

1 UserOffsets2 7 It defines user static offsets applied if CfgNovCal[1:0] = 10b bits[04:00] Group #2 (CfgThreshold to VDDPA max), offset_3l bits[12:08] Group #2 (CfgThreshold to VDDPA max), offset_3l_p2 bits[20:16] Group #2 (CfgThreshold to VDDPA max), offset_2l<0> bits[28:24] Group #2 (CfgThreshold to VDDPA max), offset_2l<1>

9.24.175 VDDPA_DISCHARGE (0C8Fh)

Table 303. VDDPA_DISCHARGE (address 0C8Fh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

C8F RFU

EnableFastVDDP

ADischarge

7:1 RFU

0 1 - Enables fast discharge of VDDPA by setting VDDPA=5.7 and then to 1.5 V, during RF

OFF

0 - Enables fast discharge of VDDPA by setting VDDPA=5.7 and then to 1.5 V, during RF

OFF

9.24.176 ARC_RM_A106_FDT (0C9Dh)

This is the setting for type A-106.

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Table 304. ARC_RM_A106_FDT (address 0C9Dh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

CA5 RM_RX_ARC_

FDT_4

15:0 Bit[15]: RFU

Bit [14]: Has to be always "0"

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

CA3 RM_RX_ARC_

FDT_3

CA1 RM_RX_ARC_

FDT_2

15:0 Bit[15]: RFU

Bit [14]: Has to be always "0"

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]: RFU

Bit [14]: Has to be always "0"

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

C9F RM_RX_ARC_

FDT_1

C9D RM_RX_ARC_

FDT_0

15:0 Bit[15]: RFU

Bit [14]: Has to be always "0"

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

15:0 Bit[15]: RFU

Bit [14]: Has to be always "0"

Bits[13:10] = RFU

Bit [9] = Enable the IIR filter.

Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register, applies as soon as the ARC is enabled)

Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the

DGRM_RSSI register, applies as soon as the ARC is enabled)

Note: For ISO14443-A: In case ARC is disabled, it requires DPC_

SIGNAL_DETECT_TH_OVR_VAL larger than 0x50 (with MF_GAIN = 2 (default))

Note: For ISO14443-A: In case Bit[15] is configured to 0, it requires DPC_

SIGNAL_DETECT_TH_OVR_VAL larger than 0x50 (with MF_GAIN = 2 (default)) if the

ARC is enabled.

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Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can be used to limit the LMA sensitivity of the RX.

9.24.177 Tx_Symbol23_Mod_Reg_BR_53 (0CC5h)

Table 305. Tx_Symbol23_Mod_Reg_BR_53 (0CC5Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

CC5 15693_BR_CFG 31:0 CLIF_TX_SYMBOL23_MOD_REG value loaded for 15693 BR 53 kbit/s

9.24.178 Tx_Data_Mod_Reg_BR_53 (0CC9h)

Table 306. Tx_Data_Mod_Reg_BR_53 (0CC9Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

CC9 15693_BR_CFG 31:0 CLIF_TX_Data_MOD_REG value loaded for 15693 BR 53 kbit/s

9.24.179 Tx_Symbol23_Mod_Reg_BR_106 (0CCDh)

Table 307. Tx_Symbol23_Mod_Reg_BR_106 (0CCDEh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

CCD 15693_BR_CFG 31:0 CLIF_TX_Symbol23_MOD_REG value loaded for 15693 BR 106 kbit/s

9.24.180 Tx_Data_Mod_Reg_BR_106 (0CD1h)

Table 308. Tx_Data_Mod_Reg_BR_106 (0CD1Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

CD1 15693_BR_CFG 31:0 CLIF_TX_Data_MOD_REG value loaded for 15693 BR 106 kbit/s

9.24.181 Tx_Symbol23_Mod_Reg_BR_212 (0CD5h)

Table 309. Tx_Symbol23_Mod_Reg_BR_212 (0CD5Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

CD5 15693_BR_CFG 31:0 CLIF_TX_Symbol23_MOD_REG value loaded for 15693 BR 212 kbit/s

9.24.182 Tx_Data_Mod_Reg_BR_212 (0CD9h)

Table 310. Tx_Data_Mod_Reg_BR_212 (0CD9Eh) EEPROM configuration bit description

Address

(hex)

Function Bit Description

CD9 15693_BR_CFG 31:0 CLIF_TX_Data_MOD_REG value loaded for 15693 BR 212 kbit/s

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10 Limiting values

Table 311. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

DD(VUP_TX)

DD(VBAT)

DD(VDDIO)

Parameter supply voltage on pin VUP_TX -

Conditions supply voltage on pin VBAT supply voltage on pin VDDIO

on pin VDDIO, power supply for host interface and GPIOs

DD(VDDPA)

T i(RXP) i(RXN)

ESD j(max)

T stg supply voltage on pin VDDPA maximum limiting values for

DD(VDDPA)

and T j(max)

not violated input voltage on pin RXP input voltage on pin RXN electrostatic discharge voltage junction temperature -

human body model (HBM)

[1]

charge device model (CDM)

[2]

storage temperature no supply voltage applied

Min

-0.3

Max

5.8

3.8

6.0

-0.3

+ 2.0

-2000 2000 V

-500 +500 V

125 °C

-55 +150 °C

Unit

[1] According to ANSI/ESDA/JEDEC JS-001

[2] According to ANSI/ESDA/JEDEC JS-002

Stress above one or more of the limiting values may cause permanent damage to the device or limit the lifetime.

Product might not behave according to specification.

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11 Characteristics

This chapter describes the electrical characteristics for the usage of the product.

Functionality according to this specification and compliancy to referred standards is guaranteed if the device is operated within the limits.

For further information, refer to the PQP (product qualification package) which summarizes the results of the characterization and qualification performed.

11.1 Thermal characteristics

Table 312. Operating conditions

Symbol Parameter

T amb ambient operating temperature

Typ

+25

Max

+85

Unit

°C

Conditions in still air with exposed pins soldered on a 4 layer JEDEC PCB, transmitter output current up to 350 mA depends on operating condition: Supply voltage, without DC-

DC, Transmitter current

Min

-40

-40 +25 +105 °C

Table 313. Thermal characteristics HVQFN40 package

Symbol

R th(j-a)

Parameter Conditions thermal resistance from junction to ambient in free air with exposed pad soldered on a 4 layer JEDEC

PCB, package HVQFN40

R th(j-c) thermal resistance from junction to case -

Typ

44.2

24.2

Unit

K/W

Table 314. Thermal characteristics VFBGA64 package

Symbol

R th(j-a) th(j-c)

Parameter Conditions thermal resistance from junction to ambient in free air with exposed pad soldered on a 4 layer JEDEC

PCB, package VFBGA64 thermal resistance from junction to case -

Typ

Unit

K/W

Table 315. Junction Temperature

Symbol Parameter

T j_max maximum junction temperature -

Conditions

Min Max

+125

Unit

°C

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Table 316. Thermal Shutdown Temperature

Symbol Parameter

T shutdown shutdown of chip due to high temperature detected by temp sensor

11.2 Static characteristics

Conditions Typ

125

Unit

°C

Table 317. Supply voltage

Symbol Parameter

DD(VBAT_PWR) supply voltage on pin VBAT_PWR

(DC-DC input pin)

DD(VUP_TX) supply voltage on pin VUP_TX

(TX_LDO input pin)

Conditions

DC-DC disabled

DC-DC enabled

Remark: If DC-DC is used, its output

DD(BOOST)

Min is limited to 3.1 V

Min

2.4

2.8

2.4

Typ Max

5.5

4.8

6.0

Unit

DD(VDDPA)

DD(VBAT)

DD(VDDIO)

I(RXP)

I(RXN) supply voltage on pin VDDPA

(input of the transmitter power amplifier) supply voltage on pin VBAT

(analog and digital supply) supply voltage on pin VDDIO

(supply for host interface and

GPIOs) input voltage on pin RXP input voltage on pin RXN

VBAT >= VDDIO

1.5

2.4

typical 1.8 V interface supply voltage typical 3.3 V interface supply voltage

1.62

2.4

-0.5

5.7

5.5

1.98

3.6

1.8

Note: The voltage on pin VDDIO must always be smaller or equal to the voltage on pin

VBAT.

Table 318. Current consumption in active mode

Symbol Parameter Conditions

DD(VBAT)

DD(VDDIO) system supply

DD(BOOST_IN)

DC-DC boost supply

This current depends on the output current of peripherals. At no time, the sum of the maximum output currents shall exceed

DD(VDDIO)

max average input current peak input current

(short peak)

DD(VUP_TX) input supply for transmitter

LDO

DD(VDDPA)

RF power amplifier

(transmitter) current supplied via VUP_TX

(TX_LDO active)

Min

Typ Max

1.0

1.7

350

Unit mA mA mA mA

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Table 318. Current consumption in active mode

...continued

Symbol Parameter Conditions supplied without DC-DC and TXLDO active

Min

Typ Max

400

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Unit mA

Table 319. Current consumption during power-saving modes

Symbol Parameter Conditions

OFF Plus Mode

(VDDIO+VBAT) sum of supply current on pin

VDDIO and VBAT in OFF

Plus mode

25 °C ambient operating temperature

OFF Plus ULFO Mode

(VDDIO+VBAT)

25 °C ambient operating temperature

I hard power down

(VDDIO+VBAT) sum of supply current on pin

VDDIO and VBAT in OFF

Plus mode, ULFO active

(ULPCD during RF-OFF) sum of supply current on pin

VDDIO and VBAT in hard power-down mode

25 °C ambient operating temperature

I standby (VDDIO

+VBAT)

25 °C ambient operating temperature

I suspend (VBAT)

ULPCD (VDDIO

+VBAT)

LPCD (VDDIO+VBAT) sum of supply current on pin

VDDIO and VBAT in standby mode supply current on pin VBAT in suspend mode sum of supply current on pin VDDIO and VBAT in

ULPCD (Ultra Low-Power

Card Detection) mode sum of supply current on pin VDDIO and VBAT in

LPCD (Enhanced Low-Power

Card Detection with highest sensitivity) mode, without DC-

DC used

25 °C ambient operating temperature

25 °C ambient operating temperature,

VBAT supply voltage

3.3 V, antenna matching

50 R, 3.3 V antenna supply voltage, 3x RFon per second

25 °C ambient operating temperature,

VBAT supply voltage

3.3 V, antenna matching

50 R, 3.3 V antenna supply voltage, 3x RFon per second

Min

2.5

Typ

5 -

Max

240 -

105

110

μA

μA mA

μA

Unit

μA

Table 320. Overcurrent detection function

[1]

Symbol Parameter

DD(VUP_TX) current of overcurrent detection becoming active

Conditions Min

450

Typ

550

Max

650

Unit mA

[1] Please refer to the Errata sheet if the device is used with smaller or equal than FW2.1.

This is a safety feature only. A design shall not functionally rely on this feature since the operating conditions will be violated if the overcurrent detection becomes active.

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Table 321. VEN pin

Symbol Parameter

HIGH-level input voltage

LOW-level input voltage

C i t

(ULPCD_abort)

Conditions

DD(VDDIO)

DD(VBAT)

HIGH-level input current

LOW-level input current input capacitance

VEN time required to abort ULPCD

= V

DD(VBAT)

= 0 V

Table 322. GPIO (GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO4, GPIO5) pins

Symbol Parameter Conditions

HIGH-level input voltage V

DD(VDDIO)

<= V

DD(VBAT)

; 1.62 <=

VDDIO <= 1.98 or

2.4 <= VDDIO <= 3.6

Min

0.65x

VDDIO

LOW-level input voltage V

DD(VDDIO)

<= V

DD(VBAT)

VDDIO <= 1.98 or

2.4 <= VDDIO <= 3.6

; 1.62 <= - 0.5

HIGH-level output voltage

LOW-level output voltage

DD(VDDIO)

= 3.3 V

HIGH-level output current

DD(VDDIO)

= 3.3 V

LOW-level output current V

DD(VDDIO)

= 3.3 V

Weak pullup resistor -

Weak pull-down resistor -

VDDIO -

0.4

Typ

Max Unit

VDDIO+0.5 V

0.35 ×

VDDIO

0.4

V mA mA kΩ kΩ

Table 323. CLK1, CLK2 pins

Symbol Parameter

V i(p-p)

IH peak-to-peak input voltage

HIGH-level input current

LOW-level input current I

C i(CLK1) duty cycle input capacitance on pin CLK1

Conditions

Min

0.7 *

DD(VDDIO)

-1

VI= 1.65 V, no power saving, active mode

VI = 0 V, no power saving, active mode

VDD = 1.8 V,

VDC = 0.65 V,

VAC = 0.9 V (p-p)

Typ

Min

0.4

Typ

Max

DD(VDDIO)

0.3 *

DD(VDDIO)

Max

1.65

Unit

μA

μA pF ms

μA

% pF

Unit

μA

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Table 323. CLK1, CLK2 pins

...continued

Symbol

C i(CLK2)

Parameter input capacitance on pin CLK2

Conditions

VDD = 1.8 V,

VDC = 0.65 V,

VAC = 0.9 V (p-p)

Min Typ

1 -

Max Unit pF

Table 324. IRQ pin

Symbol Parameter

HIGH-level output voltage t f t r

R pd

LOW-level output voltage

HIGH-level output current

LOW-level output current load capacitance fall time rise time pull-down resistance

C i

Table 325. SCLK, MOSI, NSS pins

Symbol Parameter

HIGH-level input voltage

LOW-level input voltage

HIGH-level input current

LOW-level input current input capacitance

Conditions

< 3 mA

= 12 pF max

Conditions

= V

VDDIO

= 0 V

Min

DD(VDDIO)

-0.4

Typ

Min

0.65 x

DD(VDDIO)

- 0.5

Typ

Table 326. MISO pin

Symbol Parameter

HIGH-level output voltage t f t r

LOW-level output voltage

HIGH-level output current

LOW-level output current load capacitance fall time rise time

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Conditions

< 3 mA

= 12 pF max

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Min

DD(VDDIO)

-0.4

0 -

Typ

Max

DD(VDDIO)

Unit

0.4

10 ns ns kΩ

V mA mA pF

DD(VDDIO)

0.35 x

DD(VDDIO)

Max

DD(VDDIO)

Unit

0.4

V mA mA pF ns ns

μA

μA pF

Unit

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Table 327. RXp, RXn pins

Symbol Parameter

V i(dyn)

C i

Z i dynamic input voltage input capacitance input impedance from RXN, RXP pins to VMID

Conditions

Reader, card and

P2P modes

Min

Typ Max

1.8

Unit

V pF kΩ

Table 328. TX1, TX2 pins

Symbol Parameter

HIGH-level output voltage

LOW-level output voltage

Conditions

DD(VDDPA)

=5.0 V; with internal

VDDPA LDO

DD(VDDPA)

=5.0 V;with internal

VDDPA LDO

Table 329. AUX1, AUX2, AUX3 pins (Debug output)

Symbol Parameter Conditions

AUX_OH

HIGH-level output voltage

AUX_OL

LOW-level output voltage pin used as debug signal output pin used as debug signal output

AUX_OH

AUX_OL

O_LOAD

HIGH-level output current

LOW-level output current output capacitance load of pin

DD(VDDIO)

= 3.3 V

DD(VDDIO)

= 3.3 V

Table 330. DAC_1, DAC_2 output pins (Tuning DAC)

Symbol Parameter Conditions

O_max

HIGH-level maximum output voltage connected to a variable capacitor (varicap)

O_min

LOW-level minimum output voltage connected to a variable capacitor (varicap)

O_LOAD

DAC resolution output capacitance load of pin

11.3 Timing characteristics

Min

- 0.3

Min

VDDIO

-0.4

0 -

Typ

DD(VDDPA) mV

-150

200 -

Max

DD(VDDPA)

Unit

V mV

Typ

DD(VDDIO)

Max

3.65

200

3.0

Max

VDDIO

0.4

mA mA pF

Unit

V mV

Unit

V mV bits nF

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VBAT = VBATPWR

VDDIO

VEN

V bat

= V batpwr

>2.4 V t vbat_vddio t vbat_ven t vddio_ven

IRQ t boot aaa-037021

Figure 29. Startup timing

Table 331. Power supply connection timing

Symbol Parameter t rise_vbat t vbat_vddio

VBAT supply ramp time between ramping up VBAT and ramping VDDIO t t vbat_ven boot time between ramping VBAT and VEN start-up time

[1]

Conditions

VEN = Low vddio condition:

VBAT>2.4 V,

VDDIO supply

(External), hpd_ off_sel = x vddio condition:

VBAT>2.4 V,

VDDIO supply

(External), hpd_ off_sel = x vddio condition:

VBAT>2.4 V,

VDDIO supply

(External), hpd_ off_sel = x

Min

3.2

Typ

500

500.5

Max

2.75

1000

1001

Unit

V/us ms ms

3.27

dependent on configuration of

XTAL_BOOT_ TIME in EEPROM. This configuration can be used to optimize the boot time for crystals which allow a fast settling. This allows to optimize the average current consumption during ULPCD and

LPCD.

default EEPROM configuration: 3.4

[1] (PN5190B1 ready to receive commands on the host interface). The PN5190B1 indicates the ability to receive commands from a host by raising an IDLE

IRQ.

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Table 332. Pulse length

Symbol Parameter t

(VEN) on Pin VEN, pulse width to reset the chip or exit from

ULPCD / Hard Power Down

State t t

(wake-up)

VEN(GPIO) on pin GPIOx, pulse width to wake up time from VEN high to GPIO’s available for use

Conditions Min

100 -

Typ

Max

Table 333. DAC1, DAC2 conversion timing (Tuning DAC)

Symbol Parameter Conditions t conversion

Conversion speed of 8-bit

DAC1, DAC2

1 LSB rising falling,

(depends on capacitive load)

RF cut resistance: 100 kOhm (max),

Cin: 8 nF (max)

Full signal rising from 0.0 V to 3

(depends on capacitive load)

RF cut resistance: 100 kOhm (max),

Cin: 8 nF (max) falling from 3 V to 300 mV,

(depends on capacitive load)

RF cut resistance: 100 kOhm (max),

Cin: 8 nF (max)

Min

Typ Max

0.15

Unit ms

μs ms

Unit ms ms ms

Table 334. SPI interface

Symbol Parameter

SCK LOW time t

SCKL t

SCKH t h(SCKH-D)

SCK HIGH time

SCK HIGH to data input hold time t su(D-SCKH) t h(SCKL-Q) data input to SCK HIGH set-up time

SCK LOW to data output hold time

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Min

12.5

Typ

Max

Unit ns ns ns ns ns

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Table 334. SPI interface

...continued

Symbol Parameter t

(SCKL-NSSH) t

NSSH

SCK LOW to NSS HIGH time

NSS HIGH time

Min

25 -

Typ

Max Unit ns ns

Table 335. RF_ON command timing following a previous RF_OFF

Symbol Parameter Conditions Min Typ Max t

(RF_OFF-

RF_ON)

RF_ON command timing guard time between command sends for

RF_OFF and command send for

RF_ON, capacitors on transmitter need to be fully decharged before

RF_ON command is sent

5.1

5.6

11.4 Clock input

Table 336. Crystal requirements for ISO/IEC14443 compliant operation

Symbol Parameter Conditions Min Typ f xtal

27.12

delta f

ESR xtal crystal frequency crystal frequency accuracy for full RF operating range equivalent series resistance

ISO/IEC compliancy

-40

L t startupl

P xtal load capacitance crystal startup time crystal power dissipation -

Unit ms

Max

+40

Unit

MHz ppm

100

Ω pF ms

μW

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Table 337. Frequency requirements for a direct clock input (no crystal)

Symbol Parameter Conditions Min Typ f clk clock frequency ISO/IEC compliancy

32 -

Max Unit

MHz

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Table 337. Frequency requirements for a direct clock input (no crystal)

...continued

Symbol Parameter Conditions Min Typ Max delta f clk clock frequency accuracy for full RF operating range

-40 -

48 -

+40

φ n

- 150 -145

V i n i(p-p) i(clk) phase noise phase noise input phase noise floor at 100 kHz offset input phase noise floor at

1 MHz offset

Input voltage boundary sinus signal 0 peak-to-peak Input voltage sinus signal 0.4

clock input voltage square signal

- 152 -149

1.8

+/-10%

Unit ppm dBc/Hz dBc/Hz

11.5 EEPROM characteristics

Table 338. EEPROM characteristics

Symbol Parameter Conditions t

N endu(W) ret write endurance at ambient temperature retention time

T a

= +25 °C at ambient temperature

T a

=+25 °C

Min

100

25 -

Typ

Max Unit

K cycles years

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12 Package outline

12.1 VFBGA64 package

Table 339. Package outline VFBGA64 (SOT1307-2)

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Figure 30. Package outline VFBGA64 (SOT1307-2)

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Figure 31. Package outline note VFBGA64 (SOT1307-2)

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12.2 HVQFN40 package

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Figure 32. Package outline HVQFN40, SOT2062-1

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Figure 33. Package outline detail HVQFN40, SOT2062-1

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13 Package marking

13.1 Package marking drawing VFBGA64

Terminal 1 index area

A : 5

B : 5

C : 8

0 5 aaa-036197

Figure 34. Marking VFBGA64 Package

Line A: 5 characters; "PN5190D" (FW2.0) or "5190E" (FW2.1)

Line B: 5 characters; contains the DB ID and AS ID

Line C: 8 characters; stDYYWW(X) - contains information assembly center, date code and maturity level (“X” = engineering samples, “ “ = released product)

13.2 Package marking drawing HVQFN40

Terminal 1 index area

A : 5

B1 : 5

B2 : 7

C : 7

0 5 aaa-036198

Figure 35. Marking HVQFN40 package SOT2062-1

Line A: 5 characters; "PN5190D" (FW2.0) or "5190E" (FW2.1)

Line B1: 5 characters; contains the DB ID

Line B2: 7 characters; contains the DB ID (continued) and AS ID (2 digits)

Line C: 7 characters; stDYYWW(X) - contains information assembly center, date code and maturity level (“X” = engineering samples, “Y” = customer qualification samples, “ “ = released product)

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14 Reflow soldering footprint VFBGA64

PN5190

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Figure 36. Reflow soldering footprint part1 for VFBGA64 (SOT1307-2)

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Figure 37. Reflow soldering footprint part2 for VFBGA64 (SOT1307-2)

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Figure 38. Reflow soldering footprint part3 for VFBGA64 (SOT1307-2)

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Cu plating

OSP finishing before reflow laminate 2L solder mask

250 µm solder mask opening

350 µm ball aaa-032325

Figure 39. Soldering and footprint representative illustration for VFBGA64 (SOT1307-2)

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15 Reflow soldering footprint HVQFN40

PN5190

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Figure 40. Package outline HVQFN40, SOT2062-1

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Figure 41. Package outline HVQFN40, SOT2062-1

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Figure 42. Package outline HVQFN40, SOT2062-1

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Figure 43. Package outline HVQFN40, SOT2062-1

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16 Surface mount reflow soldering

For information on surface mount, reflow soldering and component handling please refer to the related application note.

This application note provides guidelines for the board mounting and handling of NXP

Semiconductor packages: https://www.nxp.com/docs/en/application-note/AN10365.pdf

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17 Handling information

Moisture Sensitivity Level (MSL) evaluation has been performed according to SNW-

FQ-225B rev.04/07/07 (JEDEC J-STD-020C) .

An MSL corresponds to a certain out-of-bag time (or floor life). If semiconductor packages are removed from their sealed dry-bags and not soldered within their out-ofbag time, they must be baked prior to reflow soldering, in order to remove any moisture that might have soaked into the package.

For MSL3:

168h out-of-pack floor life at maximum ambient temperature, conditions < 30 °C / 60 %

RH.

For MSL2:

• 1 year out-of-pack floor life at maximum ambient temperature, conditions < 30 °C° / 60

% RH.

For MSL1:

• No out-of-pack floor live spec. required. Conditions: <30 °C° / 85 % RH.

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,

JESD625-A or equivalent standards.

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18 Appendix: EEPROM LOAD_RF_CONFIGURATION FW2.0

Firmware 2.0

<?xml version="1.0" encoding="utf-8"?>

</Region>

</Region>

</Region>

</Region>

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</Region>

</Region>

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</Region>

</Region>

</Region>

</Region>

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NFC frontend

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NFC frontend

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</Region>

</Region>

</Region>

</Region>

</Region>

</Region>

</Region>

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NFC frontend

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</Region>

</Region>

</Region>

</Region>

</Region>

</Region>

</Region>

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</Region>

</Region>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Region>

</EEPROM>

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19 Appendix: EEPROM LOAD_RF_CONFIGURATION FW2.1

Firmware 2.1

<?xml version="1.0" encoding="utf-8"?>

</Region>

</Region>

</Region>

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</Region>

</Region>

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</Region>

</Region>

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</Region>

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</Region>

</Region>

</Region>

</Region>

</Region>

</Region>

</Region>

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</Region>

</Region>

</Region>

</Region>

</Region>

</Region>

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</Region>

</Region>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Protocol>

</Protocol>

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</Protocol>

</Region>

</EEPROM>

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20 Abbreviations

SCK

SCL

SPI

TFT

PCB

PCD

PICC

RSSI

UID

DPC

EMD

GPIO

HPD

LDO

LPCD

MISO

MOSI

NSS

Table 340. Abbreviations

Acronym Description

ADC

AGC analog-to-digital converter automatic gain control

ARC

AWC adaptive receiver control adaptive waveshape control

CLIF

DAC

DC-DC contactless interface digital-to-analog converter switch-mode voltage regulator which uses an inductor to store and transfer energy to the output, used for a power supply voltage conversion. PN5190B1

integrates a step-up/boost converter dynamic power control electromagnetic disturbance general-purpose input output hard power down low dropout regulator low-power card detection

SPI interface Master In Slave Out

SPI interface Master Out Slave In

SPI interface active-low slave-select signal operating system printed-circuit board power card detection proximity inductive coupling card radio frequency receiver signal strength indicator

ULPCD

SPI interface serial clock

C interface serial clock serial peripheral interface display technology: thin-film transistor-display transmit

Unique identifier of a card, used during anti-collision sequence to select one out of multiple cards.

ultra low-power card detection

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21 References

[1] Application note - AN12551 PN5190 Design-in document

[2] Application note - AN12549 PN5190 Antenna design guide

[3] Product data sheet addendum - AD PN5190 Instruction layer

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22 Revision history

Table 341. Revision history

Document ID Release date Data sheet status

PN5190B1 v. 3.0 20210421

Modifications: •

Product data sheet

General update

• Data sheet status changed to "Product data sheet"

PN5190B1 v. 1.0 20210322

Modifications: •

Objective data sheet

First official released version

PN5190

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Supersedes

PN5190B1 v. 1.0

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23 Legal information

23.1 Data sheet status

Document status

[1][2]

Objective [short] data sheet

Preliminary [short] data sheet

Product [short] data sheet

Product status

Development

Qualification

Production

[3]

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

23.2 Definitions

Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

23.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

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No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability.

Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team

(PSIRT) (reachable at [email protected]) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.

23.4 Licenses

Purchase of NXP ICs with ISO/IEC 14443 type B functionality

RATP/Innovatron

Technology

This NXP Semiconductors IC is ISO/IEC

14443 Type B software enabled and is licensed under Innovatron’s Contactless

Card patents license for ISO/IEC 14443 B.

The license includes the right to use the IC in systems and/or end-user equipment.

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that complies with one of the

Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/

IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. Purchase of NXP

Semiconductors IC does not include a license to any NXP patent (or other

IP right) covering combinations of those products with other products, whether hardware or software.

23.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I 2 C-bus — logo is a trademark of NXP B.V.

MIFARE — is a trademark of NXP B.V.

DESFire — is a trademark of NXP B.V.

ICODE and I-CODE — are trademarks of NXP B.V.

MIFARE Plus — is a trademark of NXP B.V.

MIFARE Ultralight — is a trademark of NXP B.V.

MIFARE Classic — is a trademark of NXP B.V.

NTAG — is a trademark of NXP B.V.

NXP — wordmark and logo are trademarks of NXP B.V.

FeliCa — is a trademark of Sony Corporation.

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Tables

Tab. 1.

Quick reference data .........................................6

Tab. 2.

Ordering information ..........................................7

Tab. 3.

Pin description VFBGA64 ................................. 9

Tab. 4.

Pin description HVQFN40 ............................... 13

Tab. 5.

Supply voltage range ...................................... 27

Tab. 6.

DPC_LOOKUP_TABLE element, defining the configuration for one dedicated VDDPA voltage .............................................................33

Tab. 7.

Dynamic power control characteristics ............33

Tab. 8.

ARC_VDDPA (0139Eh) EEPROM configuration bit description ............................ 37

Tab. 9.

ARC_RM_A106 (address 013Eh)

EEPROM configuration bit description ............ 37

Tab. 10. Low-Power Card Detection: relevant

EEPROM configuration ................................... 43

Tab. 11. Low-Power Card Detection - semiautonomous mode: relevant REGISTERS ...... 44

Tab. 12. DEBUG SIGNALS ...........................................47

Tab. 13. TRIGGER SIGNALS ....................................... 49

Tab. 14. Host interface commands ............................... 52

Tab. 15. WRITE_REGISTER .........................................54

Tab. 16. WRITE_REGISTER_OR_MASK ..................... 55

Tab. 17. WRITE_REGISTER_AND_MASK ...................55

Tab. 18. WRITE_REGISTER_MULTIPLE ..................... 56

Tab. 19. READ_REGISTER .......................................... 57

Tab. 20. READ_REGISTER_MULTIPLE ....................... 57

Tab. 21. WRITE_EEPROM ........................................... 58

Tab. 22. READ_EEPROM ............................................. 59

Tab. 23. TANSMIT_RF_DATA ....................................... 60

Tab. 24. RETRIEVE_RF_DATA .....................................60

Tab. 25. EXCHANGE_RF_DATA ...................................61

Tab. 26. EXCHANGE_RF_DATA Parameter RF

Exchange Config: Bitmask .............................. 62

Tab. 27. MFC_AUTHENTICATE ....................................62

Tab. 28. EPC_GEN2_INVENTORY ...............................64

Tab. 29. LOAD_RF_CONFIGURATION ........................ 66

Tab. 30. TX Parameter for command LOAD_RF_

CONFIGURATION ...........................................66

Tab. 31. RX Parameter for command LOAD_RF_

CONFIGURATION ...........................................67

Tab. 32. UPDATE_RF_CONFIGURATION ....................69

Tab. 33. GET_RF_CONFIGURATION ...........................69

Tab. 34. RF_ON ............................................................ 70

Tab. 35. RF_OFF ...........................................................71

Tab. 36. RF_OFF ...........................................................71

Tab. 37. RF_OFF ...........................................................72

Tab. 38. CTS_ENABLE ................................................. 73

Tab. 39. CTS_CONFIGURE ..........................................73

Tab. 40. CTS_RETRIEVE_LOG ....................................77

Tab. 41. RECEIVE_RF_DATA .......................................78

Tab. 42. EVT_SWITCH_MODE_NORMAL ................... 79

Tab. 43. SWITCH_MODE_NORMAL ............................ 79

Tab. 44. EVT_SWITCH_MODE_AUTOCOLL ............... 79

Tab. 45. SWITCH_MODE_AUTOCOLL ........................ 80

Tab. 46. RF Technologies parameter: Bitmask ..............80

Tab. 47. EVT_SWITCH_MODE_STANDBY .................. 81

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Tab. 48. SWITCH_MODE_STANDBY ...........................81

Tab. 49. STANDBY control parameter: Bitmask ............81

Tab. 50. EVT_SWITCH_MODE_LPCD ......................... 82

Tab. 51. SWITCH_MODE_LPCD .................................. 82

Tab. 52. SWITCH_MODE_DOWNLOAD .......................83

Tab. 53. GET_DIE_ID ....................................................83

Tab. 54. GET_VERSION ............................................... 84

Tab. 55. PRBS_TEST ....................................................85

Tab. 56. RESPONSE STATUS CODES LIST ............... 85

Tab. 57. IRQ EVENT LIST ............................................ 87

Tab. 58. Register Overview ...........................................88

Tab. 59. SYSTEM_CONFIG register (address

0000h) bit description ......................................91

Tab. 60. EVENT_ENABLE register (address 0001h) bit description .................................................. 91

Tab. 61. EVENT_STATUS register (address 0002h) bit description .................................................. 92

Tab. 62. EMVCO_EMD_CONTROL register

(address 0003h) bit description .......................92

Tab. 63. FELICA_EMD_CONTROL register

(address 0004h) bit description .......................93

Tab. 64. RX_STATUS register (address 0005h) bit description ....................................................... 94

Tab. 65. RX_STATUS_ERROR register (address

0006h) bit description ......................................95

Tab. 66. CLIF_STATUS register (address 0007h) bit description ....................................................... 97

Tab. 67. RF_EXCHANGE_CONTROL register

(address 0008h) bit description .......................98

Tab. 68. TX_SYMBOL01_MOD register (address

0009h) bit description ......................................99

Tab. 69. TX_SYMBOL1_DEF register (address

000Ah) bit description ..................................... 99

Tab. 70. TX_SYMBOL0_DEF register (address

000Bh) bit description ................................... 100

Tab. 71. TX_SYMBOL23_MOD register (address

000Ch) bit description ................................... 100

Tab. 72. TX_SYMBOL23_DEF register (address

000Dh) bit description ................................... 100

Tab. 73. TX_SYMBOL_CONFIG register (address

000Eh) bit description ................................... 100

Tab. 74. TX_FRAME_CONFIG register (address

000Fh) bit description ....................................101

Tab. 75. TX_DATA_MOD register (address 0010h) bit description ................................................ 102

Tab. 76. TX_CLIF_WAIT register (address 0011h) bit description ................................................ 103

Tab. 77. TX_CRC_CONFIG (address 0012h) bit description ..................................................... 104

Tab. 78. SS_TX_CONFIG register (address 0015h) bit description ................................................ 104

Tab. 79. SS_TX1_RMCFG register (address 0016h) bit description ................................................ 105

Tab. 80. SS_TX2_RMCFG register (address 0017h) bit description ................................................ 105

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Tab. 81. SS_TX_TRANS_CFG register (address

0019h) bit description ....................................106

Tab. 82. SIGPRO_RM_PATTERN register (address

0020h) bit description ....................................106

Tab. 83. SIGPRO_RM_TECH register (address

0022h) bit description ....................................106

Tab. 84. RX_FRAME_LENGTH register (address

0026h) bit description ....................................107

Tab. 85. RX_ERROR_CONFIG register (address

0027h) bit description ....................................107

Tab. 86. RX_CTRL_STATUS register (address

0028h) bit description ....................................107

Tab. 87. SIGPRO_IIR_CONFIG0 register (address

002Ah) bit description ................................... 108

Tab. 88. DGRM_RSSI register (address 0030h) bit description ..................................................... 108

Tab. 89. RX_CRC_CONFIG register (address

0031h) bit description ....................................108

Tab. 90. RX_WAIT register (address 0032h) bit description ..................................................... 109

Tab. 91. RXM_CTRL register (address 0035h) bit description ..................................................... 110

Tab. 92. SS_TX1_CMCFG register (address 003Bh) bit description ................................................ 110

Tab. 93. SS_TX2_CMCFG register (address 003Ch) bit description ................................................ 110

Tab. 94. TIMER0_CONFIG register (address

003Dh) bit description ................................... 110

Tab. 95. TIMER0_RELOAD register (address

003Eh) bit description ................................... 111

Tab. 96. TIMER1_CONFIG register (address

003Fh) bit description ....................................111

Tab. 97. TIMER1_RELOAD register (address

0040h) bit description ....................................113

Tab. 98. EMD_1_CFG register (address 0047h) bit description ..................................................... 113

Tab. 99. EMD_0_CONFIG register (address 0048h) bit description ................................................ 114

Tab. 100. LPCD_CALIBRATE_CTRL register

(address 0050h) bit description .....................114

Tab. 101. IQ_CHANNEL_VALS register (address

0051h) bit description ....................................114

Tab. 102. PAD_CONFIG register (address 0052h) bit description ..................................................... 114

Tab. 103. CALIBRATE_STATUS register (address

0053h) bit description ....................................115

Tab. 104. TXLDO_VDDPA_CONFIG register

(address 0054h) bit description .....................115

Tab. 105. GENERAL_ERROR_STATUS register

(address 0055h) bit description .....................116

Tab. 106. TXLDO_VOUT_CURR register (address

0056h) bit description ....................................116

Tab. 107. CLIF_DAC register (address 0057h) bit description ..................................................... 117

Tab. 108. PMU_ANA_SMPS_CTRL_REG register

(address 0058h) bit description .....................118

Tab. 109. RXM_FREQ register (address 0059h) bit description ..................................................... 118

Tab. 110. RXM_RSSI register (address 005Ah) bit description ..................................................... 118

Tab. 111. TEMP_SENSOR register (address 005Bh) bit description ................................................ 119

Tab. 112. TX_NOV_CALIBRATE register (address

005Dh) bit description ................................... 119

Tab. 113. SS_TX1_RTRTRANS0 register (address

0080h) bit description ....................................119

Tab. 114. SS_TX1_RTRTRANS1 register (address

0081h) bit description ....................................119

Tab. 115. SS_TX1_RTRTRANS2 register (address

0082h) bit description ....................................120

Tab. 116. SS_TX1_RTRTRANS0 register (address

0080h) bit description ....................................120

Tab. 117. SS_TX2_RTRTRANS0 register (address

00804) bit description ....................................120

Tab. 118. SS_TX2_RTRTRANS1 register (address

0085h) bit description ....................................120

Tab. 119. SS_TX2_RTRTRANS2 register (address

0086h) bit description ....................................121

Tab. 120. SS_TX2_RTRTRANS3 register (address

0087h) bit description ....................................121

Tab. 121. SS_TX1_FTRTRANS0 register (address

0088h) bit description ....................................121

Tab. 122. SS_TX1_FTRTRANS1 register (address

0089h) bit description ....................................121

Tab. 123. SS_TX1_FTRTRANS2 register (address

008Ah) bit description ................................... 121

Tab. 124. SS_TX1_FTRTRANS3 register (address

008Bh) bit description ................................... 122

Tab. 125. SS_TX2_FTRTRANS0 register (address

008Ch) bit description ................................... 122

Tab. 126. SS_TX2_FTRTRANS1 register (address

008Dh) bit description ................................... 122

Tab. 127. SS_TX2_FTRTRANS2 register (address

008Eh) bit description ................................... 122

Tab. 128. SS_TX2_FTRTRANS3 register (address

008Fh) bit description ....................................123

Tab. 129. EEPROM CONFIGURATION REGISTER .....123

Tab. 130. PWR_CONFIG (address 0000h) EEPROM configuration bit description ...........................129

Tab. 131. DCDC_CONFIG (address 0001h)

EEPROM configuration bit description .......... 129

Tab. 132. TXLDO_CONFIG (address 0002h)

EEPROM configuration bit description .......... 130

Tab. 133. TXLDO_VDDPA_HIGH (address 0006h)

EEPROM configuration bit description .......... 131

Tab. 134. TXLDO_VDDPA_LOW (address 0007h)

EEPROM configuration bit description .......... 132

Tab. 135. TXLDO_VDDPA_MAX_RDR (address

0008h) EEPROM configuration bit description ..................................................... 133

Tab. 136. TXLDO_VDDPA_MAX_CARD (address

0009h) EEPROM configuration bit description ..................................................... 134

Tab. 137. BOOST_DEFAULT_VOLTAGE (address

000Ah) EEPROM configuration bit description ..................................................... 135

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Tab. 138. XTAL_CONFIG (address 0010h) EEPROM configuration bit description ...........................135

Tab. 139. XTAL_TIMEOUT (address 0011h)

EEPROM configuration bit description .......... 136

Tab. 140. CLK_INPUT_FREQ (address 0012h)

EEPROM configuration bit description .......... 136

Tab. 141. XTAL_CHECK_DELAY (address 0013h)

EEPROM configuration bit description .......... 136

Tab. 142. TEMP_WARNING (address 0014h)

EEPROM configuration bit description .......... 137

Tab. 143. ENABLE_GPIO0_ON_OVERTEMP

(address 0016h) EEPROM configuration bit description ..................................................... 137

Tab. 144. RESIDUAL_AMPL_LEVEL_A106 (address

0022h) EEPROM configuration bit description ..................................................... 137

Tab. 145. EDGE_TYPE_A106 (address 0023h)

EEPROM configuration bit description .......... 138

Tab. 146. EDGE_STYLE_A106 (address 0024h)

EEPROM configuration bit description .......... 138

Tab. 147. EDGE_LENGTH_A106 (address 0025h)

EEPROM configuration bit description .......... 139

Tab. 148. RESIDUAL_AMPL_LEVEL_A212 (address

0026h) EEPROM configuration bit description ..................................................... 139

Tab. 149. EDGE_TYPE_A212 (address 0027h)

EEPROM configuration bit description .......... 139

Tab. 150. EDGE_STYLE_A212 (address 0028h)

EEPROM configuration bit description .......... 140

Tab. 151. EDGE_LENGTH_A212 (address 0029h)

EEPROM configuration bit description .......... 140

Tab. 152. RESIDUAL_AMPL_LEVEL_A424 (address

002Ah) EEPROM configuration bit description ..................................................... 141

Tab. 153. EDGE_TYPE_A424 (address 002Bh)

EEPROM configuration bit description .......... 141

Tab. 154. EDGE_STYLE_A424 (address 002Ch)

EEPROM configuration bit description .......... 141

Tab. 155. EDGE_LENGTH_A424 (address 002Ch)

EEPROM configuration bit description .......... 142

Tab. 156. RESIDUAL_AMPL_LEVEL_A848 (address

002Eh) EEPROM configuration bit description ..................................................... 142

Tab. 157. EDGE_TYPE_A848 (address 002Fh)

EEPROM configuration bit description .......... 143

Tab. 158. EDGE_STYLE_A848 (address 0030h)

EEPROM configuration bit description .......... 143

Tab. 159. EDGE_LENGTH_A848 (address 0031h)

EEPROM configuration bit description .......... 144

Tab. 160. RESIDUAL_AMPL_LEVEL_B106 (address

0032h) EEPROM configuration bit description ..................................................... 144

Tab. 161. EDGE_TYPE_B106 (address 0033h)

EEPROM configuration bit description .......... 144

Tab. 162. EDGE_STYLE_B106 (address 0034h)

EEPROM configuration bit description .......... 145

Tab. 163. EDGE_LENGTH_B106 (address 0035h)

EEPROM configuration bit description .......... 145

Tab. 164. RESIDUAL_AMPL_LEVEL_B212 (address

0036h) EEPROM configuration bit description ..................................................... 146

Tab. 165. EDGE_TYPE_B212 (address 0037h)

EEPROM configuration bit description .......... 146

Tab. 166. EDGE_STYLE_B212 (address 0038h)

EEPROM configuration bit description .......... 146

Tab. 167. EDGE_LENGTH_B212 (address 0039h)

EEPROM configuration bit description .......... 147

Tab. 168. RESIDUAL_AMPL_LEVEL_B424 (address

003Ah) EEPROM configuration bit description ..................................................... 147

Tab. 169. EDGE_TYPE_B424 (address 003Bh)

EEPROM configuration bit description .......... 148

Tab. 170. EDGE_STYLE_B424 (address 003Ch)

EEPROM configuration bit description .......... 148

Tab. 171. EDGE_LENGTH_B424 (address 003Dh)

EEPROM configuration bit description .......... 149

Tab. 172. RESIDUAL_AMPL_LEVEL_B848 (address

003Eh) EEPROM configuration bit description ..................................................... 149

Tab. 173. EDGE_TYPE_B848 (address 003Fh)

EEPROM configuration bit description .......... 149

Tab. 174. EDGE_STYLE_B848 (address 0040h)

EEPROM configuration bit description .......... 150

Tab. 175. EDGE_LENGTH_B848 (address 0041h)

EEPROM configuration bit description .......... 150

Tab. 176. RESIDUAL_AMPL_LEVEL_F212 (address

0042h) EEPROM configuration bit description ..................................................... 151

Tab. 177. EDGE_TYPE_F212 (address 0043h)

EEPROM configuration bit description .......... 151

Tab. 178. EDGE_STYLE_F212 (address 0044h)

EEPROM configuration bit description .......... 151

Tab. 179. EDGE_LENGTH_F212 (address 0045h)

EEPROM configuration bit description .......... 152

Tab. 180. RESIDUAL_AMPL_LEVEL_F424 (address

0046h) EEPROM configuration bit description ..................................................... 152

Tab. 181. EDGE_TYPE_F424 (address 0047h)

EEPROM configuration bit description .......... 153

Tab. 182. EDGE_STYLE_F424 (address 0048h)

EEPROM configuration bit description .......... 153

Tab. 183. EDGE_LENGTH_F424 (address 0049h)

EEPROM configuration bit description .......... 154

Tab. 184. RESIDUAL_AMPL_LEVEL_V100_26

(address 004Ah) EEPROM configuration bit description ................................................ 154

Tab. 185. EDGE_TYPE_V100_26 (address 004Bh)

EEPROM configuration bit description .......... 154

Tab. 186. EDGE_STYLE_V100_26 (address 004Ch)

EEPROM configuration bit description .......... 155

Tab. 187. EDGE_LENGTH_V100_26 (address

004Dh) EEPROM configuration bit description ..................................................... 155

Tab. 188. RESIDUAL_AMPL_LEVEL_V100_53

(address 004Eh) EEPROM configuration bit description ................................................ 156

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Tab. 189. EDGE_TYPE_V100_53 (address 004Fh)

EEPROM configuration bit description .......... 156

Tab. 190. EDGE_STYLE_A106 (address 0050h)

EEPROM configuration bit description .......... 156

Tab. 191. EDGE_LENGTH_V100_53 (address

0051h) EEPROM configuration bit description ..................................................... 157

Tab. 192. RESIDUAL_AMPL_LEVEL_V100_106

(address 0052h) EEPROM configuration bit description ..................................................... 157

Tab. 193. EDGE_TYPE_V100_106 (address 0053h)

EEPROM configuration bit description .......... 158

Tab. 194. EDGE_STYLE_V100_106 (address 0054h)

EEPROM configuration bit description .......... 158

Tab. 195. EDGE_LENGTH_V100_106 (address

0055h) EEPROM configuration bit description ..................................................... 159

Tab. 196. RESIDUAL_AMPL_LEVEL_100_212

(address 0056h) EEPROM configuration bit description ..................................................... 159

Tab. 197. EDGE_TYPE_V100_212 (address 0057h)

EEPROM configuration bit description .......... 159

Tab. 198. EDGE_STYLE_V100_212 (address 0058h)

EEPROM configuration bit description .......... 160

Tab. 199. EDGE_LENGTH_V100_212 (address

0059h) EEPROM configuration bit description ..................................................... 160

Tab. 200. RESIDUAL_AMPL_LEVEL_V10_26

(address 005Ah) EEPROM configuration bit description ................................................ 161

Tab. 201. EDGE_TYPE_V10_26 (address 005Bh)

EEPROM configuration bit description .......... 161

Tab. 202. EDGE_STYLE_V10_26 (address 005Ch)

EEPROM configuration bit description .......... 161

Tab. 203. EDGE_LENGTH_V10_26 (address 005Dh)

EEPROM configuration bit description .......... 162

Tab. 204. RESIDUAL_AMPL_LEVEL_V10_53

(address 005Eh) EEPROM configuration bit description ................................................ 162

Tab. 205. EDGE_TYPE_V10_53 (address 005Fh)

EEPROM configuration bit description .......... 163

Tab. 206. EDGE_STYLE_V10_53 (address 0060h)

EEPROM configuration bit description .......... 163

Tab. 207. EDGE_LENGTH_V10_53 (address 0061h)

EEPROM configuration bit description .......... 164

Tab. 208. RESIDUAL_AMPL_LEVEL_V10_106

(address 0062h) EEPROM configuration bit description ..................................................... 164

Tab. 209. EDGE_TYPE_V10_106 (address 0063h)

EEPROM configuration bit description .......... 164

Tab. 210. EDGE_STYLE_V100_212 (address 0064h)

EEPROM configuration bit description .......... 165

Tab. 211. EDGE_LENGTH_V10_106 (address

0065h) EEPROM configuration bit description ..................................................... 165

Tab. 212. RESIDUAL_AMPL_LEVEL_V10_212

(address 0066h) EEPROM configuration bit description ..................................................... 166

Tab. 213. EDGE_TYPE_V10_212 (address 0067h)

EEPROM configuration bit description .......... 166

Tab. 214. EDGE_STYLE_V10_212 (address 0068h)

EEPROM configuration bit description .......... 166

Tab. 215. EDGE_LENGTH_V100_212 (address

0069h) EEPROM configuration bit description ..................................................... 167

Tab. 216. RESIDUAL_AMPL_LEVEL_180003m3_ tari18p88 (address 006Ah) EEPROM configuration bit description ...........................167

Tab. 217. EDGE_TYPE_180003m3_tari18p88

(address 006Bh) EEPROM configuration bit description ................................................ 168

Tab. 218. EDGE_STYLE_180003m3_tari18p88

(address 006Ch) EEPROM configuration bit description ................................................ 168

Tab. 219. EDGE_LENGTH_180003m3_tari18p88

(address 006Dh) EEPROM configuration bit description ................................................ 169

Tab. 220. RESIDUAL_AMPL_LEVEL_180003m3_ tari9p44 (address 006Eh) EEPROM configuration bit description ...........................169

Tab. 221. EDGE_TYPE_180003m3_tari9p44

(address 006Fh) EEPROM configuration bit description ..................................................... 169

Tab. 222. EDGE_STYLE_180003m3_tari9p44

(address 0070h) EEPROM configuration bit description ..................................................... 170

Tab. 223. EDGE_LENGTH_180003m3_tari9p44

(address 0071h) EEPROM configuration bit description ..................................................... 170

Tab. 224. RESIDUAL_AMPL_LEVEL_180003m3_ tari18p88 (address 0072h) EEPROM configuration bit description ...........................171

Tab. 225. EDGE_TYPE_B_PRIME_106 (address

0073h) EEPROM configuration bit description ..................................................... 171

Tab. 226. EDGE_STYLE_B_PRIME_106 (address

0074h) EEPROM configuration bit description ..................................................... 171

Tab. 227. EDGE_LENGTH_B_PRIME_106 (address

0075h) EEPROM configuration bit description ..................................................... 172

Tab. 228. DPC_CONFIG (address 0076h) EEPROM configuration bit description ...........................172

Tab. 229. DPC_TARGET_CURRENT (address 077h)

EEPROM configuration bit description .......... 173

Tab. 230. DPC_HYSTERESIS_LOADING (address

079h) EEPROM configuration bit description ..................................................... 173

Tab. 231. DPC_HYSTERESIS_UNLOADING

(address 07Ch) EEPROM configuration bit description ..................................................... 173

Tab. 232. DPC_TXLDOVDDPALow (address 007Dh)

EEPROM configuration register bit description ..................................................... 174

Tab. 233. DPC_TXGSN (address 007Eh) EEPROM configuration register bit description ..............174

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Tab. 234. DPC_RDON_Control (address 007Fh)

EEPROM configuration register bit description ..................................................... 174

Tab. 235. DPC_InitialRDOn_RFOn (address 0080h)

EEPROM configuration register bit description ..................................................... 174

Tab. 236. DPC_GUARD_TIME (address 087h)

EEPROM configuration bit description .......... 174

Tab. 237. DPC_ENABLE_DURING_FDT (address

088h) EEPROM configuration bit description ..................................................... 175

Tab. 238. DPC_GUARD_TIME_AFTER_RX (address

089h) EEPROM configuration bit description ..................................................... 175

Tab. 239. DPC_LOOKUP_TABLE (008Bh-0133h)

EEPROM configuration bit description .......... 175

Tab. 240. ARC_CONFIG (address 0137h) EEPROM configuration bit description ...........................176

Tab. 241. ARC_VDDPA (0139Eh) EEPROM configuration bit description ...........................176

Tab. 242. ARC_RM_A106 (address 013Eh)

EEPROM configuration bit description .......... 178

Tab. 243. ARC_RM_A212 (address 0148h) EEPROM configuration bit description ...........................179

Tab. 244. ARC_RM_A424 (address 0152h) EEPROM configuration bit description ...........................181

Tab. 245. ARC_RM_A848 (address 015Ch)

EEPROM configuration bit description .......... 182

Tab. 246. ARC_RM_B106 (address 0166h) EEPROM configuration bit description ...........................184

Tab. 247. ARC_RM_B212 (address 0170h) EEPROM configuration bit description ...........................185

Tab. 248. ARC_RM_B424 (address 017Ah)

EEPROM configuration bit description .......... 187

Tab. 249. ARC_RM_B848 (address 0184h) EEPROM configuration bit description ...........................188

Tab. 250. ARC_RM_F212 (address 018Eh)

EEPROM configuration bit description .......... 190

Tab. 251. ARC_RM_F424 (address 0198h) EEPROM configuration bit description ...........................191

Tab. 252. ARC_RM_V_6p6 (address 01A2h)

EEPROM configuration bit description .......... 193

Tab. 253. ARC_RM_V_26 (address 01ACh)

EEPROM configuration bit description .......... 194

Tab. 254. ARC_RM_V53(address 01B6h) EEPROM configuration bit description ...........................196

Tab. 255. ARC_RM_V106(address 01C0h) EEPROM configuration bit description ...........................197

Tab. 256. ARC_RM_V212(address 01CAh) EEPROM configuration bit description ...........................199

Tab. 257. ARC_RM_180003m3_SC424_4Man

(address 01D4h) EEPROM configuration bit description ................................................ 200

Tab. 258. ARC_RM_180003m3_SC424_2Man

(address 01DEh) EEPROM configuration bit description ................................................ 202

Tab. 259. ARC_RM_180003m3_SC848_4Man

(address 01E8h) EEPROM configuration bit description ................................................ 203

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Tab. 260. ARC_RM_180003m3_SC848_2Man

(address 01F2h) EEPROM configuration bit description ..................................................... 205

Tab. 261. ARC_RM_AI106 (address 01FCh)

EEPROM configuration bit description .......... 206

Tab. 262. ARC_RM_AI212 (0206h) EEPROM configuration bit description ...........................208

Tab. 263. ARC_RM_AI424 (0210h) EEPROM configuration bit description ...........................209

Tab. 264. RF_DEBOUNCE_TIMEOUT (address

02B2h) EEPROM configuration bit description ..................................................... 210

Tab. 265. SENSE_RES (address 02B3) EEPROM configuration bit description ...........................211

Tab. 266. SIGNAL_SCALING_CONFIG (address

2B5h) EEPROM configuration bit description ..................................................... 211

Tab. 267. SEL_RES (address 2B8h) EEPROM configuration bit description ...........................211

Tab. 268. FELICA_POLL_RES (address 02B9)

EEPROM configuration bit description .......... 211

Tab. 269. RANDOM_UID_ENABLE (address 2CBh)

EEPROM configuration bit description .......... 212

Tab. 270. MFC_AUTH_TIMEOUT (address 2CCh)

EEPROM configuration bit description .......... 212

Tab. 271. RSSI_TIMER (address 2DAh) EEPROM configuration bit description ...........................212

Tab. 272. RSSI_TIMER_FIRST_PERIOD (address

2DCh) EEPROM configuration bit description ..................................................... 212

Tab. 273. RSSI_CTRL_00_AB (address 2DEh)

EEPROM configuration bit description .......... 212

Tab. 274. RSSI_NB_ENTRIES_AB (address 2DFh)

EEPROM configuration bit description .......... 213

Tab. 275. RSSI_THRESHOLD_PHASE_TABLE

(address 2E0h) EEPROM configuration bit description ..................................................... 213

Tab. 276. TX_PARAM_ENTRY_TABLE (address

3A2h) EEPROM configuration bit description ..................................................... 214

Tab. 277. LPCD_AVG_SAMPLES (address 0492h)

EEPROM configuration bit description .......... 218

Tab. 278. LPCD_RSSI_TARGET (address 0494h)

EEPROM configuration bit description .......... 218

Tab. 279. LPCD_RSSI_HYST (address 0496h)

EEPROM configuration bit description .......... 218

Tab. 280. LPCD_CONFIG (address 0497h) EEPROM configuration register bit description ..............218

Tab. 281. LPCD_THRESHOLD_COARSE (address

049Ah) EEPROM configuration bit description ..................................................... 219

Tab. 282. LPCD_VDDPA (address 04B5h) EEPROM configuration bit description ...........................220

Tab. 283. ULPCD_VDDPA_CTRL (address 4BFh)

EEPROM configuration bit description .......... 221

Tab. 284. ULPCD_TIMING_CTRL (address 4C2h)

EEPROM configuration bit description .......... 222

Tab. 285. ULPCD_VOLTAGE_CTRL (address 4C6h)

EEPROM configuration bit description .......... 222

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Tab. 286. ULPCD_RSSI_GUARD_TIME (address

4C9h) EEPROM configuration bit description ..................................................... 222

Tab. 287. ULPCD_RSSI_SAMPLE_CFG (address

4CAh) EEPROM configuration bit description ..................................................... 222

Tab. 288. ULPCD_THRESH_LVL (address 4CBh)

EEPROM configuration bit description .......... 223

Tab. 289. ULPCD_GPIO3 (address 4CCh) EEPROM configuration bit description ...........................223

Tab. 290. FELICA_POLL_RES (address 0559)

EEPROM configuration bit description .......... 223

Tab. 291. FDT_default_val (address 055D) EEPROM configuration bit description ...........................223

Tab. 292. RXIRQ_GuardTime (address 0561h)

EEPROM configuration bit description .......... 223

Tab. 293. NFCLD_RFLD_Valid (address 06D3h)

EEPROM configuration register bit description ..................................................... 224

Tab. 294. CurrentSensorTrimConfig (address

0CACh) EEPROM configuration bit description ..................................................... 224

Tab. 295. CORRECTION_ENTRY_TABLE (address

0BDAh) EEPROM configuration bit description ..................................................... 224

Tab. 296. RTRANS_FTRANS_TABLE (address

C03h) EEPROM configuration bit description ..................................................... 226

Tab. 297. CFG_NOV_CAL (address 0083h)

EEPROM configuration bit description .......... 227

Tab. 298. NOV_CAL_VAL1 (address 0C84h)

EEPROM configuration bit description .......... 227

Tab. 299. NOV_CAL_VAL2 (0C85h) EEPROM configuration bit description ...........................227

Tab. 300. NOV_CAL_THRESHOLD (address 0C86h)

EEPROM configuration bit description .......... 228

Tab. 301. NOV_CAL_OFFSET1 (address 0C87h)

EEPROM configuration bit description .......... 228

Tab. 302. NOV_CAL_OFFSET1 (address 0C8Bh)

EEPROM configuration bit description .......... 228

Tab. 303. VDDPA_DISCHARGE (address 0C8Fh)

EEPROM configuration bit description .......... 228

Tab. 304. ARC_RM_A106_FDT (address 0C9Dh)

EEPROM configuration bit description .......... 229

Tab. 305. Tx_Symbol23_Mod_Reg_BR_53

(0CC5Eh) EEPROM configuration bit description ..................................................... 230

Tab. 306. Tx_Data_Mod_Reg_BR_53 (0CC9Eh)

EEPROM configuration bit description .......... 230

Tab. 307. Tx_Symbol23_Mod_Reg_BR_106

(0CCDEh) EEPROM configuration bit description ..................................................... 230

Tab. 308. Tx_Data_Mod_Reg_BR_106 (0CD1Eh)

EEPROM configuration bit description .......... 230

Tab. 309. Tx_Symbol23_Mod_Reg_BR_212

(0CD5Eh) EEPROM configuration bit description ..................................................... 230

Tab. 310. Tx_Data_Mod_Reg_BR_212 (0CD9Eh)

EEPROM configuration bit description .......... 230

Tab. 311. Limiting values .............................................. 231

Tab. 312. Operating conditions ..................................... 232

Tab. 313. Thermal characteristics HVQFN40 package . 232

Tab. 314. Thermal characteristics VFBGA64 package ..232

Tab. 315. Junction Temperature ....................................232

Tab. 316. Thermal Shutdown Temperature ................... 233

Tab. 317. Supply voltage ...............................................233

Tab. 318. Current consumption in active mode .............233

Tab. 319. Current consumption during power-saving modes ............................................................234

Tab. 320. Overcurrent detection function ...................... 234

Tab. 321. VEN pin .........................................................235

Tab. 322. GPIO (GPIO_0, GPIO_1, GPIO_2, GPIO_

3, GPIO4, GPIO5) pins ................................. 235

Tab. 323. CLK1, CLK2 pins .......................................... 235

Tab. 324. IRQ pin ..........................................................236

Tab. 325. SCLK, MOSI, NSS pins ................................ 236

Tab. 326. MISO pin ....................................................... 236

Tab. 327. RXp, RXn pins .............................................. 237

Tab. 328. TX1, TX2 pins ............................................... 237

Tab. 329. AUX1, AUX2, AUX3 pins (Debug output) ......237

Tab. 330. DAC_1, DAC_2 output pins (Tuning DAC) .... 237

Tab. 331. Power supply connection timing ....................238

Tab. 332. Pulse length .................................................. 239

Tab. 333. DAC1, DAC2 conversion timing (Tuning

DAC) ..............................................................239

Tab. 334. SPI interface ..................................................239

Tab. 335. RF_ON command timing following a previous RF_OFF ..........................................240

Tab. 336. Crystal requirements for ISO/IEC14443 compliant operation .......................................240

Tab. 337. Frequency requirements for a direct clock input (no crystal) ........................................... 240

Tab. 338. EEPROM characteristics ...............................241

Tab. 339. Package outline VFBGA64 (SOT1307-2) ......242

Tab. 340. Abbreviations .................................................293

Tab. 341. Revision history .............................................295

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Figures

Block diagram ................................................... 8

Pin configuration for VFBGA64 ......................... 9

Pin configuration for HVQFN40

(SOT2062-1) ....................................................13

Endianness examples ..................................... 18

Blocking capacitors ......................................... 21

Transmitter supply ...........................................22

Direct transmitter supply ................................. 23

Fig. 8.

Fig. 9.

Transmitter supply by DC-DC ......................... 23

DC-DC active .................................................. 24

Fig. 10.

DC-DC bypassed (in DCDC_PWR_

CONFIG) ......................................................... 24

Fig. 11.

No DC-DC used ..............................................25

Fig. 12.

No DC-DC used ..............................................25

Fig. 13.

No DC-DC used - no VDDPALDO .................. 26

Fig. 14.

Clocking by crystal .......................................... 27

Fig. 15.

System overview: DPC, AWC and ARC ..........30

Fig. 16.

System overview: DPC, AWC and ARC ..........31

Fig. 17.

System overview: DPC, AWC and ARC ..........31

Fig. 18.

System overview: DPC, AWC and ARC ..........32

Fig. 19.

Waveshaping transitions (example falling edge) ............................................................... 34

Fig. 20.

One linear transition (example falling edge) .... 35

Fig. 21.

Two linear transitions (example falling edge) ............................................................... 36

Fig. 22.

Three linear transitions (example falling edge) ............................................................... 36

Fig. 23.

Timer overview ................................................40

Fig. 24.

LPCD configuration and card detection loop ..................................................................41

Fig. 25.

LPCD configuration ......................................... 42

Fig. 26.

Autocall state machine ....................................45

Fig. 27.

Antenna connection using variable capacitors ........................................................ 47

Fig. 28.

Receiver block diagram ...................................47

Fig. 29.

Startup timing ................................................ 238

Fig. 30.

Package outline VFBGA64 (SOT1307-2) ......242

Fig. 31.

Package outline note VFBGA64

(SOT1307-2) ..................................................243

Fig. 32.

Package outline HVQFN40, SOT2062-1 .......244

Fig. 33.

Package outline detail HVQFN40,

SOT2062-1 ....................................................245

Fig. 34.

Marking VFBGA64 Package ......................... 246

Fig. 35.

Marking HVQFN40 package SOT2062-1 ...... 246

Fig. 36.

Reflow soldering footprint part1 for

VFBGA64 (SOT1307-2) ................................ 247

Fig. 37.

Reflow soldering footprint part2 for

VFBGA64 (SOT1307-2) ................................ 248

Fig. 38.

Reflow soldering footprint part3 for

VFBGA64 (SOT1307-2) ................................ 249

Fig. 39.

Soldering and footprint representative illustration for VFBGA64 (SOT1307-2) .......... 250

Fig. 40.

Package outline HVQFN40, SOT2062-1 .......251

Fig. 41.

Package outline HVQFN40, SOT2062-1 .......252

Fig. 42.

Package outline HVQFN40, SOT2062-1 .......253

Fig. 43.

Package outline HVQFN40, SOT2062-1 .......254

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NFC frontend

General description ............................................ 1

Features and benefits .........................................2

RF functionality ..................................................2

ISO/IEC14443-A ................................................ 2

ISO/IEC14443-B ................................................ 2

FeliCa .................................................................2

Tag type reading ................................................2

MIFARE card reading ........................................ 2

ISO/IEC 15693 .................................................. 2

Peer to peer ...................................................... 2

Host interface .................................................... 3

Applications .........................................................4

Firmware versions .............................................. 5

Quick reference data .......................................... 6

Ordering information .......................................... 7

Block diagram with VFBGA64 connections ......8

Pinning information ............................................ 9

Pin description VFBGA64 ..................................9

Pin description HVQFN40 ............................... 13

Functional description ......................................15

Functional overview .........................................15

Endianness ...................................................... 17

Initial calibration ...............................................18

System power states ....................................... 19

Power supply ................................................... 20

System power supply overview ....................... 20

Connecting blocking capacitors ....................... 21

Transmitter power supply ................................ 21

9.5.3.1

VDDPALDO transmitter supply ........................22

9.5.3.2

Direct transmitter supply ..................................22

9.5.3.3

DC-DC (boost) supply ..................................... 23

9.5.3.4

Configuration example 1: VDDPALDO transmitter supply - DC-DC active ................... 23

9.5.3.5

Configuration example 2: VDDPALDO transmitter supply - DC-DC bypassed ............. 24

9.5.3.6

Configuration example 3: VDDPALDO transmitter supply connected to VBAT - no

DC-DC ............................................................. 24

9.5.3.7

Configuration example 4: VDDPALDO supplied independent from VBAT - no DC-

DC ....................................................................25

9.5.3.8

Configuration example 5: VDDPALDO not used - no DC-DC ............................................ 25

9.5.3.9

Supply voltage range for transmitter supply

9.6

9.7

9.8

configuration examples ....................................27

Clock generation ..............................................27

External interfaces ...........................................27

Transmitter overcurrent and temperature

protection ......................................................... 28

Loading a dedicated RF configuration ............. 28

Dynamic power control (DPC) ......................... 28

DPC algorithm ................................................. 32

DPC characteristics ......................................... 33

Adaptive waveshape control (AWC) ................ 34

Adaptive receiver control (ARC) ...................... 36

Timer ................................................................39

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Low-power card detection ............................... 40

Low-power card detection (LPCD) ...................41

Semi-autonomous mode (LPCD) .....................43

Automatic EMD error handling ........................ 44

Autocoll (card emulation) .................................44

RF-level detection ............................................46

Antenna tuning with variable capacitors .......... 46

RF debug signals ............................................ 47

Secure firmware update .................................. 49

SPI host interface ............................................ 50

Host interface commands ................................51

Logical command layer ....................................51

9.22.1.1 Logical frame definition ....................................51

9.22.1.2 Logical flow definition ...................................... 51

9.22.1.3 Logical message type definition ...................... 51

9.22.1.4 Logical message format .................................. 52

9.22.1.5 Split frame definition ........................................52

9.22.2

9.22.3

9.22.4

Host interface command list ............................ 52

Command WRITE_REGISTER (00h) .............. 54

9.22.5

9.22.6

Command WRITE_REGISTER_OR_MASK

(01h) .................................................................54

Command WRITE_REGISTER_AND_

MASK (02h) ..................................................... 55

Command WRITE_REGISTER_MULTIPLE

(03h) .................................................................55

Command READ_REGISTER (04h) ................56

Command READ_REGISTER_MULTIPLE

9.22.7

9.22.8

9.22.9

(05h) .................................................................57

Command WRITE_EEPROM (06h) .................58

9.22.10 Command READ_EEPROM (07h) .................. 59

9.22.11

Command TRANSMIT_RF_DATA (08h) ..........59

9.22.12 Command RETRIEVE_RF_DATA (09h) .......... 60

9.22.13 Command EXCHANGE_RF_DATA (0Ah) ........60

9.22.14 Command MFC_AUTHENTICATE (0Bh) .........62

9.22.15 Command EPC_GEN2_INVENTORY (0Ch) ....63

9.22.16 Command LOAD_RF_CONFIGURATION

(0Dh) ................................................................65

9.22.16.1 Parameter for command LOAD_RF_

CONFIGURATION ........................................... 66

9.22.17 Command UPDATE_RF_

CONFIGURATION (0Eh) ................................. 68

9.22.18 Command GET_ RF_CONFIGURATION

(0Fh) ................................................................ 69

9.22.19 Command RF_ON (10h) ................................. 70

9.22.20 Command RF_OFF (11h) ................................70

9.22.21 Command CONFIGURE_ TESTBUS_

DIGITAL (12h) ..................................................71

9.22.22 Command CONFIGURE_TESTBUS_

ANALOG (13h) ................................................ 72

9.22.23 Command CTS_ENABLE (14h) ...................... 72

9.22.24 Command CTS_CONFIGURE (15h) ............... 73

9.22.25 Command CTS_RETRIEVE_LOG (16h) ......... 77

9.22.26 Command RECEIVE_RF_DATA (1Ah) ............ 77

9.22.27 Command SWITCH_MODE_NORMAL

(20h) .................................................................78

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NXP Semiconductors PN5190

NFC frontend

9.22.28 Command SWITCH_MODE_AUTOCOLL

(21h) .................................................................79

9.22.29 Command SWITCH_MODE_STANDBY

(22h) .................................................................81

9.22.30 Command SWITCH_MODE_LPCD (23h) ........81

9.22.31 Command SWITCH_MODE_DOWNLOAD

(25h) .................................................................82

9.22.32 Command GET_DIE_ID (26h) .........................83

9.22.33 Command GET_VERSION (27h) .................... 83

9.22.34 Command PRBS_TEST (41h) .........................84

9.22.35 RESPONSE STATUS CODES ........................ 85

9.22.36 EVENTS INDICATED BY INTERRUPT ........... 87

9.22.37 EVENTS INDICATED ON GPIO ......................88

SYSTEM_CONFIG (0000h) .............................91

EVENT_ENABLE (0001h) ............................... 91

EVENT_STATUS (0002h) ................................92

EMVCO_EMD_CONTROL (0003h) .................92

FELICA_EMD_CONTROL (0004h) ................. 93

RX_STATUS (0005h) .......................................94

RX_STATUS_ERROR (0006h) ........................95

CLIF_STATUS (0007h) ....................................97

9.23.9

9.23.10 RF_EXCHANGE_CONTROL (0008h) ............. 98

9.23.11

TX_SYMBOL01_MOD (0009h) ........................99

9.23.12 TX_SYMBOL1_DEF (000Ah) .......................... 99

9.23.13 TX_SYMBOL0_DEF (000Bh) ........................ 100

9.23.14 TX_SYMBOL23_MOD (000Ch) ..................... 100

9.23.15 TX_SYMBOL23_DEF (000Dh) ...................... 100

9.23.16 TX_SYMBOL_CONFIG (000Eh) ....................100

9.23.17 TX_FRAME_CONFIG (000Fh) ...................... 101

9.23.18 TX_DATA_MOD (0010h) ............................... 102

9.23.19 TX_WAIT (0011h) .......................................... 103

9.23.20 TX_CRC_CONFIG (0012h) ........................... 104

9.23.21 SS_TX_CONFIG (00015h) ............................ 104

9.23.22 SS_TX1_RMCFG (00016h) ...........................105

9.23.23 SS_TX2_RMCFG (00017h) ...........................105

9.23.24 SS_TX_TRANS_CFG (00019h) .................... 106

9.23.25 SIGPRO_RM_PATTERN (0020h) ..................106

9.23.26 SIGPRO_RM_TECH (0022h) ........................ 106

9.23.27 RX_FRAME_LENGTH (0026h) ..................... 107

9.23.28 RX_ERROR_CONFIG (0027h) ......................107

9.23.29 RX_CTRL_STATUS (0028h) ......................... 107

9.23.30 SIGPRO_IIR_CONFIG0 (0002Ah) .................108

9.23.31 DGRM_RSSI (0030h) .................................... 108

9.23.32 RX_CRC_CONFIG (0031h) ...........................108

9.23.33 RX_WAIT (0032h) ......................................... 109

9.23.34 RXM_CTRL (0035h) ......................................110

9.23.35 SS_TX1_CMCFG (0003Bh) ...........................110

9.23.36 SS_TX2_CMCFG (0003Ch) .......................... 110

9.23.37 TIMER0_CONFIG (003Dh) ............................110

9.23.38 TIMER0_RELOAD (003Eh) ........................... 111

9.23.39 TIMER1_CONFIG (003Fh) ............................ 111

9.23.40 TIMER1_RELOAD (0040h) ............................113

9.23.41 EMD_1_CFG (0047h) ....................................113

9.23.42 EMD_0_CONFIG (0048h) ............................. 113

9.23.43 LPCD_CALIBRATE_CTRL (00050h) .............114

9.23.44 IQ_CHANNEL_VALS (00051h) ......................114

9.23.45 PAD_CONFIG (0052h) .................................. 114

PN5190B1

Product data sheet

COMPANY PUBLIC

9.23.46 CALIBRATE_STATUS (00053h) .................... 115

9.23.47 TXLDO_VDDPA_CONFIG (00054h) ..............115

9.23.48 GENERAL_ERROR_STATUS (0055h) ..........116

9.23.49 TXLDO_VOUT_CURR (0056h) ..................... 116

9.23.50 CLIF_DAC (00057h) ......................................117

9.23.51 PMU_ANA_SMPS_CTRL_REG (00058h) ..... 118

9.23.52 RXM_FREQ (00059h) ................................... 118

9.23.53 RXM_RSSI (0005Ah) .....................................118

9.23.54 TEMP_SENSOR (005Bh) ..............................119

9.23.55 TX_NOV_CALIBRATE (005Dh) .....................119

9.23.56 SS_TX1_RTRTRANS0 (00080h) ...................119

9.23.57 SS_TX1_RTRTRANS1 (00081h) ...................119

9.23.58 SS_TX1_RTRTRANS2 (00082h) ...................120

9.23.59 SS_TX1_RTRTRANS3 (00083h) ...................120

9.23.60 SS_TX2_RTRTRANS0 (00084h) ...................120

9.23.61 SS_TX2_RTRTRANS1 (00085h) ...................120

9.23.62 SS_TX2_RTRTRANS2 (00086h) ...................121

9.23.63 SS_TX2_RTRTRANS3 (00087h) ...................121

9.23.64 SS_TX1_FTRTRANS0 (00088h) ................... 121

9.23.65 SS_TX1_FTRTRANS1 (00089h) ................... 121

9.23.66 SS_TX1_FTRTRANS2 (0008Ah) ...................121

9.23.67 SS_TX1_FTRTRANS3 (0008Bh) ...................122

9.23.68 SS_TX2_FTRTRANS0 (0008Ch) ...................122

9.23.69 SS_TX2_FTRTRANS1 (0008Dh) ...................122

9.23.70 SS_TX2_FTRTRANS2 (0008Eh) ...................122

9.23.71 SS_TX2_FTRTRANS3 (0008Fh) ...................123

9.24

9.24.1

EEPROM configuration description ............... 123

EEPROM configuration overview ...................123

DCDC_PWR_CONFIG (0000h) .....................129

DCDC_CONFIG (0001h) ............................... 129

TXLDO_CONFIG (0002h) ..............................130

TXLDO_VDDPA_HIGH (0006h) .................... 131

TXLDO_VDDPA_LOW (0007h) ..................... 132

TXLDO_VDDPA_MAX_RDR (0008h) ............133

TXLDO_VDDPA_MAX_CARD (0009h) ..........134

BOOST_DEFAULT_VOLTAGE (000Ah) ........ 135

9.24.10 XTAL_CONFIG (0010h) .................................135

9.24.11

XTAL_TIMEOUT (0011h) ...............................136

9.24.12 CLK_INPUT_FREQ (0012h) ..........................136

9.24.13 XTAL_CHECK_DELAY (0013h) .....................136

9.24.14 TEMP_WARNING (0014h) ............................ 137

9.24.15 ENABLE_GPIO0_ON_OVERTEMP

(0016h) ...........................................................137

9.24.16 RESIDUAL_AMPL_LEVEL_A106 (0022h) .... 137

9.24.17 EDGE_TYPE_A106 (0023h) ..........................138

9.24.18 EDGE_STYLE_A106 (0024h) ........................138

9.24.19 EDGE_LENGTH_A106 (0025h) .................... 139

9.24.20 RESIDUAL_AMPL_LEVEL_A212 (0026h) .... 139

9.24.21 EDGE_TYPE_A212 (0027h) ..........................139

9.24.22 EDGE_STYLE_A212 (0028h) ........................140

9.24.23 EDGE_LENGTH_A212 (0029h) .................... 140

9.24.24 RESIDUAL_AMPL_LEVEL_A424 (002Ah) .... 141

9.24.25 EDGE_TYPE_A424 (002Bh) ......................... 141

9.24.26 EDGE_STYLE_A424 (002Ch) .......................141

9.24.27 EDGE_LENGTH_A424 (002Dh) ....................142

9.24.28 RESIDUAL_AMPL_LEVEL_A848 (002Eh) .... 142

9.24.29 EDGE_TYPE_A848 (002Fh) ......................... 143

9.24.30 EDGE_STYLE_A848 (0030h) ........................143

9.24.31 EDGE_LENGTH_A848 (0031h) .................... 144

All information provided in this document is subject to legal disclaimers.

Rev. 3.0 — 21 April 2021

662230 306 / 308

NXP Semiconductors PN5190

NFC frontend

9.24.32 RESIDUAL_AMPL_LEVEL_B106 (0032h) .... 144

9.24.33 EDGE_TYPE_B106 (0033h) ..........................144

9.24.34 EDGE_STYLE_B106 (0034h) ........................145

9.24.35 EDGE_LENGTH_B106 (0035h) .................... 145

9.24.36 RESIDUAL_AMPL_LEVEL_B212 (0036h) .... 146

9.24.37 EDGE_TYPE_B212 (0037h) ..........................146

9.24.38 EDGE_STYLE_B212 (0038h) ........................146

9.24.39 EDGE_LENGTH_B212 (0039h) .................... 147

9.24.40 RESIDUAL_AMPL_LEVEL_B424 (003Ah) .... 147

9.24.41 EDGE_TYPE_B424 (003Bh) ......................... 148

9.24.42 EDGE_STYLE_B424 (003Ch) .......................148

9.24.43 EDGE_LENGTH_B424 (003Dh) ....................149

9.24.44 RESIDUAL_AMPL_LEVEL_B848 (003Eh) .... 149

9.24.45 EDGE_TYPE_B848 (003Fh) ......................... 149

9.24.46 EDGE_STYLE_B848 (0040h) ........................150

9.24.47 EDGE_LENGTH_B848 (0041h) .................... 150

9.24.48 RESIDUAL_AMPL_LEVEL_F212 (0042h) .....151

9.24.49 EDGE_TYPE_F212 (0043h) ..........................151

9.24.50 EDGE_STYLE_F212 (0044h) ........................151

9.24.51 EDGE_LENGTH_F212 (0045h) .....................152

9.24.52 RESIDUAL_AMPL_LEVEL_F424 (0046h) .....152

9.24.53 EDGE_TYPE_F424 (0047h) ..........................153

9.24.54 EDGE_STYLE_F424 (0048h) ........................153

9.24.55 EDGE_LENGTH_F424 (0049h) .....................154

9.24.56 RESIDUAL_AMPL_LEVEL_V100_26

(004Ah) .......................................................... 154

9.24.57 EDGE_TYPE_V100_26 (004Bh) ................... 154

9.24.58 EDGE_STYLE_V100_26 (004Ch) ................. 155

9.24.59 EDGE_LENGTH_V100_26 (004Dh) ..............155

9.24.60 RESIDUAL_AMPL_LEVEL_V100_53

(004Eh) .......................................................... 156

9.24.61 EDGE_TYPE_V100_53 (004Fh) ................... 156

9.24.62 EDGE_STYLE_V100_53 (0050h) ..................156

9.24.63 EDGE_LENGTH_V100_53 (0051h) .............. 157

9.24.64 RESIDUAL_AMPL_LEVEL_V100_106

(0052h) ...........................................................157

9.24.65 EDGE_TYPE_V100_106 (0053h) ..................158

9.24.66 EDGE_STYLE_V100_106 (0054h) ................158

9.24.67 EDGE_LENGTH_V100_106 (0055h) .............159

9.24.68 RESIDUAL_AMPL_LEVEL_100_212

(0056h) ...........................................................159

9.24.69 EDGE_TYPE_V100_212 (0057h) ..................159

9.24.70 EDGE_STYLE_V100_212 (0058h) ................160

9.24.71 EDGE_LENGTH_V100_212 (0059h) .............160

9.24.72 RESIDUAL_AMPL_LEVEL_V10_26

(005Ah) .......................................................... 161

9.24.73 EDGE_TYPE_V10_26 (005Bh) ..................... 161

9.24.74 EDGE_STYLE_V10_26 (005Ch) ................... 161

9.24.75 EDGE_LENGTH_V10_26 (005Dh) ................162

9.24.76 RESIDUAL_AMPL_LEVEL_V10_53

(005Eh) .......................................................... 162

9.24.77 EDGE_TYPE_V10_53 (005Fh) ..................... 163

9.24.78 EDGE_STYLE_V10_53 (0060h) ....................163

9.24.79 EDGE_LENGTH_V10_53 (0061h) ................ 164

9.24.80 RESIDUAL_AMPL_LEVEL_V10_106

(0062h) ...........................................................164

9.24.81 EDGE_TYPE_V10_106 (0063h) ....................164

9.24.82 EDGE_STYLE_V10_106 (0064h) ..................165

9.24.83 EDGE_LENGTH_V10_106 (0065h) .............. 165

PN5190B1

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.0 — 21 April 2021

662230

9.24.84 RESIDUAL_AMPL_LEVEL_V10_212

(0066h) ...........................................................166

9.24.85 EDGE_TYPE_V10_212 (0067h) ....................166

9.24.86 EDGE_STYLE_V10_212 (0068h) ..................166

9.24.87 EDGE_LENGTH_V10_212 (0069h) .............. 167

9.24.88 RESIDUAL_AMPL_LEVEL_180003m3_ tari18p88 (006Ah) ..........................................167

9.24.89 EDGE_TYPE_180003m3_tari18p88

(006Bh) .......................................................... 168

9.24.90 EDGE_STYLE_180003m3_tari18p88

(006Ch) ..........................................................168

9.24.91 EDGE_LENGTH_180003m3_tari18p88

(006Dh) ..........................................................169

9.24.92 RESIDUAL_AMPL_LEVEL_180003m3_ tari9p44 (006Eh) ............................................169

9.24.93 EDGE_TYPE_180003m3_tari9p44 (006Fh) .. 169

9.24.94 EDGE_STYLE_180003m3_tari9p44

(0070h) ...........................................................170

9.24.95 EDGE_LENGTH_180003m3_tari9p44

(0071h) ...........................................................170

9.24.96 RESIDUAL_AMPL_LEVEL_B_PRIME_106

(0072h) ...........................................................171

9.24.97 EDGE_TYPE_B_PRIME_106 (0073h) .......... 171

9.24.98 EDGE_STYLE_B_PRIME_106 (0074h) ........ 171

9.24.99 EDGE_LENGTH_B_PRIME_106 (0075h) ..... 172

9.24.100 DPC_CONFIG (0076h) ..................................172

9.24.101 DPC_TARGET_CURRENT (077h) ................ 173

9.24.102 DPC_HYSTERESIS_LOADING (079h) ......... 173

9.24.103 DPC_HYSTERESIS_UNLOADING (07Ch) ... 173

9.24.104 DPC_TXLDOVDDPALow (007Dh) .................174

9.24.105 DPC_TXGSN (007Eh) ................................... 174

9.24.106 DPC_RDON_Control (007Fh) ........................174

9.24.107 DPC_InitialRDOn_RFOn (0080h) .................. 174

9.24.108 DPC_GUARD_TIME (087h) .......................... 174

9.24.109 DPC_ENABLE_DURING_FDT (088h) ...........175

9.24.110 DPC_GUARD_TIME_AFTER_RX (089h) ......175

9.24.111 DPC_LOOKUP_TABLE (008Bh-0133h) ........ 175

9.24.112 ARC_CONFIG (0137h) ..................................176

9.24.113 ARC_VDDPA (0139h) ....................................176

9.24.114 ARC_RM_A106 (013Eh) ............................... 177

9.24.115 ARC_RM_A212 (0148h) ................................179

9.24.116 ARC_RM_A424 (0152h) ................................180

9.24.117 ARC_RM_A848 (015Ch) ............................... 182

9.24.118 ARC_RM_B106 (0166h) ................................183

9.24.119 ARC_RM_B212 (0170h) ................................185

9.24.120 ARC_RM_B424 (017Ah) ............................... 186

9.24.121 ARC_RM_B848 (0184h) ................................188

9.24.122 ARC_RM_F212 (018Eh) ................................189

9.24.123 ARC_RM_F424 (0198h) ................................ 191

9.24.124 ARC_RM_V_6p6 (01A2h) ............................. 192

9.24.125 ARC_RM_V_26 (01ACh) ...............................194

9.24.126 ARC_RM_V53 (01B6h) ................................. 195

9.24.127 ARC_RM_V106 (01C0h) ............................... 197

9.24.128 ARC_RM_V212 (01CAh) ...............................198

9.24.129 ARC_RM_180003m3_SC424_4Man

(01D4h) ..........................................................200

9.24.130 ARC_RM_180003m3_SC424_2Man

(01DEh) ..........................................................201

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9.24.131 ARC_RM_180003m3_SC848_4Man

(01E8h) .......................................................... 203

9.24.132 ARC_RM_180003m3_SC848_2Man

(01F2h) .......................................................... 204

9.24.133 ARC_RM_AI106 (01FCh) .............................. 206

9.24.134 ARC_RM_AI212 (0206h) ...............................207

9.24.135 ARC_RM_AI424 (0210h) ...............................209

9.24.136 RF_DEBOUNCE_TIMEOUT (02B2h) ............210

9.24.137 SENSE_RES (02B3h) ................................... 211

9.24.138 NFC_ID1 (02B5h) ..........................................211

9.24.139 SEL_RES (02B8h) .........................................211

9.24.140 FELICA_POLL_RES (02B9h) ........................211

9.24.141 RANDOM_UID_ENABLE (02CBh) ................ 212

9.24.142 MFC_AUTH_TIMEOUT (02CCh) ...................212

9.24.143 RSSI_TIMER (02DAh) ...................................212

9.24.144 RSSI_TIMER_FIRST_PERIOD (02DCh) .......212

9.24.145 RSSI_CTRL_00_AB (02DEh) ........................212

9.24.146 RSSI_NB_ENTRIES_AB (02DFh) ................. 213

9.24.147 RSSI_THRESHOLD_PHASE_TABLE

(02E0h) .......................................................... 213

9.24.148 TX_PARAM_ENTRY_TABLE (03A2h) ...........214

9.24.149 LPCD_AVG_SAMPLES (0492h) ....................217

9.24.150 LPCD_RSSI_TARGET (0494h) ..................... 218

9.24.151 LPCD_RSSI_HYST (0496h) ..........................218

9.24.152 LPCD_CONFIG (0497h) ................................218

9.24.153 LPCD_THRESHOLD_COARSE (049Ah) ...... 219

9.24.154 LPCD_VDDPA (04B5h) ................................. 220

9.24.155 ULPCD_VDDPA_CTRL (04BFh) ................... 221

9.24.156 ULPCD_TIMING_CTRL (04C2h) ...................222

9.24.157 ULPCD_VOLTAGE_CTRL (04C6h) ............... 222

9.24.158 ULPCD_RSSI_GUARD_TIME (04C9h) .........222

9.24.159 ULPCD_RSSI_SAMPLE_CFG (04CAh) ........222

9.24.160 ULPCD_THRESH_LVL(04CBh) .....................223

9.24.161 ULPCD_GPIO3 (04CCh) ............................... 223

9.24.162 TXIRQ_GuardTime (0559h) ...........................223

9.24.163 FDT_default_val (055Dh) .............................. 223

9.24.164 RXIRQ_GuardTime (0561h) .......................... 223

9.24.165 NFCLD_RFLD_Valid (006D3h) ......................224

9.24.166 CurrentSensorTrimConfig (0ABCh) ............... 224

9.24.167 CORRECTION_ENTRY_TABLE (0BDAh) .....224

9.24.168 RTRANS_FTRANS_TABLE (0C03h) .............226

9.24.169 CFG_NOV_CAL (0C83h) .............................. 227

9.24.170 NOV_CAL_VAL1 (0C84h) ..............................227

9.24.171 NOV_CAL_VAL2 (0C85h) ..............................227

9.24.172 NOV_CAL_THRESHOLD (0C86h) ................ 228

9.24.173 NOV_CAL_OFFSET1 (0C87h) ...................... 228

9.24.174 NOV_CAL_OFFSET2 (0C8Bh) ......................228

9.24.175 VDDPA_DISCHARGE (0C8Fh) ..................... 228

9.24.176 ARC_RM_A106_FDT (0C9Dh) ......................228

9.24.177 Tx_Symbol23_Mod_Reg_BR_53 (0CC5h) .... 230

9.24.178 Tx_Data_Mod_Reg_BR_53 (0CC9h) ............ 230

9.24.179 Tx_Symbol23_Mod_Reg_BR_106 (0CCDh) . 230

9.24.180 Tx_Data_Mod_Reg_BR_106 (0CD1h) .......... 230

9.24.181 Tx_Symbol23_Mod_Reg_BR_212 (0CD5h) ..230

9.24.182 Tx_Data_Mod_Reg_BR_212 (0CD9h) .......... 230

10 Limiting values ................................................231

Characteristics ................................................ 232

Thermal characteristics ..................................232

Static characteristics ......................................233

Timing characteristics .................................... 237

Clock input .....................................................240

EEPROM characteristics ............................... 241

Package outline ...............................................242

VFBGA64 package ........................................242

HVQFN40 package ........................................244

Package marking .............................................246

Package marking drawing VFBGA64 ............ 246

Package marking drawing HVQFN40 ............ 246

Reflow soldering footprint VFBGA64 ............ 247

Reflow soldering footprint HVQFN40 ............ 251

Surface mount reflow soldering .................... 255

Handling information ...................................... 256

Appendix: EEPROM LOAD_RF_

CONFIGURATION FW2.0 .................................257

Appendix: EEPROM LOAD_RF_

CONFIGURATION FW2.1 .................................275

Abbreviations .................................................. 293

References .......................................................294

Revision history .............................................. 295

Legal information ............................................296

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 21 April 2021

Document identifier: PN5190B1

Document number: 662230

Hi there! I've finished reading the NXP PN5190 NFC frontend datasheet. I can answer your questions about this high-power NFC IC, including its features (like DPC and AWC), applications, firmware versions, and detailed specifications. The document also covers its pinouts and EEPROM configuration.

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Key features

Supports all major NFC protocols
Complies with the NFC Forum specifications
Integrated RF transceiver, host interface, and power management unit
Supports peer-to-peer communication
Can be used in a variety of applications, including payment, physical access, and eGov
RF operating modes:
- ISO/IEC14443-A
- ISO/IEC14443-B
- FeliCa
- ISO/IEC 15693

Frequently asked questions

The PN5190 requires a supply voltage of 2.4 V to 5.5 V on the VBAT pin and a supply voltage of 1.62 V to 1.98 V on the VDDIO pin.

The PN5190 supports data rates up to 848 kbit/s.

The PN5190 supports all types of NFC cards, including MIFARE Classic, MIFARE Ultralight, MIFARE DESFire, and FeliCa cards.

The PN5190 has a host interface based on SPI.

NFC frontend

1 General description

2 Features and benefits

3 Applications

4 Firmware versions

5 Quick reference data

6 Ordering information

7 Block diagram with VFBGA64 connections

8 Pinning information

9 Functional description

10 Limiting values

11 Characteristics

12 Package outline

13 Package marking

14 Reflow soldering footprint VFBGA64

15 Reflow soldering footprint HVQFN40

16 Surface mount reflow soldering

17 Handling information

18 Appendix: EEPROM LOAD_RF_CONFIGURATION FW2.0

19 Appendix: EEPROM LOAD_RF_CONFIGURATION FW2.1

20 Abbreviations

21 References

22 Revision history

23 Legal information

Tables

Figures

Contents

What are the power supply requirements for the PN5190?

What is the maximum data rate supported by the PN5190?

What types of cards does the PN5190 support?

What is the host interface for the PN5190?

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