Below you will find brief information for CMT2300A-EQR. This ultra-low power sub-1GHz RF transceiver is suited for applications from 127 to 1020 MHz. It supports OOK, (G)FSK and (G)MSK modulation. Key features include a configurable packet handler, 64-byte FIFO, and low power consumption, which helps the performance of the application. It is suitable for automatic meter reading, home security, and industrial control.
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CMT2300A
CMT2300A
Frequency range: 127 ~1020MHz
Modem:
Data rate:
OOK, (G)FSK 和
0.5 ~ 300 kbps
(G)MSK
Sensitivity: -121 dBm 2.0 kbps, F
RF
= 433.92 MHz
-111 dBm 50 kbps, F
RF
= 433.92 MHz
Voltage range: 1.8 ~3.6 V
Transmit current: 23 mA @ 13 dBm, 433.92 MHz, FSK
72 mA @ 20 dBm, 433.92 MHz, FSK,
Rx current: 8.5 mA @ 433.92 MHz, FSK (High power mode)
7.2 mA @ 433.92 MHz, FSK (Low power mode)
Super Low Power receive mode
Sleep current: 300 nA, Duty Cycle = OFF
Fast and stable automatic frequency control (AFC)
3 types of clock data recovery system (CDR)
Fast and accurate signal detection (PJD)
4-wire SPI interface
800 nA, Duty Cycle = ON
Receiver Features:
Direct and packet mode supported
Configurable packet handler and 64-Byte FIFO.
NRZ, Manchester codec, Whitening codec, Forward Error
Automatic meter reading
Home security and building automation
ISM band data communication
Industrial monitoring and control
Remote control and security system
Remote key entry
Wireless sensor node
Tag reader
Model Frequency Package
CMT2300A-EQR 433.92 MHz QFN16
For more information, see Page 42 Table 23.
MOQ
3,000 pcs
Correction (FEC)
:
CMT2300A is an ultra-low power, high performance, OOK (G)
FSK RF transceiver suitable for a variety of 140 to 1020 MHz wireless applications. It is part of the CMOSTEK NextGenRF TM
RF product line. The product line contains the complete transmitters, receivers and transceivers.The high integration of
CMT2300A simplifies the peripheral materials required in the system design. Up to +20 dBmTx Power and -121 dBm sensitivity optimize the performance of the application. It supports a variety of packet formats and codec methodsto meet the needs of various different applications.In addition,
CMT2300A also supports64-byte Tx/Rx FIFO, GPIO and interrupt configuration, Duty-Cycle operation mode, channel sensing, high-precision RSSI, low-voltage detection, power-on reset, low frequency clock output, manual fast frequency hopping, squelch and etc. The features make the application design more flexible and differentiated. CMT2300A operates from 1.8 V to 3.6 V. Only 8.5 mA current is consumed when the sensitivity is -121 dBm, SuperLow Power mode can further reduce the chip power consumption. Only 23mA Txcurrent is consumed when the output power is 13dBm.
RFIP
RFIN
PA
AVDD
1
2
3
4
5
QFN16 (3 X 3)
16 15
6
17
GND
14
7
13
8
12
11
10
9
CMT2300A top view
FCSB
CSB
SDIO
SCLK
Copyright © By CMOSTEK Rev 1.0 | Page1/46 www.cmostek.com
CMT2300A
Rev 1.0 | Page2/46 www.cmostek.com
CMT2300A
Rev 1.0 | Page3/46 www.cmostek.com
CMT2300A
V
DD
= 3.3 V, T
OP
= 25 °C, F
RF
= 433.92 MHz, the sensitivity is measured by receiving a PN9 coded data and matching the impedance to 50Ωunder the 0.1%BER standard.Unless otherwise stated, all results are tested on theCMT2300A-EM evaluation board.
Parameter
Power voltage
Operating temperature
Power voltage slope
Symbol
V
DD
T
OP
Condition
[1]
Min.
1.8
-40
1
Typ. Max.
3.6
85
Unit
V
℃ mV/us
Parameter Symbol Conditions Min Max Unit
Supply Voltage
Interface Voltage
Junction Temperature
Storage Temperature
Soldering Temperature
ESD Rating [2]
Latch-up Current
V
DD
V
IN
T
J
T
STG
T
SDR
Lasts at least 30 seconds
Human Body Model (HBM)
@ 85 ℃
-0.3
-0.3
-40
-50
-2
-100
3.6
V
DD
+0.3
125
150
255
2
100
V
V
℃
℃
℃ kV mA
Notes:
[1]. Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating
[2]. conditions for extended periods may affect device reliability.
Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.
Rev 1.0 | Page4/46 www.cmostek.com
CMT2300A
Parameter
Sleepcurrent
Standbycurrent
RFScurrent
TFScurrent
RXcurrent(high powermode)
RXcurrent(low power mode)
TXcurrent
Symbol
I
I
I
I
SLEEP
Standby
I
I
Rx-HP
Rx-LP
I
RFS
TFS
Tx
Condition
Sleep mode, sleep timeris off
Sleep mode, sleep timeris on
Crystal oscillatoris on
433 MHz
868 MHz
915 MHz
433 MHz
868 MHz
915 MHz
FSK, 433 MHz, 10 kbps,10 kHz F
DEV
FSK, 868 MHz, 10 kbps, 10 kHz F
DEV
FSK, 915 MHz, 10 kbps,10 kHz F
DEV
FSK, 433 MHz, 10 kbps, 10 kHz F
DEV
FSK, 868 MHz, 10 kbps, 10 kHz F
DEV
FSK, 915 MHz, 10 kbps, 10 kHz F
DEV
FSK, 433 MHz, +20 dBm (Direct Tie)
FSK, 433 MHz, +20 dBm (RF switch)
FSK, 433 MHz, +13 dBm (Direct Tie)
FSK, 433 MHz, +10 dBm (Direct Tie)
FSK, 433 MHz, -10 dBm(Direct Tie)
FSK, 868 MHz, +20 dBm(Direct Tie)
FSK, 868 MHz, +20 dBm(RF switch)
FSK, 868 MHz, +13 dBm (Direct Tie)
FSK, 868 MHz, +10 dBm (Direct Tie)
FSK, 868 MHz, -10 dBm (Direct Tie)
FSK, 915 MHz, +20 dBm (Direct Tie)
FSK, 915 MHz, +20 dBm (RF switch)
FSK, 915 MHz, +13 dBm (Direct Tie)
FSK, 915 MHz, +10 dBm (Direct Tie)
FSK, 915 MHz, -10 dBm (Direct Tie)
Min. Typ. Max. Unit
300
800
1.45
5.7 nA nA mA mA
5.8
5.8 mA mA
5.6
5.9 mA mA
5.9
8.5
8.6
8.9
7.2
7.3
7.6
72
77
23
18 mA mA mA mA mA mA mA mA mA mA mA
8
87 mA mA
80
27
19
8
70 mA mA mA mA mA
75
28 mA mA
19
8 mA mA
Rev 1.0 | Page5/46 www.cmostek.com
CMT2300A
Parameter
Data rate
Deviation
Sensitivity
@ 433 MHz
Sensitivity
@ 868 MHz
Sensitivity
@ 915 MHz
Saturation Input Signal
Level
Symbol
S
S
S
F
DR
DEV
433-HP
868-HP
915-HP
Condition
OOK
FSK and GFSK
FSK and GFSK
DR = 2.0 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz （ Low power setting ）
DR = 20 kbps, F
DEV
= 20 kHz
DR = 20 kbps, F
DEV
= 20 kHz （ Low power setting ）
DR = 50 kbps, F
DEV
= 25 kHz
DR =100 kbps, F
DEV
= 50 kHz
DR =200 kbps, F
DEV
= 100 kHz
DR =300 kbps, F
DEV
= 100 kHz
DR = 2.0 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz （ Low power setting ）
DR = 20 kbps, F
DEV
= 20 kHz
DR = 20 kbps, F
DEV
= 20 kHz （ Low power setting ）
DR = 50 kbps, F
DEV
= 25 kHz
DR =100 kbps, F
DEV
= 50 kHz
DR =200 kbps, F
DEV
= 100 kHz
DR =300 kbps, F
DEV
= 100 kHz
DR = 2.0 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz （ Low power mode ）
DR = 20 kbps, F
DEV
= 20 kHz
DR = 20 kbps, F
DEV
= 20 kHz （ Low power mode ）
DR = 50 kbps, F
DEV
= 25 kHz
DR =100 kbps, F
DEV
= 50 kHz
DR =200 kbps, F
DEV
= 100 kHz
DR =300 kbps, F
DEV
= 100 kHz
P
LVL
Min.
0.5
0.5
2
Image Rejection Ratio
RX Channel
Bandwidth
Co-channel Rejection
Ratio
Adjacent Channel
Rejection Ratio
IMR
BW
CCR
ACR-I
F
RF
=433 MHz
F
RF
=868 MHz
F
RF
=915 MHz
RX channel bandwidth
DR = 10 kbps, F
DEV
= 10 kHz; Interference with the same modulation
DR = 10 kbps, F
DEV
= 10 kHz; BW=100kHz, 200 kHzChannel spacing, interference with the same modulation
50
35
33
33
-108
-105
-102
-99
-117
-113
-111
-111
-109
-109
-105
-102
--99
-121
-116
-115
-113
-112
-111
-108
-105
--103
-119
Typ. Max. Unit
40
300
200 kbps kbps kHz dBm dBm dBm dBm dBm
-113
-111
-111
-109 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
20
500 dBm dBc dBc dBc kHz
-7
30 dBc dBc
Rev 1.0 | Page6/46 www.cmostek.com
CMT2300A
Parameter
AlternateChannel
Rejection Ratio
Blocking Rejection
Ratio
Input 3 rd Order
Intercept Point
RSSIRange
More Sensitivity
(Typical Configuration)
Symbol Condition
ACR-II
BI
IIP3
RSSI
DR = 10 kbps, F
DEV
= 10 kHz; BW=100kHz, 400 kHzChannel spacing, interference with the same modulation
DR = 10 kbps, F
DEV
= 10 kHz; ±1 MHzDeviation, continuous wave interference
DR = 10 kbps, F
DEV
= 10 kHz; ± 2 MHzDeviation, continuous wave interference
DR = 10 kbps, F
DEV
= 10 kHz; ±10 MHzDeviation, continuous wave interference
DR = 10 kbps, F
DEV
= 10 kHz; 1 MHz and 2 MHz
Deviation dual tone test, maximum system gain setting.
433.92 MHz, DR = 1.2kbps, F
DEV
= 5 kHz
433.92 MHz, DR = 1.2kbps, F
DEV
= 10 kHz
433.92 MHz, DR = 1.2kbps, F
DEV
= 20 kHz
433.92 MHz, DR = 2.4kbps, F
DEV
= 5 kHz
433.92 MHz, DR = 2.4kbps, F
DEV
= 10 kHz
433.92 MHz, DR = 2.4kbps, F
DEV
= 20 kHz
433.92 MHz, DR = 9.6 kbps, F
DEV
= 9.6 kHz
433.92 MHz, DR = 9.6 kbps, FDEV = 19.2 kHz
433.92 MHz, DR = 20 kbps, FDEV = 10 kHz
433.92 MHz, DR = 20 kbps, FDEV = 20 kHz
433.92 MHz, DR = 50 kbps, FDEV = 25 kHz
433.92 MHz, DR = 50 kbps, FDEV = 50 kHz
433.92 MHz, DR = 100 kbps, FDEV = 50 kHz
433.92 MHz, DR = 200 kbps, FDEV = 50 kHz
433.92 MHz, DR = 200 kbps, FDEV = 100 kHz
433.92 MHz, DR = 300 kbps, FDEV = 50 kHz
433.92 MHz, DR = 300 kbps, FDEV = 150 kHz
Min. Typ. Max. Unit
45
70
72
75
-25
-114.2
-113.0
-110.6
-109.0
-107.8
-103.5
-104.3
-98.0
-101.6
-122.9
-121.8
-119.5
-120.6
-120.3
-119.7
-116.0
-116.1
-120 dBc dBc dBc dBc dBm
20 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
Parameter
Output power
Output power step
GFSK Gaussian filter coefficient
Output power variation
Stray radiation
Harmonic output for
Symbol
P
P
OUT
STEP
Condition
Need specific peripheral materials for different frequency bands
BT
P
OUT-TOP
Temperature from -40 to +85 C
H2
433
P
OUT
= +13 dBm,433MHz, F
RF
<1 GHz
1 GHz to 12.75 GHz, with harmonic
2 nd harmonic +20 dBm P
OUT
Min.
-20
0.3
Typ.
1
0.5
1
-46
Max.
+20
1.0
-42
-36
Unit dBm dB
- dB dBm dBm dBm
Rev 1.0 | Page7/46 www.cmostek.com
CMT2300A
Parameter
F
RF
= 433 MHz [1]
Harmonic output for
F
RF
= 868 MHz [1]
Harmonic output for
F
RF
= 915 MHz [1]
Harmonic output for
F
RF
= 433 MHz [1]
Harmonic output for
F
RF
= 868 MHz [1]
Harmonic output for
F
RF
= 915 MHz [1]
Symbol
H3
433
H2
868
H3
868
H2
868
H3
868
H2
433
H3
433
H2
868
H3
868
H2
868
H3
868
Condition
3 nd harmonic +20 dBm P
OUT
2 nd harmonic +20 dBm P
OUT
3 nd harmonic +20 dBm P
OUT
2 nd harmonic +20 dBm P
OUT
3 nd harmonic +20 dBm P
OUT
2 nd harmonic +13 dBm P
OUT
3 nd harmonic +13 dBm P
OUT
2 nd harmonic +13 dBm P
OUT
3 nd harmonic +13 dBm P
OUT
2 nd harmonic +13 dBm P
OUT
3 nd harmonic +13 dBm P
OUT
Min. Typ.
-53
-52
-52
-52
-50
-43
-52
-48
-52
-52
-52
Parameter
Settle time
Symbol Condition
T
SLP-RX
From Sleep to RX
T
SLP-TX
From Sleep to TX
T
STB-RX
From Standby to RX
T
STB-TX
From Standby to TX
T
RFS-RX
From RFS to RX
T
TFS-RX
From TFS to TX
T
TX-RX
From TX to RX
（ Ramp Down time needs 2T symbol
）
T
RX-TX
From RX to TX
Min. Typ.
1000
1000
350
350
20
20
2T symbol
+350
350
Note:
[1]. T
SLP-RX is dominated by the crystal oscillator startup time, which depends on its own characteristics.
Parameter
Frequency range
Frequency resolution
Frequency tuning time
Phase noise@ 433
MHz
Phase noise@ 868
Symbol
F
RF
F
RES t
TUNE
PN
433
PN
868
Condition
Need different matching networks
10 kHz frequency deviation
100 kHz frequency deviation
500 kHz frequency deviation
1MHz frequency deviation
10 MHz frequency deviation
10 kHz frequency deviation
Min.
760
380
190
127
Typ.
25
150
-94
-99
-118
-127
-134
-92
Max.
Max.
1020
510
340
170
Max.
Unit
MHz
MHz
MHz
MHz
Hz us dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Unit dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
Unit us us us us us us us us
Rev 1.0 | Page8/46 www.cmostek.com
CMT2300A
MHz
Parameter
Phase noise@ 915
MHz
Symbol
PN
915
Condition
100 kHz frequency deviation
500 kHz frequency deviation
1MHz frequency deviation
10 MHz frequency deviation
10 kHz frequency deviation
100 kHz frequency deviation
500 kHz frequency deviation
1MHz frequency deviation
10 MHz frequency deviation
Min. Typ.
95
-114
-121
-130
-89
-92
-111
-121
-130
Max.
Parameter
Crystal frequency [1]
Frequency tolerance [2]
Load capacitance
Symbol
F
XTAL ppm
C
LOAD
Condition Min. Typ.
26
20
15
Max. Unit
MHz ppm pF
Equivalent resistance
Start-up time [3]
Rm t
XTAL
60
400
Ω us
Remarks:
[1]. CMT2300A can use the external reference clock to drive the XIN pin through the coupling capacitor. The peak value of the external clock signal is between 0.3V and 0.7V.
[2]. The value includes (1) initial error; (2) crystal load; (3) aging; and (4) change with temperature. The acceptable crystal frequency tolerance is limited by the receiver bandwidth and the RF frequency offset between the transmitter and the receiver.
[3]. The parameter is largely related to the crystal.
Parameter Symbol Condition Min. Typ. Max.
Calibration frequency [1]
Frequency accuracy
Temperature coefficient [2]
Supply voltage coefficient
Initial calibration time
[3]
F
LPOSC t
LPOSC-CAL
After calibration
32
± 1
-0.02
+0.5
4
Remarks:
[1]. The low frequency oscillator is automatically calibrated to the crystal oscillator frequency at the PUP stage and periodically calibrated at this stage.
[2]. After calibration, the frequency changes with temperature.
[3]. After calibration, the frequency changes with the change of the supply voltage.
Unit kHz
%
%/°C
%/V ms
Rev 1.0 | Page9/46 www.cmostek.com
Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
CMT2300A
Parameter Symbol
Detection accuracy
LBD
RES
Condition Min.
Parameter
Digital input high level
Digital input low level
Digital output high level
Digital output low level
SCLKFrequency
SCLK high time
SCLK low time
SCLKrise time
SCLKfall time
Symbol
V
IH
V
IL
V
OH
V
OL
F
SCL
T
CH
T
CL
T
CR
T
CF
@I
OH
= -0.5mA
@I
OL
= 0.5mA
Condition Min.
0.8
Vdd-0.4
50
50
50
50
Rev 1.0 | Page10/46
Typ.
50
Typ.
Max.
Max.
0.2
0.4
5
Unit mV
Unit
V
DD
V
DD
V
V
MHz ns ns ns ns www.cmostek.com
CMT2300A
434MHz
868MHz
8.80
8.60
8.40
8.20
8.00
7.80
7.60
7.40
1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage(V)
Testing Condition: Freq = 434MHz / 868MHz, Fdev = 10KHz, BR = 10Kbps
9.5
9.3
9.0
8.8
8.5
8.3
8.0
7.8
7.5
7.3
7.0
-40 25
Temperature( ℃ )
Test Condition: Freq = 434MHz,Fdev = 10KHz, BR = 10Kbps
Rev 1.0 | Page11/46
85
3.3V
1.8V
3.6V www.cmostek.com
CMT2300A
9.5
9.3
9.0
8.8
8.5
8.3
8.0
7.8
7.5
7.3
7.0
-40 25
Temperature( ℃ )
Test Condition: Freq = 868MHz, Fdev = 10KHz, BR = 10Kbps
-113.0
-113.5
-114.0
-114.5
-115.0
-115.5
-116.0
-116.5
-117.0
-117.5
1.8 2.1 2.4 2.8
Supply Voltage(V)
3.0
Test Condition: FSK, DEV = 10KHz, BR = 10Kbps
Rev 1.0 | Page12/46
3.3
85
3.3V
3.6V
1.8V
434MHz
868MHz
3.6 www.cmostek.com
CMT2300A
434MHz
868MHz
-112.0
-113.0
-114.0
-115.0
-116.0
-117.0
-118.0
-40 25
Temperature( ℃ )
85
Test Condition: FSK, DEV = 10KHz, BR = 10Kbps
20dBm
13dBm
20.0
19.0
18.0
17.0
16.0
15.0
14.0
13.0
12.0
11.0
10.0
1.8 1.9 2.0 2.1 2.2 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
Supply Voltage(V)
3.1 3.2 3.3 3.4 3.5 3.6
Test Condition:Freq = 434MHz, 20dBm / 13dBmmatching network
Rev 1.0 | Page13/46 www.cmostek.com
CMT2300A
13dBm
20dBm
20.0
19.0
18.0
17.0
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
1.8 1.9 2.0 2.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage(V)
Test Condition:Freq = 868MHz, 20dBm / 13dBmmatching network
Rev 1.0 | Page14/46 www.cmostek.com
CMT2300A
RFIP 1
RFIN 2
PA 3
AVDD 4
16 15 14 13
17
GND
12 FCSB
11 CSB
10 SDIO
9 SCLK
5 6 7 8
Pin No. Name I/O
1 RFIP I
2 RFIN I
5
6
3
4
7
8 [1]
PA
AVDD
AGND
DGND
DVDD
GPIO3
O
IO
IO
IO
IO
IO
GPIO3
VDD
Internal IO Schematic pd_dout default value is “0” pd_dout
Descriptions
RF signal input P
RF signal input N
PA output
Analog VDD
Analog GND
Digital GND
Digital VDD
Configured as CLKO, DOUT/DIN, INT2 and DCLK (TX/RX)
Data tristate dout
9 SCLK I pd_din pd_din default value is “1”
VDD
SCLK
Buffer din din
SPI clock
Rev 1.0 | Page15/46 www.cmostek.com
10 SDIO IO
SDIO
VDD
Data tristate dout pd_dout default value is “1” pd_dout
SPI data input and output
CMT2300A
11 CSB I pd_din pd_din default value is “0”
VDD
CSB din
Buffer
SPI chip selection bar for register access, active low
12 FCSB I
13
14
15 [1]
XI
XO
I
O
GPIO2 IO VDD
GPIO2
FCSB
VDD
SPI chip selection bar for FIFO access, active low
Buffer
Data tristate dout pd_dout default value is “0” pd_dout
Crystal circuit input
Crystal circuit output
Configured as INT1, INT2, DOUT/DIN,
DCLK (TX/RX) and RF_SWT
16 [1] GPIO1 IO
GPIO1
VDD pd_din pd_din default value is “1”
Data tristate din dout pd_dout default value is “0” pd_dout
Configured as DOUT/DIN, INT1, INT2,
DCLK (TX/RX) and RF_SWT pd_din pd_din default value is “1” din
17 GND I Analog GND. It must be grounded.
Note:
[1]. INT1 and INT2 are interrupts. DOUT is demodulated output. DIN is a modulation input. DCLK is a modulation or demodulation data rate synchronization clock, automatic switching in TX/RX mode.
Rev 1.0 | Page16/46 www.cmostek.com
CMT2300A
No.
C1 ±5%, 0603 NP0, 50 V
C2 ±5%, 0603 NP0, 50 V
C3 ±5%, 0603 NP0, 50 V
C4 ±5%, 0603 NP0, 50 V
C5 ±5%, 0603 NP0, 50 V
C6 ±5%, 0603 NP0, 50 V
C7 ±5%, 0603 NP0, 50 V
C8 ±5%, 0603 NP0, 50 V
C9 ±5%, 0603 NP0, 50 V
C10 ±5%, 0603 NP0, 50 V
C11 ±5%, 0603 NP0, 50 V
L1 ±5%, 0603 Multilayer chip inductor
L2 ±5%, 0603 Multilayer chip inductor
L3 ±5%, 0603 Multilayer chip inductor
L4 ±5%, 0603 Multilayer chip inductor
L5 ±5%, 0603 Multilayer chip inductor
L6 ±5%, 0603 Multilayer chip inductor
L7 ±5%, 0603 Multilayer chip inductor
L8 ±5%, 0603 Multilayer chip inductor
Y1 ±10 ppm, SMD32*25 mm
U1
CMT2300A, Ultra Low Power Sub-1GHz RF
Transceiver
180
56
39
18
18
27
27
68
433 MHz
+13 dBm
15
5.6
7.5
24
24
4.7
4.7
Values
100
10
8.2
10
10
15
15
12
4.7
470
0.1
0.1
868 MHz
+13dBm
22
6.2
3.6
24
24
2.2
2.2
26
100
8.2
6.8
8.2
8.2
12
12
12
915 MHz
+13dBm
22
6.2
3.3
24
24
2.2
2.2
Unit uF nH nH nH nH nH nH nH nH
MHz pF pF pF pF pF pF pF uF pF uF
-
Rev 1.0 | Page17/46
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Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
EPSON
CMOSTEK
CMT2300A
No.
Descriptions
C1 ±5%, 0603 NP0, 50 V
C2 ±5%, 0603 NP0, 50 V
C3 ±5%, 0603 NP0, 50 V
C4 ±5%, 0603 NP0, 50 V
C5 ±5%, 0603 NP0, 50 V
C6 ±5%, 0603 NP0, 50 V
C7 ±5%, 0603 NP0, 50 V
C8 ±5%, 0603 NP0, 50 V
C9 ±5%, 0603 NP0, 50 V
C10 ±5%, 0603 NP0, 50 V
C11 ±5%, 0603 NP0, 50 V
L1 ±5%, 0603 Multilayer chip inductor
L2 ±5%, 0603 Multilayer chip inductor,
L3 ±5%, 0603 Multilayer chip inductor
L4 ±5%, 0603 Multilayer chip inductor
L5 ±5%, 0603 Multilayer chip inductor
L6 ±5%, 0603 Multilayer chip inductor
L7 ±5%, 0603 Multilayer chip inductor
L8 ±5%, 0603 Multilayer chip inductor
Y1 ±10 ppm, SMD32*25 mm
U1
CMT2300A, Ultra Low Power Sub-1GHz RF
Transceiver
433 MHz
+20 dBm
15
3.0
6.2
24
24
4.7
4.7
180
22 cap 15pF
33
33
27
27
68
0.1
100
12
15
6.2
6.2
15
15
12
26
Values
868 MHz
+20 dBm
18
3.6
3.3
24
24
2
2
4.7
100
12
15
6.2
6.2
15
15
12
915 MHz
+20 dBm
18
3.6
3.3
24
24
1.8
1.8
Unit uF nH nH nH nH nH nH nH nH
MHz pF pF pF pF pF pF pF uF pF uF
-
Supplier
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EPSON
CMOSTEK
Rev 1.0 | Page18/46 www.cmostek.com
CMT2300A
No.
C5
C6
C7
C8
C9
C1
C2
C3
C4
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
C10 ±5%, 0402 NP0, 50 V
C11 ±5%, 0402 NP0, 50 V
C12 ±5%, 0402 NP0, 50 V
C13 ±5%, 0402 NP0, 50 V
C14 ±5%, 0402 NP0, 50 V
C15 ±5%, 0402 NP0, 50 V
C16 ±5%, 0402 NP0, 50 V
C17 ±5%, 0402 NP0, 50 V
C18 ±5%, 0402 NP0, 50 V
C19 ±5%, 0402 NP0, 50 V
C20 ±5%, 0402 NP0, 50 V
C21 ±5%, 0402 NP0, 50 V
C22 ±5%, 0402 NP0, 50 V
L1 ±5%, 0603 Multilayer chip inductor
Descriptions
434 MHz
+20 dBm
15
10
8.2
8.2
18nH
4.7
4.7
220
220
Values
0.1
868 /915 MHz
+20 dBm
15
3.9
2.7
2.7
220
2
2
220
220
Unit
24
24
10
10
180
4.7
27
27
27
27
24
24
10
10
100 pF pF pF nH pF pF pF pF uF uF pF pF uF pF pF pF pF uF pF pF pF pF pF
Rev 1.0 | Page19/46
Supplier www.cmostek.com
Sunlord SDCL
No. Descriptions
L6
L7
L8
Y1
L2
L3
L4
L5
U1
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±10 ppm, SMD32*25 mm
CMT2300A, Ultra Low Power Sub-1GHz RF
Transceiver
U2 AS179, PHEMT GaAs IC SPDT Switch
R1 ±5%, 0402
R2 ±5%, 0402
CMT2300A
434 MHz
+20 dBm
27
18
33
15
27
27
68
Values
868 /915 MHz
+20 dBm
6.8
12
22
10
12
12
18
26
-
-
2.2
2.2
Unit nH nH nH nH nH nH nH
MHz
-
- kΩ kΩ
Supplier
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
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EPSON
CMOSTEK
SKYWORKS
Rev 1.0 | Page20/46 www.cmostek.com
CMT2300A
CMT2300A is an ultra-low power, high performancetransceiver chip. It supports OOK, (G) FSK and (G) MSK.It is suitable for applications in the range from 140 to 1020MHz. The product belongs to CMOSTEK NextGenRFTM series. The series includes transmitters, receivers and transceivers and other complete product lines. CMT2300A block diagramis as shown in the following figure.
XIN XOUT
VCO
LFOSC LDOs POR
Bandgap
VDD
GND
LOOP
FILTER
CP PFD
26 Mhz
XO
Registers
PA PA D-DIV M-DIV
AFC LOOP
Radio
Controller SPI, FIFO
Interface
FCSB
CSB
SCLK
SDIO
I LMT
RXIP
RXIN
LNA
RSSI
Q LMT
MODEM
Packet Handler
FIFO
IO
Ctrl
GPIO 1
GPIO 2
GPIO 3
ADC
AGC LOOP
In the receiver part, the chip uses LNA+MIXER+IFFILTER+LIMITTER+PLL low-IF architecture to achieve the Sub-GHz wireless reception function. The chip uses PLL+PA architecture to achieve the Sub-GHz wireless transmitting function.
In the receiver system, the analog circuit mixes the RF signal to IF and converts the signal from analog to digital through the
Limiter module, then outputs I/Q two single bit signals to the digital circuit for (G) FSK demodulation. At the same time, SARADC will convert the real-time RSSI signal to 8-bit digital signal, and sent them to the digital part for OOK demodulation and other processing. The digital circuit is responsible for mixing the intermediate frequency to zero frequency (Baseband) and performing a series of filtering and decision processing, while AFC and AGC control the analog circuit dynamically, finally the 1-bit original signal is demodulated. After demodulation, the signal will be sent to the decoder to decode and fill in the FIFO, or output to the
PAD directly.
In the transmitter system, the digital circuitry will encode the data and then send them to the modulator (or send them to the modulator directly without encoding). The modulator will directly control the PLL and PA, modulate the data by (G) FSK or OOK and transmit them.
The chip provides the SPI communication port. The external MCU can configure the various functions by accessing to the register, control the main state machine, and access to the FIFO.
The transmitter is based on direct frequency synthesis technology. The carrier is generated by a low noise fractional-N frequency synthesizer.
The modulated data is transmitted by an efficient single-ended power amplifier (PA). The output power can be read and written
Rev 1.0 | Page21/46 www.cmostek.com
CMT2300A via registers, step by step from -20dBm to +20dBm with 1dB.
When the PA is switched fast, the varying input impedance will disturb the output frequency of the VCO instantaneously. The effect iscalled VCO pulling. It will generate the spurious and spurson the spectrumaround the desired carrier.The PA spurs can be reduced to a minimum instantaneously by thePA output power ramping. CMT2300A has a built-in PA ramping mechanism. When the PA Ramp is turned on, the PA output power can ramp the desired amplitude in a pre-configured rate, so as to reduce the spurs.In FSK mode, the signal can be filtered by a Gaussian Filter before transmitted, e.g. GFSK, which can reduce the spectral width and interference with neighboring channels.
According to different application requirements, the user can design a PA matching network to optimize the transmitting efficiency.
The typical application schematic and the required BOM is shown in Chapter 3 "Typical application schematic". For more schematic details and layout guidelines, please refer to “ AN141 CMT2300A Schematic and PCB Layout Design Guideline”.
The transmitter can operate in direct mode and package mode. In the direct mode, the data to be transmitted can be sent to the chip by the DIN pin and transmitted directly. In the package mode, the data can be pre-loaded into the TX FIFO in STBY state, and transmitted together with other package elements.
CMT2300A has a built-in ultra-low power, high performance low-IF OOK, FSK receiver. The RF signal induced by the antennais amplified by a low noise amplifier, and is converted to an intermediate frequency by an orthogonal mixer. The signal is filtered by the image rejection filter, and is amplified by the limiting amplifier and then sent to the digital domain for digital demodulation.
During power on reset (POR) each analog block is calibrated to the internal reference voltage. This allows the chip to remain its best performance at different temperatures and voltages. Baseband filtering and demodulation isdone by the digital demodulator.The AGC loop adjust the system gain by the broadband power detector and attenuation network nearby LNA, so as to obtain the best system linearity, selectivity, sensitivity and other performance.
LeveragingCMOSTEK's low power design technology, the receiver consumes only a very low power when it is turned on. The periodic operation mode and wake up function can further reduce the average power consumption of the system in the application with strict requirements of power consumption.
Similar to the transmitter, the CMT2300A receiver can operate in direct mode and packet mode.In the direct mode, the demodulator output data can be directly output through the DOUT pin of the chip. DOUT can be assigned to GPIO1/2/3. In the packet mode, the demodulator data output is sent to the data packet handler, get decodedand is filled in the FIFO. MCU can read the FIFO by the SPI interface.
The Power-On Reset circuit detect the change of the VDD power supply, and generate the reset signal for the entire CMT2300A system. After the POR, the MCU must go through the initialization process and re-configure the CMT2300A. There are two circumstances those will lead to the generation of POR.
The first case is a very short and sudden decrease of VDD. The POR triggering condition is, VDD dramatically decreases by 0.9V
+/- 20% (e.g. 0.72V – 1.08V) within less than 2 us. To be noticed, it detects a decreasing amplitude of the VDD, not the absolute value of VDD.
Rev 1.0 | Page22/46 www.cmostek.com
CMT2300A
VDD
0.9 V x (1 +/- 20%)
< 0.2 us
POR
The second case is, a slow decrease of the VDD. The POR triggering condition is, VDD decreases to 1.45V +/- 20% (e.g. 1.16V
– 1.74V) within a time more than or equal to 2 us. To be noticed, it detects an absolute value of VDD, not a decreasing amplitude.
> 0.2 us
VDD
1.45 V x (1 +/- 20%)
POR
The crystal oscillator provides a reference clock for the phase locked loop as well as a system clock for the digital circuits. The value of load capacitance depends on the crystal specified CL parameters. The total load capacitance between XI and XO should be equal to CL, in order to make the crystal accurately oscillate at 26 MHz.
C15 and C16 are the load capacitancesat both ends of the crystal. Cpar is the parasitic capacitance on the PCB. Each crystal pin has 5pF internal parasitic capacitance, together is equivalent to 2.5pF. The equivalent series resistance of the crystal must be within the specifications so that the crystal can have a reliable vibration. Also, an external signal source can be connected to the
XI pin to replace the conventional crystal. The recommended peak value of this clock signal is from 300mV to 700mV. The clock is coupled to XI pin via a blocking capacitor.
The CMT2300A integrates a sleep timer driven by 32 kHz low power oscillator (LPOSC). When this function is enabled, the timer wakes the chip from sleep periodically. When the chip operates in a duty cycle mode, the sleep time can be configured from
0.03125 ms to 41922560 ms. Due to the low power oscillator frequency will change with the temperature and voltage drift, it will
Rev 1.0 | Page23/46 www.cmostek.com
CMT2300A be automatically calibrated during power on and will be periodically calibrated since then. These calibrations will keep the frequency tolerance of the oscillator within + 1%.
The chip sets up low voltage detection.When the chip is tuned to a certain frequency, the test is performed once.Frequency tuning occurs when the chip jumps from the SLEEP/STBY state to the RFS/TFS/TX/RX state. The result can be read by the
LBD_VALUE register.
RSSI is used to evaluate the signal strengthinside the channel. The cascaded I/Q logarithmic amplifier amplifies the signal before it is sent to the demodulator. The logarithmic amplifier of I channels and Q channel contains the received signal indicator, in which the DC voltage is generated is proportional to the input signal strength. The output of RSSI is the sum of thevalues of the two channels’ signals. The output has 80dB dynamic range above the sensitivity. After the RSSI output is sampled by the ADC and filtered by a SAR FILTER and a RSSI AVG FILTER. The order of the average filter can be set by RSSI_AVG_MODE<2:0>. The code value is translated into dBm value after filtering. Users can read the registerRSSI_CODE<7:0> to obtain the RSSI code value, or RSSI_DBM<7:0> to obtain the dBm value. By setting the register RSSI_DET_SEL<1:0> Users can determine whether the RSSI is output to the MCU in real time, or latched at the instance when the preamble, sync, or the whole packet is received.
Also, CMT2300A allows the user to setup a threshold by RSSI_TRIG_TH<7:0> to compare with the real-time RSSI value. If the
RSSI is larger than the threshold it outputs logic 1, otherwise outputs logic 0. The output can be used as a source of the RSSI
VLD interrupt, ofthe receive time extending condition in the super low power (SLP) mode.
RSSI_DET_SEL<1:0>
RSSI_AVG_MODE<2:0>
RSSI_CODE<7:0>
LATCH
SAR
ADC
SAR
FILTER
RSSI AVG
FILTER
CODE to dBm
CONVERT
LATCH
RSSI_DBM<7:0>
RSSI_DET_SEL<1:0>
COMPARE to
RSSI_TRIG_TH<7:0>
RESULT
CMT2300A has done a certain degree of calibration before delivery. In order to obtain more accurate RSSI measurement results, the user needs to recalibrate the RSSI circuit in their dedicated applications. For further information, please refer to the
“AN144-CMT2300AW RSSI Usage Guideline”.
（
）
PJD is Phase Jump Detector. When the chip is in FSK demodulation, itcan automatically observe the phase jump characteristics of the received signal to determine whether it is awanted signal or an unwanted noise.
Rev 1.0 | Page24/46 www.cmostek.com
CMT2300A
2
SYM
2
SYM
1
SYM
1
SYM
1
SYM
1
SYM
The PJD mechanism defines that the input signal switching from 0 to 1 or from 1 to 0 is a phase jump. Users can configure the
PJD_WIN_SEL<1:0> to determine the number of detected jumps for the PJD to identify a wanted signal.As shown in the above figure, in total 8 symbols are received. But the phase jump only appeared 6 times. Therefore, the number of jumpsis not equal to the number of symbols. Only when a preamble is received theyare equal.In general, the more jumps are used to identify the signal, the more reliable they result is; the less jumps are used, the faster the result is obtained.If the RX time is set to a relatively short period, it is necessary to reduce the number of jumps to meet the timing requirements. Normally, 4 jumps allow pretty reliable result, e.g. the chip will not mistakenly treat an incoming noise as a wanted signal, and vice versa will not treat a wanted signal as noise.
Detecting the phase jump of a signal, is identical to detect whether the signal has the expecteddata rate. In fact, at the same time, the PJD will also detect the FSK deviation and see if it is legal, as well as to see if the SNR is over 7 dB.With these three parameters the PJD is able to make a very reliable judgement. If the signal is wanted it outputs logic 1, otherwise outputs logic 0.
The output can be used as a source of the RSSI VLD interrupt, or the receive time extending condition in the super low power
(SLP) mode. In direct data mode, by setting the DOUT_MUTE register bit to 1, the PJD can mute the FSK demodulated data output while there is not wanted signal received.
The PJD technique is similar to the traditional carrier sense technique, but more reliable. While users combine the RSSI detection and PJD technique, they can precisely identify the status of the current channel.
The AFC mechanism allows the receiver to minimize the frequency error between the TX and RX in a very short time once a wanted signal comes in. This helps the receiver to maintain its highest sensitivity performance. CMT2300A has the most advanced AFC technology. Compare with the other competitors, within the same bandwidth, CMT2300A can identify larger frequency error, and remove the error in a much shorter time (8-10 symbols).
Normally the frequency error between the TX and RX is caused by the crystal oscillators used in both sides. CMT2300A allows the user to fill in the value of crystal tolerance (in PPM) on RFPDK. Based on the crystal tolerance, the RFPDK will calculate the
AFC range whileminimizing the receiver bandwidth (to maintain the best performance). Due to the excellent performance of the
AFC, it provides a good solution to the crystal aging problem which would lead to more frequency error as time goes by.
Therefore, compare to other similar transceiver chips, CMT2300A can solve more severe crystal aging problem and effectively extend the life time of the product.Please refer to “AN196-CMT2300A-CMT2219B-CMT2218B The Advantages of the Receiver
AFC.” for more details.
The basic task of a CDR system is to recover the clock signal that is synchronized with the symbol rate, while receiving the data.
Not only for decoding inside the chip, but also for outputting the synchronized clock to GPIO for users to sample the data.So
CDR's task is simple and important. If the recovered clock frequency is in error with the actual symbol rate, it will cause data acquisition errors at the time of reception.
CMT2300AW has designed three types of CDR systems, as follows:
1. COUNTING system –The system is designed for the symbol rates to be more accurate. If the symbol rate is 100% aligned, the unlimited length of 0 can be received continuously without error.
Rev 1.0 | Page25/46 www.cmostek.com
CMT2300A
2. TRACING system –The system is designed to correctthe symbol rate error. It has the tracking function. It can automatically detect the symbol rate transmitted by TX, and adjust quickly the local symbol rate of RX at the same time, so as to minimize the error between them.The system can withstand up to 15.6% or symbol rate error. Other similar products in the industry cannot reach this level.
3. MANCHESTER system –This system evolves from the COUNTING system. The basic feature is the same.The only difference is that the system is specially designed for Manchester codec.Special processing can be done when the TX symbol rate has unexpected changes.
The mechanism of fast frequency hopping is, based on the frequency configured on the RFPDFK, for instance 433.92MHz, during applications the MCU can simply change 1 or 2 registers to quickly switch to another frequency channel. This simplify the way of change the RX or TX frequency in multiple channels application.
In general, the user can configure FH_OFFSET<7:0>during the chip initialization process. And then in the application, the user can switch the channel by changing FH_CHANNEL<7:0>.
When users need to use the fast frequency hopping in the RX mode, in some particular frequency points, one parameter of the
AFC circuit must be re-configured. Please refer to “AN197-CMT2300A-CMT2119B-CMT2219B fast frequency hopping” and
“CMT2300A-CMT2219B frequency hopping calculation tool” for more details.
Rev 1.0 | Page26/46 www.cmostek.com
CMT2300A
The chip communicates with the outside through the 4-wire SPI interface. The CSB is the active-lowchip select signal for accessing to the registers. The FCSB is the active-low select signal for accessing to the FIFO. They cannot be set to low at the same time. The SCLK is the serial clock.Its highest speed is 5MHz.The chip itself and the external MCU send the data at the falling edge of SCLK and capture the data at the rising edge of SCLK. The SDA is a bidirectional pin for input and output data.
The address and data are transferred starting from the MSB.
When accessing to the register, CSB is pulled low. A R/W bit is sent first, followed by a 7-bit register address. After the external
MCU pulls down the CSB, it must wait for at least half a SCL cycle, and then send the R/W bit. After the MCU sends out the last falling edge of SCLK, it must wait for at least half a SCLK cycle, and then pull the CSB high.
To be noticed, when reading a register, MCU and CMT2300A will have to switch the direction of their IO (SDIO) between the address bit 0 and the data bit 7. It is required that the MCU switches the IO to input mode before send out the falling edge of the
SCLK; CMT2300A should switch the IO to output mode after it has seen the falling edge of the SCLK. This avoids data contention of the SDIO (both of the MCU and CMT2300A set the SDIO to output mode at the same time), which would cause unexpected electrical problem.
> 0.5 SCLK cycle > 0.5 SCLK cycle
CSB
FCSB
SCLK
SDIO X 7 r/w = 1
6 5 4 3 2 register address
1 0 7 6 5 4 3 2 register read data
1 0 X
> 0.5 SCLK cycle > 0.5 SCLK cycle
CSB
FCSB
SCLK
SDIO X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X r/w = 0 register address register write data
CMT2300A provides two separated 32-byte FIFO by default. They are used for RX and TX, respectively. Users can also set
Rev 1.0 | Page27/46 www.cmostek.com
CMT2300A
FIFO_MARGE_EN to 1 to merge the two separated FIFO into one 64-byte FIFO. It can be used both under TX and RX. By configuring the FIFO_RX_TX_SEL to indicate whether it is currently used as TX FIFO or RX FIFO. When the two FIFO are not merged, users can fill in the TX FIFO while the RX FIFO is used to receive data in the RX mode.
The FIFO can be accessedvia the SPI interface. The user can clear the FIFO by setting FIFO_CLR_TXor FIFO_CLR_RX to 1.
Also, the user can re-send the old datain the TX FIFO by setting FIFO_RESTORE to 1, without the need of re-filling the data.
When the MCU accesses to the FIFO, the user must first configure a few registers to setup the FIFO read/write mode, as well as some other working mode. The details are introduced in “AN143-CMT2219B FIFO and Data Packet Usage Guideline”. Here is the read-write timing diagram. Note that there is a slight difference in the control of the FCSB for accessing to the FIFO and the control of the CSB for accessing to the register. When the MCU starts to access to the FIFO, FCSB must be pulled down 1-clock cycle at first, and then send the rising edge of SCL. After the last falling edge of SCL is sent, the MCU must wait at least 2 us to pull up the FCSB. Between the adjacent read/write operations, the FCSB must be pulled high for 4us at least. When writing the
FIFO, the first bit data must be ready 0.5 clock cycles before sending the first rising edge of SCL.
> 1 SCLK cycle > 2 us > 4 us > 1 SCLK cycle > 2 us
CSB
FCSB
SCLK
SDIO 7 6 5 4 3 2
FIFO read data
1 0 X 7 6 5 4 3 2 1 0 X
FIFO read data
> 1 SCLK cycle > 2 us > 4 us > 1 SCLK cycle > 2 us
CSB
FCSB
SCLK
SDIO 7 6 5 4 3 2
FIFO write data
1 0 X 7 6 5 4 3 2
FIFO write data
1 0 X
CMT2300A provides rich interrupt sources associated with the FIFO. The interrupt timing for Tx and Rx FIFO is shown below:
Rev 1.0 | Page28/46 www.cmostek.com
CMT2300A
RX DATA Noise Sync 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SYNC_OK
RX_FIFO_WBYTE
RX_FIFO_NMTY
(FIFO_TH = 16)
RX_FIFO_TH
RX_FIFO_FULL
RX_FIFO_OVF
RX FIFO ARRAY
Noise
EMPTY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FULL
TX DATA
TX_FIFO_NMTY
TX_FIFO_TH
TX_FIFO_FULL
Prefix Pream Sync 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0
(FIFO_TH = 16)
FIFO ARRAY EMPTY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FULL
After the chip VDD is powered up, the chip usually needs to wait about 1ms, then POR will release. After the release of the POR, the crystal will start, the start time is 200 us - 1 ms, depending on the characteristics of the crystal itself. After starting, the user need to wait for the crystal settled, then the system starts working. The default setting is 2.48ms. This time can be modified by writing XTAL_STB_TIME <2:0> afterword (it has to be longer than the crystal inherent settling time). However, if the inherent settling time of the crystal is difficult to observed by the user, the default setting of 2.48 ms is recommended and is able to cover most of the crystals.
The chip remains in the IDLE status until the crystal is settled. After the crystal is settled, the chip will leave the IDLE state and begin to do the calibration of each module. After the calibration is completed, the chip will stay in the SLEEP and wait until the user to initialize the configuration. At any time, as long as the soft reset is performed, the chip will go back to the IDLE and be powered up again.
Rev 1.0 | Page29/46 www.cmostek.com
CMT2300A
VDD
POR
POR Release
<= 1 ms
XTAL Start up
<= N ms
XTAL Stablize
<= 2.5 ms
Block Calibrations
<= 6.5 ms
Enters the SLEEP State Ready for customer initializing
When the calibration is completed, the chip enters the SLEEP mode. From this time, the MCU can switch the chip to different operating states by setting the register CHIP_MODE_SWT<7:0>.
CMT2300A has 7 operationstates:IDLE, SLEEP, STBY, RFS, RX, TFS and TX, as shown below.
State
IDLE
SLEEP
STBY
RFS
TFS
RX
TX
Binary code
0000
0001
0010
0011
0100
0101
0110
Switch command soft_rst go_sleep go_stby go_rfs go_tfs go_rx go_tx
Active Blocks
SPI, POR
SPI, POR, FIFO
SPI, POR, XTAL, FIFO
Optional Blocks
None
LFOSC, Sleep Timer
CLKO
SPI, POR, XTAL, PLL, FIFO
SPI, POR, XTAL, PLL, FIFO
CLKO
CLKO
SPI, POR, XTAL, PLL, LNA+MIXER+IF, FIFO CLKO, RX Timer
SPI, POR, XTAL, PLL, PA, FIFO CLKO
Rev 1.0 | Page30/46 www.cmostek.com
CMT2300A go_sleep go_tx
IDLE
0000
Power up
SLEEP
0001 go_sleep go_rx go_stby go_sleep go_tx go_stby go
_t fs go
_s tb y
STBY
0010 go
_st go by
_rfs
TFS
0100 go_rx go_stby
RFS
0011 go_tfs go_sleep go_rfs go_sleep go_tfs go_tx go_rfs go_rx
TX
0110 go_switch go_switch
RX
0101
The chip power consumption is the lowest in SLEEP state, and almost all the modules are turned off. SPI is open, the registers of the configuration bank and control bank 1 will be saved, and the contents filled in the FIFO before will remain unchanged.
However, the user cannot operate the FIFO and cannot change the contents of the register. If the user opens the wake-up function, the LFOSC and the sleep counter will turn on and start working. The time required to switch from IDLE to SLEEP is the power up time. Switch from other state to SLEEP will be completed immediately.
In STBY state, the crystal is turned on, the LDO of the digital circuit will also be turned on, the current will be slightly increased, and the FIFO can be operated. The user can choose whether to output CLKO (system clock) to PIN. Because the crystal and
LDO is turned on, compared to the SLEEP, the time switching from the STBY to transmitting or receiving will be relatively short.
Switching from SLEEP to STBY will be completed after the crystal is turned on and settled. Switching from other state to STBY will be completed immediately.
RFS is a transition state before switching to RX. Except that the receiver RF module is off, the other modules are turned on, and the current will be larger than STBY. Because PLL has been locked in the RX frequency, RFS cannot switch to TX. Switching from STBY to RFS probably requires PLL calibration and stability time of 350us. Switching from SLEEP to RFS needs to add the crystal start-up and stability time. Switching from other state to RFS will be completed immediately.
TFS is a transition state before switching to TX. Except that the transmitter RF module is off, the other modules are turned on, and the current will be larger than STBY. Because PLL has been locked in the TX frequency, TFS cannot switch to RX. Switching from STBY to TFS probably requires PLL calibration and stability time of 350us. Switching from SLEEP to TFS needs to add the
Rev 1.0 | Page31/46 www.cmostek.com
CMT2300A crystal start-up and settled time. Switching from other state to TFS will be completed immediately.
All modules on the receiver will be opened in RX state. Switching from RFS to RX requires only 20us. Switching from STBY to RX needs to add the PLL calibration and settled time of 350us. Switching from SLEEP to RX needs to add the crystal start-up and settled time. TX can be quickly switched to RX by sending go_switch command. Whether the TX and RX setting frequency is the same, the user need to wait for the PLL re-calibration and settled time of 350us to switch successfully.
All modules on the transmitter will be opened in TX state. Switching from TFS to TX requires only 20us. Switching from STBY to
TX needs to add the PLL calibration and settled time of 350us. Switching from SLEEP to TX needs to add the crystal start-up and settled time. RX can be quickly switched to TX by sending go_switch command. Whether the RX and TX setting frequency is the same, the user need to wait for the PLL re-calibration and settled time of 350us to switch successfully.
CMT2300A has 3 GPIO ports.Each GPIO can be configured as a different input or output. CMT2300A has 2 interrupt ports. They can be configured to different GPIO outputs.
Pin No. Name I/O Function
16
15
GPIO1
GPIO2
IO Configuredas:DOUT/DIN, INT1, INT2, DCLK (TX/RX), RF_SWT
IO Configuredas:INT1, INT2, DOUT/DIN, DCLK (TX/RX), RF_SWT
8 GPIO3 IO Configuredas:CLKO, DOUT/DIN, INT2, DCLK (TX/RX)
Interrupt mapping table is as below. INT1 and INT2 mapping is the same. Take INT1 as an example.
Rev 1.0 | Page32/46 www.cmostek.com
CMT2300A
Name INT1_SEL Descriptions Clearing methods
Auto RX_ACTIVE
TX_ACTIVE
RSSI_VLD
PREAM_OK
SYNC_OK
NODE_OK
CRC_OK
PKT_OK
SL_TMO
00000
00001
00010
00011
00100
00101
00110
00111
01000
Indicates the chip is entering RX and is already in RX. It is 1 in PLL tuningand RX state, and it is 0 in the other states.
Indicates the chip is entering TX and is already in TX. It is 1 in PLL tuning and TX state, and it is 0 in the other states.
Indicates whether the RSSI is active.
Indicates that the Preamble is received successfully.
Indicatesthat the Sync Wordis received successfully.
Indicatesthat the Node ID is received successfully.
Indicates that the CRC for the current packet is correct.
Indicates that a packet has been received.
Indicates that the SLEEP counter timed out.
Auto
Auto by MCU by MCU by MCU by MCU by MCU by MCU
RX_TMO
TX_DONE
RX_FIFO_NMTY
RX_FIFO_TH
RX_FIFO_FULL
RX_FIFO_WBYTE
RX_FIFO_OVF
TX_FIFO_NMTY
TX_FIFO_TH
TX_FIFO_FULL
STATE_IS_STBY
STATE_IS_FS
STATE_IS_RX
STATE_IS_TX
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
Indicates that the RX counter timed out.
Indicates that the TX operation is completed.
Indicates that the RX FIFO is not empty.
Indicatesthe number of unread bytes of the RX FIFO is over FIFO TH
Indicates RX FIFO is full.
Indicates each time a byte is written to the RX FIFO. Itis a pulse. indicates RX FIFO is overflow
Indicates that TX FIFO is not empty
Indicates the number of unread bytes of the TX FIFO is over FIFO TH.
Indicates TX FIFO is full.
Indicates that the current state is STBY.
Indicates that the current state is RFS or TFS.
Indicates that the current state is RX.
Indicates that the current state is TX. by MCU by MCU
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
LBD
TRX_ACTIVE
PKT_DONE
10111
11000
11001
Indicates that low battery is detected (VDD is lower than TH)
Indicates the chip is entering TX or RX and is already in TX or RX. It is 1 in
PLL tuning, TX or RX state, and it is 0 in the other states.
Indicates that the current packet has been received, covering 4 possible different situations.
1. The packet is received completely and correctly.
2. Manchester decoding has error. Decoder is automatically reset.
3. NODE ID receiving has error. Decoderis automatically reset.
4. Signal collision occurred.Decoder is not reset, waiting for MCU to
Auto
Auto by MCU response.
By default, Interrupt is active high (logic 1 is valid). Users can set the INT_POLARregister bit to 1to make all interrupts active low
(logic 0 is valid).Taking INT1 as an example, the control and sources selection of all the available interrupts is shown below. The control and mapping ofINT1 and INT2 are the same.
Rev 1.0 | Page33/46 www.cmostek.com
CMT2300A
RX_ACTIVE
RSSI_VLD_FLG
Preamble OK
Interrupt Source
0
PREAM_OK_CLR
0
1
D Q
PREAM_OK_EN
PREAM_OK_FLG
SYNC_OK_CLR SYNC_OK_EN
Sycn Word OK
Interrupt Source
0
0
1
D Q
SYNC_OK_FLG
NODE_OK_CLR NODE_OK_EN
Node ID OK
Interrupt Source
0
0
1
D Q
NODE_OK_FLG
CRC_OK_CLR CRC_OK_EN
CRC OK
Interrupt Source
0
0
1
D Q
CRC_OK_FLG
PKT_DONE_CLR PKT_DONE_EN
Packet OK
Interrupt Source
0
0
1
D Q
PKT_OK_FLG
SL_TMO_CLR SL_TMO_EN
Sleep Timeout
Interrupt Source
0
0
1
D Q
SL_TMO_FLG
RX_TMO_CLR RX_TMO_EN
Receive Timeout
Interrupt Source
0
0
1
D Q
RX_TMO_FLG
TX_DONE_CLR TX_DONE_EN
Transmit Done
Interrupt Source
0
0
1
D Q
RX_DONE_FLG
LBD
Interrupt Source
Packet OK
0
Interrupt Source
Packet Err
Interrupt Source
Collision Err
Interrupt Source
LBD_CLR
RX_FIFO_NMTY_FLG
RX_FIFO_TH_FLG
RX_FIFO_FULL_FLG
RX_FIFO_WBYTE_FLG
RX_FIFO_OVF_FLG
TX_FIFO_NMTY_FLG
TX_FIFO_TH_FLG
TX_FIFO_FULL_FLG
STATE_IS_STBY
STATE_IS_FS
STATE_IS_RX
STATE_IS_TX
0
1
D Q
LBD_FLG
RX_ACTIVE
TX_ACTIVE
TRX_ACTIVE
0
PKT_DONE_CLR
0
1
D Q
PKT_DONE_EN
PKT_DONE_FLG
INT1_CTL <4:0>
0
0
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
00000
00001
00010
00011
00100
10010
10011
10100
10101
10110
10111
11000
11001
其它
INT_POLAR
0
1
INT1
GPO3_SEL <1:0>
GPO2_SEL <1:0>
GPO1_SEL <1:0>
GPIO3
GPIO2
GPIO1
Rev 1.0 | Page34/46 www.cmostek.com
CMT2300A
CMT2300A supports direct mode and packet mode:
Direct Mode – In Rx mode, only supports preamble and sync detection, FIFO does not work, demodulated data sent out from GPIO. In Tx mode, only supports transmitting the data input from GPIO.
Packet Mode – Supports all packet formats, demodulated data is stored in FIFO, accessed by SPI.
EEPROM (CMT Parameters)
RF
MODEM clock
1 data
1
Preamble (Opt)
Sync (Opt) clock
1 data
1
SPI
DCLK
CSB
SCLK
SDIO
User Registers
INT1/INT2
DOUT/DIN
In direct mode, the data from the demodulator is sent directly to the external MCU via the DOUT pin. DOUT can be set to GPIO1,
2 or 3.The typicalRX direct mode controlsequencefor the MCU is:
1. Configures GPIOsusing theCUS_IO_SEL register.
2. Configures DATA_MODE = 0.
3. Send thego_rx command.
4. Capture the data from DOUT continuously.
5. Send thego_sleep/go_stby/go_rfs command to stop receiving and save the power.
In the direct mode, the data to be transmitted is sent directly to the chip from the external MCU by via DIN pin. The data rate is determined by the MCU but must be less than +/- 30% of the data rate configured on the RFPDK. The typical TX direct mode control sequence for the MCU is:
1. Set register TX_DIN_EN to 1 to enable DIN on GPIO.
2. Set TX_DIN_SEL to 0 to configure GPIO1 as DIN, or 1 to configure GPIO2 as DIN.
3. Send thego_tx command,send in the data to the DIN pinwith the desired data rate, the data is transmitted immediately.
4. Send thego_sleep/go_stby/go_rfs command to stop transmission and save the power.
Rev 1.0 | Page35/46 www.cmostek.com
CMT2300A
EEPROM (CMT Parameters)
RF
MODEM clock
1 data
1
Packet
Handler data
8
FIFO SPI
FCSB
CSB
SCLK
SDIO
User Registers
INT1
INT2
The packet handler supportsthe classic and more flexible packet format in both TX and RX mode. It includes variable packet format (Length in front of the Node ID), variable packet format (Length in the back of the Node ID) and fixed packet format. Each element in the packet supports flexible configurations, as shown below.
Manchester Manchester/Whiten/FEC(7,4)
Preamble
1
Sync Word
2
Length
3
Node ID
4
Data
5
CRC
6
Preamble
1
Data-Only CRC
Payload/CRC
图
Manchester Manchester/Whiten/FEC(7,4)
Sync Word
2
Node ID
3
Length
4
Data
5
CRC
6
Data-Only CRC
Payload/CRC
图
Rev 1.0 | Page36/46 www.cmostek.com
CMT2300A
Preamble
1
Manchester
Sync Word
2
Node ID
3
Manchester/Whiten/FEC(7,4)
Data
4
CRC
5
Data-Only CRC
Payload/CRC
图
In the packet mode, the output data from the demodulator will be transferred to the packet handler for decoding, and then filled in the FIFO. The packet handler provides a variety of decoding mechanisms and options to determine the validity of the data. These can reduce the work load of the MCU. The typical package mode control sequence for the MCU is:
1. Configures GPIO usingthe CUS_IO_SEL register.
2. Setup the interruptsusingCUS_INT1_CTL, CUS_INT2_CTL and CUS_INT_EN registers.
3. Send thego_rx command.
4. Reads the RX FIFO according to the relevant interrupts.
5. Sends the go_sleep/go_stby/go_rfs command to stop the receiving and save the power.
6. Clears the packet interruptsusingCUS_ INT_CLR1 and CUS_INT_CLR2 registers.
In the packet mode, MCU can fill the data in the FIFO in advance in the STBY and TFS state, or fill them in the FIFO while the chip sends the data, or use the combination of the above two methods. The typical Txpacket mode control sequence for the MCU is:
1. Configures GPIO usingthe CUS_IO_SEL register
2. Sends go_stby/go_tfs command when the data is filled in FIFO in advance.
3. Sends go_tx command.
4. Writes the data into FIFO according to the relevant interrupt status.
5. Sends go_sleep/go_stby/go_rfs command to save power.
CMT2300A has rich configurable hardware resources of FIFO, packet and their interrupts, which makes it compatible with most of the similar RF products in the market. For more details please refer to the interface of RFPDK and “AN143-CMT2300A FIFO and Data Packet Usage Guideline”.
Rev 1.0 | Page37/46 www.cmostek.com
CMT2300A
CMT2300A makes the Tx and Rx work in duty cycle operation mode to save the power consumption.Among them, the Rx Duty
Cycle can be classified into the following 5 modes.
1. Fully manual control
2. Automatic SLEEP wakeup, switch to manual control
3. Automatic SLEEP wakeup, automaticallyenter to RX, manually exit RX
4. Automatic SLEEP wakeup, manually enter RX, automatically exit RX
5. Fully automatic receive and sleep control
The Tx Duty Cycle can be divided into the following 3 modes.
1. Manually enter TX, automatically exit TX
2. Automatic SLEEP wakeup, manually enter TX, automatically exit TX
3. Fully automatic transmit and sleep control
CMT2300A provides a set of options to help users achieve supper low power consumption (SLP - Supper Low Power) reception under different application requirements.These options can be used whensetting RX_TIMER_EN to 1, e.g. when the Rx timer is enabled. The principle of the SLP mechanism is to shorten the Rx time when there is no wanted signal coming in, and properly extend the Rx time when there is wanted signal detected, so that the power consumption is minimized while the stability of reception is guaranteed.
The traditional short-range wireless receiver generally uses the following basic scheme to achieve low powercommunication.CMT2300A is also compatible with this scheme, and expands it to 13 more power-saving schemes. The figure below introduces the most basic scheme, whichwill be enabled when the RX_EXTEND_MODE<3:0> is set to 0.
One Packet
Length of Packet x 2 +
Packet Gap < RX Time TX Burst Time > RX Cycle
IDLE IDLE t
TX starts transmittion
TX starts transmittion
Received Missed Received
SLEEP t
SLEEP SLEEP SLEEP
Receiving Sleeping XTAL stabilizing and Frequency Tuning
XTAL,
TUNE
RX Sleep
RX Cycle < TX Burst Time
Rev 1.0 | Page38/46 www.cmostek.com
CMT2300A
The traditional low-power communication scheme and the 13-extendedlow-power schemes are listed in the following table.
No. Rx Extended Methods Rx Extended Condition
0
No Rx extension is supported. Exit Rx state as soon as
T1 timed out.
None
1
2
3
Once meet the Rx extended condition during T1, leave
T1 and pass the control authority to MCU.
RSSI_VLD is valid.
PREAM_OK is valid.
RSSI_VLD and PREAM_OK are valid simultaneously.
4
Once detect RSSI_VLD = 1 during T1, leave T1 and stays in Rx state, exit Rx state until RSSI_VLD = 0.
RSSI_VLD is valid.
5
6
7
8
9
Once meet the Rx extended condition during T1, switch to T2. Exit Rx as soon as T2 timed out.
RSSI_VLD is valid
PREAM_OK is valid
RSSI_VLDandPREAM_OK are valid simultaneously.
Any one of PREAM_OK or SYNC_OK is valid.
10
11
12
13
Once meet the Rx extended condition during T1, switch to T2. Leave T2 and pass the control authority to MCU as soon as SYNC is detected, otherwise exit Rx when
T2 timed out.
Any one of PREAM_OK or NODE_OK is valid.
Any one of PREAM_OK or SYNC_OK or NODE_OK is valid.
RSSI_VLD is valid.
PREAM_OK is valid.
RSSI_VLD 与 PREAM_OK are valid simultaneously.
The T1 and T2 mentioned in the table refer to the RX T1 and the RX T2 time interval that can be set via the registers or RFPDK.
The source of RSSI_VLD can be the comparison result of the RSSI or the detection result of the phase jump detector (PJD). For more details, please refer to “AN146-CMT2300AW Low Power Mode Usage Guideline”.
CMT2300A provides a set of registers to select the power consumption and sensitivity performance of the RF frontend circuit.
The below table shows how they are configured:
电流档
Low
Medium
High
性能档
Low
Medium
High
2
2
1
2
2
2
1
1
3
1
2
2
Rev 1.0 | Page39/46 www.cmostek.com
CMT2300A
CMT2300A is configured by writing in the registers. The following is the register table.
Name
CUS_RF1
CUS_RF2
CUS_RF3
CUS_RF4
CUS_RF5
CUS_RF6
CUS_RF7
CUS_RF8
Name
CUS_RF9
CUS_RF10
CUS_RF11
CUS_RF12
CUS_FSK1
CUS_FSK2
CUS_FSK3
CUS_FSK4
CUS_FSK5
CUS_FSK6
CUS_FSK7
CUS_CDR1
CUS_CDR2
CUS_CDR3
CUS_CDR4
CUS_AGC1
CUS_AGC2
CUS_AGC3
CUS_AGC4
CUS_OOK1
CUS_OOK2
CUS_OOK3
CUS_OOK4
CUS_OOK5
Name
CUS_CMT1
CUS_CMT2
CUS_CMT3
CUS_CMT4
CUS_CMT5
CUS_CMT6
CUS_CMT7
CUS_CMT8
CUS_CMT9
CUS_CMT10
CUS_CMT11
CUS_RSSI
Name
CUS_SYS1
CUS_SYS2
CUS_SYS3
CUS_SYS4
CUS_SYS5
CUS_SYS6
CUS_SYS7
CUS_SYS8
CUS_SYS9
CUS_SYS10
CUS_SYS11
CUS_SYS12
Name
CUS_PKT1
CUS_PKT2
CUS_PKT3
CUS_PKT4
CUS_PKT5
CUS_PKT6
CUS_PKT7
CUS_PKT8
CUS_PKT9
CUS_PKT10
CUS_PKT11
CUS_PKT12
CUS_PKT13
CUS_PKT14
CUS_PKT15
CUS_PKT16
CUS_PKT17
CUS_PKT18
CUS_PKT19
CUS_PKT20
CUS_PKT21
CUS_PKT22
CUS_PKT23
CUS_PKT24
CUS_PKT25
CUS_PKT26
CUS_PKT27
CUS_PKT28
CUS_PKT29
Name
CUS_TX1
CUS_TX2
CUS_TX3
CUS_TX4
CUS_TX5
CUS_TX6
CUS_TX7
CUS_TX8
CUS_TX9
CUS_TX10
CUS_LBD
Name
CUS_MODE_CTL
CUS_MODE_STA
CUS_EN_CTL
CUS_FREQ_CHNL
CUS_FREQ_OFS
CUS_IO_SEL
CUS_INT1_CTL
CUS_INT2_CTL
CUS_INT_EN
CUS_FIFO_CTL
CUS_INT_CLR1
Name
CUS_INT_CLR2
CUS_FIFO_CLR
CUS_INT_FLAG
CUS_FIFO_FLAG
CUS_RSSI_CODE
CUS_RSSI_DBM
CUS_LBD_RESULT
Addr R/W
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
RW
RW
RW
RW
RW
RW
RW
RW
Addr R/W
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
Addr R/W
0x00 RW
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
Addr R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Addr R/W
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x44
0x45
0x46
0x47
0x48
0x49
0x50
0x51
0x52
0x53
0x54
0x3E
0x3F
0x40
0x41
0x42
0x43
0x38
0x39
0x3A
0x3B
0x3C
0x3D
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Addr R/W
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
Addr R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
Addr R/W
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
R
R
R
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
Bit 7
Bit 7
Bit 7
RESV
RESV
User does not need to understand the details, just directly export the register contents from the RFPDK
User does not need to understand the details, just directly export the register contents from the RFPDK
User does not need to understand the details, just directly export the register contents from the RFPDK
User does not need to understand the details, just directly export the register contents from the RFPDK
RESV
RF_SWT1_EN
RESV
SL_TMO_EN
TX_DIN_EN
RESV
Bit 7
RESV
RESV
LBD_FLG
RESV
Bit 6
Bit 6
FEC_EN
WHITEN_SEED [8]
RESV
Bit 5
CRC_BYTE_SWAP
WHITEN_SEED_TYPE
RESV
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LFOSC_RECAL_EN
SLEEP_BYPASS_EN
LMT_VTR [1:0]
LFOSC_CAL1_EN
MIXER_BIAS [1:0]
LFOSC_CAL2_EN
XTAL_STB_TIME [2:0]
RX_TIMER_EN
LNA_MODE [1:0]
SLEEP_TIMER_EN
TX_EXIT_STATE [1:0]
TX_DC_EN
SLEEP_TIMER_M [7:0]
SLEEP_TIMER_M [10:8] SLEEP_TIMER_R [3:0]
RX_DC_EN
RX_TIMER_T1_M [7:0]
RX_TIMER_T1_M [10:8] RX_TIMER_T1_R [3:0]
LNA_BIAS [1:0]
RX_EXIT_STATE [1:0]
DC_PAUSE
RX_TIMER_T2_M [7:0]
RX_TIMER_T2_M [10:8]
COL_DET_EN
PJD_TH_SEL
PJD_WIN_SEL [1:0]
COL_OFS_SEL RX_AUTO_EXIT_DIS
CCA_INT_SEL [1:0]
CLKOUT_EN
DOUT_MUTE
RSSI_DET_SEL [1:0]
RX_TIMER_T2_R [3:0]
RX_EXTEND_MODE [3:0]
RSSI_AVG_MODE [2:0]
CLKOUT_DIV [4:0]
Bit 7
Bit 7
Bit 7
RESV
RESV
RESV
FEC_TYPE
CRC_BIT_ORDER
RESV
FIFO_AUTO_RES_EN
Bit 7
Bit 6
Bit 6
Bit 6
RESV
Bit 6
Bit 6
RESV
RESV
Bit 5
Bit 5
Bit 5
Bit 5
RX_PREAM_SIZE [4:0]
SYNC_TOL [2:0]
PAYLOAD_LENG [10:8]
NODE_FREE_EN
Bit 5
Bit 5
RSTN_IN_EN
LOCKING_EN
RESV
RF_SWT2_EN INT_POLAR
LFOSC_OUT_EN
RX_TMO_EN
TX_DIN_SEL [1:0]
TX_DIN_INV
TX_DONE_EN
RESV SL_TMO_FLG
Bit 6
RESV
RESV
COL_ERR_FLG
RX_FIFO_FULL_FLG
Bit 5
LBD_CLR
RESV
PKT_ERR_FLG
RX_FIFO_NMTY_FLG
Bit 4
Bit 4
Bit 4
Bit 4
Bit 3
Bit 3
Bit 3
TX_PREAM_SIZE [7:0]
TX_PREAM_SIZE [15:8]
PREAM_VALUE [7:0]
Bit 3
Bit 2
Bit 2
Bit 2
Bit 2
PREAM_LENG_UNIT
Bit 1
Bit 1
Bit 1
Bit 1
DATA_MODE [1:0]
Bit 0
Bit 0
Bit 0
Bit 0
SYNC_SIZE [2:0] SYNC_MAN_EN
SYNC_VALUE [7:0]
SYNC_VALUE [15:8]
SYNC_VALUE [23:16]
SYNC_VALUE [31:24]
SYNC_VALUE [39:32]
SYNC_VALUE [47:40]
SYNC_VALUE [63:56]
AUTO_ACK_EN
PAYLOAD_LENG [7:0]
NODE_ERR_MASK
NODE_VALUE [7:0]
NODE_VALUE [15:8]
NODE_LENG_POS_SEL
NODE_SIZE [1:0]
CRC_BIT_INV
NODE_VALUE [23:16]
NODE_VALUE [31:24]
CRC_RANGE
RESV
CRC_SEED [7:0]
CRC_SEED [15:8]
WHITEN_TYPE [1:0]
WHITEN_SEED [7:0]
RESV
TX_PKT_NUM [7:0]
TX_PKT_GAP [7:0]
FIFO_TH [6:0]
WHITEN_EN
RESV
PAYLOAD_BIT_ORDER
CRC_TYPE [1:0]
NODE_DET_MODE [1:0]
MANCH_TYPE
TX_PREFIX_TYPE [1:0]
PKT_TYPE
CRC_EN
MANCH_EN
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO3_SEL [1:0]
CHIP_MODE_SWT [7:0]
CFG_RETAIN
RESV
FH_CHANNEL [7:0]
FH_OFFSET [7:0]
PREAM_OK_EN
FIFO_AUTO_CLR_DIS
RX_TMO_FLG
RESV RESV
CHIP_MODE_STA [3:0]
SYNC_OK_EN
FIFO_TX_RD_EN
TX_DONE_FLG
GPIO2_SEL [1:0]
INT1_SEL [4:0]
INT2_SEL [4:0]
NODE_OK_EN
FIFO_RX_TX_SEL
TX_DONE_CLR
RESV
CRC_OK_EN
FIFO_MERGE_EN
SL_TMO_CLR
GPIO1_SEL [1:0]
RESV
PKT_DONE_EN
SPI_FIFO_RD_WR_SEL
RX_TMO_CLR
Bit 4 Bit 3
PREAM_OK_CLR
RESV
PREAM_OK_FLG
SYNC_OK_CLR
RESV
SYNC_OK_FLG
RX_FIFO_TH_FLG RX_FIFO_OVF_FLG
RSSI_CODE [7:0]
RSSI_DBM [7:0]
LBD_RESULT [7:0]
Bit 2
NODE_OK_CLR
FIFO_RESTORE
NODE_OK_FLG
TX_FIFO_FULL_FLG
Bit 1
CRC_OK_CLR
FIFO_CLR_RX
CRC_OK_FLG
TX_FIFO_NMTY_FLG
Bit 0
PKT_DONE_CLR
FIFO_CLR_TX
PKT_OK_FLG
TX_FIFO_TH_FLG
Function
CMT Bank
Function
System Bank
Function
Frequency Bank
Function
Data Rate Bank
Function
Baseband Bank
Function
TX Bank
Function
Control Bank 1
Function
Control Bank 2
Rev 1.0 | Page40/46 www.cmostek.com
CMT2300A
From the above table, it can be seen that the address range is from 0x00 to 0x71, which can be divided into 3 main banks for better understanding. They are: Configuration bank (including 6 sub-banks), Control Bank1, and Control Bank 2. For the 3 banks the address is continuous. They are all accessed via the SPI bus. They have different functionalities and design purposes, which are shown in the below table:
Address
0x00-0x0B
Bank Name
CMT Bank
Bank Name in the
RFPDKExport File
CMT Bank
Functionality
Users do not change them.
0x0C-0x17
0x18-0x1F
System Bank
Frequency Bank
System Bank
Frequency Bank
Mainly relates to low power mode.
To setup the TX and RX frequencies.
0x20-0x37
0x38-0x54
0x55-0x5F
Configuration Bank
(RFPDKexportthe register values ）
Data Rate Bank
Baseband Bank
TX Bank
Data Rate Bank
Baseband Bank
TX Bank
To setup data rate, deviation, bandwidths and other related parameters.
To setup packet format and some FIFO features.
To setup TX deviation and power.
0x60-0x6A
Control Bank 1 （ Set by MCU in application, not generated by RFPDK ）
--
To setup chip working state, frequency hopping, GPIOs and interrupts control.
Control Bank 1 （ Set by MCU in To read interrupt flags and RSSI value,
0x6B-0x71 -- application, not generated by RFPDK ） control the FIFO.
To simplify the operation, users should firstly setup all the desired parameters on the RFPDK, export the register contents to the
HEX file, and use it to initialize the CMT2300A. For the CMT Bank, Frequency Bank, Data Rate Bank, and the TX Bank, users do not need to study the details of the registers. Instead, these register configurations totally rely on the RFPDK. For System Bank and Baseband Bank, users must study the details in order to play with them in different applications. Meanwhile, for Control Bank
1 and 2, users must also understand the meaning of each register.
CMOSTEK provides a series Application Notes (AN) for the users to studyhow to play with the chip, how to configure the parameters on RFPDK, how to use each register, and other notable application skills. Users can start their learning from reading
“AN142 CMT2300AW Quick Start Guide”, which provides step-by-step guidance and leads the users to read other documents.
Rev 1.0 | Page41/46 www.cmostek.com
CMT2300A
Part Number Descriptions Packaging Packing Condition
CMT2300A-EQR [1]
CMT2300A, Ultra Low Power
Sub-1GHz RF Transceiver
QFN16 (3x3) Tape& Reel
Note:
[1]. “E” represents extended industrial grade.The temperature range is from -40 to +85.
“Q” represents QFN16 packaging.
“R” represents tape &reel packing. MOQ is 3000pcs.
For more information about product, please visit www.cmostek.com
.
For purchasing or price requirements, please contact [email protected]
or local sales representative.
1.8 to 3.6V,
-40 to 85 ℃
MOQ
3,000
Rev 1.0 | Page42/46 www.cmostek.com
CMT2300A packaging is QFN16 (3x3). The packaging information is as below.
D e
16
1
Top View b
D2
1
Bottom View
16
CMT2300A
Symbol
D
D2 e
E
A
A1 b c
E2
L
Side View
Size (mm)
Min.
0.7
—
0.18
0.18
2.90
1.55
0.50 BSC
2.90
1.55
0.35
Max.
0.8
0.05
0.30
0.25
3.10
1.75
3.10
1.75
0.45
Rev 1.0 | Page43/46 www.cmostek.com
CMT2300A
Marking method
Pin 1 mark
Font size
Line 1 marking
Line 2 marking
Line 3 marking
3 0 0 A
① ② ③ ④
Y WW
Laser
Circle diameter = 0.3 mm
0.5 mm,
300A represents model CMT2300A
①②③④ represents th e internal tracking coding
Date code is assigned by assembly factory. Y represents the last digit of the year. WW represents working week.
Rev 1.0 | Page44/46 www.cmostek.com
CMT2300A
Preliminary
Preliminary 0.2
0.6
0.7
0.8
0.9
1.0
All
5.14.1
5.14.2
All
All
All
All
All
Preliminary version for internal verification
Update 1 st paragraph
Update Table 34
Split Chapter 5 and 6 from Chapter 4
Initial release for production version
Changed T&R to 3,000 pcs
Added AN document list
Added new RF parameters and curves
Added and changed some performance numbers
Changed RSSI descriptions
Added POR descriptions
Added PJD, AFC and CDR descriptions
Added receiver “Power VS Performance” descriptions
Changed some characters and figures
Detected the AN document list
Changed some decriptions
2015-06-09
2015-06-10
2015-08-06
2017-03-22
2017-08-10
2018-01-03
2018-01-15
Rev 1.0 | Page45/46 www.cmostek.com
Wuxi CMOSTEK Microelectronics Co., Ltd. Shenzhen Branch
Room 203, Honghai Building, Qianhai Road, Nanshan District, Shenzhen, Guangdong, China
Zip Code: 518000
Tel:
Fax:
+86 - 755 - 83235017
+86 - 755 - 82761326
Sales: [email protected]
Technical support: [email protected]
Website: www.cmostek.com
CMT2300A
Copyright. CMOSTEK Microelectronics Co., Ltd. All rights are reserved.
The information furnished by CMOSTEK is believed to be accurate and reliable. However, no responsibility is assumed for inaccuracies and specifications within this document are subject to change without notice. The material contained herein is the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support devices or systems without express written approval of CMOSTEK. The CMOSTEK logo is a registered trademark of
CMOSTEK Microelectronics Co., Ltd. All other names are the property of their respective owners.
Rev 1.0 | Page46/46 www.cmostek.com
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Frequency range: 127 ~ 1020MHz
Modulation: OOK, (G)FSK, (G)MSK
Data rate: 0.5 ~ 300 kbps
Sensitivity: Up to -121 dBm
Ultra-low power consumption
Configurable packet handler and 64-Byte FIFO
The CMT2300A supports OOK, (G)FSK, and (G)MSK modulation.
The CMT2300A operates in the frequency range of 127 MHz to 1020 MHz.
The CMT2300A supports data rates from 0.5 kbps to 300 kbps.
The CMT2300A features a sleep current of 300 nA when the duty cycle is off and 800 nA when it's on.
CMT2300A is suitable for automatic meter reading, home security and building automation, ISM band data communication and more.
How to perform fast frequency switching during transmission on the CMT2300A?
Configure FH_OFFSET (0x64) during initialization, then modify the FH_CHANNEL (0x63) register via SPI to switch channels. If in TFS state, follow the state machine requirements (such as the go_tfs instruction). The typical frequency tuning time is 150 μs.
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