CMOSTEK CMT2300A-EQR Manual
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CMT2300A
Features
CMT2300A
Ultra-low Power Sub-1GHz RF Transceiver
SoC
Frequency range: 127 ~1020 MHz
Modem: OOK, (G)FSK and (G)MSK
Data rate: 0.5 ~ 300 kbps
Sensitivity: - 121 dBm 2.0 kbps, FRF = 433.92 MHz
-111 dBm 50 kbps, FRF = 433.92 MHz
Voltage range: 1.8 ~3.6 V
Transmit current: 23 mA @ 13 dBm, 433.92 MHz, FSK
72 mA @ 20 dBm, 433.92 MHz, FSK
Rx current: 8.5 mA @ 433.92 MHz, FSK (High power mode)
7.2 mA @ 433.92 MHz, FSK (Low power mode)
Super-low Power receive mode
Sleep current: 300 nA, Duty Cycle = OFF
800 nA, Duty Cycle = ON
Receiver features:
Fast and stable automatic frequency control (AFC)
3 types of clock data recovery system (CDR)
Fast and accurate signal detection (PJD)
4-wire SPI interface
Direct and packet mode supported
Configurable packet handler and 64-Byte FIFO.
NRZ, Manchester codec, Whitening codec, Forward
Error Correction (FEC)
Automatic meter reading
Home security and building automation
ISM band data communication
Industrial monitoring and control
Remote control and security system
Remote key entry
Wireless sensor node
Tag reader
Ordering Information
Model Frequency Package MOQ
CMT2300A-EQR 433.92 MHz QFN16 3,000 pcs
Please see Table 23 for more ordering details.
Description
CMT2300A is an ultra-low power, high performance, OOK (G)
FSK RF transceiver suitable for a variety of 140 to 1020 MHz wireless applications. It is part of the CMOSTEK
NextGenRF
TM
RF product line. The product line contains the complete transmitters, receivers and transceivers. The high integration of CMT2300A simplifies the peripheral materials required in the system design. Up to +20 dBmTx Power and
-121 dBm sensitivity optimize the performance of the application. It supports a variety of packet formats and codec methods to meet the needs of various different applications.
In addition, CMT2300A also supports 64-byte Tx/Rx
FIFO, GPIO and interrupt configuration, Duty-Cycle operation mode, channel sensing, high-precision RSSI, low-voltage detection, power-on reset, low frequency clock output, manual fast frequency hopping, squelch and etc. The features make the application design more flexible and differentiated. CMT2300A operates from 1.8 V to 3.6 V. Only
8.5 mA current is consumed when the sensitivity is -121 dBm,
SuperLow Power mode can further reduce the chip power consumption. Only 23mA Tx current is consumed when the output power is 13 dBm.
QFN16 (3 X 3) Packaging
RFIP 1
RFIN 2
PA 3
AVDD 4
16 15 14 13
17
GND
12 FCSB
11 CSB
10 SDIO
9 SCLK
5 6 7 8
CMT2300 Top View www.cmostek.com
Rev1.0a | 1/50
CMT2300A
Table of Contents
（
）
Rev1.0a | 2/50 www.cmostek.com
CMT2300A
Rev1.0a | 3/50 www.cmostek.com
CMT2300A
1. Electrical Characteristics
V
DD
= 3.3 V, T
OP
= 25 °C, F
RF
= 433.92 MHz, the sensitivity is measured by receiving a PN9 coded data and matching the impedance to 50Ω under the 0.1%BER standard. Unless otherwise stated, all results are tested on the CMT2300A-EM evaluation board.
1.1 Recommended Operation Condition
Table 1. Recommended Operation Conditions
Parameter
Power voltage
Operating temperature
Power voltage slope
Symbol
V
DD
T
OP
1.2 Absolute Maximum Rating
Condition Min.
1.8
-40
1
Typ.
Max.
3.6
85
Unit
V
℃ mV/us
Table 2. Absolute Maximum Ratings
[1]
Parameter Symbol Conditions Min Max Unit
Supply Voltage
Interface Voltage
Junction Temperature
Storage Temperature
V
DD
T
V
T
IN
J
STG
-0.3
-0.3
-40
-50
3.6
V
DD
+0.3
125
150
V
Soldering Temperature
ESD Rating
[2]
Latch-up Current
T
SDR
Lasts at least 30 seconds
Human Body Model (HBM)
@ 85 ℃
-2
-100
255
2
100 kV mA
Notes:
[1]. Exceeding the Absolute Maximum Ratings may cause permanent damage to the equipment. This value is a pressure
V
℃
℃
℃ rating and does not imply that the function of the equipment is affected under this pressure condition, but if it is exposed to absolute maximum ratings for extended periods of time, it may affect equipment reliability.
[2]. The CMT2300A is a high performance RF integrated circuit. The operation and assembly of this chip should only be performed on a workbench with good ESD protection.
[2].
Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.
Rev1.0a | 4/50 www.cmostek.com
CMT2300A
1.3 Power Consumption
Table 3. Power Consumption Specification
Parameter
Sleep current
Standby current
RFS current
TFS current
RXcurrent (high power mode)
RX current (low power mode)
TX current
Symbol
I
SLEEP
Condition
Sleep mode, sleep timer is off
Sleep mode, sleep timer is on
I
Standby
Crystal oscillator is on
433 MHz
I
RFS
868 MHz
915 MHz
433 MHz
I
TFS
868 MHz
I
Rx-HP
I
Rx-LP
915 MHz
FSK, 433 MHz, 10 kbps,10 kHz F
DEV
FSK, 868 MHz, 10 kbps, 10 kHz F
DEV
FSK, 915 MHz, 10 kbps,10 kHz F
DEV
FSK, 433 MHz, 10 kbps, 10 kHz F
DEV
FSK, 868 MHz, 10 kbps, 10 kHz F
DEV
FSK, 915 MHz, 10 kbps, 10 kHz F
DEV
FSK, 433 MHz, +20 dBm (Direct Tie)
FSK, 433 MHz, +20 dBm (RF switch)
FSK, 433 MHz, +13 dBm (Direct Tie)
FSK, 433 MHz, +10 dBm (Direct Tie)
I
Tx
FSK, 433 MHz, -10 dBm(Direct Tie)
FSK, 868 MHz, +20 dBm(Direct Tie)
FSK, 868 MHz, +20 dBm(RF switch)
FSK, 868 MHz, +13 dBm (Direct Tie)
FSK, 868 MHz, +10 dBm (Direct Tie)
FSK, 868 MHz, -10 dBm (Direct Tie)
FSK, 915 MHz, +20 dBm (Direct Tie)
FSK, 915 MHz, +20 dBm (RF switch)
FSK, 915 MHz, +13 dBm (Direct Tie)
FSK, 915 MHz, +10 dBm (Direct Tie)
FSK, 915 MHz, -10 dBm (Direct Tie)
Min.
8
87
80
27
19
8
70
75
28
19
8
7.3
7.6
72
77
23
18
5.6
5.9
5.9
8.5
8.6
8.9
7.2
Typ.
300
800
1.45
5.7
5.8
5.8
Max.
Unit nA nA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Rev1.0a | 5/50 www.cmostek.com
CMT2300A
1.4 Receiver
Table 4. Receiver specification
Parameter
Data rate
Deviation
Sensitivity
@ 433 MHz
Sensitivity
@ 868 MHz
Sensitivity
@ 915 MHz
Symbol
DR
S
F
DEV
433-HP
Condition
OOK
FSK and GFSK
FSK and GFSK
DR = 2.0 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz （ Low power setting ）
DR = 20 kbps, F
DEV
= 20 kHz
DR = 20 kbps, F
DEV
= 20 kHz （ Low power setting ）
DR = 50 kbps, F
DEV
= 25 kHz
DR =100 kbps, F
DEV
= 50 kHz
DR =200 kbps, F
DEV
= 100 kHz
DR =300 kbps, F
DEV
= 100 kHz
DR = 2.0 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz （ Low power setting ）
DR = 20 kbps, F
DEV
= 20 kHz
DR = 20 kbps, F
DEV
= 20 kHz （ Low power setting ）
S
868-HP
S
915-HP
DR = 50 kbps, F
DEV
= 25 kHz
DR =100 kbps, F
DEV
= 50 kHz
DR =200 kbps, F
DEV
= 100 kHz
DR =300 kbps, F
DEV
= 100 kHz
DR = 2.0 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz
DR = 10 kbps, F
DEV
= 10 kHz （ Low power mode ）
DR = 20 kbps, F
DEV
= 20 kHz
DR = 20 kbps, F
DEV
= 20 kHz （ Low power mode ）
DR = 50 kbps, F
DEV
= 25 kHz
DR =100 kbps, F
DEV
= 50 kHz
DR =200 kbps, F
DEV
= 100 kHz
DR =300 kbps, F
DEV
= 100 kHz
Saturation Input Signal Level
Image Rejection Ratio
RX Channel
Bandwidth
Co-channel Rejection
Ratio
Adjacent Channel
Rejection Ratio
P
LVL
F
RF
=433 MHz
IMR
BW
F
RF
=868 MHz
F
RF
=915 MHz
RX channel bandwidth
CCR
ACR-I
DR = 10 kbps, F
DEV
= 10 kHz; Interference with the same modulation
DR = 10 kbps, F
DEV
= 10 kHz; BW=100kHz, 200 kHzChannel spacing, interference with the same modulation
Rev1.0a | 6/50
Min.
0.5
0.5
2
Typ.
Max.
40
Unit kbps
300 kbps
200 kHz
-121
-116
-115 dBm dBm dBm
-113
-112
-111
-108 dBm dBm dBm dBm
-105
--103
-119
-113 dBm dBm dBm dBm
-111
-111 dBm dBm
-109 dBm
-108
-105
-102 dBm dBm dBm
-99
-117
-113
-111
-111
-109
-109
-105
-102
-99
20 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
35 dBc
33
33 dBc dBc
50 500 kHz
-7 dBc
30 dBc www.cmostek.com
CMT2300A
Parameter
AlternateChannel
Rejection Ratio
Blocking Rejection
Ratio
Input 3 rd
Order
Intercept Point
RSSIRange
More Sensitivity
(Typical Configuration)
Symbol Condition
ACR-II
BI
IIP3
RSSI
DR = 10 kbps, F
DEV
= 10 kHz; BW=100kHz, 400 kHz Channel spacing, interference with the same modulation
DR = 10 kbps, F
DEV
= 10 kHz; ±1 MHz Deviation, continuous wave interference
DR = 10 kbps, F
DEV
= 10 kHz; ± 2 MHz Deviation, continuous wave interference
DR = 10 kbps, F
DEV
= 10 kHz; ±10 MHz Deviation, continuous wave interference
DR = 10 kbps, F
DEV
= 10 kHz; 1 MHz and 2 MHz
Deviation dual tone test, maximum system gain setting.
433.92 MHz, DR = 1.2kbps, F
DEV
= 5 kHz
433.92 MHz, DR = 1.2kbps, F
DEV
= 10 kHz
433.92 MHz, DR = 1.2kbps, F
DEV
= 20 kHz
433.92 MHz, DR = 2.4kbps, F
DEV
= 5 kHz
433.92 MHz, DR = 2.4kbps, F
DEV
= 10 kHz
433.92 MHz, DR = 2.4kbps, F
DEV
= 20 kHz
433.92 MHz, DR = 9.6 kbps, F
DEV
= 9.6 kHz
433.92 MHz, DR = 9.6 kbps, FDEV = 19.2 kHz
Min.
-120
433.92 MHz, DR = 20 kbps, FDEV = 10 kHz
433.92 MHz, DR = 20 kbps, FDEV = 20 kHz
433.92 MHz, DR = 50 kbps, FDEV = 25 kHz
433.92 MHz, DR = 50 kbps, FDEV = 50 kHz
433.92 MHz, DR = 100 kbps, FDEV = 50 kHz
433.92 MHz, DR = 200 kbps, FDEV = 50 kHz
433.92 MHz, DR = 200 kbps, FDEV = 100 kHz
433.92 MHz, DR = 300 kbps, FDEV = 50 kHz
433.92 MHz, DR = 300 kbps, FDEV = 150 kHz
Typ.
45
70
72
75
-25
-114.2
-113.0
-110.6
-109.0
-107.8
-103.5
-104.3
-98.0
-101.6
-122.9
-121.8
-119.5
-120.6
-120.3
-119.7
-116.0
-116.1
Max.
20
Unit dBc dBc dBc dBc dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
Rev1.0a | 7/50 www.cmostek.com
CMT2300A
1.5 Transmitter
Table 5. Transmitter Specifications
Parameter
Output power
Output power step
GFSK Gaussian filter
Symbol
P
OUT
Condition
Need specific peripheral materials for different frequency bands
P
STEP
BT
Min.
-20
0.3
Typ.
1
0.5
Max.
+20
1.0
Unit dBm dB
- coefficient
Output power variation
Stray radiation
Harmonic output for
F
RF
= 433 MHz
[1]
F
RF
= 868 MHz
[1]
F
RF
= 915 MHz
F
RF
= 915 MHz
[1]
[1]
Harmonic output for
Harmonic output for
Harmonic output for
F
RF
= 433 MHz
[1]
Harmonic output for
F
RF
= 868 MHz
[1]
Harmonic output for
P
OUT-TOP
H2
433
H3
433
H2
868
H3
868
H2
868
H3
868
H2
433
H3
433
H2
H3
868
868
H2
868
H3
868
Temperature from -40 to +85 C
P
OUT
= +13 dBm,433MHz, F
RF
<1 GHz
1 GHz to 12.75 GHz, with harmonic
2 nd harmonic +20 dBm P
OUT
3 nd harmonic +20 dBm P
OUT
2 nd harmonic +20 dBm P
OUT
3 nd harmonic +20 dBm P
OUT
2 nd harmonic +20 dBm P
OUT
3 nd harmonic +20 dBm P
OUT
2 nd harmonic +13 dBm P
OUT
3 nd harmonic +13 dBm P
OUT
2 nd harmonic +13 dBm P
OUT
3 nd harmonic +13 dBm P
OUT
2 nd harmonic +13 dBm P
OUT
3 nd harmonic +13 dBm P
OUT
1
-46
-50
-43
-52
-48
-53
-52
-52
-52
-52
-52
-52
-42
-36
Notes:
[1]. The harmonic parameter values mainly depend on the quality of the hardware matching network. The above data is measured based on the CMT2300A-EM module. dB dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
1.6 Settling Time
Table 6. Settling Time
Parameter
Settle time
Symbol
T
SLP-RX
T
SLP-TX
T
STB-RX
T
STB-TX
T
RFS-RX
T
TFS-RX
T
TX-RX
Condition
From Sleep to RX
From Sleep to TX
From Standby to RX
From Standby to TX
From RFS to RX
From TFS to TX
From TX to RX
（ Ramp Down time needs 2T symbol
）
Min.
Typ.
1000
1000
350
350
20
20
2T symbol
+350
350 T
RX-TX
From RX to TX
Notes:
[1]. T
SLP-RX
and T
SLP-TX depend on the crystal oscillator startup time, which is related to crystal characteristics.
Max.
Unit us us us us us us us us
Rev1.0a | 8/50 www.cmostek.com
CMT2300A
1.7 Frequency Synthesizer
Parameter
Frequency range
Frequency resolution
Frequency tuning time
Phase noise@ 433
MHz
Phase noise@ 868
MHz
Phase noise@ 915
MHz
Table 7. Frequency Synthesizer Specifications
Symbol
F
RF
Condition
Need different matching networks
Min.
760
380
190
127
Typ.
F
RES t
TUNE
PN
433
PN
868
PN
915
10 kHz frequency deviation
100 kHz frequency deviation
500 kHz frequency deviation
1MHz frequency deviation
10 MHz frequency deviation
10 kHz frequency deviation
100 kHz frequency deviation
500 kHz frequency deviation
1MHz frequency deviation
10 MHz frequency deviation
10 kHz frequency deviation
100 kHz frequency deviation
500 kHz frequency deviation
1MHz frequency deviation
10 MHz frequency deviation
95
-114
-121
-130
-89
-92
-111
-121
-130
25
150
-94
-99
-118
-127
-134
-92
Max.
1020
510
340
170
Unit
MHz
MHz
MHz
MHz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Hz us dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Rev1.0a | 9/50 www.cmostek.com
CMT2300A
1.8 Crystal Oscillator
Table 8. Crystal Oscillator Specifications
Parameter
Crystal frequency
[1]
Frequency tolerance
[2]
Load capacitance
Equivalent resistance
Start-up time [3]
Symbol
F
XTAL ppm
C
LOAD
Rm t
XTAL
Condition Min.
Typ.
26
20
15
60
400
Max.
Unit
MHz ppm pF
Ω us
Notes:
[1]. CMT2300A can use the external reference clock to drive the XIN pin through the coupling capacitor. The peak value of the external clock signal is between 0.3V and 0.7V.
[2]. The value includes (1) initial error; (2) crystal load; (3) aging; and (4) change with temperature. The acceptable crystal frequency tolerance is limited by the receiver bandwidth and the RF frequency offset between the transmitter and the receiver.
[3]. The parameter is largely related to the crystal.
1.9 Low Frequency Oscillator
Table 9. Low Frequency Oscillator Specifications
Parameter
Calibration frequency [1]
Frequency accuracy
Temperature coefficient
[2]
Supply voltage coefficient [3]
Initial calibration time
Symbol Condition
F
LPOSC t
LPOSC-CAL
After calibration
Min.
Typ.
32
±1
-0.02
+0.5
4
Max.
Notes:
[1]. The low frequency oscillator is automatically calibrated to the crystal oscillator frequency at the PUP stage and periodically calibrated at this stage.
[2]. After calibration, the frequency changes with temperature.
[3]. After calibration, the frequency changes with the change of the supply voltage.
Unit kHz
%
%/°C
%/V ms
Rev1.0a | 10/50 www.cmostek.com
1.10 Low Battery Detection
Parameter
Table 10. Low Battery Detection Specifications
Symbol Condition Min.
Detection accuracy
1.11 Digital Interface
LBD
RES
Typ.
50
Max.
Parameter
Digital input high level
Digital input low level
Digital output high level
Digital output low level
SCLK Frequency
SCLK high time
SCLK low time
SCLKrise time
SCLKfall time
Symbol
Table 11. Digital interface specifications
Condition Min.
V
IH
V
IL
V
OH
V
OL
F
SCL
T
CH
T
CL
T
CR
T
CF
@I
OH
= -0.5mA
@I
OL
= 0.5mA
1.12 Figures of Critical Parameters
1.12.1 Rx Current VS. Supply Voltage
0.8
Vdd-0.4
50
50
50
50
Typ.
Max.
0.2
0.4
5
CMT2300A
Unit mV
Unit
V
DD
V
DD
V
V
MHz ns ns ns ns
Rx Current vs. Supply Voltage
434MHz
868MHz
8.80
8.60
8.40
8.20
8.00
7.80
7.60
7.40
1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage(V)
Testing Condition: Freq = 434MHz / 868MHz, Fdev = 10KHz, BR = 10Kbps
Rev1.0a | 11/50 www.cmostek.com
1.12.2 Rx Current VS. Voltage Temperature
Rx Current vs. Volt-Temp
9.5
9.3
9.0
8.8
8.5
8.3
8.0
7.8
7.5
7.3
7.0
-40 25
Temperature( ℃ )
Test Condition: Freq = 434MHz,Fdev = 10KHz, BR = 10Kbps
Rx Current vs. Volt-Temp
9.5
9.3
9.0
8.8
8.5
8.3
8.0
7.8
7.5
7.3
7.0
-40 25
Temperature( ℃ )
Test Condition: Freq = 868MHz, Fdev = 10KHz, BR = 10Kbps
1.12.3 Sensitivity VS. Voltage
85
85
3.3V
3.6V
3.3V
1.8V
3.6V
1.8V
CMT2300A
Rev1.0a | 12/50 www.cmostek.com
Sensitivity vs. Voltage
-113.0
-113.5
-114.0
-114.5
-115.0
-115.5
-116.0
-116.5
-117.0
-117.5
1.8 2.1 2.4 2.8
Supply Voltage(V)
3.0
Test Condition: FSK modulation, DEV = 10KHz, BR = 10Kbps
1.12.4 Sensitivity VS. Temperature
Sensitivity vs. Temperature
3.3
-112.0
-113.0
-114.0
-115.0
-116.0
-117.0
-118.0
-40 25
Temperature( ℃ )
Test Condition: FSK, DEV = 10KHz, BR = 10Kbps
Rev1.0a | 13/50
85
434MHz
868MHz
CMT2300A
3.6
434MHz
868MHz www.cmostek.com
1.12.5 Tx Power VS. Supply Voltage
Tx Power vs. Supply Voltage
20dBm
13dBm
20.0
19.0
18.0
17.0
16.0
15.0
14.0
13.0
12.0
11.0
10.0
1.8 1.9 2.0 2.1 2.2 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage(V)
Test Condition: Freq = 434 MHz, 20 dBm / 13dBm matching network
CMT2300A
Tx Power vs. Supply Voltage
13dBm
20dBm
20.0
19.0
18.0
17.0
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
1.8 1.9 2.0 2.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage(V)
Test Condition: Freq = 868 MHz, 20 dBm / 13dBm matching network
1.12.6 Tx Phase Noise
Rev1.0a | 14/50 www.cmostek.com
-20
-40
-60
20
0
-80
-100
866
CMT2300A
433.92MHz Phase Noise
output 13dBm span=4MHz att30dB
13.4dBm
20
0
-20
-40
-60
-80
-100
431.92 432.42 432.92 433.42 433.92 434.42 434.92 435.42 435.92 center 433.92MHz sweep 5s (2000pts )
Res BW 1kHz
868MHz Phase Noise
output 13dBm span=4MHz att30dB
12.4dBm
866.5 867 867.5 868 868.5 869 869.5 center 868MHz sweep 5s (2000pts )
870
Res BW 1kHz
Rev1.0a | 15/50 www.cmostek.com
CMT2300A
2. Pin Descriptions
RFIP 1
RFIN 2
PA 3
AVDD 4
16 15 14 13
17
GND
12 FCSB
11 CSB
10 SDIO
9 SCLK
5 6 7 8
Figure 1. CMT2300A pin descriptions
Pin #
1
2
3
4
5
6
7
8 [1]
Name
RFIP
RFIN
PA
AVDD
AGND
DGND
DVDD
GPIO3
O
IO
IO
I/O
I
I
IO
IO
IO
Table 12. CMT2300A Pin Descriptions
Internal IO Schematic
VDD pd_dout default value is “0” pd_dout
GPIO3
Data tristate dout
Descriptions
RF signal input P
RF signal input N
PA output
Analog VDD
Analog GND
Digital GND
Digital VDD
Configured as CLKO,
DOUT/DIN, INT2 and
DCLK (TX/RX)
9 SCLK I pd_din pd_din default value is “1”
VDD
SCLK
Buffer din din
SPI clock
Rev1.0a | 16/50 www.cmostek.com
Pin #
10
Name
SDIO
I/O
IO
SDIO
VDD
Internal IO Schematic pd_dout default value is “1” pd_dout
Data tristate dout
CMT2300A
Descriptions
SPI data input and output
11
12
CSB
FCSB
13
14
15 [1]
XI
XO
GPIO2
I pd_din pd_din default value is
“0”
VDD
CSB din
Buffer
SPI chip selection bar for register access, active low
I
I
O
IO
VDD
GPIO2
FCSB
VDD
SPI chip selection bar for
FIFO access, active low
Buffer
Data tristate dout pd_dout default value is “0” pd_dout
Crystal circuit input
Crystal circuit output
Configured as INT1, INT2,
DOUT/DIN, DCLK
(TX/RX) and RF_SWT
16 [1]
GPIO1 IO
GPIO1
VDD pd_din pd_din default value is “1”
Data tristate din pd_dout default value is “0” pd_dout dout
Configured as DOUT/DIN,
INT1, INT2, DCLK
(TX/RX) and RF_SWT pd_din pd_din default value is “1” din
17 GND I Analog GND. It must be grounded.
Notes:
[1]. [1]INT1 and INT2 are interrupts. DOUT is demodulated output. DIN is a modulation input. DCLK is a modulation or demodulation data rate synchronization clock, automatic switching in TX/RX mode.
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CMT2300A
3. Typical Application Schematic
3.1 Direct Tie Schematic Diagram
Figure 2. Direct Tie Application Schematic Diagram
Table 13. 13 dBm direct tie application BOM
No.
Descriptions
C1 ±5%, 0603 NP0, 50 V
C2 ±5%, 0603 NP0, 50 V
C3 ±5%, 0603 NP0, 50 V
C4 ±5%, 0603 NP0, 50 V
C5 ±5%, 0603 NP0, 50 V
C6 ±5%, 0603 NP0, 50 V
C7 ±5%, 0603 NP0, 50 V
C8 ±5%, 0603 NP0, 50 V
C9 ±5%, 0603 NP0, 50 V
C10 ±5%, 0603 NP0, 50 V
C11 ±5%, 0603 NP0, 50 V
L1 ±5%, 0603 Multilayer chip inductor
L2 ±5%, 0603 Multilayer chip inductor
L3 ±5%, 0603 Multilayer chip inductor
L4 ±5%, 0603 Multilayer chip inductor
L5 ±5%, 0603 Multilayer chip inductor
L6 ±5%, 0603 Multilayer chip inductor
L7 ±5%, 0603 Multilayer chip inductor
L8 ±5%, 0603 Multilayer chip inductor
Y1 ±10 ppm, SMD32*25 mm
U1
CMT2300A, Ultra Low Power Sub-1GHz RF
Transceiver
18
27
27
68
180
56
39
18
433 MHz
+13 dBm
15
5.6
7.5
24
24
4.7
4.7
2.2
2.2
4.7
470
0.1
0.1
100
10
Values
868 MHz
+13dBm
22
6.2
3.6
24
24
8.2
10
10
15
15
12
26
8.2
12
12
12
100
8.2
6.8
8.2
915 MHz
+13dBm
22
6.2
3.3
24
24
2.2
2.2
Unit pF pF pF pF pF pF pF uF pF uF uF nH nH nH nH nH nH nH nH
MHz
-
Rev1.0a | 18/50
Supplier
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
EPSON
CMOSTEK www.cmostek.com
CMT2300A
No.
C1 ±5%, 0603 NP0, 50 V
C2 ±5%, 0603 NP0, 50 V
C3 ±5%, 0603 NP0, 50 V
C4 ±5%, 0603 NP0, 50 V
C5 ±5%, 0603 NP0, 50 V
C6 ±5%, 0603 NP0, 50 V
C7 ±5%, 0603 NP0, 50 V
C8 ±5%, 0603 NP0, 50 V
C9 ±5%, 0603 NP0, 50 V
C10 ±5%, 0603 NP0, 50 V
C11 ±5%, 0603 NP0, 50 V
L1 ±5%, 0603 Multilayer chip inductor
L2 ±5%, 0603 Multilayer chip inductor,
L3 ±5%, 0603 Multilayer chip inductor
L4 ±5%, 0603 Multilayer chip inductor
L5 ±5%, 0603 Multilayer chip inductor
L6 ±5%, 0603 Multilayer chip inductor
L7 ±5%, 0603 Multilayer chip inductor
L8 ±5%, 0603 Multilayer chip inductor
Y1 ±10 ppm, SMD32*25 mm
U1
CMT2300A, Ultra Low Power Sub-1GHz RF
Transceiver
Table 14. 20 dBm Direct Tie Application BOM
Descriptions 433 MHz
+20 dBm
15
3.0
6.2
24
24
4.7
4.7
180
22 cap 15pF
33
33
27
27
68
Values
868 MHz
+20 dBm
18
4.7
470
0.1
0.1
100
12
3.6
3.3
24
24
2
2
15
6.2
6.2
15
15
12
26
915 MHz
+20 dBm
Unit
18
3.6
3.3
24
24
1.8
1.8 pF pF pF pF pF pF pF uF pF uF uF
100 nH
12 nH
15
6.2
6.2
15
15
12 nH nH nH nH nH nH
MHz
-
Supplier
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
EPSON
CMOSTEK
Rev1.0a | 19/50 www.cmostek.com
3.2 RF Switch Type Schematic
Figure 3. Application Schematic Diagram for RF Switch Type
CMT2300A
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CMT2300A
L5
L6
L7
L8
No.
C1
C2
C3
C4
C5
C6
C7
C8
Figure 15. Typical Application BOM for RF Switch Type
Values
Descriptions
±5%, 0402 NP0, 50 V
434 MHz
+20 dBm
15
868 /915 MHz
+20 dBm
15
Unit pF
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
±5%, 0402 NP0, 50 V
C9 ±5%, 0402 NP0, 50 V
C10 ±5%, 0402 NP0, 50 V
C11 ±5%, 0402 NP0, 50 V
C12 ±5%, 0402 NP0, 50 V
C13 ±5%, 0402 NP0, 50 V
C14 ±5%, 0402 NP0, 50 V
C15 ±5%, 0402 NP0, 50 V
C16 ±5%, 0402 NP0, 50 V
C17 ±5%, 0402 NP0, 50 V
10
8.2
8.2
18nH
4.7
4.7
220
220
24
24
10
10
0.1
0.1
470
2200
4.7
24
24
10
10
3.9
2.7
2.7
220
2
2
220
220 uF pF pF uF pF pF pF pF pF pF pF uF pF uF
C18 ±5%, 0402 NP0, 50 V
C19 ±5%, 0402 NP0, 50 V
C20 ±5%, 0402 NP0, 50 V
C21 ±5%, 0402 NP0, 50 V
C22 ±5%, 0402 NP0, 50 V
L1 ±5%, 0603 Multilayer chip inductor
L2
L3
L4
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
180
27
18
33
15
27
27
68
27
27
27
27
100
6.8
12
22
10
12
12
18 nH nH nH nH pF pF pF nH nH pF pF pF pF nH nH
Y1
U1
U2
R1
R2
±10 ppm, SMD32*25 mm
CMT2300A, Ultra Low Power Sub-1GHz RF
±5%, 0402
±5%, 0402
2.2
2.2
26
-
-
- kΩ kΩ
MHz
-
CMOS
-
TEK
Supplier
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
EPSON
CMOSTEK
SKYWORKS
Rev1.0a | 21/50 www.cmostek.com
No.
Descriptions
L2
L3
L4
L5
L6
L7
L8
Y1
U1
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±5%, 0402 Multilayer chip inductor
±10 ppm, SMD32*25 mm
CMT2300A, Ultra Low Power Sub-1GHz RF
Transceiver
U2 AS179, PHEMT GaAs IC SPDT Switch
R1 ±5%, 0402
R2 ±5%, 0402
CMT2300A
434 MHz
+20 dBm
27
18
33
15
27
27
68
Values
868 /915 MHz
+20 dBm
6.8
12
22
10
12
12
18
26
Unit nH nH nH nH nH nH nH
MHz
- -
Supplier
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
Sunlord SDCL
EPSON
CMOSTEK
-
2.2
2.2
- kΩ kΩ
SKYWORKS
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CMT2300A
4. Function Descriptions
CMT2300A is an ultra-low power, high performance transceiver chip. It supports OOK, (G) FSK and (G) MSK. It is suitable for applications in the range from 140 to 1020 MHz. The product belongs to CMOSTEK NextGenRF TM series. The series includes transmitters, receivers and transceivers and other complete product lines. CMT2300A block diagram is as shown in the following figure.
XIN XOUT
VCO
LFOSC LDOs POR
Bandgap
VDD
GND
LOOP
FILTER
CP PFD
26 Mhz
XO
Registers
PA PA D-DIV M-DIV
AFC LOOP
Radio
Controller
SPI, FIFO
Interface
FCSB
CSB
SCLK
SDIO
I LMT
RXIP
RXIN
LNA
Q LMT
RSSI
MODEM
Packet Handler
FIFO
IO
Ctrl
GPIO 1
GPIO 2
GPIO 3
ADC
AGC LOOP
Figure 4. Functional Block Diagram
In the receiver part, the chip uses LNA+MIXER+IFFILTER+LIMITTER+PLL low-IF architecture to achieve the Sub-GHz wireless reception function. The chip uses PLL+PA architecture to achieve the Sub-GHz wireless transmitting function.
In the receiver system, the analog circuit mixes the RF signal to IF and converts the signal from analog to digital through the Limiter module, then outputs I/Q two single bit signals to the digital circuit for (G) FSK demodulation. At the same time, SARADC will convert the real-time RSSI signal to 8-bit digital signal, and sent them to the digital part for OOK demodulation and other processing.
The digital circuit is responsible for mixing the intermediate frequency to zero frequency (Baseband) and performing a series of filtering and decision processing, while AFC and AGC control the analog circuit dynamically, finally the 1-bit original signal is demodulated. After demodulation, the signal will be sent to the decoder to decode and fill in the FIFO, or output to the PAD directly.
In the transmitter system, the digital circuitry will encode the data and then send them to the modulator (or send them to the modulator directly without encoding). The modulator will directly control the PLL and PA, modulate the data by (G) FSK or OOK and transmit them.
The chip provides the SPI communication port. The external MCU can configure the various functions by accessing to the register, control the main state machine, and access to the FIFO.
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CMT2300A
4.1 Transmitter
The transmitter is based on direct frequency synthesis technology. The carrier is generated by a low noise fractional-N frequency synthesizer. The modulated data is transmitted by an efficient single-ended power amplifier (PA). The output power can be read and written via registers, step by step from -20dBm to +20dBm with 1dB.
When the PA is switched fast, the varying input impedance will disturb the output frequency of the VCO instantaneously. The effect is called VCO pulling. It will generate the spurious and spurs on the spectrum around the desired carrier. The PA spurs can be reduced to a minimum instantaneously by the PA output power ramping. CMT2300A has a built-in PA ramping mechanism. When the PA Ramp is turned on, the PA output power can ramp the desired amplitude in a pre-configured rate, so as to reduce the spurs.
In FSK mode, the signal can be filtered by a Gaussian Filter before transmitted, e.g. GFSK, which can reduce the spectral width and interference with neighboring channels.
According to different application requirements, the user can design a PA matching network to optimize the transmitting efficiency.
The typical application schematic and the required BOM is shown in Chapter 3 "Typical application schematic". For more schematic details and layout guidelines, please refer to
“AN141 CMT2300A Schematic and PCB Layout Design Guideline”.
The transmitter can operate in direct mode and package mode. In the direct mode, the data to be transmitted can be sent to the chip by the DIN pin and transmitted directly. In the package mode, the data can be pre-loaded into the TX FIFO in STBY state, and transmitted together with other package elements.
4.2 Receiver
CMT2300A has a built-in ultra-low power, high performance low-IF OOK, FSK receiver. The RF signal induced by the antenna is amplified by a low noise amplifier, and is converted to an intermediate frequency by an orthogonal mixer. The signal is filtered by the image rejection filter, and is amplified by the limiting amplifier and then sent to the digital domain for digital demodulation.
During power on reset (POR) each analog block is calibrated to the internal reference voltage. This allows the chip to remain its best performance at different temperatures and voltages. Baseband filtering and demodulation is done by the digital demodulator.
The AGC loop adjust the system gain by the broadband power detector and attenuation network nearby LNA, so as to obtain the best system linearity, selectivity, sensitivity and other performance.
Leveraging CMOSTEK's low power design technology, the receiver consumes only a very low power when it is turned on. The periodic operation mode and wake up function can further reduce the average power consumption of the system in the application with strict requirements of power consumption.
Similar to the transmitter, the CMT2300A receiver can operate in direct mode and packet mode. In the direct mode, the demodulator output data can be directly output through the DOUT pin of the chip. DOUT can be assigned to GPIO1/2/3. In the packet mode, the demodulator data output is sent to the data packet handler, get decoded and is filled in the FIFO. MCU can read the FIFO by the SPI interface.
4.3 Additional Functions
4.3.1 Power-On Reset (POR)
The Power-On Reset circuit detect the change of the VDD power supply, and generate the reset signal for the entire CMT2300A system. After the POR, the MCU must go through the initialization process and re-configure the CMT2300A. There are two circumstances those will lead to the generation of POR.
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CMT2300A
The first case is a very short and sudden decrease of VDD. The POR triggering condition is, VDD dramatically decreases by 0.9V
+/- 20% (e.g. 0.72V – 1.08V) within less than 2 us. To be noticed, it detects a decreasing amplitude of the VDD, not the absolute value of VDD as shown in the below figure.
< 0.2 us
VDD
0.9 V x (1 +/- 20%)
POR
Figure 5. Sudden Decrease of VDD lead to Generation of POR
The second case is, a slow decrease of the VDD. The POR triggering condition is, VDD decreases to 1.45V +/- 20% (e.g. 1.16V
– 1.74V) within a time more than or equal to 2 us. To be noticed, it detects an absolute value of VDD, not a decreasing amplitude.
> 0.2 us
VDD
1.45 V x (1 +/- 20%)
POR
Figure 6. Slow Decrease of VDD lead to Generation of POR
4.3.2 Crystal Oscillator
The crystal oscillator provides a reference clock for the phase locked loop as well as a system clock for the digital circuits. The value of load capacitance depends on the crystal specified CL parameters. The total load capacitance between XI and XO should be equal to CL, in order to make the crystal accurately oscillate at 26 MHz.
C15 and C16 are the load capacitances at both ends of the crystal. Cpar is the parasitic capacitance on the PCB. Each crystal pin has 5pF internal parasitic capacitance, together is equivalent to 2.5pF. The equivalent series resistance of the crystal must be within the specifications so that the crystal can have a reliable vibration. Also, an external signal source can be connected to the XI pin to replace the conventional crystal. The recommended peak value of this clock signal is from 300mV to 700mV. The clock is coupled to XI pin via a blocking capacitor.
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CMT2300A
4.3.3 Sleep Timer
The CMT2300A integrates a sleep timer driven by 32 kHz low power oscillator (LPOSC). When this function is enabled, the timer wakes the chip from sleep periodically. When the chip operates in a duty cycle mode, the sleep time can be configured from
0.03125 ms to 41922560 ms. Due to the low power oscillator frequency will change with the temperature and voltage drift, it will be automatically calibrated during power on and will be periodically calibrated since then. These calibrations will keep the frequency tolerance of the oscillator within + 1%.
4.3.4 Low Battery Detection
The chip sets up low voltage detection.When the chip is tuned to a certain frequency, the test is performed once.Frequency tuning occurs when the chip jumps from the SLEEP/STBY state to the RFS/TFS/TX/RX state. The result can be read by the
LBD_VALUE register.
4.3.5 Received Signal Strength Indicator(RSSI)
RSSI is used to evaluate the signal strength inside the channel. The cascaded I/Q logarithmic amplifier amplifies the signal before it is sent to the demodulator. The logarithmic amplifier of I channels and Q channel contains the received signal indicator, in which the
DC voltage is generated is proportional to the input signal strength. The output of RSSI is the sum of the values of the two channels’ signals. The output has 80dB dynamic range above the sensitivity. After the RSSI output is sampled by the ADC and filtered by a
SAR FILTER and a RSSI AVG FILTER. The order of the average filter can be set by RSSI_AVG_MODE<2:0>. The code value is translated into dBm value after filtering. Users can read the register RSSI_CODE<7:0> to obtain the RSSI code value, or
RSSI_DBM<7:0> to obtain the dBm value. By setting the register RSSI_DET_SEL<1:0> Users can determine whether the RSSI is output to the MCU in real time, or latched at the instance when the preamble, sync, or the whole packet is received.
Also, CMT2300A allows the user to setup a threshold by RSSI_TRIG_TH<7:0> to compare with the real-time RSSI value. If the
RSSI is larger than the threshold it outputs logic 1, otherwise outputs logic 0. The output can be used as a source of the RSSI VLD interrupt, of the receive time extending condition in the super- low power (SLP) mode
SAR
ADC
SAR
FILTER
RSSI_AVG_MODE<2:0>
RSSI AVG
FILTER
CODE to dBm
CONVERT
RSSI_DET_SEL<1:0>
LATCH
LATCH
RSSI_CODE<7:0>
RSSI_DBM<7:0>
RSSI_DET_SEL<1:0>
COMPARE to
RSSI_TRIG_TH<7:0>
RESULT
Figure 7. RSSI detection and comparison circuit
CMT2300A has done a certain degree of calibration before delivery. In order to obtain more accurate RSSI measurement results, the user needs to recalibrate the RSSI circuit in their dedicated applications. For further information, please refer to the
“AN144-CMT2300AW RSSI Usage Guideline”.
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CMT2300A
4.3.6 Phase Jump Detector
（
PJD
）
PJD is Phase Jump Detector. When the chip is in FSK demodulation, it can automatically observe the phase jump characteristics of the received signal to determine whether it is a wanted signal or an unwanted noise.
2
SYM
2
SYM
1 1 1 1
SYM SYM SYM
SYM
Figure 8. Received signal jump diagram
The PJD mechanism defines that the input signal switching from 0 to 1 or from 1 to 0 is a phase jump. Users can configure the
PJD_WIN_SEL<1:0> to determine the number of detected jumps for the PJD to identify a wanted signal .As shown in the above figure, in total 8 symbols are received. But the phase jump only appeared 6 times. Therefore, the number of jumpsis not equal to the number of symbols. Only when a preamble is received they are equal .In general, the more jumps are used to identify the signal, the more reliable they result is; the less jumps are used, the faster the result is obtained. If the RX time is set to a relatively short period, it is necessary to reduce the number of jumps to meet the timing requirements. Normally, 4 jumps allow pretty reliable result, e.g. the chip will not mistakenly treat an incoming noise as a wanted signal, and vice versa will not treat a wanted signal as noise.
Detecting the phase jump of a signal, is identical to detect whether the signal has the expected data rate. In fact, at the same time, the PJD will also detect the FSK deviation and see if it is legal, as well as to see if the SNR is over 7 dB. With these three parameters the PJD is able to make a very reliable judgment. If the signal is wanted it outputs logic 1, otherwise outputs logic 0. The output can be used as a source of the RSSI VLD interrupt, or the receive time extending condition in the super low power (SLP) mode. In direct data mode, by setting the DOUT_MUTE register bit to 1, the PJD can mute the FSK demodulated data output while there is not wanted signal received.
The PJD technique is similar to the traditional carrier sense technique, but more reliable. While users combine the RSSI detection and PJD technique, they can precisely identify the status of the current channel.
4.3.7 Automatic Frequency Control (AFC)
The AFC mechanism allows the receiver to minimize the frequency error between the TX and RX in a very short time once a wanted signal comes in. This helps the receiver to maintain its highest sensitivity performance. CMT2300A has the most advanced
AFC technology. Compare with the other competitors, within the same bandwidth, CMT2300A can identify larger frequency error, and remove the error in a much shorter time (8-10 symbols).
Normally the frequency error between the TX and RX is caused by the crystal oscillators used in both sides. CMT2300A allows the user to fill in the value of crystal tolerance (in PPM) on RFPDK. Based on the crystal tolerance, the RFPDK will calculate the AFC range while minimizing the receiver bandwidth (to maintain the best performance). Due to the excellent performance of the AFC, it provides a good solution to the crystal aging problem which would lead to more frequency error as time goes by.
Therefore, compare to other similar transceiver chips, CMT2300A can solve more severe crystal aging problem and effectively extend the life time of the product. Please refer to
“AN196-CMT2300A-CMT2219B-CMT2218B The Advantages of the Receiver
AFC.” for more details.
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CMT2300A
4.3.8 Clock Data Recovery (CDR)
The basic task of a CDR system is to recover the clock signal that is synchronized with the symbol rate, while receiving the data. Not only for decoding inside the chip, but also for outputting the synchronized clock to GPIO for users to sample the data. So CDR's task is simple and important. If the recovered clock frequency is in error with the actual symbol rate, it will cause data acquisition errors at the time of reception.
CMT2300A has designed three types of CDR systems, as follows:
1. COUNTING system
–The system is designed for the symbol rates to be more accurate. If the symbol rate is 100% aligned, the unlimited length of 0 can be received continuously without error.
2. TRACING system –The system is designed to correct the symbol rate error. It has the tracking function. It can automatically detect the symbol rate transmitted by TX, and adjust quickly the local symbol rate of RX at the same time, so as to minimize the error between them. The system can withstand up to 15.6% or symbol rate error. Other similar products in the industry cannot reach this level.
3. MANCHESTER system
–This system evolves from the COUNTING system. The basic feature is the same. The only difference is that the system is specially designed for Manchester codec. Special processing can be done when the TX symbol rate has unexpected changes.
4.3.9 Fast Frequency Hopping
The mechanism of fast frequency hopping is, based on the frequency configured on the RFPDFK, for instance 433.92 MHz, during applications the MCU can simply change 1 or 2 registers to quickly switch to another frequency channel. This simplify the way of change the RX or TX frequency in multiple channels application.
In general, the user can configure FH_OFFSET<7:0>during the chip initialization process. And then in the application, the user can switch the channel by changing FH_CHANNEL<7:0>.
When users need to use the fast frequency hopping in the RX mode, in some particular frequency points, one parameter of the
AFC circuit must be re-configured. Please refer to “AN197-CMT2300A-CMT2119B-CMT2219B fast frequency hopping” and
“CMT2300A-CMT2219B frequency hopping calculation tool” for more details.
Rev1.0a | 28/50 www.cmostek.com
CMT2300A
5. Chip Operation
5.1 SPI Interface
The chip communicates with the outside through the 4-wire SPI interface. The CSB is the active-low chip select signal for accessing to the registers. The FCSB is the active-low select signal for accessing to the FIFO. They cannot be set to low at the same time. The
SCLK is the serial clock. Its highest speed is 5MHz.The chip itself and the external MCU send the data at the falling edge of SCLK and capture the data at the rising edge of SCLK. The SDA is a bidirectional pin for input and output data. The address and data are transferred starting from the MSB.
When accessing to the register, CSB is pulled low. A R/W bit is sent first, followed by a 7-bit register address. After the external
MCU pulls down the CSB, it must wait for at least half a SCL cycle, and then send the R/W bit. After the MCU sends out the last falling edge of SCLK, it must wait for at least half a SCLK cycle, and then pull the CSB high.
To be noticed, when reading a register, MCU and CMT2300A will have to switch the direction of their IO (SDIO) between the address bit 0 and the data bit 7. It is required that the MCU switches the IO to input mode before send out the falling edge of the
SCLK; CMT2300A should switch the IO to output mode after it has seen the falling edge of the SCLK. This avoids data contention of the SDIO (both of the MCU and CMT2300A set the SDIO to output mode at the same time), which would cause unexpected electrical problem.
> 0.5 SCLK cycle > 0.5 SCLK cycle
CSB
FCSB
SCLK
SDIO X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X r/w = 1 register address register read data
Figure 9. SPI read register timing
> 0.5 SCLK cycle > 0.5 SCLK cycle
CSB
FCSB
SCLK
SDIO X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X r/w = 0 register address register write data
Figure 10. SPI write register timing
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CMT2300A
5.2 FIFO
CMT2300A provides two separated 32-byte FIFO by default. They are used for RX and TX, respectively. Users can also set
FIFO_MARGE_EN to 1 to merge the two separated FIFO into one 64-byte FIFO. It can be used both under TX and RX. By configuring the FIFO_RX_TX_SEL to indicate whether it is currently used as TX FIFO or RX FIFO. When the two FIFO are not merged, users can fill in the TX FIFO while the RX FIFO is used to receive data in the RX mode.
The FIFO can be accessed via the SPI interface. The user can clear the FIFO by setting FIFO_CLR_TXor FIFO_CLR_RX to 1. Also, the user can re-send the old data in the TX FIFO by setting FIFO_RESTORE to 1, without the need of re-filling the data.
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CMT2300A
5.2.1 FIFO Read Operation
When the MCU accesses to the FIFO, the user must first configure a few registers to setup the FIFO read/write mode, as well as some other working mode. The details are introduced in “AN143-CMT2219B FIFO and Data Packet Usage Guideline”. Here is the read-write timing diagram. Note that there is a slight difference in the control of the FCSB for accessing to the FIFO and the control of the CSB for accessing to the register. When the MCU starts to access to the FIFO, FCSB must be pulled down 1-clock cycle at first, and then send the rising edge of SCL. After the last falling edge of SCL is sent, the MCU must wait at least 2 us to pull up the
FCSB. Between the adjacent read/write operations, the FCSB must be pulled high for 4us at least. When writing the FIFO, the first bit data must be ready 0.5 clock cycles before sending the first rising edge of SCL.
> 1 SCLK cycle > 2 us > 4 us > 1 SCLK cycle > 2 us
CSB
FCSB
SCLK
SDIO 7 6 5 4 3 2 1 0
FIFO read data
X 7 6 5 4 3 2 1 0 X
FIFO read data
Figure 11. SPI read FIFO timing
> 1 SCLK cycle > 2 us > 4 us > 1 SCLK cycle > 2 us
CSB
FCSB
SCLK
SDIO 7 6 5 4 3 2 1 0
FIFO write data
X 7 6 5 4 3 2 1 0 X
FIFO write data
Figure 12. SPI write FIFO timing
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CMT2300A
5.2.2 FIFO Associated Interrupt
CMT2300A provides rich interrupt sources associated with the FIFO. The interrupt timing for Tx and Rx FIFO is shown below:
Noise RX DATA Noise Sync 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SYNC_OK
RX_FIFO_WBYTE
RX_FIFO_NMTY
RX_FIFO_TH
RX_FIFO_FULL
RX_FIFO_OVF
(FIFO_TH = 16)
RX FIFO ARRAY EMPTY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FULL
Figure 13. CMT2300ARX FIFO interrupt timing diagram
TX DATA Prefix Pream Sync 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0
TX_FIFO_NMTY
TX_FIFO_TH
TX_FIFO_FULL
(FIFO_TH = 16)
FIFO ARRAY EMPTY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FULL
Figure 14. CMT2300A TX FIFO interrupt timing diagram
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CMT2300A
5.3 Operation State, Timing and Power Consumption
5.3.1 Startup Timing
After the chip VDD is powered up, the chip usually needs to wait about 1ms, then POR will release. After the release of the POR, the crystal will start, the start time is N ms, depending on the characteristics of the crystal itself. After starting, the user need to wait for the crystal settled, then the system starts working. The default setting is 2.48 ms. This time can be modified by writing
XTAL_STB_TIME <2:0> afterword (it has to be longer than the crystal inherent settling time). The chip stays in IDLE state until the crystal is settled. After the crystal is settled, the chip perform calibration of each module and stay in SLEEP state after then to wait for initialization configuration by user. The chip will back to IDLE state and redo startup steps upon reset at anytime.
VDD
POR
POR Release
<= 1 ms
XTAL Start up
<= N ms
XTAL Stablize
<= 2.48 ms
Block Calibrations
<= 6.5 ms
Enters the SLEEP State Ready for customer initializing
Figure 15. Power-on Timing
The chip enters SLEEP state after calibration. From then on, the MCU can control the chip to switch to different operation states through setting the register CHIP_MODE_SWT<7:0>.
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CMT2300A
5.3.2 Operation State
CMT2300A has 7 operation states: IDLE, SLEEP, STBY, RFS, RX, TFS and TX, as shown below.
Table 16. CMT2300A state and corresponding active module
State Binary code Switch command Active Modules Optional Moduels
IDLE
SLEEP
0000
0001 soft_rst go_sleep
SPI, POR
SPI, POR, FIFO
None
LFOSC, Sleep Timer
STBY
RFS
TFS
RX
TX
0010
0011
0100
0101
0110 go_stby go_rfs go_tfs go_rx go_tx
SPI, POR, XTAL, FIFO
SPI, POR, XTAL, PLL, FIFO
CLKO
CLKO
SPI, POR, XTAL, PLL, FIFO CLKO
SPI, POR, XTAL, PLL, LNA+MIXER+IF, FIFO CLKO, RX Timer
SPI, POR, XTAL, PLL, PA, FIFO CLKO
IDLE
0000 go_sleep go_tx
Power up
SLEEP
0001 go_sleep go_rx go_stby go_sleep go_tx go_stby go
_t fs go
_s tb y
STBY
0010 go
_s go
_rf s tb y
TFS
0100 go_rx go_stby
RFS
0011 go_tfs go_sleep go_rfs go_sleep go_tfs go_tx go_rfs go_rx
TX
0110 go_switch
RX
0101 go_switch
Figure 16. State Switch Diagram
SLEEP State
The chip power consumption is the lowest in SLEEP state, and almost all the modules are turned off. SPI is open, the registers of the configuration bank and control bank 1 will be saved, and the contents filled in the FIFO before will remain unchanged.
However, the user cannot operate the FIFO and cannot change the contents of the register. If the user opens the wake-up function, the LFOSC and the sleep counter will turn on and start working. The time required to switch from IDLE to SLEEP is the power up time. Switch from other state to SLEEP will be completed immediately. www.cmostek.com
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CMT2300A
STBY State
In STBY state, the crystal is turned on, the LDO of the digital circuit will also be turned on, the current will be slightly increased, and the FIFO can be operated. The user can choose whether to output CLKO (system clock) to PIN. Because the crystal and LDO is turned on, compared to the SLEEP, the time switching from the STBY to transmitting or receiving will be relatively short. Switching from SLEEP to STBY will be completed after the crystal is turned on and settled. Switching from other state to STBY will be completed immediately.
RFS State
RFS is a transition state before switching to RX. Except that the receiver RF module is off, the other modules are turned on, and the current will be larger than STBY. Because PLL has been locked in the RX frequency, RFS cannot switch to TX. Switching from
STBY to RFS probably requires PLL calibration and stability time of 350us. Switching from SLEEP to RFS needs to add the crystal start-up and stability time. Switching from other state to RFS will be completed immediately.
TFS State
TFS is a transition state before switching to TX. Except that the transmitter RF module is off, the other modules are turned on, and the current will be larger than STBY. Because PLL has been locked in the TX frequency, TFS cannot switch to RX. Switching from
STBY to TFS probably requires PLL calibration and stability time of 350us. Switching from SLEEP to TFS needs to add the crystal start-up and settled time. Switching from other state to TFS will be completed immediately.
RX State
All modules on the receiver will be opened in RX state. Switching from RFS to RX requires only 20us. Switching from STBY to RX needs to add the PLL calibration and settled time of 350us. Switching from SLEEP to RX needs to add the crystal start-up and settled time. TX can be quickly switched to RX by sending go_switch command. Whether the TX and RX setting frequency is the same, the user need to wait for the PLL re-calibration and settled time of 350us to switch successfully.
TX State
All modules on the transmitter will be opened in TX state. Switching from TFS to TX requires only 20us. Switching from STBY to TX needs to add the PLL calibration and settled time of 350us. Switching from SLEEP to TX needs to add the crystal start-up and settled time. RX can be quickly switched to TX by sending go_switch command. Whether the RX and TX setting frequency is the same, the user need to wait for the PLL re-calibration and settled time of 350us to switch successfully.
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CMT2300A
5.4 GPIO and Interrupt
CMT2300A has 3 GPIO ports. Each GPIO can be configured as a different input or output. CMT2300A has 2 interrupt ports. They can be configured to different GPIO outputs.
Table 17. CMT2300A GPIO
Pin No.
Name I/O Function
16
15
GPIO1
GPIO2
IO
IO
Configured as: DOUT/DIN, INT1, INT2, DCLK (TX/RX), RF_SWT
Configured as: INT1, INT2, DOUT/DIN, DCLK (TX/RX), RF_SWT
8 GPIO3 IO Configured as: CLKO, DOUT/DIN, INT2, DCLK (TX/RX)
Interrupt mapping table is as below. INT1 and INT2 mapping is the same. Take INT1 as an example.
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CMT2300A
Table 18. CMT2300A interrupt mapping table
Name INT1_SEL Descriptions Clearing methods
Auto RX_ACTIVE
TX_ACTIVE
RSSI_VLD
PREAM_OK
SYNC_OK
NODE_OK
CRC_OK
PKT_OK
SL_TMO
RX_TMO
TX_DONE
RX_FIFO_NMTY
RX_FIFO_TH
RX_FIFO_FULL
RX_FIFO_WBYTE
RX_FIFO_OVF
TX_FIFO_NMTY
TX_FIFO_TH
TX_FIFO_FULL
STATE_IS_STBY
STATE_IS_FS
STATE_IS_RX
STATE_IS_TX
00000
00001
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
Indicates the chip is entering RX and is already in RX. It is 1 in PLL
Tuning and RX state, and it is 0 in the other states.
Indicates the chip is entering TX and is already in TX. It is 1 in PLL tuning and TX state, and it is 0 in the other states.
Indicates whether the RSSI is active.
Indicates that the Preamble is received successfully.
Indicates that the Sync Word is received successfully.
Indicates that the Node ID is received successfully.
Indicates that the CRC for the current packet is correct.
Indicates that a packet has been received.
Indicates that the SLEEP counter timed out.
Indicates that the RX counter timed out.
Indicates that the TX operation is completed.
Indicates that the RX FIFO is not empty.
Indicates the number of unread bytes of the RX FIFO is over FIFO TH
Indicates RX FIFO is full.
Indicates each time a byte is written to the RX FIFO. Itis a pulse. indicates RX FIFO is overflow
Indicates that TX FIFO is not empty
Indicates the number of unread bytes of the TX FIFO is over FIFO TH.
Indicates TX FIFO is full.
Indicates that the current state is STBY.
Indicates that the current state is RFS or TFS.
Indicates that the current state is RX.
Indicates that the current state is TX.
Auto
LBD
TRX_ACTIVE
PKT_DONE
10111
11000
11001
Indicates that low battery is detected (VDD is lower than TH)
Indicates the chip is entering TX or RX and is already in TX or RX. It is 1 in
PLL tuning, TX or RX state, and it is 0 in the other states.
Indicates that the current packet has been received, covering 4 possible different situations.
1. The packet is received completely and correctly.
2. Manchester decoding has error. Decoder is automatically reset.
3. NODE ID receiving has error. Decoder is automatically reset.
Auto
Auto by MCU
4. Signal collision occurred. Decoder is not reset, waiting for MCU to response.
By default, Interrupt is active high (logic 1 is valid). Users can set the INT_POLAR register bit to 1 to make all interrupts active low
(logic 0 is valid).Taking INT1 as an example, the control and sources selection of all the available interrupts is shown below. The control and mapping of INT1 and INT2 are the same.
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto by MCU by MCU by MCU by MCU by MCU by MCU by MCU by MCU
Auto
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CMT2300A
RX_ACTIVE
RSSI_VLD_FLG
Sycn Word OK
Interrupt Source
0
PREAM_OK_CLR
Preamble OK
Interrupt Source
0
0
1
SYNC_OK_CLR
D Q
PREAM_OK_FLG
SYNC_OK_EN
0
1
D Q
PREAM_OK_EN
SYNC_OK_FLG
NODE_OK_CLR NODE_OK_EN
Node ID OK
Interrupt Source
0
0
1
D Q
NODE_OK_FLG
CRC_OK_CLR CRC_OK_EN
CRC OK
Interrupt Source
0
0
1
D Q
CRC_OK_FLG
PKT_DONE_CLR PKT_DONE_EN
Packet OK
Interrupt Source
0
0
1
D Q
PKT_OK_FLG
SL_TMO_CLR SL_TMO_EN
Sleep Timeout
Interrupt Source
0
0
1
D Q
SL_TMO_FLG
RX_TMO_CLR RX_TMO_EN
Receive Timeout
Interrupt Source
0
0
1
D Q
RX_TMO_FLG
TX_DONE_CLR TX_DONE_EN
Transmit Done
Interrupt Source
0
0
1
D Q
RX_DONE_FLG
LBD
Interrupt Source
0
RX_FIFO_NMTY_FLG
RX_FIFO_TH_FLG
RX_FIFO_FULL_FLG
RX_FIFO_WBYTE_FLG
RX_FIFO_OVF_FLG
TX_FIFO_NMTY_FLG
TX_FIFO_TH_FLG
LBD_CLR
TX_FIFO_FULL_FLG
STATE_IS_STBY
STATE_IS_FS
STATE_IS_RX
STATE_IS_TX
0
1
D Q
LBD_FLG
RX_ACTIVE
TX_ACTIVE
TRX_ACTIVE
Packet OK
Interrupt Source
Packet Err
Interrupt Source
Collision Err
Interrupt Source
0
PKT_DONE_CLR
0
1
D Q
PKT_DONE_EN
PKT_DONE_FLG
INT1_CTL <4:0>
Figure 17. CMT2300A INT1 interrupt mapping diagram
0
0
01101
01110
01111
10000
10001
10010
00111
01000
01001
01010
01011
01100
00000
00001
00010
00011
00100
00101
00110
10011
10100
10101
10110
10111
11000
11001
其它
INT_POLAR
0
1
INT1
GPO3_SEL <1:0>
GPO2_SEL <1:0>
GPO1_SEL <1:0>
GPIO3
GPIO2
GPIO1
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CMT2300A
6. Packet Handler
CMT2300A supports direct mode and packet mode:
Direct Mode
– In Rx mode, only supports preamble and sync detection, FIFO does not work, demodulated data sent out from GPIO. In Tx mode, only supports transmitting the data input from GPIO.
Packet Mode
– Supports all packet formats, demodulated data is stored in FIFO, accessed by SPI.
6.1 Direct Mode
EEPROM (CMT Parameters)
RF
MODEM clock
1 data
1
Preamble (Opt)
Sync (Opt) clock
1 data
1
SPI
DCLK
CSB
SCLK
SDIO
User Registers
INT1/INT2
DOUT/DIN
Figure 5. Direct mode data path
Rx processing
In direct mode, the data from the demodulator is sent directly to the external MCU via the DOUT pin. DOUT can be set to GPIO1,
2 or 3. The typicalRX direct mode control sequence for the MCU is:
1. Configures GPIOsusing theCUS_IO_SEL register.
2. Configures DATA_MODE = 0.
3. Send the go_rx command.
4. Capture the data from DOUT continuously.
5. Send the go_sleep/go_stby/go_rfs command to stop receiving and save the power.
Tx processing
In the direct mode, the data to be transmitted is sent directly to the chip from the external MCU by via DIN pin. The data rate is determined by the MCU but must be less than +/- 30% of the data rate configured on the RFPDK. The typical TX direct mode control sequence for the MCU is:
1. Set register TX_DIN_EN to 1 to enable DIN on GPIO.
2. Set TX_DIN_SEL to 0 to configure GPIO1 as DIN, or 1 to configure GPIO2 as DIN.
3. Send the go_tx command,send in the data to the DIN pinwith the desired data rate, the data is transmitted immediately.
4. Send the go_sleep/go_stby/go_rfs command to stop transmission and save the power.
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CMT2300A
6.2 Packet Mode
EEPROM (CMT Parameters)
RF
MODEM clock
1 data
1
Packet
Handler data
8
FIFO SPI
FCSB
CSB
SCLK
SDIO
User Registers
INT1
INT2
Figure 6. Packet mode data path
The packet handler supports the classic and more flexible packet format in both TX and RX mode. It includes variable packet format
(Length in front of the Node ID), variable packet format (Length in the back of the Node ID) and fixed packet format. Each element in the packet supports flexible configurations, as shown below.
Manchester Manchester/Whiten/FEC(7,4)
Preamble
1
Sync Word
2
Node ID
3
Length
4
Data
5
CRC
6
Data-Only CRC
Payload/CRC
Figure 20. Variable length packet (Length in front of Node ID)
Manchester Manchester/Whiten/FEC(7,4)
Preamble
1
Sync Word
2
Node ID
3
Length
4
Data
5
CRC
6
Data-Only CRC
Payload/CRC
Figure 21. Variable length packet (Length behind Node ID)
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CMT2300A
Preamble
1
Manchester
Sync Word
2
Node ID
3
Manchester/Whiten/FEC(7,4)
Data
4
CRC
5
Data-Only CRC
Payload/CRC
Figure 22. Fixed length packet
Rx processing
In the packet mode, the output data from the demodulator will be transferred to the packet handler for decoding, and then filled in the
FIFO. The packet handler provides a variety of decoding mechanisms and options to determine the validity of the data. These can reduce the work load of the MCU. The typical package mode control sequence for the MCU is:
1. Configures GPIO using the CUS_IO_SEL register.
2. Setup the interrupts usingCUS_INT1_CTL, CUS_INT2_CTL and CUS_INT_EN registers.
3. Send the go_rx command.
4. Reads the RX FIFO according to the relevant interrupts.
5. Sends the go_sleep/go_stby/go_rfs command to stop the receiving and save the power.
6. Clears the packet interrupts using CUS_ INT_CLR1 and CUS_INT_CLR2 registers.
Tx processing
In the packet mode, MCU can fill the data in the FIFO in advance in the STBY and TFS state, or fill them in the FIFO while the chip sends the data, or use the combination of the above two methods. The typical Txpacket mode control sequence for the MCU is:
1. Configures GPIO usingthe CUS_IO_SEL register
2. Sends go_stby/go_tfs command when the data is filled in FIFO in advance.
3. Sends go_tx command.
4. Writes the data into FIFO according to the relevant interrupt status.
5. Sends go_sleep/go_stby/go_rfs command to save power.
CMT2300A has rich configurable hardware resources of FIFO, packet and their interrupts, which makes it compatible with most of the similar RF products in the market. For more details please refer to the interface of RFPDK and “AN143-CMT2300A FIFO and
Data Packet Usage Guideline”.
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CMT2300A
7. Low Power Operation
7.1 Duty Cycle Operation Mode
CMT2300A makes the Tx and Rx work in duty cycle operation mode to save the power consumption. Among them, the Rx Duty
Cycle can be classified into the following 5 modes.
Fully manual control.
1. Automatic SLEEP wakeup, switch to manual control.
2. Automatic SLEEP wakeup, automatically enter to RX, manually exit RX.
3. Automatic SLEEP wakeup, manually enter RX, automatically exit RX.
4. Fully automatic receive and sleep control.
The Tx Duty Cycle can be divided into the following 3 modes.
1. Manually enter TX, automatically exit TX
2. Automatic SLEEP wakeup, manually enter TX, automatically exit TX
3. Fully automatic transmit and sleep control
7.2 Super-low Power Rx Mode
The CMT2300A provides a series of options helping users achieving super-low power (SLP) Rx upon different application requirements. All these options are available only when RX_TIMER_EN is set as 1, namely Rx counter is active. The core function of SLP Rx is to reduce Rx time to the best during no-signal period meanwhile properly extend Rx time during signal existing time, then to reach stable Rx with minimum power consumption.
In general, traditional short-range wireless transceiver systems apply the solution as shown in the below figure to fulfill low-power transceiver. Based on the solution, the CMT2300A extends 13 solutions with better power consumption performance. Among them, a fundamental solution by setting RX_EXTEND_MODE<3:0> to 0 is shown in the below figure.
发射数据：
Tx Data:
One Packet
Length of Packet x 2 +
Packet Gap < RX Time TX Burst Time > RX Cycle
IDLE IDLE t
TX starts transmittion
接收时间：
Rx Time:
Received
TX starts transmittion
Missed Received
SLEEP SLEEP
Receiving Sleeping XTAL stabilizing and Frequency Tuning
SLEEP
XTAL,
TUNE
RX Sleep
RX Cycle < TX Burst Time
SLEEP t
Figure 23. Basic low-power receiver scheme
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CMT2300A
The traditional low-power transceiver solution and the 13 extended low-power solutions based on it are listed in the below table.
Table 19. Low-power Rx mode
No.
Rx Extended Methods Rx Extended Condition
0
1
2
3
No Rx extension is supported. Exit Rx state as soon as
T1 timed out. None
RSSI_VLD is valid.
PREAM_OK is valid.
Once meet the Rx extended condition during T1, leave
T1 and pass the control authority to MCU.
RSSI_VLD and PREAM_OK are valid simultaneously.
4
5
6
7
8
9
10
11
12
13
Once detect RSSI_VLD = 1 during T1, leave T1 and stays in Rx state, exit Rx state until RSSI_VLD = 0.
Once meet the Rx extended condition during T1, switch to T2. Exit Rx as soon as T2 timed out.
RSSI_VLD is valid.
RSSI_VLD is valid
PREAM_OK is valid
RSSI_VLDandPREAM_OK are valid simultaneously.
Any one of PREAM_OK or SYNC_OK is valid.
Any one of PREAM_OK or NODE_OK is valid.
Any one of PREAM_OK or SYNC_OK or NODE_OK is valid.
RSSI_VLD is valid.
PREAM_OK is valid.
Once meet the Rx extended condition during T1, switch to T2. Leave T2 and pass the control authority to MCU as soon as SYNC is detected, otherwise exit Rx when
T2 timed out. RSSI_VLD and PREAM_OK are valid simultaneously.
The T1 and T2 mentioned in the table refer to the RX T1 and the RX T2 time interval that can be set via the registers or RFPDK.
The source of RSSI_VLD can be the comparison result of the RSSI or the detection result of the phase jump detector (PJD). For more details, please refer to “AN146-CMT2300AW Low Power Mode Usage Guideline”.
7.3 Receiver “Power VS Performance” Configuration
CMT2300A provides a set of registers to select the power consumption and sensitivity performance of the RF frontend circuit. The below table shows how they are configured:
Table 20. Low-power receiver mode
Current level RF Performance LMT_VTR<1:0> MIXER_BIAS<1:0> LNA_MODE<1:0> LNA_BIAS<1:0>
Low
Medium
High
Low
Medium
High
2
2
1
2
2
2
1
1
3
1
2
2
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CMT2300A
8. User Register
CMT2300A is configured by writing in the registers. The register details are listed in the below table.
Bit 7 Bit 6
Table 21. CMT2300A Register Table
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Addr
R/W
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Addr
R/W
0x61
0x62
RW
RW
0x63
0x64
0x65
RW
RW
RW
0x66
0x67
0x68
RW
RW
RW
0x69
0x6A
RW
RW
W Addr
R/W
0x6C
0x6D
W
W
0x6E
0x6F
0x70
0x71
R
R
R
R
R
Addr R/W
0x38
0x39
0x3A
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
Addr
R/W
0x56
0x57
0x58
0x59
RW
RW
RW
RW
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
RW
RW
RW
RW
RW
RW
RW
Name
CUS_TX1
CUS_TX2
CUS_TX3
CUS_TX4
CUS_TX5
CUS_TX6
CUS_TX7
CUS_TX8
CUS_TX9
CUS_TX10
CUS_LBD
Name
CUS_MODE_CTL
CUS_MODE_STA
CUS_EN_CTL
CUS_FREQ_CHNL
CUS_FREQ_OFS
CUS_IO_SEL
CUS_INT1_CTL
CUS_INT2_CTL
CUS_INT_EN
CUS_FIFO_CTL
CUS_INT_CLR1
Name
CUS_INT_CLR2
CUS_FIFO_CLR
CUS_INT_FLAG
CUS_FIFO_FLAG
CUS_RSSI_CODE
CUS_RSSI_DBM
CUS_LBD_RESULT
Name
CUS_PKT1
CUS_PKT2
CUS_PKT3
CUS_PKT4
CUS_PKT5
CUS_PKT6
CUS_PKT7
CUS_PKT8
CUS_PKT9
CUS_PKT10
CUS_PKT11
CUS_PKT12
CUS_PKT13
CUS_PKT14
CUS_PKT15
CUS_PKT16
CUS_PKT17
CUS_PKT18
CUS_PKT19
CUS_PKT20
CUS_PKT21
CUS_PKT22
CUS_PKT23
CUS_PKT24
CUS_PKT25
CUS_PKT26
CUS_PKT27
CUS_PKT28
CUS_PKT29
CUS_SYS1
CUS_SYS2
CUS_SYS3
CUS_SYS4
CUS_SYS5
CUS_SYS6
CUS_SYS7
CUS_SYS8
CUS_SYS9
CUS_SYS10
CUS_SYS11
CUS_SYS12
Name
CUS_RF1
CUS_RF2
CUS_RF3
CUS_RF4
CUS_RF5
CUS_RF6
CUS_RF7
CUS_RF8
Name
CUS_RF9
CUS_RF10
CUS_RF11
CUS_RF12
CUS_FSK1
CUS_FSK2
CUS_FSK3
CUS_FSK4
CUS_FSK5
CUS_FSK6
CUS_FSK7
CUS_CDR1
CUS_CDR2
CUS_CDR3
CUS_CDR4
CUS_AGC1
CUS_AGC2
CUS_AGC3
CUS_AGC4
CUS_OOK1
CUS_OOK2
CUS_OOK3
CUS_OOK4
CUS_OOK5
Name
CUS_CMT1
CUS_CMT2
CUS_CMT3
CUS_CMT4
CUS_CMT5
CUS_CMT6
CUS_CMT7
CUS_CMT8
CUS_CMT9
CUS_CMT10
CUS_CMT11
CUS_RSSI
Name Addr
R/W
0x0D
0x0E
0x0F
0x10
RW
RW
RW
RW
RW
0x11
0x12
0x13
0x14
0x15
0x16
0x17
RW
RW
RW
RW
RW
RW
RW
Addr
R/W
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
RW
RW
RW
RW
RW
RW
RW
0x1F RW
Addr
0x20
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
User does not need to understand the details, just directly export the register contents from the RFPDK
Bit 7
LMT_VTR [1:0]
LFOSC_RECAL_EN
SLEEP_BYPASS_EN
Bit 6
LFOSC_CAL1_EN
COL_DET_EN
PJD_TH_SEL
PJD_WIN_SEL [1:0]
COL_OFS_SEL
Bit 7 Bit 6
Bit 5 Bit 4
MIXER_BIAS [1:0]
LFOSC_CAL2_EN
XTAL_STB_TIME [2:0]
RX_TIMER_EN
SLEEP_TIMER_M
[7:0]
SLEEP_TIMER_M
[10:8]
RX_TIMER_T1_M
[10:8]
RX_TIMER_T1_M
[7:0]
RX_TIMER_T2_M
[7:0]
Bit 3 Bit 2
LNA_MODE [1:0]
SLEEP_TIMER_EN
TX_EXIT_STATE [1:0]
TX_DC_EN
RX_TIMER_T2_M
[10:8]
DOUT_MUTE
RSSI_DET_SEL [1:0]
SLEEP_TIMER_R [3:0]
RX_TIMER_T1_R [3:0]
Bit 1
RX_DC_EN
RX_TIMER_T2_R [3:0]
RX_EXTEND_MODE [3:0]
RSSI_AVG_MODE
[2:0]
LNA_BIAS [1:0]
RX_EXIT_STATE [1:0]
CLKOUT_EN
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Bit 0
DC_PAUSE
User does not need to understand the details, just directly export the register contents from the RFPDK
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
User does not need to understand the details, just directly export the register contents from the RFPDK
Bit 7
RESV
RESV
RESV
FEC_TYPE
CRC_BIT_ORDER
RESV
FIFO_AUTO_RES_EN
Bit 7
Bit 7
RESV
RESV
RESV
RF_SWT1_EN
RESV
SL_TMO_EN
TX_DIN_EN
RESV
Bit 7
RESV
RESV
LBD_FLG
RESV
Bit 6
RESV
FEC_EN
WHITEN_SEED [8]
RESV
Bit 6
Bit 5
RX_PREAM_SIZE [4:0]
SYNC_TOL [2:0]
PAYLOAD_LENG
[10:8]
NODE_FREE_EN
CRC_BYTE_SWAP
WHITEN_SEED_TYPE
RESV
Bit 5
Bit 4
TX_PREAM_SIZE [7:0]
TX_PREAM_SIZE
[15:8]
PREAM_VALUE [7:0]
SYNC_VALUE [7:0]
SYNC_VALUE [15:8]
SYNC_VALUE [23:16]
SYNC_VALUE [31:24]
SYNC_VALUE [39:32]
SYNC_VALUE [47:40]
Bit 3 Bit 2
PREAM_LENG_UNIT
SYNC_SIZE [2:0]
Bit 1
DATA_MODE [1:0]
Bit 0
SYNC_MAN_EN
SYNC_VALUE [63:56]
AUTO_ACK_EN
PAYLOAD_LENG [7:0]
NODE_ERR_MASK
NODE_VALUE [7:0]
NODE_VALUE [15:8]
NODE_VALUE [23:16]
NODE_VALUE [31:24]
NODE_LENG_POS_SEL
NODE_SIZE [1:0]
CRC_BIT_INV
CRC_SEED [7:0]
CRC_SEED [15:8]
WHITEN_TYPE [1:0]
WHITEN_SEED [7:0]
CRC_RANGE
RESV RESV
TX_PKT_NUM [7:0]
TX_PKT_GAP [7:0]
FIFO_TH [6:0]
WHITEN_EN
RESV
PAYLOAD_BIT_ORDER
CRC_TYPE [1:0]
NODE_DET_MODE
[1:0]
MANCH_TYPE
TX_PREFIX_TYPE
[1:0]
Bit 4 Bit 3 Bit 2 Bit 1
PKT_TYPE
CRC_EN
MANCH_EN
Bit 0
User does not need to understand the details, just directly export the register contents from the RFPDK
Bit 0
Bit 0
Bit 6 Bit 5 Bit 4 Bit 3
CHIP_MODE_SWT [7:0]
Bit 2 Bit 1 Bit 0
RESV
RESV
RSTN_IN_EN
LOCKING_EN
CFG_RETAIN
RESV RESV RESV
CHIP_MODE_STA [3:0]
RESV
RF_SWT2_EN
LFOSC_OUT_EN
RX_TMO_EN
RESV
INT_POLAR
TX_DIN_INV
TX_DONE_EN
TX_DIN_SEL [1:0]
SL_TMO_FLG
GPIO3_SEL [1:0]
PREAM_OK_EN
FIFO_AUTO_CLR_DIS
RX_TMO_FLG
FH_CHANNEL [7:0]
FH_OFFSET [7:0]
SYNC_OK_EN
FIFO_TX_RD_EN
TX_DONE_FLG
GPIO2_SEL [1:0]
INT1_SEL [4:0]
INT2_SEL [4:0]
NODE_OK_EN
FIFO_RX_TX_SEL
TX_DONE_CLR
RESV
CRC_OK_EN
FIFO_MERGE_EN
SL_TMO_CLR
GPIO1_SEL [1:0]
RESV
PKT_DONE_EN
SPI_FIFO_RD_WR_SEL
RX_TMO_CLR
Bit 6
RESV
RESV
COL_ERR_FLG
RX_FIFO_FULL_FLG
Bit 5
LBD_CLR
RESV
PKT_ERR_FLG
RX_FIFO_NMTY_FLG
Bit 4 Bit 3
PREAM_OK_CLR
RESV
PREAM_OK_FLG
RX_FIFO_TH_FLG
RSSI_CODE [7:0]
RSSI_DBM [7:0]
LBD_RESULT [7:0]
SYNC_OK_CLR
RESV
SYNC_OK_FLG
RX_FIFO_OVF_FLG
Bit 2
NODE_OK_CLR
FIFO_RESTORE
NODE_OK_FLG
TX_FIFO_FULL_FLG
Bit 1
CRC_OK_CLR
FIFO_CLR_RX
CRC_OK_FLG
TX_FIFO_NMTY_FLG
Bit 0
PKT_DONE_CLR
FIFO_CLR_TX
PKT_OK_FLG
TX_FIFO_TH_FLG
Rev1.0 | 44/ 50
Function
CMT Bank
Function
System Bank
Function
Frequency Bank
Function
Data Rate Bank
Function
Baseband Bank
Function
TX Bank
Function
Control Bank 1
Function
Control Bank 2 www.cmostek.com
CMT2300A
From the above table, it can be seen that the address range is from 0x00 to 0x71, which can be divided into 3 main banks for better understanding. They are: Configuration bank (including 6 sub-banks), Control Bank1, and Control Bank 2. For the 3 banks the address is continuous. They are all accessed via the SPI bus. They have different functionalities and design purposes, which are shown in the below table:
Table 22. Description of Register Banks
Bank Name in the
Address Bank Name Functionality
RFPDKExport File
0x00-0x0B
0x0C-0x17
0x18-0x1F
0x20-0x37
Configuration Bank
(RFPDK export the register values ）
CMT Bank
System Bank
Frequency Bank
Data Rate Bank
0x38-0x54 Baseband Bank
CMT Bank
System Bank
Frequency Bank
Data Rate Bank
Baseband Bank
Users do not change them.
Mainly relates to low power mode.
To setup the TX and RX frequencies.
To setup data rate, deviation, bandwidths and other related parameters.
To setup packet format and some FIFO features.
0x55-0x5F
0x60-0x6A
0x6B-0x71
TX Bank
Control Bank 1 （ Set by MCU in application, not generated by RFPDK ）
Control Bank 1(Set by MCU in application, not generated by RFPDK ）
TX Bank
--
--
To setup TX deviation and power.
To setup chip working state, frequency hopping, GPIOs and interrupts control.
To read interrupt flags and RSSI value, control the FIFO.
To simplify the operation, users should firstly setup all the desired parameters on the RFPDK, export the register contents to the HEX file, and use it to initialize the CMT2300A. For the CMT Bank, Frequency Bank, Data Rate Bank, and the TX Bank, users do not need to study the details of the registers. Instead, these register configurations totally rely on the RFPDK. For System Bank and Baseband
Bank, users must study the details in order to play with them in different applications. Meanwhile, for Control Bank 1 and 2, users must also understand the meaning of each register.
CMOSTEK provides a series Application Notes (AN) for the users to study how to play with the chip, how to configure the parameters on RFPDK, how to use each register, and other notable application skills. Users can start their learning from reading “AN142
CMT2300A
W Quick Start Guide”, which provides step-by-step guidance and leads the users to read other documents.
Rev1.0a | 45/50 www.cmostek.com
CMT2300A
9. Ordering Information
Table 23. CMT2300A ordering information
Part Number Descriptions Packaging Packing Condition
CMT2300A, Ultra Low Power
CMT2300A-EQR [1] QFN16 (3x3) Tape& Reel
Sub-1GHz RF Transceiver
Notes:
[1].
“E” represents extended industrial grade. The temperature range is from -40 to +85.
“Q” represents QFN16 packaging.
“R” represents tape &reel packing. MOQ is 3000pcs.
For more information about product, please visit www.cmostek.com
.
For purchasing or price requirements, please contact [email protected] or local sales representative
1.8 to 3.6V,
-40 to 85 ℃
MOQ
3,000
Rev1.0a | 46/50 www.cmostek.com
10. Packaging Information
CMT2300A packaging is QFN16 (3x3). The packaging information is as below.
D e
16
1
Top View b
D2
1
Bottom View
16
CMT2300A
Symbol
D
D2 e
E
A
A1 b c
E2
L
Side View
Figure 24. 16-Pin QFN 3x3 packaging
Table 24. 16-Pin QFN 3x3 packaging
Size (mm)
Min.
0.7
—
0.18
0.18
2.90
1.55
0.50 BSC
2.90
1.55
0.35
Max.
0.8
0.05
0.30
0.25
3.10
1.75
3.10
1.75
0.45
Rev1.0a | 47/50 www.cmostek.com
CMT2300A
11. Top Marking
Marking method
Pin 1 mark
Font size
Line 1 marking
Line 2 marking
Line 3 marking
3 0 0 A
① ② ③ ④
Y WW
Figure 25. CMT2300A top marking
Table 25. CMT2300A top marking description
Laser
Circle diameter = 0.3 mm
0.5 mm,
right aligned.
300A represents model CMT2300A
①②③④ represents th e internal tracking coding
Date code is assigned by assembly factory. Y represents the last digit of the year. WW represents working week.
Rev1.0a | 48/50 www.cmostek.com
CMT2300A
12. Revise History
Version No.
Preliminary
Preliminary 0.2
0.6
0.7
0.8
Chapter
All
5.14.1
5.14.2
All
All
All
0.9
1.0
1.0a
All
All
All
Table 1. Revise History Records
Description
Preliminary version for internal verification
Update 1 st paragraph
Update Table 34
Split Chapter 5 and 6 from Chapter 4
Initial release for production version
Changed T&R to 3,000 pcs Added AN document list
Added new RF parameters and curves
Added and changed some performance numbers Changed RSSI descriptions
Added POR descriptions
Added PJD, AFC and CDR descriptions
Added receiver
“Power VS Performance” descriptions
Changed some characters and figures Detected the AN document list
Changed some descriptions
Reformat on English version
Date
2015-06-09
2015-06-10
2015-08-06
2017-03-22
2017-08-10
2018-01-03
2018-01-15
2020-03-03
Rev1.0a | 49/50 www.cmostek.com
CMT2300A
13. Contacts
CMOSTEK Microelectronics Co., Ltd. Shenzhen Branch
Address: 2/F Building 3, Pingshan Private Enterprise S.T. Park, Xili, Nanshan District, Shenzhen, Guangdong, China
Tel:
Website:
+86-755-83231427
Post Code: 518071
Sales: [email protected]
Supports: [email protected]
www.cmostek.com
Copyright. CMOSTEK Microelectronics Co., Ltd. All rights are reserved.
The information furnished by CMOSTEK is believed to be accurate and reliable. However, no responsibility is assumed for inaccuracies and specifications within this document are subject to change without notice. The material contained herein is the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support devices or systems without express written approval of CMOSTEK. The CMOSTEK logo is a registered trademark of
CMOSTEK Microelectronics Co., Ltd. All other names are the property of their respective owners. www.cmostek.com
Rev1.0a | 50/50
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