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MNL-EPXA1DEVBD-1.
1
EPXA1 Development Board
Hardware Reference Manual
September 2002
Version 1.1
EPXA1 Development Board Hardware Reference Manual
Copyright 2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights.
Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. All rights reserved.
ii Altera Corporation
About this Manual
How to Find
Information
This manual provides comprehensive information about the Altera ®
EPXA1 development board.
shows the manual revision history.
Table 1. Revision History
Date
August 2002
September 2002
First publication
Minor amendments
Description
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About this Manual
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Altera
EPXA1 Development Board Hardware Reference Manual
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com
.
For technical support on this product, go to http://www.altera.com/mysupport . For additional information about
Altera products, consult the sources shown in Table 2 .
Table 2. How to Contact Altera
Information Type
Technical support
Product literature
Altera literature services
Non-technical customer service
USA & Canada http://www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m.
Pacific Time) http://www.altera.com
(800) 767-3753
FTP site ftp.altera.com
Note:
(1) You can also contact your local Altera sales office or sales representative.
All Other Locations http://www.altera.com/mysupport/
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(7:00 a.m. to 5:00 p.m.
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Pacific Time) ftp.altera.com
iv Altera Corporation
EPXA1 Development Board Hardware Reference Manual
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1999 Device Data Book .
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Notes:
Contents
EPXA1 Development Board ........................................................................9
Altera Corporation vii
Contents Excalibur EPXA1 Development Board Hardware Refewrence Manual
viii Altera Corporation
EPXA1 Development Board
1
Features
Functional
Overview
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■
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Powerful development board for embedded processor FPGA designs
– Features an EPXA1F484 device
– Supports intellectual property-based (IP-based) designs using a microprocessor
Industry-standard interconnections
– 10/100 megabits per second (Mbps) Ethernet
– Two RS-232 ports
Memory subsystem
– 8 Mbytes of flash memory
– 32 Mbytes of single data rate (SDR) SDRAM
Multiple clocks for communications system design
Multiple ports for configuration and debugging
– IEEE Std. 1149.1 Joint Test Action Group (JTAG)
– Support for configuring the EPXA1 device using flash memory, with a MasterBlaster ™ or ByteBlasterMV ™ cable
– Multi-ICE header for debugging
Expansion headers for greater flexibility and capacity
– 5-V standard expansion header
– 5-V long expansion card header
Additional user-interface features
– One user-definable 8-bit dual in-line package (DIP) switch block
– Four user-definable push-button switches, plus reset switch
– Ten user-definable LEDs, plus function-specific LEDs
Test points provided to facilitate system development ■
The EPXA1 development board is a powerful, low-cost, product which you can use as a desktop hardware platform to start developing embedded systems immediately. In addition, the board can be used for system prototyping, emulation, hardware and software development or other special requirements. The development board provides a flexible, powerful debug and development environment to support the development of systems using Excalibur ™ devices.
Altera Corporation 9
EPXA1
Development
Board
Components
EPXA1 Development Board Hardware Reference Manual
This section describes the components on the EPXA1 development board, which is shown in
Figure 1. EPXA1 Development Board Layout
10
EPXA1 Device
The EPXA1 development board features the lowest-cost member of the
Excalibur family, the EPXA1. The EPXA1 device contains an ARM922T ™
32-bit RISC microprocessor combined with an APEX ™ 20KE FPGA in a
484-pin FineLine BGA ™ package.
lists the main features of the device.
Table 1. EPXA1 Device Features
Feature
Maximum system gates
Typical gates
LEs
ESBs
Maximum RAM bits
Maximum macrocells
Maximum user I/O pins
Capacity
263,000
100,000
4,160
26
53,248
416
186
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EPXA1 Development Board Hardware Reference Manual
In addition, the EPXA1 device provides a variety of peripherals, as listed
Table 2. EPXA1 Device Peripherals
Peripheral Description
ARM922T 32-bit RISC processor For speed grade –1: up to 200 MHz
For speed grade –2: up to 166 MHz
Interrupt controller Used for the interrupt system
Internal single-port SRAM
Internal dual-port SRAM
SDRAM controller
External SDRAM
Expansion bus interface (EBI)
External flash memory
32 Kbytes
16 Kbytes
Interfaces between the internal system bus and SDRAM
Refer to the Excalibur Devices Hardware Reference Manual for details of supported sizes
Interfaces to the flash memory and the Ethernet
Watchdog timer
UART
Reset controller
Refer to the Excalibur Devices Hardware Reference Manual for details of supported sizes
Protects the system against software failure
Facilitates serial communication
Resets the device
Refer to the Excalibur Devices Hardware Reference Manual for details about
EPXA1 devices.
Prototyping Area
This area can be used to develop and test custom circuitry, such as I/O interfaces, using the EPXA1 development board. The prototyping area has both 3.3-V and 5-V supply, plus ground connections, 32 I/O pins that facilitate connection to the Excalibur device, and a reset pin in a 6 × 15
matrix. Figure 2 shows the prototyping area on the development board.
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12
EPXA1 Development Board Hardware Reference Manual
Figure 2. Prototyping Area on the EPXA1 Development Board
A1
shows how the pins are located in the prototyping area.
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EPXA1 Development Board Hardware Reference Manual
Figure 3. Pin Layout in the Prototyping Area
P
R
M
N
K
L
H
J
E
F
C
D
G
A
B
RESET_n
1 2 3 4 5 6
PROTOIO_n
5V
NC
3.3 V
GND
See Table 37 on page 46 for details of the prototyping area pin-outs.
Interfaces
lists the interfaces supported by the EPXA1 development board.
Table 3. Development Board Interfaces
Interface Description
10/100 Ethernet with full- and halfduplexing
Expansion headers
This interface consists of an RJ45 connector and transformer connected to the EPXA1 using an external MAC/PHY device connected to the EBI
These headers are used to connect Altera daughter cards or customerdesigned daughter cards to develop and test custom circuitry
IEEE Std. 488 RS-232 serial interfaces This is a 250-kbps true RS-232 data terminal equipment (DTE) interface
Debugging/programming ports The board supports in-circuit debugging by means of the MasterBlaster,
ByteBlasterMV, or Multi-ICE cables
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EPXA1 Development Board Hardware Reference Manual
Serial I/O Interfaces
There can be two UARTs in the EPXA1 device. A dedicated UART is located in the embedded stripe; optionally, an additional IP UART can be implemented in the FPGA. If the IP UART is used, it is connected to 3.3-V standard EPXA1 I/O pins. Each UART is connected to a transceiver (U6 for the embedded stripe UART and U1 for the IP UART) to translate
LVTTL voltage for RS-232 compatibility at up to 250 Kbps. Each UART also has its own DB9 male RS-232 connector wired as a DTE.
The transceiver uses a 3.3-V power supply. If the RS-232 input pins are used as outputs, contention occurs because the bus transceiver is always active. If these pins are not used as part of a design, ensure that they remain in the high-impedance state.
All unused I/O pins can be set to tri-state mode in the Quartus II software (see
“Unused I/O Pins” on page 50 ).
See
Table 23 on page 33 for information on the RS-232 signals.
Table 4 shows the UART interface characteristics.
Table 4. UART Interface Characteristics
Features
UART 1 TX, RX & Control
UART 2 TX, RX & Control
I/O Pins
8
8
Voltage (V)
3.3
3.3
Table 5 lists the UART LEDs on the EPXA1 development board.
Table 5. UART LEDs
Board
Reference
D2
D3
D4
D7
Signal
TXD
RXD
XA-TXD
XA-RXD
Description
This LED indicates activity on the line
This LED indicates activity on the line
This LED indicates activity on the line
This LED indicates activity on the line
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EPXA1 Development Board Hardware Reference Manual
10/100 Ethernet Parallel Interface
On the EPXA1 development board, the Ethernet interface consists of an integrated MAC/PHY device and an RJ45 connector which includes the transformer and LEDs.
lists the LEDs built into the RJ45 connector.
Table 6. Ethernet LEDs
Board Reference Signal
RJ1 LEDA LEDA
RJ1 LEDB LEDB
Description
Green LED. This defaults to being set on when the
10/100 link is detected
Unused
Note:
(1) Although the default setting for LEDA ‘10/100 link detected’, the user can program the LEDA and LEDB select signals by writing to the LED select signal registers.
The Ethernet and flash memory device share addresses and data on the
EBI.
Memory Interfaces
The EPXA1 development board supports the following types and
capacities of on-board memory, as listed in Table 7 .
Table 7. Development Board Memory Characteristics
Type
SDR SDRAM
Flash
Address Lines Data Lines Control Lines Memory Organization
13
22
16
16
10
5
4 M
×
16 × 4 banks
2
×
4 Mbytes
Size
32 Mbytes; 16-bit
8 Mbytes
Figure 4 on page 16 shows the location of the on-board memory.
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EPXA1 Development Board Hardware Reference Manual
Figure 4. EPXA1 Development Board On-Board Memory
16
Flash memory (pin 1s indicated) SDRAM (pin 1 indicated)
Two flash memory chips, FLASH1 and FLASH2, are connected to the EBI of the EPXA1 development board (see
).
Figure 5. Flash Memory Interface
EPXA1
EBI
A1-A22
D0-D15
OE, WE, CE
Flash Memory (2 x 4 Mbyte)
EBI_CS1 EBI_CS0
A0-A21
FLASH1 FLASH2
PHY/MAC
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EPXA1 Development Board Hardware Reference Manual
LED & Switch Interfaces
The EPXA1 development board provides a variety of LED and switch interfaces. Some are user-definable and some are function-specific.
shows the location of LEDs and switches on the development board.
Figure 6. Switches & LEDs on the EPXA1 Development Board
Ethernet
TX/RX LEDs
UART LEDs
Altera Corporation
Push-button switches
SW2, SW3, SW4, SW5
Voltage LEDs
NPOR
SOFT_RESET_N
SW6 (pin 1 indicated)
User LEDs (LED 0 indicated)
User-Defined LEDs
On the EPXA1 development board, there are ten user-definable LEDs in a graph-type LED package, DG1. They connect directly to the EPXA1 device
I/O pins and can be used for any kind of application.
lists the user LEDs on the development board.
17
EPXA1 Development Board Hardware Reference Manual
Table 8. DG1 LED Interface Characteristics
LED Reference EPXA1 I/O Pin
DG1_J
DG1_I
DG1_H
DG1_G
DG1_F
DG1_E
DG1_D
DG1_C
DG1_B
DG1_A
W17
W18
W20
W21
W22
Y17
Y18
Y19
Y20
Y21
Signal
USER_LED9
USER_LED8
USER_LED7
USER_LED6
USER_LED5
USER_LED4
USER_LED3
USER_LED2
USER_LED1
USER_LED0
Voltage (V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
Function-Specific LEDs
LEDs are also used for specific application functions, such as the
configuration, RS-232 and Ethernet interfaces. Table 9 lists the function-
specific LEDs, their power supply status, their connection details, and their functions.
Table 9. Function-Specific LED Usage
Signal
INIT_DONE
VCC_5V
VCC_3V3
VCC_1V8
TXD
RXD
XA-TXD
XA-RXD
TX
RX
Board Reference
D15
D12
D13
D14
D2
D3
D4
D7
RJ1
RJ1
EPXA1 I/O Pin
(or Board
Connector)
K7
Description
Used by FPGA initialization; signifies that initialization is complete
5-V power indicator
3.3-V power indicator
1.8-V power indicator
FPGA UART signal indicator
FPGA UART signal indicator
Embedded stripe UART signal indicator
Embedded stripe UART signal indicator
Ethernet signal indicator
Ethernet signal indicator
Voltage (V)
3.3
3.3
3.3
3.3
3.3
3.3
5
3.3
1.8
3.3
18 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Switch Interfaces
The EPXA1 development board provides eight user-definable, active-low switches in a dip-switch block, four debounced push-button switches, and two dedicated reset switches.
documents the interface characteristics of the dip-switch block, SW6.
Table 10. SW6 Dip Switch Connections (Active-Low)
Switch Name EPXA1 I/O Pin
SW6_1
SW6_2
SW6_3
SW6_4
SW6_5
SW6_6
SW6_7
SW6_8
V20
V19
V18
V17
V16
U21
U20
U19
Signal
USER_SW7
USER_SW6
USER_SW5
USER_SW4
USER_SW3
USER_SW2
USER_SW1
USER_SW0
Voltage (V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
Tables 11 and 12 detail the push-button switches on the development
board.
Table 11. Push-Button Switches
Push Button EPXA1 I/O
Pin
SW1 H1
SW7 R4
Signal
NPOR
N_CONFIG
Use
Active-low switch that generates a full power-on reset when pressed for more than two seconds
Active-low switch that generates a warm reset
Voltage
(V)
3.3
3.3
Table 12. User-Definable Push-Button Switches
Push Button
SW2
SW3
SW4
SW5
EPXA1 I/O Pin
U18
U17
U16
T18
Signal
USER_PB0
USER_PB1
USER_PB2
USER_PB3
Voltage (V)
3.3
3.3
3.3
3.3
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EPXA1 Development Board Hardware Reference Manual
■
■
Development Board Expansion
The EPXA1 development board hosts the EPXA1 device and two 5-V expansion headers, which are implemented on the board for use with expansion cards. There are two types of expansion header on the EPXA1 development board:
Standard expansion header—a set of three 0.1-inch, two-row header pins (7 × 2, 10 × 2, 20 × 2)
Long expansion header—the same set of three 0.1-inch, two-row header pins (7 × 2, 10 × 2, 20 × 2) plus an extra 20 × 2 header pins
shows the location of the expansion headers on the
EPXA1 development board.
Figure 7. EPXA1 Development Board Expansion Header Connectors
Pin 1
Pin 1
20
The expansion header interfaces can be used to interface to specialfunction daughter cards; contact your Altera representative for details of the daughter cards available for use with the expansion header interfaces.
By using the EPXA1 I/O pins and the power-supply pins on the expansion headers, you can design expansion cards to your specific requirements using the I/O pins on the EPXA1 device and power supplies from the EPXA1 development board.
Altera Corporation
EPXA1 Development Board Hardware Reference Manual
The expansion headers are on a common 0.1-inch pitch/spacing to make it easier to use both headers together if desired.
Standard Expansion Header
The standard expansion header interface includes the following features:
■
■
■
■
■
■
■
■
■
■
■
40 APEX ® device general-purpose I/O signals
A buffered, zero-skew copy of the on-board OSC output
A buffered, zero-skew copy of the EPXA1’s PLL-output
An APEX device clock-input (for daughter cards that drive a clock to the FPGA
An active-low power-on-reset signal
Three regulated 3.3-V power-supply pins
One regulated 5-V power-supply pin
Unregulated power-supply pin (connects directly to J1 power-input plug)
Numerous ground connections
Card-select I/O
RC-filtered I/O
Long Expansion Header
The long expansion header interface shares the same characteristics as the standard interface, and has the following additional pins in use:
■
■
■
Two regulated 3.3-V power-supply pins
Sixteen address pins
Sixteen data pins
Expansion Header Pin Details
In addition, the following points apply to either standard or long expansion headers:
■
■
■
■
■
J9.38 and J15.38 can be used as a global card-enable signal
A low-current, 5-V power supply is presented on J4.2 and J11.2
The V
REF
voltage for the analog switches is presented on J10.3 and
J3.3.
The maximum current load on each header is 500 mA at 3.3 V, 50 mA at 5 V and 100 mA at 12 V
The remaining pins on the expansion headers connect to user I/O pins on the EPXA1 device.
Table 24 on page 34 lists the expansion
header signal pin assignments
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EPXA1 Development Board Hardware Reference Manual
Difference Between Standard and Long Expansion Headers
On the standard expansion header, there is an RC-filtered connection to
EPXA1 device I/O pin AB5 from header pin J11.3. This circuit is suitable for producing a high-impedance, low-precision analog output if the appropriate pin is driven with a duty-cycle-modulated waveform by user logic. However, there is no RC-filtered connection to an EPXA1 device
I/O pin from the long expansion header. Instead, header pin J4.3 supports an additional user I/O.
EPXA1 Device Signal Definitions for the Expansion Headers
Table 13 on page 22 shows the definitions for the EPXA1 device signals
available to the standard expansion header interface. The definitions are used with Altera daughter cards. The general purpose I/O signals can be used as required.
Table 13. Standard Expansion Header Signal Definitions
Function
General purpose I/O
Clock
Bias voltage input
Reset
Supply voltage
Signals
H5V_IO[40..0]
H5V_OSC
H5V_CLK
H5V_CLKOUT
H5V_VEE
H5V_RST_N
VCC_5V
VCC_A
VCC_3V3
Number
41
3
1
1
1
1
3
See
Table 24 on page 34 for standard expansion header pin-out details.
The long expansion header includes the signals in
Table 13 , plus the additional signals in Figure 14 .
Table 14. Additional Signal Definitions for the Long Expansion Header
Function
Address
Data
Supply voltage
Signals eup_A[15..0] eup_D[15..0]
VCC_5V
VCC_A2
VCC_3V3
Number
16
16
1
1
2
Altera Corporation
EPXA1 Development Board Hardware Reference Manual
See Table 25 on page 35 for long expansion header pin-out details.
f
Refer to the Nios Embedded Processor Development Board data sheet for further details about the expansion header interface.
Jumper
Configuration
The jumpers on the EPXA1 development board serve several functions:
■
■
■
Clock distribution
Enabling clocks
JTAG configuration
shows the location of jumpers on the development board.
Figure 8. Jumper Locations on the EPXA1 Development Board
JSELECT
(J5)
CLKA Select
(J13)
CLKB Select
(J14)
Table 15 on page 24 lists the jumper settings and their uses.
Altera Corporation 23
EPXA1 Development Board Hardware Reference Manual
Table 15. Jumpers on the EPXA1 Development Board
Jumper Function Pins 1-2 Connected
JSELECT
(J5)
CLKA Select
(J13)
CLKB Select
(J14)
JTAG connector selection ARM922 TAP available on Multi-
ICE connector
Clock A input selection 25 MHz on-board oscillator selected
Clock B input selection 25 MHz on-board oscillator selected
Pins 2-3 Connected
ARM922 TAP available on JTAG connector
Alternative 5-V DIL14 oscillator or
SMA connector selected
Alternative 5-V DIL14 oscillator or
SMA connector selected
Note:
(1) Determines whether the JTAG chains operate in serial or parallel mode.
Clocks
■
■
■
There are three potential clock sources on the EPXA1 development board, which can be enabled and disabled according to your design requirements:
Dedicated on-board, 25-MHz crystal oscillator, X1 (default clock for all devices)
Socket for alternative 5-V DIL14 crystal oscillator, XSKT1
Generator clock input via SMA connector, SMA1
The location of the clocks on the development board is shown in Figure 9
.
Figure 9. Clocks on the EPXA1 Development Board
24 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
The only device for which you cannot change the clock input is the Ethernet. The Ethernet clock input is the 25-MHz oscillator,
X1.
Apart from selecting the clock inputs, you can also select the target devices for each clock input.
If you plug in an alternative crystal oscillator, it drives the same clock line as the SMA connector. To drive a clock through the
SMA connector, you must remove the alternative crystal oscillator.
Table 16 on page 25 lists all the clock signals on the development board.
Table 16. EPXA1 Development Board Clocks (Part 1 of 2)
Clock Source EPXA1 Pin
(or Board
Connection)
CLK_REF
H7
CLKA_1
CLKA_2
CLKA_3
(OSC_BUFF1)
CLKA_4
(OSC_BUFF2)
U1
R21
(J3.9)
(J11.9)
CLKB_0
CLKB_1
V1
P21
OSC_25MHZ (U9:1)
CLKLK_ENA R6
CLKLK_OUT2p U22
Signal Name Description Target
Device
CLK_REF
CLK1p
CLK2p
H5V_OSC
H5V_OSC
Main clock used to drive the embedded stripe of the EPXA1. Dedicated input selected from either the SMA connector or the 25 MHz crystal oscillator using jumper CLKA Select (J13)
Dedicated pin that drives PLL1
EPXA1
EPXA1
Dedicated pin that drives PLL2
Clock to long expansion header
Clock to standard expansion header
EPXA1
Long expansion header
Standard expansion header
CLK3p
CLK4p
Dedicated pin that drives PLL3
Dedicated pin that drives PLL4
EPXA1
EPXA1
XTAL1
CLKLK_ENA
Clock to Ethernet; optionally used for other development board modules
Ethernet
Clock-enable for PLL circuitry; permanently on EPXA1
CLKLK_OUT2p Dedicated pin allowing PLL2 output to be driven off-chip, providing the PLL clock to the expansion headers as H5V_CLK
Standard expansion header,
Long expansion header
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EPXA1 Development Board Hardware Reference Manual
Table 16. EPXA1 Development Board Clocks (Part 2 of 2)
Clock Source EPXA1 Pin
(or Board
Connection)
CLKLK_FB2p N21
Signal Name Description Target
Device
CLKLK_FB2p Dedicated pin that allows external feedback to
PLL2. Available on test pad T14 (see
EPXA1
Note:
(1) See
“Jumper Configuration for the Clock Inputs” for details of selecting a source for the stripe
CLK_REF pin.
Up to two sources can be selected to clock the devices on the development board at any given time. Of the three sources available, the dedicated
25-MHz on-board oscillator cannot be varied in frequency.
As detailed in
, four of the clock buffer outputs drive dedicated inputs on the EPXA1 device.
One is the dedicated input providing the embedded stripe reference clock
CLK_REF . The four FPGA clocks service the ClockLock ™ and ClockBoost ™ circuitry on the Excalibur device. The clocks on the development board can be configured as required, depending on which devices are used.
Two clocks drive each expansion header: two from the main clock buffer and two from buffered copies of the EPXA1 PLL2 outputs.
Jumper Configuration for the Clock Inputs
Jumpers CLKA Select (J13) and CLKB Select (J14) are used to select different clock inputs. CLKA Select is used to determine the clock supply to the EPXA1 device clock reference, two of the four PLLs in the FPGA, and the two expansion headers. CLKB Select can be used to route an additional, alternative clock input to the EPXA1 device.
During development, if you need to run the clock at a rate other than
25 MHz, you can do so using the SMA connector or an alternative 5-V
DIL14 oscillator.
26 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
By selecting the position of jumpers CLKA Select and CLKB Select, as shown in
, either the SMA connector or an alternative 5-V DIL14 oscillator can be used instead of the 25-MHz on-board oscillator. To use the SMA connector to drive a clock onto the board from an external source, the alternative 5-V DIL14 oscillator socket must not contain an oscillator. To use an alternative 5-V DIL14 oscillator, ensure that no clock is attached to the SMA connector .
Table 17. CLKA Select & CLKB Select Jumper Settings
CLKA
Select
CLKB
Select
Pin 1-2 Connected Pin 2-3 Connected
25-MHz on-board oscillator provides a clock to
CLK_REF
CLK2
, EPXA1 dedicated inputs
, and both expansion headers
CLK1 and
25-MHz on-board oscillator provides the clock to
EPXA1 dedicated inputs CLK3 and CLK4
Alternative 5-V DIL14 oscillator or SMA connector selected provides CLK_REF , EPXA1 dedicated inputs CLK1 and CLK2 , and both expansion headers
Alternative 5-V DIL14 oscillator or SMA connector provides the clock to EPXA1 dedicated inputs
CLK3 and CLK4
■
■
■
Sources for the Stripe Clock Reference
There are three options for providing a source for the EPXA1 embedded stripe clock reference, CLK_REF :
25-MHz on-board oscillator
SMA connector
Alternative 5-V DIL14 oscillator
Using the 25-MHz On-board Oscillator
To use the 25-MHz on-board oscillator, set CLKA Select to position 1-2 to select it.
Using the SMA Connector
To select the SMA connector, follow the steps below:
1.
Remove any alternative 5-V DIL14 oscillator from the socket, XSKT1.
2.
Apply an external clock source to the SMA connector.
The clock signal should be a maximum 5 V
PP
.
3.
Set CLKA Select to position 2-3.
Altera Corporation 27
Device
Configuration
28
EPXA1 Development Board Hardware Reference Manual
Using the Alternative 5-V DIL14 Oscillator
To use the alternative oscillator as the stripe clock reference, follow the steps below:
1.
Remove any external clock input from the SMA connector.
2.
Plug the DIL14 crystal oscillator package into XSKT1.
3.
Set CLKA Select to position 2-3.
The clock buffer converts the 5-V input from the alternative 5-V
DIL14 oscillator to the 3.3 V required for the stripe.
Sources for CLK3 & CLK4
Clock sources for CLK3 and CLK4 can be selected in the same way as for the embedded stripe clock sources. Follow the instructions given in
“Sources for the Stripe Clock Reference” on page 27 , but use jumper
CLKB Select to select the clock source, instead of CLKA Select.
There are two methods of programming and configuring the EPXA1 device:
■
■
Booting from flash memory
Using the Quartus ® II software to configure the device via JTAG
See
for more details about using the JTAG interface.
On the EPXA1 device, the settings of BOOT_FLASH , MSEL0 , and
MSEL1 determine the configuration mode and method. On the
EPXA1 development board, BOOT_FLASH , MSEL0 and MSEL1 are tied to a setting that forces the device to boot from 16-bit flash memory.
Booting from Flash Memory
The Altera flash memory programmer ( exc_flash_programmer.exe
) is a utility that allows you to program flash memory on the EBI using the
JTAG interface and the ByteBlasterMV or MasterBlaster download cable, so that you can boot from it.
After reset, the processor boots up and executes the bootloader from flash memory. The bootloader configures the stripe, loads the user software into memory, configures the FPGA side of the EPXA1, and then begins to execute the user code.
Altera Corporation
EPXA1 Development Board Hardware Reference Manual f
For further details about booting the device from flash memory, refer to the Excalibur Devices Hardware Reference Manual .
Using the Quartus II Software
The Quartus II software can generate an SRAM object file (.
sof ) containing both hardware and software.
The Quartus II programmer uses the .
sof file to configure the EPXA1 device via JTAG, using either the MasterBlaster or ByteBlasterMV download cables.
f
For further details of how to create a .
sof file and configure the EPXA1 device via JTAG, consult the Quartus II Help.
JTAG Interfaces
There are two JTAG connectors on the EPXA1 development board, as shown in
Figure 10. JTAG Interfaces on the EPXA1 Development Board
JTAG connectors
(pin 1s indicated)
Altera Corporation
The JTAG connector, J6, is used to connect an Altera ByteBlaster or
MasterBlaster download cable. The Multi-ICE connector, J8, is used to connect a Multi-ICE cable or any other compatible cable.
29
EPXA1 Development Board Hardware Reference Manual
The JTAG connector can be used with both the flash programmer and the
Quartus programmer. In addition, the MasterBlaster and ByteBlasterMV cables support in-circuit debugging on the JTAG connector, using the
SignalTap ® embedded logic analyzer. The JSELECT setting does not affect this.
The JSELECT jumper, J5, determines whether a JTAG debugger can be connected to the JTAG connector or to the Multi-ICE connector. When using Altera-RDI via a ByteBlasterMV or MasterBlaster cable, the
JSELECT jumper must be set to 2-3; when using Multi-ICE or a compatible device on the Multi-ICE connector, JSELECT must be set to 1-2.
f
For further details about jumper settings, refer to Table 15 on page 24 .
Tables 26 and 27 starting on page 37 list the pin-outs of the JTAG and
Multi-ICE connectors.
Power Supply
A 12-V, 20-W supply unit powers the EPXA1 development board. The board has reverse-polarity protection and a 2-A fuse to provide overcurrent protection.
Figure 11 on page 30 shows the location of the power supply inputs for
the EPXA1 development board.
Figure 11. Power Supply Inputs on the EPXA1 Development Board
30 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
A voltage regulator regulates the main supplies for the board. The input supply is unregulated 12 V (±5%), which is reduced to 3.3 V for the I/O pins and to 1.8 V for the processor core. Voltage regulator U5 reduces the input to 5 V and distributes it to a pin on the expansion headers. The unregulated input is also routed to a pin on the expansion headers.
The maximum current permitted on the expansion headers depends on the input voltage: for 3.3 V, it is 500 mA, and for 5 V, it is 50 mA. If the input supply is 12 V, the maximum current per header depends on how much power is consumed by the rest of the board, but should not exceed
100 mA.
Three function-specific status LEDs indicate the presence of 1.8 V, 3.3 V, and 5 V to the board, as listed in
Table 18. Power Supply LEDs
Board Reference
D14
D13
D12
Signal
VCC_1V8
VCC_3V3
VCC_5V
Description
Indicates the presence of 1.8 V
Indicates the presence of 3.3 V
Indicates the presence of 5 V
list the estimated maximum power-supply requirements for the development board modules.
The typical power-supply requirement for the development board is 250 mA/500 mA.
Table 19. 12-V Supply Requirements
Module
Expansion headers 100 per header
Max mA
Table 20. 5-V Supply Requirements
Module
CLK_REF
Expansion headers
Max mA
Alternative crystal oscillator—75
50 per header
Altera Corporation 31
Test Points &
Test Pads
EPXA1 Development Board Hardware Reference Manual
Table 21. 3.3-V Supply Requirements
Module
EPXA1 I/O
SDRAM
Flash memory
UARTs
Ethernet
LEDs
Crystal oscillator
Clock buffers
Expansion headers
Max mA
500 (sum over all I/O pins)
285
45 × 2 = 90
20
140
15 × 18 = 270
+ (5 × 2) = 10
= 280
10
37 + 22 = 59
500 per header
Table 22. 1.8-V Supply Requirements
Module
EPXA1 device core mA
Depends on application (1.1 A maximum)
Test points on the EPXA1 development board, annotated as TP x, are provided for voltages and ground connections; see
For selected signals, test pads are provided on the board, annotated as T x ;
they are listed in Table 36 on page 45
.
32 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Signals
document the device signals for the following peripherals:
■
■
■
UART
Expansion headers
Configuration/debugging interfaces
UART
Figure 12 shows the DB9 male connector used on the development board.
Figure 12. UART DB9 Male Connector
1 2 3 4 5
6 7 8 9
Table 23 lists the UART DB9 signals.
Table 23. DTE UART DB9 Male Connector Signals
Pin
6
7
4
5
8
9
1
2
3
DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
RI
Signal Description
Data carrier detect
Receive data
Transmit data
Data terminal ready
Signal ground
Data set ready
Request to send
Clear to send
Ring indicator
Note:
(1) The EPXA1 development board has two DB9 male connectors.
Table 33 on page 44 lists pin-out information for the UARTs on the
development board.
Altera Corporation 33
34
EPXA1 Development Board Hardware Reference Manual
Expansion Headers
On the development board, there is a standard expansion header and a wide expansion header.
lists the signals on the standard expansion header.
Table 24. Standard Expansion Header Signals
7
10
20
×
×
×
2 Header, J11
2 Header, J10
2 Header, J15
Pin Signal
6
7
4
5
2
3
5
1
1
2
3
4
3
4
5
1
2
GND
VCC_5V
H5V_VEE
B_H5V_IO29
B_H5V_IO30
Vcc_UNREG
GND
VCC_A2
GND
VCC_3V3
GND
VCC_3V3
H5_RST_N
GND
B_H5V_IO0
B_H5V_IO1
B_H5V_IO2
8
9
6
7
B_H5V_IO3
B_H5V_IO4
B_H5V_IO5
B_H5V_IO6
10 B_H5V_IO7
11 B_H5V_IO8
12 B_H5V_IO9
13 B_H5V_IO10
14 B_H5V_IO11
Pin Signal
6 B_H5V_IO31
7
8
9
B_H5V_IO32
B_H5V_IO33
B_H5V_IO34
10 B_H5V_IO35
8 GND
9 H5V_OSC
10 GND
11 H5V_CLK
12 GND
13 H5V_CLKOUT
14 GND
15 B_H5V_IO12
16 B_H5V_IO13
17 B_H5V_IO14
18 B_H5V_IO15
19 GND
20 Removed
21 B_H5V_IO16
22 GND
23 B_H5V_IO17
24 GND
25 B_H5V_IO18
26 GND
27 B_H5V_IO19
28 B_H5V_IO20
Pin Signal
11 B_H5V_IO36
12 B_H5V_IO37
13 B_H5V_IO38
14 B_H5V_IO39
15 VCC_3V3
16 GND
17 NC
18 GND
19 NC
20 GND
29 B_H5V_IO21
30 GND
31 B_H5V_IO22
32 B_H5V_IO23
33 B_H5V_IO24
34 NC
35 B_H5V_IO25
36 B_H5V_IO26
37 B_H5V_IO27
38 H5_CS_N
39 B_H5V_IO28
40 GND
Table 39 on page 48 lists pin-out information for the standard expansion
header on development board.
Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Table 25 lists the signals on the long expansion header.
Table 25. Long Expansion Header Signals (Part 1 of 2)
7
10
20
×
×
×
2 Header, J4
2 Header, J3
2 Header, J9
Pin Signal
2
3
7
1
5
6
3
4
3
4
1
2
5
1
2
GND
VCC_5V
B_H5V_IO40
B_H5V_IO29
B_H5V_IO30
Vcc_UNREG
GND
VCC_A
GND
VCC_3V3
GND
VCC_3V3
H5_RST_N
GND
B_H5V_IO0
6
7
8
4
5
9
B_H5V_IO1
B_H5V_IO2
B_H5V_IO3
B_H5V_IO4
B_H5V_IO5
B_H5V_IO6
10 B_H5V_IO7
11 B_H5V_IO8
12 B_H5V_IO9
13 B_H5V_IO10
14 B_H5V_IO11
Pin Signal
8
9
6
7
B_H5V_IO31
B_H5V_IO32
B_H5V_IO33
B_H5V_IO34
10 B_H5V_IO35
8 GND
9 H5V_OSC
10 GND
11 H5V_CLK
12 GND
13 H5V_CLKOUT
14 GND
15 B_H5V_IO12
16 B_H5V_IO13
17 B_H5V_IO14
18 B_H5V_IO15
19 GND
20 Removed
21 B_H5V_IO16
22 GND
23 B_H5V_IO17
24 GND
25 B_H5V_IO18
26 GND
27 B_H5V_IO19
28 B_H5V_IO20
Pin Signal
11 B_H5V_IO36
12 B_H5V_IO37
13 B_H5V_IO38
14 B_H5V_IO39
15 VCC_3V3
16 GND
17 NC
18 GND
19 NC
20 GND
29 B_H5V_IO21
30 GND
31 B_H5V_IO22
32 B_H5V_IO23
33 B_H5V_IO24
34 NC
35 B_H5V_IO25
36 B_H5V_IO26
37 B_H5V_IO27
38 H5_CS_N
39 B_H5V_IO28
40 GND
Altera Corporation 35
EPXA1 Development Board Hardware Reference Manual
Table 25. Long Expansion Header Signals (Part 2 of 2)
20 × 2 Header, J2
Pin Signal
3
4
1
2
5
6
GND
GND
B_eup_A0
B_eup_D0
B_eup_A1
B_eup_D1
7
8
9
B_eup_A2
B_eup_D2
B_eup_A3
10 B_eup_D3
11 B_eup_A4
12 B_eup_D4
13 GND
14 GND
Pin Signal
15 B_eup_A5
16 B_eup_D5
17 B_eup_A6
18 B_eup_D6
19 B_eup_A7
20 B_eup_D7
21 B_eup_A8
22 B_eup_D8
23 B_eup_A9
24 B_eup_D9
25 B_eup_A10
26 B_eup_D10
27 GND
28 GND
Pin Signal
29 B_eup_A11
30 B_eup_D11
31 B_eup_A12
32 B_eup_D12
33 B_eup_A13
34 B_eup_D13
35 B_eup_A14
36 B_eup_D14
37 B_eup_A15
38 B_eup_D15
39 GND
40 GND
Table 38 on page 47 lists pin-out information for the long expansion
header on the development board.
36 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Configuration/Debugging Interfaces
On the development board, there are interfaces for a MasterBlaster or
ByteBlasterMV cable, and a Multi-ICE connector.
on the MasterBlaster/ByteBlasterMV connector.
on the Multi-ICE connector.
lists pin-out information for the development board configuration and debugging interfaces.
Table 26. MasterBlaster/ByteBlasterMV Female Connector Signals
Pin JTAG Mode
Signal Description
1 TCK Clock signal
2 GND Signal ground
3 TDO Data from device
4 V
CC
Power supply
5 TMS JTAG state machine control
6 V
IO
7 NC
Reference voltage for MasterBlaster output driver
No connect
8 No connection
9 TDI Data to device
10 GND Signal ground
Table 27. Multi-ICE Connector Signals (Part 1 of 2)
Pin Signal Description
1 VCC
2 VCC
Power supply
Power supply
3 PROC_NTRTST Processor reset
4 GND Ground
5 PROC_TDI
6 GND
7 PROC_TMS
8 GND
Processor test data input
Ground
Processor test mode select
Ground
9 PROC_TCK
10 GND
11 GND
12 GND
13 PROC_TDO
14 GND
Processor test clock input
Ground
Ground
Ground
Processor test data output
Ground
Direction
N/A
N/A
Output
N/A
Input
N/A
Input
N/A
Input
N/A
N/A
N/A
O
N/A
Altera Corporation 37
EPXA1 Development Board Hardware Reference Manual
Development
Board Pin-Outs
Table 27. Multi-ICE Connector Signals (Part 2 of 2)
Pin Signal
15 NSRST
16 GND
17 NC
18 GND
19 NC
20 GND
Warm reset
Ground
No connection
Ground
No connection
Ground
Description Direction
I/O
N/A
N/A
N/A
N/A
N/A
The main component of the EPXA1 development board is the EPXA1F484 device. The pins on the EPXA1 device are assigned to functions on the board. When generating IP cores for the EPXA1 device, the pins must be used as defined to avoid damaging the device and any unused pins should be tri-stated using the Quartus II software. The following sections list the interfaces and dedicated pins on the board. Any pins not used for a design should be left in a high-impedance state to avoid contention.
This section details the pins on the EPXA1 device which are assigned to the following purposes:
■
■
■
■
■
■
■
■
Configuration
SDR SDRAM
EBI—for the Ethernet and flash memory devices
UARTs 1 and 2
Fast I/O pins
Expansion headers
Prototyping area
Test pads
Pin assignments are grouped into tables for control pins, address pins, and data bus pins where appropriate. The tables also detail signals passing across a connection. The remaining I/O pins on the EPXA1 device are listed at the end of this section.
38 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Configuration
The EPXA1 device pins listed in
are used exclusively for configuring the device. Refer to
“Device Configuration” on page 28
for more information about EPXA1 configuration.
Table 28. EPXA1 Device Configuration Pins (Part 1 of 2)
DATA7
TDI
TDO
TCK
TMS
TRST
PROC_TDI
PROC_TDO
PROC_TCK
PROC_TMS
PROC_TRST
DEV_CLR_n nCEO
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
MSEL0
MSEL1
BOOT_FLASH
NSTATUS
NCONFIG
DCLK
CONF_DONE
INIT_DONE nCE
Signal Name EPXA1 Device
Pin
Y11
U11
J6
G7
G2
G3
H6
G6
R20
J1
L5
L4
L6
L22
M18
T20
J4
K7
P19
H3
P18
K3
R5
T3
J5
AB12
R4
R16
V12
Board
Reference
J6.9
J6.3
J6.1
J6.5
J8.5
J8.13
J8.9
J8.7
J8.3
T15, T14
Description
Configuration mode select (tied to GND )
Configuration mode select (tied to GND )
Tied high (mandatory boot from flash)
Pulled high
Connected to SOFT_RESET line
Pulled high
Pulled high
Initialization complete LED
Pulled low
Not connected
Pulled low
Unused. Used as general-purpose I/O
JTAG data input
JTAG data output (to next device in the chain
JTAG clock
JTAG mode select
JTAG reset (pulled high)
JTAG data input
JTAG data output (to next device in the chain)
JTAG clock
JTAG mode select
JTAG reset (pulled high)
FPGA clear signal taken to test pad T15, placed next to grounded test pad T14 near SW1; allows use of this signal, if required
Altera Corporation 39
EPXA1 Development Board Hardware Reference Manual
Table 28. EPXA1 Device Configuration Pins (Part 2 of 2)
Signal Name EPXA1 Device
Pin
DEV_OE nWS nRS nCS
CS
RDYnBSY
CLKUSR
U16
M21
P16
N20
P17
K4
L7
Board
Reference
Description
Device output enable. GPIO
Write strobe. GPIO
Read strobe. GPIO
Signal providing handshaking between devices. GPIO
Chip select. GPIO
Ready/busy. GPIO
Clock signal. GPIO
SDR SDRAM Interface
The EPXA1 development board contains one 16-bit SDR SDRAM device connected to the EPXA1 SDRAM controller.
f
For further details about the SDRAM controller, refer to the Excalibur
Devices Hardware Reference Manual .
The SDRAM_DQM[1:0] lines are used as byte enables for both reading from and writing to the SDRAM.
Table 29 shows the pin-outs for the SDR SDRAM control signals.
Table 29. SDR SDRAM Control Signal Pin-Outs
Signal Name
SD_RAS_N
SD_CAS_N
SD_WE_N
SD_CS0_N
SD_CLKE
SD_CLK
SD_CLK_N
SD_DQM[0]
SD_DQM[1]
SD_DQS[0]
SD_DQM_ECC
EPXA1 Device Pin Board Reference
J16
E21
J20
D22
B13
C14
A17
F14
U13.18
U13.17
U13.16
G15 U13.19
E15 U13.37
C15 U13.38
U13.15
U13.39
Description
Row address strobe
Column address strobe
Write enable
Clock enable
SDRAM clock
Read data strobe output in SDR mode
Data byte mask
Data byte mask
Read data strobe input in SDR mode
Not used
Note:
(1) These pins are tied together to provide a data-read strobe. See the Excalibur Devices Hardware Reference Manual .
40 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Table 30 lists the SDRAM data and address bus pin-outs.
Table 30. SDR SDRAM Data Bank & Address Bus Pin-Outs
Signal Name Signal Name
SD_DQ0
SD_DQ2
SD_DQ4
SD_DQ6
SD_DQ8
SD_DQ10
SD_DQ12
SD_DQ14
SD_A0
SD_A2
SD_A4
SD_A6
SD_A8
SD_A10
SD_A12
SD_A14
EPXA1 Device
Pin
A19
B18
C17
B19
D19
E18
B20
F18
E20
F20
H19
E22
G21
H17
B17
D16
Board
Reference
U13.2
U13.5
U13.8
U13.11
U13.42
U13.45
U13.48
U13.51
U13.23
U13.25
U13.29
U13.31
U13.33
U13.22
U13.36
U13.21
SD_DQ1
SD_DQ3
SD_DQ5
SD_DQ7
SD_DQ9
SD_DQ11
SD_DQ13
SD_DQ15
SD_A1
SD_A3
SD_A5
SD_A7
SD_A9
SD_A11
SD_A13
EPXA1 Device
Pin
C20
C21
F19
G18
G20
H18
H20
H22
G16
F16
E16
F17
D17
D18
C19
Board
Reference
U13.4
U13.7
U13.10
U13.13
U13.44
U13.47
U13.50
U13.53
U13.24
U13.26
U13.30
U13.32
U13.34
U13.35
U13.20
Altera Corporation 41
EPXA1 Development Board Hardware Reference Manual
EBI
The EBI shares addresses and data with the flash and Ethernet MAC/PHY devices. Each device has separate chip-select lines.
Table 31 shows the EPXA1 pin-outs for the EBI control signals and the
board references for the flash memory and Ethernet.
Table 31. EBI Control Signal Pin-Outs
Signal Name
EBI_BE0
EBI_BE1
EBI_OE_N
EBI_WE_N
EBI_CS0
EBI_CS1
EBI_CS2
EBI_CS3
EBI_CLK
EBI_ACK
EPXA1
Device Pin
D1
H9
D2
G8
Ethernet Board
Reference
U9.96
U9.97
U9.33
U9.34
Flash Memory
Board Reference
FLASH1.11,
FLASH2.11
FLASH1.26
FLASH2.26
C2
B3
D3
C4
C3
B4
U9.43
U9.44
Byte enable
Byte enable
Output enable
Write enable
Description
Chip select (flash memory 1)
Chip select (flash memory 2)
Chip select (not used)
Chip select (ethernet)
EBI clock
EBI acknowledge (not used)
Table 32 shows the EPXA1 pin-outs for the EBI data bank and address bus
and the board references for the flash memory and Ethernet.
EBI_DQ0
EBI_DQ1
EBI_DQ2
EBI_DQ3
EBI_DQ4
EBI_DQ5
EBI_DQ6
EBI_DQ7
EBI_DQ8
EBI_DQ9
Table 32. EBI Data Bank and Address Bus Pin-Outs (Part 1 of 2)
Signal Name EPXA1 Device Pin
D10
F10
C10
E10
A10
G11
B10
F11
D11
E11
Ethernet Board
Reference
U9.109
U9.108
U9.107
U9.106
U9.104
U9.103
U9.102
U9.101
U9.78
U9.77
Flash Memory 1
Board Reference
FLASH1.29
FLASH1.31
FLASH1.33
FLASH1.35
FLASH1.38
FLASH1.40
FLASH1.42
FLASH1.44
FLASH1.30
FLASH1.32
Flash Memory 2
Board Reference
FLASH2.29
FLASH2.31
FLASH2.33
FLASH2.35
FLASH2.38
FLASH2.40
FLASH2.42
FLASH2.44
FLASH2.30
FLASH2.32
42 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
EBI_A6
EBI_A7
EBI_A8
EBI_A9
EBI_A10
EBI_A11
EBI_A12
EBI_A13
EBI_A14
EBI_A15
EBI_A16
EBI_A17
EBI_A18
EBI_DQ10
EBI_DQ11
EBI_DQ12
EBI_DQ13
EBI_DQ14
EBI_DQ15
EBI_A0
EBI_A1
EBI_A2
EBI_A3
EBI_A4
EBI_A5
EBI_A19
EBI_A20
EBI_A21
EBI_A22
EBI_A23
EBI_A24
Table 32. EBI Data Bank and Address Bus Pin-Outs (Part 2 of 2)
Signal Name EPXA1 Device Pin
C7
A6
F8
B7
D7
A5
E7
B6
D8
C8
E8
A7
G9
C11
B11
F12
A12
E12
B12
C5
A4
C9
D9
B9
H10
B8
F9
A8
E9
A9 (not used)
G10 (not used)
Ethernet Board
Reference
U9.76
U9.75
U9.73
U9.72
U9.71
U9.70
(not used)
U9.80
U9.81
U9.82
U9.83
U9.84
U9.85
U9.86
U9.87
U9.88
U9.89
U9.90
U9.91
U9.92
U9.93
U9.94
Flash Memory 1
Board Reference
FLASH1.34
FLASH1.36
FLASH1.39
FLASH1.41
FLASH1.43
FLASH1.45
FLASH1.25
FLASH1.24
FLASH1.23
FLASH1.22
FLASH1.21
FLASH1.20
FLASH1.19
FLASH1.18
FLASH1.8
FLASH1.7
FLASH1.6
FLASH1.5
FLASH1.4
FLASH1.3
FLASH1.2
FLASH1.1
FLASH1.48
FLASH1.17
FLASH1.16
FLASH1.15
FLASH1.10
FLASH1.9
Flash Memory 2
Board Reference
FLASH2.34
FLASH2.36
FLASH2.39
FLASH2.41
FLASH2.43
FLASH2.45
FLASH2.25
FLASH2.24
FLASH2.23
FLASH2.22
FLASH2.21
FLASH2.20
FLASH2.19
FLASH2.18
FLASH2.8
FLASH2.7
FLASH2.6
FLASH2.5
FLASH2.4
FLASH2.3
FLASH2.2
FLASH2.1
FLASH2.48
FLASH2.17
FLASH2.16
FLASH2.15
FLASH2.10
FLASH2.9
Altera Corporation 43
EPXA1 Development Board Hardware Reference Manual
UART1 & UART2
Table 33 details the pins used for UARTs 1 and 2.
Table 33. UARTs 1 & 2 I/O Pin-Outs
FPGA UART
EPXA1 I/O
Pin
K4
J1
K5
L5
K3
L7
L6
L4
Connector
Pin
P1.4
P1.3
P1.2
P1.6
P1.7
P1.9
P1.1
P1.8
P1.5
DTR
TXD
RXD
DSR
RTS
RI
DCD
CTS
GND
Device
Signal
Embedded Stripe UART
EPXA1
Device Pin
E6
G5
F2
G4
E2
F3
F6
F1
Connector
Pin
P2.4
P2.3
P2.2
P2.6
P2.7
P2.9
P2.1
P2.8
P2.5
Device
Signal
XA_DTR
XA_TXD
XA_RXD
XA_DSR
XA_RTS
XA_RI
XA_DCD
XA_CTS
GND
Fast I/O Pins
Table 34 details the EPXA1 fast I/O pins, which are used as expansion
header clock inputs.
Table 34. EPXA1 Fast I/O Pins
EPXA1 Pin Name Board Signal
FAST1
FAST4
H5V_CLKOUT
H5V_CLKOUT
Description
Dedicated fast I/O pin
Dedicated fast I/O pin
EPXA1 Pin Expansion Header Card
Connector
J2
W12
J3.13
J10.13
44 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Test Points
lists the test points on the EPXA1 development board.
Table 35. EPXA1 Development Board Test Points
Test Point
TP1
TP2
TP3
TP4
TP5
Connected To
GND
GND
EBI_CLK
GND
3V3
Test Point
TP6
TP7
TP8
TP9
TP10
Connected To
1V8
GND
GND
5V
GND
Test Pads
Table 36 lists the test pads on the EPXA1 development board.
Table 36. EPXA1 Development Board Test Pads
Test Pad
T5
T6
T7
T8
T1
T2
T3
T4
Connected To
EBI chip-select 3
EBI write enable
Ethernet loopback active output
EBI output enable
EBI chip-select 0
EBI chip-select 2
EBI byte enable 0
EBI chip-select 1
Test Pad
T9
T10
T11
T12
T13
T14
T15
Connected To
EBI byte enable 1
JTAG clock
JTAG data output
JTAG mode select
JTAG data input
Feedback clock to PLL2
25-MHz clock
Altera Corporation 45
EPXA1 Development Board Hardware Reference Manual
Prototyping Area
Table 36 lists the pin assignments for the prototyping area on the EPXA1
development board.
Table 37. EPXA1 Development Board Prototyping Area Pin-Outs
Row/Column
P
R
K
L
M
N
H
J
F
G
C
D
E
A
B
1
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
VCC_5V GND
2
Board Reference
(EPXA1 Device Pin)
3 4 5 6
VCC_3V3 protoIO_29 (K15) protoIO_19 (L19) protoIO_9 (M22)
VCC_3V3 protoIO_28 (K17) protoIO_18 (L20) protoIO_8 (N16)
VCC_3V3 protoIO_27 (K18) protoIO_17 (L21) protoIO_7 (N20)
VCC_3V3 protoIO_26 (K19) protoIO_16 (L22) protoIO_6 (N22)
VCC_3V3 protoIO_25 (K20) protoIO_15 (M16) protoIO_5 (P16)
VCC_3V3 protoIO_24 (K21) protoIO_14 (M17) protoIO_4 (P17)
VCC_3V3 protoIO_23 (L15) protoIO_13 (M18) protoIO_3 (P20)
VCC_3V3 protoIO_22 (L16) protoIO_12 (M19) protoIO_2 (P22)
VCC_3V3 protoIO_21 (L17) protoIO_11 (M20) protoIO_1 (R22)
VCC_3V3 protoIO_20 (L18) protoIO_10 (M21) NC
VCC_3V3 NC NC NC
VCC_3V3 NC
VCC_3V3 NC
NC
NC protoIO_32 (AA19) protoIO_31 (AA20)
VCC_3V3 NC
VCC_3V3 NC
NC
NC protoIO_30 (AB19)
RESET_n (H4)
46 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Expansion Header I/O Pins
and 38 list the remaining I/O pins on the standard expansion
header and long expansion header, respectively, and their connections on the EPXA1 device.
Table 38. Development Board Long Expansion Header (Header 1) I/O Pin-Outs
Board Connector EPXA1 Device Board Connector EPXA1 Device Board Connector EPXA1 Device
J2.3
J2.4
J2.5
J2.6
J2.7
J2.8
J2.9
J2.10
J2.11
J2.12
J2.15
J2.16
J2.17
J2.18
J2.19
J2.20
J2.21
J2.22
J2.23
J2.24
J2.25
J2.26
J2.29
J2.30
J2.31
W1
P6
V3
P5
V2
W3
R1
W2
P7
P2
U2
P1
T8
P4
U4
P3
U3
N7
T7
N6
T6
N5
T5
N4
T4
N3
R7
N2
R3
N1
R2
M7
AB9
T10
M5
M4
M3
L3
T9
R10
AB10
M6
L2
L1
Y10
Y9
Y8
Y7
Y6
Y5
J2.32
J2.33
J2.34
J2.35
J2.36
J2.37
J2.38
J4.3
J4.4
J4.5
J4.6
J4.7
J4.8
J4.9
J4.10
J4.11
J4.12
J4.13
J4.14
J9.3
J9.4
J9.5
J9.6
J9.7
J9.8
J9.18
J9.21
J9.23
J9.25
J9.27
J9.28
J9.29
J9.31
J9.32
J9.33
J9.35
J9.36
J9.37
J9.39
J9.9
J9.10
J9.11
J9.12
J9.13
J9.14
J9.15
J9.16
J9.17
H5_CS_N
(J15.38)
V7
V6
V5
V4
V11
V10
V9
V8
U10
U9
U8
U7
U6
T11
AB8
Y4
Y3
Y2
W11
W10
W9
W8
W7
W5
Altera Corporation 47
EPXA1 Development Board Hardware Reference Manual
Table 39. Development Board Standard Expansion Header (Header 2) I/O Pin-Outs
Board Connector EPXA1 Device Board Connector EPXA1 Device Board Connector EPXA1 Device
J11.4
J11.5
J11.6
J11.7
J11.8
J11.9
J11.10
J11.11
J11.12
J11.13
J11.14
J15.3
J15.4
J15.5
AA14
AA12
AB4
AA10
AA9
AA8
AA7
AA6
AA5
AA4
AA3
Y22
Y16
Y15
J15.6
J15.7
J15.8
J15.9
J15.10
J15.11
J15.12
J15.13
J15.14
J15.15
J15.16
J15.17
J15.18
J15.21
Y14
Y13
Y12
W16
W15
W14
W13
V15
V14
V13
U15
U14
U13
U12
J15.23
J15.25
J15.27
J15.28
J15.29
J15.31
J15.32
J15.33
J15.35
J15.36
J15.37
J15.39
H5_CS_N
(J9.38)
T15
T14
T13
T12
R13
AB17
AB16
AB15
AB14
AA17
AA16
AA15
AB6
General Usage
Guidelines
To use the development board properly, and to avoid damage to it, follow the guidelines in this section.
Anti-Static Handling
Before handling the development board, you should take proper antistatic precautions, otherwise it can be damaged.
Power Consumption
The level of power consumption in the EPXA1 development board depends on what peripherals are implemented in the FPGA, typically in relation to the following variables:
■
■
■
Number of interfaces used
Density and speed of the device
Population of the interfaces
The board’s typical operating current while running diagnostics is approximately 250 mA.
A 20-W power supply is supplied as part of the EPXA1 development kit.
It is capable of meeting the maximum power requirement imposed by the board if all interfaces are used within specification.
48 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Test Core Functionality
The EPXA1 board is supplied with a diagnostic software image directly programmed into flash memory. When the embedded processor boots, it configures the FPGA and runs the software using the test FPGA image.
The software is controlled using a serial terminal connected to the board connector, P2, and the following PC communications port settings: baud rate 38400, 8 data bits, no parity, one stop bit and no flow control.
Ensure that the serial terminal program is configured to output carriage return and line feeds—not all terminals default to these settings.
The options on the software menu are as follows: e—Run Ethernet internal loopback test
E—Run Ethernet external loopback test (requires loopback connector) h—Show this screen i—Show interrupt usage m—Run memory test t—Toggle terminal output between UARTS
■
■
■
The Ethernet internal loopback test checks that the Ethernet chip is working properly—the external loopback test is for manufacturing test only
The toggle between the UARTS switches the output of the program between P1 and P2. P2 is connected to the UART in the EPXA1 embedded stripe; P1 is connected to a UART which has been programmed into the FPGA. After switching the port using the t command, you can connect the serial terminal to the currentlyunused serial connector (i.e., if you were using P2, you will now use
P1), and type h
↵ to invoke the help menu.
The memory test tests the integrity of the SDRAM on the board.
In addition, the LEDS and switches can be tested as follows:
■
■
■
■
■
Each of the eight switches on the switch block can turn the corresponding LED on or off; for example, SW6_1 turns on the first
LED
When held down, SW5 toggles the 9th LED
When held down, SW4 toggles the 10th LED
When held down, SW3 inverts the current setting of all the LEDS
SW2 shifts all the LEDS right (as viewed) by one place
Altera Corporation 49
50
EPXA1 Development Board Hardware Reference Manual
Unused I/O Pins
Damage could result to the EPXA1 device, if all unused I/O pins are not set to tri-state mode in the Quartus II software.
To set the unused I/O pins to tri-state mode, run the Quartus II software, open the appropriate project, and follow the steps below:
1.
Choose Compile Mode (Processing menu).
2.
Choose Compiler Settings (Processing menu).
3.
Click the Chips & Devices tab.
4.
Click Device & Pin Options .
5.
Click the Unused Pins tab.
6.
Select As inputs, tri-stated .
7.
Click Apply .
Altera Corporation
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