Texas Instruments DRV8301-RM48-KIT - RM48 Hercules Safety MCU Motor Control Kit DRV8301-RM48-KIT Dev Kit Data Sheet

DRV8301 www.ti.com

SLOS719B – AUGUST 2011 – REVISED AUGUST 2013

Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator

Check for Samples: DRV8301

1

FEATURES

• Operating Supply Voltage 6V–60V

• 2.3A Sink and 1.7A Source Gate Drive Current

Capability

• Integrated Dual Shunt Current Amplifiers With

Adjustable Gain and Offset

• Integrated Buck Converter to Support up to

1.5A External Load

• Independent Control of 3 or 6 PWM Inputs

• Bootstrap Gate Driver With 100% Duty Cycle

Support

• Programmable Dead Time to Protect External

FETs from Shoot Through

• Slew Rate Control for EMI Reduction

• Programmable Overcurrent Protection of

External MOSFETs

• Support Both 3.3V and 5V Digital Interface

• SPI Interface

• Thermally Enhanced 56-Pin TSSOP Pad Down

DCA Package

APPLICATIONS

• 3-Phase Brushless DC Motor and Permanent

Magnet Synchronous Motor

• CPAP and Pump

• E-bike, Hospital Bed, Wheel Chair

• Power Drill, Blender, Chopper

DESCRIPTION

The DRV8301 is a gate driver IC for three phase motor drive applications. It provides three half bridge drivers, each capable of driving two N-type

MOSFETs, one for the high-side and one for the low side. It supports up to 2.3A sink and 1.7A source peak current capability and only needs a single power supply with a wide range from 6V to 60V. The

DRV8301 uses bootstrap gate drivers with trickle charge circuitry to support 100% duty cycle. The gate driver uses automatic hand shaking when high side

FET or low side FET is switching to prevent current shoot through. Vds of FETs is sensed to protect external power stage during overcurrent conditions.

The DRV8301 includes two current shunt amplifiers for accurate current measurement.

The current amplifiers support bi-directional current sensing and provide an adjustable output offset of up to 3V.

The DRV8301 also has an integrated switching mode buck converter with adjustable output and switching frequency to support MCU or additional system power needs. The buck is capable to drive up to 1.5A load.

The SPI interface provides detailed fault reporting and flexible parameter settings such as gain options for current shunt amplifier, slew rate control of gate driver, etc.

PVDD

Vs

Motor

Controller

PWM

3 or 6

SPI

Error

Reporting

ADC1

Vref

ADC2

DRV8301

Buck

Converter

Control and

Protection

Logic offset offset

Three-Phase

NMOS Gate

Driver

_

+

_

+

GH_ A

GL_A

GH_ B

GL_B

GH_C

GL_C

MOTOR

Figure 1. DRV8301 Simplified Application Schematic

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2011–2013, Texas Instruments Incorporated

DRV8301

SLOS719B – AUGUST 2011 – REVISED AUGUST 2013 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DEVICE INFORMATION

PIN ASSIGNMENT

The DRV8301 is designed to fit the 56pin DCA package. Here is the pinout of the device.

RT_CLK 1

COMP 2

VSENSE 3

PWRGD 4

OCTW 5

FAULT 6

DTC 7

SCS 8

SDI 9

SDO 10

SCLK 11

DC_CAL 12

GVDD 13

CP1 14

CP2 15

EN_GATE 16

INH_A 17

INL_A 18

INH_B 19

INL_B 20

INH_C 21

INL_C 22

DVDD 23

REF 24

SO1 25

SO2 26

AVDD 27

AGND 28

37

36

35

34

41

40

39

38

44

43

42

4 8

47

46

45

33

32

31

30

29

52

51

50

49

56

55

54

53

GH_C

SH_C

GL_C

SL_C

SN1

SP1

SN2

SP2

PVDD1

SS_TR

EN_BUCK

PVDD2

PVDD2

BST_BK

PH

PH

VDD_S PI

BST_A

GH_A

SH_A

GL_A

SL_A

BST_B

GH_B

SH_B

GL_B

SL_B

BST_C

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Product Folder Links: DRV8301


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REF

SO1

SO2

AVDD

AGND

PVDD1

SP2

SN2

SP1

SN1

SL_C

GL_C

SH_C

GH_C

NAME

RT_CLK

PIN

COMP

VSENSE

PWRGD

OCTW

FAULT

DTC

SCS

SDI

SDO

SCLK

DC_CAL

GVDD

CP1

CP2

EN_GATE

INH_A

INL_A

INH_B

INL_B

INH_C

INL_C

DVDD

31

32

33

34

28

29

30

35

36

24

25

26

27

19

20

21

22

23

13

14

15

16

17

18

8

9

10

11

12

6

7

NO.

1

2

3

4

5

37

DRV8301

I

I

O

O

I

I

I

I

I

P

I

I

P

I

I

I

P

P

I/O

(1)

I

O

O

P

O

I

O

O

O

I

I

I

I

I

P

P

I

I

O


PIN FUNCTIONS

DESCRIPTION

Resistor timing and external clock for buck regulator. Resistor should connect to GND (power pad) with very short trace to reduce the potential clock jitter due to noise.

Buck error amplifier output and input to the output switch current comparator.

Buck output voltage sense pin. Inverting node of error amplifier.

An open drain output with external pull-up resistor required. Asserts low if buck output voltage is low due to thermal shutdown, dropout, over-voltage, or EN_BUCK shut down

Over current or/and over temperature warning indicator. This output is open drain with external pull-up resistor required. Programmable output mode via SPI registers.

Fault report indicator. This output is open drain with external pull-up resistor required.

Dead-time adjustment with external resistor to GND

SPI chip select

SPI input

SPI output

SPI clock signal

When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset calibration can be done through external microcontroller.

Internal gate driver voltage regulator. GVDD cap should connect to GND

Charge pump pin 1, ceramic cap should be used between CP1 and CP2

Charge pump pin 2, ceramic cap should be used between CP1 and CP2

Enable gate driver and current shunt amplifiers. Control buck via EN_BUCK pin.

PWM Input signal (high side), half-bridge A

PWM Input signal (low side), half-bridge A

PWM Input signal (high side), half-bridge B

PWM Input signal (low side), half-bridge B

PWM Input signal (high side), half-bridge C

PWM Input signal (low side), half-bridge C

Internal 3.3V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified to drive external circuitry.

Reference voltage to set output of shunt amplfiiers with a bias voltage which equals to half of the voltage set on this pin. Connect to ADC reference in microcontroller.

Output of current amplifier 1

Output of current amplifier 2

Internal 6V supply voltage, AVDD cap should always be installed and connected to AGND. This is an output, but not specified to drive external circuitry.

Analog ground pin

Power supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD1 is independent of buck power supply, PVDD2. PVDD1 cap should connect to GND

Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best commom mode rejection.

Input of current amplifier 2 (connecting to negative input of amplifier).

Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best commom mode rejection.

Input of current amplifier 1 (connecting to negative input of amplifier).

Low-Side MOSFET source connection, half-bridge C. Low-side V

DS

SH_C.

measured between this pin and

Gate drive output for Low-Side MOSFET, half-bridge C

High-Side MOSFET source connection, half-bridge C. High-side V

DS

PVDD1.


Gate drive output for High-Side MOSFET, half-bridge C

(1) KEY: I =Input, O = Output, P = Power

Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 3


DRV8301


NAME

BST_C

SL_B

GL_B

SH_B

GH_B

BST_B

SL_A

GL_A

SH_A

PIN

GH_A

BST_A

VDD_SPI

PH

BST_BK

PVDD2

EN_BUCK

SS_TR

GND

(POWER

PAD)

NO.

38

39

40

41

42

43

44

45

46

47

48

49

50, 51

52

53,54

55

56

57 www.ti.com

PIN FUNCTIONS (continued)

P

P

I

O

P

I

O

I/O

(1)

P

I

O

O

P

I

O

I

I

I

P

DESCRIPTION

Bootstrap cap pin for half-bridge C

Low-Side MOSFET source connection, half-bridge B. Low-side V

DS

SH_B.


Gate drive output for Low-Side MOSFET, half-bridge B

High-Side MOSFET source connection, half-bridge B. High-side V

DS

PVDD1.


Gate drive output for High-Side MOSFET, half-bridge B

Bootstrap cap pin for half-bridge B

Low-Side MOSFET source connection, half-bridge A. Low-side V

DS

SH_A.


Gate drive output for Low-Side MOSFET, half-bridge A

High-Side MOSFET source connection, half-bridge A. High-side V

DS

PVDD1.


Gate drive output for High-Side MOSFET, half-bridge A

Bootstrap cap pin for half-bridge A

SPI supply pin to support 3.3V or 5V logic. Connect to either 3.3V or 5V.

The source of the internal high side MOSFET of buck converter

Bootstrap cap pin for buck converter

Power supply pin for buck converter, PVDD2 cap should connect to GND.

Enable buck converter. Internal pull-up current source. Pull below 1.2V to disable. Float to enable.

Adjust the input undervoltage lockout with two resistors

Buck soft-start and tracking. An external capacitor connected to this pin sets the output rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. Cap should connect to GND

GND pin. The exposed power pad must be electrically connected to ground plane through soldering to

PCB for proper operation and connected to bottom side of PCB through vias for better thermal spreading.




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FUNCTION BLOCK DIAGRAM

OCTW

FAULT

EN _GATE

DTC

SCLK

SDI

SDO

SCS

VDD _SPI

Phase A

( repeated for B& C)

Gate Driver

Control

&

Fault

Handling

(PVDD_UV,

CP_UV,

OTW, OTSD,

OC_LIMIT)

INH _A

INL _A

OSC

Timing and

Control

Logic

Charge

Pump

Regulator

Trickle

Charge

High Side

Gate Drive

Low Side

Gate Drive

DRV8301


PVDD1

CP2

CP1

GVDD

BST _A

GH _A

SH_A

GL _A

SL _A

PVDD1

Motor

PVDD2

VSENSE

BST _ BK

PH

EN _BUCK

PWRGD

SS_TR

RT_CLK

COMP

Current

Sense

Amplifier1

Buck

Converter

Offset

½ Vref

Offset

½ Vref

Current

Sense

Amplifier2

SN1

SP1

REF

DC_CAL

SN2

SP2

AVDD

DVDD

Rshunt1

PGND

Power

Pad

GND

SO1 SO2

AGND

AGND GND PGND



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DRV8301


ABSOLUTE MAXIMUM RATINGS

(1)

I

PVDD

PVDD

RAMP

V

PGND

I

IN_MAX

IN_OD_MAX

V

V

V

OPA_IN

LOGIC

GVDD

V

AVDD

V

DVDD

V

VDD_SPI

V

SDO

V

REF

I

REF

T

J

T

STORAGE

Supply voltage range including transient Relative to PGND

Maximum supply voltage ramp rate Voltage rising up to PVDD

MAX

Maximum voltage between PGND and GND

Maximum current for all digital and analog inputs (INH_A, INL_A, INH_B, INL_B,

INH_C, INL_C, SCLK, SCS, SDI, EN_GATE, DC_CAL, DTC)

Maximum sinking current for open drain pins (FAULT and OCTW Pins)

Voltage range for SPx and SNx pins

Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C,

INL_C, EN_GATE, SCLK, SDI, SCS, DC_CAL)

Maximum voltage for GVDD Pin

Maximum voltage for AVDD Pin

Maximum voltage for DVDD Pin

Maximum voltage for VDD_SPI Pin

Maximum voltage for SDO Pin

Maximum reference voltage for current amplifier

Maximum current for REF Pin

Maximum operating junction temperature range

Storage temperature range

Capacitive discharge model

Human body model

VALUE

MIN

–0.3

±0.3

±1

7

±0.6

-0.3

13.2

8

3.6

7

VDD_SPI +0.3

7

100

–40

–55

500

2000

MAX

70

1

7

150

150

UNITS

V

V/µS

V mA mA

V

V

°C

V

V

V

µA

°C

V

V

V

V

V

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION

θ

JA

θ

JCtop

θ

JB

ψ

JT

ψ

JB

θ

JCbot

THERMAL METRIC

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

(1)

DRV8301

DCA

(56) PINS

30.3

33.5

17.5

0.9

7.2

0.9

UNITS

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953 .





RECOMMENDED OPERATING CONDITIONS


R

DTC

I

FAULT

I

OCTW

V

REF f gate

PVDD1

PVDD2

C

PVDD1

C

PVDD2

C

AVDD

C

DVDD

C

GVDD

C

CP

C

BST

I

DIN_EN

I

DIN_DIS

C

DIN

C

O_OPA

I gate

T

A

DC supply voltage PVDD1 for normal operation

DC supply voltage PVDD2 for buck converter

Relative to PGND

External capacitance on PVDD1 pin (ceramic cap) 20% tolerance

External capacitance on PVDD2 pin (ceramic cap) 20% tolerance

External capacitance on AVDD pin (ceramic cap) 20% tolerance

External capacitance on DVDD pin (ceramic cap) 20% tolerance

External capacitance on GVDD pin (ceramic cap) 20% tolerance

Flying cap on charge pump pins (between CP1 and CP2) (ceramic cap) 20% tolerance

Bootstrap cap (ceramic cap)

Input current of digital pins when EN_GATE is high

Input current of digital pins when EN_GATE is low

Maximum capacitance on digital input pin

Maximum output capacitance on outputs of shunt amplifier

Dead time control resistor range. Time range is 50ns (-GND) to 500ns (150k Ω ) with a linear approximation.

FAULT pin sink current. Open-drain

OCTW pin sink current. Open-drain

V = 0.4 V

V = 0.4 V

External voltage reference voltage for current shunt amplifiers

Operating switching frequency of gate driver

Qg(TOT) = 25 nC or total 30 mA gate drive average current

Total average gate drive current

Ambient temperature

ELECTRICAL CHARACTERISTICS

PVDD = 6 V to 60 V, T

C

= 25°C, unless specified under test condition

PARAMETER TEST CONDITIONS

I

INPUT PINS: INH_X, INL_X, M_PWM (SCS), M_OC (SDI), GAIN(SDO), EN_GATE, DC_CAL

V

IH

V

IL

R

EN_GATE

High input threshold

Low input threshold

Internal pull down resistor for EN_GATE

R

INH_X

Internal pull down resistor for high side PWMs

(INH_A, INH_B, and INH_C)

EN_GATE high

R

INH_X

Internal pull down resistor for low side PWMs

(INL_A, INL_B, and INL_C)

R

SCS

Internal pull down resistor for SCS

R

SDI

R

DC_CAL

Internal pull down resistor for SDI

Internal pull down resistor for DC_CAL

R

SCLK

Internal pull down resistor for SCLK

OUTPUT PINS: FAULT AND OCTW

V

OL

Low output threshold

V

OH

High output threshold

EN_GATE high

EN_GATE high

EN_GATE high

EN_GATE high

EN_GATE high

I

O

= 2 mA

External 47 k Ω pull up resistor connected to 3-5.5 V

OH

Leakage Current on Open Drain Pins When

Logic High (FAULT and OCTW)

MIN TYP MAX UNITS

6 60 V

3.5

4.7

4.7

60 V

µF

µF

1

1

2.2

22 220

100

µF

µF

µF nF

100

1

10

20 nF

µA

µA pF pF

0

2

150

2

2

6

200 k Ω mA mA

V kHz

–40

30

125 mA

°C

MIN TYP MAX UNIT

2

2.4

100

100

100

100

100

100

100

0.8

V

V k Ω k Ω k Ω k Ω k Ω k Ω k Ω

0.4

V

V

1 µA




DRV8301


ELECTRICAL CHARACTERISTICS (continued)

PVDD = 6 V to 60 V, T

C

= 25°C, unless specified under test condition

PARAMETER TEST CONDITIONS

GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C

V

GX_NORM

V

GX_MIN

Gate driver Vgs voltage

Gate driver Vgs voltage

I oso1

I osi1

I oso2

I osi2

Maximum source current setting 1, peak

Maximum sink current setting 1, peak

Source current setting 2, peak

Sink current setting 2, peak

I oso3

I osi3

Source current setting 3, peak

Sink current setting 3, peak

R gate_off

Gate output impedence during standby mode when EN_GATE low (pins GH_x, GL_x)

SUPPLY CURRENTS

I

PVDD1_STB

PVDD1 supply current, standby

PVDD = 8V–60V, I gate

C

CP

= 22nF

= 30mA,


C

CP

= 220nF

= 30mA,


C

CP

= 22nF

= 15mA,


C

CP

= 220nF

= 30mA,

Vgs of FET equals to 2 V. REG 0x02






I

PVDD1_OP

PVDD1 supply current, operating

I

PVDD1_HIZ

PVDD1 Supply current, HiZ

INTERNAL REGULATOR VOLTAGE

EN_GATE is low. PVDD1 = 8V.

EN_GATE is high, no load on gate drive output, switching at 10 kHz,

100 nC gate charge

EN_GATE is high, gate not switching

A

VDD

AVDD voltage

PVDD = 8V - 60V

PVDD = 6V - 60V

D

VDD

DVDD voltage

VOLTAGE PROTECTION

V

PVDD_UV

Under voltage protection limit, PVDD

PVDD falling

PVDD rising

GVDD falling V

GVDD_UV

V

GVDD_OV

Under voltage protection limit, GVDD

Over voltage protection limit, GVDD

CURRENT PROTECTION, (VDS SENSING)

V

DS_OC

Drain-source voltage protection limit

PVDD = 8V - 60V

PVDD = 6V - 8V

(1)

T oc

T

OC_PULSE

OC sensing response time

OCTW pin reporting pulse stretch length for OC event

(1) Reduced A

VDD voltage range results in limitations on settings for over current protection. See

Table 9

.


9.5

9.5

8.8

8.3

1.6

2

6

5.5

3

0.125

0.125

1.7

2.3

0.7

1

0.25

0.5

20

15

5

6.5

3.3

16

1.5

64

11.5

11.5

7

6

3.6

5.9

6

8

2.4

1.491

V

V

A

A

A

A

A

A

2.4

k Ω

50 µA mA

10 mA

V

V

V

V

V

V

µs

µs






GATE TIMING AND PROTECTION CHARACTERISTICS

TIMING, OUTPUT PINS

PARAMETER TEST CONDITIONS t pd,If-O t pd,Ir-O

T d_min

T dtp t

GDr t

GDF

T

ON_MIN

Positive input falling to GH_x falling

Positive input rising to GL_x falling

Minimum dead time after hand shaking

(1)

Dead Time

Rise time, gate drive output

Fall time, gate drive output

Minimum on pulse

CL=1nF, 50% to 50%

CL=1nF, 50% to 50%

With R

DTC set to different values

CL=1nF, 10% to 90%

CL=1nF, 90% to 10%

Not including handshake communication.

Hiz to on state, output of gate driver

T pd_match

Propagation delay matching between high side and low side

T dt_match

Deadtime matching

TIMING, PROTECTION AND CONTROL t pd,R_GATE-OP

Start up time, from EN_GATE active high to device ready for normal operation

PVDD is up before start up, all charge pump caps and regulator caps as in recommended condition t pd,R_GATE-Quick t pd,E-L t pd,E-FAULT

OTW_CLR

OTW_SET/OTSD

_CLR

OTSD_SET

If EN_GATE goes from high to low and back to high state within quick reset time, it will only reset all faults and gate driver without powering down charge pump, current amp, and related internal voltage regulators.

Delay, error event to all gates low

Delay, error event to FAULT low

Junction temperature for resetting over temperature warning

Junction temperature for over temperature warning and resetting over temperature shut down

Junction temperature for over temperature shut down

Maximum low pulse time


50

45

45

25

25

5

200

200

115

130

150 ns ns

50 ns

500 ns ns ns

50 ns

5 ns

5 ns

10 ms

10 us ns ns

°C

°C

°C

(1) Dead time programming definition: Adjustable delay from GH_x falling edge to GL_X rising edge, and GL_X falling edge to GH_X rising edge. In 6-PWM input mode, this adjustable value is added to the timing delay between inputs as set by the microcontroller externally.




DRV8301


CURRENT SHUNT AMPLIFIER CHARACTERISTICS

T

C

= 25°C unless otherwise specified

PARAMETER

G1 Gain option 1

G2

G3

G4

Tsettling

Tsettling

Gain option 2

Gain Option 3

Gain Option 4

Settling time to 1%

Settling time to 1%

Tsettling

Tsettling

Vswing

Settling time to 1%

Settling time to 1%

Output swing linear range

Slew Rate

DC_offset Offset error RTI

Drift_offset Offset drift RTI

Ibias

Vin_com

Vin_dif

Vo_bias

CMRR_OV

Input bias current

Common input mode range

Differential input range

Output bias

Overall CMRR with gain resistor mismatch

TEST CONDITIONS

Tc = -40°C-125°C

Tc = -40°C-125°C

Tc = -40°C-125°C

Tc = -40°C-125°C

Tc = 0-60°C, G = 10, Vstep = 2 V

Tc = 0-60°C, G = 20, Vstep = 2 V

Tc = 0-60°C, G = 40, Vstep = 2 V

Tc = 0-60°C, G = 80, Vstep = 2 V

G = 10

G = 10 with input shorted

With zero input current, Vref up to 6 V

CMRR at DC, gain = 10

BUCK CONVERTER CHARACTERISTICS

T

C

= 25°C unless otherwise specified

PARAMETER

V

UVLO

I

SD(PVDD2)

I

NON_SW(PVDD2)

Internal undervoltage lockout threshold

Shutdown supply current

Operating: nonswitching supply current

V

EN_BUCK

R

DS_ON

I

LIM

OTSD_BK

F sw

PWRGD

Enable threshold voltage

On-resistance

Current limit threshold

Thermal shutdown

Switching frequency

VSENSE threshold

Hysteresis

Output high leakage

On resistance

TEST CONDITIONS

No voltage hysteresis, rising and falling

EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V

VSENSE = 0.83 V, VIN = 12 V

No voltage hysteresis, rising and falling,

25°C

VIN = 3.5 V, BOOT-PH = 3 V

VIN = 12 V, T

J

= 25°C

RT = 200 k Ω

VSENSE falling

VSENSE rising

VSENSE rising

VSENSE falling

VSENSE falling

VSENSE = VREF, V(PWRGD) = 5.5 V,

25°C

I(PWRGD) = 3 mA, VSENSE < 0.79 V www.ti.com

MIN

9.5

18

38

75

TYP MAX UNIT

10 10.5

V/V

20

40

21

42

V/V

V/V

80

300

600

1.2

2.4

85 V/V ns ns

µs

µs

0.3

10

10

–0.15

100

0.15

–0.3

0.3

–0.5% 0.5×Vref 0.5%

5.7

V

V/µs

4 mV

µV/C

µA

V

V

V

70 85 dB


2.5

V

1.3

116

4

136

µA

µA

0.9

1.25

1.55

V

1.8

450

300

2.7

182

581

92%

94%

109%

107%

2%

10

50 m Ω

A

°C

720 kHz nA

Ω

SPI CHARACTERISTICS (Slave Mode Only)

PARAMETER t

SPI_READY t

CLK t

CLKH t

CLKL

SPI ready after EN_GATE transitions to

HIGH

Minimum SPI clock period

Clock high time

Clock low time

PVDD > 6 V

TEST CONDITIONS MIN TYP MAX UNIT

5 10 ms ns 100

40

40

10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated



SPI CHARACTERISTICS (Slave Mode Only) (continued)

t

SU_SDI t

HD_SDI

PARAMETER

SDI input data setup time

SDI input data hold time

TEST CONDITIONS t

D_SDO

SDO output data delay time, CLK high to

SDO valid

SDO output data hold time

C

L

= 20 pF t

HD_SDO t

SU_SCS t

HD_SCS

SCS setup time

SCS hold time t

HI_SCS

SCS minimum high time before SCS active low t

ACC t

DIS

SCS access time, SCS low to SDO out of high impedance

SCS disable time, SCS high to SDO high impedance



20 ns

30 ns

20 ns

40

50

50

40 ns ns ns

10

10 ns ns t

HI_SCS

_ t

SU_SCS t

HD_SCS

SCS t

CLK

SCLK t

CLKH t

CLKL

SDI

SDO

Z t

ACC

MSB in

(must be valid) t

SU_SDI t

HD_SDI

MSB out (is valid) t

D_SDO t

HD_SDO

Figure 2. SPI Slave Mode Timing Definition

LSB

LSB t

DIS

Z

1 2 3 4 X 15 16

SCS

SCLK

SDI

SDO

Receive latch Points

MSB

MSB

LSB

LSB

Figure 3. SPI Slave Mode Timing Diagram




DRV8301


FUNCTIONAL DESCRIPTION

www.ti.com

THREE-PHASE GATE DRIVER

The DRV8301 provides three half bridge drivers, each capable of driving two N-type MOSFETs, one for the highside and one for the low side.

Gate driver has following features:

• Internal hand shake between high side and low side FETs during switching transition to prevent current shoot through.

• Programmable slew rate or current driving capability through SPI interface.

• Support up to 200kHz switching frequency with Qg(TOT)=25nC or total 30mA gate drive average current

• Provide cycle-by-cycle current limiting and latch over-current (OC) shut down of external FETs. Current is sensed through FET drain-to-source voltage and the over-current level is programmable through SPI interface

• Vds sensing range is programmable from 0.060V to 2.4V and with 5 bit programmable resolution through SPI.

• High side gate drive will survive negative output from half bridge up to –10V for 10ns

• During EN_GATE pin low and fault conditions, gate driver will keep external FETs in high impedance mode.

• Programmable dead time through DTC pin. Dead time control range: 50ns to 500ns. Short DTC pin to ground will provide minimum dead time (50ns). External dead time will override internal dead time as long as the time is longer than the dead time setting (minimum hand shake time cannot be reduced in order to prevent shoot through current).

• Bootstraps are used in high side FETs of three-phase pre-gate driver. Trickle charge circuitry is used to replenish current leakage from bootstrap cap and support 100% duty cycle operation.

CURRENT SHUNT AMPLIFIERS

The DRV8301 includes two high performance current shunt amplifiers for accurate current measurement. The current amplifiers provide output offset up to 3V to support bi-directional current sensing.

Current shunt amplifier has following features:

• Programmable gain: 4 gain settings through SPI command

• Programmable output offset through reference pin (half of the Vref)

• Minimize DC offset and drift over temperature with dc calibrating through SPI command or DC_CAL pin.

When DC calibration is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating can be done at anytime even when FET is switching since the load is disconnected. For best result, perform the DC calibrating during switching off period when no load is present to reduce the potential noise impact to the amplifier.

The output of current shunt amplifier can be calculated as:

V

REF

V =

O

2

G ´ ( SN

X

SP

X

)

(1)

Where Vref is the reference voltage, G is the gain of the amplifier; SNx and SPx are the inputs of channel x. SPx should connect to resistor ground for the best common mode rejection.

Figure 4

shows current amplifier simplified block diagram.




DRV8301


SN

DC_CAL

DC_CAL

5 k W

400 k W

200 k W

100 k W

50 k W

_

SP

DC_CAL

5 k W

+

50 k W

100 k W

200 k W

400 k W

S4

S3

S2

S1

AVDD

S1

S2

S3

S4

REF

_

AVDD

50 k W

50 k W

+

100 W

SO

Vref /2

Figure 4. Current Shunt Amplifier Simplified Block Diagram

BUCK CONVERTER

The buck converter in the DR8301 is the same as the TPS54160 buck converter. Although integrated in the same device, buck converter is designed completely independent of rest of the gate driver circuitry. Since buck will support external MCU or other external power need, the independency of buck operation is very critical for a reliable system; this will give buck minimum impact from gate driver operations. Some examples are: when gate driver shuts down due to any failure, buck will still operate unless the fault is coming from buck itself. The buck keeps operating at much lower PVDD of 3.5V, this will assure the system to have a smooth power up and power down sequence when gate driver is not able to operate due to a low PVDD.

The buck has an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.

The wide switching frequency of 300kHz to 2200kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT_CLK pin.

The device has an internal phase lock loop (PLL) on the RT_CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock.

The buck converter has a default start up voltage of approximately 2.5V. The EN_BUCK pin has an internal pullup current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external resistors. In addition, the pull up current provides a default condition. When the EN_BUCK pin is floating the device will operate. The operating current is 116µA when not switching and under no load. When the device is disabled, the supply current is 1.3µA.




DRV8301


The integrated 200m Ω high side MOSFET allows for high efficiency power supply designs capable of delivering

1.5 amperes of continuous current to a load. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high side MOSFET off when the boot voltage falls below a preset threshold. The buck can operate at high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V

reference.

The BUCK has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the pin to transition high when a pull-up resistor is used.

The BUCK minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from turning on until the output voltage is lower than 107%.

The SS_TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor divider can be coupled to the pin for critical power supply sequencing requirements. The SS_TR pin is discharged before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,

The BUCK, also, discharges the slow start capacitor during overload conditions with an overload recovery circuit.

The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startup and overcurrent fault conditions to help control the inductor current.

PROTECTION FEATURES

Power Stage Protection

The DRV8301 provides over-current and under-voltage protection for the MOSFET power stage. During fault shut down conditions, all gate driver outputs will be kept low to ensure external FETs at high impedance state.

Over-Current Protection (OCP) and Reporting

To protect the power stage from damage due to high currents, a V

DS sensing circuitry is implemented in the

DRV8301. Based on R

DS(on) of the power MOSFETs and the maximum allowed I

DS

, a voltage threshold can be calculated which, when exceeded, triggers the OC protection feature. This voltage threshold level is programmable through SPI command.

There are total 4 OC_MODE settings in SPI.

1. Current Limit Mode

When current limit mode is enabled, device operates current limiting instead of OC shut down during OC event. The over-current event is reported through OCTW pin. OCTW reporting should hold low during same

PWM cycle or for a max 64µs period (internal timer) so external controller has enough time to sample the warning signal. If in the middle of reporting, other FET(s) gets OC, then OCTW reporting will hold low and recount another 64µS unless PWM cycles on both FETs are ended.

There are two current control settings in current limit mode (selected by one bit in SPI and default is CBC mode).

– Setting 1 (CBC mode): during OC event, the FET that detected OC will turn off until next PWM cycle.

– Setting 2 (off-time control mode):

– During OC event, the FET that detected OC will turn off for 64us as off time and back to normal after that (so same FET will be on again) if PWM signal is still holding high. Since all three phases or 6

FETs share a single timer, if more than one FET get OC, the FETs will not be back to normal until the all FETs that have OC event pass 64µs.

– If PWM signal is toggled for this FET during timer running period, device will resume normal operation for this toggled FET. So real off-time could be less than 64uS in this case.

– If two FETs get OC and one FET’s PWM signal gets toggled during timer running period, this FET will be back to normal, and the other FET will be off till timer end (unless its PWM is also toggled)





2. OC latch shut down mode

When OC occurs, device will turn off both high side and low side FETs in the same phase if any of the FETs in that phase has OC.

3. Report only mode

No protection action will be performance in this mode. OC detection will be reported through OCTW pin and

SPI status register. External MCU should take actions based on its own control algorithm. A pulse stretching of 64µS will be implemented on OCTW pin so controller can have enough time to sense the OC signal.

4. OC disable mode

Device will ignore all the OC detections and will not report them either.

Under-Voltage Protection (UVP)

To protect the power output stage during startup, shutdown and other possible under-voltage conditions, the

DRV8301 provides power stage under-voltage protection by driving its outputs low whenever PVDD is below 6V

(PVDD_UV) or GVDD is below 8V (GVDD_UV). When UVP is triggered, the DRV8301 outputs are driven low and the external MOSFETs will go to a high impedance state.

Over-Voltage Protection (GVDD_OV)

Device will shut down both gate driver and charge pump if GVDD voltage exceeds 16V to prevent potential issue related to GVDD or charge pump (e.g. short of external GVDD cap or charge pump). The fault is a latched fault and can only be reset through a transition on EN_GATE pin.

Over-Temperature Protection

A two-level over-temperature detection circuit is implemented:

• Level 1: over temperature warning (OTW)

OTW is reported through OCTW pin (over-current-temperature warning) for default setting. OCTW pin can be set to report OTW or OCW only through SPI command. See SPI Register section.

• Level 2: over temperature (OT) latched shut down of gate driver and charge pump (OTSD_GATE)

Fault will be reported to FAULT pin. This is a latched shut down, so gate driver will not be recovered automatically even OT condition is not present anymore. An EN_GATE reset through pin or SPI

(RESET_GATE) is required to recover gate driver to normal operation after temperature goes below a preset value, t

OTSD_CLR

.

SPI operation is still available and register settings will be remaining in the device during OTSD operation as long as PVDD is still within defined operation range.

Fault and Protection Handling

The FAULT pin indicates an error event with shut down has occurred such as over-current, over-temperature, over-voltage, or under-voltage. Note that FAULT is an open-drain signal. FAULT will go high when gate driver is ready for PWM signal (internal EN_GATE goes high) during start up.

The OCTW pin indicates over current event and over temperature event that not necessary related to shut down.

Following is the summary of all protection features and their reporting structure:




DRV8301


EVENT

PVDD undervoltage

DVDD undervoltage

GVDD undervoltage

GVDD overvoltage

OTW

OTSD_GATE

OTSD_BUCK

Buck output undervoltage

Table 1. Fault and Warning Reporting and Handling

ACTION LATCH

REPORTING ON REPORTING ON

FAULT PIN OCTW PIN

External FETs HiZ;

Weak pull down of all gate driver output

External FETs HiZ;

Weak pull down of all gate driver output; When recovering, reset all status registers

External FETs HiZ;


External FETs HiZ;


Shut down the charge pump

Won’t recover and reset through

SPI reset command or quick EN_GATE toggling

N

N

N

Y

Y

Y

Y

Y

N

N

N

N

None N N

Y (in default setting)

Gate driver latched shut down.

Weak pull down of all gate driver output to force external FETs HiZ

Shut down the charge pump

OTSD of Buck

Y

Y

Y

N

Y

N

UVLO_BUCK: auto-restart N Y, in PWRGD pin N

Buck overload

External FET overload – current limit mode

External FET overload – Latch mode

Buck current limiting

(HiZ high side until current reaches zero and then auto-recovering)

External FETs current Limiting

(only OC detected FET)

Weak pull down of gate driver output and PWM logic “0” of

LS and HS in the same phase.

External FETs HiZ

N

N

Y

N

N

Y

N

Y

Y

External FET overload – reporting only mode

Reporting only N N Y

REPORTING IN SPI

STATUS REGISTER

Y

N

Y

Y

Y

Y

N

N

N

Y www.ti.com

Y, indicates which phase has OC

Y, indicates which phase has OC





PIN CONTROL FUNCTIONS


EN_GATE

EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into a low power consumption mode to save energy. SPI communication is not supported during this state. Device will put the MOSFET output stage to high impedance mode as long as PVDD is still present.

When EN_GATE pin goes to high, it will go through a power up sequence, and enable gate driver, current amplifiers, charge pump, internal regulator, etc and reset all latched faults related to gate driver block. It will also reset status registers in SPI table. All latched faults can be reset when EN_GATE is toggled after an error event unless the fault is still present.

When EN_GATE goes from high to low, it will shut down gate driver block immediately, so gate output can put external FETs in high impedance mode. It will then wait for 10us before completely shutting down the rest of the blocks. A quick fault reset mode can be done by toggling EN_GATE pin for a very short period (less than 10µS).

This will prevent device to shut down other function blocks such as charge pump and internal regulators and bring a quicker and simple fault recovery. SPI will still function with such a quick EN_GATE reset mode.

The other way to reset all the faults is to use SPI command (RESET_GATE), which will only reset gate driver block and all the SPI status registers without shutting down other function blocks.

One exception is to reset a GVDD_OV fault. A quick EN_GATE quick fault reset or SPI command reset won’t work with GVDD_OV fault. A complete EN_GATE with low level holding longer than 10µS is required to reset

GVDD_OV fault. It is highly recommended to inspect the system and board when GVDD_OV occurs.

EN_BUCK

Buck enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable.

DTC

Dead time can be programmed through DTC pin. A resistor should be connected from DTC to ground to control the dead time. Dead time control range is from 50ns to 500ns. Short DTC pin to ground will provide minimum dead time (50ns). Resistor range is 0 to 150k Ω . Dead time is linearly set over this resistor range.

Current shoot through prevention protection will be enabled in the device all time independent of dead time setting and input mode setting.

VDD_SPI

VDD_SPI is the power supply to power SDO pin. It has to be connected to the same power supply (3.3V or 5V) that MCU uses for its SPI operation.

During power up or down transient, VDD_SPI pin could be zero voltage shortly. During this period, no SDO signal should be present at SDO pin from any other devices in the system since it causes a parasitic diode in the

DRV8301 conducting from SDO to VDD_SPI pin as a short. This should be considered and prevented from system power sequence design.

DC_CAL

When DC_CAL is enabled, device will short inputs of shunt amplifier and disconnect from the load, so external microcontroller can do a DC offset calibration. DC offset calibration can be also done with SPI command. If using

SPI exclusively for DC calibration, the DC_CAL pin can connected to GND.

SPI Pins

SDO pin has to be 3-state, so a data bus line can be connected to multiple SPI slave devices. SCS pin is active low. When SCS is high, SDO is at high impendence mode.




DRV8301


STARTUP AND SHUTDOWN SEQUENCE CONTROL

During power-up all gate drive outputs are held low. Normal operation of gate driver and current shunt amplifiers can be initiated by toggling EN_GATE from a low state to a high state. If no errors are present, the DRV8301 is ready to accept PWM inputs. Gate driver always has control of the power FETs even in gate disable mode as long as PVDD is within functional region.

There is an internal diode from SDO to VDD_SPI, so VDD_SPI is required to be powered to the same power level as other SPI devices (if there is any SDO signal from other devices) all the time. VDD_SPI supply should be powered up first before any signal appears at SDO pin and powered down after completing all communications at SDO pin.

SPI COMMUNICATION

SPI Interface

SPI interface is used to set device configuration, operating parameters and read out diagnostic information. The

DRV8301 SPI Interface operates in the slave mode.

The SPI input data (SDI) word consists of 16bit word, with 11 bit data and 5 bit (MSB) command. The SPI output data (SDO) word consists of 16bit word, with 11 bit register data and 4 bit MSB address data and 1 frame fault bit (active 1). When a frame is not valid, frame fault bit will set to 1, and rest of SDO bit will shift out zeros.

A valid frame has to meet following conditions:

1. Clock must be low when /SCS goes low.

2. We should have 16 full clock cycles.

3. Clock must be low when /SCS goes high.

When SCS is asserted high, any signals at the SCLK and SDI pins are ignored, and SDO is forced into a high impedance state. When SCS transitions from HIGH to LOW, SDO is enabled and the SPI response word loads into the shift register based on 5 bit command in SPI at previous clock cycle.

The SCLK pin must be low when SCS transitions low. While SCS is low, at each rising edge of the clock, the response bit is serially shifted out on the SDO pin with MSB shifted out first.

While SCS is low, at each falling edge of the clock, the new control bit is sampled on the SDI pin. The SPI command bits are decoded to determine the register address and access type (read or write). The MSB will be shifted in first. If the word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error. If it is a write command, the data will be ignored. The fault bit in SDO (MSB) will report 1 at next 16 bit word cycle.

After the 16th clock cycle or when SCS transitions from LOW to HIGH, in case of write access type, the SPI receive shift register data is transferred into the latch where address matches decoded SPI command address value. Any amount of time may pass between bits, as long as SCS stays active low. This allows two 8-bit words to be used.

For a read command (Nth cycle) in SPI, SP0 will send out data in the register with address in read command in next cycle (N+1).

For a write command in SPI, SPO will send out data in the status register 0x00h in next 16 bit word cycle (N+1).

For most of the time, this feature will maximize SPI communication efficiency when having a write command, but still get fault status values back without sending extra read command.

SPI Format

SPI input data control word is 16-bit long, consisting of:

• 1 read or write bit W [15]

• 4 address bits A [14:11]

• 11 data bits D [10:0]

SPI output data response word is 16-bit long, and its content depends on the given SPI command (SPI Control

Word) in the previous cycle. When a SPI Control Word is shifted in, the SPI Response Word (that is shifted out during the same transition time) is the response to the previous SPI Command (shift in SPI Control Word "N" and shift out SPI Response Word "N-1").





Therefore, each SPI Control / Response pair requires two full 16-bit shift cycles to complete.

Table 2. SPI Input Data Control Word Format

R/W Address

Word Bit B15 B14 B13 B12 B11 B10

Command W0 A3 A2 A1 A0 D10

B9

D9

B8

D8

B7

D7

B6

D6

Data

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

Table 3. SPI Output Data Response Word Format

R/W

Word Bit B15 B14 B13 B12 B11 B10

Command F0 A3 A2 A1 A0 D10

B9

D9

B8

D8

Data

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

B0

D0

SPI Control and Status Registers

Read / Write Bit

The MSB bit of SDI word (W0) is read/write bit. When W0 = 0, input data is a write command; when W0 = 1, input data is a read command, and the register value will send out on the same word cycle from SDO from D10 to D0.

Address Bits

Register Type Address [A3..A0]

Status

Register

Control

Register

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

1

Register

Name

Status

Register 1

Table 4. Register Address

Description

Report occurred faults after previous reading

Device ID and report occurred faults after previous reading

Status

Register 2

Control

Register 1

Control

Register 2

Read and Write Access

R (auto reset to default values after read)

Device ID: R

Fault report: R (auto reset to default values after read)

R/W

R/W

SPI Data Bits

Status Registers

Address

0x00

Register

Name

Status

Register 1

Table 5. Status Register 1 (Address: 0x00) (all default values are zero)

D10 D9 D8 D7 D6 D5 D4 D3 D2

FAULT GVDD_UV PVDD_UV OTSD OTW FETHA_OC FETLA_OC

D1 D0

FETHB_OC FETLB_OC FETHC_OC FETLC_OC

Table 6. Status Register 2 (Address: 0x01) (all default values are zero)

Address Register Name

0x01 Status

Register 2

D7

GVDD_OV

D6 D5 D4 D3 D2

Device ID

D1

0 0

D0

0 0

• All status register bits are in latched mode. Read each status register will reset the bits in this register. Read fault register twice to get an updated status condition.

• EN_GATE toggling with “low” level holding longer than 10µS will force a shut down and start up sequence and reset all values in status registers including GVDD_OV fault.

• EN_GATE toggling (quick fault reset) with low level holding less than 10uS or GATE_RESET high (in SPI) will reset all values in status registers except GVDD_OV fault which will still be latched as a fault.

Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 19


DRV8301


• FAULT is high when any fault occurs to cause a shut down (GVDD_UV, PVDD_UV, OTSD, OCSD,

GVDD_OV), which is opposite to FAULT hardware pin.

Control Registers

Address

0x02

Table 7. Control Register 1 for Gate Driver Control (Address: 0x02)

(1)

D10 D9 D8 D7 D6 D5 D4 D3 Name

GATE_CURRENT

GATE_RESET

PWM_MODE

Description

Gate driver peak current 1.7A (for slew rate control)

Gate driver peak current 0.7A

Gate driver peak current 0.25A

Reserved

Normal mode

Reset all latched faults related to gate driver, reset gate driver back to normal operation, reset status register values to default

GATE_RESET value will automatically reset to zero after gate driver completes reset

PWM with six independent inputs

PWM with three independent inputs. PWM control high side gates only. Low side is complementary to high side gates with minimum internal dead time.

OC_MODE

(gate driver only)

Current limiting when OC detected

OC_ADJ_SET

Latched shut down when OC detected

Report only (no current limiting or shut down) when OC detected

OC protection disabled (no OC sensing and reporting)

See OC_ADJ_SET table X X X X X

0

0

1

1

0

1

0

1

0

1

(1) Bold is default value

D2

0

1

Address

0x03

Table 8. Control Register 2 for Current Shunt Amplifiers and Misc Control (Address: 0x03)

(1)

Name

OCTW_SET

GAIN

DC_CAL_CH1

DC_CAL_CH2

OC_TOFF

Description

Report both OT and OC at /OCTW pin

Report OT only

Report OC only

Report OC Only (Reserved)

Gain of shunt amplifier: 10V/V




Shunt amplifier 1 connects to load through input pins

Shunt amplifier 1 shorts input pins and disconnected from load for external calibration

Shunt amplifier 2 connects to load through input pins

Shunt amplifier 2 shorts input pins and disconnected from load for external calibration

Normal CBC operation (recovering at next PWM cycle)

Off time control during OC

D10 D9 D8 D7 D6

0

1

D5

0

1

D4

0

1

D3

0

0

1

1

D2

0

1

0

1

D1

0

0

1

1

Reserved

(1) Bold value is default value

D1

0

0

1

1

D0

0

1

0

1

D0

0

1

0

1






Over Current Adjustment

When external MOSFET is turned on, the output current flows the MOSFET, which creates a voltage drop V

DS

The overcurrent protection event will be enabled when the V

DS exceeds a pre-set value IOC. The OC tripped

.

value can be programmed through SPI command. Assuming the on resistance of MOSFET is R

DS(on) can be calculated as:

, the Vds

V

DS

= I

OC

× R

DS(on)

V

DS is measured across the SL_x and SH_x pins for the low-side MOSFET. For the high-side MOSFET, V

DS is measured across PVDD1 (internally) and SH_x. Therefore, it is important to limit the ripple on the PVDD1 supply for accurate high-side current sensing.

It is also important to note that there can be up to a 20% tolerance across channels for the OC trip point. This is meant for protection and not to be used for regulating current in a motor phase.

Control Bit (D6–D10) (0xH)

Vds (V)


Vds (V)


Vds (V)

Code Number (0xH)

Vds (V)

0

0.060

8

0.155

16

0.403

24

1.043

Table 9. OC_ADJ_SET Table

1

0.068

9

0.175

17

0.454

25

1.175

2

0.076

10

0.197

18

0.511

26

1.324

3

0.086

11

0.222

19

0.576

27

1.491

4

0.097

12

0.250

20

0.648

28

1.679

(1)

5

0.109

13

0.282

21

0.730

29

1.892

(1)

(1) Do not use settings 28, 29, 30, 31 for V

DS sensing if the IC is expected to operate in the 6V – 8V range.

6

0.123

14

0.317

22

0.822

30

2.131

(1)

7

0.138

15

0.358

23

0.926

31

2.400

(1)




DRV8301


Application Schematic Example

Example:

Buck: PVDD= 3.5V – 40V, Iout_max = 1.5A, Vo = 3.3V, Fs = 570 kHz www.ti.com

VCC

120pF

6.8 nF

205 k W

31.6 k W

VCC

10 k W

Motor

Controller

16 .2 K

10k W

RT _CLK

COMP

VSENSE

PWRGD

10 k W

2.2

10k W m F

OCTW

FAULT

DTC

SCS

SDI

SDO

SCLK

DC_ CAL

GVDD

22 nF

CP1

1 m F

CP2

EN_ GATE

INH_ A

INL_ A

INH_ B

INL_ B

INH_

C

INL_ C

DVDD

REF

SO1

SO2

AVDD

1 m F

AGND

0 .015

m F

SS _TR

EN_BUCK

PVDD 2

PVDD 2

BST _BK

PH

PH

VDD _SPI

BST _A

GH_A

SH_A

GL _A

SL_A

BST _B

GH_B

SH_B

GL _B

SL_B

BST_ C

GH_ C

SH_ C

GL_ C

SL_ C

SN1

SP 1

SN2

SP 2

PVDD 1

0.1

m F

0.1

m F

VCC

0.1

m F

0.1

m F

0.1

m F

1 nF

4.7

m F

1 nF

PVDD

22 m H

47 m F

10 m W RS1

0 .1

m F 4.7

m F

PVDD

AGND GND

3 .3

10 nF

VCC ( 3.3V )

PVDD

RS2

10m W

PVDD

470 m F

GND

MOTOR

Power

Pad

GND

PGND






PCB LAYOUT RECOMMENDATIONS

Below are a few layout recommendations to utilize when designing a PCB for the DRV8301/2.

2

2

6/7

1

5

4

6/7

3

XX

1. The DRV8301/2 makes an electrical connection to GND through the PowerPAD. Always check to ensure that the PowerPAD has been properly soldered (See PowerPAD application report, SLMA002 ).

2. C1/C2/C8/C9, PVDD decoupling capacitors should be placed close to their corresponding pins with a low impedance path to device GND (PowerPAD).

3. C4, GVDD capacitor should be placed close its corresponding pin with a low impedance path to device GND

(PowerPAD).

4. C16/C17, AVDD & DVDD capacitors should be placed close to their corresponding pins with a low impedance path to the AGND pin. It’s preferable to make this connection on the same layer.

5. AGND should be tied to device GND (PowerPAD) through a low impedance trace/copper fill.

6. Add stitching vias to reduce the impedance of the GND path from the top to bottom side.

7. Try to clear the space around and underneath the DRV8301/2 to allow for better heat spreading from the

PowerPAD.

DESIGNATOR

C1

C2

C8

C9

C4

C16

C17

Table 10. Recommended Values

PIN

PVDD1 – pin 29

PVDD1 – pin 29

PVDD2 – pins 53 & 54

PVDD2 – pins 53 & 54

GVDD – pin 13

AVDD – pin 27

DVDD – pin 23

RECOMMENDED VALUE

2.2uF

0.1uF

2.2uF

0.1uF

2.2uF

1.0uF

1.0uF

DESCRIPTION

CAP CER 2.2UF 100V 10% X7R





CAP CER 1UF 25V 10% X7R

CAP CER 1UF 25V 10% X7R




PACKAGE OPTION ADDENDUM

www.ti.com

13-May-2013

PACKAGING INFORMATION

Orderable Device

DRV8301DCA

Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

HTSSOP DCA 56 35

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Lead/Ball Finish MSL Peak Temp

(3)

CU NIPDAU Level-3-260C-168 HR

Op Temp (°C)

-40 to 125

Top-Side Markings

(4)

DRV8301

DRV8301DCAR ACTIVE HTSSOP DCA 56 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 125

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

DRV8301

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Samples

Addendum-Page 1

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

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Texas Instruments DRV8301-RM48-KIT - RM48 Hercules Safety MCU Motor Control Kit DRV8301-RM48-KIT Dev Kit Data Sheet

Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator

FEATURES

APPLICATIONS

DESCRIPTION

DEVICE INFORMATION

PIN ASSIGNMENT

FUNCTION BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

THERMAL INFORMATION

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS (continued)

GATE TIMING AND PROTECTION CHARACTERISTICS

CURRENT SHUNT AMPLIFIER CHARACTERISTICS

BUCK CONVERTER CHARACTERISTICS

SPI CHARACTERISTICS (Slave Mode Only)

SPI CHARACTERISTICS (Slave Mode Only) (continued)

FUNCTIONAL DESCRIPTION

THREE-PHASE GATE DRIVER

CURRENT SHUNT AMPLIFIERS

BUCK CONVERTER

PROTECTION FEATURES

PIN CONTROL FUNCTIONS

STARTUP AND SHUTDOWN SEQUENCE CONTROL

SPI COMMUNICATION

PCB LAYOUT RECOMMENDATIONS

PACKAGE OPTION ADDENDUM

PACKAGING INFORMATION

Related manuals

Table of contents

Texas Instruments DRV8301-RM48-KIT - RM48 Hercules Safety MCU Motor Control Kit DRV8301-RM48-KIT Dev Kit Data Sheet

Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator

FEATURES

APPLICATIONS

DESCRIPTION

DEVICE INFORMATION

PIN ASSIGNMENT

FUNCTION BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

THERMAL INFORMATION

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS (continued)

GATE TIMING AND PROTECTION CHARACTERISTICS

CURRENT SHUNT AMPLIFIER CHARACTERISTICS

BUCK CONVERTER CHARACTERISTICS

SPI CHARACTERISTICS (Slave Mode Only)

SPI CHARACTERISTICS (Slave Mode Only) (continued)

FUNCTIONAL DESCRIPTION

THREE-PHASE GATE DRIVER

CURRENT SHUNT AMPLIFIERS

BUCK CONVERTER

PROTECTION FEATURES

PIN CONTROL FUNCTIONS

STARTUP AND SHUTDOWN SEQUENCE CONTROL

SPI COMMUNICATION

PCB LAYOUT RECOMMENDATIONS

PACKAGE OPTION ADDENDUM

PACKAGING INFORMATION

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Table of contents