RECOMMENDED OPERATING CONDITIONS. Texas Instruments DRV8301-RM48-KIT - RM48 Hercules Safety MCU Motor Control Kit DRV8301-RM48-KIT

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RECOMMENDED OPERATING CONDITIONS

SLOS719B – AUGUST 2011 – REVISED AUGUST 2013

R

DTC

I

FAULT

I

OCTW

V

REF f gate

PVDD1

PVDD2

C

PVDD1

C

PVDD2

C

AVDD

C

DVDD

C

GVDD

C

CP

C

BST

I

DIN_EN

I

DIN_DIS

C

DIN

C

O_OPA

I gate

T

A

DC supply voltage PVDD1 for normal operation

DC supply voltage PVDD2 for buck converter

Relative to PGND

External capacitance on PVDD1 pin (ceramic cap) 20% tolerance

External capacitance on PVDD2 pin (ceramic cap) 20% tolerance

External capacitance on AVDD pin (ceramic cap) 20% tolerance

External capacitance on DVDD pin (ceramic cap) 20% tolerance

External capacitance on GVDD pin (ceramic cap) 20% tolerance

Flying cap on charge pump pins (between CP1 and CP2) (ceramic cap) 20% tolerance

Bootstrap cap (ceramic cap)

Input current of digital pins when EN_GATE is high

Input current of digital pins when EN_GATE is low

Maximum capacitance on digital input pin

Maximum output capacitance on outputs of shunt amplifier

Dead time control resistor range. Time range is 50ns (-GND) to 500ns (150k Ω ) with a linear approximation.

FAULT pin sink current. Open-drain

OCTW pin sink current. Open-drain

V = 0.4 V

V = 0.4 V

External voltage reference voltage for current shunt amplifiers

Operating switching frequency of gate driver

Qg(TOT) = 25 nC or total 30 mA gate drive average current

Total average gate drive current

Ambient temperature

ELECTRICAL CHARACTERISTICS

PVDD = 6 V to 60 V, T

C

= 25°C, unless specified under test condition

PARAMETER TEST CONDITIONS

I

INPUT PINS: INH_X, INL_X, M_PWM (SCS), M_OC (SDI), GAIN(SDO), EN_GATE, DC_CAL

V

IH

V

IL

R

EN_GATE

High input threshold

Low input threshold

Internal pull down resistor for EN_GATE

R

INH_X

Internal pull down resistor for high side PWMs

(INH_A, INH_B, and INH_C)

EN_GATE high

R

INH_X

Internal pull down resistor for low side PWMs

(INL_A, INL_B, and INL_C)

R

SCS

Internal pull down resistor for SCS

R

SDI

R

DC_CAL

Internal pull down resistor for SDI

Internal pull down resistor for DC_CAL

R

SCLK

Internal pull down resistor for SCLK

OUTPUT PINS: FAULT AND OCTW

V

OL

Low output threshold

V

OH

High output threshold

EN_GATE high

EN_GATE high

EN_GATE high

EN_GATE high

EN_GATE high

I

O

= 2 mA

External 47 k Ω pull up resistor connected to 3-5.5 V

OH

Leakage Current on Open Drain Pins When

Logic High (FAULT and OCTW)

MIN TYP MAX UNITS

6 60 V

3.5

4.7

4.7

60 V

µF

µF

1

1

2.2

22 220

100

µF

µF

µF nF

100

1

10

20 nF

µA

µA pF pF

0

2

150

2

2

6

200 k Ω mA mA

V kHz

–40

30

125 mA

°C

MIN TYP MAX UNIT

2

2.4

100

100

100

100

100

100

100

0.8

V

V k Ω k Ω k Ω k Ω k Ω k Ω k Ω

0.4

V

V

1 µA

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SLOS719B – AUGUST 2011 – REVISED AUGUST 2013 www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

PVDD = 6 V to 60 V, T

C

= 25°C, unless specified under test condition

PARAMETER TEST CONDITIONS

GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C

V

GX_NORM

V

GX_MIN

Gate driver Vgs voltage

Gate driver Vgs voltage

I oso1

I osi1

I oso2

I osi2

Maximum source current setting 1, peak

Maximum sink current setting 1, peak

Source current setting 2, peak

Sink current setting 2, peak

I oso3

I osi3

Source current setting 3, peak

Sink current setting 3, peak

R gate_off

Gate output impedence during standby mode when EN_GATE low (pins GH_x, GL_x)

SUPPLY CURRENTS

I

PVDD1_STB

PVDD1 supply current, standby

PVDD = 8V–60V, I gate

C

CP

= 22nF

= 30mA,

PVDD = 8V–60V, I gate

C

CP

= 220nF

= 30mA,

PVDD = 6V–8V, I gate

C

CP

= 22nF

= 15mA,

PVDD = 6V–8V, I gate

C

CP

= 220nF

= 30mA,

Vgs of FET equals to 2 V. REG 0x02

Vgs of FET equals to 8 V. REG 0x02

Vgs of FET equals to 2 V. REG 0x02

Vgs of FET equals to 8 V. REG 0x02

Vgs of FET equals to 2 V. REG 0x02

Vgs of FET equals to 8 V. REG 0x02

I

PVDD1_OP

PVDD1 supply current, operating

I

PVDD1_HIZ

PVDD1 Supply current, HiZ

INTERNAL REGULATOR VOLTAGE

EN_GATE is low. PVDD1 = 8V.

EN_GATE is high, no load on gate drive output, switching at 10 kHz,

100 nC gate charge

EN_GATE is high, gate not switching

A

VDD

AVDD voltage

PVDD = 8V - 60V

PVDD = 6V - 60V

D

VDD

DVDD voltage

VOLTAGE PROTECTION

V

PVDD_UV

Under voltage protection limit, PVDD

PVDD falling

PVDD rising

GVDD falling V

GVDD_UV

V

GVDD_OV

Under voltage protection limit, GVDD

Over voltage protection limit, GVDD

CURRENT PROTECTION, (VDS SENSING)

V

DS_OC

Drain-source voltage protection limit

PVDD = 8V - 60V

PVDD = 6V - 8V

(1)

T oc

T

OC_PULSE

OC sensing response time

OCTW pin reporting pulse stretch length for OC event

(1) Reduced A

VDD voltage range results in limitations on settings for over current protection. See

Table 9

.

MIN TYP MAX UNIT

9.5

9.5

8.8

8.3

1.6

2

6

5.5

3

0.125

0.125

1.7

2.3

0.7

1

0.25

0.5

20

15

5

6.5

3.3

16

1.5

64

11.5

11.5

7

6

3.6

5.9

6

8

2.4

1.491

V

V

A

A

A

A

A

A

2.4

k Ω

50 µA mA

10 mA

V

V

V

V

V

V

µs

µs

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