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Intel ® Arria ® 10 Transceiver PHY
User Guide
Updated for Intel ® Quartus ® Prime Design Suite: 18.0
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UG-01143 | 2018.06.15
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Contents
Contents
1.1.3. Arria 10 GX and GT Device Package Details ................................................ 17
2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller........................... 40
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Arria ® 10 Transceiver PHY User Guide
Contents
2.5.1. Metaframe Format and Framing Layer Control Word.....................................95
2.5.2. Interlaken Configuration Clocking and Bonding............................................97
2.5.3. How to Implement Interlaken in Arria 10 Transceivers.................................103
2.5.5. Native PHY IP Parameter Settings for Interlaken........................................ 107
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2..................................... 112
2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC
2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core....................................... 164
2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core.......................................199
2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes................... 240
2.7.4. How to Implement PCI Express (PIPE) in Arria 10 Transceivers.................... 246
2.7.5. Native PHY IP Parameter Settings for PIPE ............................................... 248
2.7.7. ATX PLL IP Parameter Core Settings for PIPE..............................................255
2.7.11. Preset Mappings to TX De-emphasis........................................................267
2.7.12. How to Place Channels for PIPE Configurations......................................... 268
2.7.13. PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate............... 274
2.7.14. Using Transceiver Toolkit (TTK)/System Console/Reconfiguration
Interface to manually tune Arria 10 PCIe designs (Hard IP(HIP) and PIPE)
2.8.1. Transceiver Channel Datapath and Clocking for CPRI...................................280
2.8.4. How to Implement CPRI in Arria 10 Transceivers........................................ 284
2.8.5. Native PHY IP Parameter Settings for CPRI............................................... 285
2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of
2.9.3. Design Considerations for Implementing Arria 10 GT Channels..................... 319
2.9.4. How to Implement PCS Direct Transceiver Configuration Rule....................... 324
2.11. Implementing Protocols in Intel Arria 10 Transceivers Revision History.....................335
Intel ® Arria ® 10 Transceiver PHY User Guide
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Contents
3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs.................. 349
3.2.3. PLL Cascading as an Input Reference Clock Source..................................... 375
3.2.5. Global Clock or Core Clock as an Input Reference Clock...............................375
3.9.3. Selecting Channel Bonding Schemes.........................................................392
3.11.5. Timing Closure Recommendations...........................................................413
4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals....................... 432
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP............................... 435
4.4.2. Transceiver PHY Reset Controller Parameters............................................. 435
4.4.4. Transceiver PHY Reset Controller Resource Utilization.................................. 441
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Contents
6.2.1. Reading from the Reconfiguration Interface............................................... 505
6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow................. 530
6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow.. 531
6.12.3. CTLE Settings in Triggered Adaptation Mode.............................................531
6.12.4. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow...533
6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks...................... 542
6.16.1. Using PRBS Data Pattern Generator and Checker..................................... 550
6.16.2. Using Pseudo Random Pattern Mode........................................................559
Intel ® Arria ® 10 Transceiver PHY User Guide
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Contents
7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine .................567
7.4.1. Recalibration After Transceiver Reference Clock Frequency or Data Rate
8.1. Making Analog Parameter Settings using the Assignment Editor................................585
8.4.2. XCVR_A10_RX_TERM_SEL......................................................................589
8.4.3. XCVR_VCCR_VCCT_VOLTAGE - RX............................................................589
8.5.3. Decision Feedback Equalizer (DFE) Settings.............................................. 594
8.6.3. XCVR_A10_TX_COMPENSATION_EN........................................................ 597
8.6.4. XCVR_VCCR_VCCT_VOLTAGE - TX............................................................ 598
8.6.5. XCVR_A10_TX_SLEW_RATE_CTRL............................................................ 599
8.7.1. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T............................................600
8.7.2. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T............................................600
8.7.3. XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP........................................601
8.7.4. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP....................................... 601
8.7.5. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T......................... 602
8.7.6. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T......................... 602
8.7.7. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP..................... 603
8.7.8. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP.....................604
8.8.1. XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL.............................................604
8.9.1. XCVR_A10_REFCLK_TERM_TRISTATE.......................................................605
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Contents
8.9.2. XCVR_A10_TX_XTX_PATH_ANALOG_MODE................................................606
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1. Arria
®
10 Transceiver PHY Overview
This user guide provides details about the Arria ® 10 transceiver physical (PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP. It also provides protocol specific implementation details and describes features such as transceiver reset and dynamic reconfiguration of transceiver channels and PLLs.
Intel ® Arria 10 FPGAs offer up to 96 GX transceiver channels with integrated advanced high speed analog signal conditioning and clock data recovery techniques for chip-tochip, chip-to-module, and backplane applications.
The Arria 10 GX and SX devices have GX transceiver channels that can support data rates up to 17.4 Gbps for chip-to-chip applications and 12.5 Gbps for backplane applications.
The Arria 10 GT device has up to 6 GT transceiver channels, that can support data rates up to 25.8 Gbps for short reach chip-to-chip and chip-to-module applications.
Additionally, the GT devices have GX transceiver channels that can support data rates up to 17.4 Gbps for chip-to-chip and 12.5 Gbps for backplane applications. If all 6 GT channels are used in GT mode, then the GT device also has up to 54 GX transceiver channels.
The Arria 10 transceivers support reduced power modes with data rates up to 11.3
Gbps (chip-to-chip) for critical power sensitive designs. In GX devices that have transceivers on both sides of the device, each side can be operated independently in standard and reduced power modes. You can achieve transmit and receive data rates below 1.0 Gbps with oversampling.
Table 1.
SX (
GX (
GT (
Data Rates Supported by GX Transceiver Channel Type
Device Variant Standard Power Mode
Chip-to-Chip
1.0 Gbps to 17.4 Gbps
1.0 Gbps to 17.4 Gbps
1.0 Gbps to 17.4 Gbps
Backplane
1.0 Gbps to 12.5 Gbps
1.0 Gbps to 12.5 Gbps
1.0 Gbps to 12.5 Gbps
Reduced Power Mode
Chip-to-Chip
1.0 Gbps to 11.3 Gbps
1.0 Gbps to 11.3 Gbps
1.0 Gbps to 11.3 Gbps
(1) To operate GX transceiver channels at designated data rates in standard and reduced power modes, apply the corresponding core and periphery power supplies. Refer to the Arria 10
Device Datasheet for more details.
(2) The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
(3) For SX and GX device variants, the maximum transceiver data rates are specified for the fastest (–1) transceiver speed grade.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
1. Arria ® 10 Transceiver PHY Overview
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Table 2.
Device Variant
GT
Data Rates Supported by GT Transceiver Channel Type
Chip-to-Chip
1.0 Gbps to 25.8 Gbps
Data Rates (5),
Backplane
1.0 Gbps to 12.5 Gbps
Note: The device data rates depend on the device speed grade. Refer to IntelArria 10 Device
Datasheet for details on available speed grades and supported data rates.
Related Information
• IntelArria 10 Device Datasheet
• IntelArria 10 Device Overview
1.1. Device Transceiver Layout
Figure 1.
Arria 10 FPGA Architecture Block Diagram
The transceiver channels are placed on the left side periphery in most Arria 10 devices. For larger Arria 10 devices, additional transceiver channels are placed on the right side periphery.
(4) For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade.
(5) Because the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation.
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1.1.1. Arria 10 GX Device Transceiver Layout
The largest Arria 10 GX device includes 96 transceiver channels. A column array of eight transceiver banks on the left and the right side periphery of the device is shown in the following figure. Each transceiver bank has six transceiver channels. Some devices have transceiver banks with only three channels. The transceiver banks with only three channels are the uppermost transceiver banks. Arria 10 devices also include
PCI Express* Hard IP blocks.
The figures below illustrate different transceiver bank layouts for Arria 10 GX device variants.
For more information about PCIe* Hard IP transceiver placements, refer to Related
Information at the end of this section.
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Figure 2.
Arria 10 GX Devices with 96 Transceiver Channels and Four PCIe Hard IP
Blocks
GXBL1J
GXBL1I
Transceiver
Bank
Transceiver
Bank
GX 115 UF45
GX 090 UF45 Transceiver
Bank
Transceiver
Bank
GXBR4J
GXBR4I
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
GXBR4H GXBL1H
GXBL1G
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
GXBL1F
GXBL1E
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
Transceiver
Bank
GXBL1D
GXBL1C
(1)
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Notes:
(1) Nomenclature of left column bottom transceiver banks always ends with “C”.
(2) Nomenclature of right column bottom transceiver banks may end with “C”, “D”, or “E”.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 96 transceiver channels and four PCIe Hard IP blocks.
Transceiver
Bank
Transceiver
Bank
GXBR4G
GXBR4F
GXBR4E
GXBR4D
GXBR4C
(2)
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Figure 3.
Arria 10 GX Devices with 72 and 48 Transceiver Channels and Four PCIe Hard
IP Blocks.
GXBL1H
Transceiver
Bank
GX 115 SF45
GX 090 SF45
Transceiver
Bank
GXBR4H
GXBL1G
Transceiver
Bank
Transceiver
Bank
GXBR4G
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
GXBL1F
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
GXBR4F
GXBL1E
Transceiver
Bank GX 115 NF45
GX 090 NF45
Transceiver
Bank
GXBR4E
GXBL1D
GXBL1C
(1)
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
Transceiver
Bank
GXBR4D
GXBR4C
(2)
Notes:
(1) Nomenclature of left column bottom transceiver banks always ends with “C”.
(2) Nomenclature of right column bottom transceiver banks may end with “C”, “D”, or “E”.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 72 transceiver channels and four PCIe Hard IP blocks.
Arria 10 GX device with 48 transceiver channels and four PCIe Hard IP blocks.
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Figure 4.
Arria 10 GX Devices with 66 Transceiver Channels and Three PCIe Hard IP
Blocks
GXBL1H Transceiver
Bank
GX 115 RF40
GX 090 RF40 Transceiver
Bank
GXBR4J
GXBL1G
GXBL1F
GXBL1E
Transceiver
Bank
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
GXBR4I
GXBR4H
GXBR4G
Transceiver
Bank
Transceiver
Bank
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
GXBR4F GXBL1D
GXBL1C
(1)
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
Transceiver
Bank
Notes:
(1) Nomenclature of left column bottom transceiver banks always ends with “C”.
(2) Nomenclature of right column bottom transceiver banks may end with “C”, “D”, or “E”.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 66 transceiver channels and three PCIe Hard IP blocks.
GXBR4E
(2)
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Figure 5.
Arria 10 GX Devices with 48, 36, and 24 Transceiver Channels and Two PCIe
Hard IP Blocks
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
GX 115 NF40
GX 090 NF40
GX 066 NF40
GX 057 NF40
Transceiver
Bank
GX 066 KF40
GX 057 KF40
GX 066 KF35
GX 057 KF35
GX 048 KF35
Transceiver
Bank
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
GX 115 HF34
GX 090 HF34
GX 066 HF34
GX 057 HF34
GX 048 HF34
GX 032 HF35
GX 032 HF34
GX 027 HF35
GX 027 HF34
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Transceiver
Bank
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 48 transceiver channels and two PCIe Hard IP blocks.
Arria 10 GX device with 36 transceiver channels and two PCIe Hard IP blocks.
Arria 10 GX device with 24 transceiver channels and two PCIe Hard IP blocks.
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Figure 6.
Arria 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP
Block
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
GXBL1D
GXBL1C
Transceiver
Bank
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
GX 048 EF29
GX 032 EF29
GX 027 EF29
GX 032 EF27
GX 027 EF27
GX 022 EF29
GX 022 EF27
GX 016 EF29
GX 016 EF27
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 12 transceiver channels and one PCIe Hard IP block.
Figure 7.
Arria 10 GX Devices with 6 Transceiver Channels and One PCIe Hard IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
Transceiver
Bank
PCIe Hard IP (1)
GX 022 CU19
GX 016 CU19
Note:
(1) Only CH5 and CH4 support PCIe Hard IP block with CvP capabilities.
(2) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP block with Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with six transceiver channels and one PCIe Hard IP block.
Related Information
• IntelArria 10 Avalon-ST Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
1.1.2. Arria 10 GT Device Transceiver Layout
The Arria 10 GT device has 72 transceiver channels and four PCI Express Hard IP blocks. A total of 6 GT transceiver channels that can support data rates up to 25.8
Gbps.
In the GT device, transceiver banks GXBL1E, GXBL1G, and GXBL1H each contain two
GT transceiver channels. Transceiver banks GXBL1E and GXBL1H channels 3 and 4 can be used as GT or GX transceiver channel. Transceiver bank GXBL1G channels 0 and 1 can be used as GT or GX transceiver channels. When none of the GT capable transceiver channels are used as GT transceiver channels, the entire transceiver
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Figure 8.
channels in the bank can be reconfigured as GX transceiver channels. However, when any of the GT capable transceiver channels in transceiver banks GXBL1E, GXBL1G, and GXBL1H is enabled as a GT transceiver channel, the remaining channels in the transceiver bank cannot be used with the exception of the other GT capable channel in the transceiver bank.
If you're using GT transceivers in bank GXBL1E, then the adjacent PCIe Hard IP block cannot be used.
Arria 10 GT Device with 72 Transceiver Channels and Four PCIe Hard IP
Blocks
GXBL1H
Transceiver
Bank
GT 115 SF45
GT 090 SF45
Transceiver
Bank
GXBR4H
CH5
CH4
CH3
CH2
CH1
CH0
GX or Restricted
GT or GX
GT or GX
GX or Restricted
GX or Restricted
GX or Restricted
GT Channels
Capable of Short
Reach 25.8 Gbps
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
GX or Restricted
GX or Restricted
GX or Restricted
GX or Restricted
GT or GX
GT or GX
GXBL1G
GXBL1F
Transceiver
Bank
Transceiver
Bank
GXBR4G
GXBR4F
GXBL1E
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
Transceiver
Bank
GXBR4E
GXBL1D
GXBL1C
(1)
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Transceiver
Bank
Notes:
(1) Nomenclature of left column bottom transceiver banks always end with “C”.
(2) Nomenclature of right column bottom transceiver banks may end with “C”, “D”, or “E”.
(3) If a GT channel is used in transceiver bank GXBL1E, the PCIe Hard IP adjacent to GXBL1F and GXBL1E cannot be used.
Legend:
GT transceiver channels (channel 0, 1, 3, and 4).
GX transceiver channels (channel 2 and 5) with usage restrictions.
GX transceiver channels without usage restrictions.
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
Transceiver
Bank
GXBR4D
GXBR4C
(2)
The GT device has 72 transceiver channels, which include 6 GT transceiver channels supporting data rates greater than 17.4 Gbps. If all six GT transceiver channels are used in GT mode, there are 54 GX transceiver channels that can drive chip to chip data rates up to 17.4 Gbps and backplanes at data rates up to 12.5 Gbps and 12 GX channels that are unusable.
In the GT device, the GX transceiver channels on the entire right side can be used in standard or reduced power mode. In GT devices where none of the GT channels are used to operate in GT data rates above 17.4 Gbps, the transceiver channels on either the entire right side or entire left side can be used as GX channels in standard or reduced power mode.
Related Information
• IntelArria 10 Avalon-ST Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
Intel ®
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• IntelArria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
1.1.3. Arria 10 GX and GT Device Package Details
The following tables list package sizes, available transceiver channels, and PCI Express
Hard IP blocks for Arria 10 GX and GT devices.
Table 3.
Device
GX 016
GX 022
GX 027
GX 032
GX 048
GX 057
GX 066
GX 090
GX 115
•
•
•
•
•
Package Details for GX Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device
Package U19: 19mm x 19mm package; 484 pins.
Package F27: 27mm x 27mm package; 672 pins.
Package F29: 29mm x 29mm package; 780 pins.
Packages F34 and F35: 35 mm x 35 mm package size; 1152 pins.
Package F40: 40 mm x 40 mm package size; 1517 pins. K = 36 transceiver channels, N = 48 transceiver channels.
U19 K F40 N F40
6, 1
6, 1
F27
12, 1
12, 1
F29 F34 F35
Transceiver Count, PCIe Hard IP Block Count
12, 1
12, 1
12, 1
12, 1
12, 1
12, 1
12, 1
24, 2
24, 2
24, 2
24, 2
24, 2
24, 2
24, 2
24, 2
24, 2
36, 2
36, 2
36, 2
36, 2
36, 2
48, 2
48, 2
48, 2
48, 2
Table 4.
GX 090
GX 115
GT 090
GT 115
Device
•
•
Package Details for GX and GT Devices with Transceivers and Hard IP Blocks
Located on the Left and Right Side Periphery of the Device
•
Package F40: 40 mm x 40 mm package size; 1517 pins. R = 66 transceiver channels.
Package F45: 45mm x 45mm package size; 1932 pins. N = 48 transceiver channels, S = 72 transceiver channels, U = 96 transceiver channels.
If you're using GT transceivers in bank GXBL1E, the nth adjacent PCIe Hard IP block cannot be used.
R F40 U F45
66, 3
66, 3
N F45 S F45
Transceiver Count, PCIe Hard IP Block Count
48, 4
48, 4
72, 4
72, 4
72, 4
72, 4
96, 4
96, 4
1.1.4. Arria 10 SX Device Transceiver Layout
The largest SX device includes 48 transceiver channels. All SX devices include GX transceiver channel type. The transceiver banks in SX devices are located on the left side periphery of the device.
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Figure 9.
For more information about PCIe Hard IP transceiver placements, refer to Related
Information at the end of this section.
Arria 10 SX Device with 48, 36, and 24 Transceiver Channels and Two Hard IP
Blocks
GXBL1J Transceiver
Bank
SX 066 NF40
SX 057 NF40
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
GXBL1I
GXBL1H
Transceiver
Bank
Transceiver
Bank
SX 066 KF40
SX 066 KF35
SX 057 KF40
SX 057 KF35
SX 048 KF35
GXBL1G Transceiver
Bank
GXBL1F
GXBL1E
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
SX 066 HF34
SX 057 HF34
SX 048 HF34
SX 032 HF35
SX 032 HF34
SX 027 HF35
SX 027 HF34
GXBL1D
GXBL1C
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Transceiver
Bank
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1- Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 SX device with 48 transceiver channels and two PCIe Hard IP blocks.
Arria 10 SX device with 36 transceiver channels and two PCIe Hard IP blocks.
Arria 10 SX device with 24 transceiver channels and two PCIe Hard IP blocks.
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Figure 10.
Arria 10 SX Device with 12 Transceiver Channels and One Hard IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
SX 048 EF29
SX 032 EF29
SX 032 EF27
SX 027 EF29
SX 027 EF27
SX 022 EF29
SX 022 EF27
SX 016 EF29
SX 016 EF27
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Arria 10 SX device with 12 transceiver channels and one Hard IP block.
Figure 11.
Arria 10 SX Device with Six Transceiver Channels and One Hard IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
GXBL1C Transceiver
Bank
PCIe Hard IP (1)
SX 022 CU19
SX 016 CU19
Note:
(1) Only CH5 and CH4 support PCIe Hard IP block with Configuration via Protocol (CvP) capabilities.
(2) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP block with Configuration via Protocol (CvP) capabilities.
Arria 10 SX device with six transceiver channels and one PCIe Hard IP block.
Related Information
• IntelArria 10 Avalon-ST Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
1.1.5. Arria 10 SX Device Package Details
The following tables list package sizes, available transceiver channels, and PCI Express
Hard IP blocks for Arria 10 SX devices.
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Table 5.
Device
SX 016
SX 022
SX 027
SX 032
SX 048
SX 057
SX 066
•
•
•
•
•
Package Details for SX Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device
Package U19: 19mm x 19mm package; 484 pins.
Package F27: 27mm x 27mm package; 672 pins.
Package F29: 29mm x 29mm package; 780 pins.
Packages F34 and F35: 35 mm x 35 mm package size; 1152 pins.
Package F40: 40 mm x 40 mm package size; 1517 pins. K = 36 transceiver channels, N = 48 transceiver channels.
U19 F27 K F40 N F40
6, 1
6, 1
12, 1
12, 1
12, 1
12, 1
F29 F34 F35
Transceiver Count, PCIe Hard IP Block Count
12, 1
12, 1
12, 1
12, 1
12, 1
24, 2
24, 2
24, 2
24, 2
24, 2
24, 2
24, 2
36, 2
36, 2
36, 2
36, 2
36, 2
48, 2
48, 2
1.2. Transceiver PHY Architecture Overview
A link is defined as a single entity communication port. A link can have one or more transceiver channels. A transceiver channel is synonymous with a transceiver lane.
For example, a 10GBASE-R link has one transceiver channel or lane with a data rate of
10.3125 Gbps. A 40GBASE-R link has four transceiver channels. Each transceiver channel operates at a lane data rate of 10.3125 Gbps. Four transceiver channels give a total collective link bandwidth of 41.25 Gbps (40 Gbps before and after 64B/66B
Physical Coding Sublayer (PCS) encoding and decoding).
1.2.1. Transceiver Bank Architecture
The transceiver bank is the fundamental unit that contains all the functional blocks related to the device's high speed serial transceivers.
Each transceiver bank includes six transceiver channels in all devices except for the devices with 66 transceiver channels. Devices with 66 transceiver channels have both six channel and three channel transceiver banks. The uppermost transceiver bank on the left and the right side of these devices is a three channel transceiver bank. All other devices contain only six channel transceiver banks.
The figures below show the transceiver bank architecture with the phase locked loop
(PLL) and clock generation block (CGB) resources available in each bank.
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Figure 12.
Three-Channel GX Transceiver Bank Architecture
Three-Channel GX Transceiver Bank
PMA
Channel PLL
(CDR Only)
CH2
PCS
Local CGB2
Clock
Distribution
Network fPLL0
PMA
Channel PLL
(CMU/CDR)
CH1
PCS
Local CGB1
Master
CGB0
PMA
Channel PLL
(CDR Only)
CH0
PCS
Local CGB0 ATX
PLL0
Note:
FPGA Core
Fabric
This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.
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Figure 13.
Six-Channel GX Transceiver Bank Architecture
Six-Channel GX Transceiver Bank
Clock
Distribution
Network
PMA
Channel PLL
(CDR Only)
CH5
PCS
Local CGB5 fPLL1
PMA
Channel PLL
(CMU/CDR)
CH4
PCS
Local CGB4
Master
CGB1
PMA
Channel PLL
(CDR Only)
CH3
PCS
Local CGB3
ATX
PLL1
PMA
Channel PLL
(CDR Only)
CH2
PCS
Local CGB2 fPLL0
PMA
Channel PLL
(CMU/CDR)
CH1
PCS
Local CGB1
Master
CGB0
PMA
Channel PLL
(CDR Only)
CH0
PCS
Local CGB0
ATX
PLL0
FPGA Core
Fabric
Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.
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Figure 14.
GT Transceiver Bank Architecture
In the GT device, the transceiver banks GXBL1E, GXBL1G, and GXBL1H include GT channels.
Six-Channel GT Transceiver Bank GXBL1G
Clock
Distribution
Network
PMA
Channel PLL
(CDR Only)
CH5
PCS
Local CGB5 fPLL1
PMA
Channel PLL
(CMU/CDR)
CH4
PCS
Local CGB4
Master
CGB1
PMA
Channel PLL
(CDR Only)
CH3
PCS
Local CGB3
ATX
PLL1
FPGA Core
Fabric
PMA
Channel PLL
(CDR Only)
CH2
PCS
Local CGB2 fPLL0
PMA
Channel PLL
(CMU/CDR)
CH1
PCS
Local CGB1
Master
CGB0
PMA
Channel PLL
(CDR Only)
CH0
PCS
Local CGB0
ATX
PLL0
Note:
Legend
GT/GX Channel GX Channel
This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.
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Figure 15.
GT Transceiver Bank Architecture for Banks GXBL1E and GXBL1H
Six-Channel GT
Transceiver Banks GXBL1E and GXBL1H
PMA
Channel PLL
(CDR Only)
CH5
PCS
Local CGB5
Clock
Distribution
Network fPLL1
PMA
Channel PLL
(CMU/CDR)
CH4
PCS
Local CGB4
Master
CGB1
PMA
Channel PLL
(CDR Only)
CH3
PCS
Local CGB3
ATX
PLL1
FPGA Core
Fabric
PMA
Channel PLL
(CDR Only)
CH2
PCS
Local CGB2 fPLL0
PMA
Channel PLL
(CMU/CDR)
CH1
PCS
Local CGB1
Master
CGB0
PMA
Channel PLL
(CDR Only)
CH0
PCS
Local CGB0
ATX
PLL0
Note:
Legend
GT/GX Channel GX Channel
This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.
The transceiver channels perform all the required PHY layer functions between the
FPGA fabric and the physical medium. The high speed clock required by the transceiver channels is generated by the transceiver PLLs. The master and local clock generation blocks (CGBs) provide the necessary high speed serial and low speed parallel clocks to drive the non-bonded and bonded channels in the transceiver bank.
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Related Information
•
PLLs and Clock Networks on page 347
• Transceiver Basics
Online training course for transceivers.
1.2.2. PHY Layer Transceiver Components
Transceivers in Arria 10 devices support both Physical Medium Attachment (PMA) and
Physical Coding Sublayer (PCS) functions at the physical (PHY) layer.
A PMA is the transceiver's electrical interface to the physical medium. The transceiver
PMA consists of standard blocks such as:
• serializer/deserializer (SERDES)
• clock and data recovery PLL
• analog front end transmit drivers
• analog front end receive buffers
The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS blocks are fed by multiple clock networks driven by high performance PLLs. In PCS
Direct configuration, the data flow is through the PCS block, but all the internal PCS blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA fabric.
1.2.2.1. The GX Transceiver Channel
Figure 16.
GX Transceiver Channel in Full Duplex Mode.
Transmitter PMA
Serializer
(1)
KR FEC
Transmitter PCS
Standard PCS
PCIe Gen3 PCS
Enhanced PCS
PCS Direct
FPGA Fabric
(1) Soft PIPE
(Optional)
Hard IP
(Optional)
CDR
Receiver PMA
Deserializer
(1)
KR FEC
Receiver PCS
Standard PCS
PCIe Gen3 PCS
Enhanced PCS
PCS Direct
(1)
Notes:
(1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.
Arria 10 GX transceiver channels have three types of PCS blocks that together support continuous data rates between 1.0 Gbps and 17.4 Gbps.
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Table 6.
Standard PCS
Enhanced PCS
PCIe Gen3 PCS
PCS Types Supported by GX Transceiver Channels
PCS Type Data Rate
1.0 Gbps to 10.81344 Gbps
1.0 Gbps (6) to 17.4 Gbps
8 Gbps
Note: 1. The GX channel can also operate in PCS Direct configuration for data rates from
1.0 Gbps to 17.4 Gbps. To operate GX transceiver channels in PCS Direct designated data rates, refer to the IntelArria 10 Device Datasheet for more details on power supply, speed grade, and transceiver configurations requirement.
2. The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
3. To operate GX transceiver channels with the PCS at designated data rates, refer to the IntelArria 10 Device Datasheet for more details on power supply, speed grade, and transceiver configurations requirement.
Related Information
IntelArria 10 Device Datasheet
1.2.2.2. The GT Transceiver Channel
The GT transceiver channels are used for supporting data rates from 17.4 Gbps to
25.8 Gbps. The PCS Direct datapath that bypasses all PCS blocks is the primary configuration used to support GT data rates from 17.4 Gbps to 25.8 Gbps.
Alternatively, the Enhanced PCS in Basic low latency configuration can also be used to support GT data rates from 17.4 Gbps to 25.8 Gbps. The GT transceiver channels can also be configured as GX transceiver channels. When they are configured as GX transceiver channels, the Standard PCS, Enhanced PCS, and PCIe Gen3 PCS are available and they support data rates from 1.0 Gbps to 17.4 Gbps.
(6) Applies when operating in reduced power modes. For standard power modes, the Enhanced
PCS minimum data rate is 1600 Mbps.
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Figure 17.
GT Transceiver Channel in Full Duplex Mode Operating Between 17.4 Gbps and 25.8 Gbps
Transmitter PMA
FPGA Fabric
Serializer
(2)
Transmitter PCS
Standard PCS
KR FEC
PCIe Gen3 PCS
Enhanced PCS
(3)
(3)
(1)
(2)
PCS Direct
CDR
Receiver PMA
Deserializer
(2)
Receiver PCS
Standard PCS
KR FEC
PCIe Gen3 PCS
Enhanced PCS
PCS Direct
(3)
(3)
(1)
(2)
Notes:
(1) The Enhanced PCS must be configured in Basic low latency mode to support data rate range from 17.4 Gbps to 25.8 Gbps.
(2) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.
(3) The Standard PCS and PCIe Gen3 PCS blocks are available when the GT channel is configured as a GX transceiver channel.
Table 7.
GT
GX
PCS Types and Data Rates Supported by GT Channel Configurations
GT Channel Configuration
Standard PCS
Enhanced PCS
PCS Type
PCIe Gen3 PCS
Standard PCS
Enhanced PCS
PCIe Gen3 PCS
Data Rates Supported
Not available for GT configuration
17.4 Gbps to 25.8 Gbps (7)
Not available for GT configuration
1.0 Gbps to 12 Gbps
1.0 Gbps (8) to 17.4 Gbps
8 Gbps
Note: 1. The GT channels can also operate in PCS Direct configuration for data rates from
1.0 Gbps to 25.8 Gbps. The PCS Direct datapath that bypasses all PCS blocks is the primary configuration used to support GT data rates from 17.4 Gbps to 25.8
Gbps. To operate GX and GT transceiver channels in PCS Direct designated data rates, refer to the IntelArria 10 Device Datasheet for more details on power supply, speed grade, and transceiver configurations requirement.
2. The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
3. To operate GX and GT transceiver channels with the PCS at designated data rates, refer to the IntelArria 10 Device Datasheet for more details on power supply, speed grade, and transceiver configurations requirement.
(7) The Enhanced PCS must be configured in Basic low latency mode to support data rate range from 17.4 Gbps to 25.8 Gbps.
(8) Applies when operating in reduced power modes. For standard power modes, the Enhanced
PCS minimum data rate is 1600 Mbps.
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Related Information
IntelArria 10 Device Datasheet
1.2.3. Transceiver Phase-Locked Loops
Each transceiver channel in Arria 10 devices has direct access to three types of high performance PLLs:
• Advanced Transmit (ATX) PLL
• Fractional PLL (fPLL)
• Channel PLL / Clock Multiplier Unit (CMU) PLL.
These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the transceiver channels.
Related Information
For more information on transceiver PLLs in Arria 10 devices.
1.2.3.1. Advanced Transmit (ATX) PLL
An advanced transmit (ATX ) PLL is a high performance PLL. It supports both integer frequency synthesis and coarse resolution fractional frequency synthesis. The ATX PLL is the transceiver channel’s primary transmit PLL. It can operate over the full range of supported data rates required for high data rate applications.
Related Information
•
on page 350
For more information on ATX PLL.
•
on page 354
For details on implementing the ATX PLL IP.
1.2.3.2. Fractional PLL (fPLL)
A fractional PLL (fPLL) is an alternate transmit PLL used for generating lower clock frequencies for 12.5 Gbps and lower data rate applications. fPLLs support both integer frequency synthesis and fine resolution fractional frequency synthesis. Unlike the ATX
PLL, the fPLL can also be used to synthesize frequencies that can drive the core through the FPGA fabric clock networks.
Related Information
•
on page 359
For more information on fPLL.
•
on page 362
For details on implementing the fPLL IP.
1.2.3.3. Channel PLL (CMU/CDR PLL)
A channel PLL resides locally within each transceiver channel. Its primary function is clock and data recovery in the transceiver channel when the PLL is used in clock data recovery (CDR) mode. The channel PLLs of channel 1 and 4 can be used as transmit
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PLLs when configured in clock multiplier unit (CMU) mode. The channel PLLs of channel 0, 2, 3, and 5 cannot be configured in CMU mode and therefore cannot be used as transmit PLLs.
Related Information
•
on page 368
For more information on CMU PLL.
•
For information on implementing CMU PLL IP.
1.2.4. Clock Generation Block (CGB)
In Arria 10 devices, there are two types of clock generation blocks (CGBs):
• Master CGB
• Local CGB
Transceiver banks with six transceiver channels have two master CGBs. Master CGB1 is located at the top of the transceiver bank and master CGB0 is located at the bottom of the transceiver bank. Transceiver banks with three channels have only one master
CGB. The master CGB divides and distributes bonded clocks to a bonded channel group. It also distributes non-bonded clocks to non-bonded channels across the x6/xN clock network.
Each transceiver channel has a local CGB. The local CGB is used for dividing and distributing non-bonded clocks to its own PCS and PMA blocks.
Related Information
on page 383
For more information on clock generation block.
1.3. Calibration
Arria 10 FPGAs contain a dedicated calibration engine to compensate for process variations. The calibration engine calibrates the analog portion of the transceiver to allow both the transmitter and receiver to operate at optimum performance.
The
CLKUSR
pin clocks the calibration engine. All transceiver reference clocks and the
CLKUSR
clock must be free running and stable at the start of FPGA configuration to successfully complete the calibration process and for optimal transceiver performance.
Note: For more information about
CLKUSR
electrical characteristics, refer to IntelArria 10
Device Datasheet. The
CLKUSR
can also be used as an FPGA configuration clock. For information about configuration requirements for the
CLKUSR
pin, refer to the
Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices chapter in the Arria 10 Core Fabric and General-Purpose I/O Handbook. For more information about calibration, refer to the Calibration chapter. For more information about
CLKUSR
pin requirements, refer to the IntelArria 10 GX, GT, and SX Device
Family Pin Connection Guidelines.
Related Information
• IntelArria 10 Device Datasheet
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• Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices
• IntelArria 10 GX, GT, and SX Device Family Pin Connection Guidelines
1.4. Intel Arria 10 Transceiver PHY Overview Revision History
Changes Document
Version
2018.06.15
2016.05.02
2016.02.11
2015.11.02
2015.05.11
2014.12.15
2014.08.15
Made the following changes:
• Changed the data rate range for the Standard PCS in the "PCS types Supported by GX Transceiver
Channels" table.
Made the following changes:
• Maximum backplane rate updated from 16.0 Gbps to 12.5 Gbps.
• No Backplane support when VCCR/T_GXB=0.95 (Low Power Mode).
• Added a footnote to refer to Arria 10 Device datasheet for PCS Types Supported by GX and GT
Transceiver Channels.
Made the following changes:
• Changed the "Arria 10 GT Devices with 72 Transceiver Channels and Four PCIe Hard IP Blocks" figure.
• Changed the "GT Transceiver Bank Architecture" figure.
• Added the "GT Transceiver Bank Architecture for Banks GXBL1E and GXBL1H" figure.
Made the following changes:
• Changed the minimum data rate from 611 Mbps to 1.0 Gbps.
• Changed the location of a PCIe Hard IP block in the "Arria 10 GX Devices with 66 Transceiver
Channels and Three PCIe Hard IP Blocks" figure.
Changed lower limit of supported data rate from 1.0 Gbps to 611 Mbps
Made the following changes:
• Added statement that a 125-Mbps data rate is possible with oversampling in the "Arria 10
Transceiver PHY Overview" section.
• Changed the data rate ranges for Standard PCS and Enhanced PCS in the "PCS Types Supported by
GX Transceiver Channels" table.
• Changed the note in "The GX Transceiver Channel" section.
• Changed the data rate ranges for Standard PCS and Enhanced PCS in the "PCS Types and Data
Rates Supported by GT Channel Configurations" table.
• Added a legend entry to the "Arria 10 GT Devices with 96 Transceiver Channels and Four PCIe Hard
IP Blocks" figure.
• Added a legend entry to the "Arria 10 GT Devices with 72 Transceiver Channels and Four PCIe Hard
IP Blocks" figure.
• Added a legend entry to the "Arria 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard
IP Blocks" figure.
• Changed the note to the "PCS Types and Data Rates Supported by GT Channel Configurations" table.
• Changed the Data Rates Supported for GT channel Standard PCS and PCIe Gen3 PCS types in the
"PCS Types and Data Rates Supported by GT Channel Configurations" table.
• Added a related link to the Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines in the
"Calibration" section.
Made the following changes:
• Changed the maximum data rate for GT channels to 25.8 Gbps.
• Changed minimum data rate supported by GT transceiver channels to 1 Gbps from 611 Mbps.
• Changed the figure "Arria 10 GX Devices with Six Transceiver Channels and One PCIe Hard IP
Block" to adda a clarification about PCIe Hard IP block.
• Updated the legend for all figures in "Arria 10 GT Device Transceiver Layout" section.
• Changed the device package names in Table1-3 and Table 1-4 in "Arria 10 GX and GT Device
Package Details Section." continued...
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Document
Version
2013.12.02
Changes
• Updated figure "Arria 10 SX Device with 48,36, and 24 Transceiver Channels and Two PCIe Hard IP
Blocks.
• Updated figure "Arria 10 SX Devices with Six Transceiver Channels and One PCIe Hard IP Block" to add a clarification about PCIe Hard IP.
• Updated the device package names in Table 1-5 in "Arria 10 SX Device Package Details" section.
• Removed all references of the note about PCS-Direct support available in future release.
Initial release.
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2. Implementing Protocols in Arria 10 Transceivers
2.1. Transceiver Design IP Blocks
Figure 18.
Arria 10 Transceiver Design Fundamental Building Blocks
Reset controller is used for resetting the
transceiver channels.
Transceiver PHY
Reset Controller (2)
Analog and Digital
Reset Bus
Reset Ports
Transceiver PLL IP core provides a clock source to clock networks that drive the transceiver channels. In Arria 10 devices, PLL IP Core is separate from the transceiver PHY IP core.
Avalon master allows access to Avalon-MM reconfiguration registers via the Avalon
Memory Mapped interface. It enables PCS,
PMA , and PLL reconfiguration. To access the reconfiguration registers, implement an
Avalon master in the FPGA fabric. This faciliates reconfiguration by performing reads and writes through the Avalon-MM interface.
This block can be either a MAC IP core, or a frame generator / analyzer or a data generator / analyzer.
Transceiver
PLL IP Core
Master/Local
Clock
Generation
Block
Avalon-MM Master
MAC IP Core /
Data Generator /
Data Analyzer
Non-Bonded and
Bonded Clocks
Avalon-MM
Interface
Transceiver PHY IP Core
(1)
Reconfiguration
Registers
Parallel Data Bus
Note:
(1) The Transceiver PHY IP core can be one of the supported PHY IP Cores ( For example: Native PHY IP Core, XAUI PHY IP Core, and so on)
(2) You can either design your own reset controller or use the Transceiver PHY Reset Controller.
Legend:
Intel generated IP block
User created IP block
Transceiver PHY IP core controls the PCS and
PMA configurations and transceiver channels functions for all communication protocols.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
2. Implementing Protocols in Arria 10 Transceivers
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2.2. Transceiver Design Flow
Figure 19.
Transceiver Design Flow
Note: The design examples on the Intel FPGA wiki page provide useful guidance for developing your own design.
However, the content on the Intel FPGA wiki page is not guaranteed by Intel.
Select PHY IP Core
Configure the PHY IP Core
Generate the Transceiver PHY Reset Controller or create your own User-Coded Reset Controller
Generate PHY IP Core Select PLL IP Core
Configure the PLL IP Core
Generate PLL IP Core
Create reconfiguration logic
(if needed)
Connect PHY IP Core to PLL IP Core, Reset Controller, and
connect reconfiguration logic via Avalon-MM interface
Connect Transceiver Datapath to MAC IP Core or to a Data Generator / Analyzer
Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File
Compile Design
Verify Design Functionality
Related Information http://www.alterawiki.com
2.2.1. Select and Instantiate the PHY IP Core
Select the appropriate PHY IP core to implement your protocol.
Refer to the Arria 10 Transceiver Protocols and PHY IP Support section to decide which
PHY IP to select to implement your protocol.
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You can create your Quartus ® Prime project first, and then instantiate the various IPs required for your design. In this case, specify the location to save your IP HDL files.
The current version of the PHY IP does not have the option to set the speed grade.
Specify the device family and speed grade when you create the Quartus Prime project.
You can also instantiate the PHY IP directly to evaluate the various features.
To instantiate a PHY IP:
1. Open the Quartus Prime software.
2. Click Tools ➤ IP Catalog.
3. At the top of the IP Catalog window, select Arria 10 device family
4. In IP Catalog, under Library ➤ Interface Protocols, select the appropriate PHY
IP and then click Add.
5. In the New IP Instance Dialog Box, provide the IP instance name.
6. Select Arria 10 device family.
7. Select the appropriate device and click OK.
The PHY IP Parameter Editor window opens.
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Figure 20.
Arria 10 Transceiver PHY Types
Related Information
Arria 10 Transceiver Protocols and PHY IP Support
on page 41
2.2.2. Configure the PHY IP Core
Configure the PHY IP core by selecting the valid parameters for your design. The valid parameter settings are different for each protocol. Refer to the appropriate protocol's section for selecting valid parameters for each protocol.
Related Information
•
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
For information on Native PHY IP.
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•
on page 94
•
Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 112
•
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants
on page 124
•
on page 135
•
1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core
on page 164
•
PCI Express (PIPE) on page 229
•
on page 279
•
Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
•
Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
on page 300
•
Design Considerations for Implementing Arria 10 GT Channels
on page 319
2.2.3. Generate the PHY IP Core
After configuring the PHY IP, complete the following steps to generate the PHY IP.
1. Click the Generate HDL button in the Parameter Editor window. The
Generation dialog box opens.
2. In Synthesis options, under Create HDL design for synthesis select
Verilog or
VHDL
.
3. Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.
4. In Output Directory, select Clear output directories for selected generation
targets if you want to clear any previous IP generation files from the selected output directory.
5. Click Generate.
The Quartus Prime software generates a <phy ip instance name> folder, <phy ip
instance name>_sim folder, <phy ip instance name>.qip file, <phy ip instance
name>.qsys file, and <phy ip instance name>.v file or <phy ip instance name>.vhd
file. This <phy ip instance name>.v file is the top level design file for the PHY IP and is placed in the <phy ip instance name>/synth folder. The other folders contain lower level design files used for simulation and compilation.
Related Information
IP Core File Locations on page 91
For more information about IP core file structure
2.2.4. Select the PLL IP Core
Arria 10 devices have three types of PLL IP cores:
• Advanced Transmit (ATX) PLL IP core.
• Fractional PLL (fPLL) IP core.
• Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.
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Select the appropriate PLL IP for your design. For additional details, refer to the PLLs
and Clock Networks chapter.
To instantiate a PLL IP:
1. Open the Quartus Prime software.
2. Click Tools ➤ IP Catalog.
3. At the top of the IP Catalog window, select Arria 10 device family
4. In IP Catalog, under Library ➤ Basic Functions ➤ Clocks, PLLs, and Resets
➤ PLL choose the PLL IP (Arria 10 fPLL, Arria 10 Transceiver ATX PLL, or
Arria 10 Transceiver CMU PLL) you want to include in your design and then click Add.
5. In the New IP Instance Dialog Box, provide the IP instance name.
6. Select Arria 10 device family.
7. Select the appropriate device and click OK.
The PLL IP GUI window opens.
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Figure 21.
Arria 10 Transceiver PLL Types
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Related Information
2.2.5. Configure the PLL IP Core
Understand the available PLLs, clock networks, and the supported clocking configurations. Configure the PLL IP to achieve the adequate data rate for your design.
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Related Information
•
on page 354
•
on page 362
•
•
on page 398
2.2.6. Generate the PLL IP Core
After configuring the PLL IP core, complete the following steps to generate the PLL IP core.
1. Click the Generate HDL button in the Parameter Editor window. The
Generation dialog box opens.
2. In Synthesis options, under Create HDL design for synthesis select
Verilog or
VHDL
.
3. Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.
4. In Output Directory, select Clear output directories for selected generation
targets if you want to clear any previous IP generation files from the selected output directory.
5. Click Generate.
The Quartus ® Prime software generates a <pll ip core instance name> folder, <pll ip
core instance name>_sim folder, <pll ip core instance name>.qip file, <pll ip core
instance name>.qsys, and <pll ip core instance name>.v file or <pll ip core instance
name>.vhd file. The <pll ip core instance name>.v file is the top level design file for the PLL IP core and is placed in the <pll ip core instance name>/ synth folder. The other folders contain lower level design files used for simulation and compilation.
Related Information
IP Core File Locations on page 91
For more information about IP core file structure
2.2.7. Reset Controller
There are two methods to reset the transceivers in Arria 10 devices:
• Use the Transceiver PHY Reset Controller.
• Create your own reset controller that follows the recommended reset sequence.
Related Information
Resetting Transceiver Channels
on page 416
2.2.8. Create Reconfiguration Logic
Dynamic reconfiguration is the ability to dynamically modify the transceiver channels and PLL settings during device operation. To support dynamic reconfiguration, your design must include an Avalon master that can access the dynamic reconfiguration registers using the Avalon-MM interface.
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The Avalon-MM master enables PLL and channel reconfiguration. You can dynamically adjust the PMA parameters, such as differential output voltage swing (Vod), and preemphasis settings. This adjustment can be done by writing to the Avalon-MM reconfiguration registers through the user generated Avalon-MM master.
For detailed information on dynamic reconfiguration, refer to Reconfiguration Interface
and Dynamic Reconfiguration chapter.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration
on page 502
2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller
Connect the PHY IP, PLL IP core, and the reset controller. Write the top level module to connect all the IP blocks.
All of the I/O ports for each IP, can be seen in the <phy instance name>.v file or <phy
instance name>.vhd, and in the <phy_instance_name>_bb.v file.
For more information about description of the ports, refer to the ports tables in the
PLLs, Using the Transceiver Native PHY IP Core, and Resetting Transceiver Channels chapters.
Related Information
•
•
•
Resetting Transceiver Channels
on page 416
•
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
•
PLLs and Clock Networks on page 347
2.2.10. Connect Datapath
Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core or to a data generator / analyzer or a frame generator / analyzer.
2.2.11. Make Analog Parameter Settings
Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File.
After verifying your design functionality, make pin assignments and PMA analog parameter settings for the transceiver pins.
1. Assign FPGA pins to all the transceiver and reference clock I/O pins. For more details, refer to the Arria 10 Pin Connection Guidelines.
2. Set the analog parameters to the transmitter, receiver, and reference clock pins using the Assignment Editor.
All of the pin assignments and analog parameters set using the Pin Planner and the Assignment Editor are saved in the <top_level_project_name>.qsf file. You can also directly modify the Quartus Settings File (.qsf) to set PMA analog parameters.
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Related Information
•
Analog Parameter Settings on page 585
• Arria 10 Pin Connection Guidelines
2.2.12. Compile the Design
To compile the transceiver design, add the <phy_instancename>.qip files for all the IP blocks generated using the IP Catalog to the Quartus Prime project library. You can alternatively add the .qsys and .qip variants of the IP cores.
Note: If you add both the .qsys and the .qip file into the Quartus Prime project, the software generates an error.
Related Information
Intel Quartus Prime Incremental Compilation for Hierarchical and Team-Based Design
For more information about compilation details.
2.2.13. Verify Design Functionality
Simulate your design to verify the functionality of your design. For more details, refer to Simulating the Native Transceiver PHY IP Core section.
Related Information
•
Simulating the Transceiver Native PHY IP Core on page 325
• Quartus Prime Handbook - Volume 3: Verification
Information about design simulation and verification.
2.3. Arria 10 Transceiver Protocols and PHY IP Support
Table 8.
Arria 10 Transceiver Protocols and PHY IP Support
Protocol
PCIe Gen3 x1, x2, x4, x8
PCIe Gen2 x1, x2, x4, x8
PCIe Gen1 x1, x2, x4, x8
Transceiver PHY IP
Core
Native PHY IP core
(PIPE)/Hard IP for PCI
Express (
)
Native PHY IP (PIPE) core/Hard IP for PCI
Express (
Native PHY IP (PIPE) core/Hard IP for PCI
Express (
PCS Support
Standard and Gen3
Standard
Standard
Transceiver
Configuration Rule (9)
Gen3 PIPE
Gen2 PIPE
Gen1 PIPE
Protocol Preset (10)
PCIe PIPE Gen3 x1
PCIe PIPE Gen3 x8
PCIe PIPE Gen2 x1
PCIe PIPE Gen2 x8
User created continued...
(9) For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10) For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(11) Hard IP for PCI Express is also available as a separate IP core.
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Protocol
1000BASE-X Gigabit
Ethernet
1000BASE-X Gigabit
Ethernet with 1588
10GBASE-R
Transceiver PHY IP
Core
Native PHY IP core
Native PHY IP core
Native PHY IP core
10GBASE-R 1588
10GBASE-R with KR
FEC
10GBASE-KR and
1000BASE-X
Native PHY IP core
Native PHY IP core
1G/10GbE and
10GBASE-KR PHY
IP (12)
40GBASE-R
40GBASE-R with FEC/
40GBASE-KR4 (14)
100GBASE-R via
CAUI-4/CPPI-4/BP and
CEI-25G
100GBASE-R via CAUI
100GBASE-R via CAUI with FEC
XAUI
SPAUI
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
XAUI PHY IP core
Native PHY IP core
PCS Support
Standard
Standard
Enhanced
Enhanced
Enhanced
Standard and
Enhanced
Enhanced
Enhanced
Enhanced and PCS
Direct
Transceiver
Configuration Rule (9)
GbE
Protocol Preset (10)
GIGE - 1.25 Gbps
GbE 1588
10GBASE-R
GIGE - 1.25 Gbps
1588
10GBASE-R Low
Latency
10GBASE-R 1588 10GBASE-R 1588
10GBASE-R w/KR FEC 10GBASE-R w/KR FEC
Not applicable BackPlane_wo_1588
LineSide (optical)
LineSide(optical)_158
8
Basic (Enhanced PCS) Low Latency Enhanced
PCS (13)
Basic w/KR FEC User created
Basic (Enhanced
PCS) / PCS Direct
Low Latency GT (15)
Enhanced
Enhanced
Soft PCS
Standard and
Enhanced
Basic (Enhanced PCS) Low Latency Enhanced
PCS (16)
Basic w/KR FEC User created
Not applicable
Basic/Custom
(Standard PCS)
Not applicable
User created continued...
(9) For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10) For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(12) The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training, auto speed negotiation, and sequencer functions.
(13) To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(14) Link training, auto speed negotiation and sequencer functions are not included in the Native
PHY IP. The user would have to create soft logic to implement these functions when using
Native PHY IP.
(15) Low Latency GT protocol preset requires some modification to implement CAUI-4/CPPI-4/BP-4 and CEI-25G.
(16) To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the number of data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
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Protocol
DDR XAUI
Transceiver PHY IP
Core
Native PHY IP core
Interlaken (CEI-6G/
11G) (17)
Native PHY IP core
OTU-4 (100G) via
OTL4.10/OIF SFI-S
OTU-3 (40G) via
OTL3.4/OIF SFI-5.2/
SFI-5.1
OTU-2 (10G) via SFP
+/SFF-8431/CEI-11G
OTU-2 (10G) via OIF
SFI-5.1s
OTU-1 (2.7G)
SONET/SDH STS-768/
STM-256 (40G) via
OIF SFI-5.2/STL256.4
SONET/SDH STS-768/
STM-256 (40G) via
OIF SFI-5.1
SONET/SDH STS-192/
STM-64 (10G) via SFP
+/SFF-8431/CEI-11G
SONET/SDH STS-192/
STM-64 (10G) via OIF
SFI-5.1s/SxI-5/
SFI-4.2
SONET STS-96 (5G) via OIF SFI-5.1s
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
PCS Support
Standard and
Enhanced
Enhanced
Enhanced
Enhanced
Transceiver
Configuration Rule (9)
Basic (Enhanced PCS)
Basic/Custom
(Standard PCS)
Basic (Enhanced PCS)
Interlaken
Protocol Preset (10)
User created
Basic (Enhanced PCS)
Basic (Enhanced PCS)
Interlaken
10x12.5Gbps
Interlaken
6x10.3Gbps
Interlaken
1x6.25Gbps
SFI-S 64:64 4x11.3
Gbps (18)
User created
Enhanced
Enhanced
Standard
Enhanced
Basic (Enhanced PCS)
Basic (Enhanced PCS)
Basic/Custom
(Standard PCS)
Basic (Enhanced PCS)
User created
User created
User created
User created
Enhanced
Enhanced
Enhanced
Basic (Enhanced PCS)
Basic (Enhanced PCS)
Basic (Enhanced PCS)
User created
User created
User created
Enhanced Basic/Custom
(Standard PCS)
SONET/SDH OC-96 continued...
(9) For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10) For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(17) A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in the design example.
(18) To implement OTU-4 (100G) via OTL4.10/OIF SFI-S using SFI-S 64:64 4x11.3Gbps preset, change the number of data channels to 10 for OTL4.10 or user desired number of channels and datarate implemented for SFI-S.
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Protocol
SONET/SDH STS-48/
STM-16 (2.5G) via
SFP/TFI-5.1
SONET/SDH STS-12/
STM-4 (0.622G) via
SFP/TFI-5.1
Intel QPI 1.1/2.0
SD-SDI/HD-SDI/3G-
SDI
Vx1
DisplayPort
1.25G/ 2.5G
10G GPON/EPON
2.5G/1.25G GPON/
EPON
16G/10G Fibre
Channel
8G/4G/2G/1G Fibre
Channel
(20)
EDR Infiniband x1, x4
Transceiver PHY IP
Core
Native PHY IP core
Native PHY IP core (
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
FDR/FDR-10 Infiniband x1, x4, x12
SDR/DDR/QDR
Infiniband x1, x4, x12
CPRI v6.1 12.16512/
CPRI v6.0 10.1376 Gbps
CPRI 4.2/OBSAI RP3 v4.2
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
PCS Support
Standard
Standard
PCS Direct
Standard
Standard
Standard
Enhanced
Transceiver
Configuration Rule
Basic/Custom
(Standard PCS)
Basic/Custom
(Standard PCS)
(9)
PCS Direct
Basic/Custom
(Standard PCS)
Basic/Custom
(Standard PCS)
Basic/Custom
(Standard PCS)
Basic (Enhanced PCS)
Standard
Enhanced
Standard
Enhanced (low latency mode)
PCS Direct
Enhanced
Basic/Custom
(Standard PCS)
Basic (Enhanced PCS)
PCS Direct
Basic (Enhanced PCS)
Standard
Enhanced
Standard
Basic/Custom
(Standard PCS)
Basic (Enhanced PCS)
Basic/Custom
(Standard PCS)
10GBASE-R 1588
10GBASE-R
CPRI (Auto) / CPRI
(Manual)
Protocol Preset (10)
SONET/SDH OC-48
SONET/SDH OC-12
User created
3G/HD SDI NTSC
3G/HD SDI PAL
User created
User created
User created
User created
User created
User created
User created
User created
User created
User created
CPRI 9.8Gbps Auto
Mode continued...
(9) For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10) For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(19) The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter.
For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
(20) To meet DisplayPort TX electrical full compliance to VESA DisplayPort Standard version 1.3 and
VESA DisplayPort PHY Compliance Specification version 1.2b ,
VCCT_GXB
&
VCCR_GXB
needs to be 1.03V or higher. Test Refer to AN745: Design Guidelines for DisplayPort and HDMI
Interfaces for further details.
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Protocol
SRIO 2.2/1.3
SAS 3.0
SATA 3.0/2.0/1.0 and
SAS 2.0/1.1/1.0
HiGig/HiGig+/HiGig2/
HiGig2+
JESD204A / JESD204B
ASI
Transceiver PHY IP
Core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
PCS Support
Standard
Enhanced
Standard
Standard
Standard and
Enhanced
Standard
Transceiver
Configuration Rule (9)
Protocol Preset (10)
CPRI 9.8 Gbps Manual
Mode
Serial Rapid IO 1.25
Gbps
Basic/Custom with
Rate Match(Standard
PCS)
Basic (Enhanced PCS)
Basic/Custom
(Standard PCS)
User created
SAS Gen2/Gen1.1/
Gen1
SATA Gen3/Gen2/
Gen1
User created Basic/Custom
(Standard PCS)
Basic/Custom
(Standard PCS) Basic
(Enhanced PCS)
)
Basic/Custom
(Standard PCS)
Basic (Enhanced PCS)
User created
User created
User created SPI-5 (100G) / SPI-5
(50G)
Custom and other protocols
Native PHY IP core
Native PHY IP core
Enhanced
Standard and
Enhanced
PCS Direct
Basis/Custom
(Standard PCS)
Basic (Enhanced PCS)
Basic/Custom with
Rate Match (Standard
PCS)
PCS Direct
Related Information
•
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
• AN745: Design Guidelines for DisplayPort and HDMI Interfaces
User created
2.4. Using the Arria 10 Transceiver Native PHY IP Core
This section describes the use of the Intel-provided Arria 10 Transceiver Native PHY IP core. This Native PHY IP core provides direct access to Arria 10 transceiver PHY features.
Use the Native PHY IP core to configure the transceiver PHY for your protocol implementation. To instantiate the IP, click Tools
➤
IP Catalog to select your IP core variation. Use the Parameter Editor to specify the IP parameters and configure the
PHY IP for your protocol implementation. To quickly configure the PHY IP, select a
(9) For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10) For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(21) For JESD204B, Enhanced PCS is used when the data rate is above 12.0 Gbps
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Reconfiguration Interface
Transmit and Receive Clocks
Reconfiguration
Registers
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preset that matches your protocol configuration as a starting point. Presets are PHY IP configuration settings for various protocols that are stored in the IP Parameter
Editor. Presets are explained in detail in the Presets section below.
You can also configure the PHY IP by selecting an appropriate Transceiver
Configuration Rule. The transceiver configuration rules check the valid combinations of the PCS and PMA blocks in the transceiver PHY layer, and report errors or warnings for any invalid settings.
Use the Native PHY IP core to instantiate the following PCS options:
• Standard PCS
• Enhanced PCS
• PCIe Gen3 PCS
• PCS Direct
Based on the Transceiver Configuration Rule that you select, the PHY IP core selects the appropriate PCS. The PHY IP core allows you to select all the PCS blocks if you intend to dynamically reconfigure from one PCS to another. Refer to General and
Datapath Parameters section for more details on how to enable PCS blocks for dynamic reconfiguration. Refer to the How to Place Channels for PIPE Configuration section or the PCIE solutions guides on restrictions on placement of transceiver channels next to active banks with PCI Express interfaces that are Gen3 capable..
After you configure the PHY IP core in the Parameter Editor, click Generate HDL to generate the IP instance. The top level file generated with the IP instance includes all the available ports for your configuration. Use these ports to connect the PHY IP core to the PLL IP core, the reset controller IP core, and to other IP cores in your design.
Figure 22.
Native PHY IP Core Ports and Functional Blocks
Transmit
PMA
Transmit Serial Data
Transmit Parallel Data
Receive Parallel Data
Reset Signals
Enhanced PCS
Standard PCS
PCIe Gen3 PCS
PCS-Direct
Receive
PMA
Receive Serial Data
Nios II
Calibration
Calibration Signals
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Figure 23.
Native PHY IP Core Parameter Editor
General
Options
Common
PMA Options
Datapath
Options
Documentation
Presets
Note:
PMA/PCS, Dynamic Reconfiguration, Optional Analog PMA Settings, and General Options
Although the Quartus Prime software provides legality checks, the supported FPGA fabric to PCS interface widths and the supported data rates are pending characterization.
Related Information
•
Configure the PHY IP Core on page 35
•
on page 94
•
Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 112
•
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants
on page 124
•
on page 135
•
1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core
on page 164
•
PCI Express (PIPE) on page 229
•
on page 279
•
Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
•
Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
on page 300
•
Design Considerations for Implementing Arria 10 GT Channels
on page 319
•
•
•
General and Datapath Parameters
on page 48
•
•
•
on page 73
•
How to Place Channels for Pipe Configuration on page 268
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2.4.1. Presets
You can select preset settings for the Native PHY IP core defined for each protocol. Use presets as a starting point to specify parameters for your specific protocol or application.
To apply a preset to the Native PHY IP core, double-click on the preset name. When you apply a preset, all relevant options and parameters are set in the current instance of the Native PHY IP core. For example, selecting the Interlaken preset enables all parameters and ports that the Interlaken protocol requires.
Selecting a preset does not prevent you from changing any parameter to meet the requirements of your design. Any changes that you make are validated by the design rules for the transceiver configuration rules you specified, not the selected preset.
Note: Selecting a preset clears any prior selections user has made so far.
2.4.2. General and Datapath Parameters
You can customize your instance of the Native PHY IP core by specifying parameter values. In the Parameter Editor, the parameters are organized in the following sections for each functional block and feature:
• General, Common PMA Options, and Datapath Options
• TX PMA
• RX PMA
• Standard PCS
• Enhanced PCS
• PCS Direct Datapath
• Dynamic Reconfiguration
• Analog PMA Settings (Optional)
• Generation Options
Table 9.
General, Common PMA Options, and Datapath Options
Parameter
Message level for rule violations error warning
Value Description
Specifies the messaging level for parameter rule violations.
Selecting error causes all rule violations to prevent IP generation.
Selecting warning displays all rule violations as warnings in the message window and allows IP generation despite the violations.
(22)
VCCR_GXB
and
VCCT_GXB
supply voltage for the Transceiver
0_9V, 1_0V, 1_1V
Transceiver Link Type sr, lr
Selects the
Transceiver.
VCCR_GXB
and
VCCT_GXB
supply voltage for the
Note: This option is only used for GUI rule validation. Use
Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.
Selects the type of transceiver link. sr-Short Reach (Chip-to-chip communication), lr-Long Reach (Backplane communication).
continued...
(22) Although you can generate the PHY with warnings, you can not compile the PHY in Quartus
Prime.
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Parameter
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Basic
SATA/SAS
QPI
GPON
TX/RX Duplex
TX Simplex
RX Simplex
1 – <n>
Value
User Selection
< valid Transceiver data
rate >
Description
Note: This option is only used for GUI rule validation. Use
Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.
Specifies the valid configuration rules for the transceiver.
This parameter specifies the configuration rule against which the
Parameter Editor checks your PMA and PCS parameter settings for specific protocols. Depending on the transceiver configuration rule selected, the Parameter Editor validates the parameters and options selected by you and generates error messages or warnings for all invalid settings.
To determine the transceiver configuration rule to be selected for
your protocol, refer to Table 8
on page 41 Transceiver
Configuration Rule Parameters table for more details about each transceiver configuration rule.
This parameter is used for rule checking and is not a preset. You need to set all parameters for your protocol implementation.
Specifies the configuration rule for PMA.
Select Basic for all other protocol modes except for SATA, GPON, and QPI.
SATA (Serial ATA) can be used only if the Transceiver
configuration rule is set to Basic/Custom (Standard PCS).
GPON can be used only if the Transceiver configuration rule is set to Basic (Enhanced PCS).
QPI can be used only if the Transceiver configuration rule is set to PCS Direct.
Specifies the operational mode of the transceiver.
• TX/RX Duplex : Specifies a single channel that supports both transmission and reception.
• TX Simplex : Specifies a single channel that supports only transmission.
• RX Simplex : Specifies a single channel that supports only reception.
The default is TX/RX Duplex.
Specifies the number of transceiver channels to be implemented.
The maximum number of channels available, ( <n> ), depends on the package you select.
The default value is 1.
Specifies the data rate in megabits per second (Mbps).
continued...
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Parameter
Enable datapath and interface reconfiguration
On/Off
Value
Enable simplified data interface
On/Off
Description
When you turn this option on, you can preconfigure and dynamically switch between the Standard PCS, Enhanced PCS, and
PCS direct datapaths.
The default value is Off.
By default, all 128-bits are ports for the tx_parallel_data
and rx_parallel_data
buses are exposed. You must understand the mapping of data and control signals within the interface. Refer to the Enhanced PCS TX and RX Control Ports section for details about mapping of data and control signals.
When you turn on this option, the Native PHY IP core presents a simplified data and control interface between the FPGA fabric and transceiver. Only the sub-set of the 128-bits that are active for a particular FPGA fabric width are ports.
The default value is Off.
(23)
When selected the Native PHY IP core presents separate data, reset and clock interfaces for each channel rather than a wide bus.
Provide separate interface for each channel
On/Off
Table 10.
GbE
GbE 1588
Interlaken
10GBASE-R
Transceiver Configuration Rule Parameters
Transceiver Configuration Setting
Basic/Custom (Standard PCS)
Basic/Custom w /Rate Match
(Standard PCS)
CPRI (Auto)
CPRI (Manual)
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE
Basic (Enhanced PCS)
Description
Enforces a standard set of rules within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.
Enforces a standard set of rules including rules for the Rate Match FIFO within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.
Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Auto. In Auto mode, the word aligner is set to deterministic latency.
Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Manual. In Manual mode, logic in the FPGA fabric controls the word aligner.
Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.
Enforces rules for the 1 GbE protocol with support for Precision time protocol
(PTP) as defined in the IEEE 1588 Standard.
Enforces rules for a Gen1 PCIe ®
MAC and Data Link Layer.
PIPE interface that you can connect to a soft
Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer.
Enforces rules for a Gen3 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer.
Enforces a standard set of rules within the Enhanced PCS. Select these rules to implement protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.
Enforces rules required by the Interlaken protocol.
Enforces rules required by the 10GBASE-R protocol.
continued...
(23) This option cannot be used, if you intend to dynamically reconfigure between PCS datapaths, or reconfigure the interface of the transceiver.
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Transceiver Configuration Setting
10GBASE-R 1588
10GBASE-R w/KR FEC
40GBASE-R w/KR FEC
Basic w/KR FEC
PCS Direct
Description
Enforces rules required by the 10GBASE-R protocol with 1588 enabled.
Enforces rules required by the 10GBASE-R protocol with KR FEC block enabled.
Enforces rules required by the 40GBASE-R protocol with the KR FEC block enabled.
Enforces a standard set of rules required by the Enhanced PCS when you enable the KR FEC block. Select this rule to implement custom protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.
Enforces rules required by the PCS Direct mode. In this configuration the data flows through the PCS channel, but all the internal PCS blocks are bypassed. If required, the PCS functionality can be implemented in the FPGA fabric.
Related Information
•
on page 9
•
Enhanced PCS TX and RX Control Ports
on page 83
2.4.3. PMA Parameters
You can specify values for the following types of PMA parameters:
TX PMA
• TX Bonding Options
• TX PLL Options
• TX PMA Optional Ports
RX PMA
• RX CDR Options
• Equalization
• RX PMA Optional Ports
Table 11.
TX Bonding Options
Parameter
TX channel bonding mode
Value
Not bonded
PMA only bonding
PMA and PCS bonding
Description
Selects the bonding mode to be used for the channels specified.
Bonded channels use a single TX PLL to generate a clock that drives multiple channels, reducing channel-to-channel skew. The following options are available:
Not bonded: In a non-bonded configuration, only the high speed serial clock is expected to be connected from the TX PLL to the
Native PHY IP core. The low speed parallel clock is generated by the local clock generation block (CGB) present in the transceiver channel. For non-bonded configurations, because the channels are not related to each other and the feedback path is local to the PLL, the skew between channels cannot be calculated.
PMA only bonding: In PMA bonding, the high speed serial clock is routed from the transmitter PLL to the master CGB. The master
CGB generates the high speed and low parallel clocks and the local
CGB for each channel is bypassed. Refer to the Channel Bonding section for more details.
PMA and PCS bonding : In a PMA and PCS bonded configuration, the local CGB in each channel is bypassed and the parallel clocks generated by the master CGB are used to clock the continued...
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Parameter
PCS TX channel bonding master
Actual PCS TX channel bonding master
Value
Auto, 0 to <number of channels> -1
0 to <number of channels> -1
Description network. The master CGB generates both the high and low speed clocks. The master channel generates the PCS control signals and distributes to other channels through a control plane block.
The default value is Not bonded.
Refer to Channel Bonding section in PLLs and Clock Networks chapter for more details.
Specifies the master PCS channel for PCS bonded configurations.
Each Native PHY IP core instance configured with bonding must specify a bonding master. If you select Auto, the Native PHY IP core automatically selects a recommended channel.
The default value is Auto. Refer to the PLLs and Clock Networks chapter for more information about the TX channel bonding master.
This parameter is automatically populated based on your selection for the PCS TX channel bonding master parameter. Indicates the selected master PCS channel for PCS bonded configurations.
Table 12.
TX PLL Options
Parameter
TX local clock division factor
1, 2, 4, 8
Value
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
1, 2, 3 , 4
0 to <number of TX
PLL clock inputs> -1
Description
Specifies the value of the divider available in the transceiver channels to divide the TX PLL output clock to generate the correct frequencies for the parallel and serial clocks.
Specifies the number of TX PLL clock inputs per channel. Use this parameter when you plan to dynamically switch between TX PLL clock sources. Up to four input sources are possible.
Specifies the initially selected TX PLL clock input. This parameter is necessary when you plan to switch between multiple TX PLL clock inputs.
Table 13.
TX PMA Optional Ports
Parameter
Enable tx_pma_analog_reset_ack port
Enable tx_pma_clkout port
Value
On/Off
On/Off
Description
Enables the optional tx_pma_analog_reset_ack
output port.
This port should not be used for register mode data transfers.
Enable tx_pma_div_clkout port
On/Off tx_pma_div_clkout division factor
Disabled, 1, 2,
33, 40, 66
Enables the optional tx_pma_clkout
output clock. This is the low speed parallel clock from the TX PMA. The source of this clock is the serializer. It is driven by the PCS/PMA interface block. (24)
Enables the optional tx_pma_div_clkout
output clock. This clock is generated by the serializer. You can use this to drive core logic, to drive the FPGA - transceivers interface.
If you select a tx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock. If you select a tx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA high serial clock. This clock is commonly used when the interface to the TX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.
Selects the division factor for the clock when enabled. (25) tx_pma_div_clkout
output continued...
(24) This clock should not be used to clock the FPGA - transceivers interface. This clock may be used as a reference clock to an external clock cleaner.
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Parameter
Enable tx_pma_iqtxrx_clkout port
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Enable tx_pma_qpipulldn port (QPI)
Enable tx_pma_txdetectrx port (QPI)
Enable tx_pma_rxfound port (QPI)
Value
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Enable rx_seriallpbken port On/Off
Description
Enables the optional of a PLL.
tx_pma_iqtxrx_clkout
output clock. This clock can be used to cascade the TX PMA output clock to the input
Enables the tx_pma_elecidle
port. When you assert this port, the transmitter is forced into an electrical idle condition. This port has no effect when the transceiver is configured for PCI Express.
Enables the tx_pma_qpipullup
control input port. Use this port only for Quick Path Interconnect (QPI) applications.
Enables the tx_pma_qpipulldn only for QPI applications.
control input port. Use this port
Enables the tx_pma_txdetectrx
control input port. The receiver detect block in the TX PMA detects the presence of a receiver at the other end of the channel. After receiving a tx_pma_txdetectrx
request the receiver detect block initiates the detection process. Use this port only in QPI applications.
Enables the tx_pma_rxfound detect block in TX PMA detects the presence of a receiver at the other end by using the
status output port. The receiver tx_pma_txdetectrx
input. The tx_pma_rxfound
port reports the status of the detection operation. Use this port only in QPI applications.
Enables the optional rx_seriallpbken
control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal.
Table 14.
RX CDR Options
Parameter
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
1 - 5
100
300
500
1000
Value
0 to <number of CDR reference clocks> -1
< data rate dependent >
Description
Specifies the number of CDR reference clocks. Up to 5 sources are possible.
The default value is 1.
Use this feature when you want to dynamically re-configure CDR reference clock source.
Specifies the initial CDR reference clock. This parameter determines the available CDR references used.
The default value is 0.
Specifies the CDR reference clock frequency. This value depends on the data rate specified.
Specifies the PPM threshold for the CDR. If the PPM between the incoming serial data and the CDR reference clock, exceeds this threshold value, the CDR loses lock.
The default value is 1000.
Table 15.
Equalization
Parameters
CTLE adaptation mode Manual
Value Description
Specifies the Continuous Time Linear Equalization (CTLE) operation mode.
continued...
(25) The default value is Disabled.
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Parameters
DFE adaptation mode
Number of fixed DFE taps
Adaptation enabled
Manual, Disabled
3, 7 , 11
Value Description
For manual mode, set the CTLE options through the Assignment
Editor, or modify the Quartus Settings File (.qsf), or write to the reconfiguration registers using the Avalon Memory-Mapped
(Avalon-MM) interface.
Refer to Continuous Time Linear Equalization (CTLE) on page 452
section in Arria 10 Transceiver Architecture chapter for more
details about CTLE architecture. Refer to How to Enable CTLE and
on page 456 for more details on supported adaptation modes.
Specifies the operating mode for the Decision Feedback
Equalization (DFE) block in the RX PMA.
The default value is Disabled.
For manual mode, you can set the DFE options through the
Assignment Editor, or by modifying the Quartus Settings File
(.qsf), or write to the reconfiguration registers using the Avalon-
MM interface.
Refer to the
Decision Feedback Equalization (DFE)
on page 454 section in the Arria 10 Transceiver PHY Architecture chapter for
more details about DFE. Refer to How to Enable CTLE and DFE on
page 456 for more details on supported adaptation modes.
Specifies the number of fixed DFE taps. Select the number of taps depending on the loss in your transmission channel and the type of equalization required.
Table 16.
RX PMA Optional Ports
Parameters
Enable rx_analog_reset_ack port
Enable rx_pma_clkout port
On/Off
On/Off
Value Description
Enables the optional rx_analog_reset_ack
output. This port should not be used for register mode data transfers.
Enable rx_pma_div_clkout port
On/Off rx_pma_div_clkout division factor
Enable rx_pma_iqtxrx_clkout port
Enable rx_pma_clkslip port
Disabled, 1, 2, 33, 40,
66
On/Off
On/Off
Enables the optional
(CDR). (26) rx_pma_clkout
output clock. This port is the recovered parallel clock from the RX clock data recovery
Enables the optional rx_pma_div_clkout
output clock. The deserializer generates this clock. Use this to drive core logic, to drive the RX PCS-to-FPGA fabric interface, or both.
If you select a rx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock. If you select a
rx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the RX FIFO runs at a different rate than the
PMA parallel clock frequency, such as 66:40 applications.
Selects the division factor for the clock when enabled. (27) rx_pma_div_clkout
output
Enables the optional of a PLL.
rx_pma_iqtxrx_clkout
output clock. This clock can be used to cascade the RX PMA output clock to the input
Enables the optional rx_pma_clkslip
control input port. A rising edge on this signal causes the RX serializer to slip the serial data by one clock cycle, or 2 unit intervals (UI).
continued...
(26) This clock should not be used to clock the FPGA - transceiver interface. This clock may be used as a reference clock to an external clock cleaner.
(27) The default value is Disabled.
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Parameters
Enable rx_pma_qpipulldn port
(QPI)
Enable rx_is_lockedtodata port
On/Off
On/Off
Value
Enable rx_is_lockedtoref port
On/Off
Enable rx_set_lockedtodata port and rx_set_lockedtoref ports
Enable rx_seriallpbken port
On/Off
On/Off
Description
Enables the rx_pma_qpipulldn only for QPI applications.
control input port. Use this port
Enables the optional rx_is_lockedtodata
status output port.
This signal indicates that the RX CDR is currently in lock to data mode or is attempting to lock to the incoming data stream. This is an asynchronous output signal.
Enables the optional rx_is_lockedtoref
status output port.
This signal indicates that the RX CDR is currently locked to the
CDR reference clock. This is an asynchronous output signal.
Enables the optional rx_set_lockedtodata
and rx_set_lockedtoref
control input ports. You can use these control ports to manually control the lock mode of the RX CDR.
These are asynchronous input signals.
Enable PRBS (Pseudo
Random Bit Sequence) verifier control and status port
On/Off
Enables the optional rx_seriallpbken
control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal.
Enables the optional rx_prbs_err
, rx_prbs_clr
, and rx_prbs_done
control ports. These ports control and collect status from the internal PRBS verifier.
Related Information
•
PLLs and Clock Networks on page 347
•
on page 389
•
Continuous Time Linear Equalization (CTLE)
on page 452
•
Decision Feedback Equalization (DFE) on page 454
•
Analog Parameter Settings on page 585
•
on page 456
2.4.4. Enhanced PCS Parameters
This section defines parameters available in the Native PHY IP core GUI to customize the individual blocks in the Enhanced PCS.
The following tables describe the available parameters. Based on the selection of the
Transceiver Configuration Rule , if the specified settings violate the protocol standard, the Native PHY IP core Parameter Editor prints error or warning messages.
Note: For detailed descriptions about the optional ports that you can enable or disable, refer to the Enhanced PCS Ports section.
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Table 17.
Enhanced PCS Parameters
Parameter
Enhanced PCS / PMA interface width
FPGA fabric /Enhanced
PCS interface width
Enable Enhanced PCS low latency mode
Enable RX/TX FIFO double width mode
Range
32, 40, 64
32, 40, , 64, 66, 67
On/Off
On/Off
Description
Specifies the interface width between the Enhanced PCS and the
PMA.
Specifies the interface width between the Enhanced PCS and the
FPGA fabric.
The 66-bit FPGA fabric to PCS interface width uses 64-bits from the
TX and RX parallel data. The block synchronizer determines the block boundary of the 66-bit word, with lower 2 bits from the control bus.
The 67-bit FPGA fabric to PCS interface width uses the 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 67-bit word with lower 3 bits from the control bus.
Enables the low latency path for the Enhanced PCS. When you turn on this option, the individual functional blocks within the Enhanced
PCS are bypassed to provide the lowest latency path from the PMA through the Enhanced PCS. When enabled, this mode is applicable for GX devices. Intel recommends not enabling it for GT devices.
Enables the double width mode for the RX and TX FIFOs. You can use double width mode to run the FPGA fabric at half the frequency of the PCS.
Table 18.
Enhanced PCS TX FIFO Parameters
Parameter
TX FIFO Mode
TX FIFO partially full threshold
Range
Phase-Compensation
Register
Interlaken
Basic
Fast Register
10, 11, 12, 13
Description
Specifies one of the following modes:
• Phase Compensation: The TX FIFO compensates for the clock phase difference between the read clock rx_clkout
and the write clocks tx_coreclkin
or tx_clkout
. You can tie tx_enh_data_valid
to 1'b1.
• Register: The TX FIFO is bypassed. The tx_parallel_data
, tx_control
and tx_enh_data_valid are registered at the
FIFO output. Assert tx_enh_data_valid port 1'b1 at all times. The user must connect the write clock tx_coreclkin
to the read clock tx_clkout
.
• Interlaken: The TX FIFO acts as an elastic buffer. In this mode, there are additional signals to control the data flow into the
FIFO. Therefore, the FIFO write clock frequency does not have to be the same as the read clock frequency. You can control writes to the FIFO with tx_enh_data_valid
. By monitoring the FIFO flags, you can avoid the FIFO full and empty conditions. The Interlaken frame generator controls reads.
• Basic: The TX FIFO acts as an elastic buffer. This mode allows driving write and read side of FIFO with different clock frequencies. that tx_coreclkin
must have a minimum frequency of the lane data rate divided by 66. The frequency range for rate/32) - (data rate/66). For best results, Intel recommends tx_coreclkin tx_coreclkin
or
or rx_coreclkin
or rx_coreclkin rx_coreclkin
is (data
= (data rate/32).
Monitor FIFO flag to control write and read operations. For additional details refer to
on page
297 section
• Fast Register: The TX FIFO allows a higher maximum frequency (f
MAX
) between the FPGA fabric and the TX PCS at the expense of higher latency.
Specifies the partially full threshold for the Enhanced PCS TX FIFO.
Enter the value at which you want the TX FIFO to flag a partially full status.
continued...
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Parameter
TX FIFO partially empty threshold
Enable tx_enh_fifo_full port
Enable tx_enh_fifo_pfull port
On / Off
On / Off
Enable tx_enh_fifo_empty port
Enable tx_enh_fifo_pempty port
Range
2, 3, 4, 5
On / Off
On / Off
Description
Specifies the partially empty threshold for the Enhanced PCS TX
FIFO. Enter the value at which you want the TX FIFO to flag a partially empty status.
Enables the tx_enh_fifo_full port. This signal indicates when the
TX FIFO is full. This signal is synchronous to tx_coreclkin
.
Enables the tx_enh_fifo_pfull port. This signal indicates when the TX FIFO reaches the specified partially full threshold. This signal is synchronous to tx_coreclkin
.
Enables the tx_enh_fifo_empty port. This signal indicates when the TX FIFO is empty. This signal is synchronous to tx_coreclkin
.
Enables the tx_enh_fifo_pempty port. This signal indicates when the TX FIFO reaches the specified partially empty threshold. This signal is synchronous to tx_coreclkin
.
Table 19.
Enhanced PCS RX FIFO Parameters
Parameter
RX FIFO Mode
Range
Phase-Compensation
Register
Interlaken
10GBASE-R
Basic
RX FIFO partially full threshold
RX FIFO partially empty threshold
Enable RX FIFO alignment word deletion (Interlaken)
18-29
2-10
On / Off
Description
Specifies one of the following modes for Enhanced PCS RX FIFO:
• Phase Compensation: This mode compensates for the clock phase difference between the read clocks rx_coreclkin
or tx_clkout
and the write clock rx_clkout
.
• Register : The RX FIFO is bypassed. The rx_parallel_data
, rx_control
, and rx_enh_data_valid
are registered at the FIFO output. The
FIFO's read clock are tied together.
rx_coreclkin
and write clock rx_clkout
• Interlaken: Select this mode for the Interlaken protocol. To implement the deskew process, you must implement an FSM that controls the FIFO operation based on FIFO flags. In this mode the FIFO acts as an elastic buffer.
• 10GBASE-R: In this mode, data passes through the FIFO after block lock is achieved. OS (Ordered Sets) are deleted and
Idles are inserted to compensate for the clock difference between the RX PMA clock and the fabric clock of +/- 100 ppm for a maximum packet length of 64000 bytes.
• Basic: In this mode, the RX FIFO acts as an elastic buffer. This mode allows driving write and read side of FIFO with different clock frequencies. tx_coreclkin
or rx_coreclkin
must have a minimum frequency of the lane data rate divided by
66. The frequency range for tx_coreclkin
or rx_coreclkin
is (data rate/32) - (data rate/66). The gearbox data valid flag controls the FIFO read enable. You can monitor the rx_enh_fifo_pfull
and rx_enh_fifo_empty flags to determine whether or not to read from the FIFO. For additional details refer to
on page 297.
Note: The flags are for Interlaken and Basic modes only. They should be ignored in all other cases.
Specifies the partially full threshold for the Enhanced PCS RX
FIFO. The default value is 23.
Specifies the partially empty threshold for the Enhanced PCS RX
FIFO. The default value is 2.
When you turn on this option, all alignment words (sync words), including the first sync word, are removed after frame synchronization is achieved. If you enable this option, you must also enable control word deletion.
continued...
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Parameter
Enable RX FIFO control word deletion
(Interlaken)
On / Off
Range
Enable rx_enh_data_valid port
On / Off
Enable rx_enh_fifo_full port
Enable rx_enh_fifo_pfull port
On / Off
On / Off
Enable rx_enh_fifo_empty port
Enable rx_enh_fifo_pempty port
Enable rx_enh_fifo_del port (10GBASE-R)
On / Off
On / Off
On / Off
Enable rx_enh_fifo_insert port
(10GBASE-R)
On / Off
Enable rx_enh_fifo_rd_en port
On / Off
Description
When you turn on this option, Interlaken control word removal is enabled. When the Enhanced PCS RX FIFO is configured in
Interlaken mode, enabling this option, removes all control words after frame synchronization is achieved. Enabling this option requires that you also enable alignment word deletion.
Enables the rx_enh_data_valid port. This signal indicates when
RX data from RX FIFO is valid. This signal is synchronous to rx_coreclkin.
Enables the rx_enh_fifo_full port. This signal indicates when the RX FIFO is full. This is an asynchronous signal.
Enables the rx_enh_fifo_pfull port. This signal indicates when the RX FIFO has reached the specified partially full threshold. This is an asynchronous signal.
Enables the rx_enh_fifo_empty port. This signal indicates when the RX FIFO is empty. This signal is synchronous to rx_coreclkin
.
Enables the rx_enh_fifo_pempty port. This signal indicates when the RX FIFO has reached the specified partially empty threshold. This signal is synchronous to rx_coreclkin
.
Enables the optional rx_enh_fifo_del status output port. This signal indicates when a word has been deleted from the rate match FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This is an asynchronous signal.
Enables the rx_enh_fifo_insert port. This signal indicates when a word has been inserted into the rate match FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This signal is synchronous to rx_coreclkin
.
Enables the rx_enh_fifo_rd_en input port. This signal is enabled to read a word from the RX FIFO. This signal is synchronous to
rx_coreclkin
.
Enables the rx_enh_fifo_align_val status output port. Only used for Interlaken transceiver configuration rule. This signal is synchronous to rx_clkout
.
Enables the rx_enh_fifo_align_clr input port. Only used for
Interlaken. This signal is synchronous to rx_clkout
.
Enable rx_enh_fifo_align_val port (Interlaken)
Enable rx_enh_fifo_align_clr port (Interlaken)
On / Off
On / Off
Table 20.
Interlaken Frame Generator Parameters
Parameter
Enable Interlaken frame generator
Frame generator metaframe length
Enable Frame
Generator Burst
Control
On / Off
Range
5-8192
On / Off
Description
Enables the frame generator block of the Enhanced PCS.
Specifies the metaframe length of the frame generator. This metaframe length includes 4 framing control words created by the frame generator.
Enables frame generator burst. This determines whether the frame generator reads data from the TX FIFO based on the input of port tx_enh_frame_burst_en
.
continued...
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Parameter
Enable tx_enh_frame port
On / Off
Range
Enable tx_enh_frame_diag_st atus port
On / Off
Enable tx_enh_frame_burst_e n port
On / Off
Description
Enables the tx_enh_frame
status output port. When the
Interlaken frame generator is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.
Enables the tx_enh_frame_diag_status
2-bit input port.
When the Interlaken frame generator is enabled, the value of this signal contains the status message from the framing layer diagnostic word. This signal is synchronous to tx_clkout
.
Enables the tx_enh_frame_burst_en
FIFO. This signal is synchronous to
input port. When burst control is enabled for the Interlaken frame generator, this signal is asserted to control the frame generator data reads from the TX tx_clkout
.
Table 21.
Interlaken Frame Synchronizer Parameters
Parameter
Enable Interlaken frame synchronizer
Frame synchronizer metaframe length
Enable rx_enh_frame port
Enable rx_enh_frame_lock port
Enable rx_enh_frame_diag_st atus port
On / Off
Range
5-8192
On / Off
On / Off
On / Off
Description
When you turn on this option, the Enhanced PCS frame synchronizer is enabled.
Specifies the metaframe length of the frame synchronizer.
Enables the rx_enh_frame status output port. When the
Interlaken frame synchronizer is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.
Enables the rx_enh_frame_lock output port. When the
Interlaken frame synchronizer is enabled, this signal is asserted to indicate that the frame synchronizer has achieved metaframe delineation. This is an asynchronous output signal.
Enables therx_enh_frame_diag_status output port. When the
Interlaken frame synchronizer is enabled, this signal contains the value of the framing layer diagnostic word (bits [33:32]). This is a
2 bit per lane output signal. It is latched when a valid diagnostic word is received. This is an asynchronous signal.
Table 22.
Interlaken CRC32 Generator and Checker Parameters
Parameter
Enable Interlaken TX
CRC-32 Generator
Enable Interlaken TX
CRC-32 generator error insertion
Enable Interlaken RX
CRC-32 checker
Enable rx_enh_crc32_err port
On / Off
Range
On / Off
On / Off
On / Off
Description
When you turn on this option, the TX Enhanced PCS datapath enables the CRC32 generator function. CRC32 can be used as a diagnostic tool. The CRC contains the entire metaframe including the diagnostic word.
When you turn on this option, the error insertion of the interlaken
CRC-32 generator is enabled. Error insertion is cycle-accurate.
When this feature is enabled, the assertion of tx_control[8]
or tx_err_ins
signal causes the CRC calculation during that word is incorrectly inverted, and thus, the CRC created for that metaframe is incorrect.
Enables the CRC-32 checker function.
When you turn on this option, the Enhanced PCS enables the
rx_enh_crc32_err port. This signal is asserted to indicate that the CRC checker has found an error in the current metaframe.
This is an asynchronous signal.
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Table 23.
10GBASE-R BER Checker Parameters
Parameter
Enable rx_enh_highber port
(10GBASE-R)
Enable rx_enh_highber_clr_c nt port (10GBASE-R)
Enable rx_enh_clr_errblk_cou nt port (10GBASE-R)
On / Off
Range
On / Off
On / Off
Description
Enables the rx_enh_highber port. For 10GBASE-R transceiver configuration rule, this signal is asserted to indicate a bit error rate higher than 10 -4 . Per the 10GBASE-R specification, this occurs when there are at least 16 errors within 125 μs. This is an asynchronous signal.
Enables the rx_enh_highber_clr_cnt input port. For the
10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of times the BER state machine has entered the "BER_BAD_SH" state. This is an asynchronous signal.
Enables the rx_enh_clr_errblk_count input port. For the
10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of the times the RX state machine has entered the RX_E state. For protocols with FEC block enabled, this signal is asserted to reset the status counters within the RX FEC block. This is an asynchronous signal.
Table 24.
64b/66b Encoder and Decoder Parameters
Parameter
Enable TX 64b/66b encoder (10GBASE-R)
Enable RX 64b/66b decoder (10GBASE-R)
Enable TX sync header error insertion
On / Off
Range
On / Off
On / Off
Description
When you turn on this option, the Enhanced PCS enables the TX
64b/66b encoder.
When you turn on this option, the Enhanced PCS enables the RX
64b/66b decoder.
When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition testing on the receiver. When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly. If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.
Table 25.
Scrambler and Descrambler Parameters
Parameter
Enable TX scrambler
(10GBASE-R/
Interlaken)
TX scrambler seed
(10GBASE-R/
Interlaken)
Enable RX descrambler
(10GBASE-R/
Interlaken)
On / Off
Range
User-specified 58-bit value
On / Off
Description
Enables the scrambler function. This option is available for the
Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the scrambler in Basic (Enhanced PCS) mode when the block synchronizer is enabled and with 66:32,
66:40, or 66:64 gear box ratios.
You must provide a non-zero seed for the Interlaken protocol. For a multi-lane Interlaken Transceiver Native PHY IP, the first lane scrambler has this seed. For other lanes' scrambler, this seed is increased by 1 per each lane. The initial seed for 10GBASE-R is
0x03FFFFFFFFFFFFFF. This parameter is required for the
10GBASE-R and Interlaken protocols.
Enables the descrambler function. This option is available for Basic
(Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the descrambler in Basic (Enhanced PCS) mode with the block synchronizer enabled and with 66:32, 66:40, or 66:64 gear box ratios.
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Table 26.
Interlaken Disparity Generator and Checker Parameters
Parameter
Enable Interlaken TX disparity generator
Enable Interlaken RX disparity checker
Enable Interlaken TX random disparity bit
On / Off
Range
On / Off
On / Off
Description
When you turn on this option, the Enhanced PCS enables the disparity generator. This option is available for the Interlaken protocol.
When you turn on this option, the Enhanced PCS enables the disparity checker. This option is available for the Interlaken protocol.
Enables the Interlaken random disparity bit. When enabled, a random number is used as disparity bit which saves one cycle of latency.
Table 27.
Block Synchronizer Parameters
Parameter
Enable RX block synchronizer
Enable rx_enh_blk_lock port
On / Off
Range
On / Off
Description
When you turn on this option, the Enhanced PCS enables the RX block synchronizer. This options is available for the Basic
(Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols.
Enables the rx_enh_blk_lock delineation has been achieved.
port. When you enable the block synchronizer, this signal is asserted to indicate that the block
Table 28.
Gearbox Parameters
Parameter
Enable TX data bitslip On / Off
Range
Enable TX data polarity inversion
On / Off
Enable RX data bitslip
Enable RX data polarity inversion
Enable tx_enh_bitslip port
Enable rx_bitslip port
On / Off
On / Off
On / Off
On / Off
Description
When you turn on this option, the TX gearbox operates in bitslip mode. The tx_enh_bitslip port controls number of bits which TX parallel data slips before going to the PMA.
When you turn on this option, the polarity of TX data is inverted.
This allows you to correct incorrect placement and routing on the
PCB.
When you turn on this option, the Enhanced PCS RX block synchronizer operates in bitslip mode. When enabled, the
rx_bitslip port is asserted on the rising edge to ensure that RX parallel data from the PMA slips by one bit before passing to the
PCS.
When you turn on this option, the polarity of the RX data is inverted. This allows you to correct incorrect placement and routing on the PCB.
Enables the tx_enh_bitslip port. When TX bit slip is enabled, this signal controls the number of bits which TX parallel data slips before going to the PMA.
Enables the rx_bitslip port. When RX bit slip is enabled, the rx_bitslip
signal is asserted on the rising edge to ensure that
RX parallel data from the PMA slips by one bit before passing to the PCS. This port is shared between Standard PCS and Enhanced
PCS.
Note: If a design is slipping more bits than the PCS/PMA width, the Enhanced RX PCS FIFO could overflow. To clear the overflow, assert rx_digitalreset
.
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Table 29.
KR-FEC Parameters
Parameter
Enable RX KR-FEC error marking
Error marking type
Enable KR-FEC TX error insertion
On/Off
Range
10G, 40G
On/Off
Description
When you turn on this option, the decoder asserts both sync bits
(2'b11) when it detects an uncorrectable error. This feature increases the latency through the KR-FEC decoder.
Specifies the error marking type (10G or 40G).
Enables the error insertion feature of the KR-FEC encoder. This feature allows you to insert errors by corrupting data starting a bit
0 of the current word.
Specifies the spacing of the KR-FEC TX error insertion.
KR-FEC TX error insertion spacing
Enable tx_enh_frame port
Enable rx_enh_frame port
Enable rx_enh_frame_diag_st atus port
User Input (1 bit to 15 bit)
On/Off
On/Off
On/Off
Enables the tx_enh_frame port.
Enables the rx_enh_frame port.
Enables the rx_enh_frame_diag_status port.
Related Information
•
Arria 10 Enhanced PCS Architecture
on page 461
•
Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
•
on page 94
•
on page 135
•
•
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants
on page 124
2.4.5. Standard PCS Parameters
This section provides descriptions of the parameters that you can specify to customize the Standard PCS.
For specific information about configuring the Standard PCS for these protocols, refer to the sections of this user guide that describe support for these protocols.
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Table 30.
Standard PCS Parameters
Note: For detailed descriptions of the optional ports that you can enable or disable, refer to the
Standard PCS Ports on page 86 section.
Parameter
Standard PCS/PMA interface width
FPGA fabric/Standard
TX PCS interface width
FPGA fabric/Standard
RX PCS interface width
Enable Standard PCS low latency mode
Range
8, 10, 16, 20
8, 10, 16, 20, 32, 40
8, 10, 16, 20, 32, 40
On / Off
Description
Specifies the data interface width between the Standard PCS and the transceiver PMA.
Shows the FPGA fabric to TX PCS interface width. This value is determined by the current configuration of individual blocks within the Standard TX PCS datapath.
Shows the FPGA fabric to RX PCS interface width. This value is determined by the current configuration of individual blocks within the Standard RX PCS datapath.
Enables the low latency path for the Standard PCS. Some of the functional blocks within the Standard PCS are bypassed to provide the lowest latency. You cannot turn on this parameter while using the Basic/Custom w/Rate Match (Standard PCS) specified for
Transceiver configuration rules.
Table 31.
Standard PCS FIFO Parameters
Parameter
TX FIFO mode
Range low_latency register_fifo fast_register
RX FIFO mode
Enable tx_std_pcfifo_full port
Enable tx_std_pcfifo_empty port
Enable rx_std_pcfifo_full port
Enable rx_std_pcfifo_empty port low_latency register_fifo
On / Off
On / Off
On / Off
On / Off
Description
Specifies the Standard PCS TX FIFO mode. The following modes are available:
• low_latency: This mode adds 2-3 cycles of latency to the TX datapath.
• register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI.
• fast_register: This mode allows a higher maximum frequency
(f
MAX
) between the FPGA fabric and the TX PCS at the expense of higher latency.
The following modes are available:
• low_latency: This mode adds 2-3 cycles of latency to the RX datapath.
• register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI or
1588.
Enables the tx_std_pcfifo_full
port. This signal indicates when the standard TX phase compensation FIFO is full. This signal is synchronous with tx_coreclkin
.
Enables the tx_std_pcfifo_empty when the standard TX phase compensation FIFO is empty. This signal is synchronous with
port. This signal indicates tx_coreclkin
.
Enables the rx_std_pcfifo_full
port. This signal indicates when the standard RX phase compensation FIFO is full. This signal is synchronous with rx_coreclkin
.
Enables the rx_std_pcfifo_empty when the standard RX phase compensation FIFO is empty. This signal is synchronous with
port. This signal indicates rx_coreclkin
.
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Table 32.
Byte Serializer and Deserializer Parameters
Parameter
Enable TX byte serializer
Enable RX byte deserializer
Range
Disabled
Serialize x2
Serialize x4
Disabled
Deserialize x2
Deserialize x4
Description
Specifies the TX byte serializer mode for the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA serializer. The byte serializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths.
Serialize x4 is only applicable for PCIe protocol implementation.
Specifies the mode for the RX byte deserializer in the Standard
PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA deserializer. The byte deserializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths. Deserialize x4 is only applicable for PCIe protocol implementation.
Table 33.
8B/10B Encoder and Decoder Parameters
Parameter
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
Range
On / Off
On / Off
On / Off
Description
When you turn on this option, the Standard PCS enables the TX
8B/10B encoder.
When you turn on this option, the Standard PCS includes disparity control for the 8B/10B encoder. You can force the disparity of the
8B/10B encoder using the tx_forcedisp
control signal.
When you turn on this option, the Standard PCS includes the
8B/10B decoder.
Table 34.
Rate Match FIFO Parameters
Parameter
RX rate match FIFO mode
RX rate match insert/ delete -ve pattern (hex)
RX rate match insert/ delete +ve pattern (hex)
Enable rx_std_rmfifo_full port
Enable rx_std_rmfifo_empty port
PCI Express* Gen3 rate match FIFO mode
Range
Disabled
Basic 10-bit PMA width
Basic 20-bit PMA width
GbE
PIPE
PIPE 0 ppm
User-specified 20 bit pattern
User-specified 20 bit pattern
On / Off
On / Off
Bypass
0 ppm
600 ppm
Description
Specifies the operation of the RX rate match FIFO in the Standard
PCS.
Rate Match FIFO in Basic (Single Width) Mode on page 306
Rate Match FIFO Basic (Double Width) Mode on page 308
on page 117
Transceiver Channel Datapath for PIPE
on page 230
Specifies the -ve (negative) disparity value for the RX rate match
FIFO as a hexadecimal string.
Specifies the +ve (positive) disparity value for the RX rate match
FIFO as a hexadecimal string.
Enables the optional rx_std_rmfifo_full
port.
Enables the rx_std_rmfifo_empty
port.
Specifies the PPM tolerance for the PCI Express Gen3 rate match
FIFO.
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Table 35.
Word Aligner and Bitslip Parameters
Parameter
Enable TX bitslip
Range
On / Off
Description
When you turn on this option, the PCS includes the bitslip function. The outgoing TX data can be slipped by the number of bits specified by the tx_std_bitslipboundarysel
control signal.
Enables the tx_std_bitslipboundarysel
control signal.
Enable tx_std_bitslipboundarysel port
RX word aligner mode
RX word aligner pattern length
On / Off bitslip manual (PLD controlled) synchronous state machine deterministic latency
7, 8, 10, 16, 20,
32, 40
Specifies the RX word aligner mode for the Standard PCS.
The word aligned width depends on the PCS and PMA width, and whether or not 8B/10B is enabled.
Refer to "Word Aligner" for more information.
RX word aligner pattern (hex)
Number of word alignment patterns to achieve sync
Number of invalid words to lose sync
Number of valid data words to decrement error count
Enable fast sync status reporting for deterministic Latency SM
Enable rx_std_wa_patternalign port
Enable rx_std_wa_a1a2size port
Enable rx_std_bitslipboundarysel port
Enable rx_bitslip port
User-specified
0-255
0-63
0-255
On / Off
On / Off
On / Off
On / Off
On / Off
Specifies the length of the pattern the word aligner uses for alignment.
Refer to "RX Word Aligner Pattern Length" table in "Word
Aligner". It shows the possible values of "Rx Word Aligner
Pattern Length" in all available word aligner modes.
Specifies the word alignment pattern in hex.
Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock. The default is 3.
Specifies the number of invalid data codes or disparity errors that must be received before the word aligner loses synchronization. The default is 3.
Specifies the number of valid data codes that must be received to decrement the error counter. If the word aligner receives enough valid data codes to decrement the error count to 0, the word aligner returns to synchronization lock.
When enabled, the rx_syncstatus
asserts high immediately after the deserializer has completed slipping the bits to achieve word alignment. When it is not selected, rx_syncstatus
asserts after the cycle slip operation is complete and the word alignment pattern is detected by the
PCS (i.e. rx_patterndetect
is asserted). This parameter is only applicable when the selected protocol is CPRI (Auto).
Enables the rx_std_wa_patternalign
port. When the word aligner is configured in manual mode and when this signal is enabled, the word aligner aligns to next incoming word alignment pattern.
Enables the optional port.
rx_std_wa_a1a2size
control input
Enables the optional output port.
rx_std_bitslipboundarysel
status
Enables the rx_bitslip
port. This port is shared between the Standard PCS and Enhanced PCS.
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Table 36.
Bit Reversal and Polarity Inversion
Parameter
Enable TX bit reversal
Enable TX byte reversal
Enable TX polarity inversion
Enable tx_polinv port
Enable RX bit reversal
Enable rx_std_bitrev_ena port
Enable RX byte reversal
Enable rx_std_byterev_ena port
Enable RX polarity inversion
Enable rx_polinv port
Enable rx_std_signaldetect port
Range
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
Description
When you turn on this option, the 8B/10B Encoder reverses TX parallel data before transmitting it to the PMA for serialization.
The transmitted TX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. During the operation of the circuit, this setting can be changed through dynamic reconfiguration.
When you turn on this option, the 8B/10B Encoder reverses the byte order before transmitting data. This function allows you to reverse the order of bytes that were erroneously swapped. The
PCS can swap the ordering of either one of the 8- or 10-bit words, when the PCS/PMA interface width is 16 or 20 bits. This option is not valid under certain Transceiver configuration
rules.
When you turn on this option, the tx_std_polinv
port controls polarity inversion of TX parallel data to the PMA. When you turn on this parameter, you also need to turn on the Enable
tx_polinv port.
When you turn on this option, the tx_polinv
input control port is enabled. You can use this control port to swap the positive and negative signals of a serial differential link, if they were erroneously swapped during board layout.
When you turn on this option, the word aligner reverses RX parallel data. The received RX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB.
This setting can be changed through dynamic reconfiguration.
When you enable Enable RX bit reversal, you must also enable
Enable rx_std_bitrev_ena port.
When you turn on this option and assert the rx_std_bitrev_ena
control port, the RX data order is reversed. The normal order is LSB to MSB. The reverse order is
MSB to LSB.
When you turn on this option, the word aligner reverses the byte order, before storing the data in the RX FIFO. This function allows you to reverse the order of bytes that are erroneously swapped.
The PCS can swap the ordering of either one of the 8- or 10-bit words, when the PCS / PMA interface width is 16 or 20 bits. This option is not valid under certain Transceiver configuration
rules.
When you enable Enable RX byte reversal, you must also select the Enable rx_std_byterev_ena port.
When you turn on this option and assert the rx_std_byterev_ena
input control port, the order of the individual 8- or 10-bit words received from the PMA is swapped.
When you turn on this option, the rx_std_polinv
port inverts the polarity of RX parallel data. When you turn on this parameter, you also need to enable Enable rx_polinv port.
When you turn on this option, the rx_polinv
input is enabled.
You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout.
When you turn on this option, the optional rx_std_signaldetect
output port is enabled. This signal is required for the PCI Express protocol. If enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect continued...
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Parameter Range Description threshold voltage that you specified. You can specify the signal detect threshold using a Quartus Prime Assignment Editor or by modifying the Quartus Settings File (.qsf)
Table 37.
PCIe Ports
Parameter
Enable PCIe dynamic datarate switch ports
Enable PCIe pipe_hclk_in and pipe_hclk_out ports
Enable PCIe Gen3 analog control ports
Enable PCIe electrical idle control and status ports
Enable PCIe pipe_rx_polarity port
Range
On / Off
On / Off
On / Off
On / Off
On / Off
Related Information
•
•
2.4.6. PCS Direct
Table 38.
PCS Direct Datapath Parameters
Parameter
PCS Direct interface width
Range
8, 10, 16, 20, 32, 40, 64
Description
When you turn on this option, the pipe_rate
, pipe_sw
, and pipe_sw_done
ports are enabled. You should connect these ports to the PLL IP core instance in multi-lane PCIe Gen2 and Gen3 configurations. The pipe_sw
and pipe_sw_done available for multi-lane bonded configurations.
ports are only
When you turn on this option, the pipe_hclk_in
, and pipe_hclk_out
ports are enabled. The pipe_hclk_in
port must be connected to the PLL IP core instance for the PCI Express configurations. The pipe_hclk_out
port can be left floating when you connect tx_clkout
to the MAC clock input.
When you turn on this option, the pipe_g3_txdeemph
and pipe_g3_rxpresenthint ports are enabled. You can use these ports for equalization for Gen3 configurations.
When you turn on this option, the pipe_rx_eidleinfersel
and pipe_rx_elecidle
ports are enabled. These ports are used for
PCI Express configurations.
When you turn on this option, the control port is enabled. You can use this option to control channel signal polarity for PCI Express configurations. When the Standard
PCS is configured for PCIe, the assertion of this signal inverts the
RX bit polarity. For other Transceiver configuration rules the optional rx_polinv pipe_rx_polarity
input
port inverts the polarity of the RX bit stream.
Description
Specifies the data interface width between the PLD and the transceiver PMA.
2.4.7. Dynamic Reconfiguration Parameters
Dynamic reconfiguration allows you to change the behavior of the transceiver channels and PLLs without powering down the device.
Each transceiver channel and PLL includes an Avalon-MM slave interface for reconfiguration. This interface provides direct access to the programmable address space of each channel and PLL. Because each channel and PLL includes a dedicated
Avalon-MM slave interface, you can dynamically modify channels either concurrently or sequentially. If your system does not require concurrent reconfiguration, you can parameterize the Transceiver Native PHY IP to share a single reconfiguration interface.
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You can use dynamic reconfiguration to change many functions and features of the transceiver channels and PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths.
To enable Intel Arria 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options:
• Enable dynamic reconfiguration
• Enable Altera Debug Master Endpoint
• Enable capability registers
• Enable control and status registers
• Enable PRBS (Pseudo Random Binary Sequence) soft accumulators
Table 39.
Dynamic Reconfiguration
Parameter
Enable dynamic reconfiguration
Share reconfiguration interface
Value
On/Off
On/Off
Enable Altera Debug
Master Endpoint
Separate reconfig_waitrequest from the status of
AVMM arbitration with
PreSICE
On/Off
On/Off
Description
When you turn on this option, the dynamic reconfiguration interface is enabled.
When you turn on this option, the Transceiver Native PHY IP presents a single Avalon-MM slave interface for dynamic reconfiguration for all channels. In this configuration, the upper
[n-1:10] address bits of the reconfiguration address bus specify the channel. The channel numbers are binary encoded. Address bits [9:0] provide the register offset address within the reconfiguration space for a channel.
When you turn on this option, the Transceiver Native PHY IP includes an embedded Altera Debug Master Endpoint (ADME) that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the Share reconfiguration interface option for configurations using more than one channel.
When enabled, the reconfig_waitrequest
does not indicate the status of AVMM arbitration with PreSICE. The AVMM arbitration status is reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled.
Table 40.
Optional Reconfiguration Logic
Parameter
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Enable PRBS (Pseudo
Random Binary
Sequence) soft accumulators
Value
On/Off
Description
Enables capability registers that provide high level information about the configuration of the transceiver channel.
User-defined Sets a user-defined numeric identifier that can be read from the user_identifier
offset when the capability registers are enabled.
On/Off
On/Off
Enables soft registers to read status signals and write control signals on the
PHY interface through the embedded debug.
Enables soft logic for performing PRBS bit and error accumulation when the hard PRBS generator and checker are used.
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Table 41.
Configuration Files
Parameter
Configuration file prefix
Generate
SystemVerilog package file
Generate C header file
Generate MIF (Memory
Initialization File)
Include PMA analog settings in configuration files
Value
<prefix>
On/Off
On/Off
On/Off
On/Off
Description
Here, the file prefix to use for generated configuration files is specified. Each variant of the Transceiver Native PHY IP should use a unique prefix for configuration files.
When you turn on this option, the Transceiver Native PHY IP generates a SystemVerilog package file,
reconfig_parameters.sv. This file contains parameters defined with the attribute values required for reconfiguration.
When you turn on this option, the Transceiver Native PHY IP generates a C header file, reconfig_parameters.h. This file contains macros defined with the attribute values required for reconfiguration.
When you turn on this option, the Transceiver Native PHY IP generates a MIF, reconfig_parameters.mif. This file contains the attribute values required for reconfiguration in a data format.
When enabled, the IP allows you to configure the PMA analog settings that are selected in the Analog PMA settings (Optional) tab. These settings are included in your generated configuration files.
Note: You must still specify the analog settings for your current configuration using Quartus Prime Setting File (.qsf) assignments in Quartus. This option does not remove the requirement to specify Quartus Prime Setting File (.qsf) assignments for your analog settings. Refer to the Analog
Parameter Settings chapter in the Arria 10 Transceiver PHY
User Guide for details on using the QSF assignments.
Table 42.
Parameter
Enable multiple reconfiguratio n profiles
Enable embedded reconfiguratio n streamer
Generate reduced reconfiguratio n files
Number of reconfiguratio n profiles
Selected reconfiguratio n profile
Configuration Profiles
Value
On/Off
On/Off
On/Off
1-8
0-7
Description
When enabled, you can use the GUI to store multiple configurations. This information is used by Quartus to include the necessary timing arcs for all configurations during timing driven compilation. The Native PHY generates reconfiguration files for all of the stored profiles. The Native PHY also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them. Among other things this checks that you have exposed the same ports for each configuration.
(28)
Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles. This is optional and increases logic utilization. The PHY includes all of the logic and data necessary to dynamically reconfigure between pre-configured profiles.
When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles. The reconfiguration time decreases with the use of reduced .mif files.
Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Selects which reconfiguration profile to store/load/clear/refresh, when clicking the relevant button for the selected profile.
continued...
(28) For more information on timing closure, refer to the Reconfiguration Interface and Dynamic
Reconfiguration chapter.
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Parameter
Store configuration to selected profile
Load configuration from selected profile
Clear selected profile
Value
-
-
Description
Clicking this button saves or stores the current Native PHY parameter settings to the profile specified by the Selected reconfiguration profile parameter.
Clicking this button loads the current Native PHY with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter.
Clicking this button clears or erases the stored Native PHY parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY.
Clicking this button clears the Native PHY parameter settings for all the profiles.
Clear all profiles
Refresh selected profile
-
Clicking this button is equivalent to clicking the Load configuration from selected
profile and Store configuration to selected profile buttons in sequence. This operation loads the Native PHY parameter settings from stored profile specified by the
Selected reconfiguration profile parameter and subsequently stores or saves the parameters back to the profile.
Table 43.
Analog PMA Settings (Optional) for Dynamic Reconfiguration
Parameter
TX Analog PMA Settings
Analog Mode (Load Intelrecommended Default settings)
Cei_11100_lr to xfp_9950
Override Intel-recommended
Analog Mode Default settings
On/Off
Output Swing Level (VOD)
Pre-Emphasis First Pre-Tap
Polarit
Pre-Emphasis First Pre-Tap
Magnitude
Pre-Emphasis Second Pre-
Tap Polarity
Pre-Emphasis Second Pre-
Tap Magnitude
0-31
Value
Fir_pre_1t_neg
Fir_pre_1t_pos
0-16 (29)
Fir_pre_2t_neg
Fir_pre_2t_pos
0-7 (30)
Description
Selects the analog protocol mode to pre-select the
TX pin swing settings (VOD, Pre-emphasis, and
Slew Rate). After loading the pre-selected values in the GUI, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intel-recommended defaults to individually modify the settings.
Enables the option to override the Intelrecommended settings for the selected TX Analog
Mode for one or more TX analog parameters.
Selects the transmitter programmable output differential voltage swing.
Selects the polarity of the first pre-tap for preemphasis.
Selects the magnitude of the first pre-tap for preemphasis
Selects the polarity of the second pre-tap for preemphasis.
Selects the magnitude of the second pre-tap for pre-emphasis.
continued...
(29) For more information refer to Available Options table in the
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T section of the Analog Parameter
Settings chapter.
(30) For more information refer to Available Options table in the
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T section of the Analog Parameter
Settings chapter.
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Parameter
Pre-Emphasis First Post-Tap
Polarity
Pre-Emphasis First Post-Tap
Magnitude
Pre-Emphasis Second Post-
Tap Polarity
Pre-Emphasis Second Post-
Tap Magnitude
Slew Rate Control
Fir_post_1t_neg
Fir_post_1t_pos
0-25 (31)
Value
Fir_post_2t_neg
Fir_post_2t_pos
0-12 (32) slew_r0
to slew_r5
High-Speed Compensation Enable/Disable
Description
Selects the polarity of the first post-tap for preemphasis
Selects the magnitude of the first post-tap for pre-emphasis.
Selects the polarity of the second post-tap for pre-emphasis.
Selects the magnitude of the second post-tap for pre-emphasis
Selects the slew rate of the TX output signal. Valid values span from slowest to the fastest rate.
Enables the power-distribution network (PDN) induced inter-symbol interference (ISI) compensation in the TX driver. When enabled, it reduces the PDN induced ISI jitter, but increases the power consumption.
Selects the on-chip TX differential termination.
On-Chip termination r_r1 r_r2
RX Analog PMA settings
Override Intel-recommended
Default settings
On/Off
CTLE (Continuous Time
Linear Equalizer) mode non_s1_mode
S1_mode
DC gain control of high gain mode CTLE
AC Gain Control of High Gain
Mode CTLE
No_dc_gain
to stg4_gain7 radp_ctle_acgain_4s_0
to radp_ctle_acgain_4s_28
AC Gain Control of High Data
Rate Mode CTLE radp_ctle_eqz_1s_sel_0
to
Radp_ctle_eqz_1s_sel_15
Variable Gain Amplifier
(VGA) Voltage Swing Select radp_vga_sel_0
to radp_vga_sel_7
Decision Feedback Equalizer
(DFE) Fixed Tap 1 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 2 Coefficient radp_dfe_fxtap1_0
to radp_dfe_fxtap1_127 radp_dfe_fxtap2_0 to radp_dfe_fxtap2_127
Enables the option to override the Intelrecommended settings for one or more RX analog parameters
Selects between the RX high gain mode non_s1_mode
or RX high data rate mode s1_mode
for the Continuous Time Linear
Equalizer (CTLE).
Selects the DC gain of the Continuous Time Linear
Equalizer (CTLE) in high gain mode
Selects the AC gain of the Continuous Time Linear
Equalizer (CTLE) in high gain mode when CTLE is in manual mode.
Selects the AC gain of the Continuous Time Linear
Equalizer (CTLE) in high data rate mode when
CTLE is in manual mode.
Selects the Variable Gain Amplifier (VGA) output voltage swing when both the CTLE and DFE blocks are in manual mode
Selects the co-efficient of the fixed tap 1 of the
Decision Feedback Equalizer (DFE) when operating in manual mode
Selects the co-efficient of the fixed tap 2 of the
Decision Feedback Equalizer (DFE) when operating in manual mode continued...
(31) For more information refer to Available Options table in the
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP section of the Analog Parameter
Settings chapter.
(32) For more information refer to Available Options table in the
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP section of the Analog Parameter
Settings chapter.
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Parameter
Decision Feedback Equalizer
(DFE) Fixed Tap 3 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 4 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 5 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 6 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 7 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 8 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 9 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 10 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 11 Coefficient
On-Chip termination
Value radp_dfe_fxtap3_0
to radp_dfe_fxtap3_127 radp_dfe_fxtap4_0
to radp_dfe_fxtap4_63 radp_dfe_fxtap5_0
to radp_dfe_fxtap5_63 radp_dfe_fxtap6_0
to radp_dfe_fxtap6_31 radp_dfe_fxtap7_0
to radp_dfe_fxtap7_31 radp_dfe_fxtap8_0
to radp_dfe_fxtap8_31 radp_dfe_fxtap9_0
to radp_dfe_fxtap9_31 radp_dfe_fxtap10_0
to radp_dfe_fxtap10_31 radp_dfe_fxtap11_0
to radp_dfe_fxtap11_31
R_ext0, r_r1, r_r2
Description
Selects the co-efficient of the fixed tap 3 of the
Decision Feedback Equalizer (DFE) when operating in manual mode.
Selects the co-efficient of the fixed tap 4 of the
Decision Feedback Equalizer (DFE) when operating in manual mode.
Selects the co-efficient of the fixed tap 5 of the
Decision Feedback Equalizer (DFE) when operating in manual mode.
Selects the co-efficient of the fixed tap 6 of the
Decision Feedback Equalizer (DFE) when operating in manual mode.
Selects the co-efficient of the fixed tap 7 of the
Decision Feedback Equalizer (DFE) when operating in manual mode.
Selects the co-efficient of the fixed tap 8 of the
Decision Feedback Equalizer (DFE) when operating in manual mode.
Selects the co-efficient of the fixed tap 9 of the
Decision Feedback Equalizer (DFE) when operating in manual mode.
Selects the co-efficient of the fixed tap 10 of the
Decision Feedback Equalizer (DFE) when operating in manual mode.
Selects the co-efficient of the fixed tap 11 of the
Decision Feedback Equalizer (DFE) when operating in manual mode.
Selects the on-chip RX differential termination.
Table 44.
Generation Options
Parameter
Generate parameter documentation file
Value
On/Off
Description
When you turn on this option, generation produces a Comma-
Separated Value (.csv ) file with descriptions of the Transceiver
Native PHY IP parameters.
Related Information
•
Analog Parameter Settings on page 585
•
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T on page 602
•
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T on page 602
•
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
on page 603
•
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
on page 604
•
Reconfiguration Interface and Dynamic Reconfiguration
on page 502
•
Transmitter Pre-Emphasis First Pre-Tap Value
on page 600
•
Transmitter Pre-Emphasis Second Pre-Tap Value
on page 600
•
Transmitter Pre-Emphasis First Post-Tap Value on page 601
•
Transmitter Pre-Emphasis Second Post-Tap Value
on page 601
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2.4.8. PMA Ports
This section describes the PMA and calibration ports for the Arria 10 Transceiver Native
PHY IP core.
The following tables, the variables represent these parameters:
• <n>—The number of lanes
• <d>—The serialization factor
• <s>—The symbol size
• <p>—The number of PLLs
Table 45.
TX PMA Ports
Name tx_serial_data[<n>
-1:0]
Direction
Input tx_serial_clk0
Input
Clock Domain
N/A
Clock tx_bonding_clocks[
<n><6>-1:0] tx_serial_clk1 tx_serial_clk2 tx_serial_clk3 tx_serial_clk4 tx_analog_reset_ac k tx_pma_clkout
Input
Inputs
Output
Output
Clock
Clocks
Asynchronous
Clock
Description
This is the serial data output of the TX PMA.
This is the serial clock from the TX PLL. The frequency of this clock depends on the data rate and clock division factor. This clock is for non bonded channels only. For bonded channels use the tx_bonding_clocks
clock TX input.
This is a 6-bit bus which carries the low speed parallel clock per channel. These clocks are outputs from the master CGB.
Use these clocks for bonded channels only.
Optional Ports
These are the serial clocks from the TX PLL. The frequency of these clocks depends on the data rate and clock division factor. These additional ports are enabled when you specify more than one TX PLL.
tx_pma_div_clkout tx_pma_iqtxrx_clko u t tx_pma_elecidle[<n
>-1:0]
Output
Output
Input
Clock
Clock
Asynchronous
Enables the optional tx_pma_analog_reset_ack
output.
This port should not be used for register mode data transfers
This clock is the low speed parallel clock from the TX PMA. It is available when you turn on Enable tx_pma_clkout port in the Transceiver Native PHY IP core Parameter Editor. (33)
If you specify a tx_pma_div_clkout
division factor of 1 or
2, this clock output is derived from the PMA parallel clock
(low speed parallel clock). If you specify a tx_pma_div_clkout
division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the TX FIFO runs at a different rate than the PMA parallel clock frequency, such as
66:40 applications.
This port is available if you turn on Enable tx_
pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the TX PMA output clock to the input of a PLL.
When you assert this signal, the transmitter is forced to electrical idle. This port has no effect when you configure the transceiver for the PCI Express protocol.
continued...
(33) This clock is not to be used to clock the FPGA - transceiver interface. This clock may be used as a reference clock to an external clock cleaner.
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Name tx_pma_qpipullup[< n>-1:0] tx_pma_qpipulldn[< n>-1:0] tx_pma_txdetectrx[
<n>-1:0] tx_pma_rxfound[<n>
-1:0] rx_seriallpbken[<n
>-1:0]
Direction
Input
Input
Input
Output
Input
Clock Domain
Asynchronous
Asynchronous
Asynchronous
Synchronous to rx_coreclkin
or rx_clkout
based on the configuration.
Asynchronous
Description
This port is available if you turn on Enable
tx_pma_qpipullup port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick Path
Interconnect (QPI) applications.
This port is available if you turn on Enable
tx_pma_qpipulldn port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick Path
Interconnect (QPI) applications.
This port is available if you turn on Enable
tx_pma_txdetectrx port (QPI) in the Transceiver Native
PHY IP core Parameter Editor. When asserted, the receiver detect block in TX PMA detects the presence of a receiver at the other end of the channel. After receiving the tx_pma_txdetectrx
request, the receiver detect block initiates the detection process. Use this port for Quick Path
Interconnect (QPI) applications only.
This port is available if you turn on Enable
tx_rxfound_pma port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. When asserted, indicates that the receiver detect block in TX PMA has detected a receiver at the other end of the channel. Use this port for Quick Path
Interconnect (QPI) applications only.
This port is available if you turn on Enable rx_seriallpbken port in the Transceiver Native PHY IP core Parameter
Editor. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal can be enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation.
Table 46.
RX PMA Ports
Name rx_serial_data[<n>
-1:0]
Direction
Input rx_cdr_refclk0
Input rx_cdr_refclk1
– rx_cdr_refclk4 rx_analog_reset_ac k rx_pma_clkout rx_pma_div_clkout
Input
Output
Output
Output
Clock Domain
N/A
Description
Specifies serial data input to the RX PMA.
Clock
Clock
Specifies reference clock input to the RX clock data recovery
(CDR) circuitry.
Optional Ports
Specifies reference clock inputs to the RX clock data recovery
(CDR) circuitry.
Asynchronous
Clock
Clock
Enables the optional rx_pma_analog_reset_ack output. This port should not be used for register mode data transfers.
This clock is the recovered parallel clock from the RX CDR circuitry.
The deserializer generates this clock. This is used to drive core logic, PCS-to-FPGA fabric interface, or both. If you specify a
rx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock (low speed parallel clock). If you specify a rx_pma_div_clkout division factor of
33, 40, or 66, this clock is derived from the PMA serial clock.
This clock is commonly used when the interface to the RX FIFO runs at a different rate than the PMA parallel clock (low speed parallel clock) frequency, such as 66:40 applications.
continued...
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Name rx_pma_iqtxrx_clko ut rx_pma_clkslip rx_pma_qpipulldn[< n>-1:0] rx_is_lockedtodat a[<n>-1:0] rx_is_lockedtoref[
<n>-1:0] rx_set_locktodata[
<n>-1:0] rx_set_locktoref[< n>-1:0] rx_seriallpbken[<n
>-1:0]
Direction
Output
Clock Domain
Clock
Output Clock
Description
This port is available if you turn on Enable rx_
pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the RX PMA output clock to the input of a PLL.
When asserted, indicates that the deserializer has either skipped one serial bit or paused the serial clock for one cycle to achieve word alignment. As a result, the period of the parallel clock could be extended by 1 unit interval (UI) during the clock slip operation.
This port is only used for Quick Path Interconnect (QPI) applications.
When asserted, indicates that the CDR PLL is locked to the incoming data, rx_serial_data
.
When asserted, indicates that the CDR PLL is locked to the input reference clock.
This port provides manual control of the RX CDR circuitry.
rx_prbs_done[<n>-1
:0] rx_prbs_err[<n>-1:
0] rx_prbs_err_clr[<n
>-1:0]
Input
Output
Output
Input
Asynchronous rx_coreclkin or rx_clkout rx_coreclkin or rx_clkout rx_coreclkin or rx_clkout
This port is available if you turn on Enable rx_ seriallpbken
port in the Transceiver Native PHY IP core Parameter Editor.
The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal is enabled in
Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation.
When asserted, indicates the verifier has aligned and captured consecutive PRBS patterns and the first pass through a polynomial is complete.
When asserted, indicates an error only after the rx_prbs_done
signal has been asserted. This signal gets asserted for three parallel clock cycles for every error that occurs. Errors can only occur once per word.
When asserted, clears the PRBS pattern and deasserts the rx_prbs_done
signal.
Table 47.
Calibration Status Ports
Name tx_cal_busy[<n>-1:0]
Direction
Output
Clock Domain
Asynchronous rx_cal_busy[<n>-1:0]
Input
Output
Output
Input
Input
Output
Asynchronous rx_clkout rx_clkout
Asynchronous
Asynchronous This port provides manual control of the RX CDR circuitry.
Asynchronous
Description
When asserted, indicates that the initial TX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed. You must hold the channel in reset until calibration completes.
When asserted, indicates that the initial RX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed.
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Table 48.
Reset Ports
Name tx_analogreset[<n>-1:
0]
Direction
Input tx_digitalreset[<n>-1
:0]
Input rx_analogreset[<n>-1:
0]
Input rx_digitalreset[<n>-1
:0]
Input
Clock Domain (34)
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Description
Resets the analog TX portion of the transceiver
PHY.
Resets the digital TX portion of the transceiver
PHY.
Resets the analog RX portion of the transceiver
PHY.
Resets the digital RX portion of the transceiver
PHY.
2.4.9. Enhanced PCS Ports
Figure 24.
Enhanced PCS Interfaces
The labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.
Arria 10 Transceiver Native PHY tx_cal_busy rx_cal_busy
Nios Hard
Calibration IP
Reconfiguration
Registers reconfig_reset reconfig_clk reconfig_avmm
TX PMA TX Enhanced PCS
Serial Data
Clocks
QPI
Optional Ports
Serializer
TX Parallel Data, Control, Clocks
Enhanced PCS TX FIFO
Interlaken Frame Generator tx_serial_clk0
(from TX PLL)
Serial Data
Optional Ports
CDR Control
QPI
Clocks
Clock
Generation
Block
RX PMA
CDR Deserializer
RX Enhanced PCS
In the following tables, the variables represent these parameters:
• <n>—The number of lanes
• <d>—The serialization factor
• <s>— The symbol size
• <p>—The number of PLLs tx_analog_reset rx_analog_reset
RX Parallel Data, Control, Clocks
Enhanced PCS RX FIFO
Interlaken Frame Synchronizer
10GBASE-R BER Checker
Bitslip
(34) Although the reset ports are not synchronous to any clock domain, Intel recommends that you synchronize the reset ports with the system clock.
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Table 49.
Enhanced TX PCS: Parallel Data, Control, and Clocks
Name tx_parallel_data[
<n>128-1:0] unused_tx_paralle l_data tx_control[<n><3>
-1:0]
or tx_control[<n><18
>-1:0] unused_tx_contro l[<n> <15>-1:0]
Direction
Input
Input
Input
Input
Clock Domain
Synchronous to the clock driving the write side of the FIFO
( tx_coreclkin or
tx_clkout
) tx_clkout
Synchronous to the clock driving the write side of the FIFO
( tx_coreclkin or
tx_clkout
)
Synchronous to the clock driving the write side of the FIFO
( tx_coreclkin or
tx_clkout
)
Description
TX parallel data inputs from the FPGA fabric to the TX PCS. If you select Enable simplified interface in the Transceiver
Native PHY IP Parameter Editor, tx_parallel_data includes only the bits required for the configuration you specify.
You must ground the data pins that are not active. For single width configuration, the following bits are active:
• 32-bit FPGA fabric to PCS interface width: tx_parallel_data[31:0]. Ground [127:32].
• 40-bit FPGA fabric to PCS interface width: tx_parallel_data[39:0]. Ground [127:40].
• 64-bit FPGA fabric to PCS interface width: tx_parallel_data[63:0] Ground [127:64].
For double width configuration, the following bits are active:
• 40-bit FPGA fabric to PCS interface width: data[103:64],
[39:0]. Ground [127:104], [63:40].
• 64-bit FPGA fabric to PCS interface width: data[127:64],
[63:0].
Double-width mode is not supported for 32-bit, 50-bit, and 67bit FPGA fabric to PCS interface widths.
Port is enabled, when you enable Enable simplified data
interface. Connect all of these bits to 0. When Enable
simplified data interface is disabled, the unused bits are a part of tx_parallel_data
. Refer to identify the bits you need to ground.
tx_parallel_data
to tx_control
bits have different functionality depending on the transceiver configuration rule selected. When Simplified data
interface is enabled, the number of bits in this bus change because the unused bits are shown as part of the unused_tx_control
port.
Refer to Enhanced PCS TX and RX Control Ports on page 83
section for more details.
This port is enabled when you enable Enable simplified data
interface. Connect all of these bits to 0. When Enable
simplified data interface is disabled, the unused bits are a part of the tx_control
.
Refer to tx_control
to identify the bits you need to ground.
tx_err_ins
Input tx_coreclkin
For the Interlaken protocol, you can use this bit to insert the synchronous header and CRC32 errors if you have turned on
Enable simplified data interface.
When asserted, the synchronous header for that cycle word is replaced with a corrupted one. A CRC32 error is also inserted if
Enable Interlaken TX CRC-32 generator error insertion is turned on. The corrupted sync header is 2'b00 for a control word, and 2'b11 for a data word. For CRC32 error insertion, the word used for CRC calculation for that cycle is incorrectly inverted, causing an incorrect CRC32 in the Diagnostic Word of the Metaframe.
Note that a synchronous header error and a CRC32 error cannot be created for the Framing Control Words because the
Frame Control Words are created in the frame generator continued...
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Name tx_coreclkin tx_clkout
Direction
Input
Output
Clock Domain
Clock
Clock
Description embedded in TX PCS. Both the synchronous header error and the CRC32 errors are inserted if the CRC-32 error insertion feature is enabled in the Transceiver Native PHY IP GUI.
The FPGA fabric clock. Drives the write side of the TX FIFO. For the Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32. Using frequency lower than this range can cause the TX FIFO to underflow and result in data corruption.
This is a parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configurations. This clocks the blocks of the TX Enhanced PCS.
The frequency of this clock is equal to the datarate divided by
PCS/PMA interface width.
Table 50.
Enhanced RX PCS: Parallel Data, Control, and Clocks
Name rx_parallel_data[<n
>128-1:0] unused_rx_parallel_ data rx_control[<n>
<20>-1:0] unused_rx_control[<
n>10-1:0]
Direction Clock Domain
Output Synchronous to the clock driving the read side of the FIFO
( rx_coreclk in
or rx_clkout
)
Output
Output
Output rx_clkout
Synchronous to the clock driving the read side of the FIFO
( rx_coreclk in
or rx_clkout
)
Synchronous to the clock driving the read side of the FIFO
Description
RX parallel data from the RX PCS to the FPGA fabric. If you select, Enable simplified data interface in the Transceiver
Native PHY IP GUI, rx_parallel_data interface is 128 bits wide.
includes only the bits required for the configuration you specify. Otherwise, this
When FPGA fabric to PCS interface width is 64 bits, the following bits are active for interfaces less than 128 bits. You can leave the unused bits floating or not connected.
• 32-bit FPGA fabric to PCS width: data[31:0].
• 40-bit FPGA fabric to PCS width: data[39:0].
• 64-bit FPGA fabric to PCS width: data[63:0].
When the FPGA fabric to PCS interface width is 128 bits, the following bits are active:
• 40-bit FPGA fabric to PCS width: data[103:64], [39:0].
• 64-bit FPGA fabric to PCS width: data[127:0].
This signal specifies the unused data when you turn on Enable
simplified data interface. When simplified data interface is not set, the unused bits are a part of
You can leave the unused data outputs floating or not connected.
rx_parallel_data
.
Indicates whether the data.
rx_parallel_data
bus is control or
Refer to the Enhanced PCS TX and RX Control Ports on page
83 section for more details.
These signals only exist when you turn on Enable simplified
data interface. When simplified data interface is not set, the unused bits are a part of left floating.
rx_control
. These outputs can be continued...
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Name rx_coreclkin rx_clkout
Direction Clock Domain
Input
( rx_coreclk in
or rx_clkout
)
Clock
Output Clock
Description
The FPGA fabric clock. Drives the read side of the RX FIFO. For
Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32.
The low speed parallel clock recovered by the transceiver RX
PMA, that clocks the blocks in the RX Enhanced PCS. The frequency of this clock is equal to data rate divided by
PCS/PMA interface width.
Table 51.
Enhanced PCS TX FIFO
Name tx_enh_data_valid[<n>-
1:0]
Direction
Input tx_enh_fifo_full[<n>-1
:0]
Output tx_enh_fifo_pfull[<n>-
1:0]
Output tx_enh_fifo_empty[<n>-
1:0]
Output tx_enh_fifo_pempty[<n>
-1:0]
Output
Clock Domain
Synchronous to the clock driving the write side of the FIFO
( tx_coreclkin or
tx_clkout
)
Synchronous to the clock driving the write side of the FIFO
( tx_coreclkin or
tx_clkout
)
Synchronous to the clock driving the write side of the FIFO tx_coreclkin or
tx_clkout
Synchronous to the clock driving the write side of the FIFO tx_coreclkin or
tx_clkout
Synchronous to the clock driving the write side of the FIFO tx_coreclkin or
tx_clkout
Description
Assertion of this signal indicates that the TX data is valid.
Connect this signal to 1'b1 for 10GBASE-R without 1588.
For 10GBASE-R with 1588, you must control this signal based on the gearbox ratio. For Basic and Interlaken, you need to control this port based on TX FIFO flags so that the FIFO does not underflow or overflow.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
Assertion of this signal indicates the TX FIFO is full.
Because the depth is always constant, you can ignore this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
This signal gets asserted when the TX FIFO reaches its partially full threshold. Because the depth is always constant, you can ignore this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
When asserted, indicates that the TX FIFO is empty. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
When asserted, indicates that the TX FIFO has reached its specified partially empty threshold. When you turn this option on, the Enhanced PCS enables the tx_enh_fifo_pempty
port, which is asynchronous. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 297 for
more details.
Table 52.
Enhanced PCS RX FIFO
Name rx_enh_data_valid[<n>
-1:0]
Direction
Output
Clock Domain
Synchronous to the clock driving the read side of
Description
When asserted, indicates that rx_parallel_data valid. Discard invalid RX parallel data
is when rx_enh_data_valid
signal is low.
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rx_enh_fifo_full[<n>-
1:0] rx_enh_fifo_pfull[<n>
-1:0] rx_enh_fifo_empty[<n>
-1:0] rx_enh_fifo_pempty[<n
>-1:0] rx_enh_fifo_del[<n>-1
:0] rx_enh_fifo_insert[<n
>-1:0]
-1:0]
Name rx_enh_fifo_rd_en[<n> rx_enh_fifo_align_va l[<n>-1:0]
Direction
Output
Output
Output
Output
Output
Output
Output
Input
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout
Synchronous to the clock driving the read side of
Clock Domain the FIFO rx_coreclkin or rx_clkout
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout
Description
This option is available when you select the following parameters:
• Enhanced PCS Transceiver configuration rules specifies Interlaken
• Enhanced PCS Transceiver configuration rules specifies Basic, and RX FIFO mode is Phase compensation
• Enhanced PCS Transceiver configuration rules specifies Basic, and RX FIFO mode is Register
Refer to
on page 297 for more details.
When asserted, indicates that the RX FIFO is full. This signal gets asserted for 2 to 3 clock cycles.Because
the depth is always constant, you can ignore this signal for the phase compensation mode.
Refer to
on page 297 for more details.
When asserted, indicates that the RX FIFO has reached its specified partially full threshold. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.
Refer to
on page 297 for more details.
When asserted, indicates that the RX FIFO is empty.
Because the depth is always constant, you can ignore this signal for the phase compensation mode.
Refer to
on page 297 for more details.
When asserted, indicates that the RX FIFO has reached its specified partially empty threshold.
Because the depth is always constant, you can ignore this signal for the phase compensation mode.
Refer to
on page 297 for more details.
When asserted, indicates that a word has been deleted from the RX FIFO. This signal gets asserted for 2 to 3 clock cycles. This signal is used for the 10GBASE-R protocol.
When asserted, indicates that a word has been inserted into the RX FIFO. This signal is used for the
10GBASE-R protocol.
For Interlaken only, when this signal is asserted, a word is read form the RX FIFO. You need to control this signal based on RX FIFO flags so that the FIFO does not underflow or overflow.
When asserted, indicates that the word alignment pattern has been found. This signal is only valid for the Interlaken protocol.
continued...
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Name rx_enh_fifo_align_cl r[<n>-1:0]
Direction
Input
Clock Domain the FIFO rx_coreclkin or rx_clkout
Synchronous to the clock driving the read side of the FIFO rx_coreclkin or rx_clkout
Description
When asserted, the FIFO resets and begins searching for a new alignment pattern. This signal is only valid for the Interlaken protocol. Assert this signal for at least 4 cycles.
Table 53.
Interlaken Frame Generator, Synchronizer, and CRC32
Name tx_enh_frame[<n>-1:0] tx_enh_frame_diag_stat us[<n> 2-1:0] tx_enh_frame_burst_en[
<n>-1:0] rx_enh_frame[<n>-1:0] rx_enh_frame_lock[<n>-
1:0] rx_enh_frame_diag_stat us[2 <n>-1:0] rx_enh_crc32_err[<n>-1
:0]
Direction Clock Domain
Output tx_clkout
Input
Input
Output
Output
Output
Output tx_clkout tx_clkout rx_clkout rx_clkout rx_clkout rx_clkout
Description
Asserted for 2 or 3 parallel clock cycles to indicate the beginning of a new metaframe.
Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This message is inserted into the next diagnostic word generated by the frame generator block. This bus must be held constant for 5 clock cycles before and after the following encodings are defined: tx_enh_frame
pulse. The
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
If Enable frame burst is enabled, this port controls frame generator data reads from the TX FIFO to the frame generator. It is latched once at the beginning of each
Metaframe. If the value of tx_enh_frame_burst_en
is 0, the frame generator does not read data from the TX FIFO for current Metaframe. Instead, the frame generator inserts
SKIP words as the payload of Metaframe. When tx_enh_frame_burst_en
is 1, the frame generator reads data from the TX FIFO for the current Metaframe. This port must be held constant for 5 clock cycles before and after the tx_enh_frame
pulse.
When asserted, indicates the beginning of a new received
Metaframe. This signal is pulse stretched.
When asserted, indicates the Frame Synchronizer state machine has achieved Metaframe delineation. This signal is pulse stretched.
Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This signal is latched when a valid diagnostic word is received in the end of the
Metaframe while the frame is locked. The following encodings are defined:
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
When asserted, indicates a CRC error in the current
Metaframe. Asserted at the end of current Metaframe. This signal gets asserted for 2 or 3 cycles.
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Table 54.
10GBASE-R BER Checker
Name rx_enh_highber[<n>-1:0
] rx_enh_highber_clr_cn t[<n>-1:0]
Direction
Output
Input rx_enh_clr_errblk_coun t[<n>-1:0]
(10GBASE-R and FEC)
Input
Clock Domain rx_clkout rx_clkout rx_clkout
Description
When asserted, indicates a bit error rate that is greater than 10 -4 . For the 10GBASE-R protocol, this BER rate occurs when there are at least 16 errors within 125 µs.
This signal gets asserted for 2 to 3 clock cycles.
When asserted, clears the internal counter that indicates the number of times the BER state machine has entered the BER_BAD_SH state.
When asserted the error block counter resets to 0.
Assertion of this signal clears the internal counter that counts the number of times the RX state machine has entered the
RX_E
state. In modes where the FEC block is enabled, the assertion of this signal resets the status counters within the RX FEC block.
Table 55.
Block Synchronizer
Name rx_enh_blk_lock<n>-1:0
]
Direction Clock Domain
Output rx_clkout
Description
When asserted, indicates that block synchronizer has achieved block delineation. This signal is used for
10GBASE-R and Interlaken.
Table 56.
Gearbox
Name rx_bitslip[<n>-1:0] tx_enh_bitslip[<n>-1:0
]
Direction Clock Domain
Input rx_clkout
Input rx_clkout
Description
The
rx_parallel_data
slips 1 bit for every positive edge of the rx_bitslip
input. Keep the minimum interval between rx_bitslip
pulses to at least 20 cycles. The maximum shift is < pcswidth -1> bits, so that if the PCS is
64 bits wide, you can shift 0-63 bits.
The value of this signal controls the number of bits to slip the tx_parallel_data
before passing to the PMA.
Table 57.
KR-FEC
Name Direction tx_enh_frame[<n>-1:0]
Output rx_enh_frame[<n>-1:0]
Output rx_enh_frame_diag_stat us
Output
Clock Domain tx_clkout rx_clkout rx_clkout
Description
Asynchronous status flag output of TX KR-FEC that signifies the beginning of generated KR FEC frame
Asynchronous status flag output of RX KR-FEC that signifies the beginning of received KR FEC frame
Asynchronous status flag output of RX KR-FEC that indicates the status of the current received frame.
• 00: No error
• 01: Correctable Error
• 10: Un-correctale error
• 11: Reset condition/pre-lock condition
Related Information
•
on page 354
•
•
on page 362
•
on page 535
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•
Transceiver PHY Reset Controller Interfaces
on page 437
2.4.9.1. Enhanced PCS TX and RX Control Ports
This section describes the protocol configurations.
tx_control
and rx_control
bit encodings for different
When Enable simplified data interface is ON, all of the unused ports shown in the tables below, appear as a separate port. For example: It appears as unused_tx_control
/ unused_rx_control
port.
Enhanced PCS TX Control Port Bit Encodings
Table 58.
Name tx_control
Bit Encodings for Interlaken
Bit
[1:0]
Functionality
Synchronous header
[2] Inversion control
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
A logic low indicates that the built-in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity.
[7:3]
[8]
Unused
Insert synchronous header error or
CRC32
You can use this bit to insert synchronous header error or CRC32 errors. The functionality is similar to tx_err_ins
. Refer to tx_err_ins description for more details.
signal
[17:9] Unused
Table 59.
Name tx_control
Bit Encodings for 10GBASE-R , 10GBASE-KR with FEC
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[17:8]
Functionality
XGMII control signal for parallel_data[7:0]
XGMII control signal for parallel_data[15:8]
XGMII control signal for parallel_data[23:16]
XGMII control signal for
parallel_data[31:24]
XGMII control signal for parallel_data[39:32]
XGMII control signal for parallel_data[47:40]
XGMII control signal for parallel_data[55:48]
XGMII control signal for
parallel_data[63:56]
Unused
Table 60.
Name tx_control
Bit Encodings for Basic Single Width Mode
For basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Bit
[1:0]
Functionality
Synchronous header
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[17:2] Unused
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Table 61.
Name tx_control
Bit Encodings for Basic Double Width Mode
For basic double width mode, the total word length is 66-bit with 128-bit data and 4-bit synchronous header.
Bit
[1:0]
Functionality
Synchronous header
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[8:2]
[10:9]
Unused
Synchronous header The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[17:11] Unused
Table 62.
Name tx_control
Bit Encodings for Basic Mode
In this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.
Bit
[1:0]
[2]
Functionality
Synchronous header
Inversion control
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
A logic low indicates that built-in disparity generator block in the Enhanced PCS maintains the running disparity.
Enhanced PCS RX Control Port Bit Encodings
Table 63.
Name rx_control
Bit Encodings for Interlaken
Bit
[1:0]
Functionality
Synchronous header
[2]
[3]
[4]
[5]
[6]
[7]
Inversion control
Payload word location
Synchronization word location
Scrambler state word location
SKIP word location
Diagnostic word location
Description
The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
A logic low indicates that the builtin disparity generator block in the
Enhanced PCS maintains the
Interlaken running disparity. In the current implementation, this bit is always tied logic low (1'b0).
A logic high (1'b1) indicates the payload word location in a metaframe.
A logic high (1'b1) indicates the synchronization word location in a metaframe.
A logic high (1'b1) indicates the scrambler word location in a metaframe.
A logic high (1'b1) indicates the
SKIP word location in a metaframe.
A logic high (1'b1) indicates the diagnostic word location in a metaframe.
continued...
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Name
[8]
Bit
[9]
Functionality
Synchronization header error, metaframe error, or CRC32 error status
Block lock and frame lock status
[19:10] Unused
Table 64.
Name rx_control
Bit Encodings for 10GBASE-R , 10GBASE-KR with FEC
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[19:8]
Functionality
XGMII control signal for parallel_data[7:0]
XGMII control signal for parallel_data[15:8]
XGMII control signal for parallel_data[23:16]
XGMII control signal for
parallel_data[31:24]
XGMII control signal for parallel_data[39:32]
XGMII control signal for parallel_data[47:40]
XGMII control signal for parallel_data[55:48]
XGMII control signal for parallel_data[63:56]
Unused
Description
A logic high (1'b1) indicates synchronization header error, metaframe error, or CRC32 error status.
A logic high (1'b1) indicates that block lock and frame lock have been achieved.
Table 65.
Name rx_control
Bit Encodings for Basic Single Width Mode
For basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Bit
[1:0]
Functionality
Synchronous header
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[7:2]
[9:8]
Unused
Synchronous header error status The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[19:10] Unused
Table 66.
Name rx_control
Bit Encodings for Basic Double Width Mode
For basic double width mode, total word length is 66-bit with 128-bit data, and 4-bit synchronous header.
Bit
[1:0]
Functionality
Synchronous header
Description
The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
[7:2]
[8]
Unused
Synchronous header error status
[9]
[11:10]
Block lock is achieved
Synchronous header
Active-high status signal that indicates a synchronous header error.
Active-high status signal indicating when block lock is achieved.
The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
continued...
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Name Bit
[17:12]
[18]
Functionality
Unused
Synchronous header error status
Description
[19] Block lock is achieved
Active-high status signal that indicates a synchronous header error.
Active-high status signal indicating when Block
Lock is achieved.
Table 67.
Name rx_control
Bit Encodings for Basic Mode
In this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.
Bit
[1:0]
[2]
Functionality
Synchronous header
Inversion control
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
A logic low indicates that built-in disparity generator block in the Enhanced PCS maintains the running disparity.
2.4.10. Standard PCS Ports
Figure 25.
Transceiver Channel using the Standard PCS Ports
Standard PCS ports appear if either one of the transceiver configuration modes is selected that uses Standard
PCS or if Data Path Reconfiguration is selected even if the transceiver configuration is not one of those that uses Standard PCS.
Arria 10 Transceiver Native PHY tx_cal_busy rx_cal_busy
Nios Hard
Calibration IP
Reconfiguration
Registers reconfig_reset reconfig_clk reconfig_avmm
TX PMA TX Standard PCS
Serial Data
Clocks
QPI
PCIe
Optional Ports
Serializer
Parallel Data, Control, Clocks
TX FIFO
8B/10B Encoder/Decoder
PCIe tx_serial_clk0
(from TX PLL)
Serial Data
Optional Ports
CDR Control
QPI
Clocks
PRBS
Clock
Generation
Block
RX PMA
CDR Deserializer
RX Standard PCS tx_analog_reset rx_analog_reset
Parallel Data, Control, Clocks
RX FIFO
Rate Match FIFO
Word Aligner & Bitslip
PCIe
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In the following tables, the variables represent these parameters:
• <n>—The number of lanes
• <w>—The width of the interface
• <d>—The serialization factor
• <s>— The symbol size
• <p>—The number of PLLs
Table 68.
TX Standard PCS: Data, Control, and Clocks
Name tx_parallel_data[<n>
128-1:0]
Direction
Input
Clock Domain tx_clkout
Description
TX parallel data input from the FPGA fabric to the TX PCS.
unused_tx_parallel_d ata tx_coreclkin tx_clkout
Input
Input
Output tx_clkout
Clock
Clock
This signal specifies the unused data when you turn on
Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of tx_parallel_data
. Connect all these bits to 0. If you do not connect the unused data bits to 0, then TX parallel data may not be serialized correctly by the Native PHY IP core.
The FPGA fabric clock. This clock drives the write port of the
TX FIFO.
This is the parallel clock generated by the local CGB for non bonded configurations, and master CGB for bonded configuration. This clocks the
FPGA fabric to the TX PCS.
tx_parallel_data
from the
Table 69.
RX Standard PCS: Data, Control, Status, and Clocks rx_parallel_data[<n>
128-1:0]
Name unused_rx_parallel_da ta rx_clkout rx_coreclkin
Direction Clock Domain
Output Synchronous to the clock driving the read side of the FIFO
( rx_coreclk in or rx_clkout
)
Output
Output
Synchronous to the clock driving the read side of the FIFO
( rx_coreclk in or rx_clkout
)
Clock
Input Clock
Description
RX parallel data from the RX PCS to the FPGA fabric. For each 128-bit word of rx_parallel_data
, the data bits correspond to rx_parallel_data[7:0]
when 8B/10B decoder is enabled and rx_parallel_data[9:0]
8B/10B decoder is disabled.
when
This signal specifies the unused data when you turn on
Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of rx_parallel_data
. These outputs can be left floating.
The low speed parallel clock recovered by the transceiver RX
PMA, that clocks the blocks in the RX Standard PCS.
RX parallel clock that drives the read side clock of the RX
FIFO.
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Table 70.
Standard PCS FIFO
Name tx_std_pcfifo_full[<n
>-1:0]
Direction
Output tx_std_pcfifo_empty[< n>-1:0]
Output rx_std_pcfifo_full[<n
>-1:0]
Output rx_std_pcfifo_empty[< n>-1:0]
Output
Clock Domain
Synchronous to the clock driving the write side of the FIFO
( tx_coreclki n or tx_clkout
)
Synchronous to the clock driving the write side of the FIFO
( tx_coreclki n or tx_clkout
)
Synchronous to the clock driving the read side of the FIFO
( rx_coreclki n or rx_clkout
)
Synchronous to the clock driving the read side of the FIFO
( rx_coreclki n or rx_clkout
)
Description
Indicates when the standard TX FIFO is full.
Indicates when the standard TX FIFO is empty.
Indicates when the standard RX FIFO is full.
Indicates when the standard RX FIFO is empty.
Table 71.
Rate Match FIFO
Name rx_std_rmfifo_full[<n
>-1:0]
Direction Clock Domain
Output Asynchronous rx_std_rmfifo_empty[< n>-1:0] rx_rmfifostatus[<n>-1
:0]
Output
Output
Asynchronous
Asynchronous
Description
Rate match FIFO full flag. When asserted the rate match
FIFO is full. You must synchronize this signal. This port is only used for GigE mode.
Rate match FIFO empty flag. When asserted, match FIFO is empty. You must synchronize this signal. This port is only used for GigE mode.
Indicates FIFO status. The following encodings are defined:
• 2'b00: Normal operation
• 2'b01: Deletion, rx_std_rmfifo_full = 1
• 2'b10: Insertion, rx_std_rmfifo_empty = 1
• 2'b11: Full. rx_rmfifostatus
is a part of rx_parallel_data
. rx_rmfifostatus
corresponds to rx_parallel_data[14:13]
.
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Table 72.
tx_datak
8B/10B Encoder and Decoder
Name tx_forcedisp[<n>(<w>/
<s>-1:0] tx_dispval[<n>(<w>/
<s>-1:0] rx_datak[<n><w>/
<s>-1:0] rx_errdetect[<n><w>/
<s>-1:0] rx_disperr[<n><w>/
<s>-1:0] rx_runningdisp[<n><w>
/<s>-1:0] rx_patterndetect[<n>< w>/<s>-1:0]
Direction Clock Domain
Input tx_clkout
Input
Input
Output
Output
Output
Output
Output
Asynchronous
Asynchronous rx_clkout
Synchronous to the clock driving the read side of the
FIFO
( rx_coreclki n or rx_clkout
)
Description tx_datak
is exposed if 8B/10B enabled and simplified data interface is set.When 1, indicates that the 8B/10B encoded word of tx_parallel_data is control. When 0, indicates that the 8B/10B encoded word of tx_parallel_data
is data.
tx_datak
is a part of tx_parallel_data
when simplified data interface is not set.
This signal allows you to force the disparity of the 8B/10B encoder. When "1", forces the disparity of the output data to the value driven on tx_dispval running disparity continues.
. When "0", the current tx_forcedisp
is a part of tx_parallel_data
. tx_forcedisp
corresponds to tx_parallel_data[9]
.
Specifies the disparity of the data. When 0, indicates positive disparity, and when 1, indicates negative disparity.
tx_dispval
is a part of tx_parallel_data
. tx_dispval corresponds to tx_dispval[10]
.
rx_datak
is exposed if 8B/10B is enabled and simplified data interface is set. When 1, indicates that the 8B/10B decoded word of rx_parallel_data is control. When 0, indicates that the 8B/10B decoded word of rx_parallel_data
is data. rx_datak
is a part of rx_parallel_data
when simplified data interface is not set.
When asserted, indicates a code group violation detected on the received code group. Used along with rx_disperr signal to differentiate between code group violation and disparity errors. The following encodings are defined for rx_errdetect/rx_disperr
:
• 2'b00: no error
• 2'b10: code group violation
• 2'b11: disparity error. rx_errdetect
is a part of rx_parallel_data
. For each 128-bit word, rx_errdetect
corresponds to rx_parallel_data[9]
.
When asserted, indicates a disparity error on the received code group. rx_disperr
is a part of rx_parallel_data
.
For each 128-bit word, rx_disperr
corresponds to rx_parallel_data[11]
.
Synchronous to the clock driving the read side of the
FIFO
( rx_coreclki n or rx_clkout
)
Synchronous to the clock driving the read side of the
FIFO
( rx_coreclki n or rx_clkout
)
Asynchronous
When high, indicates that rx_parallel_data
was received with negative disparity. When low, indicates that rx_parallel_data
was received with positive disparity.
rx_runningdisp
is a part of rx_parallel_data
. For each 128 bit word, rx_runningdisp
corresponds to rx_parallel_data[15]
.
When asserted, indicates that the programmed word alignment pattern has been detected in the current word boundary. rx_patterndetect
is a part of continued...
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Name rx_syncstatus[<n><w>/
<s>-1:0]
Direction Clock Domain
Output Asynchronous
Description rx_parallel_data
. For each 128-bit word, rx_patterndetect
corresponds to rx_parallel_data[12]
.
When asserted, indicates that the conditions required for synchronization are being met.
rx_syncstatus
is a part of rx_parallel_data
. For each 128-bit word, rx_syncstatus
corresponds to
rx_parallel_data[10]
.
Table 73.
Word Aligner and Bitslip
Name tx_std_bitslipboundary sel[5 <n>-1:0]
Direction Clock Domain
Input Asynchronous rx_std_bitslipboundary sel[5 <n>-1:0]
Output Asynchronous rx_std_wa_patternalig n[<n>-1:0] rx_std_wa_a1a2size[<n>
-1:0]
Input rx_bitslip[<n>-1:0]
Input
Input
Synchronous to rx_clkout
Asynchronous
Asynchronous
Description
Bitslip boundary selection signal. Specifies the number of bits that the TX bit slipper must slip.
This port is used in deterministic latency word aligner mode.
This port reports the number of bits that the RX block slipped. This port values should be taken into consideration in either Deterministic Latency Mode or Manual Mode of
Word Aligner.
Active when you place the word aligner in manual mode. In manual mode, you align words by asserting rx_std_wa_patternalign
. When the PCS-PMA Interface width is 10 bits, rx_std_wa_patternalign
is level sensitive. For all the other PCS-PMA Interface widths, rx_std_wa_patternalign
is positive edge sensitive.
You can use this port only when the word aligner is configured in manual or deterministic latency mode.
When the word aligner is in manual mode, and the PCS-PMA interface width is 10 bits, this is a level sensitive signal. In this case, the word aligner monitors the input data for the word alignment pattern, and updates the word boundary when it finds the alignment pattern.
For all other PCS-PMA interface widths, this signal is edge sensitive.This signal is internally synchronized inside the
PCS using the PCS parallel clock and should be asserted for at least 2 clock cycles to allow synchronization.
Used for the SONET protocol. Assert when the A1 and A2 framing bytes must be detected. A1 and A2 are SONET backplane bytes and are only used when the PMA data width is 8 bits.
Used when word aligner mode is bitslip mode. When the
Word Aligner is in either Manual (PLD controlled),
Synchronous State Machine or Deterministic Latency ,the rx_bitslip signal
is not valid and should be tied to 0.
For every rising edge of the rx_std_bitslip earliest received bit from the received data.
signal, the word boundary is shifted by 1 bit. Each bitslip removes the
Table 74.
Bit Reversal and Polarity Inversion
Name rx_std_byterev_ena[<n>
-1:0]
Direction Clock Domain
Input Asynchronous rx_std_bitrev_ena[<n>-
1:0]
Input Asynchronous
Description
This control signal is available when the PMA width is 16 or
20 bits. When asserted, enables byte reversal on the RX interface. Used if the MSB and LSB of the transmitted data are erroneously swapped.
When asserted, enables bit reversal on the RX interface. Bit order may be reversed if external transmission circuitry transmits the most significant bit first. When enabled, the continued...
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Name tx_polinv[<n>-1:0] rx_polinv[<n>-1:0] rx_std_signaldetect[<n
>-1:0]
Direction Clock Domain
Input
Input
Output
Asynchronous
Asynchronous
Asynchronous
Description receive circuitry receives all words in the reverse order. The bit reversal circuitry operates on the output of the word aligner.
When asserted, the TX polarity bit is inverted. Only active when TX bit polarity inversion is enabled.
When asserted, the RX polarity bit is inverted. Only active when RX bit polarity inversion is enabled.
When enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage. You can specify the signal detect threshold using a Quartus Prime
Settings File (.qsf) assignment. This signal is required for the PCI Express, SATA and SAS protocols.
Related Information
•
on page 354
•
•
on page 362
•
on page 535
•
Transceiver PHY Reset Controller Interfaces
on page 437
•
Analog Parameter Settings on page 585
2.4.11. IP Core File Locations
When you generate your Transceiver Native PHY IP, the Quartus ® Prime software generates the HDL files that define your instance of the IP. In addition, the Quartus
Prime software generates an example Tcl script to compile and simulate your design in the ModelSim* simulator. It also generates simulation scripts for Synopsys* VCS,
Aldec* Active-HDL, Aldec Riviera-Pro, and Cadence* Incisive Enterprise.
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Figure 26.
Directory Structure for Generated Files
<Project Directory>
<your_ip_or_system_name>.qsys - Top-level IP variation file
<your_ip_or_system_name>.sopcinfo
<your_ip_name> - IP core variation files
<your_ip_name>.cmp - VHDL component declaration file
<your_ip_name>_bb - Verilog HDL black-box EDA synthesis file
<your_ip_name>_inst - IP instantiation template file
<your_ip_name>.ppf - XML I/O pin information file
<your_ip_name>.qip - Lists IP synthesis files
<your_ip_name>.sip - Lists files for simulation
<your_ip_name>.v or .vhd - Greybox timing netlist sim - IP simulation files
<your_ip_name>.v or .vhd - Top-level simulation file
aldec- Simulator setup scripts cadence - Simulator setup scripts mentor - Simulator setup scripts synopsys - Simulator setup scripts
synth - IP synthesis files
<your_ip_name>.v or .vhd - Top-level IP synthesis file
<IP subcore> - IP subcore files sim
<HDL files> synth
<HDL files>
The following table describes the directories and the most important files for the parameterized Transceiver Native PHY IP core and the simulation environment. These files are in clear text.
Table 75.
Transceiver Native PHY Files and Directories
File Name
<project_dir>
<your_ip_name> .v or .vhd
<your_ip_name> .qip
Description
The top-level project directory.
The top-level design file.
A list of all files necessary for Quartus Prime compilation.
continued...
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<your_ip_name> .bsf
File Name
<project_dir>/<your_ip_name>/
<project_dir>/sim
<project_dir>/sim/aldec
<project_dir>/sim/cadence
<project_dir>/sim/mentor
<project_dir>/sim/synopsys
<project_dir>/synth
Description
A Block Symbol File (.bsf) for your Transceiver Native PHY instance.
The directory that stores the HDL files that define the
Transceiver Native PHY IP.
The simulation directory.
Simulation files for Riviera-PRO simulation tools.
Simulation files for Cadence simulation tools.
Simulation files for Mentor simulation tools.
Simulation files for Synopsys simulation tools.
The directory that stores files used for synthesis.
The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the following simulators:
• ModelSim SE
• Synopsys VCS MX
• Cadence NCSim
If you select VHDL for your transceiver PHY, only the wrapper generated by the
Quartus Prime software is in VHDL. All the underlying files are written in Verilog or
SystemVerilog. To enable simulation using a VHDL-only ModelSim license, the underlying Verilog and SystemVerilog files for the Transceiver Native PHY IP are encrypted so that they can be used with the top-level VHDL wrapper without using a mixed-language simulator.
For more information about simulating with ModelSim, refer to the Mentor Graphics
ModelSim and QuestaSim Support chapter in volume 3 of the Quartus Prime
Handbook.
The Transceiver Native PHY IP cores do not support the NativeLink feature in the
Quartus Prime software.
Related Information
•
Simulating the Transceiver Native PHY IP Core on page 325
• Mentor Graphics ModelSim and QuestaSim Support
2.4.12. Unused Transceiver RX Channels
To prevent performance degradation of unused transceiver RX channels over time, the following assignments must be added to an Arria 10 device QSF. You can either use a global assignment or per-pin assignments.
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON or set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to pin_name
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When you perform this procedure, the Intel Quartus Prime software instantiates the clock data recovery (CDR) PLL corresponding to each unused receiver channel. The
CDR uses
CLKUSR
as reference clock and is configured to run at 1 Gbps. To use
CLKUSR
as reference clock, the pin must be assigned a 100- to 125 MHz clock. When you implement these assignments, it causes a power consumption increase per receiver channel. Please contact your local support center for details.
Related Information
Unused/Idle Clock Line Requirements on page 389
2.4.13. Unsupported Features
Native PHY should not be included in QXP.
2.5. Interlaken
Interlaken is a scalable, channelized chip-to-chip interconnect protocol.
The key advantages of Interlaken are scalability and low I/O count compared to earlier protocols such as SPI 4.2. Other key features include flow control, low overhead framing, and extensive integrity checking. Interlaken operates on 64-bit data words and 3 control bits, which are striped round-robin across the lanes. The protocol accepts packets on 256 logical channels and is expandable to accommodate up to
65,536 logical channels. Packets are split into small bursts that can optionally be interleaved. The burst semantics include integrity checking and per logical channel flow control.
The Interlaken interface is supported with 1 to 48 lanes running at data rates up to
12.5 Gbps per lane on Arria 10 devices. Interlaken is implemented using the Enhanced
PCS. The Enhanced PCS has demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers.
Arria 10 devices provide three preset variations for Interlaken in the Arria 10
Transceiver Native PHY IP Parameter Editor:
• Interlaken 10x12.5 Gbps
• Interlaken 1x6.25 Gbps
• Interlaken 6x10.3 Gbps
Depending on the line rate, the enhanced PCS can use a PMA to PCS interface width of
32, 40, or 64 bits.
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Figure 27.
Transceiver Channel Datapath and Clocking for Interlaken
This figure assumes the serial data rate is 12.5 Gbps and the PMA width is 40 bits.
Transmitter PMA Transmitter Enhanced PCS
40
64 bits data +
3 bits control
FPGA
Fabric
186.57 MHz to 312.5MHz
tx_clkout
PRBS
Generator
PRP
Generator
Parallel Clock (312.5 MHz)
KR FEC TX G KR FEC Scr KR FEC Enc
Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout rx_pma_div_clkout
64 bits data +
3 bits control
40
Div 40
PRBS
Verifier
Parallel Clock (312.5 MHz)
PRP
Verifier
10GBASE-R
BER Checker
186.57 MHz to 312.5MHz
KR FEC Block S KR FEC Dec
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clocks
(6.25 GHz) =
Data rate/2
ATX PLL fPLL
CMU PLL
Serial Clock
Input Reference Clock
Related Information
• Interlaken Protocol Definition v1.2
• Interlaken Look-Aside Protocol Definition, v1.1
2.5.1. Metaframe Format and Framing Layer Control Word
The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words.
However, for stability and performance, Intel recommends you set the frame length to no less than 128 words. In simulation, use a smaller metaframe length to reduce simulation times. The payload of a metaframe could be pure data payload and a
Burst/Idle control word from the MAC layer.
rx_clkout
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Figure 28.
Framing Layer Metaframe Format
Metaframe Length
Control and
Data Words
The framing control words include:
• Synchronization (SYNC)—for frame delineation and lane alignment (deskew)
• Scrambler State (SCRM)—to synchronize the scrambler
• Skip (SKIP)—for clock compensation in a repeater
• Diagnostic (DIAG)—provides per-lane error check and optional status message
To form a metaframe, the Enhanced PCS frame generator inserts the framing control words and encapsulates the control and data words read from the TX FIFO as the metaframe payload.
Figure 29.
Interlaken Synchronization and Scrambler State Words Format
bx10 b011110 bx10 b001010
66 63 58 57 h0F678F678F678F6
Scrambler State
0
Figure 30.
Interlaken Skip Word Format
bx10 b000111
66 63 h21E
58 57 h1E
48 47 40 h1E h1E h1E h1E h1E
0
The DIAG word is comprised of a status field and a CRC-32 field. The 2-bit status is defined by the Interlaken specification as:
• Bit 1 (Bit 33): Lane health
— 1: Lane is healthy
— 0: Lane is not healthy
• Bit 0 (Bit 32): Link health
— 1: Link is healthy
— 0: Link is not healthy
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The tx_enh_frame_diag_status[1:0]
input from the FPGA fabric is inserted into the Status field each time a DIAG word is created by the framing generator.
Figure 31.
Interlaken Diagnostic Word
bx10 b011001
66 63 58 57 h000000
34
Status
33 32 31
CRC32
0
2.5.2. Interlaken Configuration Clocking and Bonding
The Arria 10 Interlaken PHY layer solution is scalable and has flexible data rates. You can implement a single lane link or bond up to 48 lanes together. You can choose a lane data rate up to 17.4 Gbps for GX devices and 25.8 Gbps for GT devices. You can also choose between different reference clock frequencies, depending on the PLL used to clock the transceiver. Refer to the Arria 10 Device Datasheet for the minimum and maximum data rates that Arria 10 transceivers can support at different speed grades.
You can use an ATX PLL or fPLL to provide the clock for the transmit channel. An ATX
PLL has better jitter performance compared to an fPLL. You can use the CMU PLL to clock only the non-bonded Interlaken transmit channels. However, if you use the CMU
PLL, you lose one RX transceiver channel.
For the multi-lane Interlaken interface, TX channels are usually bonded together to minimize the transmit skew between all bonded channels. Currently, xN bonding and
PLL feedback compensation bonding schemes are available to support a multi-lane
Interlaken implementation. If the system tolerates higher channel-to-channel skew, you can choose to not bond the TX channels.
To implement bonded multi-channel Interlaken, all channels must be placed contiguously. The channels may all be placed in one bank (if not greater than six lanes) or they may span several banks.
Related Information
•
on page 398
For more information about implementing PLLs and clocks
• Arria 10 Device Datasheet
2.5.2.1. xN Clock Bonding Scenario
The following figure shows a xN bonding example supporting 10 lanes. Each lane is running at 12.5 Gbps. The first six TX channels reside in one transceiver bank and the other four TX channels reside in the adjacent transceiver bank. The ATX PLL provides the serial clock to the master CGB. The CGB then provides parallel and serial clocks to all of the TX channels inside the same bank and other banks through the xN clock network.
Because of xN clock network skew, the maximum achievable data rate decreases when TX channels span several transceiver banks.
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Figure 32.
10X12.5 Gbps xN Bonding
Transceiver PLL
Instance (6.25 GHz)
ATX PLL
Master
CGB xN
Native PHY Instance
(10 Ch Bonded 12.5 Gbps)
Transceiver Bank 1
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Transceiver Bank 2
TX Channel
TX Channel
TX Channel
TX Channel
Related Information
•
Implementing x6/xN Bonding Mode
on page 404
For detailed information on xN bonding limitations
•
on page 398
For more information about implementing PLLs and clocks
2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State
Machine
The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port signals are provided to the FPGA fabric. Connect these signals to the MAC layer as required by the protocol. Based on these FIFO status and control signals, you can implement the multi-lane deskew alignment state machine in the FPGA fabric to control the transceiver RX FIFO block.
Note: You must also implement the soft bonding logic to control the transceiver TX FIFO block.
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2.5.2.2.1. TX FIFO Soft Bonding
The MAC layer logic and TX soft bonding logic control the writing of the Interlaken word to the TX FIFO with tx_enh_data_valid
(functions as a TX FIFO write enable) by monitoring the TX FIFO flags ( tx_fifo_full
, tx_fifo_pfull
, tx_fifo_empty
, tx_fifo_pempty
, and so forth). On the TX FIFO read side, a read enable is controlled by the frame generator. If tx_enh_frame_burst_en
is asserted high, the frame generator reads data from the TX FIFO.
A TX FIFO pre-fill stage must be implemented to perform the TX channel soft bonding.
The following figure shows the state of the pre-fill process.
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Figure 33.
TX Soft Bonding Flow
Exit from tx_digitalreset
Deassert all lanes tx_enh_frame_burst_en
Assert all lanes tx_enh_data_valid
All lanes full?
yes
Deassert all lanes tx_enh_data_valid
no no
Any lane send new frame?
tx_enh_frame asserted?
yes
Wait for extra 16 tx_coreclkin cycles no
All lanes full?
yes
TX FIFO pre-fill completed
The following figure shows that after deasserting tx_digitalreset logic starts filling the TX FIFO until all lanes are full.
, TX soft bonding
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Figure 34.
TX FIFO Pre-fill (6-lane Interface)
Deassert tx_digitalreset
00 tx_digitalreset tx_enh_data_valid tx_enh_fifo_full tx_enh_fifo_pfull tx_enh_fifo_empty tx_enh_fifo_pempty tx_enh_fifo_cnt tx_enh_frame tx_enh_frame_burst_en
3f
00
00
00
3f
3f
000000
00
00
3f
00
3f
3f
1... 2... 3... 4... 5... 6... 7... 8... 9... a... b... c... d... e... ffffff
3f 00
00
Deassert burst_en for all Lanes and Fill
TX FIFO Until all Lane FIFOs Are Full
After the TX FIFO pre-fill stage completes, the transmit lanes synchronize and the MAC layer begins to send valid data to the transceiver’s TX FIFO. You must never allow the
TX FIFO to overflow or underflow. If it does, you must reset the transceiver and repeat the TX FIFO pre-fill stage.
For a single lane Interlaken implementation, TX FIFO soft bonding is not required. You can begin sending an Interlaken word to the TX FIFO after tx_digitalreset deasserts.
The following figure shows the MAC layer sending valid data to the Native PHY after the pre-fill stage. tx_enh_frame_burst_en
is asserted, allowing the frame generator to read data from the TX FIFO. The TX MAC layer can now control tx_enh_data_valid
and write data to the TX FIFO based on the FIFO status signals.
Figure 35.
MAC Sending Valid Data (6-lane Interface) tx_digitalreset tx_enh_data_valid tx_enh_fifo_full tx_enh_fifo_pfull tx_enh_fifo_empty tx_enh_fifo_pempty tx_enh_fifo_cnt tx_enh_frame tx_enh_frame_burst_en
00
00
3f
3f
00
00 ffffff
00
3f
3f 00
00
00
3f
3f
00
After the Pre-fill Stage, Assert burst_en.
The Frame Generator Reads Data from the TX FIFO for the Next Metaframe
The User Logic Asserts data_valid to Send Data to the TX FIFO Based on the FIFO Status
The TX FIFO
Writes Backpressure
2.5.2.2.2. RX Multi-lane FIFO Deskew State Machine
Add deskew logic at the receiver side to eliminate the lane-to-lane skew created at the transmitter of the link partner, PCB, medium, and local receiver PMA.
Implement a multi-lane alignment deskew state machine to control the RX FIFO operation based on available RX FIFO status flags and control signals.
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Figure 36.
State Flow of the RX FIFO Deskew
Exit from rx_digitalreset
Deassert all Lane’s rx_enh_fifo_rd_en
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All Lane’s rx_enh_fifo_pempty
Deasserted?
yes
no
Assert rx_enh_fifo_align_clr for at least 4 rx_coreclkin Cycles
All Lane’s rx_enh_fifo_pfull
Deasserted?
no
yes
RX FIFO Deskew
Completed
Each lane's rx_enh_fifo_rd_en
should remain deasserted before the RX FIFO deskew is completed. After frame lock is achieved (indicated by the assertion of rx_enh_frame_lock
; this signal is not shown in the above state flow), data is written into the RX FIFO after the first alignment word (SYNC word) is found on that channel. Accordingly, the RX FIFO partially empty flag ( rx_enh_fifo_pempty
) of that channel is asserted. The state machine monitors the rx_enh_fifo_pempty
and rx_enh_fifo_pfull
signals of all channels. If the rx_enh_fifo_pempty
signals from all channels deassert before any channels rx_enh_fifo_pfull
assert, which implies the SYNC word has been found on all lanes of the link, the MAC layer can start reading from all the RX FIFO by asserting rx_enh_fifo_rd_en
simultaneously.
Otherwise, if the rx_enh_fifo_pfull
signal of any channel asserts high before the rx_enh_fifo_pempty
signals deassertion on all channels, the state machine needs to flush the RX FIFO by asserting rx_enh_fifo_align_clr
high for 4 cycles and repeating the soft deskew process.
The following figure shows one RX deskew scenario. In this scenario, all of the RX
FIFO partially empty lanes are deasserted while the pfull lanes are still deasserted.
This indicates the deskew is successful and the FPGA fabric starts reading data from the RX FIFO.
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Figure 37.
RX FIFO Deskew
After deskew is successful, the user logic asserts rd_en for all lanes to start reading data from the RX FIFO.
rx_enh_fifo_full rx_enh_fifo_empty rx_enh_fifo_rd_en rx_enh_data_valid rx_enh_fifo_pfull rx_enh_fifo_pempty rx_enh_frame_lock
[5]
Each Lane Is
Frame-Locked in a Different
Cycle
[4]
[3]
[2]
[1]
[0] rx_enh_fifo_align_val rx_enh_fifo_align_clr
00
00
00
3f
00
00
00
3f
00 21 3b 3f
21
1e
3f
00
1e
3f
3f
00
3f data_valid is asserted, indicating that the RX FIFO is outputting valid data.
Deassertion of pempty of all lanes before any lane pfull goes high, which means the deskew is complete.
2.5.3. How to Implement Interlaken in Arria 10 Transceivers
You should be familiar with the Interlaken protocol, Enhanced PCS and PMA architecture, PLL architecture, and the reset controller before implementing the
Interlaken protocol PHY layer.
Arria 10 devices provide three preset variations for Interlaken in the IP Parameter
Editor:
• Interlaken 10x12.5 Gbps
• Interlaken 1x6.25 Gbps
• Interlaken 6x10.3 Gbps
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog
(Installed IP
➤
Library
➤
Interface Protocols
➤
Transceiver PHY
➤
Arria
10 Transceiver Native PHY).
Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
2. Select Interlaken from the Transceiver configuration rules list located under
Datapath Options, depending on which protocol you are implementing.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
Interlaken Transceiver Configuration Rules . Or you can use the protocol presets
described in Transceiver Native PHY Presets
. You can then modify the settings to meet your specific requirements.
4. Click Generate to generate the Native PHY IP (this is your RTL file).
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Figure 38.
Signals and Ports of Native PHY IP for Interlaken
Arria 10 Transceiver Native PHY tx_cal_busy rx_cal_busy tx_serial_data tx_serial_clk or tx_bonding_clocks[5:0]
(from TX PLL) rx_serialloopback rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref
Hard
Calibration Block
CDR
TX PMA
Serializer
RX PMA
Deserializer
32/40/64
32/40/64
Reconfiguration
Registers
TX Enhanced PCS
RX Enhanced PCS reconfig_reset reconfig_clk reconfig_avmm tx_digital_reset tx_clkout tx_coreclkin tx_control[17:0] (1) tx_parallel_data[127:0] (1) tx_enh_data_valid tx_enh_frame_burst_en tx_enh_frame_diag_status[1:0] tx_enh_frame tx_enh_fifo_cnt[3:0] tx_enh_fifo_full tx_enh_fifo_pfull tx_enh_fifo_empty tx_enh_fifo_pempty tx_analog_reset rx_analog_reset rx_digital_reset rx_clkout rx_coreclkin rx_parallel_data[127:0] (2) rx_control[19:0] (2) rx_enh_fifo_rd_en rx_enh_data_valid rx_enh_fifo_align_val rx_enh_fifo_align_clr rx_enh_frame rx_enh_fifo_cnt[3:0] rx_enh_fifo_full rx_enh_fifo_pfull rx_enh_fifo_empty rx_enh_fifo_pempty rx_enh_frame_diag_status[1:0] rx_enh_frame_lock rx_enh_crc32_err rx_enh_blk_lock
Notes:
(1) The width of tx_parallel_data and tx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then
tx_parallel_data = 64 bits and tx_control = 3 bits. The width shown here is without simplified interface.
(2) The width of rx_parallel_data and rx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then
rx_parallel_data = 64 bits and rx_control = 10 bits. The width shown here is without simplified interface.
5. Configure and instantiate your PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
7. Implement a TX soft bonding logic and an RX multi-lane alignment deskew state machine using fabric logic resources for multi-lane Interlaken implementation.
8. Connect the Native PHY IP to the PLL IP and the reset controller.
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Figure 39.
Connection Guidelines for an Interlaken PHY Design
This figure shows the connection of all these blocks in the Interlaken PHY design example available on the Intel
FPGA Wiki website.
For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic that is included in the design example. The white blocks are your test logic or MAC layer logic.
Reset
Controller
PLL and CGB Reset
PLL IP
TX/RX Analog/Digital Reset
TX Clocks
Pattern
Generator
Control and Status
TX Soft
Bonding
TX Data Stream
TX FIFO Status
TX FIFO Control
Arria 10
Transceiver
Native PHY
RX FIFO Status
RX FIFO Control
Pattern
Verifier
Control and Status
RX
Deskew
RX Data Stream
9. Simulate your design to verify its functionality.
Figure 40.
24 Lanes Bonded Interlaken Link, TX Direction
To show more details, three different time segments are shown with the same zoom level.
tx_ready
Asserted
Pre-Fill
Stage
Pre-Fill Completed
Assert burst_en for
All Lanes
Send Data
Based on
FIFO Flags pll_locked tx_analogreset tx_clkout[0] tx_clkout tx_digitalreset tx_ready[0] tx_ready tx_enh_data_valid[0] tx_enh_data_valid tx_enh_fifo_full tx_enh_frame[0] tx_enh_frame tx_enh_frame_burst_en[0] tx_enh_frame_burst_en tx_parallel_data tx_control tx_enh_fifo_empty tx_enh_fifo_pempty
24`h000000
24`h000000
24`... 24`hffffff
24`h000000
24`h000000
24`h000000
24`hffffff
24`h000000
24`hffffff 24`h000000
1536`h0123456789abcdef01234567
72`h249249249249249249
24`hffffff
24`hffffff
24`h000000
24`h000000
24`hffffff
24`...
24`h000000
24`h000000
24`hffffff
24`h000000
24`hffffff
24`h000...
24`h000000
24`h000000
1536`h0123456789abcdef01234567
72`h249249249249249249
24`h000000
24`h000000
24`h000000
24`h000000
24`hffffff
24`h000000
24`hffffff 24`h000000
24`h000000
24`hffffff
1536`h0123456789abcdef01234567
72`h249249249249249249
24`h000000
24`h000000
24`hffffff
24 lanes bonded Interlaken link, TX direction
24`h000000
1536`hbd212...
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Figure 41.
24 Lanes Bonded Interlaken Link, RX Direction
To show more details, three different time segments are shown with different zoom level.
rx_ready
Asserted
Some Lanes pfull Signal Is Asserted before All Lanes pempty is Deasserted;
RX Deskew Fails. Need to Realign
All Lanes pfull Low and All
Lanes pempty Deasserted
RX Deskew Complete rx_clkout[0] rx_digitalreset rx_ready rx_enh_blk_lock rx_enh_frame_lock rx_enh_fifo_pfull[0] rx_enh_fifo_pfull rx_enh_fifo_pempty rx_enh_fifo_align_clr rx_enh_fifo_align_val rx_enh_fifi_rd_en rx_enh_data_valid rx_parallel_data rx_control
24`hffffff
24`h000000
24`h000000
24`h000000
24`h000000
24`hffffff
24`h000000
24`h000000
24`h000000
24`h000000
1536`h0100009c0100
240`h0441104411044
24`h00...
24`hff...
24`h000000
24`hffffff
24`hffffff
24`h0...
24`h000001
24`h000000
24`hffffff
24`hffffff
24`hffffff
24`h000000
24`hffffff
24`h000000
24`h00...
24`h000000
24`h000000
24`hfffffe
24`h000001
24`h000000 24`h00..
24`hffffff
24`hffffff
24`h00..
1536`h0100009c0100009c0100009c0100009c0100009c0100009c0100009c01000
240`h044110441104404411044110441104411044110441104411044110441104411
24`h000000
24`hffffff
24`h000000
24`hffffff
24`h000000
24`h000000
1536`h01000...
240`h044110...
24`h000000
24`hffffff
24`h000000
24`h00..
24`hffffff
24`hffffff
24`h00..
24`hffffff
1536`h1e...
240`h90a... 240`h826...
Assert align_clr to Re-Align
Start Reading Data
Based on FIFO Flags
Related Information
•
Arria 10 Enhanced PCS Architecture
on page 461
For more information about Enhanced PCS architecture
•
Arria 10 PMA Architecture on page 447
For more information about PMA architecture
•
on page 398
For more information about implementing PLLs and clocks
•
PLL architecture and implementation details
•
Resetting Transceiver Channels
on page 416
Reset controller general information and implementation details
•
For detailed information about the available ports in the Interlaken protocol
2.5.4. Design Example
Intel provides a PHY layer-only design example to help you integrate an Interlaken
PHY into your complete design.
The TX soft bonding logic is included in the design example. Intel recommends that you integrate this module into your design.
The Interlaken Design Example is available on the Arria 10 Transceiver PHY Design
Examples Wiki page.
Note: The design examples on the Wiki page provide useful guidance for developing your own designs, but they are not guaranteed by Intel. Use them with caution.
Related Information
Interlaken Design Example
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2.5.5. Native PHY IP Parameter Settings for Interlaken
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Table 76.
General and Datapath Parameters
Parameter
Message level for rule violations
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Provide separate interface for each channel
Value error warning
Interlaken basic
TX / RX Duplex
TX Simplex
RX Simplex
1 to 96
Up to 17.4 Gbps for GX devices
(Depending on Enhanced PCS to PMA interface width selection)
On / Off
On / Off
On / Off
Table 77.
TX PMA Parameters
Parameter
TX channel bonding mode
PCS TX channel bonding master
Actual PCS TX channel bonding master
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Value
Not bonded
PMA-only bonding
PMA and PCS bonding
If TX channel bonding mode is set to PMA and PCS
bonding, then:
Auto, 0, 1, 2, 3 through [Number of data channels – 1]
If TX channel bonding mode is set to PMA and PCS
bonding, then:
0, 1, 2, 3 through [Number of data channels – 1]
If TX channel bonding mode is not bonded, then:
1, 2, 4, 8
If TX channel bonding mode is not bonded, then:
1, 2, 3, 4
0
On / Off
On / Off
When Enable tx_pma_div_clkout port is On, then:
Disabled, 1, 2, 33, 40, 66
On / Off
Off continued...
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Parameter
Enable tx_pma_qpipulldn port (QPI)
Enable tx_pma_txdetectrx port (QPI)
Enable tx_pma_rxfound port (QPI)
Enable rx_seriallpbken port
Table 78.
RX PMA Parameters
Parameter
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
DFE adaptation mode
Number of fixed dfe taps
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_pma_qpipulldn port (QPI)
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
Table 79.
Enhanced PCS Parameters
Parameter
Enhanced PCS / PMA interface width
FPGA fabric / Enhanced PCS interface width
Enable 'Enhanced PCS' low latency mode
Enable RX/TX FIFO double-width mode
TX FIFO mode
TX FIFO partially full threshold
TX FIFO partially empty threshold
Enable tx_enh_fifo_full port
Off
Off
Off
On / Off
Value
On / Off
Off
On / Off
On / Off
On / Off
On / Off
On / Off
Value
1 to 5
0 to 4
Select legal range defined by the Quartus Prime software
100, 300, 500, 1000
manual,
adaptation enabled, manual, disabled
3, 7, 11
On / Off
On / Off
When Enable rx_pma_div_clkout port is On, then:
Disabled, 1, 2, 33, 40, 66
Value
32, 40, 64
67
Allowed when the PMA interface width is 32 and preset variations for data rate is 10.3125 Gbps or 6.25 Gbps; otherwise Off
Off
Interlaken
8 to 15
1 to 8
On / Off continued...
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Parameter
Enable tx_enh_fifo_pfull port
Enable tx_enh_fifo_empty port
Enable tx_enh_fifo_pempty port
RX FIFO mode
RX FIFO partially full threshold
On / Off
On / Off
On / Off
Interlaken
Value from 10-29 (no less than pempty_threshold+8)
RX FIFO partially empty threshold 2 to 10
Enable RX FIFO alignment word deletion (Interlaken) On / Off
Enable RX FIFO control word deletion (Interlaken)
Enable rx_enh_data_valid port
On / Off
On / Off
Enable rx_enh_fifo_full port
Enable rx_enh_fifo_pfull port
Enable rx_enh_fifo_empty port
On / Off
On / Off
On / Off
Enable rx_enh_fifo_pempty port
Enable rx_enh_fifo_del port (10GBASE-R)
Enable rx_enh_fifo_insert port (10GBASE-R)
Enable rx_enh_fifo_rd_en port
Enable rx_enh_fifo_align_val port (Interlaken)
Enable rx_enh_fifo_align_clr port (Interlaken)
On / Off
Off
Off
On
On / Off
On
Table 80.
Interlaken Frame Generator Parameters
Parameter
Enable Interlaken frame generator
Frame generator metaframe length
Enable frame generator burst control
Enable tx_enh_frame port
Enable tx_enh_frame_diag_status port
Enable tx_enh_frame_burst_en port
On
On
On
Value
On
5 to 8192 (Intel recommends a minimum metaframe length of 128)
On
Table 81.
Interlaken Frame Synchronizer Parameters
Parameter
Enable Interlaken frame synchronizer
Frame synchronizer metaframe length
Enable rx_enh_frame port
Enable rx_enh_frame_lock port
Enable rx_enh_frame_diag_status port
Value
On
5 to 8192 (Intel recommends a minimum metaframe length of 128)
On
On / Off
On / Off
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Table 82.
Interlaken CRC-32 Generator and Checker Parameters
Parameter
Enable Interlaken TX CRC-32 generator
Enable Interlaken TX CRC-32 generator error insertion
Enable Interlaken RX CRC-32 checker
Enable rx_enh_crc32_err port
On
On / Off
On
On / Off
Value
Table 83.
Scrambler and Descrambler Parameters
Parameter
Enable TX scrambler (10GBASE-R / Interlaken)
TX scrambler seed (10GBASE-R / Interlaken)
Enable RX descrambler (10GBASE-R / Interlaken)
Value
On
0x1 to 0x3FFFFFFFFFFFFFF
On
Table 84.
Interlaken Disparity Generator and Checker Parameters
Parameter
Enable Interlaken TX disparity generator
Enable Interlaken RX disparity checker
Enable Interlaken TX random disparity bit
On
On
On / Off
Value
Table 85.
Block Sync Parameters
Parameter
Enable RX block synchronizer
Enable rx_enh_blk_lock port
On
On / Off
Value
Table 86.
Gearbox Parameters
Enable TX data bitslip
Parameter
Enable TX data polarity inversion
Enable RX data bitslip
Enable RX data polarity inversion
Enable tx_enh_bitslip port
Enable rx_bitslip port
Off
On / Off
Off
On / Off
Off
Off
Table 87.
Dynamic Reconfiguration Parameters
Parameter
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
On / Off
On / Off
On / Off
Value
Value continued...
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Parameter
Separate reconfig_waitrequest from the status of
AVMM arbitration with PreSICE
Enable capability registers
Set user-defined IP identifier:
Enable control and status registers
Enable prbs soft accumulators
Table 88.
Configuration Files Parameters
Parameter
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
Generate MIF (Memory Initialization File)
Include PMA analog settings in configuration files
On / Off
On / Off
0 to 255
On / Off
On / Off
—
On / Off
On / Off
On / Off
On / Off
Table 89.
Configuration Profiles Parameters
Parameter
Enable multiple reconfiguration profiles
Enable embedded reconfiguration streamer
Generate reduced reconfiguration files
Number of reconfiguration profiles
Selected reconfiguration profile
On / Off
On / Off
On / Off
1 to 8
1 to 7
Value
Value
Value
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
2.6. Ethernet
1G
10G
1G/10G
The Ethernet standard comprises many different PHY standards with variations in signal transmission medium and data rates. The 1G/10GbE and 10GBASE-KR PHY IP
Core enables Ethernet connectivity at 1 Gbps and 10 Gbps over backplanes. The
10GBASE-KR PHY IP is also known as the Backplane Ethernet PHY IP. It includes link training and auto negotiation to support the IEEE Backplane Ethernet standard.
Data Rate
• Gigabit Ethernet
• Gigabit Ethernet 1588
• 10GBASE-R
• 10GBASE-R 1588
• 10GBASE-R with KR FEC
• 10GBASE-KR PHY IP
1G/10G Ethernet PHY IP
Transceiver Configuration Rule/IP
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2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2
Gigabit Ethernet (GbE) is a high-speed local area network technology that provides data transfer rates of about 1 Gbps. GbE builds on top of the ethernet protocol, but increases speed tenfold over Fast Ethernet. IEEE 802.3 defines GbE as an intermediate
(or transition) layer that interfaces various physical media with the media access control (MAC) in a Gigabit Ethernet system. Gigabit Ethernet PHY shields the MAC layer from the specific nature of the underlying medium and is divided into three sublayers shown in the following figure.
Figure 42.
GbE PHY Connection to IEEE 802.3 MAC and RS
OSI
Reference
Model
Layers
LAN
CSMA/CD
LAYERS
Higher Layers
LLC (Logical Link Control) or other MAC Client
MAC Control (Optional)
Media Access Control (MAC)
Reconciliation
RECONCILIATION
Application
Presentation
Session
Transport
Network
Data Link
Physical
GMII
MDI
PCS
PMA
PMD
PHY
Sublayers
Medium
1 Gbps
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Figure 43.
Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with
IEEE 1588v2
Transmitter PMA Transmitter Standard PCS FPGA
Fabric
10 8
PRBS
Generator tx_coreclkin
625 MHz
125 MHz tx_clkout tx_pma_div_clkout
/2
125 MHz tx_clkout
Receiver PMA Receiver Standard PCS
10 8 rx_clkout tx_clkout
PRBS
Verifier
125 MHz rx_coreclkin
625 MHz
Parallel Clock
(Recovered)
125 MHz
Parallel Clock
(From Clock
Divider)
/2 rx_pma_div_clkout
Clock Generation Block (CGB) (5)
Clock Divider rx_clkout or tx_clkout
ATX PLL
CMU PLL fPLL
Parallel Clock
Serial Clock
Parallel and Serial Clock Parallel and Serial Clock
Serial Clock
Notes:
1. This block is set in low latency mode for GbE and register_fifo mode for GbE with IEEE 1588v2.
2. The rate match FIFO of the hard PCS is disabled for GbE with IEEE 1588v2 because it is not able to acheive deterministic latency. It is also disabled for Triple-speed Ethernet (TSE) configurations that require an auto-negotiation sequency.
The insertion/deletion operation could break the auto-negotiation functionality due to the rate matching of different frequency PPM scenarios.The soft rate match FIFO is constructed in the GbE Serial Gigabit Media Independent Interface
(SGMII) IP core.
3. The byte serializer can be enabled or disabled.
4. The byte deserializer can be enabled or disabled.
5. The CGB is in the Native PHY.
Note: The Native PHY only supports basic PCS functions. The Native PHY does not support auto-negotiation state machine, collision-detect, and carrier-sense. If required, you must implement these functions in the FPGA fabric or external circuits.
GbE with IEEE 1588v2
GbE with IEEE 1588v2 provides a standard method to synchronize devices on a network with submicrosecond precision. To improve performance, the protocol synchronizes slave clocks to a master clock so that events and time stamps are synchronized in all devices. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster clock.
The TX FIFO and RX FIFO are set to register_fifo mode for GbE with IEEE 1588v2.
Related Information
Triple-Speed Ethernet IP Function User Guide.
For more information about the IEEE 1588v2 implementation in GbE PHY and MAC, and design examples.
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2
The 8B/10B encoder clocks 8-bit data and 1-bit control identifiers from the transmitter phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded data is sent to the PMA.
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Note:
The IEEE 802.3 specification requires GbE to transmit Idle ordered sets (/I/) continuously and repetitively whenever the gigabit media-independent interface
(GMII) is Idle. This transmission ensures that the receiver maintains bit and word synchronization whenever there is no active data to be transmitted.
For the GbE protocol, the transmitter replaces any /Dx.y/ following a /K28.5/ comma with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set), depending on the current running disparity. The exception is when the data following the /K28.5/ is /
D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the running disparity before the /K28.5/ is positive, an /I1/ ordered set is generated. If the running disparity is negative, a /I2/ ordered set is generated. The disparity at the end of a /I1/ is the opposite of that at the beginning of the /I1/. The disparity at the end of a /I2/ is the same as the beginning running disparity immediately preceding transmission of the
Idle code. This sequence ensures a negative running disparity at the end of an Idle ordered set. A /Kx.y/ following a /K28.5/ does not get replaced.
/D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for I1 and I2 ordered sets). D21.5 (/C1/) is not replaced.
Figure 44.
Idle Ordered-Set Generation Example
Clock (i) tx_datain (i) K28.5
D14.3
K28.5
D24.0
K28.5
D15.8
K28.5
D21.5
Dx.y
tx_dataout (o)
Ordered Set (o)
Dx.y
K28.5
/I1/
D5.6
K28.5
/I2/
D16.2
K28.5
/I2/
D16.2
K28.5
/C1/
D21.5
Legend:
(i) = Input signal
(o) = Output signal
Related Information
on page 482
2.6.1.1.1. Reset Condition for 8B/10B Encoder in GbE, GbE with IEEE 1588v2
After deassertion of tx_digitalreset
, the transmitters automatically transmit at least three /K28.5/ comma code groups before transmitting user data on the tx_parallel_data
port. This transmission could affect the synchronization state machine behavior at the receiver.
Depending on when you start transmitting the synchronization sequence, there could be an even or odd number of /Dx.y/ code groups transmitted between the last of the three automatically sent /K28.5/ code groups and the first /K28.5/ code group of the synchronization sequence. If there is an even number of /Dx.y/code groups received between these two /K28.5/ code groups, the first /K28.5/ code group of the synchronization sequence begins at an odd code group boundary. The synchronization state machine treats this as an error condition and goes into the loss of synchronization state.
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Figure 45.
Reset Condition n clock tx_digitalreset tx_parallel_data K28.5
xxx K28.5
K28.5
K28.5
n + 1 n + 2 n + 3 n + 4
Dx.y
Dx.y
K28.5
Dx.y
K28.5
Dx.y
K28.5
Dx.y
Automatically transmitted /K28.5/ User transmitted synchronization sequence
User transmitted data
2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2
The word aligner for the GbE and GbE with IEEE 1588v2 protocols is configured in automatic synchronization state machine mode. The software automatically configures the synchronization state machine to indicate synchronization when the receiver receives three consecutive synchronization ordered sets. A synchronization ordered set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code groups.
The fastest way for the receiver to achieve synchronization is to receive three continuous {/K28.5/, /Dx.y/} ordered sets.
The GbE PHY IP core signals receiver synchronization status on the rx_syncstatus port of each channel. A high on the rx_syncstatus
port indicates that the lane is synchronized; a low on the rx_syncstatus
port indicates that the lane has fallen out of synchronization. The receiver loses synchronization when it detects three invalid code groups separated by less than three valid code groups or when it is reset.
Table 90.
Synchronization State Machine Parameter Settings for GbE
Synchronization State Machine Parameter
Number of word alignment patterns to achieve sync
Number of invalid data words to lose sync
Number of valid data words to decrement error count
Setting
3
3
3
The following figure shows rx_syncstatus
high when three consecutive ordered sets are sent through rx_parallel_data
.
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Figure 46.
rx_syncstatus High
Three Consecutive Ordered Sets Received to Achieve Synchronization
rx_parallel_data rx_datak rx_syncstatus bc c5 bc 50 bc 50 8c 8d 00 8c 8d rx_patterndetect rx_disperr rx_errdetect
Related Information
2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2
The 8B/10B decoder takes a 10-bit encoded value as input and produces an 8-bit data value and 1-bit control value as output.
Figure 47.
Decoding for GbE
Dx.y(0x8d), Dx.y(0xa4), K28.5(0xbc), and Dx.y(0x50) are received at rx_parallel_data
. /K28.5/ is set as the word alignment pattern. rx_patterndetect
goes high whenever it detects /K28.5/(0xbc). rx_datak
is high when bc is received, indicating that the decoded word is a control word. Otherwise, rx_datak
is low.
rx_runningdisp
is high for 0x8d, indicating that the decoded word has negative disparity and 0xa4 has positive disparity.
rx_datak rx_parallel_data 8d rx_patterndetect a4 bc 50 8d a4 bc 50 8d a4 bc 50 8d a4 bc rx_disperr rx_errdetect rx_runningdisp
Related Information
50
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2.6.1.4. Rate Match FIFO for GbE
The rate match FIFO compensates frequency Part-Per-Million (ppm) differences between the upstream transmitter and the local receiver reference clock up to 125
MHz ± 100 ppm difference.
Note: 200 ppm total is only true if calculated as (125 MHz + 100 ppm) - (125 MHz - 100 ppm) = 200 ppm. By contrast, (125 MHz + 0 ppm) - (125 MHz - 200 ppm) is out of specification.
The GbE protocol requires the transmitter to send idle ordered sets /I1/ (/K28.5/
D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps (IPG) adhering to the rules listed in the IEEE 802.3-2008 specification.
The rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus
signal high. The rate matcher deletes or inserts both symbols /K28.5/ and /D16.2/ of the /I2/ ordered sets as a pair in the operation to prevent the rate match FIFO from overflowing or underflowing. The rate match operation can insert or delete as many /I2/ ordered sets as necessary.
The following figure shows a rate match deletion operation example where three symbols must be deleted. Because the rate match FIFO can only delete /I2/ ordered sets, it deletes two /I2/ ordered sets (four symbols deleted).
Figure 48.
Rate Match FIFO Deletion
/I2/ SKP Symbol Deleted
First /I2/ Ordered S et S econd /I2/ Ordered S et Third /I2/ Ordered S et datain
Dx .y
K 28 .5
D 16 .2
K 28 .5
D 16 .2
K 28 .5
D 16 .2
Dx .y
dataout Dx .y
K 28 .5
D 16 .2
Dx .y
The following figure shows an example of rate match FIFO insertion in the case where one symbol must be inserted. Because the rate match FIFO can only insert /I2/ ordered sets, it inserts one /I2/ ordered set (two symbols inserted).
Figure 49.
Rate Match FIFO Insertion
First /I2/ Ordered Set Second /I2/ Ordered Set
/I2/ SKP Symbol Inserted dataout Dx .y
K 28 .5
D 16 .2
K 28 .5
D 16 .2
datain
Dx .y
K 28 .5
D 16 .2
K 28 .5
D 16 .2
K 28 .5
D 16 .2
Dx .y
rx_std_rmfifo_full
and rx_std_rmfifo_empty
are forwarded to the FPGA fabric to indicate rate match FIFO full and empty conditions.
The rate match FIFO does not delete code groups to overcome a FIFO full condition. It asserts the rx_std_rmfifo_full
flag for at least two recovered clock cycles to indicate rate match FIFO full. The following figure shows the rate match FIFO full condition when the write pointer is faster than the read pointer.
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Figure 50.
Rate Match FIFO Full Condition
tx_parallel_data 2D 2E 2F 30 31 32 33 34 35 36 37 38 rx_parallel_data 03 rx_std_rmfifo_full
04 05 06 07 08 09 0A 0B 0C 0D 0E
The rx_std_rmfifo_full status flag indicates that the FIFO is full at this time
The rate match FIFO does not insert code groups to overcome the FIFO empty condition. It asserts the rx_std_rmfifo_empty
flag for at least two recovered clock cycles to indicate that the rate match FIFO is empty. The following figure shows the rate match FIFO empty condition when the read pointer is faster than the write pointer.
Figure 51.
Rate Match FIFO Empty Condition tx_parallel_data 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D rx_parallel_data 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 00 01 02 rx_std_rmfifo_empty
The rx_std_rmfifo_empty status flag indicates that the FIFO is empty at this time
In the case of rate match FIFO full and empty conditions, you must assert the rx_digitalreset
signal to reset the receiver PCS blocks.
Related Information
2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing the GbE protocol.
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
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Refer to Select and Instantiate the PHY IP Core on page 33.
2. Select GbE or GbE 1588 from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.
3. Use the parameter values in the tables in Native PHY IP Parameter Settings for
GbE and GbE with IEEE 1588v2 on page 120 as a starting point. Or, you can use
the protocol presets described in
Transceiver Native PHY Presets . Use the
GIGE-1.25 Gbps preset for GbE, and the GIGE-1.25 Gbps 1588 preset for GbE
1588. You can then modify the setting to meet your specific requirements.
4. Click Generate to generate the Native PHY IP core top-level RTL file.
Figure 52.
Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE
1588v2
Generating the IP core creates signals and ports based on your parameter settings.
Arria 10 Transceiver Native PHY tx_cal_busy rx_cal_busy
NIOS
Hard Calibration IP
Reconfiguration
Registers reconfig_reset reconfig_clk reconfig_avmm tx_serial_data
TX PMA
Serializer
10
TX Standard PCS tx_datak tx_parallel_data[7:0] tx_coreclkin tx_clkout unused_tx_parallel_data[118:0] tx_digitalreset gmii_tx_ctrl gmii_tx_d[7:0] gmii_tx_clk tx_clkout tx_serial_clk0
(from TX PLL) rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref
Local Clock
Generation
Block
RX PMA
Deserializer
CDR
10
RX Standard PCS rx_datak rx_parallel_data[7:0] rx_clkout rx_coreclkin rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus rx_rmfifostatus unused_rx_parallel_data[111:0] tx_analogreset rx_analogreset rx_digitalreset gmii_rx_ctrl gmii_rx_d[7:0] gmii_rx_clk rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus rx_rmfifostatus (1)
Note:
1. rx_rmfifostatus is not available in the GbE with 1588 configuration.
5. Instantiate and configure your PLL.
6. Instantiate a transceiver reset controller.
You can use your own reset controller or use the Native PHY Reset Controller IP core.
7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the information in the figure below to connect the ports.
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Figure 53.
Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design pll_ref_clk reset
Pattern
Generator tx_parallel_data tx_datak tx_clkout tx_serial_data rx_serial_data
PLL pll_locked pll_powerdown (2) rx_ready tx_ready clk pll_cal_busy (1) reset
Reset
Controller tx_digitalreset tx_analogreset rx_digitalreset rx_analogreset rx_is_lockedtodata rx_cal_busy rx_cdr_refclk
Arria 10
Transceiver
Native
PHY reset
Pattern
Checker tx_cal_busy rx_parallel_data rx_datak rx_clkout tx_serial_clk
Note:
1. The pll_cal_busy signal is not available when using the CMU PLL.
2. The pll_powerdown signal is not available separately for user control when using the fPLL.
The reset controller handles PLL reset for the fPLL.
8. Simulate your design to verify its functionality.
Related Information
•
Arria 10 Standard PCS Architecture
on page 479
For more information about Standard PCS architecture
•
Arria 10 PMA Architecture on page 447
For more information about PMA architecture
•
on page 398
For more information about implementing PLLs and clocks
•
PLL architecture and implementation details
•
Resetting Transceiver Channels
on page 416
Reset controller general information and implementation details
•
Port definitions for the Transceiver Native PHY Standard Datapath
2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
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Table 91.
General and Datapath Options
The first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.
Parameter
Message level for rule violations
Transceiver configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Value error warning
GbE (for GbE)
GbE 1588 (for GbE with IEEE 1588v2)
TX/RX Duplex
TX Simplex
RX Simplex
1 to 96
1250 Mbps
On/Off
On/Off
Table 92.
TX PMA Parameters
Parameter
TX channel bonding mode
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Enable tx_pma_qpipulldn port (QPI)
Enable tx_pma_txdetectrx port (QPI)
Enable tx_pma_rxfound port (QPI)
Enable rx_seriallpbken port
Value
Not bonded
1, 2, 4, 8
1, 2, 3, 4
0 to 3
On/Off
On/Off
Disabled, 1, 2, 33, 40, 66
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Table 93.
RX PMA Parameters
Parameter
Number of CDR reference Clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
Value
1 to 5
0 to 4
Select legal range defined by the Quartus Prime software
100, 300, 500, 1000 manual continued...
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Parameter
DFE adaptation mode
Number of fixed dfe taps
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port rx_pma_div_clkout division factor
Enable rx_pma_iqtxrx_clkout port
Enable rx_pma_clkslip port
Enable rx_pma_qpipulldn port (QPI)
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
Table 94.
Standard PCS Parameters
Parameters
Standard PCS / PMA interface width
FPGA fabric / Standard TX PCS interface width
FPGA fabric / Standard RX PCS interface width
Enable Standard PCS low latency mode
TX FIFO mode
RX FIFO mode
Enable tx_std_pcfifo_full port
Enable tx_std_pcfifo_empty port
Enable rx_std_pcfifo_full port
Enable rx_std_pcfifo_empty port
TX byte serializer mode
RX byte deserializer mode
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
RX rate match FIFO mode
RX rate match insert / delete -ve pattern (hex)
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Value disabled
N/A
On/Off
On/Off
Disabled, 1, 2, 33, 40, 66
On/Off
On/Off
Off
On/Off
On/Off
On/Off
On/Off
On/Off
Value
10
8
8
Off
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
On/Off
On/Off
On/Off
On/Off
Disabled
Disabled
On
On/Off
On
gige (for GbE)
disabled (for GbE with IEEE 1588v2)
0x000ab683
(/K28.5/D2.2/) (for GbE)
0x00000000
(disabled for GbE with IEEE
1588v2) continued...
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Parameters
RX rate match insert / delete +ve pattern (hex)
Enable rx_std_rmfifo_full port
Enable rx_std_rmfifo_empty port
PCI Express Gen3 rate match FIFO mode
Enable TX bit slip
Enable tx_std_bitslipboundarysel port
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Number of word alignment patterns to achieve sync
Number of invalid data words to lose sync
Number of valid data words to decrement error count
Enable fast sync status reporting for deterministic latency SM
Enable rx_std_wa_patternalign port
Enable rx_std_wa_a1a2size port
Enable rx_std_bitslipboundarysel port
Enable rx_bitslip port
Enable TX bit reversal
Enable TX byte reversal
Enable TX polarity inversion
Enable tx_polinv port
Enable RX bit reversal
Enable rx_std_bitrev_ena port
Enable RX byte reversal
Enable rx_std_byterev_ena port
Enable RX polarity inversion
Enable rx_polinv port
Enable rx_std_signaldetect port
All options under PCIe Ports
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
Value
0x000a257c
(/K28.5/D16.2/) (for GbE)
0x00000000
(disabled for GbE with IEEE
1588v2)
On/Off
(option disabled for GbE with IEEE 1588v2)
On/Off
(option disabled for GbE with IEEE 1588v2)
Bypass
Off
On/Off
Synchronous state machine
7
0x000000000000007c
(Comma) (for 7-bit aligner pattern length),
0x000000000000017c
(/K28.5/) (for 10-bit aligner pattern length)
On/Off
Off
Off
Off
Off
On/Off
On/Off
On/Off
Off
3
3
3
On/Off
Off
Off
Off
Off
Off
Off
On/Off
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2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with
FEC Variants
10GBASE-R PHY is the Ethernet-specific physical layer running at a 10.3125-Gbps data rate as defined in Clause 49 of the IEEE 802.3-2008 specification. Arria 10 transceivers can implement 10GBASE-R variants like 10GBASE-R with IEEE 1588v2, and with forward error correction (FEC).
The 10GBASE-R parallel data interface is the 10 Gigabit Media Independent Interface
(XGMII) that interfaces with the Media Access Control (MAC), which has the optional
Reconciliation Sub-layer (RS).
Figure 54.
10GBASE-R PHY as Part of the IEEE802.3-2008 Open System Interconnection
(OSI)
LAN
CSMA/CD
LAYERS
Higher Layers
Logical Link Control (LLC) or other MAC Client
MAC Control (Optional)
Media Access Control (MAC)
Reconciliation
OSI Reference
Model Layers
Application
Presentation
Session
Transport
Network
Data Link
Physical
10GBASE-R
PHY
To 10GBASE-R PHY
(Point-to-Point Link)
XGMII
10GBASE-R PCS
10GBASE-R FEC (Optional)
PMA
PMD
MDI
Medium
10GBASE-R
(PCS, FEC, PMA, PMD)
Legend
MDI: Medium Dependent Interface
PCS: Physical Coding Sublayer
PHY: Physical Layer Device
PMA: Physical Medium Attachment
PMD: Physical Medium Dependent
FEC: Forwarad Error Correction
XGMII: 10 GB Media Independent Interface
10GBASE-R is a single-channel protocol that runs independently. You can configure the transceivers to implement 10GBASE-R PHY functionality by using the presets of the Native PHY IP. The 10GBASE-R PHY IP is compatible with the 10-Gbps Ethernet
MAC Intel FPGA IP Core Function. The complete PCS and PHY solutions can be used to interface with a third-party PHY MAC layer as well.
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The following 10GBASE-R variants area available from presets:
• 10GBASE-R
• 10GBASE-R Low Latency
• 10GBASE-R Register Mode
• 10GBASE-R w/ KR-FEC
Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly if you are configuring through the Native PHY IP core.
Figure 55.
Transceiver Channel Datapath and Clocking for 10GBASE-R
Transmitter PMA Transmitter Enhanced PCS FPGA
Fabric
10.3125 Gbps
40
64
TX
Data &
Control
64 + 8
PRBS
Generator
Parallel Clock
@ 257.8125 MHz (2)
66
PRP
Generator tx_clkout
@ 156.25 MHz from XGMII
KR FEC TX G KR FEC Scr KR FEC Enc
Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout rx_pma_div_clkout
40
66
RX
Data &
Control
64 + 8 64
PRBS
Verifier
Parallel Clock
@ 257.8125 MHz (2)
PRP
Verifier
10GBASE-R
BER Checker rx_clkout
@ 156.25 MHz from XGMII
KR FEC Block S KR FEC Dec
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
ATX PLL fPLL
CMU PLL
Serial Clock
Input Reference Clock
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
3. This block is in Phase Compensation mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.
4. This block is in 10GBASE-R mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.
10GBASE-R with IEEE 1588v2
When choosing the 10GBASE-R PHY with IEEE 1588v2 mode preset, the hard TX and
RX FIFO are set to register mode. The output clock frequency of tx_clkout
and rx_clkout
to the FPGA fabric is based on the PCS-PMA interface width. For example, if the PCS-PMA interface is 40-bit, tx_clkout
and rx_clkout
run at 10.3125
Gbps/40-bit = 257.8125 MHz.
The 10GBASE-R PHY with IEEE 1588v2 creates the soft TX phase compensation FIFO and the RX clock compensation FIFO in the FPGA core so that the effective XGMII data is running at 156.25 MHz interfacing with the MAC layer.
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The IEEE 1588 Precision Time Protocol (PTP) is supported by the preset of the Arria 10 transceiver Native PHY that configures 10GBASE-R PHY IP in IEEE-1588v2 mode. PTP is used for precise synchronization of clocks in applications such as:
• Distributed systems in telecommunications
• Power generation and distribution
• Industrial automation
• Robotics
• Data acquisition
• Test equipment
• Measurement
The protocol is applicable to systems communicating by local area networks including, but not limited to, Ethernet. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster clock.
Figure 56.
Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2
Transmitter PMA Transmitter Enhanced PCS FPGA
Fabric
40
10.3125 Gbps
Soft Phase
Compensation
FIFO
64 (data) + 8 (control)
64
66 TX XGMII
@ 156.25 MHz
PRBS
Generator
Parallel Clock
@ 257.8125 MHz (2)
PRP
Generator tx_clkout
KR FEC TX G
KR FEC Scr KR FEC Enc
Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout rx_pma_div_clkout
40
66
Soft Clock
Compensation
FIFO
64 (data) + 8 (control)
PRBS
Verifier
Parallel Clock
@ 257.8125 MHz (2)
64
PRP
Verifier
10GBASE-R
BER Checker rx_clkout
RX XGMII
@ 156.25 MHz
KR FEC Block S KR FEC Dec
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clocks
ATX PLL fPLL
CMU PLL
Serial Clock
Input Reference Clock
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
10GBASE-R with FEC
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Arria 10 10GBASE-R has the optional FEC variant that also targets the 10GBASE-KR
PHY. This provides a coding gain to increase the link budget and BER performance on a broader set of backplane channels as defined in Clause 69. It provides additional margin to account for variations in manufacturing and environment conditions. The additional TX FEC sublayer:
• Receives data from the TX PCS
• Transcodes 64b/66b words
• Performs encoding/framing
• Scrambles and sends the FEC data to the PMA
The RX FEC sublayer:
• Receives data from the PMA
• Performs descrambling
• Achieves FEC framing synchronization
• Decodes and corrects data where necessary and possible
• Recodes 64b/66b words and sends the data to the PCS
The 10GBASE-R with KR FEC protocol is a KR FEC sublayer placed between the PCS and PMA sublayers of the 10GBASE-R physical layer.
Figure 57.
Transceiver Channel Datapath and Clocking for 10GBASE-R with KR FEC
Transmitter PMA Transmitter Enhanced PCS FPGA
Fabric
TX
Data &
Control
64
64
66
64 + 8 tx_hf_clk tx_pma_clk tx_krfec_clk
PRBS
Generator
Parallel Clock (161.1 MHz) (3)
PRP
Generator tx_clkout
@ 156.25 MHz from XGMII
KR FEC TX G
KR FEC Scr KR FEC Enc
KR FEC
Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout rx_pma_div_clkout
64
RX
Data &
Control
64 + 8
@ 156.25 MHz from XGMII rx_rcvd_clk rx_pma_clk
PRBS
Verifier rx_krfec_clk Parallel Clock (161.1 MHz) (3)
PRP
Verifier
10GBASE-R
BER Checker
KR FEC Block S KR FEC Dec
KR FEC
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Notes:
1. Value is based on the clock division factor chosen
2. Value is calculated as data rate/FPGA fabric - PCS interface width
3. Value is calculated as data rate/PCS-PMA interface width
4. For 10GBASE-R with KR FEC, TX FIFO is in phase compensation mode
5. For 10GBASE-R with KR FEC, RX FIFO is in 10GBASE-R mode
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clocks tx_serial_clk0
(5156.25 MHz) =
Data rate/2
ATX PLL fPLL
CMU PLL
Serial Clock
Input Reference Clock
The CMU PLL or the ATX PLLs generate the TX high speed serial clock.
rx_clkout
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Figure 58.
Clock Generation and Distribution for 10GBASE-R with FEC Support
Example using a 64-bit PCS-PMA interface width.
10GBASE-R Hard IP Transceiver Channel
TX
64 Bit Data
8 Bit Control 64
TX PCS TX PMA
10.3125 Gbps
Serial
161.13 MHz
TX PLL pll_ref_clk
644.53125 MHz
RX
64 Bit Data
8 Bit Control
156.25 MHz
RX PCS
64
161.13 MHz
RX PMA
10.3125 Gbps
Serial rx_coreclkin fPLL
8/33
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R
The XGMII interface, specified by IEEE 802.3-2008, defines the 32-bit data and 4-bit wide control character. These characters are clocked between the MAC/RS and the PCS at both the positive and negative edge (double data rate – DDR) of the 156.25 MHz interface clock.
The transceivers do not support the XGMII interface to the MAC/RS as defined in the
IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control single data rate (SDR) interface between the MAC/RS and the PCS.
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Figure 59.
XGMII Interface (DDR) and Transceiver Interface (SDR) for 10GBASE-R
Configurations
XGMII Transfer (DDR)
Interface Clock (156.25) MHz
TXD/RXD[31:0]
TXC/RXC[3:0]
Transceiver Interface (SDR)
Interface Clock (156.25) MHz
TXD/RXD[63:0]
TXC/RXC[7:0]
D0
C0
{D1, D0}
{C1, C0}
D1
C1
D2
C2
{D3, D2}
{C3, C2}
D3
C3
D4
C4
{D5, D4}
{C5, C4}
D5
C5
D6
C6
Note: Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the 10GBASE-R PCS and the Ethernet MAC/RS.
The dedicated reference clock input to the variants of the 10GBASE-R PHY can be run at either 322.265625 MHz or 644.53125 MHz.
For 10GBASE-R, you must achieve 0 ppm of the frequency between the read clock of
TX phase compensation FIFO (PCS data) and the write clock of TX phase compensation FIFO (XGMII data in the FPGA fabric). This can be achieved by using the same reference clock as the transceiver dedicated reference clock input as well as the reference clock input for a core PLL (fPLL, for example) to produce the XGMII clock.
The same core PLL can be used to drive the RX XGMII data. This is because the RX clock compensation FIFO is able to handle the frequency PPM difference of ±100 ppm between RX PCS data driven by the RX recovered clock and RX XGMII data.
Note: 10GBASE-R is the single-channel protocol that runs independently. Therefore Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly. If it is being configured through the Native PHY IP, the channel bonding option should be disabled. Enabling the channel bonding for multiple channels could degrade the link performance in terms of TX jitter eye and RX jitter tolerance.
2.6.2.1.1. TX FIFO and RX FIFO
In 10GBASE-R configuration, the TX FIFO behaves as a phase compensation FIFO and the RX FIFO behaves as a clock compensation FIFO.
In 10GBASE-R with 1588 configuration, both the TX FIFO and the RX FIFO are used in register mode. The TX phase compensation FIFO and the RX clock compensation FIFO are constructed in the FPGA fabric by the PHY IP automatically.
In 10GBASE-R with KR FEC configuration, you use the TX FIFO in phase compensation mode and the RX FIFO behaves as a clock compensation FIFO.
Related Information
Arria 10 Enhanced PCS Architecture
on page 461
For more information about the Enhanced PCS Architecture
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2.6.2.2. How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and
10GBASE-R with FEC in Arria 10 Transceivers
You should be familiar with the 10GBASE-R and PMA architecture, PLL architecture, and the reset controller before implementing the 10GBASE-R, 10GBASE-R with IEEE
1588v2, or 10GBASE-R with FEC Transceiver Configuration Rules.
You must design your own MAC and other layers in the FPGA to implement the
10GBASE-R, 10GBASE-R with 1588, or 10GBASE-R with KR FEC Transceiver
Configuration Rule using the Native PHY IP.
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
2. Select 10GBASE-R, 10GBASE-R 1588, or 10GBASE-R with KR FEC from the
Transceiver configuration rule list located under Datapath Options, depending on which protocol you are implementing.
described in Transceiver Native PHY Presets
. Select 10GBASE-R Register Mode
for 10GBASE-R with IEEE 1588v2. You can then modify the settings to meet your specific requirements.
4. Click Generate to generate the Native PHY IP core RTL file.
Figure 60.
Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with
IEEE 1588v2, and 10GBASE-R with FEC
Generating the IP core creates signals and ports based on your parameter settings.
Arria 10 Transceiver Native PHY tx_cal_busy rx_cal_busy tx_serial_data
Nios Hard
Calibration IP
TX PMA
Serializer
Reconfiguration
Registers
TX Enhanced PCS tx_control[17:0] tx_parallel_data[127:0] tx_coreclkin tx_clkout tx_enh_data_valid tx_fifo_flags reconfig_reset reconfig_clk reconfig_avmm tx_digitalreset xgmii_tx_c[7:0] (2) xgmii_tx_d[63:0] (2) xgmii_tx_clk
1’b1 (1) tx_serial_clk0 (from TX PLL)
Clock
Generation
Block rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref
CDR
RX PMA
Deserializer
RX Enhanced PCS rx_clkout rx_coreclkin rx_enh_blk_lock rx_enh_highber rx_fifo_flags rx_parallel_data[127:0] rx_control[19:0]
Notes:
1. For 10GBASE-R with 1588 configurations, this signal is user-controlled.
2. For 10GBASE-R with 1588 configurations, this signal is connected from the output of TX FIFO in the FPGA fabric.
5. Instantiate and configure your PLL.
tx_analogreset rx_analogreset rx_digitalreset xgmii_rx_clk
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6. Create a transceiver reset controller. You can use your own reset controller or use the Arria 10 Transceiver Native PHY Reset Controller IP.
7. Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller.
Figure 61.
Connection Guidelines for a 10GBASE-R or 10GBASE-R with FEC PHY Design
PLL IP
Reset
Controller
To MAC/RS through XGMII
Interface
64d + 8c
Arria 10 Transceiver
Native PHY
Medium
Figure 62.
Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
To MAC/RS through XGMII
Interface
PLL IP
Reset
Controller
64d + 8c
FIFO in the
FPGA core for TX
Arria 10 Transceiver
Native PHY
Medium
64d + 8c
FIFO in the
FPGA core for RX
8. Simulate your design to verify its functionality.
Related Information
•
Arria 10 Enhanced PCS Architecture
on page 461
For more information about Enhanced PCS architecture
•
Arria 10 PMA Architecture on page 447
For more information about PMA architecture
•
on page 398
For more information about implementing PLLs and clocks
•
PLL architecture and implementation details
•
Resetting Transceiver Channels
on page 416
Reset controller general information and implementation details
•
For detailed information about the available ports in the 10GBASE-R 1588 protocol.
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2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE
1588v2, and 10GBASE-R with FEC
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Table 95.
General and Datapath Parameters
The first two sections of the Transceiver Native PHY parameter editor provide a list of general and datapath options to customize the transceiver.
Parameter
Message level for rule violations
Transceiver Configuration Rule
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
error, warning
10GBASE-R
10GBASE-R 1588
10GBASE-R with KR FEC
Range
TX / RX Duplex, TX Simplex, RX Simplex
1 to 96
10312.5 Mbps
Off
On
Off
Table 96.
TX PMA Parameters
Parameter
TX channel bonding mode
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Table 97.
RX PMA Parameters
Parameter
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency (
PPM detector threshold
CTLE adaptation mode
DFE adaptation mode
Number of fixed DFE taps
Not bonded
1, 2, 4, 8
1, 2, 3, 4
0
Range
Range
1 to 5
0 to 4
156.25 MHz, 322.265625 MHz, and 644.53125 MHz
100, 300, 500, 1000 manual adaptation enabled, manual, disabled
3, 7, 11
(35) The CDR reference clock frequency depends on your design settings. Intel recommends that you verify the link datarates to ensure the CDR locking capability before production.
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Table 98.
Enhanced PCS Parameters
Parameter
Enhanced PCS/PMA interface width
FPGA fabric/Enhanced PCS interface width
Enable Enhanced PCS low latency mode
Enable RX/TX FIFO double-width mode
TX FIFO mode
TX FIFO partially full threshold
TX FIFO partially empty threshold
RX FIFO mode
RX FIFO partially full threshold
RX FIFO partially empty threshold
Range
32, 40, 64
Note: 10GBASE-R with KR-FEC allows 64 only.
66
On
Off
Off
• Phase Compensation (10GBASE-R and 10GBASE-R with KR FEC)
• Register or Fast register (10GBASE-R with 1588)
11
2
• 10GBASE-R (10GBASE-R and 10GBASE-R with KR FEC)
• Register (10GBASE-R with 1588)
23
2
Table 99.
64B/66B Encoder and Decoder Parameters
Parameter
Enable TX 64B/66B encoder
Enable RX 64B/66B decoder
Enable TX sync header error insertion
On
On
On
Off
Range
Table 100.
Scrambler and Descrambler Parameters
Parameter
Enable TX scrambler (10GBASE-R / Interlaken)
TX scrambler seed (10GBASE-R / Interlaken)
Enable RX descrambler (10GBASE-R / Interlaken)
On
0x03ffffffffffffff
On
Table 101.
Block Sync Parameters
Parameter
Enable RX block synchronizer
Enable rx_enh_blk_lock port
On
On
Off
Table 102.
Gearbox Parameters
Parameter
Enable TX data polarity inversion
Range
Range
Range
Enable RX data polarity inversion
On
Off
On
Off
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Table 103.
Dynamic Reconfiguration Parameters
Parameter
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
De-couple reconfig_waitrequest from calibration
On
Off
On
Off
On
Off
On
Off
Table 104.
Configuration Files Parameters
Parameter
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
Generate MIF (Memory Initialization File)
—
On
Off
On
Off
On
Off
Table 105.
Generation Options Parameters
Parameter
Generate parameter documentation file On
Off
Range
Range
Range
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2
Transceiver Configurations
Figure 63.
High BER
This figure shows the rx_enh_highber
status signal going high when there are errors on the rx_parallel_data
output.
rx_parallel_data rx_control tx_parallel_data tx_control rx_enh_highber
1122334455667788h
0h
1122324455667788h 112233405566F788h
00h
1122334455667788h
00h
1122334455667788h
1h
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Figure 64.
Block Lock Assertion
This figure shows the assertion on rx_enh_blk_lock
signal when the Receiver detects the block delineation.
rx_parallel_data rx_control tx_parallel_data tx_control rx_enh_highber
0100009C0100009Ch
11h
0h
0707070707070707h
FFh
1h
0707070707070707h
FFh rx_ready rx_enh_block_lock 0h 1h
The following figures show Idle insertion and deletion.
Figure 65.
IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
Before Insertion rx_parallel_data[79:0] FD000000000004AEh BBBBBB9CDDDDDD9Ch 00000000000000FBh rx_parallel_data[79:0]
After Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch 0707070707070707h
AAAAAAAAAAAAAAAAh
00000000000000FBh
Idle Inserted
Figure 66.
IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
Before Deletion rx_parallel_data[79:0] 00000000000004ADh 00000000000004AEh 0707070707FD0000h rx_parallel_data[79:0]
After Deletion
00000000000004ADh 00000000000004AEh 0707070707FD0000h
Idle Deleted
Figure 67.
OS Word Deletion
This figure shows the deletion of Ordered set word in the receiver data stream.
Before Deletion rx_parallel_data[79:0] FD000000000004AEh DDDDDD9CDDDDDD9Ch 00000000000000FBh rx_parallel_data[79:0]
After Deletion
FD000000000004AEh 000000FBDDDDDD9Ch AAAAAAAA00000000h
OS Deleted
000000FB07070707h
AAAAAAAA000000FBh
AAAAAAAAAAAAAAAAh
00000000AAAAAAAAh
2.6.3. 10GBASE-KR PHY IP Core
The 10GBASE-KR Ethernet PHY IP core supports the following features of Ethernet standards:
• Auto negotiation for backplane Ethernet as defined in Clause 73 of the IEEE 802.3
2008 Standard. The 10GBASE-KR Ethernet PHY IP Function can auto negotiate between 1000BASE-X, 1000BASE-KR , and 1000BASE-KR with FEC.
• 10GBASE-KR Ethernet protocol with link training as defined in Clause 72 of the
IEEE 802.3 2008 Standard. In addition to the link-partner TX tuning as defined in
Clause 72, this PHY also automatically configures the local device RX interface to achieve less than 10 -12 bit error rate (BER) target.
• Gigabit Media Independent Interface (GMII) to connect PHY with media access control (MAC) as defined in Clause 35 of the IEEE 802.3 2008 Standard
• Forward Error Correction (FEC) as defined in Clause 74 of the IEEE 802.3 2008
Standard
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The Backplane Ethernet 10GBASE-KR PHY IP core includes the following new modules to enable operation over a backplane:
• Link Training (LT)— The LT mechanism allows the 10GBASE-KR PHY to automatically configure the link-partner TX PMDs for the lowest Bit Error Rate
(BER). LT is defined in Clause 72 of IEEE Std 802.3ap-2007.
• Auto negotiation (AN)—The 10GBASE-KR PHY IP core can auto-negotiate between
1000BASE-KX (1GbE) and 10GBASE-KR (10GbE) PHY types. The AN function is mandatory for Backplane Ethernet. It is defined in Clause 73 of the IEEE Std
802.3ap-2007.
• Forward Error Correction (FEC)—FEC function is an optional feature defined in
Clause 74 of IEEE 802.3ap-2007. It provides an error detection and correction mechanism.
Related Information
• IEEE Std 802.3ap-2008 Standard
• Standard for a Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems
2.6.3.1. 10GBASE-KR PHY Release Information
Table 106.
10GBASE-KR PHY Release Information
Version
Release Date
Ordering Codes
Product ID
Vendor ID
Item Description
16.0
May 2016
IP-10GBASEKRPHY (IP)
IPR-10GBASEKRPHY (Renewal)
0106
6AF7
2.6.3.2. 10GBASE-KR PHY Performance and Resource Utilization
This topic provides performance and resource utilization for the IP.
The following table shows the typical expected resource utilization for selected configurations using the Quartus Prime software v15.1 for Arria 10 devices. The numbers of ALMs and logic registers are rounded up to the nearest 100.
Table 107.
10GBASE-KR PHY Performance and Resource Utilization
Variant
10GBASE-KR PHY
10GBASE-KR PHY with FEC
2400
2400
ALMs
3750
3750
ALUTs Registers
3100
3100
1
1
M20K
2.6.3.3. 10GBASE-KR Functional Description
The following figure shows the supporting components inside the 10GBASE-KR PHY IP core.
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Figure 68.
10GBASE-KR PHY IP Core Block Diagram
10GBASE-KR PHY IP
Avalon-MM
Nios II Sequencer
Interface
XGMII_TX_CLK
8 + 2
TX_GMII_DATA
GbE
PCS
1588
FIFO
64 + 8
TX_XGMII_DATA
Auto-Negotiation
Clause 73
64 + 8
Link Training
Clause 72
32
Nios II LT Interface
TX_PMA_CLKOUT
RX_XGMII_DATA
64 + 8
64 + 8
1588
FIFO
Note:
Register
Access
HSSI Reconfiguration
Requests
Registers
Native PHY
Standard TX PCS tx_pld_clk tx_pma_clk
Enhanced TX PCS tx_pld_clk tx_pma_clk
40/32
TX PMA
Standard RX PCS rx_pld_clk rx_pma_clk
Enhanced RX PCS rx_pld_clk rx_pma_clk
Divide by 33/1/2
40/32
RX PMA
XGMII_RX_CLK
RX_GMII_DATA
Soft Logic
8 + 2
Hard Logic
GbE
PCS
Unused
The 10GBASE-KR PHY IP core does not support backplane applications with IEEE 1588
Precision Time Protocol.
The 10GBASE-KR PHY IP core includes the following components:
Standard and Enhanced PCS Datapaths
The Enhanced PCS and PMA inside the Native PHY are configured to be the 10GBASE-
R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters for more details on how these blocks support 1G, 10G protocols and FEC.
Auto Negotiation, IEEE 802.3 Clause 73
The auto negotiation (AN) is needed to synchronize the start time of the link training on both sides of the link partners. This ensures that the link training can be done effectively within the 500 ms of the specified time frame as required.
Link Training (LT), IEEE 802.3 Clause 72
Arria 10 devices have soft link training IP that complies with the IEEE 802.3 Clause 72 standard training procedure. This IP includes:
• training frame lock that is different from the regular 64b/66b frame_lock
• training frame generation
• the control channel codec
• Local Device (LD) coefficient update
• Link Partner (LP) coefficient generation
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Reconfiguration Block
The Reconfiguration Block performs Avalon-MM writes to the PHY for both PCS and
PMA reconfiguration. The Avalon-MM master accepts requests from the PMA or PCS controller. It performs the Read-Modify-Write or Write commands on the Avalon-MM interface. The PCS controller receives rate change requests from the Sequencer and translates them to a series of Read-Modify-Write or Write commands to the PMA and
PCS.
Eight compile-time configuration modes are supported. The configuration modes include one set of four with reference clock at 322 MHz and one set of four with reference clock at 644 MHz. Each set of four consists of all combinations of FEC sublayer on/off.
Figure 69.
Reconfiguration Block Details
MGMT_CLK
(2) rcfg_data
PCS
Reconfiguration
Interface
PCS
Controller rcfg_data rcfg_data rcfg_data
(1)
Avalon-MM Bus
Avalon-MM Bus
PMA Controller
TX EQ Controller
DFE Controller
CTLE Controller
Avalon-MM Bus
Avalon-MM reconfig_busy Signal
Avalon-MM
Decoder
HSSI
Reconfiguration
Requests
PMA
Reconfiguration
Interface
Notes:
1. rcfg = Reconfiguration
2. MGMT_CLK = Management Clock
Related Information
•
Arria 10 Enhanced PCS Architecture
on page 461
•
Arria 10 Standard PCS Architecture
on page 479
2.6.3.4. Parameterizing the 10GBASE-KR PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the
Backplane-KR or 1Gb/10Gb Ethernet variant. When you select the Backplane-KR variant, the Link Training (LT) and Auto Negotiation (AN) tabs appear. The 1Gb/
10Gb Ethernet variant (1G/10GbE) does not implement the LT and AN functions.
Complete the following steps to parameterize the 10GBASE-KR PHY IP core in the parameter editor:
1. Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY from the IP Catalog.
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Note:
Refer to Select and Instantiate the PHY IP Core on page 33.
2. Select Backplane-KR from the IP variant list located under Ethernet Intel
FPGA IP Core Type.
3. Use the parameter values in the tables in 10GBASE-R Parameters on page 140,
10GBASE-KR Auto-Negotiation and Link Training Parameters
on page 140, and
10GBASE-KR Optional Parameters on page 141 as a starting point. You can then
modify the setting to meet your specific requirements.
4. Click Generate HDL to generate the 10GBASE-KR PHY IP core top-level HDL file.
You might observe timing violations. If the timing path is within the IP, you can ignore these violations. This will be fixed in a future release of the Intel Quartus Prime software.
Related Information
•
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
•
10GBASE-KR Auto-Negotiation and Link Training Parameters
on page 140
2.6.3.4.1. General Options
The General Options allow you to specify options common to 10GBASE-KR mode.
Table 108.
General Options Parameters
Parameter Name
Enable internal PCS reconfiguration logic
On
Off
Options
Enable IEEE 1588 Precision
Time Protocol
Enable M20K block ECC protection
Enable tx_pma_clkout port
Enable rx_pma_clkout port
Enable tx_divclk port
Enable rx_divclk port
Enable tx_clkout port
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
Description
This parameter is only an option when set to 0, it does not include the reconfiguration module or expose the start_pcs_reconfig between 1G and 10G modes.
or
SYNTH_SEQ rc_busy
= 0. When
ports. When set to 1, it provides a simple interface to initiate reconfiguration
When you turn on this parameter, you enable the IEEE 1588
Precision Time Protocol logic for both 1G and 10G modes.
When you turn on this parameter, you enable error correction code (ECC) support on the embedded Nios CPU system. This parameter is only valid for the backplane variant.
When you turn on this parameter, the more information about this port.
tx_pma_clkout
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, the more information about this port.
rx_pma_clkout
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, the more information about this port.
tx_divclk
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, the more information about this port.
rx_divclk
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, the more information about this port.
tx_clkout
port is enabled. Refer to the Clock and Reset Interfaces section for continued...
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Parameter Name
Enable rx_clkout port
Enable Hard PRBS support and ADME support
Reference clock frequency
Enable additional control and status ports
Include FEC sublayer
Set
FEC_ability
bit on power up and reset
Set
FEC_Enable
bit on power up and reset
On
Off
On
Off
644.53125 MHz
322.265625 MHz
On
Off
On
Off
On
Off
On
Off
Options Description
When you turn on this parameter, the more information about this port.
rx_clkout
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, you enable the ADME and
Hard PRBS data generation and checking logic in the Native PHY.
The transceiver toolkit (TTK) requires ADME to be enabled in the
Native PHY IP core.
Specifies the input reference clock frequency. The default is
322.265625 MHz.
When you turn this option on, the core includes the rx_block_lock
and rx_hi_ber
output.
When you turn on this parameter, the core includes logic to implement FEC and a soft 10GBASE-R PCS. This is applicable only for the 10G mode.
When you turn on this parameter, the core sets the
Assert KR
FEC Ability
bit (0xB0[16]) FEC ability bit during power up and reset, causing the core to assert the FEC ability. This option is required for FEC functionality.
When you turn on this parameter, the core sets the
KR FEC
Request
bit (
0xB0[18]
) during power up and reset, causing the core to request the FEC ability during Auto Negotiation. This option is required for FEC functionality.
Related Information
Clock and Reset Interfaces on page 143
2.6.3.4.2. 10GBASE-R Parameters
The 10GBASE-R parameters specify basic features of the 10GBASE-R PCS. The FEC options also allow you to specify the FEC ability.
Table 109.
10GBASE-R Parameters
Parameter Name
10GbE Reference clock frequency
Enable additional control and status ports
Options
644.53125 MHz
322.265625 MHz
On
Off
Description
Specifies the input reference clock frequency. The default is
322.265625 MHz.
When you turn on this parameter, the core includes the rx_block_lock
and rx_hi_ber
ports.
Table 110.
FEC Options
Parameter Name
Include FEC sublayer On
Off
Options Description
When you turn on this parameter, the core includes logic to implement FEC and a soft 10GBASE-R PCS.
2.6.3.4.3. 10GBASE-KR Auto-Negotiation and Link Training Parameters
Table 111.
Auto Negotiation and Link Training Settings
Name
Enable Auto-Negotiation On
Range Description
Enables or disables the Auto-Negotiation feature.
continued...
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Name
Pause ability-C0
Pause ability-C1
Off
On
Off
Range
On
Off
Description
Depends upon MAC. Local device pause capability C2:0 = D12:10 of
AN word.
C0 is the same as PAUSE.
Depends upon MAC. Local device pause capability C2:0 = D12:10 of
AN word.
C1 is the same as ASM_DIR.
Enables or disables the Link Training feature.
Enable Link Training
Maximum bit error count
Number of frames to send before sending actual data
On
Off
15, 31, 63,
127, 255,
511, 1023
127, 255
Specifies the number of bit errors for the error counter expected during each step of the link training. If the number of errors exceeds this number for each step, the core returns an error. The number of errors depends upon the amount of time for each step and the quality of the physical link media.
The default value is 511.
This timer is started when the local receiver is trained and detects that the remote receiver is ready to receive data. The local physical medium dependent (PMD) layer delivers local receiver state.
wait_timer
additional training frames to ensure that the link partner correctly detects the
The default value is 127.
2.6.3.4.4. 10GBASE-KR Optional Parameters
Table 112.
Optional Parameters
In the following table, the exact correspondence between numerical values and voltages is pending characterization of the Native PHY.
Value Name
PHY Management clock
(MGMT_CLK) frequency in
MHz
100-162
0-31
Description
Determines the value of the Link Fail Inhibit timer in IEEE 802.3
clause 73.10.2.
• 500 - 510 ms for BASE-R
• 40 – 50 ms for GbE, XAUI
The default value is 125.
Specifies the maximum V
OD
. The default value is 30.
VMAXRULE VOD tap MAX
Rule
VMINRULE Device VMIN
Rule
VODMINRULE VOD tap
MIN Rule
VPOSTRULE
0-31
0-31
0-38
Specifies the minimum V
OD
. The default value is 6.
Specifies the minimum V
OD
for the first tap. The default value is 14.
VPRERULE
PREMAINVAL Preset VOD tap Value
PREPOSTVAL
0-31
0-31
0-31
Specifies the maximum value that the internal algorithm for preemphasis tests in determining the optimum post-tap setting. The default value is 25.
Specifies the maximum value that the internal algorithm for preemphasis will ever test in determining the optimum pre-tap setting.
The default value is 16.
Specifies the Preset V
OD
value. This value is set by the Preset command of the link training protocol, defined in Clause
72.6.10.2.3.1 of the Link Training protocol. This is the value from which the algorithm starts. The default value is 30.
Specifies the preset Post-tap value. The default value is 0.
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Name
PREPREVAL
INITMAINVAL Init VOD tap Value
0-15
0-31
Value Description
Specifies the preset Pre-tap value. The default value is 0.
Specifies the initial V
OD
value. This value is set by the Initialize command of the link training protocol, defined in Clause
72.6.10.2.3.2 of IEEE Std 802.3ap–2007. The default value is 25.
Specifies the initial Post-tap value. The default value is 13.
INITPOSTVAL Init Post tap Value
INITPREVAL Init Pre tap
Value
0-38
0-15
Specifies the initial Pre-tap value. The default value is 3.
2.6.3.4.5. Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/10GbE but have disabled Auto-Negotiation. During Auto-Negotiation, if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner, the Sequencer reconfigures to 1GbE and 10GbE modes (Speed/Parallel detection) until it detects a valid 1G or 10GbE pattern.
Table 113.
Speed Detection
Parameter Name
Enable automatic speed detection
On
Off
Options
Avalon-MM clock frequency
Link fail inhibit time for
10Gb Ethernet
Link fail inhibit time for
1Gb Ethernet
Enable PCS-Mode port
100-162 MHz
504 ms
40-50 ms
On
Off
Description
When you turn this option On, the core includes the Sequencer block that sends reconfiguration requests to detect 1G or 10GbE when the Auto Negotiation block is not able to detect AN data.
Specifies the clock frequency for phy_mgmt_clk
.
Specifies the time before link_status
is set to FAIL or OK. A link fails if the link_fail_inhibit_time
has expired before link_status
is set to OK. The legal range is 500-510 ms. For more information, refer to "Clause 73 Auto Negotiation for
Backplane Ethernet" in IEEE Std 802.3ap-2007.
Specifies the time before
link_status
is set to FAIL or OK . A link fails if the link_fail_inhibit_time
has expired before link_status
is set to OK. The legal range is 40-50 ms.
Enables or disables the PCS-Mode port.
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2.6.3.5. 10GBASE-KR PHY Interfaces
Figure 70.
10GBASE-KR Top-Level Signals
XGMII
Interfaces xgmii_tx_dc[71:0] xgmii_tx_clk xgmii_rx_dc[71:0] xgmii_rx_clk
10GBASE-KR Top-Level Ports
Avalon-MM PHY
Management
Interface mgmt_clk mgmt_clk_reset mgmt_address[10:0] mgmt_writedata[31:0] mgmt_readdata[31:0] mgmt_write mgmt_read mgmt_waitrequest rx_serial_data tx_serial_data rx_block_lock rx_hi_ber rx_is_lockedtodata tx_cal_busy rx_cal_busy rx_syncstatus lcl_rf rx_clkslip rx_latency_adj_10g[11:0] tx_latency_adj_10g[11:0] rx_data_ready
Clocks and
Reset
Interface tx_serial_clk_10g rx_cdr_ref_clk_10g tx_pma_clkout rx_pma_clkout tx_clkout rx_clkout tx_pma_div_clkout rx_pma_div_clkout tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset usr_seq_reset
Transceiver
Serial Data
Status
The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the _hw.tcl file. If you turn on Show signals, the block diagram displays all toplevel signal names.
Related Information
Component Interface Tcl Reference
For more information about _hw.tcl files
2.6.3.5.1. Clock and Reset Interfaces
Table 114.
Clock and Reset Signals
Signal Name tx_serial_clk_10g
Direction
Input tx_serial_clk_1g rx_cdr_ref_clk_10g rx_cdr_ref_clk_1g
Input
Input
Input
Description
High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz.
High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock is not required if GbE is not used. The frequency of this clock is 625
MHz.
10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
1G PHY RX PLL reference clock. The frequency is 125 MHz. This clock is only required if 1G is enabled.
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Signal Name tx_pma_clkout rx_pma_clkout tx_clkout rx_clkout tx_pma_div_clkout rx_pma_div_clkout tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset usr_seq_reset
Direction
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Description
Clock used to drive the 10G TX PCS and 1G TX PCS parallel data. For example, when the hard PCS is reconfigured to the 10G mode without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
Clock used to drive the 10G RX PCS and 1G RX PCS parallel data. For example, when the hard PCS is reconfigured to the 10G mode without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
XGMII/GMII TX clock for the TX parallel data source interface. This clock frequency is 257.81 MHz in 10G mode, and 161.13 MHz with
FEC enabled.
XGMII RX clock for the RX parallel data source interface. This clock frequency is 257.81 in 10G mode, and 161.13 MHz with FEC enabled.
The divided 33 clock from the TX serializer. You can use this clock for the for xgmii_tx_clk enable FEC.
or xgmii_rx_clk
. The frequency is 156.25
MHz for 10G. The frequencies are the same whether or not you
The divided 33 clock from CDR recovered clock. The frequency is
156.25 MHz for 10G. The frequencies are the same whether or not you enable FEC. This clock is not used for clocking the 10G RX datapath.
Resets the analog TX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the digital TX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the analog RX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the digital RX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the sequencer. Initiates a PCS reconfiguration, and may restart AN, LT or both if these modes are enabled. Synchronous to mgmt_clk
.
Related Information
•
Input Reference Clock Sources on page 372
•
2.6.3.5.2. Data Interfaces
Table 115.
XGMII Signals
The MAC drives the TX XGMII signals to the 10GbE PHY. The 10GbE PHY drives the RX XGMII signals to the
MAC.
Signal Name Direction xgmii_tx_dc[71:0
] xgmii_tx_clk
Input
Input
Clock Domain
10GbE XGMII Data Interface
Synchronous to xgmii_tx_clk
Description
XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.
Clock signal Clock for single data rate (SDR) XGMII TX interface to the
MAC. It should connect to connected to the xgmii_rx_clk
. This clock can be tx_div_clkout
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Signal Name Direction xgmii_rx_dc[71:0
]
Output xgmii_rx_clk
Input
Clock Domain
Synchronous to xgmii_rx_clk
Clock signal
Description recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
RX XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.
Clock for SDR XGMII RX interface to the MAC. This clock can be connected to the tx_div_clkout
; however, Intel recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
2.6.3.5.3. XGMII Mapping to Standard SDR XGMII Data
Table 116.
TX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name SDR XGMII Signal Name xgmii_tx_dc[7:0] xgmii_tx_dc[8] xgmii_tx_dc[16:9] xgmii_tx_dc[17] xgmii_tx_dc[25:18] xgmii_tx_dc[26] xgmii_tx_dc[34:27] xgmii_tx_dc[35] xgmii_tx_dc[43:36] xgmii_tx_dc[44] xgmii_tx_dc[52:45] xgmii_tx_dc[53] xgmii_tx_dc[61:54] xgmii_tx_dc[62] xgmii_tx_dc[70:63] xgmii_tx_dc[71] xgmii_sdr_data[7:0] xgmii_sdr_ctrl[0] xgmii_sdr_data[15:8] xgmii_sdr_ctrl[1] xgmii_sdr_data[23:16] xgmii_sdr_ctrl[2] xgmii_sdr_data[31:24] xgmii_sdr_ctrl[3] xgmii_sdr_data[39:32] xgmii_sdr_ctrl[4] xgmii_sdr_data[47:40] xgmii_sdr_ctrl[5] xgmii_sdr_data[55:48] xgmii_sdr_ctrl[6] xgmii_sdr_data[63:56] xgmii_sdr_ctrl[7]
Description
Lane 0 data
Lane 0 control
Lane 1 data
Lane 1 control
Lane 2 data
Lane 2 control
Lane 3 data
Lane 3 control
Lane 4 data
Lane 4 control
Lane 5 data
Lane 5 control
Lane 6 data
Lane 6 control
Lane 7 data
Lane 7 control
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Table 117.
RX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name XGMII Signal Name xgmii_rx_dc[7:0] xgmii_rx_dc[8] xgmii_rx_dc[16:9] xgmii_rx_dc[17] xgmii_rx_dc[25:18] xgmii_sdr_data[7:0] xgmii_sdr_ctrl[0] xgmii_sdr_data[15:8] xgmii_sdr_ctrl[1] xgmii_sdr_data[23:16]
Description
Lane 0 data
Lane 0 control
Lane 1 data
Lane 1 control
Lane 2 data xgmii_rx_dc[26] xgmii_rx_dc[34:27] xgmii_rx_dc[35] xgmii_rx_dc[43:36] xgmii_rx_dc[44] xgmii_rx_dc[52:45] xgmii_rx_dc[53] xgmii_rx_dc[61:54] xgmii_rx_dc[62] xgmii_rx_dc[70:63] xgmii_rx_dc[71] xgmii_sdr_ctrl[2] xgmii_sdr_data[31:24] xgmii_sdr_ctrl[3] xgmii_sdr_data[39:32] xgmii_sdr_ctrl[4] xgmii_sdr_data[47:40] xgmii_sdr_ctrl[5] xgmii_sdr_data[55:48] xgmii_sdr_ctrl[6] xgmii_sdr_data[63:56] xgmii_sdr_ctrl[7]
Lane 2 control
Lane 3 data
Lane 3 control
Lane 4 data
Lane 4 control
Lane 5 data
Lane 5 control
Lane 6 data
Lane 6 control
Lane 7 data
Lane 7 control
2.6.3.5.4. Serial Data Interface
Table 118.
Serial Data Signals
Signal Name rx_serial_data tx_serial_data
Direction
Input
Output
2.6.3.5.5. Control and Status Interfaces
Table 119.
Control and Status Signals
Signal Name led_link led_disp_err
Direction
Output
Output
Clock Domain
Synchronous to tx_clkout
Synchronous to rx_clkout led_an
Output Synchronous to rx_clkout
Description
RX serial input data
TX serial output data
Description
When asserted, indicates successful link synchronization.
Disparity error signal indicating a 10-bit running disparity error. Asserted for one
rx_clkout_1g
cycle when a disparity error is detected. A running disparity error indicates that more than the previous and perhaps the current received group had an error.
Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
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Signal Name led_panel_link rx_block_lock
Output rx_hi_ber
Output rx_is_lockedtodat a
Output tx_cal_busy
Output rx_cal_busy
Output tx_pcfifo_error_1 g
Output rx_pcfifo_error_1 g
Output lcl_rf
Input rx_clkslip rx_data_ready
Direction
Output
Input
Output rx_latency_adj_10 g[15:0]
Output
Clock Domain
Synchronous to mgmt_clk
Description
When asserted, this signal indicates the following behavior:
Mode
1000 Base-X without Autonegotiation
SGMII mode without Autonegotiation
1000 Base-X with Autonegotiation
SGMII mode with MAC mode Auto-negotiation
Behavior
When asserted, indicates successful link synchronization.
When asserted, indicates successful link synchronization.
Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
Synchronous to rx_clkout
Synchronous to rx_clkout
Asynchronous signal
Synchronous to mgmt_clk
Synchronous to mgmt_clk
N/A
N/A
Synchronous to xgmii_tx_clk
Asynchronous signal
Synchronous to xgmii_rx_clk
Synchronous to xgmii_rx_clk
Asserted to indicate that the block synchronizer has established synchronization.
Asserted by the BER monitor block to indicate a Sync
Header high bit error rate greater than 10 -4 .
When asserted, indicates the RX channel is locked to input data.
When asserted, indicates that the TX channel is being calibrated.
When asserted, indicates that the RX channel is being calibrated.
When asserted, indicates that the standard PCS TX phase compensation FIFO is either full or empty.
When asserted, indicates that the Standard PCS RX phase compensation FIFO is either full or empty.
When asserted, indicates a Remote Fault (RF).The MAC sends this fault signal to its link partner. Bit D13 of the
Auto Negotiation Advanced Remote Fault
register
(0xC2) records this error.
When asserted, the deserializer either skips one serial bit or pauses the serial clock for one cycle to achieve word alignment. As a result, the period of the parallel clock could be extended by 1 unit interval (UI) during the clock slip operation.This is an optional control input signal.
When asserted, indicates that the MAC can begin sending data to the PHY.
When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the RX
PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
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Signal Name tx_latency_adj_10 g[15:0]
Direction
Output
Clock Domain
Synchronous to xgmii_tx_clk rx_latency_adj_1 g[21:0]
Output tx_latency_adj_1 g[21:0]
Output
Synchronous to gmii_rx_clk
Synchronous to gmii_tx_clk
Description
When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the TX
PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
When you enable 1588, this signal outputs the real time latency in GMII clock cycles (125 MHz) for the RX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 21 represent the number of clock cycles.
When you enable 1588, this signal outputs the real time latency in GMII clock cycles (125 MHz) for the TX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 21 represent the number of clock cycles.
2.6.3.5.6. Dynamic Reconfiguration Interface
You can use the dynamic reconfiguration interface signals to dynamically change between 1G and 10G data rates.
Table 120.
Dynamic Reconfiguration Interface Signals
Signal Name rc_busy start_pcs_reconf ig mode_1g_10gbar
Direction
Output
Input
Input
Clock Domain
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Description
When asserted, indicates that reconfiguration is in progress. Synchronous to the mgmt_clk
. This signal is only exposed under the following condition:
• Turn on Enable internal PCS reconfiguration logic
When asserted, initiates reconfiguration of the PCS.
Sampled with the mgmt_clk
. This signal is only exposed under the following condition:
• Turn on Enable internal PCS reconfiguration logic
This signal selects either the 1G or 10G tx-parallel-data going to the PCS. It is only used for the 1G/10G application (variant) under the following circumstances:
• the Sequencer (auto-rate detect) is not enabled
• 1G mode is enabled
2.6.3.6. Avalon-MM Register Interface
The Avalon-MM slave interface signals provide access to all registers.
Table 121.
Avalon-MM Interface Signals
Signal Name mgmt_clk
Direction
Input
Clock Domain
Clock mgmt_clk_res et mgmt_addr[10
:0]
Input
Input
Asynchronous reset
Synchronous to mgmt_clk
Description
The clock signal that controls the Avalon-MM PHY management interface. If you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you must restrict the frequency to 100-125 MHz to meet the specification for the transceiver reconfiguration clock.
Resets the PHY management interface. This signal is active high and level sensitive.
11-bit Avalon-MM address.
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Signal Name mgmt_writeda ta[31:0] mgmt_readdat a[31:0] mgmt_write
Direction
Input
Output
Input mgmt_read mgmt_waitreq uest
Input
Output
Clock Domain
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Input data.
Output data.
Write signal. Active high.
Read signal. Active high.
Description
When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.
Related Information
Avalon Interface Specifications
2.6.3.6.1. 10GBASE-KR PHY Register Definitions
The Avalon-MM slave interface signals provide access to the control and status registers.
The following table specifies the control and status registers that you can access over the Avalon-MM PHY management interface. A single address space provides access to all registers.
Note: Unless otherwise indicated, the default value of all registers is 0.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 122.
10GBASE-KR Register Definitions
Word
Addr
0x4B0 0
Bit R/W
RW
Name
Reset SEQ
1
2
3
RW
RW
RW
Disable AN Timer
Disable LF Timer fail_lt_if_ber
Description
When set to 1, resets the 10GBASE-KR sequencer (auto rate detect logic), initiates a PCS reconfiguration, and may restart
Auto-Negotiation, Link Training or both if AN and LT are enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these modes. This reset self clears.
Auto-Negotiation disable timer. If disabled (
Disable AN
Timer = 1
) , AN may get stuck and require software support to remove the ABILITY_DETECT capability if the link partner does not include this feature. In addition, software may have to take the link out of loopback mode if the link is stuck in the
ACKNOWLEDGE_DETECT state. To enable this timer set
Disable AN Timer
= 0.
When set to 1, disables the Link Fail timer. When set to 0, the
Link Fault timer is enabled.
When set to 1, the last LT measurement is a non-zero number. Treat this as a failed run. 0 = normal.
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Word
Addr
7:4
Bit
8
0x4B1 0
1
11:9
12
16
17
18
2
13:8
16
17
0x4B2 0:10
11
RW
R
R
R/W
RW
RW
RW
RW
RW
RW
R
R
R
R
—
RW
Name Description
SEQ Force Mode[3:0]
Enable Arria 10
Calibration
Reserved
LT failure response
KR FEC enable 171.0
KR FEC enable err ind 171.1
KR FEC request
SEQ Link Ready
SEQ AN timeout
Forces the sequencer to a specific protocol. Must write the
Reset SEQ
bit to 1 for the Force to take effect. The following encodings are defined:
• 0000: No force
• 0001: GigE
• 0010: XAUI
• 0100: 10GBASE-R
• 0101: 10GBASE-KR
• 1100: 10GBASE-KR FEC
When set to 1, it enables the Arria 10 HSSI reconfiguration calibration as part of the PCS dynamic reconfiguration. 0 skips the calibration when the PCS is reconfigured.
—
When set to 1, LT failure causes the PHY to go into data mode. When set to 0, LT failure restarts auto-negotiation (if enabled). If auto-negotiation is not enabled, the PHY restarts
LT.
When set to 1, FEC is enabled. When set to 0, FEC is disabled. Resets to the CAPABLE_FEC parameter value.
When set to 1, KR PHY FEC decoding errors are signaled to the PCS. When set to 0, FEC errors are not signaled to the
PCS. See Clause 74.8.3 of IEEE 802.3ap-2007 for details.
When set to 1, enables the FEC request. When this bit changes, you must assert the
FEC request.
Reset SEQ
bit (0x4B0[0]) to renegotiate with the new value. When set to 0, disables the
When asserted, the sequencer is indicating that the link is ready.
When asserted, the sequencer has had an Auto Negotiation timeout. This bit is latched and is reset when the sequencer restarts Auto Negotiation.
When set, indicates that the Sequencer has had a timeout.
SEQ LT timeout
SEQ Reconfig
Mode[5:0]
Specifies the Sequencer mode for PCS reconfiguration. The following modes are defined:
• Bit 8, mode[0]: AN mode
• Bit 9, mode[1]: LT Mode
• Bit 10, mode[2]: 10G data mode
• Bit 11, mode[3]: GigE data mode
• Bit 12, mode[4]: Reserved for XAUI
• Bit 13, mode[5]: 10G FEC mode
KR FEC ability 170.0
When set to 1, indicates that the 10GBASE-KR PHY supports
FEC. Set as parameter
SYNTH_FEC
. For more information, refer to Clause 45.2.1.84 of IEEE 802.3ap-2007.
KR FEC err ind ability 170.0
Reserved
KR FEC TX Error
Insert
When set to 1, indicates that the 10GBASE-KR PHY is capable of reporting FEC decoding errors to the PCS. For more information, refer to Clause 74.8.3 of IEEE 802.3ap-2007.
—
Writing a 1 inserts one error pulse into the TX FEC depending on the Transcoder and Burst error settings. This bit self clears.
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Word
Addr
Bit
31:12
0x4B5 to
0x4BF
0x4C0 0
1
2
3
0x4C1 0
4
4
5
8
0x4C2 1
2
3
4
R/W
—
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
Name Description
Reserved
Reserved for 40G KR
AN enable
AN base pages ctrl
AN next pages ctrl
Local device remote fault
Reset AN
Restart AN TX SM
AN Next Page
AN page received
AN Complete
AN ADV Remote Fault
AN RX SM Idle
—
Intentionally left empty for address compatibility with 40G
MAC + PHY KR solutions.
When set to 1, enables Auto Negotiation function. The default value is 1. For additional information, refer to 7.0.12 in
Clause 73.8 Management Register Requirements, of IEEE
802.3ap-2007.
When set to 1, the user base pages are enabled. You can send any arbitrary data via the user base page low/high bits.
When set to 0, the user base pages are disabled and the state machine generates the base pages to send.
When set to 1, the user next pages are enabled. You can send any arbitrary data via the user next page low/high bits. When set to 0, the user next pages are disabled. The state machine generates the null message to send as next pages.
When set to 1, the local device signals Remote Faults in the
Auto Negotiation pages. When set to 0, a fault has not occurred.
Force TX nonce value
When set to 1, forces the TX nonce value to support some
UNH testing modes. When set to 0, this is normal operation.
Override AN
Parameters Enable
When set to 1, overrides the
AN_TECH
,
AN_FEC
, and
AN_PAUSE
parameters and uses the bits in 0x4C3 instead.
You must reset the Sequencer to reconfigure and restart into
Auto Negotiation mode. When set to 0, this is normal operation and is used with 0x4B0 bit 0 and 0x4C3 bits[30:16].
When set to 1, resets all the 10GBASE-KR Auto Negotiation state machines. This bit is self-clearing.
When set to 1, restarts the 10GBASE-KR TX state machine.
This bit self clears. This bit is active only when the TX state machine is in the Auto Negotiation state. For more information, refer to 7.0.9 in Clause 73.8 Management
Register Requirements of IEEE 802.3ap-2007.
When asserted, new next page info is ready to send. The data is in the XNP TX registers. When 0, the TX interface sends null pages. This bit self clears. Next Page (NP) is encoded in bit D15 of Link Codeword. For more information, refer to
Clause 73.6.9 and 7.16.15 of Clause 45.2.7.6 of IEEE
802.3ap-2007.
When set to 1, a page has been received. When 0, a page has not been received. The current value clears when the register is read. For more information, refer to 7.1.6 in Clause 73.8 of
IEEE 802.3ap-2007.
When asserted, Auto-Negotiation has completed. When 0,
Auto Negotiation is in progress. For more information, refer to
7.1.5 in Clause 73.8 of IEEE 802.3ap-2007.
When set to 1, fault information has been sent to the link partner. When 0, a fault has not occurred. The current value clears when the register is read. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword. For more information, refer to Clause 73.6.7 of and 7.16.13 of IEEE 802.3ap-2007.
When set to 1, the Auto-Negotiation state machine is in the idle state. Incoming data is not Clause 73 compatible. When
0, the Auto-Negotiation is in progress.
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Word
Addr
5
6
7
0x4C2 8
9
Bit
17:12
0x4C3 15:0
21:16
25:24
R/W
RO
RO
RO
RO
RO
RO
RW
RW
RW
Name Description
AN Ability
AN Status
LP AN Ability
When set to 1, the transceiver PHY is able to perform Auto
Negotiation. When set to 0, the transceiver PHY i s not able to perform Auto Negotiation. If your variant includes Auto
Negotiation, this bit is tied to 1. For more information, refer to 7.1.3 and 7.48.0 of Clause 45 of IEEE 802.3ap-2007.
When set to 1, link is up. When 0, the link is down. The current value clears when the register is read. For more information, refer to 7.1.2 of Clause 45 of IEEE
802.3ap-2007.
When set to 1, the link partner is able to perform Auto
Negotiation. When 0, the link partner is not able to perform
Auto-Negotiation. For more information, refer to 7.1.0 of
Clause 45 of IEEE 802.3ap-2007.
When set to 1, PHY is negotiated to perform FEC. When set to
0, PHY is not negotiated to perform FEC.
FEC negotiated – enable FEC from SEQ
Seq AN Failure
When set to 1, a sequencer Auto Negotiation failure has been detected. When set to 0, an Auto Negotiation failure has not been detected.
KR AN Link
Ready[5:0]
User base page low
Provides a one-hot encoding of an_receive_idle
73.10.1. The following encodings are defined:
= true and link status for the supported link as described in Clause
• 6'b000000: 1000BASE-KX
• 6'b000001: 10GBASE-KX4
• 6'b000100: 10GBASE-KR
• 6'b001000: 40GBASE-KR4
• 6'b010000: 40GBASE-CR4
• 6'b100000: 100GBASE-CR10
The Auto Negotiation TX state machine uses these bits if the
Auto Negotiation base pages ctrl bit is set. The following bits are defined:
• [15]: Next page bit
• [14]: ACK which is controlled by the SM
• [13]: Remote Fault bit
• [12:10]: Pause bits
• [9:5]: Echoed nonce which are set by the state machine
• [4:0]: Selector
Bit 49, the PRBS bit, is generated by the Auto Negotiation TX state machine.
Override
AN_TECH[5:0]
AN_TECH
value with which to override the current value. The following bits are defined:
• Bit-16 =
AN_TECH[0]
= 1000BASE-KX
• Bit-17 =
AN_TECH[1]
= XAUI
• Bit-18 =
AN_TECH[2]
= 10GBASE-KR
• Bit-19 =
AN_TECH[3]
= 40G
• Bit-20 =
AN_TECH[4]
= CR-4
• Bit-21 =
AN_TECH[5]
= 100G
You must set 0x4C0 bit-5 for this to take effect .
Override AN_FEC[1:0] AN_FEC
value with which to override the current value. The following bits are defined:
• Bit-24 =
AN_ FEC [0]
= Capability
• Bit-25 =
AN_ FEC [1]
= Request
You must set 0x4C0 bit-5 for this to take effect.
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Word
Addr
Bit
30:28
0x4C4 31:0
0x4C5 15:0
0x4C6 31:0
0x4C7 15:0
0x4C8 31:0
0x4C9 15:0
R/W
RW
RW
RW
RW
RO
RO
RO
Name Description
Override
AN_PAUSE[2:0]
User base page high
User Next page low
User Next page high
LP base page low
LP base page high
LP Next page low
AN_PAUSE value with which to override the current value. The following bits are defined:
• Bit-28 =
AN_PAUSE [0]
= Pause Ability
• Bit-29 =
AN_PAUSE [1]
= Asymmetric Direction
• Bit-30 =
AN_PAUSE [2]
= Reserved
You must set 0x4C0 bit-5 for this to take effect.
The Auto Negotiation TX state machine uses these bits if the
Auto Negotiation base pages ctrl bit is set. The following bits are defined:
• [29:5]: Correspond to page bits 45:21 which are the technology ability.
• [4:0]: Correspond to bits 20:16 which are TX nonce bits.
Bit 49, the PRBS bit, is generated by the Auto Negotiation TX state machine.
The Auto Negotiation TX state machine uses these bits if the
AN Next Page
control bit is set. The following bits are defined:
• [15]: next page bit
• [14]: ACK controlled by the state machine
• [13]: Message Page (MP) bit
• [12]: ACK2 bit
• [11]: Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007. Bit 49, the PRBS bit, is generated by the Auto-Negotiation TX state machine.
The Auto Negotiation TX state machine uses these bits if the
Auto Negotiation next pages ctrl bit is set. Bits [31:0] correspond to page bits [47:16]. Bit 49, the PRBS bit, is generated by the Auto Negotiation TX state machine.
The AN RX state machine receives these bits from the link partner. The following bits are defined:
• [15] Next page bit
• [14] ACK which is controlled by the state machine
• [13] RF bit
• [12:10] Pause bits
• [9:5] Echoed Nonce which are set by the state machine
• [4:0] Selector
The AN RX state machine receives these bits from the link partner. The following bits are defined:
• [31:30]: Reserved
• [29:5]: Correspond to page bits [45:21] which are the technology ability
• [4:0]: Correspond to bits [20:16] which are TX Nonce bits
The AN RX state machine receives these bits from the link partner. The following bits are defined:
• [15]: Next page bit
• [14]: ACK which is controlled by the state machine
• [13]: MP bit
• [12] ACK2 bit
• [11] Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007.
continued...
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Word
Addr
0x4CA
Bit
31:0
0x4CB 24:0
26:25
27
30:28
0x4D0 0
1
2
3
7:4
11:8
0x4D0 14:12
RW
RW
RW
R/W
RO
RO
RO
RO
RO
RW
RW
RW
RW
Name Description
LP Next page high
AN LP ADV
Tech_A[24:0]
The AN RX state machine receives these bits from the link partner. Bits [31:0] correspond to page bits [47:16]
Received technology ability field bits of Clause 73 Auto
Negotiation. The 10GBASE-KR PHY supports A0 and A2. The following protocols are defined:
• A0 1000BASE-KX
• A1 10GBASE-KX4
• A2 10GBASE-KR
• A3 40GBASE-KR4
• A4 40GBASE-CR4
• A5 100GBASE-CR10
• A24:6 are reserved
For more information, refer to Clause 73.6.4 and AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE
802.3ap-2007.
AN LP ADV FEC_F[1:0]
Received FEC ability bits FEC (F0:F1) is encoded in bits
D46:D47 of the base Link Codeword. F0 is FEC ability. F1 is
FEC requested. See Clause 73.6.5 of IEEE 802.3ap-2007 for details.
AN LP ADV Remote
Fault
AN LP ADV Pause
Ability_C[2:0]
Received Remote Fault (RF) ability bits. RF is encoded in bit
D13 of the base link codeword in Clause 73 AN. For more information, refer to Clause 73.6.7 of IEEE 802.3ap-2007.
Received pause ability bits. Pause (C0:C1) is encoded in bits
D11:D10 of the base link codeword in Clause 73 AN as follows:
• C0 is the same as PAUSE as defined in Annex 28B
• C1 is the same as ASM_DIR as defined in Annex 28B
• C2 is reserved
Link Training enable
When 1, enables the 10GBASE-KR start-up protocol. When 0, disables the 10GBASE-KR start-up protocol. The default value is 1. For more information, refer to Clause 72.6.10.3.1 and
10GBASE-KR PMD control register bit (1.150.1) of IEEE
802.3ap-2007.
dis_max_wait_tmr
Reserved
Reserved main_step_cnt [3:0] prepost_step_cnt
[3:0] equal_cnt [2:0]
When set to 1, disables the LT values. The default value is 0.
max_wait_timer
. Used for characterization mode when setting much longer BER timer
Reserved
Reserved
Specifies the number of equalization steps for each main tap update. There are about 20 settings for the internal algorithm to test. The valid range is 1-15. The default value is 4'b0001.
Specifies the number of equalization steps for each pre- and post-tap update. From 16-31 steps are possible. The default value is 4'b0001.
Adds hysteresis to the error count to avoid local minimums.
The following values are defined:
• 000 = 0
• 001 = 2
• 010 = 4
• 011 = 8
• 100 = 16 continued...
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Word
Addr
15
16
17
0x4D0 18
19
0x4D0 22
Bit
21:20
R/W
RW
RW
RW
RW
RW
RW
RW
Name Description disable Initialize
PMA on max_wait_timeout
Ovride LP Coef enable
Ovride Local RX Coef enable
VOD Training Enable
Bypass DFE dfe_freeze_mode adp_ctle_vga_mode
• 101 = 32
• 110 = 64
• 111 = 128
The default value is 101.
When set to 1, PMA values (VOD, Pre-tap, Post-tap) are not initialized upon entry into the happens when
Training_Failure
state. This max_wait_timer_done
, which sets training_failure
= true (reg 0xD2 bit 3). Used for UNH testing. When set to 0, PMA values are initialized upon entry into
Training_Failure
state. Refer to Figure 72-5 of IEEE
802.3ap-2007 for more details. The default value is 0.
When set to 1, overrides the link partner's equalization coefficients; software changes the update commands sent to the link partner TX equalizer coefficients. When set to 0, uses the Link Training logic to determine the link partner coefficients. Used with 0x4D1 bit-4 and 0x4D4 bits[7:0]. The default value is 0.
When set to 1, overrides the local device equalization coefficients generation protocol. When set, the software changes the local TX equalizer coefficients. When set to 0, uses the update command received from the link partner to determine local device coefficients. Used with 0x4D1 bit-8 and
0x4D4 bits[23:16]. The default value is 0.
Defines whether or not to skip adjustment of the link partner’s VOD (main tap) during link training. The following values are defined:
• 1 = Exercise VOD (main tap) adjustment during link training
• 0 = Skip VOD (main tap) adjustment during link training
The default value is 0.
Defines whether or not Decision Feedback Equalization (DFE) is enabled at the end of link training. The following values are defined:
• 1 = Bypass continuous adaptive DFE at the end of link training
• 0 = Enable continuous adaptive DFE at the end of link training
The default value for simulation is 1. The default value for hardware is 0.
Defines the behavior of DFE taps at the end of link training
• 00 = do not freeze any DFE taps
• 01 = Freeze all DFE taps
• 10 = reserved
• 11 = reserved
The default value is 01.
Note: These bits are only effective when bit [19] is set to 0.
Defines whether or not CTLE/VGA adaptation is in adaptive or manual mode. The following values are defined:
• 0 = CTLE sweep before start of TX-EQ during link training.
• 1 = manual CTLE mode. Link training algorithm sets fixed
CTLE value, as specified in bits [28:24]. The default value is 1 for simulation. .
The default value is 0 for hardware.
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Word
Addr
Bit
28:24
31:29
0x4D1 0
4
8
0x4D2
21:20
0
1
2
3
6
7
4
5
R/W
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
Name Description
Manual CTLE
Manual VGA
Restart Link training
Defines the CTLE value used by the link training algorithm when in manual CTLE mode. These bits are only effective when 0x4D0[22] is set to 1.
The default value is 1.
Defines the VGA value used by the link training algorithm when in manual VGA mode. These bits are only effective when 0x4D0[22] is set to 1.
The default value is 4 for simulation. The default value is 7 for hardware.
When set to 1, resets the 10GBASE-KR start-up protocol.
When set to 0, continues normal operation. This bit self clears. For more information, refer to the state variable mr_restart_training
as defined in Clause 72.6.10.3.1
and 10GBASE-KR PMD control register bit (1.150.0) IEEE
802.3ap-2007.
Updated TX Coef new
Updated RX coef new
Reserved
Link Trained -
Receiver status
Link Training Frame lock
Link Training Startup protocol status
Link Training failure
Link Training Error
Link Training Frame lock Error
When set to 1, there are new link partner coefficients available to send. The LT logic starts sending the new values set in 0x4D4 bits[7:0] to the remote device. When set to 0, continues normal operation. This bit self clears. Must enable this override in 0x4D0 bit16.
When set to 1, new local device coefficients are available. The
LT logic changes the local TX equalizer coefficients as specified in 0x4D4 bits[23:16]. When set to 0, continues normal operation. This bit self clears. Must enable the override in 0x4D0 bit17.
Reserved
When set to 1, the receiver is trained and is ready to receive data. When set to 0, receiver training is in progress. For more information, refer to the state variable rx_trained as defined in Clause 72.6.10.3.1 of IEEE 802.3ap-2007.
When set to 1, the training frame delineation has been detected. When set to 0, the training frame delineation has not been detected. For more information, refer to the state variable frame_lock as defined in Clause 72.6.10.3.1 of IEEE
802.3ap-2007.
When set to 1, the start-up protocol is in progress. When set to 0, start-up protocol has completed. For more information, refer to the state training as defined in Clause 72.6.10.3.1 of
IEEE 802.3ap-2007.
When set to 1, a training failure has been detected. When set to 0, a training failure has not been detected For more information, refer to the state variable training_failure as defined in Clause 72.6.10.3.1 of IEEE 802.3ap-2007.
When set to 1, excessive errors occurred during Link Training.
When set to 0, the BER is acceptable.
When set to 1, indicates a frame lock was lost during Link
Training. If the tap settings specified by the fields of 0x4D5 are the same as the initial parameter value, the frame lock error was unrecoverable.
RXEQ Frame Lock Loss
Frame lock not detected at some point during RXEQ, possibly triggering conditional RXEQ mode.
CTLE Fine-grained
Tuning Error
Could not determine the best CTLE due to maximum BER limit at each step in the Fine-grained Tuning mode.
continued...
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Word
Addr
0x4D3 9:0
Bit
19:10 RW ber_time_k_frames
29:20
0x4D4 5:0
6
7
0x4D4 13:8
R/W
RW
Name ber_time_frames
RW ber_time_m_frames
RO or
RW
RO or
RW
RO or
RW
RO
LD coefficient update[5:0]
LD Initialize
Coefficients
LD Preset
Coefficients
LD coefficient status[5:0]
Description
Specifies the number of training frames to examine for bit errors on the link for each step of the equalization settings.
Used only when ber_time_k_frames is 0.The following values are defined:
• A value of 2 is about 10 3 bytes
• A value of 20 is about 10 4 bytes
• A value of 200 is about 10 5 bytes
The default value for simulation is 2'b11. The default value for hardware is 0.
Specifies the number of thousands of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_m_frames = 0 for time/ bits to match the following values:
• A value of 3 is about 10 7 bits = about 1.3 ms
• A value of 25 is about 10 8 bits = about 11ms
• A value of 250 is about 10 9 bits = about 11 0ms
The default value for simulation is 0. The default value for hardware is 0xF.
Specifies the number of millions of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_k_frames = 4'd1000 = 0x43E8 for time/bits to match the following values:
• A value of 3 is about 10 10 bits = about 1.3 seconds
• A value of 25 is about 10 11 bits = about 11 seconds
• A value of 250 is about 10 12 bits = about 110 seconds
Reflects the contents of the first 16-bit word of the training frame sent from the local device control channel. Normally, the bits in this register are read-only; however, when you override training by setting the
Ovride Coef enable control bit, these bits become writable. The following fields are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to 10G BASE-KR LD coefficient update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE
802.3ap-2007.
When set to 1, requests the link partner coefficients be set to configure the TX equalizer to its INITIALIZE state. When set to 0, continues normal operation. For more information, refer to 10G BASE-KR LD coefficient update register bits (1.154.12) in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE
802.3ap-2007.
When set to 1, requests the link partner coefficients be set to a state where equalization is turned off. When set to 0 the link operates normally. For more information, refer to 10G
BASE-KR LD coefficient update register bit (1.154.13) in
Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE
802.3ap-2007.
Status report register for the contents of the second, 16-bit word of the training frame most recently sent from the local device control channel. The following fields are defined: continued...
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Word
Addr
14
0x4D4 21:16
22
23
Bit
0x4D4 29:24
R/W Name Description
RO
RO or
RW
RO or
RW
RO or
RW
RO
Link Training ready
- LD Receiver ready
LP coefficient update[5:0]
LP Initialize
Coefficients
LP Preset
Coefficients
LP coefficient status[5:0]
• [5:4]: Coefficient (post-tap)
— 2'b11: Maximum
— 2'b01: Minimum
— 2'b10: Updated
— 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• [1:0]: Coefficient (pre-tap) (same encoding as [5:4])
For more information, refer to 10G BASE-KR LD status report register bit (1.155.5:0) in Clause 45.2.1.81 of IEEE
802.3ap-2007.
When set to 1, the local device receiver has determined that training is complete and is prepared to receive data. When set to 0, the local device receiver is requesting that training continue. Values for the receiver ready bit are defined in
Clause 72.6.10.2.4.4. For more information, refer to 10G
BASE-KR LD status report register bit (1.155.15) in Clause
45.2.1.81 of IEEE 802.3ap-2007.
Reflects the contents of the first 16-bit word of the training frame most recently received from the control channel.
Normally the bits in this register are read only; however, when training is disabled by setting low the KR Training enable control bit, these bits become writable. The following fields are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to 10G BASE-KR LP coefficient update register bits (1.152.5:0) in Clause 45.2.1.78.3 of IEEE
802.3ap-2007.
When set to 1, the local device transmit equalizer coefficients are set to the INITIALIZE state. When set to 0, normal operation continues. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. For more information, refer to 10G BASE-KR LP coefficient update register bits
(1.152.12) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
When set to 1, the local device TX coefficients are set to a state where equalization is turned off. Preset coefficients are used. When set to 0, the local device operates normally. The function and values of the preset bit are defined in
72.6.10.2.3.1. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. For more information, refer to 10G BASE-KR LP coefficient update register bits (1.152.13) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
Status report register reflects the contents of the second, 16bit word of the training frame most recently received from the control channel: The following fields are defined: continued...
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Word
Addr
30
0x4D5 4:0
Bit
13:8
20:16
0x4D5
0x4D6
27:24
29:28
31:30
4:0
5
12:8
R
R
R/W
RO
R
R
R
R
RW
RW
RW
Name Description
LP Receiver ready
LT V
OD
setting
LT Post-tap setting
LT Pre-tap setting
RXEQ CTLE Setting
RXEQ CTLE Mode
RXEQ DFE Mode
LT VODMAX ovrd
LT VODMAX ovrd
Enable
LT VODMin ovrd
• [5:4]: Coefficient (+1)
— 2'b11: Maximum
— 2'b01: Minimum
— 2'b10: Updated
— 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• n [1:0]: Coefficient (-1) (same encoding as [5:4])
For more information, refer to 10G BASE-KR LP status report register bits (1.153.5:0) in Clause 45.2.1.79 of IEEE
802.3ap-2007.
When set to 1, the link partner receiver has determined that training is complete and is prepared to receive data. When set to 0, the link partner receiver is requesting that training continue.
Values for the receiver ready bit are defined in Clause
72.6.10.2.4.4. For more information, refer to 10G BASE-KR
LP status report register bits (1.153.15) in Clause 45.2.1.79
of IEEE 802.3ap-2007.
Stores the most recent TX V
OD
setting trained by the link partner's RX based on the LT coefficient update logic driven by Clause 72. It reflects Link Partner commands to fine-tune the TX preemphasis taps.
Stores the most recent TX post-tap setting trained by the link partner’s RX based on the LT coefficient update logic driven by Clause 72. It reflects Link Partner commands to fine-tune the TX pre-emphasis taps.
Store the most recent TX pre-tap setting trained by the link partner’s RX based on the LT coefficient update logic driven by Clause 72. It reflects Link Partner commands to fine-tune the TX pre-emphasis taps.
Most recent ctle_rc
setting sent to the reconfig bundle during RX equalization.
Most recent ctle_mode during RX equalization.
setting sent to the reconfig bundle
Most recent dfe_mode during RX equalization.
setting sent to the reconfig bundle
Override value for the VMAXRULE parameter. When enabled, this value substitutes for the VMAXRULE to allow channelby-channel override of the device settings. This only affects the local device TX output for the channel specified.
This value must be greater than the INITMAINVAL parameter for proper operation. Note this also overrides the
PREMAINVAL parameter value.
When set to 1, enables the override value for the VMAXRULE parameter stored in the
LT VODMAX ovrd
register field.
Override value for the VODMINRULE parameter. When enabled, this value substitutes for the VMINRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.
The value to be substituted must be less than the
INITMAINVAL parameter and greater than the VMINRULE parameter for proper operation.
continued...
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Word
Addr
Bit R/W Name Description
0x4D7 to 0x4FF
13
21:16
22
28:24
29
RW
RW
RW
RW
RW
LT VODMin ovrd
Enable
LT VPOST ovrd
When set to 1, enables the override value for the
VODMINRULE parameter stored in the register field.
LT VODMin ovrd
Override value for the VPOSTRULE parameter. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.
The value to be substituted must be greater than the
INITPOSTVAL parameter for proper operation.
LT VPOST ovrd Enable
When set to 1, enables the override value for the
VPOSTRULE parameter stored in the register field.
LT VPOST ovrd
LT VPre ovrd
LT VPre ovrd Enable
Reserved for 40G KR
Override value for the VPRERULE parameter. When enabled, this value substitutes for the VPOSTRULE to allow channelby-channel override of the device settings. This override only effects the local device TX output for this channel.
The value to be substituted must be greater than the
INITPREVAL parameter for proper operation.
When set to 1, enables the override value for the VPRERULE parameter stored in the
LT VPre ovrd
register field.
Left empty for address compatibility with 40G MAC+PHY KR solution.
2.6.3.6.2. Hard Transceiver PHY Registers
Table 123.
Hard Transceiver PHY Registers
Addr
0x000-0 x3FF
Bit
[9:0]
Access
RW
Name
Access to HSSI registers
Description
All registers in the physical coding sub-layer (PCS) and physical media attachment (PMA) that you can dynamically reconfigure are in this address space. Refer to the Arria 10 Dynamic
Transceiver Reconfiguration chapter for further information.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration
on page 502
2.6.3.6.3. Enhanced PCS Registers
Table 124.
Enhanced PCS Registers
Addr
0x480
Bit
31:0
Access
RW
Name
Indirect_addr
0x481 2
3
RW
RW
RCLR_ERRBLK_CNT
RCLR_BER_COUNT
Description
Because the PHY implements a single channel, this register must remain at the default value of 0 to specify logical channel 0.
Error block counter clear register. When set to 1, clears the
RCLR_ERRBLK_CNT operation continues.
register. When set to 0, normal
BER counter clear register. When set to 1, clears the
RCLR_BER_COUNT
register. When set to 0, normal operation continues.
continued...
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Addr
0x482 1
Bit
2
3
4
7
Access
RO
HI_BER
Name
RO
RO
RO
RO
BLOCK_LOCK
TX_FIFO_FULL
RX_FIFO_FULL
Rx_DATA_READY
Description
High BER status. When set to 1, the PCS reports a high
BER. When set to 0, the PCS does not report a high
BER.
Block lock status. When set to 1, the PCS is locked to received blocks. When set to 0, the PCS is not locked to received blocks.
When set to 1, the
TX_FIFO
is full.
When set to 1, the
RX_FIFO
is full.
When set to 1, indicates the PHY is ready to receive data.
2.6.3.6.4. PMA Registers
The PMA registers allow you to reset the PMA, customize the TX and RX serial data interface, and provide status information.
Table 125.
1G Data Mode
Addr
0x4A8 0
Bit R/W
RW
Name tx_invpolarity
0x4A9
1
2
3
5
6
3
4
1
2
4
0
RW
RW
RW
R
R
R
R
R
R
RW
R rx_invpolarity rx_bitreversal_enable rx_bytereversal_enable force_electrical_idle rx_syncstatus rx_patterndetect rx_rlv rx_rmfifodatainserted rx_rmfifodatadeleted rx_disperr rx_errdetect
Description
When set, the TX interface inverts the polarity of the TX data to the 8B/10B encoder.
When set, the RX channels inverts the polarity of the received data to the 8B/10B decoder.
When set, enables bit reversal on the RX interface to the word aligner.
When set, enables byte reversal on the RX interface to the byte deserializer.
When set, forces the TX outputs to electrical idle.
When set, the word aligner is synchronized.
GbE word aligner detected comma.
Run length violation.
Rate match FIFO inserted code group.
Rate match FIFO deleted code group.
RX 8B10B disparity error.
RX 8B10B error detected.
Table 126.
PMA Registers
Address
0x444 1
0x461
2
3
0
Bit R/W
RW
RW
RW
RW
Name reset_tx_digital reset_rx_analog reset_rx_digital
Description
Writing a 1 asserts the internal TX digital reset signal. You must write a 0 to clear the reset condition.
Writing a 1 causes the internal RX analog reset signal to be asserted. You must write a 0 to clear the reset condition.
Writing a 1 causes the internal RX digital reset signal to be asserted. You must write a 0 to clear the reset condition.
phy_serial_loopback
Writing a 1 puts the channel in serial loopback mode.
continued...
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Address
0x464 0
Bit
0x465 0
0x466 0
0x467 0
R/W
RW
Name pma_rx_set_locktoda ta
RW pma_rx_set_locktore f
RO pma_rx_is_lockedtod ata
RO pma_rx_is_lockedtor ef
Description
When set, programs the RX clock data recovery (CDR) PLL to lock to the incoming data.
When set, programs the RX CDR PLL to lock to the reference clock.
When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to
LTD mode.
When asserted, indicates that the RX CDR PLL is locked to the reference clock.
2.6.3.7. Creating a 10GBASE-KR Design
Follow these steps to create a 10GBASE-KR design.
1. Generate the 10GBASE-KR PHY with the required parameterization.
The 10GBASE-KR PHY IP core includes a reconfiguration block. The reconfiguration block provides the Avalon-MM interface to access the PHY registers.
2. Instantiate a reset controller. You can generate a Transceiver Reset Controller IP core from the IP Catalog. You must connect the Transceiver Reset Controller IP core and 10GBASE-KR PHY IP core power and reset signals.
3. Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate.
Connect the high speed serial clock and PLL lock signals between 10GBASE-KR
PHY and TX PLLs. For the 1G data rate you can use either fPLL, ATX PLL, or CMU
PLL. For the 10G data rate you can use ATX PLL or CMU PLL.
4. Generate a fPLL to create the 156.25 MHz XGMII clock from the 10G reference clock.
5. Use the tx_pma_divclk
from the 10GBASE-KR PHY or generate a fPLL to create the 156.25 MHz XGMII clock from the 10G reference clock.
Unlike in the 10GBASE-KR PHY IP core for Stratix V devices, no Memory
Initialization Files (.mif) are required for the 10GBASE-KR design in Arria 10 devices.
6. Complete the design by creating a top level module to connect all the IP
(10GBASE-KR PHY IP core, PLL IP core, and Reset Controller) blocks.
Related Information
•
on page 359
•
on page 368
•
on page 350
•
Using the Transceiver PHY Reset Controller
on page 433
•
10GBASE-KR Functional Description
on page 136
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2.6.3.8. Design Example
Figure 71.
PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side
(1G/10G) Ethernet Channels
A10_DE_WRAPPER
Management
Master
ISSP
JTAG-to-
Avalon-MM
Master
Test Harness
XGMII
Source
XGMII
Source
XGMII
Sink
XGMII
Sink
XGMII
GEN
XGMII
GEN
TH0_ADDR = 0xF nnn
XGMII
CHK
XGMII
CHK
...
Clock and
Reset
A10_IP_WRAPPER
XGMII
CLK FPLL
1G Ref CLK
CMU PLL
10G Ref CLK
ATX PLL
Reset
Control
Reset
Control
Reset
Control
Reset
Control
CH0: PHY_ADDR = 0x0
CH1: PHY_ADDR = 0x1
CH2: PHY_ADDR = 0x2
CH3: PHY_ADDR = 0x3
KR PHY IP
KR PHY IP
KR PHY IP
KR PHY IP
Sequencer
1588 Soft
FIFOs
Sequencer
STD
TX PCS
1588 Soft
FIFOs 1588 Soft
FIFOs
GMII
RS
GMII
RS
Auto Neg cls 73
Auto Neg cls 73
Sequencer
10-GB
TX PCS
Sequencer
Link Training cls 72
Link Training cls 72
GMII
RS GMII
RS
STD
RX PCS
Auto Neg cls 73 Auto Neg cls 73
Link Training cls 72 cls 72
10-GB
RX PCS
A10
Reconfiguration
NF
Reconfiguration
STD
TX PCS
Registers CSR
Avalon-MM Slave
Reconfiguration
STD
TX PCS STD
TX PCS
Registers CSR
Native Hard PHY
NF
TX PMA
Registers CSR
Native Hard PHY
Registers CSR
Avalon-MM Slave
Native Hard PHY
TX PMA
Native Hard PHY
TX PMA
TX PMA
10-GB
TX PCS
STD
RX PCS
10-GB
RX PCS
Divide
10-GB
TX PCS
STD
RX PCS
10-GB
RX PCS
10-GB
TX PCS
STD
RX PMA
10-GB
RX PCS
RX PMA
RX PMA
RX PMA
Divide
Divide
Divide
Related Information
• Arria 10 Transceiver PHY Design Examples
• 10-Gbps Ethernet MAC IP Function User Guide.
For more information about latency in the MAC as part of the Precision Time
Protocol implementation.
2.6.3.9. Simulation Support
The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Intel-supported simulators for this Quartus Prime software release:
• ModelSim Verilog
• ModelSim VHDL
• VCS Verilog
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• VCS VHDL
• NCSIM Verilog
• NCSIM VHDL simulation
When you generate a 1G/10GbE or 10GBASE-KR PHY IP core, the Quartus Prime software optionally generates an IP functional simulation model.
2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core
The Ethernet standard comprises many different PHY standards with variations in signal transmission medium and data rates.
The 1G/10Gbps Ethernet PHY IP core targets the reconfigurable 10-Mbps/100-Mbps/1-
Gbps/10-Gbps data rates with one core dynamically. This Ethernet PHY interfaces to
1G/10GbE dual speed SFP+ pluggable modules, 10MB–10GbE 10GBASE-T, and 10MB/
100MB/1000MB 1000BASE-T copper external PHY devices to drive CAT-6/7 shielded twisted pair cables, and chip-to-chip interfaces.
The 1G/10 Gbps Ethernet PHY (1G/10GbE ) IP function allows you to support the following features of Ethernet standards:
• 1 GbE protocol as defined in Clause 36 of the IEEE 802.3-2008 Standard
• GMII to connect the PHY with a media access control (MAC) as defined in Clause
35 of the IEEE 802.3-2008 Standard
• Gigabit Ethernet Auto-negotiation as defined in Clause 37 of the IEEE 802.3-2008
Standard
• 10GBASE-R Ethernet protocol as defined in Clause 49 of the IEEE 802.3-2008
Standard
• Single data rate (64 data bits and 8 control bits) XGMII to provide simple and inexpensive interconnection between the MAC and the PHY as defined in Clause 46 of the IEEE 802.3-2008 Standard
• SGMII 10-Mbps/100-Mbps/1-Gbps data rate where 10-Mbps/100-Mbps MII to connect physical media with the MAC as defined in Clause 22 of the IEEE
802.3-2008 Standard
• Forward Error correction(FEC) as defined in Clause 74 of the IEEE 802.3-2008
Standard
• Precision time protocol (PTP) as defined in the IEEE 1588 Standard
The 1G/10Gbps Ethernet PHY IP Core allows you to implement the 1GbE protocol using the Standard PCS and to implement the 10GbE protocol using Enhanced PCS and PMA. You can switch dynamically between the 1G and 10G data rates using dynamic reconfiguration to reprogram the core. Or, you can use the speed detection option to automatically switch data rates based on received data.
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Figure 72.
Top Level Modules of the 1G/10GbE PHY IP Function
The Enhanced PCS receives and transmits XGMII data. The Standard PCS receives and transmits GMII data.
Intel Device with 10.3125-Gbps Transceivers
To/From
1G/10Gb
Ethernet
MAC
Optional
1588 TX and
RX Latency
Adjust 1G and 10G
TX XGMII Data
@156.25 MHz
RX XGMII Data
TX GMII/MII Data
@ 125 MHz
RX GMII Data
1G/10Gb Ethernet PHY Intel FPGA IP Core Function
Native PHY Hard IP
1 GigE
PCS
10 Gb
Ethernet
Enhanced PCS
w FEC
257.8 MHz
161.1 MHz
40 64
40 64 1.25 Gb/
10.3125 Gb
Hard PMA
1 Gb
Ethernet
Standard
PCS
Link
Status
PCS Reconfig
Request
Avalon-MM
PHY Management
Interface
To/From Modules in the PHY MegaCore
Control and Status
Registers
Sequencer
(Optional)
Reconfiguration
Block
ATX/CMU
TX PLL
For
10 GbE
CMU or fPLL
TX PLL
For 1 GbE
TX
Serial
Data
RX
Serial
Data
1 Gb SFP /
10 Gb SFP+ or XFP /
1G/10 Gb SFP+
Module/
Standard PHY
Product
322.265625 MHz or 644.53125 MHz
Reference Clock
125 MHz
Reference Clock
Legend
Hard IP Soft IP
Red = With FEC Option
1G/ 10 Gb
Ethernet
Network
Interface
For more information about clock and reset signal descriptions, refer to Clock and
Reset Interfaces.
An Avalon-MM slave interface provides access to the 1G/10GbE PHY IP Core registers.
These registers control many of the functions of the other blocks. Many of these bits are defined in Clause 45 of IEEE 802.3ap-2008 Standard.
Related Information
•
Clock and Reset Interfaces on page 168
• IEEE Std 802.3ap-2008 Standard
• Standard for a Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems
2.6.4.1. 1G/10GbE PHY Release Information
This topic provides information about this release of the 1G/10GbE PHY IP Core.
Table 127.
1G/10GbE Release Information
Item
Version
Release Date
Ordering Codes
Product ID
Vendor ID
Description
16.0
May 2016
IP-1G10GBASER (primary)
IPR-1G10GBASER (renewal code)
0107
6AF7
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2.6.4.2. 1G/10GbE PHY Performance and Resource Utilization
This topic provides performance and resource utilization for the 1G/10GbE PHY IP core in Arria 10 devices.
The following table shows the typical expected resource utilization for selected configurations using the Quartus Prime software version 15.1. The numbers of ALMs and logic registers are rounded up to the nearest 50.
Table 128.
1GbE/10GbE PHY Performance and Resource Utilization
Variant
1G/10GbE PHY with IEEE 1588 v2
1G/10GbE PHY
1G/10GbE PHY with FEC
2650
1500
1500
ALMs
3950
2350
2350
ALUTs Registers
5100
2850
2850
6
2
2
M20K
2.6.4.3. 1G/10GbE PHY Functional Description
Figure 73.
1G/10GbE PHY Block Diagram
Avalon-MM
User PCS Reconfiguration
MGMT_CLK
Sequencer
(Auto-Speed
Detect)
PCS Reconfiguration I/F
PMA Reconfiguration I/F Reconfiguration
Block
Registers
TX_GMII_DATA
XGMII_TX_CLK
8 + 2
64 + 8
TX_XGMII_DATA
TX_PMA_CLKOUT
RX_XGMII_DATA
64 + 8
Link Training
Clause 72
Auto-Negotiation
Clause 73
66
40
40
1588
FIFO
GigE
PCS
1588
FIFO
XGMII_RX_CLK
RX_GMII_DATA
8 + 2 GigE
PCS
Native PHY
HSSI Reconfiguration Requests
Standard TX PCS tx_pld_clk tx_pma_clk
Enhanced TX PCS tx_pld_clk tx_pma_clk
40/32
TX PMA
Standard RX PCS rx_pld_clk rx_pma_clk
Enhanced RX PCS rx_pld_clk rx_pma_clk
Divide by 33/1/2
40/32
RX PMA
RX_PMA_CLKOUT
RX_DIV_CLKOUT
Soft Logic Hard Logic Not Available
Standard and Enhanced PCS Datapaths
The Standard PCS and PMA inside the Native PHY are configured as the Gigabit
Ethernet PHY. The Enhanced PCS and PMA inside the Native PHY are configured as the
10GBASE-R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters for more details.
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Sequencer
The Sequencer controls the start-up sequence of the PHY IP, including reset and power-on. It selects which PCS (1G or 10G) and PMA interface is active. The
Sequencer interfaces to the reconfiguration block to request a change from one data rate to the other data rate.
GigE PCS
The GigE PCS includes the GMII interface and Clause 37 auto negotiation and SGMII functionality.
Soft Enhanced PCS FIFO for IEEE 1588v2
In IEEE 1588v2 mode, the enhanced PCS FIFOs for both TX and RX are constructed in soft IP to include the latency information via the latency adjustment ports. For more information about the required latency information in the MAC as part of the Precision
Time Protocol implementation, refer to the 10-Gbps Ethernet MAC IP Function User
Guide.
Reconfiguration Block
The reconfiguration logic performs the Avalon-MM writes to the PHY for both PCS and
PMA reconfiguration. The following figure shows the details of the reconfiguration blocks. The Avalon-MM master accepts requests from the PMA or PCS controller. It performs the Read-Modify-Write or Write commands using the Avalon-MM interface.
The PCS controller receives data rate change requests from the Sequencer and translates them to a series of Read-Modify-Write or Write commands to the PMA and
PCS.
Figure 74.
Reconfiguration Block Details
The 1G/10GbE PHY IP core is very flexible. For example, you can configure it with or without IEEE 1588v2, and with or without FEC in the enhanced PCS datapath.
MGMT_CLK
(2)
PCS
Reconfiguration
Interface
PCS
Controller
PMA
Reconfiguration
Interface
Notes:
1. rcfg = Reconfiguration
2. MGMT_CLK = Management Clock
PMA Controller
TX EQ Controller
DFE Controller
CTLE Controller rcfg_data rcfg_data rcfg_data rcfg_data
(1)
Avalon-MM Bus
Avalon-MM Bus
Avalon-MM
Decoder
Avalon-MM Bus
Avalon-MM reconfig_busy Signal
HSSI
Reconfiguration
Requests
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Related Information
•
Arria 10 Enhanced PCS Architecture
on page 461
•
Arria 10 Standard PCS Architecture
on page 479
•
Arria 10 PMA Architecture on page 447
• 10-Gbps Ethernet MAC IP Function User Guide.
For more information about latency in the MAC as part of the Precision Time
Protocol implementation.
2.6.4.4. Clock and Reset Interfaces
You can use a fPLL or a CMU PLL to generate the clock for the TX PMA for the 1G data rate. For the 10G data rate, you can use the ATX PLL or the CMU PLL. For the 1G data rate, the frequency of the TX and RX clocks is 125 MHz, which is 1/8 of the MAC data rate. For the 10G data rate, the frequency of TX and RX clocks is 156.25 MHz, 1/64 of the MAC data rate. You can generate the 156.25 MHz clock directly by using a fPLL, or you can divide the clock from TX PLL by 33. The 1G/10GbE PHY does not support bonded clocks.
The following figure provides an overview of the clocking for this core.
Figure 75.
Clocks for Standard and 10G PCS and TX PLLs
1GbE/10GbE PHY
GMII TX
Data & Control SGMII
PCS tx_coreclkin_1g
125 MHz
8+1
Standard TX PCS tx_pld_clk tx_pma_clk
10 TX data
40 fractional
PLL
(instantiate separately)
XGMII TX Data & Control xgmii_tx_clk
156.25 MHz
64 + 8
64 + 8 tx_pld_clk
Enhanced TX PCS tx_pld_clk tx_pma_clk
64
TX data red = datapath includes FEC
GMII RX
Data & Control SGMII
PCS
8+1 rx_coreclkin_1g
125 MHz
XGMII RX Data & Control rx_pld_clk
64 + 8
64 + 8 xgmii_rx_clk
156.25 MHz
Standard RX PCS rx_pma_clk
Enhanced RX PCS rx_pld_clk rx_pma_clk
10 RX data
TX PMA
TX PLL
TX PLL
RX PMA
60
40 recovered clk
125 MHz
257.8125 MHz (1)
161.1 MHz (2)
TX serial data pll_ref_clk_1g
125 MHz pll_ref_clk_10g
644.53125 MHz
or
322.265625 MHz serial data
Notes:
1. 257.8125 MHz is for 10GbE.
2. 161.1 MHz is the FEC clock for 10GbE.
The following table describes the clock and reset signals.
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Table 129.
Clock and Reset Signals
Signal Name tx_serial_clk_10g
Direction
Input tx_serial_clk_1g
Input rx_cdr_ref_clk_10g rx_cdr_refclk_1g mgmt_clk mgmt_clk_reset xgmii_tx_clk xgmii_rx_clk tx_clkout rx_clkout tx_pma_clkout rx_pma_clkout tx_div_clk rx_div_clk
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Description
High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz.
The clock from the external 1G PLL to drive the TX high speed serial interface (HSSI) circuits. Connected to the the native PHY.
tx_serial_clk
input of
10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
The RX 1G PLL reference clock to drive the RX HSSI circuits.
Connected to the rx_cdr_refclk
input of the native PHY.
Avalon-MM clock and control system clock. Its frequency range is
100 MHz to 125 MHz.
When asserted, it resets the whole PHY.
Clock for XGMII TX interface with MAC. Can be connected to tx_div_clkout
. This drives the tx_coreclkin
port of the Native
PHY.
The clock for the XGMII RX interface with the MAC. Intel recommends connecting it directly to a PLL for use with TSE. This drives rx_coreclkin
312.5 MHz.
of the native PHY. Its frequency is 156.25 or
Transmit parallel clock. It is sourced from out_pld_pcs_tx_clk_out
on the HSSI. This could be used to provide the XGMII clocks or the GMII clocks, though if the PHY is reconfigured, the frequency changes. Its frequency is 125, 156.25,
161, 258, or 312.5 MHz.
Receive parallel clock. It is sourced from out_pld_pcs_rx_clk_out
on the HSSI. If the PHY is reconfigured, the frequency changes. Its frequency is 125, 156.25, 161, 258, or
312.5 MHz.
Transmit PMA clock. This is the clock for the 1588 mode TX FIFO and the 1G TX and RX PCS parallel data interface. Note: Use tx_div_clkout
or xgmii_tx_clk
for 10G TX datapath clocking.
This clock is provided for the 1G mode GMII/MII data and SyncE mode where the clock can be used as a reference to lock an external clock source. Its frequency is 125, 161, or 258 MHz.
Receive PMA clock. This is the clock for the 1588 mode RX FIFO and the 1G RX FIFO. Note: Use tx_div_clkout
or xgmii_rx_clk
for
10G RX datapath clocking. This clock is provided for the SyncE mode where the clock can be used as a reference to lock an external clock source. Its frequency is 125, 161, or 258 MHz.
This is the transmit div33 clock, which is sourced from the Native
PHY tx_pma_div_clkout
. It could be connected to the xgmii_tx_clk
and xgmii_rx_clk
clock inputs to drive the MAC interface, though if the PHY is reconfigured to 1G mode, the frequency changes. Its frequency is 125, 156.25, or 312.5 MHz.
This is the receive div33 clock, which is recovered from the received data. It drives the Auto Negotiation (AN) and Link Training (LT) logic and is sourced from the Native PHY
Note: Use tx_clkout
or rx_pma_div_clkout xgmii_rx_clk
port.
for 10G TX datapath clocking. If the PHY is reconfigured to 1G mode, the frequency changes. Its frequency is 125, 156.25, or 312.5 MHz.
continued...
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Signal Name calc_clk_1g tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset usr_seq_reset rx_data_ready
Direction
Input
Input
Input
Input
Input
Input
Output
Description
This is the clock for the GIGE PCS 1588 mode. To achieve high accuracy for all speed modes, the recommended frequency for calc_clk_1g
is 80 MHz. In addition, the 80 MHz clock should have the same parts per million (ppm) as the 125 MHz pll_ref_clk_1g input. The random error without a rate match FIFO mode is:
• ±1 ns at 1000 Mbps
• ± 5 ns at 100 Mbps
• ± 25 ns at 10 Mbps
Resets the analog TX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the digital TX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the analog RX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the digital RX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the sequencer. Initiates a PCS reconfiguration, and may restart AN, LT or both if these modes are enabled. Synchronous to mgmt_clk
.
When asserted, indicates that you can start to send the 10G data.
Synchronous to xgmii_rx_clk
.
Related Information
•
Input Reference Clock Sources on page 372
•
2.6.4.5. Parameterizing the 1G/10GbE PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the
Backplane-KR or 1Gb/10Gb Ethernet variant. The 1Gb/10Gb Ethernet variant
(1G/10GbE) does not implement the link training and auto-negotiation functions.
Complete the following steps to parameterize the 1Gb/10Gb Ethernet PHY IP core in the parameter editor:
1. Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 33.
2. Select 1Gb/10Gb Ethernet from the IP variant list located under Ethernet
Intel FPGA IP Core Type.
3. Use the parameter values in the tables in 10GBASE-R Parameters on page 140,
10M/100M/1Gb Ethernet Parameters
on page 172 , Speed Detection Parameters
on page 142, and
on page 173 as a starting point. Or, you can select the BackPlane_wo_1588 option in the Presets tab on the right side of the IP Parameter Editor. You can then modify the setting to meet your specific requirements.
4. Click Generate HDL to generate the 1Gb/10Gb Ethernet IP core top-level HDL file.
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Note: You might observe timing violations. If the timing path is within the IP, you can ignore these violations. This will be fixed in a future release of the Intel Quartus Prime software.
Related Information
•
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
•
•
on page 140
•
10M/100M/1Gb Ethernet Parameters
on page 172
•
Speed Detection Parameters on page 142
•
PHY Analog Parameters on page 173
2.6.4.5.1. General Options
The General Options allow you to specify options common to 10GBASE-KR mode.
Table 130.
General Options Parameters
Parameter Name
Enable internal PCS reconfiguration logic
On
Off
Options
Enable IEEE 1588 Precision
Time Protocol
Enable M20K block ECC protection
Enable tx_pma_clkout port
Enable rx_pma_clkout port
Enable tx_divclk port
Enable rx_divclk port
Enable tx_clkout port
Enable rx_clkout port
Enable Hard PRBS support and ADME support
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
Description
This parameter is only an option when set to 0, it does not include the reconfiguration module or expose the start_pcs_reconfig between 1G and 10G modes.
or
SYNTH_SEQ rc_busy
= 0. When
ports. When set to 1, it provides a simple interface to initiate reconfiguration
When you turn on this parameter, you enable the IEEE 1588
Precision Time Protocol logic for both 1G and 10G modes.
When you turn on this parameter, you enable error correction code (ECC) support on the embedded Nios CPU system. This parameter is only valid for the backplane variant.
When you turn on this parameter, the more information about this port.
tx_pma_clkout
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, the more information about this port.
rx_pma_clkout
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, the more information about this port.
tx_divclk
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, the more information about this port.
rx_divclk
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, the more information about this port.
tx_clkout
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, the more information about this port.
rx_clkout
port is enabled. Refer to the Clock and Reset Interfaces section for
When you turn on this parameter, you enable the ADME and
Hard PRBS data generation and checking logic in the Native PHY.
The transceiver toolkit (TTK) requires ADME to be enabled in the
Native PHY IP core.
continued...
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Parameter Name
Reference clock frequency
Enable additional control and status ports
Include FEC sublayer
Set
FEC_ability
bit on power up and reset
Set
FEC_Enable
bit on power up and reset
Options
644.53125 MHz
322.265625 MHz
On
Off
On
Off
On
Off
On
Off
Description
Specifies the input reference clock frequency. The default is
322.265625 MHz.
When you turn this option on, the core includes the rx_block_lock
and rx_hi_ber
output.
When you turn on this parameter, the core includes logic to implement FEC and a soft 10GBASE-R PCS. This is applicable only for the 10G mode.
When you turn on this parameter, the core sets the
Assert KR
FEC Ability
bit (0xB0[16]) FEC ability bit during power up and reset, causing the core to assert the FEC ability. This option is required for FEC functionality.
When you turn on this parameter, the core sets the
KR FEC
Request
bit (
0xB0[18]
) during power up and reset, causing the core to request the FEC ability during Auto Negotiation. This option is required for FEC functionality.
Related Information
Clock and Reset Interfaces on page 143
2.6.4.5.2. 10GBASE-R Parameters
The 10GBASE-R parameters specify basic features of the 10GBASE-R PCS. The FEC options also allow you to specify the FEC ability.
Table 131.
10GBASE-R Parameters
Parameter Name
10GbE Reference clock frequency
Enable additional control and status ports
Options
644.53125 MHz
322.265625 MHz
On
Off
Description
Specifies the input reference clock frequency. The default is
322.265625 MHz.
When you turn on this parameter, the core includes the rx_block_lock
and rx_hi_ber
ports.
Table 132.
FEC Options
Parameter Name
Include FEC sublayer On
Off
Options Description
When you turn on this parameter, the core includes logic to implement FEC and a soft 10GBASE-R PCS.
2.6.4.5.3. 10M/100M/1Gb Ethernet Parameters
The 10M/100M/1GbE parameters allow you to specify options for the MII interface and the 1GbE data rate.
Table 133.
10M/100M/1Gb Ethernet
Parameter Name
Enable 1Gb Ethernet protocol
On
Options Description
When you turn this option on, the core includes the GMII interface and related logic.
continued...
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Parameter Name Options Description
Enable 10Mb/100Mb
Ethernet functionality
PHY ID (32 bits)
PHY core version (16 bits)
Off
On
Off
32-bit value
16-bit value
When you turn this option on, the core includes the MII PCS. It also supports 4-speed mode to implement a 10M/100M interface to the MAC for the GbE line rate.
An optional 32-bit value that serves as a unique identifier for a particular type of PCS. The identifier includes the following components:
• Bits 3-24 of the Organizationally Unique Identifier (OUI) assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value which is
0x00000000.
This is an optional 16-bit value that identifies the PHY core version.
2.6.4.5.4. Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/10GbE but have disabled Auto-Negotiation. During Auto-Negotiation, if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner, the Sequencer reconfigures to 1GbE and 10GbE modes (Speed/Parallel detection) until it detects a valid 1G or 10GbE pattern.
Table 134.
Speed Detection
Parameter Name
Enable automatic speed detection
On
Off
Options
Avalon-MM clock frequency
Link fail inhibit time for
10Gb Ethernet
Link fail inhibit time for
1Gb Ethernet
Enable PCS-Mode port
100-162 MHz
504 ms
40-50 ms
On
Off
Description
When you turn this option On, the core includes the Sequencer block that sends reconfiguration requests to detect 1G or 10GbE when the Auto Negotiation block is not able to detect AN data.
Specifies the clock frequency for phy_mgmt_clk
.
Specifies the time before link_status
is set to FAIL or OK. A link fails if the link_fail_inhibit_time
has expired before link_status
is set to OK. The legal range is 500-510 ms. For more information, refer to "Clause 73 Auto Negotiation for
Backplane Ethernet" in IEEE Std 802.3ap-2007.
Specifies the time before
link_status
is set to FAIL or OK . A link fails if the link_fail_inhibit_time
has expired before link_status
is set to OK. The legal range is 40-50 ms.
Enables or disables the PCS-Mode port.
2.6.4.5.5. PHY Analog Parameters
You can specify analog parameters using the Intel Quartus Prime Assignment Editor, the Pin Planner, or the Intel Quartus Prime Settings File (.qsf).
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2.6.4.6. 1G/10GbE PHY Interfaces
Figure 76.
1G/10GbE PHY Top-Level Signals
XGMII
GMII
Interfaces
Avalon-MM PHY
Management
Interface
Clocks and
Reset
Interface xgmii_tx_dc[71:0] xgmii_tx_clk xgmii_rx_dc[71:0] xgmii_rx_clk gmii_tx_d[7:0] gmii_rx_d[7:0] gmii_tx_en gmii_tx_err gmii_rx_err gmii_rx_dv
1G/10GbE Top-Level Signals mgmt_clk mgmt_clk_reset mgmt_address[10:0] mgmt_writedata[31:0] mgmt_readdata[31:0] mgmt_write mgmt_read mgmt_waitrequest rx_serial_data tx_serial_data led_char_err led_link led_disp_err led_an led_panel_link rx_block_lock rx_hi_ber rx_is_lockedtodata tx_cal_busy rx_cal_busy rx_syncstatus tx_pcfifo_error_1g rx_pcfifo_error_1g rx_clkslip rx_data_ready rx_latency_adj_1g[21:0] tx_latency_adj_1g[21:0] tx_serial_clk_1g tx_serial_clk_10g rx_cdr_ref_clk_10g rx_cdr_ref_clk_1g tx_pma_clkout rx_pma_clkout tx_clkout rx_clkout tx_pma_div_clkout rx_pma_div_clkout tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset usr_seq_reset mii_tx_d[3:0] mii_tx_en mii_tx_err mii_rx_d[3:0] mii_rx_dv mii_rx_err mii_col mii_crs
Note:
Transceiver
Serial Data
Status
MII
Interfaces
The block diagram shown in the parameter editor labels the external pins with the interface type and places the interface name inside the box. The interface type and name are provided in the _hw.tcl file. If you turn on Show signals, the block
diagram displays all top-level signal names. For more information about _hw.tcl files, refer to the Component Interface Tcl Reference chapter in volume 1 of the Intel
Quartus Prime Handbook.
Intel is deprecating some of the signals shown in this figure. The descriptions of these signals identifies them as not functional.
Related Information
Component Interface Tcl Reference
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2.6.4.6.1. Clock and Reset Interfaces
Table 135.
Clock and Reset Signals
Signal Name tx_serial_clk_10g tx_serial_clk_1g rx_cdr_ref_clk_10g rx_cdr_ref_clk_1g tx_pma_clkout rx_pma_clkout tx_clkout rx_clkout tx_pma_div_clkout rx_pma_div_clkout tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset usr_seq_reset
Direction
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Description
High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz.
High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock is not required if GbE is not used. The frequency of this clock is 625
MHz.
10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
1G PHY RX PLL reference clock. The frequency is 125 MHz. This clock is only required if 1G is enabled.
Clock used to drive the 10G TX PCS and 1G TX PCS parallel data. For example, when the hard PCS is reconfigured to the 10G mode without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
Clock used to drive the 10G RX PCS and 1G RX PCS parallel data. For example, when the hard PCS is reconfigured to the 10G mode without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
XGMII/GMII TX clock for the TX parallel data source interface. This clock frequency is 257.81 MHz in 10G mode, and 161.13 MHz with
FEC enabled.
XGMII RX clock for the RX parallel data source interface. This clock frequency is 257.81 in 10G mode, and 161.13 MHz with FEC enabled.
The divided 33 clock from the TX serializer. You can use this clock for the for xgmii_tx_clk enable FEC.
or xgmii_rx_clk
. The frequency is 156.25
MHz for 10G. The frequencies are the same whether or not you
The divided 33 clock from CDR recovered clock. The frequency is
156.25 MHz for 10G. The frequencies are the same whether or not you enable FEC. This clock is not used for clocking the 10G RX datapath.
Resets the analog TX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the digital TX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the analog RX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the digital RX portion of the transceiver PHY. Synchronous to mgmt_clk
.
Resets the sequencer. Initiates a PCS reconfiguration, and may restart AN, LT or both if these modes are enabled. Synchronous to mgmt_clk
.
Related Information
•
Input Reference Clock Sources on page 372
•
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2.6.4.6.2. Data Interfaces
Table 136.
XGMII Signals
The MAC drives the TX XGMII signals to the 10GbE PHY. The 10GbE PHY drives the RX XGMII signals to the
MAC.
Signal Name Direction xgmii_tx_dc[71:0
] xgmii_tx_clk xgmii_rx_dc[71:0
] xgmii_rx_clk
Input
Input
Output
Input
Clock Domain Description
10GbE XGMII Data Interface
Synchronous to xgmii_tx_clk
XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.
Clock signal
Synchronous to xgmii_rx_clk
Clock signal
Clock for single data rate (SDR) XGMII TX interface to the
MAC. It should connect to xgmii_rx_clk
. This clock can be connected to the tx_div_clkout
; however, Intel recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
RX XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.
Clock for SDR XGMII RX interface to the MAC. This clock can be connected to the tx_div_clkout
; however, Intel recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
2.6.4.6.3. XGMII Mapping to Standard SDR XGMII Data
Table 137.
TX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name SDR XGMII Signal Name xgmii_tx_dc[7:0] xgmii_tx_dc[8] xgmii_tx_dc[16:9] xgmii_tx_dc[17] xgmii_tx_dc[25:18] xgmii_tx_dc[26] xgmii_tx_dc[34:27] xgmii_tx_dc[35] xgmii_tx_dc[43:36] xgmii_tx_dc[44] xgmii_tx_dc[52:45] xgmii_tx_dc[53] xgmii_sdr_data[7:0] xgmii_sdr_ctrl[0] xgmii_sdr_data[15:8] xgmii_sdr_ctrl[1] xgmii_sdr_data[23:16] xgmii_sdr_ctrl[2] xgmii_sdr_data[31:24] xgmii_sdr_ctrl[3] xgmii_sdr_data[39:32] xgmii_sdr_ctrl[4] xgmii_sdr_data[47:40] xgmii_sdr_ctrl[5]
Description
Lane 0 data
Lane 0 control
Lane 1 data
Lane 1 control
Lane 2 data
Lane 2 control
Lane 3 data
Lane 3 control
Lane 4 data
Lane 4 control
Lane 5 data
Lane 5 control continued...
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Signal Name xgmii_tx_dc[61:54] xgmii_tx_dc[62] xgmii_tx_dc[70:63] xgmii_tx_dc[71]
SDR XGMII Signal Name xgmii_sdr_data[55:48] xgmii_sdr_ctrl[6] xgmii_sdr_data[63:56] xgmii_sdr_ctrl[7]
Description
Lane 6 data
Lane 6 control
Lane 7 data
Lane 7 control
Table 138.
RX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name XGMII Signal Name Description xgmii_rx_dc[7:0] xgmii_sdr_data[7:0]
Lane 0 data xgmii_rx_dc[8] xgmii_rx_dc[16:9] xgmii_rx_dc[17] xgmii_rx_dc[25:18] xgmii_rx_dc[26] xgmii_rx_dc[34:27] xgmii_rx_dc[35] xgmii_rx_dc[43:36] xgmii_rx_dc[44] xgmii_sdr_ctrl[0] xgmii_sdr_data[15:8] xgmii_sdr_ctrl[1] xgmii_sdr_data[23:16] xgmii_sdr_ctrl[2] xgmii_sdr_data[31:24] xgmii_sdr_ctrl[3] xgmii_sdr_data[39:32] xgmii_sdr_ctrl[4]
Lane 0 control
Lane 1 data
Lane 1 control
Lane 2 data
Lane 2 control
Lane 3 data
Lane 3 control
Lane 4 data
Lane 4 control xgmii_rx_dc[52:45] xgmii_rx_dc[53] xgmii_rx_dc[61:54] xgmii_rx_dc[62] xgmii_rx_dc[70:63] xgmii_rx_dc[71] xgmii_sdr_data[47:40] xgmii_sdr_ctrl[5] xgmii_sdr_data[55:48] xgmii_sdr_ctrl[6] xgmii_sdr_data[63:56] xgmii_sdr_ctrl[7]
Lane 5 data
Lane 5 control
Lane 6 data
Lane 6 control
Lane 7 data
Lane 7 control
2.6.4.6.4. GMII Interface
The GMII interface signals drive data to and from the PHY.
Table 139.
GMII Interface Ports
Signal Name gmii_tx_d[7:0]
Direction
Input gmii_tx_en gmii_tx_err gmii_rx_d[7:0] gmii_rx_dv
Input
Input
Output
Output
Description
Data to be encoded and sent to the link partner. This signal is clocked with tx_clkout
.
The GMII TX control signal. Synchronous to tx_clkout
.
The GMII TX error signal. Synchronous to tx_clkout
.
Data to be encoded and sent to the link partner. This signal is clocked with tx_clkout
.
The GMII RX control signal. Synchronous to tx_clkout
.
continued...
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Signal Name gmii_rx_err led_char_err led_link led_disp_err led_an
Direction
Output
Output
Output
Output
Output
Description
The GMII RX error signal. Synchronous to tx_clkout
.
10-bit character error. Asserted for one rx_clkout_1g cycle when an erroneous 10-bit character is detected.
When asserted, this signal indicates successful link synchronization.
When asserted, this signal indicates a 10-bit running disparity error. Asserted for one rx_clkout_1g
cycle when a disparity error is detected. A running disparity error indicates that errors were detected on more received groups than the previous and possibly current groups.
This signal indicates the auto-negotiation status. The PCS function asserts this signal when an auto-negotiation completes.
2.6.4.6.5. Serial Data Interface
Table 140.
Serial Data Signals
Signal Name rx_serial_data tx_serial_data
Direction
Input
Output
2.6.4.6.6. Control and Status Interfaces
Table 141.
Control and Status Signals
Signal Name led_link led_disp_err
Direction
Output
Output
Clock Domain
Synchronous to tx_clkout
Synchronous to rx_clkout
Description
RX serial input data
TX serial output data
Description
When asserted, indicates successful link synchronization.
led_an led_panel_link
Output
Output
Synchronous to rx_clkout
Synchronous to mgmt_clk
Disparity error signal indicating a 10-bit running disparity error. Asserted for one
rx_clkout_1g
cycle when a disparity error is detected. A running disparity error indicates that more than the previous and perhaps the current received group had an error.
Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
When asserted, this signal indicates the following behavior:
Mode
1000 Base-X without Autonegotiation
Behavior
When asserted, indicates successful link synchronization.
continued...
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Signal Name rx_block_lock
Output rx_hi_ber
Output rx_is_lockedtodat a
Output tx_cal_busy
Output rx_cal_busy
Output tx_pcfifo_error_1 g
Output rx_pcfifo_error_1 g
Output lcl_rf
Input rx_clkslip rx_data_ready
Direction
Input
Output rx_latency_adj_10 g[15:0]
Output
Clock Domain Description
Mode
SGMII mode without Autonegotiation
1000 Base-X with Autonegotiation
SGMII mode with MAC mode Auto-negotiation
Behavior
When asserted, indicates successful link synchronization.
Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
Synchronous to rx_clkout
Synchronous to rx_clkout
Asynchronous signal
Synchronous to mgmt_clk
Synchronous to mgmt_clk
N/A
N/A
Synchronous to xgmii_tx_clk
Asynchronous signal
Synchronous to xgmii_rx_clk
Synchronous to xgmii_rx_clk
Asserted to indicate that the block synchronizer has established synchronization.
Asserted by the BER monitor block to indicate a Sync
Header high bit error rate greater than 10 -4 .
When asserted, indicates the RX channel is locked to input data.
When asserted, indicates that the TX channel is being calibrated.
When asserted, indicates that the RX channel is being calibrated.
When asserted, indicates that the standard PCS TX phase compensation FIFO is either full or empty.
When asserted, indicates that the Standard PCS RX phase compensation FIFO is either full or empty.
When asserted, indicates a Remote Fault (RF).The MAC sends this fault signal to its link partner. Bit D13 of the
Auto Negotiation Advanced Remote Fault
register
(0xC2) records this error.
When asserted, the deserializer either skips one serial bit or pauses the serial clock for one cycle to achieve word alignment. As a result, the period of the parallel clock could be extended by 1 unit interval (UI) during the clock slip operation.This is an optional control input signal.
When asserted, indicates that the MAC can begin sending data to the PHY.
When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the RX
PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
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Signal Name tx_latency_adj_10 g[15:0]
Direction
Output
Clock Domain
Synchronous to xgmii_tx_clk rx_latency_adj_1 g[21:0]
Output tx_latency_adj_1 g[21:0]
Output
Synchronous to gmii_rx_clk
Synchronous to gmii_tx_clk
Description
When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the TX
PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
When you enable 1588, this signal outputs the real time latency in GMII clock cycles (125 MHz) for the RX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 21 represent the number of clock cycles.
When you enable 1588, this signal outputs the real time latency in GMII clock cycles (125 MHz) for the TX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 21 represent the number of clock cycles.
2.6.4.6.7. MII
Table 142.
MII Signals
Name Directi on
Description
MII Transmit Interface mii_tx_d[3:0] mii_tx_en mii_tx_err
MII Receive Interface mii_rx_d[3:0] mii_rx_dv
Input
Input
Input
MII transmit data bus.
Assert this signal to indicate that the data on mii_tx_d[3:0] is valid.
Assert this signal to indicate to the PHY device that the frame sent is invalid.
mii_rx_err mii_col mii_crs
Output MII receive data bus.
Output Asserted to indicate that the data on the CRC field is received.
mii_rx_d[3:0] is valid. The signal stays asserted during frame reception, from the first preamble byte until the last byte of
Output Asserted by the PHY to indicate that the current frame contains errors.
Output Collision detection. Asserted by the PCS function to indicate that a collision was detected during frame transmission.
Output Carrier sense detection. Asserted by the PCS function to indicate that a transmit or receive activity is detected on the Ethernet line.
2.6.4.6.8. Dynamic Reconfiguration Interface
You can use the dynamic reconfiguration interface signals to dynamically change between 1G and 10G data rates.
Table 143.
Dynamic Reconfiguration Interface Signals
Signal Name rc_busy
Direction
Output
Clock Domain
Synchronous to mgmt_clk
Description
When asserted, indicates that reconfiguration is in progress. Synchronous to the mgmt_clk
. This signal is only exposed under the following condition: continued...
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Signal Name start_pcs_reconf ig
Input mode_1g_10gbar
Direction
Input
Clock Domain
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Description
• Turn on Enable internal PCS reconfiguration logic
When asserted, initiates reconfiguration of the PCS.
Sampled with the mgmt_clk
. This signal is only exposed under the following condition:
• Turn on Enable internal PCS reconfiguration logic
This signal selects either the 1G or 10G tx-parallel-data going to the PCS. It is only used for the 1G/10G application (variant) under the following circumstances:
• the Sequencer (auto-rate detect) is not enabled
• 1G mode is enabled
2.6.4.7. Avalon-MM Register Interface
The Avalon-MM slave interface signals provide access to all registers.
Table 144.
Avalon-MM Interface Signals
Signal Name mgmt_clk
Direction
Input
Clock Domain
Clock mgmt_clk_res et mgmt_addr[10
:0]
Input
Input
Asynchronous reset
Description
The clock signal that controls the Avalon-MM PHY management interface. If you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you must restrict the frequency to 100-125 MHz to meet the specification for the transceiver reconfiguration clock.
Resets the PHY management interface. This signal is active high and level sensitive.
11-bit Avalon-MM address.
mgmt_writeda ta[31:0] mgmt_readdat a[31:0] mgmt_write mgmt_read mgmt_waitreq uest
Input
Output
Input
Input
Output
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Synchronous to mgmt_clk
Input data.
Output data.
Write signal. Active high.
Read signal. Active high.
When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.
Related Information
Avalon Interface Specifications
2.6.4.7.1. 1G/10GbE Register Definitions
The Avalon-MM master interface signals provide access to the control and status registers.
The following table specifies the control and status registers that you can access over the Avalon-MM interface. A single address space provides access to all registers.
Note: Unless otherwise indicated, the default value of all registers is 0.
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Note: Do not write to any register that is not specified.
Table 145.
1G/10GbE Register Definitions
Word
Addr
0x4B0 0
Bit R/W
RW
Name
0x4B1
1
2
3
7:4
8
16
17
18
0
1
2
13:8
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
Description
Reset SEQ
When set to 1, resets the 10GBASE-KR sequencer (auto rate detect logic), initiates a PCS reconfiguration, and may restart
Auto-Negotiation (AN), Link Training (LT), or both if AN and LT are enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these modes. This reset self clears.
Disable AN Timer
Disable LF Timer fail_lt_if_ber
AN disable timer. If disabled (
Disable AN Timer
= 1) , AN may get stuck and require software support to remove the
ABILITY_DETECT capability if the link partner does not include this feature. In addition, software may have to take the link out of loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT state. To enable this timer set
Disable AN Timer = 0
.
When set to 1, disables the Link Fail timer. When set to 0, the
Link Fault timer is enabled.
When set to 1, the last LT measurement is a non-zero number.
Treat this as a failed run. 0 = Normal.
SEQ Force Mode[2:0]
Other than the "No force" mode (0x4B0[7:4] = 4'b0000), you must write the
Reset SEQ
(0x4B0[0]) to 1 when switching to the required data mode by changing (forcing) the 0x4B0[7:4] bits.
The following encodings are defined:
• 0000: No force
• 0001: GbE
• 0010: XAUI
• 0100: 10GBASE-R
• 0101: 10GBASE-KR
• 1100: 10GBASE-KR FEC
Enable Arria 10
Calibration
KR FEC enable err ind 171.1
When set to 1, it enables the Arria 10 HSSI reconfiguration calibration as part of the PCS dynamic reconfiguration. 0 skips the calibration when the PCS is reconfigured.
KR FEC enable 171.0
When set to 1, FEC is enabled. When set to 0, FEC is disabled.
Resets to the CAPABLE_FEC parameter value.
When set to 1, KR PHY FEC decoding errors are signaled to the
PCS. When set to 0, FEC errors are not signaled to the PCS. See
Clause 74.8.3 of IEEE 802.3ap-2007 for details.
KR FEC request
SEQ Link Ready
When set to 1, enables the FEC request. When this bit changes, you must assert the
Reset SEQ
bit (0x4B0[0]) to renegotiate with the new value. When set to 0, disables the FEC request.
When asserted, the sequencer indicates the link is ready.
SEQ AN timeout
SEQ LT timeout
SEQ Reconfig
Mode[5:0]
When asserted, the sequencer has had an AN timeout. This bit is latched and is reset when the sequencer restarts AN.
When set, indicates that the sequencer has had a timeout.
Specifies the sequencer mode for PCS reconfiguration. The following modes are defined:
• Bit 8, mode[0]: AN mode
• Bit 9, mode[1]: LT Mode
• Bit 10, mode[2]: 10G data mode
• Bit 11, mode[3]: GbE data mode
• Bit 12, mode[4]: Reserved for XAUI
• Bit13, mode[5]: 10G FEC mode continued...
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Word
Addr
Bit R/W Name Description
16
17
R
R
KR FEC ability
170.0
KR FEC err ind ability 170.0
0x4B2 0:10
11
RW
RWSC
31:15 RWSC
0x4B5 to
0x4BF
0x4C0
)
0 RW
Reserved
KR FEC TX Error
Insert
Reserved
Reserved for 40G KR
0x4C1
0x4C2
1
2
3
4
5
0
4
8
1
RW
RW
RW
RW
RW
RW
RW
RW
RO
When set to 1, indicates that the 10GBASE-KR PHY supports FEC.
Set as parameter
SYNTH_FEC
. For more information, refer to
Clause 45.2.1.84 of IEEE 802.3ap-2007.
When set to 1, indicates that the 10GBASE-KR PHY is capable of reporting FEC decoding errors to the PCS. For more information, refer to Clause 74.8.3 of IEEE 802.3ap-2007.
—
Writing a 1 inserts one error pulse into the TX FEC depending on the transcoder and burst error settings.
—
Intentionally left empty for address compatibility with 40G MAC +
PHY KR solutions.
AN enable
AN base pages ctrl
AN next pages ctrl
Local device remote fault
Force TX nonce value
Override AN
Parameters Enable
Reset AN
Restart AN TX SM
AN Next Page
AN page received
When set to 1, enables the AN function. The default value is 1.
For additional information, refer to bit 7.0.12 in Clause 73.8
Management Register Requirements of IEEE 802.3ap-2007.
When set to 1, the user base pages are enabled. You can send any arbitrary data via the user base page low/high bits. When set to 0, the user base pages are disabled and the state machine generates the base pages to send.
When set to 1, the user next pages are enabled. You can send any arbitrary data via the user next page low/high bits. When set to 0, the user next pages are disabled. The state machine generates the null message to send as next pages.
When set to 1, the local device signals Remote Faults in the AN pages. When set to 0, a fault has not occurred.
When set to 1, forces the TX nonce value to support some UNH testing modes. When set to 0, this is normal operation.
When set to 1, overrides the
AN_TECH
,
AN_FEC
, and
AN_PAUSE parameters and uses the bits in 0x4C3 instead. You must reset the Sequencer to reconfigure and restart into AN mode. When set to 0, this is normal operation and is used with 0x4B0 bit 0 and
0x4C3 bits[30:16].
When set to 1, resets all the 10GBASE-KR AN state machines.
This bit is self clearing.
When set to 1, restarts the 10GBASE-KR TX state machine. This bit self clears and is active only when the TX state machine is in the AN state. For more information, refer to bit 7.0.9 in Clause
73.8 Management Register Requirements of IEEE 802.3ap-2007.
When asserted, new next page (NP) info is ready to send. The data is in the XNP TX registers. When 0, the TX interface sends null pages. This bit self clears. NP is encoded in bit D15 of Link
Codeword. For more information, refer to Clause 73.6.9 and bit
7.16.15 of Clause 45.2.7.6 of IEEE 802.3ap-2007.
When set to 1, a page has been received. When 0, a page has not been received. The current value clears when the register is read.
For more information, refer to bit 7.1.6 in Clause 73.8 of IEEE
802.3ap-2007.
continued...
(36) These register bits are only applicable to the 10GBASE-KR mode.
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Word
Addr
2
3
4
5
6
7
8
Bit
0x4C2 9 RO
17:12 RO
0x4C3 15:0
R/W
RO
RO
RO
RO
RO
RO
RO
RW
21:16 RW
25:24 RW
Name Description
AN Complete
When asserted, AN has completed. When 0, AN is in progress. For more information, refer to bit 7.1.5 in Clause 73.8 of IEEE
802.3ap-2007.
AN ADV Remote Fault
When set to 1, fault information has been sent to the link partner.
When 0, a fault has not occurred. The current value clears when the register is read. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword. For more information, refer to Clause
73.6.7 of and bit 7.16.13 of IEEE 802.3ap-2007.
AN RX SM Idle
AN Ability
AN Status
LP AN Ability
FEC negotiated – enable FEC from SEQ
When set to 1, the AN state machine is in the idle state. Incoming data is not Clause 73 compatible. When 0, the AN is in progress.
When set to 1, the transceiver PHY is able to perform AN. When set to 0, the transceiver PHY is not able to perform AN. If your variant includes AN, this bit is tied to 1. For more information, refer to bits 7.1.3 and 7.48.0 of Clause 45 of IEEE 802.3ap-2007.
When set to 1, link is up. When 0, the link is down. The current value clears when the register is read. For more information, refer to bit 7.1.2 of Clause 45 of IEEE 802.3ap-2007.
When set to 1, the link partner is able to perform AN. When 0, the link partner is not able to perform AN. For more information, refer to bit 7.1.0 of Clause 45 of IEEE 802.3ap-2007.
When set to 1, the PHY is negotiated to perform FEC. When set to
0, the PHY is not negotiated to perform FEC.
Seq AN Failure
KR AN Link
Ready[5:0]
User base page low
When set to 1, a sequencer AN failure has been detected. When set to 0, an AN failure has not been detected.
Provides a one-hot encoding of an_receive_idle = true
The following encodings are defined:
and link status for the supported link as described in Clause 73.10.1.
• 6'b000000: 1000BASE-KX
• 6'b000001: 10GBASE-KX4
• 6'b000100: 10GBASE-KR
• 6'b001000: 40GBASE-KR4
• 6'b010000: 40GBASE-CR4
• 6'b100000: 100GBASE-CR10
The AN TX state machine uses these bits if the AN base pages ctrl bit is set. The following bits are defined:
• [15]: Next page bit
• [14]: ACK, controlled by the SM
• [13]: Remote Fault bit
• [12:10]: Pause bits
• [9:5]: Echoed nonce, set by the state machine
• [4:0]: Selector
The auto generation TX state machine generates the PRBS bit 49.
Override
AN_TECH[5:0]
Override
AN_FEC[1:0]
AN_TECH
value to override. The following bits are defined:
• Bit-16 =
AN_TECH[0]
= 1000BASE-KX
• Bit-18 =
AN_TECH[2]
= 10GBASE-KR
You must set 0xC0 bit-5 for this to take effect .
AN_FEC
value to override. The following bits are defined:
• Bit-24 =
AN_FEC [0]
= Capability
• Bit-25 =
AN_FEC [1]
= Request
You must set 0xC0 bit-5 for this to take effect.
continued...
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Word
Addr
Bit R/W
30:28 RW
0x4C4 31:0
0x4C5 15:0
0x4C6 31:0
0x4C7 15:0
0x4C8 31:0
0x4C9 15:0
0x4CA 31:0
0x4CB 24:0
RW
RW
RW
RO
RO
RO
RO
RO
Name Description
Override
AN_PAUSE[2:0]
AN_PAUSE value to override. The following bits are defined:
• Bit-28 =
AN_PAUSE [0]
= Pause Ability
• Bit-29 =
AN_PAUSE [1]
= Asymmetric Direction
• Bit-30 =
AN_PAUSE [2]
= Reserved
You must set 0xC0 bit-5 for this to take effect.
User base page high
The AN TX state machine uses these bits if the AN base pages ctrl bit is set. The following bits are defined:
• [29:5]: Correspond to page bits 45:21, the technology ability.
• [4:0]: Correspond to bits 20:16, the TX nonce bits.
The AN TX state machine generates the PRBS bit 49.
User Next page low
The AN TX state machine uses these bits if the AN next pages ctrl bit is set. The following bits are defined:
• [15]: Next page bit
• [14]: ACK, controlled by the state machine
• [13]: Message Page (MP) bit
• [12]: ACK2 bit
• [11]: Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007. Bit 49, the PRBS bit, is generated by the AN TX state machine.
User Next page high
The AN TX state machine uses these bits if the AN next pages ctrl bit is set. Bits [31:0] correspond to page bits [47:16]. Bit 49, the
PRBS bit, is generated by the AN TX state machine.
LP base page low
LP base page high
LP Next page low
LP Next page high
AN LP ADV
Tech_A[24:0]
The AN RX state machine receives these bits from the link partner. The following bits are defined:
• [15] Next page bit
• [14] ACK, which is controlled by the state machine
• [13] RF bit
• [12:10] Pause bits
• [9:5] Echoed nonce which are set by the state machine
• [4:0] Selector
The AN RX state machine received these bits from the link partner. The following bits are defined:
• [31:30]: Reserved
• [29:5]: Correspond to page bits [45:21], the technology ability
• [4:0]: Correspond to bits [20:16], the TX Nonce bits
The AN RX state machine receives these bits from the link partner. The following bits are defined:
• [15]: Next page bit
• [14]: ACK which is controlled by the state machine
• [13]: MP bit
• [12] ACK2 bit
• [11] Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007.
The AN RX state machine receives these bits from the link partner. Bits [31:0] correspond to page bits [47:16].
Received technology ability field bits of Clause 73 Auto-
Negotiation. The 10GBASE-KR PHY supports A0 and A2. The following protocols are defined: continued...
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Word
Addr
Bit
26:25 RO
27 RO
30:28 RO
0x4D0 0
1
2
3
7:4
R/W
RW
RW
RW
RW
RW
11:8 RW
0x4D0 14:12 RW
Name Description
AN LP ADV
FEC_F[1:0]
AN LP ADV Remote
Fault
AN LP ADV Pause
Ability_C[2:0]
Link Training enable
• A0 1000BASE-KX
• A1 10GBASE-KX4
• A2 10GBASE-KR
• A3 40GBASE-KR4
• A4 40GBASE-CR4
• A5 100GBASE-CR10
• A24:6 are reserved
For more information, refer to Clause 73.6.4 and AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.
Received FEC ability bits (F0:F1) is encoded in bits D46:D47 of the base Link Codeword. F0 is FEC ability. F1 is FEC requested.
See Clause 73.6.5 of IEEE 802.3ap-2007 for details.
Received Remote Fault (RF) ability bits. RF is encoded in bit D13 of the base link codeword in Clause 73 AN. For more information, refer to Clause 73.6.7 and bits AN LP base page ability register
AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE
802.3ap-2007.
Received pause ability bits. Pause (C0:C1) is encoded in bits
D11:D10 of the base link codeword in Clause 73 AN as follows:
• C0 is the same as PAUSE as defined in Annex 28B
• C1 is the same as ASM_DIR as defined in Annex 28B
• C2 is reserved
For more information, refer to bits AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.
When 1, enables the 10GBASE-KR start-up protocol. When 0, disables the 10GBASE-KR start-up protocol. The default value is
1. For more information, refer to Clause 72.6.10.3.1 and
10GBASE-KR PMD control register bit (1.150.1) of IEEE
802.3ap-2007.
dis_max_wait_tmr quick_mode
When set to 1, disables the LT
(BER) timer values.
max_wait_timer
. Used for characterization mode when setting much longer bit error rate
When set to 1, only the init and preset values calculate the best
BER.
pass_one
When set to 1, the BER algorithm considers more than the first local minimum when searching for the lowest BER. The default value is 1.
main_step_cnt [3:0]
Specifies the number of equalization steps for each main tap update. There are about 20 settings for the internal algorithm to test. The valid range is 1-15. The default value is 4'b0010.
prpo_step_cnt [3:0]
Specifies the number of equalization steps for each pre- and posttap update. From 16-31 steps are possible. The default value is
4'b0001.
equal_cnt [2:0]
Adds hysteresis to the error count to avoid local minimums. The following values are defined:
• 000 = 0
• 001 = 1
• 010 = 2
• 011 = 3
• 100 = 4
• 101 = 8
• 110 = 16
• 111 = Reserved continued...
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Word
Addr
4
8
0x4D2 0
1
2
Bit
15
16
17
0x4D0
0x4D1
22
28:24
31:29
0
RW
RW
RW
RW
R/W
RW
RW
RW
RW
RW
RO
RO
RO
Name Description disable Initialize
PMA on max_wait_timeout
Ovride LP Coef enable
Ovride Local RX
Coef enable adp_ctle_mode
The default value is 010.
When set to 1, PMA values (VOD, pre-tap, post-tap) are not initialized upon entry into the
Training_Failure
state. This happens when max_wait_timer_done
, which sets training_failure
= true (reg 0x4D2 bit 3). Used for
University of New Hampshire (UNH) testing. When set to 0, PMA values are initialized upon entry into
Training_Failure
state.
Refer to Figure 72-5 of IEEE 802.3ap-2007 for more details.
When set to 1, overrides the link partner's equalization coefficients; software changes the update commands sent to the link partner TX equalizer coefficients. When set to 0, uses the Link
Training logic to determine the link partner coefficients. Used with
0x4D1 bit-4 and 0x4D4 bits[7:0].
When set to 1, overrides the local device equalization coefficients generation protocol. When set, the software changes the local TX equalizer coefficients. When set to 0, uses the update command received from the link partner to determine local device coefficients. Used with 0x4D1 bit-8 and 0x4D4 bits[23:16]. The default value is 1.
Reserved. Default = 000
Manual ctle
Reserved
Reserved max_post_step[2:0]
Restart Link training
When set to 1, resets the 10GBASE-KR start-up protocol. When set to 0, continues normal operation. This bit self clears. For more information, refer to the state variable mr_restart_training as defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (1.150.0) IEEE 802.3ap-2007.
Updated TX Coef new
When set to 1, there are new link partner coefficients available to send. The LT logic starts sending the new values set in 0x4D4 bits[7:0] to the remote device. When set to 0, continues normal operation. This bit self clears. Must enable this override in 0x4D0 bit 16.
Updated RX coef new
When set to 1, new local device coefficients are available. The LT logic changes the local TX equalizer coefficients as specified in
0x4D4 bits[23:16]. When set to 0, continues normal operation.
This bit self clears. Must enable the override in 0x4D0 bit17.
Link Trained -
Receiver status
Link Training Frame lock
Link Training
Start-up protocol status
When set to 1, the receiver is trained and is ready to receive data. When set to 0, receiver training is in progress. For more information, refer to the state variable rx_trained as defined in
Clause 72.6.10.3.1 and bit 10GBASE-KR PMD control register bit
10GBASE_KR PMD status register bit (1.151.0) of IEEE
802.3ap-2007.
When set to 1, the training frame delineation has been detected.
When set to 0, the training frame delineation has not been detected. For more information, refer to the state variable frame_lock as defined in Clause 72.6.10.3.1 and 10GBASE_KR
PMD status register bit 10GBASE_KR PMD status register bit
(1.151.1) of IEEE 802.3ap-2007.
When set to 1, the start-up protocol is in progress. When set to 0, start-up protocol has completed. For more information, refer to the state training as defined in Clause 72.6.10.3.1 and
10GBASE_KR PMD status register bit (1.151.2) of IEEE
802.3ap-2007.
continued...
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Word
Addr
Bit R/W Name Description
0x4D3
0x4D4
3
4
5
6
7
9:0
29:20 RW
5:0
RO
RO
RO
RO
RO
RW
19:10 RW
RO or
RW
Link Training failure
When set to 1, a training failure has been detected. When set to
0, a training failure has not been detected. For more information, refer to the state variable training_failure as defined in Clause
72.6.10.3.1 and bit 10GBASE_KR PMD status register bit
(1.151.3) of IEEE 802.3ap-2007.
Link Training Error
When set to 1, excessive errors occurred during Link Training.
When set to 0, the BER is acceptable.
Link Training Frame lock Error
RXEQ Frame Lock
Loss
When set to 1, indicates a frame lock was lost during Link
Training. If the tap settings specified by the fields of 0x4D5 are the same as the initial parameter value, the frame lock error was unrecoverable.
Frame lock not detected at some point during RXEQ, possibly triggering conditional RXEQ mode.
CTLE Fine-grained
Tuning Error
Could not determine the best CTLE due to maximum BER limit at each step in the fine-grained tuning mode.
ber_time_frames ber_time_k_frames ber_time_m_frames
LD coefficient update[5:0]
Specifies the number of training frames to examine for bit errors on the link for each step of the equalization settings. Used only when ber_time_k_frames defined:
is 0. The following values are
• A value of 2 is about 10 3 bytes
• A value of 20 is about 10 4 bytes
• A value of 200 is about 10 5 bytes
The default value for simulation is 2'b11. The default value for hardware is 0.
Specifies the number of thousands of training frames to examine for bit errors on the link for each step of the equalization settings.
Set ber_time_m_frames = 0 following values:
for time/bits to match the
• A value of 3 is about 10 7 bits = About 1.3 ms
• A value of 25 is about 10 8 bits = About 11 ms
• A value of 250 is about 10 9 bits = About 110 ms
The default value for simulation is 0. The default value for hardware is 0x415.
Specifies the number of millions of training frames to examine for bit errors on the link for each step of the equalization settings.
Set ber_time_k_frames = 4'd1000 = 0x43E8 for time/bits to match the following values:
• A value of 3 is about 10 10 bits = About 1.3 seconds
• A value of 25 is about 10 11 bits = About 11 seconds
• A value of 250 is about 10 12 bits = About 110 seconds
Reflects the contents of the first 16-bit word of the training frame sent from the local device control channel. Normally, the bits in this register are read-only; however, when you override training by setting the
Ovride Coef enable
control bit, these bits become writable. The following fields are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4]) continued...
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Word
Addr
Bit R/W Name Description
0x4D4
6
7
13:8
14
22
RO or
RW
RO or
RW
RO
RO
21:16 RO or
RW
RO or
RW
LD Initialize
Coefficients
LD Preset
Coefficients
LD coefficient status[5:0]
Link Training ready
- LD Receiver ready
LP coefficient update[5:0]
LP Initialize
Coefficients
For more information, refer to bit 10G BASE-KR LD coefficient update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE
802.3ap-2007.
When set to 1, requests the link partner coefficients be set to configure the TX equalizer to its INITIALIZE state. When set to 0, continues normal operation. For more information, refer to 10G
BASE-KR LD coefficient update register bits (1.154.12) in Clause
45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3ap-2007.
When set to 1, requests the link partner coefficients be set to a state where equalization is turned off. When set to 0 the link operates normally. For more information, refer to bit 10GBASE-KR
LD coefficient update register bit (1.154.13) in Clause 45.2.1.80.3
and Clause 72.6.10.2.3.2 of IEEE 802.3ap-2007.
Status report register for the contents of the second, 16-bit word of the training frame most recently sent from the local device control channel. The following fields are defined:
• [5:4]: Coefficient (post-tap)
— 2'b11: Maximum
— 2'b01: Minimum
— 2'b10: Updated
— 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• [1:0]: Coefficient (pre-tap) (same encoding as [5:4])
For more information, refer to bit 10GBASE-KR LD status report register bit (1.155.5:0) in Clause 45.2.1.81 of IEEE
802.3ap-2007.
When set to 1, the local device receiver has determined that training is complete and it is prepared to receive data. When set to 0, the local device receiver requests that training continue.
Values for the receiver ready bit are defined in Clause
72.6.10.2.4.4. For more information, refer to bit 10GBASE-KR LD status report register bit (1.155.15) in Clause 45.2.1.81 of IEEE
802.3ap-2007.
Reflects the contents of the first 16-bit word of the training frame most recently received from the control channel.
Normally the bits in this register are read only; however, when training is disabled by setting low the KR training enable control bit, these bits become writable. The following fields are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to bit 10GBASE-KR LP coefficient update register bits (1.152.5:0) in Clause 45.2.1.78.3 of IEEE
802.3ap-2007.
When set to 1, the local device transmit equalizer coefficients are set to the INITIALIZE state. When set to 0, normal operation continues. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. For more information, refer to bit
10GBASE-KR LP coefficient update register bits (1.152.12) in
Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
continued...
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Word
Addr
0x4D4
Bit
23
0x4D5
0x4D5
0x4D6
R/W Name Description
30
4:0
13:8
20:16 R
27:24 R
29:28 R
31:30 R
4:0
5
RO or
RW
29:24 RO
RO
R
R
RW
RW
LP Preset
Coefficients
LP coefficient status[5:0]
LP Receiver ready
When set to 1, the local device TX coefficients are set to a state where equalization is turned off. Preset coefficients are used.
When set to 0, the local device operates normally. The function and values of the preset bit are defined in 72.6.10.2.3.1. The function and values of the initialize bit are defined in Clause
72.6.10.2.3.2. For more information, refer to bit 10GBASE-KR LP coefficient update register bits (1.152.13) in Clause 45.2.1.78.3
of IEEE 802.3ap-2007.
Status report register reflecting the contents of the second, 16-bit word of the training frame most recently received from the control channel. The following fields are defined:
• [5:4]: Coefficient (+1)
— 2'b11: Maximum
— 2'b01: Minimum
— 2'b10: Updated
— 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• n [1:0]: Coefficient (-1) (same encoding as [5:4])
For more information, refer to bit 10GBASE-KR LP status report register bits (1.153.5:0) in Clause 45.2.1.79 of IEEE
802.3ap-2007.
When set to 1, the link partner receiver has determined that training is complete and is prepared to receive data. When set to
0, the link partner receiver is requesting that training continue.
Values for the receiver ready bit are defined in Clause
72.6.10.2.4.4. For more information, refer to bit 10GBASE-KR LP status report register bits (1.153.15) in Clause 45.2.1.79 of IEEE
802.3ap-2007.
LT V
OD
setting
Stores the most recent V
OD
setting that LT specified. It reflects
Link Partner commands to fine-tune the V
OD
.
LT Post-tap setting
Stores the most recent post-tap setting that LT specified. It reflects Link Partner commands to fine-tune the TX pre-emphasis taps.
LT Pre-tap setting
RXEQ CTLE Setting
Stores the most recent pre-tap setting that LT specified. It reflects Link Partner commands to fine-tune the TX pre-emphasis taps.
Most recent ctle_rc
RX equalization.
setting sent to the reconfig bundle during
RXEQ CTLE Mode
RXEQ DFE Mode
LT VODMAX ovrd
LT VODMAX ovrd
Enable
Most recent ctle_mode during RX equalization.
setting sent to the reconfig bundle
Most recent dfe_mode
RX equalization.
setting sent to the reconfig bundle during
Override value for the
VMAXRULE
parameter. When enabled, this value substitutes for the
VMAXRULE
TX output for the channel specified.
to allow channel-by-channel override of the device settings. This only effects the local device
This value must be greater than the
INITMAINVAL
parameter for proper operation. Note this also overrides the parameter value.
PREMAINVAL
When set to 1, enables the override value for the
VMAXRULE parameter stored in the
LT VODMAX ovrd
register field.
continued...
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Word
Addr
Bit R/W Name Description
12:8
13
21:16 RW
22
28:24 RW
29
RW
RW
RW
RW
LT VODMin ovrd
LT VODMin ovrd
Enable
LT VPOST ovrd
Override value for the
VODMINRULE
parameter. When enabled, this value substitutes for the
VMINRULE
to allow channel-bychannel override of the device settings. This override only effects the local device TX output for this channel.
The value to be substituted must be less than the
INITMAINVAL parameter and greater than the operation.
VMINRULE
parameter for proper
When set to 1, enables the override value for the parameter stored in the
VODMINRULE
LT VODMin ovrd
register field.
Override value for the
VPOSTRULE
parameter. When enabled, this value substitutes for the
VPOSTRULE device TX output for this channel.
to allow channel-by-channel override of the device settings. This override only effects the local
The value to be substituted must be greater than the
INITPOSTVAL
parameter for proper operation.
When set to 1, enables the override value for the parameter stored in the
VPOSTRULE
LT VPOST ovrd
register field.
LT VPOST ovrd
Enable
LT VPre ovrd
Override value for the
VPRERULE
parameter. When enabled, this value substitutes for the
VPOSTRULE device TX output for this channel.
to allow channel-by-channel override of the device settings. This override only effects the local
The value greater than the operation.
INITPREVAL
parameter for proper
LT VPre ovrd Enable
When set to 1, enables the override value for the
VPRERULE parameter stored in the
LT VPre ovrd
register field.
Reserved for 40G KR Left empty for address compatibility with 40G MAC+PHY KR solution.
0x4D7 to
0x4FF
Related Information
Reconfiguration Interface and Dynamic Reconfiguration
on page 502
2.6.4.7.2. Hard Transceiver PHY Registers
Table 146.
Hard Transceiver PHY Registers
Addr
0x000-0 x3FF
Bit
[9:0]
Access
RW
Name
Access to HSSI registers
Description
All registers in the physical coding sub-layer (PCS) and physical media attachment (PMA) that you can dynamically reconfigure are in this address space. Refer to the Arria 10 Dynamic
Transceiver Reconfiguration chapter for further information.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration
on page 502
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2.6.4.7.3. Enhanced PCS Registers
Table 147.
Enhanced PCS Registers
Addr
0x480
0x481
0x482
3
4
7
Bit
31:0
2
3
1
2
Access
RW
RW
RW
RO
RO
RO
RO
RO
Name
Indirect_addr
RCLR_ERRBLK_CNT
RCLR_BER_COUNT
HI_BER
BLOCK_LOCK
TX_FIFO_FULL
RX_FIFO_FULL
Rx_DATA_READY
Description
Because the PHY implements a single channel, this register must remain at the default value of 0 to specify logical channel 0.
Error block counter clear register. When set to 1, clears the
RCLR_ERRBLK_CNT operation continues.
register. When set to 0, normal
BER counter clear register. When set to 1, clears the
RCLR_BER_COUNT
register. When set to 0, normal operation continues.
High BER status. When set to 1, the PCS reports a high
BER. When set to 0, the PCS does not report a high
BER.
Block lock status. When set to 1, the PCS is locked to received blocks. When set to 0, the PCS is not locked to received blocks.
When set to 1, the
TX_FIFO
is full.
When set to 1, the
RX_FIFO
is full.
When set to 1, indicates the PHY is ready to receive data.
2.6.4.7.4. Arria 10 GMII PCS Registers
Addr
0x490
0x491
Bit R/W
9 RW
Name
RESTART_AUTO_ NEGOTIATION
2
0x494
(1000BASE-
X mode)
5
6
3
5
12
15
RW
AUTO_NEGOTIATION_ ENABLE
RW
Reset
R
R
R
RW
FD
RW
HD
LINK_STATUS
AUTO_NEGOTIATION_ ABILITY
AUTO_NEGOTIATION_ COMPLETE
Description
Set this bit to 1 to restart the Clause 37 autonegotiation (AN) sequence. For normal operation, set this bit to the default 0 value. This bit is self-clearing.
Set this bit to 1 to enable Clause 37 AN. The default value is 1.
Set this bit to 1 to generate a synchronous reset pulse which resets all the PCS state machines, comma detection function, and the 8B/10B encoder and decoder. For normal operation, set this bit to 0. This bit self clears.
A value of 1 indicates that a valid link is operating. A value of 0 indicates an invalid link. If link synchronization is lost, this bit is 0.
A value of 1 indicates that the PCS function supports
Clause 37 AN.
A value of 1 indicates the following status:
• The AN process is complete.
• The AN control registers are valid.
Full-duplex mode enable for the local device. Set to 1 for full-duplex support.
Half-duplex mode enable for the local device. Set to 1 for half-duplex support. This bit should always be set to 0 for the KR PHY IP.
continued...
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Addr Bit R/W
8:7 RW
PS2,PS1
Name
13:
12
RW
RF2,RF1
14 R0
ACK
15
0x495
(1000BASE-
X mode)
5
6 R
RW
NP
R
FD
HD
8:7 R
PS2,PS1
13:
12
R
RF2,RF1
14 R
ACK
15 R
NP
0x494
(SGMII mode)
0x495
(SGMII mode)
14 RO
ACK
11:
10
RO
Speed[1:0]
Description
Pause support for the local device. The following encodings are defined for PS1/PS2:
• PS1=0 / PS2=0: Pause is not supported
• PS1=0 / PS2=1: Asymmetric pause toward link partner
• PS1=1 / PS2=0: Symmetric pause
• PS1=1 / PS2=1: Pause is supported on TX and RX
Remote fault condition for local device. The following encodings are defined for RF1/RF2:
• RF1=0 / RF2=0: No error, link is valid (reset condition)
• RF1=0 / RF2=1: Offline
• RF1=1 / RF2=0: Failure condition
• RF1=1 / RF2=1: AN error
Acknowledge for local device. A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.
Next page. In the device ability register, this bit is always set to 0.
Full-duplex mode enable for the link partner. This bit must be 1 because only full duplex is supported.
Half-duplex mode enable for the link partner. A value of 1 indicates support for half duplex. This bit must be
0 because half-duplex mode is not supported.
Specifies pause support for link partner. The following encodings are defined for PS1/PS2:
• PS1=0 / PS2=0: Pause is not supported
• PS1=0 / PS2=1: Asymmetric pause toward link partner
• PS1=1 / PS2=0: Symmetric pause
• PS1=1 / PS2=1: Pause is supported on TX and RX
Remote fault condition for link partner. The following encodings are defined for RF1/RF2:
• RF1=0 / RF2=0: No error, link is valid (reset condition)
• RF1=0 / RF2=1: Offline
• RF1=1 / RF2=0: Failure condition
• RF1=1 / RF2=1: AN error
Acknowledge for link partner. A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.
Next page. In link partner register. When set to 0, the link partner has a Next Page to send. When set to 1, the link partner does not send a Next Page. Next Page is not supported in AN.
Local device acknowledge. Value as specified in IEEE
802.3z standard.
Link partner speed:
• 00: copper interface speed is 10 Mbps
• 01: copper interface speed is 100 Mbps
• 10: copper interface speed is 1 Gigabit
• 11: reserved continued...
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Addr
0x496
0x4A2
0x4A3
0x4A4
Bit R/W
12 RO
14
15
0
1
15:
0
4:0
0
1
3:2
4
RO
RO
R
R
RW
RW
RW
RW
RW
RW
Name
COPPER_DUPLEX_STATUS
ACK
COPPER_LINK_STATUS
LINK_PARTNER_AUTO_NEGOTIATIO
N_ABLE
PAGE_RECEIVE
Link timer[15:0]
Link timer[20:16]
SGMII_ENA
USE_SGMII_AN
SGMII_SPEED
SGMII half-duplex
Description
Link partner capability:
• 1: copper interface is capable of full-duplex operation
• 0: copper interface is capable of half-duplex operation
Note: The PHY IP Core does not support half duplex operation because it is not supported in SGMII mode of the 1G/10G PHY IP core.
Link partner acknowledge. Value as specified in IEEE
802.3z standard.
Link partner status:
• 1: copper interface link is up
• 0: copper interface link is down
Set to 1, indicates that the link partner supports AN.
The default value is 0.
A value of 1 indicates that a new page has been received with new partner ability available in the register partner ability. The default value is 0 when the system management agent performs a read access.
Low-order 16 bits of the 21-bit auto-negotiation link timer. Each timer step corresponds to 8 ns (assuming a 125 MHz clock). The total timer corresponds to 16 ms. The reset value sets the timer to 10 ms for hardware mode and 10 us for simulation mode.
High-order 5 bits of the 21-bit auto-negotiation link timer.
Determines the PCS function operating mode. Setting this bit to 1b'1 enables SGMII mode. Setting this bit to 1b'0 enables 1000BASE-X gigabit mode.
In SGMII mode, setting this bit to 1b'1 configures the
PCS with the link partner abilities advertised during auto-negotiation. If this bit is set to 1b'0, the PCS function should be configured with the
SGMII_SPEED and
SGMII_DUPLEX
bits.
SGMII speed. When the PCS operates in SGMII mode
(
SGMII_ENA = 1
) and is not programmed for automatic configuration (
USE_SGMII_AN = 0 following encodings specify the speed :
), the
• 2'b00: 10 Mbps
• 2'b01: 100 Mbps
• 2'b10: Gigabit
• 2'b11: Reserved
These bits are not used when
SGMII_ENA = 0 or
USE_SGMII_AN = 1
.
When set to 1, enables half-duplex mode for 10/100
Mbps speed. This bit is ignored when or
USE_SGMII_AN
SGMII_ENA
= 0
= 1. These bits are only valid when you enable the SGMII mode only and not the clause-37 auto-negotiation mode.
2.6.4.7.5. PMA Registers
The PMA registers allow you to reset the PMA, customize the TX and RX serial data interface, and provide status information.
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Table 148.
1G Data Mode
Addr
0x4A8
0x4A9
1
2
3
5
6
3
4
1
2
4
0
0
Bit R/W
RW
RW
RW
RW
R
R
R
R
R
R
RW
R
Name tx_invpolarity rx_invpolarity rx_bitreversal_enable rx_bytereversal_enable force_electrical_idle rx_syncstatus rx_patterndetect rx_rlv rx_rmfifodatainserted rx_rmfifodatadeleted rx_disperr rx_errdetect
Description
When set, the TX interface inverts the polarity of the TX data to the 8B/10B encoder.
When set, the RX channels inverts the polarity of the received data to the 8B/10B decoder.
When set, enables bit reversal on the RX interface to the word aligner.
When set, enables byte reversal on the RX interface to the byte deserializer.
When set, forces the TX outputs to electrical idle.
When set, the word aligner is synchronized.
GbE word aligner detected comma.
Run length violation.
Rate match FIFO inserted code group.
Rate match FIFO deleted code group.
RX 8B10B disparity error.
RX 8B10B error detected.
Table 149.
PMA Registers
Address
0x444 1
0x461
0x464
0x465
0x466
0x467
2
3
0
0
0
0
0
Bit R/W
RW
RW
RW
RW
RW
RW
RO
RO
Name reset_tx_digital reset_rx_analog reset_rx_digital
Description
Writing a 1 asserts the internal TX digital reset signal. You must write a 0 to clear the reset condition.
Writing a 1 causes the internal RX analog reset signal to be asserted. You must write a 0 to clear the reset condition.
Writing a 1 causes the internal RX digital reset signal to be asserted. You must write a 0 to clear the reset condition.
phy_serial_loopback
Writing a 1 puts the channel in serial loopback mode.
pma_rx_set_locktoda ta
When set, programs the RX clock data recovery (CDR) PLL to lock to the incoming data.
pma_rx_set_locktore f
When set, programs the RX CDR PLL to lock to the reference clock.
pma_rx_is_lockedtod ata pma_rx_is_lockedtor ef
When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to
LTD mode.
When asserted, indicates that the RX CDR PLL is locked to the reference clock.
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2.6.4.7.6. Speed Change Summary
Table 150.
Speed Change Summary
Speed Change
1GbE and 10GBASE-R
Speed Change Method
Interface Signals
SGMII (10M, 100M and 1GbE)
1GbE, 10GBASE-R, and 10GBASE-R with FEC
Avalon-MM bus
Avalon-MM bus
Detailed Information
• Refer to Dynamic Reconfiguration
Interface.
•
on page 197
Note: You can configure the static speed while generating the IP core using the IP Parameter
Editor.
Related Information
Dynamic Reconfiguration Interface on page 148
2.6.4.8. Creating a 1G/10GbE Design
Follow these steps to create a 1G/10GbE design using the 1G/10GbE PHY IP.
1. Generate the 1G/10GbE PHY with the required parameterization.
The 1G/10GbE PHY IP Core includes reconfiguration logic. This logic provides the
Avalon-MM interface that you can use to read and write to PHY registers. All read and write operations must adhere to the Avalon specification.
2. Instantiate a reset controller using the Transceiver Reset Controller Intel FPGA IP
Core in the IP Catalog. Connect the power and reset signals between the 1G/
10GbE PHY and the reset controller.
3. Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate.
Connect the high speed serial clock and PLL lock signals between 1G/10GbE PHY and TX PLLs. You can use any combination of fPLLs, ATX, or CMU PLLs.
4. Use the tx_pma_divclk
from 1G/10GbE PHY or generate a fPLL to create the
156.25 MHz XGMII clock from the 10G reference clock.
No Memory Initialization Files (.mif) are required for the 1G/10GbE design in Arria
10 devices.
5. Complete the design by creating a top level module to connect all the IP (1G/
10GbE PHY IP, PLL IP and Reset Controller) blocks.
Related Information
•
on page 359
•
on page 368
•
on page 350
•
Using the Transceiver PHY Reset Controller
on page 433
•
1G/10GbE PHY Functional Description on page 166
2.6.4.9. Design Guidelines
Consider the following guidelines while designing with 1G/10GbE PHY.
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Using the 1G/10GbE PHY without the Sequencer
The sequencer brings up channel-based initial datapath and performs parallel detection. To use the 1G/10GbE PHY without the sequencer, turn off the Enable
automatic speed detection parameter.
Turning off the sequencer results in the following additional ports:
• rc_busy
• start_pcs_reconfig
• mode_1g_10gbar
These ports perform manual reconfiguration. The following figure shows how these ports are used for 1G and 10G configuration.
Figure 77.
Timing for Reconfiguration without the Sequencer mgmt_clk rc_busy start_pcs_reconfig mode_1g_10bar
2.6.4.10. Channel Placement Guidelines
The channels of multi-channel 1G/10G designs do not need to be placed contiguously.
However, channels instantiated in different transceiver banks require PLLs in the same bank.
Related Information
Arria 10 Avalon-MM Interface for PCIe* Solutions
2.6.4.11. Design Example
Intel provides a design example to assist you in integrating your Ethernet PHY IP into your complete design.
The MAC and PHY design example instantiates the 1G/10GbE PHY IP along with the
1G/10G Ethernet MAC and supporting logic. It is part of the Quartus II software installation and is located in the <quartus2_install_dir>/ip subdirectory. For more information about this example design, refer to the 10-Gbps Ethernet MAC IP Function
User Guide .
A design example that instantiates the 1G/10G PHY and its supporting logic is available on the Intel FPGA wiki. The following figure shows the block diagram of the
1G/10GbE PHY-only design example. The default configuration includes two channels for backplane Ethernet and two channels for line-side (1G/10G) applications.
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Figure 78.
1G/10GbE PHY Only Design Example
A10_DE_WRAPPER
Management
Master
ISSP
Clock and
Reset
JTAG-to-
Avalon-MM
Master
Test Harness
XGMII
Source
XGMII
Source
XGMII
Sink
XGMII
Sink
XGMII
GEN
XGMII
GEN
TH0_ADDR = 0xF nnn
XGMII
CHK
XGMII
CHK
...
A10_IP_WRAPPER
XGMII
CLK FPLL
1G Ref CLK
CMU PLL
10G Ref CLK
ATX PLL
Reset
Control
Reset
Control
Reset
Control
Reset
Control
CH0: PHY_ADDR = 0x0 nnn
CH1: PHY_ADDR = 0x1 nnn
CH2: PHY_ADDR = 0x2 nnn
CH3: PHY_ADDR = 0x3 nnn
1G/10GbE PHY IP
KR PHY IP
1588 Soft
FIFOs
GMII
RS
1588 Soft
FIFOs
GMII
RS
KR PHY IP
KR PHY IP
Sequencer
Sequencer
STD
TX PCS
1588 Soft
FIFOs 1588 Soft
FIFOs
Sequencer
10-GB
TX PCS
Sequencer
Auto Neg cls 73
Link Training cls 72
GMII
RS
Auto Neg cls 73 Auto Neg cls 73
Link Training cls 72
GMII
RS cls 72
STD
RX PCS
10-GB
RX PCS
A10
Reconfiguration
NF
Reconfiguration
STD
TX PCS
Registers CSR
Avalon-MM Slave
Reconfiguration
STD
TX PCS STD
TX PCS
Registers CSR
Native Hard PHY
NF
TX PMA
Registers CSR
Native Hard PHY
Registers CSR
Avalon-MM Slave
Native Hard PHY
TX PMA Native Hard PHY
TX PMA
TX PMA
10-GB
TX PCS
STD
RX PCS
10-GB
RX PCS
Divide
10-GB
TX PCS
STD
RX PCS
10-GB
RX PCS
10-GB
TX PCS
STD
RX PMA
10-GB
RX PCS
RX PMA
RX PMA
RX PMA
Divide
Divide
Divide
Related Information
Arria 10 Transceiver PHY Design Examples
2.6.4.12. Simulation Support
The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Intel-supported simulators for this Quartus Prime software release:
• ModelSim Verilog
• ModelSim VHDL
• VCS Verilog
• VCS VHDL
• NCSIM Verilog
• NCSIM VHDL simulation
When you generate a 1G/10GbE or 10GBASE-KR PHY IP core, the Quartus Prime software optionally generates an IP functional simulation model.
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2.6.4.13. TimeQuest Timing Constraints
To pass timing analysis, you must decouple the clocks in different time domains. The necessary Synopsys Design Constraints File (.sdc) timing constraints are included in the top-level wrapper file.
2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
2.6.5.1. About 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core implements the Ethernet protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard. The PHY IP core consists of a physical coding sublayer (PCS) function and an embedded physical media attachment (PMA). You can dynamically switch the PHY operating speed.
Figure 79.
Block Diagram of the PHY IP Core
Intel Device with Serial Transceivers
1G/2.5G/5G/10G Multi-rate Ethernet PHY
Native PHY Hard IP
TX
GMII / XGMII
LL Ethernet
10G MAC
RX
GMII / XGMII
Soft PCS Hard PCS
TX
Serial Clock
User
Application
Avalon-MM
Interface
Configuration
Registers
PMA
RX CDR
Reference
Clock
TX Serial
RX Serial
External
PHY
Legend
Hard IP
Soft Logic
Transceiver
Reset
Controller
Reconfiguration Block
PLL for 1 GbE
PLL for 2.5 GbE
PLL for 10 GbE
125-MHz
Reference Clock
Related Information
•
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
•
on page 418
• Low Latency Ethernet 10G MAC User Guide
Describes the Low Latency Ethernet 10G MAC IP Core.
322-MHz
Reference Clock
2.6.5.1.1. Features
Table 151.
PHY Features
Feature
Multiple operating speeds
MAC-side interface
1G, 2.5G, 5G, and 10G.
16-bit GMII for 1G and 2.5G.
Description continued...
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Feature
Network-side interface
Description
32-bit XGMII for 1G/2.5G/5G/10G (USXGMII).
64-bit XGMII for 10G.
1.25 Gbps for 1G.
3.125 Gbps for 2.5G.
10.3125 Gbps for 1G/2.5G/5G/10G (USXGMII).
Provides access to the configuration registers of the PHY.
Avalon ® interface
Memory-Mapped (Avalon-MM)
PCS function
Auto-negotiation
IEEE 1588v2
Sync-E
2.6.5.1.2. Release Information
Table 152.
PHY Release Information
Item
Version
Release Date
Ordering Codes
Product ID
Vendor ID
Open Core Plus
2.6.5.1.3. Device Family Support
1000BASE-X for 1G and 2.5G.
10GBASE-R for 10G.
USXGMII PCS for 1G/2.5G/5G/10G
Implements clause 37. Supported in 1GbE only.
USXGMII Auto-negotiation supported in the 1G/2.5G/5G/10G (USXGMII) configuration.
Provides the required latency to the MAC if the MAC enables the IEEE
1588v2 feature.
Provides the clock for Sync-E implementation.
Description
16.0
May 2016
IP-10GMRPHY
00E4
6AF7
Supported
Device Family
Arria 10
Arria V GX/GT/SX/ST
Operating Mode
2.5G
1G/2.5G
1G/2.5G/5G/10G
2.5G
1G/2.5G
Support Level
Final
Final
Other device families No support
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Definition: Device Support Level
Intel FPGA IP cores provide the following support for Intel FPGA device families:
• Preliminary support—Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. This IP core can be used in production designs with caution.
• Final support—Intel verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. This IP core is ready to be used in production designs.
2.6.5.1.4. Resource Utilization
The following estimates are obtained by compiling the PHY IP core with the Intel
Quartus Prime software.
Table 153.
Resource Utilization
Arria 10
Device
1G/2.5G
Speed
1G/2.5G with IEEE
1588v2 enabled
1G/2.5G/5G/10G
1G/2.5G/5G/10G
(USXGMII)
ALMs
550
1200
1150
650
ALUTs
750
1850
1500
800
Logic Registers
1200
2550
2550
1500
Memory Block
2 (M20K)
2 (M20K)
6 (M20K)
3 (M20K)
2.6.5.2. Using the IP Core
The Intel FPGA IP Library is installed as part of the Intel Quartus Prime installation process. You can select the 1G/2.5G/5G/10G Multi-rate Ethernet IP core from the library and parameterize it using the IP parameter editor.
2.6.5.2.1. Parameter Settings
You customize the PHY IP core by specifying the parameters in the parameter editor in the Intel Quartus Prime software. The parameter editor enables only the parameters that are applicable to the selected speed.
Table 154.
1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters
Speed
Name
Enable IEEE 1588 Precision
Time Protocol
Value
2.5G
1G/2.5G
1G/2.5G/5G/10G
On, Off
Description
The operating speed of the PHY.
Connect to MGBASE-T PHY On, Off
Select this parameter for the PHY to provide latency information to the MAC. The MAC requires this information if it enables the IEEE 1588v2 feature.
This parameter is enabled only for 2.5G and 1G/2.5G.
Select this option when the external PHY is MGBASE-T compatible.
This parameter is enabled for 2.5G, 1G/2.5G, and 1G/
2.5G/10G (MGBASE-T) modes.
continued...
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Name
Connect to NBASE-T PHY
PHY ID (32 bit)
Value
On, Off
32-bit value
Description
Select this option when the external PHY is NBASE-T compatible.
This parameter is enabled for 1G/2.5G/5G/10G
(USXGMII) modes.
An optional 32-bit unique identifier:
• Bits 3 to 24 of the Organizationally Unique Identifier
(OUI) assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value, which is
0x00000000.
Specify the frequency of the reference clock for 10GbE.
Reference clock frequency for
10 GbE (MHz)
Selected TX PMA local clock division factor for 1 GbE
Selected TX PMA local clock division factor for 2.5 GbE
Enable Altera Debug Master
Endpoint
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Enable PRBS soft accumulators
322.265625, 644.53125
1
,
2
,
4
,
8
1
,
2
On, Off
On, Off
User-specified
On, Off
On, Off
This parameter is the local clock division factor in the 1G mode. It is directly mapped to the Native PHY IP Core
GUI options.
This parameter is the local clock division factor in the
2.5G mode. It is directly mapped to the Native PHY IP
Core GUI options.
Available in Native PHY and TX PLL IP parameter editors.
When enabled, the Altera Debug Master Endpoint
(ADME) is instantiated and has access to the Avalon-MM interface of the Native PHY. You can access certain test and debug functions using System Console with the
ADME. Refer to the Embedded Debug Features section for more details about ADME.
Available in Native PHY and TX PLL IP parameter editors.
Enables capability registers. These registers provide high-level information about the transceiver channel's /
PLL's configuration.
Available in Native PHY and TX PLL IP parameter editors.
Sets a user-defined numeric identifier that can be read from the user_identifier registers are enabled.
offset when the capability
Available in Native PHY and TX PLL IP parameter editors.
Enables soft registers for reading status signals and writing control signals on the PHY /PLL interface through the ADME or reconfiguration interface.
Available in Native PHY IP parameter editor only.
Enables soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and checker.
Related Information
on page 544
2.6.5.2.2. Timing Constraints
Constrain the PHY based on the fastest speed. For example, if you configure the PHY as 1G/2.5G, constrain it based on 2.5G.
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For the 1G/2.5G/5G/10G operating mode, constrain the PHY for the 10G datapath as well as the 1G/2.5G datapath. Refer to the example provided:
<Installation Directory>
/ip/altera/ethernet/alt_mge_phy/example/ alt_mge_phy_multi_speed_10g.sdc
.
2.6.5.2.3. Changing the PHY's Speed
You can change the PHY's speed through the reconfiguration block.
1. The user application initiates the speed change by writing to the corresponding register of the reconfiguration block.
2. The reconfiguration block performs the following steps:
• In Arria 10 devices: a. Sets the xcvr_mode
signal of the 1G/2.5G/5G/10G Multi-rate Ethernet
PHY IP core to the requested speed.
b. Reads the generated .mif file for the configuration settings and configures the transceiver accordingly.
The
.mif
files, alt_mge_phy_reconfig_parameters_CFG*.mif
, are generated in the <IP working directory>
/ altera_xcvr_native_a10_
<version>
/synth/reconfig
directory.
c. Selects the corresponding transceiver PLL.
d. Triggers the transceiver recalibration.
3. The reconfiguration block triggers the PHY reset through the transceiver reset controller.
2.6.5.3. Configuration Registers
You can access the 16-bit configuration registers via the Avalon-MM interface. These configuration registers apply only to 2.5G and 1G/2.5G operating modes.
Observe the following guidelines when accessing the registers:
• Do not write to reserved or undefined registers.
• When writing to the registers, perform read-modify-write to ensure that reserved or undefined register bits are not overwritten.
Table 155.
PHY Register Definitions
Addr Name Description
0x00 control
Access HW Reset
Value
RWC 0 • Bit [15]: reset.
RESET
. Set this bit to 1 to trigger a soft
The PHY clears the bit when the reset is completed.
The register values remain intact during the reset.
• Bit[14]:
LOOPBACK
. Set this bit to 1 to enable loopback on the serial interface.
• Bit [12]:
AUTO_NEGOTIATION_ENABLE to 1 to enable auto-negotiation.
. Set this bit
Auto-negotiation is supported only in 1GbE.
Therefore, set this bit to 0 when you switch to a speed other than 1GbE.
RW
RW
0
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0x01
0x04
0x05
Addr
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Name status phy_identifier
Description
• Bit [9]:
RESTART_AUTO_NEGOTIATION to 1 to restart auto-negotiation.
. Set this bit
The PHY clears the bit as soon as auto-negotiation is restarted.
• The rest of the bits are reserved.
• Bit [5]:
AUTO_NEGOTIATION_COMPLETE
. A value of
"1" indicates that the auto-negotiation is completed.
• Bit [3]:
AUTO_NEGOTIATION_ABILITY negotiation.
. A value of
"1" indicates that the PCS function supports auto-
• Bit [2]:
LINK_STATUS established.
. A value of "0" indicates that the link is lost. Value of 1 indicates that the link is
• The rest of the bits are reserved.
The value set in the PHY_IDENTIFIER parameter.
Access HW Reset
Value
RWC 0
—
RO
RO
RO
—
RO
—
—
0
1
0
—
Value of
PHY_IDEN
TIFIER parameter
— dev_ability
Use this register to advertise the device abilities during auto-negotiation.
• Bits [13:12]:
RF
. Specify the remote fault.
— 00: No error.
— 01: Link failure.
— 10: Offline.
— 11: Auto-negotiation error.
• Bits [8:7]:
PS
. Specify the PAUSE support.
— 00: No PAUSE.
— 01: Symmetric PAUSE.
— 10: Asymmetric PAUSE towards the link partner.
— 11: Asymmetric and symmetric PAUSE towards the link device.
• Bit [5]:
FD
. Ensure that this bit is always set to 1.
• The rest of the bits are reserved.
partner_ability
The device abilities of the link partner during autonegotiation.
• Bit [14]:
ACK
. A value of "1" indicates that the link partner has received three consecutive matching ability values from the device.
• Bits [13:12]:
RF
. The remote fault.
— 00: No error.
— 01: Link failure.
— 10: Offline.
— 11: Auto-negotiation error.
RW
RW
RW
—
—
RO
RO
00
11
1
—
—
0
0 continued...
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Addr
0x06
0x07
0x08
0x09:0x0F
0x10
0x11
0x12:0x13
0x14:0x1F
0x400
Name an_expansion device_next_page
Description
• Bits [8:7]:
PS
. The PAUSE support.
— 00: No PAUSE.
— 01: Symmetric PAUSE.
— 10: Asymmetric PAUSE towards the link partner.
— 11: Asymmetric and symmetric PAUSE towards the link device.
• Bit [6]:
HD
. A value of "1" indicates that half-duplex is supported.
• Bit [5]:
FD
. A value of "1" indicates that full-duplex is supported.
• The rest of the bits are reserved.
The PCS capabilities and auto-negotiation status.
Bit [1]:
PAGE_RECEIVE
. A value of "1" indicates that the partner_ability register has been updated. This bit is automatically cleared once it is read.
Bit [0]:
LINK_PARTNER_AUTO_NEGOTIATION_ABLE value of "1" indicates that the link partner supports auto-negotiation.
. A
Access HW Reset
Value
RO 0
RO
RO
—
—
RO
RO
0
0
—
—
0
0
The PHY does not support the next page feature. These registers are always set to 0.
RO
RO
0
0 partner_next_pag e
Reserved scratch rev
—
Provides a memory location to test read and write operations.
The current version of the PHY IP core.
—
RW
RO
—
0
RW
Current version of the PHY
0 link_timer
Reserved
21-bit auto-negotiation link timer.
• Offset 0x12: link_timer[15:0]. Bits [8:0] are always be set to 0.
• Offset 0x13: link_timer[20:16] occupies the lower 5 bits. The remaining 11 bits are reserved and must always be set to 0.
— usxgmii_control
Control Register
Bit [0]:
USXGMII_ENA
:
• 0: 10GBASE-R mode
• 1: USXGMII mode
Bit [1]:
USXGMII_AN_ENA is set to 1:
is used when
USXGMII_ENA
• 0: Disables USXGMII Auto-Negotiation and manually configures the operating speed with the
USXGMII_SPEED
register.
• 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto-
Negotiation.
—
—
RW
RW
—
—
0x0
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0x401
Addr
0x402:0x404
0x405
Name Description
Bit [4:2]:
USXGMII_SPEED
is the operating speed of the PHY in USXGMII mode and to 0.
USE_USXGMII_AN
is set
• 3’b000: Reserved
• 3’b001: Reserved
• 3’b010: 1G
• 3’b011: 10G
• 3’b100: 2.5G
• 3’b101: 5G
• 3’b110: Reserved
• 3’b111: Reserved
Bit [8:5]: Reserved
Bit [9]: RESTART_AUTO_NEGOTIATION
Write 1 to restart Auto-Negotiation sequence The bit is cleared by hardware when Auto-Negotiation is restarted.
Access HW Reset
Value
RW 0x0
—
RWC
(hardw are selfclear)
—
—
—
—
RO
—
0x0
—
—
—
—
0x0 usxgmii_status
Reserved usxgmii_partner_ ability
Bit [15:10]: Reserved
Bit [30:16]: Reserved
Status Register
Bit [1:0]: Reserved
Bit [2]:
LINK_STATUS all speeds
indicates link status for USXGMII
• 1: Link is established
• 0: Link synchronization is lost, a 0 is latched
Bit [3]: Reserved
Bit [4]: Reserved
Bit [5]:
AUTO_NEGOTIATION_COMPLETE
A value of 1 indicates the Auto-Negotiation process is completed.
Bit [15:6]: Reserved
Bit [31:16]: Reserved
—
Device abilities advertised to the link partner during
Auto-Negotiation
Bit [0]: Reserved
Bit [6:1]: Reserved
Bit [7]:
EEE_CLOCK_STOP_CAPABILITY
Indicates whether or not energy efficient ethernet (EEE) clock stop is supported.
• 0: Not supported
• 1: Supported
Bit [8]:
EEE_CAPABILITY
Indicates whether or not EEE is supported.
• 0: Not supported
• 1: Supported
—
—
RO
—
—
—
—
—
—
RO
RO
—
—
0x0
—
—
—
—
—
—
0x0
0x0 continued...
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Addr
0x406:0x411
0x412
0x413:0x41F
0x461
Name
Reserved usxgmii_link_tim er
Reserved phy_serial_loopb ack
Description
Bit [11:9]:
SPEED
• 3'b000: 10M
• 3'b001: 100M
• 3'b010: 1G
• 3'b011: 10G
• 3'b100: 2.5G
• 3'b101: 5G
• 3'b110: Reserved
• 3'b111: Reserved
Bit [12]:
DUPLEX
Indicates the duplex mode.
• 0: Half duplex
• 1: Full duplex
Bit [13]: Reserved
Bit [14]:
ACKNOWLEDGE
A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.
Bit [15]:
LINK
Indicates the link status.
• 0: Link down
• 1: Link up
Bit [31:16]: Reserved
—
Auto-Negotiation link timer. Sets the link timer value in bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensure that it matches the link timer value of the external NBASE-T
PHY IP Core.
The reset value sets the link timer to approximately 1.6
ms.
Bits [13:0] are reserved and always set to 0.
—
Configures the transceiver serial loopback in the PMA from TX to RX.
Bit [0]
• 0: Disables the PHY serial loopback
• 1: Enables the PHY serial loopback
Bit [15:1]: Reserved
Bit [31:16]: Reserved
Access HW Reset
Value
RO 0x0
RO
—
RO
RO
—
—
[19:14
]: RW
[13:0]:
RO
—
—
RW
—
—
0x0
—
0x0
0x0
—
—
[19:14]:
0x1F
[13:0]:
0x0
—
—
—
—
0x0
2.6.5.3.1. Register Map
You can access the 16-bit/32-bit configuration registers (
interface.
via the Avalon-MM
(37) These registers are identical to the Intel Arria 10 variation of 1G/2.5G/5G/10G Multi-rate
Ethernet PHY IP core.
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Table 156.
Register Map
Address Range
0x00 : 0x1F
0x400 : 0x41F
0x461
Usage
1000BASE-X/SGMII
USXGMII
Serial Loopback
Bit
16
32
32
Configuration
2.5G, 1G/2.5G, 10M/
100M/1G/2.5, 10M/
100M/1G/2.5G/10G
(MGBASE-T), 1G/2.5G/10G
(MGBASE-T)
1G/2.5G/5G/10G (USXGMII)
1G/2.5G/5G/10G (USXGMII)
2.6.5.3.2. Definition: Register Access
Table 157.
Types of Register Access
RO
RW
RWC
Access Definition
Read only.
Read and write.
Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP core clears the bit(s) upon executing the instruction.
2.6.5.4. Interface Signals
Figure 80.
PHY Interface Signals
Serial
Interface tx_serial_clk rx_cdr_refclk rx_cdr_refclk1 rx_pma_clkout tx_serial_data rx_serial_data
Avalon-MM
Control & Status
Interface csr_clk csr_address[4:0] csr_write csr_read csr_writedata[] (i) csr_readdata[] (i) csr_waitrequest xcvr_mode[1:0] operating_speed[2:0] latency_measure_clk
Reset reset pll_powerdown tx_digitalreset rx_digitalreset tx_analogreset rx_analogreset
Status
Interface led_link led_char_err led_disp_err led_an rx_block_lock
PHY tx_clkout gmii16b_tx_d[15:0] gmii16b_tx_en[1:0] gmii16b_tx_err[1:0] gmii16b_tx_latency[21:0] rx_clkout gmii16b_rx_d[15:0] gmii16b_rx_dv[1:0] gmii16b_rx_err[1:0] gmii16b_rx_latency[21:0] xgmii_tx_coreclkin xgmii_tx_control[7:0] xgmii_tx_data[63:0] xgmii_tx_valid xgmii_rx_coreclkin xgmii_rx_control[7:0] xgmii_rx_data[63:0] xgmii_rx_valid rx_is_lockedtodata tx_cal_busy rx_cal_busy reconfig_clk reconfig_reset reconfig_address[9:0] reconfig_write reconfig_read reconfig_writedata[31:0] reconfig_readdata[31:0] reconfig_waitrequest
TX GMII
RX GMII
TX XGMII
RX XGMII
Arria 10
Transceiver Status &
Reconfiguration Interface
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2.6.5.4.1. Clock and Reset Signals
Table 158.
Clock and Reset Signals
Signal Name
Clock signals
Direction tx_clkout
Output rx_clkout
Output
Width
1
1 csr_clk xgmii_tx_coreclkin xgmii_rx_coreclkin latency_measure_clk tx_serial_clk rx_cdr_refclk rx_cdr_refclk_1 rx_pma_clkout
Reset signals reset tx_analogreset
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
1
1
1
1
1
1
1
1
1-3
1
Description
GMII TX clock, derived from tx_serial_clk[1:0]
. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE.
GMII RX clock, derived from tx_serial_clk[1:0]
. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE.
Clock for the Avalon-MM control and status interface. Intel recommends 125 – 156.25 MHz for this clock.
XGMII TX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 1G/
2.5G/5G/10G (USXGMII) mode. Synchronous to tx_serial_clk
with zero ppm.
XGMII RX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 1G/
2.5G/5G/10G (USXGMII) mode.
Sampling clock for measuring the latency of the
16-bit GMII datapath. This clock operates at 80
MHz and is available only when the IEEE 1588v2 feature is enabled.
Serial clock from transceiver PLLs.
• 2.5GbE: Connect bit [0] to the transceiver PLL.
This clock operates at 1562.5 MHz.
• 1GbE: Connect bit [1] to the transceiver PLL.
This clock operates at 625 MHz.
• 10GbE: Connect bit [2] to the transceiver PLL.
This clock operates at 5156.25 MHz.
• 1G/2.5G/5G/10G (USXGMII) mode: Connect bit
[0] to 5156.25 MHz.
125-MHz RX CDR reference clock for 1GbE and
2.5GbE
RX CDR reference clock for 10GbE. The frequency of this clock can be either 322.265625 MHz or
644.53125 MHz, as specified by the Reference
clock frequency for 10 GbE (MHz) parameter setting.
Recovered clock from CDR, operates at the following frequency:
• 1GbE: 125 MHz
• 2.5GbE: 312.5 MHz
• 5GbE/10GbE: 322.265625 MHz
Active-high global reset. Assert this signal to trigger an asynchronous global reset.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an asynchronous reset to the analog block on the TX path.
continued...
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Signal Name tx_digitalreset rx_analogreset rx_digitalreset
Direction
Input
Input
Input
Width
1
1
1
Description
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the TX path.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an asynchronous reset to the receiver CDR.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the RX path.
2.6.5.4.2. Operating Mode and Speed Signals
Table 159.
Transceiver Mode and Operating Speed Signals
Signal Name xcvr_mode operating_speed
Direction
Input
Output
Width
2
3
Description
Connect this signal to the reconfiguration block.
Use the values below to set the speed:
• 0x0 = 1G
• 0x1 = 2.5G
• 0x3 = 10G
Connect this signal to the MAC. This signal provides the current operating speed of the PHY:
• 0x0 = 10G
• 0x1 = 1G
• 0x4 = 2.5G
• 0x5 = 5G
2.6.5.4.3. GMII Signals
The 16-bit TX and RX GMII supports 1GbE and 2.5GbE at 62.5 MHz and 156.25 MHz respectively.
Table 160.
GMII Signals
Signal Name Direction
TX GMII signals—synchronous to tx_clkout gmii16b_tx_d
Input
Width
16
Description gmii16b_tx_en gmii16b_tx_err
Input
Input
2
2
TX data from the MAC. The MAC sends the lower byte first followed by the upper byte.
When asserted, indicates the start of a new frame from the MAC. Bit[0] corresponds to gmii16b_tx_d
[7:0]; bit[1] corresponds to gmii16b_tx_d
[15:8].
This signal remains asserted until the PHY receives the last byte of the data frame.
When asserted, indicates an error. Bit[0] corresponds to gmii16b_tx_err
[7:0]; bit[1] corresponds to gmii16b_tx_err
[15:8].
The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.
continued...
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Signal Name gmii16b_tx_latency
Direction
Output
Width
22
Description
The latency of the PHY excluding the PMA block on the TX datapath:
• Bits [21:10]: The number of clock cycles.
• Bits [9:0]: The fractional number of clock cycles.
This signal is available when only the Enable IEEE
1588 Precision Time Protocol parameter is selected.
RX GMII signals—synchronous to rx_clkout gmii16b_rx_d
Output gmii16b_rx_err gmii16b_rx_dv gmii16b_rx_latency
Output
Output
Output
16
2
2
22
RX data to the MAC. The PHY sends the lower byte first followed by the upper byte. Rate matching is done by the PHY on the RX data from the RX recovered clock to rx_clkout
.
When asserted, indicates an error. Bit[0] corresponds to gmii16b_rx_err
[7:0]; bit[1] corresponds to gmii16b_rx_err
[15:8].
The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.
When asserted, indicates the start of a new frame.
Bit[0] corresponds to gmii16b_rx_d
[7:0]; bit[1] corresponds to gmii16b_rx_d
[15:8].
This signal remains asserted until the PHY sends the last byte of the data frame.
The latency of the PHY excluding the PMA block on the RX datapath:
• Bits [21:10]: The number of clock cycles.
• Bits [9:0]: The fractional number of clock cycles.
This signal is available only when the Enable IEEE
1588 Precision Time Protocol parameter is selected.
2.6.5.4.4. XGMII Signals
The XGMII supports 10GbE at 156.25 MHz.
Table 161.
XGMII Signals
Signal Name Direction Width
TX XGMII signals—synchronous to xgmii_tx_coreclkin xgmii_tx_data
Input 64, 32 xgmii_tx_control
Input 8, 4
Description
TX data from the MAC. The MAC sends the data in the following order: bits[7:0], bits[15:8], and so forth.
The width is:
• 64 bits for 1G/2.5G/10G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations.
TX control from the MAC:
• xgmii_tx_control
[0] corresponds to xgmii_tx_data
[7:0]
• xgmii_tx_control
[1] corresponds to xgmii_tx_data
[15:8]
• and so forth.
The width is: continued...
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Signal Name xgmii_tx_valid
Direction
Output
Width
1
Description
• 8 bits for 1G/2.5G/10G configurations.
• 4 bits for 1G/2.5G/5G/10G configurations.
Indicates valid data on xgmii_tx_control
and xgmii_tx_data
from the MAC.
Your logic/MAC must toggle the valid data as shown below:
1G
2.5G
5G
10G
Speed Toggle Rate
Asserted once every 10 clock cycles
Asserted once every 4 clock cycles
Asserted once every 2 clock cycles
Always asserted
RX XGMII signals—synchronous to xgmii_rx_coreclkin xgmii_rx_data
Output 64, 32 xgmii_rx_control xgmii_rx_valid
Output
Output
8, 4
1
RX data to the MAC. The PHY sends the data in the following order: bits[7:0], bits[15:8], and so forth.
The width is:
• 64 bits for 1G/2.5G/10G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations.
RX control to the MAC.
• xgmii_rx_control
[0] corresponds to xgmii_rx_data
[7:0]
• xgmii_rx_control
[1] corresponds to xgmii_rx_data
[15:8]
• and so forth.
The width is:
• 8 bits for 1G/2.5G/10G configurations.
• 4 bits for 1G/2.5G/5G/10G configurations.
Indicates valid data on xgmii_rx_control
and xgmii_rx_data
from the MAC.
The toggle rate from the PHY is shown in the table below.
Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.
Speed
1G
2.5G
5G
10G
Toggle Rate
Asserted once every 10 clock cycles
Asserted once every 4 clock cycles
Asserted once every 2 clock cycles
Always asserted
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2.6.5.4.5. Status Signals
Table 162.
Status Signals
Signal Name Direction Clock
Domain
Width Description led_char_err led_link led_disp_err led_an rx_block_lock
Output
Output
Output
Output
Output
Synchronous to tx_clkout
Synchronous to rx_clkout
Synchronous to rx_clkout
Synchronous to rx_clkout
1
1
1
1
1
Asserted when a 10-bit character error is detected in the RX data.
Asserted when the link synchronization for
1GbE or 2.5GbE is successful
Asserted when a 10-bit running disparity error is detected in the RX data.
Asserted when auto-negotiation is completed.
Asserted when the link synchronization for
10GbE is successful.
2.6.5.4.6. Serial Interface Signals
The serial interface connects to an external device.
Table 163.
Serial Interface Signals
Signal Name tx_serial_data rx_serial_data
Direction
Output
Input
Width
1
1
TX data.
RX data.
Description
2.6.5.4.7. Transceiver Status and Reconfiguration Signals
Table 164.
Control and Status Signals
Signal Name rx_is_lockedtodata tx_cal_busy
Direction
Output
Output
Output
Width
1
1
1 rx_cal_busy
Transceiver reconfiguration signals for Arria 10 devices reconfig_clk
Input 1 reconfig_reset reconfig_address reconfig_write reconfig_read reconfig_writedata reconfig_readdata reconfig_waitrequest
Input
Input
Input
Input
Input
Output
Output
32
32
1
1
1
1
10
Description
Asserted when the CDR is locked to the RX data.
Asserted when TX calibration is in progress.
Asserted when RX calibration is in progress.
Reconfiguration signals connected to the reconfiguration block. The reconfig_clk
signal provides the timing reference for this interface.
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2.6.5.4.8. Avalon-MM Interface Signals
The Avalon-MM interface is an Avalon-MM slave port. This interface uses word addressing and provides access to the 16-bit configuration registers of the PHY.
Table 165.
Avalon-MM Interface Signals
Signal Name csr_address
Direction
Input
Width
5, 11 csr_read csr_readdata csr_write csr_writedata csr_waitrequest
Input
Output
Input
Input
Output
1
16, 32
1
16, 32
1
Description
Use this bus to specify the register address to read from or write to. The width is:
• 5 bits for 2.5G and 1G/2.5G configurations.
• 11 bits for 1G/2.5G/5G/10G configurations.
Assert this signal to request a read operation.
Data read from the specified register. The data is valid only when the csr_waitrequest deasserted. The width is:
signal is
• 16 bits for 2.5G and 1G/2.5G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations. The upper 16 bits are reserved.
Assert this signal to request a write operation.
Data to be written to the specified register. The data is written only when the csr_waitrequest signal is deasserted. The width is:
• 16 bits for 2.5G and 1G/2.5G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations. The upper 16 bits are reserved.
When asserted, indicates that the PHY is busy and not ready to accept any read or write requests.
• When you have requested for a read or write, keep the control signals to the Avalon-MM interface constant while this signal is asserted.
The request is complete when it is deasserted.
• This signal can be high or low during idle cycles and reset. Therefore, the user application must not make any assumption of its assertion state during these periods.
2.6.6. XAUI PHY IP Core
In a XAUI configuration, the transceiver channel data path is configured using a soft
PCS. The XAUI configuration provides the transceiver channel datapath, clocking, and channel placement guidelines. You can implement a XAUI link using the IP Catalog.
Under Ethernet in the Interfaces menu, select the XAUI PHY IP core. The XAUI PHY IP core implements the XAUI PCS in soft logic.
XAUI is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in the IEEE 802.3ae-2008 specification. The XAUI PHY uses the XGMII interface to connect to the IEEE802.3 MAC and Reconciliation Sublayer (RS). The IEEE
802.3ae-2008 specification requires the XAUI PHY link to support:
• A 10 Gbps data rate at the XGMII interface
• Four lanes each at 3.125 Gbps at the PMD interface
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Figure 81.
XAUI and XGMII Layers
LAN Carrier Sense Multiple
Access/Collision Detect (CSMA/CD)
Layers
Higher Layers
Logical Link Control (LLC)
OSI
Reference
Model Layers
MAC Control (Optional)
Media Access Control (MAC)
Application
Reconciliation
Presentation
10 Gigabit Media Independent Interface
Session
Transport
Optional
XGMII
Extender
XGMII Extender Sublayer
10 Gigabit Attachment Unit Interface
XGMII Extender Sublayer
10 Gigabit Media Independent Interface
Network
Data Link
PCS
PMA
PMD
Physical Layer Device
Physical
Medium Dependent Interface
Medium
10 Gbps
Intel's XAUI PHY IP core implements the IEEE 802.3 Clause 48 specification to extend the operational distance of the XGMII interface and reduce the number of interface signals.
XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC function and the Ethernet standard PHY component to one meter. The XAUI PHY IP core accepts 72-bit data (single data rate–SDR XGMII) from the application layer at
156.25 Mbps. The serial interface runs at 4 × 3.125 Gbps.
Figure 82.
XAUI PHY IP Core
XAUI PHY IP
SDR XGMII
72 bits @ 156.25 Mbps
XAUI PHY IP Core
PCS
8B/10B
Word Aligner
Phase Comp
Hard PMA
Avalon-MM
Control & Status
4
4
4 x 3.125 Gbps serial
Intel's third-party IP partner for Dual Data Rate XAUI (DDR XAUI or DXAUI) and
Reduced XAUI (RXAUI) support is MorethanIP (MTIP).
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XAUI does not support open compute project (OCP) networking.
Related Information
• IEEE 802.3 Clause 48
• MorethanIP
2.6.6.1. Transceiver Datapath in a XAUI Configuration
The XAUI PHY IP core is partially implemented in soft logic inside the FPGA core. You must ensure that your channel placement is compatible with the soft PCS implementation.
Figure 83.
Transceiver Channel Datapath for XAUI Configuration
The XAUI configuration uses both the soft PCS and the Standard PCS as shown in the following figure.
Channel 3
Channel 2
Channel 1
Channel 0
FPGA Fabric
Soft PCS
Soft PCS
Soft PCS
Soft PCS
Channel 3
Channel 2
Channel 1
Channel 0
Portable solution using Custom PHY or Native PHY
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter PMA Ch3
Transmitter PMA Ch2
Transmitter PMA Ch1
Transmitter PMA Ch0
16 20 20 10
20
Receiver Standard PCS
10 10
Receiver PMA
16 20 20 20
2.6.6.2. XAUI Supported Features
64-Bit SDR Interface to the MAC/RS
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the XAUI PCS and the Ethernet MAC/RS. Each of the four XAUI lanes must transfer 8bit data and a 1-bit control code at both the positive and negative edge (double data rate) of the 156.25 MHz interface clock.
Arria 10 transceivers and a soft PCS solution in a XAUI configuration do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification.
Instead, they transfer 16-bit data and the 2-bit control code on each of the four XAUI lanes. The transfer occurs only at the positive edge (single data rate) of the 156.25
MHz interface clock.
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Figure 84.
Implementation of the XGMII Specification in Arria 10 Devices Configuration
The ATX PLL is only supported to drive the internal transceiver. The FPLL is only supported to drive xgmii_tx_clk
and xgmii_rx_clk
. Both the ATX PLL and the FPLL must be clocked by the same reference clock to maintain 0 ppm.
XGMII Transfer (DDR)
Interface Clock (156.25 MHz)
Lane 0
8-bit
D0 D1 D2 D3
Lane 1 D0 D1 D2 D3
D2
D2
D3
D3
Lane 2 D0
Lane 3
Arria 10 Soft PCS Interface (SDR)
Interface Clock (156.25 MHz)
D0
Lane 0
16-bit
{D1, D0}
D1
Lane 1 {D1, D0}
D1
{D3, D2}
{D3, D2}
Lane 2
{D1, D0} {D3, D2}
Lane 3 {D1, D0} {D3, D2}
8B/10B Encoding/Decoding
Each of the four lanes in a XAUI configuration supports an independent 8B/10B encoder/decoder as specified in Clause 48 of the IEEE802.3-2008 specification.
8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial data stream to five. This limit ensures DC balance as well as enough transitions for the receiver CDR to maintain a lock to the incoming data.
The XAUI PHY IP core provides status signals to indicate both running disparity and the 8B/10B code group error.
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Transmitter and Receiver State Machines
In a XAUI configuration, the Arria 10 soft PCS implements the transmitter and receiver state diagrams shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008 specification.
The transmitter state machine performs the following functions in conformance with the 10GBASE-X PCS:
• Encoding the XGMII data to PCS code groups
• Converting Idle ||I|| ordered sets into Sync ||K||, Align ||A||, and Skip ||R|| ordered sets
The receiver state machine performs the following functions in conformance with the
10GBASE-X PCS:
• Decoding the PCS code groups to XGMII data
• Converting Sync ||K||, Align ||A||, and Skip ||R|| ordered sets into Idle ||I|| ordered sets
Synchronization
The word aligner block in the receiver PCS of each of the four XAUI lanes implements the receiver synchronization state diagram shown in Figure 48-7 of the
IEEE802.3-2008 specification.
The XAUI PHY IP core provides a status signal per lane to indicate if the word aligner is synchronized to a valid word boundary.
Deskew
The lane aligner block in the receiver PCS implements the receiver deskew state diagram shown in Figure 48-8 of the IEEE 802.3-2008 specification.
The lane aligner starts the deskew process only after the word aligner block in each of the four XAUI lanes indicates successful synchronization to a valid word boundary.
The XAUI PHY IP core provides a status signal to indicate successful lane deskew in the receiver PCS.
Clock Compensation
The rate match FIFO in the receiver PCS datapath compensates up to ±100 ppm difference between the remote transmitter and the local receiver. It compensates by inserting and deleting Skip ||R|| columns, depending on the ppm difference.
The clock compensation operation begins after:
• The word aligner in all four XAUI lanes indicates successful synchronization to a valid word boundary.
• The lane aligner indicates a successful lane deskew.
The rate match FIFO provides status signals to indicate the insertion and deletion of the Skip ||R|| column for clock rate compensation.
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2.6.6.3. XAUI PHY Release Information
Table 166.
XAUI Release Information
Item
Version
Release Date
Product ID
Vendor ID
16.0
November 2016
00D7
6AF7
Description
2.6.6.4. XAUI PHY Device Family Support
IP cores provide either final or preliminary support for target Intel device families.
These terms have the following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 167.
Device Family Support
Device Family Support
Arria 10
XAUI
Preliminary
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2.6.6.5. Transceiver Clocking and Channel Placement Guidelines in XAUI
Configuration
Transceiver Clocking
Figure 85.
Transceiver Clocking for XAUI Configuration Without Phase Compensation
FIFO Enabled
The external ATX PLL generates the transmitter serial and parallel clocks for the four XAUI channels. You must instantiate the PLL and connect it to XAUI. The x6 clock line carries the transmitter serial and parallel clocks to the PMA and PCS of each of the four channels.
XAUI PHY IP Core
Channel 3
Channel 2
Channel 1
Channel 0
Soft PCS
Soft PCS
Soft PCS
Soft PCS
Channel 3
Channel 2
Channel 1
Channel 0
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter PMA Ch 3
Transmitter PMA Ch 2
Transmitter PMA Ch 1
Transmitter PMA Ch 0
16 20 20 10 xgmii_tx_clk
16 20 20 20
/2
Parallel Clock
Receiver Standard PCS
10 10
Receiver PMA
Note: xgmii_rx_clk
Parallel Clock
Parallel Clock
(Recovered) from Channel 0
/2
Parallel Clock (Recovered)
Master Clock Generation Block
(1)
ATX PLL
Serial Clock
(From the ×1 Clock Lines)
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Note:
1. Use the ATX PLL as the transmit PLL for XAUI support in Arria 10 devices.
When configuring ATX PLL, the PMA width setting must be set to 20-bit per transceiver channel. This ensures that the serial clock is running at 3.125 Gbps while the input reference clock is 156.25 MHz.
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Figure 86.
Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO
Enabled
When phase compensation FIFO is enabled, you can connect the core to different clocks on the Avalon-ST interface.
Parallel Clock
Parallel Clock (x6 Network)
Serial Clock
Parallel Recovered Clock
Parallel Recovered Clock 2
Serial Recovered Clock
XAUI PHY IP Core
Soft PCS
Transmitter Standard PCS Transmitter PMA
32/64b
Avalon-ST
Adapter
MAC
36/72b
XGMII
Adapter xgmii_tx_clk 156.25 MHz
Receiver Standard PCS Receiver PMA
156.25 MHz
Parallel Recovered Clock 2 (1) Parallel Recovered Clock
Serial Recovered Clock fPLL
REFCLK 156.25 MHz
ATX PLL x1 Network
Master CGB
Parallel Clock (x6 Network)
Serial Clock (x6 Network)
Note:
1. One recovered clock drives four XAUI channels.
2.6.6.6. XAUI PHY Performance and Resource Utilization
The following table lists the typical expected device resource utilization for different configurations using the current version of the Quartus II software targeting an Arria
10 device. The numbers of combinational ALUTs and logic registers are rounded to the nearest 100.
Table 168.
XAUI PHY Performance and Resource Utilization
Implementation
Soft XAUI 4
Number of 3.125
Gbps Channels
Combinational ALUTs
1700
Dedicated Logic
Registers
1700
M20K Memory Blocks
3
2.6.6.7. Parameterizing the XAUI PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Complete the following steps to configure the XAUI PHY IP core in the IP Catalog:
1. For Which device family will you be using?, select Arria 10.
2. Click Installed IP
➤
Library
➤
Interface Protocols
➤
Ethernet
➤
XAUI PHY.
3. Use the tabs on the IP Catalog to select the options required for the protocol.
4. Refer to the following topics to learn more about the parameters: a. General Parameters
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b. Analog Parameters c. Advanced Options Parameters
5. Click Finish to generate your customized XAUI PHY IP core.
Related Information
•
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
•
XAUI PHY General Parameters on page 222
•
Analog Parameter Settings on page 585
•
XAUI PHY Advanced Options Parameters
on page 222
2.6.6.7.1. XAUI PHY General Parameters
This section describes the settings available on the General Options tab.
Table 169.
General Options
Name
Device family
XAUI interface type
Arria 10
Soft XAUI
Enable Sync-E support On / Off
Number of XAUI interfaces 1
Value Description
The target device family.
Implements the PCS in soft logic and the PMA in hard logic. Includes four channels.
Shows separate reference clocks for CDR PLL and TX PLL.
Specifies the number of XAUI interfaces. Only 1 is available in the current release.
2.6.6.7.2. XAUI PHY Advanced Options Parameters
This section describes the settings available on the Advanced Options tab.
Table 170.
Advanced Options
Name
Include control and status ports
Value
On / Off
Enable dynamic reconfiguration
Enable rx_recovered_clk pin
Enable phase compensation
FIFO
On / Off
On / Off
On / Off
Description
If you turn this option on, the top-level IP core includes the status signals and digital resets shown in XAUI Top-Level Signals
—Soft PCS and PMA and XAUI Top-Level Signals—Hard IP PCS and PMA. If you turn this option off, you can access control and status information using the Avalon-MM interface to the control and status registers. The default setting is off.
When you turn this option on, you can connect the dynamic reconfiguration ports to an external reconfiguration module.
When you turn this option on, the RX recovered clock signal is an output signal.
Enables the phase compensation FIFO to allow different clocks on the xgmii interface.
2.6.6.8. XAUI PHY Ports
The following figure illustrates the top-level signals of the XAUI PHY IP core for the soft IP implementation.
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Figure 87.
XAUI Top-Level Signals—Soft PCS and PMA
XAUI Top-Level Signals
SDR TX XGMII
SDR RX XGMII
Avalon-MM PHY
Management
Interface
Clocks
PLL xgmii_tx_dc[71:0] xgmii_tx_clk xgmii_rx_dc[71:0] xgmii_rx_clk xgmii_rx_inclk phy_mgmt_clk phy_mgmt_clk_reset phy_mgmt_address[8:0] phy_mgmt_writedata[31:0] phy_mgmt_readdata[31:0] phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest pll_ref_clk cdr_ref_clk pll_locked_i pll_powerdown_o tx_bonding_clock[5:0] pll_cal_busy_i xaui_rx_serial_data[3:0] xaui_tx_serial_data[3:0] rx_channelaligned rx_disperr[7:0] rx_errdetect[7:0] rx_syncstatus[7:0] reconfig_clk reconfig_reset reconfig_address[11:0] reconfig_writedata[31:0] reconfig_readdata[31:0] reconfig_write reconfig_read reconfig_waitrequest rx_recovered_clk[3:0] rx_ready tx_ready
Transceiver
Serial Data
RX Status
Optional
Avalon-MM
Dynamic
Reconfiguration
PMA
Channel
Controller
2.6.6.9. XAUI PHY Interfaces
The XAUI PCS interface to the FPGA fabric uses a SDR XGMII interface. This interface implements a simple version of the Avalon-ST protocol. The interface does not include ready or valid signals. Consequently, the sources always drive data and the sinks must always be ready to receive data.
For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Specifications.
Depending on the parameters you choose, the application interface runs at either
156.25 Mbps or 312.5 Mbps. At either frequency, data is only driven on the rising edge of clock. To meet the bandwidth requirements, the datapath is eight bytes wide with eight control bits, instead of the standard four bytes of data and four bits of control.
The XAUI PHY IP core treats the datapath as two, 32-bit data buses and includes logic to interleave them, starting with the low-order bytes.
Figure 88.
Interleaved SDR XGMII Data Mapping
Original XGMII Data
[63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0]
[63:56] [31:24] [55:48]
Related Information
Avalon Interface Specifications
[23:16]
Interleaved Result
[47:40] [15:8] [39:32] [7:0]
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2.6.6.9.1. SDR XGMII TX Interface
Table 171.
SDR TX XGMII Interface
Signal Name xgmii_tx_dc[71:0]
Direction
Input xgmii_tx_clk
Input
Description
Contains 4 lanes of data and control for XGMII. Each lane consists of
16 bits of data and 2 bits of control. Synchronous to mgmt_clk
.
• Lane 0–[7:0]/[8], [43:36]/[44]
• Lane 1–[16:9]/[17], [52:45]/[53]
• Lane 2–[25:18]/[26], [61:54]/[62]
• Lane 3–[34:27]/[35],[70:63]/[71]
The XGMII SDR TX clock which runs at 156.25 MHz.
2.6.6.9.2. SDR XGMII RX Interface
Table 172.
SDR RX XGMII Interface
Signal Name xgmii_rx_dc_[71:0]
Direction
Output xgmii_rx_clk xgmii_rx_inclk
Output
Input
Description
Contains 4 lanes of data and control for XGMII. Each lane consists of
16 bits of data and 2 bits of control. Synchronous to mgmt_clk
.
• Lane 0–[7:0]/[8], [43:36]/[44]
• Lane 1–[16:9]/[17], [52:45]/[53]
• Lane 2–[25:18]/[26], [61:54]/[62]
• Lane 3–[34:27]/[35],[70:63]/[71]
The XGMII SDR RX clock which runs at 156.25 MHz.
The XGMII SDR RX input clock which runs at 156.25 MHz. This port is only available when Enable phase compensation FIFO is selected.
2.6.6.9.3. Transceiver Serial Data Interface
The XAUI transceiver serial data interface has four lanes of serial data for both the TX and RX interfaces. This interface runs at 3.125 Gbps. There is no separate clock signal because it is encoded in the data.
Table 173.
Serial Data Interface
Signal Name xaui_rx_serial_data[3:0] xaui_tx_serial_data[3:0]
Direction
Input
Output
Serial input data.
Serial output data.
Description
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2.6.6.9.4. XAUI PHY Clocks, Reset, and Powerdown Interfaces
Figure 89.
Clock Inputs and Outputs for IP Core with Soft PCS phy_mgmt_clk pll_ref_clk
XAUI Soft IP Core xgmii_tx_clk xgmii_rx_clk
Soft PCS
pma_pll_inclk sysclk pma_tx_clkout pma_rx_clkout pll_ref_clk
PMA
tx_clkout rx_recovered_clk
4
4
4 x 3.125 Gbps serial
Table 174.
Clock and Reset Signals
Signal Name pll_ref_clk
Direction
Input
Description
This is a 156.25 MHz reference clock that is used by the CDR logic.
2.6.6.9.5. XAUI PHY PMA Channel Controller Interface
Table 175.
PMA Channel Controller Signals
Signal Name rx_recovered_clk[3:0]
Direction
Output rx_ready tx_ready pll_cal_busy_i
Output
Output
Input
Description
This is the RX clock, which is recovered from the received data stream.
Indicates PMA RX has exited the reset state and the transceiver can receive data. Synchronous to mgmt_clk
.
Indicates PMA TX has exited the reset state and the transceiver can transmit data. Synchronous to mgmt_clk
.
Indicates the PLL calibration status.
2.6.6.9.6. XAUI PHY Optional PMA Control and Status Interface
Use the Avalon-MM PHY Management interface to read the state of the optional PMA control and status signals available in the XAUI PHY IP core registers. In some cases you may need to know the instantaneous value of a signal to ensure correct functioning of the XAUI PHY. In such cases, you can include the required signal in the top-level module of your XAUI PHY IP core.
Table 176.
Optional Control and Status Signals—Soft IP Implementation
Signal Name rx_channelaligned rx_disperr[7:0]
Direction
Output
Output
Description
When asserted, indicates that all 4 RX channels are aligned. Synchronous to to receive data.
mgmt_clk
. This signal is asserted when the RX lanes are fully aligned and ready
Received 10-bit code or data group has a disparity error. It is paired with rx_errdetect
which is also asserted when a disparity error occurs. The continued...
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Signal Name rx_errdetect[7:0] rx_syncstatus[7:0]
Direction
Output
Output
Description rx_disperr
signal is 2 bits wide per channel for a total of 8 bits per XAUI link. Synchronous to mgmt_clk
.
When asserted, indicates an 8B/10B code group violation. It is asserted if the received 10-bit code group has a code violation or disparity error. Use rx_errdetect
with the rx_disperr
signal to differentiate between a code violation error, a disparity error, or both. The rx_errdetect
signal is 2 bits wide per channel for a total of 8 bits per XAUI link.
Synchronous to mgmt_clk
.
Synchronization indication. RX synchronization is indicated on the rx_syncstatus
port of each channel. The rx_syncstatus
signal is 2 bits per channel for a total of 8 bits per hard XAUI link. The rx_syncstatus
signal is 1 bit per channel for a total of 4 bits per soft XAUI link. Synchronous to mgmt_clk
.
2.6.6.10. XAUI PHY Register Interface and Register Descriptions
The Avalon-MM PHY management interface provides access to the XAUI PHY IP core
PCS, PMA, and transceiver reconfiguration registers.
Table 177.
Signals in the Avalon-MM PHY Management Interface phy_mgmt_clk
Signal Name phy_mgmt_clk_reset phy_mgmt_addr[8:0] phy_mgmt_writedata[31:0] phy_mgmt_readdata[31:0] phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest
Direction
Input
Input
Input
Input
Output
Input
Input
Output
Description
Avalon-MM clock input.
Global reset signal that resets the entire XAUI PHY. This signal is active high and level sensitive.
9-bit Avalon-MM address.
32-bit input data.
32-bit output data.
Write signal. Asserted high.
Read signal. Asserted high.
When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request.
When asserted, control signals to the Avalon-MM slave interface must remain constant.
Note:
For more information about the Avalon-MM interface, including timing diagrams, refer to the Avalon Interface Specification.
The following table specifies the registers that you can access using the Avalon-MM
PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers.
Writing to reserved or undefined register addresses may have undefined side effects.
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Table 178.
XAUI PHY IP Core Registers
Word
Addr
Bits R/W Register Name
0x041
0x042
0x044
[31:0]
[1:0]
RW
W
R
RW
Description
Reset Control Registers–Automatic Reset Controller reset_ch_bitmask
Bit mask for reset registers at addresses 0x042 and
0x044. The default value is all 1s. You can reset channel < n
> when bit< n
> = 1.
reset_control
(write) Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the a 1 to bit 1 initiates a RX digital reset of channels enabled in the clears.
reset_ch_bitmask reset_ch_bitmask
. Writing
. This bit selfreset_status
Reserved
(read) Reading bit 0 returns the status of the reset controller
TX ready bit. Reading bit 1 returns the status of the reset controller RX ready bit. This bit self-clears.
Reset Controls –Manual Mode
It is safe to write 0s to reserved bits.
[31:4,0
]
[1] RW
0x061
0x064
0x065
0x066
0x067
0x084
[2]
[3]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:16]
[15:8]
RW
RW
RW
RW
RW
RO
RO
N/A
R reset_tx_digital reset_rx_analog pma_rx_set_locktoref pma_rx_is_lockedtodata pma_rx_is_lockedtoref
Writing a 1 causes the internal TX digital reset signal to be asserted, resetting all channels enabled in reset_ch_bitmask
. You must write a 0 to clear the reset condition.
Writing a 1 causes the internal RX analog reset signal to be asserted, resetting the RX analog logic of all channels enabled in reset_ch_bitmask write a 0 to clear the reset condition.
. You must reset_rx_digital
Writing a 1 causes the RX digital reset signal to be asserted, resetting the RX digital channels enabled in reset_ch_bitmask
. You must write a 0 to clear the reset condition.
PMA Control and Status Registers phy_serial_loopback pma_rx_set_locktodata
Writing a 1 to channel < n
> puts channel < n
> in serial loopback mode. For information about pre- or post-CDR serial loopback modes, refer to Loopback
Modes.
When set, programs the RX CDR PLL to lock to the incoming data. Bit < n
> corresponds to channel < n
>.
When set, programs the RX CDR PLL to lock to the reference clock. Bit < n
> corresponds to channel < n
>.
When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit < n
> corresponds to channel < n
>.
When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit < n
> corresponds to channel < n
>.
XAUI PCS
Reserved
Reserved
N/A
N/A continued...
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Word
Addr
Bits R/W Register Name Description
0x085 [31:16]
[15:8]
0x08a
[7:0]
[7:0]
[0]
N/A
R
RW syncstatus[7:0]
Reserved errdetect[7:0] disperr[7:0] simulation_flag
Records the synchronization status of the corresponding bit. The RX sync status register has 1 bit per channel for a total of 4 bits per soft XAUI link; soft XAUI uses bits 0–3. Reading the value of the syncstatus
register clears the bits.
From block: Word aligner
N/A
When set, indicates that a received 10-bit code group has an 8B/10B code violation or disparity error. Use errdetect
with disperr
to differentiate between a code violation error, a disparity error, or both. There are 2 bits per RX channel for a total of 8 bits per XAUI link. Reading the value of the clears the bits.
errdetect
register
From block: 8B/10B decoder
Indicates that the received 10-bit code or data group has a disparity error. When set, the corresponding errdetect
bits are also set. There are 2 bits per RX channel for a total of 8 bits per XAUI link. Reading the value of the errdetect
register clears the bits.
From block: 8B/10B decoder
Setting this bit to 1 shortens the duration of reset and loss timer when simulating. Intel recommends that you keep this bit set for simulation.
Related Information
Avalon Interface Specifications
2.6.6.11. XAUI PHY Timing Analyzer SDC Constraint
Refer to the "Timing Constraints for Bonded PCS and PMA Channels" section for the
Synopsis Design Constraints (SDC) for XAUI.
Related Information
Timing Constraints for Bonded PCS and PMA Channels
on page 443
2.6.7. Acronyms
This table defines some commonly used Ethernet acronyms.
Table 179.
Ethernet Acronyms
AN
BER
DME
FEC
GMII
KR
Acronym Definition
Auto-Negotiation in Ethernet as described in Clause 73 of IEEE 802.3ap-2007.
Bit Error Rate.
Differential Manchester Encoding.
Forward error correction.
Gigabit Media Independent Interface.
Short hand notation for Backplane Ethernet with 64b/66b encoding.
continued...
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LD
LT
LP
MAC
MII
OSI
PCS
PHY
PMA
PMD
SGMII
WAN
XAUI
Acronym Definition
Local Device.
Link training in backplane Ethernet Clause 72 for 10GBASE-KR and 40GBASE-KR4.
Link partner, to which the LD is connected.
Media Access Control.
Media independent interface.
Open System Interconnection.
Physical Coding Sublayer.
Physical Layer in OSI 7-layer architecture, also in Intel device scope is: PCS + PMA.
Physical Medium Attachment.
Physical Medium Dependent.
Serial Gigabit Media Independent Interface.
Wide Area Network.
10 Gigabit Attachment Unit Interface.
2.7. PCI Express (PIPE)
You can use Arria 10 transceivers to implement a complete PCI Express solution for
Gen1, Gen2, and Gen3, at data rates of 2.5, 5.0, and 8 Gbps, respectively.
Configure the transceivers for PCIe functionality using one of the following methods:
• Arria 10 Hard IP for PCIe
This is a complete PCIe solution that includes the Transaction, Data Link, and
PHY/MAC layers. The Hard IP solution contains dedicated hard logic, which connects to the transceiver PHY interface.
Note: For more information, refer to the Arria 10 Avalon-ST Interface for PCIe
Solutions User Guide .
• Native PHY IP Core in PIPE Gen1/Gen2/Gen3 Transceiver Configuration
Rules
Use the Native PHY IP (Native PHY IP Core) to configure the transceivers in PCIe mode, giving access to the PIPE interface (commonly called PIPE mode in transceivers). This mode enables you to connect the transceiver to a third-party
MAC to create a complete PCIe solution.
The PIPE specification (version 3.0) provides implementation details for a PCIecompliant physical layer. The Native PHY IP Core for PIPE Gen1, Gen2, and Gen3 supports x1, x2, x4, or x8 operation for a total aggregate bandwidth ranging from
2 to 64 Gbps. In a x1 configuration, the PCS and PMA blocks of each channel are clocked and reset independently. The x2, x4, and x8 configurations support channel bonding for two-lane, four-lane, and eight-lane links. In these bonded channel configurations, the PCS and PMA blocks of all bonded channels share common clock and reset signals.
Gen1 and Gen2 modes use 8B/10B encoding, which has a 20% overhead to overall link bandwidth. Gen3 modes use 128b/130b encoding, which has an overhead of less than 2%. Gen1 and Gen2 modes use the Standard PCS, and Gen3 mode uses the
Gen3 PCS for its operation.
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Table 180.
Transceiver Solutions
Support
Gen1, Gen2, and Gen3 data rates
MAC, data link, and transaction layer
Transceiver interface
Arria 10 Hard IP for PCI Express
Yes
Yes
Hard IP through PIPE 3.0 based interface
Native PHY IP Core for PCI Express
(PIPE)
Yes
User implementation in FPGA fabric
• PIPE 2.0 for Gen1 and Gen2
• PIPE 3.0 based for Gen3 with Gen1/
Gen2 support
Related Information
• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express
• Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
2.7.1. Transceiver Channel Datapath for PIPE
Figure 90.
Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations
Transmitter PMA Transmitter Standard PCS FPGA
Fabric
PRBS
Generator
Receiver PMA Receiver Standard PCS
PRBS
Verifier
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Figure 91.
Transceiver Channel Datapath for PIPE Gen1/Gen2/Gen3 Configurations
Transmitter PMA Transmitter Gen3 PCS FPGA
Fabric
Transmitter Standard PCS
Receiver PMA Receiver Gen3 PCS
PRBS
Generator
Receiver Standard PCS
PRBS
Verifier
2.7.2. Supported PIPE Features
PIPE Gen1, Gen2, and Gen3 configurations support different features.
Table 181.
Supported Features for PIPE Configurations
Protocol Feature x1, x2, x4, x8 link configurations
PCIe-compliant synchronization state machine
±300 ppm (total 600 ppm) clock rate compensation
Transmitter driver electrical idle
Receiver detection
8B/10B encoding/decoding disparity control
128b/130b encoding/decoding
Gen1
(2.5 Gbps)
Yes
Yes
Yes
Yes
Yes
Yes
No
Gen2
(5 Gbps)
Yes
Yes
Yes
Yes
Yes
Yes
No
Scrambling/Descrambling
Power state management
Receiver PIPE status encoding pipe_rxstatus[2:0]
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate
No
Yes
Yes
No
No
Yes
Yes
Yes
Gen3
(8 Gbps)
Yes
Yes
Yes
Yes
Yes
No
Yes (supported through the
Gearbox)
Yes
(implemented in FPGA fabric)
(38)
Yes
Yes
No continued...
(38) You must enable scrambling/descrambling in Gen1/Gen2 when using Arria 10 PCIe Gen3 configurations.
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Protocol Feature Gen1
(2.5 Gbps)
No
Gen2
(5 Gbps)
No
Gen3
(8 Gbps)
Yes Dynamic switching between 2.5 Gbps, 5 Gbps, and 8 Gbps signaling rate
Dynamic transmitter margining for differential output voltage control
Dynamic transmitter buffer de-emphasis of –3.5 dB and –6 dB
Dynamic Gen3 transceiver pre-emphasis, de-emphasis, and equalization
PCS PMA interface width (bits)
Receiver Electrical Idle Inference (EII)
No
No
No
Yes
Yes
No
Yes
Yes
Yes
10
Implement in FPGA fabric
10
Implement in
FPGA fabric
32
Implement in
FPGA fabric
Related Information
•
PCIe Gen3 PCS Architecture on page 495
For more information about PIPE Gen3.
• Intel PHY Interface for the PCI Express* (PIPE) Architecture PCI Express 2.0
• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 3.0
2.7.2.1. Gen1/Gen2 Features
In a PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status signals between the PHY-MAC layer and the transceiver channel
PCS and PMA blocks. The PIPE configuration is based on the PIPE 2.0 specification. If you use a PIPE configuration, you must implement the PHY-MAC layer using soft IP in the FPGA fabric.
2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
In a PIPE configuration, Native PHY IP Core provides an input signal pipe_rate
[1:0]
that is functionally equivalent to the RATE signal specified in the PCIe specification. A change in value from 2'b00 to 2'b01 on this input signal pipe_rate
[1:0]
initiates a data rate switch from Gen1 to Gen2. A change in value from 2'b01 to 2'b00 on the input signal initiates a data rate switch from Gen2 to Gen1.
2.7.2.1.2. Transmitter Electrical Idle Generation
The PIPE interface block in Arria 10 devices puts the transmitter buffer in an electrical idle state when the electrical idle input signal is asserted. During electrical idle, the transmitter buffer differential and common mode output voltage levels are compliant with the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data rates.
The PCIe specification requires the transmitter driver to be in electrical idle in certain power states.
Note: For more information about input signal levels required in different power states, refer to Power State Management in the next section.
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2.7.2.1.3. Power State Management
Table 182.
Power States Defined in the PCIe Specification
To minimize power consumption, the physical layer device must support the following power states.
Power States
P0
Description
Normal operating state during which packet data is transferred on the PCIe link.
P0s, P1, and P2 The PHY-MAC layer directs the physical layer to transition into these low-power states.
The PIPE interface in Arria 10 transceivers provides a pipe_powerdown each transceiver channel configured in a PIPE configuration.
input port for
The PCIe specification requires the physical layer device to implement power-saving measures when the P0 power state transitions to the low power states. Arria 10 transceivers do not implement these power-saving measures except for putting the transmitter buffer in electrical idle mode in the lower power states.
2.7.2.1.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and
Status State Machine (LTSSM) enters the Polling.Compliance substate. The
Polling.Compliance substate assesses if the transmitter is electrically compliant with the PCIe voltage and timing specifications.
2.7.2.1.5. Receiver Status
The PCIe specification requires the PHY to encode the receiver status on a 3-bit status signal pipe_rx_status[2:0]
. This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives status signals from the transceiver channel PCS and PMA blocks, and encodes the status on the pipe_rx_status[2:0] signal to the FPGA fabric. The encoding of the status signals on the pipe_rx_status[2:0]
signal conforms to the PCIe specification.
2.7.2.1.6. Receiver Detection
The PIPE interface block in Arria 10 transceivers provides an input signal pipe_tx_detectrx_loopback
for the receiver detect operation. The PCIe protocol requires this signal to be high during the Detect state of the LTSSM. When the pipe_tx_detectrx_loopback
signal is asserted in the P1 power state, the PIPE interface block sends a command signal to the transmitter driver in that channel to initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must always be in the electrical idle state. After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. The time constant of the step voltage on the trace increases if an active receiver that complies with the PCIe input impedance requirements is present at the far end. The receiver detect circuitry monitors this time constant to determine if a receiver is present.
Note: For the receiver detect circuitry to function reliably, the transceiver on-chip termination must be used. Also, the AC-coupling capacitor on the serial link and the receiver termination values used in your system must be compliant with the PCIe Base
Specification 2.0.
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The PIPE core provides a 1-bit PHY status signal pipe_phy_status
and a 3-bit receiver status signal pipe_rx_status[2:0]
to indicate whether a receiver is detected, as per the PIPE 2.0 specifications.
2.7.2.1.7. Gen1 and Gen2 Clock Compensation
In compliance with the PIPE specification, Arria 10 receiver channels have a rate match FIFO to compensate for small clock frequency differences up to ±300 ppm between the upstream transmitter and the local receiver clocks.
Consider the following guidelines for PIPE clock compensation:
• Insert or delete one SKP symbol in an SKP ordered set.
• Minimum limit is imposed on the number of SKP symbols in SKP ordered set after deletion. An ordered set may have an empty COM case after deletion.
• Maximum limit is imposed on the number of the SKP symbols in the SKP ordered set after insertion. An ordered set may have more than five symbols after insertion.
• For INSERT/DELETE cases: The flag status appears on the COM symbol of the SKP ordered set where insertion or deletion occurs.
• For FULL/EMPTY cases: The flag status appears where the character is inserted or deleted.
Note: When the PIPE interface is on, it translates the value of the flag to the appropriate pipe_rx_status
signal.
• The PIPE mode also has a “0 ppm” configuration option that you can use in synchronous systems. The Rate Match FIFO Block is not expected to do any clock compensation in this configuration, but latency is minimized.
Figure 92.
Rate Match Deletion
This figure shows an example of rate match deletion in the case where two /K28.0/ SKP symbols must be deleted. Only one /K28.0/ SKP symbol is deleted per SKP ordered set received.
SKP Symbol
Deleted
First SKP Ordered Set Second SKP Ordered Set
K28.0
Dx.y
rmfifo_input_data rx_parallel_data pipe_rx_status[2:0]
K28.5
K28.5
3’b010
K28.0
Dx.y
xxx
Dx.y
K28.5
3’b010
K28.5
K28.0
xxx
K28.0
K28.0
xxx
K28.0
Dx.y
xxx
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Figure 93.
Rate Match Insertion
The figure below shows an example of rate match insertion in the case where two SKP symbols must be inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received.
First SKP Ordered Set Second SKP Ordered Set rmfifo_input_data rx_parallel_data pipe_rx_status[2:0]
K28.5
K28.5
3’b001
K28.0
K28.0
xxx
Dx.y
K28.0
xxx
K28.5
Dx.y
xxx
K28.0
K28.5
3’b001
K28.0
K28.0
xxx
K28.0
K28.0
xxx
K28.0
K28.0
xxx
K28.0
xxx
K28.0
xxx
SKP Symbol Inserted
Figure 94.
Rate Match FIFO Full
The rate match FIFO in PIPE mode automatically deletes the data byte that causes the FIFO to go full and drives pipe_rx_status[2:0]
= 3'b101 synchronous to the subsequent data byte. The figure below shows the rate match FIFO full condition in PIPE mode. The rate match FIFO becomes full after receiving data byte
D4.
tx_parallel_data D1 D2 D3 D4 D5 D6 D7 D8 rx_parallel_data D1 D2 D3 D4 D6 D7 D8 xx xx xx pipe_rx_status[2:0] xxx xxx xxx xxx 3’b101 xxx xxx xxx
Figure 95.
Rate Match FIFO Empty
The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to become empty and drives pipe_rx_status[2:0]
= 3'b110 synchronous to the inserted /K30.7/ (9'h1FE). The figure below shows rate match FIFO empty condition in PIPE mode. The rate match FIFO becomes empty after reading out data byte D3.
tx_parallel_data D1 D2 D3 D4
D5
D6 rx_parallel_data D1 D2 D3 /K.30.7/ D4 D5 pipe_rx_status[2:0] xxx xxx xxx 3’b110 xxx xxx
PIPE 0 ppm
The PIPE mode also has a "0 ppm" configuration option that can be used in synchronous systems. The Rate Match FIFO Block is not expected to do any clock compensation in this configuration, but latency is minimized.
2.7.2.1.8. PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in a PCIe functional configuration for
Gen1, Gen2, and Gen3 data rates. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. The data is then looped back to the transmitter serializer and transmitted out through the transmitter buffer. The received data is also available to the FPGA fabric through the rx_parallel_data
port. This loopback mode is based on PCIe specification 2.0.
Arria 10 devices provide an input signal this loopback mode.
pipe_tx_detectrx_loopback
to enable
Note: This is the only loopback option supported in PIPE configurations.
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Figure 96.
PCIe Reverse Parallel Loopback Mode Datapath
Transmitter PMA Transmitter Standard PCS FPGA
Fabric
Reverse Parallel
Loopback Path
PRBS
Generator
Receiver PMA Receiver Standard PCS
PRBS
Verifier
Related Information
•
Arria 10 Standard PCS Architecture
on page 479
• Intel PHY Interface for the PCI Express* (PIPE) Architecture PCI Express 2.0
2.7.2.2. Gen3 Features
The following subsections describes the Arria 10 transceiver block support for PIPE
Gen3 features.
The PCS supports the PIPE 3.0 base specification. The 32-bit wide PIPE 3.0-based interface controls PHY functions such as transmission of electrical idle, receiver detection, and speed negotiation and control.
2.7.2.2.1. Auto-Speed Negotiation
PIPE Gen3 mode enables ASN between Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3
(8.0 Gbps) signaling data rates. The signaling rate switch is accomplished through frequency scaling and configuration of the PMA and PCS blocks using a fixed 32-bit wide PIPE 3.0-based interface.
The PMA switches clocks between Gen1, Gen2, and Gen3 data rates. For a non bonded x1 channel, an ASN module facilitates speed negotiation in that channel. For bonded x2, x4, x8 and x16 channels, the ASN module selects the master channel to control the rate switch. The master channel distributes the speed change request to the other
PMA and PCS channels.
The PCIe Gen3 speed negotiation process is initiated when Hard IP or the FPGA fabric requests a rate change. The ASN then places the PCS in reset, and dynamically shuts down the clock paths to disengage the current active state PCS (either Standard PCS or Gen3 PCS). If a switch to or from Gen3 is requested, the ASN automatically selects the correct PCS clock paths and datapath selection in the multiplexers. The ASN block then sends a request to the PMA block to switch the data rate, and waits for a rate change done signal for confirmation. When the PMA completes the rate change and sends confirmation to the ASN block, the ASN enables the clock paths to engage the new PCS block and releases the PCS reset. Assertion of the pipe_phy_status
signal by the ASN block indicates the successful completion of this process.
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Note: In Native PHY IP core - PIPE configuration, you must set pipe_rate[1:0] to initiate the transceiver datarate switch sequence.
2.7.2.2.2. Rate Switch
This section provides an overview of auto rate change between PIPE Gen1 (2.5 Gbps),
Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) modes.
In Arria 10 devices, there is one ASN block common to the Standard PCS and Gen3
PCS, located in the PMA PCS interface that handles all PIPE speed changes. The PIPE interface clock rate is adjusted to match the data throughput when a rate switch is requested.
Table 183.
PIPE Gen3 32 bit PCS Clock Rates
PCIe Gen3 Capability Mode
Enabled
Lane data rate
PCS clock frequency
FPGA fabric IP clock frequency
PIPE interface width pipe_rate [1:0]
2.5 Gbps
250 MHz
62.5 MHz
32-bit
2'b00
Gen1
5 Gbps
500 MHz
125 MHz
32-bit
2'b01
Gen2
8 Gbps
250 MHz
250 MHz
32-bit
2'b10
Gen3
Figure 97.
Rate Switch Change
The block-level diagram below shows a high level connectivity between ASN and Standard PCS and Gen3 PCS.
Control Plane
Bonding Up pipe_rate[1:0] from FPGA Fabric
Standard PCS PCS/PMA INF
Gen3 ASN
(Gen1, Gen2, Gen3)
Gen3 PCS pipe_sw pipe_sw_done
PMA
PHYSTATUS
GEN
PHYSTATUS
GEN pipe_phy_status pll_pcie_clk
TX
FIFO
/2
(for Gen1 Only)
Control Plane
Bonding Down
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The sequence of speed change between Gen1, Gen2, and Gen3 occurs as follows:
1. The PHY-MAC layer implemented in FPGA fabric requests a rate change through pipe_rate[1:0]
.
2. The ASN block waits for the TX FIFO to flush out data. Then the ASN block asserts the PCS reset.
3. The ASN asserts the clock shutdown signal to the Standard PCS and Gen3 PCS to dynamically shut down the clock.
4. When the rate changes to or from the Gen3 speed, the ASN asserts the clock and data multiplexer selection signals.
5. The ASN uses a pipe_sw[1:0]
output signal to send a rate change request to the PMA.
6. The ASN continuously monitors the
PMA.
pipe_sw_done[1:0]
input signal from the
7. After the ASN receives the pipe_sw_done[1:0]
signal, it deasserts the clock shut down signals to release the clock.
8. The ASN deasserts the PCS reset.
9. The ASN sends the speed change completion to the PHY-MAC interface. This is done through the pipe_phy_status
signal to PHY-MAC interface.
Figure 98.
Speed Change Sequence pipe_tx_elecidle pipe_rate[1:0] pipe_sw[1:0] pipe_sw_done[1:0] pipe_phy_status
00
00
00
10
10
10
2.7.2.2.3. Gen3 Transmitter Electrical Idle Generation
In the PIPE 3.0-based interface, you can place the transmitter in electrical idle during low power states. Before the transmitter enters electrical idle, you must send the
Electrical Idle ordered set, consisting of 16 symbols with value 0x66. During electrical idle, the transmitter differential and common mode voltage levels are based on the
PCIe Base Specification 3.0.
2.7.2.2.4. Gen3 Clock Compensation
Enable this mode from the Parameter Editor when using the Gen3 PIPE transceiver configuration rule.
To accommodate PCIe protocol requirements and to compensate for clock frequency differences of up to ±300 ppm between source and termination equipment, receiver channels have a rate match FIFO. The rate match FIFO adds or deletes four SKP characters (32 bits) to keep the FIFO from becoming empty or full. If the rate match
FIFO is almost full, the FIFO deletes four SKP characters. If the rate match FIFO is nearly empty, the FIFO inserts a SKP character at the start of the next available SKP ordered set. The and deletion.
pipe_rx_status [2:0]
signal indicates FIFO full, empty, insertion
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Note: Refer to the Gen1 and Gen2 Clock Compensation section for waveforms.
Related Information
Gen1 and Gen2 Clock Compensation on page 234
2.7.2.2.5. Gen3 Power State Management
The PCIe base specification defines low power states for PHY layer devices to minimize power consumption. The Gen3 PCS does not implement these power saving measures, except when placing the transmitter driver in electrical idle in the low power state. In the P2 low power state, the transceivers do not disable the PIPE block clock.
Figure 99.
P1 to P0 Transition
The figure below shows the transition from P1 to P0 with completion provided by pipe_phy_status
.
tx_coreclkin pipe_powerdown pipe_phy_status
P1 P0
2.7.2.2.6. CDR Control
The CDR control block performs the following functions:
• Controls the PMA CDR to obtain bit and symbol alignment
• Controls the PMA CDR to deskew within the allocated time
• Generates status signals for other PCS blocks
The PCIe base specification requires that the receiver L0s power state exit time be a maximum of 4 ms for Gen1, 2 ms for Gen2, and 4 ms for Gen3 signaling rates. The transceivers have an improved CDR control block to accommodate fast lock times.
Fast lock times are necessary for the CDR to relock to the new multiplier/divider settings when entering or exiting Gen3 speeds.
2.7.2.2.7. Gearbox
As per the PIPE 3.0 specification, for every 128 bits that are moved across the Gen3
PCS, the PHY must transmit 130 bits of data. Intel uses the pipe_tx_data_valid signal every 16 blocks of data to transmit the built-up backlog of 32 bits of data.
The 130-bit block is received as follows in the 32-bit data path: 34 (32+2-bit sync header), 32, 32, 32. During the first cycle, the gearbox converts the 34-bit input data to 32-bit data. During the next three clock cycles, the gearbox merges bits from adjacent cycles. For the gearbox to work correctly, a gap must be provided in the data for every 16 shifts because each shift contains two extra bits for converting the initial
34 bits to 32 bits in the gearbox. After 16 shifts, the gearbox has an extra 32 bits of data that are transmitted out. This requires a gap in the input data stream, which is achieved by driving pipe_tx_data_valid
low for one cycle after every 16 blocks of data.
Figure 100. Gen3 Data Transmission tx_coreclkin pipe_tx_sync_hdr pipe_tx_blk_start pipe_tx_data_valid
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2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes
Figure 101. Use ATX PLL or fPLL for Gen1/Gen2 x1 Mode
X1 Network
6
CGB
Ch 5 fPLL1
ATX PLL1
6
CGB
CDR
Ch 4
Master
CGB1
4
6
CGB
CDR
Ch 3
Path for Clocking in
Gen1/Gen2 x1 Mode fPLL0
6
CGB
CDR
Ch 2
Master
CGB0
4
6
CGB
CDR
Ch 1
ATX PLL0
6
CGB
CDR
Ch 0
Path for Clocking in
Gen1/Gen2 x1 Mode
CDR
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x1 mode.
2. Gen1/Gen2 x1 mode uses the ATX PLL or fPLL.
3. Gen1/Gen2 x1 can use any channel from the given bank for which the ATX PLL or fPLL is enabled.
4. Use the pll_pcie_clk from either the ATX PLL or fPLL. This is the hclk required by the PIPE interface.
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Figure 102. Use ATX PLL or fPLL for Gen1/Gen2 x4 Mode
XN
Network
X6
Network fPLL1
ATX PLL1
Connections Done via X1 Network
Master
CGB
Master
CGB
6 6
6
6
6
6
CGB
CGB
CGB
CGB
CGB
CGB
CDR
Ch 3
CDR
Ch 2
Ch 5
CDR
Ch 4
CDR
Ch 1
CDR
Ch 0
CDR
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x4 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines.
4. Gen1/Gen2 x4 modes use the ATX PLL or fPLL only.
5. Use the pll_pcie_clk from either the ATX or fPLL. This is the hclk required by the PIPE interface.
6.
In this case the Master PCS channel is logical channel 3 (physical channel 4).
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Figure 103. Use ATX PLL or fPLL for Gen1/Gen2 x8 Mode
Use Any
One PLL fPLL1
ATX PLL1
Master
CGB
Connections Done via X1 Network
Master
CGB
6 6
6
6
6
6
CGB
CGB
Master
CGB
6
Notes:
1. Figure shown is just one possible combination for the PCIe Gen1/Gen2 x8 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines. The x6 lines further drive the xN lines.
4. Gen1/Gen2 x8 mode uses the ATX PLL or fPLL only.
5. Use the pll_pcie_clk from either the ATX or fPLL. This is the hclk required by the PIPE interface.
6. In this case the Master PCS channel is logical channel 4 (Ch 1 in the top bank).
CGB
CGB
CGB
CGB
CGB
CGB
Ch 5
CDR
Ch 4
CDR
Ch 3
CDR
Ch 2
Transceiver bank
CDR
Ch 1
CDR
Ch 0
CDR
Ch 5
CDR
Ch 4
CDR
Transceiver bank
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Figure 104. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x1 Mode
X1 Network
6
CGB fPLL1
ATX PLL1
6
CGB
Ch 5
CDR
Ch 4
Master
CGB1
4
CDR
Ch 3
6
CGB
CDR
Ch 2
6
CGB fPLL0
Master
CGB0
4
CDR
Ch 1
6
CGB
ATX PLL0
CDR
Ch 0
6
CGB
CDR
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x1 mode.
2. Gen1/Gen2 modes use the fPLL only.
3. Gen3 mode uses the ATX PLL only.
4. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
5. Select the number of TX PLLs (2) in the Native PHY IP core wizard.
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Figure 105. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x4 Mode
XN
Network
X6
Network fPLL1
ATX PLL1
Connections Done via X1 Network
Master
CGB
Master
CGB
6 6
6
6
6
6
CGB
CGB
CGB
CGB
CGB
CGB
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x4 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines.
4. Gen1/Gen2 modes use the fPLL only.
5. Gen3 mode uses the ATX PLL only.
6. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
CDR
Ch 1
CDR
Ch 0
CDR
CDR
Ch 3
CDR
Ch 2
Ch 5
CDR
Ch 4
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Figure 106. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x8 Mode
Master
CGB fPLL1
ATX PLL1
Connections Done via X1 Network
Master
CGB
6 6
6
6
6
6
CGB
CGB
CGB
CGB
CGB
CGB
Ch 5
CDR
Ch 4
CDR
Ch 3
CDR
Ch 2
Transceiver bank
CDR
Ch 1
CDR
Ch 0
CDR
Ch 5
CGB
CDR
Ch 4
CGB
Master
CGB
6
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x8 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines. The x6 lines further drive the xN lines.
4. Gen1/Gen2 x8 modes use the fPLL only.
5. Gen3 mode uses the ATX PLL only.
6. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
CDR
Transceiver bank
Related Information
•
on page 398
For more information about implementing clock configurations and configuring
PLLs.
• PIPE Design Example
For more information about the PLL configuration for PCIe.
•
Transmit PLL recommendation based on Data rates
on page 349
For more information about ATX PLL placement restrictions
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2.7.4. How to Implement PCI Express (PIPE) in Arria 10 Transceivers
You must be familiar with the Standard PCS architecture, Gen3 PCS architecture, PLL architecture, and the reset controller before implementing the PCI Express protocol.
1. Go to the IP Catalog and select the Arria 10 Transceiver Native PHY IP Core.
Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
2. Select Gen1/Gen2/Gen3 PIPE from the Arria 10 Transceiver configuration
rules list, located under Datapath Options.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
PCI Express Transceiver Configurations Rules as a starting point. Alternatively, you
can use Arria 10 Transceiver Native PHY Presets . You can then modify the settings to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the
information in Transceiver Native PHY IP Ports for PCI Express Transceiver
Configuration Rules to connect the ports.
8. Simulate your design to verify its functionality.
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Figure 107. Connection Guidelines for a PIPE Gen3 Design
pll_refclk
ATX PLL and Master
CGB (Gen3) tx_bonding_clocks mcgb_aux_clk fPLL
(Gen1/Gen2) pll_pcie_clk tx_serial_clk
Arria 10
Transceiver
Native PHY tx_bonding_clocks pipe_hclk_in
(1)
Reset Controller (2) clock reset
Notes:
(1). If you enable the input pll_cal_busy port in the Transceiver PHY Reset Controller, you can connect the pll_cal_busy output signals from the PLLs directly to the input port on the reset-controller without ORing the tx_cal_busy and pll_cal_busy signals.
(2).
a. If you are using the Transceiver PHY Reset Controller, you must configure the TX digital reset mode and RX digital reset mode to Manual to avoid resetting the Auto Speed
Negotiation (ASN) block which handles the rate switch whenever the channel PCS is reset.
b. When the TX digitalreset is in Auto mode, the associated tx_digitalreset controller automatically resets whenever the pll_locked signal is deasserted. When in Manual mode, the associated tx_digitalreset controller is not reset when the pll_locked signal is deasserted, allowing the user to choose what to do.
c. When the RX digitalreset is in Auto mode, the associated rx_digitalreset controller automatically resets whenever the rx_is_lockedtodata signal is deasserted. When in
Manual mode, the associated rx_digitalreset controller is not reset when the rx_is_lockedtodata signal is deasserted, allowing the user to choose what to do.
d. If the resets are configured to Auto mode for PIPE designs, then the digital reset will get asserted automatically when the lock signal is deasserted.
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Recommendations:
Intel recommends that you not reset the PLL and channels (TX and RX) when using the PIPE mode of Native PHY. This is to avoid resetting the Auto Speed Negotiation
(ASN) block in the PCS.
Related Information
•
For information about PLL architecture and implementation details.
•
Arria 10 Standard PCS Architecture
on page 479
•
Resetting Transceiver Channels
on page 416
For information about the Reset controller and implementation details.
2.7.5. Native PHY IP Parameter Settings for PIPE
Table 184.
Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE
Parameter
Message level for rule violations
Common PMA Options
VCCR_GXB and VCCT_GXB supply voltage for the
Transceiver
Transceiver link type
Datapath Options
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Provide separate interface for each channel
Error
Gen1: 1_1V, 1_0V, 0_9V
Gen1: sr,lr
Gen1 PIPE
Basic
TX / RX Duplex
Gen1 x1: 1 channel
Gen1 x2: 2 channels
Gen1 x4: 4 channels
Gen1 x8: 8 channels
2.5 Gbps
Optional
Optional (
Optional
Error
Gen2: 1_1V, 1_0V, 0_9V
Gen2: sr,lr
Gen2 PIPE
Basic
TX / RX Duplex
Gen2 x1: 1 channel
Gen2 x2: 2 channels
Gen2 x4: 4 channels
Gen2 x8: 8 channels
5 Gbps
Optional
Optional
)
Optional
Error
Gen3: 1_1V, 1_0V, 0_9V
Gen3: sr,lr
Gen3 PIPE
Basic
TX / RX Duplex
Gen3 x1: 1 channel
Gen3 x2: 2 channels
Gen3 x4: 4 channels
Gen3 x8: 8 channels
5 Gbps (39)
Optional
Optional
)
Optional
(39) The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for 8 Gbps.
(40) Refer to
Table 191 on page 263 for bit settings when simplified data interface is enabled.
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Table 185.
Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX
PMA
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE
TX Bonding Options
TX channel bonding mode
PCS TX channel bonding master
Default PCS TX channel bonding master
Nonbonded (x1)
PMA & PCS Bonding
Auto (
Gen1 x1: 0
Gen1 x2: 1
Gen1 x4: 2
Gen1 x8: 4
Nonbonded (x1)
PMA & PCS Bonding
Auto
)
Gen1 x1: 0
Gen1 x2: 1
Gen1 x4: 2
Gen1 x8: 4
Nonbonded (x1)
PMA & PCS Bonding
Auto (
Gen1 x1: 0
Gen1 x2: 1
Gen1 x4: 2
Gen1 x8: 4
TX PLL Options
TX local clock division factor 1 1
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
1
0
1
0
1
Gen3 x1: 2
All other modes: 1
Gen1 / Gen2 clock connection should be used for Initial clock input selection in
Gen3x1
All other modes: 0
TX PMA Optional Ports
Enable tx_analog_reset_ack port
Enable tx_pma_clkout
port
Enable tx_pma_div_clkout port tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Enable tx_pma_qpipulldn port (QPI)
Enable tx_pma_txdetectrx port (QPI)
Enable tx_pma_rxfound
port (QPI)
Enable rx_seriallpbken
port
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
(41) Setting this parameter is placement-dependent. In AUTO mode, the Native PHY IP Parameter
Editor selects the middle-most channel of the configuration as the default PCS TX channel bonding master. You must ensure that this selected channel is physically placed as Ch1 or Ch4 of the transceiver bank. Else, use the manual selection for the PCS TX channel bonding master to select a channel that can be physically placed as Ch1 or Ch4 of the transceiver bank. Refer to section How to place channels for PIPE configurations for more details.
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Table 186.
Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX
PMA
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE
RX CDR Options
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
Equalization
CTLE adaptation mode
1
0
100, 125 MHz
1000
1
0
100, 125 MHz
1000
1
0
100, 125 MHz
1000
Manual / Triggered Manual / Triggered Manual / Triggered
DFE adaptation mode
Number of fixed dfe taps
RX PMA Optional Ports
Enable rx_analog_reset_ack
port
Enable rx_pma_clkout
port
Enable rx_pma_div_clkout port rx_pma_div_clkout division factor
Enable rx_pma_clkslip
port
Enable rx_pma_qpipulldn port (QPI)
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata
and rx_set_locktoref
ports
Enable rx_seriallpbken
port
Enable PRBS Verifier Control and Status ports
Disabled
NA
Optional
Optional
Optional
Optional
Optional
Off
Optional
Optional
Optional
Optional
Optional
Disabled
NA
Optional
Optional
Optional
Optional
Optional
Off
Optional
Optional
Optional
Optional
Optional
Disabled
NA
Table 187.
Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes -
Standard PCS
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE Parameter
Standard PCS configurations
Standard PCS / PMA interface width 10 10 10 (42) continued...
Optional
Optional
Optional
Optional
Optional
Off
Optional
Optional
Optional
Optional
Optional
(42) The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for PCS/PMA width of 32.
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Parameter
FPGA Fabric / Standard TX PCS interface width
FPGA Fabric / Standard RX PCS interface width
Enable Standard PCS low latency mode
Standard PCS FIFO
TX FIFO mode
RX FIFO mode
Enable tx_std_pcfifo_full
port
Enable tx_std_pcfifo_empty
port
Enable rx_std_pcfifo_full
port
Enable rx_std_pcfifo_empty
port
Byte Serializer and Deserializer
TX byte serializer mode
RX byte deserializer mode
8B/10B Encoder and Decoder
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
Rate Match FIFO
Rate Match FIFO mode
RX rate match insert / delete -ve pattern
(hex)
RX rate match insert / delete +ve pattern (hex)
Enable rx_std_rmfifo_full
port
Enable rx_std_rmfifo_empty
port
PCI Express Gen 3 rate match FIFO mode
Word Aligner and Bit Slip
Enable TX bit slip
Enable port tx_std_bitslipboundarysel
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Gen1 PIPE
8, 16
8, 16
Off low_latency low_latency
Optional
Optional
Optional
Optional
Disabled, Serialize x2
Disabled, Serialize x2
Enabled
Enabled
Enabled
PIPE, PIPE 0ppm
0x0002f17c (K28.5/
K28.0/)
0x000d0e83 (K28.5/
K28.0/)
Optional
Optional
Bypass
Off
Optional
Synchronous State
Machine
10
0x0000 00000000017c (/
K28.5/)
Gen2 PIPE
16
16
Off low_latency low_latency
Optional
Optional
Optional
Optional
Serialize x2
Serialize x2
Enabled
Enabled
Enabled
PIPE, PIPE 0ppm
0x0002f17c (K28.5/
K28.0/)
0x000d0e83 (K28.5/
K28.0/)
Optional
Optional
Bypass
Off
Optional
Synchronous State
Machine
10
0x0000 00000000017c (/
K28.5/)
Gen3 PIPE
32
32
Off low_latency low_latency
Optional
Optional
Optional
Optional
Serialize x4
Deserialize x4
Enabled
Enabled
Enabled
PIPE, PIPE 0ppm
0x0002f17c (K28.5/
K28.0/)
0x000d0e83
(K28.5/K28.0/)
Optional
Optional
600
Off
Optional
Synchronous State
Machine
10
0x0000
00000000017c(/
K28.5/) continued...
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Parameter
Number of word alignment patterns to achieve sync
Number of invalid data words to lose sync
Number of valid data words to decrement error count
Enable rx_std_wa_patternalign
port
Enable rx_std_wa_a1a2size
port
Enable port rx_std_bitslipboundarysel
Enable rx_bitslip
port
Bit Reversal and Polarity Inversion
Enable TX bit reversal
Enable TX byte reversal
Enable TX polarity inversion
Enable tx_polinv
port
Enable RX bit reversal
Enable rx_std_bitrev_ena
port
Enable RX byte reversal
Enable rx_std_byterev_ena
port
Enable RX polarity inversion
Enable rx_polinv
port
Enable rx_std_signaldetect
port
PCIe Ports
Enable PCIe dynamic datarate switch ports
Enable PCIe pipe_hclk_in
and pipe_hclk_out
ports
Enable PCIe Gen3 analog control ports
Enable PCIe electrical idle control and status ports
Enable PCIe pipe_rx_polarity
port
Dynamic reconfiguration
Enable dynamic reconfiguration
Note:
Gen1 PIPE
3
16
15
Optional
Off
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Optional
Off
Enabled
Off
Enabled
Enabled
Disabled
Gen2 PIPE
3
16
15
Optional
Off
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Optional
Enabled
Enabled
Off
Enabled
Enabled
Disabled
Gen3 PIPE
3
16
15
Optional
Off
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Optional
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
The signals in the left-most column are automatically mapped to a subset of a 128-bit tx_parallel_data
word when the Simplified Interface is enabled.
Related Information
•
How to Place Channels for PIPE Configurations
on page 268
•
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
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•
Bit Mappings When the Simplified Interface Is Disabled on page 263
2.7.6. fPLL IP Parameter Core Settings for PIPE
Table 188.
Parameter Settings for Arria 10 fPLL IP core in PIPE Gen1, Gen2, Gen3 modes
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen1/
Gen2 speeds)
PLL
General fPLL mode
Protocol Mode
Message level for rule violation
Number of PLL reference clocks
Selected reference clock source
Enable fractional mode
Enable manual counter configuration
Enable ATX to fPLL cascade clock input port
Settings
Bandwidth
Feedback
Operation mode
Output frequency
Transceiver
PCIe Gen 1
Error
1
0
Disable
Disable
Disable
Low, Medium, High
Direct
Transceiver usage
PLL output frequency
PLL datarate
PLL integer reference clock frequency
250oMHz
2500Mbps
100 MHz, 125 MHZ
Master Clock Generation Block (MCGB)
Include master clock generation block
Clock division factor
Disable for x1
Enable for x2, x4, x8
N/A for x1
1 for x2, x4, x8
Enable x6/xN non-bonded high-speed clock output port
Enable PCIe clock switch interface
N/A for x1
Disable for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
Transceiver
PCIe Gen 2
Error
1
0
Disable
Disable
Disable
Low, Medium, High
Direct
2500MHz
5000Mbps
100 MHz, 125 MHZ
Disable for x1
Enable for x2, x4, x8
N/A for x1
1 for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
Transceiver
PCIe Gen 2
Error
1
0
Disable
Disable
Disable
Low, Medium, High
Direct
2500MHz
5000Mbps
100 MHz, 125 MHZ
Disable for x1
Disable for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
N/A for x1
N/A for x2,x4, x8
N/A for x1
N/A for x2, x4, x8 continued...
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Parameter Gen1 PIPE Gen2 PIPE
Number of auxiliary MCGB clock input ports
MCGB input clock frequency
MCGB output data rate
Bonding
Enable bonding clock output ports
Enable feedback compensation bonding
PMA interface width
N/A for x1
0 for x2, x4, x8
1250MHz
2500Mbps
N/A for x1 design
Enable for x2, x4, x8
N/A for x1 design
Disable for x2, x4, x8
N/A for x1 design
10 for x2, x4, x8
Dynamic Reconfiguration
Enable dynamic reconfiguration
Enable Altera Debug Master
Endpoint
Separate avmm_busy from reconfig_waitrequest
Disable
Disable
N/A
Optional Reconfiguration Logic
Enable capability registers N/A
Set user-defined IP identifier N/A
Enable control and status registers
N/A
Configuration Files
Configuration file prefix
Generate SystemVerilog package file
Generate C Header file
Generate MIF (Memory
Initialize file)
Generation Options
Generate parameter documentation file
N/A
N/A
N/A
N/A
Enable
N/A for x1
0 for x2, x4, x8
2500MHz
5000Mbps
N/A for x1 design
Enable for x2, x4, x8
N/A for x1 design
Disable for x2, x4, x8
N/A for x1 design
10 for x2, x4, x8
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
Gen3 PIPE (For Gen1/
Gen2 speeds)
N/A for x1
N/A for x2, x4, x8
2500MHz
5000Mbps
N/A for x1
N/A for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable
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2.7.7. ATX PLL IP Parameter Core Settings for PIPE
Table 189.
Parameters for Arria 10 ATX PLL IP core in PIPE Gen1, Gen2, Gen3 modes
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen3 speed)
PLL
General
Message level for rule violations
Protocol Mode
Bandwidth
Number of PLL reference clocks
Selected reference clock source
Ports
Primary PLL clock output buffer
Enable PLL GX clock output port
Enable PLL GT clock output port
Enable PCIe clock output port pll_pcie_clk
Error
PCIe Gen 1
Low, medium, high
1
0
Error
PCIe Gen 2
Low, medium, high
1
0
Error
PCIe Gen 3
Low, medium, high
1
0
GX clock output buffer GX clock output buffer GX clock output buffer
Enable Enable Enable
Disable
Enable
Disable
Disable
Enable
Disable
Disable
Disable (Use the pll_pcie_clk
output port from the fPLL to drive the hclk)
Disable Enable ATX to fPLL cascade clock output port
Output Frequency
PLL output frequency
PLL output datarate
Enable fractional mode
PLL integer reference clock frequency
Configure counters manually
Multiple factor (M counter)
Divide factor (N counter)
Divide factor (L counter)
Master Clock Generation Block
MCGB
Include master clock generation block
Clock division factor
Enable x6/xN non-bnded high speed clock output port
Enable PCIe clock switch interface
2500MHz
2500Mbps
Disable
100MHz, 125MHZ
Disable
N/A
N/A
N/A
Disable for x1
Enable for x2, x4, x8
N/A for x1
1 for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
2500MHz
5000Mbps
Disable
100MHz, 125MHZ
Disable
N/A
N/A
N/A
Disable for x1
Enable for x2, x4, x8
N/A for x1
1 for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
4000MHz
8000Mbps
Disable
100MHz, 125MHZ
Disable
N/A
N/A
N/A
Disable for x1
Enable for x2, x4, x8
N/A for x1
1 for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8 continued...
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Parameter
Number of auxiliary MCGB clock input ports
MCGB input clock frequency
MCGB output data rate
Bonding
Enable bonding clock output ports
Gen1 PIPE
N/A for x1
0 for x2, x4, x8
1250 MHz
2500 Mbps
Gen2 PIPE
N/A for x1
0 for x2, x4, x8
2500 MHz
5000 Mbps
Gen3 PIPE (For Gen3 speed)
N/A for x1
1 for x2, x4, x8
4000 MHz
8000 Mbps
Enable feedback compensation bonding
PMA interface width
N/A for x1
Enable for x2, x4, x8
N/A for x1 design
Disable for x2, x4, x8
N/A for x1 design
10 for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
N/A for x1 design
Disable for x2, x4, x8
N/A for x1 design
10 for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
Disable for x1
Disable for x2, x4, x8
N/A for x1
10 for x2, x4, x8
Dynamic Reconfiguration
Enable dynamic reconfiguration
Enable Altera Debug Master Endpoint
Separate avmm_busy from reconfig_waitrequest
Optional Reconfiguration Logic
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Configuration Files
Configuration file prefix
Generate SystemVerilog package file
Generate C Header file
Generate MIF (Memory Initialize file)
Generation Options
Generate parameter documentation file
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable Enable
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable
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2.7.8. Native PHY IP Ports for PIPE
Figure 108. Signals and Ports of Native PHY IP for PIPE reconfig_reset reconfig_clk reconfig_avmm tx_digitalreset tx_datak [3:0], [1:0], or [0] tx_parallel_data [31:0], [15:0], or [7:0] tx_coreclkin tx_clkout pipe_rx_elecidle [(N-1):0] pipe_phy_status [(N-1):0] pipe_rx_data_valid [(N-1):0] pipe_rx_sync_hdr [(2N-1):0] pipe_rx_blk_start [(N-1):0] pipe_rate [1:0] pipe_g3_tx_deemph [(18N-1):0] pipe_g3_rxpresethint [(3N-1):0] pipe_sw_done [1:0] pipe_rx_polarity [(N-1):0] pipe_tx_elecidle [(4N-1):0] pipe_tx_detectrx_loopback [(N-1):0] pipe_powerdown [(2N-1):0] pipe_rx_eidleinfersel [(3N-1):0] pipe_tx_sync_hdr [(2N-1):0] pipe_tx_data_valid [(N-1):0] pipe_tx_blk_start [(N-1):0] pipe_tx_deemph [(N-1):0] tx_bonding_clocks[(6n-1):0] tx_analogreset rx_analogreset rx_digitalreset rx_datak [3:0], [1:0], or [0] rx_parallel_data [31:0], [15:0], or [7:0] rx_clkout rx_coreclkin rx_syncstatus
Reconfiguration
Registers
Arria 10 Transceiver Native PHY
Nios II Hard
Calibration IP
TX PMA TX Standard PCS tx_datak [3:0], [1:0], or [0] tx_parallel_data[31:0],[15:0],or[7:0] tx_coreclkin tx_clkout unused_tx_parallel_data[118:0]
10
Serializer
PIPE Interface
RX Standard PCS rx_datak [3:0], [1:0], or [0] rx_parallel_data[31:0],[15:0],or[7:0] rx_clkout rx_coreclkin rx_syncstatus unused_rx_parallel_data[118:0]
Local CGB
(for X1 Modes Only
-
RX PMA
Deserializer CDR
Gen1/Gen2/Gen3 - Black
Gen2/Gen3 - Red
Note: N is the number of PCIe channels tx_cal_busy rx_cal_busy tx_serial_data pipe_hclk_out [0] pipe_hclk_in [0] (from TX PLL) pipe_tx_compliance [(4N-1):0] pipe_tx_margin [(3N-1):0] pipe_tx_swing [(N-1):0] pipe_rx_valid [(N-1):0] pipe_rx_status [(3N-1):0] pipe_sw [1:0] tx_serial_data rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref
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Table 190.
Ports for Arria 10 Transceiver Native PHY in PIPE Mode
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter settings.
Port rx_cdr_refclk0 tx_serial_clk0/ tx_serial_clk1 pipe_hclk_in[0] pipe_hclk_out[0] tx_parallel_data[31:0]
,
[15:0]
, or
[7:0] tx_datak[3:0]
,
[1:0]
, or
[0] pipe_tx_sync_hdr[(2N-1)
:0]
(43)
Direction
In
In
In
Out
Clock Domain
Clocks
Description
N/A
N/A
N/A
The 100/125 MHz input reference clock source for the PHY's TX PLL and RX CDR.
The high speed serial clock generated by the
PLL.
Note: For Gen3 x1 ONLY is used.
tx_serial_clk1
The 500 MHz clock used for the ASN block.
This clock is generated by the PLL, configured for Gen1/Gen2.
Note: For Gen3 designs, use from the fPLL that is used for Gen1/Gen2.
N/A
The 500 MHz clock output provided to the
PHY - MAC interface. The pipe_hclk_out
[0]
port can be left floating when you connect tx_clkout
to the MAC clock input.
PIPE Input from PHY - MAC Layer
In
In
In tx_coreclkin tx_coreclkin tx_coreclkin
The TX parallel data driven from the MAC.
For Gen1 this can be 8 or 16 bits. For Gen2 this is 16 bits. For Gen3 this is 32 bits.
Note: unused_tx_parallel_data be tied to '0'.
should
Active High. Refer to table Bit Mappings when
the Simplified Interface is Disabled for additional details.
The data and control indicator for the transmitted data.
For Gen1 or Gen2, when 0, indicates that tx_parallel_data
is data, when 1, indicates that control.
tx_parallel_data
is
For Gen3, bit[0]
corresponds to tx_parallel_data[7:0]
, bit[1] corresponds to and so on.
tx_parallel_data[15:8]
,
Active High. Refer to table Bit Mappings when
the Simplified Interface is Disabled for additional details.
For Gen3, indicates whether the 130-bit block transmitted is a Data or Control
Ordered Set Block.
The following encodings are defined:
2'b10: Data block
2'b01: Control Ordered Set Block
This value is read when pipe_tx_blk_start = 1b'1
.
continued...
(43) N is the number of PCIe channels.
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Port Direction Clock Domain pipe_tx_blk_start[(N-1)
:0] pipe_tx_elecidle[(4N-1)
:0] pipe_tx_detectrx_loopba ck [(N-1):0] pipe_tx_compliance[(4N-
1):0]
In
In
In
In tx_coreclkin
Asynchronous tx_coreclkin tx_coreclkin
Description
Refer to Lane Level Encoding in the PCI
Express Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding.
Not used for Gen1 and Gen2 data rates.
Active High
For Gen3, specifies the start block byte location for TX data in the 128-bit block data.
Used when the interface between the PCS and PHY-MAC (FPGA Core) is 32 bits.
Not used for Gen1 and Gen2 data rates.
Active High
Forces the transmit output to electrical idle.
Refer to the Intel PHY Interface for PCI
Express (PIPE) for timing diagrams.
Gen1 - Width of signal is 1 bit/lane.
Gen2 - Width of signal is 2 bits/lane. For example, if the MAC connected to PIPE
Gen2x4 has 1bit/lane, then you can use the following mapping to connect to PIPE:
{pipe_tx_elecidle[7:0] =
{{2{tx_elecidle_ch3}},
{2{tx_elecidle_ch2}},{2{tx_elecidle_ch1}},
{2{tx_elecidle_ch0}}} where tx_elecidle_* is the output signal from MAC.
Gen3 - Width of signal is 4 bits/lane. For example, if the MAC connected to PIPE
Gen3x4 has 1bit/lane, then you can use the following mapping to connect to PIPE:
{pipe_tx_elecidle[15:0] =
{{4{tx_elecidle_ch3}},
{4{tx_elecidle_ch2}},{4{tx_elecidle_ch1}},
{4{tx_elecidle_ch0}}} where tx_elecidle_* is the output signal from MAC.
Active High
Instructs the PHY to start a receive detection operation. After power-up, asserting this signal starts a loopback operation. Refer to section 6.4 of the Intel PHY Interface for PCI
Express (PIPE) for a timing diagram.
Active High
Asserted for one cycle to set the running disparity to negative. Used when transmitting the compliance pattern. Refer to section 6.11
of the Intel PHY Interface for PCI Express
(PIPE) Architecture for more information.
Gen1 - Width of signal is 1 bit/lane.
Gen2 - Width of signal is 2 bits/lane.
For example, if the MAC connected to PIPE
Gen2x4 has 1bit/lane, then you can use the following mapping to connect to PIPE:
{pipe_tx_compliance[7:0] =
{{2{tx_compliance_ch3}},
{2{tx_compliance _ch2}},
{2{tx_compliance_ch1}}, {2{tx_compliance
_ch0}}}. Where tx_compliance_* is the output signal from MAC.
Gen3 - Width of signal is 4 bits/lane.
continued...
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Port pipe_rx_polarity[(N-1):
0] pipe_powerdown[(2N-1):
0] pipe_tx_margin[(3N-1):
0] pipe_tx_swing[(N-1):0] pipe_tx_deemph[(N-1):0] pipe_g3_tx_deemph[(18N-
1):0]
Direction
In
In
In
In
In
In
Clock Domain
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Asynchronous tx_coreclkin tx_coreclkin tx_coreclkin
Asynchronous
Asynchronous
Description
For example, if the MAC connected to PIPE
Gen3x4 has 1bit/lane, then you can use the following mapping to connect to PIPE:
{pipe_tx_compliance[15:0]= {{4{tx_ compliance _ch3}}, {4{tx_ compliance
_ch2}}, {4{tx_ compliance _ch1}}, {4{tx_ compliance _ch0}}}. Where tx_ compliance
_* is the output signal from MAC.
Active High
When 1'b1, instructs the PHY layer to invert the polarity on the received data.
Active High
Requests the PHY to change its power state to the specified state. The Power States are encoded as follows:
2'b00: P0 - Normal operation.
2'b01: P0s - Low recovery time, power saving state.
2'b10: P1 - Longer recovery time, lower power state .
2'b11: P2 - Lowest power state.
Transmit V
OD
margin selection. The PHY-MAC sets the value for this signal based on the value from the Link Control 2 Register. The following encodings are defined:
3'b000: Normal operating range
3'b001: Full swing: 800 - 1200 mV; Half swing: 400 - 700 mV.
3'b010:-3'b011: Reserved.
3'b100-3'b111: Full swing: 200 - 400mV;
Half swing: 100 - 200 mV else reserved.
Indicates whether the transceiver is using
Full swing or Half swing voltage as defined by the pipe_tx_margin
.
1'b0-Full swing.
1'b1-Half swing.
Transmit de-emphasis selection. In PCI
Express Gen2 (5 Gbps) mode it selects the transmitter de-emphasis:
1'b0: –6 dB.
1'b1: –3.5 dB.
The pipe_g3_tx_deemph
port is used to select the link partners transmitter deemphasis during equalization. The 18 bits specify the following coefficients:
[5:0]: C
-1
[11:6]: C
0
[17:12]: C
+1
Refer to Preset Mappings to TX De-emphasis
on page 267 for presets to TX de-emphasis mappings. In Gen3 capable designs, the TX de-emphasis for Gen2 data rate is always -6 dB. The TX de-emphasis for Gen1 data rate is always -3.5 dB.
Refer to section 6.6 of Intel PHY Interface for
PCI Express (PIPE) Architecture for more information.
continued...
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Port pipe_g3_rxpresethint[(3
N-1):0] pipe_rx_eidleinfersel[(
3N-1):0] pipe_rate[1:0] pipe_sw_done[1:0] pipe_tx_data_valid[(N-1
):0] rx_parallel_data[31:0]
[15:0]
, or
[7:0]
,
Direction
In
In
In
In
In
Out
Clock Domain
Asynchronous
Asynchronous
Asynchronous
N/A
Description
Note: Intel recommends transmitting Preset
P8 coefficients for Arria 10 receiver to recover data successfully.
This is used to trigger CTLE adaptation in
Phase2 (EP) /Phase 3 (RP) to achieve receiver Bit Error Rate (BER) that is less than
10 -12 .
Gen3 capable design at Gen1/Gen2 speeds:
This should be set to 3’b000.
Gen3 capable design at Gen3 speed: Refer to section “PHY IP Core for PCIe (PIPE) Link
Equalization for Gen3 Data Rate” for details on when to set/reset this port.
When asserted high, the electrical idle state is inferred instead of being identified using analog circuitry to detect a device at the other end of the link. The following encodings are defined:
3'b0xx: Electrical Idle Inference not required in current LTSSM state.
3'b100: Absence of COM/SKP OS in 128 ms.
3'b101: Absence of TS1/TS2 OS in 1280 UI interval for Gen1 or Gen2.
3'b110: Absence of Electrical Idle Exit in
2000 UI interval for Gen1 and 16000 UI interval for Gen2.
3'b111: Absence of Electrical Idle exit in 128 ms window for Gen1.
Note: Recommended to implement Receiver
Electrical Idle Inference (EII) in FPGA fabric.
The 2-bit encodings defined in the following list:
2'b00: Gen1 rate (2.5 Gbps)
2'b01: Gen2 rate (5.0 Gbps)
2'b10: Gen3 rate (8.0 Gbps)
Signal from the Master clock generation buffer, indicating that the rate switch has completed. Use this signal for bonding mode only.
For non-bonded applications, this signal is internally connected to the local CGB.
tx_coreclkin
For Gen3, this signal is deasserted by the
MAC to instruct the PHY to ignore tx_parallel_data
for current clock cycle.
A value of 1'b1 indicates the PHY should use the data. A value of 0 indicates the PHY should not use the data.
Active High
PIPE Output to PHY - MAC Layer rx_coreclkin
The RX parallel data driven to the MAC.
For Gen1 this can be 8 or 16 bits. For Gen2 this is 16 bits only. For Gen3 this is 32 bits.Refer to Bit Mappings When the
Simplified Interface is Disabled for more details.
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Port rx_datak[3:0]
,
[1:0]
, or
[0] pipe_rx_sync_hdr[(2N-1)
:0] pipe_rx_blk_start[(N-1)
:0] pipe_rx_data_valid[(N-1
):0] pipe_rx_valid[(N-1):0] pipe_phy_status[(N-1):
0] pipe_rx_elecidle[(N-1):
0] pipe_rx_status[(3N-1):
0]
Direction
Out
Out
Out
Out
Out
Out
Out
Out
Clock Domain
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rx_coreclkin rx_coreclkin rx_coreclkin rx_coreclkin rx_coreclkin rx_coreclkin
Asynchronous rx_coreclkin
Description
The data and control indicator.
For Gen1 or Gen2, when 0, indicates that rx_parallel_data
is data, when 1, indicates that control.
rx_parallel_data is
For Gen3,
Bit[0]
corresponds to rx_parallel_data[7:0]
,
Bit[1] corresponds to rx_parallel_data[15:8] and so on. Refer to tableBit Mappings When
the Simplified Interface is Disabled for more details.
,
For Gen3, indicates whether the 130-bit block being transmitted is a Data or Control
Ordered Set Block. The following encodings are defined:
2'b10: Data block
2'b01: Control Ordered Set block
This value is read when pipe_rx_blk_start
= 4'b0001. Refer to
Section 4.2.2.1. Lane Level Encoding in the
PCI Express Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding.
For Gen3, specifies the start block byte location for RX data in the 128-bit block data. Used when the interface between the
PCS and PHY-MAC (FPGA Core) is 32 bits.
Not used for Gen1 and Gen2 data rates.
Active High
For Gen3, this signal is deasserted by the
PHY to instruct the MAC to ignore rx_parallel_data
for current clock cycle.
A value of 1'b1 indicates the MAC should use the data. A value of 1'b0 indicates the MAC should not use the data.
Active High
Asserted when RX data and control are valid.
Signal used to communicate completion of several PHY requests.
Active High
When asserted, the receiver has detected an electrical idle.
Active High
Signal encodes receive status and error codes for the receive data stream and receiver detection. The following encodings are defined:
3'b000 - Receive data OK
3'b001 - 1 SKP added
3'b010 - 1 SKP removed
3'b011 - Receiver detected
3'b100 - Either 8B/10B or 128b/130b decode error and (optionally) RX disparity error
3'b101 - Elastic buffer overflow
3'b110 - Elastic buffer underflow continued...
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Port pipe_sw[1:0]
Direction
Out
Clock Domain
N/A
Description
3'b111 - Receive disparity error, not used if disparity error is reported using 3'b100.
Signal to clock generation buffer indicating the rate switch request. Use this signal for bonding mode only.
For non-bonded applications this signal is internally connected to the local CGB.
Active High. Refer to Table 191 on page 263
Bit Mappings When the Simplified Interface is
Disabled for more details.
Table 191.
Bit Mappings When the Simplified Interface Is Disabled
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter values.
Signal Name Gen1 (TX Byte
Serializer and RX
Byte Deserializer disabled)
Gen1 (TX Byte
Serializer and RX Byte
Deserializer in X2 mode), Gen2 (TX Byte
Serializer and RX Byte
Deserializer in X2 mode)
Gen3 tx_parallel_data tx_parallel_dat a[7:0] tx_parallel_data[29
:22,7:0] tx_parallel_data[40:33,29:22,18
:11,7:0] tx_datak pipe_tx_compliance pipe_tx_elecidle pipe_tx_detectrx_loop bacK pipe_powerdown pipe_tx_margin pipe_tx_swing rx_parallel_data rx_datak rx_syncstatus pipe_phy_status pipe_rx_valid pipe_rx_status tx_parallel_dat a[8] tx_parallel_dat a[9] tx_parallel_dat a[10] tx_parallel_dat a[46] tx_parallel_dat a[48:47] tx_parallel_dat a[51:49] tx_parallel_dat a[53] rx_parallel_dat a[7:0] rx_parallel_dat a[8] rx_parallel_dat a[10] rx_parallel_dat a[65] rx_parallel_dat a[66] rx_parallel_dat a[69:67] tx_parallel_data[30
,8] tx_parallel_data[41,30,19,8] tx_parallel_data[31
,9] tx_parallel_data[42,31,20,9] tx_parallel_data[32
,10] tx_parallel_data[43,32,21,10] tx_parallel_data[46
] tx_parallel_data[46] tx_parallel_data[48
:47] tx_parallel_data[48:47] tx_parallel_data[51
:49] tx_parallel_data[51:49] tx_parallel_data[53
] tx_parallel_data[53] rx_parallel_data[39
:32,7:0] rx_parallel_data[40
,8] rx_parallel_data[55:48,39:32,23
:16,7:0] rx_parallel_data[56,40,24,8] rx_parallel_data[42
,10] rx_parallel_data[58,42,26,10] rx_parallel_data[65
] rx_parallel_data[65] rx_parallel_data[66
] rx_parallel_data[66] rx_parallel_data[69
:67] rx_parallel_data[69:67] continued...
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Signal Name pipe_tx_deemph pipe_tx_sync_hdr pipe_tx_blk_start pipe_tx_data_valid pipe_rx_sync_hdr pipe_rx_blk_start pipe_rx_data_valid
Gen1 (TX Byte
Serializer and RX
Byte Deserializer disabled)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Gen1 (TX Byte
Serializer and RX Byte
Deserializer in X2 mode), Gen2 (TX Byte
Serializer and RX Byte
Deserializer in X2 mode) tx_parallel_data[52
]
N/A
N/A
N/A
N/A
N/A
N/A
Gen3
N/A tx_parallel_data[55:54] tx_parallel_data[56] tx_parallel_data[60] rx_parallel_data[71:70] rx_parallel_data[72] rx_parallel_data[76]
Refer to section 6.6 of Intel PHY Interface for PCI Express (PIPE) Architecture for more information.
Related Information
•
PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate on page 274
• Intel PHY Interface for PCI Express (PIPE) Architecture
•
Bit Mappings When the Simplified Interface is Disabled
on page 263
•
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
2.7.9. fPLL Ports for PIPE
Table 192.
fPLL Ports for PIPE
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter settings.
Port
Pll_powerdown
Pll_reflck0 tx_serial_clk
Direction Clock Domain
Input
Description
Asynchronous Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY
Reset Controller
FPGA IP).
pll_powerdown
output if using this Intel
Input N/A
Output N/A
Reference clock input port 0. There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.
High speed serial clock output port for GX channels.
Represents the x1 clock network.
For Gen1x1, Gen2x1, connect the output from this port to the tx_serial_clk
input of the native PHY IP.
For Gen1x2, x4, x8, use the tx_bonding_clocks port to connect to the Native PHY IP.
output
For Gen2x2, x4, x8, use the tx_bonding_clocks port to connect to the Native PHY IP.
output
For Gen3x1, connect the output from this port to one of the two tx_serial_clk
input ports on the native PHY IP.
For Gen3x2, x4, x8, connect the output from this port to the Auxiliary Master CGB clock input port of the ATX PLL IP.
continued...
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pll_locked
Port pll_pcie_clk
Pll_cal_busy
Mcgb_rst mcgb_aux_clk0 tx_bonding_clocks[6n-1:0] pcie_sw[1:0] pcie_sw_done[1:0]
]
Direction Clock Domain
Output Asynchronous
Description
Active high status signal which indicates if PLL is locked.
Output
Output
Input
Input
N/A This is the hclk required for PIPE interface.
For Gen1x1, x2, x4, x8 use this port to drive the the PIPE interface.
hclk for
For Gen2x1, x2, x4, x8 use this port to drive the the PIPE interface.
hclk
for
For Gen3x1, x2, x4, x8, use the interface.
pll_pcie_clk
from fPLL
(configured as Gen1/Gen2) as the hclk for the PIPE
Asynchronous Status signal which is asserted high when PLL calibration is in progress.
If this port is not enabled in Transceiver PHY Reset
Controller, then perform logical OR with this signal and the tx_cal_busy
output signal from Native PHY to input the tx_cal_busy
on the reset controller IP.
Asynchronous Master CGB reset control.
Output
Input
Output
N/A
N/A
Used for Gen3 to switch between fPLL/ATX PLL during link speed negotiation. For gen3x2, x4, x8 use the mcgb_aux_clk
input port on the ATX PLL.
Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB. It is used for channel bonding, and represents the x6/xN clock network.
For Gen1x1, this port is disabled.
For Gen1x2, x4, x8 connect the output from this port to the tx_bonding_clocks
input on Native PHY.
For Gen2x1, this port is disabled.
For Gen2x2, x4, x8 connect the output from this port to the tx_bonding_clocks
input on Native PHY.
For Gen3x1, this port is disabled.
For Gen3x2, x4, x8, use the tx_bonding_clocks
output from the ATX PLL to connect to the input of the Native PHY.
tx_bonding_clocks
Asynchronous 2-bit rate switch control input used for PCIe protocol implementation.
For Gen1, this port is N/A
For Gen 2x2, x4, x8 connect the
Native PHY to this port.
pipe_sw
output from
For Gen3x2, x4, x8 connect the
Native PHY to this port.
pipe_sw
output from the
For Gen3x2, x4, x8, this port is not used. You must use the pipe_sw
from Native PHY to drive the pcie_sw
input port on the ATX PLL.
Asynchronous 2-bit rate switch status output used for PCIe protocol implementation.
For Gen1, this port is N/A.
For Gen 2x2, x4, x8 connect the pcie_sw_done
output from ATX PLL to the pipe_sw_done
input of Native PHY .
For Gen3x2, x4, x8 connect the from ATX PLL to the pcie_sw_done
output pipe_sw_done
input of Native PHY.
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
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2.7.10. ATX PLL Ports for PIPE
Table 193.
ATX PLL Ports for PIPE
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter settings.
Port
Pll_powerdown
Pll_reflck0 tx_serial_clk pll_locked pll_pcie_clk
Pll_cal_busy
Mcgb_rst mcgb_aux_clk0 tx_bonding_clocks[5:0]
Direction Clock Domain
Input
Description
Asynchronous Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY Reset
Controller pll_powerdown
output if using this Intel FPGA IP.
Input
Output
Output
N/A
N/A
Reference clock input port 0. There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.
High speed serial clock output port for GX channels. Represents the x1 clock network.
For Gen1x1, Gen2x1, connect the output from this port to the tx_serial_clk input of the native PHY IP.
For Gen1x2, x4, x8, use the tx_bonding_clocks output port to connect to the Native PHY.
For Gen2x2, x4, x8, use the tx_bonding_clocks output port to connect to the Native PHY.
For Gen3x1, connect the output from this port to one of the two tx_serial_clk input ports on the native PHY IP.
For Gen3x2, x4, x8, this port is not used. Use the tx_serial_clk output from the fPLL to drive the Auxiliary Master CGB clock input port of the ATX PLL.
Asynchronous Active high status signal which indicates if PLL is locked.
Output
Output
Input
Input
N/A This is the hclk required for PIPE interface.
For Gen1x1,x2,x4,x8 use this port to drive the hclk for the PIPE interface.
For Gen2x1,x2,x4,x8 use this port to drive the hclk for the PIPE interface.
For Gen3x1,x2,x4,x8, this port is not used. Use the pll_pcie_clk
from fPLL (configured as Gen1/Gen2) as the hclk for the PIPE interface.
Asynchronous Status signal which is asserted high when PLL calibration is in progress. If this port is not enabled in the Transceiver PHY
Reset Controller, then perform logical OR with this signal and the tx_cal_busy
output signal from Native PHY to input the tx_cal_busy
on the reset controller IP.
Asynchronous Master CGB reset control.
N/A
Output N/A
Used for Gen3 to switch.
between fPLL/ATX PLL during link speed negotiation.
For gen3x2,x4,x8 use the tx_serial_clk output
port from fPLL (configured for Gen1/Gen2) to drive the input port on the ATX PLL.
mcgb_aux_clk
Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB. Used for channel bonding, and represents the x6/xN clock network.
For Gen1x1, this port is disabled.
For Gen1x2,x4,x8 connect the output from this port to the tx_bonding_clocks
input on Native PHY.
For Gen2x1, this port is disabled
For Gen2x2,x4,x8 connect the output from this port to tx_bonding_clocks
input on Native PHY.
For Gen3x1, this port is disabled.
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Port pcie_sw[1:0] pcie_sw_done[1:0]
Direction Clock Domain
Input
Output
Description
For Gen3x2,x4,x8 use the tx_bonding_clocks
output from the ATX PLL to connect to the the Native PHY.
tx_bonding_clocks
input of
Asynchronous 2-bit rate switch control input used for PCIe protocol implementation.
For Gen1, this port is N/A.
For Gen 2x2,x4,x8 connect the
PHY to this port.
pipe_sw
output from Native
For Gen3x2,x4,x8 use the drive this port.
pipe_sw
output from Native PHY to
Asynchronous 2-bit rate switch status output used for PCIe protocol implementation.
For Gen1, this port is N/A.
For Gen2x2, x4, x8 connect the pcie_sw_done
output from
ATX PLL to pipe_sw_done input of Native PHY .
For Gen3x2, x4, x8 pcie_sw_done
output from ATX PLL to pipe_sw_done
input of Native PHY.
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
2.7.11. Preset Mappings to TX De-emphasis
Table 194.
Arria 10 Preset Mappings to TX De-emphasis
Preset C
+1
C
0
6
7
4
5
8
9
10
0
1
2
3
001111
001010
001100
001000
000000
000000
000000
001100
001000
000000
010110
101101
110010
110000
110100
111100
110110
110100
101010
101100
110010
100110
000000
000000
000000
000000
000000
000110
001000
000110
001000
001010
000000
C
-1
The pipe_g3_txdeemph
port is used to select the link partner’s transmitter deemphasis during equalization. The 18 bits specify the following coefficients:
[5:0]: C
-1
[11:6]: C
0
[17:12]: C
+1
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Note: Intel recommends transmitting Preset P8 coefficients for Arria 10 receiver to recover data successfully.
2.7.12. How to Place Channels for PIPE Configurations
Instead of the fitter or software model, the hardware dictates all the placement restrictions. The restrictions are listed below:
• The channels must be contiguous for bonded designs.
• The master CGB is the only way to access x6 lines and must be used in bonded designs. The local CGB cannot be used to route clock signals to slave channels because the local CGB does not have access to x6 lines.
• When implementing a Gen3-capable PIPE configuration in a -2 or -3 core speed grade, you cannot place the Logical PCS Master Channel in a location adjacent to the Hard IP (HIP).
• Non PCIe-Channels that are placed next to active banks with PIPE interfaces that are Gen3 capable have the following restrictions
— When VCCR_GXB and VCCT_GXB are set to 1.03 V or 1.12 V, the maximum data rate supported for the non-PCIe channels in those banks is 12.5 Gbps for chip-to-chip applications. These channels cannot be used to drive backplanes or for GT rates.
— When VCCR_GXB and VCCT_GXB are set to 0.95 V, the non-PCIe channels in those banks cannot be used.
For channel placement guidelines when using Arria 10 Hard IP for PCIe, refer to the
PCIe User Guide.
For ATX PLL placement restrictions, refer to the section "Transmit PLL
Recommendations Based on Data Rates" of PLLs and Clock Networks chapter.
Related Information
• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
•
PLLs and Clock Networks on page 347
2.7.12.1. Master Channel in Bonded Configurations
For PCIe, both the PMA and PCS must be bonded. There is no need to specify the PMA
Master Channel because of the separate Master CGB in the hardware. However, you must specify the PCS Master Channel through the Native PHY. You can choose any one of the data channels (part of the bonded group) as the logical PCS Master Channel.
Note: Whichever channel you pick as the PCS master, the fitter selects the physical CH1 or
CH4 of a transceiver bank as the master channel. This is because the ASN and Master
CGB connectivity only exists in the hardware of these two channels of the transceiver bank.
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Table 195.
Logical PCS Master Channel for PIPE Configuration
PIPE Configuration x1 x2 x4 x8
Logical PCS Master Channel # (default)
0 (
1 (
2 (
4 (
The following figures show the default configurations:
Figure 109. x2 Configuration
1
0
Logical
Channel
CH1
CH0
Physical
Channel
CH1
CH0
CH5
CH4
CH3
CH2
CH5
CH4
CH3
CH2
Master CH
Data CH
Master
CGB
Master
CGB
Master
CGB
Master
CGB fPLL
ATX
PLL fPLL
ATX
PLL fPLL
ATX
PLL fPLL
ATX
PLL
Note:
Transceiver bank
Transceiver bank
The physical channel 0 aligns with logical channel 0. The logical PCS Master Channel 1 is specified as Physical Channel 1.
(44) Ensure that the Logical PCS Master Channel aligns with Physical Channel 1 or 4 in a given transceiver bank.
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Figure 110. x4 Configuration
The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master
Channel number 2 must be specified as Physical channel 4.
fPLL
3
2
1
0
Logical
Channel
CH4
CH3
CH2
CH1
CH0
Physical
Channel
CH1
CH0
CH5
CH5
CH4
CH3
CH2
Data CH
Master CH
Data CH
Data CH
Master
CGB
Master
CGB
Master
CGB
Master
CGB
ATX
PLL fPLL
ATX
PLL fPLL
ATX
PLL fPLL
ATX
PLL
Transceiver bank
Transceiver bank
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Figure 111. x8 Configuration
For x8 configurations, Intel recommends you choose a master channel that is a maximum of four channels away from the farthest slave channel.
fPLL
7
6
5
4
3
2
1
0
Logical
Channel
CH4
CH3
CH2
CH1
CH0
Physical
Channel
CH1
CH0
CH5
CH5
CH4
CH3
CH2
Data CH
Data CH
Data CH
Master CH
Data CH
Data CH
Data CH
Data CH
Master
CGB
Master
CGB
Master
CGB
Master
CGB
ATX
PLL fPLL
ATX
PLL fPLL
ATX
PLL fPLL
ATX
PLL
Transceiver bank
Transceiver bank
Note: The physical channel 0 aligns with logical channel 0. The logical PCS master channel 4 is specified as Physical channel 4.
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Figure 112. x4 Alternate Configuration
The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master
Channel number 2 must be specified as Physical channel 1.
fPLL
3
2
1
0
Logical
Channel
CH4
CH3
CH2
CH1
CH0
Physical
Channel
CH1
CH0
CH5
CH5
CH4
CH3
CH2 Data CH
Master CH
Data CH
Data CH
Master
CGB
Master
CGB
Master
CGB
Master
CGB
ATX
PLL fPLL
ATX
PLL fPLL
ATX
PLL fPLL
ATX
PLL
Transceiver bank
Transceiver bank
As indicated in the figures above, the fitter picks either physical CH1 or CH4 as the
PCS master in bonded configurations for PIPE.
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Figure 113. x4 Configuration with the Master Channel Adjacent to a Hard IP
The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is adjacent to a Hard IP.
3
2
1
0
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH5
CH4
CH3
CH2
CH3
CH2
CH1
CH0
CH1
CH0
Hard
IP
Data CH
Master CH
Data CH
Data CH fPLL
Master CGB fPLL
Master CGB fPLL
Master CGB fPLL
Master CGB fPLL
Master CGB fPLL
Master CGB
ATX
PLL
ATX
PLL
ATX
PLL
ATX
PLL
ATX
PLL
ATX
PLL
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Logical
Channel
Physical
Channel
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Figure 114. x4 Configuration with the Master Channel not Adjacent to a Hard IP
The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is not adjacent to a Hard IP.
3
2
1
CH5
CH4
CH3
CH2
CH1
CH0
Data CH
Master CH
Data CH fPLL
Master CGB fPLL
Master CGB
ATX
PLL
ATX
PLL
Transceiver
Bank
0 CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
Hard
IP
Data CH fPLL
Master CGB fPLL
Master CGB fPLL
Master CGB fPLL
Master CGB
ATX
PLL
ATX
PLL
ATX
PLL
ATX
PLL
Transceiver
Bank
Transceiver
Bank
Logical
Channel
Physical
Channel
2.7.13. PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate
Gen3 mode requires TX and RX link equalization because of the data rate, the channel characteristics, receiver design, and process variations. The link equalization process allows the Endpoint and Root Port to adjust the TX and RX setup of each lane to improve signal quality. This process results in Gen3 links with a receiver Bit Error Rate
(BER) that is less than 10 -12 .
For detailed information about the four-stage link equalization procedure for 8.0 GT/s data rate, refer to Section 4.2.3 in the PCI Express Base Specification, Rev 3.0. A new
LTSSM state, Recovery.Equalization with Phases 0–3, reflects progress through Gen3 equalization. Phases 2 and 3 of link equalization are optional. Each link must progress through all four phases, even if no adjustments occur. If you skip Phases 2 and 3, you speed up link training at the expense of link BER optimization.
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Phase 0
Phase 0 includes the following steps:
1. The upstream component enters Phase 0 of equalization during
Recovery.Rcvrconfig by sending EQ TS2 training sets with starting presets for the downstream component. EQ TS2 training sets may be sent at 2.5 GT/s or 5 GT/s.
2. The downstream component enters Phase 0 of equalization after exiting
Recovery.Speed at 8 GT/s. It receives the starting presets from the training sequences and applies them to its transmitter. At this time, the upstream component has entered Phase 1 and is operating at 8 GT/s.
3. To move to Phase 1, the receiver must have a BER < 10 able to decode enough consecutive training sequences.
-4 . The receiver should be
4. In order to move to Equalization Phase 1, the downstream component must detect training sets with Equalization Control (EC) bits set to 2’b01.
Phase 1
During Phase 1 of the equalization process, the link partners exchange Full Swing (FS) and Low Frequency (LF) information. These values represent the upper and lower bounds for the TX coefficients. The receiver uses this information to calculate and request the next set of transmitter coefficients.
1. The upstream component moves to EQ Phase 2 when training sets with EC bits set to 1’b0 are captured on all lanes. It also sends EC=2’b10, starting pre-cursor, main cursor, and post-cursor coefficients.
2. The downstream component moves to EQ Phase 2 after detecting these new training sets.
Use the pipe_g3_txdeemph[17:0] port to select the transmitter de-emphasis. The
18 bits specify the following coefficients:
• [5:0]: C
-1
• [11:6]: C
0
• [17:12]: C
+1
Refer to Preset Mappings to TX De-emphasis for the mapping between presets and TX de-emphasis.
Phase 2 (Optional)
During Phase 2, the Endpoint tunes the TX coefficients of the Root Port. The TS1 Use
Preset bit determines whether the Endpoint uses presets for coarse resolution or coefficients for fine resolution.
If you are using the PHY IP Core for PCI Express (PIPE) as the Root Port, the Endpoint can tune the Root Port TX coefficients.
The tuning sequence typically includes the following steps:
1. The Endpoint receives the starting presets from the Phase 2 training sets sent by the Root Port.
2. The circuitry in the Endpoint receiver determines the BER. It calculates the next set of transmitter coefficients using FS and LF. It also embeds this information in the Training Sets for the Link Partner to apply to its transmitter.
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The Root Port decodes these coefficients and presets, performs legality checks for the three transmitter coefficient rules and applies the settings to its transmitter and also sends them in the Training Sets. The default Full Swing (FS) value advertised by the Intel device is 60 and Low Frequency (LF) is 20. The three rules for transmitter coefficients are: a. |C
-1
| <= Floor (FS/4) b. |C
-1
|+C
0
+|C
+1
| = FS c. C
0
-|C
-1
|-|C
+1
|>= LF
Where: C
0
is the main cursor (boost), C
-1
is the pre-cursor (pre-shoot), and C
+1
is
the post-cursor (de-emphasis).
3. This process is repeated until the downstream component's receiver achieves a
BER of < 10 -12
Phase 3 (Optional)
During this phase, the Root Port tunes the Endpoint’s transmitter. This process is analogous to Phase 2 but operates in the opposite direction.
After Phase 3 tuning is complete, the Root Port moves to Recovery.RcvrLock, sending
EC=2’b00, and the final coefficients or preset agreed upon in Phase 2. The Endpoint moves to Recovery.RcvrLock using the final coefficients or preset agreed upon in
Phase 3.
Recommendations for Tuning Link
To improve the BER of the receiver, Intel recommends that you turn on CTLE in triggered mode during Phase 2 Equalization for Endpoints or Phase 3 Equalization for
Root Ports.
Use the port pipe_g3_txdeemph[17:0]
to transmit the coefficients corresponding to the Gen3 presets. Intel recommends transmitting Preset P8 coefficients for A10 receiver to recover data successfully. The pipe_g3_txdeemph
is used to select the link partner’s transmitter de-emphasis during equalization.
Use the port pipe_g3_rxpresethint[2:0]
to turn on CTLE in triggered mode during equalization phases.
Table 196.
CTLE mode for Gen1/Gen2 speeds of Gen3 capable design
Use this table to drive the pipe_g3_rxpresethint
Gen1/Gen2 speeds of a Gen3 capable design.
port and set the CTLE in manual mode when operating at
Supported CTLE - mode Manual. To use CTLE in manual mode Gen3 capable design running at Gen1/Gen2 speeds during
Power up
Down train to Gen1/Gen2 (directed or not) and subsequent re-entry to Gen3
Down train to Gen1/Gen2
• During power up, set pipe_g3_rxpresethint[2:0]
= 3’b000
• You can use the default CTLE 4S AC Gain set by Quartus (or)
• Set the manual CTLE 4S AC Gain using QSF assignments
• On entry to Gen1/2, set pipe_g3_rxpresethint[2:0]
= 3’b000
• You can use the default CTLE 4S AC Gain set by Quartus (or)
• Set the manual CTLE 4S AC Gain using QSF assignments
• On entry to Gen1/2, set pipe_g3_rxpresethint[2:0]
= 3’b000
• You can use the default CTLE 4S AC Gain set by Quartus (or)
• Set the manual CTLE 4S AC Gain using QSF assignments
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Note: Intel does not support use of CTLE in adaptive mode for Gen1/Gen2 speeds. You must use CTLE in manual mode.
Table 197.
CTLE mode for Gen3 speed of Gen3 capable design
Use this table to drive the pipe_g3_rxpresethint operating at Gen3 speed for Gen3 capable designs.
port and set the CTLE mode to adaptation mode when
Supported CTLE - mode Triggered adaptation. To use CTLE in adaptation mode, Set Gen3 capable design running at Gen3 speed during
1st time entry to Gen3
Redoing EQ in Gen3
• In EQ Phase2/3, after far end TX preset/coefficient requests are completed, set pipe_g3_rxpresethint
= 3’b111 and link needs to stay in Recovery for at least 12ms for
CTLE adaptation
• If there is not enough time in EQ phases, delay can be inserted in Recovery.RcvrLock after the EQ
• After that, pipe_g3_rxpresethint
should remain 3’b111 for Gen3 even in Recovery
• pipe_g3_rxpresethint
should be set to 3’b000 in EQ Phase2/3 entry
• Follow the same procedure as first time link up to Gen3
Re-entry to Gen3 after down train to Gen1/
Gen2 (directed or not)
• On subsequent entry to Gen3, set pipe_g3_rxpresethint[2:0] valid data and wait for 12ms in Recovery state for CTLE adaptation
= 3’b111 when there is
Note: Intel recommends that you use CTLE in adaptive mode for Gen3 speed. If you want to use CTLE in manual mode for Gen3 speed, then you must set pipe_g3_rxpresethint[2:0]
= 3’b000 and set the CTLE 4S AC gain value
• You can use the default CTLE 4S AC Gain set by Quartus (or)
• Set the manual CTLE 4S AC Gain using QSF assignments
Related Information
•
Preset Mappings to TX De-emphasis
on page 267
•
Continuous Time Linear Equalization (CTLE)
on page 452
• PCI Express Base Specification
• PIPE Specification
2.7.14. Using Transceiver Toolkit (TTK)/System Console/Reconfiguration
Interface to manually tune Arria 10 PCIe designs (Hard IP(HIP) and
PIPE) (For debug only)
Table 198.
Manual tuning of TX analog settings for PCIe channels
To manually tune TX channels of the Arria 10 PCIe designs using TTK/System Console/Reconfiguration
Interface, you must set the following attributes
Attribute Description Default value in PCIe mode
1’b1
Value to be set to use TTK/
System Console
1’b0 user_fir_coe ff_ctrl_sel
0x105[7]
Mux to select between static vs dynamic (port) control
• 0 for static setting (to use TTK/ system console for manual tuning)
• 1 for dynamic control (PCIe mode) continued...
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Attribute Default value in PCIe mode pre_emp_swit ching_ctrl_p re_tap_1t
0x107[4:0] pre_emp_sign
_pre_tap_1t
0x107[5]
Controlled by coefficients on the port pipe_g3_txdeemph negative vod_output_s wing_ctrl
0x109[4:0] pre_emp_swit ching_ctrl_1 st_post_tap
0x105[4:0] pre_emp_sign
_1st_post_ta p 0x105[6]
Controlled by coefficients on the port pipe_g3_txdeemph
Controlled by coefficients on the port pipe_g3_txdeemph
Negative
Value to be set to use TTK/
System Console
Description
Depends on value set by pre_emp_switching_ctrl_pre_ tap_1t
register setting
Setting this mux affects VOD, pre tap and post tap attributes
Sets 1st Pre tap value
• Direct mapped
Depends on value set by pre_emp_sign_pre_tap_1t register
setting
Depends on value set by vod_output_swing_ctrl
register setting
Depends on value set by pre_emp_switching_ctrl_1st_ post_tap register setting
Sets 1st Pre tap sign
• - 1 negative (default for PCIe mode)
• 0 positive
Output swing
• Direct mapped
Sets 1st Post tap value
• Direct mapped
Depends on value set by pre_emp_sign_1st_post_tap reg ister setting
Set 1st Post tap sign
• - 1 negative (default for PCIe mode)
• - 0 positive
Note: You must set the attribute user_fir_coeff_ctrl_sel
located at register address
0x105[7] back to 1’b1 to allow the Arria 10 PCI Express PIPE design to listen to the port pipe_g3_txdeemph[17:0]
on each channel for normal PCIe operation.
Table 199.
Manual tunning of RX analog settings for PCIe channels
To manually tune RX channels of the Arria 10 PCI Express designs using TTK/System Console/Reconfiguration
Interface, you must set the following attribute
Attribute Description rrx_pcie_eqz
0x161[2]
Default value in PCIe mode
1’b1
Value to be set to use TTK/
System Console
1’b0 adp_4s_ctle_ bypass
0x167[0]
1’b0 • 1’b0 for Gen3 for Adaptive 4S
CTLE
• 1’b1 for Gen1/Gen2 for Manual
4S CTLE
Mux to select between static vs dynamic control
• 0 for static setting (use for manual tuning)
• 1 for dynamic control (PCIe mode)
Setting this mux affects the CTLE 4s gain and 1s gain values
Mux to select between CTLE 4S manual mode vs adaptive mode
• 0 for CTLE 4S adaptive mode
• 1 for CTLE 4S manual mode continued...
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Attribute adp_ctle_acg ain_4s
0x167[5:1]
Adp_status_s el
0x14C[5:0]
Test_mux
0x177[3:0]
Default value in PCIe mode
5’b0
Set the mux to 6’b011011 Set the mux to 6’b011011
Read values. Map 4 bit value read out to 5 bit gain values
Value to be set to use TTK/
System Console
Depends on the value set by adp_ctle_acgain_4s Register setting
Description
Set CTLE manual 4S AC gain
• Direct mapped
Read values. Map 4 bit value read out to 5 bit gain values
Sets the test mux to read the CTLE converged values from 0x177[3:0]
Reflects the converged values from
CTLE adaptation
Note: You must set the attribute rrx_pcie_eqz
located at register address 0x161[2] back to 1’b1 to allow the Arria 10 PCIe PIPE design to listen to the port pipe_g3_rxpresethint[2:0]
on each channel for normal PCIe operation.
Related Information
•
Analog Parameter Settings on page 585
• Debugging Transceiver Links with Transceiver Toolkit
• Arria 10 Register Map
2.8. CPRI
The common public radio interface (CPRI) is a high-speed serial interface developed for wireless network radio equipment controller (REC) to uplink and downlink data from available remote radio equipment (RE).
The CPRI protocol defines the interface of radio base stations between the REC and the RE. The physical layer supports both the electrical interfaces (for example, traditional radio base stations) and the optical interface (for example, radio base stations with a remote radio head). The scope of the CPRI specification is restricted to the link interface only, which is a point-to-point interface. The link has all the features necessary to enable a simple and robust usage of any given REC and RE network topology, including a direct interconnection of multiport REs.
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2.8.1. Transceiver Channel Datapath and Clocking for CPRI
Figure 115. Transceiver Channel Datapath and Clocking for CPRI
Transmitter PMA Transmitter Standard PCS
40 32
FPGA
Fabric
245 MHz tx_clkout tx_pma_div_clkout
PRBS
Generator
/2, /4 tx_coreclkin
245 MHz tx_clkout
Receiver PMA Receiver Standard PCS
40
Parallel Clock
(Recovered)
245 MHz
Parallel Clock
(From Clock
Divider) rx_clkout tx_clkout
PRBS
Verifier
/2, /4 rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
32 rx_coreclkin
245 MHz rx_clkout or tx_clkout
ATX PLL
CMU PLL fPLL
Parallel Clock
Serial Clock
Parallel and Serial Clock Parallel and Serial Clock
Serial Clock
Table 200.
Channel Width Options for Supported Serial Data Rates
Serial Data
Rate
(Mbps)
614.4
(45)
1228.8
2457.6
3072
4915.2
6144
9830.4
8-Bit
Yes
Yes
Yes
Yes
N/A
N/A
N/A
8/10 Bit Width
Channel Width (FPGA-PCS Fabric)
16/20 Bit Width
16-Bit
Yes
Yes
Yes
16-Bit
N/A
Yes
Yes
32-Bit
N/A
Yes
Yes
Yes
N/A
N/A
N/A
Yes
Yes
Yes
N/A
Yes
Yes
Yes
Yes
Table 201.
Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates
Serial Data Rate
(Mbps)
10137.6
12165.12
Interface Width
FPGA fabric - Enhanced PCS (bit)
66
66
Enhanced PCS - PMA (bit)
32, 40, 64
40, 64
(45) Over-sampling is required to implement 614.4Mbps
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2.8.1.1. TX PLL Selection for CPRI
Choose a transmitter PLL that fits your required data rate.
Table 202.
TX PLL Supported Data Rates
ATX and fPLL support the clock bonding feature.
TX PLLs
ATX fPLL
CMU
Supported Data Rate (Mbps)
614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 8110.08, 9830.4, 10137.6, 12165.12
614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 8110.08, 9830.4, 10137.6, 12165.12
614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 8110.08, 9830.4, 10137.6
Note: • Channels that use the CMU PLL cannot be bonded. The CMU PLL that provides the clock can only drive channels in the transceiver bank where it resides.
• Over-sampling is required to implement 614.4Mbps.
2.8.1.2. Auto-Negotiation
When auto-negotiation is required, the channels initialize at the highest supported frequency and switch to successively lower data rates if frame synchronization is not achieved. If your design requires auto-negotiation, choose a base data rate that minimizes the number of PLLs required to generate the clocks required for data transmission.
By selecting an appropriate base data rate, you can change data rates by changing the local clock generation block (CGB) divider. If a single base data rate is not possible, you can use an additional PLL to generate the required data rates.
Table 203.
Recommended Base Data Rates and Clock Generation Blocks for Available
Data Rates
Data Rate (Mbps)
1228.8
2457.6
3072.0
4915.2
6144.0
9830.4
Base Data Rate (Mbps)
9830.4
9830.4
6144.0
9830.4
6144.0
9830.4
Local CGB Divider
8
4
2
2
1
1
2.8.2. Supported Features for CPRI
The CPRI protocol places stringent requirements on the amount of latency variation that is permissible through a link that implements these protocols.
CPRI (Auto) and CPRI (Manual) transceiver configuration rules are both available for
CPRI designs. Both modes use the same functional blocks, but the configuration mode of the word aligner is different between the Auto and Manual modes. In CPRI (Auto) mode, the word aligner works in deterministic mode. In CPRI (Manual) mode, the word aligner works in manual mode.
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To avoid transmission interference in time division multiplexed systems, every radio in a cell network requires accurate delay estimates with minimal delay uncertainty. Lower delay uncertainty is always desired for increased spectrum efficiency and bandwidth.
The Arria 10 devices are designed with features to minimize the delay uncertainty for both RECs and REs.
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI
The deterministic latency state machine in the word aligner reduces the known delay variation from the word alignment process. It automatically synchronizes and aligns the word boundary by slipping one half of a serial clock cycle (1UI) in the deserializer.
Incoming data to the word aligner is aligned to the boundary of the word alignment pattern (K28.5).
Figure 116. Deterministic Latency State Machine in the Word Aligner
Clock-Slip
Control
Parallel
Clock
From RX CDR Deserializer
Deterministic Latency
Synchronization State Machine
To 8B/10B Decoder
When using deterministic latency state machine mode, assert rx_std_wa_patternalign
to initiate the pattern alignment after the reset sequence is complete. This is an edge-triggered signal in all cases except one: when the word aligner is in manual mode and the PMA width is 10, in which case rx_std_wa_patternalign
is level sensitive.
Figure 117. Word Aligner in Deterministic Mode Waveform rx_clkout rx_std_wa_patternalign rx_parallel_data rx_errdetect rx_disperr rx_patterndetect rx_syncstatus f1e4b6e4
1101
1101
0000
0000 b9dbf1db 915d061d e13f913f 7a4ae24a bbae9b10 bcbcbcbc
0000
0000
1010
1010
1000
1000
0010
0000
1010
1010
0000
0000
1111
1111
95cd3c50 91c295cd
0000
Related Information
2.8.2.1.1. Transmitter and Receiver Latency
The latency variation from the link synchronization function (in the word aligner block) is deterministic with the rx_bitslipboundaryselectout
port. Additionally, you can use the tx_bitslipboundaryselect
port to fix the round trip transceiver latency for port implementation in the remote radio head to compensate for latency variation in the word aligner block. The tx_bitslipboundaryselect
port is available to control the number of bits to be slipped in the transmitter serial data stream. You can optionally use the tx_bitslipboundaryselect round-trip latency to a whole number of cycles.
port to round the
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When using the byte deserializer, additional logic is required in the FPGA fabric to determine if the comma byte is received in the lower or upper byte of the word. The delay is dependent on the word in which the comma byte appears.
2.8.3. Word Aligner in Manual Mode for CPRI
When configuring the word aligner in CPRI (Manual), the word aligner parses the incoming data stream for a specific alignment character. After rx_digitalreset deasserts, asserting the rx_std_wa_patternalign
triggers the word aligner to look for the predefined word alignment pattern or its complement in the received data stream. It is important to note that the behavior of the word aligner in Manual mode operates in different ways depending on the PCS-PMA interface width.
Table 204.
Word Aligner Signal Status Behaviors in Manual Mode
PCS-PMA Interface Width
10 rx_std_wa_patternali gn
Behavior
Level sensitive
20 Edge sensitive rx_syncstatus
Behavior
One parallel clock cycle (When three control patterns are detected)
Remains asserted until next rising edge of rx_std_wa_patternalign rx_patterndetect
Behavior
One parallel clock cycle
One parallel clock cycle
PCS-PMA Width = 10
When the PCS-PMA interface width is 10, 3 consecutive word alignment patterns found after the initial word alignment in a different word boundary causes the word aligner to resynchronize to this new word boundary if the rx_std_wa_patternalign remains asserted; rx_std_wa_patternalign
is level sensitive. If you deassert rx_std_wa_patternalign
, the word aligner maintains the current word boundary even when it finds the alignment pattern in a new word boundary. When the word aligner is synchronized to the new word boundary, rx_patterndetect
and rx_syncstatus
are asserted for one parallel clock cycle.
PCS-PMA Width =20
When the PMA-PCS width is 20, any alignment pattern found after the initial alignment in a different word boundary causes the word aligner to resynchronize to this new word boundary on the rising edge of rx_std_wa_patternalign
; rx_std_wa_patternalign
is edge sensitive. The word aligner maintains the current word boundary until the next rising edge of rx_std_wa_patternalign
. When the word aligner is synchronized to the new word boundary, rx_patterndetect
asserts for one parallel clock cycle and rx_syncstatus remains asserted until the next rising edge of rx_std_wa_patternalign
.
Figure 118. Word Aligner in Manual Alignment Mode Waveform rx_clkout rx_std_wa_patternalign rx_parallel_data rx_patterndetect rx_syncstatus
0...
0
0000 f1e4b6e4 b9dbf1db 915d061d e13f913f 7a4ae24a bcbc7b78 bcbcbcbc
1100 1111
1100 1111
95cd3c50 91c295cd ded691c2
0000
Related Information
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2.8.4. How to Implement CPRI in Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing your CPRI protocol.
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
2. Select CPRI (Auto) or CPRI (Manual) from the Transceiver configuration
rules list located under Datapath Options, depending on which protocol you are implementing.
3. Use the parameter values in the tables in Native PHY IP Parameter Settings for
on page 285 as a starting point. Or, you can use the protocol presets
described in Preset Configuration Options . You can then modify the setting to meet
your specific requirements.
4. Click Generate to generate the Native PHY IP (this is your RTL file).
Figure 119. Signals and Ports of Native PHY IP for CPRI
Arria 10 Transceiver Native PHY tx_cal_busy rx_cal_busy
NIOS
Hard Calibration IP
Reconfiguration
Registers tx_serial_data
TX PMA
Serializer
10/20
TX Standard PCS tx_datak tx_parallel_data tx_coreclkin tx_clkout unused_tx_parallel_data[118:0] reconfig_reset reconfig_clk reconfig_avmm tx_digital_reset tx_datak[1:0] tx_parallel_data[15:0] tx_coreclkin tx_clkout tx_serial_clk0
(from TX PLL) rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref
Local Clock
Generation
Block
RX PMA
Deserializer
CDR
10/20
RX Standard PCS rx_datak rx_parallel_data rx_clkout rx_coreclkin rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus rx_std_wa_patternalign unused_rx_parallel_data[118:0] tx_analog_reset rx_analog_reset rx_digital_reset rx_datak[1:0] rx_parallel_data[15:0] rx_clkout rx_coreclkin rx_errdetect[1:0] rx_disperr[1:0] rx_runningdisp[1:0] rx_patterndetect[1:0] rx_syncstatus[1:0] rx_std_wa_patternalign unused_rx_parallel_data[118:0]
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller.
You can use your own reset controller or use the Native PHY Reset Controller IP.
7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the information in the following figure to connect the ports.
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Figure 120. Connection Guidelines for a CPRI PHY Design pll_refclk PLL IP Core clk reset pll_sel pll_locked
Reset Controller pll_cal_busy tx_ready rx_ready rx_cdr_refclk tx_serialclk0
Data
Generator tx_clkout tx_parallel_data
Data
Verifier rx_clkout rx_parallel_data
Arria 10 Transceiver Native PHY tx_serial_data rx_serial_data
8. Simulate your design to verify its functionality.
Related Information
•
Arria 10 Standard PCS Architecture
on page 479
For more information about Standard PCS architecture
•
Arria 10 PMA Architecture on page 447
For more information about PMA architecture
•
on page 398
For more information about implementing PLLs and clocks
•
PLL architecture and implementation details
•
Resetting Transceiver Channels
on page 416
Reset controller general information and implementation details
•
Port definitions for the Transceiver Native PHY Standard Datapath
2.8.5. Native PHY IP Parameter Settings for CPRI
Table 205.
General and Datapath Options
The first two sections of the Parameter Editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.
Parameter
Message level for rule violations
Value error continued...
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Parameter
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Table 206.
TX PMA Parameters
Parameter
TX channel bonding mode
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Enable tx_pma_qpipulldn port (QPI)
Enable tx_pma_txdetectrx port (QPI)
Enable tx_pma_rxfound port (QPI)
Enable rx_seriallpbken port
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Value warning
CPRI (Auto)
CPRI (Manual) basic
TX/RX Duplex
1-36
1228.8 Mbps
2457.6 Mbps
3072 Mbps
4915.2 Mbps
6144 Mbps
8110.08 Mbps
9830.4 Mbps
10137.6 Mbps
12165.12 Mbps
(
)
Off
On
Value
Not Bonded / PMA Bonding Only / PMA and PCS Bonding
1
1
0
Off
On
2
Off
Off
Off
Off
Off
Off
(46) 10137.6 Mbps and 12165.12 Mbps are implemented by selecting 10GBase-R or 10GBase-R
1588 under Transceiver configuration rules. The Enhanced PCS is selected when the CPRI data rate is 10137.6 Mbps and above.
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Table 207.
RX PMA Parameters
Parameter
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
DFE adaptation mode
Number of fixed dfe taps
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_pma_qpipulldn port (QPI)
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
Table 208.
Standard PCS Parameters
Parameters
Standard PCS / PMA interface width
FPGA fabric / Standard TX PCS interface width
FPGA fabric / Standard RX PCS interface width
Enable 'Standard PCS' low latency mode
TX FIFO mode
RX FIFO mode
Enable tx_std_pcfifo_full port
Enable tx_std_pcfifo_empty port
Enable rx_std_pcfifo_full port
Enable rx_std_pcfifo_empty port
TX byte serializer mode
RX byte deserializer mode
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
Value
1
0
Select legal range defined by the Quartus Prime software
1000 manual disabled
3
Off
On
2
Off
Off
On
On
Off
Off
Off
Value
20
32
32
Off register_fifo register_fifo
Off
Off
Off
Off
Serialize x2
Deserialize x2
On
Off
On continued...
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Parameters
RX rate match FIFO mode
RX rate match insert / delete -ve pattern (hex)
RX rate match insert / delete +ve pattern (hex)
Enable rx_std_rmfifo_full port
Enable rx_std_rmfifo_empty port
PCI Express Gen3 rate match FIFO mode
Enable TX bit slip
Enable tx_std_bitslipboundarysel port
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Number of word alignment patterns to achieve sync
Number of invalid data words to lose sync
Number of valid data words to decrement error count
Enable fast sync status reporting for deterministic latency SM
Enable rx_std_wa_patternalign port
Enable rx_std_wa_a1a2size port
Enable rx_std_bitslipboundarysel port
Enable rx_bitslip port
All options under Bit Reversal and Polarity Inversion
All options under PCIe Ports
Table 209.
Dynamic Reconfiguration
Parameter
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
Enable embedded debug
Enable capability registers
Set user-defined IP identifier
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Value
Disabled
0x00000000
0x00000000
Off
Off
Bypass
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
deterministic latency (CPRI Auto configuration)
manual (FPGA fabric controlled) (CPRI
Manual configuration)
10
0x000000000000017c
3
)
3
)
3
)
On / Off
On / Off
Off
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Off
Off
Value
Off
Off
Off
Off
Off
0 continued...
(47) These are unused when the transceiver PHY is in CPRI mode.
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Parameter
Enable control and status registers
Enable prbs soft accumulators
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
Generate MIF (Memory Initialization File)
Table 210.
Generation Options
Parameter
Generate parameter documentation file
Value
Off
Off altera_xcvr_native_a10
Off
Off
Off
Value
On
2.9. Other Protocols
2.9.1. Using the "Basic (Enhanced PCS)" and "Basic with KR FEC"
Configurations of Enhanced PCS
You can use Arria 10 transceivers to configure the Enhanced PCS to support other 10G or 10G-like protocols. The Basic (Enhanced PCS) transceiver configuration rule allows access to the Enhanced PCS with full user control over the transceiver interfaces, parameters, and ports.
You can configure the transceivers for Basic functionality using the Native PHY IP
Basic (Enhanced PCS) transceiver configuration rule.
Basic with KR FEC is a KR FEC sublayer support with a low latency physical coding sublayer (PCS). The KR FEC sublayer increases the bit error rate (BER) performance of a link. This mode can run up to a data rate of 25.8 Gbps. Use this configuration to implement applications with low latency or low BER requirements or applications such as 10 Gbps, 40 Gbps or 100 Gbps Ethernet over backplane (10GBASE-KR protocol).
The Forward Error Correction (FEC) function is defined in Clause 74 of IEEE
802.3ap-2007. FEC provides an error detection and correction mechanism that allows noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10 -12 . The
FEC sublayer provides additional link margin by compensating for variations in manufacturing and environmental conditions. To distinguish it from other FEC mechanisms (for example, Optical Transport Network FEC), FEC as defined in Clause
74 of IEEE 802.3ap-2007 is called KR FEC.
Note: This configuration supports the FIFO in phase compensation and register modes, and
KR FEC PCS blocks. You can implement all other required logic for your specific application, such as standard or proprietary protocol multi-channel alignment, either in the FPGA fabric in soft IP or use Intel's 10GBASE-KR PHY IP core product as full solutions in the FPGA.
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Figure 121. Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS)
Configuration
Transmitter PMA Transmitter Enhanced PCS FPGA
Fabric
32
32
32-bit data
PRBS
Generator
PRP
Generator
Parallel Clock (322.265625 MHz) tx_clkout
KR FEC TX G KR FEC Scr
KR FEC Enc
Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout rx_pma_div_clkout
32 32
32-bit data
PRBS
Verifier
Parallel Clock (322.265625 MHz)
KR FEC Block S KR FEC Dec
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Notes:
1. Can be enabled or disabled based on the gearbox ratio selected
2. Depends on the value of the clock division factor chosen
3. To use the Scrambler and Descrambler, you must use a 66:32, 66:40, or 66:64 gear ratio and the Block Synchronizer must be enabled
Clock Divider
Parallel and Serial Clocks
PRP
Verifier
10GBASE-R
BER Checker
(5156.25 MHz) =
Data rate/2 (2)
ATX PLL fPLL
CMU PLL
Serial Clock
Input Reference Clock rx_clkout
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Figure 122. Transceiver Channel Datapath and Clocking for a Basic with KR FEC
Configuration
Clock frequencies in this figure are examples based on a 10.3125 Gbps data rate.
Transmitter PMA Transmitter Enhanced PCS
64
TX
Data &
Control
64 + 2 tx_hf_clk tx_pma_clk tx_krfec_clk
PRBS
Generator
Parallel Clock (161.13 MHz) (3)
PRP
Generator
156.25 MHz (2)
FPGA
Fabric tx_clkout
KR FEC TX G KR FEC Scr
KR FEC Enc
KR FEC
Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout rx_pma_div_clkout
RX
Data &
Control
64 + 2 rx_rcvd_clk rx_pma_clk
/64
PRBS
Verifier rx_krfec_clk
Parallel Clock (161.13 MHz) (3)
PRP
Verifier
10GBASE-R
BER Checker
156.25 MHz (2) rx_clkout
KR FEC Block S
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Notes:
1. Value is based on the clock division factor chosen
2. Value is calculated as data rate on parallel interface/FPGA fabric - PCS interface width
3. Value is calculated as data rate on serial interface/PCS-PMA interface width
KR FEC Dec
Clock Generation Block (CGB)
KR FEC
Clock Divider
Parallel and Serial Clocks tx_serial_clk0
(5156.25 MHz) =
Data rate/2
ATX PLL fPLL
CMU PLL
Serial Clock
Input Reference Clock
2.9.1.1. How to Implement the Basic (Enhanced PCS) and Basic with KR FEC
Transceiver Configuration Rules in Arria 10 Transceivers
You should be familiar with the Basic (Enhanced PCS) and PMA architecture, PLL architecture, and the reset controller before implementing the Basic (Enhanced PCS) or Basic with KR FEC Transceiver Configuration Rule.
1. Open the IP Catalog and select the Arria 10 Transceiver Native PHY IP.
Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
2. Select Basic (Enhanced PCS) or Basic with KR FEC from the Transceiver
Configuration Rules list located under Datapath Options.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
Basic (Enhanced PCS) and Basic with KR FEC Transceiver Configuration Rules
as a starting point. Or, you can use the protocol presets described in
. You can then modify the settings to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
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Figure 123. Signals and Ports of Native PHY IP for Basic (Enhanced PCS) and Basic with
KR FEC Configurations tx_cal_busy rx_cal_busy
NIOS
Hard Calibration IP
Reconfiguration
Registers reconfig_reset reconfig_clk reconfig_avmm tx_serial_data
TX PMA
Serializer
TX Enhanced PCS tx_digital_reset tx_control[17:0] tx_parallel_data[127:0] tx_coreclkin tx_clkout tx_enh_data_valid tx_digital_reset tx_control[17:0] tx_parallel_data[127:0] tx_coreclkin tx_clkout tx_enh_data_valid tx_serial_clk0
(from TX PLL)
Clock
Generation
Block
RX PMA RX Enhanced PCS tx_analog_reset rx_analog_reset
Deserializer rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref
CDR rx_digital_reset rx_clkout rx_coreclkin rx_parallel_data[127:0] rx_control[19:0] rx_digital_reset rx_clkout rx_coreclkin rx_parallel_data[127:0] rx_control[19:0] rx_cdr_refclk0
5. Configure and instantiate the PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
7. Connect the Native PHY IP core to the PLL IP core and the reset controller.
Figure 124. Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design
PLL IP Core
Reset
Controller
Design
Testbench
32-bit data
(32:32 gearbox ratio)
Arria 10 Transceiver
Native PHY
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Figure 125. Connection Guidelines for a Basic with KR FEC Transceiver Design
PLL IP Core
Reset
Controller
Design
Testbench
64d + 2c
Arria 10 Transceiver
Native PHY
8. Simulate your design to verify its functionality.
Related Information
•
Arria 10 Enhanced PCS Architecture
on page 461
For more information about Enhanced PCS architecture
•
Arria 10 PMA Architecture on page 447
For more information about PMA architecture
•
on page 398
For more information about implementing PLLs and clocks
•
PLL architecture and implementation details
•
Resetting Transceiver Channels
on page 416
Reset controller general information and implementation details
•
For detailed information about the available ports in the Basic protocol.
2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic with KR FEC
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Table 211.
General and Datapath Parameters
The first two sections of the Parameter Editor for the Transceiver Native PHY provide a list of general and datapath options to customize the transceiver.
Parameter
Message level for rule violations
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Range
error, warning
Basic (Enhanced PCS), Basic w/KR FEC
Basic, QPI, GPON
TX / RX Duplex, TX Simplex, RX Simplex
1 to 96
GX transceiver channel: 1 Gbps (
to 17.4 Gbps continued...
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Parameter
Enable datapath and interface reconfiguration
Enable simplified data interface
Table 212.
TX PMA Parameters
Parameter
TX channel bonding mode
PCS TX channel bonding master
Actual PCS TX channel bonding master
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Enable tx_pma_qpipulldn port (QPI)
Enable tx_pma_txdetectrx port (QPI)
Enable tx_pma_rxfound port (QPI)
Enable rx_serialpbken port
Table 213.
RX PMA Parameters
Parameter
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
Range
GT transceiver channel: 1 Gbps (
) to 25.8 Gbps (49)
On / Off
On / Off
Range
Not bonded, PMA only bonding, PMA and PCS bonding
Auto, 0 to n-1, n (where n = the number of data channels)
n-1 (where n = the number of data channels)
1, 2, 4, 8
1, 2, 3, 4
0
On / Off
On / Off
Disabled, 1, 2, 33, 40, 66
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
PPM detector threshold
CTLE adaptation mode
DFE adaptation mode
Number of fixed dfe taps
Enable rx_pma_clkout port
Range
1 to 5
0 to 4
For Basic (Enhanced PCS): Depends on the data rate parameter
For Basic with KR FEC: 50 to 800
100, 300, 500, 1000 manual
adaptation enabled, manual, disabled
3, 7
On / Off continued...
(48) Applies when operating in reduced power modes. For standard power modes, the Enhanced
PCS minimum data rate is 1600 Mbps.
(49) The Enhanced PCS must be configured in basic mode to support this data rate range.
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Parameter
Enable rx_pma_div_clkout port rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_pma_qpipulldn port (QPI)
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_serialpbken port
Enable PRBS verifier control and status ports
Range
On / Off
Disabled, 1, 2, 33, 40, 66
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
Table 214.
Enhanced PCS Parameters
Enable Enhanced PCS low latency mode
Enable RX/TX FIFO double width mode
TX FIFO mode
Parameter
Enhanced PCS/PMA interface width
FPGA fabric/Enhanced PCS interface width
Range
32, 40, 64
Note: Basic with KR FEC allows 64 only
32, 40, 50, 64, 66, 67
Note: Basic with KR FEC allows 66 only
On / Off
On / Off
Phase compensation, Register, Interlaken, Basic, Fast register
Note: Only Basic Enhanced and Basic Enhanced with
KRFEC are valid.
10, 11, 12, 13, 14, 15
1, 2, 3, 4, 5
On / Off
TX FIFO partially full threshold
TX FIFO partially empty threshold
Enable tx_enh_fifo_full port
Enable tx_enh_fifo_pfull port
Enable tx_enh_fifo_empty port
Enable tx_enh_fifo_pempty port
RX FIFO mode
RX FIFO partially full threshold
On / Off
On / Off
On / Off
Phase Compensation, Register, Basic
0 to 31
RX FIFO partially empty threshold 0 to 31
Enable RX FIFO alignment word deletion (Interlaken) On / Off
Enable RX FIFO control word deletion (Interlaken)
Enable rx_enh_data_valid port
On / Off
On / Off
Enable rx_enh_fifo_full port
Enable rx_enh_fifo_pfull port
Enable rx_enh_fifo_empty port
Enable rx_enh_fifo_pempty port
On / Off
On / Off
On / Off
On / Off continued...
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Range Parameter
Enable rx_enh_fifo_del port (10GBASE-R)
Enable rx_enh_fifo_insert port (10GBASE-R)
Enable rx_enh_fifo_rd_en port (Interlaken)
Enable rx_enh_fifo_align_val port (Interlaken)
Enable rx_enh_fifo_align_cir port (Interlaken)
Enable TX 64b/66b encoder
Enable RX 64b/66b decoder
Enable TX sync header error insertion
Enable RX block synchronizer
Enable rx_enh_blk_lock port
Enable TX data bitslip
Enable TX data polarity inversion
Enable RX data bitslip
Enable RX data polarity inversion
Enable tx_enh_bitslip port
Enable rx_bitslip port
Enable RX KR-FEC error marking
Error marking type
Enable KR-FEC TX error insertion
KR-FEC TX error insertion spacing
Enable tx_enh_frame port
Enable rx_enh_frame port
Enable rx_enh_frame_dian_status port
Table 215.
Dynamic Reconfiguration Parameters
Parameter
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
Enable embedded debug
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Enable prbs soft accumulators
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
On / Off
On / Off
On / Off
On / Off
On / Off number
On / Off
On / Off text string
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
10G, 40G
On / Off
On / Off
On / Off
On / Off
On / Off
Range
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Table 216.
Generate Options Parameters
Parameter
Generate parameter documentation file On / Off
Range
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS
In the Parameter Editor, use the following settings to enable low latency:
1. Select the Enable 'Enhanced PCS' low latency mode option.
2. Select one of the following gear ratios:
Single-width mode: 32:32, 40:40, 64:64, 66:40, 66:64, or 64:32
Double-width mode: 40:40, 64:64, or 66:64
3. Select Phase_compensation in the TX and RX FIFO mode list.
4. If you need the Scrambler and Descrambler features, enable Block Synchronize and use the 66:32, 66:40, or 66:64 gear ratio.
2.9.1.4. Enhanced PCS FIFO Operation
Phase Compensation Mode
Phase compensation mode ensures correct data transfer between the core clock and parallel clock domains. The read and write sides of the TX Core or RX Core FIFO must be driven by the same clock frequency. The depth of the TX or RX FIFO is constant in this mode. Therefore, the TX Core or RX Core FIFO flag status can be ignored. You can tie tx_fifo_wr_en
or rx_data_valid
to 1.
Basic Mode
Basic mode allows you to drive the write and read side of a FIFO with different clock frequencies. tx_coreclkin
or rx_coreclkin
must have a minimum frequency of the lane data rate divided by 66. The frequency range for tx_coreclkin
or rx_coreclkin
is (data rate/32) to (data rate/66). For best results, Intel recommends that tx_coreclkin
or rx_coreclkin the FIFO flag to control write and read operations.
be set to (data rate/32). Monitor
For TX FIFO, assert tx_enh_data_valid
with the tx_fifo_pfull
This can be done with the following example assignment:
signal going low.
assign tx_enh_data_valid = ~tx_fifo_pfull;
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Figure 126. TX FIFO Basic Mode Operation tx_clkout (read side) tx_coreclk (write side) tx_parallel_data[63:0] tx_digitalreset tx_enh_datavalid tx_fifo_pempty tx_fifo_full tx_fifo_pfull
64’d0 64’d1 64’d2 64’d3 64’d4 64’d5 64’d6 64’d7 64’d8 64’d9 64’ha
For RX FIFO, assert rx_enh_read_en
with the rx_fifo_pempty
This can be done with the following example assignment:
signal going low.
assign rx_enh_read_en = ~rx_fifo_pempty;
Figure 127. RX FIFO Basic Mode Operation rx_clkout (write side) rx_coreclkin (read side) rx_parallel_data[63:0] rx_digitalreset rx_enh_read_en rx_fifo_pfull rx_fifo_empty rx_fifo_pempty
64’d0 64’d1 64’d2 64’d3 64’d4 64’d5 64’d6 64’d7 64’d8 64’d9 64’ha
If you are using even gear ratios, the rx_enh_data_valid
signal is always high. For uneven gear ratios, rx_enh_data_valid
toggles. RX parallel data is valid when rx_enh_data_valid
is high. Discard invalid RX parallel data when the rx_enh_datavalid
signal is low.
Register and Fast Register Mode
This FIFO mode is used for protocols, which require deterministic latency. You can tie tx_fifo_wr_en
to 1.
2.9.1.5. TX Data Bitslip
The bit slip feature in the TX gearbox allows you to slip the transmitter bits before they are sent to the serializer.
The value specified on the TX bit slip bus indicates the number of bit slips. The minimum slip is one UI. The maximum number of bits slipped is equal to the FPGA fabric-to-transceiver interface width minus 1. For example, if the FPGA fabric-totransceiver interface width is 64 bits, the bit slip logic can slip a maximum of 63 bits.
Each channel has 6 bits to determine the number of bits to slip. The TX bit slip bus is a level-sensitive port, so the TX serial data is bit slipped statically by TX bit slip port
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assignments. Each TX channel has its own TX bit slip assignment and the bit slip amount is relative to the other TX channels. You can improve lane-to-lane skew by assigning TX bit slip ports with proper values.
The following figure shows the effect of slipping tx_serial_data[0]
by one UI to reduce the skew with tx_serial_data[1]
. After the bit slip, tx_serial_data[0] and tx_serial_data[1]
are aligned.
Figure 128. TX Bit Slip tx_serial_clock tx_enh_bitslip[0] 0000000 tx_serial_data[0] (Before) tx_enh_bitslip[0] 0000001 tx_serial_data[0] (After) tx_serial_data[1]
1 UI
2.9.1.6. TX Data Polarity Inversion
Use the TX data polarity inversion feature to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout. To enable TX data polarity inversion, select the Enable TX data polarity inversion option in the Gearbox section of Platform Designer (Standard). It can also be dynamically controlled with dynamic reconfiguration.
2.9.1.7. RX Data Bitslip
The RX data bit slip in the RX gearbox allows you to slip the recovered data. An asynchronous active high edge on the rx_bitslip
port changes the word boundary, shifting rx_parallel_data
one bit at a time. Use the rx_bitslip
port with its own word aligning logic. Assert the rx_bitslip
signal for at least two parallel clock cycles to allow synchronization. You can verify the word alignment by monitoring rx_parallel_data
. Using the RX data bit slip feature is optional.
Figure 129. RX Bit Slip rx_clkout rx_bitslip rx_parallel_data[63:0] 64’d0 64’d1
2.9.1.8. RX Data Polarity Inversion
Use the RX data polarity inversion feature to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout. To enable RX data polarity inversion, select the Enable RX data polarity inversion option in the Gearbox section of Platform Designer (Standard). It can also be dynamically controlled with dynamic reconfiguration.
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2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match
Configurations of Standard PCS
Use one of the following transceiver configuration rules to implement protocols such as
SONET/SDH, SDI/HD, SATA, or your own custom protocol:
• Basic protocol
• Basic protocol with low latency enabled
• Basic with rate match protocol
Figure 130. Transceiver Channel Datapath and Clocking for the Basic and Basic with Rate
Match Configurations
The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.
Transmitter PMA Transmitter Standard PCS FPGA
Fabric
10
16
625 MHz (2)
Receiver PMA
125 MHz (1) tx_clkout tx_pma_div_clkout
PRBS
Generator
/2 tx_coreclkin
Receiver Standard PCS
62.5 MHz (1) tx_clkout
10
16
Parallel Clock
(Recovered)
125 MHz (1)
Parallel Clock
(From Clock
Divider) rx_clkout tx_clkout
PRBS
Verifier
/2 rx_coreclkin
62.5 MHz (1) rx_clkout or tx_clkout rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
ATX PLL
CMU PLL fPLL
Parallel Clock
Serial Clock
Parallel and Serial Clock
Notes:
1. The parallel clock (tx_clkout or rx_clkout) is calculated as data rate/PCS-PMA interface width =1250/10 = 125 MHz.
When the Byte Serializer is set to Serialize x2 mode, tx_clkout and rx_clkout become 1250/20 = 62.5 MHz.
2. The serial clock is calculated as data rate/2. The PMA runs on a dual data rate clock.
3. This block is only enabled when using the Basic with Rate Match transceiver configuration rule.
Parallel and Serial Clock
Serial Clock
In low latency modes, the transmitter and receiver FIFOs are always enabled.
Depending on the targeted data rate, you can optionally bypass the byte serializer and deserializer blocks.
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Figure 131. Transceiver Channel Datapath and Clocking for Basic Configuration with Low
Latency Enabled
The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.
Transmitter PMA Transmitter Standard PCS FPGA
Fabric
10
16
625 MHz (2)
125 MHz (1) tx_clkout tx_pma_div_clkout
PRBS
Generator
/2 tx_coreclkin
Receiver Standard PCS
62.5 MHz (1) tx_clkout
Receiver PMA
10
16
Parallel Clock
(Recovered)
125 MHz (1)
Parallel Clock
(From Clock
Divider) rx_clkout tx_clkout
PRBS
Verifier
/2 rx_coreclkin
62.5 MHz (1) rx_clkout or tx_clkout rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
ATX PLL
CMU PLL fPLL
Parallel Clock
Serial Clock
Parallel and Serial Clock
Notes:
1. The parallel clock (tx_clkout or rx_clkout) is calculated as data rate/PCS-PMA interface width = 1250/10 = 125 MHz.
When the Byte Serializer is set to Serialize x2 mode, tx_clkout and rx_clkout become 1250/20 = 62.5 MHz.
2. The serial clock is calculated as data rate/2. The PMA runs on a dual data rate clock.
Parallel and Serial Clock
Serial Clock
In low latency modes, the transmitter and receiver FIFOs are always enabled.
Depending on the targeted data rate, you can optionally bypass the byte serializer and deserializer blocks.
Related Information
Arria 10 Standard PCS Architecture
on page 479
2.9.2.1. Word Aligner Manual Mode
To use this mode:
1. Set the RX word aligner mode to Manual (FPGA Fabric controlled).
2. Set the RX word aligner pattern length option according to the PCS-PMA interface width.
3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.
This mode adds rx_patterndetect
and rx_syncstatus
Enable rx_std_wa_patternalign port option to enable
. You can select the rx_std_wa_patternalign
. An active high on rx_std_wa_patternalign
re-aligns the word aligner one time.
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Note: • rx_patterndetect
is asserted whenever there is a pattern match.
• rx_syncstatus
is asserted after the word aligner achieves synchronization.
• rx_std_wa_patternalign
is asserted to re-align and resynchronize.
• If there is more than one channel in the design, rx_patterndetect
, rx_syncstatus
and rx_std_wa_patternalign
become buses in which each bit corresponds to one channel.
You can verify this feature by monitoring rx_parallel_data
.
The following timing diagrams demonstrate how to use the ports and show the relationship between the various control and status signals. In the top waveform, rx_parallel_data
is initially misaligned. After asserting the rx_std_wa_patternalign
signal, it becomes aligned. The bottom waveform shows the behavior of the rx_syncstatus
signal when rx_parallel_data
is already aligned.
Figure 132. Manual Mode when the PCS-PMA Interface Width is 8 Bits tx_parallel_data
= 8'hBC and the word aligner pattern = 8'hBC rx_std_wa_patternalign tx_parallel_data bc
00 bc rx_parallel_data rx_patterndetect rx_syncstatus rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus bc bc
In manual alignment mode, the word alignment operation is manually controlled with the rx_std_wa_patternalign
input signal or the rx_enapatternalign
register.
The word aligner operation is level-sensitive to rx_enapatternalign
. The word aligner asserts the rx_syncstatus
signal for one parallel clock cycle whenever it realigns to the new word boundary.
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Figure 133. Manual Mode when the PCS-PMA Interface Width is 10 Bits tx_parallel_data
= 10'h3BC and the word aligner pattern = 10'h3BC rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus
3bc
000 3bc rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus
3bc
3bc
Figure 134. Manual Mode when the PCS-PMA Interface Width is 16 Bits tx_parallel_data
= 16'hF3BC and the word aligner pattern = 16'hF3BC rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus f3bc
0000
00
00 f3bc
01
11 11 rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus f3bc f3bc
01
11 00 11
Figure 135. Manual Mode when the PCS-PMA Interface Width is 20 Bits tx_parallel_data
= 20'hFC3BC and the word aligner pattern = 20'hFC3BC rx_std_wa_patternalign tx_parallel_data fc3bc rx_parallel_data rx_patterndetect rx_syncstatus
0000
00
00 fc3bc
01
11 11 11 rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus fc3bc fc3bc
01
11 00 11
2.9.2.2. Word Aligner Synchronous State Machine Mode
To use this mode:
• Select the Enable TX 8B/10B encoder option.
• Select the Enable RX 8B/10B decoder option.
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Note:
The 8B/10B encoder and decoder add the following additional ports:
• tx_datak
• rx_datak
• rx_errdetect
• rx_disperr
• rx_runningdisp
1. Set the RX word aligner mode to synchronous state machine.
2. Set the RX word aligner pattern length option according to the PCS-PMA interface width.
3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.
The RX word aligner pattern is the 8B/10B encoded version of the data pattern. You can also specify the number of word alignment patterns to achieve synchronization, the number of invalid data words to lose synchronization, and the number of valid data words to decrement error count. This mode adds two additional ports: rx_patterndetect
and rx_syncstatus
.
• rx_patterndetect
is asserted whenever there is a pattern match.
• rx_syncstatus
is asserted after the word aligner achieves synchronization.
• rx_std_wa_patternalign
is asserted to re-align and re-synchronize.
• If there is more than one channel in the design, tx_datak
, rx_datak
, rx_errdetect
, rx_disperr
, rx_runningdisp
, rx_patterndetect
, and rx_syncstatus
become buses in which each bit corresponds to one channel.
You can verify this feature by monitoring rx_parallel_data
.
Figure 136. Synchronization State Machine Mode when the PCS-PMA Interface Width is
20 Bits rx_std_wa_patternalign tx_datak tx_parallel_data rx_parallel_data rx_datak rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus
11
00
00
11
00
00
11 bc02
0000 02bc
01
00
00
11
01
00 11 00
11
11 00 11
2.9.2.3. RX Bit Slip
To use the RX bit slip, select Enable rx_bitslip port and set the word aligner mode to
bit slip. This adds rx_bitslip
as an input control port. An active high edge on rx_bitslip
slips one bit at a time. When rx_bitslip
is toggled, the word aligner slips one bit at a time on every active high edge. Assert the rx_bitslip
signal for at least two parallel clock cycles to allow synchronization. You can verify this feature by monitoring rx_parallel_data
.
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The RX bit slip feature is optional and may or may not be enabled.
Figure 137. RX Bit Slip in 8-bit Mode tx_parallel_data
= 8'hbc rx_std_bitslipboundarysel rx_bitslip
01111 tx_parallel_data rx_parallel_data bc
00 97 cb e5 f2 79
Figure 138. RX Bit Slip in 10-bit Mode tx_parallel_data
= 10'h3bc rx_std_bitslipboundarysel 01111 rx_bitslip tx_parallel_data rx_parallel_data
3bc
000 1de 0ef 277 33b 39d 3ce 1e7 2f3
Figure 139. RX Bit Slip in 16-bit Mode tx_parallel_data
= 16'hfcbc
00010 rx_std_bitslipboundarysel rx_bitslip
00001 tx_parallel_data rx_parallel_data fcbc
979f cbcf
00011 e5e7
00100 f2f3
00101 f979
00110 fcbc
379 bc
3bc
Figure 140. RX Bit Slip in 20-bit Mode tx_parallel_data
= 20'h3fcbc rx_std_bitslipboundarysel rx_bitslip
00001 00010 tx_parallel_data rx_parallel_data
3fcbc e5e1f f2f0f
00011 f9787
00100 fcbc3
00101 de5e1
00110 ff2f0
00111
7f978
01000
3fcbc
2.9.2.4. RX Polarity Inversion
Receiver polarity inversion can be enabled in low latency, basic, and basic rate match modes.
To enable the RX polarity inversion feature, select the Enable RX polarity inversion and Enable rx_polinv port options.
This mode adds rx_polinv
. If there is more than one channel in the design, rx_polinv
is a bus in which each bit corresponds to a channel. As long as rx_polinv
is asserted, the RX data received has a reverse polarity.
You can verify this feature by monitoring rx_parallel_data
.
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Figure 141. RX Polarity Inversion rx_polinv tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus
11111100001110111100
11111100001...
01
00000011110001000011
11
11111100001110111100
2.9.2.5. RX Bit Reversal
The RX bit reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode, bit slip, manual, or synchronous state machine.
To enable this feature, select the Enable RX bit reversal and Enable
rx_std_bitrev_ena port options. This adds rx_std_bitrev_ena
. If there is more than one channel in the design, rx_std_bitrev_ena
becomes a bus in which each bit corresponds to a channel. As long as rx_std_bitrev_ena
is asserted, the RX data received by the core shows bit reversal.
You can verify this feature by monitoring rx_parallel_data
.
Figure 142. RX Bit Reversal rx_std_bitrev_ena tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus
11111100001110111100
11111100001110111100
01
11
00111101110000111111
00
11111100001110111100
01
2.9.2.6. RX Byte Reversal
The RX byte reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode.
To enable this feature, select the Enable RX byte reversal and Enable
rx_std_byterev_ena port options. This adds rx_std_byterev_ena
. If there is more than one channel in the design, rx_std_byterev_ena
becomes a bus in which each bit corresponds to a channel. As long as rx_std_byterev_ena
RX data received by the core shows byte reversal.
is asserted, the
You can verify this feature by monitoring rx_parallel_data
.
Figure 143. RX Byte Reversal rx_std_byterev_ena tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus
01
11
11111100001110111100
111111...
11101111001111110000
10
11111100001110111100
01
2.9.2.7. Rate Match FIFO in Basic (Single Width) Mode
Only the rate match FIFO operation is covered in these steps.
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1. Select basic (single width) in the RX rate match FIFO mode list.
2. Enter values for the following parameters.
Parameter
RX rate match insert/delete +ve pattern (hex)
RX rate match insert/delete –ve pattern (hex)
Value
20 bits of data specified as a hexadecimal string
20 bits of data specified as a hexadecimal string
Description
The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity.
The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity.
ve (volt encodes) are NRZ_L conditions where +ve encodes 0 and –ve encodes 1.
ve is a running disparity (+/–RD) specifically used with the rate matcher.
Depending on the ppm difference (which is defined by protocol) between the recovered clock and the local clock, the rate matcher adds or deletes a maximum of four skip patterns (neutral disparity). The net neutrality is conserved even after the skip word insertion or deletion because the control words alternate between positive and negative disparity.
In the following figure, the first skip cluster has a /K28.5/ control pattern followed by two /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control pattern followed by four /K28.0/ skip patterns. The rate match FIFO deletes only one /K28.0/ skip pattern from the first skip cluster to maintain at least one skip pattern in the cluster after deletion. Two /K28.0/ skip patterns are deleted from the second cluster for a total of three skip patterns deletion requirement.
The rate match FIFO can insert a maximum of four skip patterns in a cluster, if there are no more than five skip patterns in the cluster after insertion.
Figure 144. Rate Match FIFO Deletion with Three Skip Patterns Required for Deletion
First Skip Cluster Second Skip Cluster
K28.0
K28.0
tx_parallel_data rx_parallel_data
K28.5
K28.5
K28.0
K28.0
K28.0
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
Three Skip Patterns Deleted
Note: /K28.5/ is the control pattern and /K28.0/ is the skip pattern
In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a /K28.5/ control pattern followed by three /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control pattern followed by two /K28.0/ skip patterns. The rate match FIFO inserts only two /
K28.0/ skip patterns into the first skip cluster to maintain a maximum of five skip patterns in the cluster after insertion. One /K28.0/ skip pattern is inserted into the second cluster for a total of three skip patterns to meet the insertion requirement.
Figure 145. Rate Match FIFO Insertion with Three Skip Patterns Required for Insertion
First Skip Cluster Second Skip Cluster tx_parallel_data K28.5
K28.0
K28.0
K28.0
K28.5
K28.0
K28.0
Dx.y
rx_parallel_data K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
K28.5
K28.0
K28.0
K28.0
Dx.y
Three Skip Patterns Inserted
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The following figure shows the deletion of D5 when the upstream transmitter reference clock frequency is greater than the local receiver reference clock frequency. It asserts deletion takes place.
rx_std_rmfifo_full
for one parallel clock cycle while the
Figure 146. Rate Match FIFO Becoming Full After Receiving D5 tx_parallel_data D1 D2 D3 D4 D5 D6 rx_parallel_data D1 D2 D3 D4 D6 D7
D7
D8
D8 xx xx xx rx_std_rmfifo_full
The following figure shows the insertion of skip symbols when the local receiver reference clock frequency is greater than the upstream transmitter reference clock frequency. It asserts rx_std_rmfifo_empty
for one parallel clock cycle while the insertion takes place.
Figure 147. Rate Match FIFO Becoming Empty After Receiving D3 tx_parallel_data D1 D2 D3 D4 D5 D6 rx_parallel_data D1 D2 D3 /K30.7/ D4 D5 rx_std_rmfifo_empty
2.9.2.8. Rate Match FIFO Basic (Double Width) Mode
1. Select basic (double width) in the RX rate match FIFO mode list.
2. Enter values for the following parameters.
Parameter
RX rate match insert/delete +ve pattern (hex)
RX rate match insert/delete -ve pattern (hex)
Value
20 bits of data specified as a hexadecimal string
20 bits of data specified as a hexadecimal string
Description
The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity.
The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity.
The rate match FIFO can delete as many pairs of skip patterns from a cluster as necessary to avoid the rate match FIFO from overflowing. The rate match FIFO can delete a pair of skip patterns only if the two 10-bit skip patterns appear in the same clock cycle on the LSByte and MSByte of the 20-bit word. If the two skip patterns appear straddled on the MSByte of a clock cycle and the LSByte of the next clock cycle, the rate match FIFO cannot delete the pair of skip patterns.
In the following figure, the first skip cluster has a /K28.5/ control pattern in the
LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle followed by one /
K28.0/ skip pattern in the LSByte of the next clock cycle. The rate match FIFO cannot delete the two skip patterns in this skip cluster because they do not appear in the same clock cycle. The second skip cluster has a /K28.5/ control pattern in the MSByte of a clock cycle followed by two pairs of /K28.0/ skip patterns in the next two cycles. The rate match FIFO deletes both pairs of /K28.0/ skip patterns
(for a total of four skip patterns deleted) from the second skip cluster to meet the three skip pattern deletion requirement.
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The rate match FIFO can insert as many pairs of skip patterns into a cluster necessary to avoid the rate match FIFO from under running. The 10-bit skip pattern can appear on the MSByte, the LSByte, or both, of the 20-bit word.
Figure 148. Rate Match FIFO Deletion with Four Skip Patterns Required for Deletion
/K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern.
First Skip Cluster Second Skip Cluster
Two Pairs of Skip
Patterns Deleted tx_parallel_data[19:10] tx_parallel_data[9:0] rx_parallel_data[19:0]
Dx.y
Dx.y
Dx.y
K28.0
K28.5
K28.0
Dx.y
K28.0
Dx.y
K28.5
Dx.y
K28.5
K28.0
K28.0
Dx.y
K28.0
K28.0
Dx.y
Dx.y
rx_parallel_data[9:0] Dx.y
K28.5
K28.0
Dx.y
Dx.y
In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a /K28.5/ control pattern in the
LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle. The rate match
FIFO inserts pairs of skip patterns in this skip cluster to meet the three skip pattern insertion requirement.
Figure 149. Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion
First Skip Cluster Second Skip Cluster tx_parallel_data[19:10] tx_parallel_data[9:0] rx_parallel_data[19:0] rx_parallel_data[9:0]
Dx.y
Dx.y
Dx.y
Dx.y
K28.0
K28.5
K28.0
K28.5
Dx.y
Dx.y
K28.0
K28.0
K28.5
Dx.y
K28.0
K28.0
K28.0
K28.0
Dx.y
Dx.y
K28.0
K28.0
K28.5
Dx.y
K28.0
K28.0
K28.0
K28.0
The following figure shows the deletion of the 20-bit word D7D8.
Figure 150. Rate Match FIFO Becoming Full After Receiving the 20-Bit Word D5D6 tx_parallel_data[19:0] D2 D4 D6 D8 D10 D12 tx_parallel_data[9:0] D1 D3 D5 D7 D9 D11 rx_parallel_data[19:10] rx_parallel_data[9:0]
D2
D1
D4
D3
D6
D5
D10
D9
D12
D11 xx xx rx_std_rmfifo_full
The following figure shows the insertion of two skip symbols.
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Figure 151. Rate Match FIFO Becoming Empty After Reading out the 20-Bit Word D5D6 tx_parallel_data[19:0] D2 D4 D6
D8 D10
D12 tx_parallel_data[9:0] D1 D3 D5
D7
D9 D11 rx_parallel_data[19:10] rx_parallel_data[9:0]
D2
D1
D4
D3
D6
D5
/K30.7/
/K30.7/
D8
D7
D10
D9 rx_std_rmfifo_empty
2.9.2.9. 8B/10B Encoder and Decoder
To enable the 8B/10B Encoder and the 8B/10B Decoder, select the Enable TX
8B/10B Encoder and Enable RX 8B/10B Decoder options on the Standard PCS tab in the IP Editor. Platform Designer (Standard) allows implementing the 8B/10B decoder in RX-only mode.
The following ports are added:
• tx_datak
• rx_datak
• rx_runningdisp
• rx_disperr
• rx_errdetect rx_datak
and tx_datak
indicate whether the parallel data is a control word or a data word. The incoming 8-bit data ( tx_parallel_data
) and the control identifier
( tx_datak
) are converted into a 10-bit data. After a power on reset, the 8B/10B encoder takes the 10-bit data from the RD- column. Next, the encoder chooses the
10-bit data from the RD+ column to maintain neutral disparity. The running disparity is shown by rx_runningdisp
.
2.9.2.10. 8B/10B TX Disparity Control
The Disparity Control feature controls the running disparity of the output from the
8B/10B Decoder.
To enable TX Disparity Control, select the Enable TX 8B/10B Disparity Control option. The following ports are added:
• tx_forcedisp be forced or not
—a control signal that indicates whether a disparity value has to
• tx_dispval being forced
—a signal that indicates the value of the running disparity that is
When the number of data channels is more than 1, tx_forcedisp
and tx_dispval are shown as buses in which each bit corresponds to one channel.
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The following figure shows the current running disparity being altered in Basic singlewidth mode by forcing a positive disparity /K28.5/ when it was supposed to be a negative disparity /K28.5/. In this example, a series of /K28.5/ code groups are continuously being sent. The stream alternates between a positive running disparity
(RD+) /K28.5/ and a negative running disparity (RD-) /K28.5/ to maintain a neutral overall disparity. The current running disparity at time n + 3 indicates that the /K28.5/ in time n + 4 should be encoded with a negative disparity. Because tx_forcedisp
is high at time n + 4, and tx_dispval positive disparity code group.
is low, the /K28.5/ at time n + 4 is encoded as a
Figure 152. 8B/10B TX Disparity Control n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 clock tx_in[7:0] tx_ctrlenable tx_forcedisp tx_dispval
Current Running Disparity dataout[9:0]
BC
RD–
17C
BC
RD+
283
BC
RD–
17C
BC
RD+
283
BC
RD+
283
BC
RD–
17C
BC
RD+
283
BC
RD–
17C
2.9.2.11. How to Enable Low Latency in Basic
In the Arria 10 Transceiver Native PHY IP Parameter Editor, use the following settings to enable low latency:
1. Select the Enable 'Standard PCS' low latency mode option.
2. Select either low_latency or register FIFO in the TX FIFO mode list.
3. Select either low_latency or register FIFO in the RX FIFO mode list.
4. Select either Disabled or Serialize x2 in the TX byte serializer mode list.
5. Select either Disabled or Serialize x2 in the RX byte deserializer mode list.
6. Ensure that RX rate match FIFO mode is disabled.
7. Set the RX word aligner mode to bitslip.
8. Set the RX word aligner pattern length to 7 or 16.
Note: TX bitslip, RX bitslip, bit reversal, and polarity inversion modes are supported.
2.9.2.12. TX Bit Slip
To use the TX bit slip, select the Enable TX bitslip and Enable
tx_std_bitslipboundarysel port options. This adds the tx_std_bitslipboundarysel
input port. The TX PCS automatically slips the number of bits specified by tx_std_bitslipboundarysel bit slip. If there is more than one channel in the design,
. There is no port for TX tx_std_bitslipboundarysel
ports are multiplied by the number of channels. You can verify this feature by monitoring the tx_parallel_data
port.
Enabling the TX bit slip feature is optional.
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Note: The rx_parallel_data
values in the following figures are based on the TX and RX bit reversal features being disabled.
Figure 153. TX Bit Slip in 8-bit Mode tx_parallel_data
= 8'hbc. tx_std_bitslipboundarysel
= 5'b00001 (bit slip by 1 bit).
tx_std_bitslipboundarysel tx_parallel_data rx_parallel_data
00001 bc
79
Figure 154. TX Bit Slip in 10-bit Mode tx_parallel_data
= 10'h3bc. tx_std_bitslipboundarysel
= 5'b00011 (bit slip by 3 bits).
tx_std_bitslipboundarysel tx_parallel_data rx_parallel_data
00011
3bc
1e7
Figure 155. TX Bit Slip in 16-bit Mode tx_parallel_data
= 16'hfcbc. tx_std_bitslipboundarysel
=5'b00011 (bit slip by 3 bits).
tx_std_bitslipboundarysel tx_parallel_data rx_parallel_data
00011 fcbc
5e7f
Figure 156. TX Bit Slip in 20-bit Mode tx_parallel_data
= 20'hF3CBC. tx_std_bitslipboundarysel
= 5'b00111 (bit slip by 7 bits).
tx_std_bitslipboundarysel tx_parallel_data rx_parallel_data
00111 f3cbc e5e1f
2.9.2.13. TX Polarity Inversion
The positive and negative signals of a serial differential link might accidentally be swapped during board layout. Solutions such as a board respin or major updates to the PLD logic can be expensive. The transmitter polarity inversion feature is provided to correct this situation.
Transmitter polarity inversion can be enabled in low latency, basic, and basic rate match modes.
To enable TX polarity inversion, select the Enable tx_polinv port option in Platform
Designer (Standard). It can also be dynamically controlled with dynamic reconfiguration.
This mode adds tx_polinv
. If there is more than one channel in the design, tx_polinv
is a bus with each bit corresponding to a channel. As long as tx_polinv is asserted, the TX data transmitted has a reverse polarity.
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2.9.2.14. TX Bit Reversal
The TX bit reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode. This feature is parameter-based, and creates no additional ports. If there is more than one channel in the design, all channels have TX bit reversal.
To enable TX bit reversal, select the Enable TX bit reversal option in Platform
Designer (Standard). It can also be dynamically controlled with dynamic reconfiguration.
Figure 157. TX Bit Reversal tx_parallel_data rx_parallel_data
11111100001110111100
00000...
00111101110000111111
2.9.2.15. TX Byte Reversal
The TX byte reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode. This feature is parameterbased, and creates no additional ports. If there is more than one channel in the design, all channels have TX byte reversal.
To enable TX byte reversal, select the Enable TX byte reversal option in Platform
Designer (Standard). It can also be dynamically controlled with dynamic reconfiguration.
Figure 158. TX Byte Reversal tx_parallel_data rx_parallel_data
11111100001110111100
00000000... 11101111001111110000
2.9.2.16. How to Implement the Basic, Basic with Rate Match Transceiver
Configuration Rules in Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing your Basic protocol IP.
1. Open the IP Catalog and select the Native PHY IP.
Refer to Select and Instantiate the PHY IP Core on page 33.
2. Select Basic/Custom (Standard PCS) or Basic/Custom w/Rate Match
(Standard PCS) from the Transceiver configuration rules list located under
Datapath Options depending on which configuration you want to use.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameter
Settings for the Basic Protocol
as a starting point. Or, you can use the protocol
presets described in Transceiver Native PHY Presets
. You can then modify the setting to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
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Figure 159. Signals and Ports of Native PHY IP for Basic, Basic with Rate Match
Configurations
Arria 10 Transceiver Native PHY
Reconfiguration
Registers
Nios Hard
Calibration IP tx_cal_busy rx_cal_busy reconfig_reset reconfig_clk reconfig_avmm tx_digital_reset tx_datak tx_parallel_data[7:0] tx_clkout
TX Standard PCS tx_datak tx_parallel_data[7:0] tx_coreclkin tx_clkout unused_tx_parallel_data[118:0]
10
TX PMA
Serializer tx_serial_data
Central/Local
Clock Divider tx_serial_clk0 (from TX PLL) tx_analog_reset rx_analog_reset rx_digital_reset rx_datak rx_parallel_data[7:0] rx_clkout rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus rx_rmfifostatus (1)
RX Standard PCS rx_datak rx_parallel_data[7:0] rx_clkout rx_coreclkin rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus rx_rmfifostatus (1) unused_rx_parallel_data[113:0]
10
RX PMA
Deserializer CDR rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref
Note:
1. Only applies when using the Basic with Rate Match transceiver configuration rule.
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller.
7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the
information in Transceiver Native PHY Ports for the Protocol
to connect the ports.
Figure 160. Connection Guidelines for a Basic/Custom Design pll_ref_clk reset
Pattern
Generator tx_parallel_data tx_datak tx_clkout tx_serial_data rx_serial_data rx_cdr_refclk
PLL IP tx_serial_clk pll_locked pll_powerdown rx_ready tx_ready clk reset reset
Reset
Controller
Pattern
Checker tx_digital_reset tx_analog_reset rx_digital_reset rx_analog_reset rx_is_lockedtoref rx_is_lockedtodata rx_parallel_data rx_datak rx_clkout
Arria 10
Transceiver
Native
PHY reconfig_clk reconfig_reset reconfig_write reconfig_read reconfig_address reconfig_writedata reconfig_readdata reconfig_waitrequest cal_busy
For
Reconfiguration
8. Simulate your design to verify its functionality.
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Related Information
•
Arria 10 Standard PCS Architecture
on page 479
For more information about Standard PCS architecture
•
Arria 10 PMA Architecture on page 447
For more information about PMA architecture
•
on page 398
For more information about implementing PLLs and clocks
•
PLL architecture and implementation details
•
Resetting Transceiver Channels
on page 416
Reset controller general information and implementation details
•
Port definitions for the Transceiver Native PHY Standard Datapath
2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match
Configurations
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Table 217.
General and Datapath Options Parameters
Parameter
Message level for rule violations
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Range error warning
Basic/Custom (Standard PCS)
Basic/Custom w/Rate Match (Standard
PCS) basic
TX/RX Duplex
TX Simplex
RX Simplex
1
to
96
611
Mbps to
12
Gbps
On/Off
On/Off
Table 218.
TX PMA Parameters
Parameter
TX channel bonding mode
PCS TX channel bonding master
Actual PCS TX channel bonding master
Range
Not bonded
PMA-only bonding
PMA and PCS bonding
Auto, n-1 (where n = the number of data channels)
n-1 (where n = the number of data channels) continued...
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Parameter
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Enable tx_pma_qpipulldn port (QPI)
Enable tx_pma_txdetectrx port (QPI)
Enable tx_pma_rxfound port (QPI)
Enable rx_seriallpbken port
Table 219.
RX PMA Parameters
Parameter
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
DFE adaptation mode
Number of fixed dfe taps
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_pma_qpipulldn port (QPI)
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
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Range
1, 2, 4, 8
1, 2, 3, 4
0 (Depends on the Number of TX PLL clock
inputs per channel value)
On/Off
On/Off
Disabled, 1, 2, 33, 40, 66
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Range
1, 2, 3, 4, 5
0, 1, 2, 3, 4
Legal range defined by Quartus Prime software
100, 300, 500, 1000 manual disabled
3, 7
On/Off
On/Off
Disabled, 1, 2, 33, 40, 50, 66
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
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Table 220.
Standard PCS Parameters
Parameter
Standard PCS / PMA interface width
FPGA fabric / Standard TX PCS interface width
FPGA fabric / Standard RX PCS interface width
Enable 'Standard PCS' low latency mode
TX FIFO mode
RX FIFO Mode
Enable tx_std_pcfifo_full port
Enable tx_std_pcfifo_empty port
Enable rx_std_pcfifo_full port
Enable rx_std_pcfifo_empty port
TX byte serializer mode
RX byte deserializer mode
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
RX rate match FIFO mode
RX rate match insert/delete -ve pattern (hex)
RX rate match insert/delete +ve pattern (hex)
Enable rx_std_rmfifo_full port
Enable rx_std_rmfifo_empty port
PCI Express* Gen 3 rate match FIFO mode
Enable TX bit slip
Enable tx_std_bitslipboundarysel port
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Number of word alignment patterns to achieve sync
Range
8, 10, 16, 20
8, 10, 16, 20, 32, 40
8, 10, 16, 20, 32, 40
On/Off
Off (for Basic with Rate Match) low_latency register_fifo fast_register low_latency register_fifo
On/Off
On/Off
On/Off
On/Off
Disabled
Serialize x2
Serialize x4
Disabled
Deserialize x2
Deserialize x4
On/Off
On/Off
On/Off
Disabled
Basic 10-bit PMA (for Basic with Rate Match)
Basic 20-bit PMA (for Basic with Rate Match)
User-defined value
User-defined value
On/Off
On/Off
Bypass
On/Off
On/Off bitslip manual (PLD controlled) synchronous state machine
7, 8, 10, 16, 20, 32, 40
User-defined value
0-255 continued...
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Parameter
Number of invalid data words to lose sync
Number of valid data words to decrement error count
Enable fast sync status reporting for deterministic latency SM
Enable rx_std_wa_patternalign port
Enable rx_std_wa_a1a2size port
Enable rx_std_bitslipboundarysel port
Enable rx_bitslip port
Enable TX bit reversal
Enable TX byte reversal
Enable TX polarity inversion
Enable tx_polinv port
Enable RX bit reversal
Enable rx_std_bitrev_ena port
Enable RX byte reversal
Enable rx_std_byterev_ena port
Enable RX polarity inversion
Enable rx_polinv port
Enable rx_std_signaldetect port
Enable PCIe dynamic datarate switch ports
Enable PCIe pipe_hclk_in and pipe_hclk_out ports
Enable PCIe Gen 3 analog control ports
Enable PCIe electrical idle control and status ports
Enable PCIe pipe_rx_polarity port
Table 221.
Dynamic Reconfiguration Parameters
Parameter
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
Range
On/Off
On/Off
On/Off
Table 222.
Generation Options Parameters
Parameter
Generate parameter documentation file
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
on page 45
Range
On/Off
Off
Off
Off
Off
Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Range
0-63
0-255
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
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2.9.3. Design Considerations for Implementing Arria 10 GT Channels
This section provides information on using the Arria 10 GT transceiver channels .
GT channels can be used in Enhanced PCS basic mode and PCS-Direct configuration to support 25.8 Gbps. When GT channels are used in PCS-Direct configuration, the PCS blocks are bypassed. The serializer/deserializer in GT channels supports 64 bit and
128 bit serialization factors.
2.9.3.1. Transceiver PHY IP
Arria 10 GT transceiver channels are implemented using the Native PHY IP with the
Basic (Enhanced PCS) transceiver configuration rule.
• To support 25.8 Gbps, the Enhanced PCS must be configured in basic mode with the low latency check box unselected. To configure the Enhanced PCS, do not enable any functional blocks in the Enhanced PCS (that is, disable Block
Synchronizer, Gearbox, Scrambler, and Encoder).
• You can also use the PCS-Direct mode for 25.8 Gbps.
You can bundle several GT transceiver channels with one Native PHY IP instantiation, but you must instantiate a separate ATX PLL IP for every ATX PLL used.
2.9.3.2. PLL and GT Transceiver Channel Clock Lines
The ATX PLL is used to provide the clock source for the GT transceiver channels. Each
ATX PLL has two dedicated GT clock lines which connect the PLL directly to the GT transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and
4, and the bottom ATX PLL drives channels 0 and 1. These connections bypass the rest of the clock network for higher performance.
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Figure 161. GT Channel Configuration
Ch 5
CGB
CDR
Ch 4
CGB
ATX PLL1
CMU or CDR
Ch 3
CGB
CDR
Ch 2
CGB
CDR
Ch 1
CGB
ATX PLL0
CMU or CDR
Ch 0
CGB
CDR
When both the channels 0 and 1 are configured as GT channels, they are driven by the same ATX PLL and have to be configured to run at the same data rates. This is also true for channels 3 and 4 when they are configured as GT channels.
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Note: • GT channel bonding is not supported.
• For optimum performance of GT channel, the reference clock of ATX PLL is recommended to be from a dedicated reference clock pin in the same bank.
Related Information
Input Reference Clock Sources on page 372
2.9.3.3. Reset Controller
Each GT channel instantiated has independent analog and digital reset ports. Refer to the Resetting Transceiver Channels chapter for more details on designing a reset controller to reset these ports.
Related Information
Resetting Transceiver Channels
on page 416
Reset controller general information and implementation details
2.9.3.4. How to Implement Designs for Data Rates Above 17.4 Gbps Using
Enhanced PCS in Low Latency Mode
• You should be familiar with the Enhanced PCS and PMA architecture, PLL architecture, and the reset controller.
• Make sure you have selected an Arria 10 GT device for the project
1. Select Tools
➤
IP Catalog
➤
Interface Protocols
➤
Transceiver PHY
➤
Arria
10 Transceiver Native PHY. Refer to Select and Instantiate the PHY IP Core on
page 33 for detailed steps.
2. Set VCCR_GXB and VCCT_GXB to 1.1V. Note these settings are overridden by the QSF file settings which should also be set to 1.1V. QII makes sure the actual voltage prescribed is in line with pin connection guidelines and the Arria10 Data
Sheet.
3. Select Basic (Enhanced PCS) from the Transceiver configuration rules list located under Datapath Options.
4. Use the parameter values in the tables in Transceiver Native PHY IP Parameters
Settings for Basic (Enhanced PCS) and Basic with KR FEC for each input of the
Arria 10 Transceiver Native PHY Parameter Editor as a starting point. Or, you can
use the protocol presets described in Transceiver Native PHY Presets
. You can then modify the settings to meet your specific requirements.
• Ensure that the data rate is set to 25781.25 Mbps. To achieve the higher data rates, use Enhanced PCS basic mode with the low latency option unchecked.
Select a CDR reference clock to match your data rate. Use Phase compensation FIFO modes.
• Make sure DFE is disabled from Rx PMA settings.
• Set the Enhanced PCS / PMA interface width to 64 bits.
• Set the FPGA fabric / Enhanced PCS interface width to 64 bits.
• You can enable RX/TX FIFO double width mode to create a FPGA fabric / PCS interface width of 128 bits.
• Click Finish to generate the Native PHY IP (this is your RTL file).
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Figure 162. Signals and Ports of the Native PHY for Basic (Enhanced PCS) Transceiver
Configuration Rule for Data Rates Above 17.4 Gbps and FPGA Fabric / PCS
Interface width of 128 bits tx_cal_busy rx_cal_busy
NIOS
Hard Calibration IP
Reconfiguration
Registers reconfig_reset reconfig_clk reconfig_avmm tx_serial_data
TX PMA
Serializer
TX Enhanced PCS tx_digital_reset tx_control[17:0] tx_parallel_data[127:0] tx_coreclkin tx_clkout tx_enh_data_valid tx_digital_reset tx_control[17:0] tx_parallel_data[127:0] tx_coreclkin tx_clkout tx_enh_data_valid tx_serial_clk0
(from TX PLL) tx_analog_reset rx_analog_reset
RX PMA
Deserializer
RX Enhanced PCS rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref
CDR rx_digital_reset rx_clkout rx_coreclkin rx_parallel_data[127:0] rx_control[19:0] rx_digital_reset rx_clkout rx_coreclkin rx_parallel_data[127:0] rx_control[19:0] refclk
5. Select Tools ➤ IP Catalog ➤ Basic Functions ➤ Clocks ➤ PLLs and Resets ➤
PLL ➤ Arria 10 Transceiver ATX PLL. Refer to
Instantiating the ATX PLL IP Core
on page 354 for detailed steps.
6. Configure the ATX PLL IP using the Parameter Editor.
• Select the GT clock output buffer.
• Enable the PLL GT clock output port.
• Set the PLL output clock frequency to the Native PHY IP recommended frequency.
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Figure 163. ATX PLL IP with GT Clock Lines Enabled
7. Create a transceiver reset controller. Refer to Resetting Transceiver Channels on
page 416 for more details about configuring the reset IP core.
8. Connect the Native PHY IP core to the PLL IP core and the reset controller.
The ATX PLL's port tx_serial_clk_gt
represents the dedicated GT clock lines.
Connect this port to the Native PHY IP core's tx_serial_clk0
port. The Quartus
Prime software automatically uses the dedicated GT clocks instead of the x1 clock network.
2.9.3.5. Arria 10 GT Channel Usage
All Arria 10 GT devices have a total of six GT transceiver channels to support 25.8
Gbps.
Arria 10 GT devices have three transceiver banks that support up to two GT channels.
Each channel can operate as a duplex channel, TX only, or RX only channel.
Transceiver banks GXBL1E and GXBL1H each contain two GT transceiver channels:
Ch3 and Ch4. Transceiver bank GXBL1G contains two GT transceiver channels: Ch0 and Ch1. Channels 2 and 5 on any bank can only be configured as GX transceiver channels.
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Table 223.
Valid Permutations for GT and GX Channel Configuration in Transceiver Bank
GXBL1G for Channels 0, 1, and 2
GT Transceiver Channel
Ch2
Ch1
Ch0
Configuration A
Unusable
GT
GT
Configuration B
Unusable
GT
Unusable
Configuration C
Unusable
Unusable
GT
Configuration D
GX
GX
GX
Notes on grouping channels Ch0, Ch1, and Ch2:
• If channels 0 and 1 are configured as GT channels, channel 2 is unusable
(Configuration A).
• If either channel 0 or 1 is configured as a GT channel, the remaining channels are unusable (Configurations B and C).
• If channels 0 and 1 are not configured as GT channels, this grouping can be all configured as GX channels (Configuration D).
• If either channel 0 or 1 is used as a GT channel, then the ATX PLL adjacent to channel 0 and 1 must be reserved for GT channel configurations.
Table 224.
Valid Permutations for GT and GX Channel Configuration in Transceiver Banks
GXBL1E and GXBL1H for Channels 3, 4, and 5
GT Transceiver Channel
Ch5
Ch4
Ch3
Configuration A
Unusable
GT
GT
Configuration B
Unusable
GT
Unusable
Configuration C
Unusable
Unusable
GT
Configuration D
GX
GX
GX
Notes on grouping channels Ch3, Ch4, and Ch5:
• If channels 3 and 4 are configured as GT channels, channel 5 is unusable
(Configuration A).
• If either channel 3 or 4 is configured as a GT channel, the remaining channels are unusable (Configurations B and C).
• If channels 3 and 4 are not configured as GT channels, this grouping can be all configured as GX channels (Configuration D).
• If either channel 3 or 4 is used as a GT channel, then the ATX PLL adjacent to channel 3 and 4 must be reserved for GT channel configurations.
2.9.4. How to Implement PCS Direct Transceiver Configuration Rule
You should be familiar with PCS Direct architecture, PMA architecture, PLL architecture, and the reset controller before implementing PCS Direct Transceiver
Configuration Rule.
1. Open the IP Catalog and select Arria 10 Transceiver Native PHY IP. Refer to
Select and Instantiate the PHY IP Core on page 33 for detailed steps.
2. Select PCS Direct from the Transceiver configuration rules list located under
Datapath Options.
3. Configure your Native PHY IP.
4. Click Generate to generate the Native PHY IP (this is your RTL file).
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5. Instantiate and configure your PLL.
6. Create a transceiver reset controller. You can use your own controller or use the
Transceiver PHY Reset Controller.
7. Connect the Native PHY IP to the PLL IP and the reset controller.
Figure 164. Connection Guidelines for a PCS Direct PHY Design pll_refclk PLL IP Core clk reset pll_sel pll_locked
Reset Controller tx_ready rx_ready pll_cal_busy rx_cdr_refclk tx_serialclk0
Data
Generator tx_clkout tx_parallel_data
Data
Verifier rx_clkout rx_parallel_data
Arria 10 Transceiver Native PHY tx_serial_data rx_serial_data
8. Simulate your design to verify its functionality.
2.10. Simulating the Transceiver Native PHY IP Core
Use simulation to verify the Native PHY transceiver functionality. The Quartus Prime software supports register transfer level (RTL) and gate-level simulation in both
ModelSim - Intel FPGA Edition and third-party simulators. You run simulations using your Quartus Prime project files.
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The following simulation flows are available:
• NativeLink—This flow simplifies simulation by allowing you to start a simulation from the Quartus Prime software. This flow automatically creates a simulation script and compiles design files, IP simulation model files, and Intel simulation library models.
Note: The Quartus Prime Pro Edition software does not support NativeLink RTL simulation
• Scripting IP Simulation—In this flow you perform the following actions:
1. Run the ip-setup-simulation utility to generate a single simulation script that compiles simulation files for all the underlying IPs in your design. This script needs to be regenerated whenever you upgrade or modify IPs in the design.
2. You create a top-level simulation script for compiling your testbench files and simulating the testbench. It sources the script generated in the first action.
You do not have to modify this script even if you upgrade or modify the IPs in your design.
• Custom Flow—This flow allows you to customize simulation for more complex requirements. You can use this flow to compile design files, IP simulation model files, and Intel simulation library models manually.
You can simulate the following netlist:
• The RTL functional netlist—This netlist provides cycle-accurate simulation using
Verilog HDL, SystemVerilog, and VHDL design source code. Intel and third-party
EDA vendors provide the simulation models.
Prerequisites to Simulation
Before you can simulate your design, you must have successfully passed Quartus
Prime Analysis and Synthesis.
Related Information
Simulating Intel FPGA Designs
2.10.1. NativeLink Simulation Flow
The NativeLink settings available in the Quartus Prime software allow you to specify your simulation environment, simulation scripts, and testbenches. The Quartus Prime software saves these settings in your project. After you specify the NativeLink settings, you can start simulations easily from the Quartus Prime software.
2.10.1.1. How to Use NativeLink to Specify a ModelSim Simulation
Complete the following steps to specify the directory path and testbench settings for your simulator:
1. On the Tools menu, click Options, and then click EDA Tool Options.
2. Browse to the directory for your simulator. The following table lists the directories for supported simulators:
Table 225.
Simulator Path
Simulator
Mentor Graphics* ModelSim - Intel FPGA Edition
Path
<drive>:\<simulator install path>\win32aloem (Windows)
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Simulator Path
/<simulator install path>/bin (Linux*)
3. On the Assignments menu, click Settings.
4. In the Category list, under EDA Tool Settings select Simulation.
5. In the Tool name list, select your simulator.
Note: ModelSim refers to ModelSim SE and PE. These simulators use the same commands as QuestaSim.ModelSim - Intel FPGA Edition refers to ModelSim - Intel
FPGA Edition Starter Edition and ModelSim - Intel FPGA Edition Subscription
Edition.
6. In the Output directory, browse to the directory for your output files.
7. To map illegal HDL characters, turn on Map illegal HDL characters.
8. To filter netlist glitches , turn on Enable glitch filtering.
9. Complete the following steps to specify additional options for NativeLink automation: a. Turn on Compile test bench.
b. Click Test Benches.
The Test Benches dialog box appears.
c. Click New.
d. Under Create new test bench settings, for Test bench name type the test bench name. For Top level module in the test bench, type the top-level module name. These names should match the actual test bench module names.
e. Select Use test bench to perform VHDL timing simulation and specify the name of your design instance under Design instance name in test bench.
f.
Under the Simulation period, turn on Run simulation until all vector
stimuli are used.
g. Under Test bench and simulation files, select your test bench file from your folder. Click Add.
h. Click OK.
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2.10.1.2. How to Use NativeLink to Run a ModelSim RTL Simulation
Figure 165. NativeLink Simulation Flow Diagram
Specify EDA Simulator &
Simulator Directory
Run RTL Functional or
Gate-Level Simulation
Does
Simulation Give
Expected Results?
No
Debug Design &
Make RTL Changes
Yes
Run Quartus Prime
Analysis and Elaboration
Define Control Signals Using
In-System Sources & Probes
Run Simulation
No
Does
Simulation Give
Expected Results?
Yes
Simulation Complete
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Complete the following steps to run an RTL functional simulation:
1. Open your Quartus Prime project.
2. On the Tools menu, select Run Simulation Tool, then select RTL Simulation or
Gate Level Simulation.
3. Run Quartus Prime Analysis and Elaboration and re-instantiate control signals that you defined using the In-System Sources and Probe Editor. The In-System Sources and Probe Editor can only access the pins of the device. Consequently, you must route any signal that you want to observe to the top-level of your design.
4. To monitor additional signals, highlight the desired instances or nodes in
Instance, and right-click Add wave.
5. Select Simulate and then Run.
6. Specify the simulation duration.
7. Complete the following steps to restart the simulation: a. On the Simulate menu, select restart, then click ok.
This action clears the existing waves.
b. Highlight run and select the appropriate options to run the simulation.
Related Information
Simulating the Transceiver Native PHY IP Core on page 325
2.10.1.3. How to Use NativeLink to Specify Third-Party RTL Simulators
The following figure illustrates the high-level steps for using the NativeLink with Third-
Party EDA RTL simulator.
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Figure 166. Using NativeLink with Third-Party Simulators
Specify EDA Simulator &
Simulator Directory
Perform
Functional Simulation
Does
Simulation Give
Expected Results?
No
Debug Design &
Make RTL Changes
Yes
Run Quartus Prime
Analysis and Elaboration
Start Simulator, Compile
Design and Testbench
Load Design &
Run Simulation
No
Does
Simulation Give
Expected Results?
Yes
Simulation Complete
Complete the following steps to specify the directory path and testbench settings for your simulator:
1. On the Tools menu, click Options, and then click EDA Tool Options.
2. Browse to the directory for your simulator. The following table lists the directories for supported third-party simulators:
Table 226.
Simulator Path
Simulator
Mentor Graphics ModelSim
Mentor Graphics QuestaSim*
Synopsys VCS/VCS MX
Cadence Incisive Enterprise
Aldec Active-HDL
Aldec Riviera-Pro
Path
<drive>:\<simulator install path>\win32 (Windows)
/<simulator install path>/bin (Linux)
/<simulator install path>/bin (Linux)
/<simulator install path>/tools/bin (Linux)
<drive>:\<simulator install path>\bin (Windows)
/<simulator install path>/bin (Linux)
3. On Assignments menu, click Settings.
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4. In the Category list, under EDA Tool Settings, select Simulation.
5. In the Tool name list, select your simulator.
6. To enable your simulator, on the Tools menu, click Options and then click
License Setup . Make necessary changes for EDA tool licenses.
7. Compile your design and testbench files.
8. Load the design and run the simulation in the EDA tool.
To learn more about third-party simulators, click on the appropriate link below.
Related Information
• Mentor Graphics ModelSim and QuestaSim Support
• Synopsys VCS and VCS MX Support
• Cadence Incisive Enterprise Simulator Support
• Aldec Active-HDL and Riviera-Pro Support
2.10.2. Scripting IP Simulation
The Intel Quartus Prime software supports the use of scripts to automate simulation processing in your preferred simulation environment. You can use your preferred scripting methodology to control simulation.
Intel recommends the use of a version-independent top-level simulation script to control design, testbench, and IP core simulation. Because Quartus Prime-generated simulation file names may change.
You can use the ip-setup simulation utility to generate or regenerate underlying setup scripts after any software or IP version upgrade or regeneration. Use of a top-level script and ip-setup-simulation eliminates the requirement to manually update simulation scripts.
2.10.2.1. Generating a Combined Simulator Setup Script
Platform Designer (Standard) system generation creates the interconnect between components. It also generates files for synthesis and simulation, including the .spd files necessary for the ip-setup-simulation utility.
The Intel Quartus Prime software provides utilities to help you generate and update IP simulation scripts. You can use the ip-setup-simulation utility to generate a combined simulator setup script, for all Intel FPGA IP in your design, for each supported simulator. You can subsequently rerun ip-setup-simulation to automatically update the combined script. Each simulator's combined script file contains a rudimentary template that you can adapt for integration of the setup script into a top-level simulation script.
Related Information
Intel Quartus Prime Standard Edition Handbook Volume 3: Verification
Provides more information about the steps to generate top-level simulation script.
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2.10.3. Custom Simulation Flow
The custom simulation flow allows you to customize the simulation process for more complex simulation requirements. This flow allows you to control the following aspects of your design:
• Component binding
• Compilation order
• Run commands
• IP cores
• Simulation library model files
The following figure illustrates the steps for custom flow simulation. If you use a simulation script, you can automate some of the steps.
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Figure 167. Custom flow Simulation
Compile Sim Model Libs
Using Sim Lib Compiler
Start Simulator & Open
Quartus Prime Project
Compile Design, Testbench,
& Simulation Libraries
Load Design
& Run Simulation
Does
Simulation Give
Expected Results?
No
Debug Design &
Make RTL Changes
Yes
Compile Design, Testbench,
& Simulation Libraries
Load Design &
Run Simulation
No
Does
Simulation Give
Expected Results?
Yes
Simulation Complete
2.10.3.1. How to Use the Simulation Library Compiler
The Simulation Library Compiler compiles Intel simulation libraries for supported simulation tools, and saves the simulation files in the output directory you specify.
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Note: Because the ModelSim - Intel FPGA Edition software provides precompiled simulation libraries, you do not have to compile simulation libraries if you are using the software.
Complete the following steps to compile the simulation model libraries using the
Simulation Library Compiler:
1. On the Tools menu, click Launch Simulation Library Compiler.
2. Under EDA simulation tool, for the Tool name, select your simulation tool.
3. Under Executable location, browse to the location of the simulation tool you specified. You must specify this location before you can run the EDA Simulation
Library Compiler.
4. Under Library families, select one or more family names and move them to the
Selected families list.
5. Under Library language, select Verilog, VHDL, or both.
6. In the Output directory field, specify a location to store the compiled libraries.
7. Click Start Compilation.
Complete the following steps to add the simulation files to your project:
1. On the Assignments menu, click Settings.
2. In the Category list, select Files.
3. Click Browse to open the Select File dialog box and select one or more files in the Files list to add to your project.
4. Click Open, and then Add to add the selected file(s) to your project.
5. Click OK to close the Settings dialog box.
Related Information
• Preparing for EDA Simulation
• Intel FPGA Simulation Models
2.10.3.2. Custom Simulation Scripts
You can automate simulations by creating customized scripts. You can generate scripts manually. In addition, you can use NativeLink to generate a simulation script as a template and then make the necessary changes. The following table shows a list of script directories NativeLink generates.
Table 227.
Custom Simulation Scripts for Third Party RTL Simulation
Simulator
Mentor Graphics
ModelSim or
QuestaSim
Aldec Riviera Pro
Simulation File
/simulation/ modelsim/ modelsim_setup.do
Or mentor/msim_setup.tcl
/simulation/ aldec/ rivierapro_setup.tcl
Use
Source directly with your simulator. Run do msim_setup.tcl
, followed by ld_debug
. If you have more than one IP, each IP has a dedicated msim_setup.tcl
all the files included in the
file. Make sure that you combine msim_setup.tcl
files into one common msim_setup.tcl
file.
Source directly with your simulator
.
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Simulator
Synopsys VCS
Cadence Incisive
(NCSim)
Simulation File
/simulation/synopsys/vcs/ vcs_setup.sh
Synopsys VCS MX /simulation/synopsys/ vcsmx/vcsmx_setup.sh
/simulation/cadence/ ncsim_setup.sh
Use
Add your testbench file name to this file to pass the testbench file to VCS using the
–file
option. If you specify a testbench file for
NativeLink and do not choose to simulate, NativeLink generates a script that runs VCS.
Run this script at the command line using quartus_sh–t
<script>
. Any testbench you specify with NativeLink is included in this script.
Run this script at the command line using this script.
quartus_sh –t
<script>. Any testbench you specify with NativeLink is included in
2.11. Implementing Protocols in Intel Arria 10 Transceivers
Revision History
Changes Document
Version
2018.06.15
2017.11.06
2016.10.31
Made the following changes:
• For the 1G/2.5G/5G/10G Multi-rate Ethernet status signal, added a Clock Domain column and values for all except led_char_err.
• Changed the Gen1 PIPE PLL output frequency from 1250MHz to 2500MHz in fPLL IP Parameter Core
Settings for PIPE and ATX PLL IP Parameter Core Settings for PIPE.
• Updated Disabling/Enabling PRBS Pattern Inversion to address the hard PRBS generator and checker pattern being inverted.
• Updated the description of 0x4C0 bit 5 Override AN Parameters Enable to refer to 0x4C3 and changed the start address of the reserved space to 0x4D7 in 10GBASE-KR PHY Register Definitions.
• Changed the start address of the reserved space to 0x4D7 in 1G/10GbE Register Definitions.
• Added a frequency to the description of and added a footnote to the Selected CDR reference
clock frequency parameter in the "RX PMA Parameters" table.
• Added a note about bit slipping after the "Gearbox Parameters" table.
• Added a reference and a link to Clock and Reset Interfaces in the "1-Gigabit/10-Gigabit Ethernet
(GbE) PHY IP Core" section.
• Clarified the description of the Enable PCIe pipe_hclk_in and pipe_hclk_out ports parameter in the "PCIe Ports" table.
• Clarified the description of the pipe_hclk_out[0]
Native PHY in PIPE Mode" table.
port in the "Ports for Arria 10 Transceiver
• Changed the values for the Number of fixed dfe taps parameter in the "RX PMA Parameters" table of the Interlaken section.
• Changed the description of bit 15 of register address 0x4D0 in the "1G/10GbE Register Definitions" table.
• Changed the description of bit 5 of register address 0x4C0 in the "1G/10GbE Register Definitions" table.
Made the following changes to the CPRI section:
• Removed a note from the "Transmitter and Receiver Latency" section.
Made the following changes to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core section:
• Added the "Register Map" section.
Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Added MII Interface signals to the "1G/10GbE PHY Top-Level Signals" figure.
• Added the MII section.
• Added the tx_pcfifo_error_1g
Signals" table.
and rx_pcfifo_error_1g
signals to the "Control and Status
• Removed bit addresses from the 0x494 register in the "GMII PCS Registers" table.
• Changed the read/write description for the 0x495 register in the "GMII PCS Registers" table.
• Changed the note for
COPPER_DUPLEX_OPERATION
in the "GMII PCS Registers" table.
continued...
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Document
Version
2016.05.02
Changes
Made the following changes to the Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 section:
• Added description about the RX FIFO and TX FIFO in the "GbE with IEEE 1588v2" section.
• Added a note to the pll_powerdown
1588v2 PHY Design" figure.
signal in the "Connection Guidelines for a GbE/GbE with IEEE
• Updated the parameter descriptions for in the "Standard PCS Parameters" table.
Made the following changes to the XAUI PHY IP Core section:
• Added further description to the rx_channelaligned
Signals—Soft IP Implementation" table.
signal in the "Optional Control and Status
Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:
• Added "Synchronous to rx_clkout
" for rx_std_wa_patternalign[<n>-1:0] domain column in Word Aligner and Bitslip table.
in the clock
• Added "Unused Transceiver Channels" section.
Made the following changes to the CPRI section:
• New table "Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates" added.
• Supported data rates updated for TX PLLs.
• Data rate values updated in table "General and Datapath Options".
Made the following changes to the PCI Express section:
• Added PIPE Interface width number in the Port column in table "Ports for Arria 10 Transceiver
Native PHY in PIPE Mode".
Made the following changes to the 10GBASE-KR PHY IP Core section:
• Updated the version and release date in the "10GBASE-KR PHY Release Information" table.
• Changed the definitions and parameters in the "General Options Parameters" table.
• Added the "Speed Detection Parameters" table.
• Added and removed parameters in the "Auto Negotiation and Link Training Settings" table.
• Removed parameter from the "10GBASE-R Parameters" table.
• Changed descriptions in the "10GBASE-KR Register Definitions" table for 0x4B0 and 0x4D0.
• Added signals to the "Control and Status Signals" table.
• Added a new bit field for 0x4D1 in the "10GBASE-KR Register Definitions" table.
• Changed the default value for INITPOSTVAL Init Post tap Value in the "10GBASE-KR Optional
Parameters" table.
Made the following changes to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core section:
• Changed the "Block Diagram of the PHY IP Core" figure.
• Updated the version and release date in the "PHY Release Information" table.
• Updated the "Resource Utilization" table.
• Updated the "PHY Features" table.
• Changed the "1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters" table.
• Added signals to the "PHY Interface Signals" figure.
• Added descriptions in the "Clock and Reset Signals" table.
• Added descriptions in the "Transceiver Mode and Operating Speed Signals" table.
• Changed the "Avalon-MM Interface Signals" table.
• Added signals to the "XGMII Signals" table.
• Added registers to the "PHY Register Definitions" table.
• Added parameters to the "1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters" table.
Made the following changes to the 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core section:
• Updated the version and release date in the "1G/10GbE Release Information" table.
• Added signals to the "1G/10GbE PHY Top-Level Signals" figure.
• Added signals to the "PHY Interface Signals" figure.
• Added signals to the "Control and Status Signals" table.
• Changed descriptions in the "GMII Interface Ports " table.
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Document
Version
2016.02.11
2015.12.18
Changes
Made the following changes to the Simulating the Transceiver Native PHY IP section:
• Added a footnote to inform that the "NativeLink" mode is not supported by the "Quartus Prime Pro" edition.
• Added the “Scripting IP Simulation” flow..
• Replaced the “Generation Version Agnostic IP" and "Platform DesignerPlatform Designer Simulation
Scripts", “Use the ip-make-simscript Utility”, and “How to Generate Scripts” sections with the
“Scripting IP Simulation” section.
Made the following changes to the PCI Express section:
• Updated the "How to Place Channels for PIPE Configuration" section.
• Updated the“x4 Configuration with Master Channel Adjacent to a HIP”, “x4 Configuration with
Master Channel not Adjacent to a HIP”, “Rate Switch Change” figures.
Made the following changes to the Other Protocols section:
• Replaced the "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT Channels” section.
• Changed the title from "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT
Channels” to "Design Considerations for implementing Arria 10 GT Channels”.
• Changed the data rate from a range of “17.4 Gbps to 28.3 Gbps” to 25.78125 Gbps.
• Changed the titles of “Valid Permutations for GT and GX Channel Configuration in Transceiver Bank
GXBL1G for Channels 0, 1, and 2” and “Valid Permutations for GT and GX Channel Configuration in
Transceiver Banks GXBL1E and GXBL1H for Channels 3, 4, and 5".
• Removed the “Native PHY IP Parameter Settings for PCS Direct Transceiver Configuration Rules” section.
• Changed “How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced PCS in Low
Latency Mode” section.
• Changed the “ATX PLL IP with GT Clock Lines Enabled” figure.
• Updated the "Valid Permutations for GT and GX Channel Configuration in Transceiver Bank GXBL1G for Channels 0, 1, and 2" and "Valid Permutations for GT and GX Channel Configuration in
Transceiver Banks GXBL1E, and GXBL1H for Channels 3, 4, and 5"" tables.
Made the following changes to the CPRI section:
• Updated the "Transceiver Channel Datapath and Clocking for CPRI" figure.
• Added a note in the "Channel Width Options for Supported Serial Data Rates" table.
• Changed the fPLL supported data rate in the "TX PLL Supported Data Rates" table.
• Changed the "General and Datapath Options" table in the "Native PHY IP Parameter Settings for
CPRI" section.
Made the following changes to the Arria 10 Transceiver Protocols and PHY IP Support section:
• Moved the 19th footnote from "Protocol Preset" column to "Transceiver PHY IP Core" column.
• Changed the footnote 14 to the following: “Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP”.
Made the following changes to the Other Protocols section:
• Removed the "Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels" section.
• Updated the maximum data rate for GT channels to 25.8 Gbps.
Made the following changes to the 1G/2.5G/10G Multi-rate Ethernet PHY IP Core section:
• Removed signals from the "XGMII Signals" table.
• Removed signals from the "PHY Interface Signals" figure.
• Changed the ordering code in the "PHY Release Information" table.
Made the following changes to the XAUI PHY IP Core section:
• Added a description to the "Implementation of the XGMII Specification in Arria 10 Devices
Configuration" figure.
Made the following changes to the 10GBASE-KR PHY IP with FEC Option section:
• Added a note to the "Parameterizing the 10GBASE-KR PHY" section.
• Added new signals to the "Control and Status Signals" table.
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Document
Version
2015.11.02
Changes
Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Added a note to the "Parameterizing the 1G/10GbE PHY" section.
• Added new signals to the "Control and Status Signals" table.
• Changed the description for calc_clk_1g in the "Clock and Reset Signals" table.
Made the following changes to the PCI Express (PIPE) section:
• Updated the "Rate Switch Change" figure in the Gen3 features section.
Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:
• Changed the title of “TX and RX FIFO” to “Standard PCS FIFO” in the Standard PCS Ports table.
• Updated the description and range for “Enable fast sync status reporting for deterministic Latency
SM” parameter in the Standard PCS Parameters table.
• Changed the title of “TX and RX FIFO Parameters” to “Standard PCS FIFO Parameters” in the
Standard PCS Parameters table.
• Updated the “Error marking type” range in the KR-FEC Parameters table in the Enhanced PCS
Parameters section.
• Updated the “Number of fixed DFE taps” value in the Equalization table in the PMA Parameters section.
• Added a new parameter “Provide separate interface for each channel” in the General and Datapath
Options table in the General and Datapath Parameters section.
• Updated the “PMA configuration rules” value in the General and Datapath Options table in the
General and Datapath Parameters section.
• Removed footnote and added "Hard IP for PCI Express to Native PHY IP" in the “Arria 10 Transceiver
Protocols and PHY IP Support” table.
• Updated the description for “Enable tx_pma_ rxfound port (QPI)” parameter in the TX PMA Optional
Ports table in the PMA Parameters section.
• Updated the descriptions for “TX FIFO Mode”,“Enable tx_enh_fifo_full port”, “Enable tx_enh_fifo_empty port” parameters in the Enhanced PCS TX FIFO Parameters table in the
Enhanced PCS Parameters section.
• Updated the descriptions for “Enable rx_enh_fifo_full port”, “Enable rx_enh_fifo_empty port” parameters in the Enhanced PCS RX FIFO Parameters table in the Enhanced PCS Parameters section.
• Updated the description for “Enable RX byte deserializer” parameter in the Byte Serializer and
Deserializer Parameters table in the Standard PCS Parameters section.
• Updated the description for “Share reconfiguration interface” parameter in the Dynamic
Reconfiguration table in the Dynamic Reconfiguration Parameters section.
• Updated the values and descriptions in the Configuration Profiles table in the Dynamic
Reconfiguration Parameters section.
• Updated the foot note for “tx_pma_clkout” clock to suggest what to do with the clock.
• Updated the description for “tx_dispval[<n>(<w>/<s>-1:0]” signal in the 8B/10B Encoder and
Decoder table in the Standard PCS Ports section.
• Updated the values and descriptions in the Configuration Profiles table in the Dynamic
Reconfiguration Parameters section.
• Updated the descriptions for “Enable tx_std_ pcfifo_full port”, “Enable tx_std_ pcfifo_empty port”,
“Enable rx_std_ pcfifo_full port”, “Enable rx_std_ pcfifo_empty port” in the TX and RX FIFO
Parameters table in the Standard PCS Parameters section.
• Added links to other sections which describe the RX rate match FIFO in Basic, GBE and Transceiver channel datapath modes in the Rate Match FIFO Parameters table in the Standard PCS Parameters section.
• Updated value for Transceiver Configuration rules parameter in the " General and Datapath Options" table in the General and Datapath Parameters section.
• Added a new parameter "Provide separate interface for each channel" in the " General and Datapath
Options" table in the General and Datapath Parameters section.
• Updated “Transceiver Native PHY IP Core Parameter Editor” figure.
• Updated “General, Common PMA Options, and Datapath Options” table.
• Added parameter “Enable tx_pma_analog_reset_ackport” in “TX PMA Optional Ports” table.
• Updated parameter “Number of fixed DFE taps” in "Equalization" table.
• Added parameter “Enable rx_analog_reset_ack port” in "RX PMA Optional Ports” table.
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Document
Version
Changes
• Added parameter “Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE” in “Dynamic Reconfiguration” table.
• Added parameter “Include PMA analog settings in configuration Files”in “Configuration Files”.
• Added “Analog PMA Settings (Optional) in Dynamic Reconfiguration” tabl.e
Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Changed the release date and version in the "1G/10GbE Release Information" table.
• Changed the descriptions for
Reset Signals" table.
tx_serial_clk_1g
and rx_cdr_refclk_1g
in the "Clock and
• Changed descriptions in the "General Options Parameters" table.
• Added the "1G Data Mode" table to the PMA Registers section.
• Removed the "1G Data Mode" rows from the Arria 10 GMII PCS Registers section.
Made the following changes to the 10GBASE-KR PHY IP Core with FEC Option section:
• Added bit 12 to the 0x4B0 word address in the "10GBASE-KR Register Definitions" table.
Made the following changes to the Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 section:
• Added a note to the "Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with
IEEE 1588v2" figure.
• Changed the note in the "Gigabit Ethernet (GbE) and GbE with IEEE 1588v2" section.
• Changed some signal names in the "Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE 1588v2" figure.
• Changed the values in the "TX PMA Parameters" table.
• Added a parameter to and updated values in the "RX PMA Parameters" table.
• Changed the values in the "Standard PCS Parameters" table.
Made the following changes to the 10GBASE-R section:
• Added description text to the "10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with
FEC Variants" section.
• Changed steps in the "How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and
10GBASE-R with FEC in Arria 10 Transceivers" section.
• Changed signal names in the "Signals and Ports of Native PHY IP Core for the 10GBASE-R,
10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC" figure.
• Updated parameters in the "General and Datapath Parameters" table.
• Updated parameters in the "RX PMA Parameters" table.
• Updated parameters in the "Enhanced PCS Parameters" table.
• Updated parameters in the "Block Sync Parameters" table.
• Updated parameters in the "Dynamic Reconfiguration Parameters" table.
Made the following changes to the XAUI PHY IP Core section:
• Changed the release date and version in the "XAUI Release Information" table.
• Changed the descriptions in the "XAUI PHY IP Core Registers" table.
• Added description in the "XAUI PHY IP Core" section.
Made the following changes to the 1G/2.5G/10G Multi-rate Ethernet PHY IP Core section:
• Added this section.
Made the following changes to the PCI Express (PIPE) section:
• Updated description for port "pipe_g3_txdeemph[17:0]" in the "Ports for Arria 10 Transceiver
Native PHY in PIPE Mode" table.
• Updated "Ports for Arria 10 Transceiver Native PHY in PIPE Mode" table for presets to TX Deemphasis mappings.
• Updated x4 Configuration and x4 Alternate Configuration figures in the "Master Channel in Bonded
Configurations section".
• Updated "PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate" section.
• Updated “Connection Guidelines for a PIPE Gen3 Design” figure.
• Added recommendations in the “How to Implement PCI Express (PIPE) in Arria 10 Transceivers” section.
• Updated description of parameter “PCS TX channel bonding master” in the “Parameters for Arria 10
Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA” table.
• Added table “Parameter Settings for Arria 10 fPLL IP in PIPE Gen1, Gen2, Gen3 modes” in the “fPLL
IP Parameter Settings for PIPE” section.
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Document
Version
2015.05.11
Changes
• Added table “Parameters for Arria 10 ATX PLL IP in PIPE Gen1, Gen2, Gen3 modes” in the “ATX PLL
IP Parameter Settings for PIPE” section.
• Updated description of port pipe_tx_elecidle in the “Ports for Arria 10 Transceiver Native PHY in
PIPE Mode” table.
• Updated description of port pipe_tx_compliance in the “Ports for Arria 10 Transceiver Native PHY in
PIPE Mode” table.
• Updated description of port pipe_g3_txdeemph[17:0] in the “Ports for Arria 10 Transceiver Native
PHY in PIPE Mode” table.
• Added table “fPLL Ports for PIPE” in the section “fPLL Ports for PIPE” section.
• Added table” ATX PLL Ports for PIPE “ in the “ATX PLL Ports for PIPE” section.
• Added table “Arria 10 Preset Mappings to TX De-emphasis” in the “Preset Mappings to TX Deemphasis” section.
• Updated figure “Alternate Configuration” figure in the “How to Place Channels for PIPE
Configurations” section.
• Updated the “PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate” section.
Made the following changes to the Other Protocols section:
• Added the "Enhanced PCS FIFO Operation" section.
• Changed the minimum data rate from 960 Mbps to 1.0 Gbps in the "General and Datapath
Parameters" table.
Made the following changes to the 10GBASE-KR PHY IP Core section:
• Changed the register definitions for word address 0x4D0 in the "10GBASE-KR PHY Register
Definitions" section.
Made the following changes to the 10GBASE-R section:
• Added a parameter to the "RX PMA Parameters" table.
Made the following changes to the 10GBASE-KR PHY IP Core section:
• Changed the following bits and descriptions in the "10GBASE-KR PHY Register Definitions" section:
— Changed the bit and description for address 0x4D0[21:20].
— Added address 0x4D0[22].
— Removed address 0x4D0[26:24].
— Added address 0x4D0[28:24].
— Removed addresses 0x4D0[27] and 0x4D0[28].
Made the following changes to the Interlaken section:
• Added available preset variations to the "Interlaken" and "How to Implement Interlaken in Arria 10
Transceivers" sections.
• Updated the values for some parameters in the "TX PMA Parameters", "RX PMA Parameters",
"Enhanced PCS Parameters", "Interlaken Frame Generator Parameters", and "Interlaken Frame
Synchronizer Parameters" tables.
Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Changed the product ID in the "1G/10GbE Release Information" table.
• Changed the descriptions in the "Clock and Reset Signals" table.
• Removed the following bits from address 0x4D0 in the "Register Definitions" table:
— 19:18
— 26:24
— 27
Made the following changes to the PCI Express section:
• Updated the "Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations", "PIPE Gen1/Gen2/
Gen3 Configurations", "PCIe Reverse Parallel Loopback Mode Datapath", and "Signals and Ports of
Native PHY IP for PIPE" figures.
• Updated "Rate Switch" Gen3 features.
• Updated the "Enable simplified interface" and "Provide separate interface for each channel" parameters in the "Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes" table.
• Updated the "PCS TX channel; bonding master" parameters in the table "Parameters for Arria 10
Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA" table.
• Updated the "Selected CDR reference clock frequency" parameter in the "Parameters for Arria 10
Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX PMA" table.
• Updated "How to place channels for PIPE configurations" section to include placement guidelines for using Arria 10 PCIe Hard IP.
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Document
Version
2014.12.15
Changes
Made the following changes to the CPRI section:
• Updated the "Connection Guidelines for a CPRI PHY Design" figure.
• Added table for the "Behavior of word aligner status signals for varying interface widths", when in
Manual Mode.
Made the following changes to the Other Protocols section:
• Updated the "Connection Guidelines for a PCS Direct PHY Design" figure.
• Updated the "Connection Guidelines for an Enhanced PCS in Low Latency Mode Design" figure.
• Updated the description following the "Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion" figure.
• Added a Note to the "TX Bit Slip" section.
• Changed the value for rx_parallel_data in the "TX Bit Slip in 8-bit Mode" and "TX Bit Slip in 16-bit
Mode" figures.
Made the following changes to the XAUI PHY IP Core section:
• Removed the section.
set_max_skew
constraint from the "XAUI PHY Timing Analyzer SDC Constraints"
Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:
• Updated the figure for Transceiver Native PHY IP Core Parameter Editor.
• PMA parameters
— Updated the PMA parameter categorization in the TX PMA and RX PMA "Equalization" section.
— Added parameters
Enable tx_pma_iqtxrx_clkout port
and
Enable tx_seriallpbken port
in "TX PMA Optional Ports" table.
— Added parameters
Enable rx_pma_iqtxrx_clkout port
in "RX PMA Optional Ports" table.
— Updated "RX PMA Parameters" table into "RX CDR Options" and "Equalization" sections.
— Removed the option ports table.
Enable rx_pma_div_clkout division
factor from RX PMA optional
— Updated the description of "CTLE Adaptation Mode" and "DFE Adaptation Mode" in "RX PMA" parameter table.
— Updated value and description for parameter
Enable tx_pma_clkout port
and
Enable tx_pma_div_clkout port
in "TX Bonding Options" table.
— Updated value and description for parameter
Enable rx_pma_clkout port
and
Enable rx_pma_div_clkout port
in "RX PMA Optional Ports" table.
Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:
• Updated the description of tx_cal_busy
and rx_cal_busy
signals in the PMA Ports section.
• Added a new section Enhanced PCS TX and RX Control Ports to better describe the tx_control and rx_control
bit encodings used for different protocols. Removed the bit encodings for tx_control
and rx_control
signals from Enhanced PCS Ports section.
• Updated the clock domain information about signals mentioned in
Enhanced PCS Ports
section.
• Updated the description of rx_std_wa_patternalign
signal in Standard PCS Ports section.
• Updated the parameter descriptions in General Datapath Parameters and PMA Parameters sections.
• Updated the port descriptions in PMA Ports section.
Made the following changes to the Interlaken section:
• Added another value to the "TX channel bonding mode" parameter in the "TX PMA Parameters" table.
• Added values to the "PCS TX channel bonding master" and "Actual PCS TX channel bonding master" parameters in the "TX PMA Parameters" table.
• Corrected the values to the "CTLE adaptation mode" parameter in the "RX PMA Parameters" table.
• Added the "Enable Interlaken TX random disparity bit" parameter to the "Interlaken Disparity
Generator and Checker Parameters" table.
• Changed the values to four parameters to "Off" in the "Gearbox Parameters" table.
• Removed the "Enable embedded debug" parameter from the "Dynamic Reconfiguration Parameters" table.
Made the following changes to the Gigabit Ethernet (GbE) and GvE with IEEE 1588v2 section:
• Added a figure description to the "Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE 1588v2" figure.
continued...
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Version
Changes
Made the following changes to the 10GBASE-R section:
• Added a figure description to the "Signals and Ports of Native PHY IP Core for the 10GBASE-R,
10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC" figure.
Made the following changes to the 10GBASE-KR PHY IP with FEC Option section:
• Changed the "10GBASE-KR PHY IP Core Block Diagram" figure to activate the Standard TX PCS,
Standard RX PCS, and GbE PCS blocks.
• Added a note to the "10GBASE-KR Functional Description" section.
• Added new parameters to the "General Options" table.
• Changed the default values for VPOSTRULE, VPRERULE, INITPOSTVAL, and INITPREVAL in the
"Optional Parameters" table.
• "10GBASE-KR PHY Register Definitions" table:
— Changed the default value for register address 0x4D0[7:4]
— Changed the default value for register address 0x4D0[17].
— Changed the descriptions for register address 0x4B2.
— Changed the descriptions for register addresses 0x4D5 and 0x4D6.
• Changed the descriptions for the following signals in the in the "Clock and Reset Signals" table.
— tx_pma_clkout
—
— rx_pma_clkout tx_pma_div_clkout
— rx_pma_div_clkout
• Changed the descriptions for the following signals in the in the "XGMII Signals" table.
— xgmii_tx_clk
— xgmii_rx_clk
• Removed the 1588 Soft FIFOs block from the "PHY-Only Design Example with Two Backplane
Ethernet and Two Line-Side (1G/10G) Ethernet Channels" figure
Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Changed the descriptions for register address 0x4D5 in the "1G/10GbE Register Definitions" table.
• Removed the Daisy Chain and μP I/F lines from the Link Training block in the "1G/10GbE PHY Block
Diagram" figure.
• Changed the descriptions for 0x494 and 0x495, and added 0x4a4 bit 4 to the "GMII PCS Registers" section.
Made the following changes to the XAUI section:
• Added a PMA width requirement in the "Transceiver Clocking and Channel Placement Guidelines in
XAUI Configuration" section.
• Changed the figure description for the "Transceiver Clocking for XAUI Configuration" figure.
• Changed the note in the "Transceiver Clocking and Channel Placement Guidelines in XAUI
Configuration" section.
• Added a note to the "Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO
Enabled" figure.
• Added the "Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO Enabled" figure.
• Removed the Data rate parameter from the "General Options" table.
• Removed the tx_digitalreset
signal from the "Clock and Reset Signals" table.
• Changed the available signals in the "PMA Channel Controller Signals" table.
• Added the Enable phase compensation FIFO parameter to the "Advanced Options" table.
• Added the pll_cal_busy_i
signal to the "XAUI Top-Level Signals—Soft PCS and PMA" figure.
• Added the xgmii_rx_inclk
port to the "XAUI Top-Level Signals—Soft PCS and PMA" figure.
• Changed the description in the "Clock and Reset Signals" table.
• Removed the following signals from the "PMA Channel Controller Signals" table:
— tx_bonding_clocks[5:0]
— pll_cal_busy_i
—
— pll_powerdown_o pll_locked_i continued...
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Version
2014.10.08
2014.08.15
Changes
• Made the following changes to the "XAUI PHY IP Core Registers" table.
— Removed cal_blk_powerdown
— Removed pma_tx_pll_is_locked
— Removed Word Addresses 0x082, 0x083, 0x086, 0x087, 0x088, 0x089
— Removed patterndetect[7:0]
— Changed the description for syncstatus [7:0]
• Added the xgmii_rx_inclk
port to the "SDR RX XGMII Interface " table.
• Added the pll_cal_busy_i
port to the "PMA Channel Controller Signals" table.
• Added the "XAUI PHY Timing Analyzer SDC Constraint" section.
Made the following changes to the PCI Express section:
• Added PIPE Gen3 32 bit PCS Clock Rates table in the Gen3 Rate Switchsection.
• Updated the Rate Switch Change figure.
• Updated the Bit Mappings When the Simplified Interface Is Disabledtable.
• Updated the figures in How to Place Channels for PIPE Configurations.
• Updated the Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA table.
• Updated the clock domains in Signals and Ports of Native PHY IP for PIPE figure.
• Updated the Ports for Arria 10 Transceiver Native PHY in PIPE Mode table.
• Updated Logical PCS Master Channel for PIPE Configuration table.
• Updated the PCIe Reverse Parallel Loopback in Gen1/Gen2 features with input signal name.
• Updated the Rate Switch Change figure.
• Updated the Gearbox Gen3 Transmission signals in the Gen3 Data Transmission figure.
• Updated the PIPE Design Example section.
• Updated the Gen3 Power State Management P1 to P0 Transition signals.
• Updated the Supported Features for PIPE Configurations table.
• Updated the Gen1/Gen2 Features section.
Made the following changes to the CPRI section:
• Updated the parameter values for “RX word aligner mode”.
• Added a new option for Interlaken in the GUI "Enable Interlaken TX random disparity bit".
• For PMA configuration rules changed the option “SATA” to “SATA/SAS”.
• Changed the GUI option “CTLE adaptation mode” to “DFE adaptation mode”.
Made the following changes to the Other Protocols section:
• Added four new sections: "TX Bit Slip", "TX Polarity Inversion", "RX Bit Slip", and "RX Polarity
Inversion".
• Changed the initial value of tx_parallel_data
in the "Manual Mode when the PCS-PMA Interface
Width is 10 Bits" and "Manual Mode when the PCS-PMA Interface Width is 16 Bits" figures.
• Changed the minimum value for the "Data rate" parameter to 1 Gbps in the "General and Datapath
Options Parameters" table.
Made the following changes to the Simulating the Native Transceiver PHY section:
• In the introductory section, removed the third bullet in the list of netlists you can simulate because gate-level timing simulation is no longer supported.
• Removed mention of the ModelSim DE simulator in the "How to Use NativeLink to Specify a
ModelSim Simulation" section.
Made the following changes to the Ethernet section:
• Changed the frequency for mgmt_clk
in the "Avalon-MM Interface Signals" table for Document
Version10GBASE-KR PHY IP Core with FEC Option and for 1G/10 Gbps Ethernet PHY IP Core.
Made the following changes to the Other Protocols section:
• Removed an erroneous note regarding Quartus II software legality check restrictions.
Made the following changes to the Transceiver Design Flow section:
• Added "Make Pin Assignments Using Pin Planner and Assignment Editor" block to figure "Transceiver
Design Flow"
• Updated Select and Instantiate PHY IP, Generate PHY IP, Select and Instantiate PLL IP, and
Generate PLL IP sections to indicate the new IP instantiation flow per ACDS 14.0A10 release.
• Added a new section for Make Pin Assignments Using Pin Planner and Assignment Editor continued...
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Made the following changes to the Arria 10 Transceiver Protocols and PHY IP Support section:
• Updated table "Arria 10 Transceiver Protocols and PHY IP Support"
— Removed SFIS and 10G SDI from the table.
— Updated Protocol Preset, Transceiver Configuration Rule, and PCS Support for protocols in the table.
Made the following changes to the Using the Arria 10 Transceiver Native PHY IP section:
• Updated references of MegaWizard Plug-In Manager to IP Catalog and Parameter Editor.
• Added PCS Direct block in figure "Transceiver Native PHY IP Top Level Interfaces and Functional
Blocks".
• Updated figure "Transceiver Native PHY IP GUI" for 14.0A10 release IP GUI.
• Updated General and Datapath Parameters section
— Updated parameter descriptions in table "General and Datapath Options".
— Updated parameter descriptions in table "Transceiver Configuration Rule Parameters".
• Updated PMA Parameters section
— Updated parameter descriptions in tables "TX PMA Bonding options", "TX PLL Options", "RX PMA
Parameters".
— Added description for CTLE adaptation mode and updated description for DFE adaptation
mode.
• Enhanced PCS Parameters section
— Added a new table "Enhanced PCS Parameters"
— Updated the parameter descriptions in tables "Enhanced PCS TX FIFO Parameters", "Enhanced
PCS RX FIFO Parameters", "Interlaken Frame Generator Parameters", "Interlaken Frame
Synchronizer Parameters", "10GBASE-R BER Checker Parameters", "Scrambler-Descrambler
Parameters", "Block Synchronizer Parameters", "Gearbox Parameters".
— Added descriptions in "KR-FEC Parameters" table.
• Standard PCS Parameters
— Updated the descriptions in tables "TX and RX FIFO Parameters", "Rate Match FIFO Parameters",
"Word Aligner and Bitslip Parameters", and "PCIe Ports".
• Dynamic Reconfiguration Parameters
— Removed Enable Embedded JTAG Avalon-MM Master parameter and added Altera Debug
Master Endpoint parameter and updated its description.
— Added a table for "Embedded Debug Parameters".
• Updated the figure "Directory Structure for Generated Files" in IP Core File Locations section.
• Changed "one-time" to "triggered" adaptation mode for DFE and CTLE.
Made the following changes to the Interlaken section:
• Changed parameter name in the "Signals and Ports of Native PHY IP for Interlaken" figure from tx_bonding_clock to tx_bonding_clock[5:0].
• Updated tables in the "Native PHY IP Parameter Settings for Interlaken" section:
— Added new tables: "10GBASE-R BER Checker Parameters", "KR-FEC Parameters".
— Deleted table: "Configuration Profiles Parameters".
— Added new parameters and updated existing ones to tables: "General and Datapath
Parameters", "TX PMA Parameters", "RX PMA Parameters", "Enhanced PCS Parameters",
"Dynamic Reconfiguration Parameters".
— Updated existing parameters to tables: "Interlaken Frame Generator Parameters", "Interlaken
CRC-32 Generator and Checker Parameters".
Made the following changes to the Ethernet section:
• Initial release of the XAUI PHY IP Core section.
• Changed the bus width between the FPGA fabric and PCS, and added notes 3 and 4 to the
"Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2" figure.
• Provided the full hexadecimal values for rx_parallel_data
, rx_patterndetect
, and rx_runningdisp
in the "Decoding for GbE" figure description.
• Changed the note in the Rate Match FIFO for GbE section to clarify the case where 200 ppm total is valid.
• Added the pll_cal_busy
circuitry, updated signals, and added a note to the "Connection
Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design" figure.
• Removed the Device and speed grade parameter from the "General and Datapath Options" table.
continued...
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Version
Changes
• Changed the values for the PPM detector threshold parameter and removed the Decision feedback equalization parameter in the "RX PMA Parameters" table.
• Changed the 10GBASE-R PHY grouping in the "10GBASE-R PHY as Part of the IEEE802.3-2008 Open
System Interconnection (OSI)" figure.
• Added that 10GBASE-R is compatible with the Altera 10-Gbps Ethernet MAC Intel FPGA IPCore
Function in the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants section.
• Added the "Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2" figure.
• Changed steps 1 and 4 in the How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and
10GBASE-R with FEC in Arria 10 Transceivers section to match the GUI.
• Specified the target BER of 10 -12 in the 10GBASE-KR PHY IP Core section.
• Removed the "Top Level Modules of the 1G/10GbE PHY Intel FPGA IP Core Function" figure.
• Removed the 10GBASE-KR PHY with 1588 variant from the "10GBASE-KR PHY Performance and
Resource Utilization" table. This is not supported.
• Replaced the "10GBASE-KR PHY IP Block Diagram" figure.
• Added the Auto Negotiation, IEEE 802.3 Clause 73 section.
• Substantially rewrote the Link Training (LT), IEEE 802.3 Clause 72 section.
• Removed the "TX Equalization for Link Partners" figure.
• Removed the "TX Equalization in Daisy Chain Mode" figure. Daisy chain is not supported.
• Removed the Auto Negotiation section.
• Replaced the "Reconfiguration Block Details" figure.
• Removed the Initial Datapath, Enable internal PCS reconfiguration logic, and Enable IEEE
1588 Precision time Protocol parameters from the "General Options Parameters" table.
• Added the Reference clock frequency, Enable additional control and status pins, Include
FEC sublayer, Set FEC_ability bit on power up and reset, and Set FEC_Enable bit on power
up and reset parameters to the "General Options Parameters" table.
• Removed the 10GBASE-R Parameters section.
• Removed the 10M/100M/1Gb Ethernet Parameters section.
• Removed the Speed Detection Parameters section.
• Substantially changed the "Auto Negotiation and Link Training Settings" table, adding the
AN_PAUSE Pause Ability, CAPABLE_FEC ENABLE_FEC (request), AN_TECH Technology
Ability, AN_SELECTOR Selector Field, and Width of the Training Wait Counter parameters.
• Updated all parameter names, values, and descriptions in the "Optional Parameters" table.
• Updated the signals in the "10GBASE-KR Top-Level Signals" figure.
• Removed the rx_serial_clk_1g
and tx_serial_clk_1g
signals, and removed all references to
"1G" from all descriptions in the "Clock and Reset Signals" table.
• Removed references to GMII and MII interfaces from the Data Interfaces section.
• Removed GMII and MII signals from the "XGMII Signals" table.
• Updated the list of signals in the "Control and Status Signals" table.
• Removed the Daisy-Chain Interface Signals section.
• Removed the Embedded Processor Interface Signals section.
• Updated the list of signals in the "Dynamic Reconfiguration Interface Signals" table.
• Added new registers and updated descriptions of existing registers in the "10GBASE-KR Register
Definitions" table.
• Updated the 0x482 registers in the "PCS Registers" table.
• Updated and removed some addresses in the "PMA Registers" table.
• Added the Speed Change Summary section.
• Removed the 10GBASE-KR, Backplane, FEC, GMII PCS Registers section.
• Removed the 1588 Delay Requirement section.
• Removed the Channel Placement Guidelines section.
• Removed the introductory paragraph from the Design Example section.
• Removed the 1588 FIFO block from the "Top Level Modules of the 1G/10GbE PHY Intel FPGA IP
Core Function" figure.
• Updated all values for ALMs, ALUTs, Registers, and M20K in the "1G/10GbE PHY Performance and
Resource Utilization" table.
• Updated the blocks in the "Reconfiguration Block Details" figure.
continued...
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2013.12.02
Changes
• Changed the blocks and clock connections in the "Clocks for Standard and 10G PCS and TX PLLs" figure.
• Changed signal names and descriptions in the "Clock and Reset Signals" table.
• Changed the parameter name for 10GbE Reference Clock frequency and added the 1G
Reference clock frequency parameter in the "10GBASE-R Parameters" table.
• Removed the Set FEC_ability bit on power up and reset and Set FEC_enable bit on power
up and resetparameters from the "FEC Options" table.
• Updated the list of available signals in the "1G/10GbE PHY Top-Level Signals" figure.
• Added new registers and updated descriptions of existing registers in the "10GBASE-KR Register
Definitions" table.
• Added the 0x4A8 and 0x4A9 addresses and updated the name for address 0x4A2 and 0x4A3 in the
"10GBASE-KR, Backplane, FEC GMII PCS Registers" table.
• Added the Speed Change Summary section.
Made the following changes to the PCI Express section:
• Added a new topic Pipe link equalization for Gen 3 data rate.
• Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the How to Connect
TX PLLs for PIPE Gen1, Gen2 and Gen3 Mode section.
• Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the How to Implement
PCI Express in Arria 10 Transceivers section.
• Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the Supported Pipe
Features section.
Made the following changes to the CPRI section:
• Added new values to each row in the "TX PLL Supported Data Rates" table.
Made the following changes to the Other Protocols section:
• Updated the "How to Use NativeLink to Specify a ModelSim Simulation" section.
• Updated the "NativeLink Generated Scripts for Third-Party RTL Simulation" table.
• Changed references from MegaWizard to IP Catalog or Parameters Editor.
• Using the Basic and Basic with KR FEC Configurations of Enhanced PCS
— Updated the "Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS)
Configuration" figure and added footnote 3.
— Updated the "General and Datapath Parameters", "TX PMA Parameters", "RX PMA Parameters", and "Enhanced PCS Parameters" tables.
— Added the "Equalization" table.
— Added the "How to Enable Low Latency in Basic Enhanced PCS" section.
• Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS
— Updated the values in the "Manual Mode when the PCS-PMA Interface is 8 Bits", "Manual Mode when the PCS-PMA Interface is 10 Bits", and "Manual Mode when the PCS-PMA Interface is 16
Bits" figures.
— Added the "8B/10B Encoder and Decoder" and "8B/10B TX Disparity Control" sections.
— Updated the "Connection Guidelines for a Basic/Custom Design" figure.
— Updated the "General and Datapath Options Parameters", "TX PMA Parameters", "RX PMA
Parameters", and "Standard PCS Parameters" tables.
• Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels
— Updated the maximum data rate for GT channels to 25.4 Gbps.
— Added information about PCS Direct mode.
— Updated "ATX PLL IP with GT Clock Lines Enabled" figure.
• Updated the How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in
Arria 10 Transceivers section.
Made the following changes to the Simulating the Transceiver Native PHY IP Core section:
• Updated the "How to Use NativeLink to Specify a ModelSim Simulation" section.
• Updated the "NativeLink Generated Scripts for Third-Party RTL Simulation" table.
Initial release.
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3. PLLs and Clock Networks
This chapter describes the transceiver phase locked loops (PLLs), internal clocking architecture, and the clocking options for the transceiver and the FPGA fabric interface.
As shown in the following figure, transceiver banks can have either three or six transceiver channels. For every three channels, you get one advanced transmit (ATX)
PLL, one fractional PLL (fPLL), and one Master clock generation block (CGB). Refer to the Device Transceiver Layout section to identify which devices have three channel transceiver banks.
The Arria 10 transceiver clocking architecture supports both bonded and non-bonded transceiver channel configurations. Channel bonding is used to minimize the clock skew between multiple transceiver channels. For Arria 10 transceivers, the term bonding can refer to PMA bonding as well as PMA and PCS bonding. Refer to the
Channel Bonding section for more details.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Figure 168. Arria 10 PLLs and Clock Networks x1 Clock Lines
CH2 CDR
Local CGB
CH1 CDR/CMU
Local CGB
CH0
CDR
Local CGB x6 Clock Lines xN Clock Lines
Transceiver
Bank fPLL
ATX
PLL
Master
CGB
Transceiver
Bank
CH5
CDR
Local CGB
CH4
CDR/CMU
Local CGB
CH3 CDR
Local CGB
CH2
CDR
Local CGB
CH1 CDR/CMU
Local CGB
CH0
CDR
Local CGB fPLL
ATX
PLL
Master
CGB fPLL
ATX
PLL
Master
CGB
Related Information
•
on page 389
•
on page 9
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•
on page 398
Information on how to use PLL IP to implement bonded and non-bonded transceiver designs.
3.1. PLLs
Table 228.
Transmit PLLs in Arria 10 Devices
PLL Type
Advanced Transmit (ATX) PLL
Fractional PLL (fPLL)
Clock Multiplier Unit (CMU) PLL or Channel PLL (50)
Characteristics
• Best jitter performance
• LC tank based voltage controlled oscillator (VCO)
• Supports fractional synthesis mode (in cascade mode only)
• Used for both bonded and non-bonded channel configurations
• Ring oscillator based VCO
• Supports fractional synthesis mode
• Used for both bonded and non-bonded channel configurations
• Ring oscillator based VCO
• Used as an additional clock source for non-bonded applications
Figure 169. Transmit PLL Recommendation Based on Data Rates
Related Information
Refer to Using PLL and Clock Networks section for guidelines and usage
on page 398
3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs
ATX PLL-to-ATX PLL Spacing Guidelines
For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 7 ATX PLLs apart (skip 6).
(50) The CMU PLL or Channel PLL of channel 1 and channel 4 can be used as a transmit PLL or as a clock data recovery (CDR) block. The channel PLL of all other channels (0, 2, 3, and 5) can only be used as a CDR.
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Note:
For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GX channels, they must be placed 4 ATX PLLs apart (skip 3).
For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GT channels, they must be placed 3 ATX PLLs apart (skip 2).
For two ATX PLLs providing the serial clock for PCIe/PIPE Gen3, they must be placed 4
ATX PLL apart (skip 3).
If these spacing rules are violated, Intel Quartus Prime issues a critical warning.
When two ATX PLLs are being used, and you meet the following two conditions in your applications:
• One of the ATX PLL re-calibration process is triggered.
• The other channel (that is clocked by another ATX PLL) is in data transmission mode.
You must place the two ATX PLLs 7 ATX PLLs apart (skip 6). ATX PLLs between the 2 active ATX PLLs should not be used.
ATX PLL-to-fPLL Spacing Guidelines
If you are using both ATX PLL and fPLL, and you meet the below two conditions in your applications:
• When ATX PLL VCO frequency and fPLL VCO frequency is within 50MHz.
• ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/
OC192/STM64, 10G GPON or protocol that has jitter integration start range
<1MHz and data rate > 3Gbps.
The ATX PLL and fPLL must be separated at least by 1 ATX PLL in between.
If you are using both ATX PLL and fPLL, and you meet the below two conditions in your applications:
• fPLL user re-calibration process is triggered.
• ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/
OC192/STM64, 10G GPON or protocol that has jitter integration start range
<1MHz and data rate > 3Gbps.
then the ATX PLL and fPLL must be separated at least by 1 ATX PLL in between
(regardless of the ATX PLL and fPLL VCO frequency offset).
3.1.2. ATX PLL
The ATX PLL contains LC tank-based voltage controlled oscillators (VCOs). These LC
VCOs have different frequency ranges to support a continuous range of operation.
When driving the Transceiver directly, the ATX PLL only supports the integer mode. In cascade mode, the ATX PLL only supports fractional mode.
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Figure 170. ATX PLL Block Diagram
Dedicated reference clock pin
Reference clock network
Receiver input pin
Output of another PLL with PLL cascading
Global clock or core clock
CP &
LF
Refclk
Multiplexer
Input reference
clock
N Counter refclk
Up
PFD
Down fbclk
VCO
Delta Sigma
Modulator (1)
Lock
Detector pll_locked
2
L Counter
2
/2
Note:
Input Reference Clock
This is the dedicated input reference clock source for the PLL.
The input reference clock can be sourced from one of the following:
• Dedicated reference clock pin
• Reference clock network
• Receiver input pin
• Output of another PLL with PLL cascading
• Global clock or the core clock network
The input reference clock to the dedicated reference clock pin is a differential signal.
Intel recommends using the dedicated reference clock pin as the input reference clock source for the best jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation and PLL calibration. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.
Sourcing reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to the ATX PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details.
The ATX PLL calibration is clocked by the CLKUSR clock which must be stable and available for calibration to proceed. Refer to the Calibration section for more details about the CLKUSR clock.
Reference Clock Multiplexer
The reference clock
(refclk
) multiplexer selects the reference clock to the PLL from the various reference clock sources available.
N Counter
The N counter divides the
2, 4, and 8.
refclk
mux's output. The division factors supported are 1,
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Phase Frequency Detector (PFD)
The reference clock
(refclk)
signal at the output of the N counter block and the feedback clock
(fbclk)
signal at the output of the M counter block are supplied as inputs to the PFD. The output of the PFD is proportional to the phase difference between the refclk
and fbclk
inputs. It is used to align the refclk
signal at the output of the N counter to the feedback clock
(fbclk)
signal. The PFD generates an
"Up" signal when the reference clock's falling edge occurs before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's falling edge occurs before the reference clock's falling edge.
Charge Pump and Loop Filter
The PFD output is used by the charge pump and loop filter (CP and LF) to generate a control voltage for the VCO. The charge pump translates the "Up" or "Down" pulses from the PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency. The charge pump, loop filter, and VCO settings determine the bandwidth of the ATX PLL.
Lock Detector
The lock detector block indicates when the reference clock and the feedback clock are phase aligned. The lock detector generates an active high pll_locked
signal to indicate that the PLL is locked to its input reference clock.
Voltage Controlled Oscillator
The voltage controlled oscillator (VCO) used in the ATX PLL is LC tank based. The output of charge pump and loop filter serves as an input to the VCO. The output frequency of the VCO depends on the input control voltage. The output frequency is adjusted based on the output voltage of the charge pump and loop filter.
L Counter
The L counter divides the differential clocks generated by the ATX PLL. The L counter is not in the feedback path of the PLL.
M Counter
The M counter's output is the same frequency as the N counter's output. The VCO frequency is governed by the equation:
VCO freq = 2 * M * input reference clock/N
An additional divider divides the high speed serial clock output of the VCO by 2 before it reaches the M counter.
The M counter supports division factors in a continuous range from 8 to 127 in integer frequency synthesis mode and 11 to 123 in fractional mode.
Delta Sigma Modulator
The fractional mode is only supported when the ATX PLL is configured as a cascade source for OTN and SDI protocols. The delta sigma modulator is used in fractional mode. It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis. In fractional mode, the M value is as follows: .
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M (integer) + K/2^32, where K is the Fractional multiply factor (K) in the ATX PLL IP
Parameter Editor
K legal values are 1 through 2^32-1 and can only be manually entered in the ATX PLL
IP Parameter Editor in Quartus Prime software.
The output frequencies can be exact when the ATX PLL is configured in fractional mode. Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz
VCO frequency, not all desired fractional values can be achieved exactly. The lock signal is not available, when configured in fractional mode in k-precision mode (K <
0.1 or K > 0.9).
Multiple Reconfiguration Profiles
Under the ATX PLL IP Parameter Editor Dynamic Reconfiguration tab, in the
Configuration Profiles section, multiple reconfiguration profiles can be enabled. This allows to create, store, and analyze the parameter settings for multiple configurations or profiles of the ATX PLL IP.
The ATX PLL IP GUI can generate configuration files (SystemVerilog, C header or MIF) for a given configuration. With the multi reconfiguration profile options enabled, the
ATX PLL IP Parameter Editor can produce configuration files for all of the profiles simultaneously. In addition, by enabling the reduced reconfiguration files generation, the IP Parameter Editor produces a reduced configuration file by internally comparing the corresponding parameter settings of all the profiles and identifying the differences.
Embedded Reconfiguration Streamer
This option enables a push-button flow to reconfigure between multiple configurations or profiles. Here are the steps to follow:
1. Multiple reconfiguration profiles creation
• In the ATX PLL IP GUI, create configurations for each profiles using the multiprofile feature.
2. Reconfiguration report files
• The IP GUI generates the reconfiguration report files that contain parameter and register settings for all the selected profiles. If the reduced reconfiguration files option is selected, the IP parameter editor compares the settings between the profiles and generate reduced report files which only contain the differences.
3. Select “Enable embedded reconfiguration streamer logic” in the GUI to generate the following:
• Necessary HDL files to perform streaming.
• The individual report files for each profile, an SystemVerilog package file with configuration data for all the profiles concatenated together which is used to initialize the configuration ROM
4. Generate the ATX PLL IP and control the reconfiguration streamer using the AVMM master.
Related Information
•
on page 567
• How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?
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3.1.2.1. Instantiating the ATX PLL IP Core
The Arria 10 transceiver ATX PLL IP core provides access to the ATX PLLs in the hardware. One instance of the PLL IP core represents one ATX PLL in the hardware.
1. Open the Quartus Prime software.
2. Click Tools ➤ IP Catalog.
3. In IP Catalog, under Library ➤
Transceiver PLL
➤
, select Arria 10
Transceiver ATX PLL and click Add.
4. In the New IP Instance dialog box, provide the IP instance name.
5. Select the Arria 10 device family.
6. Select the appropriate device and click OK.
The ATX PLL IP core Parameter Editor window opens.
3.1.2.2. ATX PLL IP Core
Table 229.
ATX PLL Configuration Options, Parameters, and Settings
Parameter
Message level for rule violations
Protocol mode
Range
Error
Warning
Description
Specifies the messaging level to use for parameter rule violations.
• Error—Causes all rule violations to prevent IP generation.
• Warning—Displays all rule violations as warnings and allows IP generation in spite of violations.
Governs the internal setting rules for the VCO.
This parameter is not a preset. You must set all other parameters for your protocol.
Bandwidth
Number of PLL reference clocks
Basic
PCIe* Gen1
PCIe Gen2
PCIe Gen3
SDI_cascade
OTN_cascade
UPI TX
SAS TX
Low
Medium
High
1 to 5
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection.
Selected reference clock source
Primary PLL clock output buffer
0 to 4
GX clock output buffer
GT clock output buffer
Specifies the number of input reference clocks for the ATX
PLL.
You can use this parameter for data rate reconfiguration.
Specifies the initially selected reference clock input to the
ATX PLL.
Specifies which PLL output is active initially.
• If GX is selected, turn ON "Enable PLL GX clock
output port".
• If GT is selected, turn ON “Enable PLL GT clock
output port".
continued...
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Parameter
Enable PLL GX clock output port (
)
Range
On/Off
Enable PCIe clock output port On/Off
Description
Enables the GX output port which feeds x1 clock lines.
You must select this parameter for PLL output frequency less than 8.7 GHz, or if you intend to reconfigure the PLL to a frequency below 8.7 GHz.
Turn ON this port if GX is selected in the "Primary PLL
clock output buffer".
Exposes the
The port should be connected to the port.
pll_pcie_clk port used for PCI Express.
pipe_hclk_input
Enables the ATX to FPLL cascade clock output port.
Enable ATX to FPLL cascade clock output port
Enable fref and clklow port (52) .
PLL output frequency
PLL integer reference clock frequency
Multiply factor (M-Counter)
Divide factor (N-Counter)
Divide factor (L-Counter)
Predivide factor (L-Cascade
Predivider)
Fractional multiply factor (K)
On/Off
On/Off
Refer to Intel
Arria 10 Device
Datasheet .
Refer to the GUI
Enables fref
and clklow
ports for external lock detector.
Use this parameter to specify the target output frequency for the PLL.
Selects the input reference clock frequency for the PLL.
Read only
For
OTN_cascade or
SDI_cascade, refer to the GUI.
Read only
For
SDI_cascade or
OTN_cascade, refer to the GUI.
Displays the M-counter value.
Specifies the M-counter value (In SDI_cascade or
OTN_cascade Protocol mode only).
Displays the N-counter value.
For SDI_cascade or OTN_cascade, refer to the GUI.
Read only Displays the L-counter value.
Refer to the GUI Specifies the L-cascade predivider value. This value must be
2 for a VCO frequency greater than 10.46 GHz and 1 for a
VCO frequency less than 10.46GHz. (In SDI_cascade or
OTN_cascade Protocol mode only).
Read only Displays the actual K-counter value. This parameter is only available in fractional mode.
Table 230.
ATX PLL—Master Clock Generation Block Parameters and Settings
Parameter
Include Master Clock Generation
Block (53)
Range
On/Off
Description
When enabled, includes a master CGB as a part of the ATX
PLL IP core. The PLL output drives the Master CGB.
continued...
(51) You can enable both the GX clock output port and the GT clock output port. However, only one port can be in operation at any given time. You can switch between the two ports using PLL reconfiguration.
(52) The fPLL fref
and clklow
signals should only be used with the Intel external soft lock detection logic.
(53) Manually enable the MCGB for bonding applications.
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Parameter
Clock division factor
Enable x6/xN non-bonded highspeed clock output port
Enable PCIe clock switch interface
Number of auxiliary MCGB clock input ports
MCGB input clock frequency
MCGB output data rate.
Enable bonding clock output ports
Enable feedback compensation bonding
PMA interface width
Range
1, 2, 4, 8
On/Off
On/Off
0, 1
Read only
Read only
On/Off
On/Off
8, 10, 16, 20,
32, 40, 64
Description
This is used for x6/xN bonded and non-bonded modes.
Divides the master CGB clock input before generating bonding clocks.
Enables the master CGB serial clock output port used for x6/xN non-bonded modes.
Enables the control signals for the PCIe clock switch circuitry. Used for PCIe clock rate switching.
Auxiliary input is used to implement the PCIe Gen3 protocol.
Displays the master CGB's input clock frequency.
Displays the master CGB's output data rate.
Enables the tx_bonding_clocks
output ports of the master CGB used for channel bonding.
This option should be turned ON for bonded designs.
Enables this setting when using feedback compensation bonding. For more details about feedback compensation bonding, refer to the PLL Feedback Compensation Bonding section later in the document.
Specifies PMA-PCS interface width.
Match this value with the PMA interface width selected for the Native PHY IP core. You must select a proper value for generating bonding clocks for the Native PHY IP core.
Table 231.
ATX PLL—Dynamic Reconfiguration
Parameter
Enable reconfiguration
Range
On/Off
Enable Altera Debug Master
Endpoint
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Configuration file prefix
On/Off
On/Off
On/Off
User-defined
On/Off
Description
Enables the PLL reconfiguration interface. Enables the simulation models and adds Avalon compliant ports for reconfiguration.
When you turn on this option, the Transceiver PLL IP core includes an embedded Altera Debug Master Endpoint
(ADME) that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
When enabled, the reconfig_waitrequest
does not indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status is reflected in a soft status register bit. (Only available if "Enable control and status registers feature" is enabled).
Enables capability registers that provide high-level information about the ATX PLL's configuration.
Sets a user-defined numeric identifier that can be read from the user_identifier are enabled.
offset when the capability registers
Enables soft registers for reading status signals and writing control signals on the PLL interface through the embedded debug logic.
Enter the prefix name for the configuration files to be generated.
continued...
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Parameter
Generate SystemVerilog package file
Generate C header file
Enable multiple reconfiguration profiles
Enable embedded reconfiguration streamer
Generate reduced reconfiguration files
Number of reconfiguration profiles
Store current configuration to profile
Generate MIF (Memory Initialize
File)
Range
On/Off
On/Off
On/Off
On/Off
On/Off
1 to 8
0 to 7
On/Off
Description
Generates a SystemVerilog package file containing all relevant parameters used by the PLL.
Generates a C header file containing all relevant parameters used by the PLL.
Enables multiple configuration profiles to be stored.
Enables embedded reconfiguration streamer which automates the dynamic reconfiguration process between multiple predefined configuration profiles.
When enabled, the IP generates reconfiguration report files containing only the setting differences between the multiple reconfiguration profiles
Specifies the number of reconfiguration profiles
Specifies which configuration profile to modify (store, load, clear or refresh) when clicking the corresponding action button.
Generates a MIF file which contains the current configuration.
Use this option for reconfiguration purposes in order to switch between different PLL configurations.
Table 232.
ATX PLL—Generation Options
Parameter
Generate parameter documentation file
Range
On/Off
Table 233.
ATX PLL IP Core Ports pll_powerdown
Port Direction
Input
Description
Generates a .csv file which contains descriptions of ATX PLL
IP core parameters and values.
pll_refclk0 pll_refclk1 pll_refclk2 pll_refclk3 pll_refclk4 tx_serial_clk
Input
Input
Input
Input
Input
Output
Clock Domain
Asynchronous
N/A
N/A
N/A
N/A
N/A
N/A
Description
Resets the PLL when asserted high.
Needs to be connected to a dynamically controlled signal (the
Transceiver PHY Reset Controller pll_powerdown output if using this
Intel FPGA IP).
Reference clock input port 0.
There are a total of five reference clock input ports. The number of reference clock ports available depends on the
Number of PLL reference clocks parameter.
Reference clock input port 1.
Reference clock input port 2.
Reference clock input port 3.
Reference clock input port 4.
High speed serial clock output port for
GX channels. Represents the x1 clock network.
continued...
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Port tx_serial_clk_gt pll_locked pll_pcie_clk reconfig_clk0 reconfig_reset0 reconfig_write0 reconfig_read0 reconfig_address0[9:0] reconfig_writedata0[31:0] reconfig_readdata0[31:0] reconfig_waitrequest0 pll_cal_busy mcgb_rst mcgb_aux_clk0 tx_bonding_clocks[5:0] mcgb_serial_clk
Direction
Output
Output
Output
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
Input
Output
Output
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Clock Domain
N/A
Asynchronous
N/A
N/A reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0
Asynchronous
Asynchronous
N/A
N/A
N/A
Description
High speed serial clock output port for
GT channels. Represents the GT clock network.
Active high status signal which indicates if the PLL is locked.
Used for PCIe. (54)
Optional Avalon interface clock. Used for PLL reconfiguration. The reconfiguration ports appear only if the
Enable Reconfiguration parameter is selected in the PLL IP Core GUI. When this parameter is not selected, the ports are set to OFF internally.
Used to reset the Avalon interface.
Asynchronous to assertion and synchronous to deassertion.
Active high write enable signal.
Active high read enable signal.
10-bit address bus used to specify address to be accessed for both read and write operations.
32-bit data bus. Carries the write data to the specified address.
32-bit data bus. Carries the read data from the specified address.
Indicates when the Avalon interface signal is busy. When asserted, all inputs must be held constant.
Status signal which is asserted high when PLL calibration is in progress.
OR this signal with before connecting to the reset controller IP.
tx_cal_busy
port
Master CGB reset control.
Deassert this reset at the same time as pll_powerdown
.
Used for PCIe implementation to switch between fPLL and ATX PLL during link speed negotiation.
Optional 6-bit bus which carries the low speed parallel clock outputs from the master CGB. Each transceiver channel in a bonded group has this 6bit bus.
Used for channel bonding, and represents the x6/xN clock network.
High speed serial clock output for x6/xN non-bonded configurations.
continued...
(54) Connect this clock to hclk
in PCIe applications.
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pcie_sw[1:0]
Port pcie_sw_done[1:0] atx_to_fpll_cascade_clk ext_lock_detect_clklow
)
ext_lock_detect_fref
)
Direction
Input
Output
Output
Output
Output
Clock Domain
Asynchronous
Asynchronous
N/A
N/A
N/A
Description
2-bit rate switch control input used for
PCIe protocol implementation.
2-bit rate switch status output used for
PCIe protocol implementation.
The ATX PLL output clock is used to drive fPLL reference clock input (only available in SDI_cascade or
OTN_cascade protocol mode).
Clklow
output for external lock detection. It can be exposed by selecting the Enable clklow and fref port
Fref output for external lock detection.
It can be exposed by selecting the
Enable clklow and fref port.
Related Information
•
on page 29
• Avalon Interface Specifications
The ports related to reconfiguration are compliant with the Avalon specification.
Refer to the Avalon specification for more details about these ports.
• Intel Arria 10 Device Datasheet
Refer to the Intel Arria 10 Device Datasheet for more details about the PLL output frequency range.
•
Reconfiguration Interface and Dynamic Reconfiguration
on page 502
•
Reconfiguring Channel and PLL Blocks on page 503
•
Steps to Perform Dynamic Reconfiguration
on page 516
• Intel Arria 10 device fPLL reports an unlocked condition
3.1.3. fPLL
There are two fPLLs in each transceiver bank with six channels (one located at the top and the other at the bottom of the bank). Transceiver banks with three channels have only one fPLL.
Figure 171. fPLL Block Diagram
Dedicated Reference Clock Pin
Reference Clock Network
Receiver Input Pin
Output of Another PLL with PLL Cascading
Global Clock or Core Clock
Refclk
Multiplexer
Input
Reference
Clock
N Counter refclk
PFD
Up
Down
Charge
Pump and
Loop Filter fbclk
VCO /2
/2
L Counter
/1, 2, 4, 8
M Counter
Delta Sigma
Modulator
C Counter
(55)
The fPLL fref
and detection logic.
clklow
signals should only be used with the Intel external soft lock
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When in core mode, for the fPLL to generate output clocks with a fixed frequency and phase relation to an input reference clock, the Enable phase alignment option must be selected. In the fractional frequency mode, the fPLL supports data rates from 1
Gbps to 12.5 Gbps.
Input Reference Clock
This is the dedicated input reference clock source for the PLL.
The input reference clock can be sourced from one of the following:
• Dedicated reference clock pin
• Reference clock network
• Receiver input pin
• Output of another PLL with PLL cascading
• Global clock or the core clock network
The input reference clock is a differential signal. Intel recommends using the dedicated reference clock pin as the input reference clock source for best jitter performance. For protocol jitter compliance at data rates > 10 Gbps, Intel recommends using the dedicated reference clock pin in the same triplet with the fPLL as the input reference clock source.The input reference clock must be stable and freerunning at device power-up for proper PLL operation. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.
Sourcing reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to the fPLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details.
The fPLL calibration is clocked by the CLKUSR clock, which must be stable and
available for the calibration to proceed. Refer to the Calibration on page 567 section
for details about PLL calibration and CLKUSR clock.
Reference Clock Multiplexer
The refclk
mux selects the reference clock to the PLL from the various available reference clock sources.
N Counter
The N counter divides the reference clock ( refclk
) mux's output. The N counter division helps lower the loop bandwidth or reduce the frequency within the phase frequency detector's (PFD) operating range. The N counter supports division factors from 1 to 32.
Phase Frequency Detector
The reference clock
(refclk)
signal at the output of the N counter block and the feedback clock
(fbclk)
signal at the output of the M counter block are supplied as an inputs to the PFD. The output of the PFD is proportional to the phase difference between the refclk
and fbclk
inputs. The PFD aligns the fbclk
to the refclk
The PFD generates an "Up" signal when the reference clock's falling edge occurs
.
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before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's falling edge occurs before the reference clock's falling edge.
Charge Pump and Loop Filter (CP + LF)
The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the
PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency.
Voltage Controlled Oscillator
The fPLL has a ring oscillator based VCO. The VCO transforms the input control voltage into an adjustable frequency clock.
VCO freq = 2 * M * Input reference clock/N. (N and M are the N counter and M counter division factors.)
L Counter
The L counter divides the VCO's clock output. When the fPLL acts as a transmit PLL, the output of the L counter drives the clock generation block (CGB) and the TX PMA via the X1 clock lines.
M Counter
The M counter divides the VCO's clock output. The M counter can select any VCO phase. The outputs of the M counter and N counter have same frequency. M counter range is 8 to 127 in integer mode and 11 to 123 in fractional mode.
Delta Sigma Modulator
The delta sigma modulator is used in fractional mode. It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis.
In fractional mode, the M value is as follows:
M (integer) + K/2^32, where K is the fractional multiply factor (K) in the fPLL IP
Parameter Editor. The legal values of K are greater than 1% and less than 99% of the full range of 2^32 and can only be manually entered in the fPLL IP Parameter Editor in the Quartus Prime software.
The output frequencies can be exact when the fPLL is configured in fractional mode.
Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz VCO frequency, not all desired fractional values can be achieved exactly. The lock signal is not available, when configured in fractional mode in the K-precision mode (K < 0.1 or
K > 0.9).
C Counter
The fPLL C counter division factors range from 1 to 512.
Dynamic Phase Shift
The dynamic phase shift block allows you to adjust the phase of the C counters in user mode. In fractional mode, dynamic phase shift is only available for the C counters.
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Latency
The C counters can be configured to select any VCO phase and a delay of up to 128 clock cycles. The selected VCO phase can be changed dynamically.
Related Information
•
on page 567
•
on page 567
Details about PLL calibration
• How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?
3.1.3.1. Instantiating the fPLL IP Core
The fPLL IP core for Arria 10 transceivers provides access to fPLLs in hardware. One instance of the fPLL IP core represents one fPLL in the hardware.
1. Open the Quartus Prime software.
2. Click Tools ➤ IP Catalog.
3. In IP Catalog, under Library
➤
Transceiver PLL , select Arria 10 Transceiver
fPLL IP core and click Add.
4. In the New IP Instance dialog box, provide the IP instance name.
5. Select the Arria 10 device family.
6. Select the appropriate device and click OK.
The fPLL IP core Parameter Editor window opens.
3.1.3.2. fPLL IP Core
Table 234.
fPLL IP Core Configuration Options, Parameters, and Settings fPLL Mode
Parameters
Protocol Mode
Range
Core
Cascade Source
Transceiver
Description
Specifies the fPLL mode of operation.
Select Core to use fPLL as a general purpose PLL to drive the FPGA core clock network.
Select Cascade Source to connect an fPLL to another PLL as a cascading source.
Select Transceiver to use an fPLL as a transmit PLL for the transceiver block.
Governs the internal setting rules for the VCO.
This parameter is not a preset. You must set all parameters for your protocol.
Enable fractional mode
Basic
PCIe* Gen1
PCIe Gen2
PCIe Gen3
SDI_cascade
OTN_cascade
SDI_direct
SATA TX
OTN_direct
SATA_Gen3
HDMI
On/Off Enables the fractional frequency mode.
continued...
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Divide factor (N-counter)
Divide factor (L-counter)
Divide factor (K-counter)
PLL output frequency
PLL Datarate
Parameters
Enable physical output clock parameters
Enable clklow and fref ports (56)
Desired Reference clock frequency
Actual reference clock frequency
Number of PLL reference clocks
New parameter: Selected reference clock source
Bandwidth
Operation mode
Multiply factor (M-counter)
Range
On/Off
On/Off
Description
This enables the PLL to output frequencies which are not integral multiples of the input reference clock.
Selecting this option allows you to manually specify M, N, C and L counter values.
Enables fref and clklow clock ports for external lock detector. In Transceiver mode when "enable fractional mode" and "SDI_direct" prot_mode are selected,
pll_locked port is not available and user can create external lock detector using fref and clklow clock ports.
Refer to the GUI Specifies the desired PLL input reference clock frequency.
Read-only Displays the actual PLL input reference clock frequency.
1 to 5
0 to 4
Specify the number of input reference clocks for the fPLL.
Specifies the initially selected reference clock input to the fPLL.
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection.
Low
Medium
High
Direct
Feedback compensation bonding
8 to 127
(integer mode)
11 to 123
(fractional mode)
Specifies the feedback operation mode for the fPLL.
Specifies the multiply factor (M-counter).
1 to 31
1, 2, 4, 8
User defined
Read-only
Read-only
Specifies the divide factor (N-counter).
Specifies the divide factor (L-counter).
Specifies the divide factor (K-counter).
Displays the target output frequency for the PLL.
Displays the PLL datarate.
Table 235.
fPLL—Master Clock Generation Block Parameters and Settings
Parameters
Include Master Clock Generation
Block
Clock division factor
Enable x6/xN non-bonded highspeed clock output port
Enable PCIe clock switch interface
Range
On/Off
1, 2, 4, 8
On/Off
On/Off
Description
When enabled, includes a master CGB as a part of the fPLL
IP core. The PLL output drives the master CGB.
This is used for x6/xN bonded and non-bonded modes.
Divides the master CGB clock input before generating bonding clocks.
Enables the master CGB serial clock output port used for x6/xN non-bonded modes.
Enables the control signals used for PCIe clock switch circuitry.
continued...
(56)
The fPLL fref
and detection logic.
clklow
signals should only be used with the Intel external soft lock
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Parameters
MCGB input clock frequency
MCGB output data rate
Enable bonding clock output ports
Enable feedback compensation bonding
PMA interface width
Range
Read only
Read only
On/Off
On/Off
8, 10, 16, 20,
32, 40, 64
Description
Displays the master CGB’s required input clock frequency.
You cannot set this parameter.
Displays the master CGB’s output data rate. You cannot set this parameter.
This value is calculated based on MCGB input clock frequency and MCGB clock division factor.
Enables the tx_bonding_clocks
output ports of the
Master CGB used for channel bonding.
You must enable this parameter for bonded designs.
Enables the feedback output path of the master CGB used for feedback compensation bonding. When enabled, the feedback connections are automatically handled by the PLL
IP.
Specifies the PMA-PCS interface width.
Match this value with the PMA interface width selected for the Native PHY IP core. You must select a proper value for generating bonding clocks for the Native PHY IP core.
Table 236.
fPLL—Dynamic Reconfiguration Parameters and Settings
Parameter
Enable reconfiguration
Enable Altera Debug Master
Endpoint
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Configuration file prefix
Generate SystemVerilog package
file
Generate C header file
Generate MIF (Memory Initialize
File)
Range
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Description
Enables the PLL reconfiguration interface. Enables the simulation models and adds more ports for reconfiguration.
When you turn this option ON, the transceiver PLL IP core includes an embedded Altera Debug Master Endpoint
(ADME) that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
When enabled, the reconfig_waitrequest
does not indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status is reflected in a soft status register bit. (Only available if "Enable control and status registers feature" is enabled).
Enables capability registers that provide high-level information about the fPLL's configuration.
Sets a user-defined numeric identifier that can be read from the user_identifier are enabled.
offset when the capability registers
Enables soft registers for reading status signals and writing control signals on the PLL interface through the embedded debug logic.
Enter the prefix name for the configuration files to be generated.
Generates a SystemVerilog package file containing all relevant parameters used by the PLL.
Generates a C header file containing all relevant parameters used by the PLL.
Generates a MIF file that contains the current configuration.
Use this option for reconfiguration purposes in order to switch between different PLL configurations.
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Table 237.
Clock Switchover (between Dynamic Reconfiguration and General Options)
Clock Switchover Parameter
Create a second input clock pllrefclk1
Second Reference Clock Frequency User Defined
Switchover Mode
Switchover Delays
Create an active_clk signal to indicate the input clock in use
Create a clkbad signal for each of the input clocks
On/Off
Automatic Switchover
Manual Switchover
Automatic Switchover with Manual
Override
0 to 7
On/Off
On/Off
Range Description
Turn on this parameter to have a backup clock attached to your fPLL that can switch with your original reference clock
Specifies the second reference clock frequency for fPLL
Specifies how Input frequency switchover is handled. Automatic
Switchover uses built in circuitry to detect if one of your input clocks has stopped toggling and switch to the other.
Manual Switchover creates an
EXTSWITCH
signal which can be used to manually switch the clock by asserting high for at least 3 cycles.
Automatic Switchover with Manual
Override acts as Automatic Switchover until the
EXTSWITCH
goes high, in which case it switches and ignores any automatic switches as long as
EXTSWITCH
stays high.
Adds a specific amount of cycle delay to the Switchover Process.
This parameter creates an output that indicates which input clock is currently in use by the PLL. Low indicates refclk
, High indicates refclk1.
This parameter creates two outputs, one for each input clock. Low indicates the
CLK clkbad
is working, High indicates the
CLK
is not working.
Table 238.
fPLL - Generation Options
Parameter
Generates parameter documentation file
Direction
On/Off
Description
Generates a .csv file that contains descriptions of all the fPLL parameters and values.
Table 239.
fPLL IP Core Ports
Port pll_powerdown
Direction input
Clock Domain
Asynchronous pll_refclk0
pll_refclk1 input input
N/A
N/A
Description
Resets the PLL when asserted high.
Needs to be connected to a dynamically controlled signal (the
Transceiver PHY Reset Controller pll_powerdown output if using this
Intel FPGA IP).
Reference clock input port 0.
There are five reference clock input ports. The number of reference clock ports available depends on the
Number of PLL reference clocks parameter.
Reference clock input port 1.
continued...
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pll_refclk2 pll_refclk3 pll_refclk4 tx_serial_clk
Port pll_locked hssi_pll_cascade_clk pll_pcie_clk reconfig_clk0 reconfig_reset0 reconfig_write0 reconfig_read0 reconfig_address0[9:0] reconfig_writedata0[31:0] reconfig_readdata0[31:0] reconfig_waitrequest0 pll_cal_busy mcgb_rst mcgb_aux_clk0 tx_bonding_clocks[5:0] mcgb_serial_clk pcie_sw[1:0]
Direction input input input output output output output input input input input input input output output output input input output output input
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Clock Domain
N/A
N/A
N/A
N/A
Asynchronous
N/A
N/A
N/A reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0
Asynchronous
Asynchronous
N/A
N/A
N/A
Asynchronous
Description
Reference clock input port 2.
Reference clock input port 3.
Reference clock input port 4.
High speed serial clock output port for GX channels. Represents the x1 clock network.
Active high status signal which indicates if PLL is locked.
fPLL cascade clock output port
Used for PCIe.
Optional Avalon interface clock. Used for PLL reconfiguration.
Used to reset the Avalon interface.
Asynchronous to assertion and synchronous to deassertion.
Active high write enable signal.
Active high read enable signal.
10-bit address bus used to specify address to be accessed for both read and write operations.
32-bit data bus. Carries the write data to the specified address.
32-bit data bus. Carries the read data from the specified address.
Indicates when the Avalon interface signal is busy. When asserted, all inputs must be held constant.
Status signal which is asserted high when PLL calibration is in progress.
Perform logical OR with this signal and the tx_cal_busy reset controller IP.
port on the
Master CGB reset control.
Deassert this reset at the same time as pll_powerdown
.
Used for PCIe to switch between fPLL/ATX PLL during link speed negotiation.
Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB.
Used for channel bonding, and represents the x6/xN clock network.
High speed serial clock output for x6/xN non-bonded configurations.
2-bit rate switch control input used for PCIe protocol implementation.
continued...
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Port pcie_sw_done[1:0] atx_to_fpll_cascade_clk fpll_to_fpll_cascade_clk active_clk outclk0 outclk1 outclk2 outclk3 ext_lock_detect_clklow
) ext_lock_detect_fref
) phase_reset phase_en updn cntsel[3:0]
Direction output input output output output output output output output output input input input input
Clock Domain
Asynchronous
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
2-bit rate switch status output used for PCIe protocol implementation.
Enables fPLL to ATX PLL cascading clock input port.
fPLL to fPLL cascade output port
(only in Core mode)
Creates an output signal that indicates the input clock being used by the PLL. A logic Low on this signal indicates refclk0
is being used and a logic High indicates refclk1
Clock Switchover enabled)
is being used (only in Core mode with
Core output clock 0. (only in Core mode)
There are four core fPLL output clock output ports. The number of output clock available depends on the
Selected reference clock source
Core output clock 1. (only in Core mode)
Core output clock 2. (only in Core mode)
Core output clock 3. (only in Core mode)
Clklow output for external lock detection. It can be exposed by selecting the Enable clklow and
fref port.
Fref output for external lock detection It can be exposed by selecting the Enable clklow and fref port.
Dynamic phase shift reset input signal. To be connected to DPS soft
IP phase_reset output.
Dynamic phase shift enable input signal. To be connected to DPS soft
IP phase_en output.
Dynamic phase shift updn input signal. To be connected to DPS soft
IP updn output.
Dynamic phase shift counter bus. To be connected to DPS soft IP cntsel output bus.
Related Information
•
on page 29
•
Reconfiguration Interface and Dynamic Reconfiguration
on page 502
(57)
The fPLL fref
and detection logic.
clklow
signals should only be used with the Intel external soft lock
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• Avalon Interface Specifications
The ports related to reconfiguration are compliant with the Avalon
Specification. Refer to the Avalon Specification for more details about these ports.
• Intel Arria 10 device fPLL reports an unlocked condition
3.1.4. CMU PLL
The clock multiplier unit (CMU) PLL resides locally within each transceiver channel.The
channel PLL's primary function is to recover the receiver clock and data in the transceiver channel. In this case the PLL is used in clock and data recovery (CDR) mode.
When the channel PLL of channels 1 or 4 is configured in the CMU mode, the channel
PLL can drive the local clock generation block (CGB) of its own channel, then the channel cannot be used as a receiver.
The CMU PLL from transceiver channel 1 and channel 4 can also be used to drive other transceiver channels within the same transceiver bank. The CDR of channels 0, 2, 3, and 5 cannot be configured as a CMU PLL.
For datarates lower than 6 Gbps, the local CGB divider has to be engaged (TX local division factor in transceiver PHY IP under the TX PMA tab) .
Figure 172. CMU PLL Block Diagram
User Control
(LTR/LTD)
Lock to
Reference
Controller
Lock
Detector
Lock to Reference
PLL Lock Status
Note:
Reference clock network
Receiver input pin
Refclk
Multiplexer
Input reference
clock
N Counter
CP &
LF refclk
Up
PFD
Down fbclk
VCO L Counter
M Counter
Output
Input Reference Clock
The input reference clock for a CMU PLL can be sourced from either the reference clock network or a receiver input pin. The input reference clock is a differential signal.
For protocol jitter compliance at data rates > 10 Gbps, Intel recommends using the dedicated reference clock pin in the same triplet with the CMU PLL as the input reference clock source.The input reference clock must be stable and free-running at device power-up for proper PLL operation. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available. Refer to the Calibration section for details about PLL calibration and the
CLKUSR
clock requirement.
The CMU PLL calibration is clocked by the
CLKUSR
clock which must be stable and available for calibration to proceed. Refer to the Calibration section for more details about the
CLKUSR
clock.
Reference Clock Multiplexer (Refclk Mux)
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The refclk mux selects the input reference clock to the PLL from the various reference clock sources available.
N Counter
The N counter divides the refclk mux's output. The N counter division helps lower the loop bandwidth or reduce the frequency to within the phase frequency detector's
(PFD) operating range. Possible divide ratios are 1 (bypass), 2, 4, and 8.
Phase Frequency Detector (PFD)
The reference clock
(refclk)
signal at the output of the N counter block and the feedback clock ( fbclk
) signal at the output of the M counter block is supplied as an input to the PFD. The PFD output is proportional to the phase difference between the two inputs. It aligns the input reference clock ( refclk
) to the feedback clock
( fbclk
). The PFD generates an "Up" signal when the reference clock's falling edge occurs before the feedback clock's falling edge. Conversely, the PFD generates a
"Down" signal when feedback clock's falling edge occurs before the reference clock's falling edge.
Charge Pump and Loop Filter (CP + LF)
The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the
PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage which drives the VCO frequency.
Voltage Controlled Oscillator (VCO)
The CMU PLL has a ring oscillator based VCO. For VCO frequency range, refer to the datasheet.
L Counter
The L counter divides the differential clocks generated by the CMU PLL.
M Counter
The M counter is used in the PFD's feedback path. The output of the L counter is connected to the M counter. The combined division ratios of the L counter and the M counter determine the overall division factor in the PFD's feedback path.
Lock Detector (LD)
The lock detector indicates when the CMU PLL is locked to the desired output's phase and frequency. The lock detector XORs the "Up"/"Down" pulses and indicates when the
M counter's output and N counter's output are phase-aligned.
The reference clock ( too high.
refclk
) and feedback clock ( fbclk
) are sent to the PCS's ppm detector block. There is a pre-divider to lower the frequency in case the frequency is
Related Information
•
on page 567
• IntelArria 10 Device Datasheet
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3.1.4.1. Instantiating CMU PLL IP Core
The CMU PLL IP core for Arria 10 transceivers provides access to the CMU PLLs in hardware. One instance of the CMU PLL IP core represents one CMU PLL in hardware.
1. Open the Quartus Prime software.
2. Click Tools ➤ IP Catalog.
3. In IP Catalog, under Library ➤
Transceiver PLL , select Arria 10 Transceiver
CMU PLL and click Add.
4. In the New IP Instance Dialog Box, provide the IP instance name.
5. Select Arria 10 device family.
6. Select the appropriate device and click OK.
The CMU PLL IP core Parameter Editor window opens.
3.1.4.2. CMU PLL IP Core
Table 240.
CMU PLL Parameters and Settings
Parameters
Message level for rule violations
Range
Error
Warning
Bandwidth
Number of PLL reference clocks
Low
Medium
High
1 to 5
Description
Specifies the messaging level to use for parameter rule violations.
• Error - Causes all rule violations to prevent IP generation.
• Warning - Displays all rule violations as warnings and allows IP generation in spite of violations.
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection.
Selected reference clock source
TX PLL Protocol mode
PLL reference clock frequency
PLL output frequency
Multiply factor (M-Counter)
Divide factor (N-Counter)
Divide factor (L-Counter)
0 to 4
BASIC
PCIe
Refer to the GUI
Refer to the GUI
Read only
Read only
Read only
Specifies the number of input reference clocks for the CMU
PLL.
You can use this parameter for data rate reconfiguration.
Specifies the initially selected reference clock input to the
CMU PLL.
This parameter governs the rules for correct protocol specific settings. Certain features of the PLL are only available for specific protocol configuration rules. This parameter is not a preset .
You must set all the other parameters for your protocol.
Selects the input reference clock frequency for the PLL.
Specify the target output frequency for the PLL.
Displays the M-multiplier value.
Displays the N-counter value.
Displays the L-counter value.
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Table 241.
CMU PLL—Dynamic Reconfiguration
Parameters
Enable dynamic reconfiguration
Range
On/Off
Enable Altera Debug Master
Endpoint
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
Generate MIF (Memory Initialize
File)
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Description
Enables the PLL reconfiguration interface. Enables the simulation models and adds more ports for reconfiguration.
When you turn this option On, the transceiver PLL IP core includes an embedded Altera Debug Master Endpoint that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
When enabled, the reconfig_waitrequest
does not indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status is reflected in a soft status register bit. (Only available if "Enable control and status registers feature" is enabled).
Enables capability registers that provide high- level information about the CMU PLL's configuration.
Sets a user-defined numeric identifier that can be read from the user_identifier are enabled.
offset when the capability registers
Enables soft registers for reading status signals and writing control signals on the PLL interface through the embedded debug logic.
Enter the prefix name for the configuration files to be generated.
Generates a SystemVerilog package file containing all relevant parameters used by the PLL.
Generates a C header file containing all relevant parameters used by the PLL.
Generates a MIF file that contains the current configuration.
Use this option for reconfiguration purposes in order to switch between different PLL configurations.
Table 242.
CMU PLL—Generation Options
Parameters
Generate parameter documentation file
Range
On/Off
Table 243.
CMU PLL IP Ports
Port pll_powerdown pll_refclk0
Range input input pll_refclk1 pll_refclk2 input input
Description
Generates a .csv file which contains the descriptions of all
CMU PLL parameters and values.
Clock Domain
Asynchronous
N/A
N/A
N/A
Description
Resets the PLL when asserted high.
Reference clock input port 0.
There are 5 reference clock input ports. The number of reference clock ports available depends on the
Number of PLL reference clocks parameter.
Reference clock input port 1.
Reference clock input port 2.
continued...
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pll_refclk3 pll_refclk4 tx_serial_clk
Port pll_locked reconfig_clk0 reconfig_reset0 reconfig_write0 reconfig_read0 reconfig_address0[9:0] reconfig_writedata0[31:0] reconfig_readdata0[31:0] reconfig_waitrequest0 pll_cal_busy
Range input input output output input input input input input input output output output
Clock Domain
N/A
N/A
Description
Reference clock input port 3.
Reference clock input port 4.
N/A
Asynchronous
N/A
High speed serial clock output port for
GX channels. Represents the x1 clock network.
Active high status signal which indicates if PLL is locked.
Optional Avalon interface clock. Used for PLL reconfiguration. The reconfiguration ports appear only if the
Enable Reconfiguration parameter is selected in the PLL IP Core GUI. When this parameter is not selected, the ports are set to OFF internally.
reconfig_clk0
Used to reset the Avalon interface.
Asynchronous to assertion and synchronous to deassertion.
reconfig_clk0
Active high write enable signal.
reconfig_clk0
Active high read enable signal.
reconfig_clk0
10-bit address bus used to specify address to be accessed for both read and write operations.
reconfig_clk0
32-bit data bus. Carries the write data to the specified address.
reconfig_clk0
32-bit data bus. Carries the read data from the specified address.
reconfig_clk0
Indicates when the Avalon interface signal is busy. When asserted, all inputs must be held constant.
Asynchronous Status signal that is asserted high when PLL calibration is in progress.
Perform logical OR with this signal and the tx_cal_busy controller IP.
port on the reset
Related Information
•
on page 29
•
Reconfiguration Interface and Dynamic Reconfiguration
on page 502
• Avalon Interface Specifications
The ports related to reconfiguration are compliant with the Avalon
Specification. Refer to the Avalon Specification for more details about these ports.
3.2. Input Reference Clock Sources
The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.
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Arria 10 transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:
• Dedicated reference clock pins
• Reference clock network
• The output of another fPLL with PLL cascading (
• Receiver input pins
• Global clock or core clock
)
For the best jitter performance, Intel recommends placing the reference clock as close as possible, to the transmit PLL. For protocol jitter compliance at data rates > 10
Gbps, place the reference clock pin in the same triplet as the transmit PLL.
The following protocols require the reference clock to be placed in same bank as the transmit PLL:
• OTU2e, OTU2, OC-192 and 10G PON
• 6G and 12G SDI
Note: Sourcing a reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to transmit PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details.
For optimum performance of GT channel, the reference clock of transmit PLL is recommended to be from a dedicated reference clock pin in the same bank.
Figure 173. Input Reference Clock Sources
Reference Clock
Network
Dedicated refclk pin
(2)
Input
Reference
Clock
fPLL
Serial Clock
RX pin 2
RX pin 1
RX pin 0
(1) fPLL or ATX PLL
(3) Global or
Core Clock
Note:
Note : (1) You can choose only one of the three RX pins to be used as an input reference clock source. Any RX pin on the same side
of the device can be used as an input reference clock.
(2) Dedicated refclk pin can be used as an input reference clock source only for ATX or fPLL or to the reference clock network.
Reference clock network can then drive the CMU PLL.
(3) The output of another PLL can be used as an input reference clock source during PLL cascading. Arria 10 transceivers support fPLL to fPLL cascading.
• In Arria 10 devices, the FPGA fabric core clock network can be used as an input reference source for any PLL type.
• To successfully complete the calibration process, the reference clocks driving the
PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of
FPGA configuration. Otherwise, recalibration is necessary.
(58) Not available for CMU.
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Related Information
on page 567
For more information about the calibration process
3.2.1. Dedicated Reference Clock Pins
To minimize the jitter, the advanced transmit (ATX) PLL and the fractional PLL (fPLL) can source the input reference clock directly from the reference clock buffer without passing through the reference clock network. The input reference clock is also fed into the reference clock network.
Figure 174. Dedicated Reference Clock Pins
There are two dedicated reference clock ( refclk
) pins available in each transceiver bank. The bottom refclk pin feeds the bottom ATX PLL, fPLL, and CMU PLL. The top refclk
pin feeds the top ATX PLL, fPLL, and CMU
PLL. The dedicated reference clock pins can also drive the reference clock network.
Reference Clock
Network fPLL1
From PLL
Cascading Clock
Network
CH5
CDR PLL
CH4
CMU PLL
CH3
CDR PLL
Reference Clock
Network
ATX PLL1
Refclk
From PLL Feedback and Cascading Clock
Network fPLL0
From PLL
Cascading Clock
Network
CH2
CDR PLL
CH1
CMU PLL
CH0
CDR PLL
Reference Clock
Network
Input Reference Clock to the PLLs
Can Come from Either the Reference
Clock Network or the PLL Feedback and Cascading Clock Network
ATX PLL0
From PLL Feedback and Cascading Clock
Network
Refclk
ATX and fPLL Can Receive the
Input Reference Clock from a
Dedicated refclk Pin
3.2.2. Receiver Input Pins
Receiver input pins can be used as an input reference clock source to transceiver PLLs.
However, they cannot be used to drive core fabric.
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The receiver input pin drives the feedback and cascading clock network, which can then feed any number of transmitter PLLs on the same side of the device. When a receiver input pin is used as an input reference clock source, the clock data recovery
(CDR) block of that channel is not available. As indicated in Figure 173 on page 373,
only one RX differential pin pair per three channels can be used as an input reference clock source at any given time.
3.2.3. PLL Cascading as an Input Reference Clock Source
In PLL cascading, PLL outputs are connected to the feedback and cascading clock network. The input reference clock to the first PLL can be sourced from the same network. In this mode, the output of one PLL drives the reference clock input of another PLL. PLL cascading can generate frequency outputs not normally possible with a single PLL solution. The transceiver in Arria 10 devices support fPLL to fPLL cascading, with only maximum two fPLLs allowed in the cascading chain. ATX PLL to fPLL cascading is available to OTN and SDI protocols only.
Note: • To successfully complete the calibration process, the reference clocks driving the
PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of
FPGA configuration. Otherwise, recalibration is necessary.
• When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.
Related Information
on page 567
For more information about the calibration process
3.2.4. Reference Clock Network
The reference clock network distributes a reference clock source to either the entire left or right side of the FPGA where the transceivers reside. This allows any reference clock pin to drive any transmitter PLL on the same side of the device. Designs using multiple transmitter PLLs which require the same reference clock frequency and are located along the same side of the device, can share the same dedicated reference clock ( refclk
) pin.
3.2.5. Global Clock or Core Clock as an Input Reference Clock
The global clock or the core clock can be used as an input reference clock for any PLL type.
The global or core clock network routes the clock directly to the PLL. In this case the
PLL reference clock network is not used. For best performance, use the dedicated reference clock pins or the reference clock network.
3.3. Transmitter Clock Network
The transmitter clock network routes the clock from the transmitter PLL to the transmitter channel. It provides two types of clocks to the transmitter channel:
• High Speed Serial clock—high-speed clock for the serializer.
• Low Speed Parallel clock—low-speed clock for the serializer and the PCS.
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In a bonded channel configuration, both the serial clock and the parallel clock are routed from the transmitter PLL to the transmitter channel. In a non-bonded channel configuration, only the serial clock is routed to the transmitter channel, and the parallel clock is generated locally within the channel. To support various bonded and non-bonded clocking configurations, four types of transmitter clock network lines are available:
• x1 clock lines
• x6 clock lines
• xN clock lines
• GT clock lines
Related Information
Unused/Idle Clock Line Requirements on page 389
For more information about unused or idle transceiver clock lines in the design.
3.3.1. x1 Clock Lines
The x1 clock lines route the high speed serial clock output of a PLL to any channel within a transceiver bank. The low speed parallel clock is then generated by that particular channel's local clock generation block (CGB). Non-bonded channel configurations use the x1 clock network.
The x1 clock lines can be driven by the ATX PLL, fPLL, or by either one of the two channel PLLs (channel 1 and 4 when used as a CMU PLL) within a transceiver bank.
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Figure 175. x1 Clock Lines x1 Network
Ch 5
CGB fPLL1
Master
CGB
CDR
Ch 4
CGB
ATX PLL1 CMU or CDR
Ch 3
CGB
CDR
Ch 2
CGB fPLL0
Master
CGB
CDR
Ch 1
CGB
ATX PLL0 CMU or CDR
Ch 0
CGB
CDR
3.3.2. x6 Clock Lines
The x6 clock lines route the clock within a transceiver bank. The x6 clock lines are driven by the master CGB. The master CGB can only be driven by the ATX PLL or the fPLL. Because the CMU PLLs cannot drive the master CGB, the CMU PLLs cannot be used for bonding purposes. There are two x6 clock lines per transceiver bank, one for each master CGB. Any channel within a transceiver bank can be driven by the x6 clock lines.
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For bonded configuration mode, the low speed parallel clock output of the master CGB is used and the local CGB within each channel is bypassed. For non-bonded configurations, the master CGB also provides a high speed serial clock output to each channel without bypassing the local CGB within each channel.
The x6 clock lines also drive the xN clock lines which route the clocks to the neighboring transceiver banks.
Figure 176. x6 Clock Lines x6
Top x6
Network x6
Bottom
CGB
Ch 5
CDR
Ch 4
CGB
Master
CGB
CGB
CMU or CDR
Ch 3
CDR
Ch 2
CGB
CDR
Ch 1
CGB
Master
CGB
CGB
CMU or CDR
Ch 0
CDR
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3.3.3. xN Clock Lines
The xN clock lines route the transceiver clocks across multiple transceiver banks.
The master CGB drives the x6 clock lines and the x6 clock lines drive the xN clock lines. There are two xN clock lines: xN Up and xN Down. xN Up clock lines route the clocks to transceiver banks located above the master CGB and xN Down clock lines route the clocks to transceiver banks located below the master CGB. The xN clock lines can be used in both bonded and non-bonded configurations. For bonded configurations, the low speed parallel clock output of the master CGB is used, and the local CGB within each channel is bypassed. For non-bonded configurations, the master
CGB provides a high speed serial clock output to each channel.
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Figure 177. xN Clock Network
Master
CGB1
Master
CGB0 xN Up xN Down x6
Top x6
Bottom
CGB
CGB
CGB
CGB
CGB
CGB
CMU or CDR
Ch 3
CDR
Ch 2
Ch 5
CDR
Ch 4
CDR
Ch 1
CMU or CDR
Ch 0
CDR xN Up xN Down
The maximum channel span of a xN clock network is two transceiver banks above and two transceiver banks below the bank that contains the driving PLL and the master
CGB. A maximum of 30 channels can be used in a single bonded or non-bonded xN group.
The maximum data rate supported by the xN clock network while driving channels in either the bonded or non-bonded mode depends on the voltage used to drive the transceiver banks.
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Related Information
•
Implementing x6/xN Bonding Mode
on page 404
•
on page 389
• IntelArria 10 Device Datasheet
3.3.4. GT Clock Lines
GT clock lines are dedicated clock lines available only in Arria 10 GT devices.
Each ATX PLL has two dedicated GT clock lines that connect the PLL directly to the transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and
4, and the bottom ATX PLL drives channels 0 and 1. These connections bypass the rest of the clock network for higher performance. These channels can be used only for non-bonded configurations.
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Figure 178. GT Clock Lines
ATX PLL1
ATX PLL0
CGB
CGB
CGB
CGB
CGB
CGB
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Ch 5
CDR
Ch 4
CMU or CDR
Ch 3
CDR
Ch 2
CDR
Ch 1
CMU or CDR
Ch 0
CDR
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3.4. Clock Generation Block
In Arria 10 devices, there are two types of clock generation blocks (CGBs)
• Local clock generation block (local CGB)
• Master clock generation block (master CGB)
Each transmitter channel has a local clock generation block (CGB). For non-bonded channel configurations, the serial clock generated by the transmit PLL drives the local
CGB of each channel. The local CGB generates the parallel clock used by the serializer and the PCS.
There are two standalone master CGBs within each transceiver bank. The master CGB provides the same functionality as the local CGB within each transceiver channel. The output of the master CGB can be routed to other channels within a transceiver bank using the x6 clock lines. The output of the master CGB can also be routed to channels in other transceiver banks using the xN clock lines. Each transmitter channel has a multiplexer to select its clock source from either the local CGB or the master CGB.
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Figure 179. Clock Generation Block and Clock Network
The local clock for each transceiver channel can be sourced from either the local CGB via the x1 network, or the master CGB via the x6/xN network. For example, as shown by the red highlighted path, the fPLL 1 drives the x1 network which in turn drives the master CGB. The master CGB then drives the x6 clock network which routes the clocks to the local channels. As shown by the blue highlighted path, the ATX PLL 0 can also drive the x1 clock network which can directly feed a channel's local CGB. In this case, the low speed parallel clock is generated by the local CGB.
x1
Network xN
Up xN
Down x6
Top x6
Bottom fPLL 1
ATX PLL 1 fPLL 0
ATX PLL 0
Master
CGB1
Master
CGB0
CGB
CGB
CGB
CGB
CGB
CGB
Ch 5
CDR
Ch 4
CMU or CDR
Ch 3
CDR
Ch 2
Transceiver
Bank
CDR
Ch 1
CMU or CDR
Ch 0
CDR
3.5. FPGA Fabric-Transceiver Interface Clocking
The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiver and clock signals from the transceiver into the FPGA fabric. These clock signals use the global (GCLK), regional (RCLK), and periphery (PCLK) clock
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networks in the FPGA core. If the Global Signal is set to Off, it does not choose any of the previously mentioned clock networks. Instead, it chooses directly from the local routing between transceiver and FPGA fabric.
The transmitter channel forwards a parallel output clock tx_clkout
to the FPGA fabric to clock the transmitter data and control signals. The receiver channel forwards a parallel output clock rx_clkout
to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric. Based on the receiver channel configuration, the parallel output clock is recovered from either the receiver serial data or the rx_clkout
clock (in configurations without the rate matcher) or the tx_clkout
clock (in configurations with the rate matcher).
Figure 180. FPGA Fabric - Transceiver Interface Clocking
Transmitter PMA Transmitter Standard PCS FPGA
Fabric
Receiver PMA tx_clkout tx_pma_div_clkout
Receiver Standard PCS
PRBS
Generator
/2, /4 tx_coreclkin tx_clkout rx_coreclkin
Parallel Clock
(From Clock
Divider)
Parallel Clock
(Recovered)
Serializer
/66
/40
/33
/2 rx_clkout tx_clkout
PRBS
Verifier
/2, /4 rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clocks tx_pma_div_clkout
Deserializer
/66
/40
/33
/2
Serial Clock
(from CGB) tx_clkout
CDR Recovered
Clock rx_pma_div_clkout rx_clkout
The divided versions of the tx_clkout
and rx_clkout
are available as tx_pma_div_clkout
and rx_pma_div_clkout
, respectively.
rx_clkout or tx_clkout
CMU PLL /
ATX PLL / fPLL
Serial Clock
Input Reference Clock
Parallel Clock
Serial Clock
Parallel and Serial Clocks
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Note:
The output frequency of of the following: tx_pma_div_clkout
and rx_pma_div_clkout can be one
• A divided down version of the tx_clkout
or rx_clkout
respectively, where divide by 1 and divide by 2 ratios are available.
• A divided down version of the serializer clock where divide by 33, 40, and 66 ratios are available.
Refer to the "TX PMA Optional Ports" table in PMA Parameters section for details about selecting the division factor.
These clocks can be used to meet core timing by operating the TX and RX FIFO in double-width mode, as this halves the required clock frequency at the PCS to/from
FPGA interface. These clocks can also be used to clock the core side of the TX and RX
FIFOs when the Enhanced PCS Gearbox is used.
For example, if you use the Enhanced PCS Gearbox with a 66:40 ratio, then you can use tx_pma_div_clkout external clock source.
with a divide-by-33 ratio to clock the write side of the TX
FIFO, instead of using a PLL to generate the required clock frequency, or using an
Related Information
3.6. Transmitter Data Path Interface Clocking
The clocks generated by the PLLs are used to clock the channel PMA and PCS blocks.
The clocking architecture is different for the standard PCS and the enhanced PCS.
Figure 181. Transmitter Standard PCS and PMA Clocking
The master or the local CGB provides the high speed serial clock to the serializer of the transmitter PMA, and the low speed parallel clock to the transmitter PCS.
Transmitter PMA Transmitter Standard PCS FPGA
Fabric
PRBS
Generator tx_coreclkin tx_clkout
From Receiver Standard PCS tx_pma_div_clkout
/2, /4 tx_clkout
Parallel Clock
Serial Clock
Parallel and Serial Clock
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clock
ATX PLL
CMU PLL fPLL
Serial Clock
Input Reference Clock
In the Standard PCS, for configurations that do not use the byte serializer, the parallel clock is used by all the blocks up to the read side of the TX phase compensation FIFO.
For configurations that use the byte serializer block, the clock divided by 2 or 4 is used by the byte serializer and the read side of the TX phase compensation FIFO. The clock used to clock the read side of the TX phase compensation FIFO is also forwarded to the FPGA fabric to provide an interface between the FPGA fabric and the transceiver.
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If the tx_clkout
that is forwarded to the FPGA fabric is used to clock the write side of the phase compensation FIFO, then both sides of the FIFO have 0 ppm frequency difference because it is the same clock that is used.
If you use a different clock than the tx_clkout
to clock the write side of the phase compensation FIFO, then you must ensure that the clock provided has a 0 ppm frequency difference with respect to the tx_clkout
.
Figure 182. Transmitter Enhanced PCS and PMA Clocking
The master or local CGB provides the serial clock to the serializer of the transmitter PMA, and the parallel clock to the transmitter PCS.
Transmitter PMA Transmitter Enhanced PCS FPGA
Fabric
TX
Data &
Control
Parallel Clock
PRBS
Generator
PRP
Generator tx_clkout
KR FEC Enc
KR FEC TX G
KR FEC Scr tx_pma_div_clkout
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
ATX PLL fPLL
CMU PLL
Serial Clock
Input Reference Clock
In the Enhanced PCS, the parallel clock is used by all the blocks up to the read side of the TX phase compensation FIFO. The clocks of all channels in bonded configuration are forwarded. You can pick tx_clkout[0]
as the source for clocking their TX logic in core.
For the enhanced PCS, the transmitter PCS forwards the following clocks to the FPGA fabric: tx_clkout
for each transmitter channel in non-bonded and bonded configuration. In bonded configuration, any requirements.
tx_clkout
can be used depending on your core timing
You can clock the transmitter datapath interface using one of the following methods:
• Quartus Prime selected transmitter datapath interface clock
• User-selected transmitter datapath interface clock
3.7. Receiver Data Path Interface Clocking
The CDR block present in the PMA of each channel recovers the serial clock from the incoming data. The CDR block also divides the recovered serial clock to generate the recovered parallel clock. Both the recovered serial and the recovered parallel clocks are used by the deserializer. The receiver PCS can use the following clocks based on the configuration of the receiver channel:
• Recovered parallel clock from the CDR in the PMA.
• Parallel clock from the clock divider used by the transmitter PCS (if enabled) for that channel.
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For configurations that use the byte deserializer block, the clock divided by 2 or 4 is used by the byte deserializer and the write side of the RX phase compensation FIFO.
Figure 183. Receiver Standard PCS and PMA Clocking
Receiver PMA Receiver Standard PCS FPGA
Fabric rx_coreclkin
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider) rx_clkout tx_clkout
PRBS
Verifier
/2, /4 rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider rx_clkout or tx_clkout
ATX PLL
CMU PLL fPLL
Parallel Clock
Serial Clock
Parallel and Serial Clock Parallel and Serial Clock
Serial Clock
All configurations that use the standard PCS channel must have a 0 ppm phase difference between the receiver datapath interface clock and the read side clock of the
RX phase compensation FIFO.
Figure 184. Receiver Enhanced PCS and PMA Clocking
Receiver PMA Receiver Enhanced PCS rx_pma_div_clkout
FPGA
Fabric
PRBS
Verifier
PRP
Verifier
10GBASE-R
BER Checker rx_clkout
KR FEC Block S KR FEC Dec
Parallel Clock
Serial Clock
Parallel and Serial Clock
The receiver PCS forwards the following clocks to the FPGA fabric:
• rx_clkout
— for each receiver channel when the rate matcher is not used.
• tx_clkout
— for each receiver channel when the rate matcher is used.
You can clock the receiver datapath interface using one of the following methods:
• Quartus Prime selected receiver datapath interface clock
• User-selected receiver datapath interface clock
Related Information
Unused or Idle Clock Line Requirements
on page 389
For more information about unused or idle transceiver clock lines in design.
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3.8. Unused/Idle Clock Line Requirements
Unused or idle transceiver clock lines can degrade if the devices are powered up to normal operating conditions and not configured. This affects designs that configure transceiver RX channels to use the idle clock lines at a later date by using dynamic reconfiguration or a new device programming file. Clock lines affected are unused, or idle RX serial clock lines. Active RX serial clock lines and non-transceiver circuits are not impacted by this issue.
In order to prevent the performance degradation, for idle transceiver RX channels, recompile designs with Intel Quartus Prime version 16.1 or later with the assignment described in the link shown below. The CLKUSR pin must be assigned a 100-125 MHz clock. For used transceiver TX and RX channels, do not assert the analog reset signals indefinitely.
Related Information
Unused Transceiver channels Settings
on page 606
For more information about unused or idle transceiver clock lines in the design. It describes the unused or idle RX serial clock lines assignments in the qsf file.
3.9. Channel Bonding
For Arria 10 devices, two types of bonding modes are available:
• PMA bonding
• PMA and PCS bonding
Note: Channel bonding is not supported by GT channels.
Related Information
Resetting Transceiver Channels
on page 416
Refer to the Timing Constraints for Bonded PCS and PMA Channels section in the
Resetting Transceiver Channels chapter for additional details.
3.9.1. PMA Bonding
PMA bonding reduces skew between PMA channels. In PMA bonding, only the PMA portion of the transceiver datapath is skew compensated and the PCS is not skew compensated.
In Arria 10 devices, there are two PMA bonding schemes:
• x6/xN bonding
• PLL feedback compensation bonding
In either case, the channels in the bonded group need not be placed contiguously.
3.9.1.1. x6/xN Bonding
In x6/xN bonding mode, a single transmit PLL is used to drive multiple channels.
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The steps below explain the x6/xN bonding process:
1. The ATX PLL or the fPLL generates a high speed serial clock.
2. The PLL drives the high speed serial clock to the master CGB via the x1 clock network.
3. The master CGB drives the high speed serial and the low speed parallel clock into the x6 clock network.
4. The x6 clock network feeds the TX clock multiplexer for the transceiver channels within the same transceiver bank. The local CGB in each transceiver channel is bypassed.
5. To drive the channels in adjacent transceiver banks, the x6 clock network drives the xN clock network. The xN clock network feeds the TX clock mutiplexer for the transceiver channels in these adjacent transceiver banks.
x6/xN Bonding Disadvantages x6/xN Bonding has the following disadvantages:
• The maximum data rate is restricted based on the transceiver supply voltage.
Refer to Arria 10 Device Data Sheet.
• The maximum channel span is limited to two transceiver banks above and below the bank containing the transmit PLL. Thus, the maximum span of 30 channels is supported.
Related Information
•
on page 379
• Arria 10 Device Datasheet
3.9.1.2. PLL Feedback Compensation Bonding
In PLL feedback compensation bonding, channels are divided into bonded groups based on physical location with a three-channel or six-channel transceiver bank. All channels within the same six-channel transceiver bank are assigned to the same bonded group.
In PLL feedback compensation bonding, each bonded group is driven by its own set of high-speed serial and low-speed parallel clocks. Each bonded group has its own PLL and master CGB. To maintain the same phase relationship, the PLL and master CGB for different groups share the same reference clocks.
The steps below explain the PLL feedback compensation bonding process:
1. The same input reference clock drives the local PLL in each three-channel or sixchannel transceiver bank.
2. The local PLL for the bonding group drives the master CGB.
3. The master CGB feeds the x6 clock lines. The master CGB drives the transceiver channels in the bonding group via the x6 clock network.
4. The parallel output of the master CGB is the feedback input to the PLL.
5. In this mode, all channels are phase aligned to the same input reference clock.
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Note:
PLL Feedback Compensation Bonding Advantages over x6/xN Bonding Mode
• There is no data rate restriction. The x6 clock network used for PLL feedback compensation bonding can run up to the maximum data rate of the device used.
• There is no channel span limitation. It is possible to bond the entire side of the device using PLL feedback compensation.
PLL Feedback Compensation Bonding Disadvantages over x6/xN Bonding
Mode
• It uses more resources compared to x6/xN bonding. One PLL and one master CGB are used per transceiver bank. This causes higher power consumption compared to x6/xN bonding.
• The skew is higher compared to x6/xN bonding. The reference clock skew between each transceiver bank is higher than the skew contributed by the xN clock network in x6/xN bonding.
• Because the feedback clock for the PLL comes from the master CGB and not from the PLL, the PLL feedback compensation bonding mode has a reference clock limitation. The PLL's N-counter (reference clock divider) is bypassed resulting in only one valid reference clock frequency for a given data rate.
• Feedback compensation bonding only supports integer mode.
In order to minimize the reference clock skew for PLL feedback compensation bonding, use a reference clock input near the center of the bonded group.
x6/xN Bonding Advantages over PLL Feedback Compensation Bonding
• x6/xN uses less resources compared to PLL feedback compensation bonding. Only one PLL and one master CGB are required to drive all channels in the bonded group.
• x6/xN has lower skew compared to PLL feedback compensation bonding.
Related Information
Implementing PLL Feedback Compensation Bonding Mode
on page 405
3.9.2. PMA and PCS Bonding
PMA and PCS bonding reduces skew between both the PMA and PCS outputs within a group of channels.
For PMA bonding, either x6/xN or PLL feedback compensation bonding is used. For
PCS bonding, some of the PCS control signals within the bonded group are skew aligned using dedicated hardware inside the PCS.
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Figure 185. PMA and PCS Bonding
Starting
Delay (Cycles)
2
4
6
4
2
0
Distribution
Delay (Cycles)
4
2
0
2
4
6
Slave PCS
Channel
Slave PCS
Channel
Master PCS
Channel
Slave PCS
Channel
Slave PCS
Channel
Slave PCS
Channel
PMA
PMA
PMA
PMA
PMA
PMA
Note:
For PMA and PCS bonding, the concept of master and slave channels is used. One PCS channel in the bonded group is selected as the master channel and all others are slave channels. To ensure that all channels start transmitting data at the same time and in the same state, the master channel generates a start condition. This condition is transmitted to all slave channels. The signal distribution of this start condition incurs a two parallel clock cycle delay. Because this signal travels sequentially through each
PCS channel, this delay is added per channel. The start condition used by each slave channel is delay compensated based on the slave channel's distance from the master channel. This results in all channels starting on the same clock cycle.
The transceiver PHY IP automatically selects the center channel to be the master PCS channel. This minimizes the total starting delay for the bonded group. For PLL feedback compensation bonding up to all channels on one side can be bonded if the master PCS channel is placed in the center of the bonded group.
Because the PMA and PCS bonding signals travel through each PCS block, the PMA and
PCS bonded groups must be contiguously placed. The channel order needs to be maintained when doing the pin assignments to the dedicated RX serial inputs and TX serial outputs (for example: PIN_BC7 and PIN_BC8 for GXBR4D_TX_CH0p and
GXBR4D_TX_CH0n TX serial outputs). Channels need to be placed in an ascending order from bottom to top. Swapping of channels, when doing pin assignments, leads to errors.
3.9.3. Selecting Channel Bonding Schemes
In Arria 10 devices, select PMA and PCS bonding for bonded protocols that are explicitly supported by the hard PCS blocks. For example, PCI Express, SFI-S, and
40GBASE-KR.
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Select PMA-only bonding when a bonded protocol is not explicitly supported by the hard PCS blocks. For example, for Interlaken protocol, PMA-only bonding is used and a soft PCS bonding IP is implemented in the FPGA fabric.
3.9.4. Skew Calculations
To calculate the maximum skew between the channels, the following parameters are used:
• PMA to PCS datapath interface width (S)
• Maximum difference in number of parallel clock cycles between deassertion of each channel's FIFO reset (N).
To calculate the channel skew, the following five scenarios are considered:
• Non-bonded
In this case, both the PMA and PCS are non-bonded. Skew ranges from 0 UI to
[(S-1) + N*S] UI.
• PMA bonding using x6 / xN clock network
In this case, the PCS is non-bonded. Skew ranges from [0 to (N*S)] UI + x6/xN clock skew.
• PMA bonding using the PLL feedback compensation clock network
In this case, the PCS is non-bonded. Skew ranges from [0 to (N*S)] UI +
(reference clock skew) + (x6 clock skew).
• PMA and PCS bonding using the x6 / xN clock network
Skew = x6 / xN clock skew.
• PMA and PCS bonding using PLL feedback compensation clock network
Skew = (reference clock skew) + (x6 clock skew).
3.10. PLL Feedback and Cascading Clock Network
The PLL feedback and cascading clock network spans the entire side of the device, and is used for PLL feedback compensation bonding and PLL cascading.
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Figure 186. PLL Feedback and Cascading Clock Network
Transceiver Bank fPLL1
C
Connection (1)
PLL Feedback and Cascading Clock Network
0 1 2 3 fbclk refclk
ATX PLL 1 refclk fbclk
Connection (3)
Connection (4)
Master CGB1
Bidirectional
Tristate Buffer fPLL0
C refclk fbclk
ATX PLL 0 refclk fbclk
Connection (2)
Master CGB0
Bidirectional
Tristate Buffer
Legend refclk Lines fbclk Lines
C, M, and CGB Outputs
PLL Cascading
PLL Feedback Compensation Bonding
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Note:
To support PLL feedback compensation bonding and PLL cascading, the following connections are present:
1. The C counter output of the fPLL drives the feedback and cascading clock network.
2. The feedback and cascading clock network drives the feedback clock input of all PLLs.
3. The feedback and cascading clock network drives the reference clock input of all PLLs.
4. The master CGB’s parallel clock output drives the feedback and cascading
clock network.
For PLL cascading, connections (1) and (3) are used to connect the output of one PLL to the reference clock input of another PLL.
The transceivers in Arria 10 devices support fPLL to fPLL, and ATX PLL to fPLL
(via dedicated ATX PLL to fPLL cascade path) cascading. Only maximum two
PLLs allowed in the cascading chain.
When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.
For PLL feedback compensation bonding, connections (2) and (4) are used to connect the master CGB's parallel clock output to the PLL feedback clock input port.
PLL feedback compensation bonding can be used instead of xN bonding. The primary difference between PLL feedback compensation and xN bonding configurations, is for
PLL feedback compensation, the bonded interface is broken down into smaller groups of 6 bonded channels within a transceiver bank. A PLL within each transceiver bank
(ATX PLL or fPLL) is used as a transmit PLL. All the transmit PLLs share the same input reference clock.
In xN bonding configurations, one PLL is used for each bonded group. In PLL feedback compensation bonding, one PLL is used for each transceiver bank that the bonded group spans. There are no data rate limitations in PLL feedback compensation bonding, other than the natural data rate limitations of the transceiver channel and the PLL.
For feedback compensation bonding, the low-speed parallel clock must be the same frequency as the reference clock for the PLL.
fPLL Driving the Core
The fPLL can be used to drive the FPGA fabric. To ensure phase alignment between the input reference clock and the fPLL output clock, the fPLL needs to be configured in integer mode. Refer to the following figures when doing dynamic reconfiguration.
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Figure 187. Fractional and not Phase Aligned refclk N Counter
PFD VCO /2 fPLL M Counter
L Counter
/2
Phase
Multiplexer
C Counters
Figure 188. Integer and Phase Aligned refclk N Counter
PFD VCO /2 fPLL M Counter
L Counter
/2
C Counters
Phase
Multiplexer
PLL Feedback Clock Network
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Figure 189. Integer Mode phase aligned and external feedback fPLL 1
C refclk fpll_t_iqtxrxclk pm_iqtxrxclk_top[5:0] fbclk pm_iqtxrxclk_top[3:0]
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1) fbclk
Ch5 ch5_iqtxrxclk_2 pm_iqtxrxclk_top[5:0] refclk pm_iqtxrxclk_top[3:0] ch5_iqtxrxclk_5
4
6
6
4 fbclk
Ch4 ch4_iqtxrxclk_4 pm_iqtxrxclk_top[5:0] refclk pm_iqtxrxclk_top[3:0] ch4_iqtxrxclk_4
4
6 fbclk
Ch3 ch3_iqtxrxclk_0 pm_iqtxrxclk_top[5:0] refclk pm_iqtxrxclk_top[3:0] ch3_iqtxrxclk_5
4
6 pm_iqtxrx_t[5:0]
0 1 2 3 4 5
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
LCPLL 1
M refclk lc_t_iqtxrxclk pm_iqtxrxclk_top[5:0] fbclk pm_iqtxrxclk_top[3:0]
6
4
Master
CGB 1
Note: (1) RX pin used as reference clock
You must recalibrate the fPLL when you enable the phase alignment option.
1. Modify the fPLL IP to enable fPLL reconfiguration
• Under the Dynamic Reconfiguration Tab, turn ON Enable dynamic reconfiguration.
2. Create logics in the core to perform following steps:
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• Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL to select internal feedback.
• Read-Modify-Write 0x1 to offset address 0x100 of the fPLL, then Read-Modify-
Write 0x1 to offset address 0x000 of the fPLL to request PreSICE to recalibrate the fPLL.
• Monitor bit 1 of offset address of 0x280 of the fPLL and wait until this bit changes to zero. This indicates recalibration is completed. Ensure the fPLL achieves lock.
• Read-Modify-Write 0x0 to offset address 0x126[0] of the fPLL to select the external feedback path.
3. Monitor the fPLL lock signal, wait until the fPLL achieves lock.
Related Information
•
on page 576
•
Implementing PLL Cascading on page 408
3.11. Using PLLs and Clock Networks
In Arria 10 devices, PLLs are not integrated in the Native PHY IP core. You must instantiate the PLL IP cores separately. Unlike in previous device families, PLL merging is no longer performed by the Quartus Prime software. This gives you more control, transparency, and flexibility in the design process. You can specify the channel configuration and PLL usage.
Related Information
PLLs and Clock Networks on page 347
3.11.1. Non-bonded Configurations
In a non-bonded configuration, only the high speed serial clock is routed from the transmitter PLL to the transmitter channel. The low speed parallel clock is generated by the local clock generation block (CGB) present in the transceiver channel. For nonbonded configurations, because the channels are not related to each other and the feedback path is local to the PLL, the skew between channels cannot be calculated.
Also, the skew introduced by the clock network is not compensated.
3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration
In x1 non-bonded configuration, the PLL source is local to the transceiver bank and the x1 clock network is used to distribute the clock from the PLL to the transmitter channel.
For a single channel design, a PLL is used to provide the clock to a transceiver channel.
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Figure 190. PHY IP Core and PLL IP Core Connection for Single Channel x1 Non-Bonded
Configuration Example
Transceiver PLL
Instance (5 GHz)
PLL
Native PHY Instance
(1 CH Non-Bonded 10 Gbps)
TX Channel
To implement this configuration, instantiate a PLL IP core and a PHY IP core and connect them together as shown in the above figure.
Steps to implement a Single Channel x1 Non-Bonded Configuration
1. Instantiate the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to use in your design.
•
Refer to Instantiating the ATX PLL IP Core on page 354 or
on page 370 or
Instantiating the fPLL IP Core on page 362 for
detailed steps.
2. Configure the PLL IP core using the IP Parameter Editor.
• For ATX PLL IP core, do not include the Master CGB.
• For fPLL IP core, set the PLL feedback operation mode to direct.
• For CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required.
3. Configure the Native PHY IP core using the IP Parameter Editor .
• Set the Native PHY IP Core TX Channel bonding mode to Non Bonded .
4. Connect the PLL IP core to the Native PHY IP core. Connect the tx_serial_clk output port of the PLL to IP to the corresponding tx_serial_clk0
input port of the Native PHY IP core. This port represents the input to the local CGB of the channel. The tx_serial_clk
for the PLL represents the high speed serial clock generated by the PLL.
3.11.1.2. Implementing Multi-Channel x1 Non-Bonded Configuration
This configuration is an extension of the x1 non-bonded case. In the following example, 10 channels are connected to two instances of the PLL IP core. Two PLL instances are required because PLLs using the x1 clock network can only span the 6 channels within the same transceiver bank. A second PLL instance is required to provide the clock to the remaining 4 channels.
Because 10 channels are not bonded and are unrelated, you can use a different PLL type for the second PLL instance. It is also possible to use more than two PLL IP cores and have different PLLs driving different channels. If some channels are running at different data rates, then you need different PLLs driving different channels.
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Figure 191. PHY IP Core and PLL IP Core Connection for Multi-Channel x1 Non-Bonded
Configuration
Transceiver PLL
Instance (5 GHz) fPLL
Transceiver PLL
Instance (5 GHz) fPLL
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
Steps to implement a Multi-Channel x1 Non-Bonded Configuration
1. Choose the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to instantiate in your design and instantiate the PLL IP core.
•
Refer to Instantiating the ATX PLL IP Core on page 354 or
on page 370 or
Instantiating the fPLL IP Core on page 362 for
detailed steps.
2. Configure the PLL IP core using the IP Parameter Editor
• For the ATX PLL IP core do not include the Master CGB. If your design uses the
ATX PLL IP core and more than 6 channels, the x1 Non-Bonded Configuration is not a suitable option. Multi-channel xN Non-Bonded or Multi-Channel x1/xN
Non-Bonded are the required configurations when using the ATX PLL IP core and more than 6 channels in the Native PHY IP core.
•
Refer to Figure 192 on page 401 Implementing Multi-Channel xN Non-Bonded
Configuration section or the Figure 193 on page 403 Multi-Channel x1/xN Non-
Bonded Example.
• For the fPLL IP core, set the PLL feedback operation mode to direct.
• For the CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required.
3. Configure the Native PHY IP core using the IP Parameter Editor
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• Set the Native PHY IP core TX Channel bonding mode to Non-Bonded.
• Set the number of channels as per your design requirement. In this example, the number of channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
• The
tx_serial_clk
output
port of the PLL IP core represents the high speed serial clock.
• The Native PHY IP core has 10 (for this example) tx_serial_clk input ports. Each port corresponds to the input of the local CGB of the transceiver channel.
• As shown in the figure above, connect the first 6 tx_serial_clk input
to the first transceiver PLL instance.
• Connect the remaining 4 tx_serial_clk input
to the second transceiver
PLL instance.
3.11.1.3. Implementing Multi-Channel xN Non-Bonded Configuration
Using the xN non-bonded configuration reduces the number of PLL resources and the reference clock sources used.
Figure 192. PHY IP Core and PLL IP Core Connection for Multi-Channel xN Non-Bonded
Configuration
In this example, the same PLL is used to drive 10 channels across two transceiver banks.
Transceiver PLL
Instance (5 GHz)
ATX PLL x1 Master
CGB x6
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel xN
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
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Steps to implement a multi-channel xN non-bonded configuration
1. You can use either the ATX PLL or fPLL for multi-channel xN non-bonded configuration.
•
Refer to Instantiating the ATX PLL IP Core on page 354 or
Instantiating the fPLL IP Core
on page 362 for detailed steps.
• Because the CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL can be used for this example.
2. Configure the PLL IP core using the IP Parameter Editor. Enable Include
Master Clock Generation Block .
3. Configure the Native PHY IP core using the IP Parameter Editor
• Set the Native PHY IP core TX Channel bonding mode to Non-Bonded .
• Set the number of channels as per your design requirement. In this example, the number of channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
• In this case, the PLL IP core has represents the xN clock line.
mcgb_serial_clk
output port. This
• The Native PHY IP core has 10 (for this example) tx_serial_clk input ports. Each port corresponds to the input of the local CGB of the transceiver channel.
• As shown in the figure above, connect the mcgb_serial_clk
output port of the PLL IP core to the 10 tx_serial_clk input
ports of the Native PHY IP core.
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Figure 193. Multi-Channel x1/xN Non-Bonded Example
The ATX PLL IP core has a tx_serial_clk output port. This port can optionally be used to clock the six channels within the same transceiver bank as the PLL. These channels are clocked by the x1 network. The remaining four channels outside the transceiver bank are clocked by the xN clock network.
Transceiver PLL
Instance (5 GHz)
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
ATX PLL x1
TX Channel
CGB xN
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
3.11.2. Bonded Configurations
In a bonded configuration, both the high speed serial and low speed parallel clocks are routed from the transmitter PLL to the transmitter channel. In this case, the local CGB in each channel is bypassed and the parallel clocks generated by the master CGB are used to clock the network.
In bonded configurations, the transceiver clock skew between the channels is minimized. Use bonded configurations for channel bonding to implement protocols such as PCIe and XAUI.
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3.11.2.1. Implementing x6/xN Bonding Mode
Figure 194. PHY IP Core and PLL IP Core Connection for x6/xN Bonding Mode
Transceiver PLL
Instance (5 GHz)
ATX PLL x1
Master
CGB x6 x6 x6 x6 x6 x6 x6 xN xN xN xN
Native PHY Instance
(10 CH x6/xN Bonding 10 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
Steps to implement a x6/xN bonded configuration
1. You can instantiate either the ATX PLL or the fPLL for x6/xN bonded configuration.
•
Refer to Instantiating the ATX PLL IP Core on page 354 or
Instantiating the fPLL IP Core
on page 362 for detailed steps. Because the CMU PLL cannot drive the Master CGB, only the ATX PLL or fPLL can be used for bonded configurations.
2. Configure the PLL IP core using the IP Parameter Editor. Enable Include
Master Clock Generation Block and Enable bonding clock output ports.
3. Configure the Native PHY IP core using the IP Parameter Editor .
• Set the Native PHY IP core TX Channel bonding mode to either PMA
bonding or PMA/PCS bonding .
• Set the number of channels required by your design. In this example, the number of channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to Native PHY IP core.
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• In this case, the PLL IP core has tx_bonding_clocks
output bus with width
[5:0].
• The Native PHY IP core has tx_bonding_clocks
input bus with width [5:0] multiplied by the number of transceiver channels (10 in this case). For 10 channels, the bus width is [59:0].
Note: While connecting tx_bonding_clocks
, leave tx_serial_clk
open to avoid any Intel Quartus Prime software fitter errors.
• Connect the PLL IP core to the PHY IP core by duplicating the output of the
PLL[5:0] for the number of channels. For 10 channels, the Verilog syntax for the input port connection is
.tx_bonding_clocks
({10{tx_bonding_clocks_output}})
.
Note: Although the above diagram looks similar to the 10-channel non-bonded configuration example, the clock input ports on the transceiver channels bypass the local CGB in x6/xN bonding configuration. This internal connection is taken care of when the
Native PHY channel bonding mode is set to Bonded.
Figure 195. x6/xN Bonding Mode —Internal Channel Connections
Ch 2
CGB
(1)
CDR
Ch 1
CGB
(1)
CDR
Ch 0
CGB
(1)
CDR
Note: (1) The local CGB is bypassed by the clock input ports in bonded mode.
Related Information
on page 379
Information on xN Clock Network Span.
3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode
In this bonding mode, the channel span limitations of xN bonding mode are removed.
This is achieved by dividing all channels into multiple bonding groups.
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Figure 196. PHY IP Core and PLL IP Core Connection for PLL Feedback Compensation
Bonding
Reference clock fPLL
Transceiver PLL
Instance (5 GHz)
CGB fPLL
Feedback Clock
Transceiver PLL
Instance (5 GHz)
Feedback Clock
CGB x6 x6
Native PHY Instance
(10 CH Bonded 10 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
The data rate is limited by the x6 network speed limit. A disadvantage of using PLL feedback compensation bonding is that it consumes more PLL resources. Each transceiver bank consumes one PLL and one master CGB.
In PLL feedback compensation bonding mode, the N counter (reference clock divider) is bypassed in order to ensure that the reference clock skew is minimized between the
PLLs in the bonded group. Because the N counter is bypassed, the PLL reference clock has a fixed value for any given data rate.
The PLL IP Core Parameter Editor window displays the required data rate in the
PLL reference clock frequency drop down menu.
Steps to implement a PLL Feedback Compensation Bonding Configuration
1. Instantiate the PLL IP core (ATX PLL or fPLL) you want to use in your design. Refer to
Instantiating the ATX PLL IP Core
on page 354 or Instantiating the fPLL IP Core
on page 362 for detailed steps. Because the CMU PLL cannot drive the master
CGB, only the ATX PLL or fPLL can be used for feedback compensation bonding.
2. Configure the PLL IP core using the IP Parameter Editor.
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• If you use the ATX PLL, set the following configuration settings:
— Under the Master Clock Generation Block Tab
• Enable Include Master Clock Generation Block.
• Turn ON Enable Bonding Clock output ports.
• Turn ON Enable feedback compensation bonding.
— Under the Dynamic Reconfiguration Tab
• Turn ON Enable dynamic reconfiguration
• If you use the fPLL, set the following configuration settings:
— Under the PLL Tab
• Set the PLL Feedback type to feedback compensation bonding.
— Under the Master Clock Generation Block Tab
• Turn ON Enable Bonding Clock output ports.
— Under the Dynamic Reconfiguration Tab
• Turn ON Enable dynamic reconfiguration
3. Configure the Native PHY IP core using the IP Parameter Editor
• Set the Native PHY IP core TX Channel bonding mode to either PMA
bonding or PMA/PCS bonding.
• Turn ON Enable dynamic reconfiguration
4. Create a top level wrapper to connect the PLL IP cores to Native PHY IP core.
• In this case, the PLL IP core has tx_bonding_clocks
output bus with width
[5:0].
• The Native PHY IP core has tx_bonding_clocks
input bus with width [5:0] multiplied by the number of channels in a transceiver bank. (six channels in the transceiver bank).
• Unlike the x6/xN bonding mode, for this mode, the PLL should be instantiated multiple times. (One PLL is required for each transceiver bank that is a part of the bonded group.) Instantiate a PLL for each transceiver bank used.
• Connect the tx_bonding_clocks
output from each PLL to (up to) six channels in the same transceiver bank.
• Connect the PLL IP core to the PHY IP core by duplicating the output of the
PLL[5:0] for the number of transceiver channels used in the bonding group.
Steps to recalibrate the PLL after power up calibration
1. Dynamic reconfigure the PLL to change the feedback from the master CGB to feedback from PLL.
• For ATX PLL, Read-Modify-Write 0x1 to offset address 0x110[2] of the ATX
PLL.
• For fPLL, Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL.
2. Recalibrate the PLL.
3. After recalibration completes, ensure the PLL achieves lock. Dynamic reconfigure the PLL to change the feedback to master CGB.
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Note:
• For ATX PLL, Read-Modify-Write 0x0 to offset address 0x110[2] of the ATX
PLL.
• For fPLL, Read-Modify-Write 0x0 to offset address 0x126[0] of the fPLL.
4. Recalibrate TX PMA of all the bonded channels driven by the ATX PLL or the fPLL.
For this 10-channel example, two ATX PLLs are instantiated. Six channels of the tx_bonding_clocks
on the Native PHY IP core are connected to the first ATX PLL and the remaining four channels are connected to the second ATX PLL's tx_bonding_clock outputs.
Related Information
•
ATX PLL Recalibration on page 581
•
Fractional PLL Recalibration on page 581
•
on page 582
3.11.3. Implementing PLL Cascading
In PLL cascading, the output of the first PLL feeds the input reference clock to the second PLL.
For example, if the input reference clock has a fixed frequency, and the desired data rate was not an integer multiple of the input reference clock, the first PLL can be used to generate the correct reference clock frequency. This output is fed as the input reference clock to the second PLL. The second PLL generates the clock frequency required for the desired data rate.
The transceivers in Arria 10 devices support fPLL to fPLL cascading. For OTN and SDI applications, there is a dedicated clock path for cascading ATX PLL to fPLL in Arria 10 production silicon. Only maximum two PLLs are allowed in the cascading chain.
Note: When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.
Figure 197. PLL Cascading fPLL (Cascade Source) pll_refclk0 hssi_pll_cascade_clk fPLL (Transceiver PLL) pll_refclk0 pll_powerdown pll_locked pll_powerdown
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Steps to implement fPLL to fPLL cascading:
1. Instantiate the fPLL IP core. Refer to Instantiating the fPLL IP Core on page 362
for detailed steps.
2. Set the following configuration settings for the fPLL IP core in the Parameter
Editor:
• Set the fPLL Mode to Cascade Source.
• Set the Desired output clock frequency.
3. Instantiate the fPLL IP core (the second PLL in PLL cascading configuration). Refer to
Instantiating the fPLL IP Core
on page 362 for detailed steps.
4. Configure the second fPLL IP core for the desired data rate and the reference clock frequency. Set reference clock frequency for the second fPLL same as the output frequency of the first fPLL.
5. Connect the fPLL IP core (cascade source) to fPLL IP core (transceiver PLL) as shown in the above figure. Ensure the following connections:
• The fPLL has an output port hssi_pll_cascade_clk
. Connect this port to the second fPLL's pll_refclk0
port.
6. Set the source (upstream) fPLL bandwidth to Low setting and the destination
(downstream) fPLL bandwidth to High setting.
7. If the input reference clock is available at device power-up, the first PLL is calibrated during the power-up calibration. The second PLL need to be recalibrated. Refer to the User Recalibration section. If the input reference clock is not available at device power-up, then re-run the calibration for the first PLL. After the first PLL has been calibrated, re-calibrate the second PLL.
Notes:
• No special configuration is required for the Native PHY instance.
• ATX PLL to fPLL cascading mode is added to address the OTN and SDI jitter requirement. In this mode, ATX PLL generates a relatively high and clean reference frequency in fractional mode. The reference is driving the fPLL, which is running in integer mode. Overall cascaded two PLLs, synthesize a needed frequency for a given data rate.
Related Information
on page 576
3.11.4. Mix and Match Example
In the Arria 10 transceiver architecture, the separate Native PHY IP core and the PLL
IP core scheme allows great flexibility. It is easy to share PLLs and reconfigure data rates. The following design example illustrates PLL sharing and both bonded and nonbonded clocking configurations.
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Figure 198. Mix and Match Design Example
Transceiver Bank
ATX PLL
6.25 GHz
Transceiver Bank
fPLL
5.15625 GHz
Transceiver Bank fPLL, 5.15625 GHz fPLL, 625 MHz
Transceiver Bank fPLL
2.5 GHz
ATX PLL
4 GHz
Transceiver Bank
MCGB
MCGB x1 x1 x6 xN x1 mcgb_aux_clk0 x6 xN
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
10GBASE-KR
10GBASE-KR
10GBASE-KR
10GBASE-KR
1.25G
1.25G
1.25G
1.25G
1.25G GbE
1.25G GbE
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
Unused
Unused
Legend
Interlaken12.5G
10GBASE-KR
1.25G/9.8G/10.3125G
1.25G GbE
PCIe Gen 1/2/3
Unused channel
PLL Instances
In this example, two ATX PLL instances and five fPLL instances are used. Choose an appropriate reference clock for each PLL instance. The IP Catalog lists the available
PLLs.
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Use the following data rates and configuration settings for PLL IP cores:
• Transceiver PLL Instance 0: ATX PLL with output clock frequency of 6.25 GHz
— Enable the Master CGB and bonding output clocks.
• Transceiver PLL instance 1: fPLL with output clock frequency of 5.1625 GHz
• Transceiver PLL instance 2: fPLL with output clock frequency of 5.1625 GHz
• Transceiver PLL instance 3: fPLL with output clock frequency of 0.625 GHz
— Select the Use as Transceiver PLL option.
• Transceiver PLL instance 4: fPLL with output clock frequency of 2.5 GHz
— Select Enable PCIe* clock output port option.
— Select Use as Transceiver PLL option.
• Set Protocol Mode to PCIe Gen2.
— Select the Use as Core PLL option
• Set the Desired frequency to 500 MHz with a phase shift of 0 ps.
• Transceiver PLL instance 6: ATX PLL with output clock frequency of 4 GHz
— Enable Master CGB and bonding output clocks.
— Select Enable PCIe clock switch interface option.
— Set Number of Auxiliary MCGB Clock Input ports to 1.
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Native PHY IP Core Instances
In this example, four Transceiver Native PHY IP core instances and four 10GBASE-KR
PHY IP instances are used. Use the following data rates and configuration settings for the PHY IPs:
• 12.5 Gbps Interlaken with a bonded group of 10 channels
— Set the Interlaken 10x12.5 Gbps preset from the Arria 10 Transceiver Native
PHY IP core GUI.
— Refer to Interlaken on page 94 for more details.
• Custom multi-data rate 1.25G/9.8G/10.3125 Gbps non-bonded group of four channels
— Set the Number of data channels to 4.
— Set TX channel bonding to Not Bonded.
— Under the TX PMA tab, set the Number of TX PLL clock inputs per
channel to 3.
— Under the RX PMA tab, set the Number of CDR reference clocks to 3.
• 1.25 Gbps Gigabit Ethernet with a non-bonded group of two channels
— Set the GIGE-1.25Gbps preset from the Arria 10 Transceiver Native PHY IP core GUI.
— Change the Number of data channels to 2.
• PCIe Gen3 with a bonded group of 8 channels
— Set the PCIe PIPE Gen3x8 preset from the Arria 10 Transceiver Native PHY
IP core GUI.
— Under TX Bonding options, set the PCS TX channel bonding master to channel 5.
Note: The PCS TX channel bonding master must be physically placed in channel 1 or channel 4 within a transceiver bank. In this example, the
5th channel of the bonded group is physically placed at channel 1 in the transceiver bank.
on page 229 for more details.
• 10.3125 Gbps 10GBASE-KR non-bonded group of 4 channels
— Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY IP four times, with one instance for each channel.
— Refer to 10GBASE-KR PHY IP Core on page 135 for more details.
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Connection Guidelines for PLL and Clock Networks
• For 12.5 Gbps Interlaken with a bonded group of 10 channels, connect the tx_bonding_clocks
to the transceiver PLL's tx_bonding_clocks
output port.
Make this connection for all 10 bonded channels. This connection uses a master
CGB and the x6 / xN clock line to reach all the channels in the bonded group.
• Connect the tx_serial_clk
port of the first two instances of the 10GBASE-KR
PHY IP to the tx_serial_clk
port of PLL instance 1 (fPLL at 5.1625 GHz). This connection uses the x1 clock line within the transceiver bank.
• Connect the tx_serial_clk
port of the remaining two instances of the
10GBASE-KR PHY IP to the tx_serial_clk
port of the PLL instance 2 (fPLL at
5.1625 GHz). This connection uses the x1 clock line within the transceiver bank.
• Connect the three tx_serial_clk
ports for the custom multi-data rate PHY IP as follows:
— Connect tx_serial_clk0
port to the tx_serial_clk
port of PLL instance 2
(fPLL at 5.1625 GHz). This PLL instance is shared with the two 10GBASE-KR
PHY IP channels and also uses the x1 clock line within the transceiver bank.
• Connect the 1.25 Gbps Gigabit Ethernet non-bonded PHY IP instance to the tx_serial_clk
port of the PLL instance 5. Make this connection twice, one for each channel. This connection uses the x1 clock line within the transceiver bank.
• Connect the PCIe Gen3 bonded group of 8 channels as follows:
— Connect the tx_bonding_clocks
of the PHY IP to the tx_bonding_clocks port of the Transceiver PLL Instance 6. Make this connection for each of the 8 bonded channels.
— Connect the pipe_sw_done
of the PHY IP to the pipe_sw
port of the transceiver PLL instance 6.
— Connect the pll_pcie_clk
port of the PLL instance 5 to the PHY IP's pipe_hclk_in port.
— Connect tx_serial_clk
port of the PLL instance 5 to the mcgb_aux_clk0 port of the PLL instance 6. This connection is required as a part of the PCIe speed negotiation protocol.
3.11.5. Timing Closure Recommendations
Register mode is harder to close timing in Arria 10 devices. Intel recommends using negative edge capture on the RX side for periphery to core transfers greater than 240
MHz. To be specific, capture on a negative edge clock in the core and then immediately transfer to a positive edge clock.
• Use PCLK clock network for frequencies up to 250 MHz.
• Local routing is recommended for higher frequencies.
For core to periphery transfers on TX targeting higher frequencies (beyond 250 MHz),
Intel recommends using TX Fast Register mode as the PCS FIFO mode. This is the mode with PCLK that should be used by default for most 10GbE 1588 modes and 9.8
Gbps/10.1376 Gbps CPRI mode.
• You can use local routing to get up to 320 MHz in Register mode for the highest speed grade.
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3.12. PLLs and Clock Networks Revision History
Changes Document
Version
2018.06.15
2017.11.06
2016.10.31
2016.05.02
2016.02.11
2015.12.18
2015.11.02
2015.05.11
2014.12.15
Made the following change:
• For fPLL IP Core, added OTN_direct, SATA_Gen3 and HDMI to the range for Protocol Mode.
Made the following changes:
• Updated the "ATX PLL-to-ATX PLL Spacing Guidelines" section with GT channels information.
• Added note "Sourcing reference clock from a cascaded PLL output, global clock or core clock network will introduce additional jitter to transmit PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details."
• Added guidance for jitter compliance for data rates >10 Gbps in the following sections:
— "fPLL"
— "CMU PLL"
— "Input Reference Clock Sources"
Made the following change:
• New section Unused/Idle Clock Line Requirements added.
• Updated ATX PLL, fPLL and CMU PLL parameters.
• Updated ATX PLL and fPLL ports.
• Added new parameters and ports when fPLL is used in core mode.
• Provided additional details for ATX PLL and fPLL fractional mode usage in the "Delta Sigma
Modulator" section.
• Added a new section describing "ATX PLL multi-profile and embedded reconfiguration".
Made the following changes:
• Updated the optimal performance placement guidelines for ATX PLL VCO frequencies.
• Updated placement recommendations for different protocols - OTU2e, OTU2, OC-192, 6G and 12G
SDI.
• Updated the "FPGA Fabric - Transceiver Interface Clocking" figure.
• Updated the maximum data rate to 25.8 Gbps.
Made the following changes:
• Updated the “PLL Cascading” figure.
• Updated the "Dedicated Reference Clock Pins" in the "Input Reference Clock Sources" section.
Made the following changes:
• Updated ATX PLL, CMU PLL and fPLL Configuration Options, Parameters and Settings.
• Updated ATX PLL placement in figures and examples.
• Clarified PLL to PLL cascade support.
• Created TX PLL Recommendations based on datarates.
• Updated ATX PLL, fPLL and CMU PLL Quartus settings.
• Added details and figures for the fPLL driving the fabric use cases.
• Updated PLL Feedback and Cascading Clock Network figure.
• Updated steps to implement PLL cascading.
Made the following changes:
• Updated ATX PLL, CMU PLL and FPLL Configuration Options, Parameters and Settings.
• Modified Transmit PLLs Data Rate Range in Arria 10 Devices.
• Increased xN clock network channel span.
• Added ATX PLL to fPLL cascading details.
Made the following changes:
• Added a note about PLL cascading support in ACDS 14.1 version of Quartus II software.
• Corrected the minimum data rate supported by ATX PLL in Table: Transmit PLLs in Arria 10 Devices.
• Corrected the error in PLL output frequency range for ATX PLL and CMU PLL IP cores.
• Corrected the PLL reference clock frequency range for ATX PLL IP core.
continued...
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Document
Version
2014.08.15
2013.12.02
Changes
• Added a note about jitter performance in Input Reference Clock Sources section.
• Updated the Mix and Match Design Example figure to indicate that MCGB is used in the example.
• Changed the minimum data rate supported by the PLLs to 1 Gbps.
Made the following changes:
• Changed the maximum data rate for GT channels to 25.8 Gbps.
• Changed figure "Arria 10 PLLs and Clock Networks" to indicate channel 0,1,3, and 5 have only the
CDR PLL.
• Updated figure "x1 Clock Lines" to indicate that the channel PLL of channel 1 and channel 4 can be used as CMU PLL or as a CDR.
• Updated ATX PLL, fPLL, and CMU PLL section with a clarification about input reference clock frequency stability at device power-up.
• Updated Instantiating ATX PLL, fPLL, and CMU PLL topics with new IP instantiation flow.
• Updated ATX PLL and fPLL architecture block diagrams to show global clock or core clock as an input reference clock.
• Updated ATX PLL IP section with 14.0 A10 release changes
— Added fractional mode support.
— Added embedded debug parameters in table ATX PLL Dynamic Reconfiguration.
• Updated fPLL IP section with 14.0A10 release changes
— Removed "fPLL -Clock Switch over Parameter and Settings" table.
— Updated table "fPLL Parameter and Settings".
— Added embedded debug parameters in table "fPLL - Dynamic Reconfiguration Parameters and
Settings".
— Removed Number of auxiliary MCGB clock input ports from fPLL IP parameters.
• Added global clock or core clock as an input reference clock source.
• Added a new section for Global Clock or Core Clock as an Input Reference Clock.
• Updated figure "Input Reference Clock Sources".
• Updated Dedicated Reference Clock Pins section "Dedicated Reference Clock Pins".
— Added a connection to indicate that dedicated refclk pins can drive the reference clock network.
— Removed a wrong connection from the diagram.
• Updated xN Clock Lines section with maximum channel span limitations and added a exception for
QPI protocols.
• Added a new image in the FPGA Fabric-Transceiver Interface Clocking section.
• Added a new section for Channel Bonding describing PMA bonding, PMA and PCS bonding in detail.
• Removed xN Clock Network Data Rate Restrictions table.
• Updated chapter to indicate Arria 10 Transceivers support fPLL to fPLL, fPLL to ATX PLL, and fPLL to
CMU PLL cascading.
• Updated Using PLLs and Clock Networks section
— Changed MegaWizard references to IP Catalog and Parameter Editor.
— Updated the valid configurations for PLL IP and Native PHY IP per 14.0A10 release change.
• Removed Table "xN Clock Network Data Rate Restrictions".
• Updated the chapter to indicate Arria 10 transceivers support to fPLL to fPLL, fPLL to ATX PLL, and fPLL to CMU PLL cascading.
Initial release.
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4. Resetting Transceiver Channels
To ensure that transceiver channels are ready to transmit and receive data, you must properly reset the transceiver PHY. Intel recommends a reset sequence that ensures the physical coding sublayer (PCS) and physical medium attachment (PMA) in each transceiver channel initialize and function correctly. You can either use the Transceiver
PHY Reset Controller or create your own reset controller.
4.1. When Is Reset Required?
You can reset the transmitter (TX) and receiver (RX) data paths independently or together. The recommended reset sequence requires reset and initialization of the PLL driving the TX or RX channels, as well as the TX and RX datapaths. A reset is required after any of the following events:
Table 244.
Reset Conditions
Event
Device power up and configuration
PLL reconfiguration
Reset Requirement
Requires reset to the transceiver PHY and the associated PLLs to a known initialize state.
Requires reset to ensure that the PLL acquires lock and also to reset the PHY. Both the
PLL and the transmitter channel must be held in reset before performing PLL reconfiguration.
Requires reset to the PLL to ensure PLL lock. You must also reset the PHY.
PLL reference clock frequency change
PLL recalibration
PLL lock loss or recovery
Channel dynamic reconfiguration
Optical module connection
RX CDR lock mode change
Requires reset to the PLL to ensure PLL lock. You must also reset the PHY. Both the PLL and the transmitter channel must be held in reset before performing PLL recalibration.
Requires reset after a PLL acquired lock from a momentary loss of lock. You must also reset the PHY.
Requires holding the channel in reset before performing a dynamic reconfiguration that causes rate change. A PLL reset is not required during channel reconfiguration.
Requires reset of RX to ensure lock of incoming data.
Requires reset of the RX channel any time the RX clock and data recovery (CDR) block switches from lock-to-reference to lock-to-data RX channel.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
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4.2. Transceiver PHY Implementation
Figure 199. Typical Transceiver PHY Implementation clock
Reset Controller
(user-coded or Intel IP) tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
Transceiver PHY Instance
Transmitter
PCS user reset tx_cal_busy (1) rx_cal_busy rx_is_lockedtoref rx_is_lockedtodata
Receiver
PCS
Transmitter
PMA
Receiver
PMA tx_analogreset_ack (2) rx_analogreset_ack (2)
Note:
Transmit
PLL clk_usrpin
Transceiver Reset Sequencer Inferred Block
Optional
Notes:
(1) You can logical OR the pll_cal_busy and tx_cal_busy signals.
(2) tx_analogreset_ack and rx_analogreset_ack are status signals from the Transceiver PHY IP core when these ports are enabled for manual user implementation of Model 2.
Transceiver Reset Endpoints—The Transceiver PHY IP core contains Transceiver
Reset Endpoints (TREs)
) .
Transceiver Reset Sequencer—The Quartus Prime software detects the presence of
TREs and automatically inserts only one Transceiver Reset Sequencer (TRS) (
. The tx_analogreset
and rx_analogreset requests from the reset controller (User coded or Transceiver PHY Reset Controller) is received by the TREs. The TRE sends the reset request to the TRS for scheduling. TRS schedules all the requested PMA resets and sends them back to TREs. You can use either Transceiver PHY Reset Controller or your own reset controller. However, for the TRS to work correctly, the required timing
duration must be followed. See Figure 200 on page 419 for required timing duration.
• The TRS IP is an inferred block and is not visible in the RTL. You have no control over this block.
CLKUSR connection—The clock to the TRS must be stable and free-running
(100-125 MHz). By default, the Quartus Prime software automatically connects the
TRS clock input to the CLKUSR pin on the device. If you are using the CLKUSR pin for your own logic (feeding it to the core), you must instantiate altera_a10_xcvr_clock_module
: altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk));
For more information about the CLKUSR pin, refer to the Arria 10 Pin Connection
Guidelines.
(59) There is only one centralized TRS instantiated for one or more Native PHY.
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Note: To successfully complete the calibration process, the reference clocks driving the PLLs
(ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration. Otherwise, recalibration is necessary.
Related Information
• Arria 10 Pin Connection Guidelines
•
on page 567
For more information about the calibration process
4.3. How Do I Reset?
You reset a transceiver PHY or PLL by integrating a reset controller in your system design to initialize the PCS and PMA blocks. You can save time by using the Intelprovided Transceiver PHY Reset Controller IP core, or you can implement your own reset controller that follows the recommended reset sequence. You can design your own reset controller if you require individual control of each signal for reset or need additional control or status signals as part of the reset functionality.
You can choose from two models for resetting the transceivers, based on your applications:
• Model 1—Default model (Minimum Assertion Time Requirement)
Choose the Arria 10 Default Settings preset for the Transceiver PHY Reset
Controller IP.
The chapter Transceiver Reset Control in Arria 10 Devices explains the default model in detail.
• Model 2—Acknowledgment model
This model uses an event-driven mechanism. The model is used for applications with strict timing requirements.
4.3.1. Model 1: Default Model
4.3.1.1. Recommended Reset Sequence
How to Enable Model 1
Choose the Figure 200 on page 419 for the Transceiver PHY Reset Controller IP. This
populates the reset duration fields with the correct values required by the transceiver reset sequencer (TRS).
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Figure 200. Arria 10 Default Settings Preset
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Figure 201. Transmitter and Receiver Reset Sequence
1
Transmit or
Receive
2
FPGA Device
Power Up/Operation
3
Ensure Calibration
Completed
4
5
6
7
PLL,TX/RX Analog
Reset Asserted
Wait for required time and all gating
conditions and release PLL/Analog
resets
Associated PLL/CDR
Locked
Release TX/RX
Digital Reset
8
TX/RX Reset
Completed
4.3.1.1.1. Resetting the Transmitter During Device Operation
Follow this reset sequence to reset the PLL or the analog or digital blocks of the transmitter at any point during the device operation. Use this reset sequence to reestablish a link or after dynamic reconfiguration. The following steps detail the transmitter reset sequence during device operation. The step numbers correspond to the numbers in the following figure.
1. Perform the following steps:
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a. Assert tx_analogreset
, pll_powerdown
, and tx_digitalreset
while pll_cal_busy
and tx_cal_busy
are low.
b. Deassert pll_powerdown
after a minimum duration of 70 μs.
c. Deassert tx_analogreset
. This step can be done at the same time or after you deassert pll_powerdown
.
2. The pll_locked
signal goes high after the TX PLL acquires lock. Wait for a minimum of 70 μs after deasserting tx_analogreset
to monitor the pll_locked
signal.
3. Deassert tx_digitalreset
, after pll_locked
goes high. The tx_digitalreset
signal must stay asserted for a minimum t tx_digitalreset duration after tx_analogreset
is deasserted.
Note: You must reset the PCS blocks by asserting tx_digitalreset
, every time you assert pll_powerdown
and tx_analogreset
.
Figure 202. Transmitter Reset Sequence During Device Operation
Device Power Up pll_cal_busy tx_cal_busy t req t req tx_analogreset pll_powerdown pll_locked tx_digitalreset treq = 70 μs
1 2
Note:
(1) The Arria 10 Default setting presets tx_digitalreset to 70 μs.
(2) Area in gray is don’t care logic state.
3 t (1) tx_digitalreset
Related Information
Arria 10 Device Datasheet
4.3.1.1.2. Resetting the Receiver During Device Operation
Follow this reset sequence to reset the analog or digital blocks of the receiver at any point during the device operation. Use this reset to re-establish a link or after dynamic reconfiguration.
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Clock Data Recovery in Auto Lock Mode
The step numbers correspond to the numbers in the following figure:
1. Assert rx_analogreset
and rx_digitalreset
. Ensure that rx_cal_busy
is low. You must reset the PCS by asserting rx_digitalreset
every time you assert
rx_analogreset
.
2. Deassert rx_analogreset
after a minimum duration of 70 μs.
3. Ensure rx_is_lockedtodata
is asserted for t
LTD
(minimum of 4 μs) before deasserting rx_digitalreset
.
Figure 203. Resetting the Receiver During Device Operation (Auto Mode)
Device Power Up rx_cal_busy t req rx_analogreset rx_is_lockedtodata rx_digitalreset t req
= 70 μs t
LTD
min 4 μs
1 2 3
Note: rx_is_lockedtodata
will toggle when there is no data at the receiver input.
rx_is_lockedtoref is a don't care when rx_is_lockedtodata
is asserted.
Clock Data Recovery in Manual Lock Mode
Use the clock data recovery (CDR) manual lock mode to override the default CDR automatic lock mode depending on your design requirements.
Related Information
"Transceiver PHY Reset Controller IP Core" chapter of the Altera Transceiver PHY IP
Core User Guide.
Refer to the description of the rx_digitalreset
signal in the "Top-Level Signals" table for information about using the manual lock mode.
Control Settings for CDR Manual Lock Mode
Use the following control settings to set the CDR lock mode:
Table 245.
Control Settings for the CDR in Manual Lock Mode rx_set_locktoref
0
1
X rx_set_locktodata
0
0
1
CDR Lock Mode
Automatic
Manual-RX CDR LTR
Manual-RX CDR LTD
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Resetting the Transceiver in CDR Manual Lock Mode
The numbers in this list correspond to the numbers in the following figure, which guides you through the steps to put the CDR in manual lock mode.
1. Make sure that the calibration is complete ( rx_cal_busy
is low) and the transceiver goes through the initial reset sequence. The rx_digitalreset
and rx_analogreset
signals should be low. The rx_is_lockedtoref
is a don't care and can be either high or low. The rx_is_lockedtodata
and rx_ready signals should be high, indicating that the transceiver is out of reset. Alternatively, you can start directly with the CDR in manual lock mode after the calibration is complete.
2. Assert the rx_set_locktoref
signal high to switch the CDR to the lock-toreference mode. The rx_is_lockedtodata
status signal is deasserted. Assert the rx_digitalreset
signal high at the same time or after rx_set_lockedtoref
is asserted if you use the user-coded reset. When the
Transceiver PHY reset controller is used, the asserted.
rx_digitalreset
is automatically
3. After the rx_digitalreset
signal gets asserted, the rx_ready
status signal is deasserted.
4. Assert the rx_set_locktodata
signal high, t
LTR_LTD_Manual
(minimum 15 μs) after the CDR is locked to reference. rx_is_locktoref
should be high and stable for a minimum t
LTR_LTD_Manual
(15 μs), before asserting rx_set_locktodata
. This is required to filter spurious glitches on rx_is_lockedtoref
. The rx_is_lockedtodata
status signal gets asserted, which indicates that the CDR is now set to LTD mode.
The rx_is_lockedtoref
status signal can be a high or low and can be ignored after asserting rx_set_locktodata
high after the CDR is locked to reference.
5. Deassert the rx_digitalreset
signal after a minimum of t
LTD_Manual
(4 μs).
6. If you are using the Transceiver PHY Reset Controller, the rx_ready
status signal gets asserted after the rx_digitalreset
signal is deasserted. This indicates that the receiver is now ready to receive data with the CDR in manual mode.
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Figure 204. Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock
Mode
Control Signals
rx_set_locktoref
2 t
LTR_LTD_Manual rx_set_locktodata 4 rx_digitalreset
1
2 t
LTD_Manual
5
1 rx_analogreset
Status Signals
rx_is_lockedtoref 1 4 rx_is_lockedtodata 1 2 4
6 rx_ready rx_cal_busy
1
3
4.3.1.1.3. Resetting the Transceiver Channel During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1. Assert tx_analogreset
, pll_powerdown
, tx_digitalreset
, rx_analogreset
, and rx_digitalreset
. Ensure that pll_cal_busy
, tx_cal_busy
, and rx_cal_busy
are low.
2. Deassert pll_powerdown
and minimum duration of 70 μs.
tx_analogreset
at the same time, after a
3. The pll_locked
signal goes high after the TX PLL acquires lock. Wait for a minimum 70 μs after deasserting tx_analogreset
to monitor the pll_locked signal.
4. Deassert tx_digitalreset
after pll_locked
goes high. The tx_digitalreset
signal must stay asserted for a minimum t tx_digitalreset
(minimum of 70 μs) duration after tx_analogreset
is deasserted.
5. Deassert rx_analogreset
after deasserting tx_analogreset
.
6. Ensure rx_is_lockedtodata
is asserted for t
LTD
(minimum of 4 μs) before deasserting rx_digitalreset
.
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Figure 205. Resetting the Transceiver Channel During Device Operation
Device Power Up pll_cal_busy tx_cal_busy rx_cal_busy t req t req tx_analogreset pll_powerdown pll_locked tx_digitalreset rx_analogreset rx_is_lockedtodata rx_digitalreset t rx_digitalreset
min 70 μs t req
= 70 μs
1 2 3 4
5 6 t
LTD
min 4 μs
4.3.1.1.4. Dynamic Reconfiguration of Channel Using the Default Model
TX Channel
The numbers in this list correspond to the numbers in the following figure.
1. Assert tx_analogreset
, pll_powerdown
, and tx_digitalreset
, while pll_cal_busy
and tx_cal_busy
are low.
2. Perform dynamic reconfiguration after minimum 70 μs of asserting tx_analogreset
.
3. Deassert pll_powerdown
after performing a dynamic reconfiguration.
Deassert tx_analogreset
. This step can be done at the same time or after you deassert pll_powerdown
.
4. The pll_locked
signal goes high after the TX PLL acquires lock. Wait for minimum 70 μs after deasserting tx_analogreset
to monitor the pll_locked signal.
5. Deassert tx_digitalreset
after pll_locked
goes high. The tx_digitalreset
signal must stay asserted for a minimum t tx_digitalreset duration after tx_analogreset
is deasserted.
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Figure 206. Dynamic Reconfiguration of Transmitter Channel During Device Operation
Device Power Up pll_cal_busy tx_cal_busy t req
Legal
Reconfiguration
Window t req tx_analogreset pll_powerdown pll_locked tx_digitalreset t tx_digitalreset
(1) t req
= 70 μs 1 2 3
Note:
(1) The Arria 10 Default setting presets ttx_digitalreset to 70 μs.
(2) Area in gray is don’t care zone.
4 5
RX Channel
The numbers in this list correspond to the numbers in the following figure.
1. Assert rx_analogreset
and rx_digitalreset
. Ensure that rx_cal_busy
is low. You must reset the PCS by asserting rx_digitalreset
every time you assert rx_analogreset
.
2. Perform dynamic reconfiguration after minimum 70 μs of asserting rx_analogreset
.
3. Deassert rx_analogreset
after performing dynamic reconfiguration.
4. The rx_is_lockedtodata
signal goes high after the CDR acquires lock.
5. Ensure rx_is_lockedtodata
is asserted for t
LTD
(minimum of 4 μs) before deasserting rx_digitalreset
.
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Figure 207. Dynamic Reconfiguration of Receiver Channel During Device Operation
Device Power Up rx_cal_busy t req
Legal
Reconfiguration
Window rx_analogreset rx_is_lockedtodata rx_digitalreset t req
= 70 μs t
LTD
min 4 μs
1 2 3 4 5
4.3.2. Model 2: Acknowledgment Model
The acknowledgment model uses an event-driven mechanism. It is used for applications with strict timing requirements. Instead of waiting for a minimum assertion time of 70 μs for tx_analogreset
and rx_analogreset
, you must wait to receive the acknowledgment from the Transceiver Native PHY IP core to ensure successful assertion and deassertion of the analog resets.
To enable the acknowledgment model, enable the following ports in the Transceiver
Native PHY IP core:
• Enable the tx_analog_reset_ack
port in the TX PMA
Figure 208. Enabling the tx_analog_reset_ack Port
• Enable the rx_analog_reset_ack
port in the RX PMA
Figure 209. Enabling the rx_analog_reset_ack Port
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Note: tx_analog_reset_ack
and rx_analog_reset_ack
must be treated as asynchronous signals. You must pass them through a synchronizer before sending them to control logic.
4.3.2.1. Recommended Reset Sequence
4.3.2.1.1. Resetting the Transmitter During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1. Assert tx_analogreset
, pll_powerdown
, and tx_digitalreset
, while pll_cal_busy
and tx_cal_busy
are low.
2. Wait for tx_analogreset_ack
to go high, to ensure successful assertion of tx_analogreset
. tx_analogreset_ack
goes high when TRS has successfully completed the reset request for assertion.
a. Deassert pll_powerdown
after t pll_powerdown
.
b. Deassert tx_analogreset
. This step can be done at the same time or after you deassert pll_powerdown
.
3. Wait for tx_analogreset_ack
to go low, to ensure successful deassertion of tx_analogreset
. tx_analogreset_ack
goes low when TRS has successfully completed the reset request for deassertion.
4. The pll_locked
signal goes high after the TX PLL acquires lock. Wait for tx_analogreset_ack
to go low before monitoring the pll_locked
signal.
5. Deassert tx_digitalreset goes high.
a minimum t tx_digitalreset
time after pll_locked
Figure 210. Transmitter Reset Sequence During Device Operation
Device Power Up pll_cal_busy tx_cal_busy tx_analogreset tx_analogreset_ack pll_powerdown pll_locked tx_digitalreset t tx_digitalreset
1 2
Note:
(1) Area in gray is don’t care logic state.
3 4 5
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4.3.2.1.2. Resetting the Receiver During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1. Assert rx_analogreset
and rx_digitalreset
while rx_cal_busy
is low.
2. Wait for rx_analogreset_ack
to go high, to ensure successful assertion of rx_analogreset
. rx_analogreset_ack
goes high when TRS has successfully completed the reset request for assertion.
a. Deassert rx_analogreset
.
3. Wait for rx_analogreset_ack
to go low, to ensure successful deassertion of rx_analogreset
.
rx_analogreset_ack
goes low when TRS has successfully completed the reset request for deassertion.
4. The rx_is_lockedtodata
signal goes high after the CDR acquires lock.
5. Ensure rx_is_lockedtodata
is asserted for t
LTD
(minimum of 4 μs) before deasserting rx_digitalreset
.
Figure 211. Receiver Reset Sequence During Device Operation
Device Power Up rx_cal_busy rx_analogreset rx_analogreset_ack rx_is_lockedtodata rx_digitalreset t
LTD
min 4 μs
1 2 3 4 5
4.3.2.1.3. Dynamic Reconfiguration of Transmitter Channel Using the Acknowledgment
Model
The numbers in this list correspond to the numbers in the following figure.
1. Assert tx_analogreset
, pll_powerdown
, and tx_digitalreset
, while pll_cal_busy
and tx_cal_busy
are low.
2. Wait for tx_analogreset_ack
to go high, to ensure successful assertion of tx_analogreset
. tx_analogreset_ack
goes high when TRS has successfully completed the reset request for assertion.
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a. Perform dynamic reconfiguration.
b. Deassert pll_powerdown
after t pll_powerdown
.
c. Deassert tx_analogreset
. This step can be done at the same time or after you deassert pll_powerdown
.
3. Wait for tx_analogreset_ack
to go low, to ensure successful deassertion of tx_analogreset
. tx_analogreset_ack
goes low when TRS has successfully completed the reset request for deassertion.
4. The pll_locked
signal goes high after the TX PLL acquires lock. Wait for tx_analogreset_ack
to go low before monitoring the pll_locked
signal.
5. Deassert tx_digitalreset
a minimum t tx_digitalreset
time after pll_locked goes high.
Figure 212. Dynamic Reconfiguration of Transmitter Channel During Device Operation
Device Power Up pll_cal_busy tx_cal_busy tx_analogreset tx_analogreset_ack
Legal
Reconfiguration
Window pll_powerdown pll_locked tx_digitalreset t tx_digitalreset
1 2
Note:
(1) Area in gray is don’t care zone.
3 4 5
4.3.2.1.4. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model
The numbers in this list correspond to the numbers in the "Dynamic Reconfiguration of
Receiver Channel During Device Operation" figure below.
1. Assert rx_analogreset
and rx_digitalreset
while rx_cal_busy
is low.
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a. To ensure successful assertion of rx_analogreset
, wait for rx_analogreset_ack
to go high. rx_analogreset_ack
goes high when the TRS has successfully completed the reset request for assertion.
b. Deassert rx_analogreset
.
2. To ensure successful deassertion of rx_analogreset
, wait for rx_analogreset_ack
to go low. rx_analogreset_ack
goes low when the TRS has successfully completed the reset request for deassertion. (60), (61)
3. Wait for rx_analogreset_ack
to go low; then ensure rx_is_lockedtodata signal goes high after the CDR (automatic lock mode) is locked to data.
4. After rx_is_lockedtodata
goes high, wait a minimum of t
LTD
(minimum of 4
μs). Then deassert rx_digitalreset
.
Figure 213. Dynamic Reconfiguration of Receiver Channel During Device Operation
Device Power Up rx_cal_busy rx_analogreset rx_analogreset_ack rx_is_lockedtodata rx_digitalreset
Legal
Reconfiguration
Window t
LTD
min 4 μs
1 2 3 4
(60) If the CDR operates in manual lock mode, step
3 on page 431 and step 4 on page 431 are not
applicable. After rx_analogreset_ack
goes low, apply the reset sequence from the "Reset
Sequence Timing Diagram for Receiver when CDR is in Manual Lock Mode" figure below.
(61) If the receiver signal detector is enabled and the CDR operates in manual lock mode, step
on page 431 and step
on page 431 are not applicable. After rx_analogreset_ack
goes low, wait for rx_std_signaldetect
to go high. When rx_std_signaldetect
is high continuously for 1 μs or more, apply the reset sequence from the "Reset Sequence Timing
Diagram for Receiver when CDR is in Manual Lock Mode" figure below.
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Figure 214. Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock
Mode
Control Signals
rx_set_locktoref
2 t
LTR_LTD_Manual rx_set_locktodata 4 rx_digitalreset
1
2 t
LTD_Manual
5
1 rx_analogreset
Status Signals
rx_is_lockedtoref 1 4 rx_is_lockedtodata 1 2 4
6 rx_ready rx_cal_busy
1
3
4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals
You must reset the digital PCS each time you reset the analog PMA or PLL. However, you can reset the digital PCS block alone.
Table 246.
Transceiver Blocks Affected by Specified Reset and Powerdown Signals
Transceiver
Block
CMU PLL
ATX PLL fPLL
CDR
Receiver
Standard PCS
Receiver
Enhanced PCS
Receiver PMA
Receiver PCIe
Gen3 PCS
Transmitter
Standard PCS
Transmitter
Enhanced PCS
Transmitter PMA
Transmitter PCIe
Gen3 PCS pll_powerdown
Yes
Yes
Yes tx_analogreset
Yes tx_digitalreset
Yes
Yes
Yes rx_analogreset
Yes
Yes rx_digitalreset
Yes
Yes
Yes
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Related Information
on page 576
4.4. Using the Transceiver PHY Reset Controller
Transceiver PHY Reset Controller is a configurable IP core that resets transceivers mainly in response to PLL lock activity. You can use this IP core rather than creating your own user-coded reset controller. You can define a custom reset sequence for the
IP core. You can also modify the IP cores's generated clear text Verilog HDL file to implement custom reset logic.
The Transceiver PHY Reset Controller handles all transceiver reset sequencing and supports the following options:
• Separate or shared reset controls per channel in response to PLL lock activity
• Separate controls for the TX and RX channels and PLLs
• Synchronization of the reset inputs
• Hysteresis for PLL locked status inputs
• Configurable reset timing
• Automatic or manual reset recovery mode in response to loss of PLL lock
You should create your own reset controller if the Transceiver PHY Reset Controller IP does not meet your requirements, especially when you require independent transceiver channel reset. The following figure illustrates the typical use of the
Transceiver PHY Reset Controller in a design that includes a transceiver PHY instance and the transmit PLL.
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Figure 215. Transceiver PHY Reset Controller System Diagram
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Status Signals
clock reset tx_ready
Reset Controller
(user-coded or Intel IP) rx_ready tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset rx_cal_busy rx_is_lockedtoref rx_is_lockedtodata
tx_analogreset_ack
(2)
rx_analogreset_ack
(2) pll_tx_cal_busy tx_cal_busy
(1)
pll_cal_busy
(1)
Transceiver PHY Instance
Transmitter
PCS
Transmitter
PMA
Receiver
PCS
Receiver
PMA
Transmit
PLL clk_usrpin
Transceiver Reset Sequencer Inferred Block
Note:
(1) You can logical OR the pll_cal_busy and tx_cal_busy signals. pll_tx_cal_busy connects to the controller’s tx_cal_busy input port.
Optional
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The Transceiver PHY Reset Controller IP core connects to the Transceiver PHY and the
Transmit PLL. The Transceiver PHY Reset Controller IP core receives status from the
Transceiver PHY and the Transmit PLL. Based on the status signals or the reset input, it generates TX and RX reset signals to the Transceiver PHY and TX PLL.
The tx_ready
signal indicates whether the TX PMA exits the reset state, and if the TX
PCS is ready to transmit data. The rx_ready
signal indicates whether the RX PMA exits the reset state, and if the RX PCS is ready to receive data. You must monitor these signals to determine when the transmitter and receiver are out of the reset sequence.
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP
This section lists steps to configure the Transceiver PHY Reset Controller IP Core in the
IP Catalog. You can customize the following Transceiver PHY Reset Controller parameters for different modes of operation by clicking Tools ➤ IP Catalog.
To parameterize and instantiate the Transceiver PHY Reset Controller IP core:
1. For Device Family, select your target device from the list.
2. Click Installed IP ➤ Library ➤ Interface Protocols ➤ Transceiver PHY ➤
Transceiver PHY Reset Controller.
3. Select the options required for your design. For a description of these options, refer to the Transceiver PHY Reset Controller Parameters.
4. Click Finish. The wizard generates files representing your parameterized IP variation for synthesis and simulation.
4.4.2. Transceiver PHY Reset Controller Parameters
The Quartus Prime software provides a GUI to define and instantiate a Transceiver PHY
Reset Controller to reset transceiver PHY and external PLL.
Table 247.
General Options
Name
Number of transceiver channels
1-1000
Range
Number of TX PLLs
Input clock frequency
Synchronize reset input
Use fast reset for simulation
1-1000
1-500 MHz
On /Off
On /Off
Description
Specifies the number of channels that connect to the Transceiver PHY Reset Controller IP core. The upper limit of the range is determined by your
FPGA architecture.
Specifies the number of TX PLLs that connect to the Transceiver PHY Reset Controller IP core.
Input clock to the Transceiver PHY Reset Controller
IP core. The frequency of the input clock in MHz.
The upper limit on the input clock frequency is the frequency achieved in timing closure.
When On, the Transceiver PHY Reset Controller synchronizes the reset to the Transceiver PHY
Reset Controller input clock before driving it to the internal reset logic. When Off, the reset input is not synchronized.
When On, the Transceiver PHY Reset Controller uses reduced reset counters for simulation.
continued...
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Name
Separate interface per channel/PLL
On /Off
Range Description
When On, the Transceiver PHY Reset Controller provides a separate reset interface for each channel and PLL.
Enable TX PLL reset control pll_powerdown duration
Synchronize reset input for PLL powerdown
Enable TX channel reset control
Use separate TX reset per channel On /Off
TX digital reset mode tx_analogreset duration tx_digitalreset duration pll_locked input hysteresis
Auto, Manual, Expose
Port
1-999999999
1-999999999
0-999999999
TX PLL
On /Off
1-999999999
On /Off
TX Channel
When On, the Transceiver PHY Reset Controller IP core enables the reset control of the TX PLL. When
Off, the TX PLL reset control is disabled.
Specifies the duration of the PLL powerdown period in ns. The value is rounded up to the nearest clock cycle. The default value is 1000 ns.
When On, the Transceiver PHY Reset Controller synchronizes the PLL powerdown reset with the
Transceiver PHY Reset Controller input clock. When
Off, the PLL powerdown reset is not synchronized.
On /Off When On, the Transceiver PHY Reset Controller enables the control logic and associated status signals for TX reset. When Off, disables TX reset control and status signals.
When On, each TX channel has a separate reset.
When Off, the Transceiver PHY Reset Controller uses a shared TX reset controller for all channels.
Specifies the Transceiver PHY Reset Controller behavior when the pll_locked
signal is deasserted. The following modes are available:
• Auto—The associated tx_digitalreset controller automatically resets whenever the pll_locked
signal is deasserted. Intel recommends this mode.
• Manual—The associated tx_digitalreset controller is not reset when the pll_locked signal is deasserted, allowing you to choose corrective action.
• Expose Port—The tx_manual
signal is a toplevel signal of the IP core. You can dynamically change this port to Auto or Manual. (1=
Manual , 0 = Auto)
Specifies the time in ns to continue to assert tx_analoglreset
after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings preset.
Specifies the time in ns to continue to assert the tx_digitalreset
after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings preset. The default value for Model 2 is 20 ns.
Specifies the amount of hysteresis in ns to add to the pll_locked
status input to filter spurious unreliable assertions of the pll_locked
signal. A continued...
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Name Range Description value of 0 adds no hysteresis. A higher value filters glitches on the pll_locked
signal. Intel recommends that the amount of hysteresis be longer than tpll_lock_max_time
.
RX Channel
Enable RX channel reset control On /Off
Use separate RX reset per channel On /Off
RX digital reset mode rx_analogreset duration rx_digitalreset duration
Auto, Manual, Expose
Port
1-999999999
1-999999999
When enabled, the IP enables control logic and status signals for the RX reset signals.
When On, each RX channel has a separate reset input. When Off, uses a shared RX reset controller for all channels.
Specifies the Transceiver PHY Reset Controller behavior when the PLL lock signal is deasserted.
The following modes are available:
• Auto—The associated rx_digitalreset controller automatically resets whenever the rx_is_lockedtodata
signal is deasserted.
• Manual—The associated rx_digitalreset controller is not reset when the rx_is_lockedtodata
signal is deasserted, allowing you to choose corrective action.
• Expose Port—The rx_manual
signal is a toplevel signal of the IP core. If the core includes separate reset control for each RX channel, each RX channel uses its respective rx_is_lockedtodata
signal for automatic reset control; otherwise, the inputs are ANDed to provide internal status for the shared reset controller.
Specifies the time in ns to continue to assert the rx_analogreset
after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle. The default value is 40 ns.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings preset.
Specifies the time in ns to continue to assert the rx_digitalreset
after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle. The default value is 4000 ns.
4.4.3. Transceiver PHY Reset Controller Interfaces
This section describes the top-level signals for the Transceiver PHY Reset Controller IP core.
The following figure illustrates the top-level signals of the Transceiver PHY Reset
Controller IP core. Many of the signals in the figure become buses if you choose separate reset controls. The variables in the figure represent the following parameters:
• <n>—The number of lanes
• <p>—The number of PLLs
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Figure 216. Transceiver PHY Reset Controller IP Core Top-Level Signals
PLL and
Calibration
Status pll_locked[<p>–1:0] pll_select[<p*n>–1:0] tx_cal_busy[<n>–1:0] rx_cal_busy[<n>–1:0]
(1) rx_is_lockedtodata[<n>–1:0] tx_digitalreset[<n>–1:0] tx_analogreset[<n>–1:0] tx_ready[<n>–1:0] rx_digitalreset[<n>–1:0] rx_analogreset[<n>–1:0] rx_ready[<n>–1:0]
PLL
Control
Clock and Reset tx_manual[<n>–1:0] rx_manual[<n>–1:0] clock reset pll_powerdown[<p>–1:0]
Note:
(1) n=1 for pll_select signal width when a single TX reset sequence is used for all channels.
TX and RX
Resets and Status
PLL Powerdown
Note: PLL control is available when you enable the Expose Port parameter.
Table 248.
Top-Level Signals
This table describes the signals in the above figure in the order that they are shown in the figure.
Signal Name pll_locked[<p>-1:0] rx_is_lockedtodata[<n
>-1:0] tx_manual[<n>-1:0]
Direction
Input pll_select[<p*n>-1:0]
Input tx_cal_busy[<n> -1:0]
Input rx_cal_busy[<n> -1:0]
Input
Input
Input
Clock Domain
Asynchronous
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Set to zero when not using multiple PLLs.
Asynchronous
Asynchronous
Synchronous to CDR
Asynchronous
Description
Provides the PLL locked status input from each PLL.
When asserted, indicates that the TX PLL is locked.
When deasserted, the PLL is not locked. There is one signal per PLL.
When you select Use separate TX reset per
channel, this bus provides enough inputs to specify an index for each channel. When Use separate TX reset per channel is disabled, the channels.
pll_locked
signal to listen to for each
pll_select
signal is used for all n=1 when a single TX reset sequence is used for all channels.
This is the calibration status signal that results from the logical OR of pll_cal_busy
and tx_cal_busy signals. The signal goes high when either the TX PLL or
Transceiver PHY initial calibration is active. It is not asserted if you manually re-trigger the calibration IP.
The signal goes low when calibration is completed. This signal gates the TX reset sequence. The width of this signals depends on the number of TX channels.
This is calibration status signal from the Transceiver
PHY IP core. When asserted, the initial calibration is active. When deasserted, calibration has completed.
This signal gates the RX reset sequence. The width of this signals depends on the number of RX channels.
Provides the rx_is_lockedtodata
status from each
RX CDR. When asserted, indicates that a particular RX
CDR is ready to receive input data. If you do not choose separate controls for the RX channels, these inputs are ANDed together internally to provide a single status signal.
This optional signal places controller under automatic or manual control. When asserted, the associated tx_digitalreset tx_digitalreset
controller continued...
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Signal Name rx_manual[<n> -1:0] clock reset tx_digitalreset[<n>-1
:0] tx_analogreset[<n>-1:
0] tx_ready[<n>-1:0] rx_digitalreset[<n>
-1:0]
Direction
Input
Input
Input
Output
Output
Output
Output
Asynchronous
N/A
Clock Domain
Asynchronous
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Description logic does not automatically respond to deassertion of the pll_locked
signal. However, the initial tx_digitalreset
sequence still requires a one-time rising edge on pll_locked
before proceeding. When deasserted, the associated controller automatically begins its reset sequence whenever the selected deasserted.
tx_digitalreset pll_locked
signal is
This optional signal places manual mode, the rx_digitalreset controller under automatic or manual control. In rx_digitalreset
logic
controller does not respond to the assertion or deassertion of the rx_is_lockedtodata
signal. The rx_digitalreset
controller asserts rx_ready
when the rx_is_lockedtodata
signal is asserted.
A free running system clock input to the Transceiver
PHY Reset Controller from which all internal logic is driven. If a free running clock is not available, hold reset until the system clock is stable.
Asynchronous reset input to the Transceiver PHY Reset
Controller. When asserted, all configured reset outputs are asserted. Holding the reset input signal asserted holds all other reset outputs asserted. An option is available to synchronize with the system clock. In synchronous mode, the reset signal needs to stay asserted for at least (2) clock cycles by default.
Digital reset for TX channels. The width of this signal depends on the number of TX channels. This signal is asserted when any of the following conditions is true:
• reset
is asserted
•
•
• pll_powerdown
is asserted pll_cal_busy
is asserted tx_cal_busy
is asserted
• PLL has not reached the initial lock ( deasserted) pll_locked
• pll_locked
is deasserted and tx_manual
is deasserted
When all of these conditions are false, the reset counter begins its countdown for deassertion of tx_digitalreset
.
Analog reset for TX channels. The width of this signal depends on the number of TX channels. This signal is asserted when reset
is asserted.
This signal follows pll_powerdown
, which is deasserted after pll_locked
goes high.
Status signal to indicate when the TX reset sequence is complete. This signal is deasserted while the TX reset is active. It is asserted a few clock cycles after the deassertion of tx_digitalreset
. Some protocol implementations may require you to monitor this signal prior to sending data. The width of this signal depends on the number of TX channels.
Digital reset for RX. The width of this signal depends on the number of channels. This signal is asserted when any of the following conditions is true: continued...
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Signal Name rx_analogreset
[<n>-1:0] rx_ready[<n>-1:0] pll_powerdown[<p>-1:0
]
Direction
Output
Output
Output
Clock Domain
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Description
• reset
is asserted
•
•
• rx_analogreset
is asserted rx_cal_busy
is asserted rx_is_lockedtodata
is deasserted and rx_manual
is deasserted
When all of these conditions are false, the reset counter begins its countdown for deassertion of rx_digitalreset
.
Analog reset for RX. When asserted, resets the RX CDR and the RX PMA blocks of the transceiver PHY. This signal is asserted when any of the following conditions is true:
• reset
is asserted
• rx_cal_busy
is asserted
The width of this signal depends on the number of channels.
Status signal to indicate when the RX reset sequence is complete. This signal is deasserted while the RX reset is active. It is asserted a few clock cycles after the deassertion of rx_digitalreset
. Some protocol implementations may require you to monitor this signal prior to sending data. The width of this signal depends on the number of RX channels.
Asserted to power down a transceiver PLL circuit. When asserted, the selected TX PLL is reset.
Usage Examples for
pll_select
• If a single channel can switch between three TX PLLs, the pll_select
signal indicates which one of the selected three TX PLL's pll_locked
signal is used to communicate the PLL lock status to the TX reset sequence. In this case, to select the 3-bits wide pll_locked
port, the pll_select
port is 2-bits wide.
• If three channels are instantiated with three TX PLLs and with a separate TX reset sequence per channel, the pll_select
field is 6-bits wide (2-bits per channel).
In this case, pll_select [1:0]
represents channel 0, pll_select[3:2] represents channel 1, and pll_select[5:4]
represents channel 2. For each channel, a separate pll_locked
signal indicates the PLL lock status.
• If three channels are instantiated with three TX PLLs and with a single TX reset sequence for all three channels, then pll_select
field is 2-bits wide. In this case, the same pll_locked
signal indicates the PLL lock status for all three channels.
• If one channel is instantiated with one TX PLL, pll_select
field is 1-bit wide.
Connect pll_select
to logic 0.
• If three channels are instantiated with only one TX PLL and with a separate TX reset sequence per channel, the pll_select
field is 3-bits wide. In this case, pll_select
should be set to 0 since there is only one TX PLL available.
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4.4.4. Transceiver PHY Reset Controller Resource Utilization
This section describes the estimated device resource utilization for two configurations of the transceiver PHY reset controller. The exact resource count varies by Quartus
Prime version number, as well as by optimization options.
Table 249.
Reset Controller Resource Utilization
Configuration
Single transceiver channel
Four transceiver channels, shared TX reset, separate RX resets
Combination ALUTs approximately 50 approximately 100
Logic Registers approximately 50 approximately 150
4.5. Using a User-Coded Reset Controller
You can design your own user-coded reset controller instead of using Transceiver PHY
Reset Controller. Your user-coded reset controller must provide the following functionality for the recommended reset sequence:
• A clock signal input for your reset logic
• Holds the transceiver channels in reset by asserting the appropriate reset control signals
• Checks the PLL status (for example, checks the status of pll_locked
and pll_cal_busy
)
Note: You must ensure a stable reference clock is present at the PLL transmitter before releasing pll_powerdown
.
4.5.1. User-Coded Reset Controller Signals
Refer to the signals in the following figure and table for implementation of a usercoded reset controller.
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Figure 217. User-Coded Reset Controller, Transceiver PHY, and TX PLL Interaction clock
User-Coded
Reset
Controller tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
Transceiver PHY Instance
Transmitter
PCS
Transmitter
PMA tx_cal_busy rx_cal_busy rx_is_lockedtoref rx_is_lockedtodata
Receiver
PCS
Receiver
PMA
You can logical OR the pll_cal_busy and tx_cal_busy signals.
Transmit
PLL
Table 250.
User-coded Reset Controller, Transceiver PHY, and TX PLL Signals pll_powerdown tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset clock
Signal Name pll_cal_busy pll_locked tx_cal_busy rx_is_lockedtodata rx_cal_busy rx_is_lockedtoref
Direction
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Description
Resets the TX PLL when asserted high.
Resets the TX PMA when asserted high.
Resets the TX PCS when asserted high.
Resets the RX PMA when asserted high.
Resets the RX PCS when asserted high.
Clock signal for the user-coded reset controller. You can use the system clock without synchronizing it to the PHY parallel clock. The upper limit on the input clock frequency is the frequency achieved in timing closure.
A high on this signal indicates the PLL is being calibrated.
A high on this signal indicates that the TX PLL is locked to the ref clock.
A high on this signal indicates that TX calibration is active. If you have multiple PLLs, you can OR their pll_cal_busy
signals together.
A high on this signal indicates that the RX CDR is in the lock-to-data (LTD) mode.
A high on this signal indicates that RX calibration is active.
A high on this signal indicates that the RX CDR is in the lock-to-reference
(LTR) mode. This signal may toggle or be deasserted when the CDR is in
LTD mode.
4.6. Combining Status or PLL Lock Signals
You can combine multiple PHY status signals before feeding into the reset controller as shown below.
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Figure 218. Combining Multiple PHY Status Signals tx_cal_busy signals from channels
To reset controller tx_cal_busy input port
Note: This configuration also applies to the rx_cal_busy
signals.
When using multiple PLLs, you can logical AND the pll_locked
signals feeding the reset controller. Similarly, you can logical OR the pll_cal_busy
signals to the reset controller tx_cal_busy
port as shown below.
Figure 219. Multiple PLL Configuration pll_lock signals from PLLs
AND
To reset controller pll_locked input port pll_cal_busy and tx_cal_busy signals
To reset controller tx_cal_busy input port
Resetting different channels separately requires multiple reset controllers. For example, a group of channels configured for Interlaken requires a separate reset controller from another group of channels that are configured for optical communication.
4.7. Timing Constraints for Bonded PCS and PMA Channels
For designs that use TX PMA and PCS Bonding, the digital reset signal
( tx_digitalreset
) to all TX channels within a bonded group must meet a maximum skew tolerance imposed by physical routing. This skew tolerance is one-half the TX parallel clock cycle ( tx_clkout
). This requirement is not necessary for TX
PMA Bonding or for RX PCS channels.
Note: If the design is not able to meet the maximum skew tolerance requirement with a positive margin, Intel recommends reassigning the channels locations that are not adjacent to the PCIe Hard IP block.
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Figure 220. Physical Routing Delay Skew in Bonded Channels
FPGA Fabric
PHY Reset
Controller tx_digitalreset
TX
Channel[ n - 1]
Bonded TX
Channels
TX
Channel[1]
TX
Channel[0]
You must provide a Synopsys Design Constraint (SDC) for the reset signals to guarantee that your design meets timing requirements. The Quartus Prime software generates an
.sdc
file when you generate the Transceiver Native PHY IP core.
This
.sdc
contains basic false paths for most asynchronous signals, including resets.
In the case of bonded designs, this file contains examples for maximum skew on bonded designs. This
.sdc
file contains an example false_path
and an example max_skew
constraint for the tx_digitalreset
signals.
All modified IP constraints from a generated
.sdc
file must be moved to the project’s main
.sdc
file, because changes are lost if the IP is regenerated.
This skew is present whether you tie all tx_digitalresets
together, or you control them separately. If your design includes the Transceiver PHY Reset Controller IP core, you can substitute your instance and interface names for the generic names shown in the example.
Example 1. SDC Constraint for TX Digital Reset When Bonded Clocks Are Used set_max_skew -from *<IP_INSTANCE_NAME> *tx_digitalreset*r_reset
-to *pld_pcs_interface* <1/2 coreclk period in ps>
In the above example, you must make the following substitutions:
• <IP_INSTANCE_NAME>—substitute the name of your reset controller IP instance or PHY IP instance
• <½ coreclk period in ps>—substitute half of the clock period of your design in picoseconds
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If your design has custom reset logic, replace the
*<IP_INSTANCE_NAME>*tx_digitalreset*r_reset
with the source register for the TX PCS reset signal, tx_digitalreset
.
For more information about the set_max_skew
Timing Analyzer API Reference Manual.
constraint, refer to the SDC and
Related Information
SDC and Timing Analyzer API Reference Manual
4.8. Resetting Transceiver Channels Revision History
Changes Document
Version
2018.06.15
2017.11.06
2016.05.02
2015.12.18
2015.11.02
2014.12.15
2014.08.15
Made the following changes:
• Clarified the Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model instructions for when the CDR is in manual lock mode.
• Updated the description for the "Enable RX channel reset control" parameter.
Made the following change:
• Added a note "If the design is not able to meet the maximum skew tolerance requirement with a positive margin, Intel recommends reassigning the channels locations that are not adjacent to the
PCIe Hard IP block."
Made the following changes
• Added port "user reset" in "Typical Transceiver PHY Implementation" diagram.
• Added note number 50.
• Updated "Transceiver and Receiver Reset Sequence" diagram.
• Added a note "Area in gray is don't care zone" in every diagram that has gray area in it.
• Changes "tLTD" to "trx_digitalreset" in all the diagrams.
Made the following changes:
• Added description to the "Recommended Reset Sequence" section.
• Added the "Arria 10 Default Settings Preset" figure.
• Changed the signals and added a note in the "Typical Transceiver PHY Implementation" figure.
• Added a parameter to the "General Options" table.
• Updated the "Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock Mode" figure.
• Updated the steps in the "Resetting the Transceiver in CDR Manual Lock Mode" section.
Made the following changes:
• Updated the "Reset Conditions" table.
• Created the "Transceiver PHY Implementation" section.
• Updated the "Typical Transceiver PHY Implementation" figure and moved it to the "Transceiver PHY
Implementation" section.
• Added the "Model 1: Default Model" and "Model 2: Acknowledgment Model" sections to the "How Do
I Reset?" section.
• Updated the "Altera Transceiver PHY Reset Controller System Diagram" in the "Using the Altera
Transceiver PHY Reset Controller" section.
• Added "Usage Examples for pll_select" to the "Transceiver PHY Reset Controller Interfaces" section.
Made the following changes:
• Updated the "Transmitter Reset Sequence After Power-Up" and "Transmitter Reset Sequence During
Device Operation" figures.
• Improved formatting in the "Transceiver PHY Reset Controller IP Core Top-Level Signals" figure.
• Updated the description of the reset, tx_analogreset, and rx_analogreset parameters in the
"Top-Level Signals" table.
Made the following changes: continued...
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Document
Version
2013.12.02
Changes
• Updated the "Transmitter Reset Sequence After Power-Up" and "Receiver Reset Sequence Following
Power-Up" figures.
• Updated the "Resetting the Receiver During Device Operation" procedure and associated figure.
• Updated the "Reset Sequence Timing Diagram for Transceiver when CDR is in Manual Lock Mode" figure.
Initial release.
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5. Arria 10 Transceiver PHY Architecture
5.1. Arria 10 PMA Architecture
The Physical Medium Attachment (PMA) acts as the analog front end for the Arria 10 transceivers.
The PMA receives and transmits high-speed serial data depending on the transceiver channel configuration. All serial data transmitted and received passes through the
PMA.
5.1.1. Transmitter
The transmitter takes the parallel data and serializes it to create a high-speed serial data stream. The transmitter portion of the PMA is composed of the transmitter serializer and the transmitter buffer. The serializer clock is provided from the transmitter PLL.
Figure 221. Transmitter PMA Block Diagram
Transmitter Serial
Differential Output
Data
Transmitter PMA
Transmitter
Buffer
Serial
Data
Serializer
Parallel
Data Transmitter
PCS
Parallel
Data FPGA
Fabric
Serial
Clock
Parallel
Clock Clock
Generation
Block
Transmitter
PLL
Input
Reference
Clock
5.1.1.1. Serializer
The serializer converts the incoming low-speed parallel data from the transceiver PCS or FPGA fabric to high-speed serial data and sends the data to the transmitter buffer.
The channel serializer supports the following serialization factors: 8, 10, 16, 20, 32,
40, and 64.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
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Figure 222. Serializer Block
The serializer block sends out the least significant bit (LSB) of the input data first.
Dn
LSB
D0 D1 D2 Dn
Serial
Data
Serializer D2
Parallel
Data
Serial
Clock
Parallel
Clock
D1
D0
5.1.1.2. Transmitter Buffer
The transmitter buffer includes the following circuitry:
• High Speed Differential I/O
• Programmable differential output voltage (V
OD
)
— Main tap
• Programmable four-tap pre-emphasis circuitry
— Two pre-cursor taps
— Two post-cursor taps
• Power distribution network (PDN) induced inter-symbol interference (ISI) compensation
• Internal termination circuitry
• Receiver detect capability to support PCI Express and Quick Path Interconnect
(QPI) configurations
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Figure 223. Transmitter Buffer
Programmable
Pre-Emphasis and V
OD
Receiver
Detect
R1* On-Chip
Termination
85Ω, 100Ω, OFF
V
TX
CM
R1*
To Serial Data
Output Pins
(tx_serial_data)
R1* - Half of the actual on-chip termination selected.
5.1.1.2.1. High Speed Differential I/O
To improve performance, the Arria 10 transmitter uses a new architecture in the output buffer—High Speed Differential I/O. You should select "High Speed Differential
I/O" for I/O standard of Arria 10 transmitter pin in Quartus Prime Assignment Editor or QSF file.
5.1.1.2.2. Programmable Output Differential Voltage
You can program the differential output voltage (output swing) to handle different channel losses and receiver requirements. There are 31 differential V
OD
settings up to
VCCT power supply level. The step size is 1/30 of the VCCT power supply level.
Figure 224. V
OD
(Differential) Signal Level
Differential Waveform
+V
P
0 V Differential
V
OD
(Differential)
–V
N
V
OD
(Differential) = V
P
- V
N
Related Information
•
XCVR_A10_RX_TERM_SEL on page 589
• For more information, refer to Arria 10 Pre-Emphasis and Output Swing Settings
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5.1.1.2.3. Programmable Pre-Emphasis
Pre-emphasis can maximize the eye at the far-end receiver. The programmable preemphasis module in each transmit buffer amplifies high frequencies in the transmit data signal, to compensate for attenuation in the transmission media.
The pre-tap pre-emphasizes the bit before the transition and de-emphasizes the remaining bits. A different polarity on pre-tap does the opposite.
Table 251.
Pre-Emphasis Taps
All four pre-emphasis taps provide inversion control, shown by negative values.
Pre-Emphasis Tap
Second pre-tap
First pre-tap
First post-tap
Second post-tap
Number of Settings
15
33
51
25
You can set pre-emphasis taps through the Quartus Assignment Editor, the Avalon-MM registers, and the QSF settings.
Related Information
For more information, refer to Arria 10 Pre-Emphasis and Output Swing Settings
5.1.1.2.4. Power Distribution Network (PDN) induced Inter-Symbol Interference (ISI) compensation
Arria 10 Transmitter driver includes a compensation circuitry to reduce PDN induced
ISI jitter. You can enable this compensation circuitry to reduce jitter through QSF setting, Quartus Assignment Editor or Avalon-MM interface. The power consumption increases when you enable the compensation.
5.1.1.2.5. Programmable Transmitter On-Chip Termination (OCT)
Transmitter buffers include programmable on-chip differential termination of 85Ω,
100Ω, or OFF. You can set the OCT value through the Quartus Assignment Editor and the Avalon-MM registers.
Related Information
Arria 10 Register Map
5.1.2. Receiver
The receiver deserializes the high-speed serial data, creates a parallel data stream for either the receiver PCS or the FPGA fabric, and recovers the clock information from the received data.
The receiver portion of the PMA is comprised of the receiver buffer, the clock data recovery (CDR) unit, and the deserializer.
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Figure 225. Receiver PMA Block Diagram
Receiver Serial
Differential Input
Data
Receiver PMA
Receiver
Buffer
Serial
Data
CDR
Serial
Data
Serial Clock
Parallel Clock
Deserializer
Parallel
Data Receiver
PCS
Parallel Data to FPGA Core
5.1.2.1. Receiver Buffer
The receiver input buffer receives serial data from rx_serial_data
and feeds the serial data to the clock data recovery (CDR) unit and deserializer.
Figure 226. Receiver Buffer
CTLE
From Serial Data
Input Pins
(rx_serial_data)
VGA DFE
Serial Data
RX
Termination
85Ω, 100Ω, OFF
Adaptive Parametric
Tuning Engine
V
RX
CM
The receiver buffer supports the following features:
• Programmable common mode voltage (V
CM
)
• Programmable differential On-Chip Termination (OCT)
• Signal Detector
• Continuous Time Linear Equalization (CTLE)
• Variable Gain Amplifiers (VGA)
• Adaptive Parametric Tuning Engine
• Decision Feedback Equalization (DFE)
5.1.2.1.1. Programmable Common Mode Voltage (V
CM
)
The receiver buffer has on-chip biasing circuitry to establish the required V
CM receiver input.
at the
The Quartus Prime software automatically chooses the optimal setting for RX V
CM
.
Note: On-chip biasing circuitry is available only if you select OCT. If you select external termination, you must implement off-chip biasing circuitry to establish the V
CM
at the receiver input buffer.
Manual V
CM
adjustment is not supported and is only adjusted by calibrations.
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5.1.2.1.2. Programmable Differential On-Chip Termination (OCT)
Receiver buffers include programmable on-chip differential termination of 85Ω, 100Ω, or OFF.
You can disable OCT and use external termination. If you select external termination, the receiver common mode is tri-stated. Common mode is based on the external termination connection. You also need to implement off-chip biasing circuitry to establish the V
CM
at the receiver buffer.
5.1.2.1.3. Signal Detector
You can enable the optional signal threshold detection circuitry. If enabled, this option senses whether the signal level present at the receiver input buffer is above the signal detect threshold voltage that you specified in the assignment editor.
5.1.2.1.4. Continuous Time Linear Equalization (CTLE)
The CTLE boosts the signal that is attenuated due to channel characteristics. Each receiver buffer has independently programmable equalization circuits. These equalization circuits amplify the high-frequency component of the incoming signal by compensating for the low-pass characteristics of the physical medium. The CTLE can support both DC and AC gain.
DC gain circuitry provides an equal amplification to the incoming signal across the low frequency spectrum. AC gain circuitry provides amplification to the high-frequency spectrum gain of the incoming signal.
Arria 10 transceivers support dual mode CTLE.
High Gain Mode
High gain mode supports data rate up to 17.4 Gbps. This mode provides both AC and
DC gain. There are two bandwidth settings available for this mode.
• Full Bandwidth—This mode has a peaking frequency of 6.25 GHz offering AC gain at 17 dB.
• Medium Bandwidth—This mode has a peaking frequency of 3.125 GHz offering AC gain at 21 dB.
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Figure 227. CTLE DC and AC Gain Conceptualization
Gain
(dB)
DC Gain
Control
Frequency
AC Gain
Control
Gain
(dB)
Frequency
Note: Final equalization curves will be available in the Arria 10 device datasheet.
High Data Rate Mode
High Data Rate Mode is a low power mode that supports data rates up to 25.8 Gbps. It is the default mode if none of the modes are selected in the Quartus Assignment
Editor or Quartus Settings File (.qsf). This mode provides an alternative path for high gain mode. High Data Rate Mode can be used to compensate for the loss similar to
CEI 28G VSR. High data rate mode supports four bandwidth modes: Full, threefourths, one-half, and one-fourth bandwidth modes. Full bandwidth mode can provide
AC peaking at approximately 8 dB at a peaking frequency of 14 GHz. High data rate mode can be operated in three-fourths, one-half, and one-fourth bandwidth with 9
GHz, 5 GHz, and 2.5 GHz peaking frequencies. In high data rate mode, AC gain values
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and DC gain values cannot be controlled individually as done in high gain mode. The recommended AC gain values in high data rate mode include the appropriate setting of DC gain to get the required peaking at respective peaking frequencies.
CTLE can only be supported in manual mode with the exception of PCIe Gen3, which supports triggered mode. CTLE mode and CTLE gain can be set through Quartus
Assignment Editor or Quartus Settings File and Avalon MM registers.
Related Information
•
CTLE Settings in Triggered Adaptation Mode on page 531
•
PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate on page 274
•
on page 456
• Arria 10 Device Datasheet
• Arria 10 Register Map
5.1.2.1.5. Variable Gain Amplifier (VGA)
Arria 10 channels have a variable gain amplifier to optimize the signal amplitude prior to the CDR sampling. VGA can only be operated in manual mode. VGA gain can be selected through Quartus Assignment Editor or Quartus Setting File (qsf) or the
Avalon MM register. You must set VGA manually for all combinations of CTLE and DFE modes.
Figure 228. VGA Frequency Response for Different Gain Settings
6
Magnitude
(dB)
-4
Frequency (Hz)
Related Information
on page 456
5.1.2.1.6. Decision Feedback Equalization (DFE)
DFE amplifies the high frequency components of a signal without amplifying the noise content. It compensates for inter-symbol interference (ISI). DFE minimizes postcursor ISI by adding or subtracting weighted versions of the previously received bits from the current bit. DFE works in synchronization with the TX pre-emphasis and downstream RX CTLE. This enables the RX CDR to receive the correct data that was transmitted through a lossy and noisy backplane.
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The DFE advantage over CTLE is improved Signal to Noise Ratio (SNR). DFE amplifies the power of the high frequency components without amplifying the noise power.
Figure 229. Signal ISI
ISI+
ISI-
Precursor Cursor Postcursor
Notes:
• An ideal pulse response is a single data point at the cursor.
• Real world pulse response is non-zero before the cursor (precursor) and after the
cursor (postcursor).
• ISI occurs when the data sampled at precursor or postcursor is not zero.
The DFE circuit stores delayed versions of the data. The stored bit is multiplied by a coefficient and then summed with the incoming signal. The polarity of each coefficient is programmable.
The DFE architecture supports eleven fixed taps.
The eleven fixed taps translate to the DFE capable of removing the ISI from the next
11 bits, beginning from the current bit.
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Figure 230. Channel Pulse Response
V Signal at the
Channel Input
Transmission Medium
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Region of Influence for Fixed Taps
Signal at the
Channel Output t
1UI
Note: The pulse at the output of the channel shows a long decaying tail. Frequencydependent losses and quality degradation affects other signals.
Supported modes for DFE:
• Disabled Mode:
— DFE disabled mode is similar to DFE manual mode, except all DFE tap values in this mode are set to zero. DFE tap values can be set in Assignment
Editor/.qsf or using Avalon MM interface.
• Manual Mode:
— In this mode, manual DFE tap values can be set in Assignment Editor/.qsf or using Avalon MM interface.
• Adaptation Enabled Mode:
— In this adaptation mode, DFE tap values are controlled by the Adaptive
Parametric Tuning Engine. This mode uses the converged DFE tap values given by the Adaptive Parametric Tuning Engine.
Related Information
on page 456
5.1.2.1.7. How to Enable CTLE and DFE
Table 252.
Summary of Receiver Equalization Modes
Receiver Equalization
CTLE adaptation mode
DFE adaptation mode
Number of fixed DFE taps
Modes
Manual, Triggered (use the triggered mode for PCIe Gen3 only)
Adaptation enabled, Manual, Disabled
3, 7, 11
Follow these steps to trigger DFE adaptation:
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1. Request user access to the internal configuration bus by writing 0x0 to offset address 0x0[7:0].
2. Monitor and wait for avmm_waitrequest
to be deasserted (logic low) if "Separate reconfig_waitrequest
from PreCISE" option is disabled. Otherwise, monitor and wait for register bit 0x281 bit[2] to go low if "Separate reconfig_waitrequest
from PreCISE" and "Enable control and status registers" option is enabled.
3. Select adaptation control by Read-Modify-Write 0x1 to bit[4] of address 0x149.
4. Enable adaptation trigger by Read-Modify-Write 0x1 to bit[6] of address 0x100.
5. Release the internal configuration bus to PreSICE by writing 0x1 to offset address
0x0[7:0].
6. Repeat step 2.
7. Monitor DFE adaptation completion by checking register bit 0x100 bit[6] to go low.
This confirms DFE trigger adaptation routine is complete.
Related Information
Analog Parameter Settings on page 585
Configuration Methods
Configure the modes using one of the following methods:
Method 1 - Using Arria 10 Transceiver Native PHY IP Core
1. Select the CTLE/DFE mode in the RX PMA tab of the PHY IP Core
2. Compile the design
3. Choose one the following:
• If CTLE or DFE is in Manual mode, set the CTLE gain value or DFE taps using one of the following ways: a. Assignment Editor/.qsf- Recompile the design to make these values effective.
Refer to Analog Parameter Settings for more details about Receiver
Equalization Settings.
b. Avalon-MM (AVMM) Interface - Value written through AVMM interface take precedence over values defined in Assignment Editor. Use this method to dynamically set values and hence avoid re-compilation.
Refer to Arria 10 Transceiver Register Map for more details on AVMM interface and to perform dynamic read/write.
Method 2 - Using AVMM Interface
1. Any changes you make using AVMM interface take precedence over what was configured in Native PHY IP GUI and/or Assignment Editor.
a. For CTLE and DFE in Manual mode, set the CTLE gain value or DFE Taps using the reconfiguration interface. The values are written dynamically and do not require design re-compilation.
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Refer to Arria 10 Register Map for details on the specific registers that set the
CTLE gain values/DFE taps.
b. For dynamically changing DFE and CTLE Adaptation modes, refer to CTLE
Settings in Triggered Adaptation Mode, Arria 10 Register Map and Arria 10
DFE Adaptation Tool for the list of adaptation registers. Use the reconfiguration interface to change the register settings.
Note: You must set VGA manually for all combinations of CTLE mode and DFE modes.
Related Information
• CTLE Settings in Triggered Adaptation Mode
• Arria 10 Register Map
Arria 10 DFE Adaptation Tool is a separate tab in the Arria 10 Register Map.
5.1.2.2. Clock Data Recovery (CDR) Unit
The PMA of each channel includes a channel PLL that you can configure as a receiver clock data recovery (CDR) for the receiver. You can also configure the channel PLL of channels 1 and 4 as a clock multiplier unit (CMU) PLL for the transmitter in the same bank.
Figure 231. Channel PLL Configured as CDR
Channel PLL
LTR/LTD
Controller rx_is_lockedtodata
Recovered Clock
/2 rx_serial_data
Phase
Detector
(PD)
Down
Up refclk
N
Divider
(1)
Phase
Frequency
Detector
(PFD)
Up
Down
Charge Pump
&
Loop Filter
Voltage
Controlled
Oscillator
(VCO)
Lock
Detect
L
Divider
(1)
Serial Clock rx_is_lockedtoref
M
Divider
(1)
Note:
1. The Quartus® Prime Pro Edition software automatically chooses the optimal values.
5.1.2.2.1. Lock-to-Reference Mode
In LTR mode, the phase frequency detector (PFD) in the CDR tracks the receiver input reference clock. The PFD controls the charge pump that tunes the VCO in the CDR.
The rx_is_lockedtoref
status signal is asserted active high to indicate that the
CDR has locked to the phase and frequency of the receiver input reference clock.
Note: The phase detector (PD) is inactive in LTR mode.
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5.1.2.2.2. Lock-to-Data Mode
During normal operation, the CDR must be in LTD mode to recover the clock from the incoming serial data. In LTD mode, the PD in the CDR tracks the incoming serial data at the receiver input. Depending on the phase difference between the incoming data and the CDR output clock, the PD controls the CDR charge pump that tunes the VCO.
Note: The PFD is inactive in LTD mode. The rx_is_lockedtoref randomly and is not significant in LTD mode.
status signal toggles
After switching to LTD mode, the rx_is_lockedtodata
status signal is asserted.
The actual lock time depends on the transition density of the incoming data and the parts per million (ppm) difference between the receiver input reference clock and the upstream transmitter reference clock. The rx_is_lockedtodata
signal toggles until the CDR sees valid data; therefore, you should hold receiver PCS logic in reset
( rx_digitalreset
) for a minimum of 4 µs after rx_is_lockedtodata
remains continuously asserted.
5.1.2.2.3. CDR Lock Modes
You can configure the CDR in either automatic lock mode or manual lock mode. By default, the Quartus Prime software configures the CDR in automatic lock mode.
Automatic Lock Mode
In automatic lock mode, the CDR initially locks to the input reference clock (LTR mode). After the CDR locks to the input reference clock, the CDR locks to the incoming serial data (LTD mode) when the following conditions are met:
• The signal threshold detection circuitry indicates the presence of valid signal levels at the receiver input buffer when rx_std_signaldetect
is enabled.
• The CDR output clock is within the configured ppm frequency threshold setting with respect to the input reference clock (frequency locked).
• The CDR output clock and the input reference clock are phase matched within approximately 0.08 unit interval (UI) (phase locked).
If the CDR does not stay locked to data because of frequency drift or severe amplitude attenuation, the CDR switches back to LTR mode.
Manual Lock Mode
The PPM detector and phase relationship detector reaction times can be too long for some applications that require faster CDR lock time. You can manually control the CDR to reduce its lock time using two optional input ports ( rx_set_locktoref
and rx_set_locktodata
).
Table 253.
Relationship Between Optional Input Ports and the CDR Lock Mode rx_set_locktoref
0
1
X rx_set_locktodata
0
0
1
CDR Lock Mode
Automatic
Manual-RX CDR LTR
Manual-RX CDR LTD
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5.1.2.3. Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes the data using the low-speed parallel recovered clock. The deserializer forwards the deserialized data to the receiver
PCS or FPGA fabric, and sends out the LSB of the input data first.
The deserializer supports the following deserialization factors: 8, 10, 16, 20, 32, 40, and 64.
Figure 232. Deserializer Block Diagram
Dn
Serial
Data
Dn D2 D1
LSB
D0 Deserializer
Serial
Clock
Parallel
Clock
D2
D1
D0
Parallel
Data
5.1.3. Loopback
The PMA supports serial, diagnostic, and reverse loopback paths.
Figure 233. Serial Loopback Path
The serial loopback path sets the CDR to recover the data from the serializer while data from receiver serial input pin is ignored by the CDR. The transmitter buffer sends data normally. Adjusting the TX VOD, TX preemphasis, and RX CTLE settings does not have an effect on the serial data that goes through the serial loopback path. Adjusting the RX VGA and RX DFE settings has an effect on the serial data that goes through the serial loopback path.
Transmitter PMA
Transmitter Serial
Differential Output
Data
Transmitter
Buffer
Serial
Data
Serializer
Parallel
Data Transmitter
PCS
Parallel Data
from FPGA Core
Receiver Serial
Differential Input
Data
Serial
Loopback
Receiver Buffer
CTLE
Serial
Clock
Parallel
Clock Clock
Generation
Block
VGA DFE
Serial
Data
Transmitter
PLL
Input
Reference
Clock
CDR
Serial
Data
Serial Clock
Parallel Clock
Deserializer
Parallel
Data Receiver
PCS
Parallel Data
to FPGA Core
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Figure 234. Reverse Serial Loopback Path/Pre CDR
The reverse serial loopback path sets the transmitter buffer to transmit data fed directly from the VGA output.
Adjusting the RX CTLE, and RX VGA settings has an effect on the serial data that goes through the diagnostic loopback path.
Transmitter PMA
Transmitter Serial
Differential Output
Data
Transmitter
Buffer
Serial
Data
Serializer
Parallel
Data Transmitter
PCS
Parallel Data from FPGA Core
Diagnostic
Loopback
Serial
Clock
Parallel
Clock Clock
Generation
Block
Transmitter
PLL
Input
Reference
Clock
Receiver Serial
Differential Input
Data
Receiver Buffer
CTLE
VGA DFE
Serial
Data
CDR
Serial
Data
Serial Clock
Parallel Clock
Deserializer
Parallel
Data
Receiver
PCS
Parallel Data to FPGA Core
Figure 235. Reverse Serial Loopback Path/Post CDR
The reverse serial loopback path sets the transmitter buffer to transmit data fed directly from the CDR recovered data. Adjusting the RX CTLE, RX VGA, and RX DFE settings has an effect on the serial data that goes through the reverse loopback path. Adjusting TX VOD and TX pre-emphasis has an effect on the transmitter serial differential output data.
Transmitter PMA
Transmitter Serial
Differential Output
Data
Transmitter
Buffer
Serial
Data
Serializer
Parallel
Data Transmitter
PCS
Parallel Data from FPGA core
Reverse
Loopback
Serial
Clock
Parallel
Clock Clock
Generation
Block
Transmitter
PLL
Input
Reference
Clock
Receiver Serial
Differential Input
Data
Receiver PMA
Receiver
Buffer Serial
Data
CDR
Serial
Data
Serial Clock
Parallel Clock
Deserializer
Parallel
Data Receiver
PCS
Parallel Data to FPGA core
5.2. Arria 10 Enhanced PCS Architecture
You can use the Enhanced PCS to implement multiple protocols that operate at around
10 Gbps or higher line rates.
The Enhanced PCS provides the following functions:
• Performs functions common to most serial data industry standards, such as word alignment, block synchronization, encoding/decoding, and framing, before data is sent or received off-chip through the PMA
• Handles data transfer to and from the FPGA fabric
• Internally handles data transfer to and from the PMA
• Provides frequency compensation
• Performs channel bonding for multi-channel low skew applications
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Figure 236. Enhanced PCS Datapath Diagram
Transmitter PMA Transmitter Enhanced PCS
TX
Data &
Control
FPGA
Fabric
Parallel Clock
PRBS
Generator
PRP
Generator tx_clkout
KR FEC TX G KR FEC Scr
KR FEC Enc
Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout rx_pma_div_clkout
RX
Data &
Control
PRBS
Verifier
Parallel Clock
PRP
Verifier
10GBASE-R
BER Checker rx_clkout
KR FEC Block S KR FEC Dec
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
ATX PLL fPLL
CMU PLL
Serial Clock
Input Reference Clock
Related Information
Implementing Protocols in Arria 10 Transceivers
on page 32
5.2.1. Transmitter Datapath
5.2.1.1. Enhanced PCS TX FIFO
The Enhanced PCS TX FIFO provides an interface between the transmitter channel PCS and the FPGA fabric. The TX FIFO can operate for phase compensation between the channel PCS and FPGA fabric. You can also use the TX FIFO as an elastic buffer to control the input data flow, using tx_enh_data_valid
. The TX FIFO also allows channel bonding. The TX FIFO has a width of 73 bits and a depth of 16 words.
You can set the TX FIFO partially full and empty thresholds through the Transceiver and PLL Address Map. Refer to the Reconfiguration Interface and Dynamic
Reconfiguration chapter for more details.
The TX FIFO supports the following operating modes:
• Phase Compensation mode
• Register mode
• Interlaken mode
• Basic mode
Related Information
Reconfiguration Interface and Dynamic Reconfiguration
on page 502
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5.2.1.1.1. Phase Compensation Mode
In Phase Compensation mode, the TX Core FIFO decouples phase variations between tx_coreclkin
and
PCS_clkout_x2(tx)
. In this mode, read and write of the TX
Core FIFO can be driven by clocks from asynchronous clock sources but must be same frequency. You can use tx_coreclkin
(FPGA fabric clock) or tx_clkout1
(TX parallel clock) to clock the write side of the TX Core FIFO.
Note: Phase Compensation mode, TX parallel data is valid for every low speed clock cycle, and tx_enh_data_valid
signal should be tied with 1'b1.
Note: Phase Compensation can also be used in double rate transfer mode, where the FPGA fabric data width is doubled to allow the FPGA fabric clock to run at half rate. The double rate transfer mode is set in the Native PHY IP Parameter Editor. Refer to the
"Transmitter Data Path Interface Clocking" and "Receiver Data Path Interface Clocking" sections in the PLLs and Clock Networks chapter for details about the clock frequencies, when using FIFO single and double rate transfer mode.
Related Information
•
Transmitter Data Path Interface Clocking on page 386
•
Receiver Data Path Interface Clocking
on page 387
5.2.1.1.2. Register Mode
The Register Mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements. This is accomplished by tying the read clock of the FIFO with its write clock.
In Register mode, tx_parallel_data
(data), tx_control
(indicates whether tx_parallel_data
is a data or control word), and tx_enh_data_valid
(data valid) are registered at the FIFO output.
Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with a minimum of 32 words under the following conditions:
• When the Enhanced PCS TX FIFO is set to register mode.
• When using the recovered clock to drive the core logic.
• When there is no soft FIFO being generated along with the IP Catalog.
5.2.1.1.3. Interlaken Mode
In Interlaken mode, the TX Core FIFO operates as an elastic buffer. In this mode, you have additional signals to control the data flow into the FIFO. Therefore, the FIFO write clock frequency does not have to be the same as the read clock frequency. You control the writing to the TX Core FIFO with tx_fifo_wr_en
by monitoring the FIFO flags. The goal is to prevent the FIFO from becoming full or empty. On the read side, read enable is controlled by the Interlaken frame generator.
5.2.1.1.4. Basic Mode
In Basic mode, the TX Core FIFO operates as an elastic buffer, where buffer depths can vary. This mode allows driving write and read side of TX Core FIFO with different clock frequencies. Monitor the FIFO flag to control write and read operations. For TX
Core FIFO, assert tx_fifo_wr_en
with tx_fifo_pempty
signal going low.
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5.2.1.2. Interlaken Frame Generator
The Interlaken frame generator block takes the data from the TX FIFO and encapsulates the payload and burst/idle control words from the FPGA fabric with the framing layer’s control words (synchronization word, scrambler state word, skip word, and diagnostic word) to form a metaframe. The Native PHY IP Parameter Editor allows you to set the metaframe length from five 8-byte words to a maximum value of 8192
(64Kbyte words).
Use the same value on frame generator metaframe length for the transmitter and receiver.
Figure 237. Interlaken Frame Generator
The Interlaken frame generator implements the Interlaken protocol.
From TX FIFO
64-Bit Data
1-Bit Control
Interlaken
Frame
Generator
66-Bit Blocks
To Interlaken
CRC-32 Generator
Synchronization
Payload
Scrambler
State Word
Skip Word 66 65 64 63 0 66 0 66
Data
Sync Header
Inversion Bit (Place Holder for Bit Inversion Information)
Used for Clock Compensation in a Repeater
Used to Synchronize the Scrambler
Used to Align the Lanes of the Bundle
0 Di
Provides Per
Lane Error Check and Optional Status
Message
5.2.1.3. Interlaken CRC-32 Generator
The Interlaken CRC-32 generator block receives data from the Interlaken frame generator and calculates the cyclic redundancy check (CRC) code for each block of data. This CRC code value is stored in the CRC32 field of the diagnostic word. CRC-32 provides a diagnostic tool for each lane. This helps to trace the errors on the interface back to an individual lane.
The CRC-32 calculation covers most of the metaframe, including the diagnostic word, except the following:
• Bits [66:64] of each word
• 58-bit scrambler state within the scrambler state word
• 32-bit CRC-32 field within the diagnostic word
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Figure 238. Interlaken CRC-32 Generator
The Interlaken CRC-32 generator implements the Interlaken protocol.
From the Interlaken Frame Generator
Interlaken
CRC-32
Generator
Metaframes with Embedded
CRC-32 Code to Scrambler
Di
Metaframe
Sy SB SK Payload
67 0 67 0 67
Total Data for CRC-32 Calculation
Di
66 0
Sy SB SK Sy SB SK Payload
Total Data for CRC-32 Calculation
66 31 0
Sy SB SK
Calculated CRC-32 Value
Inserted in the 32 Bits of Diagnostic Word
5.2.1.4. 64B/66B Encoder and Transmitter State Machine (TX SM)
The 64B/66B encoder is used to achieve DC-balance and sufficient data transitions for clock recovery. It encodes 64-bit XGMII data and 8-bit XGMII control into 10GBASE-R
66-bit control or data blocks in accordance with Clause 49 of the IEEE802.3-2008 specification.
The 66-bit encoded data contains two overhead sync header bits that the receiver PCS uses for block synchronization and bit-error rate (BER) monitoring. The sync header is
01 for data blocks and 10 for control blocks. Sync headers are not scrambled and are used for block synchronization. (The sync headers 00 and 11 are not used, and generate an error if seen.) The remainder of the block contains the payload. The payload is scrambled and the sync header bypasses the scrambler.
The encoder block also has a state machine (TX SM) designed in accordance with the
IEEE802.3-2008 specification. The TX SM ensures valid packet construction on data sent from the MAC layer. It also performs functions such as transmitting local faults under reset, as well as transmitting error codes when the 10GBASE-R PCS rules are violated.
Note: The 64B/66B encoder is available to implement the 10GBASE-R protocol.
Figure 239. Example Data Pattern for 64B/66B Encoding
XGMII data
TXC<0:3> TXD<0:31> XGMII f07070707 f07070707 8 fb D
1
D
2
D
3
0 D
4
D
5
D
6
D
7
0 D
0
D
1
D
2
D
3
0 D
4
D
5
D
6
D
7
1 D
0
D
1
D
2 fd f07070707
PCS
Data
0
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
63
S
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
T
3
C
0
C
1
C
2
C
3
66-bit encoded data
0
10 1e 000000 00000000
65
10 78 D
1
D
2
D
3
D
4
D
5
D
6
D
7
01 D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
10 b4 D
0
D
1
D
2
00000000
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64B/66B Encoder Reset Condition
The tx_digitalreset
signal resets the 64B/66B encoder. During the reset condition, the 64B/66B encoder does not output any signal in contrast with the
8B/10B encoder.
5.2.1.5. Pattern Generators
The Arria 10 transceivers contain hardened generators and checkers to provide a simple and easy way to verify and characterize high speed links. Hardening the pattern generators and checkers save FPGA core logic resources. The following pattern generator blocks are supported in Arria 10:
• Pseudo Random Binary Sequence (PRBS)
• Pseudo Random Pattern (PRP)
Note: The pattern generators and checkers are supported for non-bonded channels only.
The pattern generators or checkers are enabled by writing to the respective register bits of the Transceiver. Refer to the Reconfiguration Interface and Dynamic
Reconfiguration chapter for configuration details.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 502
5.2.1.5.1. PRBS Pattern Generator (Shared between Enhanced PCS and Standard PCS)
You can use Arria 10 pseudo-random bit sequence PRBS generator to simulate traffic without developing or fully implementing any upper layer of a protocol stack. The
PRBS generator in Arria 10 devices is a shared hardened block between the Standard and Enhanced datapaths through the PCS instead of being two unique instances: one for Standard PCS and one for the Enhanced PCS. There is only one set of control signals and registers for using this feature. The data lines from the various PCSes and shared PRBS, are muxed before they are sent to the PMA. When the PRBS generator is enabled, the data on the PRBS data lines is selected to be sent to the PMA. At any instant, either the data from the PCS or the data generated from the PRBS generator, is sent to the PMA.
The PRBS generator can be configured for two widths of the PCS-PMA interface: 10 bits and 64 bits. PRBS9 is available in 10-bit and 64-bit PCS-PMA widths. All other
PRBS patterns are available in 64-bit PCS-PMA width only. The PRBS generator patterns can only be used when PCS-PMA interface width is configured to 10 bits or 64 bits.
Table 254.
Supported PRBS Patterns
PRBS Pattern
PRBS7: x 7 + x 6 + 1
PRBS9: x 9 + x 5 + 1
PRBS15: x 15 + x 14 + 1
PRBS23: x 23 + x 18 + 1
PRBS31: x 31 + x 28 + 1
Yes
10 bit PCS-PMA width
Yes
Yes
Yes
Yes
Yes
64 bit PCS-PMA width
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PRBS test patterns may be considered equivalent to "noise". Use these patterns to test the transceiver link with a noisy signal by placing the transceiver in loopback mode.
Use PRBS7 and PRBS9 to test transceiver links with linear impairments, and with 8B/
10B.
Use PRBS15 for jitter evaluation.
Use PRBS23 or PRBS31 for jitter evaluation (data-dependent jitter) of non-8B/10B links, such as SDH/SONET/OTN jitter testers. Most 40G, 100G, and 10G applications use PRBS31 for link evaluation.
Figure 240. PRBS Generator for Serial Implementation of PRBS9 Pattern
S0 S1 S4 S5 S8
PRBS Output
Note: All supported PRBS generators are similar to the PRBS9 generator.
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for configuration details.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 502
5.2.1.5.2. Pseudo-Random Pattern Generator
The pseudo-random pattern (PRP) generator is specifically designed for the 10GBASE-
R and 1588 protocols. The PRP generator block operates in conjunction with the scrambler to generate pseudo-random patterns for the TX and RX tests in the 10G
Ethernet mode. You can use the Arria 10 Pseudo Random Pattern (PRP) generator in the scrambler to generate random data pattern and seed that the scrambler can use.
The PRP mode is a test mode of the scrambler. Two seeds are available to seed the scrambler: all 0s or two local fault-ordered sets. The seed is used in the scrambler to produce the pattern. PRP is only available when the scrambler is enabled.
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for configuration details.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 502
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5.2.1.6. Scrambler
The scrambler randomizes data to create transitions to DC-balance the signal and help
CDR circuits. The scrambler uses a x 58 + x 39 +1 polynomial and supports both synchronous scrambling used for Interlaken and asynchronous (also called selfsynchronized) scrambling used for the 10GBASE-R protocol.
The asynchronous (self-synchronizing) mode does not require an initialization seed.
Except for the two sync header bits in each 66-bit data block, the entire 64-bit payload is scrambled by feeding it into a linear feedback shift register (LFSR) continuously to generate scrambled data while the sync-header bits bypass the scrambler. The initial seed is set to all 1s. You can change the seed for the 10GBASE-R protocol using the Native PHY IP Parameter Editor.
Figure 241. Asynchronous Scrambler in Serial Implementation
IN
S0 S1 S2 S38 S39 S56 S57
OUT
In synchronous mode, the scrambler is initially reset to different programmable seeds on each lane. The scrambler then runs by itself. Its current state is XOR’d with the data to generate scrambled data. A data checker in the scrambler monitors the data to determine if it should be scrambled or not. If a synchronization word is found, it is transmitted without scrambling. If a Scrambler State Word is detected, the current scramble state is written into the 58-bit scramble state field in the Scrambler State
Word and sent over the link. The receiver uses this scramble state to synchronize the descrambler. The seed is automatically set for Interlaken protocol.
Figure 242. Synchronous Scrambler Showing Different Programmable Seeds
S0 S37
LFSR Seed
S38 S57 OUT
0 37 38 57
IN
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5.2.1.7. Interlaken Disparity Generator
The Interlaken disparity generator block is in accordance with the Interlaken protocol specification and provides a DC-balanced data output.
The Interlaken protocol solves the unbounded baseline wander, or DC imbalance, of the 64B/66B coding scheme used in 10Gb Ethernet by inverting the transmitted data.
The disparity generator monitors the transmitted data and makes sure that the running disparity always stays within a ±96-bit bound. It adds the 67th bit (bit 66) to signal the receiver whether the data is inverted or not.
Table 255.
Inversion Bit Definition
Bit 66
0
1
Interpretation
Bits [63:0] are not inverted; the receiver processes this word without modification
Bits [63:0] are inverted; the receiver inverts the bits before processing this word
Note: The Interlaken disparity generator is available to implement the Interlaken protocol.
5.2.1.8. TX Gearbox, TX Bitslip and Polarity Inversion
The TX gearbox adapts the PCS data width to the smaller bus width of the PCS-PMA interface (Gearbox Reduction). It supports different ratios (FPGA fabric-PCS Interface
Width: PCS-PMA Interface Width) such as 66:32, 66:40, 64:32, 40:40, 32:32, 64:64,
67:64, and 66:64. The gearbox mux selects a group of consecutive bits from the input data bus depending on the gearbox ratio and the data valid control signals.
The TX gearbox also has a bit slipping feature to adjust the data skew between channels. The TX parallel data is slipped on the rising edge of tx_enh_bitslip before it is passed to the PMA. The maximum number of the supported bitslips is PCS data width-1 and the slip direction is from MSB to LSB and from current to previous word.
Figure 243. TX Bitslip tx_enh_bitslip
= 2 and PCS width of gearbox is 67
You can use transmitter data polarity inversion to invert the polarity of every bit of the input data word to the serializer in the transmitter path. The inversion has the same effect as swapping the positive and negative signals of the differential TX buffer. This is useful if these signals are reversed on the board or backplane layout. Enable polarity inversion through the Native PHY IP Parameter Editor.
5.2.1.9. KR FEC Blocks
The KR FEC blocks in the Enhanced PCS are designed in accordance with the 10G-
KRFEC and 40G-KRFEC of the IEEE 802.3 specification. The KR FEC implements the
Forward Error Correction (FEC) sublayer, a sublayer between the PCS and PMA sublayers.
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Most data transmission systems, such as Ethernet, have minimum requirements for the bit error rate (BER). However, due to channel distortion or noise in the channel, the required BER may not be achievable. In these cases, adding a forward error control correction can improve the BER performance of the system.
The FEC sublayer is optional and can be bypassed. When used, it can provide additional margin to allow for variations in manufacturing and environmental conditions. FEC can achieve the following objectives:
• Support a forward error correction mechanism for the 10GBASE-R/KR and
40GBASE-R/KR protocols.
• Support the full duplex mode of operation of the Ethernet MAC.
• Support the PCS, PMA, and Physical Medium Dependent (PMD) sublayers defined for the 10GBASE-R/KR and 40GBASE-R/KR protocols.
• Support up to the maximum transceiver data rate on any protocol that is 64/66bit encoded.
With KR FEC, the BER performance of the system can be improved.
Transcode Encoder
The KR forward error correction (KR FEC) transcode encoder block performs the
64B/66B to 65-bit transcoder function by generating the transcode bit. The transcode bit is generated from a combination of 66 bits after the 64B/66B encoder which consists of a 2-bit synchronization header (S0 and S1) and a 64-bit payload (D0, D1,
…, D63). To ensure a DC-balanced pattern, the transcode word is generated by performing an XOR function on the second synchronization bit S1 and payload bit D8.
The transcode bit becomes the LSB of the 65-bit pattern output of the transcode encoder.
Figure 244. Transcode Encoder
66-Bit Input
D63 ...
D9 D8 ...
D0 S1 S0
65-Bit Output
D63 ...
D9 D8 ...
D0 S1^D8
KR FEC Encoder
FEC (2112,2080) is an FEC code specified in Clause 74 of the IEEE 802.3 specification.
The code is a shortened cyclic code (2112, 2080). For each block of 2080 message bits, another 32 parity checks are generated by the encoder to form a total of 2112 bits. The generator polynomial is: g(x) = x 32 + x 23 + x 21 + x 11 + x 2 +1
KR FEC Scrambler
The KR FEC scrambler block performs scrambling based on the generation polynomial x 58 + x 39 +1, which is necessary for establishing FEC block synchronization in the receiver and to ensure DC balance.
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KR FEC TX Gearbox
The KR FEC TX gearbox converts 65-bit input words to 64-bit output words to interface the KR FEC encoder with the PMA. This gearbox is different from the TX gearbox used in the Enhanced PCS. The KR FEC TX gearbox aligns with the FEC block.
Because the encoder output (also the scrambler output) has its unique word size pattern, the gearbox is specially designed to handle that pattern.
5.2.2. Receiver Datapath
5.2.2.1. RX Gearbox, RX Bitslip, and Polarity Inversion
The RX gearbox adapts the PMA data width to the larger bus width of the PCS channel
(Gearbox Expansion). It supports different ratios (PCS-PMA interface width : FPGA fabric–PCS interface width) such as 32:66, 40:66, 32:67, 32:64, 40:40, 32:32, 64:64,
67:64, and 66:64 and a bit slipping feature.
RX bitslip is engaged when the RX block synchronizer or rx_bitslip
is enabled to shift the word boundary. On the rising edge of the bitslip signal of the RX block synchronizer or rx_bitslip
from the FPGA fabric, the word boundary is shifted by one serial bit or 1UI. Each bit slip removes the earliest received bit from the received data.
Figure 245. RX Bitslip rx_bitslip
is toggled two times, which shifts the rx_parallel_data
boundary two bits.
rx_clkout tx_ready rx_ready tx_parallel_data (hex) 00000001 rx_bitslip rx_parallel_data (hex) 00000000 00100000 00200000 00400000
Note:
The first rising edge of rx_bitslip makes 1 serial bit
The second rising edge of rx_bitslip makes another serial bit slip.
The receiver gearbox can invert the polarity of the incoming data. This is useful if the receiver signals are reversed on the board or backplane layout. Enable polarity inversion through the Native PHY IP Parameter Editor.
Data valid generation logic is essential for gearbox operation. Each block of data is accompanied by rx_enh_data_valid
data valid signal which “qualifies” the block as valid or not. The data valid toggling pattern is dependent on the data width conversion ratio. For example, if the ratio is 66:40, the data valid signal is high in 20 out of 33 cycles or approximately 2 out of 3 cycles and the pattern repeats every 33 rx_clkout
RX low-speed parallel clock cycles.
If a design is slipping more bits than the PCS/PMA width, the Enhanced RX PCS FIFO could overflow. To clear the overflow, assert rx_digitalreset
.
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5.2.2.2. Block Synchronizer
The block synchronizer determines the block boundary of a 66-bit word in the case of the 10GBASE-R protocol or a 67-bit word in the case of the Interlaken protocol. The incoming data stream is slipped one bit at a time until a valid synchronization header
(bits 65 and 66) is detected in the received data stream. After the predefined number of synchronization headers (as required by the protocol specification) is detected, the block synchronizer asserts rx_enh_blk_lock
(block lock status signal) to other receiver PCS blocks down the receiver datapath and to the FPGA fabric.
Note: The block synchronizer is designed in accordance with Interlaken Protocol specification
(as described in Figure 13 of Interlaken Protocol Definition v1.2) and 10GBASE-R protocol specification (as described in IEEE 802.3-2008 clause-49).
5.2.2.3. Interlaken Disparity Checker
The Interlaken disparity checker examines the received inversion bit inserted by the far end disparity generator, to determine whether to reverse the inversion process of the Interlaken disparity generation.
Note: The Interlaken disparity checker is available to implement the Interlaken protocol.
5.2.2.4. Descrambler
The descrambler block descrambles received data to regenerate unscrambled data using the x 58 + x 39 +1 polynomial. Like the scrambler, it operates in asynchronous mode or synchronous mode.
Related Information
on page 468
5.2.2.5. Interlaken Frame Synchronizer
The Interlaken frame synchronizer delineates the metaframe boundaries and searches for each of the framing layer control words: Synchronization, Scrambler State, Skip, and Diagnostic. When four consecutive synchronization words have been identified, the frame synchronizer achieves the frame locked state. Subsequent metaframes are then checked for valid synchronization and scrambler state words. If four consecutive invalid synchronization words or three consecutive mismatched scrambler state words are received, the frame synchronizer loses frame lock. In addition, the frame synchronizer provides
FPGA fabric.
rx_enh_frame_lock
(receiver metaframe lock status) to the
Note: The Interlaken frame synchronizer is available to implement the Interlaken protocol.
5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM)
The 64B/66B decoder reverses the 64B/66B encoding process. The decoder block also contains a state machine (RX SM) designed in accordance with the IEEE802.3-2008 specification. The RX SM checks for a valid packet structure in the data sent from the remote side. It also performs functions such as sending local faults to the Media
Access Control (MAC)/Reconciliation Sublayer (RS) under reset and substituting error codes when the 10GBASE-R and 10GBASE-KR PCS rules are violated.
Note: The 64B/66B decoder is available to implement the 10GBASE-R protocol.
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5.2.2.6.1. PRBS Checker
You can use Arria 10 pseudo-random bit stream (PRBS) checker to easily characterize high-speed links without developing or fully implementing any upper layer of a protocol stack. The PRBS checker in Arria 10 devices is a shared hardened block between the Standard and Enhanced datapaths. Hence, there is only one set of control signals and registers for this feature.
You can use the PRBS checker block to verify the pattern generated by the PRBS generator. The PRBS checker can be configured for two widths of the PCS-PMA interface: 10 bits and 64 bits. PRBS9 is available in both 10-bit and 64-bit PCS-PMA widths. All other PRBS patterns are available in 64-bit PCS-PMA width only. The PRBS checker patterns can only be used when the PCS-PMA interface width is configured to
10 bits or 64 bits.
The pseudo-random bit stream (PRBS) block verifies the pattern generated by the
PRBS generator. The verifier supports the 64-bit PCS-PMA interface. PRBS7 supports
64-bit width only. PRBS9 supports 10-bit PMA data width to allow testing at a lower data rate.
Table 256.
Supported PRBS Patterns
PRBS Pattern
PRBS7: x 7 + x 6 + 1
PRBS9: x 9 + x 5 + 1
PRBS15: x 15 + x 14 + 1
PRBS23: x 23 + x 18 + 1
PRBS31: x 31 + x 28 + 1
Yes
10 bit PCS-PMA width
Yes
Yes
Yes
Yes
Yes
64 bit PCS-PMA width
Figure 246. PRBS9 Verify Serial Implementation
PRBS datain
S0 S1 S4 S5 S8
PRBS Error
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The PRBS checker has the following control and status signals available to the FPGA fabric:
• rx_prbs_done
—Indicates the PRBS sequence has completed one full cycle. It stays high until you reset it with rx_prbs_err_clr
.
• rx_prbs_err
—Goes high if an error occurs. This signal is pulse-extended to allow you to capture it in the RX FPGA CLK domain.
• rx_prbs_err_clr
—Used to reset the rx_prbs_err
signal.
Enable the PRBS checker control and status ports through the Native PHY IP
Parameter Editor in the Quartus Prime software.
5.2.2.7. Pseudo Random Pattern Verifier
The Pseudo Random Pattern (PRP) verifier is available for 10GBASE-R and 10GBASE-R
1588 protocol modes. The PRP verifier block operates in conjunction with the descrambler. The PRP verifier monitors the output of the descrambler when block synchronization is achieved.
The rx_prbs_err
error signal is shared between the PRBS checker and the PRP verifier.
The PRP verifier:
• Searches for a test pattern (two local faults, or all 0s) or its inverse
• Tracks the number of mismatches with a 16-bit error counter
Figure 247. PRP Verifier
Error
Counter error_count
Descrambler
Test Pattern
Detect
Pseudo Random
Verifier
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for configuration details.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 502
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5.2.2.8. 10GBASE-R Bit-Error Rate (BER) Checker
The 10GBASE-R BER checker block is designed in accordance with the 10GBASE-R protocol specification as described in IEEE 802.3-2008 clause-49. After block lock synchronization is achieved, the BER checker starts to count the number of invalid synchronization headers within a 125-μs period. If more than 16 invalid synchronization headers are observed in a 125-μs period, the BER checker provides the status signal rx_enh_highber
to the FPGA fabric, indicating a high bit error rate condition.
When the optional control input rx_enh_highber_clr_cnt
is asserted, the internal counter for the number of times the BER state machine has entered the
"BER_BAD_SH" state is cleared.
When the optional control input rx_enh_clr_errblk_count
is asserted, the internal counter for the number of times the RX state machine has entered the "RX_E" state for the 10GBASE-R protocol is cleared. In modes where the FEC block in enabled, the assertion of this signal resets the status counters within the RX FEC block.
Note: The 10GBASE-R BER checker is available to implement the 10GBASE-R protocol.
5.2.2.9. Interlaken CRC-32 Checker
The Interlaken CRC-32 checker verifies that the data transmitted has not been corrupted between the transmit PCS and the receive PCS. The CRC-32 checker calculates the 32-bit CRC for the received data and compares it against the CRC value that is transmitted within the diagnostic word. is sent to the FPGA fabric.
rx_enh_crc32_err
(CRC error signal)
5.2.2.10. Enhanced PCS RX FIFO
The Enhanced PCS RX FIFO is designed to compensate for the phase, clock, or phase and clock difference between the receiver channel PCS and the FPGA fabric. It can operate as a phase-compensation, clock-compensation, elastic buffer, or a deskew
FIFO in Interlaken mode. The RX FIFO has a width of 74 bits and a depth of 32 words for all protocols.
The RX FIFO supports the following modes:
• Phase Compensation mode
• Register mode
• Interlaken mode (deskew FIFO)
• 10GBASE-R mode (clock compensation FIFO)
• Basic mode (elastic buffer FIFO)
5.2.2.10.1. Phase Compensation Mode
The RX FIFO compensates for the phase difference between the read clock and write clocks. rx_clkout
(RX parallel low-speed clock) clocks the write side of the RX FIFO.
rx_coreclkin
(FPGA fabric clock) or rx_clkout
clocks the read side of the RX
FIFO.
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When phase compensation is used in double-width mode, the FPGA data width is doubled to allow the FPGA fabric clock to run at half rate, similar to the TX FIFO phase compensation in double-width mode.
Depth of RX FIFO is constant in this mode, therefore RX FIFO flag status can be ignored. You can tie tx_enh_data_valid
with one.
5.2.2.10.2. Register Mode
The Register Mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements. This is accomplished by tying the read clock of the FIFO with its write clock.
In Register mode, rx_parallel_data
(data), rx_control
indicates whether rx_parallel_data
is a data or control word, and rx_enh_data_valid
(data valid) are registered at the FIFO output. The RX FIFO in register mode has one register stage or one parallel clock latency.
Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with minimum of
32 words under the following conditions:
• When the Enhanced PCS RX FIFO is set to register mode.
• When using the recovered clock to drive the core logics.
• When there is no soft FIFO being generated along with the IP Catalog.
5.2.2.10.3. Interlaken Mode
In Interlaken mode, the RX FIFO operates as an Interlaken deskew FIFO. To implement the deskew process, implement an FSM that controls the FIFO operation based on available FPGA input and output flags.
For example, after frame lock is achieved, data is written after the first alignment word (SYNC word) is found on that channel. As a result, rx_enh_fifo_pempty
(FIFO partially empty flag ) of that channel goes low. You must monitor the rx_enh_fifo_pempty
and rx_enh_fifo_pfull
flags of all channels. If rx_enh_fifo_pempty
flags from all channels deassert before any rx_enh_fifo_pfull
flag asserts, which implies alignment word has been found on all lanes of the link, you start reading from all the FIFOs by asserting rx_enh_fifo_rd_en
. Otherwise, if a rx_enh_fifo_pfull
flag from any channel goes high before a rx_enh_fifo_pempty
flag deassertion on all channels, you must reset the FIFO by toggling the process.
rx_enh_fifo_align_clr
signal and repeating the
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Figure 248. RX FIFO as Interlaken Deskew FIFO
FPGA Fabric Interface rx_enh_fifo_align_clr rx_enh_fifo_rd_en
User
Deskew
FSM rx_enh_fifo_pempty rx_enh_fifo_pfull
RX FIFO
5.2.2.10.4. 10GBASE-R Mode
In 10GBASE-R mode, the RX FIFO operates as a clock compensation FIFO. When the block synchronizer achieves block lock, data is sent through the FIFO. Idle ordered sets (OS) are deleted and Idles are inserted to compensate for the clock difference between the RX low speed parallel clock and the FPGA fabric clock (±100 ppm for a maximum packet length of 64,000 bytes).
Idle OS Deletion
Deletion of Idles occurs in groups of four OS (when there are two consecutive OS) until the rx_enh_fifo_pfull
flag deasserts. Every word—consisting of a lower word
(LW) and an upper word (UW)—is checked for whether it can be deleted by looking at both the current and previous words.
For example, the current LW can be deleted if it is Idle and the previous UW is not a
Terminate.
Table 257.
Conditions Under Which a Word Can be Deleted
In this table X=don’t care, T=Terminate, I=Idle, and OS=order set.
Deletable
Lower Word
Upper Word
Case
1
2
1
2
Word
UW
LW
UW
LW
UW
LW
UW
LW
Previous
!T
X
OS
X
X
X
X
X
Current
X
I
X
OS
I
!T
OS
OS
X
X
X
X
X
!T
X
OS
Output
!T
X
X
X
OS
X
X
X
If only one word is deleted, data shifting is necessary because the datapath is two words wide. After two words have been deleted, the FIFO stops writing for one cycle and a synchronous flag ( rx_control[8]
) appears on the next block of 8-byte data.
There is also an asynchronous status signal rx_enh_fifo_del
, which does not go through the FIFO.
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Figure 249. IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
Before Deletion rx_parallel_data[79:0] 00000000000004ADh 00000000000004AEh 0707070707FD0000h rx_parallel_data[79:0]
After Deletion
00000000000004ADh 00000000000004AEh 0707070707FD0000h
Idle Deleted
Figure 250. OS Word Deletion
This figure shows the deletion of Ordered set words in the receiver data stream.
Before Deletion rx_parallel_data[79:0] FD000000000004AEh DDDDDD9CDDDDDD9Ch 00000000000000FBh rx_parallel_data[79:0]
After Deletion
FD000000000004AEh 000000FBDDDDDD9Ch AAAAAAAA00000000h
OS Deleted
000000FB07070707h
AAAAAAAA000000FBh
AAAAAAAAAAAAAAAAh
00000000AAAAAAAAh
Idle Insertion
Idle insertion occurs in groups of 8 Idles when the rx_enh_fifo_pempty
flag is deasserted. Idles can be inserted following Idles or OS. Idles are inserted in groups of
8 bytes. Data shifting is not necessary. There is a synchronous status rx_enh_fifo_insert
signal that is attached to the 8-byte Idles being inserted.
Table 258.
Cases Where Two Idle Words are Inserted
In this table X=don’t care, S=start, OS=order set, I-DS=idle in data stream, and I-In=idle inserted. In cases 3 and 4, the Idles are inserted between the LW and UW.
Case
1
2
3
4
Word
UW
LW
UW
LW
UW
LW
UW
LW
Input
I-DS
X
OS
X
S
I-DS
S
OS
I-DS
X
OS
X
I-In
I-DS
I-In
OS
Output
I-In
I-In
I-In
I-In
S
I-In
S
I-In
Figure 251. IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
rx_parallel_data[79:0]
Before Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch 00000000000000FBh rx_parallel_data[79:0]
After Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch 0707070707070707h
AAAAAAAAAAAAAAAAh
00000000000000FBh
Idle Inserted
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5.2.2.10.5. Basic Mode
In Basic mode, the RX FIFO operates as an elastic buffer, where buffer depths can vary. This mode allows driving write and read side of RX FIFO with different clock frequencies. Monitor the FIFO flag to control write and read operations. For RX FIFO, assert rx_enh_read_en
signal with rx_fifo_pfull
signal going low.
5.2.2.11. RX KR FEC Blocks
KR FEC Block Synchronization
You can obtain FEC block delineation for the RX KR FEC by locking onto correctly received FEC blocks with the KR FEC block synchronization. You can also use the KR
FEC up to the maximum transceiver data rate on any protocol that is 64/66-bit encoded.
Note: The KR FEC block synchronization is available to implement the 10GBASE-KR protocol.
KR FEC Descrambler
The KR FEC descrambler block descrambles received data to regenerate unscrambled data using the x 58 + x 39 +1 polynomial. Before the block boundary in the KR FEC sync block is detected, the data at the input of the descrambler is sent directly to the KR
FEC decoder. When the boundary is detected, the aligned word from the KR FEC sync block is descrambled with the Pseudo Noise (PN) sequence and then sent to the KR
FEC decoder.
KR FEC Decoder
The KR FEC decoder block performs the FEC (2112, 2080) decoding function by analyzing the received 32 65-bit blocks for errors. It can correct burst errors of 11 bits or less per FEC block.
KR FEC RX Gearbox
The KR FEC RX gearbox block adapts the PMA data width to the larger bus width of the PCS channel. It supports a 64:65 ratio.
Transcode Decoder
The transcode decoder block performs the 65-bit to 64B/66B reconstruction function by regenerating the 64B/66B synchronization header.
5.3. Arria 10 Standard PCS Architecture
The standard PCS can operate at a data rate of up to 10.8 Gbps. Protocols such as PCI
Express, CPRI 4.2+, GigE, IEEE 1588 are supported in Hard PCS while the other protocols can be implemented using Basic/Custom (Standard PCS) transceiver configuration rules.
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Figure 252. Standard PCS Datapath Diagram
Transmitter PMA Transmitter Standard PCS FPGA
Fabric
Receiver PMA tx_clkout tx_pma_div_clkout
PRBS
Generator
/2, /4
Receiver Standard PCS tx_coreclkin tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider) rx_clkout tx_clkout
PRBS
Verifier
/2, /4 rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clock rx_coreclkin rx_clkout or tx_clkout
ATX PLL
CMU PLL fPLL
Parallel Clock
Serial Clock
Parallel and Serial Clock
5.3.1. Transmitter Datapath
Serial Clock
5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe Gen3 PCS)
The TX FIFO interfaces between the transmitter PCS and the FPGA fabric and ensures reliable transfer of data and status signals. It compensates for the phase difference between the FPGA fabric clock and tx_clkout
(the low-speed parallel clock). The TX
FIFO has a depth of 8 and operates in low latency mode, register mode, and fast register mode.
Figure 253. TX FIFO Block Diagram
Datapath to Byte Serializer,
8B/10B Encoder, or Serializer rd_clk
TX
FIFO wr_clk
Datapath from FPGA Fabric or PIPE Interface tx_coreclkin tx_clkout
You can control the write port using tx_clkout
or tx_coreclkin
. Use the tx_clkout
signal for a single channel and tx_coreclkin
when using multiple channels. The TX FIFO is shared with PCIe Gen3 and Enhanced PCS data paths.
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5.3.1.1.1. TX FIFO Low Latency Mode
The low latency mode incurs two to three cycles of latency (latency uncertainty) when connecting it with the FPGA fabric. The FIFO empty and the FIFO full threshold values are made closer so that the depth of the FIFO decreases, which in turn decreases the latency.
5.3.1.1.2. TX FIFO Register Mode
The register mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements. This is accomplished by tying the read clock of the FIFO with its write clock. The register mode incurs only one clock cycle of latency when interfacing to the FPGA fabric.
5.3.1.1.3. TX FIFO Fast Register Mode
This mode allows a higher maximum frequency (f
MAX
) between the FPGA fabric and the TX PCS by enabling the optional fast register interface with additional latency.
5.3.1.2. Byte Serializer
In certain applications, the FPGA fabric cannot operate at the same clock rate as the transmitter channel (PCS) because the transmitter channel is capable of operating at higher clock rates compared to the FPGA fabric. The byte serializer allows the transmitter channel to operate at higher data rates while keeping the FPGA fabric interface clock rate below its maximum limit. This is accomplished by increasing the channel width two or four times (FPGA fabric-to-PCS interface width) and dividing the clock (tx_clkout) rate by 2 or 4. The byte serializer can be disabled, or operate in
Serialize x2 or Serialize x4 modes.
Figure 254. Byte Serializer Block Diagram dataout
(to the 8B/10 Encoder or the TX Bit Slip)
Byte
Serializer datain (from the TX FIFO) tx_clkout
/2,
/4
Related Information
•
Resetting Transceiver Channels
on page 416
•
Implementing Protocols in Arria 10 Transceivers
on page 32
5.3.1.2.1. Bonded Byte Serializer
The bonded byte serializer is available in Arria 10 devices, and is used in applications such as PIPE, CPRI, and custom applications where multiple channels are grouped together. The bonded byte serializer is implemented by bonding all the control signals to prevent skew induction between channels during byte serialization. In this configuration, one of the channels acts as master and the remaining channels act as slaves.
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5.3.1.2.2. Byte Serializer Disabled Mode
In disabled mode, the byte serializer is bypassed. The data from the TX FIFO is directly transmitted to the 8B/10B encoder, TX Bitslip, or Serializer, depending on whether or not the 8B/10B encoder and TX Bitslip are enabled. Disabled mode is used in low speed applications such as GigE, where the FPGA fabric and the TX standard
PCS can operate at the same clock rate.
5.3.1.2.3. Byte Serializer Serialize x2 Mode
The serialize x2 mode is used in high-speed applications such as the PCIe Gen1 or
Gen2 protocol implementation, where the FPGA fabric cannot operate as fast as the TX
PCS.
In serialize x2 mode, the byte serializer serializes 16-bit, 20-bit (when 8B/10B encoder is not enabled), 32-bit, and 40-bit (when 8B/10B encoder is not enabled) input data into 8-bit, 10-bit, 16-bit, and 20-bit data, respectively. As the parallel data width from the TX FIFO is halved, the clock rate is doubled.
After byte serialization, the byte serializer forwards the least significant word first followed by the most significant word. For example, if the FPGA fabric-to-PCS
Interface width is 32, the byte serializer forwards tx_parallel_data[15:0]
first, followed by tx_parallel_data[31:16]
.
Related Information
PCI Express (PIPE) on page 229
For more information about using the Serialize x2 mode in the PCIe protocol.
5.3.1.2.4. Byte Serializer Serialize x4 Mode
The serialize x4 mode is used in high-speed applications such as the PCIe Gen3 protocol mode, where the FPGA fabric cannot operate as fast as the TX PCS.
In serialize x4 mode, the byte serializer serializes 32-bit data into 8-bit data. As the parallel data width from the TX FIFO is divided four times, the clock rate is quadrupled.
After byte serialization, the byte serializer forwards the least significant word first followed by the most significant word. For example, if the FPGA fabric-to-PCS
Interface width is 32, the byte serializer forwards tx_parallel_data[7:0]
first, followed by tx_parallel_data[15:8]
, tx_parallel_data[23:16]
and tx_parallel_data[31:24]
.
Related Information
PCI Express (PIPE) on page 229
For more information about using the Serialize x4 mode in the PCIe protocol.
5.3.1.3. 8B/10B Encoder
The 8B/10B encoder takes in 8-bit data and 1-bit control as input and converts them into a 10-bit output. The 8B/10B encoder automatically performs running disparity check for the 10-bit output. Additionally, the 8B/10B encoder can control the running disparity manually using the tx_forcedisp
and tx_dispval
ports.
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Figure 255. 8B/10B Encoder Block Diagrams
When the PCS-PMA Interface Width is 10 bits
To the Serializer dataout[9:0] 8B/10B Encoder
From the Byte Serializer datain[7:0] tx_datak tx_forcedisp tx_dispval
When the PCS-PMA Interface Width is 20 bits
To the Serializer 8B/10B Encoder dataout[19:10]
MSB
Encoding
From the Byte Serializer datain[15:8] tx_datak[1] tx_forcedisp[1] tx_dispval[1] dataout[9:0]
LSB
Encoding datain[7:0] tx_datak[0] tx_forcedisp[0] tx_dispval[0]
Note:
When the PCS-PMA interface width is 10 bits, one 8B/10B encoder is used to convert the 8-bit data into a 10-bit output. When the PCS-PMA interface width is 20 bits, two cascaded 8B/10B encoders are used to convert the 16-bit data into a 20-bit output.
The first eight bits (LSByte) is encoded by the first 8B/10B encoder and the next eight bits (MSByte) is encoded by the second 8B/10B encoder. The running disparity of the
LSByte is calculated first and passed on to the second encoder to calculate the running disparity of the MSByte.
You cannot enable the 8B/10B encoder when the PCS-PMA interface width is 8 bits or
16 bits.
5.3.1.3.1. 8B/10B Encoder Control Code Encoding
Figure 256. Control Code Encoding Diagram tx_clkout tx_parallel_data[15:0] tx_datak[1:0]
Code Group
8378
0
BCBC
1
0F00
0
BF3C
D3.4
D24.3
D28.5
K28.5
D15.0
D0.0
D31.5
D28.1
The tx_datak
signal indicates whether the 8-bit data being sent at the tx_parallel_data
port should be a control word or a data word. When tx_datak is high, the 8-bit data is encoded as a control word (Kx.y). When tx_datak
is low, the 8-bit data is encoded as a data word (Dx.y). Depending upon the PCS-PMA interface width, the width of tx_datak
is either 1 bit or 2 bits. When the PCS-PMA interface width is 10 bits, tx_datak
is a 1-bit word. When the PCS-PMA interface width is 20 bits, tx_datak
is a 2-bit word. The LSB of tx_datak
corresponds to the
LSByte of the input data sent to the 8B/10B encoder and the MSB corresponds to the
MSByte of the input data sent to the 8B/10B encoder.
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Related Information
Refer to Specifications & Additional Information for more information about 8B/10B encoder codes.
5.3.1.3.2. 8B/10B Encoder Reset Condition
The tx_digitalreset
signal resets the 8B/10B encoder. During the reset condition, the 8B/10B encoder outputs K28.5 continuously until tx_digitalreset
goes low.
5.3.1.3.3. 8B/10B Encoder Idle Character Replacement Feature
The idle character replacement feature is used in protocols such as Gigabit Ethernet, which requires the running disparity to be maintained during idle sequences. During these idle sequences, the running disparity has to be maintained such that the first byte of the next packet always starts when the running disparity of the current packet is negative.
When an ordered set, which consists of two code-groups, is received by the 8B/10B encoder, the second code group is converted into /I1/ or /I2 so that the final running disparity of the data code-group is negative. The first code group is /K28.5/ and the second code group is a data code-group other than /D21.5/ or /D2.2/. The ordered set /I1/ (/K28.5/D5.6/) is used to flip the running disparity and /I2/ (/K28.5/D16.2/) is used to preserve the running disparity.
5.3.1.3.4. 8B/10B Encoder Current Running Disparity Control Feature
The 8B/10B encoder performs a running disparity check on the 10-bit output data.
The running disparity can also be controlled using tx_forcedisp
and tx_dispval
.
When the PCS-PMA interface width is 10 bits, tx_forcedisp
and tx_dispval
are one bit each. When the PCS-PMA interface width is 20 bits, tx_forcedisp
and tx_dispval
are two bits each. The LSB of tx_forcedisp
and tx_dispval corresponds to the LSByte of the input data and the MSB corresponds to the MSByte of the input data.
5.3.1.3.5. 8B/10B Encoder Bit Reversal Feature
Figure 257. 8B/10B Encoder Bit Reversal Feature
Output
Data
Bit Reversal Mode
(8B/10B Encoder)
Input
Data
7 0 0 7
The bit reversal feature reverses the order of the bits of the input data. Bit reversal is performed at the output of the 8B/10B Encoder and is available even when the
8B/10B Encoder is disabled. For example, if the input data is 20-bits wide, bit reversal switches bit [0] with bit [19], bit [1] with bit [18] and so on.
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5.3.1.3.6. 8B/10B Encoder Byte Reversal Feature
Figure 258. 8B/10B Encoder Byte Reversal Feature
8
B
15 0
A
7
Output
Data
Byte Reversal Mode
(8B/10B Encoder)
Input
Data
0
A
7 8
B
15
The byte reversal feature is available only when the PCS-PMA interface width is 16 bits or 20 bits. Byte reversal is performed at the output of the 8B/10B Encoder and is available even when the 8B/10B Encoder is disabled. This feature swaps the LSByte with the MSByte. For example, when the PCS-PMA interface width is 16-bits, [7:0] bits
(LSByte) gets swapped with [15:8] bits (MSByte).
5.3.1.4. Polarity Inversion Feature
The polarity inversion feature is used in situations where the positive and the negative signals of a serial differential link are erroneously swapped during board layout. You can control this feature through tx_polinv port
, by enabling the Enable TX
Polarity Inversion option under the Standard PCS tab of the Native PHY IP Core. The polarity inversion feature inverts the value of each bit of the input data. For example, if the input data is 00101001, then the data gets changed to 11010110 after polarity inversion.
5.3.1.5. Pseudo-Random Binary Sequence (PRBS) Generator
Note: Refer to the PRBS Generator section in the Enhanced PCS Architecture chapter.
Related Information
Arria 10 Enhanced PCS Architecture
on page 461
5.3.1.6. TX Bit Slip
The TX bit slip allows the word boundary to be controlled by tx_std_bitslipboundarysel
. The TX bit slip feature is used in applications, such as CPRI, which has a data rate greater than 6 Gbps. The maximum number of the supported bit slips is PCS data width-1 and the slip direction is from MSB to LSB and from current to previous word.
5.3.2. Receiver Datapath
5.3.2.1. Word Aligner
The word aligner receives the serial data from the PMA and realigns the serial data to have the correct word boundary according to the word alignment pattern configured.
This word alignment pattern can be 7, 8, 10, 16, 20, 32 and 40 bits in length.
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Depending on your PCS-PMA interface width, the word aligner can be configured in one of the following modes:
• Bit slip
• Manual alignment
• Synchronous state machine
• Deterministic latency
Figure 259. Word Aligner Conditions and Modes
Word
Aligner
Single
Width
Double
Width
8 Bit 10 Bit 16 Bit 20 Bit
Bit Slip Manual Bit Slip Deterministic
Latency (1)
Note:
1. This option is available in CPRI mode.
Synchronous
State Machine
Manual Bit Slip Manual Bit Slip Deterministic
Latency (1)
Synchronous
State Machine
Manual
5.3.2.1.1. Word Aligner Bit Slip Mode
In bit slip mode, the word aligner operation is controlled by rx_bitslip
, which has to be held for two parallel clock cycles. At every rising edge of rx_bitslip
, the bit slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. Pattern detection is not used in bit slipping mode; therefore, rx_syncstatus
is not valid in this mode.
5.3.2.1.2. Word Aligner Manual Mode
In manual alignment mode, the word aligner operation is controlled by rx_std_wa_patternalign
. The word aligner operation is edge-sensitive or levelsensitive to rx_std_wa_patternalign
, depending upon the PCS-PMA interface width selected.
Table 259.
Word Aligner
rx_std_wa_patternalign
Behavior
PCS-PMA Interface Width
8
10
16
20 rx_std_wa_patternalign
Behavior
Rising edge sensitive
Level sensitive
Rising edge sensitive
Rising edge sensitive
If rx_std_wa_patternalign
is asserted, the word aligner looks for the programmed word alignment pattern in the received data stream. It updates the word boundary if it finds the word alignment pattern in a new word boundary. If rx_std_wa_patternalign
is deasserted, the word aligner maintains the current word boundary even when it sees the word alignment pattern in a new word boundary.
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The rx_syncstatus
and rx_patterndetect
signals, with the same latency as the datapath, are forwarded to the FPGA fabric to indicate the word aligner status.
After receiving the first word alignment pattern after rx_std_wa_patternalign
is asserted, both rx_syncstatus
and rx_patterndetect
are driven high for one parallel clock cycle. Any word alignment pattern received thereafter in the same word boundary causes only rx_patterndetect
to go high for one clock cycle. Any word alignment pattern received thereafter in a different word boundary causes the word aligner to re-align to the new word boundary only if rx_std_wa_patternalign
is asserted. The word aligner asserts rx_syncstatus
for one parallel clock cycle whenever it re-aligns to the new word boundary.
5.3.2.1.3. Word Aligner Synchronous State Machine Mode
In synchronous state machine mode, when the programmed number of valid synchronization code groups or ordered sets is received, rx_syncstatus
is driven high to indicate that synchronization is acquired. The rx_syncstatus
signal is constantly driven high until the programmed number of erroneous code groups is received without receiving intermediate good groups, after which rx_syncstatus
is driven low.
The word aligner indicates loss of synchronization ( rx_syncstatus
remains low) until the programmed number of valid synchronization code groups are received again.
5.3.2.1.4. Word Aligner Deterministic Latency Mode
In deterministic latency mode, the state machine removes the bit level latency uncertainty. The deserializer of the PMA creates the bit level latency uncertainty as it comes out of reset.
The PCS performs pattern detection on the incoming data from the PMA. The PCS aligns the data, after it indicates to the PMA the number of serial bits to clock slip the boundary.
If the incoming data has to be realigned, rx_std_wa_patternalign
must be reasserted to initiate another pattern alignment. Asserting rx_std_wa_patternalign
can cause the word align to lose synchronization if already achieved. This may cause rx_syncstatus
to go low.
Table 260.
PCS-PMA Interface Widths and Protocol Implementations
8
10
16
20
PCS-PMA Interface Width Protocol Implementations
Basic
• Basic
• Basic rate match
• CPRI
• PCIe Gen1 and Gen2
• GigE
Basic
• CPRI
• Basic
• Basic rate match
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5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes
Table 261.
Word Aligner Pattern Length for Various Word Aligner Modes
8
PCS-PMA
Interface
Width
Supported Word
Aligner Modes
Bit slip
Manual
Supported
Word Aligner
Pattern
Lengths
8 rx_std_wa_patte rnalign
behavior
8, 16 rx_std_wa_patt ernalign
has no effect on word alignment. The single width word aligner updates the word boundary, only when the
FPGA fabricasserted BITSLIP signal toggles.
Word alignment is controlled by rx_std_wa_patt ernalign
and is edge-sensitive to this signal.
rx_syncstatus behavior
N/A
Asserted high for one parallel clock cycle when the word aligner aligns to a new boundary.
10 Bit slip 7 N/A rx_patterndetect behavior
N/A
Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
N/A
Manual
Deterministic latency
(CPRI mode only)
7, 10
10 rx_std_wa_patt ernalign
has no effect on word alignment. The single width word aligner updates the word boundary, only when the
FPGA fabricasserted BITSLIP signal toggles.
Word alignment is controlled by rx_std_wa_patt ernalign
and is level-sensitive to this signal.
Asserted high for one parallel clock cycle when the word aligner aligns to a new boundary.
—
Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
— Word alignment is controlled by rx_std_wa_patt ernalign
(edgesensitive to this signal) and the state machine works in conjunction with
PMA to achieve deterministic latency on the RX path for CPRI and
OBSAI applications.
Synchronous State
Machine
7, 10 rx_std_wa_patt ernalig n has no effect on word alignment.
Stays high as long as the synchronization conditions are satisfied.
Asserted high for one parallel clock cycle when the word alignment pattern continued...
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PCS-PMA
Interface
Width
16
20
Supported Word
Aligner Modes
Bit slip
Manual
Bit slip
Manual
Deterministic latency
(CPRI mode only)
Supported
Word Aligner
Pattern
Lengths rx_std_wa_patte rnalign
behavior
16
8, 16, 32
7
7, 10, 20, 40
10 rx_syncstatus behavior rx_patterndetect behavior rx_std_wa_patt ernalign
has no effect on word alignment. The double width word aligner updates the word boundary, only when the
FPGA fabricasserted BITSLIP signal toggles.
Word alignment is controlled by rising-edge of rx_std_wa_patt ernalign
.
N/A
Stays high after the word aligner aligns to the word alignment pattern.
Goes low on receiving a rising edge on rx_std_wa_patt ernalign
until a new word alignment pattern is received.
N/A rx_std_wa_patt ernalign
has no effect on word alignment. The double width word aligner updates the word boundary, only when the
FPGA fabricasserted BITSLIP signal toggles.
Word alignment is controlled by rising edge of rx_std_wa_patt ernalign
.
Word alignment is controlled by rx_std_wa_patt ernalign
(edgesensitive to this signal) and the deterministic latency state machine which controls the PMA to
Stays high after the word aligner aligns to the word alignment pattern.
Goes low on receiving a rising edge on rx_std_wa_patt ernalign
until a new word alignment pattern is received.
— appears in the current word boundary.
N/A
Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
N/A
Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
— continued...
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PCS-PMA
Interface
Width
Supported Word
Aligner Modes
Synchronous State
Machine
Supported
Word Aligner
Pattern
Lengths rx_std_wa_patte rnalign
behavior
7, 10, 20 achieve deterministic latency on the RX path for CPRI and
OBSAI applications.
FPGA fabric-driven rx_std_wa_patt ernalign
signal has no effect on word alignment.
rx_syncstatus behavior
Stays high as long as the synchronization conditions are satisfied.
rx_patterndetect behavior
Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
5.3.2.1.6. Word Aligner RX Bit Reversal Feature
The RX bit reversal feature reverses the order of the data received from the PMA. It is performed at the output of the Word Aligner and is available even when the Word
Aligner is disabled. If the data received from the PMA is a 10-bit data width, the bit reversal feature switches bit [0] with bit [9], bit [1] with bit [8], and so on. For example, if the 10-bit data is 1000010011, the bit reversal feature, when enabled, changes the data to 1100100001.
5.3.2.1.7. Word Aligner RX Byte Reversal Feature
The RX byte reversal feature is available only when the PCS-PMA interface width is 16 bits or 20 bits. This feature reverses the order of the data received from the PMA. RX byte reversal reverses the LSByte of the received data with its MSByte and vice versa.
If the data received is 20-bits, bits[0..9] are swapped with bits[10..20] so that the resulting 20-bit data is [[10..20],[0..9]]. For example, if the 20-bit data is
11001100001000011111, the byte reversal feature changes the data to
10000111111100110000.
5.3.2.2. RX Polarity Inversion Feature
The RX polarity inversion feature inverts each bit of the data received from the PMA. If the data received is a 10-bit data. Bit[0] content is inverted to its complement,
~bit[0], bit[1] is inverted to its complement, ~bit[1], bit[2] is inverted to its complement, ~bit[2], and so on. For example, if the 10-bit data is 1111100000, the polarity inversion feature inverts it to 0000011111.
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5.3.2.3. Rate Match FIFO
The rate match FIFO compensates for the frequency differences between the local clock and the recovered clock up to ± 300 ppm by inserting and deleting skip/idle characters in the data stream. The rate match FIFO has several different protocol specific modes of operation. All of the protocol specific modes depend upon the following parameters:
• Rate match deletion—occurs when the distance between the write and read pointers exceeds a certain value due to write clock having a higher frequency than the read clock.
• Rate match insertion—occurs when the distance between the write and the read pointers becomes less than a certain value due to the read clock having a higher frequency than the write clock.
• Rate match full—occurs when the write pointer wraps around and catches up to the slower-advancing read pointer.
• Rate match empty—occurs when the read pointer catches up to the sloweradvancing write pointer.
Rate match FIFO operates in six modes:
• Basic single width
• Basic double width
• GigE
• PIPE
• PIPE 0 ppm
• PCIe
Related Information
•
Rate Match FIFO in Basic (Single Width) Mode
on page 306
For more information about implementing rate match FIFO in basic single width mode.
•
Rate Match FIFO Basic (Double Width) Mode on page 308
For more information about implementing rate match FIFO in basic double width mode.
•
How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers on page
118
For more information about implementing rate match FIFO in GigE mode.
•
PCI Express (PIPE) on page 229
For more information about implementing rate match FIFO in PCIe mode.
•
How to Implement PCI Express (PIPE) in Arria 10 Transceivers on page 246
For more information about implementing rate match FIFO in PIPE mode.
•
Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
on page 300
•
How to Implement the Basic Rate Match Protocol Using the Arria 10 Transceiver
Native PHY IP Core on page 300
For more information about implementing rate match FIFO for each mode.
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5.3.2.4. 8B/10B Decoder
The general functionality for the 8B/10B decoder is to take a 10-bit encoded value as input and produce an 8-bit data value and a 1-bit control value as output. In configurations with the rate match FIFO enabled, the 8B/10B decoder receives data from the rate match FIFO. In configurations with the rate match FIFO disabled, the
8B/10B decoder receives data from the word aligner. The 8B/10B decoder operates in two conditions:
• When the PCS-PMA interface width is 10 bits and FGPA fabric-PCS interface width is 8 bits
• When the PCS-PMA interface width is 20 bits and FPGA fabric-PCS interface width is 16 bits
Figure 260. 8B/10B Decoder in Single-Width and Double-Width Mode
Single-Width Mode Double-Width Mode datain[19:10]
8B/10B Decoder
(MSByte) rx_dataout[15:8] rx_datak[1] rx_errdetect[1] rx_disperr[1] datain[9:0]
8B/10B Decoder
(LSByte) rx_dataout[7:0] rx_datak rx_errdetect rx_disperr recovered clock or tx_clkout[0] datain[9:0]
Current Running Disparity recovered clock or tx_clkout[0]
8B/10B Decoder
(LSByte) rx_dataout[7:0] rx_datak[0] rx_errdetect[0] rx_disperr[0] recovered clock or tx_clkout[0]
When the PCS-PMA interface width is 10 bits, only one 8B/10B decoder is used to perform the conversion. When the PCS-PMA interface width is 20 bits, two cascaded
8B/10B decoders are used. The 10-bit LSByte of the received 20-bit encoded data is decoded first and the ending running disparity is forwarded to the 8B/10B decoder responsible for decoding the 10-bit MSByte. The cascaded 8B/10B decoder decodes the 20- bit encoded data into 16-bit data + 2-bit control identifier. The MSB and LSB of the 2-bit control identifier correspond to the MSByte and LSByte of the 16-bit decoded data code group. The decoded data is fed to the byte deserializer or the RX
FIFO.
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5.3.2.4.1. 8B/10B Decoder Control Code Encoding
Figure 261. 8B/10B Decoder in Control Code Group Detection
When the PCS-PMA Interface Width is 10 Bits tx_clkout
TX datain[9:0] D3.4
D24.3
D28.5
K28.5
D15.0
RX rx_datak dataout[7:0] 83 78 BC BC 0F
D0.0
00
D31.5
D3.4
BF 83
When the PCS-PMA Interface Width is 20 Bits tx_clkout
TX datain[19:10] datain[9:0]
D3.4
D24.3
D28.5
K28.5
RX rx_datak[1:0] dataout[15:0]
00
16’h8378
01
16’hBCBC
D15.0
D15.0
00
D3.4
D3.4
D3.4
D24.3
00
16’h8378
D28.5
K28.5
01
16’hBCBC
D15.0
D15.0
00
D3.4
D3.4
16’h0F0F 16’h8383 16’h0F0F 16’h8383
The 8B/10B decoder indicates whether the decoded 8-bit code group is a data or control code group on rx_datak
. If the received 10-bit code group is one of the 12 control code groups (/Kx.y/) specified in the IEEE 802.3 specification, rx_datak driven high. If the received 10-bit code group is a data code group (/Dx.y/),
is rx_datak
is driven low.
5.3.2.4.2. 8B/10B Decoder Running Disparity Checker Feature
Running disparity checker resides in 8B/10B decoder module. This checker checks the current running disparity value and error based on the rate match output.
rx_runningdisp
and rx_disperr
indicate positive or negative disparity and disparity errors, respectively.
5.3.2.5. Pseudo-Random Binary Sequence (PRBS) Checker
Note: Refer to the PRBS Checker section in the Enhanced PCS Architecture chapter.
Related Information
Arria 10 Enhanced PCS Architecture
on page 461
5.3.2.6. Byte Deserializer
The byte deserializer allows the transceiver to operate at data rates higher than those supported by the FPGA fabric. It deserializes the recovered data by multiplying the data width two or four times, depending upon the deserialization mode selected. The byte deserializer is optional in designs that do not exceed the FPGA fabric interface frequency upper limit. You can bypass the byte deserializer by disabling it in the
Quartus Prime Transceiver Native PHY. The byte deserializer operates in disabled, deserialize x2, or deserialize x4 modes.
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Figure 262. Byte Deserializer Block Diagram
Datapath from the
8B/10B Decoder,
Rate Match FIFO, or Word Aligner
Byte
Deserializer
Datapath to the RX PCS FIFO
Low speed parallel clock
/2,
/4
5.3.2.6.1. Byte Deserializer Disabled Mode
In disabled mode, the byte deserializer is bypassed. The data from the 8B/10B decoder, rate match FIFO, or word aligner is directly transmitted to the RX FIFO, depending on whether or not the 8B/10B decoder and rate match FIFO are enabled.
Disabled mode is used in low speed applications such as GigE, where the FPGA fabric and the PCS can operate at the same clock rate.
5.3.2.6.2. Byte Deserializer Deserialize x2 Mode
The deserialize x2 mode is used in high-speed applications such as the PCIe Gen1 or
Gen2 protocol implementation, where the FPGA fabric cannot operate as fast as the TX
PCS.
In deserialize x2 mode, the byte deserializer deserializes 8-bit, 10-bit (when the
8B/10B encoder is not enabled), 16-bit, and 20-bit (when the 8B/10B encoder is not enabled) input data into 16-bit, 20-bit, 32-bit, and 40-bit data, respectively. As the parallel data width from the word aligner is doubled, the clock rate is halved.
5.3.2.6.3. Byte Deserializer Deserialize x4 Mode
The deserialize x4 mode is used in high-speed applications where the FPGA fabric cannot operate as fast as the TX PCS.
In deserialize x4 mode, the byte deserializer deserializes 8-bit data into 32-bit data.
As the parallel data width from the word aligner is quadrupled, the clock rate is divided four times.
5.3.2.6.4. Bonded Byte Deserializer
The bonded byte deserializer is also available for channel-bundled applications such as
PIPE. In this configuration, the control signals of the byte deserializers of all the channels are bonded together. A master channel controls all the other channels to prevent skew between the channels.
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5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe Gen3 PCS)
The RX FIFO interfaces between the PCS on the receiver side and the FPGA fabric and ensures reliable transfer of data and status signals. It compensates for the phase difference between the FPGA fabric and the PCS on the receiver side. The RX FIFO has a depth of 8. It operates in register FIFO and low latency modes.
Figure 263. RX FIFO Block Diagram
Datapath from
Byte Deserializer, 8B/10B Decoder,
Rate Match FIFO, or Deserializer wr_clk
RX
FIFO rd_clk
Datapath to FPGA Fabric or PIPE Interface
Parallel clock
(recovered) from clock divider rx_clkout rx_coreclkin
5.3.2.7.1. RX FIFO Low Latency Mode
The low latency mode incurs two to three cycles of latency when connecting it with the
FPGA fabric. The FIFO empty and the FIFO full threshold values are made closer so that the depth of the FIFO decreases, which in turn decreases the latency.
5.3.2.7.2. RX FIFO Register Mode
The register mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements. This is accomplished by tying the read clock of the FIFO with its write clock. The register mode incurs only one clock cycle of latency when interfacing to the FPGA fabric.
5.4. Arria 10 PCI Express Gen3 PCS Architecture
Arria 10 architecture supports the PCIe Gen3 specification. Intel provides two options to implement the PCI Express solution:
• You can use the Intel Hard IP solution. This complete package provides both the
MAC layer and the physical (PHY) layer functionality.
• You can implement the MAC in the FPGA core and connect this MAC to the transceiver PHY through the PIPE interface.
This section focuses on the basic blocks of PIPE 3.0-based Gen3 PCS architecture. The
PIPE 3.0-based Gen3 PCS uses a 128b/130b block encoding/decoding scheme, which is different from the 8B/10B scheme used in Gen1 and Gen2. The 130-bit block contains a 2-bit sync header and a 128-bit data payload. For this reason, Arria 10 devices include a separate Gen3 PCS that supports functionality at Gen3 speeds. This
PIPE interface supports the seamless switching of Data and Clock between the Gen1,
Gen2, and Gen3 data rates, and provides support for PIPE 3.0 features. The PCIe
Gen3 PCS supports the PIPE interface with the Hard IP enabled, as well as with the
Hard IP bypassed.
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Figure 264. Gen3 PCS Block Diagram
TX PCIe Gen3 PCS Standard
32
PCS
FPGA
Fabric
32
TX
PMA tx_clkout
PIPE Interface
CDR
Control
/4 tx_clkout
Auto-Speed Negotiation
Gen3 x1, x2, x4, x8
RX PCIe Gen3 PCS
32
32
RX
PMA rx_clkout rx_clkout or tx_clkout
Clock Generation Block (CGB)
Clock Divider
ATX PLL fPLL tx_clkout or rx_clkout
Serial Clock
Parallel and Serial Clocks hclk for ASN Block
Parallel and Serial Clocks
Serial Clock
Input Reference Clock
Related Information
•
PCI Express (PIPE) on page 229
For more information about PCIe Gen1, Gen2, and Gen3 implementation and configuration, refer to "Supported PIPE Features."
• Intel Arria 10 Hard IP for PCIe IP Cores
5.4.1. Transmitter Datapath
This section describes the TX FIFO and the Gearbox of the Gen3 PCS transmitter.
5.4.1.1. TX FIFO (Shared with Standard and Enhanced PCS)
The TX FIFO in each channel ensures a reliable transfer of data and status signals between the PCS channel and the FPGA fabric. The TX FIFO compensates for the phase difference between the low speed parallel PCS clock and the FPGA fabric clock.
The RX and TX FIFOs are shared with standard and enhanced PCS. In Hard IP mode, the TX FIFO works in register mode. In PIPE mode, the TX FIFO works in low latency mode.
The TX FIFO operates in low latency mode in PIPE Gen1, Gen2, and Gen3 configurations. The Low Latency mode incurs 3-4 cycles of latency when connecting with the FPGA fabric. The FIFO empty and the FIFO full threshold values are made closer so that the depth of the FIFO decreases, which decreases the latency.
Related Information
Arria 10 Standard PCS Architecture
on page 479
For more information about TX FIFO.
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5.4.1.2. Gearbox
The PCIe 3.0 base specification specifies a block size of 130 bits, with the exception of the SKP Ordered Sets, which can be of variable length. An implementation of a 130-bit data path takes significant resources, so the PCIe Gen3 PCS data path is implemented as 32-bits wide. Because the TX PMA data width is fixed to 32 bits, and the block size is 130 bits with variations, a gearbox is needed to convert 130 bits to 32 bits.
The gearbox block in the TX PCS converts the 130-bit data
( tx_parallel_data[127:0
] + pipe_tx_sync_hdr[1:0
]) to 32-bit data required by the TX PMA as the datapath implementation is 32 bits to reduce usage of resources. The 130-bit data is received as follows in the 32-bit datapath: 34 (32 + 2bit sync header), 32, 32, 32. During the first cycle the gearbox converts the 34-bit input data to 32-bit data. During the next 3 clock cycles the gearbox merges bits from adjacent cycles to form the 32-bit data. In order for the gearbox to work correctly, a gap must be provided in the data for every 16 shifts as each shift is 2 bits for converting the initial 34-bit to 32-bit in the gearbox. After 16 shifts the gearbox has an extra 32-bit data that was transmitted out, and thus a gap is required in the input data stream. This gap is achieved by driving pipe_tx_data_valid
low for one cycle after every 16 blocks of input data
(tx_parallel_data)
.
Related Information
on page 239
5.4.2. Receiver Datapath
This section describes the Block Synchronizer, Rate Match FIFO, and RX FIFO of the
Gen3 PCS receiver.
5.4.2.1. Block Synchronizer
PMA parallelization occurs at arbitrary word boundaries. Consequently, the parallel data from the RX PMA CDR must be realigned to meaningful character boundaries. The
PCI Express 3.0 base specification outlines that the data is formed using 130-bit blocks, with the exception of SKP blocks.
The SKP Ordered Set can be 66, 98, 130, 162, or 194 bits long. The block synchronizer searches for the Electrical Idle Exit Sequence Ordered Set (or the last number of fast training sequences (NFTS) Ordered Set) or skip (SKP) Ordered Set to identify the correct boundary for the incoming stream and to achieve the block alignment. The block is realigned to the new block boundary following the receipt of a
SKP Ordered Set, as it can be of variable length.
5.4.2.2. Rate Match FIFO
In asynchronous systems, the upstream transmitter and local receiver can be clocked with independent reference clocks. Frequency differences in the order of a few hundred PPM can corrupt the data when latching from the recovered clock domain to the local receiver reference clock domain. The rate match FIFO compensates for small clock frequency differences between these two clock domains by inserting or removing
SKP symbols in the data stream to keep the FIFO from going empty or full respectively.
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The PCI Express 3.0 base specification defines that the SKP Ordered Set (OS) can be
66, 98, 130, 162, or 194 bits long. The SKP OS has the following fixed bits: 2-bit
Sync, 8-bit SKP END, and a 24-bit LFSR = 34 Bits. The Rate Match/Clock compensation block adds or deletes the 4 SKP characters (32-bit) to keep the FIFO from going empty or full, respectively. If the FIFO is nearly full, it deletes the 4 SKP characters (32-bit) by disabling write whenever a SKP is found. If the FIFO is nearly empty, the design waits for a SKP Ordered Set to start and then stops reading the data from the FIFO, and inserts a SKP in the outgoing data. The actual FIFO core
(memory element) is in the Shared Memory block in the PCS channel.
Figure 265. Rate Match FIFO data_out
SKP
Inserter fifo_pempty rd_en data
Asynchronous
FIFO fifo_pfull wr_en data
SKP
Deleter data_in rd_clk wr_clk
5.4.2.3. RX FIFO (Shared with Standard and Enhanced PCS)
The RX FIFO in each channel ensures a reliable transfer of data and status signals between the PCS channel and the FPGA fabric. The RX FIFO compensates for the phase difference between the parallel PCS clock and the FPGA fabric clock. In PIPE mode, the RX FIFO works in low latency mode.
Related Information
Arria 10 Standard PCS Architecture
on page 479
For more information about RX FIFO.
5.4.3. PIPE Interface
This section describes the Auto Speed Negotiation and the Clock Data Recovery
Control of the PIPE interface.
5.4.3.1. Auto Speed Negotiation
Auto speed negotiation controls the operating speed of the transceiver when operating under PIPE 3.0 modes. By monitoring the pipe_rate
signal from the PHY-MAC, this feature changes the transceiver from PIPE Gen1 operation mode to Gen2 operation mode, or from PIPE Gen1 operation mode to Gen2 operation mode to Gen3 operation mode, or vice versa. The PIPE interface clock rate is adjusted to match the data throughput.
Related Information
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5.4.3.2. Clock Data Recovery Control
The CDR control feature is used for the L0s fast exit when operating in PIPE Gen3 mode. Upon detecting an Electrical Idle Ordered Set (EIOS), this feature takes manual control of the CDR by forcing it into a lock-to-reference mode. When an exit from electrical idle is detected, this feature moves the CDR into lock-to-data mode to achieve fast data lock.
5.5. Intel Arria 10 Transceiver PHY Architecture Revision History
Changes Document
Version
2018.06.15
2016.10.31
2015.05.02
2015.12.18
2015.11.02
Made the following changes:
• Changed the AC gain settings for high bandwidth and medium bandwidth mode in the "High Gain
Mode" section.
• Added a note about bit slipping to the "RX Gearbox, RX Bitslip, and Polarity Inversion" section.
• Clarified the description of DC gain circuitry in the "Continuous Time Linear Equalization (CTLE)" section.
• Clarified the description of CTLE manual mode in the "High Data Rate Mode" section.
• Removed the Channel Loss Compensation column from the "Pre-Emphasis Taps" table.
• Updated Serial Loopback Path and Reverse Serial Loopback Path/Pre CDR figures and their notes.
• Changed the instruction in step 1 of the "How to Enable CTLE and DFE" section.
Made the following changes:
• Added a note below the diagram "Diagnostic Loopback Path/Pre CDR" saying "TX pre-emp is not supported in pre-CDR loopback. TX pre-emp is recommended to set to zero for all taps."
• "Idle OS Deletion" description updated to "Deletion of Idles occurs in groups of four OS (when there are two consecutive OS) until the rx_enh_fifo_pfull flag deasserts".
• Removed square wave pattern generator.
Made the following changes:
• Updated the configuration methods for the CTLE,and DFE schemes in the Arria 10 PMA Architecture section.
• Removed a signal in the "Gen3 PCS Block Diagram" in the Arria 10 PCI Express Architecture section.
Made the following changes:
• Updated the configuration methods for the CTLE, DFE, and adaptation schemes in the Arria 10 PMA
Architecture section.
Made the following changes to the PMA Architecture section:
• Updated "Channel Pulse Response" figure in the Decision Feedback Equalization (DFE) section.
• Updated the value for the "Number of fixed DFE taps" in the Equalization table in the PMA
Parameters section.
Made the following changes to the Enhanced PCS Architecture section:
• Updated Phase Compensation Mode and Basic Mode sections.
• Added 64B/66B Encoder Reset Condition section.
• Updated TX Gearbox, TX Bitslip and Polarity Inversion sections.
• Updated RX Bitslip in RX Gearbox, RX Bitslip, and Polarity Inversion figure.
• Added “block synchronization” in Enhanced PCS introduction note.
• Updated Enhanced PCS TX FIFO section.
• Updated reference link for TX Phase Compensation Mode section.
• Updated TX Register Mode description.
• Updated Interlaken Frame Generator section description.
• Updated 64B/66B Encoder and Transmitter State Machine section title.
• Updated PRBS Pattern Generator (Shared between Enhanced and Standard) title
• Updated Square Wave Pattern Generator (Shared between Enhanced and Standard)
• Updated RX Register Mode description.
continued...
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Document
Version
2015.05.11
2014.12.15
2014.08.15
Changes
Made the following changes to the Standard PCS Architecture section:
• Updated the Byte Serializer section for Serialize x2 and x4 modes.
• Added new figures for 8B/10B Encoder Bit and Byte Reversal features.
Made the following changes to the PMA Architecture section:
• Updated link to XCVR_A10_RX_TERM_SEL in the "Transmitter Buffer".
• Updated ODI vertical steps to 63 (0 and +/-32) in the "Receiver Buffer".
• Updated CTLE section for adaptation modes. Moved CTLE in the "How to Enable CTLE and DFE" section.
• Updated VGA section for adaptation modes.
• Updated DFE section for adaptation modes. Moved DFE to the new "How to Enable CTLE and DFE" section.
• Removed Triggered DFE mode.
• Removed all references related to floating taps.
Made the following changes to the Enhanced PCS Architecture section:
• Updated pattern generators (PRBS, Square Wave and PRP), PRBS Checker and PRP Verifier sections.
• Revised the descriptions of TX FIFO Fast Register Mode.
• Changed the title and descriptions in "Enhanced PCS Pattern Generators".
• Added new sections for "PRBS Pattern Generator (Shared between Enhanced and Standard PCSes)",
"Square Wave Pattern Generator (Shared between Enhanced and Standard PCSes)", and "Pseudo-
Random Pattern Generator."
• Changed sub title "PRBS Verifier" to "PRBS Checker" and changed their descriptions.
• Changed descriptions in "PRP Verifier".
Made the following changes to the Enhanced PCS Architecture section:
• Added PRBS7 Generator to support 64-bit width only.
• Updated the rule for tx_enh_data_valid control signal when TX FIFO is used in phase compensation mode.
Made the following changes to the PCI Express Gen3 PCS Architecture section:
• Updated TX FIFO in Transmitter Datapath.
• Changed the Standard PCS data rate from 12.5 Gbps to 12 Gbps.
Made the following changes to the Standard PCS Architecture section:
• Changed the Standard PCS data rate from 12.5 Gbps to 12 Gbps.
Made the following changes to the PMA Architecture section:
• Added High Speed Differential I/O and Power Distribution Network to the Transmitter Buffer circuitry.
• Added Power Distribution Network induced Inter-Symbol Interference compensation.
• Replaced the figures related to Programmable Pre Emphasis with a link to Pre Emphasis and Output
Swing Settings Estimator.
Made the following changes to the PCI Express Gen3 PCS Architecture section:
• Corrected the low latency mode cycles of latency in the TX FIFO (Shared with Standard and
Enhanced PCS).
Made the following changes to the Standard PCS Architecture section:
• Removed the features not supported by 8B/10B Decoder.
• Changed the description of TX FIFO to include the depth of the TX FIFO.
• Updated the description of Polarity Inversion feature to include how to enable Polarity Inversion.
• Updated the description of Pseudo-Random Binary Sequence (PRBS) Generator on the supported
PCS-PMA interface widths.
• Changed the value for Supported Word Aligner Pattern Lengths for Bitslip Mode when the PCS-PMA
Interface Width is 8 in Table 5-8 Word Aligner Pattern Length for Various Word Aligner Modes.
• Changed the description of RX FIFO to include the depth of the RX FIFO.
• Changed the RX Word Aligner pattern length for PCS-PMA interface width 8 in Bitslip Mode.
Made the following changes to the Enhanced PCS Architecture section:
• Changed references from MegaWizard to Parameters Editor.
continued...
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Document
Version
2013.12.02
Changes
Made the following changes to the PMA Architecture section:
• Added 2nd post-tap and pre-tap Pre-Emphasis signals .
• Updated DFE and CTLE modes of operation and Use Models.
• Added new sections on How to Enable CTLE and How to Enable DFE.
• Changed max data rate for GT channels to 25.8 Gbps in the Receiver Buffer CTLE section.
• Updated Receiver Buffer figure by adding and modifying Adaptive Parametric Tuning Engine to include CDR and DFE.
• Updated VGA section that includes VGA Frequency response for different gain settings.
Initial release.
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6. Reconfiguration Interface and Dynamic
Reconfiguration
This chapter explains the purpose and the use of the Arria 10 reconfiguration interface that is part of the Transceiver Native PHY IP core and the Transceiver PLL IP cores.
Dynamic reconfiguration is the process of dynamically modifying transceiver channels and PLLs to meet changing requirements during device operation. Arria 10 transceiver channels and PLLs are fully customizable, allowing a system to adapt to its operating environment. You can customize channels and PLLs by dynamically triggering reconfiguration during device operation or following power-up. Dynamic reconfiguration is available for Arria 10 Transceiver Native PHY, fPLL, ATX PLL, and
CMU PLL IP cores.
Use the reconfiguration interface to dynamically change the transceiver channel or PLL settings for the following applications:
• Fine tuning signal integrity by adjusting TX and RX analog settings
• Enabling or disabling transceiver channel blocks, such as the PRBS generator and the checker
• Changing data rates to perform auto negotiation in CPRI, SATA, or SAS applications
• Changing data rates in Ethernet (1G/10G) applications by switching between standard and enhanced PCS datapaths
• Changing TX PLL settings for multi-data rate support protocols such as CPRI
• Changing RX CDR settings from one data rate to another
• Switching between multiple TX PLLs for multi-data rate support
The Native PHY and Transmit PLL IP cores provide the following features that allow dynamic reconfiguration:
• Reconfiguration interface
• Configuration files
• Feature to add PMA analog settings (optional) to the Configuration files (Native
PHY only)
• Multiple reconfiguration profiles (Native PHY and ATX PLL)
• Embedded reconfiguration streamer (Native PHY and ATX PLL)
• Altera Debug Master Endpoint (ADME)
• Optional reconfiguration logic
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*Other names and brands may be claimed as the property of others.
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9001:2008
Registered
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6.1. Reconfiguring Channel and PLL Blocks
The following table lists some of the available dynamic reconfiguration features in
Arria 10 devices.
Table 262.
Arria 10 Dynamic Reconfiguration Feature Support
Reconfiguration
Channel Reconfiguration
PLL Reconfiguration
Features
PMA analog features
• V
OD
• Pre-emphasis
• Continuous Time Linear Equalizer (CTLE)
• Decision Feedback Equalization (DFE)
TX PLL
• TX local clock dividers
• TX PLL switching
RX CDR
• RX CDR settings
• RX CDR reference clock switching
Reconfiguration of PCS blocks within the datapath
Datapath switching
• Standard, Enhanced, PCS Direct
PLL settings
• Counters
PLL reference clock switching
Related Information
on page 563
6.2. Interacting with the Reconfiguration Interface
Each transceiver channel and PLL contains an Avalon Memory-Mapped (Avalon-MM) reconfiguration interface. The reconfiguration interface provides direct access to the programmable space of each channel and PLL. Communication with the channel and
PLL reconfiguration interface requires an Avalon-MM master. Because each channel and PLL has its own dedicated Avalon-MM interface, you can dynamically modify channels either concurrently or sequentially, depending on how the Avalon-MM master is connected to the Avalon-MM reconfiguration interface.
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Figure 266. Reconfiguration Interface in Arria 10 Transceiver IP Cores
Avalon-MM Master
Native PHY IP Core
Ch0: Avalon
Reconfiguration
Interface
Embedded Controller in FPGA or Embedded Processor on PCB
Ch1: Avalon
Reconfiguration
Interface
Transceiver PLL IP Core
Avalon
Reconfiguration
Interface
A transmit PLL instance has a maximum of one reconfiguration interface. Unlike PLL instances, a Native PHY IP core instance can specify multiple channels. You can use a dedicated reconfiguration interface for each channel or share a single reconfiguration interface across all channels to perform dynamic reconfiguration.
Avalon-MM masters interact with the reconfiguration interface by performing Avalon read and write operations to initiate dynamic reconfiguration of specific transceiver parameters. All read and write operations must comply with Avalon-MM specifications.
Figure 267. Top-Level Signals of the Reconfiguration Interface reconfig_clk reconfig_reset reconfig_read reconfig_write reconfig_address reconfig_writedata reconfig_readdata reconfig_waitrequest
Native PHY IP core or
Transceiver PLL IP core
The user-accessible Avalon-MM reconfiguration interface and PreSICE Avalon-MM interface share a single internal configuration bus. This bus is arbitrated to get access to the Avalon-MM interface of the channel or PLL. Refer to the Arbitration section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.
Related Information
•
on page 512
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•
Reconfiguration Interface and Arbitration with PreSICE Calibration Engine on page
567
• Avalon Interface Specifications
6.2.1. Reading from the Reconfiguration Interface
Reading from the reconfiguration interface of the Transceiver Native PHY IP core or
Transceiver PLL IP core retrieves the current value at a specific address.
Figure 268. Reading from the Reconfiguration Interface
1 3 reconfig_clk
5 reconfig_address 119h reconfig_read reconfig_waitrequest reconfig_readdata reconfig_write reconfig_writedata
2
4
Valid readdata
Note:
1. The master asserts reconfig_address and reconfig_read after the rising edge of reconfig_clk.
2. The slave asserts reconfig_waitrequest, stalling the transfer.
3. The master samples reconfig_waitrequest. Because reconfig_waitrequest is asserted, the cycle becomes a wait state and reconfig_address,
reconfig_read, and reconfig_write remain constant.
4. The slave presents valid reconfig_readdata and deasserts reconfig_waitrequest.
5. The master samples reconfig_waitrequest and reconfig_readdata, completing the transfer.
After the reconfig_read
signal is asserted, the reconfig_waitrequest
signal asserts for a few reconfig_clock
cycles, then deasserts. This deassertion indicates the reconfig_readdata
bus contains valid data.
You must check for the internal configuration bus arbitration before performing reconfiguration. Refer to the Arbitration section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.
Related Information
on page 512
6.2.2. Writing to the Reconfiguration Interface
Writing to the reconfiguration interface of the Transceiver Native PHY IP core or TX PLL
IP core changes the data value at a specific address. All writes to the reconfiguration interface must be read-modify-writes, because two or more features may share the same reconfiguration address. When two or more features share the same reconfiguration address, one feature's data bits are interleaved with another feature's data bits.
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Figure 269. Writing to the Reconfiguration Interface
1 2 reconfig_clk
119h reconfig_address reconfig_write reconfig_writedata reconfig_waitrequest
0000000c
Note: reconfig_read reconfig_readdata
1. The master asserts the reconfig_address, reconfig_write, and reconfig_writedata signals.
2. The slave (channel or PLL) captures reconfig_writedata, ending the transfer.
You must check for the internal configuration bus arbitration before performing reconfiguration. Refer to the Arbitration section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.
Related Information
•
on page 512
•
on page 535
6.3. Configuration Files
The Arria 10 Transceiver Native PHY and Transmit PLL IP cores optionally allow you to save the parameters you specify for the IP instances as configuration files. The configuration file stores addresses and data values for that specific IP instance.
The configuration files are generated during IP generation. They are located in the
<IP instance name>\altera_xcvr_<IP type>_a10_<quartus version>\synth
\reconfig
subfolder of the IP instance. The configuration data is available in the following formats:
• SystemVerilog packages: <name>.sv
• C Header files: <name>.h
• Memory Initialization File (MIF): <name>.mif
Select one or more of the configuration file formats on the Dynamic
Reconfiguration tab of the Transceiver Native PHY or Transmit PLL parameter editor to store the configuration data. All configuration files generated for a particular IP instance contain the same address and data values. The contents of the configuration files can be used to reconfigure from one transceiver /PLL configuration to another.
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You can optionally allow the Native PHY IP core to include PMA Analog settings in the configuration files by enabling the feature Include PMA Analog settings in
configuration files in the Dynamic Reconfirmation tab of the Transceiver Native
PHY IP Parameter Editor. This feature is disabled by default. Enabling this feature adds the PMA analog settings specified in the Analog PMA settings (Optional) tab of the
Native PHY IP Parameter Editor to the configuration files. Even with this option enabled in the Native PHY IP Parameter Editor, you must still specify Quartus Settings
File (QSF) assignments for your analog settings when compiling your static design.
The analog settings selected in the Native PHY IP Parameter Editor are used only to include these settings and their dependent settings in the selected configuration files.
Refer to the Analog Parameter Settings chapter for details about QSF assignments for the analog settings.
Example 2. SystemVerilog Configuration File
26'h008FF04,
// [25:16]-DPRIO address=0x008;
// [15:8]-bit mask=0xFF;
// [7:7]- hssi_tx_pcs_pma_interface_pldif_datawidth_mode=pldif_data_10bit(1'h0);
// [6:5]-hssi_tx_pcs_pma_interface_tx_pma_data_sel=ten_g_pcs(2'h0);
// [4:4]-hssi_tx_pcs_pma_interface_prbs_gen_pat=prbs_gen_dis(1'h0);
// [3:0]-hssi_tx_pcs_pma_interface_sq_wave_num=sq_wave_default(4'h4);
… localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_VALUE = "pldif_data_10bit"; localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_OFST = 8; localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_OFST = 7; localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_HIGH = 7; localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_SIZE = 1; localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_BITMASK =
32'h00000080; localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALMASK =
32'h00000000; localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALUE = 1'h0;
The SystemVerilog configuration files contain two parts. The first part consists of a data array of 26-bit hexadecimal values. The second part consists of parameter values. For the data array, each 26-bit hexadecimal value is associated with a comment that describes the various bit positions.
Table 263.
Mapping of SystemVerilog Configuration File Line
Bit Position
[25:16]
[15:8]
[7:0]
Description
DPRIO address. Refer to Intel Arria 10 Transceiver Register Map for details of the address.
The channel or PLL bit mask. The bit mask exposes the bits that are configured in either the Transceiver
Native PHY or the transmit PLL IP cores.
Feature bit values.
For example, a value of 26'h008FF04 represents an address of 0x008 and a bit mask of 0xFF. The four features that reside at address 0x008 are:
• hssi_tx_pcs_pma_interface_pldif_datawidth_mode
with a value of 1'h0
• hssi_tx_pcs_pma_interface_tx_pma_data_sel
with a value of 2'h0
• hssi_tx_pcs_pma_interface_prbs_gen_pat
with a value of 1'h0
• hssi_tx_pcs_pma_interface_sq_wave_num
with a value of 4'h4
Writing to bit 7 of address 0x008 changes the hssi_tx_pcs_pma_interface_pldif_datawidth_mode
feature.
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The MIF file and C header file are set up similarly to the SystemVerilog package file.
Multiple transceiver features may reside at the same address. Also, a single transceiver feature may span across multiple addresses.
Dynamic reconfiguration requires at least two configurations of the Transceiver Native
PHY IP core or PLL IP core. One configuration defines the base transceiver or PLL configuration and the other configurations define the modified or target configurations.
Use the IP Parameter Editor to create base and modified configurations of the
Transceiver Native PHY or PLL IP core, according to the following table.
Table 264.
Transceiver Native PHY or PLL IP Parameters (Base and Modified
Configurations)
Saved In Native PHY or PLL
Instance
Base Configuration
Modified
Configuration
Required Parameter Settings
• Click Interfaces
➤ Transceiver PHY ➤ Arria 10
Transceiver Native PHY for the Native PHY IP core. Or, select one of the supported transmit PLL IP cores under PLL. Enable all options required for the base configuration, such as data rate, PCS options, and PMA options.
• Enable all ports to be used by the modified configuration. For example, if the bitslip feature is not required in the base configuration, but required in modified configuration, then you must enable the tx_std_bitslipboundarysel
port. Reconfiguring between Standard PCS, Enhanced PCS, and PCS
Direct requires that you turn on Enable datapath
and interface reconfiguration. The Transceiver
configuration rules define the initial mode of the
PHY instance.
• On the Dynamic Reconfiguration tab, turn on
Enable dynamic reconfiguration and specify the
Configuration Options.
This flow requires that you turn on Configuration file option.
• Click Interfaces ➤ Transceiver PHY ➤ Arria 10
Transceiver Native PHY. Or, select one of the supported transmit PLL IP cores under PLL. Enable all options required for the modified configuration, such as data rate, PCS options, and PMA options.
• Enable all ports that are used by the modified configuration. Reconfiguring between Standard PCS,
Enhanced PCS, and PCS Direct requires Enable
datapath and interface reconfiguration be enabled. The Transceiver configuration rules define the mode of the PHY instance.
• On the Dynamic Reconfiguration tab, turn on
Enable dynamic reconfiguration and specify the same Configuration Options as the base instance.
• <Native PHY Base Instance Name>
/ reconfig/ altera_xcvr_native_a10_reconf ig_parameters.sv
contains all transceiver register addresses and their bit value for that transceiver configuration.
Or
• <PLL Base Instance Name>
/ reconfig/ altera_xcvr_<type>_pll_a10_re config_parameters.sv contains all PLL register addresses and their bit value for that PLL configuration.
• <Native PHY Modified Instance
Name>
/reconfig/ altera_xcvr_native_a10_reconf ig_parameters.sv
contains all transceiver register addresses and their bit value for that transceiver configuration.
Or
• <PLL Modified Instance Name>
/ reconfig/ altera_xcvr_<type>_pll_a10_re config_parameters.sv contains all PLL register addresses and their bit value for that PLL configuration.
Note: You can generate the base and modified configuration files in the same or different folders. If you use the same folder, each configuration name must be unique.
Intel recommends following the flow described in the Steps to Perform Dynamic
Reconfiguration section when performing dynamic reconfiguration of either the Native
PHY IP core or transmit PLL IP core.
Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
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•
Analog Parameter Settings on page 585
• Arria 10 Transceiver Register Map
6.4. Multiple Reconfiguration Profiles
You can optionally enable multiple configurations or profiles in the same Native PHY IP or ATX PLL IP core Parameter Editor (or both) for performing dynamic reconfiguration.
This allows the IP Parameter Editor to create, store, and analyze the parameter settings for multiple configurations or profiles.
When you enable the multiple reconfiguration profiles feature, the Native PHY IP Core,
ATX PLL IP core, or both can generate configuration files for all the profiles in the format desired (SystemVerilog package, MIF, or C header file). The configuration files are located in the
<IP instance name>\altera_xcvr_<IP type>_a10_<quartus version>\synth\reconfig
subfolder of the IP instance with the configuration profile index added to the filename. For example, the configuration file for Profile 0 is stored as
<filename_CFG0.sv>
. The Intel Quartus
Prime Timing Analyzer Timing Analyzer includes the necessary timing paths for all the configurations based on initial and target profiles. You can also generate reduced configuration files that contain only the attributes that differ between the multiple configured profiles. You can create up to eight reconfiguration profiles (Profile 0 to
Profile 7) at a time for each instance of the Native PHY/ATX PLL IP core.
You can optionally allow the Native PHY IP core to include PMA Analog settings in the configuration files by enabling the feature Include PMA Analog settings in
configuration files in the Dynamic Reconfiguration tab of the Transceiver Native
PHY IP Parameter Editor. This feature is disabled by default. Enabling this feature adds the PMA analog settings specified in the Analog PMA settings (Optional) tab of the
Native PHY IP Parameter Editor to the configuration files. Even with this option enabled in the Native PHY IP Parameter Editor, you must still specify QSF assignments for your analog settings when compiling your static design. The analog settings selected in the Native PHY IP Parameter Editor are used only to include these settings and their dependent settings in the selected configuration files. Refer to the Analog
Parameter Settings chapter for details about QSF assignments for the analog settings.
Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to perform dynamic reconfiguration using the IP guided reconfiguration flow with multiple reconfiguration profiles enabled.
The Quartus Prime Timing Analyzer only includes the necessary PCS timing paths for all the profiles. To perform a PMA reconfiguration such as TX PLL switching, CGB divider switching, or reference clock switching, you must use the flow described in
Steps to Perform Dynamic Reconfiguration. Refer to Timing Closure Recommendations for more details about enabling multiple profiles and running timing analyses.
You can use the multiple reconfiguration profiles feature without using the embedded reconfiguration streamer feature. When using the multiple reconfiguration profiles feature by itself, you must write the user logic to reconfigure all the entries that are different between the profiles while moving from one profile to another.
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Note: You must ensure that none of the profiles in the Native PHY IP and ATX PLL IP
Parameter Editor gives error messages, or else IP generation fails. The Native PHY IP core and ATX PLL IP only validates the current active profile dynamically. For example, if you store a profile with error messages in the Native PHY IP or ATX PLL IP Parameter
Editor and load another profile without any error messages, the error messages disappear in the IP. You are then allowed to generate the IP, but the generation fails.
Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
•
Timing Closure Recommendations on page 560
•
Analog Parameter Settings on page 585
6.5. Embedded Reconfiguration Streamer
You can optionally enable the embedded reconfiguration streamer in the Native PHY IP core, ATX PLL IP core, or both to automate the reconfiguration operation.
The embedded reconfiguration streamer is a feature block that can perform Avalon-
MM transactions to access channel/ATX PLL configuration registers in the transceiver.
When you enable the embedded streamer, the Native PHY/ATX PLL IP cores embed the reconfiguration profiles and reconfiguration control logic in the IP files.
For the ATX PLL IP, you can control the embedded streamer block through the reconfiguration interface. Control and status signals of the streamer block are memory mapped in the PLL’s soft control and status registers.
Table 265.
Control and Status Register Memory Map for Embedded Reconfiguration
Streamer in ATX PLL IP
Reconfigura tion
Address
(hex)
Reconfigura tion Bit
340 7
Attribute
Name cfg_load
Attribute
Description
Start streaming
Bit
Encoding
1'b1
Transceiver Block Description
Set to 1'b1 to initiate streaming, self-clearing bit
341
[2:0]
0 cfg_sel rcfg_busy
Configuratio n profile select
Busy Status bit
Direct mapped
1'b1
Embedded
Reconfiguration
Streamer
Embedded
Reconfiguration
Streamer
Embedded
Reconfiguration
Streamer
Binary encoding of the configuration Profile to stream
Bit is set to:
• 1'b1—streaming is in progress
• 1'b0—streaming is complete
Note: The soft control and status registers at x340 and x341 are enabled when you enable the embedded reconfiguration streamer in the ATX PLL IP core.
Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to perform dynamic reconfiguration using the IP guided reconfiguration flow with embedded streamer enabled. To perform a reference clock switching, use the reconfiguration flow for special cases described in Steps to Perform Dynamic
Reconfiguration.
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Note:
For the Native PHY IP, you can control the embedded streamer block through the reconfiguration interface. Control and status signals of the streamer block are memory mapped in the PHY’s soft control and status registers. These embedded reconfiguration control and status registers are replicated for each channel. You cannot merge reconfiguration interfaces across multiple IP cores when the embedded reconfiguration streamer is enabled because the embedded reconfiguration streamer makes use of soft logic for control and status registers.
You can optionally allow the Native PHY IP core to include PMA Analog settings in the configuration files by enabling the feature Include PMA Analog settings in
configuration files in the Dynamic Reconfirmation tab of the Transceiver Native
PHY IP Parameter Editor. This feature is disabled by default. Enabling this feature adds the PMA analog settings specified in the Analog PMA settings (Optional) tab of the
Native PHY IP Parameter Editor to the configuration files. Even with this option enabled in the Native PHY IP Parameter Editor, you must still specify QSF assignments for your analog settings when compiling your static design. The analog settings selected in the Native PHY IP Parameter Editor are used only to include these settings and their dependent settings in the selected configuration files. For details about QSF assignments for the analog settings, refer to the Analog Parameter Settings chapter.
For example, if the Native PHY IP core has four channels—logical channel 0 to logical channel 3—and you want to reconfigure logical channel 3 using the embedded reconfiguration streamer, you must write to the control register of logical channel 3 using the reconfiguration interface with the appropriate bit settings.
The soft control and status registers at x340 and x341 are enabled when you enable the embedded reconfiguration streamer in the Native PHY IP core.
Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to perform dynamic reconfiguration using the IP guided reconfiguration flow with embedded streamer enabled. To perform a PMA reconfiguration such as TX PLL switching, CGB divider switching, or reference clock switching, use the reconfiguration flow for special cases described in Steps to Perform Dynamic Reconfiguration.
Table 266.
Control and Status Register Memory Map for Embedded Reconfiguration
Streamer in Native PHY IP
Reconfigura tion
Address
(hex)
Reconfigura tion Bit
340 7
Attribute
Name cfg_load
Attribute
Description
Start streaming
Bit
Encoding
1'b1
Transceiver Block Description
Set to 1'b1 to initiate streaming, self-clearing bit
341
6
[2:0]
0 bcast_en cfg_sel rcfg_busy
Broadcast enable
Configuratio n profile select
Busy Status bit
1'b1
Direct mapped
1'b1
Embedded
Reconfiguration
Streamer
Embedded
Reconfiguration
Streamer
Embedded
Reconfiguration
Streamer
Embedded
Reconfiguration
Streamer
Set to 1'b1 to broadcast the same profile to all the channels
Binary encoding of the configuration Profile to stream
Bit is set to:
• 1'b1—streaming is in progress
• 1'b0—streaming is complete
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You can write to the address 0x340 at the same time to start the streaming, enable broadcasting, and select the profile to be streamed. Different requests to multiple channels can be made simultaneously by writing to the addresses of the desired channels through the user reconfiguration interface (shared or independent). The reconfig_waitrequest
signal remains asserted after the reconfiguration streaming is complete.
Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
•
Analog Parameter Settings on page 585
6.6. Arbitration
Figure 270. Arria 10 ATX PLL with Embedded Streamer
Arria 10 ATX PLL IP
User
Reconfiguration
Logic
Reconfiguration
Interface
Streamer
Arria 10 ATX PLL
To/From
PreSICE
Internal
Configuration
Bus
Avalon-MM
Interface
Configuration
Registers
ADME
Optional Reconfiguration Logic
(Capability, Control and Status)
Debug Fabric
Host Link
Intel IP User Logic
Connectivity to channel reconfiguration registers and optional soft registers
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Figure 271. Arria 10 Native PHY with Embedded Streamer
Arria 10 Native PHY
User
Reconfiguration
Logic
Reconfiguration
Interface
Streamer
Arria 10 Transceiver
To/From
PreSICE
Internal
Configuration
Bus
Avalon-MM
Interface
Channel
Configuration
Registers
Optional Reconfiguration Logic
(Capability, Control and Status,
PRBS Soft Accumulators
ADME
Debug Fabric
Host Link
Intel IP User Logic
Connectivity to channel reconfiguration registers and optional soft registers
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In Arria 10 devices, there are two levels of arbitration:
• Reconfiguration interface arbitration with the PreSICE calibration engine
When you have control over the internal configuration bus, refer to the second level of arbitration: Arbitration between multiple masters within the Native
PHY/PLL IPs.
For more details about arbitration between the reconfiguration interface and
PreSICE, refer to the Calibration chapter.
• Arbitration between multiple masters within the Native PHY/PLL IPs
Below are the feature blocks that can access the programmable registers:
— Embedded reconfiguration streamer (Available in the Native PHY and ATX PLL
IPs only)
— ADME
— User reconfiguration logic connected to the reconfiguration interface
When the internal configuration bus is not owned by the PreSICE, which feature block has access depends on which of them are enabled.
These feature blocks arbitrate for control over the programmable space of each transceiver channel/PLL. Each of these feature blocks can request access to the programmable registers of a channel/PLL by performing a read or write operation to that channel/PLL. For any of these feature blocks to be used, you must first have control over the internal configuration bus. You must ensure that these feature blocks have completed all the read/write operations before you return the bus access to PreSICE.
The embedded reconfiguration streamer has the highest priority, followed by the reconfiguration interface, followed by the ADME. When two feature blocks are trying to access the same transceiver channel on the same clock cycle, the feature block with the highest priority is given access. The only exception is when a lowerpriority feature block is in the middle of a read/write operation and a higherpriority feature block tries to access the same channel. In this case, the higher priority feature block is made to wait until the lower priority feature block has finished the read/write operation.
Note: When you enable ADME in your design, you must
— connect an Avalon-MM master to the reconfiguration interface
— OR connect the reconfig_clock
, reconfig_reset signals and ground the reconfig_write
, reconfig_read
, reconfig_address and reconfig_writedata
signals of the reconfiguration interface. If the reconfiguration interface signals are not connected appropriately, there is no clock or reset for the ADME, and the ADME does not function as expected.
Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
•
on page 567
• Arria 10 Transceiver Register Map
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6.7. Recommendations for Dynamic Reconfiguration
Recommendations for TX PLLs
Intel recommends you control in the following cases: pll_powerdown
for the fPLL through the soft registers
• Reconfiguring fPLL from integer mode to fractional mode
• Reconfiguring fPLL within fractional mode from one rate to another
For all other reconfiguration scenarios, do not hold the PLL in reset before and during reconfiguration.
When reconfiguring across data rates or protocol modes, Intel recommends that you hold the channel transmitter (analog and digital) associated with the PLL in reset during reconfiguration and recalibration of the PLL.You can use the tx_digitalreset
, rx_digitalreset
, tx_analogreset
, and rx_analogreset ports or use the channel soft register for digital and analog resets. For details about placing the channel in analog reset, refer to the "Model 1: Default Model" and "Model
2: Acknowledgment Model" sections of the Resetting Transceiver Channels chapter.
Note: If you need to reconfigure the ATX PLL, use TX PLL switching mode or use local clock divider to achieve new data rate to avoid recalibrating the ATX PLL. Refer to "ATX PLL
Usage Guideline" in the "PLLs and Clock Networks" chapter for more details.
Recommendations for Channels
• When reconfiguring across data rates or protocol modes, Intel recommends that you hold the channel transmitter (analog and digital) in reset during reconfiguration and recalibration of the channel transmitter. You can use the tx_digitalreset
, rx_digitalreset
, tx_analogreset
, and rx_analogreset
ports or use the channel soft register for digital and analog resets. For details about placing the channel in analog reset, refer to the "Model 1:
Default Model" and "Model 2: Acknowledgment Model" sections of the Resetting
Transceiver Channels chapter.
• When reconfiguring across data rates or protocol modes, Intel recommends that you hold the channel receiver (analog and digital) in reset during reconfiguration and recalibration of the channel receiver. You can use the tx_digitalreset
, rx_digitalreset
, tx_analogreset
, and rx_analogreset
ports or use the channel soft register for digital and analog resets. For details about placing the channel in analog reset, refer to the "Model 1: Default Model" and "Model 2:
Acknowledgment Model" sections of the Resetting Transceiver Channels chapter.
• When performing reconfiguration on channels not involving data rate or protocol mode change, Intel recommends that you hold the channel transmitter (digital only) in reset during reconfiguration.
• When performing reconfiguration on channels not involving data rate or protocol mode change, Intel recommends that you hold the channel receiver (digital only) in reset during reconfiguration.
Refer to the Arria 10 Transceiver Register Map for detailed information about the soft registers for PLL powerdown.
Related Information
•
Model 1: Default Model on page 418
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•
Model 2: Acknowledgment Model on page 427
•
PLLs and Clock Networks on page 347
• Arria 10 Transceiver Register Map
6.8. Steps to Perform Dynamic Reconfiguration
You can dynamically reconfigure blocks in the transceiver channel or PLL through the reconfiguration interface.
The following procedure shows the steps required to reconfigure the channel and PLL blocks.
1. Enable dynamic reconfiguration in the IP.
2. Enable the desired configuration file formats in the IP.
3. Enable the desired dynamic reconfiguration features (such as multiple reconfiguration profiles, including PMA analog settings in configuration files) or feature blocks (such as embedded reconfiguration streamer and ADME).
4. If you are using:
• Direct reconfiguration flow—Refer to the register map for feature address and valid value of write data for the feature.
• IP guided reconfiguration flow—Note the settings of the base configuration and generate the corresponding configuration files. Note the settings of the modified configuration and generate the corresponding configuration files. Find out the differences in settings between the base and modified configurations.
• IP guided reconfiguration flow using multiple profiles—Create and store the parameter settings between the various configurations or profiles using configuration files. Find out the differences in settings between the various configurations or profiles using configuration files.
• IP guided reconfiguration flow using the embedded streamer—Refer to the control and status register map of the embedded reconfiguration streamer to stream the desired profile settings.
• Reconfiguration flow for special cases—Refer to the lookup registers to be accessed for each special case, such as TX PLL switching, TX PLL reference clock switching, and RX CDR reference clock switching.
5. Place the channels in digital reset either simultaneously or one after another. For details about placing the channel in reset, refer to "Model 1: Default Model" and
"Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter.
If you are reconfiguring:
• PLLs—Place the channel transmitter associated with the PLL in reset (digital).
• TX simplex channels—Place the TX channels being reconfigured in reset
(digital).
• RX simplex channels—Place the RX channels being reconfigured in reset
(digital).
• Duplex channels—Place the channel TX and RX being reconfigured in reset
(digital).
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6. If you are reconfiguring across data rates or protocol modes or enabling/disabling
PRBS, place the channels in analog reset. For details about placing the channel in analog reset, refer to "Model 1: Default Model" and "Model 2: Acknowledgment
Model" in the Resetting Transceiver Channels chapter.
If you are reconfiguring:
• PLLs—Place the channel transmitter associated with the PLL in reset (analog).
• TX simplex channels—Place the TX channels being reconfigured in reset
(analog).
• RX simplex channels—Place the RX channels being reconfigured in reset
(analog).
• Duplex channels—Place the channel TX and RX being reconfigured in reset
(analog).
7. Check for internal configuration bus arbitration. If PreSICE has control, request bus arbitration, otherwise go to the next step. For more details, refer to the
"Arbitration" section.
8. Perform the necessary reconfiguration using the flow described in the following sections:
• Direct Reconfiguration Flow
• Native PHY or PLL IP Guided Reconfiguration Flow
• Reconfiguration Flow for Special Cases
9. Perform all necessary reconfiguration. If reconfiguration involved data rate or protocol mode changes, then you may have to reconfigure the PMA analog parameters of the channels. Refer to the Changing PMA Analog Parameters section for more details.
10. If reconfiguration involved data rate or protocol mode change, then request recalibration and wait for the calibration to complete. Calibration is complete when
*_cal_busy
is deasserted. For more details about calibration registers and the steps to perform recalibration, refer to the Calibration chapter.
If you reconfigured:
• PLL for data rate change—you must recalibrate the PLL and the channel TX.
• TX simplex channel for data rate change—you must recalibrate the channel
TX.
• RX simplex channel for data rate change—you must recalibrate the channel
RX.
• Duplex channel for data rate change—you must recalibrate the channel TX and
RX.
11. Release the channel analog resets. For details about placing the channel in reset, refer to "Model 1: Default Model" and "Model 2: Acknowledgment Model" in the
Resetting Transceiver Channels chapter.
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If you reconfigured:
• PLLs—Release the reset (analog) of the channel transmitters associated with the PLL reconfigured.
• TX simplex channels—Release the reset (analog) of the TX channels reconfigured.
• RX simplex channels—Release the reset (analog) of the RX channels reconfigured.
• Duplex channels—Release the reset (analog) of the TX and RX channels reconfigured.
12. Release the channel digital resets either simultaneously or one after another. For details about releasing the channel resets, refer to "Model 1: Default Model" and
"Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter.
(The figures in these sections are for analog resets, but they also contain timing information about digital resets.)
If you reconfigured:
• PLLs—Release the reset (digital) of the channel transmitters associated with the PLL reconfigured.
• TX simplex channels—Release the reset (digital) of the TX channels reconfigured.
• RX simplex channels—Release the reset (digital) of the RX channels reconfigured.
• Duplex channels—Release the reset (digital) of the TX and RX channels reconfigured.
You cannot merge multiple reconfiguration interfaces across multiple IP blocks
(merging independent instances of simplex TX/RX into the same physical location or merging separate CMU PLL and TX channel into the same physical location) when you use the optional reconfiguration logic soft control registers.
Related Information
•
Resetting Transceiver Channels
on page 416
•
Model 1: Default Model on page 418
•
Model 2: Acknowledgment Model on page 427
•
Direct Reconfiguration Flow on page 519
•
Native PHY IP or PLL IP Core Guided Reconfiguration Flow
on page 519
•
Reconfiguration Flow for Special Cases
on page 521
•
Changing PMA Analog Parameters
on page 527
•
on page 567
•
on page 512
• Arria 10 Transceiver Register Map
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6.9. Direct Reconfiguration Flow
Use this flow to perform dynamic reconfiguration when you know exactly which parameter and value to change for the transceiver channel or PLL. You can use this flow to change the PMA analog settings, enable/disable PRBS generator, and checker hard blocks of the transceiver channel.
To perform dynamic reconfiguration using direct reconfiguration flow:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the desired feature address.
3. Perform a read-modify-write to feature address with a valid value.
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
•
Changing PMA Analog Parameters
on page 527
•
Using Data Pattern Generators and Checkers
on page 550
•
Resetting Transceiver Channels
on page 416
•
on page 567
• Arria 10 Transceiver Register Map
6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow
Use the Native PHY IP core or PLL IP core guided reconfiguration flow to perform dynamic reconfiguration when you need to change multiple parameters or parameters in multiple addresses for the transceiver channel or PLL. You can use this flow to change data rates, change clock divider values, or switch from one PCS datapath to another. You must generate the required configuration files for the base and modified
Transceiver Native PHY IP core or PLL IP core configurations.
The configuration files contain addresses and bit values of the corresponding configuration. Compare the differences between the base and modified configuration files. The differences between these files indicate the addresses and bit values that must change to switch from one configuration to another. Perform read-modify-writes for the bit values that are different from the base configuration to obtain the modified configuration.
To perform dynamic reconfiguration using the IP Guided Reconfiguration Flow:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to all addresses and bit values that are different from the base configuration.
3. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
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Note: If reconfiguration involved data rate or protocol mode changes, you may need to reconfigure the PMA analog parameters of the channels. Refer to the Changing PMA
Analog Parameters section for more details.
The bit values that must be changed to obtain the new configuration may span across multiple addresses, such as when switching between Standard, Enhanced, and PCS
Direct data paths. It is difficult to manually compare these values for the base and modified configurations and then build logic to stream the different values in the modified configuration. You can use the multiple profiles feature of the Native PHY/ATX
PLL IP cores to store the parameter settings (MIF configuration file) to memory. With the configuration content saved, you can read from the memory and write the content to the target channel for reconfiguration. Optionally, you can also use the embedded reconfiguration streamer feature of the Native PHY/ATX PLL IP cores, which includes the logic to store the individual profile information and logic to perform streaming.
Using the embedded reconfiguration streamer, you can reduce the number of readmodify-write operations to obtain the modified configuration.
To perform dynamic reconfiguration using the Embedded Reconfiguration Streamer:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address x340 with the desired profile select, broadcast bit (applicable for Native PHY only), and configuration load bit set accordingly. For example, to stream profile 1 to a channel, perform a read-modifywrite to bits x340[2:0] with 3’b001, bit x340[6] with 1’b0 to disable broadcasting, and bit x340[7] with 1’b1 to initiate streaming.
3. Poll the streamer busy bit at address x341 (x341[0]) at regular intervals. When the busy bit is 1’b0, the reconfiguration is complete.
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note: If reconfiguration involved data rate or protocol mode changes, you may need to reconfigure the PMA analog parameters of the channels. Refer to the Changing PMA
Analog Parameters section for more details.
Figure 272. Timing Diagram for Embedded Streamer Reconfiguration reconfig_clk reconfig_address reconfig_read reconfig_readdata reconfig_waitrequest reconfig_write reconfig_writedata xxx xxx
0x00h
0x340h
0x00h
0x81h
0x341h
0x01h
0x00h
0x01h 0x01h
0x000h
0x00h
0x00h
Streaming Completes;
Streaming Busy Bit Is Low
User Requests
Streaming
User Polls
Streaming
Busy Bit
Streaming in
Progress; Streaming
Busy Bit Is High
Related Information
•
on page 512
•
Changing PMA Analog Parameters
on page 527
•
Steps to Perform Dynamic Reconfiguration
on page 516
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Resetting Transceiver Channels
on page 416
•
on page 567
6.11. Reconfiguration Flow for Special Cases
Dynamic reconfiguration can be performed on logical operations such as switching between multiple transmit PLLs or multiple reference clocks. In these cases, configuration files alone cannot be used. Configuration files are generated during IP generation and do not contain information on the placement of PLLs or reference clocks.
To perform dynamic reconfiguration on logical operations, you must use lookup registers that contain information about logical index to physical index mapping.
Lookup registers are read-only registers. Use these lookup registers to perform a read-modify-write to the selection MUXes to switch between PLLs or reference clocks.
To perform dynamic reconfiguration using reconfiguration flow for special cases:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the desired lookup register. Refer to the Switching Transmitter PLL and
Switching Reference Clocks sections for information about lookup registers.
3. Perform Logical Encoding (only required for Transmitter PLL switching).
4. Perform read-modify-write to the required feature address with the desired/ encoded value.
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
•
on page 521
•
on page 523
•
Resetting Transceiver Channels
on page 416
•
on page 567
6.11.1. Switching Transmitter PLL
Dynamically switching data rates increases system flexibility to support multiple protocols. You can change the transceiver channel data rate by switching from one transmit PLL to another. To switch between transmit PLLs, you must reconfigure the local CGB MUX select lines of the channel by performing a channel reconfiguration.
You can clock transceiver channels with up to four different transmitter PLLs. You can use the reconfiguration interface on the Native PHY IP core to specify which PLL drives the transceiver channel. The PLL switching method is the same, regardless of the number of transmitter PLLs involved.
Before initiating the PLL switch procedure, ensure that your Transceiver Native PHY instance defines more than one transmitter PLL input. Specify the Number of TX PLL
clock inputs per channel parameter on the TX PMA tab during Transceiver Native
PHY parameterization.
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The following table shows the addresses and bits for transmitter PLL switching. The number of exposed tx_serial_clk
bits varies according to the number of transmitter PLLs you specify. Use the Native PHY reconfiguration interface for this operation.
Table 267.
Register Map for Switching Transmitter PLLs
Transceiver Native PHY
Port
Description tx_serial_clk0 tx_serial_clk1 tx_serial_clk2 tx_serial_clk3
N/A
Address Bits
Represents logical
PLL0
. Lookup register x117[3:0] stores the mapping from logical
PLL.
PLL0
to the physical
Represents logical
PLL1
. Lookup register x117[7:4] stores the mapping from logical
PLL.
PLL1
to the physical
Represents logical stores the mapping from logical
PLL.
PLL2
. Lookup register x118[3:0]
PLL2
to the physical
Represents logical
PLL3
. Lookup register x118[7:4] stores the mapping from logical
PLL.
PLL3
to the physical
PLL selection MUX
0x117 (Lookup Register) [3:0]
0x117 (Lookup Register) [7:4]
0x118 (Lookup Register) [3:0]
0x118 (Lookup Register) [7:4]
0x111 [7:0]
When performing a PLL switch, you must specify the lookup register address and bit values you want to switch to. The following procedure describes selection of a specific transmitter PLL when more than one PLL is connected to a channel. To change the data rate of the CDR, follow the detailed steps for reconfiguring channel and PLL blocks. After determining the logical PLL to switch to, follow this procedure to switch to the desired transmitter PLL:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the appropriate lookup register address (refer to
522) and save the required 4-bit pattern. For example, switching to logical
PLL1 requires saving bits [7:4] of address 0x117.
3. Encode the 4-bit value read in the previous step into an 8-bit value according to the following table:
Table 268.
Logical PLL Encoding
4-bit Logical PLL Bits
[3..0]
[7..4]
8-bit Mapping to Address 0x111
{~logical_PLL_offset_readdata[3],
logical_PLL_offset_readdata[1:0],logical_PLL_offset_readdata[3],
logical_PLL_offset_readdata[3:0] }
{~logical_PLL_offset_readdata[7],
logical_PLL_offset_readdata[5:4],logical_PLL_offset_readdata[7],
logical_PLL_offset_readdata[7:4] }
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Note: For example, if reconfiguring to logical
PLL1
then bits [7:4] are encoded to an 8-bit value {~bit[7], bit[5:4], bit[7], bit[7:4]}.
4. Perform a read-modify-write to bits[7:0] of address 0x111 using the encoded 8-bit value.
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
Steps to Perform Dynamic Reconfiguration
on page 516
6.11.2. Switching Reference Clocks
You can dynamically switch the input clock source for the ATX PLL, the fPLL, the CDR, and the CMU.
6.11.2.1. ATX Reference Clock Switching
You can use the reconfiguration interface on the ATX PLL instance to specify which reference clock source drives the ATX PLL. The ATX PLL supports clocking up to five different reference clock sources. The flow to select between the different reference clock sources is independent of the number of transmitter PLLs specified in the
Parameter Editor.
Before initiating a reference clock switch, ensure that your ATX PLL instance defines more than one reference clock source. Specify the Number of PLL reference clocks parameter on the PLL tab during ATX PLL parameterization.
The following table shows the addresses and bits for switching between ATX PLL reference clock inputs. The number of exposed pll_refclk
ports varies according to the number of reference clocks you specify. Use the ATX PLL reconfiguration interface for this operation.
Table 269.
Register Map for Switching ATX PLL Reference Clock Inputs
Transceiver ATX PLL
Port
Description Address pll_refclk0 pll_refclk1 pll_refclk2 pll_refclk3 pll_refclk4
N/A
Represents logical refclk0
. Lookup register x113[7:0]
stores the mapping from logical refclk0
to the physical refclk.
Represents logical refclk1
. Lookup register x114[7:0]
stores the mapping from logical refclk1
to the physical refclk.
Represents logical refclk2
. Lookup register x115[7:0]
stores the mapping from logical refclk2
to the physical refclk.
Represents logical refclk3
. Lookup register x116[7:0]
stores the mapping from logical refclk3
to the physical refclk.
Represents logical refclk4
. Lookup register x117[7:0]
stores the mapping from logical refclk4
to the physical refclk.
ATX refclk selection MUX.
0x113 (Lookup Register) [7:0]
0x114 (Lookup Register) [7:0]
0x115 (Lookup Register) [7:0]
0x116 (Lookup Register) [7:0]
0x117 (Lookup Register) [7:0]
0x112
Bits
[7:0]
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When performing a reference clock switch, you must specify the lookup register address and respective bits of the replacement clock. After determining the ATX PLL, follow this procedure to switch to the selected reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register address and save the required 8-bit pattern. For example, switching to logical refclk2
requires use of bits
[7:0]
at address
0x115
.
3. Perform a read-modify-write to bits obtained from the lookup register.
[7:0]
at address
0x112
using the 8-bit value
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
Steps to Perform Dynamic Reconfiguration
on page 516
6.11.2.2. fPLL Reference Clock Switching
You can use the reconfiguration interface on the fPLL instance to specify which reference clock source drives the fPLL. The fPLL supports clocking by up to five different reference clock sources. The flow to select between the different reference clock sources is independent of the number of transmitter PLLs specified in the reconfiguration interface.
Before initiating a reference clock switch, ensure that your fPLL instance defines more than one reference clock source. Specify the Number of PLL reference clocks parameter on the PLL tab during fPLL parameterization.
The following table shows the addresses and bits for switching between fPLL reference clock inputs. The number of exposed pll_refclk
ports varies according to the number of reference clocks you specify. Use the fPLL reconfiguration interface for this operation.
Table 270.
Register Map for Switching fPLL Reference Clock Inputs
Transceiver fPLL Port pll_refclk0 pll_refclk1 pll_refclk2 pll_refclk3 pll_refclk4
Description
Represents logical register refclk0
for
MUX_0
. Lookup x117[7:0]
stores the mapping from logical refclk0
to the physical refclk for MUX_0.
Represents logical refclk1
for
MUX_0
. Lookup register x118[7:0]
stores the mapping from logical refclk1
to the physical refclk for MUX_0.
Represents logical refclk2
for
MUX_0
. Lookup register x119[7:0]
stores the mapping from logical refclk2
to the physical refclk for MUX_0.
Represents logical refclk3
for
MUX_0
. Lookup register x11A[7:0]
stores the mapping from logical refclk3
to the physical refclk for MUX_0.
Represents logical refclk4
for
MUX_0
. Lookup register x11B[7:0]
stores the mapping from logical refclk4
to the physical refclk for MUX_0.
Address Bits
0x117 (Lookup Register) [7:0]
0x118 (Lookup Register) [7:0]
0x119 (Lookup Register) [7:0]
0x11A (Lookup Register) [7:0]
0x11B (Lookup Register) [7:0] continued...
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Transceiver fPLL Port
N/A pll_refclk0 pll_refclk1 pll_refclk2 pll_refclk3 pll_refclk4
N/A
Description fPLL refclk selection
MUX_0
.
Represents logical refclk0
for
MUX_1
. Lookup register x11D[7:0]
stores the mapping from logical refclk0
to the physical refclk for MUX_1.
Represents logical refclk1
for
MUX_1
. Lookup register x11E[7:0]
stores the mapping from logical refclk1
to the physical refclk for MUX_1.
Represents logical refclk2
for
MUX_1
. Lookup register x11F[7:0]
stores the mapping from logical refclk2
to the physical refclk for MUX_1.
Represents logical refclk3
for
MUX_1
. Lookup register x120[7:0]
stores the mapping from logical refclk3
to the physical refclk for MUX_1.
Represents logical refclk4
for
MUX_1
. Lookup register x121[7:0]
stores the mapping from logical refclk4
to the physical refclk for MUX_1.
fPLL refclk selection
MUX_1
.
0x114
Address Bits
[7:0]
0x11D (Lookup Register) [7:0]
0x11E (Lookup Register) [7:0]
0x11F (Lookup Register) [7:0]
0x120 (Lookup Register) [7:0]
0x121 (Lookup Register) [7:0]
0x11C [7:0]
Specify the logical reference clock and respective address and bits of the replacement clock when performing a reference clock switch. Follow this procedure to switch to the selected reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register for MUX 0 and save the required 8-bit pattern. For example, switching to logical refclk3
requires use of bits[7:0] at lookup register
0x11A.
3. Perform a read-modify-write to bits [7:0] at address 0x114 using the 8-bit value obtained from the lookup register.
4. Read from the lookup register for MUX 1 and save the required 8-bit pattern. For example, switching to logical
0x120.
refclk3
requires use of bits[7:0] at lookup register
5. Perform a read-modify-write to bits [7:0] at address 0x11C using the 8-bit value obtained from the lookup register.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Example 1:
Switching from pll_refclk0
to pll_refclk1 both fPLL refclk selection MUX_0 and MUX_1:
, you need to read-modify-write to
1. Modify MUX_0 value:
• Read from 0x118[7:0]
• Write the value from 0x118 [7:0] to 0x114 [7:0]
2. Modify MUX_1 value:
• Read from 0x11E [7:0]
• Write the value read from 0x11E [7:0] to 0x11C [7:0]
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Example 2:
Switching from pll_refclk2
to pll_refclk3
, you need to read-modify-write to both fPLL refclk selection MUX_0 and MUX_1:
1. Modify MUX_0 value:
• Read from 0x11A [7:0]
• Write the value read from 0x11A [7:0] to 0x114 [7:0]
2. Modify MUX_1 value:
• Read from 0x120 [7:0]
• Write the value read from 0x120 [7:0] to 0x11C [7:0]
Related Information
Steps to Perform Dynamic Reconfiguration
on page 516
6.11.2.3. CDR and CMU Reference Clock Switching
You can use the reconfiguration interface to specify which reference clock source drives the CDR and CMU PLL. The CDR and CMU support clocking by up to five different reference clock sources.
Before initiating a reference clock switch, ensure that your CDR and CMU defines more than one reference clock source. For the CDR, specify the parameter on the RX PMA tab during the Native PHY IP parameterization. For the CMU, specify the Number of
PLL reference clocks under the PLL tab when parameterizing the CMU PLL.
The following table describes the addresses and bits for switching CDR and CMU reference clock inputs. The number of exposed rx_cdr_refclk
(CDR) or pll_refclk
(CMU) varies according to the number of reference clocks you specify.
Use the CMU reconfiguration interface for switching the CMU reference clock.
Table 271.
Register Map for Switching CDR Reference Clock Inputs
Native PHY Port cdr_refclk0 cdr_refclk1 cdr_refclk2
Description
Represents logical refclk0
.
Lookup register x16A[7:0] stores the mapping from logical refclk0
to the physical refclk.
Represents logical refclk1
.
Lookup register x16B[7:0] stores the mapping from logical refclk1
to the physical refclk.
Represents logical refclk2
.
Lookup register x16C[7:0] stores the mapping from logical refclk2
to the physical refclk.
Address
0x16A (Lookup Register)
0x16B (Lookup Register)
0x16C (Lookup Register)
[7:0]
Bits
[7:0]
[7:0] continued...
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Native PHY Port cdr_refclk3 cdr_refclk4
N/A
Description
Represents logical refclk3
.
Lookup register x16D[7:0] stores the mapping from logical refclk3
to the physical refclk.
Represents logical refclk4
.
Lookup register x16E[7:0] stores the mapping from logical refclk4
to the physical refclk.
CDR refclk selection MUX.
Address
0x16D (Lookup Register)
0x16E (Lookup Register)
0x141
[7:0]
Bits
[7:0]
[7:0]
When performing a reference clock switch, note the logical reference clock to switch to and the respective address and bits. After determining the logical reference clock, follow this procedure to switch to the selected CDR reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register and save the required 8-bit pattern. For example, switching to logical refclk3
requires saving bits
[7:0]
at address
0x16D
.
3. Perform a read-modify-write to bits
[7:0]
at address
0x141
using the 8-bit value obtained from the lookup register.
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
Steps to Perform Dynamic Reconfiguration
on page 516
6.12. Changing PMA Analog Parameters
You can use the reconfiguration interface on the Transceiver Native PHY IP core to change the value of PMA analog features.
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The PMA analog settings can be broadly divided into the following groups:
• PMA analog settings that are channel or system dependent:
— These settings may vary from channel to channel based on channel loss or other factors
— You can set these PMA analog settings based on IBIS-AMI or Advanced Link
Analyzer simulations
— You can set these PMA analog settings using QSF assignments or by performing RMWs to the respective registers
— These PMA analog settings are not included in the configuration files by default. To include these PMA analog settings in the configuration files, you must enable the Include PMA Analog settings in configuration files option in the Dynamic Reconfirmation tab of the Transceiver Native PHY IP
Parameter Editor. Enabling this feature adds the PMA analog settings specified in the Analog PMA settings (Optional) tab of the Native PHY IP Parameter
Editor to the configuration files. Even with this option enabled in the Native
PHY IP Parameter Editor, you must still specify QSF assignments for your analog settings when compiling your static design. The analog settings selected in the Native PHY IP Parameter Editor are used only to include these settings and their dependent settings in the selected configuration files. For details about optional analog settings, refer to the "Analog PMA Settings
(Optional) for Dynamic Reconfiguration" table in the Ports and Parameters section. For details about QSF assignments for the analog settings, refer to the
Analog Parameter Settings chapter.
— If you do not enable the Include PMA Analog settings in configuration
files option, then you can change these analog settings by performing RMWs using direct reconfiguration flow
Table 272.
PMA Analog Settings that are Channel or System Dependent
PMA Analog Feature
VOD
Pre-emphasis
CTLE
VGA
Fitter Report Name vod_output_swing_ctrl pre_emp_sign_1st_post_tap pre_emp_sign_2nd_post_tap pre_emp_sign_pre_tap_1t pre_emp_sign_pre_tap_2t pre_emp_switching_ctrl_1st_post_tap pre_emp_switching_ctrl_2nd_post_tap pre_emp_switching_ctrl_pre_tap_1t pre_emp_switching_ctrl_pre_tap_2t eq_dc_gain_trim one_stage_enable eq_bw_sel adp_ctle_eqz_1s_sel adp_ctle_acgain_4s adp_vga_sel
Arria 10 Transceiver Register Map Attribute
Name vod_output_swing_ctrl pre_emp_sign_1st_post_tap pre_emp_sign_2nd_post_tap pre_emp_sign_pre_tap_1t pre_emp_sign_pre_tap_2t pre_emp_switching_ctrl_1st_post_tap pre_emp_switching_ctrl_2nd_post_tap pre_emp_switching_ctrl_pre_tap_1t pre_emp_switching_ctrl_pre_tap_2t eq_dc_gain_trim one_stage_enable eq_bw_sel adp_ctle_eqz_1s_sel adp_ctle_acgain_4s adp_vga_sel
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• PMA analog settings that are device dependent
— These settings may vary for each transceiver protocol-type and data rate in your design
— These settings are not included in the configuration files by default. To include these analog settings in the configuration files, you must enable the feature
Include PMA Analog settings in configuration files under the Dynamic
Reconfiguration tab of the Transceiver Native PHY IP Parameter Editor.
Enabling this feature adds the PMA analog settings specified in the Analog
PMA settings (Optional) tab of Native PHY IP Parameter Editor to the configuration files. Even with this option enabled in the Native PHY IP
Parameter Editor, you must still specify QSF assignments for your analog settings when compiling your static design. The analog settings selected in the
Native PHY IP Parameter Editor are used only to include these settings and their dependent settings in the selected configuration files. For details about optional analog settings, refer to the "Analog PMA Settings (Optional) for
Dynamic Reconfiguration" table in the Ports and Parameters section. For details about QSF assignments for the analog settings, refer to the Analog
Parameter Settings chapter.
— If the Include PMA analog settings in configuration files option is disabled, then you must set these PMA analog settings. In addition to streaming the configuration files generated by the Native PHY IP Parameter
Editor, you must perform RMWs using Direct Reconfiguration Flow to change these PMA analog settings through the Avalon-MM reconfiguration interface
— The values of all these PMA analog settings that change when changing protocol-type or data rates must be obtained from the respective Fitter reports by performing full compilation for each of the base and target configurations
— For example, when changing the data rate from A to B, you must first perform a full compile with the data rate configured to A and note the PMA analog settings from the fitter report. Next, you must perform a full compile with data rate configured to B and note the PMA analog settings from the fitter report. If any of these PMA analog settings changed values between the two compiles, you must perform RMWs with the target values to the respective registers after streaming the configuration files.
— Examples: Slew rate, Equalizer Bandwidth, Compensation Enable
Table 273.
PMA Analog Settings that are Device Dependent
PMA Analog Feature
Slew Rate (TX Buffer)
Equalizer Bandwidth
(RX Buffer)
Compensation Enable
(TX Buffer)
One Stage Enable (RX
CTLE)
Fitter Report Name
Slew_rate_ctrl
Eq_bw_sel
Compensation_en
One_stage_enable
Arria 10 Transceiver Register Map Attribute
Name
Slew_rate_ctrl
Eq_bw_sel
Compensation_en
One_stage_enable
Related Information
•
on page 535
•
Analog Parameter Settings on page 585
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6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the PMA analog feature address of the channel you want to change. For example, to change pre-emphasis 1st post-tap, read and store the value of address 0x105.
3. Select a valid value for the feature according to the Arria 10 register map. For example, a valid setting for pre-emphasis 1st post-tap has a bit encoding of
5'b00001.
4. Perform a read-modify-write to the address of the PMA analog feature using the valid value. For example, to change the pre-emphasis 1st post-tap, write 5'b00001 to address 0x105.
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Table 274.
Register Map for PMA Analog Feature
PMA Analog Feature
Pre-emphasis 1st post-tap
Pre-emphasis 1st post-tap polarity
Address
0x105
0x105
Pre-emphasis 2nd post-tap
Pre-emphasis 2nd post-tap polarity
Pre-emphasis 1st pre-tap
Pre-emphasis 1st pre-tap polarity
Pre-emphasis 2nd pre-tap
Pre-emphasis 2nd pre-tap polarity
Differential output voltage (V
OD
)
0x106
0x106
0x107
0x107
0x108
0x108
0x109
[4:0]
[6]
Bit
[3:0]
[5]
[4:0]
[5]
[2:0]
[4]
[4:0]
Values
5'b00000 - 5'b11001
1'b0 = positive
1'b1 = negative
4'b0000 - 4'b1100
1'b0 = positive
1'b1 = negative
5'b00000 - 5'b10000
1'b0 = positive
1'b1 = negative
3'b000 - 3'b111
1'b0 = positive
1'b1 = negative
5'b00000 - 5'b11111
The PMA analog settings are governed by a set of rules. Not all combinations of V
OD and pre-emphasis are valid. Please refer to Arria 10 Pre-Emphasis and Output Swing
Settings for current valid settings. Also, refer to "Analog Parameter Settings" and setup guidelines on post_tap polarity settings.
Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
•
Arria 10 PMA Architecture on page 447
• Arria 10 Pre-Emphasis and Output Swing Settings
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6.12.2. Changing CTLE Settings in Manual Mode Using Direct
Reconfiguration Flow
You can use the reconfiguration interface on the Transceiver Native PHY IP core to change the CTLE settings in manual mode.
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the CTLE feature address of the channel you want to change. For example, to change CTLE AC gain in high gain mode, read and store the value of address 0x167[5:1].
3. Select a valid value for the feature according to the Arria 10 register map. For example, a valid setting for CTLE AC Gain has a bit encoding of 5’b00000.
4. Perform a read-modify-write to the address of the CTLE feature using the valid value. For example, to change the CTLE AC gain in high gain mode, write
5’b00000 to address 0x167[5:1].
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Table 275.
Register Map for CTLE Settings
CTLE Feature
One Stage Enable
DC Gain
CTLE AC Gain One
Stage
Address
0x11B
0x11C,
0x11A
0x166
[3]
Bits Values
1’b0- Selects Four Stage
1’b1- Selects One Stage
[3:0], [7:0] 12’b000000000000
12’b111000000000
12’b111111000000
12’b111111111000
12’b111111111111
[4:1] 4’b0000- 4’b1111
CTLE AC Gain Four
Stage
VGA SEL
0x167
0x160
[5:1]
[3:1]
5’b00000 – 5’b11100
3’b000 – 3’b111
Description
Selects the equalizer path as either
One Stage or Four Stage mode.
Sets the DC gain values. This register can only be controlled when in Four stage mode.
Sets the AC gain value when one stage mode (High data rate mode) is selected. A higher value means higher peaking by suppressing DC gain.
Sets the AC gain value when four stage mode (High gain mode) is selected.
Sets the VGA Gain value
Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
•
Arria 10 PMA Architecture on page 447
6.12.3. CTLE Settings in Triggered Adaptation Mode
CTLE triggered adaptation mode should only be used for PCIe Gen3. Refer to the section "How to enable CTLE and DFE" in Chapter Arria 10 Transceiver PHY
Architecture of Arria 10 Transceiver PHY User Guide for details on using the triggered adaptation mode of CTLE.
User need to change the register bit settings accordingly when moving from PCIe
Gen1/2 (CTLE manual, DFE disabled) to PCIe Gen3 (CTLE triggered, DFE disabled) or
vice versa. Refer to Table 276
on page 532 for the difference in register bit settings
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when moving from CTLE manual, DFE disabled to CTLE triggered, DFE disabled. User need to perform read modify writes to all the register bits that differ through dynamic reconfiguration (AVMM) interface.
Table 276.
Register Map for CTLE triggered and CTLE manual settings
Register Address Register Bit
0x123
0x148
0x14B
0x15B
0x15B
0x15E
0x160
0x166
0x167
0x163
0x14D
0x124
0x11F
1:1
2:2
3:3
0:0
1:1
2:2
3:3
4:4
7:7
4:4
0:0
2:2
0:0
0:0
0:0
0:0
7:5
2:0
5:5
5:4
Description
Enable Adaptation Slicers
Enable DFE Fix Tap 8 to 11
Enable DFE Fix Tap 4 to 7
Enable DFE Fix TAP 1 to 7 Adaptation
Enable DFE Fix TAP 8 to 11 Adaptation
Enable VREF Adaptation
Enable VGA Adaptation
Enable CTLE Adaptation
Enable CTLE Adaptation
Enable CTLE Adaptation
Bypass DFE Fix TAP 1 to 7 Adaptation
Bypass DFE Fix TAP 8 to 11 Adaptation
Bypass VREF Adaptations
Bypass VGA Adaptations
Bypass Single Stage CTLE
Bypass 4 Stage CTLE
CTLE Adaptation Timer Window
DFE Adaptation Mode
Enable DFT
Eq_bw_sel
Value
CTLE Triggered, DFE
Disabled
1'b1
CTLE Manual, DFE
Disabled
1'b0
1'b0
1'b0
1'b0
1'b0
1'b1
1'b1
1'b1
1'b1
1'b1
1'b0
1'b0
1'b0
1'b0
1'b0
1'b1
1'b1
1'b0 1'b1
1'b1
1'b0
1'b0
1'b1
1'b1
3'b111
3'b100 3'b111
1'b1
2'b01 (Gen3) 2'b00 (Gen1/2)
Refer to the "Arria 10 Register Map" and "Arria 10 Adaptation Tool" for details on adaptation registers.
Related Information
•
on page 456
•
Arria 10 Transceiver Register Map
on page 564
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6.12.4. Enabling and Disabling Loopback Modes Using Direct
Reconfiguration Flow
Arria 10 devices have three loopback modes:
• Serial Loopback
• Reverse Serial Loopback (Pre-CDR)
• Reverse Serial Loopback (Post-CDR)
The loopback mode can be dynamically reconfigured by accessing the register space.
Serial Loopback Mode
In serial loopback mode, a path exists between the serializer of the transmitter and the CDR of the receiver, so that the data from the CDR is recovered from the serializer while the data from the receiver serial input pin is ignored. You can enable or disable this mode.
Figure 273. Serial Loopback Mode
Transmitter
PCS PMA
Serializer
Serial Loopback
Receiver
PCS PMA
Deserializer CDR
To enable serial loopback mode:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x2E1 to set bit 0 to 1’b1
3. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable serial loopback mode:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x2E1 to set bit 0 to 1’b0
3. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
You can also enable the serial loopback mode by turning on Enable rx_seriallpbken
port in the Native PHY IP Parameter Editor and driving the port to 1’b1.
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Reverse Serial Loopback Mode (Pre-CDR)
In the pre-CDR mode, data received through the RX input buffer is looped back to the
TX output buffer. You can enable the reverse serial loopback mode by performing read-modify-write to the following registers.
Figure 274. Reverse Serial Loopback Mode (Pre-CDR)
Transmitter
PCS PMA
Serializer
Receiver
PCS
Pre-CDR Reverse
Serial Loopback
PMA
Deserializer CDR
Table 277.
Bit Values to Be Set
Address
0x137[7]
0x13C[7]
0x132[5:4]
0x142[4]
0x11D[0]
Bit Values
1’b1
1’b0
2’b00
1’b1
1’b1
Reverse Serial Loopback Mode (Post-CDR)
In the post-CDR mode, received data passes through the RX CDR and then loops back to the TX output buffer. Perform read-modify-write to the following registers to enable this mode.
Figure 275. Reverse Serial Loopback Mode (Post-CDR)
Transmitter
PCS PMA
Serializer
Receiver
PCS PMA
Post-CDR Reverse
Serial Loopback
Deserializer CDR
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Table 278.
Bit Values to Be Set
Address
0x137[7]
0x13C[7]
0x132[5:4]
0x142[4]
0x11D[0]
Disabling Reverse Serial Loopback Mode (Pre-CDR and Post-CDR)
To disable reverse-serial loopback mode, set the address bits to the following values, by performing read-modify-write.
Table 279.
Bit Values to Be Set
Address
0x137[7]
0x13C[7]
0x132[5:4]
0x142[4]
0x11D[0]
Bit Values
1’b0
1’b0
2’b00
1’b0
1’b0
Related Information
Steps to Perform Dynamic Reconfiguration
on page 516
Bit Values
1’b0
1’b1
2’b01
1’b0
1’b0
6.13. Ports and Parameters
The reconfiguration interface is integrated in the Native PHY instance and the TX PLL instances. Instantiate the Native PHY and the TX PLL IP cores in Qsys by clicking
Tools
➤
IP Catalog. You can define parameters for IP cores by using the IP corespecific parameter editor. To expose the reconfiguration interface ports, select the
Enable dynamic reconfiguration option when parameterizing the IP core.
You can share the reconfiguration interface among all the channels by turning on
Share reconfiguration interface when parameterizing the IP core. When this option is enabled, the IP core presents a single reconfiguration interface for dynamic reconfiguration of all channels. Address bits [9:0] provide the register address in the reconfiguration space of the selected channel. The remaining address bits of the reconfiguration address specify the selected logical channel. For example, if there are four channels in the Native PHY IP instance, reconfig_address[9:0]
specifies the address and reconfig_address[11:10]
are binary encoded to specify the four channels. For example, 2'b01 in reconfig_address[11:10]
specifies logical channel 1.
The following figure shows the signals available when the Native PHY IP core is configured for four channels and the Share reconfiguration interface option is enabled.
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Figure 276. Signals Available with Shared Native PHY Reconfiguration Interface reconfig_clk reconfig_reset reconfig_write reconfig_read reconfig_address[11:0] reconfig_writedata[31:0] reconfig_readdata[31:0] reconfig_waitrequest
Native PHY IP Core clk reset write read address writedata readdata waitrequest
Table 280.
Reconfiguration Interface Ports with Shared Native PHY Reconfiguration
Interface
The reconfiguration interface ports when Share reconfiguration interface is enabled. <N> represents the number of channels.
Port Name reconfig_clk reconfig_reset reconfig_write reconfig_read reconfig_address[log2<N>+9:0] reconfig_writedata[31:0] reconfig_readdata[31:0] reconfig_waitrequest
Direction
Input
Input
Input
Input
Input
Input
Output
Output
Clock Domain
N/A
Description
Avalon clock. The clock frequency is 100-125
MHz.
reconfig_clk
Resets the Avalon interface. Asynchronous to assertion and synchronous to deassertion.
reconfig_clk
Write enable signal. Signal is active high.
reconfig_clk
Read enable signal. Signal is active high.
reconfig_clk
Address bus. The lower 10 bits specify address and the upper bits specify the channel.
reconfig_clk
A 32-bit data write bus. Data to be written into the address indicated by reconfig_address
.
reconfig_clk
A 32-bit data read bus. Valid data is placed on this bus after a read operation. Signal is valid after reconfig_waitrequest then low.
goes high and reconfig_clk
A one-bit signal that indicates the Avalon interface is busy. Keep the Avalon command asserted until the interface is ready to proceed with the read/write transfer. The behavior of this signal depends on whether the feature
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not. For more details, refer to the Arbitration section.
When Share reconfiguration interface is off, the Native PHY IP core provides an independent reconfiguration interface for each channel. For example, when a reconfiguration interface is not shared for a four-channel Native PHY IP instance, reconfig_address[9:0]
corresponds to the reconfiguration address bus of logical channel 0, reconfig_address[19:10]
correspond to the reconfiguration address bus of logical channel 1, reconfig_address[29:20]
corresponds to the reconfiguration address bus of logical channel 2, and reconfig_address[39:30] correspond to the reconfiguration address bus of logical channel 3.
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The following figure shows the signals available when the Native PHY is configured for four channels and the Share reconfiguration interface option is not enabled.
Figure 277. Signals Available with Independent Native PHY Reconfiguration Interfaces reconfig_clk[3:0] reconfig_reset[3:0] reconfig_write[3:0] reconfig_read[3:0] reconfig_address[39:0] reconfig_writedata[127:0] reconfig_readdata[127:0] reconfig_waitrequest[3:0]
Native PHY IP Core clk reset write read address writedata readdata waitrequest
Table 281.
Reconfiguration Interface Ports with Independent Native PHY
Reconfiguration Interfaces
The reconfiguration interface ports when Share reconfiguration interface is disabled. <N> represents the number of channels.
Port Name reconfig_clk[N-1:0] reconfig_reset[N-1:0] reconfig_write[N-1:0] reconfig_read[N-1:0] reconfig_address[N*10-1:0] reconfig_writedata[N*32-1:0] reconfig_readdata[N*32-1:0] reconfig_waitrequest[N-1:0]
Direction
Input
Input
Input
Input
Input
Input
Output
Output
Clock Domain
N/A
Description
Avalon clock for each channel. The clock frequency is 100-125 MHz.
reconfig_clk
Resets the Avalon interface for each channel.
Asynchronous to assertion and synchronous to deassertion.
reconfig_clk
Write enable signal for each channel. Signal is active high.
reconfig_clk
Read enable signal for each channel. Signal is active high.
reconfig_clk
A 10-bit address bus for each channel.
reconfig_clk
A 32-bit data write bus for each channel. Data to be written into the address indicated by the corresponding address field in reconfig_address
.
reconfig_clk
A 32-bit data read bus for each channel. Valid data is placed on this bus after a read operation. Signal is valid after goes high and then low.
waitrequest reconfig_clk
A one-bit signal for each channel that indicates the Avalon interface is busy. Keep the Avalon command asserted until the interface is ready to proceed with the read/ write transfer. The behavior of this signal depends on whether the feature Separate reconfig_waitrequest from the status of
AVMM arbitration with PreSICE is enabled or not. For more details, refer to the
Arbitration section.
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Table 282.
Avalon Interface Parameters
The following parameters are available in the Dynamic Reconfiguration tab of the Transceiver Native PHY and TX PLL parameter editors.
Note: The Native PHY and the PLL IP Parameter Editors give an error or warning message if any of the parameter selections violate the legality checks.
Parameter
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master
Endpoint
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Enable PRBS soft accumulators
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
Value
On / Off
On / Off
On / Off
Description
Available in Native PHY and TX PLL IP parameter editors. Enables the reconfiguration interface. Off by default. The reconfiguration interface is exposed when this option is enabled.
Available in Native PHY IP parameter editor only. Enables you to use a single reconfiguration interface to control all channels. Off by default. If enabled, the uppermost bits of reconfig_address identifies the active channel. The lower 10 bits specify the reconfiguration address. Binary encoding is used to identify the active channel (available only for Transceiver Native PHY). Enable this option if the Native PHY is configured with more than one channel.
Available in Native PHY and TX PLL IP parameter editors. When enabled, the Altera Debug Master Endpoint (ADME) is instantiated and has access to the Avalon-MM interface of the Native PHY. You can access certain test and debug functions using System Console with the ADME. Refer to the Embedded Debug Features section for more details about ADME.
On / Off
On / Off
When enabled, reconfig_waitrequest
do not indicate the status of AVMM arbitration with PreSICE. The AVMM arbitration status is reflected in a soft status register bit. This feature requires that the Enable control and status registers feature under Optional Reconfiguration Logic be enabled. Refer to
Arbitration for more details on this feature. Refer to the
Calibration chapter for more details about calibration.
Available in Native PHY and TX PLL IP parameter editors. Enables capability registers. These registers provide high-level information about the transceiver channel's /PLL's configuration.
User-specified Available in Native PHY and TX PLL IP parameter editors. Sets a user-defined numeric identifier that can be read from the user_identifier
offset when the capability registers are enabled.
On / Off
On / Off
Available in Native PHY and TX PLL IP parameter editors. Enables soft registers for reading status signals and writing control signals on the PHY /PLL interface through the ADME or reconfiguration interface.
Available in Native PHY IP parameter editor only. Enables soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and checker.
User-specified Available in Native PHY and TX PLL IP parameter editors. Specifies the file prefix used for generating configuration files. Use a unique prefix for configuration files for each variant of the Native PHY and PLL.
On / Off Available in Native PHY and TX PLL IP parameter editors. Creates a SystemVerilog package file that contains the current configuration data values for all reconfiguration addresses.
Disabled by default.
On / Off Available in Native PHY and TX PLL IP parameter editors. Creates a C header file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.
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Parameter
Generate MIF (Memory Initialize
File)
Value
On / Off
Include PMA analog settings in the configuration files
On / Off
Enable multiple reconfiguration profiles
Enable embedded reconfiguration streamer
Generate reduced reconfiguration files
Number of reconfiguration profiles
Selected reconfiguration profile
Store configuration to selected profile
Load configuration from selected profile
Clear selected profile
Clear all profiles
Refresh selected_profile
On / Off
On / Off
On / Off
1 to 8
0 to 7
N/A
N/A
N/A
N/A
N/A
Description
Available in Native PHY and TX PLL IP parameter editors. Creates a MIF file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.
Available in Native PHY IP parameter editor only. When enabled, the IP allows you to configure the analog settings for the PMA.
These settings are included in your generated configuration files.
Note: Even with this option enabled in the Native PHY IP
Parameter Editor, you must still specify QSF assignments for your analog settings when compiling your static design. The analog settings selected in the Native PHY IP
Parameter Editor are used only to include these settings and their dependent settings in the selected configuration files. For details about QSF assignments for the analog settings, refer to the Analog Parameter Settings chapter.
Available in Native PHY and ATX PLL IP parameter editors only.
Use the Parameter Editor to store multiple configurations. The parameter settings for each profile are tabulated in the Parameter
Editor.
Available in Native PHY and ATX PLL IP parameter editors only.
Embeds the reconfiguration streamer into the Native PHY/ATX PLL
IP cores and automates the dynamic reconfiguration process between multiple predefined configuration profiles.
Available in Native PHY and ATX PLLIP parameter editors only.
Enables the Native PHY and ATX PLL IP cores to generate reconfiguration files that contain only the attributes that differ between multiple profiles.
Available in Native PHY and ATX PLL IP parameter editors only.
Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Available in Native PHY and ATX PLL IP parameter editors only.
Selects which reconfiguration profile to store when you click
Store profile.
Available in Native PHY and ATX PLL IP parameter editors only.
Stores the current Native PHY and ATX PLL parameter settings to the profile specified by the Selected reconfiguration profile parameter.
Available in Native PHY and ATX PLL IP parameter editors only.
Loads the current Native PHY/ATX PLL IP with parameter settings from the stored profile specified by the Selected
reconfiguration profile parameter.
Available in Native PHY and ATX PLL IP parameter editors only.
Clears the stored Native PHY/ATX PLL IP parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY/ATX PLL. In other words, an empty profile reflects the Native PHY/ATX PLL current parameter settings.
Available in Native PHY and ATX PLL IP parameter editors only.
Clears the Native PHY/ATX PLL IP parameter settings for all the profiles.
Available in Native PHY and ATX PLL IP parameter editors only.
Equivalent to clicking the Load configuration from selected
profile and Store configuration to selected profile buttons in sequence. This operation loads the parameter settings from stored profile specified by the Selected reconfiguration profile parameter and then stores the parameters back to the profile.
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Table 283.
Analog PMA Settings (Optional) for Dynamic Reconfiguration
The following parameters are available in the Analog PMA Settings (Optional) tab of the Transceiver Native
PHY parameter editor. Refer to Changing PMA Analog Parameters for more details. Refer to the Analog
Parameter Settings chapter for details about using the QSF assignments.
Value Description Parameter
TX Analog PMA Settings
Analog Mode (Load Intelrecommended Default settings)
cei_11100_lr to xfp_9950
Override Intel-recommended
Analog Mode Default settings
Output Swing Level (VOD)
On / Off
0-31
Selects the analog protocol mode to pre-select the TX pin swing settings (VOD, Pre-emphasis, and Slew Rate). After loading the pre-selected values in the Parameter Editor, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intelrecommended defaults to individually modify the settings.
For details about QSF assignments for the analog settings, refer to the Analog Parameter Settings chapter.
Enables the option to override the Intel-recommended settings for the selected TX Analog Mode for one or more TX analog parameters.
Selects the transmitter programmable output differential voltage swing.
Selects the polarity of the first pre-tap for pre-emphasis.
Pre-Emphasis First Pre-Tap
Polarity
Pre-Emphasis First Pre-Tap
Magnitude
Pre-Emphasis Second Pre-Tap
Polarity
Pre-Emphasis Second Pre-Tap
Magnitude
Pre-Emphasis First Post-Tap
Polarity
Pre-Emphasis First Post-Tap
Magnitude
Pre-Emphasis Second Post-
Tap Polarity
Pre-Emphasis Second Post-
Tap Magnitude
Slew Rate Control
High-Speed Compensation
Fir_pre_1t_neg,
Fir_pre_1t_pos
0-16
Fir_pre_2t_neg,
Fir_pre_2t_pos
0-7
Fir_post_1t_neg,
Fir_post_1t_pos
0-25
Fir_post_2t_neg,
Fir_post_2t_pos
0-12 slew_r0 to slew_r5
Enable / Disable r_r1, r_r2
Selects the magnitude of the first pre-tap for pre-emphasis.
Selects the polarity of the second pre-tap for pre-emphasis.
Selects the magnitude of the second pre-tap for preemphasis.
Selects the polarity of the first post-tap for pre-emphasis.
Selects the magnitude of the first post-tap for preemphasis.
Selects the polarity of the second post-tap for preemphasis.
Selects the magnitude of the second post-tap for preemphasis.
Selects the slew rate of the TX output signal. Valid values span from slowest to the fastest rate.
Enables the power-distribution network (PDN) induced intersymbol interference (ISI) compensation in the TX driver.
When enabled, it reduces the PDN induced ISI jitter, but increases the power consumption.
Selects the on-chip TX differential termination.
On-Chip termination
RX Analog PMA settings
Override Intel-recommended
Default settings
On / Off
CTLE (Continuous Time Linear
Equalizer) mode non_s1_mode, s1_mode
Enables the option to override the Intel-recommended settings for one or more RX analog parameters. For details about QSF assignments for the analog settings, refer to the
Analog Parameter Settings chapter.
Selects between the RX high gain mode (non_s1_mode) or
RX high data rate mode (s1_mode) for the Continuous Time
Linear Equalizer (CTLE).
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Parameter
DC gain control of high gain mode CTLE
AC Gain Control of High Gain
Mode CTLE
AC Gain Control of High Data
Rate Mode CTLE
Variable Gain Amplifier (VGA)
Voltage Swing Select
Decision Feedback Equalizer
(DFE) Fixed Tap 1 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 2 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 3 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 4 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 5 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 6 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 7 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 8 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 9 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 10 Coefficient
Decision Feedback Equalizer
(DFE) Fixed Tap 11 Coefficient
On-Chip termination radp_dfe_fxtap1_0 to radp_dfe_fxtap1_127 radp_dfe_fxtap2_0 to radp_dfe_fxtap2_127 radp_dfe_fxtap3_0 to radp_dfe_fxtap3_127 radp_dfe_fxtap4_0 to radp_dfe_fxtap4_63 radp_dfe_fxtap5_0 to radp_dfe_fxtap5_63 radp_dfe_fxtap6_0 to radp_dfe_fxtap6_31 radp_dfe_fxtap7_0 to radp_dfe_fxtap7_31 radp_dfe_fxtap8_0 to radp_dfe_fxtap8_31 radp_dfe_fxtap9_0 to radp_dfe_fxtap9_31 radp_dfe_fxtap10_0 to radp_dfe_fxtap10_31 radp_dfe_fxtap11_0 to radp_dfe_fxtap11_31 r_ext0, r_r1, r_r2
Value no_dc_gain to stg4_gain7 radp_ctle_acgain_4s_0 to radp_ctle_acgain_4s_2
8 radp_ctle_eqz_1s_sel_
0 to radp_ctle_eqz_1s_sel_
15 radp_vga_sel_0 to radp_vga_sel_7
Description
Selects the DC gain of the Continuous Time Linear Equalizer
(CTLE) in high gain mode
Selects the AC gain of the Continuous Time Linear Equalizer
(CTLE) in high gain mode when CTLE is in manual mode
Selects the AC gain of the Continuous Time Linear Equalizer
(CTLE) in high data rate mode when CTLE is in manual mode
Selects the Variable Gain Amplifier (VGA) output voltage swing when both the CTLE and DFE blocks are in manual mode.
Selects the coefficient of the fixed tap 1 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 2 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 3 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 4 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 5 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 6 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 7 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 8 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 9 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 10 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the coefficient of the fixed tap 11 of the Decision
Feedback Equalizer (DFE) when operating in manual mode.
Selects the on-chip RX differential termination.
Related Information
•
Analog Parameter Settings on page 585
•
on page 544
•
on page 512
•
Changing PMA Analog Parameters
on page 527
•
on page 567
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6.14. Dynamic Reconfiguration Interface Merging Across Multiple
IP Blocks
Dynamic reconfiguration interfaces may need to be shared between multiple IP blocks to maximize transceiver channel utilization. The Native PHY provides the ability to create channels that are either simplex or duplex instances. However, each physical transceiver channel in Arria 10 devices is fully duplex.
You can share the reconfiguration interfaces across different IP blocks by manually making a QSF assignment. There are two cases where a dynamic reconfiguration interface might need to be shared between multiple IP blocks:
• Independent instances of simplex receivers and transmitters in the same physical location
• Separate CMU PLL and TX channel in the same physical location
The following example shows one Native PHY IP instance of a TX-only channel and another instance of an RX-only channel.
Figure 278. Independent Instances of Simplex TX/RX in the Same Physical Location
Logical Physical
User Logic
Reconfiguration
Interface 0
Native PHY IP Core
TX Channel
Reconfiguration
Interface 1
Native PHY IP Core
RX Channel
Merging QSF: from Reconfiguration Interface 0 to Reconfiguration Interface 1
User Logic
Reconfiguration
Interface 1
Native PHY IP Core
TX Channel
RX Channel
Reconfiguration Interface 0 merged into
Reconfiguration Interface1
The following example shows one Native PHY IP instance of a TX-only channel and an instance of a CMU PLL.
Figure 279. Separate CMU PLL and TX Channel in the Same Physical Location
Logical Physical
User Logic
Reconfiguration
Interface 0
Transceiver PLL IP Core
CMU
Reconfiguration
Interface 1
Native PHY IP Core
TX Channel
Merging QSF: from Reconfiguration Interface 1 to Reconfiguration Interface 0
User Logic
Reconfiguration
Interface 0
Native PHY IP Core
CMU
TX Channel
Reconfiguration Interface 1 merged into
Reconfiguration Interface 0
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Rules for Merging Reconfiguration Interfaces Across Multiple IP Cores
To merge reconfiguration interfaces across multiple IP blocks, you must follow these rules:
1. The control signals for the reconfiguration interfaces of the IP blocks must be driven by the same source. The reconfig_clk
, reconfig_reset
, reconfig_write
, reconfig_read
, reconfig_address
, and reconfig_writedata
ports of the two interfaces to be merged must be driven from the same source.
2. You must make a QSF assignment to manually specify which two reconfiguration interfaces are to be merged.
a. Use the XCVR_RECONFIG_GROUP assignment.
b. Set the To field of the assignment to either the reconfiguration interfaces of the instances to be merged or to the pin names. The reconfiguration interface has the string twentynm_hssi_avmm_if_inst.
c. Assign the two instances to be merged to the same reconfiguration group.
You cannot merge multiple reconfiguration interfaces when ADME, optional reconfiguration logic, or embedded reconfiguration streamer are enabled in the Native
PHY IP core. (62)
You cannot merge the TX and RX channels when the Shared reconfiguration
interface parameter is enabled in the Native PHY IP core Parameter Editor. You can merge channels only if the reconfiguration interfaces are independent.
Refer to the following two examples to merge reconfiguration interfaces.
Example 3. Using reconfiguration interface names
This example shows how to merge a transmit-only Native PHY instance with a receiveonly instance using the reconfiguration interface names. These instances are assigned to reconfiguration group 0.
For Native PHY 0—transmit-only instance: set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to topdesign:topdesign_inst|<TX only instance name>*twentynm_hssi_avmm_if_inst*
For Native PHY 1—receive-only instance to be merged with Native PHY 0: set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to topdesign:topdesign_inst|<RX only instance name>*twentynm_hssi_avmm_if_inst*
Example 4. Using pin names
This example shows how to merge a transmit-only Native PHY instance with a receiveonly instance using pin names. These instances are assigned to reconfiguration group
1.
For Native PHY 0—transmit-only instance: set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx[0]
(62) Please refer to Calibration section on how to calibrate when those features are not available.
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For Native PHY 1—receive-only instance to be merged with Native PHY 0: set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx[0]
Related Information
on page 567
6.15. Embedded Debug Features
Note: For details on TTK usage refer to "Debugging Transceiver Links" in Quartus Prime
Standard Edition Handbook Volume 3: Verification.
The Arria 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores provide the following optional debug features to facilitate embedded test and debug capability:
• Altera Debug Master Endpoint (ADME)
• Optional Reconfiguration Logic
Related Information
Quartus Prime Standard Edition Handbook Volume 3: Verification
6.15.1. Altera Debug Master Endpoint
The ADME is a JTAG-based Avalon Memory-Mapped (Avalon-MM) master that provides access to the transceiver and PLL registers through the system console. You can enable ADME using the Enable Altera Debug Master Endpoint option available under the Dynamic Reconfiguration tab in the Native PHY and PLL IP cores. When using ADME, the Quartus Prime software inserts the debug interconnect fabric to connect with USB, JTAG, or other net hosts. Select the Share Reconfiguration
Interface parameter when the Native PHY IP instance has more than one channel.
When you enable ADME in your design, you must
• connect an Avalon-MM master to the reconfiguration interface.
• OR connect the, reconfig_reset
signals and ground the reconfig_write
, reconfig_read
, reconfig_address
and reconfig_write
data signals of the reconfiguration interface. If the reconfiguration interface signals are not connected appropriately, there is no clock or reset for the ADME, and the ADME does not function as expected.
6.15.2. Optional Reconfiguration Logic
The Arria 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores contain soft logic for debug purposes known as the Optional Reconfiguration Logic. This soft logic provides a set of registers that enable you to determine the state of the Native PHY and PLL IP cores.
You can enable the following optional reconfiguration logic options in the transceiver
Native PHY and PLL IP cores:
• Capability registers
• Control and status registers
• PRBS soft accumulators (Native PHY IP core only)
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6.15.2.1. Capability Registers
The capability registers provide high level information about the transceiver channel and PLL configuration.
The capability registers capture a set of chosen capabilities of the PHY that cannot be reconfigured. The following capability registers are available for the Native PHY IP core.
Table 284.
Capability Registers for the Native PHY IP Core
Address
0x200[7:0]
0x204[0]
0x205[0]
0x210[7:0]
0x211[7:0]
0x212[7:0]
0x213[0]
RO
Type
RO
RO
RO
RO
RO
RO
Name
IP Identifier
Status Register Enabled
Control Register Enabled
Number of Channels
Channel Number
Duplex
PRBS Soft Enabled
Description
Unique identifier for the Native PHY IP instance.
Indicates whether the status registers have been enabled. 1'b1 indicates that the status registers are enabled.
Indicates whether the control registers have been enabled. 1'b1 indicates that the control registers are enabled.
Shows the number of channels specified for the
Native PHY IP instance.
Shows the unique channel number.
Shows the transceiver mode:
• 2'b00 = Unused
• 2'b01 = TX
• 2'b10 = RX
• 2'b11 = Duplex
Indicates whether the PRBS soft accumulators are enabled. 1’b1 indicates the accumulators are enabled.
The following capability registers are available for the PLL IP cores.
Table 285.
Capability Registers for the PLL IP Cores
Address
0x200[7:0]
0x204[0]
RO
Type
RO
Name
IP Identifier
Status Register Enabled
0x205[0]
0x210[7:0]
RO
RO
Control Register Enabled
Master CGB Enabled
Description
Unique identifier for the PLL IP instance.
Indicates if the status registers have been enabled or not. 1'b1 indicates that the status registers have been enabled.
Indicates if the control registers have been enabled or not. 1'b1 indicates that the control registers have been enabled.
Indicates if the Master Clock Generation Block has been enabled. 1'b1 indicates the master CGB is enabled.
6.15.2.2. Control and Status Registers
Control and status registers are optional registers that memory-map some of the status outputs from and control inputs to the Native PHY and PLL.
The following control and status registers are available for the Native PHY IP core.
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Table 286.
Control Registers for the Native PHY IP Core
Address
0x2E0[0]
0x2E0[1]
0x2E0[2]
0x2E0[3]
0x2E1[0]
0x2E2[0]
0x2E2[1]
0x2E2[2]
0x2E2[3]
0x2E2[4]
0x2E2[5]
0x2E2[6]
0x2E2[7]
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Register set_rx_locktodata set_rx_locktoref override_set_rx_loc ktodata override_set_rx_loc ktoref rx_seriallpbken rx_analogreset rx_digitalreset tx_analogreset tx_digitalreset override_rx_analogr eset override_rx_digital reset override_tx_analogr eset override_tx_digital reset
Description
Asserts the set_rx_locktodata
signal to the receiver. 1'b1 sets the ADME set_rx_locktodata register. See override_set_rx_locktodata
.
Asserts the set_rx_locktoref receiver. 1'b1 sets the ADME
signal to the set_rx_locktoref register. See below.
override_set_rx_locktoref
row
Selects whether the receiver listens to the ADME set_rx_locktodata
register or the rx_set_locktodata
port. 1'b1 indicates that the receiver listens to the ADME register.
set_rx_locktodata
Selects whether the receiver is listens to the AMDE set_rx_locktoref
register or the rx_set_locktoref
port. 1'b1 indicates that the receiver listens to the ADME register.
set_rx_locktoref
Enables the rx_seriallopbken
feature in the transceiver. 1’b1 enables reverse serial loopback.
Drives rx_analogreset
when the override is set.
Drives rx_digitalreset
when the override is set.
Drives tx_analogreset
when the override is set.
Drives tx_digitalreset
when the override is set.
Selects whether the receiver listens to the ADME rx_analogreset
register or the rx_analogreset port. 1'b1 indicates the receiver listens to the ADME rx_analogreset
register.
Selects whether the receiver listens to the ADME rx_digitalreset
register or the rx_digitalreset
port. 1'b1 indicates the receiver listens to the ADME rx_digitalreset
register.
Selects whether the receiver listens to the ADME tx_analogreset
register or the tx_analogreset port. 1'b1 indicates the receiver listens to the ADME tx_analogreset
register.
Selects whether the receiver listens to the ADME tx_digitalreset
register or the tx_digitalreset
port. 1'b1 indicates the receiver listens to the ADME tx_digitalreset
register.
Table 287.
Status Registers for the Native PHY IP Core
Address
0x280[0]
0x280[1]
RO
Type
RO
Register rx_is_lockedtodata rx_is_lockedtoref
Description
Shows the status of the current channel’s rx_is_lockedtodata
signal. 1’b1 indicates the receiver is locked to the incoming data.
Shows the status of the current channel’s rx_is_lockedtoref
signal. 1’b1 indicates the receiver is locked to the reference clock.
continued...
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Address
0x281[0]
0x281[1]
0x281[2]
0x280[1]
0x280[2]
RO
Type
RO
RO
Register tx_cal_busy rx_cal_busy avmm_busy
Table 289.
Status Registers for the PLL IP Cores
Address
0x280[0] RO
Type Register pll_locked
RO
RO pll_cal_busy avmm_busy
Description
Shows the status of the transmitter calibration status. 1’b1 indicates the transmitter calibration is in progress.
Shows the status of the receiver calibration status.
1’b1 indicates the receiver calibration is in progress.
Shows the status of the internal configuration bus arbitration. 1’b1 indicates PreSICE has control of the internal configuration bus. 1'b0 indicates the user has control of the internal configuration bus. Refer to the Arbitration section for more details. For more details about calibration registers and performing user recalibration, refer to the Calibration chapter.
The following control and status registers are available for the PLL IP cores.
Table 288.
Control Registers for the PLL IP Cores
Address
0x2E0[0]
0x2E0[1]
RW
Type
RW
Register pll_powerdown override_pll_powerd own
Description
Drives the PLL powerdown when the Override is set.
Selects whether the receiver listens to the ADME pll_powerdown
register or the pll_powerdown port. 1’b1 indicates the receiver listens to the ADME pll_powerdown
.
Description
Indicates if the PLL is locked. 1'b1 indicates the PLL is locked.
Indicates the calibration status. 1'b1 indicates the
PLL is currently being calibrated.
Shows the status of the internal configuration bus arbitration. 1’b1 indicates PreSICE has control of the internal configuration bus. 1'b0 indicates the user has control of the internal configuration bus. Refer to the Arbitration section for more details.
Related Information
on page 512
6.15.2.3. PRBS Soft Accumulators
The Pseudo Random Binary Sequence (PRBS) soft accumulators are used in conjunction with the hard PRBS blocks in the transceiver channel. This section describes the soft logic that can be added to the Native PHY IP core. To enable this option, turn on the Enable PRBS Soft Accumulators option in the Native PHY IP
Parameter Editor.
The PRBS soft accumulator has three control bits (Enable, Reset, and Snapshot) and one status bit (PRBS Done).
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• Enable bit—used to turn on the accumulation logic. This bit is also used for selective error accumulation and to pause the sequence.
• Reset bit—resets the PRBS polynomial and the bit and error accumulators. It also resets the snapshot registers if independent channel snapshots are used.
• Snapshot bit—captures the current value of the accumulated bits and the errors simultaneously. This neutralizes the impact of the added read time when the
Avalon-MM interface is used. Capturing a snapshot provides an accurate error count with respect to the bit count at a specific time.
• PRBS Done bit—indicates the PRBS checker has had sufficient time to lock to the incoming pattern.
For example, to capture the accumulated errors at any instance of time and read them back, you can perform the following operations.
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform read-modify-write to address 0x300 and set bit 0 to 1'b1. This action enables the error and bit counters.
3. To capture the errors accumulated at a particular instant, perform read-modifywrite to address 0x300 and set bit 2 to 1'b1. This takes a snapshot of the error counters and stores the value to the error count registers.
4. To read the number of errors accumulated when the snapshot was captured, perform a read from the corresponding error registers 0x301 to 0x307.
5. To reset the bit and error accumulators, perform a read-modify-write to address
0x300 bit 1.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
You can enable the error and bit counters (0x300[0]) and capture the accumulated bits and errors at different times. The error count registers and bit count registers are updated with the latest counter values as long as the counter enable bit is set.
Use the PRBS soft accumulators to count the number of accumulated bits and errors when the hard PRBS blocks are used. PRBS soft accumulators are word-based counter.
The value read out from the PRBS soft accumulators represent the number of words counted. Hence, in order to obtain the total accumulated bit, user needs to multiply the value read out from the Accumulated bit pass through count [49:0] registers with the width of PCS-PMA interface. For Accumulated error count [49:0] registers, it counts one as long as there are bit errors in a word (be it one bit error in a word or all the bits in a word are erroneous). Hence, the Accumulated error count [49:0] registers do not give absolute bit errors counted. For each count, the absolute bit errors could range from one to the width of PCS-PMA interface.
For more information about using the hard PRBS blocks, refer to the "Using Data
Pattern Generators and Checkers" section.
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Table 290.
PRBS Accumulator Registers
Address
0x300[0]
0x300[1]
0x300[2]
Type
RW
RW
RW
Name
Counter enable (enables both error and bit counters)
Reset
Error Count Snapshot
0x300[3]
0x301[7:0]
0x302[7:0]
0x303[7:0]
0x304[7:0]
0x305[7:0]
0x306[7:0]
0x307[1:0]
0x30D[7:0]
0x30E[7:0]
0x30F[7:0]
0x310[7:0]
0x311[7:0]
0x312[7:0]
0x313[1:0]
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
PRBS Done
Accumulated error count [7:0]
Accumulated error count [15:8]
Accumulated error count [23:16]
Accumulated error count [31:24]
Accumulated error count [39:32]
Accumulated error count [47:40]
Accumulated error count [49:48]
Accumulated bit pass through count[7:0]
Accumulated bit pass through count[15:8]
Accumulated bit pass through count[23:16]
Accumulated bit pass through count[31:24]
Accumulated bit pass through count[39:32]
Accumulated bit pass through count[47:40]
Accumulated bit pass through count[49:48]
Description
Counter enable (enables both error and bit counters)
Reset the error accumulators
Snapshot captures the current value of accumulated bits and the errors at that time instance
PRBS Done when asserted indicates the verifier has captured consecutive PRBS patterns and first pass of polynomial is complete
Accumulated error count [7:0]
Accumulated error count [15:8]
Accumulated error count [23:16]
Accumulated error count [31:24]
Accumulated error count [39:32]
Accumulated error count [47:40]
Accumulated error count [49:48]
Accumulated bit pass through count[7:0]
Accumulated bit pass through count[15:8]
Accumulated bit pass through count[23:16]
Accumulated bit pass through count[31:24]
Accumulated bit pass through count[39:32]
Accumulated bit pass through count[47:40]
Accumulated bit pass through count[49:48]
Note: Intel recommends that you disable the byte serializer and deserializer blocks when using the soft PRBS accumulators. When the byte serializer and deserializer blocks are enabled, the number of bits counted are halved because the clock is running at half the rate.
Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
•
on page 512
•
Using Data Pattern Generators and Checkers
on page 550
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6.16. Using Data Pattern Generators and Checkers
The Arria 10 transceivers contain hardened data generators and checkers to provide a simple and easy way to verify and characterize high speed links. Hardening the data generators and verifiers saves FPGA fabric logic resources. The pattern generator block supports the following patterns:
• Pseudo Random Binary Sequence (PRBS)
• Pseudo Random Pattern (PRP)
The pattern generators and checkers are supported only for non-bonded channels.
6.16.1. Using PRBS Data Pattern Generator and Checker
Use the Arria 10 PRBS generator and checker to simulate traffic and easily characterize high-speed links without fully implementing any upper protocol stack layer. The PRBS generator generates a self-aligning pattern and covers a known number of unique sequences. Because the PRBS pattern is generated by a Linear
Feedback Shift Register (LFSR), the next pattern can be determined from the previous pattern. When the PRBS checker receives a portion of the received pattern, it can generate the next sequence of bits to verify whether the next data sequence received is correct.
The PRBS generator and checker are shared between the Standard and Enhanced datapaths through the PCS. Therefore, they have only one set of control signals and registers. The data lines from the various PCSs and shared PRBS generator are MUXed before they are sent to the PMA. When the PRBS generator is enabled, the data on the
PRBS data lines is selected to be sent to the PMA. Either the data from the PCS or the data generated from the PRBS generator can be sent to the PMA at any time.
The PRBS generator and checker can be configured for two widths of the PCS-PMA interface: 10 bits and 64 bits. PRBS9 is available in both 10-bit and 64-bit PCS-PMA widths. All other PRBS patterns are available in 64-bit PCS-PMA width only. The PRBS generator and checker patterns can only be used when the PCS-PMA interface width is configured to 10 bits or 64 bits. For any other PCS-PMA width, to ensure the correct clocks are provided to the PRBS blocks you must first reconfigure the width to either
10 or 64 bits before using the PRBS generator and checker. For example, when the transceiver is configured to a 20-bit PCS/PMA interface, you must first reconfigure the
PCS-PMA width to 10 bits before setting up the PRBS generator and checker. The PRBS setup does not automatically change the PCS/PMA width.
The 10-bit PCS-PMA width for PRBS9 is available for lower frequency testing. You can configure PRBS9 in either 10-bit or 64-bit width, based on the data rate. The FPGA fabric-PCS interface must run in the recommended speed range of the FPGA core.
Therefore, you must configure PRBS9 in one of the two bit width modes, so that the
FPGA fabric-PCS interface parallel clock runs in this operating range.
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Examples:
• If you want to use PRBS9 and the data rate is 2.5 Gbps, you can use the PRBS9 in
10-bit mode (PCS-PMA width = 10). In this case, the parallel clock frequency =
Data rate / PCS-PMA width = 2500 Mbps/10 = 250 MHz.
• If you want to use PRBS9 and the data rate is 6.4 Gbps, you can use the PRBS9 in
64-bit mode (PCS-PMA width = 64). In this case, the parallel clock frequency =
Data rate / PCS-PMA width = 6400 Mbps/64 = 100 MHz.
• If you want to use PRBS9 and the data rate is 12.5 Gbps, you can use the PRBS9 in 64 bit mode (PCS-PMA width = 64). In this case, the parallel clock frequency =
Data rate / PCS-PMA width = 12500 Mbps/64 = 195.3125 MHz.
Table 291.
PRBS Supported Polynomials and Data Widths
Use the 10-bit mode of PRBS9 when the data rate is lower than 3 Gbps.
Pattern Polynomial
PRBS7
PRBS9
PRBS15
PRBS23
PRBS31
G(x) = 1+ x 6 + x 7
G(x) = 1+ x 5 + x 9
G(x) = 1+ x 14 + x 15
G(x) = 1+ x 18 + x 23
G(x) = 1+ x 28 + x 31
64-Bit
X
X
X
X
X
10-Bit
X
The PRBS checker has the following control and status signals available to the FPGA fabric:
• rx_prbs_done
—Indicates the PRBS sequence has completed one full cycle. It stays high until you reset it with rx_prbs_err_clr
.
• rx_prbs_err
—Goes high if an error occurs. This signal is pulse-extended to allow you to capture it in the RX FPGA CLK domain.
• rx_prbs_err_clr
—Used to reset the rx_prbs_err signal
.
Enable the PRBS checker control and status ports through the Native PHY IP
Parameter Editor in the Quartus Prime software.
Use the PRBS soft accumulators to count the number of accumulated bits and errors when the hard PRBS blocks are used. For more information about using the accumulators and reading the error values, refer to the PRBS Soft Accumulators section.
Table 292.
Register Map for PRBS Generators for bonded and non bonded designs
Reconfigur ation
Address
(HEX)
Reconfigur ation Bit
0x006 [2:0]
Attribute Name tx_pma_data_sel
Related
Addresses
0x8
Attribute
Encoding prbs_pat
Bit
Encoding
3'b100
Description
[3] prbs9_dwidth prbs9_10b prbs9_64b
1'b1
1'b0
Select PRBS Generator
Block
Enable PRBS9 in 10-bit mode
Enable PRBS9 in 64-bit mode continued...
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Reconfigur ation
Address
(HEX)
Reconfigur ation Bit
[6]
Attribute Name prbs_clken
Related
Addresses
Attribute
Encoding prbs_clk_dis
Bit
Encoding
Description
0x007
0x008
0x110
[7:4]
[4]
[6:5]
[2:0] prbs_gen_pat prbs_gen_pat tx_pma_data_sel ser_mode
0x8
0x7
0x6 prbs_clk_en
1'b0
1'b1 prbs_7 prbs_9 prbs_15 prbs_23 prbs_31 prbs_7 prbs_9 prbs_15 prbs_23 prbs_31 prbs_pat sixty_four_bit ten_bit xn_non_bonding (6
3)
4'b0001
4'b0010
4'b0100
4'b1000
4'b0000
1'b0
1'b0
1'b0
1'b0
1'b1
2'b00
3'b011
3'b100
5'b11000
Disable PRBS generator clock
Enable PRBS generator clock
Enable PRBS7 pattern
Enable PRBS9 pattern
Enable PRBS15 pattern
Enable PRBS23 pattern
Enable PRBS31 pattern
Enable PRBS7 pattern
Enable PRBS9 pattern
Enable PRBS15 pattern
Enable PRBS23 pattern
Enable PRBS31 pattern
Enable PRBS generator
64-bit mode
10-bit mode
Enables xn non bonding 0x111 [4:0] x1_clock_source_ sel
0x119
Table 293.
Register Map for PRBS Checker for bonded and non bonded designs
Reconfiguratio n Address
(HEX)
0x00A
Reconfiguratio n Bit
Attribute Name
[7] prbs_clken
Related
Addresses
Attribute
Encoding prbs_clk_dis
Bit
Encoding
1'b0
Description
0x00B [3:2]
[7:4] rx_prbs_mask prbs_ver 0xC prbs_clk_en prbsmask1024 prbsmask128 prbsmask256 prbsmask512 prbs_7
1'b1
2'b11
2'b00
2'b01
2'b10
4'b0001
Disable PRBS checker clock
Enable PRBS checker clock
Counter threshold to
1023
Counter threshold to
127
Counter threshold to
255
Counter threshold to
511
Enable PRBS7 pattern continued...
(63) You must read and save the value in the register 0x111[5:0] before changing the x1_clcok_source_sel
setting to xN non bonding. To disable the PRBS generator, write the original values back into the read-modify-write address.
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Reconfiguratio n Address
(HEX)
Reconfiguratio n Bit
Attribute Name Related
Addresses
Attribute
Encoding
Bit
Encoding
Description
0x00C
0x13F
[0]
[3]
[3:0] prbs_ver prbs9_dwidth deser_factor
0xB prbs_9 prbs_15 prbs_23 prbs_31 prbs_7 prbs_9 prbs_15 prbs_23 prbs_31 prbs9_10b prbs9_64b
10
64
4'b0010
4'b0100
4'b1000
4'b0000
1'b0
1'b0
1'b0
1'b0
1'b1
1'b1
1'b0
4'b0001
4'b1110
Enable PRBS9 pattern
Enable PRBS15 pattern
Enable PRBS23 pattern
Enable PRBS31 pattern
Enable PRBS7 pattern
Enable PRBS9 pattern
Enable PRBS15 pattern
Enable PRBS23 pattern
Enable PRBS31 pattern
PRBS9 10-bit
PRBS9 64-bit
10-bit mode
64-bit mode
Related Information
on page 547
6.16.1.1. Enabling the PRBS Data Generator in non bonded designs
You must perform a sequence of read-modify-writes to addresses 0x006, 0x007,
0x008, and 0x110 to enable either the PRBS data generator. To enable either the
PRBS data generator, follow these steps:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x006 according to
Generators for bonded and non bonded designs
.
3. Perform a read-modify-write to address 0x007 according to
Generators for bonded and non bonded designs
.
4. Perform a read-modify-write to address 0x008 according to
Generators for bonded and non bonded designs
.
5. Perform a read-modify-write to address 0x110 with the specified width. This data width is either 64-bit or 10-bit.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable the PRBS generator, write the original values back into the read-modifywrite addresses in
Register Map for PRBS Generators for bonded and non bonded designs .
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Related Information
•
Steps to Perform Dynamic Reconfiguration
on page 516
•
on page 512
6.16.1.1.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in non bonded designs
Example 5. Enabling the PRBS9 pattern generator in 10-bit mode
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address x006[7:0] with the following bits: 8’b01- -
1100
3. Perform a read-modify-write to address x007[7:0] with the following bits: 8’b0010
- - - -
4. Perform a read-modify-write to address x008[7:0] with the following bits: 8’b -
000 - - - -
5. Perform a read-modify-write to address x110[7:0] with the following bits: 8’b - - -
- - 100
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note:
Example 6. Enabling the PRBS31 pattern generator in 64-bit mode
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address x006[7:0] with the following bits: 8’b01- -
0100
3. Perform a read-modify-write to address x007[7:0] with the following bits: 8’b0000
- - - -
4. Perform a read-modify-write to address x008[7:0] with the following bits: 8’b -
001 - - - -
5. Perform a read-modify-write to address x110[7:0] with the following bits: 8’b - - -
- - 011
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note:
A dash (-) indicates that the corresponding bit value should not be modified during read-modify-write.
A dash (-) indicates that the corresponding bit value should not be modified during read-modify-write.
Related Information
Steps to Perform Dynamic Reconfiguration
on page 516
6.16.1.2. Enabling the PRBS Data Generator in bonded designs
You must perform a sequence of read-modify-writes to addresses 0x006, 0x007,
0x008, and 0x110, 0x111and to enable either the PRBS data generator in bonded designs. To enable either the PRBS data generator, follow these steps:
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1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x006 according to
Generators for bonded and non bonded designs
.
3. Perform a read-modify-write to address 0x007 according to
Generators for bonded and non bonded designs
.
4. Perform a read-modify-write to address 0x008 according to
Generators for bonded and non bonded designs
.
5. Perform a read-modify-write to address 0x110 with the specified width. This data width is either 64-bit or 10-bit.
6. Perform a read-modify-write to address 0x111 according to
Generators for bonded and non bonded designs
. You must read and save the value in the register 0x111[5:0] before changing the x1_clock_source_sel
setting to xN non bonding.
7. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable the PRBS generator, write the original values back into the read-modifywrite addresses in
Register Map for PRBS Generators for bonded and non bonded designs .
6.16.1.2.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in bonded designs
Example 7. Enabling the PRBS9 pattern generator in 10-bit mode
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address x006[7:0] with the following bits: 8’b01- -
1100
3. Perform a read-modify-write to address x007[7:0] with the following bits: 8’b0010
- - - -
4. Perform a read-modify-write to address x008[7:0] with the following bits: 8’b -
000 - - - -
5. Perform a read-modify-write to address x110[7:0] with the following bits: 8’b - - -
- - 100
6. Perform a read-modify-write to address x111[5:0] with the following bits:
8'b---11000. You must read and save the value in the register 0x111[5:0] before changing the x1_clock_source_sel
setting to xN non bonding.
7. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note: A dash (-) indicates that the corresponding bit value should not be modified during read-modify-write.
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Example 8. Enabling the PRBS31 pattern generator in 64-bit mode
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address x006[7:0] with the following bits: 8’b01- -
0100
3. Perform a read-modify-write to address x007[7:0] with the following bits: 8’b0000
- - - -
4. Perform a read-modify-write to address x008[7:0] with the following bits: 8’b -
001 - - - -
5. Perform a read-modify-write to address x110[7:0] with the following bits: 8’b - - -
- - 011
6. Perform a read-modify-write to address x111[5:0] with the following bits:
8'b---11000. You must read and save the value in the register 0x111[5:0] before changing the x1_clock_source_sel
setting to xN non bonding.
7. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note: A dash (-) indicates that the corresponding bit value should not be modified during read-modify-write.
6.16.1.3. Enabling the PRBS Data Checker in non bonded design
You must perform a sequence of read-modify-writes to the Transceiver Native PHY reconfiguration interface to enable the PRBS checker. You must perform read-modifywrites to addresses 0x00A, 0x00B, 0x00C, and 0x13F. To enable the PRBS checker, follow these steps:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x00A with a value of 1'b1 to bit[7].
3. Perform a read-modify-write to address 0x00B according to Register Map for PRBS
Checker for bonded and non bonded designs .
4. Perform a read-modify-write to address 0x00C according to Register Map for PRBS
Checker for bonded and non bonded designs .
5. Perform a read-modify-write to address 0x13F according to
Checker for bonded and non bonded designs .
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable the PRBS verifier write the original values back into the read-modifywrite addresses listed above.
Related Information
Steps to Perform Dynamic Reconfiguration
on page 516
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6.16.1.3.1. Examples of Enabling the PRBS Data Checker
Example 9. Enabling the PRBS9 pattern checker in 10-bit mode
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address x00A[7:0] with the following bits: 8’b1- -
- - - - -
3. Perform a read-modify-write to address x00B[7:0] with the following bits: 8’b0010
00 - -
4. Perform a read-modify-write to address x00C[7:0] with the following bits: 8’b - - -
- 1 - - 0
5. Perform a read-modify-write to address x13F[7:0] with the following bits: 8’b - - -
- 0001
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note: A dash (-) indicates that the corresponding bit value should not be modified
Example 10. Enabling the PRBS31 pattern checker in 64-bit mode
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address x00A[7:0] with the following bits: 8’b1- -
- - - - -
3. Perform a read-modify-write to address x00B[7:0] with the following bits: 8’b0000
11 - -
4. Perform a read-modify-write to address x00C[7:0] with the following bits: 8’b - - -
- - - - 1
5. Perform a read-modify-write to address x13F[7:0] with the following bits: 8’b - - -
- 1110
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note: A dash (-) indicates that the corresponding bit value should not be modified
Use the PRBS soft accumulators to count the number of accumulated bits and errors when the hard PRBS blocks are used. For more details about using the accumulators and reading the error values, refer to the "PRBS Soft Accumulators" section.
Related Information
•
on page 547
•
Steps to Perform Dynamic Reconfiguration
on page 516
6.16.1.4. Enabling the PRBS Checker in bonded designs
You must perform a sequence of read-modify-writes to addresses 0x00A, 0x00B,
0x00C, 0x13F, 0x111 and to enable the PRBS data checker in bonded designs. To enable the PRBS checker, follow these steps:
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1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x00A with a value of 1'b1 to bit[7].
3. Perform a read-modify-write to address 0x00B according to Register Map for PRBS
Checker for bonded and non bonded designs .
4. Perform a read-modify-write to address 0x00C according to Register Map for PRBS
Checker for bonded and non bonded designs .
5. Perform a read-modify-write to address 0x13F according to
Checker for bonded and non bonded designs .
6. Perform a read-modify-write to address 0x111 according to
Checker for bonded and non bonded designs .
7. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable the PRBS verifier write the original values back into the read-modifywrite addresses listed above.
6.16.1.5. Disabling/Enabling PRBS Pattern Inversion
The default PRBS pattern is inverted for both the PRBS generator and checker. You can disable pattern inversion for PRBS data leaving or entering the PRBS data pattern
generator and checker, respectively. Table 294 on page 558 shows the addresses and
bits to control the inversion of the PRBS generator or checker. To disable the PRBS pattern inversion for the PRBS generator or checker, follow these steps:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. To disable the inverted PRBS pattern leaving the PRBS generator, perform a readmodify-write to bit[2] with a value of 1'b1 to address 0x7.
3. To disable the inverted PRBS pattern entering the PRBS checker, perform a readmodify-write to bit[4] with a value of 1'b1 to address 0xA.
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Table 294.
Register Map for PRBS Pattern Inversion
Reconfiguration
Address (HEX)
0x7
Reconfiguration Bit
[2]
Attribute Name tx_static_polarity_inversion
Bit Encoding
1'b1
1'b0
0xA [4] rx_static_polarity_inversion 1'b1
1'b0
Description
Disables PRBS inversion
Enables PRBS inversion
(default)
Disables PRBS inversion
Enables PRBS inversion
(default)
Related Information
Steps to Perform Dynamic Reconfiguration
on page 516
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6.16.2. Using Pseudo Random Pattern Mode
You can use the Arria 10 Pseudo Random Pattern (PRP) generator and verifier in the scrambler and descrambler to generate random data pattern and seed that the scrambler can use. PRP mode is a test mode of the scrambler. Two seeds are available to seed the scrambler: all 0s or two local fault-ordered sets. The seed is used in the scrambler to produce the pattern. The r_tx_data_pat_sel
is the data pattern that the scrambler will scramble. PRP is only available when the scrambler is enabled. The
PRP verifier shares the rx_prbs_err
error signal with PRBS. The error count can be read out from the corresponding registers.
6.16.2.1. Enabling Pseudo Random Pattern Mode
You must perform a sequence of read-modify-writes to the reconfiguration interface to enable the Pseudo Random Pattern. The read-modify-writes are required to addresses
0x082, 0x097, and 0x0AC. To enable the Pseudo Random Pattern, complete the following steps:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x082 according to
559.
3. Perform a read-modify-write to address 0x097 according to
559.
4. Perform a read-modify-write to address 0x0AC according to Table 295
on page
559.
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable the PRP verifier, write the original values back to the read-modify-write addresses listed above.
Table 295.
Register Map for Pseudo Random Pattern Mode
Reconfiguration
Address (HEX)
0x72
Reconfiguration
Bit
[7:0]
Attribute Name r_tx_seed_a[7:0]
Bit Encoding Description
0x73
0x74
0x75
0x76
0x77
0x78
0x79
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[1:0] r_tx_seed_a[15:8] r_tx_seed_a[23:16] r_tx_seed_a[31:24] r_tx_seed_a[39:32] r_tx_seed_a[47:40] r_tx_seed_a[55:48] r_tx_seed_a[57:56]
Seed A value bit[7:0]
Seed A value bit[15:8]
Seed A value bit[23:16]
Seed A value bit[31:24]
Seed A value bit[39:32]
Seed A value bit[47:40]
Seed A value bit[55:48]
Seed A value bit[57:56] continued...
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Reconfiguration
Address (HEX)
0x7A
Reconfiguration
Bit
[7:0]
Attribute Name r_tx_seed_b[7:0]
Bit Encoding Description
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[1:0] r_tx_seed_b[15:8] r_tx_seed_b[23:16] r_tx_seed_b[31:24] r_tx_seed_b[39:32] r_tx_seed_b[47:40] r_tx_seed_b[55:48] r_tx_seed_b[57:56]
0x82 [0] r_tx_data_pat_sel
0x97
0xAC
0xD7
0xD8
[1]
[3]
[2]
[0]
[7:0]
[7:0] r_tx_test_pat_sel r_tx_test_en r_rx_test_en r_rx_test_pat_sel random_err_cnt[7:0] random_err_cnt[7:0]
Related Information
Steps to Perform Dynamic Reconfiguration
on page 516
1'b0
1'b1
1'b0
1'b1
1'b1
1'b0 Pseudo random
Error count
6.17. Timing Closure Recommendations
Intel recommends that you enable the multiple reconfiguration profiles feature in the
Native PHY IP core if any of the modified or target configurations involve changes to
PCS settings. Using multiple reconfiguration profiles is optional if the reconfiguration involves changes to only PMA settings such as PLL switching, CGB divider switching, and refclk switching. When you enable multiple reconfiguration profiles, the Quartus
Prime TimeQuest Timing Analyzer includes the necessary PCS timing arcs for all profiles (initial profile and target profiles) during timing driven compilation. These timing arcs make the timing more accurate.
Seed B value bit[7:0]
Seed B value bit[15:8]
Seed B value bit[23:16]
Seed B value bit[31:24]
Seed B value bit[39:32]
Seed B value bit[47:40]
Seed B value bit[55:48]
Seed B value bit[57:56]
2 local faults
0's
Pseudo Random
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When performing a dynamic reconfiguration, you must:
• Include constraints to create the extra clocks for all modified or target configurations at the PCS-FPGA fabric interface. Clocks for the base configuration are created by the Quartus Prime software. These clocks enable the Quartus Prime software to perform static timing analysis for all the transceiver configurations and their corresponding FPGA fabric core logic blocks.
• Include the necessary false paths between the PCS – FPGA fabric interface and the core logic.
For example, you can perform dynamic reconfiguration to switch the datapath from
Standard PCS to Enhanced PCS using the multiple reconfiguration profiles feature. In the following example, the base configuration uses the Standard PCS (data rate =
1.25 Gbps, PCS-PMA width = 10) and drives core logic A in the FPGA fabric. The target or modified configuration is configured to use the Enhanced PCS (data rate = 12.5
Gbps, PCS-PMA width = 64) and drives core logic B in the FPGA fabric.
Figure 280. Using Multiple Reconfiguration Profiles
Transceiver Channel
Transmitter (TX)
FPGA Fabric tx_clkout Core Logic (A) for Standard
PCS
Receiver (RX)
Core Logic (B) for Enhanced
PCS rx_clkout
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To enable the Quartus Prime software to close timing more accurately in this example, the following constraints must be created:
• create_clock -name tx_clkout_enh -period 5.12 [get_pins
{native_inst|xcvr_native_a10_0| g_xcvr_native_insts[0].twentynm_xcvr_native_inst| twentynm_xcvr_native_inst|inst_twentynm_pcs| gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_p
ld_pcs_interface|pld_pcs_tx_clk_out}] -add
This constraint creates the tx_clkout
clock that is used to clock the core logic B in the FPGA fabric.
• create_clock -name rx_clkout_enh –period 5.12 [get_pins
{native_inst|xcvr_native_a10_0| g_xcvr_native_insts[0].twentynm_xcvr_native_inst| twentynm_xcvr_native_inst|inst_twentynm_pcs| gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_p
ld_pcs_interface|pld_pcs_rx_clk_out}] -add
This constraint creates the rx_clkout
clock that is used to clock the core logic B in the FPGA fabric.
• set_false_path -from [get_clocks {tx_clkout_enh}] -to
[get_registers <Core Logic A>]
Based on how the clocks are connected in the design, you might have to include additional constraints to set false paths from the registers in the core logic to the clocks.
• set_false_path -from [get_clocks {rx_clkout_enh}] -to
[get_registers <Core Logic A>]
Based on how the clocks are connected in the design, you may have to include additional constraints to set false paths from the registers in the core logic to the clocks.
• set_false_path -from [get_clocks {tx_clkout}] -to
[get_registers <Core Logic B>]
Based on how the clocks are connected in the design, you may have to include additional constraints to set false paths from the registers in the core logic to the clocks.
• set_false_path -from [get_clocks {rx_clkout}] -to
[get_registers <Core Logic B>]
Based on how the clocks are connected in the design, you may have to include additional constraints to set false paths from the registers in the core logic to the clocks.
Note: If any of the profile or configuration switch involves switching from FIFO to the register mode, then the false paths should be set between the PCS-PMA interface register and the core logic because the common clock point is within the PCS-PMA interface.
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Note:
For example, if the base configuration of the above case is configured for the TX and
RX FIFOs in the Register Mode, the following constraint needs to be created:
• set_false_path -from [get_registers {native:native_inst| native_altera_xcvr_native_a10_150_lzjn6xi:xcvr_native_a10_0| twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_nati
ve_inst| twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst| twentynm_pcs_rev_20nm5es:inst_twentynm_pcs| gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_p
ld_pcs_interface~pma_tx_pma_clk_reg.reg}] -to [get_registers
<Core Logic B>]
• set_false_path -from [get_registers {native:native_inst| native_altera_xcvr_native_a10_150_lzjn6xi:xcvr_native_a10_0| twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_nati
ve_inst| twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst| twentynm_pcs_rev_20nm5es:inst_twentynm_pcs| gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_p
ld_pcs_interface~pma_rx_pma_clk_reg.reg}] -to [get_registers
<Core Logic B>]
When the dynamic reconfiguration (multi profiles) is enabled, do not move or rename the IP directory. Moving the IP location causes Quartus to fail to pick up the configuration profiles. If the IP directory is changed, the default configuration can be successfully time constrained and analyzed, but the non-default configuration has timing issues as the timing arc may be missing.
6.18. Unsupported Features
The following features are not supported by either the Transceiver Native PHY IP core or the PLL IP reconfiguration interface:
• Reconfiguration from a bonded configuration to a non-bonded configuration, or vice versa
• Reconfiguration from a bonded protocol to another bonded protocol
• Reconfiguration from PCIe (with Hard IP) to PCIe (without Hard IP) or non-PCIe bonded protocol switching
• Switching between bonding schemes, such as xN to feedback compensation
• Master CGB reconfiguration
• Switching between two master CGBs
• Serialization factor changes on bonded channels
• TX PLL switching on bonded channels
Note: Transceiver Native PHY IP non-bonded configuration to another Transceiver Native PHY
IP non-bonded configuration is supported.
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6.19. Arria 10 Transceiver Register Map
The transceiver register map provides a list of available PCS, PMA, and PLL addresses that are used in the reconfiguration process.
Use the register map in conjunction with a transceiver configuration file generated by the Arria 10 Native PHY IP core. This configuration file includes details about the registers that are set for a specific transceiver configuration. Do not use the register map to locate and modify specific registers in the transceiver. Doing so may result in an illegal configuration. Refer to a valid transceiver configuration file for legal register values and combinations.
The register map is provided as an Excel spreadsheet for easy search and filtering.
Related Information
Arria 10 Transceiver Register Map
6.20. Reconfiguration Interface and Dynamic Revision History
Changes Document
Version
2018.06.15
2017.11.06
2016.10.31
2016.05.02
2015.12.18
Made the following change:
• Added instructions on how to enable the Transceiver Toolkit capability in the Native PHY IP to
Dynamic Reconfiguration Parameters.
Made the following changes:
• Updated the note in "Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow" topic to "The
PMA analog settings are governed by a set of rules. Not all combinations of V
OD
and pre-emphasis are valid. Please refer to Arria 10 Pre-Emphasis and Output Swing Settings for current valid settings. Also, refer to "Analog Parameter Settings" and setup guidelines on post_tap polarity settings."
• Updated the description of bit [25:16] in table "Mapping of SystemVerilog Configuration File Line" to
"DPRIO address. Refer to Intel Arria 10 Transceiver Register Map for details of the address."
• Changes the configurations file path to "
<IP instance name>\altera_xcvr_<IP type>_a10_<quartus version>\synth\reconfig
".
• Added Examples 1 and 2 in "fPLL Reference Clock Switching" topic.
Made the following changes:
• "VGA" PMA Analog Feature added in "PMA Analog Settings that are Channel or System Dependent" table.
• Updated the value of AC Gain Control of High Gain Mode CTLE parameter to
radp_ctle_acgain_4s_0 to radp_ctle_acgain_4s_28 in the "Analog PMA Settings (Optional) for
Dynamic Reconfiguration" table.
• Updated the value of Slew Rate Control parameter to slew_r0 to slew_r5 in the "Analog PMA
Settings (Optional) for Dynamic Reconfiguration" table.
Made the following changes
• Removed the topic "On-Die Instrumentation" and related information from the user guide.
• Edited "Native PHY IP" with "Native PHY IP and ATX PLL IP" wherever necessary.
• Edited "Embedded Reconfiguration Steamer" topic.
• Edited the "Arbitration" topic.
• Edited the "Using PRBS and Square Wave Data Pattern Generator and Checker" for bonded as well as non bonded designs. Also added all the examples for each case.
• Updated "Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow" topic.
Made the following changes: continued...
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Document
Version
2015.11.02
2015.05.11
2014.12.15
Changes
• Updated the switching bit register definitions in the “Register Map for Switching fPLL Reference
Clock Inputs” table
• Updated the “Bit Values to Be Set” table in the “Enabling and Disabling Loopback Modes Using
Direct Reconfiguration Flow” section.
Made the following changes:
• Changed the procedure in the "Steps to Perform Dynamic Reconfiguration" section to be more general, allowing procedures in other sections to refer to it.
• Added the "Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow" section.
• Added the "Analog PMA Settings (Optional) for Dynamic Reconfiguration" table.
• Removed four tables from the "On-Die Instrumentation" section.
• Changed the procedure in the "Using ODI to Build On-chip Eye Process" section.
• Added entry to “Arria 10 Dynamic Reconfiguration Feature Support” table
• Improved description of access requests in the “Interacting with the Reconfiguration Interface” section
• Updated the “Configuration Files” section
• Added information to the “Embedded Reconfiguration Streamer” section
• Modified the “Arria 10 Native PHY with Embedded Streamer” figure
• Described the two levels of arbitration in the “Arbitration” section
• Converted the “Steps to Perform Dynamic Reconfiguration” figure in the “Steps to Perform Dynamic
Reconfiguration” section to a set of procedures
• Added the “Reset Recommendations for Dynamic Reconfiguration” section
• Added information about the PMA analog settings to the “Changing PMA Analog Parameters” section
• Added steps to the procedure in the “Changing CTLE Settings in Manual Mode” section
• Updated the steps in the procedures in the “Serial Loopback Mode” section
• Changed title of “IP Guided Reconfiguration Flow” to “Native PHY or PLL IP Guided Reconfiguration
Flow”
• Updated the steps in the procedures in the “Native PHY or PLL IP Guided Reconfiguration Flow” and added a note following the first procedure
• Updated the steps in the procedure in the “Switching Transmitter PLL” section
• Updated the steps in the procedures in the “ATX Reference Clock,” “fPLL Reference Clock,” and “CDR and CMU Reference Clock,” sections
• Updated the “Avalon Interface Parameters” table to show which parameter editors are valid for each parameter
• Corrected values in step 1a in the “Start Pattern Checker” section
• Added information about hard PRBS blocks to the “PRBS Soft Accumulators” section
• Added list of PRBS checker control and status signals to the “Using PRBS and Square Wave Data
Pattern Generator and Checker” section
• Updated the steps in the procedures in the “Enabling the PRBS and Square Wave Data Generator” and the “Enabling the PRBS and Data Checker” sections
• Updated the steps in the procedures in the “Examples of Enabling the PRBS9 and PRBS31 Pattern
Generators” and the “Examples of Enabling the PRBS Data Checker” sections
• Updated the steps in the procedure in the “Enabling Pseudo Random Pattern Mode” section
Made the following changes:
• Completely revised, updated, and reorganized the chapter.
• Added the following new sections:
— Multiple Reconfiguration Profiles
— Embedded Reconfiguration Streamer
— Arbitration
— Enabling and Disabling Loopback Modes
— IP Guided Reconfiguration Flow
— On-Die Instrumentation
— Altera Debug Master Endpoint
— ODI Acceleration Logic
Made the following changes: continued...
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Document
Version
2014.10.08
2014.08.15
2013.12.02
Changes
• Re-organized the chapter outline to better match the reconfiguration flow.
• Updated the introduction section of the chapter to better explain dynamic reconfiguration use cases.
• Added figures Reconfiguration Interface in Arria 10 Transceiver IP Cores and Top Level Signals of
the Reconfiguration Interface.
• Added Timing Closure Recommendations section.
• Changed Max Vod Value in Table: PMA Analog Feature Offsets.
• Updated Table: Valid Maximum Pre-Emphasis Settings.
• Updated the Ports and Parameters section:
— Updated the description to better indicate the difference between "Shared" and "Not Shared" reconfiguration interface.
— Updated Avalon clock frequency to 100 MHz.
— Updated the signal names in Table: Reconfiguration Interface Ports with Shared Reconfiguration
Interface Enabled and Reconfiguration Interface Ports with Shared Reconfiguration Interface
Disabled.
• Added a description in Interfacing with Reconfiguration Interface section to indicate the steps to request access of the Avalon-MM interface.
• Updated steps in Performing a Read to the Reconfiguration Interface and Performing a Write to the
Reconfiguration Interface sections.
• Updated Using Configuration Files section to with a detailed description of when to use configuration files.
• Updated the steps in Switching Transmitter PLL, Switching Reference Clocks, and Changing PMA
Analog Parameters sections.
Made the following changes:
• Minor editorial changes. Corrected typographical errors in Ports and Parameters and Native PHY IP
Core Embedded Debug sections.
• Corrected an error in "Example 6-1: Steps to Merge Transceiver Channels" in Document Channel
Merging Requirements section.
Made the following changes:
• Updated MegaWizard references to IP Catalog or Parameter Editor.
• Updated table "Avalon Interface Parameters"
— Added description for Altera Debug Master Endpoint.
— Added Embedded Debug Parameters.
• Corrected typos and updated values in table "PMA Analog Feature Offsets".
• Added a new table "Valid Maximum Pre-Emphasis Settings" in Changing Analog Parameters Section.
• Updated the description for 0xB reconfiguration address bit[7:5] in table "PRBS Checker Offsets".
• Updated the Unsupported Features section and removed some unsupported features.
• Changed the name of Transceiver and PLL Address Map to Arria 10 Transceiver Register Map.
Updated the description to better explain the scope of the register map.
• Added a new section for Embedded Debug feature.
Initial release.
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7. Calibration
Note:
Transceivers include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations. Arria 10 transceiver uses hardened Precision Signal Integrity Calibration Engine (PreSICE) to perform calibration routines.
Power-up Calibration and User Recalibration are the main types of calibration.
• Power-up calibration occurs automatically at device power-up. It runs during device configuration.
• If you perform dynamic reconfiguration, then you must perform User
Recalibration. In this case, you are responsible for enabling the required calibration sequence.
If you are recalibrating your ATX PLL or fPLL, follow the ATX PLL-to-ATX PLL or fPLL-to-
ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
Arria 10 devices use CLKUSR for transceiver calibration. To successfully complete the calibration process, the CLKUSR clock must be stable and free running at the start of
FPGA configuration. Also, all reference clocks driving transceiver PLLs (ATX PLL, fPLL,
CDR/CMU PLL) must be stable and free running at start of FPGA configuration. For more information about
CLKUSR
pin requirements, refer to the Arria 10 GX, GT, and
SX Device Family Pin Connection Guidelines.
Related Information
•
Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs
on page 349
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
7.1. Reconfiguration Interface and Arbitration with PreSICE
Calibration Engine
In Arria 10 devices, calibration is performed using the Precision Signal Integrity
Calibration Engine (PreSICE). The PreSICE includes an Avalon-MM interface to access the transceiver channel and PLL programmable registers. This Avalon-MM interface includes a communication mechanism that enables you to request specific calibration sequences from the calibration controller.
The PreSICE Avalon-MM interface and user Avalon-MM reconfiguration interface both share an internal configuration bus. This bus is arbitrated to gain access to the transceiver channel and PLL programmable registers, and the calibration registers.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
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There are two ways to check who has the access to the internal configuration bus:
• Use reconfig_waitrequest
• Use capability registers
The Native PHY IP core and PLL default setting is to use reconfig_waitrequest
.
When PreSICE controls the internal configuration bus, the reconfig_waitrequest from the internal configuration bus is high. When user access is granted, the reconfig_waitrequest
from the internal configuration bus goes low. At the Avalon-
MM reconfiguration interface, the reconfig_waitrequest
can come from a few places inside Native PHY IP core. For example, it can come from the internal configuration bus, streamer, and so on. They are bundled together and become single reconfig_waitrequest
at the Avalon-MM reconfiguration interface. The reconfig_address
determines which reconfig_waitrequest
to show at the
Avalon-MM reconfiguration interface. After you return the internal configuration bus to
PreSICE, the reconfig_waitrequest
from the internal configuration bus is high. If you set the reconfig_address
to the streamer offset address at the Avalon-MM reconfiguration interface during calibration, the reconfig_waitrequest
can be low before calibration is finished. If you keep the reconfig_address internal configuration bus offset address during calibration, the
the same as the reconfig_waitrequest
at the Avalon-MM reconfiguration interface is high until
PreSICE returns the internal configuration bus to you. It is important to keep reconfig_address static during calibration.
To use capability registers to check bus arbitration, you do the following to generate the IP:
1. Select Enable dynamic reconfiguration from the Dynamic Reconfiguration tab.
2. Select both the Separate reconfig_waitrequest from the status of AVMM
arbitration with PreSICE and Enable control and status registers options.
You can read the capability register 0x281[2] to check who is controlling the channel access, and read the capability register 0x280[2] to check who is controlling the PLL access. When Separate reconfig_waitrequest from the status of AVMM
arbitration with PreSICE and Enable control and status registers are enabled, the reconfig_waitrequest
is not asserted high when PreSICE controls the internal configuration bus.
To return the internal configuration bus to PreSICE:
• In order to trigger user re-calibration:
— Write 0x01 to offset address 0x000 [7:0], user re-calibration has to request through offset address 0x100.
• In order to trigger DFE adaptation:
— Write 0x03 to offset address 0x000 [7:0], DFE adaptation triggering has to enable through 0x100[6].
• If you no longer need to use the internal reconfiguration bus:
— Write 0x03 to offset address 0x000 [7:0].
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To check if the calibration process is running, do one of the following:
• Monitor the pll_cal_busy
, tx_cal_busy
, and rx_cal_busy
signals.
• Read the
*_cal_busy
signal status from the capability registers.
The
*_cal_busy
signals remain asserted as long as the calibration process is running. To check whether or not calibration is done, you can read the capability registers or check the
*_cal_busy
signals. The reconfig_waitrequest
from the
Avalon-MM reconfiguration interface is not a reliable indicator to check whether or not calibration is done. If you write 0x2 to 0x0 during calibration, PreSICE can stop the calibration process and return the internal configuration bus back to you; therefore, calibration is not done while the reconfig_waitrequest
is low. The PMA tx_cal_busy
and rx_cal_busy
are from the same internal node which cannot be separated from the hardware. Configure the capability register 0x281[5:4] to enable or disable tx_cal_busy
or rx_cal_busy
individually through the Avalon-MM reconfiguration interface.
Related Information
•
on page 512
• Avalon Interface Specifications
•
Reconfiguration Interface and Dynamic Reconfiguration Chapter
on page 502
7.2. Calibration Registers
The Arria 10 transceiver PMA and PLLs include the following types of registers for calibration:
• Avalon-MM interface arbitration registers
• Calibration enable registers
• Capability registers
• Rate switch flag registers
The Avalon-MM interface arbitration registers enable you to request internal configuration bus access.
The PMA and PLL calibration enable registers for user recalibration are mapped to offset address 0x100. All calibration enable registers are self-cleared after the calibration process is completed.
The tx_cal_busy
, rx_cal_busy
, ATX PLL pll_cal_busy
, and fPLL pll_cal_busy
signals are available from the capability registers.
The rate switch flag registers are only used for CDR rate change.
7.2.1. Avalon-MM Interface Arbitration Registers
Table 296.
Avalon-MM Interface Arbitration Registers
Bit
[0]
Offset Address
0x0 (64)
Description
This bit arbitrates the control of Avalon-MM interface.
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Note:
Bit
[1]
Offset Address
0x0
Description
• Set this bit to 0 to request control of the internal configuration bus by user.
• Set this bit to 1 to pass the internal configuration bus control to
PreSICE.
This bit indicates whether or not calibration is done. This is the inverted cal_busy
signal. You can write to this bit; however, if you accidentally write 0x0 without enabling any calibration bit in
0x100, PreSICE may not set this bit to 0x1, and cal_busy
remain high. Channel reset is triggered if reset controller.
cal_busy
is connected to the
• 0x1 = calibration completed.
• 0x0 = calibration not completed.
The cal_busy
signal is activated two clock cycles after you write 0x0 to this bit.
During calibration when Nios is controlling the internal configuration bus, you can not read offset address 0x0. However, you can write 0x0 to offset address 0x0[0] to request bus access.
7.2.2. Transceiver Channel Calibration Registers
Table 297.
Transceiver Channel PMA Calibration Registers
5
6
3
4
Bit
0
1
2
7
PMA Calibration Enable Register Offset Address 0x100
Reserved
PMA RX calibration enable
Reserved
Reserved
Reserved
PMA TX calibration enable
Write 1'b0 to 0x100 [6] when you enable any PMA channel calibration to ensure adaptation triggering request is disable.
Reserved
7.2.3. Fractional PLL Calibration Registers
Table 298.
Fractional PLL Calibration Registers
Bit
0
1 fPLL Calibration Enable Register Offset Address 0x100
Reserved fPLL calibration enable. Set 1 to enable calibration.
(64) The transceiver channel, ATX PLL, and fPLL use the same offset address.
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7.2.4. ATX PLL Calibration Registers
Table 299.
ATX PLL Calibration Registers
Bit
0
1
ATX PLL Calibration Enable Register Offset Address 0x100
ATX PLL calibration enable. Set 1 to enable calibration.
Reserved
During calibration when reconfig_waitrequest calibration enable registers.
is high, you cannot read or write
To enable calibration, you must perform a read-modify-write on offset address 0x100.
The following steps are an example of how to enable the ATX PLL calibration enable bit:
1. Read the offset address 0x100.
2. Keep the value from MSB[7:1] and set LSB[0] to 1.
3. Write new value to offset address 0x100.
7.2.5. Capability Registers
Capability registers allow you to read calibration status through the Avalon-MM reconfiguration interface. They are soft logic and reside in the FPGA fabric.
Reading capability registers does not require bus arbitration. You can read them during the calibration process.
To use capability registers to check calibration status, you must enable the capability registers when generating the Native PHY or PLL IP cores. To enable the capability registers, select the Enable capability registers option in the Dynamic
Reconfiguration tab.
The tx_cal_busy
and rx_cal_busy
signals from the hard PHY are from the same hardware and change state (high/low) concurrently during calibration. The register bits 0x281[5:4] are defined to solve this issue. This prevents a TX channel being affected by RX calibration, or an RX channel being affected by TX calibration. This feature cannot be enabled, when a Simplex TX and Simplex RX channel merging is involved. To merge a Simplex TX and a Simplex RX channel into one physical channel, refer to
Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks
on page
542.
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Rules to Build Customized Gating Logic to Separate tx_cal_busy and rx_cal_busy signals
Figure 281. An Example of an AND Gate used as Customized Logic
The customized gates shown in the following figure are an example and not a unique solution
Customized Gates reset
Simplex
TX tx_cal_busy_out_en
JTAG to
Avalon
Master
Bridge tx/rx_cal_busy_out tx_cal_busy Reset
Controller reset reset
Simplex
RX rx_cal_busy_out_en rx_cal_busy Reset
Contoller reset
The capability register is not available for merging a Simplex TX and a Simplex RX signal into the same physical channel. The tx_cal_busy_out
and rx_cal_busy_out
signals share the same port. So, you should build customized gating logic to separate them.
• The tx_cal_busy_out_en
signal enables the tx_cal_busy
output.
• The rx_cal_busy_out_en
signal enables the rx_cal_busy
output.
• At power up,
“1”.
tx_cal_busy_out_en
and rx_cal_busy_out_en
should be set to
• At normal operation:
— When the RX is calibrating, setting tx_cal_busy_out_en
to “0” and rx_cal_busy_out_en
to “1” disables tx_cal_busy, so the TX does not reset while RX is calibrating.
— When the TX is calibrating, setting rx_cal_busy_out_en
to “0” and tx_cal_busy_out_en
to “1” disables rx_cal_busy
, so the RX does not reset while TX is calibrating.
Table 300.
PMA Capability Registers for Calibration Status
0x281[5]
0x281[4]
0x281[2]
Bit Description
PMA channel rx_cal_busy
output enable. The power up default value is 0x1.
0x1: The rx_cal_busy
output and 0x281[1] are asserted high whenever PMA TX or RX calibration is running.
0x0: The rx_cal_busy
output or 0x281[1] is never asserted high.
PMA channel tx_cal_busy
output enable. The power up default value is 0x1.
0x1: The tx_cal_busy
output and 0x281[0] are asserted high whenever PMA TX or RX calibration is running.
0x0: The tx_cal_busy
output or 0x281[0] is never asserted high.
PreSICE Avalon-MM interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest of AVMM arbitration with PreSICE is enabled or not.
from the status
0x1: PreSICE is controlling the internal configuration bus.
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0x281[1]
0x281[0]
Bit Description
0x0: The user has control of the internal configuration bus.
PMA channel rx_cal_busy
active high
0x1: PMA RX calibration is running
0x0: PMA RX calibration is done
PMA channel tx_cal_busy
active high
0x1: PMA TX calibration is running
0x0: PMA TX calibration is done
The PMA 0x281[5:4] is used to isolate the TX and RX calibration busy status. If you want rx_cal_busy
unchanged during the TX calibration, you must set 0x281[5] to
0x0 before returning the bus to PreSICE. The channel RX is not reset due to the TX calibration. If you want tx_cal_busy
unchanged during the RX calibration, you must set 0x281[4] to 0x0 before returning the bus to PreSICE. The channel TX is not reset due to the RX calibration. If you accidentally write 0x00 to 0x281[5:4], tx_cal_busy and rx_cal_busy
are never activated to high in the user interface. Neither of the
0x281[1:0] registers go high either.
Table 301.
ATX PLL Capability Registers for Calibration Status
0x280[2]
0x280[1]
Bit Description
PreSICE Avalon-MM interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest of AVMM arbitration with PreSICE is enabled or not.
from the status
0x1: PreSICE is controlling the internal configuration bus.
0x0: The user has control of the internal configuration bus.
ATX PLL pll_cal_busy
0x1: ATX PLL calibration is running
0x0: ATX PLL calibration is done
Table 302.
fPLL Capability Registers for Calibration Status
0x280[2]
0x280[1]
Bit Description
PreSICE Avalon-MM interface control
0x1: PreSICE is controlling the internal configuration bus. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not.
0x0: The user has control of the internal configuration bus.
fPLL pll_cal_busy
0x1: fPLL calibration is running
0x0: fPLL calibration is done
7.2.6. Rate Switch Flag Register
The rate switch flag is for CDR charge pump calibration. Each SOF has CDR default charge pump settings. After power up, these settings are loaded into the PreSICE memory space. If you change the line rate, it may require new charge pump settings, which are stored into the Avalon-MM reconfiguration register space. During RX PMA calibration (including CDR), PreSICE needs to know which set of CDR charge pump setting to use.
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If you set 0x166[7] = 0x1, PreSICE assumes the setting in its memory space is still valid. If after a rate change you set 0x166[7]=0x0, PreSICE uses the setting from the
Avalon-MM reconfiguration register uploaded from the dynamic reconfiguration interface or MIF streamed in. After calibration, 0x166[7] = 0x1 is set automatically and PreSICE uses the settings in its memory space. The rate switch flag only tells
PreSICE where to obtain the CDR charge pump settings for CDR calibration. The rate switch flag should be used only when there is a rate change.
Multiple MIF files are required for rate change and reconfiguration. When the MIF, which you want to stream in, has CDR charge pump setting 0x139[7] and 0x133[7:5] that is different from the previous MIF, you need to recalibrate with 0x166[7]=0x0. If you stream in the whole MIF, the 0x166[7] is set to the correct value inside the MIF. If you stream in reduced MIF, you need to check if CDR charge pump setting 0x139[7] and 0x133[7:5] are inside the reduced MIF or not. If the reduced MIF has CDR charge pump setting 0x139[7] and 0x133[7:5] updated, you need to set 0x166[7]=0x0, if the reduced MIF does not include 0x139[7] and 0x133[7:5], you need to set
0x166[7]=0x1.
Table 303.
Rate Switch Flag Register for CDR Calibration
0x166[7]
Bit Description
Rate switch flag register. Power up default value is 0x1.
0x1, PreSICE uses the default CDR charge pump bandwidth from the default memory space.
0x0, PreSICE uses the CDR charge pump bandwidth setting from the DPRIO register space.
If you use the Avalon-MM reconfiguration interface to perform a rate change, you must write 0x0 to 0x166[7] before returning the bus to PreSICE.
7.3. Power-up Calibration
After the device is powered up and programmed, PreSICE automatically initiates the calibration process. The calibration process may continue during device programming.
The time required after device power-up to complete the calibration process can vary by device. The total time taken can extend into the user-mode. The cal_busy
signals deassert to indicate the completion of the calibration process. You must ensure that the transceiver reset sequence in your design waits for the calibration to complete before resetting the transceiver PLL and the transceiver channel.
The PreSICE may still control the internal configuration bus even after power-up calibration is complete. You can request access when needed. If a system has an fPLL, an ATX PLL, and channels, the fPLL cal_busy
signal goes low first. The ATX PLL cal_busy
signal goes low after the channels’ tx_cal_busy
and rx_cal_busy signals. Intel recommends that you wait until all requesting any access.
*_cal_busy
signals are low before
All power-up calibration starts from Vreg calibration for all banks and channels.
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Figure 282. Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels
For applications not using PCIe Hard IP, the power-up calibration starts from Vreg calibration for all banks and channels. Then, PreSICE calibration is done in the sequence as shown in the following figure.
Bank ...
Bank 2
Bank 1
ATX PLL Calibration
After All ATX PLLs Calibrated
Bank ...
Bank 2
Bank 1 fPLL Calibration
After All fPLLs Calibrated
Bank ...
Bank 2
Bank 1
RX PMA and TX PMA Calibration (1)
(1) CDR and CMU PLL calibration are part of RX
PMA calibration.
For applications using both PCIe Hard IP and non-PCIe channels, the power-up calibration sequence is:
1. Vreg calibration for all banks and channels.
2. Wait for PCIe reference clock toggle.
3. PCIe Hard IP 0 calibration (if used).
4. PCIe Hard IP 1 calibration (if used).
5. Calibration of all non-PCIe Hard IP channels in calibration sequence.
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Figure 283. Power-up Calibration Sequence for PCIe Hard IP and non-PCIe Channels
Vreg Calibration for All
Transceiver Banks and Channels
PCIe Channels Calibration
ATX PLL Calibration
Hard IP 1
Hard IP 0
After All ATX PLL Calibrated
Hard IP 1
Hard IP 0 fPLL Calibration
After All fPLL Calibrated
Hard IP 1
Hard IP 0
RX PMA and TX PMA Calibration (1)
Non-PCIe Channels Calibration
Bank ...
Bank 2
Bank 1
ATX PLL Calibration
After All ATX PLLs Calibrated
Bank ...
Bank 2
Bank 1 fPLL Calibration
After All fPLLs Calibrated
Bank ...
Bank 2
Bank 1
RX PMA and TX PMA Calibration (1)
(1) CDR and CMU PLL calibration are part of RX PMA calibration.
7.4. User Recalibration
User Recalibration is needed if below conditions are met:
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Note:
• During Device Power Up:
— During device power up,
CLKUSR
is asserted and running, but the transceiver reference clock remains deasserted until after the power up process is complete.
— During device power up,
CLKUSR
and the transceiver reference clock are asserted and running. When the device power up process is complete, the transceiver reference clock changes frequency. Either the transceiver reference clock could become unstable, or your application requires a different transceiver reference clock during normal operation, which could cause a data rate change.
• After a dynamic reconfiguration process that triggers a data rate change:
After device power up in normal operation, you reconfigure the transceiver data rate by changing the channel configurations or the PLLs, recalibrate the:
— ATX PLL if ATX PLL has new VCO frequency to support new data rate.
— fPLL if the fPLL has new VCO frequency to support new data rate.
Note: fPLL recalibration is not needed if the dynamic reconfiguration method used to achieve new data rate (new VCO frequency) is done using the fPLL L counter /1,2,4,8 division factor.
— CDU/CMU as TX PLL. You must recalibrate the RX PMA of the channel which uses the CMU as TX PLL.
— RX PMA and TX PMA channel if the transceiver configuration changes to support new data rates.
• Other conditions that require a user recalibration:
— Recalibrate the fPLL if the fPLL is connected as a second PLL (downstream cascaded PLL). The downstream fPLL received the reference clock from the upstream PLL (could be from fPLL/ CDR). Recalibrating the second fPLL is important especially if the upstream PLL output clock (which is the downstream fPLL's reference clock) is not present or stable during power-up calibration.
— For ATX PLL or fPLL used to drive PLL feedback compensation bonding, recalibrate the PLL after power up calibration.
If you are recalibrating your ATX PLL or fPLL, follow the ATX PLL-to-ATX PLL or fPLL-to-
ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
You can initiate the recalibration process by writing to the specific recalibration registers. You must also reset the transceivers after performing user recalibration. For example, if you perform data rate auto-negotiation that involves PLL reconfiguration, and PLL and channel interface switching, then you must reset the transceivers.
The proper reset sequence is required after calibration. Intel recommends you use the
Transceiver PHY Reset Controller which has tx_cal_busy
and rx_cal_busy
inputs and follow Intel's recommended reset sequence. You need to connect tx_cal_busy and rx_cal_busy
from the Native PHY IP core outputs to the reset controller inputs in your design. Reset upon calibration is automatically processed when you perform user recalibration.
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Follow these steps to perform user recalibration:
1. Request internal configuration bus user access to the calibration registers by writing 0x2 to offset address 0x0[7:0].
2. Wait for reconfig_waitrequest
to be deasserted (logic low). Or wait until capability register of PreSICE Avalon-MM interface control =0x0. The avmm_busy status register is 0x281[2] for PMA channel calibration and 0x280[2] for ATX PLL and fPLL calibration.
3. Set the required calibration enable bits by doing Read-Modify-Write the proper value to offset address 0x100. You must also set the 0x100 [6] to 0x0 when you enable any PMA channel calibration to ensure adaptation triggering is disabled.
4. Set rate switch flag register for PMA calibration, skip this step for ATX PLL and fPLL calibration.
• Read-Modify-Write 0x1 to offset address 0x166[7] if no CDR rate switch.
• Read-Modify-Write 0x0 to offset address 0x166[7] if switched rate with different CDR bandwidth setting.
5. Set the proper value to capability register 0x281[5:4] for PMA calibration to enable/disable tx_cal_busy
or rx_cal_busy
output.
• To enable rx_cal_busy
, Read-Modify-Write 0x1 to 0x281[5].
• To disable rx_cal_busy
, Read-Modify-Write 0x0 to 0x281[5].
• To enable tx_cal_busy
, Read-Modify-Write 0x1 to 0x281[4].
• To disable tx_cal_busy
, Read-Modify-Write 0x0 to 0x281[4].
6. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0]. Recalibration is in progress until the cal_busy
signals are deasserted (logic low).
7. Periodically check the
*cal_busy
output signals or read the capability registers to check
*cal_busy
status until calibration is complete.
Related Information
•
on page 418
•
Implementing PLL Feedback Compensation Bonding Mode
on page 405
•
Implementing PLL Cascading on page 408
•
Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs
on page 349
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7.4.1. Recalibration After Transceiver Reference Clock Frequency or Data
Rate Change
Figure 284. Recalibration Sequence when the Transceiver Reference Clock or Data Rate
Changes
ATX PLL Calibration
fPLL Calibration
PMA RX
Calibration (1)
PMA TX
Calibration (2)
Calibration
Done
Note:
(1) If you are using the CDR/CMU PLL, you need to trigger RX PMA recalibration.
(2) If you are using the CMU PLL, you need to trigger RX PMA recalibration
followed by a TX PMA recalibration.
7.4.1.1. User Recalibration
User recalibration requires access to the internal configuration bus and calibration registers through the Avalon-MM reconfiguration interface. Follow the steps below to perform a user recalibration.
1. Proceed to the next step if ATX PLL is not used in your application, otherwise perform the ATX PLL calibration process: a. Request access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
b. Wait for reconfig_waitrequest
to deassert (logic low), or wait until capability register of PreSICE Avalon-MM interface control 0x280[2]=0x0.
c. Read-Modify-Write 0x1 to the offset address 0x100[0] of the ATX PLL.
d. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
e. Periodically check the
*cal_busy
output signals or read the capability registers 0x280[1] to check
*cal_busy
status until calibration is complete.
If you are recalibrating your ATX PLL and have adjacent ATX PLL used on the same side of the device, follow the ATX PLL-to-ATX PLL spacing guideline as stated in the
"Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
2. Proceed to the next step if fPLL is not used in your application, otherwise perform the fPLL user recalibration process:
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a. Access the internal configuration bus by writing 0x2 to offset address
0x0[7:0].
b. Wait for reconfig_waitrequest
to deassert (logic low), or wait until capability register of PreSICE Avalon-MM interface control 0x280[2]=0x0.
c. Read-Modify-Write 0x1 to the offset address 0x100[1] of the fPLL.
d. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
e. Periodically check the
*cal_busy
output signals or read the capability registers 0x280[1] to check
*cal_busy
status until calibration is complete.
If you are recalibrating your fPLL and have ATX PLL used on the same side of the device, follow the fPLL-to-ATX PLL spacing guideline as stated in the "Transmit
PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
3. Perform the PMA user recalibration process: a. Request access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
b. Wait for reconfig_waitrequest
to deassert (logic low), or wait until capability register of PreSICE Avalon-MM interface control 0x281[2]=0x0.
c. Configure the PMA calibration enable register 0x100. You must set 0x0 to
0x100[6] to enable any calibration.
• Read-Modify-Write 0x1 to 0x100[1] to start PMA RX calibration.
• Read-Modify-Write 0x1 to 0x100[5] to start PMA TX calibration.
d. Do Read-Modify-Write on the rate switch flag register if you switched rates with a different CDR bandwidth setting.
e. Do Read-Modify-Write on 0x281[5:4] to disable/enable rx_cal_busy
and tx_cal_busy
.
• To enable rx_cal_busy, write
0x1 to 0x281[5].
• To disable rx_cal_busy, write
0x0 to 0x281[5].
• To enable tx_cal_busy, write
0x1 to 0x281[4].
• To disable tx_cal_busy, write
0x0 to 0x281[4].
f.
Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
g. Perform a loop to check the tx_cal_busy
and rx_cal_busy
output signals or read the capability registers 0x281[1:0] to check
*cal_busy
status until calibration is complete.
Related Information
Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs
on page 349
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7.5. Calibration Example
7.5.1. ATX PLL Recalibration
When you use the ATX PLL in your application, and it requires a line rate or clock frequency change, you must recalibrate the ATX PLL after you have made the changes.
Follow these steps to recalibrate the ATX PLL:
1. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
2. Wait for reconfig_waitrequest
to be deasserted (logic low) or wait until capability register of PreSICE Avalon-MM interface control 0x280[2]=0x0.
3. To calibrate the ATX PLL, doing Read-Modify-Write 0x1 to bit[0] of address 0x100 of the ATX PLL.
4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
5. Periodically check the
*cal_busy
output signals or read the capability registers
0x280[1] to check
*cal_busy
status until calibration is complete.
Note: If you are recalibrating your ATX PLL and have adjacent ATX PLL used on the same side of the device, follow the ATX PLL-to-ATX PLL spacing guideline as stated in the
"Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
Related Information
Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs
on page 349
7.5.2. Fractional PLL Recalibration
Follow these steps to recalibrate the fPLL:
1. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
2. Wait for reconfig_waitrequest
to be deasserted (logic low) or wait until capability register of PreSICE Avalon-MM interface control 0x280[2]=0x0.
3. To calibrate the fPLL, Read-Modify-Write 0x1 to bit[1] of address 0x100 of the fPLL.
4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
5. Periodically check the
*cal_busy
output signals or read the capability registers
0x280[1] to check
*cal_busy
status until calibration is complete.
Note: If you are recalibrating your fPLL and have ATX PLL used on the same side of the device, follow the fPLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs
Spacing Guideline when using ATX PLLs and fPLLs" chapter.
Related Information
Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs
on page 349
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7.5.3. CDR/CMU PLL Recalibration
CDR/CMU PLL user recalibration is integrated into the PMA RX user recalibration.
Enabling 0x100[1] PMA RX calibration recalibrates the CDR/CMU PLL.
7.5.4. PMA Recalibration
PMA calibration includes:
• PMA TX calibration
• PMA RX calibration
The PMA RX calibration includes CDR/CMU PLL calibration, offset cancellation calibration, and V
CM
calibration. The TX PMA calibration includes TX termination, Vod, and DCD calibration.
Follow these steps to recalibrate the PMA:
1. Request access to the internal configuration bus by writing 0x2 to offset address
0x0[7:0].
2. Wait for reconfig_waitrequest
to be deasserted (logic low), or wait until capability register of PreSICE Avalon-MM interface control 0x281[2]=0x0.
3. Set the proper value to offset address 0x100 to enable PMA calibration. You must also set the 0x100 [6] to 0x0 when you enable any PMA channel calibration to ensure adaptation triggering is disabled.
4. Set the rate switch flag register for PMA RX calibration after the rate change.
• Read-Modify-Write 0x1 to offset address 0x166[7] if no rate switch.
• Read-Modify-Write 0x0 to offset address 0x166[7] if switched rate with different CDR bandwidth setting.
5. Do Read-Modify-Write the proper value to capability register 0x281[5:4] for PMA calibration to enable/disable tx_cal_busy
or rx_cal_busy
output.
• To enable rx_cal_busy
, Read-Modify-Write 0x1 to 0x281[5].
• To disable rx_cal_busy
, Read-Modify-Write 0x0 to 0x281[5].
• To enable tx_cal_busy
, Read-Modify-Write 0x1 to 0x281[4].
• To disable tx_cal_busy
, Read-Modify-Write 0x0 to 0x281[4].
6. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
7. Periodically check the
*cal_busy
output signals or read the capability registers
0x281[1:0] to check
*cal_busy
status until calibration is complete.
Related Information
Transceiver Channel Calibration Registers
on page 570
For more details about PMA recalibration
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7.6. Calibration Revision History
Document
Version
2018.06.15
2017.11.06
2016.10.31
2016.05.02
2015.12.18
2015.11.02
Changes
Made the following change:
• Added a footnote: CDR and CMU PLL calibration are part of RX PMA calibration.
Made the following changes:
• Updated the flow of "User Recalibration" topic.
• Updated "
— In order to trigger user re-calibration:
• Write 0x01 to offset address 0x000 [7:0], user re-calibration has to request through offset address 0x100.
— In order to trigger DFE adaptation:
• Write 0x03 to offset address 0x000 [7:0], DFE adaptation triggering has to enable through
0x100[6].
— If you no longer need to use the internal reconfiguration bus:
• Write 0x03 to offset address 0x000 [7:0].
" in the "Reconfiguration Interface and Arbitration with PreSICE Calibration Engine" topic.
• Updated "You must also set the 0x100 [6] to 0x0 when you enable any PMA channel calibration to ensure adaptation triggering is disabled." in "User Recalibration" topic.
• Updated "PMA Calibration Enable Register Offset Address 0x100" fto "Write 1'b0 to 0x100 [6] when you enable any PMA channel calibration to ensure adaptation triggering request is disable." for bit 6 in "Transceiver Channel PMA Calibration Registers" table.
Made the following change:
• In table "Avalon-MM Interface Arbitration Registers" the description for bit [1] is changed to
"0x1=calibration completed and 0x0=calibration not started".
• Changed the "user calibration" flow.
• Changed the "power up calibration" sequence.
• Added descriptions for “Simplex calibration".
• Added a new section “Rules to Build Customized Gating Logic to Separate tx_cal_busy and rx_cal_busy signals”.
• Updated the “Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels”, “Power-up
Calibration Sequence for PCIe Hard IP and non-PCIe Channels”, and “Recalibration Sequence when the Transceiver Reference Clock or Data Rate Changes” figures.
• Changed the order of the “User Recalibration” steps in the “Recalibration After Transceiver
Reference Clock Frequency or Data Rate Change” section.
Made the following changes:
• Changed the description in the "Rate Switch Flag Register" section.
• Added more description to the "User Recalibration" section.
• Added information in the "PMA Recalibration" section.
Made the following changes:
• Changed the description in the "Reconfiguration Interface and Arbitration with PreSICE Calibration
Engine" section.
• Changed the description in the "Calibration Registers" section.
• Changed the "Transceiver Channel PMA Calibration Registers for Production Devices" table.
• Removed description from the "Transceiver Channel Calibration Registers" section.
• Changed values in the "Fractional PLL Calibration Registers" table.
• Changed the "PMA Capability Registers for Calibration Status" table.
• Added the "ATX PLL Capability Registers for Calibration Status" table.
• Added the "fPLL Capability Registers for Calibration Status" table.
• Added description to the "Capability Registers" section.
• Added the "Rate Switch Flag Register" section.
• Added steps to the "User Recalibration" section.
• Changed the description in the "CDR/CMU PLL Recalibration" section.
• Added steps to the "PMA Recalibration" section.
continued...
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Document
Version
2015.05.11
2014.12.15
Changes
• Changed the "Recalibration Sequence when the Transceiver Reference Clock or Data Rate Changes" figure.
• Added steps to the "User Recalibration" section.
• Updated the "Transceiver Channel PMA Calibration Registers for Production Devices" table.
• Updated the "Fractional PLL Calibration Registers" table.
• Updated the "ATX PLL Calibration Registers" table.
• Changed the description in the "ATX PLL Calibration Registers" section.
• Added description to the "Capability Registers" section.
• Changed the "Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels" figure.
• Changed the "Power-up Calibration Sequence for PCIe HIP and non-PCIe Channels" figure.
• Removed some steps from the "User Recalibration" section.
• Removed some steps from the "ATX PLL Recalibration" section.
• Removed some steps from the "Fractional PLL Recalibration" section.
• Removed some steps from the "PMA Recalibration" section.
• Removed the "Check Calibration Status" section.
Made the following changes:
• Changed register offsets globally.
• Changed the description in the "Reconfiguration Interface and Arbitration with PreSICE Calibration
Engine" section.
• Changed the description in the "Calibration Registers" section.
• Changed the descriptions and added a bit in the "Avalon-MM Interface Arbitration Registers" table.
• Changed the descriptions in the "Transceiver Channel Calibration Registers" table.
• Changed the descriptions in the "Fractional PLL Calibration Registers" table.
• Changed the descriptions in the "ATX PLL Calibration Registers" table.
• Added the "Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels" and "Power-up
Calibration Sequence for PCIe HIP and non-PCIe Channels" figures.
• Changed "Avalon-MM interface" to "internal configuration bus" in the "User Recalibration" section.
• Changed "Avalon-MM interface" to "internal configuration bus" in the "ATX PLL Recalibration" section.
• Changed the bit to calibrate the fPLL and changed "Avalon-MM interface" to "internal configuration bus" in the "Fractional PLL Recalibration" section.
• Changed "Avalon-MM interface" to "internal configuration bus" in the "CMU or CDR PLL
Recalibration" section.
• Changed the addresses in the "User Recalibration" section.
• Changed the addresses in the "ATX PLL Recalibration" section.
• Changed the addresses in the "Fractional PLL Recalibration" section.
• Changed the addresses in the "CDR/CMU PLL Recalibration" section.
• Changed the addresses and added descriptions in the "PMA Recalibration" section.
• Changed the addresses in the "Check Calibration Status" section.
• Changed "Avalon-MM interface" to "internal configuration bus" in the "PMA Recalibration" section.
• Added the "Capability Registers" section.
Initial release.
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8. Analog Parameter Settings
Transceiver analog parameter settings are used to tune the analog functions in the physical medium attachment (PMA) and the PLL blocks while designing high-speed serial protocol solutions. You can use this feature to compensate for signal losses for high data rate communication.
Most transceiver parameters can be set using the Parameter Editor before generating the transceiver PHY IP. The parameters that depend on place and route decisions, device constraints, and tunable analog settings that cannot be set before IP generation are controlled in the following ways:
• Making analog parameter settings to I/O pins using the Assignment Editor.
• Updating the Quartus Prime Settings File (.qsf) with the known assignment.
• Using the Reconfiguration Interface to dynamically change the analog settings.
8.1. Making Analog Parameter Settings using the Assignment Editor
To make assignments using the Assignment Editor, complete the following steps:
1. On the Assignments menu, select Assignment Editor. The Assignment Editor appears.
2. Click inside the Assignment Name column and select the appropriate assignment. Refer to the PMA Analog Settings section for the list of available assignments for PMA analog settings.
3. Click inside the Value column and select the appropriate value for your assignment.
The Quartus Prime software adds these instance assignments to the .qsf file for your project.
Related Information
Analog Parameter Settings List on page 586
8.2. Updating Quartus Settings File with the Known Assignment
The Quartus Prime Settings File (.qsf) contains all the entity-level assignments and settings for the current revision of the project. The Quartus Settings File is based on
Tcl script syntax.
When you create assignments and settings using the Parameter Editor wizards and dialog boxes or Tcl commands, the Quartus Prime software automatically places the assignments at the end of the Quartus Prime Settings File. To control the analog parameters, you can directly add or modify the appropriate assignment in the Quartus
Prime Settings File. The assignments you create are recognized, regardless of where you place them in the file.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
8. Analog Parameter Settings
UG-01143 | 2018.06.15
Related Information
Quartus Prime Settings File (.qsf)
Describes the commands and options available to modify the assignments in the qsf file.
8.3. Analog Parameter Settings List
The following table lists the analog parameter settings for the transmitter and receiver.
The details of each of these settings are in the sections following this table.
Table 304.
Receiver Analog Parameter Settings
Analog Parameter Setting
XCVR_A10_RX_LINK
XCVR_A10_RX_TERM_SEL
XCVR_VCCR_VCCT_VOLTAGE
XCVR_A10_RX_ONE_STAGE_ENABL
E
XCVR_A10_RX_ADP_DFE_FXTAP1
XCVR_A10_RX_ADP_DFE_FXTAP2
Pin Planner or Assignment Editor
Name
Receiver Link Type
Receiver On-Chip-Termination
VCCR_GXB/VCCT_GXB Voltage
Receiver High Data Rate Mode
Equalizer
XCVR_A10_RX_EQ_DC_GAIN_TRIM Receiver High Gain Mode Equalizer
DC Gain Control
XCVR_A10_RX_ADP_CTLE_ACGAIN
_4S
Receiver High Gain Mode Equalizer
AC Gain Control
XCVR_A10_RX_ADP_CTLE_EQZ_1S
_SEL
XCVR_A10_RX_ADP_VGA_SEL
Receiver High Data Rate Mode
Equalizer AC Gain Control
Receiver Variable Gain Amplifier
Voltage Swing Select
Receiver Decision Feedback
Equalizer Fixed Tap One Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Two Coefficient
XCVR_A10_RX_ADP_DFE_FXTAP2_
SGN
XCVR_A10_RX_ADP_DFE_FXTAP3
Receiver Decision Feedback
Equalizer Fixed Tap Two Sign
Receiver Decision Feedback
Equalizer Fixed Tap Three
Coefficient
XCVR_A10_RX_ADP_DFE_FXTAP3_
SGN
XCVR_A10_RX_ADP_DFE_FXTAP4
XCVR_A10_RX_ADP_DFE_FXTAP4_
SGN
XCVR_A10_RX_ADP_DFE_FXTAP5
XCVR_A10_RX_ADP_DFE_FXTAP5_
SGN
XCVR_A10_RX_ADP_DFE_FXTAP6
Receiver Decision Feedback
Equalizer Fixed Tap Three Sign
Receiver Decision Feedback
Equalizer Fixed Tap Four Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Four Sign
Receiver Decision Feedback
Equalizer Fixed Tap Five Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Five Sign
Receiver Decision Feedback
Equalizer Fixed Tap Six Coefficient
Assignment
Destination
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
Chip-to-chip or backplane
On chip termination
VCCR/VCCT voltage
Continuous time-linear equalization (CTLE)
CTLE
VGA
Decision feedback equalization (DFE)
DFE
DFE
DFE
DFE
DFE
DFE
DFE
DFE
DFE
Usage Guideline
CTLE
CTLE continued...
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Analog Parameter Setting
XCVR_A10_RX_ADP_DFE_FXTAP6_
SGN
XCVR_A10_RX_ADP_DFE_FXTAP7
XCVR_A10_RX_ADP_DFE_FXTAP7_
SGN
XCVR_A10_RX_ADP_DFE_FXTAP8
XCVR_A10_RX_ADP_DFE_FXTAP8_
SGN
XCVR_A10_RX_ADP_DFE_FXTAP9
XCVR_A10_RX_ADP_DFE_FXTAP9_
SGN
XCVR_A10_RX_ADP_DFE_FXTAP10
XCVR_A10_RX_ADP_DFE_FXTAP10_
SGN
XCVR_A10_RX_ADP_DFE_FXTAP11
XCVR_A10_RX_ADP_DFE_FXTAP11_
SGN
Pin Planner or Assignment Editor
Name
Receiver Decision Feedback
Equalizer Fixed Tap Six Sign
Receiver Decision Feedback
Equalizer Fixed Tap Seven
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Seven Sign
Receiver Decision Feedback
Equalizer Fixed Tap Eight Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Eight Sign
Receiver Decision Feedback
Equalizer Fixed Tap Nine Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Nine Sign
Receiver Decision Feedback
Equalizer Fixed Tap Ten Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Ten Sign
Receiver Decision Feedback
Equalizer Fixed Tap Eleven
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Eleven Sign
Assignment
Destination
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
RX serial data
Table 305.
Transmitter Analog Parameter Settings
Analog Parameter Setting Pin Planner or Assignment Editor
Name
Transmitter Link Type XCVR_A10_TX_LINK
XCVR_A10_TX_TERM_SEL Transmitter On-Chip Termination
XCVR_A10_TX_COMPENSATION_EN Transmitter High-Speed
Compensation
XCVR_VCCR_VCCT_VOLTAGE
XCVR_A10_TX_SLEW_RATE_CTRL
VCCR_GXB/VCCT_GXB Voltage
Transmitter Slew Rate Control
XCVR_A10_TX_PRE_EMP_SIGN_PR
E_TAP_1T
XCVR_A10_TX_PRE_EMP_SIGN_PR
E_TAP_2T
XCVR_A10_TX_PRE_EMP_SIGN_1S
T_POST_TAP
XCVR_A10_TX_PRE_EMP_SIGN_2N
D_POST_TAP
XCVR_A10_TX_PRE_EMP_SWITCHI
NG_CTRL_PRE_TAP_1T
XCVR_A10_TX_PRE_EMP_SWITCHI
NG_CTRL_PRE_TAP_2T
Transmitter Pre-Emphasis First Pre-
Tap Polarity
Transmitter Pre-Emphasis Second
Pre-Tap Polarity
Transmitter Pre-Emphasis First
Post-Tap Polarity
Transmitter Pre-Emphasis Second
Post-Tap Polarity
Transmitter Pre-Emphasis First Pre-
Tap Magnitude
Transmitter Pre-Emphasis Second
Pre-Tap Magnitude
Assignment
Destination
TX serial data
TX serial data
TX serial data
TX serial data
TX serial data
TX serial data
TX serial data
TX serial data
TX serial data
TX serial data
TX serial data
DFE
DFE
DFE
DFE
DFE
DFE
DFE
DFE
DFE
DFE
DFE
Usage Guideline
Usage Guideline
Chip-to-chip or backplane
On chip termination
PDN ISI compensation
VCCR/VCCT voltage
Slew Rate
Pre-emphasis
Pre-emphasis
Pre-emphasis
Pre-emphasis
Pre-emphasis
Pre-emphasis continued...
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Analog Parameter Setting
XCVR_A10_TX_PRE_EMP_SWITCHI
NG_CTRL_1ST_POST_TAP
XCVR_A10_TX_PRE_EMP_SWITCHI
NG_CTRL_2ND_POST_TAP
XCVR_A10_TX_VOD_OUTPUT_SWI
NG_CTRL
Pin Planner or Assignment Editor
Name
Transmitter Pre-Emphasis First
Post-Tap Magnitude
Transmitter Pre-Emphasis Second
Post-Tap Magnitude
Transmitter Output Swing Level
Assignment
Destination
TX serial data
TX serial data
TX serial data
Table 306.
Reference Clock Analog Parameter Settings
Analog Parameter Setting
XCVR_A10_REFCLK_TERM_TRISTAT
E
Pin Planner or Assignment Editor
Name
Dedicated Reference Clock Pin
Termination
Assignment
Destination
Reference clock pin
Note:
Usage Guideline
Pre-emphasis
Pre-emphasis
Differential output voltage
Usage Guideline
On-chip termination
You must set all the required analog settings according to your protocol configuration.
If you do not set the appropriate settings, then the Quartus Prime software selects the default values which may not be appropriate for your protocol implementation.
8.4. Receiver General Analog Settings
8.4.1. XCVR_A10_RX_LINK
Pin planner or Assignment Editor Name
Receiver Link Type
Description
This parameter is configured depending on the link characteristic. Value SR is used for link insertion loss less than equal to 10dB and value LR is used for link insertion loss greater than 10dB. If this QSF assignment is not done, Quartus Prime assigns SR as the default value. Settings dependent on this parameter value are DC gain, VGA and sd_threshold for SATA. This is also used for data rate legality check during compilation.
For SR: sd_threshold for SATA = SDLV_4
For LR: sd_threshold for SATA = SDLV_6
For the default values of DC gain and VGA corresponding to RX_LINK setting, look for
QSF assignments XCVR_A10_RX_EQ_DC_GAIN_TRIM and
XCVR_A10_RX_ADP_VGA_SEL.
Table 307.
Available Options
Value
SR (Short Reach)
LR (Long Reach)
Description
Less than or equal to10dB IL, used for Chip-to-chip communication
>10dB IL, used for Backplane communication
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Assign To
RX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_RX_LINK <value> -to
<rx_serial_data pin name>
Related Information
Arria 10 Device Datasheet
8.4.2. XCVR_A10_RX_TERM_SEL
Pin planner or Assignment Editor Name
Receiver On-Chip Termination
Description
Controls the on-chip RX differential termination. For data rates higher than 25 Gbps, set the termination resistance to 85 Ohm.
Note: For protocols such as QPI, you need to set the termination setting to R_R2. For all the other protocols, you can either set this setting to R_R1 or R_R2. The default value set for all the protocols other than QPI depends upon the data rate. When the data rate is less than or equal to 17.4 Gbps, the default value is R_R1. When the data rate is greater than 17.4 Gbps, the default value is R_R2.
Table 308.
Available Options
Value
R_EXT0
R_R1
R_R2
Description
Tristate
100 Ohm
85 Ohm
Assign To
RX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_RX_TERM_SEL <value> -to
<rx_serial_data pin name>
8.4.3. XCVR_VCCR_VCCT_VOLTAGE - RX
Pin planner or Assignment Editor Name
VCCR_GXB and VCCT_GXB voltages
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1_1V
1_0V
0_9V
Description
Configures the VCCR_GXB and VCCT_GXB voltage for a GXB I/O pin by specifying the intended supply voltages for a GXB I/O pin. Intel recommends always including this
QSF assignment.
Value (65) Description
VCCR_GXB or VCCT_GXB voltage
VCCR_GXB or VCCT_GXB voltage
VCCR_GXB or VCCT_GXB voltage
Assign To
RX serial data pin.
Syntax set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE <value> -to
<rx_serial_data pin name>
.
Related Information
Arria 10 Device Datasheet
8.5. Receiver Analog Equalization Settings
8.5.1. CTLE Settings
8.5.1.1. XCVR_A10_RX_ONE_STAGE_ENABLE
Pin planner or Assignment Editor Name
Receiver High Data Rate Mode Equalizer
Description
Selects between the CTLE high gain mode or CTLE high data rate mode for the equalizer. For data rate greater than 17.4 Gbps, only high data rate mode is allowed.
For data rate less than or equal to 17.4 Gbps, you can select between high gain mode and high data rate mode. If no assignment is made, S1_MODE is chosen by default for datarate less than or equal to 25.8 Gbps.
(65) These values are for the assignment editor. For the actual values, refer to the Arria 10 Device
Datasheet.
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Table 309.
Available Options
Value in QSF
NON_S1_MODE
S1_MODE
Value in Assignment
Editor
Off
On
Description
Selects high gain mode for data rates up to 17.4 Gbps.
Selects high data rate mode up to 25.8 Gbps. Power consumption reduces in high data rate mode, as compared to high gain mode, when operating below 17.4 Gbps. This mode is the only option above 17.4
Gbps.
Assign To
RX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE
<value> -to <rx_serial_data pin name>
8.5.1.2. XCVR_A10_RX_EQ_DC_GAIN_TRIM
Pin planner or Assignment Editor Name
Receiver High Gain Mode Equalizer DC Gain Control
Description
Controls the DC gain of the continuous time linear equalizer (CTLE) in high gain mode.
A higher gain setting results in a larger DC gain.
For RX_LINK=SR, the default value is STG2_GAIN7.
For RX_LINK=LR, and if equalization mode = S1_MODE, default value of DC gain is
STG1_GAIN7.
For RX_LINK=LR, and if equalization mode = NON_S1_MODE, default value of DC gain is NO_DC_GAIN.
For PCIe, default value is NO_DC_GAIN.
For datarate > 17.4 Gbps, default value is NO_DC_GAIN.
Table 310.
Available Options
Value in TTK
DC Gain 0
DC Gain 1
DC Gain 2
DC Gain 3
DC Gain 4
Value in Assignment Editor / qsf (66)
NO_DC_GAIN
STG1_GAIN7
STG2_GAIN7
STG3_GAIN7
STG4_GAIN7
Description
No DC gain
Equalizer DC gain setting 6
Equalizer DC gain setting 13
Equalizer DC gain setting 20
Equalizer DC gain setting 27
(66) Refer to Arria 10 Data Sheet
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Assign To
RX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM <value>
-to <rx_serial_data pin name>
Related Information
Arria 10 Device Datasheet
8.5.1.3. XCVR_A10_RX_ADP_CTLE_ACGAIN_4S
Pin planner or Assignment Editor Name
Receiver High Gain Mode Equalizer AC Gain Control
Description
Controls the AC gain of the continuous time linear equalizer (CTLE) in high gain mode.
Arria 10 transceivers support two CTLE modes, high gain mode and high data rate mode. As a default, high data rate mode is enabled for data rates up to 25.8 Gbps.
High gain mode can be enabled for datarate less than or equal to 17.4Gbps Higher gain setting results in larger AC gain.
he default value for PCIe Gen3 is RADP_CTLE_ACGAIN_4S_7.
For all the other cases, the default value is RADP_CTLE_ACGAIN_4S_1.
Table 311.
Available Options
Value
RADP_CTLE_ACGAIN_4S_<0 to 28>
Description
CTLE AC gain setting <0 to 28>
Assign To
RX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S
<value> -to <rx_serial_data pin name>
8.5.1.4. XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
Pin planner or Assignment Editor Name
Receiver High Data Rate Mode Equalizer AC Gain Control
Description
Controls the AC gain of the continuous time linear equalizer (CTLE) in high data rate mode and when adaptation is in manual mode (adaptation is disabled).
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High data rate mode is enabled by default for data rates up to 25.8 Gbps. In high data rate mode, there is only one CTLE stage and 16 possible AC gain settings. Higher gain setting results in larger AC gain. The default value is set to
RADP_CTLE_EQZ_1S_SEL_3 i.e. CTLE AC Gain Setting 3. This QSF assignment only takes effect when one stage CTLE is enabled. If configured in four stage mode, it has no effect on CTLE gain value.
For datarate > 17.4 Gbps, default value is RADP_CTLE_EQZ_1S_SEL_13.
For datarate ≤ 17.4 Gbps, default value is RADP_CTLE_EQZ_1S_SEL_3.
Table 312.
Available Options
Value
RADP_CTLE_EQZ_1S_SEL_<0 to 15>
Description
CTLE AC Gain Setting < 0 to 15>
Assign To
RX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
<value> -to <rx_serial_data pin name>
8.5.2. VGA Settings
8.5.2.1. XCVR_A10_RX_ADP_VGA_SEL
Pin planner or Assignment Editor Name
Receiver Variable Gain Amplifier Voltage Swing Select
Description
The variable gain amplifier (VGA) amplifies the signal amplitude and ensures a constant voltage swing before the data is fed to the CDR for sampling. This assignment controls the VGA output voltage swing when adaptation mode of VGA is set to manual. The default value is set to RADP_VGA_SEL_4 for VGA Output Voltage
Swing Setting 4.
Default values for VGA if VGA are not set exclusively.
For PCIe Gen1 & Gen2: default value is RADP_VGA_SEL_4.
For PCIe Gen3: default value is RADP_VGA_SEL_4.
For datarate > 17.4 Gbps, default value is RADP_VGA_SEL_4.
For RX_LINK = LR and CTLE mode = NON_S1_MODE: default value is
RADP_VGA_SEL_4.
For RX_LINK = LR and CTLE mode = S1_MODE and datarate <= 4.5Gbps: default value is RADP_VGA_SEL_4.
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For RX_LINK = LR and CTLE mode = S1_MODE and datarate > 4.5Gbps: default value is RADP_VGA_SEL_4.
For RX_LINK = LR and CTLE mode = S1_MODE and datarate > 4.5Gbps and data rate
≤ 17.4Gbps,: default value is RADP_VGA_SEL_4.
For RX_LINK = SR and CTLE mode = NON_S1_MODE and datarate <= 4.5Gbps: default value is RADP_VGA_SEL_4.
For RX_LINK = SR and CTLE mode = NON_S1_MODE and datarate > 4.5Gbps: default value is RADP_VGA_SEL_4.
For RX_LINK = SR and CTLE mode = S1_MODE: default value is RADP_VGA_SEL_4.
Table 313.
Available Options
Value
RADP_VGA_SEL_<0 to 7>
Description
VGA Output Voltage Swing Setting <0 to 7>
Assign To
RX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL <value> -to
<rx_serial_data pin name>
8.5.3. Decision Feedback Equalizer (DFE) Settings
The decision feedback equalizer (DFE) amplifies the high frequency component of a signal without amplifying the noise content. The DFE removes the post-cursor Inter
Symbol Interference (ISI) of the bits received previously from the current bit and improves the Bit Error Rate (BER). The DFE architecture supports eleven fixed taps.
The fixed taps in DFE remove the ISI of the previous 11 bits from the current bit.
The DFE circuit stores delayed versions of the data. The stored bit is multiplied by a coefficient and then summed with the incoming signal. The polarity of each coefficient is programmable.
Note: The DFE fixed tap assignments are described in the following section.
8.5.3.1. XCVR_A10_RX_ADP_DFE_FXTAP
Description
The following assignments specify the coefficient of DFE fixed taps 1 through 11.
These assignments are applicable only when the DFE is enabled and adaptation is disabled for the DFE (DFE operates in manual mode). The default value for all assignments is set to RADP_DFE_FXTAP<1 to 11>_0 for DFE fixed tap<1 to 11> coefficient setting 0. DFE tap1 in the only tap which is always positive and hence there is no QSF assignment for DFE tap1 sign bit. Other taps can be positive or negative.
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Table 314.
DFE Fixed Tap Assignments
Assignment
XCVR_A10_RX_ADP_DFE_FX
TAP1
Pin Planner or Assignment
Editor Name
Receiver Decision Feedback
Equalizer Fixed Tap One
Coefficient
XCVR_A10_RX_ADP_DFE_FX
TAP2
XCVR_A10_RX_ADP_DFE_FX
TAP2_SGN
Receiver Decision Feedback
Equalizer Fixed Tap Two
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Two Sign
Value
RADP_DFE_FXTAP1_<0 to
127>
RADP_DFE_FXTAP2_<0 to
127>
RADP_DFE_FXTAP2_SGN_
<0 or 1>
Description
DFE fixed tap 1 Coefficient
Setting <0 to 127>
DFE fixed tap 2 Coefficient
Setting < 0 to 127>
XCVR_A10_RX_ADP_DFE_FX
TAP3
XCVR_A10_RX_ADP_DFE_FX
TAP3_SGN
Receiver Decision Feedback
Equalizer Fixed Tap Three
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Three
Sign
XCVR_A10_RX_ADP_DFE_FX
TAP4
XCVR_A10_RX_ADP_DFE_FX
TAP4_SGN
Receiver Decision Feedback
Equalizer Fixed Tap Four
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Four
Sign
RADP_DFE_FXTAP3_<0 to
127>
RADP_DFE_FXTAP3_SGN_
<0 or 1>
RADP_DFE_FXTAP4_<0 to
63>
RADP_DFE_FXTAP4_SGN_
<0 or 1>
XCVR_A10_RX_ADP_DFE_FX
TAP5
XCVR_A10_RX_ADP_DFE_FX
TAP5_SGN
Receiver Decision Feedback
Equalizer Fixed Tap Five
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Five Sign
RADP_DFE_FXTAP5_<0 to
63>
RADP_DFE_FXTAP5_SGN_
<0 or 1>
DFE fixed tap 2 coefficient sign 0 or 1
0 = Positive and 1=Negative
DFE fixed tap 3 Coefficient
Setting <0 to 127>
DFE fixed tap 3 coefficient sign 0 or 1
0 = Positive and 1=Negative
DFE fixed tap 4 Coefficient
Setting <0 to 63>
DFE fixed tap 4 coefficient sign 0 or 1
0 = Positive and 1=Negative
DFE fixed tap 5 Coefficient
Setting <0 to 63>
XCVR_A10_RX_ADP_DFE_FX
TAP6
XCVR_A10_RX_ADP_DFE_FX
TAP6_SGN
Receiver Decision Feedback
Equalizer Fixed Tap Six
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Six Sign
XCVR_A10_RX_ADP_DFE_FX
TAP7
XCVR_A10_RX_ADP_DFE_FX
TAP7_SGN
Receiver Decision Feedback
Equalizer Fixed Tap Seven
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Seven
Sign
XCVR_A10_RX_ADP_DFE_FX
TAP8
XCVR_A10_RX_ADP_DFE_FX
TAP8_SGN
Receiver Decision Feedback
Equalizer Fixed Tap Eight
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Eight
Sign
XCVR_A10_RX_ADP_DFE_FX
TAP9
Receiver Decision Feedback
Equalizer Fixed Tap Nine
Coefficient
RADP_DFE_FXTAP6_<0 to
31>
RADP_DFE_FXTAP6_SGN_
<0 or 1>
RADP_DFE_FXTAP7_<0 to
31>
RADP_DFE_FXTAP7_SGN_
<0 or 1>
RADP_DFE_FXTAP8_<0 to
63>
RADP_DFE_FXTAP8_SGN_
<0 or 1>
RADP_DFE_FXTAP9_<0 to
63>
DFE fixed tap 5 coefficient sign 0 or 1
0 = Positive and 1=Negative
DFE fixed tap 6 Coefficient
Setting <0 to 31>
DFE fixed tap 6 coefficient sign 0 or 1
0 = Positive and 1=Negative
DFE fixed tap 7 Coefficient
Setting <0 to 31>
DFE fixed tap 7 coefficient sign 0 or 1
0 = Positive and 1=Negative
DFE fixed tap 8 Coefficient
Setting <0 to 63>
DFE fixed tap 8 coefficient sign 0 or 1
0 = Positive and 1=Negative
DFE fixed tap 9 Coefficient
Setting <0 to 63> continued...
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Assignment
XCVR_A10_RX_ADP_DFE_FX
TAP9_SGN
Pin Planner or Assignment
Editor Name
Receiver Decision Feedback
Equalizer Fixed Tap Nine
Sign
Value
RADP_DFE_FXTAP9_SGN_
<0 or 1>
XCVR_A10_RX_ADP_DFE_FX
TAP10
XCVR_A10_RX_ADP_DFE_FX
TAP10_SGN
Receiver Decision Feedback
Equalizer Fixed Tap Ten
Coefficient.
Receiver Decision Feedback
Equalizer Fixed Tap Ten Sign
RADP_DFE_FXTAP10_<0 to
63>
RADP_DFE_FXTAP10_SGN_
<0 or 1>
RADP_DFE_FXTAP11_<0 to
63>
Description
DFE fixed tap 9 coefficient sign 0 or 1
0 = Positive and 1=Negative
DFE fixed tap 10 Coefficient
Setting <0 to 63>
DFE fixed tap 10 coefficient sign 0 or 1
0 = Positive and 1=Negative
DFE fixed tap 11 Coefficient
Setting <0 to 63>
XCVR_A10_RX_ADP_DFE_FX
TAP11
XCVR_A10_RX_ADP_DFE_FX
TAP11_SGN
Receiver Decision Feedback
Equalizer Fixed Tap Eleven
Coefficient
Receiver Decision Feedback
Equalizer Fixed Tap Eleven
Sign
RADP_DFE_FXTAP11_SGN_
<0 or 1>
DFE fixed tap 11 coefficient sign 0 or 1
0 = Positive and 1=Negative
Example DFE Fixed Tap Assignment
Assignment: XCVR_A10_RX_ADP_DFE_FXTAP1
Value: RADP_DFE_FXTAP1_2
Description: DFE fixed tap 1 Coefficient Setting 2
Assign To
RX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 <value>
-to <rx_serial_data pin name>
8.6. Transmitter General Analog Settings
8.6.1. XCVR_A10_TX_LINK
Pin planner or Assignment Editor Name
Transmitter Link Type
Description
This parameter is configured depending on the link characteristics. Value SR is used for link insertion loss less than or equal to 10dB and value LR is used for link insertion loss greater than 10dB. If this QSF assignment is not done, Quartus Prime assigns SR as the default value. This is used for data rate legality check during compilation.
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Table 315.
Available Options
Value
SR
LR
Description
Less than or equal to 10dB IL, used for Chip-to-chip communication
> 10dB IL, used for Backplane communication
Note: The maximum data rate supported by transceiver channels depends on the device speed grade, power mode, and the type of transceiver channel. Refer to Arria 10
Device Datasheet for more details.
Assign To
TX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_TX_LINK <value> -to
<tx_serial_data pin name>
Related Information
Arria 10 Device Datasheet
8.6.2. XCVR_A10_TX_TERM_SEL
Pin planner or Assignment Editor Name
Transmitter On-Chip Termination
Description
Controls the on-chip TX differential termination for different protocols.
Table 316.
Available Options
Value
R_R1
R_R2
100 Ohm
85 Ohm
Description
Note: For protocols such as QPI, you need to set this setting to R_R2. For all the other protocols, you can either set this setting to R_R1 or R_R2. The default value set for all the protocols other than QPI depends upon the data rate.When the data rate is less than or equal to 17.4 Gbps, the default value is R_R1. When the data rate is greater than 17.4 Gbps, the default value is R_R2.
8.6.3. XCVR_A10_TX_COMPENSATION_EN
Pin planner or Assignment Editor Name
Transmitter High-Speed Compensation
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Description
Specifies if the power distribution network (PDN) induced inter-symbol interference
(ISI) compensation is enabled or disabled in the TX driver. When enabled, it reduces the PDN induced ISI jitter, but increases the power consumption. Use this feature for high speed applications. It defaults to ENABLE for non-PCIe modes.
Table 317.
Available Options
Value
ENABLE
DISABLE
Description
Compensation ON
Compensation OFF
Table 318.
Rules
Data Rate
PCIe Gen1, Gen2
PCIe Gen3
Others
Value of XCVR_A10_TX_COMPENSATION_EN
DISABLE
ENABLE
ENABLE/DISABLE
Assign To
TX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN <value>
-to <tx_serial_data pin name>
Related Information
EPE (Early Power Estimator)
8.6.4. XCVR_VCCR_VCCT_VOLTAGE - TX
Pin planner or Assignment Editor Name
VCCR_GXB and VCCT_GXB voltages
1_1V
1_0V
0_9V
Description
Configures the VCCR_GXB and VCCT_GXB voltage for a GXB I/O pin by specifying the intended supply voltages for a GXB I/O pin.
Value (67) Description
VCCR_GXB or VCCT_GXB voltage
VCCR_GXB or VCCT_GXB voltage
VCCR_GXB or VCCT_GXB voltage
(67) These are assignment editor values. For the actual values, refer to the Arria 10 Device
Datasheet.
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Assign To
TX serial data pin.
Syntax set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE <value> -to
<tx_serial_data pin name>
Related Information
Arria 10 Device Datasheet
8.6.5. XCVR_A10_TX_SLEW_RATE_CTRL
Pin planner or Assignment Editor Name
Transmitter Slew Rate Control
Description
Specifies the slew rate of the output signal. The valid values span from the slowest rate to the fastest rate.
Note: Slew_R6 and Slew_R7 are not used.
Table 319.
Available Options
Value
SLEW_R0 to SLEW_R5
Description
R0 is the slowest rate. R5 is the fastest rate.
If QSF is not specified, the following table lists the default values.
Table 320.
Default Values
PCIe
Value
PCIe Gen1
PCIe Gen2
PCIe Gen3
Default Slew Rate
SLEW_R4
SLEW_R5
SLEW_R5
Value
(VCCT/VCCR)
0.95 V
1.03 V
1.12 V
Data rate < 1G
SLEW_R0
SLEW_R1
SLEW_R2
Assign To
TX serial data pin.
Non-PCIe
Default Slew Rate
Data rate ≥ 1G to <
3G
SLEW_R2
SLEW_R3
SLEW_R4
Data rate ≥ 3G to <
6G
SLEW_R3
SLEW_R4
SLEW_R5
Data rate ≥ 6G
SLEW_R5
SLEW_R5
SLEW_R5
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Note:
Syntax set_instance_assignment -name XCVR_A10_TX_SLEW_RATE_CTRL <value>
-to <tx_serial_data pin name>
Currently, the Quartus Prime software doesn't choose the default values for Non-PCIe mode. You must specify the setting in the .qsf file.
8.7. Transmitter Pre-Emphasis Analog Settings
The programmable pre-emphasis block in the transmit buffer amplifies the high frequencies in the transmit data to compensate for attenuation in the transmission media.
Note: Ignore all the pre-emphasis QSF assignments for PCIe Gen1 and Gen2 if your transceiver link is within the PCI Express spec requirements. Quartus Prime assigns default values for these parameters.
8.7.1. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
Pin planner or Assignment Editor Name
Transmitter Pre-Emphasis First Pre-Tap Polarity
Description
Controls the polarity of the first pre-tap for pre-emphasis. The default value is
FIR_PRE_1T_NEG.
Table 321.
Available Options
Value
FIR_PRE_1T_POS
FIR_PRE_1T_NEG
Description
Positive pre-tap 1
Negative pre-tap 1
Assign To
TX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
<value> -to <tx_serial_data pin name>
8.7.2. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
Pin Planner or Assignment Editor Name
Transmitter Pre-Emphasis Second Pre-Tap Polarity
Description
Controls the polarity of the second pre-tap for pre-emphasis. The default value is
FIR_PRE_2T_NEG.
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Table 322.
Available Options
Value
FIR_PRE_2T_POS
FIR_PRE_2T_NEG
Assign To
TX serial data pin.
Syntax
Description
Positive pre-tap 2
Negative pre-tap 2 set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
<value> -to <tx_serial_data pin name>
8.7.3. XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
Pin planner or Assignment Editor Name
Transmitter Pre-Emphasis First Post-Tap Polarity
Description
Controls the polarity of the first post-tap for pre-emphasis. The default value is
FIR_POST_1T_NEG.
Table 323.
Available Options
Value
FIR_POST_1T_POS
FIR_POST_1T_NEG
Description
Positive post-tap 1
Negative post-tap1
Assign To
TX serial data pin.
Syntax set_instance_assignment -name
XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP <value> -to <tx_serial_data pin name>
8.7.4. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
Pin planner or Assignment Editor Name
Transmitter Pre-Emphasis Second Post-Tap Polarity
Description
Controls the polarity of the second post-tap for pre-emphasis. The default value is
FIR_POST_2T_NEG.
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Table 324.
Available Options
Value
FIR_POST_2T_POS
FIR_POST_2T_NEG
Assign To
TX serial data pin.
Syntax
Description
Positive post-tap 2
Negative post-tap 2 set_instance_assignment -name
XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP <value> -to <tx_serial_data pin name>
8.7.5. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
Pin planner or Assignment Editor Name
Transmitter Pre-Emphasis First Pre-Tap Magnitude
Description
Controls the magnitude of the first pre-tap for pre-emphasis. The default value is 0.
Table 325.
Available Options
Value
0 – 16
Description
Magnitude 0 – 16
Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings.
Assign To
TX serial data pin.
Syntax set_instance_assignment -name
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T <value> -to
<tx_serial_data pin name>
Related Information
Arria 10 Pre-Emphasis and Output Swing Settings
8.7.6. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
Pin planner or Assignment Editor Name
Transmitter Pre-Emphasis Second Pre-Tap Magnitude
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Description
Controls the magnitude of the second pre-tap for pre-emphasis. The default value is
0.
Table 326.
Available Options
Value
0 – 7
Description
Magnitude 0 – 7
Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings.
Assign To
TX serial data pin.
Syntax set_instance_assignment -name
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T <value> -to
<tx_serial_data pin name>
Related Information
Arria 10 Pre-Emphasis and Output Swing Settings
8.7.7. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
Pin planner or Assignment Editor Name
Transmitter Pre-Emphasis First Post-Tap Magnitude
Description
Controls the magnitude of the first post-tap for pre-emphasis. The default value is 0.
Table 327.
Available Options
Value
0 –25
Description
Magnitude 0 –25
Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings.
Assign To
TX serial data pin.
Syntax set_instance_assignment -name
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP <value> -to
<tx_serial_data pin name>
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Related Information
Arria 10 Pre-Emphasis and Output Swing Settings
8.7.8. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
Pin planner or Assignment Editor Name
Transmitter Pre-Emphasis Second Post-Tap Magnitude
Description
Controls the magnitude of the second post-tap for pre-emphasis. The default value is
0.
Table 328.
Available Options
Value
0 – 12
Description
Magnitude 0 – 12
Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings.
Assign To
TX serial data.
Syntax set_instance_assignment -name
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP <value> -to
<tx_serial_data pin name>
Related Information
Arria 10 Pre-Emphasis and Output Swing Settings
8.8. Transmitter VOD Settings
8.8.1. XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
Pin planner or Assignment Editor Name
Transmitter Output Swing Level
Description
Controls the transmitter programmable output differential voltage swing. The default value is 31.
Note: Ignore this assignment for PCIe Gen1 and Gen2 if your transceiver link is within the
PCI Express* spec requirements. The Quartus Prime software assigns default value for this parameter.
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Table 329.
Available Options
Value
0 – 31
Note:
Description
Magnitude 0 – 31
Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings.
Assign To
TX serial data pin.
Syntax set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
<value> -to <tx_serial_data pin name>
Related Information
Arria 10 Pre-Emphasis and Output Swing Settings
8.9. Dedicated Reference Clock Settings
8.9.1. XCVR_A10_REFCLK_TERM_TRISTATE
Pin planner or Assignment Editor Name
Dedicated Reference Clock Pin Termination
Description
Specifies if the termination for dedicated reference clock pin is tri-stated. It defaults to
TRISTATE_OFF for non-HCSL cases.
Table 330.
Available Options
Value
TRISTATE_OFF
TRISTATE_ON
Description
Internal termination enabled and on-chip biasing circuitry enabled
Internal termination tri-stated. Off-chip termination and biasing circuitry must be implemented
Table 331.
Rules
I/O Standard
HCSL
CML
LVPECL
LVDS
Assign To
Reference clock pin.
Value
TRISTATE_ON
TRISTATE_OFF
TRISTATE_OFF
TRISTATE_OFF
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Syntax set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE
<value> -to <dedicated refclk pin name>
8.9.2. XCVR_A10_TX_XTX_PATH_ANALOG_MODE
Pin planner or Assignment Editor Name
Transmitter Analog Presets
Description
Specifies the TX pin swing settings such as vod output swing control, pre-emphasis and slew rate settings for various protocols. The presets are set by selecting an analog_mode setting. The selection is done as a .QSF setting on the TX pin. If individual .QSF is specified for the vod_output_swing_ctrl, pre-emphasis settings, the individual .QSF overrides the preset settings. The parameter defaults to
USER_CUSTOM, which requires the individual .QSF to be set. Available TX preset values are shown in the Assignment Editor, Transmitter Analog Preset assignment section.
8.10. Unused Transceiver RX Channels Settings
Add the following Intel Arria 10 QSF assignments to prevent performance degradation of unused RX serial clock over time. You can either use a global assignment or per-pin assignments.
Syntax set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to
<pin name>
8.11. Analog Parameter Settings Revision History
Changes Document
Version
2017.11.06
2016.10.31
2016.05.02
Made the following changes:
• Changed all default values of RADP_VGA_SEL to 4 in the "XCVR_A10_RX_ADP_VGA_SEL" section.
Made the following changes:
• Added the Value in Assignment Editor column to the table in the
"XCVR_A10_RX_ONE_STAGE_ENABLE" section.
• Added a note to the "XCVR_A10_TX_SLEW_RATE_CTRL" section.
Made the following changes:
• Updated that "DFE continuous mode" is not supported any more. DFE is supported in three modes-
Disabled, Manual, Adaptation Enabled.
• Changed the "Arria 10 Register Map” for available DFE modes, CTLE and VGA modes.
• Changed the maximum supported data rate for GT devices to 25.8 G.
continued...
Intel ®
606
Arria ® 10 Transceiver PHY User Guide
8. Analog Parameter Settings
UG-01143 | 2018.06.15
Document
Version
2016.02.11
2015.12.18
2015.11.02
2015.05.11
2014.12.15
2014.08.15
Changes
• Removed the ODI section from 'Register Map' tab.
• Changed the DFE adaptation mode from "Continuous" to "Adaptation enabled".
• Changed the DFE adaptation mode from "Continuous" to "Adaptation enabled".
Made the following changes:
• Updated the maximum data rate to 25.8 Gbps.
Made the following changes:
• Updated the “Available Options” table for non-HCSL standards, in the“Dedicated Reference Clock
Settings” section.
Made the following changes:
• Changed the setting for "XCVR_A10_RX_EQ_DC_GAIN_TRIM" parameter in the CTLE Settings section.
• Updated the "Analog Parameter Settings List" table to reflect the number of DFE fixed taps.
• Updated "DFE Fixed Tap Assignments" table in the Decision Feedback Equalizer (DFE) Settings section.
• Updated descriptions for XCVR_A10_RX_LINK QSF assignment in “Receiver General Analog
Settings” section.
• Updated description for XCVR_A10_RX_EQ_DC_GAIN_TRIM QSF,
XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL QSF,XCVR_A10_RX_ADP_CTLE_ACGAIN_4S QSF, and
XCVR_A10_RX_ADP_VGA_SEL QSF assignments in “Receiver Analog Equalization Settings” section.
• Updated description for XCVR_A10_TX_LINK QSF, XCVR_A10_TX_SLEW_RATE_CTRL QSF, and
XCVR_A10_TX_LINK QSF assignments in “Transmitter General Analog Settings” section.
Made the following changes:
• Corrected typos in the Syntax description of each parameter setting.
• Added the XCVR_A10_TX_SLEW_RATE_CTRL parameter.
• Changed the available values for the following parameters:
— XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
— XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
— XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
Made the following changes:
• Modified the Rules section for XCVR_A10_TX_COMPENSATION_EN.
• Changed Available Options for XCVR_A10_RX_ONE_STAGE_ENABLE parameter settings table.
• Changed the "XCVR_A10_RX_ADP_CTLE_ACGAIN_4S" parameter setting.
• Added "XCVR_VCCR_VCCT_VOLTAGE" parameter setting.
Initial release.
Intel ® Arria ® 10 Transceiver PHY User Guide
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