Definition: Device Support Level. Intel Arria 10 series

2. Implementing Protocols in Arria 10 Transceivers

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Definition: Device Support Level

Intel FPGA IP cores provide the following support for Intel FPGA device families:

• Preliminary support—Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. This IP core can be used in production designs with caution.

• Final support—Intel verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. This IP core is ready to be used in production designs.

2.6.5.1.4. Resource Utilization

The following estimates are obtained by compiling the PHY IP core with the Intel

Quartus Prime software.

Table 153.

Resource Utilization

Arria 10

Device

1G/2.5G

Speed

1G/2.5G with IEEE

1588v2 enabled

1G/2.5G/5G/10G

1G/2.5G/5G/10G

(USXGMII)

ALMs

550

1200

1150

650

ALUTs

750

1850

1500

800

Logic Registers

1200

2550

2550

1500

Memory Block

2 (M20K)

2 (M20K)

6 (M20K)

3 (M20K)

2.6.5.2. Using the IP Core

The Intel FPGA IP Library is installed as part of the Intel Quartus Prime installation process. You can select the 1G/2.5G/5G/10G Multi-rate Ethernet IP core from the library and parameterize it using the IP parameter editor.

2.6.5.2.1. Parameter Settings

You customize the PHY IP core by specifying the parameters in the parameter editor in the Intel Quartus Prime software. The parameter editor enables only the parameters that are applicable to the selected speed.

Table 154.

1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters

Speed

Name

Enable IEEE 1588 Precision

Time Protocol

Value

2.5G

1G/2.5G

1G/2.5G/5G/10G

On, Off

Description

The operating speed of the PHY.

Connect to MGBASE-T PHY On, Off

Select this parameter for the PHY to provide latency information to the MAC. The MAC requires this information if it enables the IEEE 1588v2 feature.

This parameter is enabled only for 2.5G and 1G/2.5G.

Select this option when the external PHY is MGBASE-T compatible.

This parameter is enabled for 2.5G, 1G/2.5G, and 1G/

2.5G/10G (MGBASE-T) modes.

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Name

Connect to NBASE-T PHY

PHY ID (32 bit)

Value

On, Off

32-bit value

Description

Select this option when the external PHY is NBASE-T compatible.

This parameter is enabled for 1G/2.5G/5G/10G

(USXGMII) modes.

An optional 32-bit unique identifier:

• Bits 3 to 24 of the Organizationally Unique Identifier

(OUI) assigned by the IEEE

• 6-bit model number

• 4-bit revision number

If unused, do not change the default value, which is

0x00000000.

Specify the frequency of the reference clock for 10GbE.

Reference clock frequency for

10 GbE (MHz)

Selected TX PMA local clock division factor for 1 GbE

Selected TX PMA local clock division factor for 2.5 GbE

Enable Altera Debug Master

Endpoint

Enable capability registers

Set user-defined IP identifier

Enable control and status registers

Enable PRBS soft accumulators

322.265625, 644.53125

1

,

2

,

4

,

8

1

,

2

On, Off

On, Off

User-specified

On, Off

On, Off

This parameter is the local clock division factor in the 1G mode. It is directly mapped to the Native PHY IP Core

GUI options.

This parameter is the local clock division factor in the

2.5G mode. It is directly mapped to the Native PHY IP

Core GUI options.

Available in Native PHY and TX PLL IP parameter editors.

When enabled, the Altera Debug Master Endpoint

(ADME) is instantiated and has access to the Avalon-MM interface of the Native PHY. You can access certain test and debug functions using System Console with the

ADME. Refer to the Embedded Debug Features section for more details about ADME.


Enables capability registers. These registers provide high-level information about the transceiver channel's /

PLL's configuration.


Sets a user-defined numeric identifier that can be read from the user_identifier registers are enabled.

offset when the capability


Enables soft registers for reading status signals and writing control signals on the PHY /PLL interface through the ADME or reconfiguration interface.

Available in Native PHY IP parameter editor only.

Enables soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and checker.

Related Information

Embedded Debug Features

on page 544

2.6.5.2.2. Timing Constraints

Constrain the PHY based on the fastest speed. For example, if you configure the PHY as 1G/2.5G, constrain it based on 2.5G.

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For the 1G/2.5G/5G/10G operating mode, constrain the PHY for the 10G datapath as well as the 1G/2.5G datapath. Refer to the example provided:

<Installation Directory>

/ip/altera/ethernet/alt_mge_phy/example/ alt_mge_phy_multi_speed_10g.sdc

.

2.6.5.2.3. Changing the PHY's Speed

You can change the PHY's speed through the reconfiguration block.

1. The user application initiates the speed change by writing to the corresponding register of the reconfiguration block.

2. The reconfiguration block performs the following steps:

• In Arria 10 devices: a. Sets the xcvr_mode

signal of the 1G/2.5G/5G/10G Multi-rate Ethernet

PHY IP core to the requested speed.

b. Reads the generated .mif file for the configuration settings and configures the transceiver accordingly.

The

.mif

files, alt_mge_phy_reconfig_parameters_CFG*.mif

, are generated in the <IP working directory>

/ altera_xcvr_native_a10_

<version>

/synth/reconfig

directory.

c. Selects the corresponding transceiver PLL.

d. Triggers the transceiver recalibration.

3. The reconfiguration block triggers the PHY reset through the transceiver reset controller.

2.6.5.3. Configuration Registers

You can access the 16-bit configuration registers via the Avalon-MM interface. These configuration registers apply only to 2.5G and 1G/2.5G operating modes.

Observe the following guidelines when accessing the registers:

• Do not write to reserved or undefined registers.

• When writing to the registers, perform read-modify-write to ensure that reserved or undefined register bits are not overwritten.

Table 155.

PHY Register Definitions

Addr Name Description

0x00 control

Access HW Reset

Value

RWC 0 • Bit [15]: reset.

RESET

. Set this bit to 1 to trigger a soft

The PHY clears the bit when the reset is completed.

The register values remain intact during the reset.

• Bit[14]:

LOOPBACK

. Set this bit to 1 to enable loopback on the serial interface.

• Bit [12]:

AUTO_NEGOTIATION_ENABLE to 1 to enable auto-negotiation.

. Set this bit

Auto-negotiation is supported only in 1GbE.

Therefore, set this bit to 0 when you switch to a speed other than 1GbE.

RW

RW

0

0 continued...


203

0x01

0x04

0x05

Addr

0x02:0x03


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Name status phy_identifier

Description

• Bit [9]:

RESTART_AUTO_NEGOTIATION to 1 to restart auto-negotiation.

. Set this bit

The PHY clears the bit as soon as auto-negotiation is restarted.

• The rest of the bits are reserved.

• Bit [5]:

AUTO_NEGOTIATION_COMPLETE

. A value of

"1" indicates that the auto-negotiation is completed.

• Bit [3]:

AUTO_NEGOTIATION_ABILITY negotiation.

. A value of

"1" indicates that the PCS function supports auto-

• Bit [2]:

LINK_STATUS established.

. A value of "0" indicates that the link is lost. Value of 1 indicates that the link is


The value set in the PHY_IDENTIFIER parameter.

Access HW Reset

Value

RWC 0

—

RO

RO

RO

—

RO

—

—

0

1

0

—

Value of

PHY_IDEN

TIFIER parameter

— dev_ability

Use this register to advertise the device abilities during auto-negotiation.

• Bits [13:12]:

RF

. Specify the remote fault.

— 00: No error.

— 01: Link failure.

— 10: Offline.

— 11: Auto-negotiation error.

• Bits [8:7]:

PS

. Specify the PAUSE support.

— 00: No PAUSE.

— 01: Symmetric PAUSE.

— 10: Asymmetric PAUSE towards the link partner.

— 11: Asymmetric and symmetric PAUSE towards the link device.

• Bit [5]:

FD

. Ensure that this bit is always set to 1.


partner_ability

The device abilities of the link partner during autonegotiation.

• Bit [14]:

ACK

. A value of "1" indicates that the link partner has received three consecutive matching ability values from the device.

• Bits [13:12]:

RF

. The remote fault.

— 00: No error.

— 01: Link failure.

— 10: Offline.

— 11: Auto-negotiation error.

RW

RW

RW

—

—

RO

RO

00

11

1

—

—

0


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Addr

0x06

0x07

0x08

0x09:0x0F

0x10

0x11

0x12:0x13

0x14:0x1F

0x400

Name an_expansion device_next_page

Description

• Bits [8:7]:

PS

. The PAUSE support.

— 00: No PAUSE.

— 01: Symmetric PAUSE.

— 10: Asymmetric PAUSE towards the link partner.

— 11: Asymmetric and symmetric PAUSE towards the link device.

• Bit [6]:

HD

. A value of "1" indicates that half-duplex is supported.

• Bit [5]:

FD

. A value of "1" indicates that full-duplex is supported.


The PCS capabilities and auto-negotiation status.

Bit [1]:

PAGE_RECEIVE

. A value of "1" indicates that the partner_ability register has been updated. This bit is automatically cleared once it is read.

Bit [0]:

LINK_PARTNER_AUTO_NEGOTIATION_ABLE value of "1" indicates that the link partner supports auto-negotiation.

. A

Access HW Reset

Value

RO 0

RO

RO

—

—

RO

RO

0

0

—

—

0

0

The PHY does not support the next page feature. These registers are always set to 0.

RO

RO

0

0 partner_next_pag e

Reserved scratch rev

—

Provides a memory location to test read and write operations.

The current version of the PHY IP core.

—

RW

RO

—

0

RW

Current version of the PHY

0 link_timer

Reserved

21-bit auto-negotiation link timer.

• Offset 0x12: link_timer[15:0]. Bits [8:0] are always be set to 0.

• Offset 0x13: link_timer[20:16] occupies the lower 5 bits. The remaining 11 bits are reserved and must always be set to 0.

— usxgmii_control

Control Register

Bit [0]:

USXGMII_ENA

:

• 0: 10GBASE-R mode

• 1: USXGMII mode

Bit [1]:

USXGMII_AN_ENA is set to 1:

is used when

USXGMII_ENA

• 0: Disables USXGMII Auto-Negotiation and manually configures the operating speed with the

USXGMII_SPEED

register.

• 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto-

Negotiation.

—

—

RW

RW

—

—

0x0

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0x401

Addr

0x402:0x404

0x405

Name Description

Bit [4:2]:

USXGMII_SPEED

is the operating speed of the PHY in USXGMII mode and to 0.

USE_USXGMII_AN

is set

• 3’b000: Reserved


• 3’b010: 1G

• 3’b011: 10G

• 3’b100: 2.5G

• 3’b101: 5G



Bit [8:5]: Reserved

Bit [9]: RESTART_AUTO_NEGOTIATION

Write 1 to restart Auto-Negotiation sequence The bit is cleared by hardware when Auto-Negotiation is restarted.

Access HW Reset

Value

RW 0x0

—

RWC

(hardw are selfclear)

—

—

—

—

RO

—

0x0

—

—

—

—

0x0 usxgmii_status

Reserved usxgmii_partner_ ability

Bit [15:10]: Reserved


Status Register

Bit [1:0]: Reserved

Bit [2]:

LINK_STATUS all speeds

indicates link status for USXGMII

• 1: Link is established

• 0: Link synchronization is lost, a 0 is latched

Bit [3]: Reserved

Bit [4]: Reserved

Bit [5]:

AUTO_NEGOTIATION_COMPLETE

A value of 1 indicates the Auto-Negotiation process is completed.



—

Device abilities advertised to the link partner during

Auto-Negotiation

Bit [0]: Reserved

Bit [6:1]: Reserved

Bit [7]:

EEE_CLOCK_STOP_CAPABILITY

Indicates whether or not energy efficient ethernet (EEE) clock stop is supported.

• 0: Not supported

• 1: Supported

Bit [8]:

EEE_CAPABILITY

Indicates whether or not EEE is supported.

• 0: Not supported

• 1: Supported

—

—

RO

—

—

—

—

—

—

RO

RO

—

—

0x0

—

—

—

—

—

—

0x0

0x0 continued...

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Addr

0x406:0x411

0x412

0x413:0x41F

0x461

Name

Reserved usxgmii_link_tim er

Reserved phy_serial_loopb ack

Description

Bit [11:9]:

SPEED

• 3'b000: 10M

• 3'b001: 100M

• 3'b010: 1G

• 3'b011: 10G

• 3'b100: 2.5G

• 3'b101: 5G

• 3'b110: Reserved

• 3'b111: Reserved

Bit [12]:

DUPLEX

Indicates the duplex mode.

• 0: Half duplex

• 1: Full duplex

Bit [13]: Reserved

Bit [14]:

ACKNOWLEDGE

A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.

Bit [15]:

LINK

Indicates the link status.

• 0: Link down

• 1: Link up


—

Auto-Negotiation link timer. Sets the link timer value in bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensure that it matches the link timer value of the external NBASE-T

PHY IP Core.

The reset value sets the link timer to approximately 1.6

ms.

Bits [13:0] are reserved and always set to 0.

—

Configures the transceiver serial loopback in the PMA from TX to RX.

Bit [0]

• 0: Disables the PHY serial loopback

• 1: Enables the PHY serial loopback



Access HW Reset

Value

RO 0x0

RO

—

RO

RO

—

—

[19:14

]: RW

[13:0]:

RO

—

—

RW

—

—

0x0

—

0x0

0x0

—

—

[19:14]:

0x1F

[13:0]:

0x0

—

—

—

—

0x0

2.6.5.3.1. Register Map

You can access the 16-bit/32-bit configuration registers (

37 )

interface.

via the Avalon-MM

(37) These registers are identical to the Intel Arria 10 variation of 1G/2.5G/5G/10G Multi-rate

Ethernet PHY IP core.


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Table 156.

Register Map

Address Range

0x00 : 0x1F

0x400 : 0x41F

0x461

Usage

1000BASE-X/SGMII

USXGMII

Serial Loopback

Bit

16

32

32

Configuration

2.5G, 1G/2.5G, 10M/

100M/1G/2.5, 10M/

100M/1G/2.5G/10G

(MGBASE-T), 1G/2.5G/10G

(MGBASE-T)

1G/2.5G/5G/10G (USXGMII)

1G/2.5G/5G/10G (USXGMII)

2.6.5.3.2. Definition: Register Access

Table 157.

Types of Register Access

RO

RW

RWC

Access Definition

Read only.

Read and write.

Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP core clears the bit(s) upon executing the instruction.

2.6.5.4. Interface Signals

Figure 80.

PHY Interface Signals

Serial

Interface tx_serial_clk rx_cdr_refclk rx_cdr_refclk1 rx_pma_clkout tx_serial_data rx_serial_data

Avalon-MM

Control & Status

Interface csr_clk csr_address[4:0] csr_write csr_read csr_writedata[] (i) csr_readdata[] (i) csr_waitrequest xcvr_mode[1:0] operating_speed[2:0] latency_measure_clk

Reset reset pll_powerdown tx_digitalreset rx_digitalreset tx_analogreset rx_analogreset

Status

Interface led_link led_char_err led_disp_err led_an rx_block_lock

PHY tx_clkout gmii16b_tx_d[15:0] gmii16b_tx_en[1:0] gmii16b_tx_err[1:0] gmii16b_tx_latency[21:0] rx_clkout gmii16b_rx_d[15:0] gmii16b_rx_dv[1:0] gmii16b_rx_err[1:0] gmii16b_rx_latency[21:0] xgmii_tx_coreclkin xgmii_tx_control[7:0] xgmii_tx_data[63:0] xgmii_tx_valid xgmii_rx_coreclkin xgmii_rx_control[7:0] xgmii_rx_data[63:0] xgmii_rx_valid rx_is_lockedtodata tx_cal_busy rx_cal_busy reconfig_clk reconfig_reset reconfig_address[9:0] reconfig_write reconfig_read reconfig_writedata[31:0] reconfig_readdata[31:0] reconfig_waitrequest

TX GMII

RX GMII

TX XGMII

RX XGMII

Arria 10

Transceiver Status &

Reconfiguration Interface

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2.6.5.4.1. Clock and Reset Signals

Table 158.

Clock and Reset Signals

Signal Name

Clock signals

Direction tx_clkout

Output rx_clkout

Output

Width

1

1 csr_clk xgmii_tx_coreclkin xgmii_rx_coreclkin latency_measure_clk tx_serial_clk rx_cdr_refclk rx_cdr_refclk_1 rx_pma_clkout

Reset signals reset tx_analogreset

Input

Input

Input

Input

Input

Input

Input

Output

Input

Input

1

1

1

1

1

1

1

1

1-3

1

Description

GMII TX clock, derived from tx_serial_clk[1:0]

. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE.

GMII RX clock, derived from tx_serial_clk[1:0]

. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE.

Clock for the Avalon-MM control and status interface. Intel recommends 125 – 156.25 MHz for this clock.

XGMII TX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 1G/

2.5G/5G/10G (USXGMII) mode. Synchronous to tx_serial_clk

with zero ppm.

XGMII RX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 1G/

2.5G/5G/10G (USXGMII) mode.

Sampling clock for measuring the latency of the

16-bit GMII datapath. This clock operates at 80

MHz and is available only when the IEEE 1588v2 feature is enabled.

Serial clock from transceiver PLLs.

• 2.5GbE: Connect bit [0] to the transceiver PLL.

This clock operates at 1562.5 MHz.

• 1GbE: Connect bit [1] to the transceiver PLL.

This clock operates at 625 MHz.

• 10GbE: Connect bit [2] to the transceiver PLL.

This clock operates at 5156.25 MHz.

• 1G/2.5G/5G/10G (USXGMII) mode: Connect bit

[0] to 5156.25 MHz.

125-MHz RX CDR reference clock for 1GbE and

2.5GbE

RX CDR reference clock for 10GbE. The frequency of this clock can be either 322.265625 MHz or

644.53125 MHz, as specified by the Reference

clock frequency for 10 GbE (MHz) parameter setting.

Recovered clock from CDR, operates at the following frequency:

• 1GbE: 125 MHz

• 2.5GbE: 312.5 MHz

• 5GbE/10GbE: 322.265625 MHz

Active-high global reset. Assert this signal to trigger an asynchronous global reset.

Connect this signal to the Transceiver PHY Reset

Controller IP core. When asserted, triggers an asynchronous reset to the analog block on the TX path.

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Signal Name tx_digitalreset rx_analogreset rx_digitalreset

Direction

Input

Input

Input

Width

1

1

1

Description


Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the TX path.


Controller IP core. When asserted, triggers an asynchronous reset to the receiver CDR.


Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the RX path.

2.6.5.4.2. Operating Mode and Speed Signals

Table 159.

Transceiver Mode and Operating Speed Signals

Signal Name xcvr_mode operating_speed

Direction

Input

Output

Width

2

3

Description

Connect this signal to the reconfiguration block.

Use the values below to set the speed:

• 0x0 = 1G

• 0x1 = 2.5G

• 0x3 = 10G

Connect this signal to the MAC. This signal provides the current operating speed of the PHY:

• 0x0 = 10G

• 0x1 = 1G

• 0x4 = 2.5G

• 0x5 = 5G

2.6.5.4.3. GMII Signals

The 16-bit TX and RX GMII supports 1GbE and 2.5GbE at 62.5 MHz and 156.25 MHz respectively.

Table 160.

GMII Signals

Signal Name Direction

TX GMII signals—synchronous to tx_clkout gmii16b_tx_d

Input

Width

16

Description gmii16b_tx_en gmii16b_tx_err

Input

Input

2

2

TX data from the MAC. The MAC sends the lower byte first followed by the upper byte.

When asserted, indicates the start of a new frame from the MAC. Bit[0] corresponds to gmii16b_tx_d

[7:0]; bit[1] corresponds to gmii16b_tx_d

[15:8].

This signal remains asserted until the PHY receives the last byte of the data frame.

When asserted, indicates an error. Bit[0] corresponds to gmii16b_tx_err

[7:0]; bit[1] corresponds to gmii16b_tx_err

[15:8].

The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.

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Signal Name gmii16b_tx_latency

Direction

Output

Width

22

Description

The latency of the PHY excluding the PMA block on the TX datapath:

• Bits [21:10]: The number of clock cycles.

• Bits [9:0]: The fractional number of clock cycles.

This signal is available when only the Enable IEEE

1588 Precision Time Protocol parameter is selected.

RX GMII signals—synchronous to rx_clkout gmii16b_rx_d

Output gmii16b_rx_err gmii16b_rx_dv gmii16b_rx_latency

Output

Output

Output

16

2

2

22

RX data to the MAC. The PHY sends the lower byte first followed by the upper byte. Rate matching is done by the PHY on the RX data from the RX recovered clock to rx_clkout

.

When asserted, indicates an error. Bit[0] corresponds to gmii16b_rx_err

[7:0]; bit[1] corresponds to gmii16b_rx_err

[15:8].

The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.

When asserted, indicates the start of a new frame.

Bit[0] corresponds to gmii16b_rx_d

[7:0]; bit[1] corresponds to gmii16b_rx_d

[15:8].

This signal remains asserted until the PHY sends the last byte of the data frame.

The latency of the PHY excluding the PMA block on the RX datapath:

• Bits [21:10]: The number of clock cycles.

• Bits [9:0]: The fractional number of clock cycles.

This signal is available only when the Enable IEEE

1588 Precision Time Protocol parameter is selected.

2.6.5.4.4. XGMII Signals

The XGMII supports 10GbE at 156.25 MHz.

Table 161.

XGMII Signals

Signal Name Direction Width

TX XGMII signals—synchronous to xgmii_tx_coreclkin xgmii_tx_data

Input 64, 32 xgmii_tx_control

Input 8, 4

Description

TX data from the MAC. The MAC sends the data in the following order: bits[7:0], bits[15:8], and so forth.

The width is:

• 64 bits for 1G/2.5G/10G configurations.

• 32 bits for 1G/2.5G/5G/10G configurations.

TX control from the MAC:

• xgmii_tx_control

[0] corresponds to xgmii_tx_data

[7:0]

• xgmii_tx_control

[1] corresponds to xgmii_tx_data

[15:8]

• and so forth.

The width is: continued...


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Signal Name xgmii_tx_valid

Direction

Output

Width

1

Description



Indicates valid data on xgmii_tx_control

and xgmii_tx_data

from the MAC.

Your logic/MAC must toggle the valid data as shown below:

1G

2.5G

5G

10G

Speed Toggle Rate

Asserted once every 10 clock cycles



Always asserted

RX XGMII signals—synchronous to xgmii_rx_coreclkin xgmii_rx_data

Output 64, 32 xgmii_rx_control xgmii_rx_valid

Output

Output

8, 4

1

RX data to the MAC. The PHY sends the data in the following order: bits[7:0], bits[15:8], and so forth.

The width is:



RX control to the MAC.

• xgmii_rx_control

[0] corresponds to xgmii_rx_data

[7:0]

• xgmii_rx_control

[1] corresponds to xgmii_rx_data

[15:8]

• and so forth.

The width is:



Indicates valid data on xgmii_rx_control

and xgmii_rx_data

from the MAC.

The toggle rate from the PHY is shown in the table below.

Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.

Speed

1G

2.5G

5G

10G

Toggle Rate




Always asserted

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2.6.5.4.5. Status Signals

Table 162.

Status Signals

Signal Name Direction Clock

Domain

Width Description led_char_err led_link led_disp_err led_an rx_block_lock

Output

Output

Output

Output

Output

Synchronous to tx_clkout

Synchronous to rx_clkout



1

1

1

1

1

Asserted when a 10-bit character error is detected in the RX data.

Asserted when the link synchronization for

1GbE or 2.5GbE is successful

Asserted when a 10-bit running disparity error is detected in the RX data.

Asserted when auto-negotiation is completed.

Asserted when the link synchronization for

10GbE is successful.

2.6.5.4.6. Serial Interface Signals

The serial interface connects to an external device.

Table 163.

Serial Interface Signals

Signal Name tx_serial_data rx_serial_data

Direction

Output

Input

Width

1

1

TX data.

RX data.

Description

2.6.5.4.7. Transceiver Status and Reconfiguration Signals

Table 164.

Control and Status Signals

Signal Name rx_is_lockedtodata tx_cal_busy

Direction

Output

Output

Output

Width

1

1

1 rx_cal_busy

Transceiver reconfiguration signals for Arria 10 devices reconfig_clk

Input 1 reconfig_reset reconfig_address reconfig_write reconfig_read reconfig_writedata reconfig_readdata reconfig_waitrequest

Input

Input

Input

Input

Input

Output

Output

32

32

1

1

1

1

10

Description

Asserted when the CDR is locked to the RX data.

Asserted when TX calibration is in progress.

Asserted when RX calibration is in progress.

Reconfiguration signals connected to the reconfiguration block. The reconfig_clk

signal provides the timing reference for this interface.


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2.6.5.4.8. Avalon-MM Interface Signals

The Avalon-MM interface is an Avalon-MM slave port. This interface uses word addressing and provides access to the 16-bit configuration registers of the PHY.

Table 165.

Avalon-MM Interface Signals

Signal Name csr_address

Direction

Input

Width

5, 11 csr_read csr_readdata csr_write csr_writedata csr_waitrequest

Input

Output

Input

Input

Output

1

16, 32

1

16, 32

1

Description

Use this bus to specify the register address to read from or write to. The width is:

• 5 bits for 2.5G and 1G/2.5G configurations.


Assert this signal to request a read operation.

Data read from the specified register. The data is valid only when the csr_waitrequest deasserted. The width is:

signal is


• 32 bits for 1G/2.5G/5G/10G configurations. The upper 16 bits are reserved.

Assert this signal to request a write operation.

Data to be written to the specified register. The data is written only when the csr_waitrequest signal is deasserted. The width is:


• 32 bits for 1G/2.5G/5G/10G configurations. The upper 16 bits are reserved.

When asserted, indicates that the PHY is busy and not ready to accept any read or write requests.

• When you have requested for a read or write, keep the control signals to the Avalon-MM interface constant while this signal is asserted.

The request is complete when it is deasserted.

• This signal can be high or low during idle cycles and reset. Therefore, the user application must not make any assumption of its assertion state during these periods.

2.6.6. XAUI PHY IP Core

In a XAUI configuration, the transceiver channel data path is configured using a soft

PCS. The XAUI configuration provides the transceiver channel datapath, clocking, and channel placement guidelines. You can implement a XAUI link using the IP Catalog.

Under Ethernet in the Interfaces menu, select the XAUI PHY IP core. The XAUI PHY IP core implements the XAUI PCS in soft logic.

XAUI is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in the IEEE 802.3ae-2008 specification. The XAUI PHY uses the XGMII interface to connect to the IEEE802.3 MAC and Reconciliation Sublayer (RS). The IEEE

802.3ae-2008 specification requires the XAUI PHY link to support:

• A 10 Gbps data rate at the XGMII interface

• Four lanes each at 3.125 Gbps at the PMD interface

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Figure 81.

XAUI and XGMII Layers

LAN Carrier Sense Multiple

Access/Collision Detect (CSMA/CD)

Layers

Higher Layers

Logical Link Control (LLC)

OSI

Reference

Model Layers

MAC Control (Optional)

Media Access Control (MAC)

Application

Reconciliation

Presentation

10 Gigabit Media Independent Interface

Session

Transport

Optional

XGMII

Extender

XGMII Extender Sublayer

10 Gigabit Attachment Unit Interface

XGMII Extender Sublayer

10 Gigabit Media Independent Interface

Network

Data Link

PCS

PMA

PMD

Physical Layer Device

Physical

Medium Dependent Interface

Medium

10 Gbps

Intel's XAUI PHY IP core implements the IEEE 802.3 Clause 48 specification to extend the operational distance of the XGMII interface and reduce the number of interface signals.

XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC function and the Ethernet standard PHY component to one meter. The XAUI PHY IP core accepts 72-bit data (single data rate–SDR XGMII) from the application layer at

156.25 Mbps. The serial interface runs at 4 × 3.125 Gbps.

Figure 82.

XAUI PHY IP Core

XAUI PHY IP

SDR XGMII

72 bits @ 156.25 Mbps

XAUI PHY IP Core

PCS

8B/10B

Word Aligner

Phase Comp

Hard PMA

Avalon-MM

Control & Status

4

4

4 x 3.125 Gbps serial

Intel's third-party IP partner for Dual Data Rate XAUI (DDR XAUI or DXAUI) and

Reduced XAUI (RXAUI) support is MorethanIP (MTIP).


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XAUI does not support open compute project (OCP) networking.


• IEEE 802.3 Clause 48

• MorethanIP

2.6.6.1. Transceiver Datapath in a XAUI Configuration

The XAUI PHY IP core is partially implemented in soft logic inside the FPGA core. You must ensure that your channel placement is compatible with the soft PCS implementation.

Figure 83.

Transceiver Channel Datapath for XAUI Configuration

The XAUI configuration uses both the soft PCS and the Standard PCS as shown in the following figure.

Channel 3

Channel 2

Channel 1

Channel 0

FPGA Fabric

Soft PCS

Soft PCS

Soft PCS

Soft PCS

Channel 3

Channel 2

Channel 1

Channel 0

Portable solution using Custom PHY or Native PHY

Transmitter Standard PCS




Transmitter PMA Ch3

Transmitter PMA Ch2

Transmitter PMA Ch1

Transmitter PMA Ch0

16 20 20 10

20

Receiver Standard PCS

10 10

Receiver PMA

16 20 20 20

2.6.6.2. XAUI Supported Features

64-Bit SDR Interface to the MAC/RS

Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the XAUI PCS and the Ethernet MAC/RS. Each of the four XAUI lanes must transfer 8bit data and a 1-bit control code at both the positive and negative edge (double data rate) of the 156.25 MHz interface clock.

Arria 10 transceivers and a soft PCS solution in a XAUI configuration do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification.

Instead, they transfer 16-bit data and the 2-bit control code on each of the four XAUI lanes. The transfer occurs only at the positive edge (single data rate) of the 156.25

MHz interface clock.

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Figure 84.

Implementation of the XGMII Specification in Arria 10 Devices Configuration

The ATX PLL is only supported to drive the internal transceiver. The FPLL is only supported to drive xgmii_tx_clk

and xgmii_rx_clk

. Both the ATX PLL and the FPLL must be clocked by the same reference clock to maintain 0 ppm.

XGMII Transfer (DDR)

Interface Clock (156.25 MHz)

Lane 0

8-bit

D0 D1 D2 D3

Lane 1 D0 D1 D2 D3

D2

D2

D3

D3

Lane 2 D0

Lane 3

Arria 10 Soft PCS Interface (SDR)

Interface Clock (156.25 MHz)

D0

Lane 0

16-bit

{D1, D0}

D1

Lane 1 {D1, D0}

D1

{D3, D2}

{D3, D2}

Lane 2

{D1, D0} {D3, D2}

Lane 3 {D1, D0} {D3, D2}

8B/10B Encoding/Decoding

Each of the four lanes in a XAUI configuration supports an independent 8B/10B encoder/decoder as specified in Clause 48 of the IEEE802.3-2008 specification.

8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial data stream to five. This limit ensures DC balance as well as enough transitions for the receiver CDR to maintain a lock to the incoming data.

The XAUI PHY IP core provides status signals to indicate both running disparity and the 8B/10B code group error.


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Transmitter and Receiver State Machines

In a XAUI configuration, the Arria 10 soft PCS implements the transmitter and receiver state diagrams shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008 specification.

The transmitter state machine performs the following functions in conformance with the 10GBASE-X PCS:

• Encoding the XGMII data to PCS code groups

• Converting Idle ||I|| ordered sets into Sync ||K||, Align ||A||, and Skip ||R|| ordered sets

The receiver state machine performs the following functions in conformance with the

10GBASE-X PCS:

• Decoding the PCS code groups to XGMII data

• Converting Sync ||K||, Align ||A||, and Skip ||R|| ordered sets into Idle ||I|| ordered sets

Synchronization

The word aligner block in the receiver PCS of each of the four XAUI lanes implements the receiver synchronization state diagram shown in Figure 48-7 of the

IEEE802.3-2008 specification.

The XAUI PHY IP core provides a status signal per lane to indicate if the word aligner is synchronized to a valid word boundary.

Deskew

The lane aligner block in the receiver PCS implements the receiver deskew state diagram shown in Figure 48-8 of the IEEE 802.3-2008 specification.

The lane aligner starts the deskew process only after the word aligner block in each of the four XAUI lanes indicates successful synchronization to a valid word boundary.

The XAUI PHY IP core provides a status signal to indicate successful lane deskew in the receiver PCS.

Clock Compensation

The rate match FIFO in the receiver PCS datapath compensates up to ±100 ppm difference between the remote transmitter and the local receiver. It compensates by inserting and deleting Skip ||R|| columns, depending on the ppm difference.

The clock compensation operation begins after:

• The word aligner in all four XAUI lanes indicates successful synchronization to a valid word boundary.

• The lane aligner indicates a successful lane deskew.

The rate match FIFO provides status signals to indicate the insertion and deletion of the Skip ||R|| column for clock rate compensation.

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2.6.6.3. XAUI PHY Release Information

Table 166.

XAUI Release Information

Item

Version

Release Date

Product ID

Vendor ID

16.0

November 2016

00D7

6AF7

Description

2.6.6.4. XAUI PHY Device Family Support

IP cores provide either final or preliminary support for target Intel device families.

These terms have the following definitions:

• Final support—Verified with final timing models for this device.

• Preliminary support—Verified with preliminary timing models for this device.

Table 167.

Device Family Support

Device Family Support

Arria 10

XAUI

Preliminary


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2.6.6.5. Transceiver Clocking and Channel Placement Guidelines in XAUI

Configuration

Transceiver Clocking

Figure 85.

Transceiver Clocking for XAUI Configuration Without Phase Compensation

FIFO Enabled

The external ATX PLL generates the transmitter serial and parallel clocks for the four XAUI channels. You must instantiate the PLL and connect it to XAUI. The x6 clock line carries the transmitter serial and parallel clocks to the PMA and PCS of each of the four channels.

XAUI PHY IP Core

Channel 3

Channel 2

Channel 1

Channel 0

Soft PCS

Soft PCS

Soft PCS

Soft PCS

Channel 3

Channel 2

Channel 1

Channel 0





Transmitter PMA Ch 3




16 20 20 10 xgmii_tx_clk

16 20 20 20

/2

Parallel Clock


10 10

Receiver PMA

Note: xgmii_rx_clk

Parallel Clock

Parallel Clock

(Recovered) from Channel 0

/2

Parallel Clock (Recovered)

Master Clock Generation Block

(1)

ATX PLL

Serial Clock

(From the ×1 Clock Lines)

Clock Divider

Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)

Parallel Clock

Serial Clock

Parallel and Serial Clocks

Note:

1. Use the ATX PLL as the transmit PLL for XAUI support in Arria 10 devices.

When configuring ATX PLL, the PMA width setting must be set to 20-bit per transceiver channel. This ensures that the serial clock is running at 3.125 Gbps while the input reference clock is 156.25 MHz.

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Figure 86.

Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO

Enabled

When phase compensation FIFO is enabled, you can connect the core to different clocks on the Avalon-ST interface.

Parallel Clock

Parallel Clock (x6 Network)

Serial Clock

Parallel Recovered Clock

Parallel Recovered Clock 2

Serial Recovered Clock

XAUI PHY IP Core

Soft PCS

Transmitter Standard PCS Transmitter PMA

32/64b

Avalon-ST

Adapter

MAC

36/72b

XGMII

Adapter xgmii_tx_clk 156.25 MHz

Receiver Standard PCS Receiver PMA

156.25 MHz

Parallel Recovered Clock 2 (1) Parallel Recovered Clock

Serial Recovered Clock fPLL

REFCLK 156.25 MHz

ATX PLL x1 Network

Master CGB

Parallel Clock (x6 Network)

Serial Clock (x6 Network)

Note:

1. One recovered clock drives four XAUI channels.

2.6.6.6. XAUI PHY Performance and Resource Utilization

The following table lists the typical expected device resource utilization for different configurations using the current version of the Quartus II software targeting an Arria

10 device. The numbers of combinational ALUTs and logic registers are rounded to the nearest 100.

Table 168.

XAUI PHY Performance and Resource Utilization

Implementation

Soft XAUI 4

Number of 3.125

Gbps Channels

Combinational ALUTs

1700

Dedicated Logic

Registers

1700

M20K Memory Blocks

3

2.6.6.7. Parameterizing the XAUI PHY

This section contains the recommended parameter values for this protocol. Refer to

Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.

Complete the following steps to configure the XAUI PHY IP core in the IP Catalog:

1. For Which device family will you be using?, select Arria 10.

2. Click Installed IP

➤

Library

➤

Interface Protocols

➤

Ethernet

➤

XAUI PHY.

3. Use the tabs on the IP Catalog to select the options required for the protocol.

4. Refer to the following topics to learn more about the parameters: a. General Parameters


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b. Analog Parameters c. Advanced Options Parameters

5. Click Finish to generate your customized XAUI PHY IP core.


•

Using the Arria 10 Transceiver Native PHY IP Core

on page 45

•

XAUI PHY General Parameters on page 222

•

Analog Parameter Settings on page 585

•

XAUI PHY Advanced Options Parameters

on page 222

2.6.6.7.1. XAUI PHY General Parameters

This section describes the settings available on the General Options tab.

Table 169.

General Options

Name

Device family

XAUI interface type

Arria 10

Soft XAUI

Enable Sync-E support On / Off

Number of XAUI interfaces 1

Value Description

The target device family.

Implements the PCS in soft logic and the PMA in hard logic. Includes four channels.

Shows separate reference clocks for CDR PLL and TX PLL.

Specifies the number of XAUI interfaces. Only 1 is available in the current release.

2.6.6.7.2. XAUI PHY Advanced Options Parameters

This section describes the settings available on the Advanced Options tab.

Table 170.

Advanced Options

Name

Include control and status ports

Value

On / Off

Enable dynamic reconfiguration

Enable rx_recovered_clk pin

Enable phase compensation

FIFO

On / Off

On / Off

On / Off

Description

If you turn this option on, the top-level IP core includes the status signals and digital resets shown in XAUI Top-Level Signals

—Soft PCS and PMA and XAUI Top-Level Signals—Hard IP PCS and PMA. If you turn this option off, you can access control and status information using the Avalon-MM interface to the control and status registers. The default setting is off.

When you turn this option on, you can connect the dynamic reconfiguration ports to an external reconfiguration module.

When you turn this option on, the RX recovered clock signal is an output signal.

Enables the phase compensation FIFO to allow different clocks on the xgmii interface.

2.6.6.8. XAUI PHY Ports

The following figure illustrates the top-level signals of the XAUI PHY IP core for the soft IP implementation.

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Figure 87.

XAUI Top-Level Signals—Soft PCS and PMA

XAUI Top-Level Signals

SDR TX XGMII

SDR RX XGMII

Avalon-MM PHY

Management

Interface

Clocks

PLL xgmii_tx_dc[71:0] xgmii_tx_clk xgmii_rx_dc[71:0] xgmii_rx_clk xgmii_rx_inclk phy_mgmt_clk phy_mgmt_clk_reset phy_mgmt_address[8:0] phy_mgmt_writedata[31:0] phy_mgmt_readdata[31:0] phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest pll_ref_clk cdr_ref_clk pll_locked_i pll_powerdown_o tx_bonding_clock[5:0] pll_cal_busy_i xaui_rx_serial_data[3:0] xaui_tx_serial_data[3:0] rx_channelaligned rx_disperr[7:0] rx_errdetect[7:0] rx_syncstatus[7:0] reconfig_clk reconfig_reset reconfig_address[11:0] reconfig_writedata[31:0] reconfig_readdata[31:0] reconfig_write reconfig_read reconfig_waitrequest rx_recovered_clk[3:0] rx_ready tx_ready

Transceiver

Serial Data

RX Status

Optional

Avalon-MM

Dynamic

Reconfiguration

PMA

Channel

Controller

2.6.6.9. XAUI PHY Interfaces

The XAUI PCS interface to the FPGA fabric uses a SDR XGMII interface. This interface implements a simple version of the Avalon-ST protocol. The interface does not include ready or valid signals. Consequently, the sources always drive data and the sinks must always be ready to receive data.

For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Specifications.

Depending on the parameters you choose, the application interface runs at either

156.25 Mbps or 312.5 Mbps. At either frequency, data is only driven on the rising edge of clock. To meet the bandwidth requirements, the datapath is eight bytes wide with eight control bits, instead of the standard four bytes of data and four bits of control.

The XAUI PHY IP core treats the datapath as two, 32-bit data buses and includes logic to interleave them, starting with the low-order bytes.

Figure 88.

Interleaved SDR XGMII Data Mapping

Original XGMII Data

[63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0]

[63:56] [31:24] [55:48]


Avalon Interface Specifications

[23:16]

Interleaved Result

[47:40] [15:8] [39:32] [7:0]


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2.6.6.9.1. SDR XGMII TX Interface

Table 171.

SDR TX XGMII Interface

Signal Name xgmii_tx_dc[71:0]

Direction

Input xgmii_tx_clk

Input

Description

Contains 4 lanes of data and control for XGMII. Each lane consists of

16 bits of data and 2 bits of control. Synchronous to mgmt_clk

.

• Lane 0–[7:0]/[8], [43:36]/[44]

• Lane 1–[16:9]/[17], [52:45]/[53]

• Lane 2–[25:18]/[26], [61:54]/[62]

• Lane 3–[34:27]/[35],[70:63]/[71]

The XGMII SDR TX clock which runs at 156.25 MHz.

2.6.6.9.2. SDR XGMII RX Interface

Table 172.

SDR RX XGMII Interface

Signal Name xgmii_rx_dc_[71:0]

Direction

Output xgmii_rx_clk xgmii_rx_inclk

Output

Input

Description

Contains 4 lanes of data and control for XGMII. Each lane consists of

16 bits of data and 2 bits of control. Synchronous to mgmt_clk

.

• Lane 0–[7:0]/[8], [43:36]/[44]

• Lane 1–[16:9]/[17], [52:45]/[53]

• Lane 2–[25:18]/[26], [61:54]/[62]

• Lane 3–[34:27]/[35],[70:63]/[71]

The XGMII SDR RX clock which runs at 156.25 MHz.

The XGMII SDR RX input clock which runs at 156.25 MHz. This port is only available when Enable phase compensation FIFO is selected.

2.6.6.9.3. Transceiver Serial Data Interface

The XAUI transceiver serial data interface has four lanes of serial data for both the TX and RX interfaces. This interface runs at 3.125 Gbps. There is no separate clock signal because it is encoded in the data.

Table 173.

Serial Data Interface

Signal Name xaui_rx_serial_data[3:0] xaui_tx_serial_data[3:0]

Direction

Input

Output

Serial input data.

Serial output data.

Description

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2.6.6.9.4. XAUI PHY Clocks, Reset, and Powerdown Interfaces

Figure 89.

Clock Inputs and Outputs for IP Core with Soft PCS phy_mgmt_clk pll_ref_clk

XAUI Soft IP Core xgmii_tx_clk xgmii_rx_clk

Soft PCS

pma_pll_inclk sysclk pma_tx_clkout pma_rx_clkout pll_ref_clk

PMA

tx_clkout rx_recovered_clk

4

4

4 x 3.125 Gbps serial

Table 174.

Clock and Reset Signals

Signal Name pll_ref_clk

Direction

Input

Description

This is a 156.25 MHz reference clock that is used by the CDR logic.

2.6.6.9.5. XAUI PHY PMA Channel Controller Interface

Table 175.

PMA Channel Controller Signals

Signal Name rx_recovered_clk[3:0]

Direction

Output rx_ready tx_ready pll_cal_busy_i

Output

Output

Input

Description

This is the RX clock, which is recovered from the received data stream.

Indicates PMA RX has exited the reset state and the transceiver can receive data. Synchronous to mgmt_clk

.

Indicates PMA TX has exited the reset state and the transceiver can transmit data. Synchronous to mgmt_clk

.

Indicates the PLL calibration status.

2.6.6.9.6. XAUI PHY Optional PMA Control and Status Interface

Use the Avalon-MM PHY Management interface to read the state of the optional PMA control and status signals available in the XAUI PHY IP core registers. In some cases you may need to know the instantaneous value of a signal to ensure correct functioning of the XAUI PHY. In such cases, you can include the required signal in the top-level module of your XAUI PHY IP core.

Table 176.

Optional Control and Status Signals—Soft IP Implementation

Signal Name rx_channelaligned rx_disperr[7:0]

Direction

Output

Output

Description

When asserted, indicates that all 4 RX channels are aligned. Synchronous to to receive data.

mgmt_clk

. This signal is asserted when the RX lanes are fully aligned and ready

Received 10-bit code or data group has a disparity error. It is paired with rx_errdetect

which is also asserted when a disparity error occurs. The continued...


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Signal Name rx_errdetect[7:0] rx_syncstatus[7:0]

Direction

Output

Output

Description rx_disperr

signal is 2 bits wide per channel for a total of 8 bits per XAUI link. Synchronous to mgmt_clk

.

When asserted, indicates an 8B/10B code group violation. It is asserted if the received 10-bit code group has a code violation or disparity error. Use rx_errdetect

with the rx_disperr

signal to differentiate between a code violation error, a disparity error, or both. The rx_errdetect

signal is 2 bits wide per channel for a total of 8 bits per XAUI link.

Synchronous to mgmt_clk

.

Synchronization indication. RX synchronization is indicated on the rx_syncstatus

port of each channel. The rx_syncstatus

signal is 2 bits per channel for a total of 8 bits per hard XAUI link. The rx_syncstatus

signal is 1 bit per channel for a total of 4 bits per soft XAUI link. Synchronous to mgmt_clk

.

2.6.6.10. XAUI PHY Register Interface and Register Descriptions

The Avalon-MM PHY management interface provides access to the XAUI PHY IP core

PCS, PMA, and transceiver reconfiguration registers.

Table 177.

Signals in the Avalon-MM PHY Management Interface phy_mgmt_clk

Signal Name phy_mgmt_clk_reset phy_mgmt_addr[8:0] phy_mgmt_writedata[31:0] phy_mgmt_readdata[31:0] phy_mgmt_write phy_mgmt_read phy_mgmt_waitrequest

Direction

Input

Input

Input

Input

Output

Input

Input

Output

Description

Avalon-MM clock input.

Global reset signal that resets the entire XAUI PHY. This signal is active high and level sensitive.

9-bit Avalon-MM address.

32-bit input data.

32-bit output data.

Write signal. Asserted high.

Read signal. Asserted high.

When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request.

When asserted, control signals to the Avalon-MM slave interface must remain constant.

Note:

For more information about the Avalon-MM interface, including timing diagrams, refer to the Avalon Interface Specification.

The following table specifies the registers that you can access using the Avalon-MM

PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers.

Writing to reserved or undefined register addresses may have undefined side effects.

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Table 178.

XAUI PHY IP Core Registers

Word

Addr

Bits R/W Register Name

0x041

0x042

0x044

[31:0]

[1:0]

RW

W

R

RW

Description

Reset Control Registers–Automatic Reset Controller reset_ch_bitmask

Bit mask for reset registers at addresses 0x042 and

0x044. The default value is all 1s. You can reset channel < n

> when bit< n

> = 1.

reset_control

(write) Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the a 1 to bit 1 initiates a RX digital reset of channels enabled in the clears.

reset_ch_bitmask reset_ch_bitmask

. Writing

. This bit selfreset_status

Reserved

(read) Reading bit 0 returns the status of the reset controller

TX ready bit. Reading bit 1 returns the status of the reset controller RX ready bit. This bit self-clears.

Reset Controls –Manual Mode

It is safe to write 0s to reserved bits.

[31:4,0

]

[1] RW

0x061

0x064

0x065

0x066

0x067

0x084

[2]

[3]

[31:0]

[31:0]

[31:0]

[31:0]

[31:0]

[31:16]

[15:8]

RW

RW

RW

RW

RW

RO

RO

N/A

R reset_tx_digital reset_rx_analog pma_rx_set_locktoref pma_rx_is_lockedtodata pma_rx_is_lockedtoref

Writing a 1 causes the internal TX digital reset signal to be asserted, resetting all channels enabled in reset_ch_bitmask

. You must write a 0 to clear the reset condition.

Writing a 1 causes the internal RX analog reset signal to be asserted, resetting the RX analog logic of all channels enabled in reset_ch_bitmask write a 0 to clear the reset condition.

. You must reset_rx_digital

Writing a 1 causes the RX digital reset signal to be asserted, resetting the RX digital channels enabled in reset_ch_bitmask

. You must write a 0 to clear the reset condition.

PMA Control and Status Registers phy_serial_loopback pma_rx_set_locktodata

Writing a 1 to channel < n

> puts channel < n

> in serial loopback mode. For information about pre- or post-CDR serial loopback modes, refer to Loopback

Modes.

When set, programs the RX CDR PLL to lock to the incoming data. Bit < n

> corresponds to channel < n

>.

When set, programs the RX CDR PLL to lock to the reference clock. Bit < n


>.

When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit < n


>.

When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit < n


>.

XAUI PCS

Reserved

Reserved

N/A

N/A continued...


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Word

Addr

Bits R/W Register Name Description

0x085 [31:16]

[15:8]

0x08a

[7:0]

[7:0]

[0]

N/A

R

RW syncstatus[7:0]

Reserved errdetect[7:0] disperr[7:0] simulation_flag

Records the synchronization status of the corresponding bit. The RX sync status register has 1 bit per channel for a total of 4 bits per soft XAUI link; soft XAUI uses bits 0–3. Reading the value of the syncstatus

register clears the bits.

From block: Word aligner

N/A

When set, indicates that a received 10-bit code group has an 8B/10B code violation or disparity error. Use errdetect

with disperr

to differentiate between a code violation error, a disparity error, or both. There are 2 bits per RX channel for a total of 8 bits per XAUI link. Reading the value of the clears the bits.

errdetect

register

From block: 8B/10B decoder

Indicates that the received 10-bit code or data group has a disparity error. When set, the corresponding errdetect

bits are also set. There are 2 bits per RX channel for a total of 8 bits per XAUI link. Reading the value of the errdetect

register clears the bits.

From block: 8B/10B decoder

Setting this bit to 1 shortens the duration of reset and loss timer when simulating. Intel recommends that you keep this bit set for simulation.


Avalon Interface Specifications

2.6.6.11. XAUI PHY Timing Analyzer SDC Constraint

Refer to the "Timing Constraints for Bonded PCS and PMA Channels" section for the

Synopsis Design Constraints (SDC) for XAUI.


Timing Constraints for Bonded PCS and PMA Channels

on page 443

2.6.7. Acronyms

This table defines some commonly used Ethernet acronyms.

Table 179.

Ethernet Acronyms

AN

BER

DME

FEC

GMII

KR

Acronym Definition

Auto-Negotiation in Ethernet as described in Clause 73 of IEEE 802.3ap-2007.

Bit Error Rate.

Differential Manchester Encoding.

Forward error correction.

Gigabit Media Independent Interface.

Short hand notation for Backplane Ethernet with 64b/66b encoding.

continued...

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LD

LT

LP

MAC

MII

OSI

PCS

PHY

PMA

PMD

SGMII

WAN

XAUI

Acronym Definition

Local Device.

Link training in backplane Ethernet Clause 72 for 10GBASE-KR and 40GBASE-KR4.

Link partner, to which the LD is connected.

Media Access Control.

Media independent interface.

Open System Interconnection.

Physical Coding Sublayer.

Physical Layer in OSI 7-layer architecture, also in Intel device scope is: PCS + PMA.

Physical Medium Attachment.

Physical Medium Dependent.

Serial Gigabit Media Independent Interface.

Wide Area Network.

10 Gigabit Attachment Unit Interface.

2.7. PCI Express (PIPE)

You can use Arria 10 transceivers to implement a complete PCI Express solution for

Gen1, Gen2, and Gen3, at data rates of 2.5, 5.0, and 8 Gbps, respectively.

Configure the transceivers for PCIe functionality using one of the following methods:

• Arria 10 Hard IP for PCIe

This is a complete PCIe solution that includes the Transaction, Data Link, and

PHY/MAC layers. The Hard IP solution contains dedicated hard logic, which connects to the transceiver PHY interface.

Note: For more information, refer to the Arria 10 Avalon-ST Interface for PCIe

Solutions User Guide .

• Native PHY IP Core in PIPE Gen1/Gen2/Gen3 Transceiver Configuration

Rules

Use the Native PHY IP (Native PHY IP Core) to configure the transceivers in PCIe mode, giving access to the PIPE interface (commonly called PIPE mode in transceivers). This mode enables you to connect the transceiver to a third-party

MAC to create a complete PCIe solution.

The PIPE specification (version 3.0) provides implementation details for a PCIecompliant physical layer. The Native PHY IP Core for PIPE Gen1, Gen2, and Gen3 supports x1, x2, x4, or x8 operation for a total aggregate bandwidth ranging from

2 to 64 Gbps. In a x1 configuration, the PCS and PMA blocks of each channel are clocked and reset independently. The x2, x4, and x8 configurations support channel bonding for two-lane, four-lane, and eight-lane links. In these bonded channel configurations, the PCS and PMA blocks of all bonded channels share common clock and reset signals.

Gen1 and Gen2 modes use 8B/10B encoding, which has a 20% overhead to overall link bandwidth. Gen3 modes use 128b/130b encoding, which has an overhead of less than 2%. Gen1 and Gen2 modes use the Standard PCS, and Gen3 mode uses the

Gen3 PCS for its operation.


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Table 180.

Transceiver Solutions

Support

Gen1, Gen2, and Gen3 data rates

MAC, data link, and transaction layer

Transceiver interface

Arria 10 Hard IP for PCI Express

Yes

Yes

Hard IP through PIPE 3.0 based interface

Native PHY IP Core for PCI Express

(PIPE)

Yes

User implementation in FPGA fabric

• PIPE 2.0 for Gen1 and Gen2

• PIPE 3.0 based for Gen3 with Gen1/

Gen2 support


• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express

• Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface

2.7.1. Transceiver Channel Datapath for PIPE

Figure 90.

Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations

Transmitter PMA Transmitter Standard PCS FPGA

Fabric

PRBS

Generator

Receiver PMA Receiver Standard PCS

PRBS

Verifier

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Figure 91.

Transceiver Channel Datapath for PIPE Gen1/Gen2/Gen3 Configurations

Transmitter PMA Transmitter Gen3 PCS FPGA

Fabric

Transmitter Standard PCS

Receiver PMA Receiver Gen3 PCS

PRBS

Generator

Receiver Standard PCS

PRBS

Verifier

2.7.2. Supported PIPE Features

PIPE Gen1, Gen2, and Gen3 configurations support different features.

Table 181.

Supported Features for PIPE Configurations

Protocol Feature x1, x2, x4, x8 link configurations

PCIe-compliant synchronization state machine

±300 ppm (total 600 ppm) clock rate compensation

Transmitter driver electrical idle

Receiver detection

8B/10B encoding/decoding disparity control

128b/130b encoding/decoding

Gen1

(2.5 Gbps)

Yes

Yes

Yes

Yes

Yes

Yes

No

Gen2

(5 Gbps)

Yes

Yes

Yes

Yes

Yes

Yes

No

Scrambling/Descrambling

Power state management

Receiver PIPE status encoding pipe_rxstatus[2:0]

Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate

No

Yes

Yes

No

No

Yes

Yes

Yes

Gen3

(8 Gbps)

Yes

Yes

Yes

Yes

Yes

No

Yes (supported through the

Gearbox)

Yes

(implemented in FPGA fabric)

(38)

Yes

Yes

No continued...

(38) You must enable scrambling/descrambling in Gen1/Gen2 when using Arria 10 PCIe Gen3 configurations.


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Protocol Feature Gen1

(2.5 Gbps)

No

Gen2

(5 Gbps)

No

Gen3

(8 Gbps)

Yes Dynamic switching between 2.5 Gbps, 5 Gbps, and 8 Gbps signaling rate

Dynamic transmitter margining for differential output voltage control

Dynamic transmitter buffer de-emphasis of –3.5 dB and –6 dB

Dynamic Gen3 transceiver pre-emphasis, de-emphasis, and equalization

PCS PMA interface width (bits)

Receiver Electrical Idle Inference (EII)

No

No

No

Yes

Yes

No

Yes

Yes

Yes

10

Implement in FPGA fabric

10

Implement in

FPGA fabric

32

Implement in

FPGA fabric


•

PCIe Gen3 PCS Architecture on page 495

For more information about PIPE Gen3.

• Intel PHY Interface for the PCI Express* (PIPE) Architecture PCI Express 2.0

• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 3.0

2.7.2.1. Gen1/Gen2 Features

In a PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status signals between the PHY-MAC layer and the transceiver channel

PCS and PMA blocks. The PIPE configuration is based on the PIPE 2.0 specification. If you use a PIPE configuration, you must implement the PHY-MAC layer using soft IP in the FPGA fabric.

2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps)

In a PIPE configuration, Native PHY IP Core provides an input signal pipe_rate

[1:0]

that is functionally equivalent to the RATE signal specified in the PCIe specification. A change in value from 2'b00 to 2'b01 on this input signal pipe_rate

[1:0]

initiates a data rate switch from Gen1 to Gen2. A change in value from 2'b01 to 2'b00 on the input signal initiates a data rate switch from Gen2 to Gen1.

2.7.2.1.2. Transmitter Electrical Idle Generation

The PIPE interface block in Arria 10 devices puts the transmitter buffer in an electrical idle state when the electrical idle input signal is asserted. During electrical idle, the transmitter buffer differential and common mode output voltage levels are compliant with the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data rates.

The PCIe specification requires the transmitter driver to be in electrical idle in certain power states.

Note: For more information about input signal levels required in different power states, refer to Power State Management in the next section.

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2.7.2.1.3. Power State Management

Table 182.

Power States Defined in the PCIe Specification

To minimize power consumption, the physical layer device must support the following power states.

Power States

P0

Description

Normal operating state during which packet data is transferred on the PCIe link.

P0s, P1, and P2 The PHY-MAC layer directs the physical layer to transition into these low-power states.

The PIPE interface in Arria 10 transceivers provides a pipe_powerdown each transceiver channel configured in a PIPE configuration.

input port for

The PCIe specification requires the physical layer device to implement power-saving measures when the P0 power state transitions to the low power states. Arria 10 transceivers do not implement these power-saving measures except for putting the transmitter buffer in electrical idle mode in the lower power states.

2.7.2.1.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support

The PCIe transmitter transmits a compliance pattern when the Link Training and

Status State Machine (LTSSM) enters the Polling.Compliance substate. The

Polling.Compliance substate assesses if the transmitter is electrically compliant with the PCIe voltage and timing specifications.

2.7.2.1.5. Receiver Status

The PCIe specification requires the PHY to encode the receiver status on a 3-bit status signal pipe_rx_status[2:0]

. This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives status signals from the transceiver channel PCS and PMA blocks, and encodes the status on the pipe_rx_status[2:0] signal to the FPGA fabric. The encoding of the status signals on the pipe_rx_status[2:0]

signal conforms to the PCIe specification.

2.7.2.1.6. Receiver Detection

The PIPE interface block in Arria 10 transceivers provides an input signal pipe_tx_detectrx_loopback

for the receiver detect operation. The PCIe protocol requires this signal to be high during the Detect state of the LTSSM. When the pipe_tx_detectrx_loopback

signal is asserted in the P1 power state, the PIPE interface block sends a command signal to the transmitter driver in that channel to initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must always be in the electrical idle state. After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. The time constant of the step voltage on the trace increases if an active receiver that complies with the PCIe input impedance requirements is present at the far end. The receiver detect circuitry monitors this time constant to determine if a receiver is present.

Note: For the receiver detect circuitry to function reliably, the transceiver on-chip termination must be used. Also, the AC-coupling capacitor on the serial link and the receiver termination values used in your system must be compliant with the PCIe Base

Specification 2.0.


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The PIPE core provides a 1-bit PHY status signal pipe_phy_status

and a 3-bit receiver status signal pipe_rx_status[2:0]

to indicate whether a receiver is detected, as per the PIPE 2.0 specifications.

2.7.2.1.7. Gen1 and Gen2 Clock Compensation

In compliance with the PIPE specification, Arria 10 receiver channels have a rate match FIFO to compensate for small clock frequency differences up to ±300 ppm between the upstream transmitter and the local receiver clocks.

Consider the following guidelines for PIPE clock compensation:

• Insert or delete one SKP symbol in an SKP ordered set.

• Minimum limit is imposed on the number of SKP symbols in SKP ordered set after deletion. An ordered set may have an empty COM case after deletion.

• Maximum limit is imposed on the number of the SKP symbols in the SKP ordered set after insertion. An ordered set may have more than five symbols after insertion.

• For INSERT/DELETE cases: The flag status appears on the COM symbol of the SKP ordered set where insertion or deletion occurs.

• For FULL/EMPTY cases: The flag status appears where the character is inserted or deleted.

Note: When the PIPE interface is on, it translates the value of the flag to the appropriate pipe_rx_status

signal.

• The PIPE mode also has a “0 ppm” configuration option that you can use in synchronous systems. The Rate Match FIFO Block is not expected to do any clock compensation in this configuration, but latency is minimized.

Figure 92.

Rate Match Deletion

This figure shows an example of rate match deletion in the case where two /K28.0/ SKP symbols must be deleted. Only one /K28.0/ SKP symbol is deleted per SKP ordered set received.

SKP Symbol

Deleted

First SKP Ordered Set Second SKP Ordered Set

K28.0

Dx.y

rmfifo_input_data rx_parallel_data pipe_rx_status[2:0]

K28.5

K28.5

3’b010

K28.0

Dx.y

xxx

Dx.y

K28.5

3’b010

K28.5

K28.0

xxx

K28.0

K28.0

xxx

K28.0

Dx.y

xxx

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Figure 93.

Rate Match Insertion

The figure below shows an example of rate match insertion in the case where two SKP symbols must be inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received.

First SKP Ordered Set Second SKP Ordered Set rmfifo_input_data rx_parallel_data pipe_rx_status[2:0]

K28.5

K28.5

3’b001

K28.0

K28.0

xxx

Dx.y

K28.0

xxx

K28.5

Dx.y

xxx

K28.0

K28.5

3’b001

K28.0

K28.0

xxx

K28.0

K28.0

xxx

K28.0

K28.0

xxx

K28.0

xxx

K28.0

xxx

SKP Symbol Inserted

Figure 94.

Rate Match FIFO Full

The rate match FIFO in PIPE mode automatically deletes the data byte that causes the FIFO to go full and drives pipe_rx_status[2:0]

= 3'b101 synchronous to the subsequent data byte. The figure below shows the rate match FIFO full condition in PIPE mode. The rate match FIFO becomes full after receiving data byte

D4.

tx_parallel_data D1 D2 D3 D4 D5 D6 D7 D8 rx_parallel_data D1 D2 D3 D4 D6 D7 D8 xx xx xx pipe_rx_status[2:0] xxx xxx xxx xxx 3’b101 xxx xxx xxx

Figure 95.

Rate Match FIFO Empty

The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to become empty and drives pipe_rx_status[2:0]

= 3'b110 synchronous to the inserted /K30.7/ (9'h1FE). The figure below shows rate match FIFO empty condition in PIPE mode. The rate match FIFO becomes empty after reading out data byte D3.

tx_parallel_data D1 D2 D3 D4

D5

D6 rx_parallel_data D1 D2 D3 /K.30.7/ D4 D5 pipe_rx_status[2:0] xxx xxx xxx 3’b110 xxx xxx

PIPE 0 ppm

The PIPE mode also has a "0 ppm" configuration option that can be used in synchronous systems. The Rate Match FIFO Block is not expected to do any clock compensation in this configuration, but latency is minimized.

2.7.2.1.8. PCIe Reverse Parallel Loopback

PCIe reverse parallel loopback is only available in a PCIe functional configuration for

Gen1, Gen2, and Gen3 data rates. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. The data is then looped back to the transmitter serializer and transmitted out through the transmitter buffer. The received data is also available to the FPGA fabric through the rx_parallel_data

port. This loopback mode is based on PCIe specification 2.0.

Arria 10 devices provide an input signal this loopback mode.

pipe_tx_detectrx_loopback

to enable

Note: This is the only loopback option supported in PIPE configurations.


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Figure 96.

PCIe Reverse Parallel Loopback Mode Datapath

Transmitter PMA Transmitter Standard PCS FPGA

Fabric

Reverse Parallel

Loopback Path

PRBS

Generator

Receiver PMA Receiver Standard PCS

PRBS

Verifier


•

Arria 10 Standard PCS Architecture

on page 479

• Intel PHY Interface for the PCI Express* (PIPE) Architecture PCI Express 2.0

2.7.2.2. Gen3 Features

The following subsections describes the Arria 10 transceiver block support for PIPE

Gen3 features.

The PCS supports the PIPE 3.0 base specification. The 32-bit wide PIPE 3.0-based interface controls PHY functions such as transmission of electrical idle, receiver detection, and speed negotiation and control.

2.7.2.2.1. Auto-Speed Negotiation

PIPE Gen3 mode enables ASN between Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3

(8.0 Gbps) signaling data rates. The signaling rate switch is accomplished through frequency scaling and configuration of the PMA and PCS blocks using a fixed 32-bit wide PIPE 3.0-based interface.

The PMA switches clocks between Gen1, Gen2, and Gen3 data rates. For a non bonded x1 channel, an ASN module facilitates speed negotiation in that channel. For bonded x2, x4, x8 and x16 channels, the ASN module selects the master channel to control the rate switch. The master channel distributes the speed change request to the other

PMA and PCS channels.

The PCIe Gen3 speed negotiation process is initiated when Hard IP or the FPGA fabric requests a rate change. The ASN then places the PCS in reset, and dynamically shuts down the clock paths to disengage the current active state PCS (either Standard PCS or Gen3 PCS). If a switch to or from Gen3 is requested, the ASN automatically selects the correct PCS clock paths and datapath selection in the multiplexers. The ASN block then sends a request to the PMA block to switch the data rate, and waits for a rate change done signal for confirmation. When the PMA completes the rate change and sends confirmation to the ASN block, the ASN enables the clock paths to engage the new PCS block and releases the PCS reset. Assertion of the pipe_phy_status

signal by the ASN block indicates the successful completion of this process.

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Note: In Native PHY IP core - PIPE configuration, you must set pipe_rate[1:0] to initiate the transceiver datarate switch sequence.

2.7.2.2.2. Rate Switch

This section provides an overview of auto rate change between PIPE Gen1 (2.5 Gbps),

Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) modes.

In Arria 10 devices, there is one ASN block common to the Standard PCS and Gen3

PCS, located in the PMA PCS interface that handles all PIPE speed changes. The PIPE interface clock rate is adjusted to match the data throughput when a rate switch is requested.

Table 183.

PIPE Gen3 32 bit PCS Clock Rates

PCIe Gen3 Capability Mode

Enabled

Lane data rate

PCS clock frequency

FPGA fabric IP clock frequency

PIPE interface width pipe_rate [1:0]

2.5 Gbps

250 MHz

62.5 MHz

32-bit

2'b00

Gen1

5 Gbps

500 MHz

125 MHz

32-bit

2'b01

Gen2

8 Gbps

250 MHz

250 MHz

32-bit

2'b10

Gen3

Figure 97.

Rate Switch Change

The block-level diagram below shows a high level connectivity between ASN and Standard PCS and Gen3 PCS.

Control Plane

Bonding Up pipe_rate[1:0] from FPGA Fabric

Standard PCS PCS/PMA INF

Gen3 ASN

(Gen1, Gen2, Gen3)

Gen3 PCS pipe_sw pipe_sw_done

PMA

PHYSTATUS

GEN

PHYSTATUS

GEN pipe_phy_status pll_pcie_clk

TX

FIFO

/2

(for Gen1 Only)

Control Plane

Bonding Down


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The sequence of speed change between Gen1, Gen2, and Gen3 occurs as follows:

1. The PHY-MAC layer implemented in FPGA fabric requests a rate change through pipe_rate[1:0]

.

2. The ASN block waits for the TX FIFO to flush out data. Then the ASN block asserts the PCS reset.

3. The ASN asserts the clock shutdown signal to the Standard PCS and Gen3 PCS to dynamically shut down the clock.

4. When the rate changes to or from the Gen3 speed, the ASN asserts the clock and data multiplexer selection signals.

5. The ASN uses a pipe_sw[1:0]

output signal to send a rate change request to the PMA.

6. The ASN continuously monitors the

PMA.

pipe_sw_done[1:0]

input signal from the

7. After the ASN receives the pipe_sw_done[1:0]

signal, it deasserts the clock shut down signals to release the clock.

8. The ASN deasserts the PCS reset.

9. The ASN sends the speed change completion to the PHY-MAC interface. This is done through the pipe_phy_status

signal to PHY-MAC interface.

Figure 98.

Speed Change Sequence pipe_tx_elecidle pipe_rate[1:0] pipe_sw[1:0] pipe_sw_done[1:0] pipe_phy_status

00

00

00

10

10

10

2.7.2.2.3. Gen3 Transmitter Electrical Idle Generation

In the PIPE 3.0-based interface, you can place the transmitter in electrical idle during low power states. Before the transmitter enters electrical idle, you must send the

Electrical Idle ordered set, consisting of 16 symbols with value 0x66. During electrical idle, the transmitter differential and common mode voltage levels are based on the

PCIe Base Specification 3.0.

2.7.2.2.4. Gen3 Clock Compensation

Enable this mode from the Parameter Editor when using the Gen3 PIPE transceiver configuration rule.

To accommodate PCIe protocol requirements and to compensate for clock frequency differences of up to ±300 ppm between source and termination equipment, receiver channels have a rate match FIFO. The rate match FIFO adds or deletes four SKP characters (32 bits) to keep the FIFO from becoming empty or full. If the rate match

FIFO is almost full, the FIFO deletes four SKP characters. If the rate match FIFO is nearly empty, the FIFO inserts a SKP character at the start of the next available SKP ordered set. The and deletion.

pipe_rx_status [2:0]

signal indicates FIFO full, empty, insertion

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Note: Refer to the Gen1 and Gen2 Clock Compensation section for waveforms.


Gen1 and Gen2 Clock Compensation on page 234

2.7.2.2.5. Gen3 Power State Management

The PCIe base specification defines low power states for PHY layer devices to minimize power consumption. The Gen3 PCS does not implement these power saving measures, except when placing the transmitter driver in electrical idle in the low power state. In the P2 low power state, the transceivers do not disable the PIPE block clock.

Figure 99.

P1 to P0 Transition

The figure below shows the transition from P1 to P0 with completion provided by pipe_phy_status

.

tx_coreclkin pipe_powerdown pipe_phy_status

P1 P0

2.7.2.2.6. CDR Control

The CDR control block performs the following functions:

• Controls the PMA CDR to obtain bit and symbol alignment

• Controls the PMA CDR to deskew within the allocated time

• Generates status signals for other PCS blocks

The PCIe base specification requires that the receiver L0s power state exit time be a maximum of 4 ms for Gen1, 2 ms for Gen2, and 4 ms for Gen3 signaling rates. The transceivers have an improved CDR control block to accommodate fast lock times.

Fast lock times are necessary for the CDR to relock to the new multiplier/divider settings when entering or exiting Gen3 speeds.

2.7.2.2.7. Gearbox

As per the PIPE 3.0 specification, for every 128 bits that are moved across the Gen3

PCS, the PHY must transmit 130 bits of data. Intel uses the pipe_tx_data_valid signal every 16 blocks of data to transmit the built-up backlog of 32 bits of data.

The 130-bit block is received as follows in the 32-bit data path: 34 (32+2-bit sync header), 32, 32, 32. During the first cycle, the gearbox converts the 34-bit input data to 32-bit data. During the next three clock cycles, the gearbox merges bits from adjacent cycles. For the gearbox to work correctly, a gap must be provided in the data for every 16 shifts because each shift contains two extra bits for converting the initial

34 bits to 32 bits in the gearbox. After 16 shifts, the gearbox has an extra 32 bits of data that are transmitted out. This requires a gap in the input data stream, which is achieved by driving pipe_tx_data_valid

low for one cycle after every 16 blocks of data.

Figure 100. Gen3 Data Transmission tx_coreclkin pipe_tx_sync_hdr pipe_tx_blk_start pipe_tx_data_valid

10


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2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes

Figure 101. Use ATX PLL or fPLL for Gen1/Gen2 x1 Mode

X1 Network

6

CGB

Ch 5 fPLL1

ATX PLL1

6

CGB

CDR

Ch 4

Master

CGB1

4

6

CGB

CDR

Ch 3

Path for Clocking in

Gen1/Gen2 x1 Mode fPLL0

6

CGB

CDR

Ch 2

Master

CGB0

4

6

CGB

CDR

Ch 1

ATX PLL0

6

CGB

CDR

Ch 0

Path for Clocking in

Gen1/Gen2 x1 Mode

CDR

Notes:

1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x1 mode.

2. Gen1/Gen2 x1 mode uses the ATX PLL or fPLL.

3. Gen1/Gen2 x1 can use any channel from the given bank for which the ATX PLL or fPLL is enabled.

4. Use the pll_pcie_clk from either the ATX PLL or fPLL. This is the hclk required by the PIPE interface.

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XN

Network

X6

Network fPLL1

ATX PLL1

Connections Done via X1 Network

Master

CGB

Master

CGB

6 6

6

6

6

6

CGB

CGB

CGB

CGB

CGB

CGB

CDR

Ch 3

CDR

Ch 2

Ch 5

CDR

Ch 4

CDR

Ch 1

CDR

Ch 0

CDR

Notes:

1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x4 mode.

2. The x6 and xN clock networks are used for channel bonding applications.

3. Each master CGB drives one set of x6 clock lines.

4. Gen1/Gen2 x4 modes use the ATX PLL or fPLL only.

5. Use the pll_pcie_clk from either the ATX or fPLL. This is the hclk required by the PIPE interface.

6.

In this case the Master PCS channel is logical channel 3 (physical channel 4).


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Use Any

One PLL fPLL1

ATX PLL1

Master

CGB


Master

CGB

6 6

6

6

6

6

CGB

CGB

Master

CGB

6

Notes:

1. Figure shown is just one possible combination for the PCIe Gen1/Gen2 x8 mode.


3. Each master CGB drives one set of x6 clock lines. The x6 lines further drive the xN lines.

4. Gen1/Gen2 x8 mode uses the ATX PLL or fPLL only.

5. Use the pll_pcie_clk from either the ATX or fPLL. This is the hclk required by the PIPE interface.

6. In this case the Master PCS channel is logical channel 4 (Ch 1 in the top bank).

CGB

CGB

CGB

CGB

CGB

CGB

Ch 5

CDR

Ch 4

CDR

Ch 3

CDR

Ch 2

Transceiver bank

CDR

Ch 1

CDR

Ch 0

CDR

Ch 5

CDR

Ch 4

CDR

Transceiver bank

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Figure 104. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x1 Mode

X1 Network

6

CGB fPLL1

ATX PLL1

6

CGB

Ch 5

CDR

Ch 4

Master

CGB1

4

CDR

Ch 3

6

CGB

CDR

Ch 2

6

CGB fPLL0

Master

CGB0

4

CDR

Ch 1

6

CGB

ATX PLL0

CDR

Ch 0

6

CGB

CDR

Notes:

1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x1 mode.

2. Gen1/Gen2 modes use the fPLL only.

3. Gen3 mode uses the ATX PLL only.

4. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.

5. Select the number of TX PLLs (2) in the Native PHY IP core wizard.


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XN

Network

X6

Network fPLL1

ATX PLL1


Master

CGB

Master

CGB

6 6

6

6

6

6

CGB

CGB

CGB

CGB

CGB

CGB

Notes:



3. Each master CGB drives one set of x6 clock lines.

4. Gen1/Gen2 modes use the fPLL only.



CDR

Ch 1

CDR

Ch 0

CDR

CDR

Ch 3

CDR

Ch 2

Ch 5

CDR

Ch 4

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Master

CGB fPLL1

ATX PLL1


Master

CGB

6 6

6

6

6

6

CGB

CGB

CGB

CGB

CGB

CGB

Ch 5

CDR

Ch 4

CDR

Ch 3

CDR

Ch 2

Transceiver bank

CDR

Ch 1

CDR

Ch 0

CDR

Ch 5

CGB

CDR

Ch 4

CGB

Master

CGB

6

Notes:



3. Each master CGB drives one set of x6 clock lines. The x6 lines further drive the xN lines.

4. Gen1/Gen2 x8 modes use the fPLL only.



CDR

Transceiver bank


•

Using PLLs and Clock Networks

on page 398

For more information about implementing clock configurations and configuring

PLLs.

• PIPE Design Example

For more information about the PLL configuration for PCIe.

•

Transmit PLL recommendation based on Data rates

on page 349

For more information about ATX PLL placement restrictions


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2.7.4. How to Implement PCI Express (PIPE) in Arria 10 Transceivers

You must be familiar with the Standard PCS architecture, Gen3 PCS architecture, PLL architecture, and the reset controller before implementing the PCI Express protocol.

1. Go to the IP Catalog and select the Arria 10 Transceiver Native PHY IP Core.

Refer to Select and Instantiate the PHY IP Core on page 33 for more details.

2. Select Gen1/Gen2/Gen3 PIPE from the Arria 10 Transceiver configuration

rules list, located under Datapath Options.

3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for

PCI Express Transceiver Configurations Rules as a starting point. Alternatively, you

can use Arria 10 Transceiver Native PHY Presets . You can then modify the settings to meet your specific requirements.

4. Click Finish to generate the Native PHY IP (this is your RTL file).

5. Instantiate and configure your PLL.

6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.

7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the

information in Transceiver Native PHY IP Ports for PCI Express Transceiver

Configuration Rules to connect the ports.

8. Simulate your design to verify its functionality.

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Figure 107. Connection Guidelines for a PIPE Gen3 Design

pll_refclk

ATX PLL and Master

CGB (Gen3) tx_bonding_clocks mcgb_aux_clk fPLL

(Gen1/Gen2) pll_pcie_clk tx_serial_clk

Arria 10

Transceiver

Native PHY tx_bonding_clocks pipe_hclk_in

(1)

Reset Controller (2) clock reset

Notes:

(1). If you enable the input pll_cal_busy port in the Transceiver PHY Reset Controller, you can connect the pll_cal_busy output signals from the PLLs directly to the input port on the reset-controller without ORing the tx_cal_busy and pll_cal_busy signals.

(2).

a. If you are using the Transceiver PHY Reset Controller, you must configure the TX digital reset mode and RX digital reset mode to Manual to avoid resetting the Auto Speed

Negotiation (ASN) block which handles the rate switch whenever the channel PCS is reset.

b. When the TX digitalreset is in Auto mode, the associated tx_digitalreset controller automatically resets whenever the pll_locked signal is deasserted. When in Manual mode, the associated tx_digitalreset controller is not reset when the pll_locked signal is deasserted, allowing the user to choose what to do.

c. When the RX digitalreset is in Auto mode, the associated rx_digitalreset controller automatically resets whenever the rx_is_lockedtodata signal is deasserted. When in

Manual mode, the associated rx_digitalreset controller is not reset when the rx_is_lockedtodata signal is deasserted, allowing the user to choose what to do.

d. If the resets are configured to Auto mode for PIPE designs, then the digital reset will get asserted automatically when the lock signal is deasserted.


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Recommendations:

Intel recommends that you not reset the PLL and channels (TX and RX) when using the PIPE mode of Native PHY. This is to avoid resetting the Auto Speed Negotiation

(ASN) block in the PCS.


•

PLLs on page 349

For information about PLL architecture and implementation details.

•


on page 479

•

Resetting Transceiver Channels

on page 416

For information about the Reset controller and implementation details.

2.7.5. Native PHY IP Parameter Settings for PIPE

Table 184.

Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes

This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10

Transceiver Native PHY IP Core for the full range of parameter values.

Gen1 PIPE Gen2 PIPE Gen3 PIPE

Parameter

Message level for rule violations

Common PMA Options

VCCR_GXB and VCCT_GXB supply voltage for the

Transceiver

Transceiver link type

Datapath Options

Transceiver configuration rules

PMA configuration rules

Transceiver mode

Number of data channels

Data rate

Enable datapath and interface reconfiguration

Enable simplified data interface

Provide separate interface for each channel

Error

Gen1: 1_1V, 1_0V, 0_9V

Gen1: sr,lr

Gen1 PIPE

Basic

TX / RX Duplex

Gen1 x1: 1 channel

Gen1 x2: 2 channels

Gen1 x4: 4 channels

Gen1 x8: 8 channels

2.5 Gbps

Optional

Optional (

40 )

Optional

Error

Gen2: 1_1V, 1_0V, 0_9V

Gen2: sr,lr

Gen2 PIPE

Basic

TX / RX Duplex

Gen2 x1: 1 channel

Gen2 x2: 2 channels

Gen2 x4: 4 channels

Gen2 x8: 8 channels

5 Gbps

Optional

Optional

( 40

)

Optional

Error

Gen3: 1_1V, 1_0V, 0_9V

Gen3: sr,lr

Gen3 PIPE

Basic

TX / RX Duplex

Gen3 x1: 1 channel

Gen3 x2: 2 channels

Gen3 x4: 4 channels

Gen3 x8: 8 channels

5 Gbps (39)

Optional

Optional

( 40

)

Optional

(39) The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for 8 Gbps.

(40) Refer to

Table 191 on page 263 for bit settings when simplified data interface is enabled.

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Table 185.

Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX

PMA




TX Bonding Options

TX channel bonding mode

PCS TX channel bonding master

Default PCS TX channel bonding master

Nonbonded (x1)

PMA & PCS Bonding

Auto (

41 )

Gen1 x1: 0

Gen1 x2: 1

Gen1 x4: 2

Gen1 x8: 4

Nonbonded (x1)

PMA & PCS Bonding

Auto

( 41

)

Gen1 x1: 0

Gen1 x2: 1

Gen1 x4: 2

Gen1 x8: 4

Nonbonded (x1)

PMA & PCS Bonding

Auto (

41 )

Gen1 x1: 0

Gen1 x2: 1

Gen1 x4: 2

Gen1 x8: 4

TX PLL Options

TX local clock division factor 1 1

Number of TX PLL clock inputs per channel

Initial TX PLL clock input selection

1

0

1

0

1

Gen3 x1: 2

All other modes: 1

Gen1 / Gen2 clock connection should be used for Initial clock input selection in

Gen3x1

All other modes: 0

TX PMA Optional Ports

Enable tx_analog_reset_ack port

Enable tx_pma_clkout

port

Enable tx_pma_div_clkout port tx_pma_div_clkout division factor

Enable tx_pma_elecidle port

Enable tx_pma_qpipullup port (QPI)

Enable tx_pma_qpipulldn port (QPI)

Enable tx_pma_txdetectrx port (QPI)

Enable tx_pma_rxfound

port (QPI)

Enable rx_seriallpbken

port

Optional

Optional

Optional

Optional

Off

Off

Off

Off

Off

Off

Optional

Optional

Optional

Optional

Off

Off

Off

Off

Off

Off

Optional

Optional

Optional

Optional

Off

Off

Off

Off

Off

Off

(41) Setting this parameter is placement-dependent. In AUTO mode, the Native PHY IP Parameter

Editor selects the middle-most channel of the configuration as the default PCS TX channel bonding master. You must ensure that this selected channel is physically placed as Ch1 or Ch4 of the transceiver bank. Else, use the manual selection for the PCS TX channel bonding master to select a channel that can be physically placed as Ch1 or Ch4 of the transceiver bank. Refer to section How to place channels for PIPE configurations for more details.


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Table 186.

Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX

PMA




RX CDR Options

Number of CDR reference clocks

Selected CDR reference clock

Selected CDR reference clock frequency

PPM detector threshold

Equalization

CTLE adaptation mode

1

0

100, 125 MHz

1000

1

0

100, 125 MHz

1000

1

0

100, 125 MHz

1000

Manual / Triggered Manual / Triggered Manual / Triggered

DFE adaptation mode

Number of fixed dfe taps

RX PMA Optional Ports

Enable rx_analog_reset_ack

port

Enable rx_pma_clkout

port

Enable rx_pma_div_clkout port rx_pma_div_clkout division factor

Enable rx_pma_clkslip

port

Enable rx_pma_qpipulldn port (QPI)

Enable rx_is_lockedtodata port

Enable rx_is_lockedtoref port

Enable rx_set_locktodata

and rx_set_locktoref

ports

Enable rx_seriallpbken

port

Enable PRBS Verifier Control and Status ports

Disabled

NA

Optional

Optional

Optional

Optional

Optional

Off

Optional

Optional

Optional

Optional

Optional

Disabled

NA

Optional

Optional

Optional

Optional

Optional

Off

Optional

Optional

Optional

Optional

Optional

Disabled

NA

Table 187.

Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes -

Standard PCS



Gen1 PIPE Gen2 PIPE Gen3 PIPE Parameter

Standard PCS configurations

Standard PCS / PMA interface width 10 10 10 (42) continued...

Optional

Optional

Optional

Optional

Optional

Off

Optional

Optional

Optional

Optional

Optional

(42) The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for PCS/PMA width of 32.

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Parameter

FPGA Fabric / Standard TX PCS interface width

FPGA Fabric / Standard RX PCS interface width

Enable Standard PCS low latency mode

Standard PCS FIFO

TX FIFO mode

RX FIFO mode

Enable tx_std_pcfifo_full

port

Enable tx_std_pcfifo_empty

port

Enable rx_std_pcfifo_full

port

Enable rx_std_pcfifo_empty

port

Byte Serializer and Deserializer

TX byte serializer mode

RX byte deserializer mode

8B/10B Encoder and Decoder

Enable TX 8B/10B encoder

Enable TX 8B/10B disparity control

Enable RX 8B/10B decoder

Rate Match FIFO

Rate Match FIFO mode

RX rate match insert / delete -ve pattern

(hex)

RX rate match insert / delete +ve pattern (hex)

Enable rx_std_rmfifo_full

port

Enable rx_std_rmfifo_empty

port

PCI Express Gen 3 rate match FIFO mode

Word Aligner and Bit Slip

Enable TX bit slip

Enable port tx_std_bitslipboundarysel

RX word aligner mode

RX word aligner pattern length

RX word aligner pattern (hex)

Gen1 PIPE

8, 16

8, 16

Off low_latency low_latency

Optional

Optional

Optional

Optional

Disabled, Serialize x2

Disabled, Serialize x2

Enabled

Enabled

Enabled

PIPE, PIPE 0ppm

0x0002f17c (K28.5/

K28.0/)

0x000d0e83 (K28.5/

K28.0/)

Optional

Optional

Bypass

Off

Optional

Synchronous State

Machine

10

0x0000 00000000017c (/

K28.5/)

Gen2 PIPE

16

16


Optional

Optional

Optional

Optional

Serialize x2

Serialize x2

Enabled

Enabled

Enabled

PIPE, PIPE 0ppm

0x0002f17c (K28.5/

K28.0/)

0x000d0e83 (K28.5/

K28.0/)

Optional

Optional

Bypass

Off

Optional

Synchronous State

Machine

10

0x0000 00000000017c (/

K28.5/)

Gen3 PIPE

32

32


Optional

Optional

Optional

Optional

Serialize x4

Deserialize x4

Enabled

Enabled

Enabled

PIPE, PIPE 0ppm

0x0002f17c (K28.5/

K28.0/)

0x000d0e83

(K28.5/K28.0/)

Optional

Optional

600

Off

Optional

Synchronous State

Machine

10

0x0000

00000000017c(/

K28.5/) continued...


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Parameter

Number of word alignment patterns to achieve sync

Number of invalid data words to lose sync

Number of valid data words to decrement error count

Enable rx_std_wa_patternalign

port

Enable rx_std_wa_a1a2size

port

Enable port rx_std_bitslipboundarysel

Enable rx_bitslip

port

Bit Reversal and Polarity Inversion

Enable TX bit reversal

Enable TX byte reversal

Enable TX polarity inversion

Enable tx_polinv

port

Enable RX bit reversal

Enable rx_std_bitrev_ena

port

Enable RX byte reversal

Enable rx_std_byterev_ena

port

Enable RX polarity inversion

Enable rx_polinv

port

Enable rx_std_signaldetect

port

PCIe Ports

Enable PCIe dynamic datarate switch ports

Enable PCIe pipe_hclk_in

and pipe_hclk_out

ports

Enable PCIe Gen3 analog control ports

Enable PCIe electrical idle control and status ports

Enable PCIe pipe_rx_polarity

port

Dynamic reconfiguration

Enable dynamic reconfiguration

Note:

Gen1 PIPE

3

16

15

Optional

Off

Optional

Off

Off

Off

Off

Off

Off

Off

Off

Off

Off

Off

Optional

Off

Enabled

Off

Enabled

Enabled

Disabled

Gen2 PIPE

3

16

15

Optional

Off

Optional

Off

Off

Off

Off

Off

Off

Off

Off

Off

Off

Off

Optional

Enabled

Enabled

Off

Enabled

Enabled

Disabled

Gen3 PIPE

3

16

15

Optional

Off

Optional

Off

Off

Off

Off

Off

Off

Off

Off

Off

Off

Off

Optional

Enabled

Enabled

Enabled

Enabled

Enabled

Disabled

The signals in the left-most column are automatically mapped to a subset of a 128-bit tx_parallel_data

word when the Simplified Interface is enabled.


•

How to Place Channels for PIPE Configurations

on page 268

•


on page 45

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•

Bit Mappings When the Simplified Interface Is Disabled on page 263

2.7.6. fPLL IP Parameter Core Settings for PIPE

Table 188.

Parameter Settings for Arria 10 fPLL IP core in PIPE Gen1, Gen2, Gen3 modes



Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen1/

Gen2 speeds)

PLL

General fPLL mode

Protocol Mode

Message level for rule violation

Number of PLL reference clocks

Selected reference clock source

Enable fractional mode

Enable manual counter configuration

Enable ATX to fPLL cascade clock input port

Settings

Bandwidth

Feedback

Operation mode

Output frequency

Transceiver

PCIe Gen 1

Error

1

0

Disable

Disable

Disable

Low, Medium, High

Direct

Transceiver usage

PLL output frequency

PLL datarate

PLL integer reference clock frequency

250oMHz

2500Mbps

100 MHz, 125 MHZ

Master Clock Generation Block (MCGB)

Include master clock generation block

Clock division factor

Disable for x1

Enable for x2, x4, x8

N/A for x1

1 for x2, x4, x8

Enable x6/xN non-bonded high-speed clock output port

Enable PCIe clock switch interface

N/A for x1

Disable for x2, x4, x8

N/A for x1


Transceiver

PCIe Gen 2

Error

1

0

Disable

Disable

Disable

Low, Medium, High

Direct

2500MHz

5000Mbps

100 MHz, 125 MHZ

Disable for x1


N/A for x1

1 for x2, x4, x8

N/A for x1


N/A for x1


Transceiver

PCIe Gen 2

Error

1

0

Disable

Disable

Disable

Low, Medium, High

Direct

2500MHz

5000Mbps

100 MHz, 125 MHZ

Disable for x1


N/A for x1

N/A for x2, x4, x8

N/A for x1

N/A for x2,x4, x8

N/A for x1

N/A for x2, x4, x8 continued...


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Parameter Gen1 PIPE Gen2 PIPE

Number of auxiliary MCGB clock input ports

MCGB input clock frequency

MCGB output data rate

Bonding

Enable bonding clock output ports

Enable feedback compensation bonding

PMA interface width

N/A for x1

0 for x2, x4, x8

1250MHz

2500Mbps

N/A for x1 design


N/A for x1 design


N/A for x1 design

10 for x2, x4, x8

Dynamic Reconfiguration


Enable Altera Debug Master

Endpoint

Separate avmm_busy from reconfig_waitrequest

Disable

Disable

N/A

Optional Reconfiguration Logic

Enable capability registers N/A

Set user-defined IP identifier N/A

Enable control and status registers

N/A

Configuration Files

Configuration file prefix

Generate SystemVerilog package file

Generate C Header file

Generate MIF (Memory

Initialize file)

Generation Options

Generate parameter documentation file

N/A

N/A

N/A

N/A

Enable

N/A for x1

0 for x2, x4, x8

2500MHz

5000Mbps

N/A for x1 design


N/A for x1 design


N/A for x1 design

10 for x2, x4, x8

Disable

Disable

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Enable



on page 45

Gen3 PIPE (For Gen1/

Gen2 speeds)

N/A for x1

N/A for x2, x4, x8

2500MHz

5000Mbps

N/A for x1

N/A for x2, x4, x8

N/A for x1

N/A for x2, x4, x8

N/A for x1

N/A for x2, x4, x8

Disable

Disable

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Enable

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2.7.7. ATX PLL IP Parameter Core Settings for PIPE

Table 189.

Parameters for Arria 10 ATX PLL IP core in PIPE Gen1, Gen2, Gen3 modes



Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen3 speed)

PLL

General

Message level for rule violations

Protocol Mode

Bandwidth

Number of PLL reference clocks

Selected reference clock source

Ports

Primary PLL clock output buffer

Enable PLL GX clock output port

Enable PLL GT clock output port

Enable PCIe clock output port pll_pcie_clk

Error

PCIe Gen 1

Low, medium, high

1

0

Error

PCIe Gen 2

Low, medium, high

1

0

Error

PCIe Gen 3

Low, medium, high

1

0

GX clock output buffer GX clock output buffer GX clock output buffer

Enable Enable Enable

Disable

Enable

Disable

Disable

Enable

Disable

Disable

Disable (Use the pll_pcie_clk

output port from the fPLL to drive the hclk)

Disable Enable ATX to fPLL cascade clock output port

Output Frequency


PLL output datarate

Enable fractional mode

PLL integer reference clock frequency

Configure counters manually

Multiple factor (M counter)

Divide factor (N counter)

Divide factor (L counter)

Master Clock Generation Block

MCGB

Include master clock generation block

Clock division factor

Enable x6/xN non-bnded high speed clock output port

Enable PCIe clock switch interface

2500MHz

2500Mbps

Disable

100MHz, 125MHZ

Disable

N/A

N/A

N/A

Disable for x1


N/A for x1

1 for x2, x4, x8

N/A for x1


N/A for x1


2500MHz

5000Mbps

Disable

100MHz, 125MHZ

Disable

N/A

N/A

N/A

Disable for x1


N/A for x1

1 for x2, x4, x8

N/A for x1


N/A for x1


4000MHz

8000Mbps

Disable

100MHz, 125MHZ

Disable

N/A

N/A

N/A

Disable for x1


N/A for x1

1 for x2, x4, x8

N/A for x1


N/A for x1

Enable for x2, x4, x8 continued...


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Parameter

Number of auxiliary MCGB clock input ports

MCGB input clock frequency

MCGB output data rate

Bonding

Enable bonding clock output ports

Gen1 PIPE

N/A for x1

0 for x2, x4, x8

1250 MHz

2500 Mbps

Gen2 PIPE

N/A for x1

0 for x2, x4, x8

2500 MHz

5000 Mbps

Gen3 PIPE (For Gen3 speed)

N/A for x1

1 for x2, x4, x8

4000 MHz

8000 Mbps

Enable feedback compensation bonding

PMA interface width

N/A for x1


N/A for x1 design


N/A for x1 design

10 for x2, x4, x8

N/A for x1


N/A for x1 design


N/A for x1 design

10 for x2, x4, x8

N/A for x1


Disable for x1


N/A for x1

10 for x2, x4, x8



Enable Altera Debug Master Endpoint

Separate avmm_busy from reconfig_waitrequest

Optional Reconfiguration Logic

Enable capability registers

Set user-defined IP identifier

Enable control and status registers

Configuration Files

Configuration file prefix

Generate SystemVerilog package file

Generate C Header file

Generate MIF (Memory Initialize file)


Generate parameter documentation file

Disable

Disable

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Disable

Disable

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Enable Enable



on page 45

Disable

Disable

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Enable

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2.7.8. Native PHY IP Ports for PIPE

Figure 108. Signals and Ports of Native PHY IP for PIPE reconfig_reset reconfig_clk reconfig_avmm tx_digitalreset tx_datak [3:0], [1:0], or [0] tx_parallel_data [31:0], [15:0], or [7:0] tx_coreclkin tx_clkout pipe_rx_elecidle [(N-1):0] pipe_phy_status [(N-1):0] pipe_rx_data_valid [(N-1):0] pipe_rx_sync_hdr [(2N-1):0] pipe_rx_blk_start [(N-1):0] pipe_rate [1:0] pipe_g3_tx_deemph [(18N-1):0] pipe_g3_rxpresethint [(3N-1):0] pipe_sw_done [1:0] pipe_rx_polarity [(N-1):0] pipe_tx_elecidle [(4N-1):0] pipe_tx_detectrx_loopback [(N-1):0] pipe_powerdown [(2N-1):0] pipe_rx_eidleinfersel [(3N-1):0] pipe_tx_sync_hdr [(2N-1):0] pipe_tx_data_valid [(N-1):0] pipe_tx_blk_start [(N-1):0] pipe_tx_deemph [(N-1):0] tx_bonding_clocks[(6n-1):0] tx_analogreset rx_analogreset rx_digitalreset rx_datak [3:0], [1:0], or [0] rx_parallel_data [31:0], [15:0], or [7:0] rx_clkout rx_coreclkin rx_syncstatus

Reconfiguration

Registers

Arria 10 Transceiver Native PHY

Nios II Hard

Calibration IP

TX PMA TX Standard PCS tx_datak [3:0], [1:0], or [0] tx_parallel_data[31:0],[15:0],or[7:0] tx_coreclkin tx_clkout unused_tx_parallel_data[118:0]

10

Serializer

PIPE Interface

RX Standard PCS rx_datak [3:0], [1:0], or [0] rx_parallel_data[31:0],[15:0],or[7:0] rx_clkout rx_coreclkin rx_syncstatus unused_rx_parallel_data[118:0]

Local CGB

(for X1 Modes Only

-

RX PMA

Deserializer CDR

Gen1/Gen2/Gen3 - Black

Gen2/Gen3 - Red

Note: N is the number of PCIe channels tx_cal_busy rx_cal_busy tx_serial_data pipe_hclk_out [0] pipe_hclk_in [0] (from TX PLL) pipe_tx_compliance [(4N-1):0] pipe_tx_margin [(3N-1):0] pipe_tx_swing [(N-1):0] pipe_rx_valid [(N-1):0] pipe_rx_status [(3N-1):0] pipe_sw [1:0] tx_serial_data rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref


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Table 190.

Ports for Arria 10 Transceiver Native PHY in PIPE Mode

This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver

Native PHY IP Core for the full range of parameter settings.

Port rx_cdr_refclk0 tx_serial_clk0/ tx_serial_clk1 pipe_hclk_in[0] pipe_hclk_out[0] tx_parallel_data[31:0]

,

[15:0]

, or

[7:0] tx_datak[3:0]

,

[1:0]

, or

[0] pipe_tx_sync_hdr[(2N-1)

:0]

(43)

Direction

In

In

In

Out

Clock Domain

Clocks

Description

N/A

N/A

N/A

The 100/125 MHz input reference clock source for the PHY's TX PLL and RX CDR.

The high speed serial clock generated by the

PLL.

Note: For Gen3 x1 ONLY is used.

tx_serial_clk1

The 500 MHz clock used for the ASN block.

This clock is generated by the PLL, configured for Gen1/Gen2.

Note: For Gen3 designs, use from the fPLL that is used for Gen1/Gen2.

N/A

The 500 MHz clock output provided to the

PHY - MAC interface. The pipe_hclk_out

[0]

port can be left floating when you connect tx_clkout

to the MAC clock input.

PIPE Input from PHY - MAC Layer

In

In

In tx_coreclkin tx_coreclkin tx_coreclkin

The TX parallel data driven from the MAC.

For Gen1 this can be 8 or 16 bits. For Gen2 this is 16 bits. For Gen3 this is 32 bits.

Note: unused_tx_parallel_data be tied to '0'.

should

Active High. Refer to table Bit Mappings when

the Simplified Interface is Disabled for additional details.

The data and control indicator for the transmitted data.

For Gen1 or Gen2, when 0, indicates that tx_parallel_data

is data, when 1, indicates that control.

tx_parallel_data

is

For Gen3, bit[0]

corresponds to tx_parallel_data[7:0]

, bit[1] corresponds to and so on.

tx_parallel_data[15:8]

,

Active High. Refer to table Bit Mappings when

the Simplified Interface is Disabled for additional details.

For Gen3, indicates whether the 130-bit block transmitted is a Data or Control

Ordered Set Block.

The following encodings are defined:

2'b10: Data block

2'b01: Control Ordered Set Block

This value is read when pipe_tx_blk_start = 1b'1

.

continued...

(43) N is the number of PCIe channels.

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Port Direction Clock Domain pipe_tx_blk_start[(N-1)

:0] pipe_tx_elecidle[(4N-1)

:0] pipe_tx_detectrx_loopba ck [(N-1):0] pipe_tx_compliance[(4N-

1):0]

In

In

In

In tx_coreclkin

Asynchronous tx_coreclkin tx_coreclkin

Description

Refer to Lane Level Encoding in the PCI

Express Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding.

Not used for Gen1 and Gen2 data rates.

Active High

For Gen3, specifies the start block byte location for TX data in the 128-bit block data.

Used when the interface between the PCS and PHY-MAC (FPGA Core) is 32 bits.


Active High

Forces the transmit output to electrical idle.

Refer to the Intel PHY Interface for PCI

Express (PIPE) for timing diagrams.

Gen1 - Width of signal is 1 bit/lane.

Gen2 - Width of signal is 2 bits/lane. For example, if the MAC connected to PIPE

Gen2x4 has 1bit/lane, then you can use the following mapping to connect to PIPE:

{pipe_tx_elecidle[7:0] =

{{2{tx_elecidle_ch3}},

{2{tx_elecidle_ch2}},{2{tx_elecidle_ch1}},

{2{tx_elecidle_ch0}}} where tx_elecidle_* is the output signal from MAC.

Gen3 - Width of signal is 4 bits/lane. For example, if the MAC connected to PIPE


{pipe_tx_elecidle[15:0] =

{{4{tx_elecidle_ch3}},

{4{tx_elecidle_ch2}},{4{tx_elecidle_ch1}},

{4{tx_elecidle_ch0}}} where tx_elecidle_* is the output signal from MAC.

Active High

Instructs the PHY to start a receive detection operation. After power-up, asserting this signal starts a loopback operation. Refer to section 6.4 of the Intel PHY Interface for PCI

Express (PIPE) for a timing diagram.

Active High

Asserted for one cycle to set the running disparity to negative. Used when transmitting the compliance pattern. Refer to section 6.11

of the Intel PHY Interface for PCI Express

(PIPE) Architecture for more information.

Gen1 - Width of signal is 1 bit/lane.

Gen2 - Width of signal is 2 bits/lane.

For example, if the MAC connected to PIPE


{pipe_tx_compliance[7:0] =

{{2{tx_compliance_ch3}},

{2{tx_compliance _ch2}},

{2{tx_compliance_ch1}}, {2{tx_compliance

_ch0}}}. Where tx_compliance_* is the output signal from MAC.

Gen3 - Width of signal is 4 bits/lane.

continued...


259

Port pipe_rx_polarity[(N-1):

0] pipe_powerdown[(2N-1):

0] pipe_tx_margin[(3N-1):

0] pipe_tx_swing[(N-1):0] pipe_tx_deemph[(N-1):0] pipe_g3_tx_deemph[(18N-

1):0]

Direction

In

In

In

In

In

In

Clock Domain


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Asynchronous tx_coreclkin tx_coreclkin tx_coreclkin

Asynchronous

Asynchronous

Description

For example, if the MAC connected to PIPE


{pipe_tx_compliance[15:0]= {{4{tx_ compliance _ch3}}, {4{tx_ compliance

_ch2}}, {4{tx_ compliance _ch1}}, {4{tx_ compliance _ch0}}}. Where tx_ compliance

_* is the output signal from MAC.

Active High

When 1'b1, instructs the PHY layer to invert the polarity on the received data.

Active High

Requests the PHY to change its power state to the specified state. The Power States are encoded as follows:

2'b00: P0 - Normal operation.

2'b01: P0s - Low recovery time, power saving state.

2'b10: P1 - Longer recovery time, lower power state .

2'b11: P2 - Lowest power state.

Transmit V

OD

margin selection. The PHY-MAC sets the value for this signal based on the value from the Link Control 2 Register. The following encodings are defined:

3'b000: Normal operating range

3'b001: Full swing: 800 - 1200 mV; Half swing: 400 - 700 mV.

3'b010:-3'b011: Reserved.

3'b100-3'b111: Full swing: 200 - 400mV;

Half swing: 100 - 200 mV else reserved.

Indicates whether the transceiver is using

Full swing or Half swing voltage as defined by the pipe_tx_margin

.

1'b0-Full swing.

1'b1-Half swing.

Transmit de-emphasis selection. In PCI

Express Gen2 (5 Gbps) mode it selects the transmitter de-emphasis:

1'b0: –6 dB.

1'b1: –3.5 dB.

The pipe_g3_tx_deemph

port is used to select the link partners transmitter deemphasis during equalization. The 18 bits specify the following coefficients:

[5:0]: C

-1

[11:6]: C

0

[17:12]: C

+1

Refer to Preset Mappings to TX De-emphasis

on page 267 for presets to TX de-emphasis mappings. In Gen3 capable designs, the TX de-emphasis for Gen2 data rate is always -6 dB. The TX de-emphasis for Gen1 data rate is always -3.5 dB.

Refer to section 6.6 of Intel PHY Interface for

PCI Express (PIPE) Architecture for more information.

continued...

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Port pipe_g3_rxpresethint[(3

N-1):0] pipe_rx_eidleinfersel[(

3N-1):0] pipe_rate[1:0] pipe_sw_done[1:0] pipe_tx_data_valid[(N-1

):0] rx_parallel_data[31:0]

[15:0]

, or

[7:0]

,

Direction

In

In

In

In

In

Out

Clock Domain

Asynchronous

Asynchronous

Asynchronous

N/A

Description

Note: Intel recommends transmitting Preset

P8 coefficients for Arria 10 receiver to recover data successfully.

This is used to trigger CTLE adaptation in

Phase2 (EP) /Phase 3 (RP) to achieve receiver Bit Error Rate (BER) that is less than

10 -12 .

Gen3 capable design at Gen1/Gen2 speeds:

This should be set to 3’b000.

Gen3 capable design at Gen3 speed: Refer to section “PHY IP Core for PCIe (PIPE) Link

Equalization for Gen3 Data Rate” for details on when to set/reset this port.

When asserted high, the electrical idle state is inferred instead of being identified using analog circuitry to detect a device at the other end of the link. The following encodings are defined:

3'b0xx: Electrical Idle Inference not required in current LTSSM state.

3'b100: Absence of COM/SKP OS in 128 ms.

3'b101: Absence of TS1/TS2 OS in 1280 UI interval for Gen1 or Gen2.

3'b110: Absence of Electrical Idle Exit in

2000 UI interval for Gen1 and 16000 UI interval for Gen2.

3'b111: Absence of Electrical Idle exit in 128 ms window for Gen1.

Note: Recommended to implement Receiver

Electrical Idle Inference (EII) in FPGA fabric.

The 2-bit encodings defined in the following list:

2'b00: Gen1 rate (2.5 Gbps)



Signal from the Master clock generation buffer, indicating that the rate switch has completed. Use this signal for bonding mode only.

For non-bonded applications, this signal is internally connected to the local CGB.

tx_coreclkin

For Gen3, this signal is deasserted by the

MAC to instruct the PHY to ignore tx_parallel_data

for current clock cycle.

A value of 1'b1 indicates the PHY should use the data. A value of 0 indicates the PHY should not use the data.

Active High

PIPE Output to PHY - MAC Layer rx_coreclkin

The RX parallel data driven to the MAC.

For Gen1 this can be 8 or 16 bits. For Gen2 this is 16 bits only. For Gen3 this is 32 bits.Refer to Bit Mappings When the

Simplified Interface is Disabled for more details.

continued...


261

Port rx_datak[3:0]

,

[1:0]

, or

[0] pipe_rx_sync_hdr[(2N-1)

:0] pipe_rx_blk_start[(N-1)

:0] pipe_rx_data_valid[(N-1

):0] pipe_rx_valid[(N-1):0] pipe_phy_status[(N-1):

0] pipe_rx_elecidle[(N-1):

0] pipe_rx_status[(3N-1):

0]

Direction

Out

Out

Out

Out

Out

Out

Out

Out

Clock Domain


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rx_coreclkin rx_coreclkin rx_coreclkin rx_coreclkin rx_coreclkin rx_coreclkin

Asynchronous rx_coreclkin

Description

The data and control indicator.

For Gen1 or Gen2, when 0, indicates that rx_parallel_data

is data, when 1, indicates that control.

rx_parallel_data is

For Gen3,

Bit[0]

corresponds to rx_parallel_data[7:0]

,

Bit[1] corresponds to rx_parallel_data[15:8] and so on. Refer to tableBit Mappings When

the Simplified Interface is Disabled for more details.

,

For Gen3, indicates whether the 130-bit block being transmitted is a Data or Control

Ordered Set Block. The following encodings are defined:

2'b10: Data block

2'b01: Control Ordered Set block

This value is read when pipe_rx_blk_start

= 4'b0001. Refer to

Section 4.2.2.1. Lane Level Encoding in the

PCI Express Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding.

For Gen3, specifies the start block byte location for RX data in the 128-bit block data. Used when the interface between the

PCS and PHY-MAC (FPGA Core) is 32 bits.


Active High

For Gen3, this signal is deasserted by the

PHY to instruct the MAC to ignore rx_parallel_data

for current clock cycle.

A value of 1'b1 indicates the MAC should use the data. A value of 1'b0 indicates the MAC should not use the data.

Active High

Asserted when RX data and control are valid.

Signal used to communicate completion of several PHY requests.

Active High

When asserted, the receiver has detected an electrical idle.

Active High

Signal encodes receive status and error codes for the receive data stream and receiver detection. The following encodings are defined:

3'b000 - Receive data OK

3'b001 - 1 SKP added

3'b010 - 1 SKP removed

3'b011 - Receiver detected

3'b100 - Either 8B/10B or 128b/130b decode error and (optionally) RX disparity error

3'b101 - Elastic buffer overflow

3'b110 - Elastic buffer underflow continued...

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Port pipe_sw[1:0]

Direction

Out

Clock Domain

N/A

Description

3'b111 - Receive disparity error, not used if disparity error is reported using 3'b100.

Signal to clock generation buffer indicating the rate switch request. Use this signal for bonding mode only.

For non-bonded applications this signal is internally connected to the local CGB.

Active High. Refer to Table 191 on page 263

Bit Mappings When the Simplified Interface is

Disabled for more details.

Table 191.

Bit Mappings When the Simplified Interface Is Disabled


Native PHY IP Core for the full range of parameter values.

Signal Name Gen1 (TX Byte

Serializer and RX

Byte Deserializer disabled)

Gen1 (TX Byte

Serializer and RX Byte

Deserializer in X2 mode), Gen2 (TX Byte


Deserializer in X2 mode)

Gen3 tx_parallel_data tx_parallel_dat a[7:0] tx_parallel_data[29

:22,7:0] tx_parallel_data[40:33,29:22,18

:11,7:0] tx_datak pipe_tx_compliance pipe_tx_elecidle pipe_tx_detectrx_loop bacK pipe_powerdown pipe_tx_margin pipe_tx_swing rx_parallel_data rx_datak rx_syncstatus pipe_phy_status pipe_rx_valid pipe_rx_status tx_parallel_dat a[8] tx_parallel_dat a[9] tx_parallel_dat a[10] tx_parallel_dat a[46] tx_parallel_dat a[48:47] tx_parallel_dat a[51:49] tx_parallel_dat a[53] rx_parallel_dat a[7:0] rx_parallel_dat a[8] rx_parallel_dat a[10] rx_parallel_dat a[65] rx_parallel_dat a[66] rx_parallel_dat a[69:67] tx_parallel_data[30

,8] tx_parallel_data[41,30,19,8] tx_parallel_data[31



] tx_parallel_data[46] tx_parallel_data[48

:47] tx_parallel_data[48:47] tx_parallel_data[51

:49] tx_parallel_data[51:49] tx_parallel_data[53

] tx_parallel_data[53] rx_parallel_data[39

:32,7:0] rx_parallel_data[40

,8] rx_parallel_data[55:48,39:32,23

:16,7:0] rx_parallel_data[56,40,24,8] rx_parallel_data[42

,10] rx_parallel_data[58,42,26,10] rx_parallel_data[65

] rx_parallel_data[65] rx_parallel_data[66

] rx_parallel_data[66] rx_parallel_data[69

:67] rx_parallel_data[69:67] continued...


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Signal Name pipe_tx_deemph pipe_tx_sync_hdr pipe_tx_blk_start pipe_tx_data_valid pipe_rx_sync_hdr pipe_rx_blk_start pipe_rx_data_valid

Gen1 (TX Byte

Serializer and RX

Byte Deserializer disabled)

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Gen1 (TX Byte


Deserializer in X2 mode), Gen2 (TX Byte


Deserializer in X2 mode) tx_parallel_data[52

]

N/A

N/A

N/A

N/A

N/A

N/A

Gen3

N/A tx_parallel_data[55:54] tx_parallel_data[56] tx_parallel_data[60] rx_parallel_data[71:70] rx_parallel_data[72] rx_parallel_data[76]

Refer to section 6.6 of Intel PHY Interface for PCI Express (PIPE) Architecture for more information.


•

PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate on page 274

• Intel PHY Interface for PCI Express (PIPE) Architecture

•

Bit Mappings When the Simplified Interface is Disabled

on page 263

•


on page 45

2.7.9. fPLL Ports for PIPE

Table 192.

fPLL Ports for PIPE



Port

Pll_powerdown

Pll_reflck0 tx_serial_clk

Direction Clock Domain

Input

Description

Asynchronous Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY

Reset Controller

FPGA IP).

pll_powerdown

output if using this Intel

Input N/A

Output N/A

Reference clock input port 0. There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.

High speed serial clock output port for GX channels.

Represents the x1 clock network.

For Gen1x1, Gen2x1, connect the output from this port to the tx_serial_clk

input of the native PHY IP.

For Gen1x2, x4, x8, use the tx_bonding_clocks port to connect to the Native PHY IP.

output

For Gen2x2, x4, x8, use the tx_bonding_clocks port to connect to the Native PHY IP.

output

For Gen3x1, connect the output from this port to one of the two tx_serial_clk

input ports on the native PHY IP.

For Gen3x2, x4, x8, connect the output from this port to the Auxiliary Master CGB clock input port of the ATX PLL IP.

continued...

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pll_locked

Port pll_pcie_clk

Pll_cal_busy

Mcgb_rst mcgb_aux_clk0 tx_bonding_clocks[6n-1:0] pcie_sw[1:0] pcie_sw_done[1:0]

]


Output Asynchronous

Description

Active high status signal which indicates if PLL is locked.

Output

Output

Input

Input

N/A This is the hclk required for PIPE interface.

For Gen1x1, x2, x4, x8 use this port to drive the the PIPE interface.

hclk for

For Gen2x1, x2, x4, x8 use this port to drive the the PIPE interface.

hclk

for

For Gen3x1, x2, x4, x8, use the interface.

pll_pcie_clk

from fPLL

(configured as Gen1/Gen2) as the hclk for the PIPE

Asynchronous Status signal which is asserted high when PLL calibration is in progress.

If this port is not enabled in Transceiver PHY Reset

Controller, then perform logical OR with this signal and the tx_cal_busy

output signal from Native PHY to input the tx_cal_busy

on the reset controller IP.

Asynchronous Master CGB reset control.

Output

Input

Output

N/A

N/A

Used for Gen3 to switch between fPLL/ATX PLL during link speed negotiation. For gen3x2, x4, x8 use the mcgb_aux_clk

input port on the ATX PLL.

Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB. It is used for channel bonding, and represents the x6/xN clock network.

For Gen1x1, this port is disabled.

For Gen1x2, x4, x8 connect the output from this port to the tx_bonding_clocks

input on Native PHY.


For Gen2x2, x4, x8 connect the output from this port to the tx_bonding_clocks



For Gen3x2, x4, x8, use the tx_bonding_clocks

output from the ATX PLL to connect to the input of the Native PHY.

tx_bonding_clocks

Asynchronous 2-bit rate switch control input used for PCIe protocol implementation.

For Gen1, this port is N/A

For Gen 2x2, x4, x8 connect the

Native PHY to this port.

pipe_sw

output from

For Gen3x2, x4, x8 connect the

Native PHY to this port.

pipe_sw

output from the

For Gen3x2, x4, x8, this port is not used. You must use the pipe_sw

from Native PHY to drive the pcie_sw

input port on the ATX PLL.

Asynchronous 2-bit rate switch status output used for PCIe protocol implementation.

For Gen1, this port is N/A.

For Gen 2x2, x4, x8 connect the pcie_sw_done

output from ATX PLL to the pipe_sw_done

input of Native PHY .

For Gen3x2, x4, x8 connect the from ATX PLL to the pcie_sw_done

output pipe_sw_done

input of Native PHY.



on page 45


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2.7.10. ATX PLL Ports for PIPE

Table 193.

ATX PLL Ports for PIPE



Port

Pll_powerdown

Pll_reflck0 tx_serial_clk pll_locked pll_pcie_clk

Pll_cal_busy

Mcgb_rst mcgb_aux_clk0 tx_bonding_clocks[5:0]


Input

Description

Asynchronous Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY Reset

Controller pll_powerdown

output if using this Intel FPGA IP.

Input

Output

Output

N/A

N/A

Reference clock input port 0. There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.

High speed serial clock output port for GX channels. Represents the x1 clock network.

For Gen1x1, Gen2x1, connect the output from this port to the tx_serial_clk input of the native PHY IP.

For Gen1x2, x4, x8, use the tx_bonding_clocks output port to connect to the Native PHY.

For Gen2x2, x4, x8, use the tx_bonding_clocks output port to connect to the Native PHY.

For Gen3x1, connect the output from this port to one of the two tx_serial_clk input ports on the native PHY IP.

For Gen3x2, x4, x8, this port is not used. Use the tx_serial_clk output from the fPLL to drive the Auxiliary Master CGB clock input port of the ATX PLL.

Asynchronous Active high status signal which indicates if PLL is locked.

Output

Output

Input

Input

N/A This is the hclk required for PIPE interface.

For Gen1x1,x2,x4,x8 use this port to drive the hclk for the PIPE interface.

For Gen2x1,x2,x4,x8 use this port to drive the hclk for the PIPE interface.

For Gen3x1,x2,x4,x8, this port is not used. Use the pll_pcie_clk

from fPLL (configured as Gen1/Gen2) as the hclk for the PIPE interface.

Asynchronous Status signal which is asserted high when PLL calibration is in progress. If this port is not enabled in the Transceiver PHY

Reset Controller, then perform logical OR with this signal and the tx_cal_busy

output signal from Native PHY to input the tx_cal_busy

on the reset controller IP.

Asynchronous Master CGB reset control.

N/A

Output N/A

Used for Gen3 to switch.

between fPLL/ATX PLL during link speed negotiation.

For gen3x2,x4,x8 use the tx_serial_clk output

port from fPLL (configured for Gen1/Gen2) to drive the input port on the ATX PLL.

mcgb_aux_clk

Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB. Used for channel bonding, and represents the x6/xN clock network.


For Gen1x2,x4,x8 connect the output from this port to the tx_bonding_clocks


For Gen2x1, this port is disabled

For Gen2x2,x4,x8 connect the output from this port to tx_bonding_clocks



continued...

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Port pcie_sw[1:0] pcie_sw_done[1:0]


Input

Output

Description

For Gen3x2,x4,x8 use the tx_bonding_clocks

output from the ATX PLL to connect to the the Native PHY.

tx_bonding_clocks

input of

Asynchronous 2-bit rate switch control input used for PCIe protocol implementation.


For Gen 2x2,x4,x8 connect the

PHY to this port.

pipe_sw

output from Native

For Gen3x2,x4,x8 use the drive this port.

pipe_sw

output from Native PHY to

Asynchronous 2-bit rate switch status output used for PCIe protocol implementation.


For Gen2x2, x4, x8 connect the pcie_sw_done

output from

ATX PLL to pipe_sw_done input of Native PHY .

For Gen3x2, x4, x8 pcie_sw_done

output from ATX PLL to pipe_sw_done

input of Native PHY.



on page 45

2.7.11. Preset Mappings to TX De-emphasis

Table 194.

Arria 10 Preset Mappings to TX De-emphasis

Preset C

+1

C

0

6

7

4

5

8

9

10

0

1

2

3

001111

001010

001100

001000

000000

000000

000000

001100

001000

000000

010110

101101

110010

110000

110100

111100

110110

110100

101010

101100

110010

100110

000000

000000

000000

000000

000000

000110

001000

000110

001000

001010

000000

C

-1

The pipe_g3_txdeemph

port is used to select the link partner’s transmitter deemphasis during equalization. The 18 bits specify the following coefficients:

[5:0]: C

-1

[11:6]: C

0

[17:12]: C

+1


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Note: Intel recommends transmitting Preset P8 coefficients for Arria 10 receiver to recover data successfully.

2.7.12. How to Place Channels for PIPE Configurations

Instead of the fitter or software model, the hardware dictates all the placement restrictions. The restrictions are listed below:

• The channels must be contiguous for bonded designs.

• The master CGB is the only way to access x6 lines and must be used in bonded designs. The local CGB cannot be used to route clock signals to slave channels because the local CGB does not have access to x6 lines.

• When implementing a Gen3-capable PIPE configuration in a -2 or -3 core speed grade, you cannot place the Logical PCS Master Channel in a location adjacent to the Hard IP (HIP).

• Non PCIe-Channels that are placed next to active banks with PIPE interfaces that are Gen3 capable have the following restrictions

— When VCCR_GXB and VCCT_GXB are set to 1.03 V or 1.12 V, the maximum data rate supported for the non-PCIe channels in those banks is 12.5 Gbps for chip-to-chip applications. These channels cannot be used to drive backplanes or for GT rates.

— When VCCR_GXB and VCCT_GXB are set to 0.95 V, the non-PCIe channels in those banks cannot be used.

For channel placement guidelines when using Arria 10 Hard IP for PCIe, refer to the

PCIe User Guide.

For ATX PLL placement restrictions, refer to the section "Transmit PLL

Recommendations Based on Data Rates" of PLLs and Clock Networks chapter.


• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide

•

PLLs and Clock Networks on page 347

2.7.12.1. Master Channel in Bonded Configurations

For PCIe, both the PMA and PCS must be bonded. There is no need to specify the PMA

Master Channel because of the separate Master CGB in the hardware. However, you must specify the PCS Master Channel through the Native PHY. You can choose any one of the data channels (part of the bonded group) as the logical PCS Master Channel.

Note: Whichever channel you pick as the PCS master, the fitter selects the physical CH1 or

CH4 of a transceiver bank as the master channel. This is because the ASN and Master

CGB connectivity only exists in the hardware of these two channels of the transceiver bank.

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Table 195.

Logical PCS Master Channel for PIPE Configuration

PIPE Configuration x1 x2 x4 x8

Logical PCS Master Channel # (default)

0 (

44 )

1 (

44 )

2 (

44 )

4 (

44 )

The following figures show the default configurations:

Figure 109. x2 Configuration

1

0

Logical

Channel

CH1

CH0

Physical

Channel

CH1

CH0

CH5

CH4

CH3

CH2

CH5

CH4

CH3

CH2

Master CH

Data CH

Master

CGB

Master

CGB

Master

CGB

Master

CGB fPLL

ATX

PLL fPLL

ATX

PLL fPLL

ATX

PLL fPLL

ATX

PLL

Note:

Transceiver bank

Transceiver bank

The physical channel 0 aligns with logical channel 0. The logical PCS Master Channel 1 is specified as Physical Channel 1.

(44) Ensure that the Logical PCS Master Channel aligns with Physical Channel 1 or 4 in a given transceiver bank.


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The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master

Channel number 2 must be specified as Physical channel 4.

fPLL

3

2

1

0

Logical

Channel

CH4

CH3

CH2

CH1

CH0

Physical

Channel

CH1

CH0

CH5

CH5

CH4

CH3

CH2

Data CH

Master CH

Data CH

Data CH

Master

CGB

Master

CGB

Master

CGB

Master

CGB

ATX

PLL fPLL

ATX

PLL fPLL

ATX

PLL fPLL

ATX

PLL

Transceiver bank

Transceiver bank

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For x8 configurations, Intel recommends you choose a master channel that is a maximum of four channels away from the farthest slave channel.

fPLL

7

6

5

4

3

2

1

0

Logical

Channel

CH4

CH3

CH2

CH1

CH0

Physical

Channel

CH1

CH0

CH5

CH5

CH4

CH3

CH2

Data CH

Data CH

Data CH

Master CH

Data CH

Data CH

Data CH

Data CH

Master

CGB

Master

CGB

Master

CGB

Master

CGB

ATX

PLL fPLL

ATX

PLL fPLL

ATX

PLL fPLL

ATX

PLL

Transceiver bank

Transceiver bank

Note: The physical channel 0 aligns with logical channel 0. The logical PCS master channel 4 is specified as Physical channel 4.


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Figure 112. x4 Alternate Configuration

The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master

Channel number 2 must be specified as Physical channel 1.

fPLL

3

2

1

0

Logical

Channel

CH4

CH3

CH2

CH1

CH0

Physical

Channel

CH1

CH0

CH5

CH5

CH4

CH3

CH2 Data CH

Master CH

Data CH

Data CH

Master

CGB

Master

CGB

Master

CGB

Master

CGB

ATX

PLL fPLL

ATX

PLL fPLL

ATX

PLL fPLL

ATX

PLL

Transceiver bank

Transceiver bank

As indicated in the figures above, the fitter picks either physical CH1 or CH4 as the

PCS master in bonded configurations for PIPE.

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Figure 113. x4 Configuration with the Master Channel Adjacent to a Hard IP

The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is adjacent to a Hard IP.

3

2

1

0

CH5

CH4

CH3

CH2

CH1

CH0

CH5

CH4

CH5

CH4

CH3

CH2

CH3

CH2

CH1

CH0

CH1

CH0

Hard

IP

Data CH

Master CH

Data CH

Data CH fPLL

Master CGB fPLL

Master CGB fPLL

Master CGB fPLL

Master CGB fPLL

Master CGB fPLL

Master CGB

ATX

PLL

ATX

PLL

ATX

PLL

ATX

PLL

ATX

PLL

ATX

PLL

Transceiver

Bank

Transceiver

Bank

Transceiver

Bank

Logical

Channel

Physical

Channel


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Figure 114. x4 Configuration with the Master Channel not Adjacent to a Hard IP

The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is not adjacent to a Hard IP.

3

2

1

CH5

CH4

CH3

CH2

CH1

CH0

Data CH

Master CH

Data CH fPLL

Master CGB fPLL

Master CGB

ATX

PLL

ATX

PLL

Transceiver

Bank

0 CH5

CH4

CH3

CH2

CH1

CH0

CH5

CH4

CH3

CH2

CH1

CH0

Hard

IP

Data CH fPLL

Master CGB fPLL

Master CGB fPLL

Master CGB fPLL

Master CGB

ATX

PLL

ATX

PLL

ATX

PLL

ATX

PLL

Transceiver

Bank

Transceiver

Bank

Logical

Channel

Physical

Channel

2.7.13. PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate

Gen3 mode requires TX and RX link equalization because of the data rate, the channel characteristics, receiver design, and process variations. The link equalization process allows the Endpoint and Root Port to adjust the TX and RX setup of each lane to improve signal quality. This process results in Gen3 links with a receiver Bit Error Rate

(BER) that is less than 10 -12 .

For detailed information about the four-stage link equalization procedure for 8.0 GT/s data rate, refer to Section 4.2.3 in the PCI Express Base Specification, Rev 3.0. A new

LTSSM state, Recovery.Equalization with Phases 0–3, reflects progress through Gen3 equalization. Phases 2 and 3 of link equalization are optional. Each link must progress through all four phases, even if no adjustments occur. If you skip Phases 2 and 3, you speed up link training at the expense of link BER optimization.

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Phase 0

Phase 0 includes the following steps:

1. The upstream component enters Phase 0 of equalization during

Recovery.Rcvrconfig by sending EQ TS2 training sets with starting presets for the downstream component. EQ TS2 training sets may be sent at 2.5 GT/s or 5 GT/s.

2. The downstream component enters Phase 0 of equalization after exiting

Recovery.Speed at 8 GT/s. It receives the starting presets from the training sequences and applies them to its transmitter. At this time, the upstream component has entered Phase 1 and is operating at 8 GT/s.

3. To move to Phase 1, the receiver must have a BER < 10 able to decode enough consecutive training sequences.

-4 . The receiver should be

4. In order to move to Equalization Phase 1, the downstream component must detect training sets with Equalization Control (EC) bits set to 2’b01.

Phase 1

During Phase 1 of the equalization process, the link partners exchange Full Swing (FS) and Low Frequency (LF) information. These values represent the upper and lower bounds for the TX coefficients. The receiver uses this information to calculate and request the next set of transmitter coefficients.

1. The upstream component moves to EQ Phase 2 when training sets with EC bits set to 1’b0 are captured on all lanes. It also sends EC=2’b10, starting pre-cursor, main cursor, and post-cursor coefficients.

2. The downstream component moves to EQ Phase 2 after detecting these new training sets.

Use the pipe_g3_txdeemph[17:0] port to select the transmitter de-emphasis. The

18 bits specify the following coefficients:

• [5:0]: C

-1

• [11:6]: C

0

• [17:12]: C

+1

Refer to Preset Mappings to TX De-emphasis for the mapping between presets and TX de-emphasis.

Phase 2 (Optional)

During Phase 2, the Endpoint tunes the TX coefficients of the Root Port. The TS1 Use

Preset bit determines whether the Endpoint uses presets for coarse resolution or coefficients for fine resolution.

If you are using the PHY IP Core for PCI Express (PIPE) as the Root Port, the Endpoint can tune the Root Port TX coefficients.

The tuning sequence typically includes the following steps:

1. The Endpoint receives the starting presets from the Phase 2 training sets sent by the Root Port.

2. The circuitry in the Endpoint receiver determines the BER. It calculates the next set of transmitter coefficients using FS and LF. It also embeds this information in the Training Sets for the Link Partner to apply to its transmitter.


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The Root Port decodes these coefficients and presets, performs legality checks for the three transmitter coefficient rules and applies the settings to its transmitter and also sends them in the Training Sets. The default Full Swing (FS) value advertised by the Intel device is 60 and Low Frequency (LF) is 20. The three rules for transmitter coefficients are: a. |C

-1

| <= Floor (FS/4) b. |C

-1

|+C

0

+|C

+1

| = FS c. C

0

-|C

-1

|-|C

+1

|>= LF

Where: C

0

is the main cursor (boost), C

-1

is the pre-cursor (pre-shoot), and C

+1

is

the post-cursor (de-emphasis).

3. This process is repeated until the downstream component's receiver achieves a

BER of < 10 -12

Phase 3 (Optional)

During this phase, the Root Port tunes the Endpoint’s transmitter. This process is analogous to Phase 2 but operates in the opposite direction.

After Phase 3 tuning is complete, the Root Port moves to Recovery.RcvrLock, sending

EC=2’b00, and the final coefficients or preset agreed upon in Phase 2. The Endpoint moves to Recovery.RcvrLock using the final coefficients or preset agreed upon in

Phase 3.

Recommendations for Tuning Link

To improve the BER of the receiver, Intel recommends that you turn on CTLE in triggered mode during Phase 2 Equalization for Endpoints or Phase 3 Equalization for

Root Ports.

Use the port pipe_g3_txdeemph[17:0]

to transmit the coefficients corresponding to the Gen3 presets. Intel recommends transmitting Preset P8 coefficients for A10 receiver to recover data successfully. The pipe_g3_txdeemph

is used to select the link partner’s transmitter de-emphasis during equalization.

Use the port pipe_g3_rxpresethint[2:0]

to turn on CTLE in triggered mode during equalization phases.

Table 196.

CTLE mode for Gen1/Gen2 speeds of Gen3 capable design

Use this table to drive the pipe_g3_rxpresethint

Gen1/Gen2 speeds of a Gen3 capable design.

port and set the CTLE in manual mode when operating at

Supported CTLE - mode Manual. To use CTLE in manual mode Gen3 capable design running at Gen1/Gen2 speeds during

Power up

Down train to Gen1/Gen2 (directed or not) and subsequent re-entry to Gen3

Down train to Gen1/Gen2

• During power up, set pipe_g3_rxpresethint[2:0]

= 3’b000

• You can use the default CTLE 4S AC Gain set by Quartus (or)

• Set the manual CTLE 4S AC Gain using QSF assignments

• On entry to Gen1/2, set pipe_g3_rxpresethint[2:0]

= 3’b000



• On entry to Gen1/2, set pipe_g3_rxpresethint[2:0]

= 3’b000



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Note: Intel does not support use of CTLE in adaptive mode for Gen1/Gen2 speeds. You must use CTLE in manual mode.

Table 197.

CTLE mode for Gen3 speed of Gen3 capable design

Use this table to drive the pipe_g3_rxpresethint operating at Gen3 speed for Gen3 capable designs.

port and set the CTLE mode to adaptation mode when

Supported CTLE - mode Triggered adaptation. To use CTLE in adaptation mode, Set Gen3 capable design running at Gen3 speed during

1st time entry to Gen3

Redoing EQ in Gen3

• In EQ Phase2/3, after far end TX preset/coefficient requests are completed, set pipe_g3_rxpresethint

= 3’b111 and link needs to stay in Recovery for at least 12ms for

CTLE adaptation

• If there is not enough time in EQ phases, delay can be inserted in Recovery.RcvrLock after the EQ

• After that, pipe_g3_rxpresethint

should remain 3’b111 for Gen3 even in Recovery

• pipe_g3_rxpresethint

should be set to 3’b000 in EQ Phase2/3 entry

• Follow the same procedure as first time link up to Gen3

Re-entry to Gen3 after down train to Gen1/

Gen2 (directed or not)

• On subsequent entry to Gen3, set pipe_g3_rxpresethint[2:0] valid data and wait for 12ms in Recovery state for CTLE adaptation

= 3’b111 when there is

Note: Intel recommends that you use CTLE in adaptive mode for Gen3 speed. If you want to use CTLE in manual mode for Gen3 speed, then you must set pipe_g3_rxpresethint[2:0]

= 3’b000 and set the CTLE 4S AC gain value




•

Preset Mappings to TX De-emphasis

on page 267

•

Continuous Time Linear Equalization (CTLE)

on page 452

• PCI Express Base Specification

• PIPE Specification

2.7.14. Using Transceiver Toolkit (TTK)/System Console/Reconfiguration

Interface to manually tune Arria 10 PCIe designs (Hard IP(HIP) and

PIPE) (For debug only)

Table 198.

Manual tuning of TX analog settings for PCIe channels

To manually tune TX channels of the Arria 10 PCIe designs using TTK/System Console/Reconfiguration

Interface, you must set the following attributes

Attribute Description Default value in PCIe mode

1’b1

Value to be set to use TTK/

System Console

1’b0 user_fir_coe ff_ctrl_sel

0x105[7]

Mux to select between static vs dynamic (port) control

• 0 for static setting (to use TTK/ system console for manual tuning)

• 1 for dynamic control (PCIe mode) continued...


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Attribute Default value in PCIe mode pre_emp_swit ching_ctrl_p re_tap_1t

0x107[4:0] pre_emp_sign

_pre_tap_1t

0x107[5]

Controlled by coefficients on the port pipe_g3_txdeemph negative vod_output_s wing_ctrl

0x109[4:0] pre_emp_swit ching_ctrl_1 st_post_tap

0x105[4:0] pre_emp_sign

_1st_post_ta p 0x105[6]

Controlled by coefficients on the port pipe_g3_txdeemph

Controlled by coefficients on the port pipe_g3_txdeemph

Negative


System Console

Description

Depends on value set by pre_emp_switching_ctrl_pre_ tap_1t

register setting

Setting this mux affects VOD, pre tap and post tap attributes

Sets 1st Pre tap value

• Direct mapped

Depends on value set by pre_emp_sign_pre_tap_1t register

setting

Depends on value set by vod_output_swing_ctrl

register setting

Depends on value set by pre_emp_switching_ctrl_1st_ post_tap register setting

Sets 1st Pre tap sign

• - 1 negative (default for PCIe mode)

• 0 positive

Output swing

• Direct mapped

Sets 1st Post tap value

• Direct mapped

Depends on value set by pre_emp_sign_1st_post_tap reg ister setting

Set 1st Post tap sign

• - 1 negative (default for PCIe mode)

• - 0 positive

Note: You must set the attribute user_fir_coeff_ctrl_sel

located at register address

0x105[7] back to 1’b1 to allow the Arria 10 PCI Express PIPE design to listen to the port pipe_g3_txdeemph[17:0]

on each channel for normal PCIe operation.

Table 199.

Manual tunning of RX analog settings for PCIe channels

To manually tune RX channels of the Arria 10 PCI Express designs using TTK/System Console/Reconfiguration

Interface, you must set the following attribute

Attribute Description rrx_pcie_eqz

0x161[2]

Default value in PCIe mode

1’b1


System Console

1’b0 adp_4s_ctle_ bypass

0x167[0]

1’b0 • 1’b0 for Gen3 for Adaptive 4S

CTLE

• 1’b1 for Gen1/Gen2 for Manual

4S CTLE

Mux to select between static vs dynamic control

• 0 for static setting (use for manual tuning)

• 1 for dynamic control (PCIe mode)

Setting this mux affects the CTLE 4s gain and 1s gain values

Mux to select between CTLE 4S manual mode vs adaptive mode

• 0 for CTLE 4S adaptive mode

• 1 for CTLE 4S manual mode continued...

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Attribute adp_ctle_acg ain_4s

0x167[5:1]

Adp_status_s el

0x14C[5:0]

Test_mux

0x177[3:0]

Default value in PCIe mode

5’b0

Set the mux to 6’b011011 Set the mux to 6’b011011

Read values. Map 4 bit value read out to 5 bit gain values


System Console

Depends on the value set by adp_ctle_acgain_4s Register setting

Description

Set CTLE manual 4S AC gain

• Direct mapped

Read values. Map 4 bit value read out to 5 bit gain values

Sets the test mux to read the CTLE converged values from 0x177[3:0]

Reflects the converged values from

CTLE adaptation

Note: You must set the attribute rrx_pcie_eqz

located at register address 0x161[2] back to 1’b1 to allow the Arria 10 PCIe PIPE design to listen to the port pipe_g3_rxpresethint[2:0]

on each channel for normal PCIe operation.


•

Analog Parameter Settings on page 585

• Debugging Transceiver Links with Transceiver Toolkit

• Arria 10 Register Map

2.8. CPRI

The common public radio interface (CPRI) is a high-speed serial interface developed for wireless network radio equipment controller (REC) to uplink and downlink data from available remote radio equipment (RE).

The CPRI protocol defines the interface of radio base stations between the REC and the RE. The physical layer supports both the electrical interfaces (for example, traditional radio base stations) and the optical interface (for example, radio base stations with a remote radio head). The scope of the CPRI specification is restricted to the link interface only, which is a point-to-point interface. The link has all the features necessary to enable a simple and robust usage of any given REC and RE network topology, including a direct interconnection of multiport REs.


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2.8.1. Transceiver Channel Datapath and Clocking for CPRI

Figure 115. Transceiver Channel Datapath and Clocking for CPRI

Transmitter PMA Transmitter Standard PCS

40 32

FPGA

Fabric

245 MHz tx_clkout tx_pma_div_clkout

PRBS

Generator

/2, /4 tx_coreclkin

245 MHz tx_clkout

Receiver PMA Receiver Standard PCS

40

Parallel Clock

(Recovered)

245 MHz

Parallel Clock

(From Clock

Divider) rx_clkout tx_clkout

PRBS

Verifier

/2, /4 rx_pma_div_clkout

Clock Generation Block (CGB)

Clock Divider

32 rx_coreclkin

245 MHz rx_clkout or tx_clkout

ATX PLL

CMU PLL fPLL

Parallel Clock

Serial Clock

Parallel and Serial Clock Parallel and Serial Clock

Serial Clock

Table 200.

Channel Width Options for Supported Serial Data Rates

Serial Data

Rate

(Mbps)

614.4

(45)

1228.8

2457.6

3072

4915.2

6144

9830.4

8-Bit

Yes

Yes

Yes

Yes

N/A

N/A

N/A

8/10 Bit Width

Channel Width (FPGA-PCS Fabric)

16/20 Bit Width

16-Bit

Yes

Yes

Yes

16-Bit

N/A

Yes

Yes

32-Bit

N/A

Yes

Yes

Yes

N/A

N/A

N/A

Yes

Yes

Yes

N/A

Yes

Yes

Yes

Yes

Table 201.

Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates

Serial Data Rate

(Mbps)

10137.6

12165.12

Interface Width

FPGA fabric - Enhanced PCS (bit)

66

66

Enhanced PCS - PMA (bit)

32, 40, 64

40, 64

(45) Over-sampling is required to implement 614.4Mbps

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2.8.1.1. TX PLL Selection for CPRI

Choose a transmitter PLL that fits your required data rate.

Table 202.

TX PLL Supported Data Rates

ATX and fPLL support the clock bonding feature.

TX PLLs

ATX fPLL

CMU

Supported Data Rate (Mbps)

614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 8110.08, 9830.4, 10137.6, 12165.12

614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 8110.08, 9830.4, 10137.6, 12165.12

614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 8110.08, 9830.4, 10137.6

Note: • Channels that use the CMU PLL cannot be bonded. The CMU PLL that provides the clock can only drive channels in the transceiver bank where it resides.

• Over-sampling is required to implement 614.4Mbps.

2.8.1.2. Auto-Negotiation

When auto-negotiation is required, the channels initialize at the highest supported frequency and switch to successively lower data rates if frame synchronization is not achieved. If your design requires auto-negotiation, choose a base data rate that minimizes the number of PLLs required to generate the clocks required for data transmission.

By selecting an appropriate base data rate, you can change data rates by changing the local clock generation block (CGB) divider. If a single base data rate is not possible, you can use an additional PLL to generate the required data rates.

Table 203.

Recommended Base Data Rates and Clock Generation Blocks for Available

Data Rates

Data Rate (Mbps)

1228.8

2457.6

3072.0

4915.2

6144.0

9830.4

Base Data Rate (Mbps)

9830.4

9830.4

6144.0

9830.4

6144.0

9830.4

Local CGB Divider

8

4

2

2

1

1

2.8.2. Supported Features for CPRI

The CPRI protocol places stringent requirements on the amount of latency variation that is permissible through a link that implements these protocols.

CPRI (Auto) and CPRI (Manual) transceiver configuration rules are both available for

CPRI designs. Both modes use the same functional blocks, but the configuration mode of the word aligner is different between the Auto and Manual modes. In CPRI (Auto) mode, the word aligner works in deterministic mode. In CPRI (Manual) mode, the word aligner works in manual mode.


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To avoid transmission interference in time division multiplexed systems, every radio in a cell network requires accurate delay estimates with minimal delay uncertainty. Lower delay uncertainty is always desired for increased spectrum efficiency and bandwidth.

The Arria 10 devices are designed with features to minimize the delay uncertainty for both RECs and REs.

2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI

The deterministic latency state machine in the word aligner reduces the known delay variation from the word alignment process. It automatically synchronizes and aligns the word boundary by slipping one half of a serial clock cycle (1UI) in the deserializer.

Incoming data to the word aligner is aligned to the boundary of the word alignment pattern (K28.5).

Figure 116. Deterministic Latency State Machine in the Word Aligner

Clock-Slip

Control

Parallel

Clock

From RX CDR Deserializer

Deterministic Latency

Synchronization State Machine

To 8B/10B Decoder

When using deterministic latency state machine mode, assert rx_std_wa_patternalign

to initiate the pattern alignment after the reset sequence is complete. This is an edge-triggered signal in all cases except one: when the word aligner is in manual mode and the PMA width is 10, in which case rx_std_wa_patternalign

is level sensitive.

Figure 117. Word Aligner in Deterministic Mode Waveform rx_clkout rx_std_wa_patternalign rx_parallel_data rx_errdetect rx_disperr rx_patterndetect rx_syncstatus f1e4b6e4

1101

1101

0000

0000 b9dbf1db 915d061d e13f913f 7a4ae24a bbae9b10 bcbcbcbc

0000

0000

1010

1010

1000

1000

0010

0000

1010

1010

0000

0000

1111

1111

95cd3c50 91c295cd

0000


Word Aligner on page 485

2.8.2.1.1. Transmitter and Receiver Latency

The latency variation from the link synchronization function (in the word aligner block) is deterministic with the rx_bitslipboundaryselectout

port. Additionally, you can use the tx_bitslipboundaryselect

port to fix the round trip transceiver latency for port implementation in the remote radio head to compensate for latency variation in the word aligner block. The tx_bitslipboundaryselect

port is available to control the number of bits to be slipped in the transmitter serial data stream. You can optionally use the tx_bitslipboundaryselect round-trip latency to a whole number of cycles.

port to round the

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When using the byte deserializer, additional logic is required in the FPGA fabric to determine if the comma byte is received in the lower or upper byte of the word. The delay is dependent on the word in which the comma byte appears.

2.8.3. Word Aligner in Manual Mode for CPRI

When configuring the word aligner in CPRI (Manual), the word aligner parses the incoming data stream for a specific alignment character. After rx_digitalreset deasserts, asserting the rx_std_wa_patternalign

triggers the word aligner to look for the predefined word alignment pattern or its complement in the received data stream. It is important to note that the behavior of the word aligner in Manual mode operates in different ways depending on the PCS-PMA interface width.

Table 204.

Word Aligner Signal Status Behaviors in Manual Mode

PCS-PMA Interface Width

10 rx_std_wa_patternali gn

Behavior

Level sensitive

20 Edge sensitive rx_syncstatus

Behavior

One parallel clock cycle (When three control patterns are detected)

Remains asserted until next rising edge of rx_std_wa_patternalign rx_patterndetect

Behavior

One parallel clock cycle

One parallel clock cycle

PCS-PMA Width = 10

When the PCS-PMA interface width is 10, 3 consecutive word alignment patterns found after the initial word alignment in a different word boundary causes the word aligner to resynchronize to this new word boundary if the rx_std_wa_patternalign remains asserted; rx_std_wa_patternalign

is level sensitive. If you deassert rx_std_wa_patternalign

, the word aligner maintains the current word boundary even when it finds the alignment pattern in a new word boundary. When the word aligner is synchronized to the new word boundary, rx_patterndetect

and rx_syncstatus

are asserted for one parallel clock cycle.

PCS-PMA Width =20

When the PMA-PCS width is 20, any alignment pattern found after the initial alignment in a different word boundary causes the word aligner to resynchronize to this new word boundary on the rising edge of rx_std_wa_patternalign

; rx_std_wa_patternalign

is edge sensitive. The word aligner maintains the current word boundary until the next rising edge of rx_std_wa_patternalign

. When the word aligner is synchronized to the new word boundary, rx_patterndetect

asserts for one parallel clock cycle and rx_syncstatus remains asserted until the next rising edge of rx_std_wa_patternalign

.

Figure 118. Word Aligner in Manual Alignment Mode Waveform rx_clkout rx_std_wa_patternalign rx_parallel_data rx_patterndetect rx_syncstatus

0...

0

0000 f1e4b6e4 b9dbf1db 915d061d e13f913f 7a4ae24a bcbc7b78 bcbcbcbc

1100 1111

1100 1111

95cd3c50 91c295cd ded691c2

0000


Word Aligner on page 485


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2.8.4. How to Implement CPRI in Arria 10 Transceivers

You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing your CPRI protocol.

1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.


2. Select CPRI (Auto) or CPRI (Manual) from the Transceiver configuration

rules list located under Datapath Options, depending on which protocol you are implementing.

3. Use the parameter values in the tables in Native PHY IP Parameter Settings for

CPRI

on page 285 as a starting point. Or, you can use the protocol presets

described in Preset Configuration Options . You can then modify the setting to meet

your specific requirements.

4. Click Generate to generate the Native PHY IP (this is your RTL file).

Figure 119. Signals and Ports of Native PHY IP for CPRI

Arria 10 Transceiver Native PHY tx_cal_busy rx_cal_busy

NIOS

Hard Calibration IP

Reconfiguration

Registers tx_serial_data

TX PMA

Serializer

10/20

TX Standard PCS tx_datak tx_parallel_data tx_coreclkin tx_clkout unused_tx_parallel_data[118:0] reconfig_reset reconfig_clk reconfig_avmm tx_digital_reset tx_datak[1:0] tx_parallel_data[15:0] tx_coreclkin tx_clkout tx_serial_clk0

(from TX PLL) rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref

Local Clock

Generation

Block

RX PMA

Deserializer

CDR

10/20

RX Standard PCS rx_datak rx_parallel_data rx_clkout rx_coreclkin rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus rx_std_wa_patternalign unused_rx_parallel_data[118:0] tx_analog_reset rx_analog_reset rx_digital_reset rx_datak[1:0] rx_parallel_data[15:0] rx_clkout rx_coreclkin rx_errdetect[1:0] rx_disperr[1:0] rx_runningdisp[1:0] rx_patterndetect[1:0] rx_syncstatus[1:0] rx_std_wa_patternalign unused_rx_parallel_data[118:0]


6. Create a transceiver reset controller.

You can use your own reset controller or use the Native PHY Reset Controller IP.

7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the information in the following figure to connect the ports.

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Figure 120. Connection Guidelines for a CPRI PHY Design pll_refclk PLL IP Core clk reset pll_sel pll_locked

Reset Controller pll_cal_busy tx_ready rx_ready rx_cdr_refclk tx_serialclk0

Data

Generator tx_clkout tx_parallel_data

Data

Verifier rx_clkout rx_parallel_data

Arria 10 Transceiver Native PHY tx_serial_data rx_serial_data



•


on page 479

For more information about Standard PCS architecture

•

Arria 10 PMA Architecture on page 447

For more information about PMA architecture

•


on page 398

For more information about implementing PLLs and clocks

•

PLLs on page 349

PLL architecture and implementation details

•


on page 416

Reset controller general information and implementation details

•

Standard PCS Ports on page 86

Port definitions for the Transceiver Native PHY Standard Datapath

2.8.5. Native PHY IP Parameter Settings for CPRI

Table 205.

General and Datapath Options

The first two sections of the Parameter Editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.

Parameter

Message level for rule violations

Value error continued...


285

Parameter

Transceiver configuration rules

PMA configuration rules

Transceiver mode

Number of data channels

Data rate

Enable datapath and interface reconfiguration

Enable simplified data interface

Table 206.

TX PMA Parameters

Parameter

TX channel bonding mode

TX local clock division factor

Number of TX PLL clock inputs per channel

Initial TX PLL clock input selection

Enable tx_pma_clkout port

Enable tx_pma_div_clkout port tx_pma_div_clkout division factor

Enable tx_pma_elecidle port

Enable tx_pma_qpipullup port (QPI)

Enable tx_pma_qpipulldn port (QPI)

Enable tx_pma_txdetectrx port (QPI)

Enable tx_pma_rxfound port (QPI)

Enable rx_seriallpbken port


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Value warning

CPRI (Auto)

CPRI (Manual) basic

TX/RX Duplex

1-36

1228.8 Mbps

2457.6 Mbps

3072 Mbps

4915.2 Mbps

6144 Mbps

8110.08 Mbps

9830.4 Mbps

10137.6 Mbps

( 46 )

12165.12 Mbps

(

46

)

Off

On

Value

Not Bonded / PMA Bonding Only / PMA and PCS Bonding

1

1

0

Off

On

2

Off

Off

Off

Off

Off

Off

(46) 10137.6 Mbps and 12165.12 Mbps are implemented by selecting 10GBase-R or 10GBase-R

1588 under Transceiver configuration rules. The Enhanced PCS is selected when the CPRI data rate is 10137.6 Mbps and above.

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Table 207.

RX PMA Parameters

Parameter

Number of CDR reference clocks

Selected CDR reference clock

Selected CDR reference clock frequency

PPM detector threshold

CTLE adaptation mode

DFE adaptation mode

Number of fixed dfe taps

Enable rx_pma_clkout port

Enable rx_pma_div_clkout port rx_pma_div_clkout division factor

Enable rx_pma_clkslip port

Enable rx_pma_qpipulldn port (QPI)

Enable rx_is_lockedtodata port

Enable rx_is_lockedtoref port

Enable rx_set_locktodata and rx_set_locktoref ports


Enable PRBS verifier control and status ports

Table 208.

Standard PCS Parameters

Parameters

Standard PCS / PMA interface width

FPGA fabric / Standard TX PCS interface width

FPGA fabric / Standard RX PCS interface width

Enable 'Standard PCS' low latency mode

TX FIFO mode

RX FIFO mode

Enable tx_std_pcfifo_full port

Enable tx_std_pcfifo_empty port

Enable rx_std_pcfifo_full port

Enable rx_std_pcfifo_empty port

TX byte serializer mode

RX byte deserializer mode

Enable TX 8B/10B encoder

Enable TX 8B/10B disparity control

Enable RX 8B/10B decoder

Value

1

0

Select legal range defined by the Quartus Prime software

1000 manual disabled

3

Off

On

2

Off

Off

On

On

Off

Off

Off

Value

20

32

32

Off register_fifo register_fifo

Off

Off

Off

Off

Serialize x2

Deserialize x2

On

Off

On continued...


287

Parameters

RX rate match FIFO mode

RX rate match insert / delete -ve pattern (hex)

RX rate match insert / delete +ve pattern (hex)

Enable rx_std_rmfifo_full port

Enable rx_std_rmfifo_empty port

PCI Express Gen3 rate match FIFO mode

Enable TX bit slip

Enable tx_std_bitslipboundarysel port

RX word aligner mode

RX word aligner pattern length

RX word aligner pattern (hex)

Number of word alignment patterns to achieve sync

Number of invalid data words to lose sync

Number of valid data words to decrement error count

Enable fast sync status reporting for deterministic latency SM

Enable rx_std_wa_patternalign port

Enable rx_std_wa_a1a2size port

Enable rx_std_bitslipboundarysel port

Enable rx_bitslip port

All options under Bit Reversal and Polarity Inversion

All options under PCIe Ports

Table 209.


Parameter


Share reconfiguration interface

Enable Altera Debug Master Endpoint

Enable embedded debug




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Value

Disabled

0x00000000

0x00000000

Off

Off

Bypass

Off (CPRI Auto configuration)

On (CPRI Manual configuration)



deterministic latency (CPRI Auto configuration)

manual (FPGA fabric controlled) (CPRI

Manual configuration)

10

0x000000000000017c

3

( 47

)

3

( 47

)

3

( 47

)

On / Off

On / Off

Off





Off

Off

Value

Off

Off

Off

Off

Off


(47) These are unused when the transceiver PHY is in CPRI mode.

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Parameter


Enable prbs soft accumulators

Configuration file prefix

Generate SystemVerilog package file

Generate C header file

Generate MIF (Memory Initialization File)

Table 210.


Parameter

Generate parameter documentation file

Value

Off

Off altera_xcvr_native_a10

Off

Off

Off

Value

On

2.9. Other Protocols

2.9.1. Using the "Basic (Enhanced PCS)" and "Basic with KR FEC"

Configurations of Enhanced PCS

You can use Arria 10 transceivers to configure the Enhanced PCS to support other 10G or 10G-like protocols. The Basic (Enhanced PCS) transceiver configuration rule allows access to the Enhanced PCS with full user control over the transceiver interfaces, parameters, and ports.

You can configure the transceivers for Basic functionality using the Native PHY IP

Basic (Enhanced PCS) transceiver configuration rule.

Basic with KR FEC is a KR FEC sublayer support with a low latency physical coding sublayer (PCS). The KR FEC sublayer increases the bit error rate (BER) performance of a link. This mode can run up to a data rate of 25.8 Gbps. Use this configuration to implement applications with low latency or low BER requirements or applications such as 10 Gbps, 40 Gbps or 100 Gbps Ethernet over backplane (10GBASE-KR protocol).

The Forward Error Correction (FEC) function is defined in Clause 74 of IEEE

802.3ap-2007. FEC provides an error detection and correction mechanism that allows noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10 -12 . The

FEC sublayer provides additional link margin by compensating for variations in manufacturing and environmental conditions. To distinguish it from other FEC mechanisms (for example, Optical Transport Network FEC), FEC as defined in Clause

74 of IEEE 802.3ap-2007 is called KR FEC.

Note: This configuration supports the FIFO in phase compensation and register modes, and

KR FEC PCS blocks. You can implement all other required logic for your specific application, such as standard or proprietary protocol multi-channel alignment, either in the FPGA fabric in soft IP or use Intel's 10GBASE-KR PHY IP core product as full solutions in the FPGA.


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Figure 121. Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS)

Configuration

Transmitter PMA Transmitter Enhanced PCS FPGA

Fabric

32

32

32-bit data

PRBS

Generator

PRP

Generator

Parallel Clock (322.265625 MHz) tx_clkout

KR FEC TX G KR FEC Scr

KR FEC Enc

Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout rx_pma_div_clkout

32 32

32-bit data

PRBS

Verifier

Parallel Clock (322.265625 MHz)

KR FEC Block S KR FEC Dec


Parallel Clock

Serial Clock


Notes:

1. Can be enabled or disabled based on the gearbox ratio selected

2. Depends on the value of the clock division factor chosen

3. To use the Scrambler and Descrambler, you must use a 66:32, 66:40, or 66:64 gear ratio and the Block Synchronizer must be enabled

Clock Divider


PRP

Verifier

10GBASE-R

BER Checker

(5156.25 MHz) =

Data rate/2 (2)

ATX PLL fPLL

CMU PLL

Serial Clock

Input Reference Clock rx_clkout

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Figure 122. Transceiver Channel Datapath and Clocking for a Basic with KR FEC

Configuration

Clock frequencies in this figure are examples based on a 10.3125 Gbps data rate.

Transmitter PMA Transmitter Enhanced PCS

64

TX

Data &

Control

64 + 2 tx_hf_clk tx_pma_clk tx_krfec_clk

PRBS

Generator

Parallel Clock (161.13 MHz) (3)

PRP

Generator

156.25 MHz (2)

FPGA

Fabric tx_clkout

KR FEC TX G KR FEC Scr

KR FEC Enc

KR FEC

Receiver PMA Receiver Enhanced PCS tx_pma_div_clkout rx_pma_div_clkout

RX

Data &

Control

64 + 2 rx_rcvd_clk rx_pma_clk

/64

PRBS

Verifier rx_krfec_clk

Parallel Clock (161.13 MHz) (3)

PRP

Verifier

10GBASE-R

BER Checker

156.25 MHz (2) rx_clkout

KR FEC Block S

Parallel Clock

Serial Clock


Notes:

1. Value is based on the clock division factor chosen

2. Value is calculated as data rate on parallel interface/FPGA fabric - PCS interface width

3. Value is calculated as data rate on serial interface/PCS-PMA interface width

KR FEC Dec


KR FEC

Clock Divider

Parallel and Serial Clocks tx_serial_clk0

(5156.25 MHz) =

Data rate/2

ATX PLL fPLL

CMU PLL

Serial Clock

Input Reference Clock

2.9.1.1. How to Implement the Basic (Enhanced PCS) and Basic with KR FEC

Transceiver Configuration Rules in Arria 10 Transceivers

You should be familiar with the Basic (Enhanced PCS) and PMA architecture, PLL architecture, and the reset controller before implementing the Basic (Enhanced PCS) or Basic with KR FEC Transceiver Configuration Rule.

1. Open the IP Catalog and select the Arria 10 Transceiver Native PHY IP.


2. Select Basic (Enhanced PCS) or Basic with KR FEC from the Transceiver

Configuration Rules list located under Datapath Options.

3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for

Basic (Enhanced PCS) and Basic with KR FEC Transceiver Configuration Rules

as a starting point. Or, you can use the protocol presets described in

Transceiver Native

PHY Presets

. You can then modify the settings to meet your specific requirements.



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Figure 123. Signals and Ports of Native PHY IP for Basic (Enhanced PCS) and Basic with

KR FEC Configurations tx_cal_busy rx_cal_busy

NIOS

Hard Calibration IP

Reconfiguration

Registers reconfig_reset reconfig_clk reconfig_avmm tx_serial_data

TX PMA

Serializer

TX Enhanced PCS tx_digital_reset tx_control[17:0] tx_parallel_data[127:0] tx_coreclkin tx_clkout tx_enh_data_valid tx_digital_reset tx_control[17:0] tx_parallel_data[127:0] tx_coreclkin tx_clkout tx_enh_data_valid tx_serial_clk0

(from TX PLL)

Clock

Generation

Block

RX PMA RX Enhanced PCS tx_analog_reset rx_analog_reset

Deserializer rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref

CDR rx_digital_reset rx_clkout rx_coreclkin rx_parallel_data[127:0] rx_control[19:0] rx_digital_reset rx_clkout rx_coreclkin rx_parallel_data[127:0] rx_control[19:0] rx_cdr_refclk0

5. Configure and instantiate the PLL.

6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.

7. Connect the Native PHY IP core to the PLL IP core and the reset controller.

Figure 124. Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design

PLL IP Core

Reset

Controller

Design

Testbench

32-bit data

(32:32 gearbox ratio)

Arria 10 Transceiver

Native PHY

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Figure 125. Connection Guidelines for a Basic with KR FEC Transceiver Design

PLL IP Core

Reset

Controller

Design

Testbench

64d + 2c

Arria 10 Transceiver

Native PHY



•

Arria 10 Enhanced PCS Architecture

on page 461

For more information about Enhanced PCS architecture

•



•


on page 398


•

PLLs on page 349


•


on page 416


•

Enhanced PCS Ports on page 76

For detailed information about the available ports in the Basic protocol.

2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic with KR FEC



Table 211.

General and Datapath Parameters

The first two sections of the Parameter Editor for the Transceiver Native PHY provide a list of general and datapath options to customize the transceiver.

Parameter






Data rate

Range

error, warning

Basic (Enhanced PCS), Basic w/KR FEC

Basic, QPI, GPON

TX / RX Duplex, TX Simplex, RX Simplex

1 to 96

GX transceiver channel: 1 Gbps (

48 )

to 17.4 Gbps continued...


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Parameter



Table 212.


Parameter


PCS TX channel bonding master

Actual PCS TX channel bonding master











Enable rx_serialpbken port

Table 213.


Parameter




Range

GT transceiver channel: 1 Gbps (

48

) to 25.8 Gbps (49)

On / Off

On / Off

Range

Not bonded, PMA only bonding, PMA and PCS bonding

Auto, 0 to n-1, n (where n = the number of data channels)

n-1 (where n = the number of data channels)

1, 2, 4, 8

1, 2, 3, 4

0

On / Off

On / Off

Disabled, 1, 2, 33, 40, 66

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off






Range

1 to 5

0 to 4

For Basic (Enhanced PCS): Depends on the data rate parameter

For Basic with KR FEC: 50 to 800

100, 300, 500, 1000 manual

adaptation enabled, manual, disabled

3, 7

On / Off continued...

(48) Applies when operating in reduced power modes. For standard power modes, the Enhanced

PCS minimum data rate is 1600 Mbps.

(49) The Enhanced PCS must be configured in basic mode to support this data rate range.

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Parameter







Enable rx_serialpbken port


Range

On / Off

Disabled, 1, 2, 33, 40, 66

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

Table 214.

Enhanced PCS Parameters

Enable Enhanced PCS low latency mode

Enable RX/TX FIFO double width mode

TX FIFO mode

Parameter

Enhanced PCS/PMA interface width

FPGA fabric/Enhanced PCS interface width

Range

32, 40, 64

Note: Basic with KR FEC allows 64 only

32, 40, 50, 64, 66, 67

Note: Basic with KR FEC allows 66 only

On / Off

On / Off

Phase compensation, Register, Interlaken, Basic, Fast register

Note: Only Basic Enhanced and Basic Enhanced with

KRFEC are valid.

10, 11, 12, 13, 14, 15

1, 2, 3, 4, 5

On / Off

TX FIFO partially full threshold

TX FIFO partially empty threshold

Enable tx_enh_fifo_full port

Enable tx_enh_fifo_pfull port

Enable tx_enh_fifo_empty port

Enable tx_enh_fifo_pempty port

RX FIFO mode

RX FIFO partially full threshold

On / Off

On / Off

On / Off

Phase Compensation, Register, Basic

0 to 31

RX FIFO partially empty threshold 0 to 31

Enable RX FIFO alignment word deletion (Interlaken) On / Off

Enable RX FIFO control word deletion (Interlaken)

Enable rx_enh_data_valid port

On / Off

On / Off

Enable rx_enh_fifo_full port

Enable rx_enh_fifo_pfull port

Enable rx_enh_fifo_empty port

Enable rx_enh_fifo_pempty port

On / Off

On / Off

On / Off

On / Off continued...


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Range Parameter

Enable rx_enh_fifo_del port (10GBASE-R)

Enable rx_enh_fifo_insert port (10GBASE-R)

Enable rx_enh_fifo_rd_en port (Interlaken)

Enable rx_enh_fifo_align_val port (Interlaken)

Enable rx_enh_fifo_align_cir port (Interlaken)

Enable TX 64b/66b encoder

Enable RX 64b/66b decoder

Enable TX sync header error insertion

Enable RX block synchronizer

Enable rx_enh_blk_lock port

Enable TX data bitslip

Enable TX data polarity inversion

Enable RX data bitslip

Enable RX data polarity inversion

Enable tx_enh_bitslip port


Enable RX KR-FEC error marking

Error marking type

Enable KR-FEC TX error insertion

KR-FEC TX error insertion spacing

Enable tx_enh_frame port

Enable rx_enh_frame port

Enable rx_enh_frame_dian_status port

Table 215.

Dynamic Reconfiguration Parameters

Parameter




Enable embedded debug




Enable prbs soft accumulators




On / Off

On / Off

On / Off

On / Off

On / Off number

On / Off

On / Off text string

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

On / Off

10G, 40G

On / Off

On / Off

On / Off

On / Off

On / Off

Range

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Table 216.

Generate Options Parameters

Parameter

Generate parameter documentation file On / Off

Range



on page 45

2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS

In the Parameter Editor, use the following settings to enable low latency:

1. Select the Enable 'Enhanced PCS' low latency mode option.

2. Select one of the following gear ratios:

Single-width mode: 32:32, 40:40, 64:64, 66:40, 66:64, or 64:32

Double-width mode: 40:40, 64:64, or 66:64

3. Select Phase_compensation in the TX and RX FIFO mode list.

4. If you need the Scrambler and Descrambler features, enable Block Synchronize and use the 66:32, 66:40, or 66:64 gear ratio.

2.9.1.4. Enhanced PCS FIFO Operation

Phase Compensation Mode

Phase compensation mode ensures correct data transfer between the core clock and parallel clock domains. The read and write sides of the TX Core or RX Core FIFO must be driven by the same clock frequency. The depth of the TX or RX FIFO is constant in this mode. Therefore, the TX Core or RX Core FIFO flag status can be ignored. You can tie tx_fifo_wr_en

or rx_data_valid

to 1.

Basic Mode

Basic mode allows you to drive the write and read side of a FIFO with different clock frequencies. tx_coreclkin

or rx_coreclkin

must have a minimum frequency of the lane data rate divided by 66. The frequency range for tx_coreclkin

or rx_coreclkin

is (data rate/32) to (data rate/66). For best results, Intel recommends that tx_coreclkin

or rx_coreclkin the FIFO flag to control write and read operations.

be set to (data rate/32). Monitor

For TX FIFO, assert tx_enh_data_valid

with the tx_fifo_pfull

This can be done with the following example assignment:

signal going low.

assign tx_enh_data_valid = ~tx_fifo_pfull;


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Figure 126. TX FIFO Basic Mode Operation tx_clkout (read side) tx_coreclk (write side) tx_parallel_data[63:0] tx_digitalreset tx_enh_datavalid tx_fifo_pempty tx_fifo_full tx_fifo_pfull

64’d0 64’d1 64’d2 64’d3 64’d4 64’d5 64’d6 64’d7 64’d8 64’d9 64’ha

For RX FIFO, assert rx_enh_read_en

with the rx_fifo_pempty

This can be done with the following example assignment:

signal going low.

assign rx_enh_read_en = ~rx_fifo_pempty;

Figure 127. RX FIFO Basic Mode Operation rx_clkout (write side) rx_coreclkin (read side) rx_parallel_data[63:0] rx_digitalreset rx_enh_read_en rx_fifo_pfull rx_fifo_empty rx_fifo_pempty

64’d0 64’d1 64’d2 64’d3 64’d4 64’d5 64’d6 64’d7 64’d8 64’d9 64’ha

If you are using even gear ratios, the rx_enh_data_valid

signal is always high. For uneven gear ratios, rx_enh_data_valid

toggles. RX parallel data is valid when rx_enh_data_valid

is high. Discard invalid RX parallel data when the rx_enh_datavalid

signal is low.

Register and Fast Register Mode

This FIFO mode is used for protocols, which require deterministic latency. You can tie tx_fifo_wr_en

to 1.

2.9.1.5. TX Data Bitslip

The bit slip feature in the TX gearbox allows you to slip the transmitter bits before they are sent to the serializer.

The value specified on the TX bit slip bus indicates the number of bit slips. The minimum slip is one UI. The maximum number of bits slipped is equal to the FPGA fabric-to-transceiver interface width minus 1. For example, if the FPGA fabric-totransceiver interface width is 64 bits, the bit slip logic can slip a maximum of 63 bits.

Each channel has 6 bits to determine the number of bits to slip. The TX bit slip bus is a level-sensitive port, so the TX serial data is bit slipped statically by TX bit slip port

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assignments. Each TX channel has its own TX bit slip assignment and the bit slip amount is relative to the other TX channels. You can improve lane-to-lane skew by assigning TX bit slip ports with proper values.

The following figure shows the effect of slipping tx_serial_data[0]

by one UI to reduce the skew with tx_serial_data[1]

. After the bit slip, tx_serial_data[0] and tx_serial_data[1]

are aligned.

Figure 128. TX Bit Slip tx_serial_clock tx_enh_bitslip[0] 0000000 tx_serial_data[0] (Before) tx_enh_bitslip[0] 0000001 tx_serial_data[0] (After) tx_serial_data[1]

1 UI

2.9.1.6. TX Data Polarity Inversion

Use the TX data polarity inversion feature to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout. To enable TX data polarity inversion, select the Enable TX data polarity inversion option in the Gearbox section of Platform Designer (Standard). It can also be dynamically controlled with dynamic reconfiguration.

2.9.1.7. RX Data Bitslip

The RX data bit slip in the RX gearbox allows you to slip the recovered data. An asynchronous active high edge on the rx_bitslip

port changes the word boundary, shifting rx_parallel_data

one bit at a time. Use the rx_bitslip

port with its own word aligning logic. Assert the rx_bitslip

signal for at least two parallel clock cycles to allow synchronization. You can verify the word alignment by monitoring rx_parallel_data

. Using the RX data bit slip feature is optional.

Figure 129. RX Bit Slip rx_clkout rx_bitslip rx_parallel_data[63:0] 64’d0 64’d1

2.9.1.8. RX Data Polarity Inversion

Use the RX data polarity inversion feature to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout. To enable RX data polarity inversion, select the Enable RX data polarity inversion option in the Gearbox section of Platform Designer (Standard). It can also be dynamically controlled with dynamic reconfiguration.


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2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match

Configurations of Standard PCS

Use one of the following transceiver configuration rules to implement protocols such as

SONET/SDH, SDI/HD, SATA, or your own custom protocol:

• Basic protocol

• Basic protocol with low latency enabled

• Basic with rate match protocol

Figure 130. Transceiver Channel Datapath and Clocking for the Basic and Basic with Rate

Match Configurations

The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.


Fabric

10

16

625 MHz (2)

Receiver PMA

125 MHz (1) tx_clkout tx_pma_div_clkout

PRBS

Generator

/2 tx_coreclkin


62.5 MHz (1) tx_clkout

10

16

Parallel Clock

(Recovered)

125 MHz (1)

Parallel Clock

(From Clock


PRBS

Verifier

/2 rx_coreclkin

62.5 MHz (1) rx_clkout or tx_clkout rx_pma_div_clkout


Clock Divider

ATX PLL

CMU PLL fPLL

Parallel Clock

Serial Clock

Parallel and Serial Clock

Notes:

1. The parallel clock (tx_clkout or rx_clkout) is calculated as data rate/PCS-PMA interface width =1250/10 = 125 MHz.

When the Byte Serializer is set to Serialize x2 mode, tx_clkout and rx_clkout become 1250/20 = 62.5 MHz.

2. The serial clock is calculated as data rate/2. The PMA runs on a dual data rate clock.

3. This block is only enabled when using the Basic with Rate Match transceiver configuration rule.


Serial Clock

In low latency modes, the transmitter and receiver FIFOs are always enabled.

Depending on the targeted data rate, you can optionally bypass the byte serializer and deserializer blocks.

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Figure 131. Transceiver Channel Datapath and Clocking for Basic Configuration with Low

Latency Enabled

The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.


Fabric

10

16

625 MHz (2)

125 MHz (1) tx_clkout tx_pma_div_clkout

PRBS

Generator

/2 tx_coreclkin


62.5 MHz (1) tx_clkout

Receiver PMA

10

16

Parallel Clock

(Recovered)

125 MHz (1)

Parallel Clock

(From Clock


PRBS

Verifier

/2 rx_coreclkin

62.5 MHz (1) rx_clkout or tx_clkout rx_pma_div_clkout


Clock Divider

ATX PLL

CMU PLL fPLL

Parallel Clock

Serial Clock


Notes:

1. The parallel clock (tx_clkout or rx_clkout) is calculated as data rate/PCS-PMA interface width = 1250/10 = 125 MHz.

When the Byte Serializer is set to Serialize x2 mode, tx_clkout and rx_clkout become 1250/20 = 62.5 MHz.

2. The serial clock is calculated as data rate/2. The PMA runs on a dual data rate clock.


Serial Clock

In low latency modes, the transmitter and receiver FIFOs are always enabled.

Depending on the targeted data rate, you can optionally bypass the byte serializer and deserializer blocks.



on page 479

2.9.2.1. Word Aligner Manual Mode

To use this mode:

1. Set the RX word aligner mode to Manual (FPGA Fabric controlled).

2. Set the RX word aligner pattern length option according to the PCS-PMA interface width.

3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.

This mode adds rx_patterndetect

and rx_syncstatus

Enable rx_std_wa_patternalign port option to enable

. You can select the rx_std_wa_patternalign

. An active high on rx_std_wa_patternalign

re-aligns the word aligner one time.


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Note: • rx_patterndetect

is asserted whenever there is a pattern match.

• rx_syncstatus

is asserted after the word aligner achieves synchronization.

• rx_std_wa_patternalign

is asserted to re-align and resynchronize.

• If there is more than one channel in the design, rx_patterndetect

, rx_syncstatus

and rx_std_wa_patternalign

become buses in which each bit corresponds to one channel.

You can verify this feature by monitoring rx_parallel_data

.

The following timing diagrams demonstrate how to use the ports and show the relationship between the various control and status signals. In the top waveform, rx_parallel_data

is initially misaligned. After asserting the rx_std_wa_patternalign

signal, it becomes aligned. The bottom waveform shows the behavior of the rx_syncstatus

signal when rx_parallel_data

is already aligned.

Figure 132. Manual Mode when the PCS-PMA Interface Width is 8 Bits tx_parallel_data

= 8'hBC and the word aligner pattern = 8'hBC rx_std_wa_patternalign tx_parallel_data bc

00 bc rx_parallel_data rx_patterndetect rx_syncstatus rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus bc bc

In manual alignment mode, the word alignment operation is manually controlled with the rx_std_wa_patternalign

input signal or the rx_enapatternalign

register.

The word aligner operation is level-sensitive to rx_enapatternalign

. The word aligner asserts the rx_syncstatus

signal for one parallel clock cycle whenever it realigns to the new word boundary.

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= 10'h3BC and the word aligner pattern = 10'h3BC rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus

3bc

000 3bc rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus

3bc

3bc


= 16'hF3BC and the word aligner pattern = 16'hF3BC rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus f3bc

0000

00

00 f3bc

01

11 11 rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus f3bc f3bc

01

11 00 11


= 20'hFC3BC and the word aligner pattern = 20'hFC3BC rx_std_wa_patternalign tx_parallel_data fc3bc rx_parallel_data rx_patterndetect rx_syncstatus

0000

00

00 fc3bc

01

11 11 11 rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus fc3bc fc3bc

01

11 00 11

2.9.2.2. Word Aligner Synchronous State Machine Mode

To use this mode:

• Select the Enable TX 8B/10B encoder option.

• Select the Enable RX 8B/10B decoder option.


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Note:

The 8B/10B encoder and decoder add the following additional ports:

• tx_datak

• rx_datak

• rx_errdetect

• rx_disperr

• rx_runningdisp

1. Set the RX word aligner mode to synchronous state machine.

2. Set the RX word aligner pattern length option according to the PCS-PMA interface width.

3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.

The RX word aligner pattern is the 8B/10B encoded version of the data pattern. You can also specify the number of word alignment patterns to achieve synchronization, the number of invalid data words to lose synchronization, and the number of valid data words to decrement error count. This mode adds two additional ports: rx_patterndetect

and rx_syncstatus

.

• rx_patterndetect

is asserted whenever there is a pattern match.

• rx_syncstatus

is asserted after the word aligner achieves synchronization.

• rx_std_wa_patternalign

is asserted to re-align and re-synchronize.

• If there is more than one channel in the design, tx_datak

, rx_datak

, rx_errdetect

, rx_disperr

, rx_runningdisp

, rx_patterndetect

, and rx_syncstatus

become buses in which each bit corresponds to one channel.


.

Figure 136. Synchronization State Machine Mode when the PCS-PMA Interface Width is

20 Bits rx_std_wa_patternalign tx_datak tx_parallel_data rx_parallel_data rx_datak rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus

11

00

00

11

00

00

11 bc02

0000 02bc

01

00

00

11

01

00 11 00

11

11 00 11

2.9.2.3. RX Bit Slip

To use the RX bit slip, select Enable rx_bitslip port and set the word aligner mode to

bit slip. This adds rx_bitslip

as an input control port. An active high edge on rx_bitslip

slips one bit at a time. When rx_bitslip

is toggled, the word aligner slips one bit at a time on every active high edge. Assert the rx_bitslip

signal for at least two parallel clock cycles to allow synchronization. You can verify this feature by monitoring rx_parallel_data

.

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The RX bit slip feature is optional and may or may not be enabled.

Figure 137. RX Bit Slip in 8-bit Mode tx_parallel_data

= 8'hbc rx_std_bitslipboundarysel rx_bitslip

01111 tx_parallel_data rx_parallel_data bc

00 97 cb e5 f2 79


= 10'h3bc rx_std_bitslipboundarysel 01111 rx_bitslip tx_parallel_data rx_parallel_data

3bc

000 1de 0ef 277 33b 39d 3ce 1e7 2f3


= 16'hfcbc

00010 rx_std_bitslipboundarysel rx_bitslip

00001 tx_parallel_data rx_parallel_data fcbc

979f cbcf

00011 e5e7

00100 f2f3

00101 f979

00110 fcbc

379 bc

3bc


= 20'h3fcbc rx_std_bitslipboundarysel rx_bitslip

00001 00010 tx_parallel_data rx_parallel_data

3fcbc e5e1f f2f0f

00011 f9787

00100 fcbc3

00101 de5e1

00110 ff2f0

00111

7f978

01000

3fcbc

2.9.2.4. RX Polarity Inversion

Receiver polarity inversion can be enabled in low latency, basic, and basic rate match modes.

To enable the RX polarity inversion feature, select the Enable RX polarity inversion and Enable rx_polinv port options.

This mode adds rx_polinv

. If there is more than one channel in the design, rx_polinv

is a bus in which each bit corresponds to a channel. As long as rx_polinv

is asserted, the RX data received has a reverse polarity.


.


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Figure 141. RX Polarity Inversion rx_polinv tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus

11111100001110111100

11111100001...

01

00000011110001000011

11

11111100001110111100

2.9.2.5. RX Bit Reversal

The RX bit reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode, bit slip, manual, or synchronous state machine.

To enable this feature, select the Enable RX bit reversal and Enable

rx_std_bitrev_ena port options. This adds rx_std_bitrev_ena

. If there is more than one channel in the design, rx_std_bitrev_ena

becomes a bus in which each bit corresponds to a channel. As long as rx_std_bitrev_ena

is asserted, the RX data received by the core shows bit reversal.


.

Figure 142. RX Bit Reversal rx_std_bitrev_ena tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus

11111100001110111100

11111100001110111100

01

11

00111101110000111111

00

11111100001110111100

01

2.9.2.6. RX Byte Reversal

The RX byte reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode.

To enable this feature, select the Enable RX byte reversal and Enable

rx_std_byterev_ena port options. This adds rx_std_byterev_ena

. If there is more than one channel in the design, rx_std_byterev_ena

becomes a bus in which each bit corresponds to a channel. As long as rx_std_byterev_ena

RX data received by the core shows byte reversal.

is asserted, the


.

Figure 143. RX Byte Reversal rx_std_byterev_ena tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus

01

11

11111100001110111100

111111...

11101111001111110000

10

11111100001110111100

01

2.9.2.7. Rate Match FIFO in Basic (Single Width) Mode

Only the rate match FIFO operation is covered in these steps.

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1. Select basic (single width) in the RX rate match FIFO mode list.

2. Enter values for the following parameters.

Parameter

RX rate match insert/delete +ve pattern (hex)

RX rate match insert/delete –ve pattern (hex)

Value

20 bits of data specified as a hexadecimal string


Description

The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity.


ve (volt encodes) are NRZ_L conditions where +ve encodes 0 and –ve encodes 1.

ve is a running disparity (+/–RD) specifically used with the rate matcher.

Depending on the ppm difference (which is defined by protocol) between the recovered clock and the local clock, the rate matcher adds or deletes a maximum of four skip patterns (neutral disparity). The net neutrality is conserved even after the skip word insertion or deletion because the control words alternate between positive and negative disparity.

In the following figure, the first skip cluster has a /K28.5/ control pattern followed by two /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control pattern followed by four /K28.0/ skip patterns. The rate match FIFO deletes only one /K28.0/ skip pattern from the first skip cluster to maintain at least one skip pattern in the cluster after deletion. Two /K28.0/ skip patterns are deleted from the second cluster for a total of three skip patterns deletion requirement.

The rate match FIFO can insert a maximum of four skip patterns in a cluster, if there are no more than five skip patterns in the cluster after insertion.

Figure 144. Rate Match FIFO Deletion with Three Skip Patterns Required for Deletion

First Skip Cluster Second Skip Cluster

K28.0

K28.0

tx_parallel_data rx_parallel_data

K28.5

K28.5

K28.0

K28.0

K28.0

K28.5

K28.5

K28.0

K28.0

K28.0

K28.0

K28.0

Three Skip Patterns Deleted

Note: /K28.5/ is the control pattern and /K28.0/ is the skip pattern

In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a /K28.5/ control pattern followed by three /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control pattern followed by two /K28.0/ skip patterns. The rate match FIFO inserts only two /

K28.0/ skip patterns into the first skip cluster to maintain a maximum of five skip patterns in the cluster after insertion. One /K28.0/ skip pattern is inserted into the second cluster for a total of three skip patterns to meet the insertion requirement.

Figure 145. Rate Match FIFO Insertion with Three Skip Patterns Required for Insertion

First Skip Cluster Second Skip Cluster tx_parallel_data K28.5

K28.0

K28.0

K28.0

K28.5

K28.0

K28.0

Dx.y

rx_parallel_data K28.5

K28.0

K28.0

K28.0

K28.0

K28.0

K28.5

K28.0

K28.0

K28.0

Dx.y

Three Skip Patterns Inserted


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The following figure shows the deletion of D5 when the upstream transmitter reference clock frequency is greater than the local receiver reference clock frequency. It asserts deletion takes place.

rx_std_rmfifo_full

for one parallel clock cycle while the

Figure 146. Rate Match FIFO Becoming Full After Receiving D5 tx_parallel_data D1 D2 D3 D4 D5 D6 rx_parallel_data D1 D2 D3 D4 D6 D7

D7

D8

D8 xx xx xx rx_std_rmfifo_full

The following figure shows the insertion of skip symbols when the local receiver reference clock frequency is greater than the upstream transmitter reference clock frequency. It asserts rx_std_rmfifo_empty

for one parallel clock cycle while the insertion takes place.

Figure 147. Rate Match FIFO Becoming Empty After Receiving D3 tx_parallel_data D1 D2 D3 D4 D5 D6 rx_parallel_data D1 D2 D3 /K30.7/ D4 D5 rx_std_rmfifo_empty

2.9.2.8. Rate Match FIFO Basic (Double Width) Mode

1. Select basic (double width) in the RX rate match FIFO mode list.

2. Enter values for the following parameters.

Parameter


RX rate match insert/delete -ve pattern (hex)

Value



Description



The rate match FIFO can delete as many pairs of skip patterns from a cluster as necessary to avoid the rate match FIFO from overflowing. The rate match FIFO can delete a pair of skip patterns only if the two 10-bit skip patterns appear in the same clock cycle on the LSByte and MSByte of the 20-bit word. If the two skip patterns appear straddled on the MSByte of a clock cycle and the LSByte of the next clock cycle, the rate match FIFO cannot delete the pair of skip patterns.

In the following figure, the first skip cluster has a /K28.5/ control pattern in the

LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle followed by one /

K28.0/ skip pattern in the LSByte of the next clock cycle. The rate match FIFO cannot delete the two skip patterns in this skip cluster because they do not appear in the same clock cycle. The second skip cluster has a /K28.5/ control pattern in the MSByte of a clock cycle followed by two pairs of /K28.0/ skip patterns in the next two cycles. The rate match FIFO deletes both pairs of /K28.0/ skip patterns

(for a total of four skip patterns deleted) from the second skip cluster to meet the three skip pattern deletion requirement.

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The rate match FIFO can insert as many pairs of skip patterns into a cluster necessary to avoid the rate match FIFO from under running. The 10-bit skip pattern can appear on the MSByte, the LSByte, or both, of the 20-bit word.

Figure 148. Rate Match FIFO Deletion with Four Skip Patterns Required for Deletion

/K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern.

First Skip Cluster Second Skip Cluster

Two Pairs of Skip

Patterns Deleted tx_parallel_data[19:10] tx_parallel_data[9:0] rx_parallel_data[19:0]

Dx.y

Dx.y

Dx.y

K28.0

K28.5

K28.0

Dx.y

K28.0

Dx.y

K28.5

Dx.y

K28.5

K28.0

K28.0

Dx.y

K28.0

K28.0

Dx.y

Dx.y

rx_parallel_data[9:0] Dx.y

K28.5

K28.0

Dx.y

Dx.y

In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a /K28.5/ control pattern in the

LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle. The rate match

FIFO inserts pairs of skip patterns in this skip cluster to meet the three skip pattern insertion requirement.

Figure 149. Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion

First Skip Cluster Second Skip Cluster tx_parallel_data[19:10] tx_parallel_data[9:0] rx_parallel_data[19:0] rx_parallel_data[9:0]

Dx.y

Dx.y

Dx.y

Dx.y

K28.0

K28.5

K28.0

K28.5

Dx.y

Dx.y

K28.0

K28.0

K28.5

Dx.y

K28.0

K28.0

K28.0

K28.0

Dx.y

Dx.y

K28.0

K28.0

K28.5

Dx.y

K28.0

K28.0

K28.0

K28.0

The following figure shows the deletion of the 20-bit word D7D8.

Figure 150. Rate Match FIFO Becoming Full After Receiving the 20-Bit Word D5D6 tx_parallel_data[19:0] D2 D4 D6 D8 D10 D12 tx_parallel_data[9:0] D1 D3 D5 D7 D9 D11 rx_parallel_data[19:10] rx_parallel_data[9:0]

D2

D1

D4

D3

D6

D5

D10

D9

D12

D11 xx xx rx_std_rmfifo_full

The following figure shows the insertion of two skip symbols.


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Figure 151. Rate Match FIFO Becoming Empty After Reading out the 20-Bit Word D5D6 tx_parallel_data[19:0] D2 D4 D6

D8 D10

D12 tx_parallel_data[9:0] D1 D3 D5

D7

D9 D11 rx_parallel_data[19:10] rx_parallel_data[9:0]

D2

D1

D4

D3

D6

D5

/K30.7/

/K30.7/

D8

D7

D10

D9 rx_std_rmfifo_empty

2.9.2.9. 8B/10B Encoder and Decoder

To enable the 8B/10B Encoder and the 8B/10B Decoder, select the Enable TX

8B/10B Encoder and Enable RX 8B/10B Decoder options on the Standard PCS tab in the IP Editor. Platform Designer (Standard) allows implementing the 8B/10B decoder in RX-only mode.

The following ports are added:

• tx_datak

• rx_datak

• rx_runningdisp

• rx_disperr

• rx_errdetect rx_datak

and tx_datak

indicate whether the parallel data is a control word or a data word. The incoming 8-bit data ( tx_parallel_data

) and the control identifier

( tx_datak

) are converted into a 10-bit data. After a power on reset, the 8B/10B encoder takes the 10-bit data from the RD- column. Next, the encoder chooses the

10-bit data from the RD+ column to maintain neutral disparity. The running disparity is shown by rx_runningdisp

.

2.9.2.10. 8B/10B TX Disparity Control

The Disparity Control feature controls the running disparity of the output from the

8B/10B Decoder.

To enable TX Disparity Control, select the Enable TX 8B/10B Disparity Control option. The following ports are added:

• tx_forcedisp be forced or not

—a control signal that indicates whether a disparity value has to

• tx_dispval being forced

—a signal that indicates the value of the running disparity that is

When the number of data channels is more than 1, tx_forcedisp

and tx_dispval are shown as buses in which each bit corresponds to one channel.

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The following figure shows the current running disparity being altered in Basic singlewidth mode by forcing a positive disparity /K28.5/ when it was supposed to be a negative disparity /K28.5/. In this example, a series of /K28.5/ code groups are continuously being sent. The stream alternates between a positive running disparity

(RD+) /K28.5/ and a negative running disparity (RD-) /K28.5/ to maintain a neutral overall disparity. The current running disparity at time n + 3 indicates that the /K28.5/ in time n + 4 should be encoded with a negative disparity. Because tx_forcedisp

is high at time n + 4, and tx_dispval positive disparity code group.

is low, the /K28.5/ at time n + 4 is encoded as a

Figure 152. 8B/10B TX Disparity Control n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 clock tx_in[7:0] tx_ctrlenable tx_forcedisp tx_dispval

Current Running Disparity dataout[9:0]

BC

RD–

17C

BC

RD+

283

BC

RD–

17C

BC

RD+

283

BC

RD+

283

BC

RD–

17C

BC

RD+

283

BC

RD–

17C

2.9.2.11. How to Enable Low Latency in Basic

In the Arria 10 Transceiver Native PHY IP Parameter Editor, use the following settings to enable low latency:

1. Select the Enable 'Standard PCS' low latency mode option.

2. Select either low_latency or register FIFO in the TX FIFO mode list.

3. Select either low_latency or register FIFO in the RX FIFO mode list.

4. Select either Disabled or Serialize x2 in the TX byte serializer mode list.

5. Select either Disabled or Serialize x2 in the RX byte deserializer mode list.

6. Ensure that RX rate match FIFO mode is disabled.

7. Set the RX word aligner mode to bitslip.

8. Set the RX word aligner pattern length to 7 or 16.

Note: TX bitslip, RX bitslip, bit reversal, and polarity inversion modes are supported.

2.9.2.12. TX Bit Slip

To use the TX bit slip, select the Enable TX bitslip and Enable

tx_std_bitslipboundarysel port options. This adds the tx_std_bitslipboundarysel

input port. The TX PCS automatically slips the number of bits specified by tx_std_bitslipboundarysel bit slip. If there is more than one channel in the design,

. There is no port for TX tx_std_bitslipboundarysel

ports are multiplied by the number of channels. You can verify this feature by monitoring the tx_parallel_data

port.

Enabling the TX bit slip feature is optional.


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Note: The rx_parallel_data

values in the following figures are based on the TX and RX bit reversal features being disabled.

Figure 153. TX Bit Slip in 8-bit Mode tx_parallel_data

= 8'hbc. tx_std_bitslipboundarysel

= 5'b00001 (bit slip by 1 bit).

tx_std_bitslipboundarysel tx_parallel_data rx_parallel_data

00001 bc

79


= 10'h3bc. tx_std_bitslipboundarysel

= 5'b00011 (bit slip by 3 bits).


00011

3bc

1e7


= 16'hfcbc. tx_std_bitslipboundarysel

=5'b00011 (bit slip by 3 bits).


00011 fcbc

5e7f


= 20'hF3CBC. tx_std_bitslipboundarysel

= 5'b00111 (bit slip by 7 bits).


00111 f3cbc e5e1f

2.9.2.13. TX Polarity Inversion

The positive and negative signals of a serial differential link might accidentally be swapped during board layout. Solutions such as a board respin or major updates to the PLD logic can be expensive. The transmitter polarity inversion feature is provided to correct this situation.

Transmitter polarity inversion can be enabled in low latency, basic, and basic rate match modes.

To enable TX polarity inversion, select the Enable tx_polinv port option in Platform

Designer (Standard). It can also be dynamically controlled with dynamic reconfiguration.

This mode adds tx_polinv

. If there is more than one channel in the design, tx_polinv

is a bus with each bit corresponding to a channel. As long as tx_polinv is asserted, the TX data transmitted has a reverse polarity.

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2.9.2.14. TX Bit Reversal

The TX bit reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode. This feature is parameter-based, and creates no additional ports. If there is more than one channel in the design, all channels have TX bit reversal.

To enable TX bit reversal, select the Enable TX bit reversal option in Platform


Figure 157. TX Bit Reversal tx_parallel_data rx_parallel_data

11111100001110111100

00000...

00111101110000111111

2.9.2.15. TX Byte Reversal

The TX byte reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode. This feature is parameterbased, and creates no additional ports. If there is more than one channel in the design, all channels have TX byte reversal.

To enable TX byte reversal, select the Enable TX byte reversal option in Platform


Figure 158. TX Byte Reversal tx_parallel_data rx_parallel_data

11111100001110111100

00000000... 11101111001111110000

2.9.2.16. How to Implement the Basic, Basic with Rate Match Transceiver

Configuration Rules in Arria 10 Transceivers

You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing your Basic protocol IP.

1. Open the IP Catalog and select the Native PHY IP.

Refer to Select and Instantiate the PHY IP Core on page 33.

2. Select Basic/Custom (Standard PCS) or Basic/Custom w/Rate Match

(Standard PCS) from the Transceiver configuration rules list located under

Datapath Options depending on which configuration you want to use.

3. Use the parameter values in the tables in Transceiver Native PHY IP Parameter

Settings for the Basic Protocol

as a starting point. Or, you can use the protocol

presets described in Transceiver Native PHY Presets

. You can then modify the setting to meet your specific requirements.



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Figure 159. Signals and Ports of Native PHY IP for Basic, Basic with Rate Match

Configurations

Arria 10 Transceiver Native PHY

Reconfiguration

Registers

Nios Hard

Calibration IP tx_cal_busy rx_cal_busy reconfig_reset reconfig_clk reconfig_avmm tx_digital_reset tx_datak tx_parallel_data[7:0] tx_clkout

TX Standard PCS tx_datak tx_parallel_data[7:0] tx_coreclkin tx_clkout unused_tx_parallel_data[118:0]

10

TX PMA

Serializer tx_serial_data

Central/Local

Clock Divider tx_serial_clk0 (from TX PLL) tx_analog_reset rx_analog_reset rx_digital_reset rx_datak rx_parallel_data[7:0] rx_clkout rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus rx_rmfifostatus (1)

RX Standard PCS rx_datak rx_parallel_data[7:0] rx_clkout rx_coreclkin rx_errdetect rx_disperr rx_runningdisp rx_patterndetect rx_syncstatus rx_rmfifostatus (1) unused_rx_parallel_data[113:0]

10

RX PMA

Deserializer CDR rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref

Note:

1. Only applies when using the Basic with Rate Match transceiver configuration rule.


6. Create a transceiver reset controller.

7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the

information in Transceiver Native PHY Ports for the Protocol

to connect the ports.

Figure 160. Connection Guidelines for a Basic/Custom Design pll_ref_clk reset

Pattern

Generator tx_parallel_data tx_datak tx_clkout tx_serial_data rx_serial_data rx_cdr_refclk

PLL IP tx_serial_clk pll_locked pll_powerdown rx_ready tx_ready clk reset reset

Reset

Controller

Pattern

Checker tx_digital_reset tx_analog_reset rx_digital_reset rx_analog_reset rx_is_lockedtoref rx_is_lockedtodata rx_parallel_data rx_datak rx_clkout

Arria 10

Transceiver

Native

PHY reconfig_clk reconfig_reset reconfig_write reconfig_read reconfig_address reconfig_writedata reconfig_readdata reconfig_waitrequest cal_busy

For

Reconfiguration


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•


on page 479

For more information about Standard PCS architecture

•



•


on page 398


•

PLLs on page 349


•


on page 416


•

Standard PCS Ports on page 86

Port definitions for the Transceiver Native PHY Standard Datapath

2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match

Configurations



Table 217.

General and Datapath Options Parameters

Parameter






Data rate



Range error warning

Basic/Custom (Standard PCS)

Basic/Custom w/Rate Match (Standard

PCS) basic

TX/RX Duplex

TX Simplex

RX Simplex

1

to

96

611

Mbps to

12

Gbps

On/Off

On/Off

Table 218.


Parameter


PCS TX channel bonding master

Actual PCS TX channel bonding master

Range

Not bonded

PMA-only bonding

PMA and PCS bonding

Auto, n-1 (where n = the number of data channels)

n-1 (where n = the number of data channels) continued...


315

Parameter












Table 219.


Parameter


















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Range

1, 2, 4, 8

1, 2, 3, 4

0 (Depends on the Number of TX PLL clock

inputs per channel value)

On/Off

On/Off

Disabled, 1, 2, 33, 40, 66

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

Range

1, 2, 3, 4, 5

0, 1, 2, 3, 4

Legal range defined by Quartus Prime software

100, 300, 500, 1000 manual disabled

3, 7

On/Off

On/Off

Disabled, 1, 2, 33, 40, 50, 66

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

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Table 220.

Standard PCS Parameters

Parameter

Standard PCS / PMA interface width

FPGA fabric / Standard TX PCS interface width

FPGA fabric / Standard RX PCS interface width

Enable 'Standard PCS' low latency mode

TX FIFO mode

RX FIFO Mode

Enable tx_std_pcfifo_full port

Enable tx_std_pcfifo_empty port

Enable rx_std_pcfifo_full port

Enable rx_std_pcfifo_empty port

TX byte serializer mode

RX byte deserializer mode

Enable TX 8B/10B encoder

Enable TX 8B/10B disparity control

Enable RX 8B/10B decoder

RX rate match FIFO mode

RX rate match insert/delete -ve pattern (hex)


Enable rx_std_rmfifo_full port

Enable rx_std_rmfifo_empty port

PCI Express* Gen 3 rate match FIFO mode

Enable TX bit slip

Enable tx_std_bitslipboundarysel port

RX word aligner mode

RX word aligner pattern length

RX word aligner pattern (hex)

Number of word alignment patterns to achieve sync

Range

8, 10, 16, 20

8, 10, 16, 20, 32, 40

8, 10, 16, 20, 32, 40

On/Off

Off (for Basic with Rate Match) low_latency register_fifo fast_register low_latency register_fifo

On/Off

On/Off

On/Off

On/Off

Disabled

Serialize x2

Serialize x4

Disabled

Deserialize x2

Deserialize x4

On/Off

On/Off

On/Off

Disabled

Basic 10-bit PMA (for Basic with Rate Match)

Basic 20-bit PMA (for Basic with Rate Match)

User-defined value

User-defined value

On/Off

On/Off

Bypass

On/Off

On/Off bitslip manual (PLD controlled) synchronous state machine

7, 8, 10, 16, 20, 32, 40

User-defined value

0-255 continued...


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Parameter

Number of invalid data words to lose sync

Number of valid data words to decrement error count

Enable fast sync status reporting for deterministic latency SM

Enable rx_std_wa_patternalign port

Enable rx_std_wa_a1a2size port

Enable rx_std_bitslipboundarysel port


Enable TX bit reversal

Enable TX byte reversal

Enable TX polarity inversion

Enable tx_polinv port

Enable RX bit reversal

Enable rx_std_bitrev_ena port

Enable RX byte reversal

Enable rx_std_byterev_ena port

Enable RX polarity inversion

Enable rx_polinv port

Enable rx_std_signaldetect port

Enable PCIe dynamic datarate switch ports

Enable PCIe pipe_hclk_in and pipe_hclk_out ports

Enable PCIe Gen 3 analog control ports

Enable PCIe electrical idle control and status ports

Enable PCIe pipe_rx_polarity port

Table 221.

Dynamic Reconfiguration Parameters

Parameter




Range

On/Off

On/Off

On/Off

Table 222.

Generation Options Parameters

Parameter




on page 45

Range

On/Off

Off

Off

Off

Off

Off

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

Range

0-63

0-255

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

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2.9.3. Design Considerations for Implementing Arria 10 GT Channels

This section provides information on using the Arria 10 GT transceiver channels .

GT channels can be used in Enhanced PCS basic mode and PCS-Direct configuration to support 25.8 Gbps. When GT channels are used in PCS-Direct configuration, the PCS blocks are bypassed. The serializer/deserializer in GT channels supports 64 bit and

128 bit serialization factors.

2.9.3.1. Transceiver PHY IP

Arria 10 GT transceiver channels are implemented using the Native PHY IP with the

Basic (Enhanced PCS) transceiver configuration rule.

• To support 25.8 Gbps, the Enhanced PCS must be configured in basic mode with the low latency check box unselected. To configure the Enhanced PCS, do not enable any functional blocks in the Enhanced PCS (that is, disable Block

Synchronizer, Gearbox, Scrambler, and Encoder).

• You can also use the PCS-Direct mode for 25.8 Gbps.

You can bundle several GT transceiver channels with one Native PHY IP instantiation, but you must instantiate a separate ATX PLL IP for every ATX PLL used.

2.9.3.2. PLL and GT Transceiver Channel Clock Lines

The ATX PLL is used to provide the clock source for the GT transceiver channels. Each

ATX PLL has two dedicated GT clock lines which connect the PLL directly to the GT transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and

4, and the bottom ATX PLL drives channels 0 and 1. These connections bypass the rest of the clock network for higher performance.


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Figure 161. GT Channel Configuration

Ch 5

CGB

CDR

Ch 4

CGB

ATX PLL1

CMU or CDR

Ch 3

CGB

CDR

Ch 2

CGB

CDR

Ch 1

CGB

ATX PLL0

CMU or CDR

Ch 0

CGB

CDR

When both the channels 0 and 1 are configured as GT channels, they are driven by the same ATX PLL and have to be configured to run at the same data rates. This is also true for channels 3 and 4 when they are configured as GT channels.

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Note: • GT channel bonding is not supported.

• For optimum performance of GT channel, the reference clock of ATX PLL is recommended to be from a dedicated reference clock pin in the same bank.


Input Reference Clock Sources on page 372

2.9.3.3. Reset Controller

Each GT channel instantiated has independent analog and digital reset ports. Refer to the Resetting Transceiver Channels chapter for more details on designing a reset controller to reset these ports.



on page 416


2.9.3.4. How to Implement Designs for Data Rates Above 17.4 Gbps Using

Enhanced PCS in Low Latency Mode

• You should be familiar with the Enhanced PCS and PMA architecture, PLL architecture, and the reset controller.

• Make sure you have selected an Arria 10 GT device for the project

1. Select Tools

➤

IP Catalog

➤

Interface Protocols

➤

Transceiver PHY

➤

Arria

10 Transceiver Native PHY. Refer to Select and Instantiate the PHY IP Core on

page 33 for detailed steps.

2. Set VCCR_GXB and VCCT_GXB to 1.1V. Note these settings are overridden by the QSF file settings which should also be set to 1.1V. QII makes sure the actual voltage prescribed is in line with pin connection guidelines and the Arria10 Data

Sheet.

3. Select Basic (Enhanced PCS) from the Transceiver configuration rules list located under Datapath Options.

4. Use the parameter values in the tables in Transceiver Native PHY IP Parameters

Settings for Basic (Enhanced PCS) and Basic with KR FEC for each input of the

Arria 10 Transceiver Native PHY Parameter Editor as a starting point. Or, you can

use the protocol presets described in Transceiver Native PHY Presets

. You can then modify the settings to meet your specific requirements.

• Ensure that the data rate is set to 25781.25 Mbps. To achieve the higher data rates, use Enhanced PCS basic mode with the low latency option unchecked.

Select a CDR reference clock to match your data rate. Use Phase compensation FIFO modes.

• Make sure DFE is disabled from Rx PMA settings.

• Set the Enhanced PCS / PMA interface width to 64 bits.

• Set the FPGA fabric / Enhanced PCS interface width to 64 bits.

• You can enable RX/TX FIFO double width mode to create a FPGA fabric / PCS interface width of 128 bits.

• Click Finish to generate the Native PHY IP (this is your RTL file).


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Figure 162. Signals and Ports of the Native PHY for Basic (Enhanced PCS) Transceiver

Configuration Rule for Data Rates Above 17.4 Gbps and FPGA Fabric / PCS

Interface width of 128 bits tx_cal_busy rx_cal_busy

NIOS

Hard Calibration IP

Reconfiguration

Registers reconfig_reset reconfig_clk reconfig_avmm tx_serial_data

TX PMA

Serializer

TX Enhanced PCS tx_digital_reset tx_control[17:0] tx_parallel_data[127:0] tx_coreclkin tx_clkout tx_enh_data_valid tx_digital_reset tx_control[17:0] tx_parallel_data[127:0] tx_coreclkin tx_clkout tx_enh_data_valid tx_serial_clk0

(from TX PLL) tx_analog_reset rx_analog_reset

RX PMA

Deserializer

RX Enhanced PCS rx_serial_data rx_cdr_refclk0 rx_is_lockedtodata rx_is_lockedtoref

CDR rx_digital_reset rx_clkout rx_coreclkin rx_parallel_data[127:0] rx_control[19:0] rx_digital_reset rx_clkout rx_coreclkin rx_parallel_data[127:0] rx_control[19:0] refclk

5. Select Tools ➤ IP Catalog ➤ Basic Functions ➤ Clocks ➤ PLLs and Resets ➤

PLL ➤ Arria 10 Transceiver ATX PLL. Refer to

Instantiating the ATX PLL IP Core

on page 354 for detailed steps.

6. Configure the ATX PLL IP using the Parameter Editor.

• Select the GT clock output buffer.

• Enable the PLL GT clock output port.

• Set the PLL output clock frequency to the Native PHY IP recommended frequency.

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Figure 163. ATX PLL IP with GT Clock Lines Enabled

7. Create a transceiver reset controller. Refer to Resetting Transceiver Channels on

page 416 for more details about configuring the reset IP core.

8. Connect the Native PHY IP core to the PLL IP core and the reset controller.

The ATX PLL's port tx_serial_clk_gt

represents the dedicated GT clock lines.

Connect this port to the Native PHY IP core's tx_serial_clk0

port. The Quartus

Prime software automatically uses the dedicated GT clocks instead of the x1 clock network.

2.9.3.5. Arria 10 GT Channel Usage

All Arria 10 GT devices have a total of six GT transceiver channels to support 25.8

Gbps.

Arria 10 GT devices have three transceiver banks that support up to two GT channels.

Each channel can operate as a duplex channel, TX only, or RX only channel.

Transceiver banks GXBL1E and GXBL1H each contain two GT transceiver channels:

Ch3 and Ch4. Transceiver bank GXBL1G contains two GT transceiver channels: Ch0 and Ch1. Channels 2 and 5 on any bank can only be configured as GX transceiver channels.


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Table 223.

Valid Permutations for GT and GX Channel Configuration in Transceiver Bank

GXBL1G for Channels 0, 1, and 2

GT Transceiver Channel

Ch2

Ch1

Ch0

Configuration A

Unusable

GT

GT

Configuration B

Unusable

GT

Unusable

Configuration C

Unusable

Unusable

GT

Configuration D

GX

GX

GX

Notes on grouping channels Ch0, Ch1, and Ch2:

• If channels 0 and 1 are configured as GT channels, channel 2 is unusable

(Configuration A).

• If either channel 0 or 1 is configured as a GT channel, the remaining channels are unusable (Configurations B and C).

• If channels 0 and 1 are not configured as GT channels, this grouping can be all configured as GX channels (Configuration D).

• If either channel 0 or 1 is used as a GT channel, then the ATX PLL adjacent to channel 0 and 1 must be reserved for GT channel configurations.

Table 224.

Valid Permutations for GT and GX Channel Configuration in Transceiver Banks

GXBL1E and GXBL1H for Channels 3, 4, and 5

GT Transceiver Channel

Ch5

Ch4

Ch3

Configuration A

Unusable

GT

GT

Configuration B

Unusable

GT

Unusable

Configuration C

Unusable

Unusable

GT

Configuration D

GX

GX

GX

Notes on grouping channels Ch3, Ch4, and Ch5:

• If channels 3 and 4 are configured as GT channels, channel 5 is unusable

(Configuration A).

• If either channel 3 or 4 is configured as a GT channel, the remaining channels are unusable (Configurations B and C).

• If channels 3 and 4 are not configured as GT channels, this grouping can be all configured as GX channels (Configuration D).

• If either channel 3 or 4 is used as a GT channel, then the ATX PLL adjacent to channel 3 and 4 must be reserved for GT channel configurations.

2.9.4. How to Implement PCS Direct Transceiver Configuration Rule

You should be familiar with PCS Direct architecture, PMA architecture, PLL architecture, and the reset controller before implementing PCS Direct Transceiver

Configuration Rule.

1. Open the IP Catalog and select Arria 10 Transceiver Native PHY IP. Refer to

Select and Instantiate the PHY IP Core on page 33 for detailed steps.

2. Select PCS Direct from the Transceiver configuration rules list located under

Datapath Options.

3. Configure your Native PHY IP.

4. Click Generate to generate the Native PHY IP (this is your RTL file).

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6. Create a transceiver reset controller. You can use your own controller or use the

Transceiver PHY Reset Controller.

7. Connect the Native PHY IP to the PLL IP and the reset controller.

Figure 164. Connection Guidelines for a PCS Direct PHY Design pll_refclk PLL IP Core clk reset pll_sel pll_locked

Reset Controller tx_ready rx_ready pll_cal_busy rx_cdr_refclk tx_serialclk0

Data

Generator tx_clkout tx_parallel_data

Data

Verifier rx_clkout rx_parallel_data

Arria 10 Transceiver Native PHY tx_serial_data rx_serial_data


2.10. Simulating the Transceiver Native PHY IP Core

Use simulation to verify the Native PHY transceiver functionality. The Quartus Prime software supports register transfer level (RTL) and gate-level simulation in both

ModelSim - Intel FPGA Edition and third-party simulators. You run simulations using your Quartus Prime project files.


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The following simulation flows are available:

• NativeLink—This flow simplifies simulation by allowing you to start a simulation from the Quartus Prime software. This flow automatically creates a simulation script and compiles design files, IP simulation model files, and Intel simulation library models.

Note: The Quartus Prime Pro Edition software does not support NativeLink RTL simulation

• Scripting IP Simulation—In this flow you perform the following actions:

1. Run the ip-setup-simulation utility to generate a single simulation script that compiles simulation files for all the underlying IPs in your design. This script needs to be regenerated whenever you upgrade or modify IPs in the design.

2. You create a top-level simulation script for compiling your testbench files and simulating the testbench. It sources the script generated in the first action.

You do not have to modify this script even if you upgrade or modify the IPs in your design.

• Custom Flow—This flow allows you to customize simulation for more complex requirements. You can use this flow to compile design files, IP simulation model files, and Intel simulation library models manually.

You can simulate the following netlist:

• The RTL functional netlist—This netlist provides cycle-accurate simulation using

Verilog HDL, SystemVerilog, and VHDL design source code. Intel and third-party

EDA vendors provide the simulation models.

Prerequisites to Simulation

Before you can simulate your design, you must have successfully passed Quartus

Prime Analysis and Synthesis.


Simulating Intel FPGA Designs

2.10.1. NativeLink Simulation Flow

The NativeLink settings available in the Quartus Prime software allow you to specify your simulation environment, simulation scripts, and testbenches. The Quartus Prime software saves these settings in your project. After you specify the NativeLink settings, you can start simulations easily from the Quartus Prime software.

2.10.1.1. How to Use NativeLink to Specify a ModelSim Simulation

Complete the following steps to specify the directory path and testbench settings for your simulator:

1. On the Tools menu, click Options, and then click EDA Tool Options.

2. Browse to the directory for your simulator. The following table lists the directories for supported simulators:

Table 225.

Simulator Path

Simulator

Mentor Graphics* ModelSim - Intel FPGA Edition

Path

<drive>:\<simulator install path>\win32aloem (Windows)

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Simulator Path

/<simulator install path>/bin (Linux*)

3. On the Assignments menu, click Settings.

4. In the Category list, under EDA Tool Settings select Simulation.

5. In the Tool name list, select your simulator.

Note: ModelSim refers to ModelSim SE and PE. These simulators use the same commands as QuestaSim.ModelSim - Intel FPGA Edition refers to ModelSim - Intel

FPGA Edition Starter Edition and ModelSim - Intel FPGA Edition Subscription

Edition.

6. In the Output directory, browse to the directory for your output files.

7. To map illegal HDL characters, turn on Map illegal HDL characters.

8. To filter netlist glitches , turn on Enable glitch filtering.

9. Complete the following steps to specify additional options for NativeLink automation: a. Turn on Compile test bench.

b. Click Test Benches.

The Test Benches dialog box appears.

c. Click New.

d. Under Create new test bench settings, for Test bench name type the test bench name. For Top level module in the test bench, type the top-level module name. These names should match the actual test bench module names.

e. Select Use test bench to perform VHDL timing simulation and specify the name of your design instance under Design instance name in test bench.

f.

Under the Simulation period, turn on Run simulation until all vector

stimuli are used.

g. Under Test bench and simulation files, select your test bench file from your folder. Click Add.

h. Click OK.


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2.10.1.2. How to Use NativeLink to Run a ModelSim RTL Simulation

Figure 165. NativeLink Simulation Flow Diagram

Specify EDA Simulator &

Simulator Directory

Run RTL Functional or

Gate-Level Simulation

Does

Simulation Give

Expected Results?

No

Debug Design &

Make RTL Changes

Yes

Run Quartus Prime

Analysis and Elaboration

Define Control Signals Using

In-System Sources & Probes

Run Simulation

No

Does

Simulation Give

Expected Results?

Yes

Simulation Complete

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Complete the following steps to run an RTL functional simulation:

1. Open your Quartus Prime project.

2. On the Tools menu, select Run Simulation Tool, then select RTL Simulation or

Gate Level Simulation.

3. Run Quartus Prime Analysis and Elaboration and re-instantiate control signals that you defined using the In-System Sources and Probe Editor. The In-System Sources and Probe Editor can only access the pins of the device. Consequently, you must route any signal that you want to observe to the top-level of your design.

4. To monitor additional signals, highlight the desired instances or nodes in

Instance, and right-click Add wave.

5. Select Simulate and then Run.

6. Specify the simulation duration.

7. Complete the following steps to restart the simulation: a. On the Simulate menu, select restart, then click ok.

This action clears the existing waves.

b. Highlight run and select the appropriate options to run the simulation.


Simulating the Transceiver Native PHY IP Core on page 325

2.10.1.3. How to Use NativeLink to Specify Third-Party RTL Simulators

The following figure illustrates the high-level steps for using the NativeLink with Third-

Party EDA RTL simulator.


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Figure 166. Using NativeLink with Third-Party Simulators

Specify EDA Simulator &

Simulator Directory

Perform

Functional Simulation

Does

Simulation Give

Expected Results?

No

Debug Design &

Make RTL Changes

Yes

Run Quartus Prime

Analysis and Elaboration

Start Simulator, Compile

Design and Testbench

Load Design &

Run Simulation

No

Does

Simulation Give

Expected Results?

Yes

Simulation Complete

Complete the following steps to specify the directory path and testbench settings for your simulator:

1. On the Tools menu, click Options, and then click EDA Tool Options.

2. Browse to the directory for your simulator. The following table lists the directories for supported third-party simulators:

Table 226.

Simulator Path

Simulator

Mentor Graphics ModelSim

Mentor Graphics QuestaSim*

Synopsys VCS/VCS MX

Cadence Incisive Enterprise

Aldec Active-HDL

Aldec Riviera-Pro

Path

<drive>:\<simulator install path>\win32 (Windows)

/<simulator install path>/bin (Linux)


/<simulator install path>/tools/bin (Linux)

<drive>:\<simulator install path>\bin (Windows)


3. On Assignments menu, click Settings.

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4. In the Category list, under EDA Tool Settings, select Simulation.

5. In the Tool name list, select your simulator.

6. To enable your simulator, on the Tools menu, click Options and then click

License Setup . Make necessary changes for EDA tool licenses.

7. Compile your design and testbench files.

8. Load the design and run the simulation in the EDA tool.

To learn more about third-party simulators, click on the appropriate link below.


• Mentor Graphics ModelSim and QuestaSim Support

• Synopsys VCS and VCS MX Support

• Cadence Incisive Enterprise Simulator Support

• Aldec Active-HDL and Riviera-Pro Support

2.10.2. Scripting IP Simulation

The Intel Quartus Prime software supports the use of scripts to automate simulation processing in your preferred simulation environment. You can use your preferred scripting methodology to control simulation.

Intel recommends the use of a version-independent top-level simulation script to control design, testbench, and IP core simulation. Because Quartus Prime-generated simulation file names may change.

You can use the ip-setup simulation utility to generate or regenerate underlying setup scripts after any software or IP version upgrade or regeneration. Use of a top-level script and ip-setup-simulation eliminates the requirement to manually update simulation scripts.

2.10.2.1. Generating a Combined Simulator Setup Script

Platform Designer (Standard) system generation creates the interconnect between components. It also generates files for synthesis and simulation, including the .spd files necessary for the ip-setup-simulation utility.

The Intel Quartus Prime software provides utilities to help you generate and update IP simulation scripts. You can use the ip-setup-simulation utility to generate a combined simulator setup script, for all Intel FPGA IP in your design, for each supported simulator. You can subsequently rerun ip-setup-simulation to automatically update the combined script. Each simulator's combined script file contains a rudimentary template that you can adapt for integration of the setup script into a top-level simulation script.


Intel Quartus Prime Standard Edition Handbook Volume 3: Verification

Provides more information about the steps to generate top-level simulation script.


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2.10.3. Custom Simulation Flow

The custom simulation flow allows you to customize the simulation process for more complex simulation requirements. This flow allows you to control the following aspects of your design:

• Component binding

• Compilation order

• Run commands

• IP cores

• Simulation library model files

The following figure illustrates the steps for custom flow simulation. If you use a simulation script, you can automate some of the steps.

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Figure 167. Custom flow Simulation

Compile Sim Model Libs

Using Sim Lib Compiler

Start Simulator & Open

Quartus Prime Project

Compile Design, Testbench,

& Simulation Libraries

Load Design

& Run Simulation

Does

Simulation Give

Expected Results?

No

Debug Design &

Make RTL Changes

Yes

Compile Design, Testbench,

& Simulation Libraries

Load Design &

Run Simulation

No

Does

Simulation Give

Expected Results?

Yes

Simulation Complete

2.10.3.1. How to Use the Simulation Library Compiler

The Simulation Library Compiler compiles Intel simulation libraries for supported simulation tools, and saves the simulation files in the output directory you specify.


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Note: Because the ModelSim - Intel FPGA Edition software provides precompiled simulation libraries, you do not have to compile simulation libraries if you are using the software.

Complete the following steps to compile the simulation model libraries using the

Simulation Library Compiler:

1. On the Tools menu, click Launch Simulation Library Compiler.

2. Under EDA simulation tool, for the Tool name, select your simulation tool.

3. Under Executable location, browse to the location of the simulation tool you specified. You must specify this location before you can run the EDA Simulation

Library Compiler.

4. Under Library families, select one or more family names and move them to the

Selected families list.

5. Under Library language, select Verilog, VHDL, or both.

6. In the Output directory field, specify a location to store the compiled libraries.

7. Click Start Compilation.

Complete the following steps to add the simulation files to your project:

1. On the Assignments menu, click Settings.

2. In the Category list, select Files.

3. Click Browse to open the Select File dialog box and select one or more files in the Files list to add to your project.

4. Click Open, and then Add to add the selected file(s) to your project.

5. Click OK to close the Settings dialog box.


• Preparing for EDA Simulation

• Intel FPGA Simulation Models

2.10.3.2. Custom Simulation Scripts

You can automate simulations by creating customized scripts. You can generate scripts manually. In addition, you can use NativeLink to generate a simulation script as a template and then make the necessary changes. The following table shows a list of script directories NativeLink generates.

Table 227.

Custom Simulation Scripts for Third Party RTL Simulation

Simulator

Mentor Graphics

ModelSim or

QuestaSim

Aldec Riviera Pro

Simulation File

/simulation/ modelsim/ modelsim_setup.do

Or mentor/msim_setup.tcl

/simulation/ aldec/ rivierapro_setup.tcl

Use

Source directly with your simulator. Run do msim_setup.tcl

, followed by ld_debug

. If you have more than one IP, each IP has a dedicated msim_setup.tcl

all the files included in the

file. Make sure that you combine msim_setup.tcl

files into one common msim_setup.tcl

file.

Source directly with your simulator

.

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Simulator

Synopsys VCS

Cadence Incisive

(NCSim)

Simulation File

/simulation/synopsys/vcs/ vcs_setup.sh

Synopsys VCS MX /simulation/synopsys/ vcsmx/vcsmx_setup.sh

/simulation/cadence/ ncsim_setup.sh

Use

Add your testbench file name to this file to pass the testbench file to VCS using the

–file

option. If you specify a testbench file for

NativeLink and do not choose to simulate, NativeLink generates a script that runs VCS.

Run this script at the command line using quartus_sh–t

<script>

. Any testbench you specify with NativeLink is included in this script.

Run this script at the command line using this script.

quartus_sh –t

<script>. Any testbench you specify with NativeLink is included in

2.11. Implementing Protocols in Intel Arria 10 Transceivers

Revision History

Changes Document

Version

2018.06.15

2017.11.06

2016.10.31

Made the following changes:

• For the 1G/2.5G/5G/10G Multi-rate Ethernet status signal, added a Clock Domain column and values for all except led_char_err.

• Changed the Gen1 PIPE PLL output frequency from 1250MHz to 2500MHz in fPLL IP Parameter Core

Settings for PIPE and ATX PLL IP Parameter Core Settings for PIPE.

• Updated Disabling/Enabling PRBS Pattern Inversion to address the hard PRBS generator and checker pattern being inverted.

• Updated the description of 0x4C0 bit 5 Override AN Parameters Enable to refer to 0x4C3 and changed the start address of the reserved space to 0x4D7 in 10GBASE-KR PHY Register Definitions.

• Changed the start address of the reserved space to 0x4D7 in 1G/10GbE Register Definitions.

• Added a frequency to the description of and added a footnote to the Selected CDR reference

clock frequency parameter in the "RX PMA Parameters" table.

• Added a note about bit slipping after the "Gearbox Parameters" table.

• Added a reference and a link to Clock and Reset Interfaces in the "1-Gigabit/10-Gigabit Ethernet

(GbE) PHY IP Core" section.

• Clarified the description of the Enable PCIe pipe_hclk_in and pipe_hclk_out ports parameter in the "PCIe Ports" table.

• Clarified the description of the pipe_hclk_out[0]

Native PHY in PIPE Mode" table.

port in the "Ports for Arria 10 Transceiver

• Changed the values for the Number of fixed dfe taps parameter in the "RX PMA Parameters" table of the Interlaken section.

• Changed the description of bit 15 of register address 0x4D0 in the "1G/10GbE Register Definitions" table.

• Changed the description of bit 5 of register address 0x4C0 in the "1G/10GbE Register Definitions" table.

Made the following changes to the CPRI section:

• Removed a note from the "Transmitter and Receiver Latency" section.

Made the following changes to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core section:

• Added the "Register Map" section.

Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:

• Added MII Interface signals to the "1G/10GbE PHY Top-Level Signals" figure.

• Added the MII section.

• Added the tx_pcfifo_error_1g

Signals" table.

and rx_pcfifo_error_1g

signals to the "Control and Status

• Removed bit addresses from the 0x494 register in the "GMII PCS Registers" table.

• Changed the read/write description for the 0x495 register in the "GMII PCS Registers" table.

• Changed the note for

COPPER_DUPLEX_OPERATION

in the "GMII PCS Registers" table.

continued...


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Document

Version

2016.05.02

Changes

Made the following changes to the Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 section:

• Added description about the RX FIFO and TX FIFO in the "GbE with IEEE 1588v2" section.

• Added a note to the pll_powerdown

1588v2 PHY Design" figure.

signal in the "Connection Guidelines for a GbE/GbE with IEEE

• Updated the parameter descriptions for in the "Standard PCS Parameters" table.

Made the following changes to the XAUI PHY IP Core section:

• Added further description to the rx_channelaligned

Signals—Soft IP Implementation" table.

signal in the "Optional Control and Status

Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:

• Added "Synchronous to rx_clkout

" for rx_std_wa_patternalign[<n>-1:0] domain column in Word Aligner and Bitslip table.

in the clock

• Added "Unused Transceiver Channels" section.


• New table "Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates" added.

• Supported data rates updated for TX PLLs.

• Data rate values updated in table "General and Datapath Options".

Made the following changes to the PCI Express section:

• Added PIPE Interface width number in the Port column in table "Ports for Arria 10 Transceiver

Native PHY in PIPE Mode".

Made the following changes to the 10GBASE-KR PHY IP Core section:

• Updated the version and release date in the "10GBASE-KR PHY Release Information" table.

• Changed the definitions and parameters in the "General Options Parameters" table.

• Added the "Speed Detection Parameters" table.

• Added and removed parameters in the "Auto Negotiation and Link Training Settings" table.

• Removed parameter from the "10GBASE-R Parameters" table.

• Changed descriptions in the "10GBASE-KR Register Definitions" table for 0x4B0 and 0x4D0.

• Added signals to the "Control and Status Signals" table.

• Added a new bit field for 0x4D1 in the "10GBASE-KR Register Definitions" table.

• Changed the default value for INITPOSTVAL Init Post tap Value in the "10GBASE-KR Optional

Parameters" table.

Made the following changes to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core section:

• Changed the "Block Diagram of the PHY IP Core" figure.

• Updated the version and release date in the "PHY Release Information" table.

• Updated the "Resource Utilization" table.

• Updated the "PHY Features" table.

• Changed the "1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters" table.

• Added signals to the "PHY Interface Signals" figure.

• Added descriptions in the "Clock and Reset Signals" table.

• Added descriptions in the "Transceiver Mode and Operating Speed Signals" table.

• Changed the "Avalon-MM Interface Signals" table.

• Added signals to the "XGMII Signals" table.

• Added registers to the "PHY Register Definitions" table.

• Added parameters to the "1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters" table.

Made the following changes to the 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core section:

• Updated the version and release date in the "1G/10GbE Release Information" table.

• Added signals to the "1G/10GbE PHY Top-Level Signals" figure.

• Added signals to the "PHY Interface Signals" figure.

• Added signals to the "Control and Status Signals" table.

• Changed descriptions in the "GMII Interface Ports " table.

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Document

Version

2016.02.11

2015.12.18

Changes

Made the following changes to the Simulating the Transceiver Native PHY IP section:

• Added a footnote to inform that the "NativeLink" mode is not supported by the "Quartus Prime Pro" edition.

• Added the “Scripting IP Simulation” flow..

• Replaced the “Generation Version Agnostic IP" and "Platform DesignerPlatform Designer Simulation

Scripts", “Use the ip-make-simscript Utility”, and “How to Generate Scripts” sections with the

“Scripting IP Simulation” section.


• Updated the "How to Place Channels for PIPE Configuration" section.

• Updated the“x4 Configuration with Master Channel Adjacent to a HIP”, “x4 Configuration with

Master Channel not Adjacent to a HIP”, “Rate Switch Change” figures.

Made the following changes to the Other Protocols section:

• Replaced the "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT Channels” section.

• Changed the title from "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT

Channels” to "Design Considerations for implementing Arria 10 GT Channels”.

• Changed the data rate from a range of “17.4 Gbps to 28.3 Gbps” to 25.78125 Gbps.

• Changed the titles of “Valid Permutations for GT and GX Channel Configuration in Transceiver Bank

GXBL1G for Channels 0, 1, and 2” and “Valid Permutations for GT and GX Channel Configuration in

Transceiver Banks GXBL1E and GXBL1H for Channels 3, 4, and 5".

• Removed the “Native PHY IP Parameter Settings for PCS Direct Transceiver Configuration Rules” section.

• Changed “How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced PCS in Low

Latency Mode” section.

• Changed the “ATX PLL IP with GT Clock Lines Enabled” figure.

• Updated the "Valid Permutations for GT and GX Channel Configuration in Transceiver Bank GXBL1G for Channels 0, 1, and 2" and "Valid Permutations for GT and GX Channel Configuration in

Transceiver Banks GXBL1E, and GXBL1H for Channels 3, 4, and 5"" tables.


• Updated the "Transceiver Channel Datapath and Clocking for CPRI" figure.

• Added a note in the "Channel Width Options for Supported Serial Data Rates" table.

• Changed the fPLL supported data rate in the "TX PLL Supported Data Rates" table.

• Changed the "General and Datapath Options" table in the "Native PHY IP Parameter Settings for

CPRI" section.

Made the following changes to the Arria 10 Transceiver Protocols and PHY IP Support section:

• Moved the 19th footnote from "Protocol Preset" column to "Transceiver PHY IP Core" column.

• Changed the footnote 14 to the following: “Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP”.


• Removed the "Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels" section.

• Updated the maximum data rate for GT channels to 25.8 Gbps.

Made the following changes to the 1G/2.5G/10G Multi-rate Ethernet PHY IP Core section:

• Removed signals from the "XGMII Signals" table.

• Removed signals from the "PHY Interface Signals" figure.

• Changed the ordering code in the "PHY Release Information" table.


• Added a description to the "Implementation of the XGMII Specification in Arria 10 Devices

Configuration" figure.

Made the following changes to the 10GBASE-KR PHY IP with FEC Option section:

• Added a note to the "Parameterizing the 10GBASE-KR PHY" section.

• Added new signals to the "Control and Status Signals" table.

continued...


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Document

Version

2015.11.02

Changes


• Added a note to the "Parameterizing the 1G/10GbE PHY" section.

• Added new signals to the "Control and Status Signals" table.

• Changed the description for calc_clk_1g in the "Clock and Reset Signals" table.

Made the following changes to the PCI Express (PIPE) section:

• Updated the "Rate Switch Change" figure in the Gen3 features section.


• Changed the title of “TX and RX FIFO” to “Standard PCS FIFO” in the Standard PCS Ports table.

• Updated the description and range for “Enable fast sync status reporting for deterministic Latency

SM” parameter in the Standard PCS Parameters table.

• Changed the title of “TX and RX FIFO Parameters” to “Standard PCS FIFO Parameters” in the

Standard PCS Parameters table.

• Updated the “Error marking type” range in the KR-FEC Parameters table in the Enhanced PCS

Parameters section.

• Updated the “Number of fixed DFE taps” value in the Equalization table in the PMA Parameters section.

• Added a new parameter “Provide separate interface for each channel” in the General and Datapath

Options table in the General and Datapath Parameters section.

• Updated the “PMA configuration rules” value in the General and Datapath Options table in the

General and Datapath Parameters section.

• Removed footnote and added "Hard IP for PCI Express to Native PHY IP" in the “Arria 10 Transceiver

Protocols and PHY IP Support” table.

• Updated the description for “Enable tx_pma_ rxfound port (QPI)” parameter in the TX PMA Optional

Ports table in the PMA Parameters section.

• Updated the descriptions for “TX FIFO Mode”,“Enable tx_enh_fifo_full port”, “Enable tx_enh_fifo_empty port” parameters in the Enhanced PCS TX FIFO Parameters table in the

Enhanced PCS Parameters section.

• Updated the descriptions for “Enable rx_enh_fifo_full port”, “Enable rx_enh_fifo_empty port” parameters in the Enhanced PCS RX FIFO Parameters table in the Enhanced PCS Parameters section.

• Updated the description for “Enable RX byte deserializer” parameter in the Byte Serializer and

Deserializer Parameters table in the Standard PCS Parameters section.

• Updated the description for “Share reconfiguration interface” parameter in the Dynamic

Reconfiguration table in the Dynamic Reconfiguration Parameters section.

• Updated the values and descriptions in the Configuration Profiles table in the Dynamic

Reconfiguration Parameters section.

• Updated the foot note for “tx_pma_clkout” clock to suggest what to do with the clock.

• Updated the description for “tx_dispval[<n>(<w>/<s>-1:0]” signal in the 8B/10B Encoder and

Decoder table in the Standard PCS Ports section.

• Updated the values and descriptions in the Configuration Profiles table in the Dynamic

Reconfiguration Parameters section.

• Updated the descriptions for “Enable tx_std_ pcfifo_full port”, “Enable tx_std_ pcfifo_empty port”,

“Enable rx_std_ pcfifo_full port”, “Enable rx_std_ pcfifo_empty port” in the TX and RX FIFO

Parameters table in the Standard PCS Parameters section.

• Added links to other sections which describe the RX rate match FIFO in Basic, GBE and Transceiver channel datapath modes in the Rate Match FIFO Parameters table in the Standard PCS Parameters section.

• Updated value for Transceiver Configuration rules parameter in the " General and Datapath Options" table in the General and Datapath Parameters section.

• Added a new parameter "Provide separate interface for each channel" in the " General and Datapath

Options" table in the General and Datapath Parameters section.

• Updated “Transceiver Native PHY IP Core Parameter Editor” figure.

• Updated “General, Common PMA Options, and Datapath Options” table.

• Added parameter “Enable tx_pma_analog_reset_ackport” in “TX PMA Optional Ports” table.

• Updated parameter “Number of fixed DFE taps” in "Equalization" table.

• Added parameter “Enable rx_analog_reset_ack port” in "RX PMA Optional Ports” table.

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Document

Version

Changes

• Added parameter “Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE” in “Dynamic Reconfiguration” table.

• Added parameter “Include PMA analog settings in configuration Files”in “Configuration Files”.

• Added “Analog PMA Settings (Optional) in Dynamic Reconfiguration” tabl.e


• Changed the release date and version in the "1G/10GbE Release Information" table.

• Changed the descriptions for

Reset Signals" table.

tx_serial_clk_1g

and rx_cdr_refclk_1g

in the "Clock and

• Changed descriptions in the "General Options Parameters" table.

• Added the "1G Data Mode" table to the PMA Registers section.

• Removed the "1G Data Mode" rows from the Arria 10 GMII PCS Registers section.

Made the following changes to the 10GBASE-KR PHY IP Core with FEC Option section:

• Added bit 12 to the 0x4B0 word address in the "10GBASE-KR Register Definitions" table.

Made the following changes to the Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 section:

• Added a note to the "Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with

IEEE 1588v2" figure.

• Changed the note in the "Gigabit Ethernet (GbE) and GbE with IEEE 1588v2" section.

• Changed some signal names in the "Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE 1588v2" figure.

• Changed the values in the "TX PMA Parameters" table.

• Added a parameter to and updated values in the "RX PMA Parameters" table.

• Changed the values in the "Standard PCS Parameters" table.

Made the following changes to the 10GBASE-R section:

• Added description text to the "10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with

FEC Variants" section.

• Changed steps in the "How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and

10GBASE-R with FEC in Arria 10 Transceivers" section.

• Changed signal names in the "Signals and Ports of Native PHY IP Core for the 10GBASE-R,

10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC" figure.

• Updated parameters in the "General and Datapath Parameters" table.

• Updated parameters in the "RX PMA Parameters" table.

• Updated parameters in the "Enhanced PCS Parameters" table.

• Updated parameters in the "Block Sync Parameters" table.

• Updated parameters in the "Dynamic Reconfiguration Parameters" table.


• Changed the release date and version in the "XAUI Release Information" table.

• Changed the descriptions in the "XAUI PHY IP Core Registers" table.

• Added description in the "XAUI PHY IP Core" section.

Made the following changes to the 1G/2.5G/10G Multi-rate Ethernet PHY IP Core section:

• Added this section.

Made the following changes to the PCI Express (PIPE) section:

• Updated description for port "pipe_g3_txdeemph[17:0]" in the "Ports for Arria 10 Transceiver

Native PHY in PIPE Mode" table.

• Updated "Ports for Arria 10 Transceiver Native PHY in PIPE Mode" table for presets to TX Deemphasis mappings.

• Updated x4 Configuration and x4 Alternate Configuration figures in the "Master Channel in Bonded

Configurations section".

• Updated "PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate" section.

• Updated “Connection Guidelines for a PIPE Gen3 Design” figure.

• Added recommendations in the “How to Implement PCI Express (PIPE) in Arria 10 Transceivers” section.

• Updated description of parameter “PCS TX channel bonding master” in the “Parameters for Arria 10

Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA” table.

• Added table “Parameter Settings for Arria 10 fPLL IP in PIPE Gen1, Gen2, Gen3 modes” in the “fPLL

IP Parameter Settings for PIPE” section.

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2015.05.11

Changes

• Added table “Parameters for Arria 10 ATX PLL IP in PIPE Gen1, Gen2, Gen3 modes” in the “ATX PLL

IP Parameter Settings for PIPE” section.

• Updated description of port pipe_tx_elecidle in the “Ports for Arria 10 Transceiver Native PHY in

PIPE Mode” table.

• Updated description of port pipe_tx_compliance in the “Ports for Arria 10 Transceiver Native PHY in

PIPE Mode” table.

• Updated description of port pipe_g3_txdeemph[17:0] in the “Ports for Arria 10 Transceiver Native

PHY in PIPE Mode” table.

• Added table “fPLL Ports for PIPE” in the section “fPLL Ports for PIPE” section.

• Added table” ATX PLL Ports for PIPE “ in the “ATX PLL Ports for PIPE” section.

• Added table “Arria 10 Preset Mappings to TX De-emphasis” in the “Preset Mappings to TX Deemphasis” section.

• Updated figure “Alternate Configuration” figure in the “How to Place Channels for PIPE

Configurations” section.

• Updated the “PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate” section.


• Added the "Enhanced PCS FIFO Operation" section.

• Changed the minimum data rate from 960 Mbps to 1.0 Gbps in the "General and Datapath

Parameters" table.


• Changed the register definitions for word address 0x4D0 in the "10GBASE-KR PHY Register

Definitions" section.


• Added a parameter to the "RX PMA Parameters" table.


• Changed the following bits and descriptions in the "10GBASE-KR PHY Register Definitions" section:

— Changed the bit and description for address 0x4D0[21:20].

— Added address 0x4D0[22].

— Removed address 0x4D0[26:24].

— Added address 0x4D0[28:24].

— Removed addresses 0x4D0[27] and 0x4D0[28].

Made the following changes to the Interlaken section:

• Added available preset variations to the "Interlaken" and "How to Implement Interlaken in Arria 10

Transceivers" sections.

• Updated the values for some parameters in the "TX PMA Parameters", "RX PMA Parameters",

"Enhanced PCS Parameters", "Interlaken Frame Generator Parameters", and "Interlaken Frame

Synchronizer Parameters" tables.


• Changed the product ID in the "1G/10GbE Release Information" table.

• Changed the descriptions in the "Clock and Reset Signals" table.

• Removed the following bits from address 0x4D0 in the "Register Definitions" table:

— 19:18

— 26:24

— 27


• Updated the "Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations", "PIPE Gen1/Gen2/

Gen3 Configurations", "PCIe Reverse Parallel Loopback Mode Datapath", and "Signals and Ports of

Native PHY IP for PIPE" figures.

• Updated "Rate Switch" Gen3 features.

• Updated the "Enable simplified interface" and "Provide separate interface for each channel" parameters in the "Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes" table.

• Updated the "PCS TX channel; bonding master" parameters in the table "Parameters for Arria 10

Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA" table.

• Updated the "Selected CDR reference clock frequency" parameter in the "Parameters for Arria 10

Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX PMA" table.

• Updated "How to place channels for PIPE configurations" section to include placement guidelines for using Arria 10 PCIe Hard IP.

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Document

Version

2014.12.15

Changes


• Updated the "Connection Guidelines for a CPRI PHY Design" figure.

• Added table for the "Behavior of word aligner status signals for varying interface widths", when in

Manual Mode.


• Updated the "Connection Guidelines for a PCS Direct PHY Design" figure.

• Updated the "Connection Guidelines for an Enhanced PCS in Low Latency Mode Design" figure.

• Updated the description following the "Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion" figure.

• Added a Note to the "TX Bit Slip" section.

• Changed the value for rx_parallel_data in the "TX Bit Slip in 8-bit Mode" and "TX Bit Slip in 16-bit

Mode" figures.


• Removed the section.

set_max_skew

constraint from the "XAUI PHY Timing Analyzer SDC Constraints"


• Updated the figure for Transceiver Native PHY IP Core Parameter Editor.

• PMA parameters

— Updated the PMA parameter categorization in the TX PMA and RX PMA "Equalization" section.

— Added parameters

Enable tx_pma_iqtxrx_clkout port

and

Enable tx_seriallpbken port

in "TX PMA Optional Ports" table.

— Added parameters

Enable rx_pma_iqtxrx_clkout port

in "RX PMA Optional Ports" table.

— Updated "RX PMA Parameters" table into "RX CDR Options" and "Equalization" sections.

— Removed the option ports table.

Enable rx_pma_div_clkout division

factor from RX PMA optional

— Updated the description of "CTLE Adaptation Mode" and "DFE Adaptation Mode" in "RX PMA" parameter table.

— Updated value and description for parameter

Enable tx_pma_clkout port

and

Enable tx_pma_div_clkout port

in "TX Bonding Options" table.

— Updated value and description for parameter

Enable rx_pma_clkout port

and

Enable rx_pma_div_clkout port

in "RX PMA Optional Ports" table.


• Updated the description of tx_cal_busy

and rx_cal_busy

signals in the PMA Ports section.

• Added a new section Enhanced PCS TX and RX Control Ports to better describe the tx_control and rx_control

bit encodings used for different protocols. Removed the bit encodings for tx_control

and rx_control

signals from Enhanced PCS Ports section.

• Updated the clock domain information about signals mentioned in

Enhanced PCS Ports

section.

• Updated the description of rx_std_wa_patternalign

signal in Standard PCS Ports section.

• Updated the parameter descriptions in General Datapath Parameters and PMA Parameters sections.

• Updated the port descriptions in PMA Ports section.


• Added another value to the "TX channel bonding mode" parameter in the "TX PMA Parameters" table.

• Added values to the "PCS TX channel bonding master" and "Actual PCS TX channel bonding master" parameters in the "TX PMA Parameters" table.

• Corrected the values to the "CTLE adaptation mode" parameter in the "RX PMA Parameters" table.

• Added the "Enable Interlaken TX random disparity bit" parameter to the "Interlaken Disparity

Generator and Checker Parameters" table.

• Changed the values to four parameters to "Off" in the "Gearbox Parameters" table.

• Removed the "Enable embedded debug" parameter from the "Dynamic Reconfiguration Parameters" table.

Made the following changes to the Gigabit Ethernet (GbE) and GvE with IEEE 1588v2 section:

• Added a figure description to the "Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE 1588v2" figure.

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Changes


• Added a figure description to the "Signals and Ports of Native PHY IP Core for the 10GBASE-R,

10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC" figure.

Made the following changes to the 10GBASE-KR PHY IP with FEC Option section:

• Changed the "10GBASE-KR PHY IP Core Block Diagram" figure to activate the Standard TX PCS,

Standard RX PCS, and GbE PCS blocks.

• Added a note to the "10GBASE-KR Functional Description" section.

• Added new parameters to the "General Options" table.

• Changed the default values for VPOSTRULE, VPRERULE, INITPOSTVAL, and INITPREVAL in the

"Optional Parameters" table.

• "10GBASE-KR PHY Register Definitions" table:

— Changed the default value for register address 0x4D0[7:4]

— Changed the default value for register address 0x4D0[17].

— Changed the descriptions for register address 0x4B2.

— Changed the descriptions for register addresses 0x4D5 and 0x4D6.

• Changed the descriptions for the following signals in the in the "Clock and Reset Signals" table.

— tx_pma_clkout

—

— rx_pma_clkout tx_pma_div_clkout

— rx_pma_div_clkout

• Changed the descriptions for the following signals in the in the "XGMII Signals" table.

— xgmii_tx_clk

— xgmii_rx_clk

• Removed the 1588 Soft FIFOs block from the "PHY-Only Design Example with Two Backplane

Ethernet and Two Line-Side (1G/10G) Ethernet Channels" figure


• Changed the descriptions for register address 0x4D5 in the "1G/10GbE Register Definitions" table.

• Removed the Daisy Chain and μP I/F lines from the Link Training block in the "1G/10GbE PHY Block

Diagram" figure.

• Changed the descriptions for 0x494 and 0x495, and added 0x4a4 bit 4 to the "GMII PCS Registers" section.

Made the following changes to the XAUI section:

• Added a PMA width requirement in the "Transceiver Clocking and Channel Placement Guidelines in

XAUI Configuration" section.

• Changed the figure description for the "Transceiver Clocking for XAUI Configuration" figure.

• Changed the note in the "Transceiver Clocking and Channel Placement Guidelines in XAUI

Configuration" section.

• Added a note to the "Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO

Enabled" figure.

• Added the "Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO Enabled" figure.

• Removed the Data rate parameter from the "General Options" table.

• Removed the tx_digitalreset

signal from the "Clock and Reset Signals" table.

• Changed the available signals in the "PMA Channel Controller Signals" table.

• Added the Enable phase compensation FIFO parameter to the "Advanced Options" table.

• Added the pll_cal_busy_i

signal to the "XAUI Top-Level Signals—Soft PCS and PMA" figure.

• Added the xgmii_rx_inclk

port to the "XAUI Top-Level Signals—Soft PCS and PMA" figure.

• Changed the description in the "Clock and Reset Signals" table.

• Removed the following signals from the "PMA Channel Controller Signals" table:

— tx_bonding_clocks[5:0]

— pll_cal_busy_i

—

— pll_powerdown_o pll_locked_i continued...

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Document

Version

2014.10.08

2014.08.15

Changes

• Made the following changes to the "XAUI PHY IP Core Registers" table.

— Removed cal_blk_powerdown

— Removed pma_tx_pll_is_locked

— Removed Word Addresses 0x082, 0x083, 0x086, 0x087, 0x088, 0x089

— Removed patterndetect[7:0]

— Changed the description for syncstatus [7:0]

• Added the xgmii_rx_inclk

port to the "SDR RX XGMII Interface " table.

• Added the pll_cal_busy_i

port to the "PMA Channel Controller Signals" table.

• Added the "XAUI PHY Timing Analyzer SDC Constraint" section.


• Added PIPE Gen3 32 bit PCS Clock Rates table in the Gen3 Rate Switchsection.

• Updated the Rate Switch Change figure.

• Updated the Bit Mappings When the Simplified Interface Is Disabledtable.

• Updated the figures in How to Place Channels for PIPE Configurations.

• Updated the Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA table.

• Updated the clock domains in Signals and Ports of Native PHY IP for PIPE figure.

• Updated the Ports for Arria 10 Transceiver Native PHY in PIPE Mode table.

• Updated Logical PCS Master Channel for PIPE Configuration table.

• Updated the PCIe Reverse Parallel Loopback in Gen1/Gen2 features with input signal name.

• Updated the Rate Switch Change figure.

• Updated the Gearbox Gen3 Transmission signals in the Gen3 Data Transmission figure.

• Updated the PIPE Design Example section.

• Updated the Gen3 Power State Management P1 to P0 Transition signals.

• Updated the Supported Features for PIPE Configurations table.

• Updated the Gen1/Gen2 Features section.


• Updated the parameter values for “RX word aligner mode”.

• Added a new option for Interlaken in the GUI "Enable Interlaken TX random disparity bit".

• For PMA configuration rules changed the option “SATA” to “SATA/SAS”.

• Changed the GUI option “CTLE adaptation mode” to “DFE adaptation mode”.


• Added four new sections: "TX Bit Slip", "TX Polarity Inversion", "RX Bit Slip", and "RX Polarity

Inversion".

• Changed the initial value of tx_parallel_data

in the "Manual Mode when the PCS-PMA Interface

Width is 10 Bits" and "Manual Mode when the PCS-PMA Interface Width is 16 Bits" figures.

• Changed the minimum value for the "Data rate" parameter to 1 Gbps in the "General and Datapath

Options Parameters" table.

Made the following changes to the Simulating the Native Transceiver PHY section:

• In the introductory section, removed the third bullet in the list of netlists you can simulate because gate-level timing simulation is no longer supported.

• Removed mention of the ModelSim DE simulator in the "How to Use NativeLink to Specify a

ModelSim Simulation" section.

Made the following changes to the Ethernet section:

• Changed the frequency for mgmt_clk

in the "Avalon-MM Interface Signals" table for Document

Version10GBASE-KR PHY IP Core with FEC Option and for 1G/10 Gbps Ethernet PHY IP Core.


• Removed an erroneous note regarding Quartus II software legality check restrictions.

Made the following changes to the Transceiver Design Flow section:

• Added "Make Pin Assignments Using Pin Planner and Assignment Editor" block to figure "Transceiver

Design Flow"

• Updated Select and Instantiate PHY IP, Generate PHY IP, Select and Instantiate PLL IP, and

Generate PLL IP sections to indicate the new IP instantiation flow per ACDS 14.0A10 release.

• Added a new section for Make Pin Assignments Using Pin Planner and Assignment Editor continued...


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Document

Version

Changes

Made the following changes to the Arria 10 Transceiver Protocols and PHY IP Support section:

• Updated table "Arria 10 Transceiver Protocols and PHY IP Support"

— Removed SFIS and 10G SDI from the table.

— Updated Protocol Preset, Transceiver Configuration Rule, and PCS Support for protocols in the table.

Made the following changes to the Using the Arria 10 Transceiver Native PHY IP section:

• Updated references of MegaWizard Plug-In Manager to IP Catalog and Parameter Editor.

• Added PCS Direct block in figure "Transceiver Native PHY IP Top Level Interfaces and Functional

Blocks".

• Updated figure "Transceiver Native PHY IP GUI" for 14.0A10 release IP GUI.

• Updated General and Datapath Parameters section

— Updated parameter descriptions in table "General and Datapath Options".

— Updated parameter descriptions in table "Transceiver Configuration Rule Parameters".

• Updated PMA Parameters section

— Updated parameter descriptions in tables "TX PMA Bonding options", "TX PLL Options", "RX PMA

Parameters".

— Added description for CTLE adaptation mode and updated description for DFE adaptation

mode.

• Enhanced PCS Parameters section

— Added a new table "Enhanced PCS Parameters"

— Updated the parameter descriptions in tables "Enhanced PCS TX FIFO Parameters", "Enhanced

PCS RX FIFO Parameters", "Interlaken Frame Generator Parameters", "Interlaken Frame

Synchronizer Parameters", "10GBASE-R BER Checker Parameters", "Scrambler-Descrambler

Parameters", "Block Synchronizer Parameters", "Gearbox Parameters".

— Added descriptions in "KR-FEC Parameters" table.

• Standard PCS Parameters

— Updated the descriptions in tables "TX and RX FIFO Parameters", "Rate Match FIFO Parameters",

"Word Aligner and Bitslip Parameters", and "PCIe Ports".

• Dynamic Reconfiguration Parameters

— Removed Enable Embedded JTAG Avalon-MM Master parameter and added Altera Debug

Master Endpoint parameter and updated its description.

— Added a table for "Embedded Debug Parameters".

• Updated the figure "Directory Structure for Generated Files" in IP Core File Locations section.

• Changed "one-time" to "triggered" adaptation mode for DFE and CTLE.


• Changed parameter name in the "Signals and Ports of Native PHY IP for Interlaken" figure from tx_bonding_clock to tx_bonding_clock[5:0].

• Updated tables in the "Native PHY IP Parameter Settings for Interlaken" section:

— Added new tables: "10GBASE-R BER Checker Parameters", "KR-FEC Parameters".

— Deleted table: "Configuration Profiles Parameters".

— Added new parameters and updated existing ones to tables: "General and Datapath

Parameters", "TX PMA Parameters", "RX PMA Parameters", "Enhanced PCS Parameters",

"Dynamic Reconfiguration Parameters".

— Updated existing parameters to tables: "Interlaken Frame Generator Parameters", "Interlaken

CRC-32 Generator and Checker Parameters".

Made the following changes to the Ethernet section:

• Initial release of the XAUI PHY IP Core section.

• Changed the bus width between the FPGA fabric and PCS, and added notes 3 and 4 to the

"Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2" figure.

• Provided the full hexadecimal values for rx_parallel_data

, rx_patterndetect

, and rx_runningdisp

in the "Decoding for GbE" figure description.

• Changed the note in the Rate Match FIFO for GbE section to clarify the case where 200 ppm total is valid.

• Added the pll_cal_busy

circuitry, updated signals, and added a note to the "Connection

Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design" figure.

• Removed the Device and speed grade parameter from the "General and Datapath Options" table.

continued...

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Document

Version

Changes

• Changed the values for the PPM detector threshold parameter and removed the Decision feedback equalization parameter in the "RX PMA Parameters" table.

• Changed the 10GBASE-R PHY grouping in the "10GBASE-R PHY as Part of the IEEE802.3-2008 Open

System Interconnection (OSI)" figure.

• Added that 10GBASE-R is compatible with the Altera 10-Gbps Ethernet MAC Intel FPGA IPCore

Function in the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants section.

• Added the "Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2" figure.

• Changed steps 1 and 4 in the How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and

10GBASE-R with FEC in Arria 10 Transceivers section to match the GUI.

• Specified the target BER of 10 -12 in the 10GBASE-KR PHY IP Core section.

• Removed the "Top Level Modules of the 1G/10GbE PHY Intel FPGA IP Core Function" figure.

• Removed the 10GBASE-KR PHY with 1588 variant from the "10GBASE-KR PHY Performance and

Resource Utilization" table. This is not supported.

• Replaced the "10GBASE-KR PHY IP Block Diagram" figure.

• Added the Auto Negotiation, IEEE 802.3 Clause 73 section.

• Substantially rewrote the Link Training (LT), IEEE 802.3 Clause 72 section.

• Removed the "TX Equalization for Link Partners" figure.

• Removed the "TX Equalization in Daisy Chain Mode" figure. Daisy chain is not supported.

• Removed the Auto Negotiation section.

• Replaced the "Reconfiguration Block Details" figure.

• Removed the Initial Datapath, Enable internal PCS reconfiguration logic, and Enable IEEE

1588 Precision time Protocol parameters from the "General Options Parameters" table.

• Added the Reference clock frequency, Enable additional control and status pins, Include

FEC sublayer, Set FEC_ability bit on power up and reset, and Set FEC_Enable bit on power

up and reset parameters to the "General Options Parameters" table.

• Removed the 10GBASE-R Parameters section.

• Removed the 10M/100M/1Gb Ethernet Parameters section.

• Removed the Speed Detection Parameters section.

• Substantially changed the "Auto Negotiation and Link Training Settings" table, adding the

AN_PAUSE Pause Ability, CAPABLE_FEC ENABLE_FEC (request), AN_TECH Technology

Ability, AN_SELECTOR Selector Field, and Width of the Training Wait Counter parameters.

• Updated all parameter names, values, and descriptions in the "Optional Parameters" table.

• Updated the signals in the "10GBASE-KR Top-Level Signals" figure.

• Removed the rx_serial_clk_1g

and tx_serial_clk_1g

signals, and removed all references to

"1G" from all descriptions in the "Clock and Reset Signals" table.

• Removed references to GMII and MII interfaces from the Data Interfaces section.

• Removed GMII and MII signals from the "XGMII Signals" table.

• Updated the list of signals in the "Control and Status Signals" table.

• Removed the Daisy-Chain Interface Signals section.

• Removed the Embedded Processor Interface Signals section.

• Updated the list of signals in the "Dynamic Reconfiguration Interface Signals" table.

• Added new registers and updated descriptions of existing registers in the "10GBASE-KR Register

Definitions" table.

• Updated the 0x482 registers in the "PCS Registers" table.

• Updated and removed some addresses in the "PMA Registers" table.

• Added the Speed Change Summary section.

• Removed the 10GBASE-KR, Backplane, FEC, GMII PCS Registers section.

• Removed the 1588 Delay Requirement section.

• Removed the Channel Placement Guidelines section.

• Removed the introductory paragraph from the Design Example section.

• Removed the 1588 FIFO block from the "Top Level Modules of the 1G/10GbE PHY Intel FPGA IP

Core Function" figure.

• Updated all values for ALMs, ALUTs, Registers, and M20K in the "1G/10GbE PHY Performance and

Resource Utilization" table.

• Updated the blocks in the "Reconfiguration Block Details" figure.

continued...


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Document

Version

2013.12.02

Changes

• Changed the blocks and clock connections in the "Clocks for Standard and 10G PCS and TX PLLs" figure.

• Changed signal names and descriptions in the "Clock and Reset Signals" table.

• Changed the parameter name for 10GbE Reference Clock frequency and added the 1G

Reference clock frequency parameter in the "10GBASE-R Parameters" table.

• Removed the Set FEC_ability bit on power up and reset and Set FEC_enable bit on power

up and resetparameters from the "FEC Options" table.

• Updated the list of available signals in the "1G/10GbE PHY Top-Level Signals" figure.

• Added new registers and updated descriptions of existing registers in the "10GBASE-KR Register

Definitions" table.

• Added the 0x4A8 and 0x4A9 addresses and updated the name for address 0x4A2 and 0x4A3 in the

"10GBASE-KR, Backplane, FEC GMII PCS Registers" table.

• Added the Speed Change Summary section.


• Added a new topic Pipe link equalization for Gen 3 data rate.

• Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the How to Connect

TX PLLs for PIPE Gen1, Gen2 and Gen3 Mode section.

• Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the How to Implement

PCI Express in Arria 10 Transceivers section.

• Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the Supported Pipe

Features section.


• Added new values to each row in the "TX PLL Supported Data Rates" table.


• Updated the "How to Use NativeLink to Specify a ModelSim Simulation" section.

• Updated the "NativeLink Generated Scripts for Third-Party RTL Simulation" table.

• Changed references from MegaWizard to IP Catalog or Parameters Editor.

• Using the Basic and Basic with KR FEC Configurations of Enhanced PCS

— Updated the "Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS)

Configuration" figure and added footnote 3.

— Updated the "General and Datapath Parameters", "TX PMA Parameters", "RX PMA Parameters", and "Enhanced PCS Parameters" tables.

— Added the "Equalization" table.

— Added the "How to Enable Low Latency in Basic Enhanced PCS" section.

• Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS

— Updated the values in the "Manual Mode when the PCS-PMA Interface is 8 Bits", "Manual Mode when the PCS-PMA Interface is 10 Bits", and "Manual Mode when the PCS-PMA Interface is 16

Bits" figures.

— Added the "8B/10B Encoder and Decoder" and "8B/10B TX Disparity Control" sections.

— Updated the "Connection Guidelines for a Basic/Custom Design" figure.

— Updated the "General and Datapath Options Parameters", "TX PMA Parameters", "RX PMA

Parameters", and "Standard PCS Parameters" tables.

• Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels

— Updated the maximum data rate for GT channels to 25.4 Gbps.

— Added information about PCS Direct mode.

— Updated "ATX PLL IP with GT Clock Lines Enabled" figure.

• Updated the How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in

Arria 10 Transceivers section.

Made the following changes to the Simulating the Transceiver Native PHY IP Core section:

• Updated the "How to Use NativeLink to Specify a ModelSim Simulation" section.

• Updated the "NativeLink Generated Scripts for Third-Party RTL Simulation" table.

Initial release.

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3. PLLs and Clock Networks

This chapter describes the transceiver phase locked loops (PLLs), internal clocking architecture, and the clocking options for the transceiver and the FPGA fabric interface.

As shown in the following figure, transceiver banks can have either three or six transceiver channels. For every three channels, you get one advanced transmit (ATX)

PLL, one fractional PLL (fPLL), and one Master clock generation block (CGB). Refer to the Device Transceiver Layout section to identify which devices have three channel transceiver banks.

The Arria 10 transceiver clocking architecture supports both bonded and non-bonded transceiver channel configurations. Channel bonding is used to minimize the clock skew between multiple transceiver channels. For Arria 10 transceivers, the term bonding can refer to PMA bonding as well as PMA and PCS bonding. Refer to the

Channel Bonding section for more details.

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2008

Registered

3. PLLs and Clock Networks

UG-01143 | 2018.06.15

Figure 168. Arria 10 PLLs and Clock Networks x1 Clock Lines

CH2 CDR

Local CGB

CH1 CDR/CMU

Local CGB

CH0

CDR

Local CGB x6 Clock Lines xN Clock Lines

Transceiver

Bank fPLL

ATX

PLL

Master

CGB

Transceiver

Bank

CH5

CDR

Local CGB

CH4

CDR/CMU

Local CGB

CH3 CDR

Local CGB

CH2

CDR

Local CGB

CH1 CDR/CMU

Local CGB

CH0

CDR

Local CGB fPLL

ATX

PLL

Master

CGB fPLL

ATX

PLL

Master

CGB


•

Channel Bonding

on page 389

•

Device Transceiver Layout

on page 9

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•


on page 398

Information on how to use PLL IP to implement bonded and non-bonded transceiver designs.

3.1. PLLs

Table 228.

Transmit PLLs in Arria 10 Devices

PLL Type

Advanced Transmit (ATX) PLL

Fractional PLL (fPLL)

Clock Multiplier Unit (CMU) PLL or Channel PLL (50)

Characteristics

• Best jitter performance

• LC tank based voltage controlled oscillator (VCO)

• Supports fractional synthesis mode (in cascade mode only)

• Used for both bonded and non-bonded channel configurations

• Ring oscillator based VCO

• Supports fractional synthesis mode

• Used for both bonded and non-bonded channel configurations

• Ring oscillator based VCO

• Used as an additional clock source for non-bonded applications

Figure 169. Transmit PLL Recommendation Based on Data Rates


Refer to Using PLL and Clock Networks section for guidelines and usage

on page 398

3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs

ATX PLL-to-ATX PLL Spacing Guidelines

For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 7 ATX PLLs apart (skip 6).

(50) The CMU PLL or Channel PLL of channel 1 and channel 4 can be used as a transmit PLL or as a clock data recovery (CDR) block. The channel PLL of all other channels (0, 2, 3, and 5) can only be used as a CDR.


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Note:

For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GX channels, they must be placed 4 ATX PLLs apart (skip 3).

For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz) and drive GT channels, they must be placed 3 ATX PLLs apart (skip 2).

For two ATX PLLs providing the serial clock for PCIe/PIPE Gen3, they must be placed 4

ATX PLL apart (skip 3).

If these spacing rules are violated, Intel Quartus Prime issues a critical warning.

When two ATX PLLs are being used, and you meet the following two conditions in your applications:

• One of the ATX PLL re-calibration process is triggered.

• The other channel (that is clocked by another ATX PLL) is in data transmission mode.

You must place the two ATX PLLs 7 ATX PLLs apart (skip 6). ATX PLLs between the 2 active ATX PLLs should not be used.

ATX PLL-to-fPLL Spacing Guidelines

If you are using both ATX PLL and fPLL, and you meet the below two conditions in your applications:

• When ATX PLL VCO frequency and fPLL VCO frequency is within 50MHz.

• ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/

OC192/STM64, 10G GPON or protocol that has jitter integration start range

<1MHz and data rate > 3Gbps.

The ATX PLL and fPLL must be separated at least by 1 ATX PLL in between.

If you are using both ATX PLL and fPLL, and you meet the below two conditions in your applications:

• fPLL user re-calibration process is triggered.

• ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/

OC192/STM64, 10G GPON or protocol that has jitter integration start range

<1MHz and data rate > 3Gbps.

then the ATX PLL and fPLL must be separated at least by 1 ATX PLL in between

(regardless of the ATX PLL and fPLL VCO frequency offset).

3.1.2. ATX PLL

The ATX PLL contains LC tank-based voltage controlled oscillators (VCOs). These LC

VCOs have different frequency ranges to support a continuous range of operation.

When driving the Transceiver directly, the ATX PLL only supports the integer mode. In cascade mode, the ATX PLL only supports fractional mode.

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Figure 170. ATX PLL Block Diagram

Dedicated reference clock pin

Reference clock network

Receiver input pin

Output of another PLL with PLL cascading

Global clock or core clock

CP &

LF

Refclk

Multiplexer

Input reference

clock

N Counter refclk

Up

PFD

Down fbclk

VCO

Delta Sigma

Modulator (1)

Lock

Detector pll_locked

2

L Counter

2

/2

Note:

Input Reference Clock

This is the dedicated input reference clock source for the PLL.

The input reference clock can be sourced from one of the following:

• Dedicated reference clock pin

• Reference clock network

• Receiver input pin

• Output of another PLL with PLL cascading

• Global clock or the core clock network

The input reference clock to the dedicated reference clock pin is a differential signal.

Intel recommends using the dedicated reference clock pin as the input reference clock source for the best jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation and PLL calibration. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.

Sourcing reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to the ATX PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details.

The ATX PLL calibration is clocked by the CLKUSR clock which must be stable and available for calibration to proceed. Refer to the Calibration section for more details about the CLKUSR clock.

Reference Clock Multiplexer

The reference clock

(refclk

) multiplexer selects the reference clock to the PLL from the various reference clock sources available.

N Counter

The N counter divides the

2, 4, and 8.

refclk

mux's output. The division factors supported are 1,


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Phase Frequency Detector (PFD)

The reference clock

(refclk)

signal at the output of the N counter block and the feedback clock

(fbclk)

signal at the output of the M counter block are supplied as inputs to the PFD. The output of the PFD is proportional to the phase difference between the refclk

and fbclk

inputs. It is used to align the refclk

signal at the output of the N counter to the feedback clock

(fbclk)

signal. The PFD generates an

"Up" signal when the reference clock's falling edge occurs before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's falling edge occurs before the reference clock's falling edge.

Charge Pump and Loop Filter

The PFD output is used by the charge pump and loop filter (CP and LF) to generate a control voltage for the VCO. The charge pump translates the "Up" or "Down" pulses from the PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency. The charge pump, loop filter, and VCO settings determine the bandwidth of the ATX PLL.

Lock Detector

The lock detector block indicates when the reference clock and the feedback clock are phase aligned. The lock detector generates an active high pll_locked

signal to indicate that the PLL is locked to its input reference clock.

Voltage Controlled Oscillator

The voltage controlled oscillator (VCO) used in the ATX PLL is LC tank based. The output of charge pump and loop filter serves as an input to the VCO. The output frequency of the VCO depends on the input control voltage. The output frequency is adjusted based on the output voltage of the charge pump and loop filter.

L Counter

The L counter divides the differential clocks generated by the ATX PLL. The L counter is not in the feedback path of the PLL.

M Counter

The M counter's output is the same frequency as the N counter's output. The VCO frequency is governed by the equation:

VCO freq = 2 * M * input reference clock/N

An additional divider divides the high speed serial clock output of the VCO by 2 before it reaches the M counter.

The M counter supports division factors in a continuous range from 8 to 127 in integer frequency synthesis mode and 11 to 123 in fractional mode.

Delta Sigma Modulator

The fractional mode is only supported when the ATX PLL is configured as a cascade source for OTN and SDI protocols. The delta sigma modulator is used in fractional mode. It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis. In fractional mode, the M value is as follows: .

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M (integer) + K/2^32, where K is the Fractional multiply factor (K) in the ATX PLL IP

Parameter Editor

K legal values are 1 through 2^32-1 and can only be manually entered in the ATX PLL

IP Parameter Editor in Quartus Prime software.

The output frequencies can be exact when the ATX PLL is configured in fractional mode. Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz

VCO frequency, not all desired fractional values can be achieved exactly. The lock signal is not available, when configured in fractional mode in k-precision mode (K <

0.1 or K > 0.9).

Multiple Reconfiguration Profiles

Under the ATX PLL IP Parameter Editor Dynamic Reconfiguration tab, in the

Configuration Profiles section, multiple reconfiguration profiles can be enabled. This allows to create, store, and analyze the parameter settings for multiple configurations or profiles of the ATX PLL IP.

The ATX PLL IP GUI can generate configuration files (SystemVerilog, C header or MIF) for a given configuration. With the multi reconfiguration profile options enabled, the

ATX PLL IP Parameter Editor can produce configuration files for all of the profiles simultaneously. In addition, by enabling the reduced reconfiguration files generation, the IP Parameter Editor produces a reduced configuration file by internally comparing the corresponding parameter settings of all the profiles and identifying the differences.

Embedded Reconfiguration Streamer

This option enables a push-button flow to reconfigure between multiple configurations or profiles. Here are the steps to follow:

1. Multiple reconfiguration profiles creation

• In the ATX PLL IP GUI, create configurations for each profiles using the multiprofile feature.

2. Reconfiguration report files

• The IP GUI generates the reconfiguration report files that contain parameter and register settings for all the selected profiles. If the reduced reconfiguration files option is selected, the IP parameter editor compares the settings between the profiles and generate reduced report files which only contain the differences.

3. Select “Enable embedded reconfiguration streamer logic” in the GUI to generate the following:

• Necessary HDL files to perform streaming.

• The individual report files for each profile, an SystemVerilog package file with configuration data for all the profiles concatenated together which is used to initialize the configuration ROM

4. Generate the ATX PLL IP and control the reconfiguration streamer using the AVMM master.


•

Calibration

on page 567

• How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?


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3.1.2.1. Instantiating the ATX PLL IP Core

The Arria 10 transceiver ATX PLL IP core provides access to the ATX PLLs in the hardware. One instance of the PLL IP core represents one ATX PLL in the hardware.

1. Open the Quartus Prime software.

2. Click Tools ➤ IP Catalog.

3. In IP Catalog, under Library ➤

Transceiver PLL

➤

, select Arria 10

Transceiver ATX PLL and click Add.

4. In the New IP Instance dialog box, provide the IP instance name.

5. Select the Arria 10 device family.

6. Select the appropriate device and click OK.

The ATX PLL IP core Parameter Editor window opens.

3.1.2.2. ATX PLL IP Core

Table 229.

ATX PLL Configuration Options, Parameters, and Settings

Parameter


Protocol mode

Range

Error

Warning

Description

Specifies the messaging level to use for parameter rule violations.

• Error—Causes all rule violations to prevent IP generation.

• Warning—Displays all rule violations as warnings and allows IP generation in spite of violations.

Governs the internal setting rules for the VCO.

This parameter is not a preset. You must set all other parameters for your protocol.

Bandwidth

Number of PLL reference clocks

Basic

PCIe* Gen1

PCIe Gen2

PCIe Gen3

SDI_cascade

OTN_cascade

UPI TX

SAS TX

Low

Medium

High

1 to 5

Specifies the VCO bandwidth.

Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection.

Selected reference clock source

Primary PLL clock output buffer

0 to 4

GX clock output buffer

GT clock output buffer

Specifies the number of input reference clocks for the ATX

PLL.

You can use this parameter for data rate reconfiguration.

Specifies the initially selected reference clock input to the

ATX PLL.

Specifies which PLL output is active initially.

• If GX is selected, turn ON "Enable PLL GX clock

output port".

• If GT is selected, turn ON “Enable PLL GT clock

output port".

continued...

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Parameter

Enable PLL GX clock output port (

51

)

Range

On/Off

Enable PCIe clock output port On/Off

Description

Enables the GX output port which feeds x1 clock lines.

You must select this parameter for PLL output frequency less than 8.7 GHz, or if you intend to reconfigure the PLL to a frequency below 8.7 GHz.

Turn ON this port if GX is selected in the "Primary PLL

clock output buffer".

Exposes the

The port should be connected to the port.

pll_pcie_clk port used for PCI Express.

pipe_hclk_input

Enables the ATX to FPLL cascade clock output port.

Enable ATX to FPLL cascade clock output port

Enable fref and clklow port (52) .

PLL output frequency

PLL integer reference clock frequency

Multiply factor (M-Counter)

Divide factor (N-Counter)

Divide factor (L-Counter)

Predivide factor (L-Cascade

Predivider)

Fractional multiply factor (K)

On/Off

On/Off

Refer to Intel

Arria 10 Device

Datasheet .

Refer to the GUI

Enables fref

and clklow

ports for external lock detector.

Use this parameter to specify the target output frequency for the PLL.

Selects the input reference clock frequency for the PLL.

Read only

For

OTN_cascade or

SDI_cascade, refer to the GUI.

Read only

For

SDI_cascade or

OTN_cascade, refer to the GUI.

Displays the M-counter value.

Specifies the M-counter value (In SDI_cascade or

OTN_cascade Protocol mode only).

Displays the N-counter value.

For SDI_cascade or OTN_cascade, refer to the GUI.

Read only Displays the L-counter value.

Refer to the GUI Specifies the L-cascade predivider value. This value must be

2 for a VCO frequency greater than 10.46 GHz and 1 for a

VCO frequency less than 10.46GHz. (In SDI_cascade or

OTN_cascade Protocol mode only).

Read only Displays the actual K-counter value. This parameter is only available in fractional mode.

Table 230.

ATX PLL—Master Clock Generation Block Parameters and Settings

Parameter

Include Master Clock Generation

Block (53)

Range

On/Off

Description

When enabled, includes a master CGB as a part of the ATX

PLL IP core. The PLL output drives the Master CGB.

continued...

(51) You can enable both the GX clock output port and the GT clock output port. However, only one port can be in operation at any given time. You can switch between the two ports using PLL reconfiguration.

(52) The fPLL fref

and clklow

signals should only be used with the Intel external soft lock detection logic.

(53) Manually enable the MCGB for bonding applications.


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Parameter

Clock division factor

Enable x6/xN non-bonded highspeed clock output port

Enable PCIe clock switch interface

Number of auxiliary MCGB clock input ports

MCGB input clock frequency

MCGB output data rate.

Enable bonding clock output ports

Enable feedback compensation bonding

PMA interface width

Range

1, 2, 4, 8

On/Off

On/Off

0, 1

Read only

Read only

On/Off

On/Off

8, 10, 16, 20,

32, 40, 64

Description

This is used for x6/xN bonded and non-bonded modes.

Divides the master CGB clock input before generating bonding clocks.

Enables the master CGB serial clock output port used for x6/xN non-bonded modes.

Enables the control signals for the PCIe clock switch circuitry. Used for PCIe clock rate switching.

Auxiliary input is used to implement the PCIe Gen3 protocol.

Displays the master CGB's input clock frequency.

Displays the master CGB's output data rate.

Enables the tx_bonding_clocks

output ports of the master CGB used for channel bonding.

This option should be turned ON for bonded designs.

Enables this setting when using feedback compensation bonding. For more details about feedback compensation bonding, refer to the PLL Feedback Compensation Bonding section later in the document.

Specifies PMA-PCS interface width.

Match this value with the PMA interface width selected for the Native PHY IP core. You must select a proper value for generating bonding clocks for the Native PHY IP core.

Table 231.

ATX PLL—Dynamic Reconfiguration

Parameter

Enable reconfiguration

Range

On/Off


Endpoint

Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE





On/Off

On/Off

On/Off

User-defined

On/Off

Description

Enables the PLL reconfiguration interface. Enables the simulation models and adds Avalon compliant ports for reconfiguration.

When you turn on this option, the Transceiver PLL IP core includes an embedded Altera Debug Master Endpoint

(ADME) that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System

Console. Refer to the Reconfiguration Interface and

Dynamic Reconfiguration chapter for more details.

When enabled, the reconfig_waitrequest

does not indicate the status of AVMM arbitration with PreSICE. The

AVMM arbitration status is reflected in a soft status register bit. (Only available if "Enable control and status registers feature" is enabled).

Enables capability registers that provide high-level information about the ATX PLL's configuration.

Sets a user-defined numeric identifier that can be read from the user_identifier are enabled.

offset when the capability registers

Enables soft registers for reading status signals and writing control signals on the PLL interface through the embedded debug logic.

Enter the prefix name for the configuration files to be generated.

continued...

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Parameter



Enable multiple reconfiguration profiles

Enable embedded reconfiguration streamer

Generate reduced reconfiguration files

Number of reconfiguration profiles

Store current configuration to profile

Generate MIF (Memory Initialize

File)

Range

On/Off

On/Off

On/Off

On/Off

On/Off

1 to 8

0 to 7

On/Off

Description

Generates a SystemVerilog package file containing all relevant parameters used by the PLL.

Generates a C header file containing all relevant parameters used by the PLL.

Enables multiple configuration profiles to be stored.

Enables embedded reconfiguration streamer which automates the dynamic reconfiguration process between multiple predefined configuration profiles.

When enabled, the IP generates reconfiguration report files containing only the setting differences between the multiple reconfiguration profiles

Specifies the number of reconfiguration profiles

Specifies which configuration profile to modify (store, load, clear or refresh) when clicking the corresponding action button.

Generates a MIF file which contains the current configuration.

Use this option for reconfiguration purposes in order to switch between different PLL configurations.

Table 232.

ATX PLL—Generation Options

Parameter


Range

On/Off

Table 233.

ATX PLL IP Core Ports pll_powerdown

Port Direction

Input

Description

Generates a .csv file which contains descriptions of ATX PLL

IP core parameters and values.

pll_refclk0 pll_refclk1 pll_refclk2 pll_refclk3 pll_refclk4 tx_serial_clk

Input

Input

Input

Input

Input

Output

Clock Domain

Asynchronous

N/A

N/A

N/A

N/A

N/A

N/A

Description

Resets the PLL when asserted high.

Needs to be connected to a dynamically controlled signal (the

Transceiver PHY Reset Controller pll_powerdown output if using this

Intel FPGA IP).

Reference clock input port 0.

There are a total of five reference clock input ports. The number of reference clock ports available depends on the

Number of PLL reference clocks parameter.





High speed serial clock output port for

GX channels. Represents the x1 clock network.

continued...


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Port tx_serial_clk_gt pll_locked pll_pcie_clk reconfig_clk0 reconfig_reset0 reconfig_write0 reconfig_read0 reconfig_address0[9:0] reconfig_writedata0[31:0] reconfig_readdata0[31:0] reconfig_waitrequest0 pll_cal_busy mcgb_rst mcgb_aux_clk0 tx_bonding_clocks[5:0] mcgb_serial_clk

Direction

Output

Output

Output

Input

Input

Input

Input

Input

Input

Output

Output

Output

Input

Input

Output

Output


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Clock Domain

N/A

Asynchronous

N/A

N/A reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0

Asynchronous

Asynchronous

N/A

N/A

N/A

Description


GT channels. Represents the GT clock network.

Active high status signal which indicates if the PLL is locked.

Used for PCIe. (54)

Optional Avalon interface clock. Used for PLL reconfiguration. The reconfiguration ports appear only if the

Enable Reconfiguration parameter is selected in the PLL IP Core GUI. When this parameter is not selected, the ports are set to OFF internally.

Used to reset the Avalon interface.

Asynchronous to assertion and synchronous to deassertion.

Active high write enable signal.

Active high read enable signal.

10-bit address bus used to specify address to be accessed for both read and write operations.

32-bit data bus. Carries the write data to the specified address.

32-bit data bus. Carries the read data from the specified address.

Indicates when the Avalon interface signal is busy. When asserted, all inputs must be held constant.

Status signal which is asserted high when PLL calibration is in progress.

OR this signal with before connecting to the reset controller IP.

tx_cal_busy

port

Master CGB reset control.

Deassert this reset at the same time as pll_powerdown

.

Used for PCIe implementation to switch between fPLL and ATX PLL during link speed negotiation.

Optional 6-bit bus which carries the low speed parallel clock outputs from the master CGB. Each transceiver channel in a bonded group has this 6bit bus.

Used for channel bonding, and represents the x6/xN clock network.

High speed serial clock output for x6/xN non-bonded configurations.

continued...

(54) Connect this clock to hclk

in PCIe applications.

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pcie_sw[1:0]

Port pcie_sw_done[1:0] atx_to_fpll_cascade_clk ext_lock_detect_clklow

( 55

)

ext_lock_detect_fref

( 55

)

Direction

Input

Output

Output

Output

Output

Clock Domain

Asynchronous

Asynchronous

N/A

N/A

N/A

Description

2-bit rate switch control input used for

PCIe protocol implementation.

2-bit rate switch status output used for

PCIe protocol implementation.

The ATX PLL output clock is used to drive fPLL reference clock input (only available in SDI_cascade or

OTN_cascade protocol mode).

Clklow

output for external lock detection. It can be exposed by selecting the Enable clklow and fref port

Fref output for external lock detection.

It can be exposed by selecting the

Enable clklow and fref port.


•

Calibration

on page 29

• Avalon Interface Specifications

The ports related to reconfiguration are compliant with the Avalon specification.

Refer to the Avalon specification for more details about these ports.

• Intel Arria 10 Device Datasheet

Refer to the Intel Arria 10 Device Datasheet for more details about the PLL output frequency range.

•

Reconfiguration Interface and Dynamic Reconfiguration

on page 502

•

Reconfiguring Channel and PLL Blocks on page 503

•

Steps to Perform Dynamic Reconfiguration

on page 516

• Intel Arria 10 device fPLL reports an unlocked condition

3.1.3. fPLL

There are two fPLLs in each transceiver bank with six channels (one located at the top and the other at the bottom of the bank). Transceiver banks with three channels have only one fPLL.

Figure 171. fPLL Block Diagram

Dedicated Reference Clock Pin

Reference Clock Network

Receiver Input Pin

Output of Another PLL with PLL Cascading

Global Clock or Core Clock

Refclk

Multiplexer

Input

Reference

Clock

N Counter refclk

PFD

Up

Down

Charge

Pump and

Loop Filter fbclk

VCO /2

/2

L Counter

/1, 2, 4, 8

M Counter

Delta Sigma

Modulator

C Counter

(55)

The fPLL fref

and detection logic.

clklow

signals should only be used with the Intel external soft lock


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Note:


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When in core mode, for the fPLL to generate output clocks with a fixed frequency and phase relation to an input reference clock, the Enable phase alignment option must be selected. In the fractional frequency mode, the fPLL supports data rates from 1

Gbps to 12.5 Gbps.


This is the dedicated input reference clock source for the PLL.

The input reference clock can be sourced from one of the following:

• Dedicated reference clock pin


• Receiver input pin

• Output of another PLL with PLL cascading

• Global clock or the core clock network

The input reference clock is a differential signal. Intel recommends using the dedicated reference clock pin as the input reference clock source for best jitter performance. For protocol jitter compliance at data rates > 10 Gbps, Intel recommends using the dedicated reference clock pin in the same triplet with the fPLL as the input reference clock source.The input reference clock must be stable and freerunning at device power-up for proper PLL operation. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.

Sourcing reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to the fPLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details.

The fPLL calibration is clocked by the CLKUSR clock, which must be stable and

available for the calibration to proceed. Refer to the Calibration on page 567 section

for details about PLL calibration and CLKUSR clock.

Reference Clock Multiplexer

The refclk

mux selects the reference clock to the PLL from the various available reference clock sources.

N Counter

The N counter divides the reference clock ( refclk

) mux's output. The N counter division helps lower the loop bandwidth or reduce the frequency within the phase frequency detector's (PFD) operating range. The N counter supports division factors from 1 to 32.

Phase Frequency Detector

The reference clock

(refclk)

signal at the output of the N counter block and the feedback clock

(fbclk)

signal at the output of the M counter block are supplied as an inputs to the PFD. The output of the PFD is proportional to the phase difference between the refclk

and fbclk

inputs. The PFD aligns the fbclk

to the refclk

The PFD generates an "Up" signal when the reference clock's falling edge occurs

.

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before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's falling edge occurs before the reference clock's falling edge.

Charge Pump and Loop Filter (CP + LF)

The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the

PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency.

Voltage Controlled Oscillator

The fPLL has a ring oscillator based VCO. The VCO transforms the input control voltage into an adjustable frequency clock.

VCO freq = 2 * M * Input reference clock/N. (N and M are the N counter and M counter division factors.)

L Counter

The L counter divides the VCO's clock output. When the fPLL acts as a transmit PLL, the output of the L counter drives the clock generation block (CGB) and the TX PMA via the X1 clock lines.

M Counter

The M counter divides the VCO's clock output. The M counter can select any VCO phase. The outputs of the M counter and N counter have same frequency. M counter range is 8 to 127 in integer mode and 11 to 123 in fractional mode.

Delta Sigma Modulator

The delta sigma modulator is used in fractional mode. It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis.

In fractional mode, the M value is as follows:

M (integer) + K/2^32, where K is the fractional multiply factor (K) in the fPLL IP

Parameter Editor. The legal values of K are greater than 1% and less than 99% of the full range of 2^32 and can only be manually entered in the fPLL IP Parameter Editor in the Quartus Prime software.

The output frequencies can be exact when the fPLL is configured in fractional mode.

Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz VCO frequency, not all desired fractional values can be achieved exactly. The lock signal is not available, when configured in fractional mode in the K-precision mode (K < 0.1 or

K > 0.9).

C Counter

The fPLL C counter division factors range from 1 to 512.

Dynamic Phase Shift

The dynamic phase shift block allows you to adjust the phase of the C counters in user mode. In fractional mode, dynamic phase shift is only available for the C counters.


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Latency

The C counters can be configured to select any VCO phase and a delay of up to 128 clock cycles. The selected VCO phase can be changed dynamically.


•

Calibration

on page 567

•

Calibration

on page 567

Details about PLL calibration

• How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?

3.1.3.1. Instantiating the fPLL IP Core

The fPLL IP core for Arria 10 transceivers provides access to fPLLs in hardware. One instance of the fPLL IP core represents one fPLL in the hardware.



3. In IP Catalog, under Library

➤

Transceiver PLL , select Arria 10 Transceiver

fPLL IP core and click Add.

4. In the New IP Instance dialog box, provide the IP instance name.

5. Select the Arria 10 device family.


The fPLL IP core Parameter Editor window opens.

3.1.3.2. fPLL IP Core

Table 234.

fPLL IP Core Configuration Options, Parameters, and Settings fPLL Mode

Parameters

Protocol Mode

Range

Core

Cascade Source

Transceiver

Description

Specifies the fPLL mode of operation.

Select Core to use fPLL as a general purpose PLL to drive the FPGA core clock network.

Select Cascade Source to connect an fPLL to another PLL as a cascading source.

Select Transceiver to use an fPLL as a transmit PLL for the transceiver block.

Governs the internal setting rules for the VCO.

This parameter is not a preset. You must set all parameters for your protocol.

Enable fractional mode

Basic

PCIe* Gen1

PCIe Gen2

PCIe Gen3

SDI_cascade

OTN_cascade

SDI_direct

SATA TX

OTN_direct

SATA_Gen3

HDMI

On/Off Enables the fractional frequency mode.

continued...

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Divide factor (N-counter)

Divide factor (L-counter)

Divide factor (K-counter)


PLL Datarate

Parameters

Enable physical output clock parameters

Enable clklow and fref ports (56)

Desired Reference clock frequency

Actual reference clock frequency


New parameter: Selected reference clock source

Bandwidth

Operation mode

Multiply factor (M-counter)

Range

On/Off

On/Off

Description

This enables the PLL to output frequencies which are not integral multiples of the input reference clock.

Selecting this option allows you to manually specify M, N, C and L counter values.

Enables fref and clklow clock ports for external lock detector. In Transceiver mode when "enable fractional mode" and "SDI_direct" prot_mode are selected,

pll_locked port is not available and user can create external lock detector using fref and clklow clock ports.

Refer to the GUI Specifies the desired PLL input reference clock frequency.

Read-only Displays the actual PLL input reference clock frequency.

1 to 5

0 to 4

Specify the number of input reference clocks for the fPLL.

Specifies the initially selected reference clock input to the fPLL.



Low

Medium

High

Direct

Feedback compensation bonding

8 to 127

(integer mode)

11 to 123

(fractional mode)

Specifies the feedback operation mode for the fPLL.

Specifies the multiply factor (M-counter).

1 to 31

1, 2, 4, 8

User defined

Read-only

Read-only

Specifies the divide factor (N-counter).

Specifies the divide factor (L-counter).

Specifies the divide factor (K-counter).

Displays the target output frequency for the PLL.

Displays the PLL datarate.

Table 235.

fPLL—Master Clock Generation Block Parameters and Settings

Parameters

Include Master Clock Generation

Block

Clock division factor

Enable x6/xN non-bonded highspeed clock output port

Enable PCIe clock switch interface

Range

On/Off

1, 2, 4, 8

On/Off

On/Off

Description

When enabled, includes a master CGB as a part of the fPLL

IP core. The PLL output drives the master CGB.

This is used for x6/xN bonded and non-bonded modes.

Divides the master CGB clock input before generating bonding clocks.

Enables the master CGB serial clock output port used for x6/xN non-bonded modes.

Enables the control signals used for PCIe clock switch circuitry.

continued...

(56)

The fPLL fref


clklow



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Parameters

MCGB input clock frequency

MCGB output data rate

Enable bonding clock output ports

Enable feedback compensation bonding

PMA interface width

Range

Read only

Read only

On/Off

On/Off

8, 10, 16, 20,

32, 40, 64

Description

Displays the master CGB’s required input clock frequency.

You cannot set this parameter.

Displays the master CGB’s output data rate. You cannot set this parameter.

This value is calculated based on MCGB input clock frequency and MCGB clock division factor.

Enables the tx_bonding_clocks

output ports of the

Master CGB used for channel bonding.

You must enable this parameter for bonded designs.

Enables the feedback output path of the master CGB used for feedback compensation bonding. When enabled, the feedback connections are automatically handled by the PLL

IP.

Specifies the PMA-PCS interface width.

Match this value with the PMA interface width selected for the Native PHY IP core. You must select a proper value for generating bonding clocks for the Native PHY IP core.

Table 236.

fPLL—Dynamic Reconfiguration Parameters and Settings

Parameter

Enable reconfiguration


Endpoint






Generate SystemVerilog package

file



File)

Range

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

Description

Enables the PLL reconfiguration interface. Enables the simulation models and adds more ports for reconfiguration.

When you turn this option ON, the transceiver PLL IP core includes an embedded Altera Debug Master Endpoint

(ADME) that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System






Enables capability registers that provide high-level information about the fPLL's configuration.







Generates a MIF file that contains the current configuration.


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Table 237.

Clock Switchover (between Dynamic Reconfiguration and General Options)

Clock Switchover Parameter

Create a second input clock pllrefclk1

Second Reference Clock Frequency User Defined

Switchover Mode

Switchover Delays

Create an active_clk signal to indicate the input clock in use

Create a clkbad signal for each of the input clocks

On/Off

Automatic Switchover

Manual Switchover

Automatic Switchover with Manual

Override

0 to 7

On/Off

On/Off

Range Description

Turn on this parameter to have a backup clock attached to your fPLL that can switch with your original reference clock

Specifies the second reference clock frequency for fPLL

Specifies how Input frequency switchover is handled. Automatic

Switchover uses built in circuitry to detect if one of your input clocks has stopped toggling and switch to the other.

Manual Switchover creates an

EXTSWITCH

signal which can be used to manually switch the clock by asserting high for at least 3 cycles.

Automatic Switchover with Manual

Override acts as Automatic Switchover until the

EXTSWITCH

goes high, in which case it switches and ignores any automatic switches as long as

EXTSWITCH

stays high.

Adds a specific amount of cycle delay to the Switchover Process.

This parameter creates an output that indicates which input clock is currently in use by the PLL. Low indicates refclk

, High indicates refclk1.

This parameter creates two outputs, one for each input clock. Low indicates the

CLK clkbad

is working, High indicates the

CLK

is not working.

Table 238.

fPLL - Generation Options

Parameter

Generates parameter documentation file

Direction

On/Off

Description

Generates a .csv file that contains descriptions of all the fPLL parameters and values.

Table 239.

fPLL IP Core Ports

Port pll_powerdown

Direction input

Clock Domain

Asynchronous pll_refclk0

pll_refclk1 input input

N/A

N/A

Description


Needs to be connected to a dynamically controlled signal (the

Transceiver PHY Reset Controller pll_powerdown output if using this

Intel FPGA IP).


There are five reference clock input ports. The number of reference clock ports available depends on the



continued...


365

pll_refclk2 pll_refclk3 pll_refclk4 tx_serial_clk

Port pll_locked hssi_pll_cascade_clk pll_pcie_clk reconfig_clk0 reconfig_reset0 reconfig_write0 reconfig_read0 reconfig_address0[9:0] reconfig_writedata0[31:0] reconfig_readdata0[31:0] reconfig_waitrequest0 pll_cal_busy mcgb_rst mcgb_aux_clk0 tx_bonding_clocks[5:0] mcgb_serial_clk pcie_sw[1:0]

Direction input input input output output output output input input input input input input output output output input input output output input


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Clock Domain

N/A

N/A

N/A

N/A

Asynchronous

N/A

N/A

N/A reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0 reconfig_clk0

Asynchronous

Asynchronous

N/A

N/A

N/A

Asynchronous

Description




High speed serial clock output port for GX channels. Represents the x1 clock network.


fPLL cascade clock output port

Used for PCIe.

Optional Avalon interface clock. Used for PLL reconfiguration.









Status signal which is asserted high when PLL calibration is in progress.

Perform logical OR with this signal and the tx_cal_busy reset controller IP.

port on the

Master CGB reset control.

Deassert this reset at the same time as pll_powerdown

.

Used for PCIe to switch between fPLL/ATX PLL during link speed negotiation.

Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB.

Used for channel bonding, and represents the x6/xN clock network.

High speed serial clock output for x6/xN non-bonded configurations.

2-bit rate switch control input used for PCIe protocol implementation.

continued...

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Port pcie_sw_done[1:0] atx_to_fpll_cascade_clk fpll_to_fpll_cascade_clk active_clk outclk0 outclk1 outclk2 outclk3 ext_lock_detect_clklow

( 57

) ext_lock_detect_fref

( 57

) phase_reset phase_en updn cntsel[3:0]

Direction output input output output output output output output output output input input input input

Clock Domain

Asynchronous

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Description

2-bit rate switch status output used for PCIe protocol implementation.

Enables fPLL to ATX PLL cascading clock input port.

fPLL to fPLL cascade output port

(only in Core mode)

Creates an output signal that indicates the input clock being used by the PLL. A logic Low on this signal indicates refclk0

is being used and a logic High indicates refclk1

Clock Switchover enabled)

is being used (only in Core mode with

Core output clock 0. (only in Core mode)

There are four core fPLL output clock output ports. The number of output clock available depends on the





Clklow output for external lock detection. It can be exposed by selecting the Enable clklow and

fref port.

Fref output for external lock detection It can be exposed by selecting the Enable clklow and fref port.

Dynamic phase shift reset input signal. To be connected to DPS soft

IP phase_reset output.

Dynamic phase shift enable input signal. To be connected to DPS soft

IP phase_en output.

Dynamic phase shift updn input signal. To be connected to DPS soft

IP updn output.

Dynamic phase shift counter bus. To be connected to DPS soft IP cntsel output bus.


•

Calibration

on page 29

•


on page 502

(57)

The fPLL fref


clklow



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The ports related to reconfiguration are compliant with the Avalon

Specification. Refer to the Avalon Specification for more details about these ports.

• Intel Arria 10 device fPLL reports an unlocked condition

3.1.4. CMU PLL

The clock multiplier unit (CMU) PLL resides locally within each transceiver channel.The

channel PLL's primary function is to recover the receiver clock and data in the transceiver channel. In this case the PLL is used in clock and data recovery (CDR) mode.

When the channel PLL of channels 1 or 4 is configured in the CMU mode, the channel

PLL can drive the local clock generation block (CGB) of its own channel, then the channel cannot be used as a receiver.

The CMU PLL from transceiver channel 1 and channel 4 can also be used to drive other transceiver channels within the same transceiver bank. The CDR of channels 0, 2, 3, and 5 cannot be configured as a CMU PLL.

For datarates lower than 6 Gbps, the local CGB divider has to be engaged (TX local division factor in transceiver PHY IP under the TX PMA tab) .

Figure 172. CMU PLL Block Diagram

User Control

(LTR/LTD)

Lock to

Reference

Controller

Lock

Detector

Lock to Reference

PLL Lock Status

Note:

Reference clock network

Receiver input pin

Refclk

Multiplexer

Input reference

clock

N Counter

CP &

LF refclk

Up

PFD

Down fbclk

VCO L Counter

M Counter

Output


The input reference clock for a CMU PLL can be sourced from either the reference clock network or a receiver input pin. The input reference clock is a differential signal.

For protocol jitter compliance at data rates > 10 Gbps, Intel recommends using the dedicated reference clock pin in the same triplet with the CMU PLL as the input reference clock source.The input reference clock must be stable and free-running at device power-up for proper PLL operation. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available. Refer to the Calibration section for details about PLL calibration and the

CLKUSR

clock requirement.

The CMU PLL calibration is clocked by the

CLKUSR

clock which must be stable and available for calibration to proceed. Refer to the Calibration section for more details about the

CLKUSR

clock.

Reference Clock Multiplexer (Refclk Mux)

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The refclk mux selects the input reference clock to the PLL from the various reference clock sources available.

N Counter

The N counter divides the refclk mux's output. The N counter division helps lower the loop bandwidth or reduce the frequency to within the phase frequency detector's

(PFD) operating range. Possible divide ratios are 1 (bypass), 2, 4, and 8.

Phase Frequency Detector (PFD)

The reference clock

(refclk)

signal at the output of the N counter block and the feedback clock ( fbclk

) signal at the output of the M counter block is supplied as an input to the PFD. The PFD output is proportional to the phase difference between the two inputs. It aligns the input reference clock ( refclk

) to the feedback clock

( fbclk

). The PFD generates an "Up" signal when the reference clock's falling edge occurs before the feedback clock's falling edge. Conversely, the PFD generates a

"Down" signal when feedback clock's falling edge occurs before the reference clock's falling edge.

Charge Pump and Loop Filter (CP + LF)

The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the

PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage which drives the VCO frequency.

Voltage Controlled Oscillator (VCO)

The CMU PLL has a ring oscillator based VCO. For VCO frequency range, refer to the datasheet.

L Counter

The L counter divides the differential clocks generated by the CMU PLL.

M Counter

The M counter is used in the PFD's feedback path. The output of the L counter is connected to the M counter. The combined division ratios of the L counter and the M counter determine the overall division factor in the PFD's feedback path.

Lock Detector (LD)

The lock detector indicates when the CMU PLL is locked to the desired output's phase and frequency. The lock detector XORs the "Up"/"Down" pulses and indicates when the

M counter's output and N counter's output are phase-aligned.

The reference clock ( too high.

refclk

) and feedback clock ( fbclk

) are sent to the PCS's ppm detector block. There is a pre-divider to lower the frequency in case the frequency is


•

Calibration

on page 567

• IntelArria 10 Device Datasheet


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3.1.4.1. Instantiating CMU PLL IP Core

The CMU PLL IP core for Arria 10 transceivers provides access to the CMU PLLs in hardware. One instance of the CMU PLL IP core represents one CMU PLL in hardware.



3. In IP Catalog, under Library ➤

Transceiver PLL , select Arria 10 Transceiver

CMU PLL and click Add.

4. In the New IP Instance Dialog Box, provide the IP instance name.

5. Select Arria 10 device family.


The CMU PLL IP core Parameter Editor window opens.

3.1.4.2. CMU PLL IP Core

Table 240.

CMU PLL Parameters and Settings

Parameters


Range

Error

Warning

Bandwidth


Low

Medium

High

1 to 5

Description

Specifies the messaging level to use for parameter rule violations.

• Error - Causes all rule violations to prevent IP generation.

• Warning - Displays all rule violations as warnings and allows IP generation in spite of violations.




TX PLL Protocol mode

PLL reference clock frequency

PLL output frequency

Multiply factor (M-Counter)

Divide factor (N-Counter)

Divide factor (L-Counter)

0 to 4

BASIC

PCIe

Refer to the GUI

Refer to the GUI

Read only

Read only

Read only

Specifies the number of input reference clocks for the CMU

PLL.

You can use this parameter for data rate reconfiguration.

Specifies the initially selected reference clock input to the

CMU PLL.

This parameter governs the rules for correct protocol specific settings. Certain features of the PLL are only available for specific protocol configuration rules. This parameter is not a preset .

You must set all the other parameters for your protocol.

Selects the input reference clock frequency for the PLL.

Specify the target output frequency for the PLL.

Displays the M-multiplier value.

Displays the N-counter value.

Displays the L-counter value.

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Table 241.

CMU PLL—Dynamic Reconfiguration

Parameters


Range

On/Off


Endpoint









File)

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

On/Off

Description

Enables the PLL reconfiguration interface. Enables the simulation models and adds more ports for reconfiguration.

When you turn this option On, the transceiver PLL IP core includes an embedded Altera Debug Master Endpoint that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System






Enables capability registers that provide high- level information about the CMU PLL's configuration.







Generates a MIF file that contains the current configuration.


Table 242.

CMU PLL—Generation Options

Parameters


Range

On/Off

Table 243.

CMU PLL IP Ports

Port pll_powerdown pll_refclk0

Range input input pll_refclk1 pll_refclk2 input input

Description

Generates a .csv file which contains the descriptions of all

CMU PLL parameters and values.

Clock Domain

Asynchronous

N/A

N/A

N/A

Description



There are 5 reference clock input ports. The number of reference clock ports available depends on the




continued...


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pll_refclk3 pll_refclk4 tx_serial_clk

Port pll_locked reconfig_clk0 reconfig_reset0 reconfig_write0 reconfig_read0 reconfig_address0[9:0] reconfig_writedata0[31:0] reconfig_readdata0[31:0] reconfig_waitrequest0 pll_cal_busy

Range input input output output input input input input input input output output output

Clock Domain

N/A

N/A

Description



N/A

Asynchronous

N/A


GX channels. Represents the x1 clock network.


Optional Avalon interface clock. Used for PLL reconfiguration. The reconfiguration ports appear only if the

Enable Reconfiguration parameter is selected in the PLL IP Core GUI. When this parameter is not selected, the ports are set to OFF internally.

reconfig_clk0



reconfig_clk0


reconfig_clk0


reconfig_clk0


reconfig_clk0


reconfig_clk0


reconfig_clk0


Asynchronous Status signal that is asserted high when PLL calibration is in progress.

Perform logical OR with this signal and the tx_cal_busy controller IP.

port on the reset


•

Calibration

on page 29

•


on page 502


The ports related to reconfiguration are compliant with the Avalon

Specification. Refer to the Avalon Specification for more details about these ports.

3.2. Input Reference Clock Sources

The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.

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Arria 10 transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:

• Dedicated reference clock pins


• The output of another fPLL with PLL cascading (

58 )

• Receiver input pins

• Global clock or core clock

( 58

)

For the best jitter performance, Intel recommends placing the reference clock as close as possible, to the transmit PLL. For protocol jitter compliance at data rates > 10

Gbps, place the reference clock pin in the same triplet as the transmit PLL.

The following protocols require the reference clock to be placed in same bank as the transmit PLL:

• OTU2e, OTU2, OC-192 and 10G PON

• 6G and 12G SDI

Note: Sourcing a reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to transmit PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details.

For optimum performance of GT channel, the reference clock of transmit PLL is recommended to be from a dedicated reference clock pin in the same bank.

Figure 173. Input Reference Clock Sources

Reference Clock

Network

Dedicated refclk pin

(2)

Input

Reference

Clock

fPLL

Serial Clock

RX pin 2

RX pin 1

RX pin 0

(1) fPLL or ATX PLL

(3) Global or

Core Clock

Note:

Note : (1) You can choose only one of the three RX pins to be used as an input reference clock source. Any RX pin on the same side

of the device can be used as an input reference clock.

(2) Dedicated refclk pin can be used as an input reference clock source only for ATX or fPLL or to the reference clock network.

Reference clock network can then drive the CMU PLL.

(3) The output of another PLL can be used as an input reference clock source during PLL cascading. Arria 10 transceivers support fPLL to fPLL cascading.

• In Arria 10 devices, the FPGA fabric core clock network can be used as an input reference source for any PLL type.

• To successfully complete the calibration process, the reference clocks driving the

PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of

FPGA configuration. Otherwise, recalibration is necessary.

(58) Not available for CMU.


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Calibration

on page 567

For more information about the calibration process

3.2.1. Dedicated Reference Clock Pins

To minimize the jitter, the advanced transmit (ATX) PLL and the fractional PLL (fPLL) can source the input reference clock directly from the reference clock buffer without passing through the reference clock network. The input reference clock is also fed into the reference clock network.

Figure 174. Dedicated Reference Clock Pins

There are two dedicated reference clock ( refclk

) pins available in each transceiver bank. The bottom refclk pin feeds the bottom ATX PLL, fPLL, and CMU PLL. The top refclk

pin feeds the top ATX PLL, fPLL, and CMU

PLL. The dedicated reference clock pins can also drive the reference clock network.

Reference Clock

Network fPLL1

From PLL

Cascading Clock

Network

CH5

CDR PLL

CH4

CMU PLL

CH3

CDR PLL

Reference Clock

Network

ATX PLL1

Refclk

From PLL Feedback and Cascading Clock

Network fPLL0

From PLL

Cascading Clock

Network

CH2

CDR PLL

CH1

CMU PLL

CH0

CDR PLL

Reference Clock

Network

Input Reference Clock to the PLLs

Can Come from Either the Reference

Clock Network or the PLL Feedback and Cascading Clock Network

ATX PLL0

From PLL Feedback and Cascading Clock

Network

Refclk

ATX and fPLL Can Receive the

Input Reference Clock from a

Dedicated refclk Pin

3.2.2. Receiver Input Pins

Receiver input pins can be used as an input reference clock source to transceiver PLLs.

However, they cannot be used to drive core fabric.

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The receiver input pin drives the feedback and cascading clock network, which can then feed any number of transmitter PLLs on the same side of the device. When a receiver input pin is used as an input reference clock source, the clock data recovery

(CDR) block of that channel is not available. As indicated in Figure 173 on page 373,

only one RX differential pin pair per three channels can be used as an input reference clock source at any given time.

3.2.3. PLL Cascading as an Input Reference Clock Source

In PLL cascading, PLL outputs are connected to the feedback and cascading clock network. The input reference clock to the first PLL can be sourced from the same network. In this mode, the output of one PLL drives the reference clock input of another PLL. PLL cascading can generate frequency outputs not normally possible with a single PLL solution. The transceiver in Arria 10 devices support fPLL to fPLL cascading, with only maximum two fPLLs allowed in the cascading chain. ATX PLL to fPLL cascading is available to OTN and SDI protocols only.

Note: • To successfully complete the calibration process, the reference clocks driving the

PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of

FPGA configuration. Otherwise, recalibration is necessary.

• When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.


Calibration

on page 567


3.2.4. Reference Clock Network

The reference clock network distributes a reference clock source to either the entire left or right side of the FPGA where the transceivers reside. This allows any reference clock pin to drive any transmitter PLL on the same side of the device. Designs using multiple transmitter PLLs which require the same reference clock frequency and are located along the same side of the device, can share the same dedicated reference clock ( refclk

) pin.

3.2.5. Global Clock or Core Clock as an Input Reference Clock

The global clock or the core clock can be used as an input reference clock for any PLL type.

The global or core clock network routes the clock directly to the PLL. In this case the

PLL reference clock network is not used. For best performance, use the dedicated reference clock pins or the reference clock network.

3.3. Transmitter Clock Network

The transmitter clock network routes the clock from the transmitter PLL to the transmitter channel. It provides two types of clocks to the transmitter channel:

• High Speed Serial clock—high-speed clock for the serializer.

• Low Speed Parallel clock—low-speed clock for the serializer and the PCS.


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In a bonded channel configuration, both the serial clock and the parallel clock are routed from the transmitter PLL to the transmitter channel. In a non-bonded channel configuration, only the serial clock is routed to the transmitter channel, and the parallel clock is generated locally within the channel. To support various bonded and non-bonded clocking configurations, four types of transmitter clock network lines are available:

• x1 clock lines

• x6 clock lines

• xN clock lines

• GT clock lines


Unused/Idle Clock Line Requirements on page 389

For more information about unused or idle transceiver clock lines in the design.

3.3.1. x1 Clock Lines

The x1 clock lines route the high speed serial clock output of a PLL to any channel within a transceiver bank. The low speed parallel clock is then generated by that particular channel's local clock generation block (CGB). Non-bonded channel configurations use the x1 clock network.

The x1 clock lines can be driven by the ATX PLL, fPLL, or by either one of the two channel PLLs (channel 1 and 4 when used as a CMU PLL) within a transceiver bank.

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Figure 175. x1 Clock Lines x1 Network

Ch 5

CGB fPLL1

Master

CGB

CDR

Ch 4

CGB

ATX PLL1 CMU or CDR

Ch 3

CGB

CDR

Ch 2

CGB fPLL0

Master

CGB

CDR

Ch 1

CGB

ATX PLL0 CMU or CDR

Ch 0

CGB

CDR

3.3.2. x6 Clock Lines

The x6 clock lines route the clock within a transceiver bank. The x6 clock lines are driven by the master CGB. The master CGB can only be driven by the ATX PLL or the fPLL. Because the CMU PLLs cannot drive the master CGB, the CMU PLLs cannot be used for bonding purposes. There are two x6 clock lines per transceiver bank, one for each master CGB. Any channel within a transceiver bank can be driven by the x6 clock lines.


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For bonded configuration mode, the low speed parallel clock output of the master CGB is used and the local CGB within each channel is bypassed. For non-bonded configurations, the master CGB also provides a high speed serial clock output to each channel without bypassing the local CGB within each channel.

The x6 clock lines also drive the xN clock lines which route the clocks to the neighboring transceiver banks.

Figure 176. x6 Clock Lines x6

Top x6

Network x6

Bottom

CGB

Ch 5

CDR

Ch 4

CGB

Master

CGB

CGB

CMU or CDR

Ch 3

CDR

Ch 2

CGB

CDR

Ch 1

CGB

Master

CGB

CGB

CMU or CDR

Ch 0

CDR

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3.3.3. xN Clock Lines

The xN clock lines route the transceiver clocks across multiple transceiver banks.

The master CGB drives the x6 clock lines and the x6 clock lines drive the xN clock lines. There are two xN clock lines: xN Up and xN Down. xN Up clock lines route the clocks to transceiver banks located above the master CGB and xN Down clock lines route the clocks to transceiver banks located below the master CGB. The xN clock lines can be used in both bonded and non-bonded configurations. For bonded configurations, the low speed parallel clock output of the master CGB is used, and the local CGB within each channel is bypassed. For non-bonded configurations, the master

CGB provides a high speed serial clock output to each channel.


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Figure 177. xN Clock Network

Master

CGB1

Master

CGB0 xN Up xN Down x6

Top x6

Bottom

CGB

CGB

CGB

CGB

CGB

CGB

CMU or CDR

Ch 3

CDR

Ch 2

Ch 5

CDR

Ch 4

CDR

Ch 1

CMU or CDR

Ch 0

CDR xN Up xN Down

The maximum channel span of a xN clock network is two transceiver banks above and two transceiver banks below the bank that contains the driving PLL and the master

CGB. A maximum of 30 channels can be used in a single bonded or non-bonded xN group.

The maximum data rate supported by the xN clock network while driving channels in either the bonded or non-bonded mode depends on the voltage used to drive the transceiver banks.

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•

Implementing x6/xN Bonding Mode

on page 404

•

x6/xN Bonding

on page 389

• IntelArria 10 Device Datasheet

3.3.4. GT Clock Lines

GT clock lines are dedicated clock lines available only in Arria 10 GT devices.

Each ATX PLL has two dedicated GT clock lines that connect the PLL directly to the transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and

4, and the bottom ATX PLL drives channels 0 and 1. These connections bypass the rest of the clock network for higher performance. These channels can be used only for non-bonded configurations.


381

Figure 178. GT Clock Lines

ATX PLL1

ATX PLL0

CGB

CGB

CGB

CGB

CGB

CGB


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Ch 5

CDR

Ch 4

CMU or CDR

Ch 3

CDR

Ch 2

CDR

Ch 1

CMU or CDR

Ch 0

CDR

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3.4. Clock Generation Block

In Arria 10 devices, there are two types of clock generation blocks (CGBs)

• Local clock generation block (local CGB)

• Master clock generation block (master CGB)

Each transmitter channel has a local clock generation block (CGB). For non-bonded channel configurations, the serial clock generated by the transmit PLL drives the local

CGB of each channel. The local CGB generates the parallel clock used by the serializer and the PCS.

There are two standalone master CGBs within each transceiver bank. The master CGB provides the same functionality as the local CGB within each transceiver channel. The output of the master CGB can be routed to other channels within a transceiver bank using the x6 clock lines. The output of the master CGB can also be routed to channels in other transceiver banks using the xN clock lines. Each transmitter channel has a multiplexer to select its clock source from either the local CGB or the master CGB.


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Figure 179. Clock Generation Block and Clock Network

The local clock for each transceiver channel can be sourced from either the local CGB via the x1 network, or the master CGB via the x6/xN network. For example, as shown by the red highlighted path, the fPLL 1 drives the x1 network which in turn drives the master CGB. The master CGB then drives the x6 clock network which routes the clocks to the local channels. As shown by the blue highlighted path, the ATX PLL 0 can also drive the x1 clock network which can directly feed a channel's local CGB. In this case, the low speed parallel clock is generated by the local CGB.

x1

Network xN

Up xN

Down x6

Top x6

Bottom fPLL 1

ATX PLL 1 fPLL 0

ATX PLL 0

Master

CGB1

Master

CGB0

CGB

CGB

CGB

CGB

CGB

CGB

Ch 5

CDR

Ch 4

CMU or CDR

Ch 3

CDR

Ch 2

Transceiver

Bank

CDR

Ch 1

CMU or CDR

Ch 0

CDR

3.5. FPGA Fabric-Transceiver Interface Clocking

The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiver and clock signals from the transceiver into the FPGA fabric. These clock signals use the global (GCLK), regional (RCLK), and periphery (PCLK) clock

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networks in the FPGA core. If the Global Signal is set to Off, it does not choose any of the previously mentioned clock networks. Instead, it chooses directly from the local routing between transceiver and FPGA fabric.

The transmitter channel forwards a parallel output clock tx_clkout

to the FPGA fabric to clock the transmitter data and control signals. The receiver channel forwards a parallel output clock rx_clkout

to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric. Based on the receiver channel configuration, the parallel output clock is recovered from either the receiver serial data or the rx_clkout

clock (in configurations without the rate matcher) or the tx_clkout

clock (in configurations with the rate matcher).

Figure 180. FPGA Fabric - Transceiver Interface Clocking


Fabric

Receiver PMA tx_clkout tx_pma_div_clkout

Receiver Standard PCS

PRBS

Generator

/2, /4 tx_coreclkin tx_clkout rx_coreclkin

Parallel Clock

(From Clock

Divider)

Parallel Clock

(Recovered)

Serializer

/66

/40

/33

/2 rx_clkout tx_clkout

PRBS

Verifier


Clock Generation Block (CGB)

Clock Divider

Parallel and Serial Clocks tx_pma_div_clkout

Deserializer

/66

/40

/33

/2

Serial Clock

(from CGB) tx_clkout

CDR Recovered

Clock rx_pma_div_clkout rx_clkout

The divided versions of the tx_clkout

and rx_clkout

are available as tx_pma_div_clkout

and rx_pma_div_clkout

, respectively.

rx_clkout or tx_clkout

CMU PLL /

ATX PLL / fPLL

Serial Clock


Parallel Clock

Serial Clock



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Note:

The output frequency of of the following: tx_pma_div_clkout

and rx_pma_div_clkout can be one

• A divided down version of the tx_clkout

or rx_clkout

respectively, where divide by 1 and divide by 2 ratios are available.

• A divided down version of the serializer clock where divide by 33, 40, and 66 ratios are available.

Refer to the "TX PMA Optional Ports" table in PMA Parameters section for details about selecting the division factor.

These clocks can be used to meet core timing by operating the TX and RX FIFO in double-width mode, as this halves the required clock frequency at the PCS to/from

FPGA interface. These clocks can also be used to clock the core side of the TX and RX

FIFOs when the Enhanced PCS Gearbox is used.

For example, if you use the Enhanced PCS Gearbox with a 66:40 ratio, then you can use tx_pma_div_clkout external clock source.

with a divide-by-33 ratio to clock the write side of the TX

FIFO, instead of using a PLL to generate the required clock frequency, or using an


PMA Parameters on page 51

3.6. Transmitter Data Path Interface Clocking

The clocks generated by the PLLs are used to clock the channel PMA and PCS blocks.

The clocking architecture is different for the standard PCS and the enhanced PCS.

Figure 181. Transmitter Standard PCS and PMA Clocking

The master or the local CGB provides the high speed serial clock to the serializer of the transmitter PMA, and the low speed parallel clock to the transmitter PCS.


Fabric

PRBS

Generator tx_coreclkin tx_clkout

From Receiver Standard PCS tx_pma_div_clkout

/2, /4 tx_clkout

Parallel Clock

Serial Clock



Clock Divider


ATX PLL

CMU PLL fPLL

Serial Clock


In the Standard PCS, for configurations that do not use the byte serializer, the parallel clock is used by all the blocks up to the read side of the TX phase compensation FIFO.

For configurations that use the byte serializer block, the clock divided by 2 or 4 is used by the byte serializer and the read side of the TX phase compensation FIFO. The clock used to clock the read side of the TX phase compensation FIFO is also forwarded to the FPGA fabric to provide an interface between the FPGA fabric and the transceiver.

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If the tx_clkout

that is forwarded to the FPGA fabric is used to clock the write side of the phase compensation FIFO, then both sides of the FIFO have 0 ppm frequency difference because it is the same clock that is used.

If you use a different clock than the tx_clkout

to clock the write side of the phase compensation FIFO, then you must ensure that the clock provided has a 0 ppm frequency difference with respect to the tx_clkout

.

Figure 182. Transmitter Enhanced PCS and PMA Clocking

The master or local CGB provides the serial clock to the serializer of the transmitter PMA, and the parallel clock to the transmitter PCS.

Transmitter PMA Transmitter Enhanced PCS FPGA

Fabric

TX

Data &

Control

Parallel Clock

PRBS

Generator

PRP

Generator tx_clkout

KR FEC Enc

KR FEC TX G

KR FEC Scr tx_pma_div_clkout


Parallel Clock

Serial Clock


Clock Divider


ATX PLL fPLL

CMU PLL

Serial Clock


In the Enhanced PCS, the parallel clock is used by all the blocks up to the read side of the TX phase compensation FIFO. The clocks of all channels in bonded configuration are forwarded. You can pick tx_clkout[0]

as the source for clocking their TX logic in core.

For the enhanced PCS, the transmitter PCS forwards the following clocks to the FPGA fabric: tx_clkout

for each transmitter channel in non-bonded and bonded configuration. In bonded configuration, any requirements.

tx_clkout

can be used depending on your core timing

You can clock the transmitter datapath interface using one of the following methods:

• Quartus Prime selected transmitter datapath interface clock

• User-selected transmitter datapath interface clock

3.7. Receiver Data Path Interface Clocking

The CDR block present in the PMA of each channel recovers the serial clock from the incoming data. The CDR block also divides the recovered serial clock to generate the recovered parallel clock. Both the recovered serial and the recovered parallel clocks are used by the deserializer. The receiver PCS can use the following clocks based on the configuration of the receiver channel:

• Recovered parallel clock from the CDR in the PMA.

• Parallel clock from the clock divider used by the transmitter PCS (if enabled) for that channel.


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For configurations that use the byte deserializer block, the clock divided by 2 or 4 is used by the byte deserializer and the write side of the RX phase compensation FIFO.

Figure 183. Receiver Standard PCS and PMA Clocking

Receiver PMA Receiver Standard PCS FPGA

Fabric rx_coreclkin

Parallel Clock

(Recovered)

Parallel Clock

(From Clock


PRBS

Verifier



Clock Divider rx_clkout or tx_clkout

ATX PLL

CMU PLL fPLL

Parallel Clock

Serial Clock

Parallel and Serial Clock Parallel and Serial Clock

Serial Clock

All configurations that use the standard PCS channel must have a 0 ppm phase difference between the receiver datapath interface clock and the read side clock of the

RX phase compensation FIFO.

Figure 184. Receiver Enhanced PCS and PMA Clocking

Receiver PMA Receiver Enhanced PCS rx_pma_div_clkout

FPGA

Fabric

PRBS

Verifier

PRP

Verifier

10GBASE-R

BER Checker rx_clkout

KR FEC Block S KR FEC Dec

Parallel Clock

Serial Clock


The receiver PCS forwards the following clocks to the FPGA fabric:

• rx_clkout

— for each receiver channel when the rate matcher is not used.

• tx_clkout

— for each receiver channel when the rate matcher is used.

You can clock the receiver datapath interface using one of the following methods:

• Quartus Prime selected receiver datapath interface clock

• User-selected receiver datapath interface clock


Unused or Idle Clock Line Requirements

on page 389

For more information about unused or idle transceiver clock lines in design.

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3.8. Unused/Idle Clock Line Requirements

Unused or idle transceiver clock lines can degrade if the devices are powered up to normal operating conditions and not configured. This affects designs that configure transceiver RX channels to use the idle clock lines at a later date by using dynamic reconfiguration or a new device programming file. Clock lines affected are unused, or idle RX serial clock lines. Active RX serial clock lines and non-transceiver circuits are not impacted by this issue.

In order to prevent the performance degradation, for idle transceiver RX channels, recompile designs with Intel Quartus Prime version 16.1 or later with the assignment described in the link shown below. The CLKUSR pin must be assigned a 100-125 MHz clock. For used transceiver TX and RX channels, do not assert the analog reset signals indefinitely.


Unused Transceiver channels Settings

on page 606

For more information about unused or idle transceiver clock lines in the design. It describes the unused or idle RX serial clock lines assignments in the qsf file.

3.9. Channel Bonding

For Arria 10 devices, two types of bonding modes are available:

• PMA bonding

• PMA and PCS bonding

Note: Channel bonding is not supported by GT channels.



on page 416

Refer to the Timing Constraints for Bonded PCS and PMA Channels section in the

Resetting Transceiver Channels chapter for additional details.

3.9.1. PMA Bonding

PMA bonding reduces skew between PMA channels. In PMA bonding, only the PMA portion of the transceiver datapath is skew compensated and the PCS is not skew compensated.

In Arria 10 devices, there are two PMA bonding schemes:

• x6/xN bonding

• PLL feedback compensation bonding

In either case, the channels in the bonded group need not be placed contiguously.

3.9.1.1. x6/xN Bonding

In x6/xN bonding mode, a single transmit PLL is used to drive multiple channels.


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The steps below explain the x6/xN bonding process:

1. The ATX PLL or the fPLL generates a high speed serial clock.

2. The PLL drives the high speed serial clock to the master CGB via the x1 clock network.

3. The master CGB drives the high speed serial and the low speed parallel clock into the x6 clock network.

4. The x6 clock network feeds the TX clock multiplexer for the transceiver channels within the same transceiver bank. The local CGB in each transceiver channel is bypassed.

5. To drive the channels in adjacent transceiver banks, the x6 clock network drives the xN clock network. The xN clock network feeds the TX clock mutiplexer for the transceiver channels in these adjacent transceiver banks.

x6/xN Bonding Disadvantages x6/xN Bonding has the following disadvantages:

• The maximum data rate is restricted based on the transceiver supply voltage.

Refer to Arria 10 Device Data Sheet.

• The maximum channel span is limited to two transceiver banks above and below the bank containing the transmit PLL. Thus, the maximum span of 30 channels is supported.


•

xN Clock Lines

on page 379

• Arria 10 Device Datasheet

3.9.1.2. PLL Feedback Compensation Bonding

In PLL feedback compensation bonding, channels are divided into bonded groups based on physical location with a three-channel or six-channel transceiver bank. All channels within the same six-channel transceiver bank are assigned to the same bonded group.

In PLL feedback compensation bonding, each bonded group is driven by its own set of high-speed serial and low-speed parallel clocks. Each bonded group has its own PLL and master CGB. To maintain the same phase relationship, the PLL and master CGB for different groups share the same reference clocks.

The steps below explain the PLL feedback compensation bonding process:

1. The same input reference clock drives the local PLL in each three-channel or sixchannel transceiver bank.

2. The local PLL for the bonding group drives the master CGB.

3. The master CGB feeds the x6 clock lines. The master CGB drives the transceiver channels in the bonding group via the x6 clock network.

4. The parallel output of the master CGB is the feedback input to the PLL.

5. In this mode, all channels are phase aligned to the same input reference clock.

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Note:

PLL Feedback Compensation Bonding Advantages over x6/xN Bonding Mode

• There is no data rate restriction. The x6 clock network used for PLL feedback compensation bonding can run up to the maximum data rate of the device used.

• There is no channel span limitation. It is possible to bond the entire side of the device using PLL feedback compensation.

PLL Feedback Compensation Bonding Disadvantages over x6/xN Bonding

Mode

• It uses more resources compared to x6/xN bonding. One PLL and one master CGB are used per transceiver bank. This causes higher power consumption compared to x6/xN bonding.

• The skew is higher compared to x6/xN bonding. The reference clock skew between each transceiver bank is higher than the skew contributed by the xN clock network in x6/xN bonding.

• Because the feedback clock for the PLL comes from the master CGB and not from the PLL, the PLL feedback compensation bonding mode has a reference clock limitation. The PLL's N-counter (reference clock divider) is bypassed resulting in only one valid reference clock frequency for a given data rate.

• Feedback compensation bonding only supports integer mode.

In order to minimize the reference clock skew for PLL feedback compensation bonding, use a reference clock input near the center of the bonded group.

x6/xN Bonding Advantages over PLL Feedback Compensation Bonding

• x6/xN uses less resources compared to PLL feedback compensation bonding. Only one PLL and one master CGB are required to drive all channels in the bonded group.

• x6/xN has lower skew compared to PLL feedback compensation bonding.


Implementing PLL Feedback Compensation Bonding Mode

on page 405

3.9.2. PMA and PCS Bonding

PMA and PCS bonding reduces skew between both the PMA and PCS outputs within a group of channels.

For PMA bonding, either x6/xN or PLL feedback compensation bonding is used. For

PCS bonding, some of the PCS control signals within the bonded group are skew aligned using dedicated hardware inside the PCS.


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Figure 185. PMA and PCS Bonding

Starting

Delay (Cycles)

2

4

6

4

2

0

Distribution

Delay (Cycles)

4

2

0

2

4

6

Slave PCS

Channel

Slave PCS

Channel

Master PCS

Channel

Slave PCS

Channel

Slave PCS

Channel

Slave PCS

Channel

PMA

PMA

PMA

PMA

PMA

PMA

Note:

For PMA and PCS bonding, the concept of master and slave channels is used. One PCS channel in the bonded group is selected as the master channel and all others are slave channels. To ensure that all channels start transmitting data at the same time and in the same state, the master channel generates a start condition. This condition is transmitted to all slave channels. The signal distribution of this start condition incurs a two parallel clock cycle delay. Because this signal travels sequentially through each

PCS channel, this delay is added per channel. The start condition used by each slave channel is delay compensated based on the slave channel's distance from the master channel. This results in all channels starting on the same clock cycle.

The transceiver PHY IP automatically selects the center channel to be the master PCS channel. This minimizes the total starting delay for the bonded group. For PLL feedback compensation bonding up to all channels on one side can be bonded if the master PCS channel is placed in the center of the bonded group.

Because the PMA and PCS bonding signals travel through each PCS block, the PMA and

PCS bonded groups must be contiguously placed. The channel order needs to be maintained when doing the pin assignments to the dedicated RX serial inputs and TX serial outputs (for example: PIN_BC7 and PIN_BC8 for GXBR4D_TX_CH0p and

GXBR4D_TX_CH0n TX serial outputs). Channels need to be placed in an ascending order from bottom to top. Swapping of channels, when doing pin assignments, leads to errors.

3.9.3. Selecting Channel Bonding Schemes

In Arria 10 devices, select PMA and PCS bonding for bonded protocols that are explicitly supported by the hard PCS blocks. For example, PCI Express, SFI-S, and

40GBASE-KR.

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Select PMA-only bonding when a bonded protocol is not explicitly supported by the hard PCS blocks. For example, for Interlaken protocol, PMA-only bonding is used and a soft PCS bonding IP is implemented in the FPGA fabric.

3.9.4. Skew Calculations

To calculate the maximum skew between the channels, the following parameters are used:

• PMA to PCS datapath interface width (S)

• Maximum difference in number of parallel clock cycles between deassertion of each channel's FIFO reset (N).

To calculate the channel skew, the following five scenarios are considered:

• Non-bonded

In this case, both the PMA and PCS are non-bonded. Skew ranges from 0 UI to

[(S-1) + N*S] UI.

• PMA bonding using x6 / xN clock network

In this case, the PCS is non-bonded. Skew ranges from [0 to (N*S)] UI + x6/xN clock skew.

• PMA bonding using the PLL feedback compensation clock network

In this case, the PCS is non-bonded. Skew ranges from [0 to (N*S)] UI +

(reference clock skew) + (x6 clock skew).

• PMA and PCS bonding using the x6 / xN clock network

Skew = x6 / xN clock skew.

• PMA and PCS bonding using PLL feedback compensation clock network

Skew = (reference clock skew) + (x6 clock skew).

3.10. PLL Feedback and Cascading Clock Network

The PLL feedback and cascading clock network spans the entire side of the device, and is used for PLL feedback compensation bonding and PLL cascading.


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Figure 186. PLL Feedback and Cascading Clock Network

Transceiver Bank fPLL1

C

Connection (1)

PLL Feedback and Cascading Clock Network

0 1 2 3 fbclk refclk

ATX PLL 1 refclk fbclk

Connection (3)

Connection (4)

Master CGB1

Bidirectional

Tristate Buffer fPLL0

C refclk fbclk

ATX PLL 0 refclk fbclk

Connection (2)

Master CGB0

Bidirectional

Tristate Buffer

Legend refclk Lines fbclk Lines

C, M, and CGB Outputs

PLL Cascading

PLL Feedback Compensation Bonding

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Note:

To support PLL feedback compensation bonding and PLL cascading, the following connections are present:

1. The C counter output of the fPLL drives the feedback and cascading clock network.

2. The feedback and cascading clock network drives the feedback clock input of all PLLs.

3. The feedback and cascading clock network drives the reference clock input of all PLLs.

4. The master CGB’s parallel clock output drives the feedback and cascading

clock network.

For PLL cascading, connections (1) and (3) are used to connect the output of one PLL to the reference clock input of another PLL.

The transceivers in Arria 10 devices support fPLL to fPLL, and ATX PLL to fPLL

(via dedicated ATX PLL to fPLL cascade path) cascading. Only maximum two

PLLs allowed in the cascading chain.

When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.

For PLL feedback compensation bonding, connections (2) and (4) are used to connect the master CGB's parallel clock output to the PLL feedback clock input port.

PLL feedback compensation bonding can be used instead of xN bonding. The primary difference between PLL feedback compensation and xN bonding configurations, is for

PLL feedback compensation, the bonded interface is broken down into smaller groups of 6 bonded channels within a transceiver bank. A PLL within each transceiver bank

(ATX PLL or fPLL) is used as a transmit PLL. All the transmit PLLs share the same input reference clock.

In xN bonding configurations, one PLL is used for each bonded group. In PLL feedback compensation bonding, one PLL is used for each transceiver bank that the bonded group spans. There are no data rate limitations in PLL feedback compensation bonding, other than the natural data rate limitations of the transceiver channel and the PLL.

For feedback compensation bonding, the low-speed parallel clock must be the same frequency as the reference clock for the PLL.

fPLL Driving the Core

The fPLL can be used to drive the FPGA fabric. To ensure phase alignment between the input reference clock and the fPLL output clock, the fPLL needs to be configured in integer mode. Refer to the following figures when doing dynamic reconfiguration.


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Figure 187. Fractional and not Phase Aligned refclk N Counter

PFD VCO /2 fPLL M Counter

L Counter

/2

Phase

Multiplexer

C Counters

Figure 188. Integer and Phase Aligned refclk N Counter

PFD VCO /2 fPLL M Counter

L Counter

/2

C Counters

Phase

Multiplexer

PLL Feedback Clock Network

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Figure 189. Integer Mode phase aligned and external feedback fPLL 1

C refclk fpll_t_iqtxrxclk pm_iqtxrxclk_top[5:0] fbclk pm_iqtxrxclk_top[3:0]

PMA_RX_CLK

PMA_TX_CLK

RX pin (1)

PMA_RX_CLK

PMA_TX_CLK

RX pin (1)

PMA_RX_CLK

PMA_TX_CLK

RX pin (1)

PMA_RX_CLK

PMA_TX_CLK

RX pin (1)

PMA_RX_CLK

PMA_TX_CLK

RX pin (1) fbclk

Ch5 ch5_iqtxrxclk_2 pm_iqtxrxclk_top[5:0] refclk pm_iqtxrxclk_top[3:0] ch5_iqtxrxclk_5

4

6

6

4 fbclk


4

6 fbclk


4

6 pm_iqtxrx_t[5:0]

0 1 2 3 4 5

PMA_RX_CLK

PMA_TX_CLK

RX pin (1)

LCPLL 1

M refclk lc_t_iqtxrxclk pm_iqtxrxclk_top[5:0] fbclk pm_iqtxrxclk_top[3:0]

6

4

Master

CGB 1

Note: (1) RX pin used as reference clock

You must recalibrate the fPLL when you enable the phase alignment option.

1. Modify the fPLL IP to enable fPLL reconfiguration

• Under the Dynamic Reconfiguration Tab, turn ON Enable dynamic reconfiguration.

2. Create logics in the core to perform following steps:


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• Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL to select internal feedback.

• Read-Modify-Write 0x1 to offset address 0x100 of the fPLL, then Read-Modify-

Write 0x1 to offset address 0x000 of the fPLL to request PreSICE to recalibrate the fPLL.

• Monitor bit 1 of offset address of 0x280 of the fPLL and wait until this bit changes to zero. This indicates recalibration is completed. Ensure the fPLL achieves lock.

• Read-Modify-Write 0x0 to offset address 0x126[0] of the fPLL to select the external feedback path.

3. Monitor the fPLL lock signal, wait until the fPLL achieves lock.


•

User Recalibration

on page 576

•

Implementing PLL Cascading on page 408

3.11. Using PLLs and Clock Networks

In Arria 10 devices, PLLs are not integrated in the Native PHY IP core. You must instantiate the PLL IP cores separately. Unlike in previous device families, PLL merging is no longer performed by the Quartus Prime software. This gives you more control, transparency, and flexibility in the design process. You can specify the channel configuration and PLL usage.


PLLs and Clock Networks on page 347

3.11.1. Non-bonded Configurations

In a non-bonded configuration, only the high speed serial clock is routed from the transmitter PLL to the transmitter channel. The low speed parallel clock is generated by the local clock generation block (CGB) present in the transceiver channel. For nonbonded configurations, because the channels are not related to each other and the feedback path is local to the PLL, the skew between channels cannot be calculated.

Also, the skew introduced by the clock network is not compensated.

3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration

In x1 non-bonded configuration, the PLL source is local to the transceiver bank and the x1 clock network is used to distribute the clock from the PLL to the transmitter channel.

For a single channel design, a PLL is used to provide the clock to a transceiver channel.

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Figure 190. PHY IP Core and PLL IP Core Connection for Single Channel x1 Non-Bonded

Configuration Example

Transceiver PLL

Instance (5 GHz)

PLL

Native PHY Instance

(1 CH Non-Bonded 10 Gbps)

TX Channel

To implement this configuration, instantiate a PLL IP core and a PHY IP core and connect them together as shown in the above figure.

Steps to implement a Single Channel x1 Non-Bonded Configuration

1. Instantiate the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to use in your design.

•

Refer to Instantiating the ATX PLL IP Core on page 354 or

Instantiating CMU

PLL IP Core

on page 370 or

Instantiating the fPLL IP Core on page 362 for

detailed steps.

2. Configure the PLL IP core using the IP Parameter Editor.

• For ATX PLL IP core, do not include the Master CGB.

• For fPLL IP core, set the PLL feedback operation mode to direct.

• For CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required.

3. Configure the Native PHY IP core using the IP Parameter Editor .

• Set the Native PHY IP Core TX Channel bonding mode to Non Bonded .

4. Connect the PLL IP core to the Native PHY IP core. Connect the tx_serial_clk output port of the PLL to IP to the corresponding tx_serial_clk0

input port of the Native PHY IP core. This port represents the input to the local CGB of the channel. The tx_serial_clk

for the PLL represents the high speed serial clock generated by the PLL.

3.11.1.2. Implementing Multi-Channel x1 Non-Bonded Configuration

This configuration is an extension of the x1 non-bonded case. In the following example, 10 channels are connected to two instances of the PLL IP core. Two PLL instances are required because PLLs using the x1 clock network can only span the 6 channels within the same transceiver bank. A second PLL instance is required to provide the clock to the remaining 4 channels.

Because 10 channels are not bonded and are unrelated, you can use a different PLL type for the second PLL instance. It is also possible to use more than two PLL IP cores and have different PLLs driving different channels. If some channels are running at different data rates, then you need different PLLs driving different channels.


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Figure 191. PHY IP Core and PLL IP Core Connection for Multi-Channel x1 Non-Bonded

Configuration

Transceiver PLL

Instance (5 GHz) fPLL

Transceiver PLL

Instance (5 GHz) fPLL

Native PHY Instance


TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

Legend:

TX channels placed in the same transceiver bank.

TX channels placed in the adjacent transceiver bank.

Steps to implement a Multi-Channel x1 Non-Bonded Configuration

1. Choose the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to instantiate in your design and instantiate the PLL IP core.

•


Instantiating CMU

PLL IP Core

on page 370 or

Instantiating the fPLL IP Core on page 362 for

detailed steps.

2. Configure the PLL IP core using the IP Parameter Editor

• For the ATX PLL IP core do not include the Master CGB. If your design uses the

ATX PLL IP core and more than 6 channels, the x1 Non-Bonded Configuration is not a suitable option. Multi-channel xN Non-Bonded or Multi-Channel x1/xN

Non-Bonded are the required configurations when using the ATX PLL IP core and more than 6 channels in the Native PHY IP core.

•

Refer to Figure 192 on page 401 Implementing Multi-Channel xN Non-Bonded

Configuration section or the Figure 193 on page 403 Multi-Channel x1/xN Non-

Bonded Example.

• For the fPLL IP core, set the PLL feedback operation mode to direct.

• For the CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required.

3. Configure the Native PHY IP core using the IP Parameter Editor

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• Set the Native PHY IP core TX Channel bonding mode to Non-Bonded.

• Set the number of channels as per your design requirement. In this example, the number of channels is set to 10.

4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.

• The

tx_serial_clk

output

port of the PLL IP core represents the high speed serial clock.

• The Native PHY IP core has 10 (for this example) tx_serial_clk input ports. Each port corresponds to the input of the local CGB of the transceiver channel.

• As shown in the figure above, connect the first 6 tx_serial_clk input

to the first transceiver PLL instance.

• Connect the remaining 4 tx_serial_clk input

to the second transceiver

PLL instance.

3.11.1.3. Implementing Multi-Channel xN Non-Bonded Configuration

Using the xN non-bonded configuration reduces the number of PLL resources and the reference clock sources used.

Figure 192. PHY IP Core and PLL IP Core Connection for Multi-Channel xN Non-Bonded

Configuration

In this example, the same PLL is used to drive 10 channels across two transceiver banks.

Transceiver PLL

Instance (5 GHz)

ATX PLL x1 Master

CGB x6

Native PHY Instance


TX Channel

TX Channel

TX Channel

TX Channel xN

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

Legend:




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Steps to implement a multi-channel xN non-bonded configuration

1. You can use either the ATX PLL or fPLL for multi-channel xN non-bonded configuration.

•


Instantiating the fPLL IP Core


• Because the CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL can be used for this example.

2. Configure the PLL IP core using the IP Parameter Editor. Enable Include

Master Clock Generation Block .


• Set the Native PHY IP core TX Channel bonding mode to Non-Bonded .

• Set the number of channels as per your design requirement. In this example, the number of channels is set to 10.

4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.

• In this case, the PLL IP core has represents the xN clock line.

mcgb_serial_clk

output port. This

• The Native PHY IP core has 10 (for this example) tx_serial_clk input ports. Each port corresponds to the input of the local CGB of the transceiver channel.

• As shown in the figure above, connect the mcgb_serial_clk

output port of the PLL IP core to the 10 tx_serial_clk input

ports of the Native PHY IP core.

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Figure 193. Multi-Channel x1/xN Non-Bonded Example

The ATX PLL IP core has a tx_serial_clk output port. This port can optionally be used to clock the six channels within the same transceiver bank as the PLL. These channels are clocked by the x1 network. The remaining four channels outside the transceiver bank are clocked by the xN clock network.

Transceiver PLL

Instance (5 GHz)

Native PHY Instance


ATX PLL x1

TX Channel

CGB xN

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

Legend:



3.11.2. Bonded Configurations

In a bonded configuration, both the high speed serial and low speed parallel clocks are routed from the transmitter PLL to the transmitter channel. In this case, the local CGB in each channel is bypassed and the parallel clocks generated by the master CGB are used to clock the network.

In bonded configurations, the transceiver clock skew between the channels is minimized. Use bonded configurations for channel bonding to implement protocols such as PCIe and XAUI.


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3.11.2.1. Implementing x6/xN Bonding Mode

Figure 194. PHY IP Core and PLL IP Core Connection for x6/xN Bonding Mode

Transceiver PLL

Instance (5 GHz)

ATX PLL x1

Master

CGB x6 x6 x6 x6 x6 x6 x6 xN xN xN xN

Native PHY Instance

(10 CH x6/xN Bonding 10 Gbps)

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

Legend:



Steps to implement a x6/xN bonded configuration

1. You can instantiate either the ATX PLL or the fPLL for x6/xN bonded configuration.

•



on page 362 for detailed steps. Because the CMU PLL cannot drive the Master CGB, only the ATX PLL or fPLL can be used for bonded configurations.

2. Configure the PLL IP core using the IP Parameter Editor. Enable Include

Master Clock Generation Block and Enable bonding clock output ports.

3. Configure the Native PHY IP core using the IP Parameter Editor .

• Set the Native PHY IP core TX Channel bonding mode to either PMA

bonding or PMA/PCS bonding .

• Set the number of channels required by your design. In this example, the number of channels is set to 10.

4. Create a top level wrapper to connect the PLL IP core to Native PHY IP core.

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• In this case, the PLL IP core has tx_bonding_clocks

output bus with width

[5:0].

• The Native PHY IP core has tx_bonding_clocks

input bus with width [5:0] multiplied by the number of transceiver channels (10 in this case). For 10 channels, the bus width is [59:0].

Note: While connecting tx_bonding_clocks

, leave tx_serial_clk

open to avoid any Intel Quartus Prime software fitter errors.

• Connect the PLL IP core to the PHY IP core by duplicating the output of the

PLL[5:0] for the number of channels. For 10 channels, the Verilog syntax for the input port connection is

.tx_bonding_clocks

({10{tx_bonding_clocks_output}})

.

Note: Although the above diagram looks similar to the 10-channel non-bonded configuration example, the clock input ports on the transceiver channels bypass the local CGB in x6/xN bonding configuration. This internal connection is taken care of when the

Native PHY channel bonding mode is set to Bonded.

Figure 195. x6/xN Bonding Mode —Internal Channel Connections

Ch 2

CGB

(1)

CDR

Ch 1

CGB

(1)

CDR

Ch 0

CGB

(1)

CDR

Note: (1) The local CGB is bypassed by the clock input ports in bonded mode.


xN Clock Lines

on page 379

Information on xN Clock Network Span.

3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode

In this bonding mode, the channel span limitations of xN bonding mode are removed.

This is achieved by dividing all channels into multiple bonding groups.


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Figure 196. PHY IP Core and PLL IP Core Connection for PLL Feedback Compensation

Bonding

Reference clock fPLL

Transceiver PLL

Instance (5 GHz)

CGB fPLL

Feedback Clock

Transceiver PLL

Instance (5 GHz)

Feedback Clock

CGB x6 x6

Native PHY Instance

(10 CH Bonded 10 Gbps)

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

TX Channel

Legend:



The data rate is limited by the x6 network speed limit. A disadvantage of using PLL feedback compensation bonding is that it consumes more PLL resources. Each transceiver bank consumes one PLL and one master CGB.

In PLL feedback compensation bonding mode, the N counter (reference clock divider) is bypassed in order to ensure that the reference clock skew is minimized between the

PLLs in the bonded group. Because the N counter is bypassed, the PLL reference clock has a fixed value for any given data rate.

The PLL IP Core Parameter Editor window displays the required data rate in the

PLL reference clock frequency drop down menu.

Steps to implement a PLL Feedback Compensation Bonding Configuration

1. Instantiate the PLL IP core (ATX PLL or fPLL) you want to use in your design. Refer to

Instantiating the ATX PLL IP Core

on page 354 or Instantiating the fPLL IP Core

on page 362 for detailed steps. Because the CMU PLL cannot drive the master

CGB, only the ATX PLL or fPLL can be used for feedback compensation bonding.

2. Configure the PLL IP core using the IP Parameter Editor.

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• If you use the ATX PLL, set the following configuration settings:

— Under the Master Clock Generation Block Tab

• Enable Include Master Clock Generation Block.

• Turn ON Enable Bonding Clock output ports.

• Turn ON Enable feedback compensation bonding.

— Under the Dynamic Reconfiguration Tab

• Turn ON Enable dynamic reconfiguration

• If you use the fPLL, set the following configuration settings:

— Under the PLL Tab

• Set the PLL Feedback type to feedback compensation bonding.

— Under the Master Clock Generation Block Tab

• Turn ON Enable Bonding Clock output ports.

— Under the Dynamic Reconfiguration Tab



• Set the Native PHY IP core TX Channel bonding mode to either PMA

bonding or PMA/PCS bonding.


4. Create a top level wrapper to connect the PLL IP cores to Native PHY IP core.

• In this case, the PLL IP core has tx_bonding_clocks

output bus with width

[5:0].

• The Native PHY IP core has tx_bonding_clocks

input bus with width [5:0] multiplied by the number of channels in a transceiver bank. (six channels in the transceiver bank).

• Unlike the x6/xN bonding mode, for this mode, the PLL should be instantiated multiple times. (One PLL is required for each transceiver bank that is a part of the bonded group.) Instantiate a PLL for each transceiver bank used.

• Connect the tx_bonding_clocks

output from each PLL to (up to) six channels in the same transceiver bank.

• Connect the PLL IP core to the PHY IP core by duplicating the output of the

PLL[5:0] for the number of transceiver channels used in the bonding group.

Steps to recalibrate the PLL after power up calibration

1. Dynamic reconfigure the PLL to change the feedback from the master CGB to feedback from PLL.

• For ATX PLL, Read-Modify-Write 0x1 to offset address 0x110[2] of the ATX

PLL.

• For fPLL, Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL.

2. Recalibrate the PLL.

3. After recalibration completes, ensure the PLL achieves lock. Dynamic reconfigure the PLL to change the feedback to master CGB.


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Note:

• For ATX PLL, Read-Modify-Write 0x0 to offset address 0x110[2] of the ATX

PLL.

• For fPLL, Read-Modify-Write 0x0 to offset address 0x126[0] of the fPLL.

4. Recalibrate TX PMA of all the bonded channels driven by the ATX PLL or the fPLL.

For this 10-channel example, two ATX PLLs are instantiated. Six channels of the tx_bonding_clocks

on the Native PHY IP core are connected to the first ATX PLL and the remaining four channels are connected to the second ATX PLL's tx_bonding_clock outputs.


•

ATX PLL Recalibration on page 581

•

Fractional PLL Recalibration on page 581

•

PMA Recalibration

on page 582

3.11.3. Implementing PLL Cascading

In PLL cascading, the output of the first PLL feeds the input reference clock to the second PLL.

For example, if the input reference clock has a fixed frequency, and the desired data rate was not an integer multiple of the input reference clock, the first PLL can be used to generate the correct reference clock frequency. This output is fed as the input reference clock to the second PLL. The second PLL generates the clock frequency required for the desired data rate.

The transceivers in Arria 10 devices support fPLL to fPLL cascading. For OTN and SDI applications, there is a dedicated clock path for cascading ATX PLL to fPLL in Arria 10 production silicon. Only maximum two PLLs are allowed in the cascading chain.

Note: When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.

Figure 197. PLL Cascading fPLL (Cascade Source) pll_refclk0 hssi_pll_cascade_clk fPLL (Transceiver PLL) pll_refclk0 pll_powerdown pll_locked pll_powerdown

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Steps to implement fPLL to fPLL cascading:

1. Instantiate the fPLL IP core. Refer to Instantiating the fPLL IP Core on page 362

for detailed steps.

2. Set the following configuration settings for the fPLL IP core in the Parameter

Editor:

• Set the fPLL Mode to Cascade Source.

• Set the Desired output clock frequency.

3. Instantiate the fPLL IP core (the second PLL in PLL cascading configuration). Refer to



4. Configure the second fPLL IP core for the desired data rate and the reference clock frequency. Set reference clock frequency for the second fPLL same as the output frequency of the first fPLL.

5. Connect the fPLL IP core (cascade source) to fPLL IP core (transceiver PLL) as shown in the above figure. Ensure the following connections:

• The fPLL has an output port hssi_pll_cascade_clk

. Connect this port to the second fPLL's pll_refclk0

port.

6. Set the source (upstream) fPLL bandwidth to Low setting and the destination

(downstream) fPLL bandwidth to High setting.

7. If the input reference clock is available at device power-up, the first PLL is calibrated during the power-up calibration. The second PLL need to be recalibrated. Refer to the User Recalibration section. If the input reference clock is not available at device power-up, then re-run the calibration for the first PLL. After the first PLL has been calibrated, re-calibrate the second PLL.

Notes:

• No special configuration is required for the Native PHY instance.

• ATX PLL to fPLL cascading mode is added to address the OTN and SDI jitter requirement. In this mode, ATX PLL generates a relatively high and clean reference frequency in fractional mode. The reference is driving the fPLL, which is running in integer mode. Overall cascaded two PLLs, synthesize a needed frequency for a given data rate.


User Recalibration

on page 576

3.11.4. Mix and Match Example

In the Arria 10 transceiver architecture, the separate Native PHY IP core and the PLL

IP core scheme allows great flexibility. It is easy to share PLLs and reconfigure data rates. The following design example illustrates PLL sharing and both bonded and nonbonded clocking configurations.


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Figure 198. Mix and Match Design Example

Transceiver Bank

ATX PLL

6.25 GHz

Transceiver Bank

fPLL

5.15625 GHz

Transceiver Bank fPLL, 5.15625 GHz fPLL, 625 MHz

Transceiver Bank fPLL

2.5 GHz

ATX PLL

4 GHz

Transceiver Bank

MCGB

MCGB x1 x1 x6 xN x1 mcgb_aux_clk0 x6 xN

Interlaken 12.5G

Interlaken 12.5G

Interlaken 12.5G

Interlaken 12.5G

Interlaken 12.5G

Interlaken 12.5G

Interlaken 12.5G

Interlaken 12.5G

Interlaken 12.5G

Interlaken 12.5G

10GBASE-KR

10GBASE-KR

10GBASE-KR

10GBASE-KR

1.25G

1.25G

1.25G

1.25G

1.25G GbE

1.25G GbE

PCIe Gen 1/2/3 x8

PCIe Gen 1/2/3 x8

PCIe Gen 1/2/3 x8

PCIe Gen 1/2/3 x8

PCIe Gen 1/2/3 x8

PCIe Gen 1/2/3 x8

PCIe Gen 1/2/3 x8

PCIe Gen 1/2/3 x8

Unused

Unused

Legend

Interlaken12.5G

10GBASE-KR

1.25G/9.8G/10.3125G

1.25G GbE

PCIe Gen 1/2/3

Unused channel

PLL Instances

In this example, two ATX PLL instances and five fPLL instances are used. Choose an appropriate reference clock for each PLL instance. The IP Catalog lists the available

PLLs.

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Use the following data rates and configuration settings for PLL IP cores:

• Transceiver PLL Instance 0: ATX PLL with output clock frequency of 6.25 GHz

— Enable the Master CGB and bonding output clocks.

• Transceiver PLL instance 1: fPLL with output clock frequency of 5.1625 GHz



— Select the Use as Transceiver PLL option.


— Select Enable PCIe* clock output port option.

— Select Use as Transceiver PLL option.

• Set Protocol Mode to PCIe Gen2.

— Select the Use as Core PLL option

• Set the Desired frequency to 500 MHz with a phase shift of 0 ps.

• Transceiver PLL instance 6: ATX PLL with output clock frequency of 4 GHz

— Enable Master CGB and bonding output clocks.

— Select Enable PCIe clock switch interface option.

— Set Number of Auxiliary MCGB Clock Input ports to 1.


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Native PHY IP Core Instances

In this example, four Transceiver Native PHY IP core instances and four 10GBASE-KR

PHY IP instances are used. Use the following data rates and configuration settings for the PHY IPs:

• 12.5 Gbps Interlaken with a bonded group of 10 channels

— Set the Interlaken 10x12.5 Gbps preset from the Arria 10 Transceiver Native

PHY IP core GUI.

— Refer to Interlaken on page 94 for more details.

• Custom multi-data rate 1.25G/9.8G/10.3125 Gbps non-bonded group of four channels

— Set the Number of data channels to 4.

— Set TX channel bonding to Not Bonded.

— Under the TX PMA tab, set the Number of TX PLL clock inputs per

channel to 3.

— Under the RX PMA tab, set the Number of CDR reference clocks to 3.

• 1.25 Gbps Gigabit Ethernet with a non-bonded group of two channels

— Set the GIGE-1.25Gbps preset from the Arria 10 Transceiver Native PHY IP core GUI.

— Change the Number of data channels to 2.

• PCIe Gen3 with a bonded group of 8 channels

— Set the PCIe PIPE Gen3x8 preset from the Arria 10 Transceiver Native PHY

IP core GUI.

— Under TX Bonding options, set the PCS TX channel bonding master to channel 5.

Note: The PCS TX channel bonding master must be physically placed in channel 1 or channel 4 within a transceiver bank. In this example, the

5th channel of the bonded group is physically placed at channel 1 in the transceiver bank.

— Refer to PCI Express (PIPE)

on page 229 for more details.

• 10.3125 Gbps 10GBASE-KR non-bonded group of 4 channels

— Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY IP four times, with one instance for each channel.

— Refer to 10GBASE-KR PHY IP Core on page 135 for more details.

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Connection Guidelines for PLL and Clock Networks

• For 12.5 Gbps Interlaken with a bonded group of 10 channels, connect the tx_bonding_clocks

to the transceiver PLL's tx_bonding_clocks

output port.

Make this connection for all 10 bonded channels. This connection uses a master

CGB and the x6 / xN clock line to reach all the channels in the bonded group.

• Connect the tx_serial_clk

port of the first two instances of the 10GBASE-KR

PHY IP to the tx_serial_clk

port of PLL instance 1 (fPLL at 5.1625 GHz). This connection uses the x1 clock line within the transceiver bank.

• Connect the tx_serial_clk

port of the remaining two instances of the

10GBASE-KR PHY IP to the tx_serial_clk

port of the PLL instance 2 (fPLL at

5.1625 GHz). This connection uses the x1 clock line within the transceiver bank.

• Connect the three tx_serial_clk

ports for the custom multi-data rate PHY IP as follows:

— Connect tx_serial_clk0

port to the tx_serial_clk

port of PLL instance 2

(fPLL at 5.1625 GHz). This PLL instance is shared with the two 10GBASE-KR

PHY IP channels and also uses the x1 clock line within the transceiver bank.

• Connect the 1.25 Gbps Gigabit Ethernet non-bonded PHY IP instance to the tx_serial_clk

port of the PLL instance 5. Make this connection twice, one for each channel. This connection uses the x1 clock line within the transceiver bank.

• Connect the PCIe Gen3 bonded group of 8 channels as follows:

— Connect the tx_bonding_clocks

of the PHY IP to the tx_bonding_clocks port of the Transceiver PLL Instance 6. Make this connection for each of the 8 bonded channels.

— Connect the pipe_sw_done

of the PHY IP to the pipe_sw

port of the transceiver PLL instance 6.

— Connect the pll_pcie_clk

port of the PLL instance 5 to the PHY IP's pipe_hclk_in port.

— Connect tx_serial_clk

port of the PLL instance 5 to the mcgb_aux_clk0 port of the PLL instance 6. This connection is required as a part of the PCIe speed negotiation protocol.

3.11.5. Timing Closure Recommendations

Register mode is harder to close timing in Arria 10 devices. Intel recommends using negative edge capture on the RX side for periphery to core transfers greater than 240

MHz. To be specific, capture on a negative edge clock in the core and then immediately transfer to a positive edge clock.

• Use PCLK clock network for frequencies up to 250 MHz.

• Local routing is recommended for higher frequencies.

For core to periphery transfers on TX targeting higher frequencies (beyond 250 MHz),

Intel recommends using TX Fast Register mode as the PCS FIFO mode. This is the mode with PCLK that should be used by default for most 10GbE 1588 modes and 9.8

Gbps/10.1376 Gbps CPRI mode.

• You can use local routing to get up to 320 MHz in Register mode for the highest speed grade.


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3.12. PLLs and Clock Networks Revision History

Changes Document

Version

2018.06.15

2017.11.06

2016.10.31

2016.05.02

2016.02.11

2015.12.18

2015.11.02

2015.05.11

2014.12.15

Made the following change:

• For fPLL IP Core, added OTN_direct, SATA_Gen3 and HDMI to the range for Protocol Mode.


• Updated the "ATX PLL-to-ATX PLL Spacing Guidelines" section with GT channels information.

• Added note "Sourcing reference clock from a cascaded PLL output, global clock or core clock network will introduce additional jitter to transmit PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details."

• Added guidance for jitter compliance for data rates >10 Gbps in the following sections:

— "fPLL"

— "CMU PLL"

— "Input Reference Clock Sources"

Made the following change:

• New section Unused/Idle Clock Line Requirements added.

• Updated ATX PLL, fPLL and CMU PLL parameters.

• Updated ATX PLL and fPLL ports.

• Added new parameters and ports when fPLL is used in core mode.

• Provided additional details for ATX PLL and fPLL fractional mode usage in the "Delta Sigma

Modulator" section.

• Added a new section describing "ATX PLL multi-profile and embedded reconfiguration".


• Updated the optimal performance placement guidelines for ATX PLL VCO frequencies.

• Updated placement recommendations for different protocols - OTU2e, OTU2, OC-192, 6G and 12G

SDI.

• Updated the "FPGA Fabric - Transceiver Interface Clocking" figure.

• Updated the maximum data rate to 25.8 Gbps.


• Updated the “PLL Cascading” figure.

• Updated the "Dedicated Reference Clock Pins" in the "Input Reference Clock Sources" section.


• Updated ATX PLL, CMU PLL and fPLL Configuration Options, Parameters and Settings.

• Updated ATX PLL placement in figures and examples.

• Clarified PLL to PLL cascade support.

• Created TX PLL Recommendations based on datarates.

• Updated ATX PLL, fPLL and CMU PLL Quartus settings.

• Added details and figures for the fPLL driving the fabric use cases.

• Updated PLL Feedback and Cascading Clock Network figure.

• Updated steps to implement PLL cascading.


• Updated ATX PLL, CMU PLL and FPLL Configuration Options, Parameters and Settings.

• Modified Transmit PLLs Data Rate Range in Arria 10 Devices.

• Increased xN clock network channel span.

• Added ATX PLL to fPLL cascading details.


• Added a note about PLL cascading support in ACDS 14.1 version of Quartus II software.

• Corrected the minimum data rate supported by ATX PLL in Table: Transmit PLLs in Arria 10 Devices.

• Corrected the error in PLL output frequency range for ATX PLL and CMU PLL IP cores.

• Corrected the PLL reference clock frequency range for ATX PLL IP core.

continued...

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Document

Version

2014.08.15

2013.12.02

Changes

• Added a note about jitter performance in Input Reference Clock Sources section.

• Updated the Mix and Match Design Example figure to indicate that MCGB is used in the example.

• Changed the minimum data rate supported by the PLLs to 1 Gbps.


• Changed the maximum data rate for GT channels to 25.8 Gbps.

• Changed figure "Arria 10 PLLs and Clock Networks" to indicate channel 0,1,3, and 5 have only the

CDR PLL.

• Updated figure "x1 Clock Lines" to indicate that the channel PLL of channel 1 and channel 4 can be used as CMU PLL or as a CDR.

• Updated ATX PLL, fPLL, and CMU PLL section with a clarification about input reference clock frequency stability at device power-up.

• Updated Instantiating ATX PLL, fPLL, and CMU PLL topics with new IP instantiation flow.

• Updated ATX PLL and fPLL architecture block diagrams to show global clock or core clock as an input reference clock.

• Updated ATX PLL IP section with 14.0 A10 release changes

— Added fractional mode support.

— Added embedded debug parameters in table ATX PLL Dynamic Reconfiguration.

• Updated fPLL IP section with 14.0A10 release changes

— Removed "fPLL -Clock Switch over Parameter and Settings" table.

— Updated table "fPLL Parameter and Settings".

— Added embedded debug parameters in table "fPLL - Dynamic Reconfiguration Parameters and

Settings".

— Removed Number of auxiliary MCGB clock input ports from fPLL IP parameters.

• Added global clock or core clock as an input reference clock source.

• Added a new section for Global Clock or Core Clock as an Input Reference Clock.

• Updated figure "Input Reference Clock Sources".

• Updated Dedicated Reference Clock Pins section "Dedicated Reference Clock Pins".

— Added a connection to indicate that dedicated refclk pins can drive the reference clock network.

— Removed a wrong connection from the diagram.

• Updated xN Clock Lines section with maximum channel span limitations and added a exception for

QPI protocols.

• Added a new image in the FPGA Fabric-Transceiver Interface Clocking section.

• Added a new section for Channel Bonding describing PMA bonding, PMA and PCS bonding in detail.

• Removed xN Clock Network Data Rate Restrictions table.

• Updated chapter to indicate Arria 10 Transceivers support fPLL to fPLL, fPLL to ATX PLL, and fPLL to

CMU PLL cascading.

• Updated Using PLLs and Clock Networks section

— Changed MegaWizard references to IP Catalog and Parameter Editor.

— Updated the valid configurations for PLL IP and Native PHY IP per 14.0A10 release change.

• Removed Table "xN Clock Network Data Rate Restrictions".

• Updated the chapter to indicate Arria 10 transceivers support to fPLL to fPLL, fPLL to ATX PLL, and fPLL to CMU PLL cascading.

Initial release.


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4. Resetting Transceiver Channels

To ensure that transceiver channels are ready to transmit and receive data, you must properly reset the transceiver PHY. Intel recommends a reset sequence that ensures the physical coding sublayer (PCS) and physical medium attachment (PMA) in each transceiver channel initialize and function correctly. You can either use the Transceiver

PHY Reset Controller or create your own reset controller.

4.1. When Is Reset Required?

You can reset the transmitter (TX) and receiver (RX) data paths independently or together. The recommended reset sequence requires reset and initialization of the PLL driving the TX or RX channels, as well as the TX and RX datapaths. A reset is required after any of the following events:

Table 244.

Reset Conditions

Event

Device power up and configuration

PLL reconfiguration

Reset Requirement

Requires reset to the transceiver PHY and the associated PLLs to a known initialize state.

Requires reset to ensure that the PLL acquires lock and also to reset the PHY. Both the

PLL and the transmitter channel must be held in reset before performing PLL reconfiguration.

Requires reset to the PLL to ensure PLL lock. You must also reset the PHY.

PLL reference clock frequency change

PLL recalibration

PLL lock loss or recovery

Channel dynamic reconfiguration

Optical module connection

RX CDR lock mode change

Requires reset to the PLL to ensure PLL lock. You must also reset the PHY. Both the PLL and the transmitter channel must be held in reset before performing PLL recalibration.

Requires reset after a PLL acquired lock from a momentary loss of lock. You must also reset the PHY.

Requires holding the channel in reset before performing a dynamic reconfiguration that causes rate change. A PLL reset is not required during channel reconfiguration.

Requires reset of RX to ensure lock of incoming data.

Requires reset of the RX channel any time the RX clock and data recovery (CDR) block switches from lock-to-reference to lock-to-data RX channel.

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2008

Registered

4. Resetting Transceiver Channels

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4.2. Transceiver PHY Implementation

Figure 199. Typical Transceiver PHY Implementation clock

Reset Controller

(user-coded or Intel IP) tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset

Transceiver PHY Instance

Transmitter

PCS user reset tx_cal_busy (1) rx_cal_busy rx_is_lockedtoref rx_is_lockedtodata

Receiver

PCS

Transmitter

PMA

Receiver

PMA tx_analogreset_ack (2) rx_analogreset_ack (2)

Note:

Transmit

PLL clk_usrpin

Transceiver Reset Sequencer Inferred Block

Optional

Notes:

(1) You can logical OR the pll_cal_busy and tx_cal_busy signals.

(2) tx_analogreset_ack and rx_analogreset_ack are status signals from the Transceiver PHY IP core when these ports are enabled for manual user implementation of Model 2.

Transceiver Reset Endpoints—The Transceiver PHY IP core contains Transceiver

Reset Endpoints (TREs)

( 59

) .

Transceiver Reset Sequencer—The Quartus Prime software detects the presence of

TREs and automatically inserts only one Transceiver Reset Sequencer (TRS) (

59 )

. The tx_analogreset

and rx_analogreset requests from the reset controller (User coded or Transceiver PHY Reset Controller) is received by the TREs. The TRE sends the reset request to the TRS for scheduling. TRS schedules all the requested PMA resets and sends them back to TREs. You can use either Transceiver PHY Reset Controller or your own reset controller. However, for the TRS to work correctly, the required timing

duration must be followed. See Figure 200 on page 419 for required timing duration.

• The TRS IP is an inferred block and is not visible in the RTL. You have no control over this block.

CLKUSR connection—The clock to the TRS must be stable and free-running

(100-125 MHz). By default, the Quartus Prime software automatically connects the

TRS clock input to the CLKUSR pin on the device. If you are using the CLKUSR pin for your own logic (feeding it to the core), you must instantiate altera_a10_xcvr_clock_module

: altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk));

For more information about the CLKUSR pin, refer to the Arria 10 Pin Connection

Guidelines.

(59) There is only one centralized TRS instantiated for one or more Native PHY.


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Note: To successfully complete the calibration process, the reference clocks driving the PLLs

(ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration. Otherwise, recalibration is necessary.


• Arria 10 Pin Connection Guidelines

•

Calibration

on page 567


4.3. How Do I Reset?

You reset a transceiver PHY or PLL by integrating a reset controller in your system design to initialize the PCS and PMA blocks. You can save time by using the Intelprovided Transceiver PHY Reset Controller IP core, or you can implement your own reset controller that follows the recommended reset sequence. You can design your own reset controller if you require individual control of each signal for reset or need additional control or status signals as part of the reset functionality.

You can choose from two models for resetting the transceivers, based on your applications:

• Model 1—Default model (Minimum Assertion Time Requirement)

Choose the Arria 10 Default Settings preset for the Transceiver PHY Reset

Controller IP.

The chapter Transceiver Reset Control in Arria 10 Devices explains the default model in detail.

• Model 2—Acknowledgment model

This model uses an event-driven mechanism. The model is used for applications with strict timing requirements.

4.3.1. Model 1: Default Model

4.3.1.1. Recommended Reset Sequence

How to Enable Model 1

Choose the Figure 200 on page 419 for the Transceiver PHY Reset Controller IP. This

populates the reset duration fields with the correct values required by the transceiver reset sequencer (TRS).

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Figure 200. Arria 10 Default Settings Preset


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Figure 201. Transmitter and Receiver Reset Sequence

1

Transmit or

Receive

2

FPGA Device

Power Up/Operation

3

Ensure Calibration

Completed

4

5

6

7

PLL,TX/RX Analog

Reset Asserted

Wait for required time and all gating

conditions and release PLL/Analog

resets

Associated PLL/CDR

Locked

Release TX/RX

Digital Reset

8

TX/RX Reset

Completed

4.3.1.1.1. Resetting the Transmitter During Device Operation

Follow this reset sequence to reset the PLL or the analog or digital blocks of the transmitter at any point during the device operation. Use this reset sequence to reestablish a link or after dynamic reconfiguration. The following steps detail the transmitter reset sequence during device operation. The step numbers correspond to the numbers in the following figure.

1. Perform the following steps:

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a. Assert tx_analogreset

, pll_powerdown

, and tx_digitalreset

while pll_cal_busy

and tx_cal_busy

are low.

b. Deassert pll_powerdown

after a minimum duration of 70 μs.

c. Deassert tx_analogreset

. This step can be done at the same time or after you deassert pll_powerdown

.

2. The pll_locked

signal goes high after the TX PLL acquires lock. Wait for a minimum of 70 μs after deasserting tx_analogreset

to monitor the pll_locked

signal.

3. Deassert tx_digitalreset

, after pll_locked

goes high. The tx_digitalreset

signal must stay asserted for a minimum t tx_digitalreset duration after tx_analogreset

is deasserted.

Note: You must reset the PCS blocks by asserting tx_digitalreset

, every time you assert pll_powerdown

and tx_analogreset

.

Figure 202. Transmitter Reset Sequence During Device Operation

Device Power Up pll_cal_busy tx_cal_busy t req t req tx_analogreset pll_powerdown pll_locked tx_digitalreset treq = 70 μs

1 2

Note:

(1) The Arria 10 Default setting presets tx_digitalreset to 70 μs.

(2) Area in gray is don’t care logic state.

3 t (1) tx_digitalreset


Arria 10 Device Datasheet

4.3.1.1.2. Resetting the Receiver During Device Operation

Follow this reset sequence to reset the analog or digital blocks of the receiver at any point during the device operation. Use this reset to re-establish a link or after dynamic reconfiguration.


421