ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals.

The ST62E60C is the erasable EPROM version of the ST62T60C device, which may be used to emulate the ST62T53C, ST62T60C and ST62T63C devices, as well as the respective ST6253C,

ST6260B and ST6263B ROM devices.

OTP and EPROM devices are functionally identical. The ROM based versions offer the same functionality selecting as ROM options the options defined in the programmable option byte of the OTP/

EPROM versions.

OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required.

These compact low-cost devices feature a Timer comprising an 8-bit counter and a 7-bit programmable prescaler, an 8-bit Auto-Reload Timer,

EEPROM data capability (except ST62T53C), a serial port communication interface, an 8-bit A/D

Converter with 7 analog inputs and a Digital

Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications.

Figure 1. Block Diagram

PORT A PA0..PA3 / Ain

8-BIT

A/D CONVERTER

TEST/V

PP TEST

PORT B

PB0..PB3 / 30 mA Sink

PB6 / ARTimin / 30 mA Sink

PB7 / ARTimout / 30 mA Sink

NMI INTERRUPT

DATA ROM

USER

SELECTABLE

PORT C PC2 / Sin / Ain

PC3 / Sout / Ain

PC4 / Sck / Ain

PROGRAM

MEMORY

1836 bytes OTP

(ST62T53C,T63C)

3884 bytes OTP

(ST62T60C)

3884 bytes EPROM

(ST62E60C)

DATA RAM

128 Bytes

AUTORELOAD

TIMER

DATA EEPROM

64 Bytes

(ST62T63C)

128 Bytes

(ST62T60C/E60C)

STACK LEVEL 1

STACK LEVEL 2

DIGITAL

STACK LEVEL 3

STACK LEVEL 4

Obsolete Product(s) - Obsolete Product(s)

STACK LEVEL 6

8 BIT CORE WATCHDOG

POWER

SUPPLY

SPI (SERIAL

PERIPHERAL

INTERFACE)

OSCILLATOR RESET

OSCin OSCout RESET

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ST6253C ST6263C ST6263B ST6260C ST6260B

1.2 PIN DESCRIPTIONS

and V

. Power is supplied to the MCU via these two pins. V

is the power connection and

is the ground connection.

OSCin and OSCout.

These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins.

The OSCin pin is the input pin, the OSCout pin is the output pin.

RESET . The active-low RESET pin is used to restart the microcontroller.

TEST/V

. The TEST must be held at V

for normal operation. If TEST pin is connected to a

+12.5V level during the reset phase, the EPROM/

OTP programming Mode is entered.

NMI . The NMI pin provides the capability for asynchronous interruption, by applying an external non maskable interrupt to the MCU. It is provided with an on-chip pullup resistor (if option has been enabled), and Schmitt trigger characteristics.

PA0-PA3. These 4 lines are organized as one I/O port (A). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs, analog inputs for the A/D converter.

PB0-PB3.

These 4 lines are organized as one I/O port (B). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs.

PB0-PB3 can also sink 30mA for direct LED driving.

PB6/ARTIMin, PB7/ARTIMout . These pins are either Port B I/O bits or the Input and Output pins of the AR TIMER. To be used as timer input function

PB6 has to be programmed as input with or without pull-up. A dedicated bit in the AR TIMER Mode

Control Register sets PB7 as timer output function.

PB6-PB7 can also sink 30mA for direct LED driving.

PC2-PC4 . These 3 lines are organized as one I/O port (C). Each line may be configured under software control as input with or without internal pullup resistor, interrupt generating input with pull-up resistor, analog input for the A/D converter, opendrain or push-pull output.

PC2-PC4 can also be used as respectively Data in, Data out and Clock I/O pins for the on-chip SPI to carry the synchronous serial I/O signals.

Figure 2ST62T53C/T60C/T63C/E60C Pin

Configuration

PB0

PB1

/TEST

PB2

PB3

ARTIMin/PB6

ARTIMout/PB7

Ain/PA0

PC2 / Sin / Ain

PC3 / Sout / Ain

PC4 / Sck / Ain

NMI

RESET

OSCout

OSCin

PA3/Ain

PA2/Ain

PA1/Ain

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

1.3 MEMORY MAP

1.3.1 Introduction

The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs.

Figure 3Memory Addressing Diagram

Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting.

PROGRAM SPACE

0000h

PROGRAM

MEMORY

0FF0h

0FFFh

INTERRUPT &

RESET VECTORS

0-63

DATA SPACE

000h

RAM / EEPROM

BANKING AREA

03Fh

040h

DATA READ-ONLY

MEMORY WINDOW

07Fh

080h

081h

082h

083h

084h

0C0h

0FFh

X REGISTER

Y REGISTER

V REGISTER

W REGISTER

RAM

DATA READ-ONLY

MEMORY

WINDOW SELECT

DATA RAM

BANK SELECT

ACCUMULATOR

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

MEMORY MAP (Cont’d)

1.3.2 Program Space

Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register

(PC register).

1.3.2.1 Program Memory Protection

The Program Memory in OTP or EPROM devices can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte.

Figure 4ST62E60C/T60C Program

Memory Map

0000h

007Fh

0080h

RESERVED

In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context erasure.

Note: Once the Readout Protection is activated, it is no longer possible, even for STMicroelectronics, to gain access to the OTP contents. Returned parts with a protection set can therefore not be accepted.

Figure 5ST62T53C/T63C Program

Memory Map

0000h

RESERVED

USER

PROGRAM MEMORY

(OTP/EPROM)

3872 BYTES

087Fh

0880h

USER

PROGRAM MEMORY

(OTP)

1824 BYTES

0F9Fh

0FA0h

0FEFh

RESERVED

0FF8h

0FFBh

0FFCh

0FFDh

0FFEh

0FFFh

INTERRUPT VECTORS

RESERVED

NMI VECTOR

USER RESET VECTOR

(*) Reserved areas should be filled with 0FFh

0F9Fh

0FA0h

0FEFh

0FF0h

0FF7h

0FF8h

0FFBh

0FFCh

0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

RESERVED

NMI VECTOR

USER RESET VECTOR

(*) Reserved areas should be filled with 0FFh

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ST6253C ST6263C ST6263B ST6260C ST6260B

MEMORY MAP (Cont’d)

1.3.3 Data Space

Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in OTP/

EPROM.

1.3.3.1 Data ROM

All read-only data is physically stored in program memory, which also accommodates the Program

Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application.

The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM.

1.3.3.2 Data RAM/EEPROM

In ST62T53C, T60C, T63C and ST62E60C devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRW register).

Additional RAM and EEPROM pages can also be addressed using banks of 64 bytes located between addresses 00h and 3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents.

Table 1. Additional RAM/EEPROM Banks

Device RAM EEPROM

Table 2ST62T53C, T60C, T63C and ST62E60C

Data Memory Space

RAM and EEPROM

DATA ROM WINDOW AREA

X REGISTER

Y REGISTER

V REGISTER

W REGISTER

DATA RAM 60 BYTES

PORT A DATA REGISTER

PORT B DATA REGISTER

PORT C DATA REGISTER

RESERVED

PORT A DIRECTION REGISTER

PORT B DIRECTION REGISTER

PORT C DIRECTION REGISTER

RESERVED

INTERRUPT OPTION REGISTER

DATA ROM WINDOW REGISTER

RESERVED

PORT A OPTION REGISTER

PORT B OPTION REGISTER

PORT C OPTION REGISTER

RESERVED

A/D DATA REGISTER

A/D CONTROL REGISTER

TIMER PRESCALER REGISTER

TIMER COUNTER REGISTER

TIMER STATUS CONTROL REGISTER

AR TIMER MODE CONTROL REGISTER

AR TIMER STATUS/CONTROL REGISTER1

AR TIMER STATUS/CONTROL REGISTER2

WATCHDOG REGISTER

AR TIMER RELOAD/CAPTURE REGISTER

AR TIMER COMPARE REGISTER

AR TIMER LOAD REGISTER

OSCILLATOR CONTROL REGISTER

MISCELLANEOUS

RESERVED

000h

03Fh

040h

0D1h

0D2h

0D3h

0D4h

0D5h

0D6h

0D7h

0D8h

0C9h*

0CAh

0CBh

0CCh

0CDh

0CEh

0CFh

0D0h

0D9h

0DAh

0DBh

0DCh*

0DDh

0DEh

0DFh

0E0h

0C1h

0C2h

0C3h

0C4h

0C5h

0C6h

0C7h

0C8h*

07Fh

080h

081h

082h

083h

084h

0BFh

0C0h

ST62T53C 1 x 64 bytes -

SPI DATA REGISTER

SPI DIVIDER REGISTER 0E1h

ST62T60C/E60C

ST62T63C

1 x 64 bytes

2 x 64 bytes

1 x 64 bytes

SPI MODE REGISTER

RESERVED

0E2h

0E3h

0E7h

DATA RAM/EEPROM REGISTER 0E8h*

0E9h RESERVED

EEPROM CONTROL REGISTER

(except ST62T53C)

0EAh

RESERVED

ACCUMULATOR

* WRITE ONLY REGISTER

0EBh

0FEh

0FFh

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ST6253C ST6263C ST6263B ST6260C ST6260B

MEMORY MAP (Cont’d)

1.3.5 Data Window Register (DWR)

The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh (top memory address depends on the specific device). All the program memory can therefore be used to store either instructions or read-only data. Indeed, the window can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the

Data Window Register (DWR).

The DWR can be addressed like any RAM location in the Data Space, it is however a write-only register and therefore cannot be accessed using singlebit operations. This register is used to position the

64-byte read-only data window (from address 40h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction

(as least significant bits) and the content of the

DWR register (as most significant bits), as illustrated in

Figure 6 below. For instance, when address-

ing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written to prior to the first access to the Data readonly memory window area.

Data Window Register (DWR)

Address: 0C9h — Write Only

DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

Bits 6, 7 = Not used.

Bit 5-0 = DWR6-DWR0: Data read-only memory

Window Register Bits.

These are the Data readonly memory Window bits that correspond to the upper bits of the data read-only memory space.

Caution: This register is undefined on reset. Neither read nor single bit instructions may be used to address this register.

Note: Care is required when handling the DWR register as it is write only. For this reason, the

DWR contents should not be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register’s previous contents. If it is impossible to avoid writing to the DWR during the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the

DWR, it must also write to the image register. The image register must be written first so that, if an interrupt occurs between the two instructions, the

DWR is not affected.

Figure 6Data read-only memory Window Memory Addressing

DATA ROM

WINDOW REGISTER

CONTENTS

(DWR)

5 4 3 2 1 0 PROGRAM SPACE ADDRESS

READ

5 4 3 2 1 0

0 1

40h-7Fh

IN INSTRUCTION

Example:

1 0 1 0 0 0

DWR=28h

0 1 1 0 0 1

59h Obsolete Product(s) - Obsolete Product(s)

ROM

0 1

1 0 1 0 0 0 0 1 1 0 0 1

ADDRESS:A19h

VR01573C

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ST6253C ST6263C ST6263B ST6260C ST6260B

MEMORY MAP (Cont’d)

1.3.6 Data RAM/EEPROM Bank Register

(DRBR)

Address: E8h — Write only

DRBR

Bit 7-5 = These bits are not used

DRBR

Bit 4 DRBR4 . This bit, when set, selects RAM

Page 2.

Bit 3-2 - Reserved. These bits are not used.

Bit 1 - DRBR1 . This bit, when set, selects

EEPROM Page 1, when available.

Bit 0 - DRBR0 . This bit, when set, selects

EEPROM Page 0, when available.

The selection of the bank is made by programming the Data RAM Bank Switch register (DRBR register) located at address E8h of the Data Space according to Table 1. No more than one bank should be set at a time.

The DRBR register can be addressed like a RAM

Data Space at the address E8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the desired 64-byte RAM/EEPROM bank of the

Data Space. The bank number has to be loaded in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from

00h address to 3Fh address).

This register is not cleared during the MCU initialization, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional information. The DRBR register is not modified when an interrupt or a subroutine occurs.

Notes :

Care is required when handling the DRBR register as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel, producing errors.

Care must also be taken not to change the

E²PROM page (when available) when the parallel writing mode is set for the E²PROM, as defined in

EECTL register.

Table 3Data RAM Bank Register Set-up

DRBR ST62T53C ST62T60C/E60C ST62T63C

10h

None

Not Available

RAM Page 2

None

EEPROM Page 0

EEPROM Page 1

Not Available

RAM Page 2

None

EEPROM Page 0

Not Available

RAM Page 2 other Reserved Reserved Reserved Obsolete Product(s) - Obsolete Product(s)

10/83

ST6253C ST6263C ST6263B ST6260C ST6260B

MEMORY MAP (Cont’d)

1.3.7 EEPROM Description

EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage.

Data space from 00h to 3Fh is paged as described in Table 4 . EEPROM locations are accessed directly by addressing these paged sections of data space.

The EEPROM does not require dedicated instructions for read or write access. Once selected via the

Data RAM Bank Register, the active EEPROM page is controlled by the EEPROM Control Register (EECTL), which is described below.

Bit E20FF of the EECTL register must be reset prior to any write or read access to the EEPROM. If no bank has been selected, or if E2OFF is set, any access is meaningless.

Programming must be enabled by setting the

E2ENA bit of the EECTL register.

The E2BUSY bit of the EECTL register is set when the EEPROM is performing a programming cycle.

Any access to the EEPROM when E2BUSY is set is meaningless.

Provided E2OFF and E2BUSY are reset, an EEP-

ROM location is read just like any other data location, also in terms of access time.

Writing to the EEPROM may be carried out in two modes: Byte Mode (BMODE) and Parallel Mode

(PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with consequent speed and power consumption advantages, the latter being particularly important in battery powered circuits).

General Notes :

Data should be written directly to the intended address in EEPROM space. There is no buffer memory between data RAM and the EEPROM space.

When the EEPROM is busy (E2BUSY = “1”)

EECTL cannot be accessed in write mode, it is only possible to read the status of E2BUSY. This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEPROM

Control Register. EECTL bits 4 and 5 are reserved and must never be set.

Care is required when dealing with the EECTL register, as some bits are write only. For this reason, the EECTL contents must not be altered while executing an interrupt service routine.

If it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt occurs between the two instructions, the EECTL will not be affected.

Table 4. Row Arrangement for Parallel Writing of EEPROM Locations

Dataspace addresses.

Banks 0 and 1.

0 1 2 3 4 5 6 7 Byte

ROW7

ROW6

ROW5

ROW4

ROW3

ROW2

38h-3Fh

30h-37h

28h-2Fh

20h-27h

18h-1Fh

10h-17h

ROW1

ROW0

08h-0Fh

Obsolete Product(s) - Obsolete Product(s)

Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.

The number of available 64-byte banks (1 or 2) is device dependent.

Note : The EEPROM is disabled as soon as STOP instruction is executed in order to achieve the lowest power-consumption.

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ST6253C ST6263C ST6263B ST6260C ST6260B

MEMORY MAP (Cont’d)

Additional Notes on Parallel Mode:

If the user wishes to perform parallel programming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be addressed in write mode, the ROW address and the data will be latched and it will be possible to change them only at the end of the programming cycle or by resetting E2PAR2 without programming the EEPROM. After the ROW address is latched, the MCU can only “see” the selected

EEPROM row and any attempt to write or read other rows will produce errors.

The EEPROM should not be read while E2PAR2 is set.

As soon as the E2PAR2 bit is set, the 8 volatile

ROW latches are cleared. From this moment on, the user can load data in all or in part of the ROW.

Setting E2PAR1 will modify the EEPROM registers corresponding to the ROW latches accessed after E2PAR2. For example, if the software sets

E2PAR2 and accesses the EEPROM by writing to addresses 18h, 1Ah and 1Bh, and then sets

E2PAR1, these three registers will be modified simultaneously; the remaining bytes in the row will be unaffected.

Note that E2PAR2 is internally reset at the end of the programming cycle. This implies that the user must set the E2PAR2 bit between two parallel programming cycles. Note that if the user tries to set

E2PAR1 while E2PAR2 is not set, there will be no programming cycle and the E2PAR1 bit will be unaffected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low. The E2PAR1 bit can be set by the user, only if the E2ENA and E2PAR2 bits are also set.

Notes : The EEPROM page shall not be changed through the DRBR register when the E2PAR2 bit is set.

EEPROM Control Register (EECTL )

Address: EAh — Read/Write

Reset status: 00h

E2O

D5 D4

E2PA

E2BU

E2E

Bit 7 = D7 : Unused.

Bit 6 = E2OFF : Stand-by Enable Bit. WRITE ONLY.

If this bit is set the EEPROM is disabled (any access will be meaningless) and the power consumption of the EEPROM is reduced to its lowest value.

Bit 5-4 = D5-D4 : Reserved. MUST be kept reset.

Bit 3 = E2PAR1 : Parallel Start Bit. WRITE ONLY.

Once in Parallel Mode, as soon as the user software sets the E2PAR1 bit, parallel writing of the 8 adjacent registers will start. This bit is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written if required, the undefined bytes being unaffected by the parallel programming cycle; this is explained in greater detail in the Additional Notes on Parallel Mode overleaf.

Bit 2 = E2PAR2 : Parallel Mode En. Bit. WRITE

ONLY. This bit must be set by the user program in order to perform parallel programming. If E2PAR2 is set and the parallel start bit (E2PAR1) is reset, up to 8 adjacent bytes can be written simultaneously. These 8 adjacent bytes are considered as a row, whose address lines A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bits, as illustrated in

Table 4

. E2PAR2 is automatically reset at the end of any parallel programming procedure. It can be reset by the user software before starting the programming procedure, thus leaving the EEPROM registers unchanged.

Bit 1 = E2BUSY : EEPROM Busy Bit. READ ON-

LY. This bit is automatically set by the EEPROM control logic when the EEPROM is in programming mode. The user program should test it before any EEPROM read or write operation; any attempt to access the EEPROM while the busy bit is set will be aborted and the writing procedure in

LY. This bit enables programming of the EEPROM cells. It must be set before any write to the EEP-

ROM register. Any attempt to write to the EEP-

ROM when E2ENA is low is meaningless and will not trigger a write cycle.

The EEPROM is disabled as soon as a STOP instruction is executed in order to achieve the lowest power-consumption.

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ST6253C ST6263C ST6263B ST6260C ST6260B

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configuration capability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when the chip reset is activated.

It can only be accessed during the programming mode. This access is made either automatically

(copy from a master device) or by selecting the

OPTION BYTE PROGRAMMING mode of the programmer.

The option bytes are located in a non-user map.

No address has to be specified.

EPROM Code Option Byte (LSB)

PRO-

TECT

EXTC-

NTL

PB2-3

PULL

PB0-1

PULL

WDACT

DE-

LAY

OSCIL OSGEN

EPROM Code Option Byte (MSB)

ADC

SYNCHRO

NMI

PULL

LVD

D15-D13. Reserved. Must be cleared.

ADC SYNCHRO . When set, an A/D conversion is started upon WAIT instruction execution, in order to reduce supply noise. When this bit is low, an A/

D conversion is started as soon as the STA bit of the A/D Converter Control Register is set.

D11 . Reserved , must be set to one.

D10 . Reserved , must be cleared.

NMI PULL . NMI Pull-Up . This bit must be set high to configure the NMI pin with a pull-up resistor.

When it is low, no pull-up is provided.

LVD.

LVD RESET enable.

When this bit is set, safe

RESET is performed by MCU when the supply voltage is too low. When this bit is cleared, only power-on reset or external RESET are active.

PROTECT . Readout Protection.

This bit allows the protection of the software contents against piracy.

When the bit PROTECT is set high, readout of the

OTP contents is prevented by hardware.. When this bit is low, the user program can be read.

EXTCNTL. External STOP MODE control .

. When

EXTCNTL is high, STOP mode is available with watchdog active by setting NMI pin to one. When

EXTCNTL is low, STOP mode is not available with the watchdog active.

PB2-3 PULL . When set this bit removes pull-up at reset on PB2-PB3 pins. When cleared PB2-PB3 pins have an internal pull-up resistor at reset.

PB0-1 PULL . When set this bit removes pull-up at reset on PB0-PB1 pins. When cleared PB0-PB1 pins have an internal pull-up resistor at reset.

WDACT . This bit controls the watchdog activation.

When it is high, hardware activation is selected.

The software activation is selected when WDACT is low.

DELAY .

This bit enables the selection of the delay internally generated after the internal reset (external pin, LVD, or watchdog activated) is released.

When DELAY is low, the delay is 2048 cycles of the oscillator, it is of 32768 cycles when DELAY is high.

OSCIL . Oscillator selection . When this bit is low, the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency.

When it is high, the oscillator must be controlled by an RC network, with only the resistor having to be externally provided.

OSGEN . Oscillator Safe Guard . This bit must be set high to enable the Oscillator Safe Guard.

When this bit is low, the OSG is disabled.

The Option byte is written during programming either by using the PC menu (PC driven Mode) or automatically (stand-alone mode).

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

PROGRAMMING MODES (Cont’d)

1.4.2 EPROM Erasing

The EPROM of the windowed package of the

MCUs may be erased by exposure to Ultra Violet light. The erasure characteristic of the MCUs is such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlights and some types of fluorescent lamps have wavelengths in the range 3000-4000Å.

It is thus recommended that the window of the

MCUs packages be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment.

The recommended erasure procedure of the

MCUs EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537A.

The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 15Wsec/cm

. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000µW/cm

power rating. The

ST62E60C should be placed within 2.5cm (1Inch) of the lamp tubes during erasure.

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the

I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 7 ; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers.

2.2 CPU REGISTERS

The ST6 Family CPU core features six registers and three pairs of flags available to the programmer.

These are described in the following paragraphs.

Accumulator (A) . The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the

ST6 can manipulate the accumulator just like any other register in Data space.

Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in

Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other register of the data space.

Short Direct Registers (V, W).

These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and

83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the

ST6 instruction set can use the short direct registers as any other register of the data space.

Program Counter (PC). The program counter is a

12-bit register which contains the address of the next ROM location to be processed by the core.

This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.

Figure 7. ST6 Core Block Diagram

RESET

0,01 TO 8MHz

OSCin OSCout

CONTROLLER

INTERRUPTS

DATA SPACE

OPCODE

FLAG

VALUES

CONTROL

SIGNALS

ADDRESS/READ LINE

DATA

RAM/EEPROM

PROGRAM

DATA

ROM/EPROM

ADDRESS

DECODER

256 Obsolete Product(s) - Obsolete Product(s)

A-DATA B-DATA

ROM/EPROM

DEDICATIONS

ACCUMULATOR

Program Counter and

6 LAYER STACK

FLAGS

ALU

RESULTS TO DATA SPACE (WRITE LINE)

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ST6253C ST6263C ST6263B ST6260C ST6260B

CPU REGISTERS (Cont’d)

However, if the program space contains more than

4096 bytes, the additional memory in program space can be addressed by using the Program

Bank Switch register.

The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways:

- JP (Jump) instructionPC=Jump address

- CALL instructionPC= Call address

- Relative Branch Instruction.PC= PC +/- offset

- Interrupt

- Reset

PC=Interrupt vector

PC= Reset vector

- RET & RETI instructionsPC= Pop (stack)

- Normal instructionPC= PC + 1 automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags.

Stack.

The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit

RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its “deepest” position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed.

In this case the next instruction will be executed.

Flags (C, Z) . The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation:

Normal mode, Interrupt mode and Non Maskable

Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZN-

MI).

Figure 8. ST6 CPU Programming Mode

INDEX

X REG. POINTER

Y REG. POINTER b0 b 7 b 7 b0

SHORT

DIRECT

ADDRESSING

MODE

The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6

CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non

Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching and thus retain their status.

b11 b 7 b 7 b 7

V REGISTER

W REGISTER

ACCUMULATOR

PROGRAM COUNTER b0 b0 b0 b0

SIX LEVELS

STACK REGISTER

The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction.

Obsolete Product(s) - Obsolete Product(s) tic or logical operation was equal to zero; other-

NORMAL FLAGS

INTERRUPT FLAGS

Z wise it is cleared.

NMI FLAGS C Z

Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is

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ST6253C ST6263C ST6263B ST6260C ST6260B

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suitable ceramic resonator, or with an external resistor

NET

). In addition, a Low Frequency Auxiliary Oscillator (LFAO) can be switched in for security reasons, to reduce power consumption, or to offer the benefits of a back-up clock system.

Figure 9. Oscillator Configurations

CRYSTAL/RESONATOR CLOCK

CRYSTAL/RESONATOR option

ST6xxx

The Oscillator Safeguard (OSG) option filters spikes from the oscillator lines, provides access to the LFAO to provide a backup oscillator in the event of main oscillator failure and also automatically limits the internal clock frequency (f

INT function of V

) as a

, in order to guarantee correct operation. These functions are illustrated in Figure 10 ,

Figure 11 , Figure 12 and Figure 13 .

A programmable divider on F

INT

is also provided in order to adjust the internal clock of the MCU to the best power consumption and performance tradeoff.

Figure 9 illustrates various possible oscillator configurations using an external crystal or ceramic resonator, an external clock input, an external resistor

NET

), or the lowest cost solution using only the

LFAO. C

an C

should have a capacitance in the range 12 to 22 pF for an oscillator frequency in the

4-8 MHz range.

The internal MCU clock frequency (f

INT

) is divided by 12 to drive the Timer, the A/D converter and the

Watchdog timer, and by 13 to drive the CPU core, as may be seen in Figure 12 .

With an 8 MHz oscillator frequency, the fastest machine cycle is therefore 1.625µs.

A machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the Program Counter). An instruction may require two, four, or five machine cycles for execution.

3.1.1 Main Oscillator

L1n

OSC in

EXTERNAL CLOCK

CRYSTAL/RESONATOR option

OSC in

RC NETWORK

RC NETWORK option

OSC in

ST6xxx

OSC out

NET

The oscillator configuration may be specified by se-

INTEGRATED CLOCK lecting the appropriate option. When the CRYSTAL/

RESONATOR option is selected, it must be used with Obsolete Product(s) - Obsolete Product(s)

WORK option is selected, the system clock is gen-

CRYSTAL/RESONATOR option

OSG ENABLED option

ST6xxx erated by an external resistor.

The main oscillator can be turned off (when the

OSG ENABLED option is selected) by setting the

OSCOFF bit of the ADC Control Register. The

Low Frequency Auxiliary Oscillator is automatically started.

OSC in

OSC out

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CLOCK SYSTEM (Cont’d)

Turning on the main oscillator is achieved by resetting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at f

LFAO

clock frequency.

3.1.2 Low Frequency Auxiliary Oscillator

(LFAO) tions: it filters spikes from the oscillator lines which would result in over frequency to the ST62 CPU; it gives access to the Low Frequency Auxiliary Oscillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumption or to provide a fixed frequency low cost oscillator; finally, it automatically limits the internal clock frequency as a function of supply voltage, in order to ensure correct operation even if the power supply should drop.

The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines.

Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a safety oscillator in case of main oscillator failure.

This oscillator is available when the OSG ENA-

BLED option is selected. In this case, it automatically starts one of its periods after the first missing edge from the main oscillator, whatever the reason

(main oscillator defective, no clock circuitry provided, main oscillator switched off...).

The OSG is enabled or disabled by choosing the relevant OSG option. It may be viewed as a filter whose cross-over frequency is device dependent.

Spikes on the oscillator lines result in an effectively increased internal clock frequency. In the absence of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The

OSG filters out such spikes (as illustrated in Figure

10 ). In all cases, when the OSG is active, the maximum internal clock frequency, f

INT f

OSG lationship is illustrated in Figure 13 .

, is limited to

, which is supply voltage dependent. This re-

User code, normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced f

LFAO

frequency. The A/D converter accuracy is decreased, since the internal frequency is below 1MHz.

When the OSG is enabled, the Low Frequency

Auxiliary Oscillator may be accessed. This oscillator starts operating after the first missing edge of the main oscillator (see Figure 11 ).

At power on, the Low Frequency Auxiliary Oscillator starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR delay until the Main Oscillator runs.

The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts.

Over-frequency, at a given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock frequency of the device is kept within the range the particular device can stand (depending on V and below f

OSG cy with OSG enabled.

: the maximum authorised frequen-

ADCR

Address: 0D1h — Read/Write

7 0

Note. The OSG should be used wherever possible as it provides maximum safety. Care must be taken, however, as it can increase power consumption and reduce the maximum operating frequency to f

OSG

ADCR

OSC

OFF

ADCR

0 Warning : Care has to be taken when using the

OSG, as the internal frequency is defined between

Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0 : a minimum and a maximum value and is not accu-

ADC Control Register . These bits are reserved for rate.

ADC Control.

Bit 2 = OSCOFF . When low, this bit enables main oscillator to run. The main oscillator is switched off

Obsolete Product(s) - Obsolete Product(s)

3.1.3 Oscillator Safe Guard

For precise timing measurements, it is not recommended to use the OSG and it should not be enabled in applications that use the SPI or the UART.

It should also be noted that power consumption in

Stop mode is higher when the OSG is enabled

The Oscillator Safe Guard (OSG) affords drastically increased operational integrity in ST62xx devices. The OSG circuit provides three basic func-

(around 50µA at nominal conditions and room temperature).

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ST6253C ST6263C ST6263B ST6260C ST6260B

CLOCK SYSTEM (Cont’d)

Figure 10. OSG Filtering Principle

(1)

(2)

(3)

(4)

(1)

(2)

(3)

(4)

Maximum Frequency for the device to work correctly

Actual Quartz Crystal Frequency at OSCin pin

Noise from OSCin

Resulting Internal Frequency

Figure 11. OSG Emergency Oscillator Principle

VR001932

Main

Oscillator

Emergency

Oscillator

Obsolete Product(s) - Obsolete Product(s)

Internal

Frequency

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ST6253C ST6263C ST6263B ST6260C ST6260B

CLOCK SYSTEM (Cont’d)

Oscillator Control Registers

Address: DCh — Write only

Reset State: 00h

OSCR

RS1 RS0

Bit 7-4. These bits are not used.

Bit 3. Reserved. Cleared at Reset. Must be kept cleared.

Bit 2. Reserved. Must be kept low.

RS1-RS0. These bits select the division ratio of the Oscillator Divider in order to generate the internal frequency. The following selctions are available:

RS1

RS0

Division Ratio

Note : Care is required when handling the OSCR register as some bits are write only. For this reason, it is not allowed to change the OSCR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to

OSCR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the

OSCR is not affected.

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ST6253C ST6263C ST6263B ST6260C ST6260B

CLOCK SYSTEM (Cont’d)

Figure 12. Clock Circuit Block Diagram

MAIN

OSCILLATOR

OSG

POR f

INT

OSCILLATOR

DIVIDER

RS0,RS1

: 13

Core

TIMER 1

Watchdog

: 12

LFAO

: 1

Main Oscillator off

Figure 13. Maximum Operating Frequency (f

MAX

) versus Supply Voltage (V

)

Maximum FREQUENCY (MHz)

2.5

3 3.6

4 4.5

5 f

OSG f

OSG

Min (at 85°C) f

OSG

Min (at 125°C)

5.5

SUPPLY VOLTAGE (V

)

VR01807J

Notes : Obsolete Product(s) - Obsolete Product(s) quartz crystal frequency.

2. When the OSG is disabled, operation in this area is guaranteed at the quartz crystal frequency.

When the OSG is enabled, access to this area is prevented. The internal frequency is kept a f

OSG.

area is guaranteed at the crystal frequency. When the OSG is enabled, operation in this area is guaranteed at a frequency of at least f

OSG Min.

3. When the OSG is disabled, operation in this

4. When the OSG is disabled, operation in this area is not guaranteed

When the OSG is enabled, access to this area is prevented. The internal frequency is kept at f

OSG.

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ST6253C ST6263C ST6263B ST6260C ST6260B

3.2 RESETS

The MCU can be reset in four ways:

– by the external Reset input being pulled low;

– by Power-on Reset;

– by the digital Watchdog peripheral timing out.

– by Low Voltage Detection (LVD)

3.2.1 RESET Input

The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in

RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal

Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided V

has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes).

The MCU is kept in the Reset state as long as the

RESET pin is held low.

If RESET activation occurs in the RUN or WAIT modes, processing of the user program is stopped

(RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors and the main Oscillator is restarted. When the level on the

RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

is executed immediately following the internal delay.

To ensure correct start-up, the user should take care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see recommended operation) before the reset signal is released. In addition, supply rising must start from

0V.

As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy

(presenting oscillation) VDD supplies.

An external RC network connected to the RESET pin, or the LVD reset can be used instead to get the best performances.

Figure 14. Reset and Interrupt Processing

RESET

NMI MASK SET

INT LATCH CLEARED

( IF PRESENT )

SELECT

NMI MODE FLAGS

If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors.

When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

PUT FFEH

ON ADDRESS BUS

3.2.2 Power-on Reset

YES

IS RESET STILL

PRESENT?

The function of the POR circuit consists in waking up the MCU by detecting around 2V a dynamic

(rising edge) variation of the VDD Supply. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to

LOAD PC

FROM RESET LOCATIONS

FFE/FFF a sufficient level, the oscillator starts to operate, Obsolete Product(s) - Obsolete Product(s) ing the first instruction. The initialization sequence

FETCH INSTRUCTION

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ST6253C ST6263C ST6263B ST6260C ST6260B

RESETS (Cont’d)

3.2.3 Watchdog Reset

The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter.

The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period.

3.2.4 LVD Reset

The on-chip Low Voltage Detector, selectable as user option, features static Reset when supply voltage is below a reference value. Thanks to this feature, external reset circuit can be removed while keeping the application safety. This SAFE

RESET is effective as well in Power-on phase as in power supply drop with different reference values, allowing hysteresis effect. Reference value in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic Reset when MCU start's running and sinking current on the supply.

As long as the supply voltage is below the reference value, there is a internal and static RESET command. The MCU can start only when the supply voltage rises over the reference value. Therefore, only two operating mode exist for the MCU:

RESET active below the voltage reference, and running mode over the voltage reference as shown on the Figure 15 , that represents a powerup, power-down sequence.

Note : When the RESET state is controlled by one of the internal RESET sources (Low Voltage Detector, Watchdog, Power on Reset), the RESET pin is tied to low logic level.

Figure 15. LVD Reset on Power-on and Power-down (Brown-out)

V dn

RESET

RESET time

VR02106A

Obsolete Product(s) - Obsolete Product(s)

No external resistor is required between V

and the Reset pin, thanks to the built-in pull-up device.

Direct external connection of the pin RESET to

must be avoided in order to ensure safe behaviour of the internal reset sources (AND.Wired structure).

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ST6253C ST6263C ST6263B ST6260C ST6260B

RESETS (Cont’d)

3.2.6 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the

MCU will continue by processing the instruction immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced.

Figure 16. Reset and Interrupt Processing

RESET

VECTOR

INITIALIZATION

ROUTINE

RESET

RETI

JP:2 BYTES/4 CYCLES

RETI: 1 BYTE/2 CYCLES

VA00181

Figure 17. Reset Block Diagram

RESET

ESD

1) f

OSC

AND. Wired

COUNTER

RESET

POWER ON RESET

WATCHDOG RESET

LVD RESET

ST6

INTERNAL

RESET

VR02107A

1) Resistive ESD protection. Value not guaranteed.

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ST6253C ST6263C ST6263B ST6260C ST6260B

RESETS (Cont’d)

Table 5Register Reset Status

Register Address(es)

Oscillator Control Register

EEPROM Control Register

Port Data Registers

Port Direction Register

Port Option Register

Interrupt Option Register

TIMER Status/Control

0DCh

0EAh

0C0h to 0C2h

0C4h to 0C6h

0CCh to 0CEh

0C8h

0D4h

AR TIMER Mode Control Register

AR TIMER Status/Control 0 Register

AR TIMER Status/Control 1 Register

AR TIMER Compare Register

0D5h

0D6h

0D7h

Miscellaneous Register

SPI Registers

SPI DIV Register

SPI MOD Register

SPI DSR Register

0DDh

0E0h to 0E2h

0E1h

0E2h

0E0h

X, Y, V, W, Register

Accumulator

Data RAM

Data RAM Page REgister

Data ROM Window Register

EEPROM

A/D Result Register

AR TIMER Load Register

AR TIMER Reload/Capture Register

080H TO 083H

0FFh

084h to 0BFh

0E8h

0C9h

00h to 03Fh

0D0h

0DBh

0D9h

TIMER Counter Register

TIMER Prescaler Register

Watchdog Counter Register

A/D Control Register

0D3h

0D2h

0D8h

0D1h

Status

00h

Undefined

FFh

7Fh

FEh

40h

Comment

EEPROM disabled (if available)

I/O are Input with pull-up

Interrupt disabled

TIMER disabled

AR TIMER stopped

SPI Output not connected to PC3

SPI disabled

As written if programmed

Max count loaded

A/D in Standby

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ST6253C ST6263C ST6263B ST6260C ST6260B

3.3 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets.

The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. In the event of a software mishap (usually caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be reloaded periodically. Consequently the timer will decrement down to 00h and reset the MCU. In order to maximise the effectiveness of the Watchdog function, user software must be written with this concept in mind.

Watchdog behaviour is governed by two options, known as “WATCHDOG ACTIVATION” (i.e.

HARDWARE or SOFTWARE) and “EXTERNAL

STOP MODE CONTROL” (see Table 6 ).

In the SOFTWARE option, the Watchdog is disabled until bit C of the DWDR register has been set.

When the Watchdog is disabled, low power Stop mode is available. Once activated, the Watchdog cannot be disabled, except by resetting the MCU.

In the HARDWARE option, the Watchdog is permanently enabled. Since the oscillator will run continuously, low power mode is not available. The

STOP instruction is interpreted as a WAIT instruction, and the Watchdog continues to countdown.

However, when the EXTERNAL STOP MODE

CONTROL option has been selected low power consumption may be achieved in Stop Mode.

Execution of the STOP instruction is then governed by a secondary function associated with the

NMI pin. If a STOP instruction is encountered when the NMI pin is low, it is interpreted as WAIT, as described above. If, however, the STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU enters STOP mode.

When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity.

Table 6. Recommended Option Choices

Functions Required

Stop Mode & Watchdog

Stop Mode

Watchdog

Recommended Options

“EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”

“SOFTWARE WATCHDOG”

“HARDWARE WATCHDOG”

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

DIGITAL WATCHDOG (Cont’d)

The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, location 0D8h) which is described in greater detail in

Section 3.3.1 Digital Watchdog Register (DWDR) .

This register is set to 0FEh on Reset: bit C is cleared to “0”, which disables the Watchdog; the timer downcounter bits, T0 to T5, and the SR bit are all set to “1”, thus selecting the longest Watchdog timer period. This time period can be set to the user’s requirements by setting the appropriate value for bits T0 to T5 in the DWDR register. The SR bit must be set to “1”, since it is this bit which generates the Reset signal when it changes to “0”; clearing this bit would generate an immediate Reset.

It should be noted that the order of the bits in the

DWDR register is inverted with respect to the associated bits in the down counter: bit 7 of the

DWDR register corresponds, in fact, to T0 and bit

2 to T5. The user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this register. The relationship between the DWDR register bits and the physical implementation of the Watchdog timer downcounter is illustrated in Figure 18 .

Only the 6 most significant bits may be used to define the time period, since it is bit 6 which triggers the Reset when it changes to “0”. This offers the user a choice of 64 timed periods ranging from

3,072 to 196,608 clock cycles (with an oscillator frequency of 8 MHz, this is equivalent to timer periods ranging from 384 µs to 24.576 ms).

Figure 18. Watchdog Counter Control

RESET

OSC

VR02068A

Obsolete Product(s) - Obsolete Product(s)

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DIGITAL WATCHDOG (Cont’d)

3.3.1 Digital Watchdog Register (DWDR)

Address: 0D8h — Read/Write

Reset status: 1111 1110 b

T0 T1 T2 T3 T4 T5 SR

Bit 0 = C : Watchdog Control bit

If the hardware option is selected, this bit is forced high and the user cannot change it (the Watchdog is always active). When the software option is selected, the Watchdog function is activated by setting bit C to 1, and cannot then be disabled (save by resetting the MCU).

When C is kept low the counter can be used as a

7-bit timer.

This bit is cleared to “0” on Reset.

Bit 1 = SR : Software Reset bit

This bit triggers a Reset when cleared.

When C = “0” (Watchdog disabled) it is the MSB of the 7-bit timer.

This bit is set to “1” on Reset.

Bits 2-7 = T5-T0 : Downcounter bits

It should be noted that the register bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the LSB of the Watchdog downcounter and bit-2 (T5) is the MSB.

These bits are set to “1” on Reset.

3.3.2 Application Notes

The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices, and should be used wherever possible. Watchdog related options should be selected on the basis of a trade-off between application security and STOP mode availability.

When STOP mode is not required, hardware activation without EXTERNAL STOP MODE CON-

TROL should be preferred, as it provides maximum security, especially during power-on.

When STOP mode is required, hardware activation and EXTERNAL STOP MODE CONTROL should be chosen. NMI should be high by default, to allow STOP mode to be entered when the MCU is idle.

The NMI pin can be connected to an I/O line (see

Figure 19 ) to allow its state to be controlled by software. The I/O line can then be used to keep NMI low while Watchdog protection is required, or to avoid noise or key bounce. When no more processing is required, the I/O line is released and the device placed in STOP mode for lowest power consumption.

When software activation is selected and the

Watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember that the bits are in reverse order).

The software activation option should be chosen only when the Watchdog counter is to be used as a timer. To ensure the Watchdog has not been unexpectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, WD, #+3 ldi WD, 0FDH

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DIGITAL WATCHDOG (Cont’d)

These instructions test the C bit and Reset the

MCU (i.e. disable the Watchdog) if the bit is set

(i.e. if the Watchdog is active), thus disabling the

Watchdog.

In all modes, a minimum of 28 instructions are executed after activation, before the Watchdog can generate a Reset. Consequently, user software should load the watchdog counter within the first

27 instructions following Watchdog activation

(software mode), or within the first 27 instructions executed following a Reset (hardware activation).

It should be noted that when the GEN bit is low (interrupts disabled), the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes.

Figure 19. A typical circuit making use of the

EXERNAL STOP MODE CONTROL feature

SWITCH

NMI

I/O

VR02002

Figure 20. Digital Watchdog Block Diagram

RESET

RSFF

-2

DB1.7

LOAD SET

-2

SET

-12

OSCILLATOR

CLOCK

DB0

WRITE

RESET

DATA BUS

VA00010

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3.4 INTERRUPTS

The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is associated with a specific Interrupt Vector which contains a Jump instruction to the associated interrupt service routine. These vectors are located in Program space (see Table 7 ).

When an interrupt source generates an interrupt request, and interrupt processing is enabled, the

PC register is loaded with the address of the interrupt vector (i.e. of the Jump instruction), which then causes a Jump to the relevant interrupt service routine, thus servicing the interrupt.

Interrupt sources are linked to events either on external pins, or on chip peripherals. Several events can be ORed on the same interrupt source, and relevant flags are available to determine which event triggered the interrupt.

The Non Maskable Interrupt request has the highest priority and can interrupt any interrupt routine at any time; the other four interrupts cannot interrupt each other. If more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. The priority of each interrupt source is fixed.

Table 7. Interrupt Vector Map

Interrupt Source

Interrupt source #0

Interrupt source #1

Interrupt source #2

Interrupt source #3

Interrupt source #4

Priority

Vector Address

(FFCh-FFDh)

(FF6h-FF7h)

(FF4h-FF5h)

(FF2h-FF3h)

(FF0h-FF1h)

3.4.1 Interrupt request

All interrupt sources but the Non Maskable Interrupt source can be disabled by setting accordingly the GEN bit of the Interrupt Option Register (IOR).

This GEN bit also defines if an interrupt source, including the Non Maskable Interrupt source, can restart the MCU from STOP/WAIT modes.

ically reset by the core at the beginning of the nonmaskable interrupt service routine.

Interrupt request from source #1 can be configured either as edge or level sensitive by setting accordingly the LES bit of the Interrupt Option Register (IOR).

Interrupt request from source #2 are always edge sensitive. The edge polarity can be configured by setting accordingly the ESB bit of the Interrupt Option Register (IOR).

Interrupt request from sources #3 & #4 are level sensitive.

In edge sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started.

So, the occurrence of an interrupt can be stored, until completion of the running interrupt routine before being processed. If several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored.

Storage of interrupt requests is not available in level sensitive mode. To be taken into account, the low level must be present on the interrupt pin when the MCU samples the line after instruction execution.

At the end of every instruction, the MCU tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropriate interrupt service routine is executed instead.

Table 8. Interrupt Option Register Description

GEN

ESB

LES

OTHERS

SET Enable all interrupts

CLEARED Disable all interrupts

SET

CLEARED

Rising edge mode on interrupt source #2

Falling edge mode on interrupt source #2

SET

CLEARED

Level-sensitive mode on interrupt source #1

Falling edge mode on interrupt source #1

NOT USED

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INTERRUPTS (Cont’d)

3.4.2 Interrupt Procedure

The interrupt procedure is very similar to a call procedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred. As a result, the user should save all Data space registers which may be used within the interrupt routines.

There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved.

MCU

– Automatically the MCU switches back to the normal flag set (or the interrupt flag set) and pops the previous PC value from the stack.

The interrupt routine usually begins by the identifying the device which generated the interrupt request (by polling). The user should save the registers which are used within the interrupt routine in a software stack. After the RETI instruction is executed, the MCU returns to the main routine.

Figure 21. Interrupt Processing Flow Chart

INSTRUCTION

The following list summarizes the interrupt procedure:

MCU

– The interrupt is detected.

– The C and Z flags are replaced by the interrupt flags (or by the NMI flags).

– The PC contents are stored in the first level of the stack.

– The normal interrupt lines are inhibited (NMI still active).

– The first internal latch is cleared.

– The associated interrupt vector is loaded in the PC.

FETCH

INSTRUCTION

EXECUTE

INSTRUCTION

WAS

THE INSTRUCTION

A RETI

LOAD PC FROM

INTERRUPT VECTOR

(FFC/FFD)

YES

WARNING: In some circumstances, when a maskable interrupt occurs while the ST6 core is in

NORMAL mode and especially during the execution of an "ldi IOR, 00h" instruction (disabling all maskable interrupts): if the interrupt arrives during the first 3 cycles of the "ldi" instruction (which is a

4-cycle instruction) the core will switch to interrupt mode BUT the flags CN and ZN will NOT switch to the interrupt pair CI and ZI.

YES

CLEAR

INTERRUPT MASK

SELECT

PROGRAM FLAGS

IS THE CORE

ALREADY IN

NORMAL MODE?

SET

INTERRUPT MASK

PUSH THE

PC INTO THE STACK

SELECT

INTERNAL MODE FLAG

User

– User selected registers are saved within the interrupt service routine (normally on a software stack).

– The source of the interrupt is found by polling the interrupt flags (if more than one source is associated with the same vector).

– The interrupt is serviced.

"POP"

THE STACKED PC

YES

CHECK IF THERE IS

AN INTERRUPT REQUEST

AND INTERRUPT MASK

VA000014

– Return from interrupt (RETI)

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INTERRUPTS (Cont’d)

3.4.3 Interrupt Option Register (IOR)

The Interrupt Option Register (IOR) is used to enable/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations.

Address: 0C8h —

Reset status: 00h

Write Only

LES ESB GEN -

Bit 5 = ESB : Edge Selection bit .

The bit ESB selects the polarity of the interrupt source #2.

Bit 4 = GEN : Global Enable Interrupt . When this bit is set to one, all interrupts are enabled. When this bit is cleared to zero all the interrupts (excluding

NMI) are disabled.

When the GEN bit is low, the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes.

This register is cleared on reset.

3.4.4 Interrupt sources

Bit 7, Bits 3-0 = Unused .

Bit 6 = LES : Level/Edge Selection bit .

When this bit is set to one, the interrupt source #1 is level sensitive. When cleared to zero the edge sensitive mode for interrupt request is selected.

Table 9Interrupt Requests and Mask Bits

Peripheral Register

Address

Register

GENERAL

TIMER

IOR

TSCR1

A/D CONVERTER ADCR

C8h

D4h

D1h

AR TIMER

SPI

Port PAn

Port PBn

Port PCn

ARMC

SPIMOD

ORPA-DRPA

ORPB-DRPB

ORPC-DRPC

D5h

E2h

C0h-C4h

C1h-C5h

C2h-C6h

Interrupt sources available on these MCUs are summarized in the

Table 9 with associated mask

bit to enable/disable the interrupt request.

Mask bit Masked Interrupt Source

Interrupt vector

GEN

ETI

EAI

OVIE

CPIE

EIE

All Interrupts, excluding NM

TMZ: TIMER Overflow

EOC: End of Conversion

OVF: AR TIMER Overflow

CPF: Successful compare

EF: Active edge on ARTIMin

Vector 4

Vector 3

SPIE SPRUN: End of Transmission Vector 2

ORPAn-DRPAn PAn pin Vector 1

ORPBn-DRPBn PBn pin

ORPCn-DRPCn PCn pin

Vector 1

Vector 2

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INTERRUPTS (Cont’d)

Figure 22. Interrupt Block Diagram

FROM REGISTER PORT A,B,C

SINGLE BIT ENABLE

PBE

PORT A

PORT B

Bits

PBE

CLK

CLR

Q 0

Start

MUX

INT #1 (FF6,7)

IOR REG. C8H, bit 6

RESTART FROM

STOP/WAIT

PORT C

Bits

INT #2 (FF4,5) PBE

SPIDIV Register

SPINT bit

SPIE bit

IOR REG. C8H, bit 5

SPIMOD Register

AR TIMER

TIMER1

ADC

OVF

OVIE

CPF

CPIE

EIE

TMZ

ETI

EOC

EAI

CLK Q

CLR

Start

INT #3 (FF2,3)

INT #4 (FF0,1)

NMI

NMI (FFC,D)

CLK

CLR

Start

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3.5 POWER SAVING MODES

The WAIT and STOP modes have been implemented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following paragraphs.

3.5.1 WAIT Mode

The MCU goes into WAIT mode as soon as the

WAIT instruction is executed. The microcontroller can be considered as being in a “software frozen” state where the core stops processing the program instructions, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage. In this mode the peripherals are still active.

WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods, while not losing track of time or the capability of monitoring external events. The active oscillator is not stopped in order to provide a clock signal to the peripherals. Timer counting may be enabled as well as the Timer interrupt, before entering the WAIT mode: this allows the WAIT mode to be exited when a Timer interrupt occurs. The same applies to other peripherals which use the clock signal.

If the WAIT mode is exited due to a Reset (either by activating the external pin or generated by the

Watchdog), the MCU enters a normal reset procedure. If an interrupt is generated during WAIT mode, the MCU’s behaviour depends on the state of the processor core prior to the WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following paragraphs. The processor core does not generate a delay following the occurrence of the interrupt, because the oscillator clock is still available and no stabilisation period is necessary.

3.5.2 STOP Mode

If the Watchdog is disabled, STOP mode is available. When in STOP mode, the MCU is placed in the lowest power consumption mode. In this operating mode, the microcontroller can be considered as being “frozen”, no instruction is executed, the oscillator is stopped, the RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage, and the ST62xx core waits for the occurrence of an external interrupt request or a

Reset to exit the STOP state.

If the STOP state is exited due to a Reset (by activating the external pin) the MCU will enter a normal reset procedure. Behaviour in response to interrupts depends on the state of the processor core prior to issuing the STOP instruction, and also on the kind of interrupt request that is generated.

This case will be described in the following paragraphs. The processor core generates a delay after occurrence of the interrupt request, in order to wait for complete stabilisation of the oscillator, before executing the first instruction.

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POWER SAVING MODE (Cont’d)

3.5.3 Exit from WAIT and STOP Modes

The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an interrupt occurs (not a Reset). It should be noted that the restart sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt mode) prior to entering WAIT or STOP mode, as well as on the interrupt type.

Interrupts do not affect the oscillator selection.

3.5.3.1 Normal Mode

If the MCU was in the main routine when the WAIT or STOP instruction was executed, exit from Stop or Wait mode will occur as soon as an interrupt occurs; the related interrupt routine is executed and, on completion, the instruction which follows the

STOP or WAIT instruction is then executed, providing no other interrupts are pending.

3.5.3.2 Non Maskable Interrupt Mode

If the STOP or WAIT instruction has been executed during execution of the non-maskable interrupt routine, the MCU exits from the Stop or Wait mode as soon as an interrupt occurs: the instruction which follows the STOP or WAIT instruction is executed, and the MCU remains in non-maskable interrupt mode, even if another interrupt has been generated.

3.5.3.3 Normal Interrupt Mode

If the MCU was in interrupt mode before the STOP or WAIT instruction was executed, it exits from

STOP or WAIT mode as soon as an interrupt occurs. Nevertheless, two cases must be considered:

– If the interrupt is a normal one, the interrupt routine in which the WAIT or STOP mode was entered will be completed, starting with the execution of the instruction which follows the

STOP or the WAIT instruction, and the MCU is still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance with their priority.

– In the event of a non-maskable interrupt, the non-maskable interrupt service routine is processed first, then the routine in which the WAIT or

STOP mode was entered will be completed by executing the instruction following the STOP or

WAIT instruction. The MCU remains in normal interrupt mode.

Notes:

To achieve the lowest power consumption during

RUN or WAIT modes, the user program must take care of:

– configuring unused I/Os as inputs without pull-up

(these should be externally tied to well defined logic levels);

– placing all peripherals in their power down modes before entering STOP mode;

When the hardware activated Watchdog is selected, or when the software Watchdog is enabled, the

STOP instruction is disabled and a WAIT instruction will be executed in its place.

If all interrupt sources are disabled (GEN low), the

MCU can only be restarted by a Reset. Although setting GEN low does not mask the NMI as an interrupt, it will stop it generating a wake-up signal.

The WAIT and STOP instructions are not executed if an enabled interrupt request is pending.

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4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations:

– Input without pull-up or interrupt

– Input with pull-up and interrupt

– Input with pull-up, but without interrupt

– Analog input

– Push-pull output

– Open drain output

The lines are organised as bytewise Ports.

Each port is associated with 3 registers in Data space. Each bit of these registers is associated with a particular line (for instance, bits 0 of Port A

Data, Direction and Option registers are associated with the PA0 line of Port A).

The DATA registers (DRx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. The port data registers can be read to get the effective logic levels of the pins, but they can

Figure 23. I/O Port Block Diagram

RESET

CONTROLS be also written by user software, in conjunction with the related option registers, to select the different input mode options.

Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is done from I/O pins while writing will directly affect the Port data register causing an undesired change of the input configuration.

The Data Direction registers (DDRx) allow the data direction (input or output) of each pin to be set.

The Option registers (ORx) are used to select the different port options available both in input and in output mode.

All I/O registers can be read or written to just as any other RAM location in Data space, so no extra

RAM cells are needed for port data storage and manipulation. During MCU initialization, all I/O registers are cleared and the input mode with pull-ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts.

DATA

DIRECTION

INPUT/OUTPUT

DATA

SHIFT

OPTION

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OUT

TO INTERRUPT

TO ADC

VA00413

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I/O PORTS (Cont’d)

4.1.1 Operating Modes

Each pin may be individually programmed as input or output with various configurations.

This is achieved by writing the relevant bit in the

Data (DR), Data Direction (DDR) and Option registers (OR). Table 10 illustrates the various port configurations which can be selected by user software.

4.1.1.1 Input Options

Pull-up, High Impedance Option. All input lines can be individually programmed with or without an internal pull-up by programming the OR and DR registers accordingly. If the pull-up option is not selected, the input pin will be in the high-impedance state.

4.1.1.2 Interrupt Options

All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The interrupt trigger modes (falling edge, rising edge and low level) can be configured by software as described in the Interrupt Chapter for each port.

4.1.1.3 Analog Input Options

Some pins can be configured as analog inputs by programming the OR and DR registers accordingly. These analog inputs are connected to the onchip 8-bit Analog to Digital Converter. ONLY ONE pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively shorted.

Table 10. I/O Port Option Selection

DDR

Mode

Input

Output

Note: X = Don’t care

With pull-up, no interrupt

No pull-up, no interrupt

With pull-up and with interrupt

Option

Analog input (when available)

Open-drain output (20mA sink when available)

Push-pull output (20mA sink when available)

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I/O PORTS (Cont’d)

4.1.2 Safe I/O State Switching Sequence

Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recommended safe transitions are illustrated in Figure

24 . All other transitions are potentially risky and should be avoided when changing the I/O operating mode, as it is most likely that undesirable sideeffects will be experienced, such as spurious interrupt generation or two pins shorted together by the analog multiplexer.

Single bit instructions (SET, RES, INC and DEC) should be used with great caution on Ports Data registers, since these instructions make an implicit read and write back of the entire register. In port input mode, however, the data register reads from the input pins directly, and not from the data register latches. Since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. As a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. In the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data register:

SET bit, datacopy

LD a, datacopy

LD DRA, a

Warning:

The WAIT and STOP instructions allow the

ST62xx to be used in situations where low power consumption is needed. The lowest power consumption is achieved by configuring I/Os in input mode with well-defined logic levels.

The user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion.

Care must also be taken to not use instructions that act on a whole port register (INC,

DEC, or read operations) when all 8 bits are not available on the device. Unavailable bits must be masked by software (AND instruction).

Figure 24. Diagram showing Safe I/O State Transitions

010* 011

Input

Analog

Interrupt pull-up

Input pull-up (Reset state)

Output

Open Drain

000

100

001

101

Input

Output

Open Drain

Output

Push-pull

110

Note *. xxx = DDR, OR, DR Bits respectively

111

Output

Push-pull

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I/O PORTS (Cont’d)

Table 11I/O Port Option Selections

MODE AVAILABLE ON (1)

Input

PA0-PA3

PB0-PB3, PB6-PB7

PC2-PC4

Input with pull up

PA0-PA3

PB0-PB3, PB6-PB7

PC2-PC4

Input with pull up with interrupt

PA0-PA3

PB0-PB3, PB6-PB7

PC2-PC4

SCHEMATIC

Analog Input

PA0-PA3

PC2-PC4

Open drain output

5mA

PA0-PA3

PC2-PC4

Open drain output

30mA

PB0-PB3, PB6-PB7

PA0-PA3

PC2-PC4

Push-pull output

30mA

PB0-PB3, PB6-PB7

Note 1 . Provided the correct configuration has been selected.

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Data out

Data in

Interrupt

Data in

Interrupt

Data in

Interrupt

ST6253C ST6263C ST6263B ST6260C ST6260B

I/O PORTS (Cont’d)

4.1.3 AR Timer Alternate function Option

When bit PWMOE of register ARMC is low, pin AR-

TIMout/PB7 is configured as any standard pin of port B through the port registers. When PWMOE is high, ARTIMout/PB7 is the PWM output, independently of the port registers configuration.

ARTIMin/PB6 is connected to the AR Timer input.

It is configured through the port registers as any standard pin of port B. To use ARTIMin/PB6 as AR

Timer input, it must be configured as input through

DDRB.

4.1.4 SPI Alternate function Option

PC2/PC4 are used as standard I/O as long as bit

SPCLK of the SPI Mode Register is kept low.

When PC2/Sin is configured as input, it is automatically connected to the SPI shift register input, independent of the state at SPCLK.

PC3/SOUT is configured as SPI push-pull output by setting bit 0 of the Miscellaneous register (address DDh), regardless of the state of Port C registers. PC4/SCK is configured as push-pull output clock (master mode) by programming it as pushpull output through DDRC register and by setting bit SPCLK of the SPI Mode Register.

PC4/SCK is configured as input clock (slave mode) by programming it as input through DDRC register and by clearing bit SPCLK of the SPI Mode Register. With this configuration, PC4 can simultaneously be used as an input.

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I/O PORTS (Cont’d)

Figure 25Peripheral Interface Configuration of SPI, Timer 1 and AR Timer

PC3/Sout

PP/OD

MUX

DR b0

MISC.

OUT

PC2/Sin DR

SPI

PC4/SCK MUX

0 DR

CLOCK IN

CLOCK OUT

SPCLK

MOD REGISTER

TOUT

TIMER 1

OUT

PC1/TIM1

MUX

ARTIMin

ARTIMin DR

AR TIMER

ARTIMout

PP/OD

PWMOE

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MUX

1 ARTIMout

VR0C1661

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4.2 TIMER

The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit programmable prescaler, giving a maximum count of 2

Figure 26 shows the Timer Block Diagram. The content of the 8-bit counter can be read/written in the Timer/Counter register, TCR, which can be addressed in Data space as a RAM location at address 0D3h. The state of the 7-bit prescaler can be read in the PSC register at address 0D2h. The control logic device is managed in the TSCR register as described in the following paragraphs.

The 8-bit counter is decrement by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. When it decrements to zero then the TMZ (Timer Zero)bit in the TSCR is set. If the ETI (Enable Timer Interrupt) bit in the TSCR is also set, an interrupt request is generated. The Timer interrupt can be used to exit the MCU from WAIT mode.

The prescaler input is the internal frequency (f

INT

) divided by 12. The prescaler decrements on the rising edge. Depending on the division factor programmed by PS2, PS1 and PS0 bits in the TSCR

(see Figure 12 ), the clock input of the timer/counter register is multiplexed to different sources. For division factor 1, the clock input of the prescaler is also that of timer/counter; for factor 2, bit 0 of the prescaler register is connected to the clock input of

TCR. This bit changes its state at half the frequency of the prescaler input clock. For factor 4, bit 1 of the PSC is connected to the clock input of TCR, and so forth. The prescaler initialize bit, PSI, in the

TSCR register must be set to allow the prescaler

(and hence the counter) to start. If it is cleared, all the prescaler bits are set and the counter is inhibited from counting. The prescaler can be loaded with any value between 0 and 7Fh, if bit PSI is set.

The prescaler tap is selected by means of the

PS2/PS1/PS0 bits in the control register.

Figure 27 illustrates the Timer’s working principle.

Figure 26. Timer Block Diagram f

INT

PSC

SELECT

1 OF 7

DATA BUS

8-BIT

COUNTER

8 b7 b6 b5 b4 b3 b2 b1 b0

STATUS/CONTROL

TMZ ETI D5 D4 PSI PS2 PS1 PS0

INTERRUPT

LINE

VR02070A

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ST6253C ST6263C ST6263B ST6260C ST6260B

TIMER (Cont’d)

4.2.1 Timer Operation

The Timer prescaler is clocked by the prescaler clock input (f

INT

÷ 12).

The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the

TCR count reaches 0, it sets the TMZ bit in the

TSCR. The TMZ bit can be tested under program control to perform a timer function whenever it goes high.

4.2.2 Timer Interrupt

When the counter register decrements to zero with the ETI (Enable Timer Interrupt) bit set to one, an interrupt request associated with Interrupt Vector

#4 is generated. When the counter decrements to

Figure 27. Timer Working Principle zero, the TMZ bit in the TSCR register is set to one.

4.2.3 Application Notes

TMZ is set when the counter reaches zero; however, it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register.

The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded with 0FFh, while the 7-bit prescaler is loaded with 07Fh, and the TSCR register is cleared.

This means that the Timer is stopped (PSI=“0”) and the timer interrupt is disabled.

CLOCK BIT0 BIT1 BIT2

7-BIT PRESCALER

BIT3 BIT4 BIT5 BIT6

0 1 2 3 4

8-1 MULTIPLEXER

5 6 7 PS0

PS1

PS2

BIT0 BIT1 BIT2 BIT3 BIT4

8-BIT COUNTER

BIT5 BIT6 BIT7

VA00186

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ST6253C ST6263C ST6263B ST6260C ST6260B

TIMER (Cont’d)

A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the

PSC registers can be read accurately at any time.

4.2.4 Timer Registers

Timer Status Control Register (TSCR)

Address: 0D4h — Read/Write

TMZ ETI D5 D4 PSI PS2 PS1

PS0

Bit 7 = TMZ : Timer Zero bit

A low-to-high transition indicates that the timer count register has decrement to zero. This bit must be cleared by user software before starting a new count.

Bit 6 = ETI : Enable Timer Interrup

When set, enables the timer interrupt request

(vector #4). If ETI=0 the timer interrupt is disabled.

If ETI=1 and TMZ=1 an interrupt request is generated.

Bit 5 = D5 : Reserved

Must be set to “1”.

Bit 4 = D4

Do not care.

Bit 3 = PSI : Prescaler Initialize Bit

Used to initialize the prescaler and inhibit its counting. When PSI=“0” the prescaler is set to 7Fh and the counter is inhibited. When PSI=“1” the prescaler is enabled to count downwards. As long as

PSI=“0” both counter and prescaler are not running.

Bit 2, 1, 0 = PS2, PS1, PS0 : Prescaler Mux. Select.

These bits select the division ratio of the prescaler register.

Table 12. Prescaler Division Factors

PS2

PS1

PS0

Divided by

128

Timer Counter Register (TCR)

Address: 0D3h — Read/Write

D7 D6 D5 D4 D3

Bit 7-0 = D7-D0 : Counter Bits.

Prescaler Register PSC

Address: 0D2h — Read/Write

D7 D6 D5 D4 D3

Bit 7 = D7 : Always read as "0".

Bit 6-0 = D6-D0 : Prescaler Bits.

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4.3 AUTO-RELOAD TIMER

The Auto-Reload Timer (AR Timer) on-chip peripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a

7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f

INT

, f

INT/3

or an external clock source. A Mode Control Register,

ARMC, two Status Control Registers, ARSC0 and

ARSC1, an output pin, ARTIMout, and an input pin, ARTIMin, allow the Auto-Reload Timer to be used in 4 modes:

– Auto-reload (PWM generation), the prescaler and counter contents are frozen.

When TEN is set, the AR counter runs at the rate of the selected clock source. The counter is cleared on system reset.

The AR counter may also be initialized by writing to the ARLR load register, which also causes an immediate copy of the value to be placed in the AR counter, regardless of whether the counter is running or not. Initialization of the counter, by either method, will also clear the ARPSC register, whereupon counting will start from a known value.

4.3.2 Timer Operating Modes – Output compare and reload on external event

(PLL),

Four different operating modes are available for the AR Timer: – Input capture and output compare for time measurement.

– Input capture and output compare for period measurement.

Auto-reload Mode with PWM Generation.

This mode allows a Pulse Width Modulated signal to be generated on the ARTIMout pin with minimum

Core processing overhead.

The AR Timer can be used to wake the MCU from

WAIT mode either with an internal or with an external clock. It also can be used to wake the MCU from STOP mode, if used with an external clock signal connected to the ARTIMin pin. A Load register allows the program to read and write the counter on the fly.

4.3.1 AR Timer Description

The free running 8-bit counter is fed by the prescaler’s output, and is incremented on every rising edge of the clock signal.

When a counter overflow occurs, the counter is automatically reloaded with the contents of the Reload/Capture Register, ARCC, and ARTIMout is set. When the counter reaches the value contained in the compare register (ARCP), ARTIMout is reset.

The AR COUNTER is an 8-bit up-counter incremented on the input clock’s rising edge. The counter is loaded from the ReLoad/Capture Register,

ARRC, for auto-reload or capture operations, as well as for initialization. Direct access to the AR counter is not possible; however, by reading or writing the ARLR load register, it is possible to read or write the counter’s contents on the fly.

On overflow, the OVF flag of the ARSC0 register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OVIE, in the

Mode Control Register (ARMC), is set. The OVF flag must be reset by the user software.

The AR Timer’s input clock can be either the internal clock (from the Oscillator Divider), the internal clock divided by 3, or the clock signal connected to the ARTIMin pin. Selection between these clock sources is effected by suitably programming bits

CC0-CC1 of the ARSC1 register. The output of the

AR Multiplexer feeds the 7-bit programmable AR

When the counter reaches the compare value, the

CPF flag of the ARSC0 register is set and a compare interrupt request is generated, if the Compare

Interrupt enable bit, CPIE, in the Mode Control

Register (ARMC), is set. The interrupt service routine may then adjust the PWM period by loading a new value into ARCP. The CPF flag must be reset by user software.

Prescaler, ARPSC, which selects one of the 8

The PWM signal is generated on the ARTIMout available taps of the prescaler, as defined by

PSC0-PSC2 in the AR Mode Control Register.

Thus the division factor of the prescaler can be set Obsolete Product(s) - Obsolete Product(s)

The clock input to the AR counter is enabled by the pin (refer to the Block Diagram). The frequency of this signal is controlled by the prescaler setting and by the auto-reload value present in the Reload/Capture register, ARRC. The duty cycle of the PWM signal is controlled by the Compare Register, ARCP.

TEN (Timer Enable) bit in the ARMC register.

When TEN is reset, the AR counter is stopped and

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AUTO-RELOAD TIMER (Cont’d)

Figure 28. AR Timer Block Diagram f

INT f

INT

CC0-CC1

7-Bit

AR PRESCALER

PS0-PS2

DATA BUS

DDRB7

AR COMPARE

COMPARE

CPF

OVF

8-Bit

AR COUNTER LOAD

DRB7

OVF

OVIE

TCLD

PWMOE

PB7/

ARTIMout

EIE

CPF

CPIE

AR TIMER

INTERRUPT

8 8

PB6/

ARTIMin

SL0-SL1

AR AR

RELOAD/CAPTURE LOAD

SYNCHRO

Obsolete Product(s) - Obsolete Product(s)

8 8

DATA BUS

VR01660A

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AUTO-RELOAD TIMER (Cont’d)

It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTI-

Mout, the contents of the ARCP register must be greater than the contents of the ARRC register.

The maximum available resolution for the ARTI-

Mout duty cycle is:

Resolution = 1/[256-(ARRC)]

Where ARRC is the content of the Reload/Capture register. The compare value loaded in the Compare Register, ARCP, must be in the range from

(ARRC) to 255.

The ARTC counter is initialized by writing to the

ARRC register and by then setting the TCLD (Timer Load) and the TEN (Timer Clock Enable) bits in the Mode Control register, ARMC.

Enabling and selection of the clock source is controlled by the CC0, CC1, SL0 and SL1 bits in the

Status Control Register, ARSC1. The prescaler division ratio is selected by the PS0, PS1 and PS2 bits in the ARSC1 register.

In Auto-reload Mode, any of the three available clock sources can be selected: Internal Clock, Internal Clock divided by 3 or the clock signal present on the ARTIMin pin.

Figure 29. Auto-reload Timer PWM Function

COUNTER

255

COMPARE

VALUE

RELOAD

000

PWM OUTPUT t

HIGH t

LOW t

VR001852 t

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AUTO-RELOAD TIMER (Cont’d)

Capture Mode with PWM Generation . In this mode, the AR counter operates as a free running

8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge.

An 8-bit capture operation from the counter to the

ARRC register is performed on every active edge on the ARTIMin pin, when enabled by Edge Control bits SL0, SL1 in the ARSC1 register. At the same time, the External Flag, EF, in the ARSC0 register is set and an external interrupt request is generated if the External Interrupt Enable bit, EIE, in the ARMC register, is set. The EF flag must be reset by user software.

Each ARTC overflow sets ARTIMout, while a match between the counter and ARCP (Compare

Register) resets ARTIMout and sets the compare flag, CPF. A compare interrupt request is generated if the related compare interrupt enable bit,

CPIE, is set. A PWM signal is generated on ARTI-

Mout. The CPF flag must be reset by user software.

The frequency of the generated signal is determined by the prescaler setting. The duty cycle is determined by the ARCP register.

Initialization and reading of the counter are identical to the auto-reload mode (see previous description).

Enabling and selection of clock sources is controlled by the CC0 and CC1 bits in the AR Status Control Register, ARSC1.

The prescaler division ratio is selected by programming the PS0, PS1 and PS2 bits in the

ARSC1 Register.

In Capture mode, the allowed clock sources are the internal clock and the internal clock divided by

3; the external ARTIMin input pin should not be used as a clock source.

Capture Mode with Reset of counter and prescaler, and PWM Generation.

This mode is identical to the previous one, with the difference that a capture condition also resets the counter and the prescaler, thus allowing easy measurement of the time between two captures (for input period measchange the ARTimer counter value from FFH to any other value by writing this value in the ARRC register and setting the TLCD bit in the ARMC register.

Load on External Input . The counter operates as a free running 8-bit counter fed by the prescaler. the count is incremented on every clock rising edge.

Each counter overflow sets the ARTIMout pin. A match between the counter and ARCP (Compare

Register) resets the ARTIMout pin and sets the compare flag, CPF. A compare interrupt request is generated if the related compare interrupt enable bit, CPIE, is set. A PWM signal is generated on

ARTIMout. The CPF flag must be reset by user software.

Initialization of the counter is as described in the previous paragraph. In addition, if the external AR-

TIMin input is enabled, an active edge on the input pin will copy the contents of the ARRC register into the counter, whether the counter is running or not.

Notes :

The allowed AR Timer clock sources are the following:

AR Timer Mode

Auto-reload mode

Capture mode

Capture/Reset mode

External Load mode

Clock Sources f

INT

, f

INT/3

, ARTIMin f

INT

, f

INT/3 f

INT

, f

INT/3 f

INT

, f

INT/3

The clock frequency should not be modified while the counter is counting, since the counter may be set to an unpredictable value. For instance, the multiplexer setting should not be modified while the counter is counting.

Loading of the counter by any means (by auto-reload, through ARLR, ARRC or by the Core) resets the prescaler at the same time.

Care should be taken when both the Capture interrupt and the Overflow interrupt are used. Capture and overflow are asynchronous. If the capture occurs when the Overflow Interrupt Flag, OVF, is high (between counter overflow and the flag being reset by software, in the interrupt routine), the External Interrupt Flag, EF, may be cleared simultaneusly without the interrupt being taken into account.

The solution consists in resetting the OVF flag by writing 06h in the ARSC0 register. The value of EF is not affected by this operation. If an interrupt has occured, it will be processed when the MCU exits from the interrupt routine (the second interrupt is latched).

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AUTO-RELOAD TIMER (Cont’d)

4.3.3 AR Timer Registers

AR Mode Control Register (ARMC)

Address: D5h — Read/Write

Reset status: 00h

Bit 2 = OVIE : Overflow Interrupt . This bit, when set, enables the overflow interrupt request. If OVIE is reset, the compare interrupt request is masked.

If OVIE is set and the related flag, OVF in the

ARSC0 register is also set, an interrupt request is generated.

7 0

TCLD TEN PWMOE EIE CPIE OVIE ARMC1 ARMC0

Bit 1-0 = ARMC1-ARMC0 : Mode Control Bits 1-0 .

These are the operating mode control bits. The following bit combinations will select the various operating modes:

The AR Mode Control Register ARMC is used to program the different operating modes of the AR

Timer, to enable the clock and to initialize the counter. It can be read and written to by the Core and it is cleared on system reset (the AR Timer is disabled).

ARMC1

ARMC0

Operating Mode

Auto-reload Mode

Capture Mode

Capture Mode with Reset of ARTC and ARPSC

Note: Care should be taken when writing to the

ARMC register while AR Timer is running: if a

PWM signal is being output while the ARMC register is overwritten with its previous value, ARTIMout pin remains at its previous state for a programmed time equal to t

HIGH new count starts.

(refer to Figure 29 ). Then, a

1 1

Load on External Edge

Mode

AR Timer Status/Control Registers ARSC0 &

ARSC1.

These registers contain the AR Timer status information bits and also allow the programming of clock sources, active edge and prescaler multiplexer setting.

Bit 7 = TLCD : Timer Load Bit. This bit, when set, will cause the contents of ARRC register to be loaded into the counter and the contents of the prescaler register, ARPSC, are cleared in order to initialize the timer before starting to count. This bit is write-only and any attempt to read it will yield a logical zero.

ARSC0 register bits 0,1 and 2 contain the interrupt flags of the AR Timer. These bits are read normally. Each one may be reset by software. Writing a one does not affect the bit value.

AR Status Control Register 0 (ARSC0)

Bit 6 = TEN : Timer Clock Enable.

This bit, when set, allows the timer to count. When cleared, it will stop the timer and freeze ARPSC and ARTSC.

Address: D6h — Read/Clear

7 0

D7 D6 D5 D4 D3 EF CPF OVF

Bit 5 = PWMOE : PWM Output Enable. This bit, when set, enables the PWM output on the ARTI-

Mout pin. When reset, the PWM output is disabled.

Bits 7-3 = D7-D3 : Unused

Bit 4 = EIE : External Interrupt Enable. This bit, Bit 2 = EF : External Interrupt Flag. This bit is set by when set, enables the external interrupt request. any active edge on the external ARTIMin input pin.

When reset, the external interrupt request is

The flag is cleared by writing a zero to the EF bit.

masked. If EIE is set and the related flag, EF, in the ARSC0 register is also set, an interrupt request is generated.

Bit 3 = CPIE : Compare Interrupt Enable. This bit, Obsolete Product(s) - Obsolete Product(s) masked. If CPIE is set and the related flag, CPF, in ter are equal. The flag is cleared by writing a zero to the CPF bit.

Bit 0 = OVF : Overflow Interrupt Flag. This bit is set by a transition of the counter from FFh to 00h

(overflow). The flag is cleared by writing a zero to the ARSC0 register is also set, an interrupt reif the contents of the counter and the ARCP registhe OVF bit.

quest is generated.

Bit 1 = CPF : Compare Interrupt Flag. This bit is set

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AUTO-RELOAD TIMER (Cont’d)

AR Status Control Register 1(ARSC1)

Address: D7h — Read/Write

PS2 PS1 PS0 D4 SL1 SL0

CC1 CC0

Bist 7-5 = PS2-PS0 : Prescaler Division Selection

Bits 2-0. These bits determine the Prescaler division ratio. The prescaler itself is not affected by these bits. The prescaler division ratio is listed in the following table:

Table 13. Prescaler Division Ratio Selection

PS2

PS1

PS0

ARPSC Division Ratio

128

Bit 4 = D4 : Reserved . Must be kept reset.

Bit 3-2 = SL1-SL0 : Timer Input Edge Control Bits 1-

0. These bits control the edge function of the Timer input pin for external synchronization. If bit SL0 is reset, edge detection is disabled; if set edge detection is enabled. If bit SL1 is reset, the AR Timer input pin is rising edge sensitive; if set, it is falling edge sensitive.

SL1

SL0

Edge Detection

Disabled

Rising Edge

Falling Edge

Bit 1-0 = CC1-CC0 : Clock Source Select Bit 1-0.

These bits select the clock source for the AR Timer through the AR Multiplexer. The programming of the clock sources is explained in the following Table

14 :

AR Load Register ARLR . The ARLR load register is used to read or write the ARTC counter register

“on the fly” (while it is counting). The ARLR register is not affected by system reset.

AR Load Register (ARLR)

Address: DBh — Read/Write

7 0

D7 D6 D5 D4 D3 D2 D1 D0

Bit 7-0 = D7-D0 : Load Register Data Bits. These are the load register data bits.

AR Reload/Capture Register . The ARRC reload/ capture register is used to hold the auto-reload value which is automatically loaded into the counter when overflow occurs.

AR Reload/Capture (ARRC)

Address: D9h — Read/Write

D7 D6 D5 D4 D3 D2 D1

Bit 7-0 = D7-D0 : Reload/Capture Data Bits . These are the Reload/Capture register data bits.

AR Compare Register . The CP compare register is used to hold the compare value for the compare function.

AR Compare Register (ARCP)

Address: DAh — Read/Write

D7 D6 D5 D4 D3 D2 D1

Bit 7-0 = D7-D0 : Compare Data Bits . These are the Compare register data bits.

CC1

CC0

Clock Source

F int

Divided by 3

ARTIMin Input Clock

Reserved

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4.4 A/D CONVERTER (ADC)

The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device dependent), offering 8-bit resolution with a typical conversion time of 70us (at an oscillator clock frequency of 8MHz).

The ADC converts the input voltage by a process of successive approximations, using a clock frequency derived from the oscillator with a division factor of twelve. With an oscillator clock frequency less than 1.2MHz, conversion accuracy is decreased.

Selection of the input pin is done by configuring the related I/O line as an analog input via the Option and Data registers (refer to I/O ports description for additional information). Only one I/O line must be configured as an analog input at any time.

The user must avoid any situation in which more than one I/O pin is selected as an analog input simultaneously, to avoid device malfunction.

The ADC uses two registers in the data space: the

ADC data conversion register, ADR, which stores the conversion result, and the ADC control register, ADCR, used to program the ADC functions.

sion to allow stabilisation of the A/D converter.

This action is also needed before entering WAIT mode, since the A/D comparator is not automatically disabled in WAIT mode.

During Reset, any conversion in progress is stopped, the control register is reset to 40h and the

ADC interrupt is masked (EAI=0).

Figure 30. ADC Block Diagram

Ain

CONTROL REGISTER

CONVERTER

CORE

CONTROL SIGNALS

INTERRUPT

CLOCK

RESET

RESULT REGISTER

CORE

VA00418

A conversion is started by writing a “1” to the Start bit (STA) in the ADC control register. This automatically clears (resets to “0”) the End Of Conversion Bit (EOC). When a conversion is complete, the EOC bit is automatically set to “1”, in order to flag that conversion is complete and that the data in the ADC data conversion register is valid. Each conversion has to be separately initiated by writing to the STA bit.

4.4.1 Application Notes

The A/D converter does not feature a sample and hold circuit. The analog voltage to be measured should therefore be stable during the entire conversion cycle. Voltage variation should not exceed

±1/2 LSB for the optimum conversion accuracy. A low pass filter may be used at the analog input pins to reduce input voltage variation during conversion.

The STA bit is continuously scanned so that, if the user sets it to “1” while a previous conversion is in progress, a new conversion is started before completing the previous one. The start bit (STA) is a write only bit, any attempt to read it will show a logical “0”.

The A/D converter features a maskable interrupt associated with the end of conversion. This interrupt is associated with interrupt vector #4 and occurs when the EOC bit is set (i.e. when a conver-

When selected as an analog channel, the input pin is internally connected to a capacitor C ad

of typically 12pF. For maximum accuracy, this capacitor must be fully charged at the beginning of conversion. In the worst case, conversion starts one instruction (6.5 µs) after the channel has been selected. In worst case conditions, the impedance,

ASI, of the analog voltage source is calculated using the following formula: sion is completed). The interrupt is masked using Obsolete Product(s) - Obsolete Product(s)

The power consumption of the device can be reduced by turning off the ADC peripheral. This is

6.5µs = 9 x C ad

x ASI

(capacitor charged to over 99.9%), i.e. 30 k Ω including a 50% guardband. ASI can be higher if C ad has been charged for a longer period by adding indone by setting the PDS bit in the ADC control regstructions before the start of conversion (adding ister to “0”. If PDS=“1”, the A/D is powered and enmore than 26 CPU cycles is pointless).

abled for conversion. This bit must be set at least one instruction before the beginning of the conver-

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A/D CONVERTER (Cont’d)

Since the ADC is on the same chip as the microprocessor, the user should not switch heavily loaded output signals during conversion, if high precision is required. Such switching will affect the supply voltages used as analog references.

The accuracy of the conversion depends on the quality of the power supplies (V

and V

). The user must take special care to ensure a well regulated reference voltage is present on the V

and

pins (power supply voltage variations must be less than 5V/ms). This implies, in particular, that a suitable decoupling capacitor is used at the V

DD pin.

The converter resolution is given by:: the noise during the conversion. But the first conversion step is performed before the execution of the WAIT when most of clocks signals are still enabled . The key is to synchronize the ADC start with the effective execution of the WAIT. This is achieved by setting ADC SYNC option. This way,

ADC conversion starts in effective WAIT for maximum accuracy.

Note: With this extra option, it is mandatory to execute WAIT instruction just after ADC start instruction. Insertion of any extra instruction may cause spurious interrupt request at ADC interrupt vector.

A/D Converter Control Register (ADCR)

Address: 0D1h — Read/Write

7 0

EAI EOC STA PDS D3 D2 D1 D0

–

----------------------------

256

The Input voltage (Ain) which is to be converted must be constant for 1µs before conversion and remain constant during conversion.

Conversion resolution can be improved if the power supply voltage (V

DD lowered.

) to the microcontroller is

In order to optimise conversion resolution, the user can configure the microcontroller in WAIT mode, because this mode minimises noise disturbances and power supply variations due to output switching. Nevertheless, the WAIT instruction should be executed as soon as possible after the beginning of the conversion, because execution of the WAIT instruction may cause a small variation of the V

DD voltage. The negative effect of this variation is minimized at the beginning of the conversion when the converter is less sensitive, rather than at the end of conversion, when the less significant bits are determined.

Bit 7 = EAI : Enable A/D Interrupt.

If this bit is set to

“1” the A/D interrupt is enabled, when EAI=0 the interrupt is disabled.

Bit 6 = EOC : End of conversion.

Read Only . This read only bit indicates when a conversion has been completed. This bit is automatically reset to

“0” when the STA bit is written. If the user is using the interrupt option then this bit can be used as an interrupt pending bit. Data in the data conversion register are valid only when this bit is set to “1”.

Bit 5 = STA : Start of Conversion. Write Only . Writing a “1” to this bit will start a conversion on the selected channel and automatically reset to “0” the

EOC bit. If the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. This bit is write only, any attempt to read it will show a logical zero.

Bit 4 = PDS : Power Down Selection.

This bit activates the A/D converter if set to “1”. Writing a “0” to this bit will put the ADC in power down mode (idle mode).

The best configuration, from an accuracy standpoint, is WAIT mode with the Timer stopped. Indeed, only the ADC peripheral and the oscillator Bit 3-0 = D3-D0.

Not used are then still working. The MCU must be woken up from WAIT mode by the ADC interrupt at the end of the conversion. It should be noted that waking Obsolete Product(s) - Obsolete Product(s) the Timer interrupt, but in this case the Timer will be working and the resulting noise could affect

A/D Converter Data Register (ADR)

Address: 0D0h — Read only

7 0 conversion accuracy.

D7 D6 D5 D4 D3 D2 D1 D0

One extra feature is available in the ADC to get a better accuracy. In fact, each ADC conversion has to be followed by a WAIT instruction to minimize

Bit 7-0 = D7-D0 : 8 Bit A/D Conversion Result.

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4.5 SERIAL PERIPHERAL INTERFACE (SPI)

The SPI peripheral is an optimized synchronous serial interface with programmable transmission modes and master/slave capabilities supporting a wide range of industry standard SPI specifications.

The SPI interface may also implement asynchronous data transfer, in which case processor overhead is limited to data transfer from or to the shift register on an interrupt driven basis.

The SPI may be controlled by simple user software to perform serial data exchange with lowcost external memory, or with serially controlled peripherals to drive displays, motors or relays.

The SPI’s shift register is simultaneously fed by the Sin pin and feeds the Sout pin, thus transmission and reception are essentially the same process. Suitable setting of the number of bits in the data frame can allow filtering of unwanted leading data bits in the incoming data stream.

The SPI comprises an 8-bit Data/Shift Register,

DSR, a Divide register, DIV, a Mode Control Register MOD, and a Miscellaneous register, MISCR.

The SPI may be operated either in Master mode or in Slave mode.

Master mode is defined by the synchronous serial clock being supplied by the MCU, by suitably programming the clock divider (DIV register). Slave

Figure 31. SPI Block Diagram

CPU

CYCLE

CLOCK

SPI

DIVIDER mode is defined by the serial clock being supplied externally on the SCK pin by the external Master device.

For maximum versatility the SPI may be programmed to sample data either on the rising or on the falling edge of SCK, with or without phase shift

(clock Polarity and Phase selection).

The Sin, Sout and SCK signals are connected as alternate I/O pin functions.

For serial input operation, Sin must be configured as an input. For serial output operation, Sout is selected as an output by programming Bit 0 of the

Miscellaneous Register: clearing this bit will set the pin as a standard I/O line, while setting the bit will select the Sout function.

An interrupt request may be associated with the end of a transmission or reception cycle; this is defined by programming the number of bits in the data frame and by enabling the interrupt. This request is associated with interrupt vector #2, and can be masked by programming the SPIE bit of the MOD register. Since the SPI interrupt is

“ORed” with the port interrupt source, an interrupt flag bit is available in the DIV register allowing discrimination of the interrupt request.

SCK FILTER

CLOCK

DATA BUS

SHIFT

VR001693

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

4.5.1 SPI Registers

SPI Mode Control Register (MOD)

Address: E2h — Read/Write

Reset status: 00h

7 0

SPRUN SPIE CPHA SPCLK SPIN SPSTRT EFILT CPOL pin is configured as input, the slave mode is selected. If SPCLK is high, the SCK pin is automaticcally configured as push pull output and the master mode is selected. In this case, the phase and polarity of the clock are controlled by CPOL and

CPHA.

Note : When the master mode is enabled, it is mandatory to configure PC4 in input mode through the i/o port registers.

Bit 3 = SPIN : Input Selection

The MOD register defines and controls the transmission modes and characteristics.

This register is read/write and all bits are cleared at reset. Setting SPSTRT = 1 and SPIN = 1 is not allowed and must be avoided.

Bit 7 = SPRUN : SPI Run . This bit is the SPI activity flag. This can be used in either transmit or receive modes; it is automatically cleared by the SPI at the end of a transmission or reception and generates an interrupt request (providing that the SPIE Interrupt Enable bit is set). The Core can stop transmission or reception at any time by resetting the

SPRUN bit; this will also generate an interrupt request (providing that the SPIE Interrupt enable bit is set). The SPRUN bit can be used as a start condition parameter, in conjunction with the SPSTRT bit, when an external signal is present on the Sin pin. Note that a rising edge is then necessary to initiate reception; this may require external data inversion. This bit can be used to poll the end of reception or transmission.

This bit enables the transfer of the data input to the

Shift Register in receive mode. If this bit is cleared the Shift Register input is 0. If this bit is set, the

Shift Register input corresponds to the input signal present on the Sin pin.

Bit 2 = SPSTRT : Start Selection

This bit selects the transmission or reception start mode. If SPSTRT is cleared, the internal start condition occurs as soon as the SPRUN bit is set. If

SPSTRT is set, the internal start signal is the logic

“AND” between the SPRUN bit and the external signal present on the Sin pin; in this case transmission will start after the latest of both signals providing that the first signal is still present (note that this implies a rising edge). After the transmission or recetion has been started, it will continue even if the

Sin signal is reset.

Bit 1 = EFILT : Enable Filters

Bit 6 = SPIE : SPI Interrupt Enable . This bit is the

SPI Interrupt Enable bit. If this bit is set the SPI interrupt (vector #2) is enabled, when SPIE is reset, the interrupt is disabled.

Bit 5 = CPHA : Clock Phase Selection . This bit selects the clock phase of the clock signal. If this bit is cleared to zero the normal state is selected; in this case Bit 7 of the data frame is present on Sout

This bit enables/disables the input noise filters on the Sin and SCK inputs. If it is cleared to zero the filters are enabled, if set to one the filters are disabled. These noise filters will eliminate any pulse on

Sin and SCK with a pulse width smaller than one to two Core clock periods (depending on the occurrence of the signal edge with respect to the

Core clock edge). For example, if the ST6260B/

65B runs with an 8MHz crystal, Sin and SCK will be delayed by 125 to 250ns.

pin as soon as the SPI Shift Register is loaded. If

Bit 0 = CPOL : Clock Polarity this bit is set to one the shifted state' is selected; in

This bit controls the relationship between the data this case Bit 7 of data frame is present on Sout pin ther the core cycle clock (f

INT

/13) (Master mode) or the signal provided at SCK pin by an external on the Sin and Sout pins and SCK. The CPOL bit on the first falling edge of Shift Register clock. The polarity relation and the division ratio between

Shift Register and SPI base clock are also pro Obsolete Product(s) - Obsolete Product(s)

Bit 4= SPCLK : Base Clock Selection lows it to change state. It has the greatest impact on the first bit transmitted (the MSB) as it does (or does not) allow a clock transition before the first data capture edge.

Refer to the timing diagrams at the end of this sec-

This bit selects the SPI base clock source. It is eiselects the clock edge which captures data and altion for additional details. These show the relationship between CPOL, CPHA and SCK, and indicate the active clock edges and strobe times.

device (slave mode). If SPCLK is low and the SCK

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ST6253C ST6263C ST6263B ST6260C ST6260B

SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

SPI DIV Register (DIV)

Address: E1h — Read/Write

Reset status: 00h

SPINT DOV6 DIV5 DIV4 DIV3 CD2 CD1

CD0

The SPIDIV register defines the transmission rate and frame format and contains the interrupt flag.

Bits CD0-CD2, DIV3-DIV6 are read/write while

SPINT can be read and cleared only. Write access is not allowed if SPRUN in the MOD register is set.

Bit 7 = SPINT : Interrupt Flag. If SPIE bit=1, SPINT is automatically set to one by the SPI at the end of a transmission or reception and an interrupt request can be generated depending on the state of the interrupt mask bit in the MOD control register.

This bit is write and read and must be cleared by user software at the end of the interrupt service routine.

DIV6-DIV3

0 0

Number of bits sent

Reserved (not to be used)

⎟

⎞

⎟ Refer to the

⎟ description of the

⎟ DIV6-DIV3 bits in

⎟ the DIV Register

⎠

Bit 6-3 = DIV6-DIV3 : Burst Mode Bit Clock Period

Selection. Define the number of shift register bits that are transmitted or received in a frame. The available selections are listed in Table 16 . The normal maximum setting is 8 bits, since the shift register is 8 bits wide. Note that by setting a greater number of bits, in conjunction with the SPIN bit in the MOD register, unwanted data bits may be filtered from the data stream.

Bit 2-0 = CD2-CD0 : Base/Bit Clock Rate Selection . Define the division ratio between the core clock (f

INT

divided by 13) and the clock supplied to the Shift Register in Master mode.

Table 15. Base/Bit Clock Ratio Selection

CD2-CD0

0 0

1 1

Divide Ratio (decimal)

Divide by 1

Divide by 2

Divide by 4

Divide by 8

SPI Data/Shift Register (SPIDSR)

Address: E0h — Read/Write

Reset status: XXh

D7 D6 D5 D4 D3 D2 D1

SPIDSR is read/write, however write access is not allowed if the SPRUN bit of Mode Control register is set to one.

Data is sampled into SPDSR on the SCK edge determined by the CPOL and CPHA bits. The affect of these setting is shown in the following diagrams.

The Shift Register transmits and receives the Most

Significant Bit first.

Bit 7-0 = DSR7-DSR0 : Data Bits. These are the

SPI shift register data bits.

Miscellaneous Register (MISCR)

1 0 0 Divide by 16 Address: DDh — Write only

Reset status: xxxxxxxb

Obsolete Product(s) - Obsolete Product(s)

Divide by 32

Divide by 64

Divide by 256

Note : For example, when an 8MHz CPU clock is used, asynchronous operation at 9600 Baud is possible (8MHz/13/64). Other Baud rates are available by proportionally selecting division factors depending on CPU clock frequency.

Bit 7-1 = D7-D1 : Reserved.

Bit 0 = D0 : Bit 0. This bit, when set, selects the

Sout pin as the SPI output line. When this bit is

Data setup time on Sin is typically 250ns min, while data hold time is typically 50ns min.

cleared, Sout acts as a standard I/O line.

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ST6253C ST6263C ST6263B ST6260C ST6260B

SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

4.6 SPI Timing Diagrams

Figure 32. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal

SPRUN

SCK

Sin

Sampling

Sout b7 b6 b5 b4 b3 b2 b1 b0

VR001694

Figure 33. CPOL = 1 Clock Polarity Inverted, CPHA = 0 Phase Selection Normal

SPRUN

SCK

Sin

Sampling

Sout b7 b6 b5 b4 b3 b2 b1 b0

VR0A1694

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

Figure 34. CPOL = 0 Clock Polarity Normal, CPHA = 1 Phase Selection Shifted

SPRUN

SCK

Sin

Sampling

Sout b7 b6 b5 b4 b3 b2

Figure 35. CPOL = 1 Clock Polarity Inverted, CPHA = 1 Phase Selection Shifted b1 b0

VR0B1694

SPRUN

SCK

Sin

Sampling

Sout b7 b6 b5 b4 b3 b2 b1 b0

VR0C1694

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

5 SOFTWARE

5.1 ST6 ARCHITECTURE

The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability.

The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction. Furthermore, the program may branch to a selected address depending on the status of any bit of the Data space. The carry bit is stored with the value of the bit when the SET or RES instruction is processed.

5.2 ADDRESSING MODES

The ST6 core offers nine addressing modes, which are described in the following paragraphs.

Three different address spaces are available: Program space, Data space, and Stack space. Program space contains the instructions which are to be executed, plus the data for immediate mode instructions. Data space contains the Accumulator, the X,Y,V and W registers, peripheral and Input/

Output registers, the RAM locations and Data

ROM locations (for storage of tables and constants). Stack space contains six 12-bit RAM cells used to stack the return addresses for subroutines and interrupts.

bits of the opcode with the byte following the opcode. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space.

An extended addressing mode instruction is twobyte long.

Program Counter Relative . The relative addressing mode is only used in conditional branch instructions. The instruction is used to perform a test and, if the condition is true, a branch with a span of

-15 to +16 locations around the address of the relative instruction. If the condition is not true, the instruction which follows the relative instruction is executed. The relative addressing mode instruction is one-byte long. The opcode is obtained in adding the three most significant bits which characterize the kind of the test, one bit which determines whether the branch is a forward (when it is

0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to Fh) which must be added or subtracted to the address of the relative instruction to obtain the address of the branch.

Immediate . In the immediate addressing mode, the operand of the instruction follows the opcode location. As the operand is a ROM byte, the immediate addressing mode is used to access constants which do not change during program execution (e.g., a constant used to initialize a loop counter).

Direct . In the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. Direct addressing allows the user to directly address the 256 bytes in Data Space memory with a single two-byte instruction.

Bit Direct . In the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the address of the byte in which the specified bit must be set or cleared. Thus, any bit in the 256 locations of

Data space memory can be set or cleared.

Bit Test & Branch . The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit test and branch instruction is three-byte long. The bit identification and the tested condition are included in the opcode byte. The address of the byte to be tested follows immediately the opcode in the Program space. The third byte is the jump displacement, which is in the range of -127 to +128. This displacement can be determined using a label, which is converted by the assembler.

Short Direct . The core can address the four RAM registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. In this case, the instruction is only one byte and the selection of the Obsolete Product(s) - Obsolete Product(s) code. Short direct addressing is a subset of the direct addressing mode. (Note that 80h and 81h are processed by the register-indirect instruction is at the address pointed by the content of one of the indirect registers, X or Y (80h,81h). The indirect register is selected by the bit 4 of the opcode. A register indirect instruction is one byte long.

also indirect registers).

Indirect . In the indirect addressing mode, the byte

Extended . In the extended addressing mode, the

12-bit address needed to define the instruction is obtained by concatenating the four less significant

Inherent . In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. These instructions are one byte long.

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ST6253C ST6263C ST6263B ST6260C ST6260B

5.3 INSTRUCTION SET

The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following paragraphs describe the different types.

All the instructions belonging to a given type are presented in individual tables.

Table 17. Load & Store Instructions

Load & Store . These instructions use one, two or three bytes in relation with the addressing mode.

One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one of the addressing modes.

For Load Immediate one operand can be any of the 256 data space bytes while the other is always immediate data.

Instruction

LD A, X

LD A, Y

LD A, V

LD A, W

LD X, A

LD Y, A

LD V, A

LD W, A

LD A, rr

LD rr, A

LD A, (X)

LD A, (Y)

LD (X), A

LD (Y), A

LDI A, #N

LDI rr, #N

Addressing Mode

Short Direct

Direct

Indirect

Immediate

Notes:

X,Y. Indirect Register Pointers, V & W Short Direct Registers

# .

Immediate data (stored in ROM memory) rr.

Data space register

Affected

* .

Not Affected

Bytes

Cycles

Flags

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

INSTRUCTION SET (Cont’d)

Arithmetic and Logic . These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulator while the other can be either a data space memory content or an immediate value in relation with the addressing mode. In CLR, DEC, INC instructions the operand can be any of the 256 data space addresses. In COM, RLC, SLA the operand is always the accumulator.

Table 18. Arithmetic & Logic Instructions

ADD A, (Y)

ADD A, rr

ADDI A, #N

AND A, (X)

AND A, (Y)

AND A, rr

ANDI A, #N

CLR A

Indirect

Direct

Immediate

Indirect

Direct

Immediate

Short Direct

Flags

Instruction

ADD A, (X)

Addressing Mode

Indirect

Bytes

Cycles

* CLR r Direct 3 4

COM A

CP A, (X)

CP A, (Y)

CP A, rr

CPI A, #N

DEC X

DEC Y

DEC V

DEC W

DEC A

DEC rr

DEC (X)

DEC (Y)

INC X

INC Y

INC V

INC W

INC A

INC rr

INC (X)

Inherent

Indirect

Direct

Immediate

Short Direct

Direct

Indirect

Short Direct

Direct

Indirect

INC (Y)

RLC A

SLA A

Indirect

Inherent

SUB A, (X) Indirect 1 4 Δ Δ

SUB A, (Y)

SUB A, rr

Indirect

Direct

Δ SUBI A, #N Immediate 2 4

Notes:

X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected

# . Immediate data (stored in ROM memory)* . Not Affected rr. Data space register

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ST6253C ST6263C ST6263B ST6260C ST6260B

INSTRUCTION SET (Cont’d)

Conditional Branch . The branch instructions achieve a branch in the program when the selected condition is met.

Bit Manipulation Instructions . These instructions can handle any bit in data space memory.

One group either sets or clears. The other group

(see Conditional Branch) performs the bit test branch operations.

Table 19. Conditional Branch Instructions

Control Instructions . The control instructions control the MCU operations during program execution.

Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space.

Flags

Instruction Branch If Bytes

JRC e

JRNC e

JRZ e

JRNZ e

JRR b, rr, ee

JRS b, rr, ee

C = 1

C = 0

Z = 1

Z = 0

Bit = 0

Bit = 1

Notes

: b.

3-bit address e.

5 bit signed displacement in the range -15 to +16<F128M> ee.

8 bit signed displacement in the range -126 to +129

Table 20. Bit Manipulation Instructions

Cycles

5 rr. Data space register

Δ . Affected. The tested bit is shifted into carry.

* . Not Affected

Flags

Instruction Addressing Mode

SET b,rr

RES b,rr

Notes: b.

3-bit address; rr.

Data space register;

Bit Direct

Bytes

Cycles

* . Not<M> Affected

Table 21. Control Instructions

Flags

Instruction Addressing Mode Bytes Cycles

NOP

RET

RETI

STOP (1)

WAIT

Notes:

This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.

Δ .

Affected

Not Affected

Obsolete Product(s) - Obsolete Product(s)

Instruction

Addressing Mode Bytes Cycles

Flags

Z C

CALL abc

JP abc

Extended

Notes: abc. 12-bit address;

* .

Not Affected

Inherent

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ST6253C ST6263C ST6263B ST6260C ST6260B

Opcode Map Summary.

The following table contains an opcode map for the instructions used by the ST6

LOW LOW

0000

0001

0010

0011

0100

0101

0110

0111

HI HI

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

RNZ pcr 2

4 e e pcr 2

JRNZ 4 e pcr 2

JRNZ 4 pcr 2 e pcr 2

JRNZ 4 e pcr 2

JRNZ 4 e

JRNZ 4 e pcr 2

JRNZ 4 ext 1

CALL 2 abc ext 1

CALL 2 abc e

JRNC 5 JRR 2 b0,rr,ee e pcr 3

JRNC 5 bt 1

JRS 2 b0,rr,ee e pcr 3

JRNC 5 b4,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 pcr 3 bt 1

JRS 2 b4,rr,ee e bt 1 e

JRNC 5 JRR 2 b2,rr,ee e pcr 3

JRNC 5 bt 1

JRS 2 b2,rr,ee e pcr 3

JRNC 5 b6,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 b6,rr,ee bt 1

JRS 2 e pcr 3

JRNC 5 b1,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 b1,rr,ee bt 1

JRS 2 e pcr 3

JRNC 5 b5,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 b5,rr,ee bt 1

JRS 2 e pcr 3

JRNC 5 b3,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 b3,rr,ee bt 1

JRS 2 e pcr 3

JRNC 5 b7,rr,ee bt 1

JRR 2 pcr 3 bt 1 e e e e e e e e e e e e e e

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

# x

# a,x

# y

# a,y

# v

# a,v

# w

INC 2 sd 1

LD 2 sd 1

INC 2 sd 1

LD 2 sd 1

INC 2 sd 1

LD 2 sd 1

INC 2 sd 1

1 e e e e e e e e e e e e e e e

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC prc

JRC 4 prc 1

JRC prc

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

AND a,(x) ind

ANDI a,nn imm a,(x)

SUB ind

SUBI a,nn imm

(x)

DEC ind

LD a,(x) ind

LDI a,nn imm

CP a,(x) ind

CPI a,nn imm

ADD a,(x) ind

ADDI a,nn imm

INC

(x) ind

(x),a

LD ind

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

2 JRNZ 4 CALL 2 JRNC 5

Abbreviations for Addressing Modes: Legend:

JRS 2 JRZ 4 LD 2 JRC

1111

1 e pcr 2 abc ext 1 e pcr 3 b7,rr,ee bt 1 e pcr 1 a,w sd 1 e prc

1111 Obsolete Product(s) - Obsolete Product(s) dir Direct # Indicates Illegal Instructions

Cycle

Mnemonic sd Short Direct e 5 Bit Displacement 2 JRC

Operand imm Immediate b 3 Bit Address e inh Inherent rr 1byte dataspace address

Bytes

1 prc ext Extended nn 1 byte immediate data b.d Bit Direct abc 12 bit address

Addressing Mode bt Bit Test pcr Program Counter Relative ind Indirect ee 8 bit Displacement

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ST6253C ST6263C ST6263B ST6260C ST6260B

Opcode Map Summary (Continued)

LOW

1000

1001

1010

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

RNZ pcr 2

4 e e pcr 2

JRNZ 4 e pcr 2

JRNZ 4 pcr 2 e pcr 2

JRNZ 4 e pcr 2

JRNZ 4 e

JRNZ 4 e pcr 2

JRNZ 4 abc abc abc abc abc abc abc abc abc abc abc abc abc abc abc

JP 2 ext 1

JP 2 ext 1 e pcr 2

JRNC 4 e pcr 2

JRNC 4 pcr 2 e pcr 2

JRNC 4 e pcr 2

JRNC 4 e

JRNC 4 e pcr 2

JRNC 4

1011 b5,rr b.d 1

RES 2 b5,rr b.d 1

SET 2 b3,rr b.d 1

RES 2 b3,rr b.d 1

SET 2 b7,rr b.d 1

RES 2 b.d 1 b0,rr

RES 2 b0,rr b.d 1

SET 2 b4,rr b.d 1

RES 2 b4,rr b.d 1

SET 2 e b.d 1 b2,rr

RES 2 b2,rr b.d 1

SET 2 b6,rr b.d 1

RES 2 b6,rr b.d 1

SET 2 b1,rr b.d 1

RES 2 b1,rr b.d 1

SET 2

1100 e e e e e e e e e e e e e e

JRZ 4 pcr 3

JRZ 4 pcr 1

JRZ 4 pcr

JRZ 4 pcr 1

JRZ 2 pcr 1

JRZ 4 pcr 1

JRZ 2 pcr 1

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ 2 pcr 1

JRZ 4 pcr 1

JRZ 2

1101

LDI 2 rr,nn imm 1

DEC 2 x sd 1

COM 2 a

LD 2 x,a sd 1

RETI 2 inh 1

DEC 2 y sd 1

STOP 2 y,a

# v a v,a w inh 1

LD 2 sd 1

DEC 2 sd 1

RCL 2 inh 1

LD 2 sd 1

RET 2 inh 1

DEC 2 sd 1

WAIT 2

1110 e e e e e e e e e e e e e e e

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4

1111

LD a,(y) ind

LD a,rr dir

CP a,(y) ind

CP a,rr dir

ADD a,(y) a,rr ind

ADD dir

INC

(y) ind

INC rr dir

(y),a ind

LD rr,a dir

AND a,(y) a,rr ind

AND a,(y) dir

SUB ind

SUB a,rr

(y) dir

DEC ind

LOW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

HI pcr 1 inh 1 prc 1

2 JRNZ 4 JP 2 JRNC 4

Abbreviations for Addressing Modes: Legend:

SET 2 JRZ 4 LD 2 JRC 4 DEC

1111

1 e pcr 2 abc ext 1 e pcr 2 b7,rr b.d 1 e pcr 1 w,a sd 1 e prc 2 rr dir

1111 Obsolete Product(s) - Obsolete Product(s) dir Direct # Indicates Illegal Instructions

Cycle

Mnemonic sd Short Direct e 5 Bit Displacement 2 JRC

Operand imm Immediate b 3 Bit Address e inh Inherent rr 1byte dataspace address

Bytes

1 prc ext Extended nn 1 byte immediate data b.d Bit Direct abc 12 bit address

Addressing Mode bt Bit Test pcr Program Counter Relative ind Indirect ee 8 bit Displacement

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ST6253C ST6263C ST6263B ST6260C ST6260B

6 ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices to protect the inputs against damage due to high static voltages, however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages.

For proper operation it is recommended that V

I and V

be higher than V

and lower than V

Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (V

DD or V

Power Considerations .The average chip-junction temperature, Tj, in Celsius can be obtained from:

Tj=TA + PD x RthJA

Where:TA = Ambient Temperature.

RthJA =Package thermal resistance (junction-to ambient).

PD = Pint + Pport.

Pint =IDD x VDD (chip internal power).

Pport =Port power dissipation (determined by the user).

Symbol

STG

Supply Voltage

Input Voltage

Output Voltage

Parameter

Total Current into V

(source)

Total Current out of V

(sink)

Junction Temperature

Storage Temperature

Value

-0.3 to 7.0

- 0.3 to V

+ 0.3

(1)

- 0.3 to V

+ 0.3

(1)

100

150

-60 to 150

Unit

V mA mA

°C

Notes:

- Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection current is kept within the specification.

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

6.2 RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Test Conditions

Value

Typ.

4.0

8.0

4.0

8.0

4.0

-5

Max.

125

6.0

Unit f

OSC

INJ+

INJ-

Operating Temperature

Operating Supply Voltage

(ST626xB ROM devices)

Oscillator Frequency

(ST626xB ROM devices)

(Except ST626xB ROM devices)

Pin Injection Current (positive)

6 Suffix Version

1 Suffix Version

3 Suffix Version f

OSC

= f

OSC

4MHz, 1 & 6 Suffix

4MHz, 3 Suffix fosc= 8MHz , 1 & 6 Suffix fosc= 8MHz , 3 Suffix f

OSC

= f

OSC

4MHz, 1 & 6 Suffix

4MHz, 3 Suffix fosc= 8MHz , 1 & 6 Suffix fosc= 8MHz , 3 Suffix

= 3.0V, 1 & 6 Suffix

= 3.0V , 3 Suffix

= 3.6V , 1 & 6 Suffix

= 3.6V , 3 Suffix

= 3.0V, 1 & 6 Suffix

= 3.0V , 3 Suffix

= 4.0V , 1 & 6 Suffix

= 4.0V , 3 Suffix

= 4.5 to 5.5V

Pin Injection Current (negative) V

= 4.5 to 5.5V

Min.

-40

3.0

3.6

4.5

3.0

4.0

4.5

°C

MHz

Notes :

1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the

A/D conversion. For a -1mA injection, a maximum 10 K Ω is recommended.

2.An oscillator frequency above 1MHz is recommended for reliable A/D results

Figure 36. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (V

)

Maximum FREQUENCY (MHz)

1 & 6 Suffix version

FUNCTIONALITY IS NOT

GUARANTEED IN

1 & 6 Suffix version

THIS AREA

3 Suffix version

2 Obsolete Product(s) - Obsolete Product(s)

2.5

3 3.6

4 4.5

5 5.5

SUPPLY VOLTAGE (V

)

All devices except ST626xB ROM devices

ST626xB ROM devices

The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.

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ST6253C ST6263C ST6263B ST6260C ST6260B

6.3 DC ELECTRICAL CHARACTERISTICS

= -40 to +125°C unless otherwise specified)

Symbol Parameter Test Conditions

Min.

Input Low Level Voltage

All Input pins

Input High Level Voltage

All Input pins

Hysteresis Voltage

(1)

All Input pins

Hys

= 5V

= 3V

I up dn

LVD Threshold in power-on

LVD threshold in powerdown

Low Level Output Voltage

All Output pins

Low Level Output Voltage

30 mA Sink I/O pins

High Level Output Voltage

All Output pins

Pull-up Resistance

Input Leakage Current

RESET pin

Supply Current in RESET

Mode

Supply Current in

RUN Mode

(2)

All Input pins but RESET

Supply Current in WAIT

Mode

(3)

Supply Current in STOP

Mode, with LVD disabled

(3)

Supply Current in STOP

Mode, with LVD enabled

(3)

Retention EPROM Data Retention

= 5.0V; I

= +10µA

= + 3mA

= +10µA

= +7mA

= +15mA

= 5.0V; I

= -10µA

= -3.0mA

All Input pins

RESET pin

= V

(No Pull-Up configured)

= V

DD f

RESET

OSC

=8MHz

=5.0V f

LOAD

=0mA

=5.0V

LOAD

=0mA

=5.0V

= 55°C

INT

=8MHz

x 0.7

0.2

3.5

4.9

3.5

150

-8

Value

Typ.

4.1

3.8

100

350

0.1

-16

Max.

x 0.3

4.3

0.1

0.8

0.1

0.8

1.3

350

900

1.0

-30

2.5

500

Unit

ΚΩ

A mA mA mA

μ A years

Notes:

(1) Hysteresis voltage between switching levels

(2) All peripherals running

(3) All peripherals in stand-by

Obsolete Product(s) - Obsolete Product(s)

66/83

ST6253C ST6263C ST6263B ST6260C ST6260B

DC ELECTRICAL CHARACTERISTICS (Cont’d)

= -40 to +85°C unless otherwise specified))

Symbol

V up

V dn

Parameter Test Conditions

LVD Threshold in power-on

LVD threshold in powerdown

Low Level Output Voltage

All Output pins

Low Level Output Voltage

30 mA Sink I/O pins

High Level Output Voltage

All Output pins

Supply Current in STOP

Mode, with LVD disabled

(*)

= 5.0V; I

= +10µA

= + 5mA

= + 10mAv

= +10µA

= +10mA

= +20mA

= +30mA

= 5.0V; I

LOAD

=0mA

=5.0V

= -10µA

= -5.0mA

Value

Min.

V dn

+50 mV 4.1

3.6

Typ.

3.8

V up

Max.

4.3

-50 mV

0.1

0.8

1.2

0.1

0.8

1.3

2.0

4.9

3.5

Unit

Note:

(*) All Peripherals in stand-by.

6.4 AC ELECTRICAL CHARACTERISTICS

= -40 to +125°C unless otherwise specified)

Symbol t

REC

Parameter

Supply Recovery Time

(1)

Test Conditions

Min.

100

Value

Typ.

WEE

EEPROM Write Time

= 25°C

= 85°C

= 125°C

Acceptance (25°C)

Endurance

(2)

EEPROM WRITE/ERASE Cycle 300,000 1 million

Retention EEPROM Data Retention f

LFAO

Internal frequency with LFAO active

= 55°C f

OSG f

OUT

Internal Frequency with OSG enabled

Internal frequency with RC oscillator and OSG disabled

Input Capacitance

Output Capacitance

2) 3)

= 3V

= 3.6V

= 4.5V

= 6V

VDD=5.0V (Except 626xB ROM)

R=47k Ω

R=100k

R=470k Ω

VDD=5.0V (626xB ROM)

R=10k

R=27k Ω

R=67k

R=100k Ω

All Inputs Pins

All Outputs Pins

Notes:

1. Period for which V

has to be connected at 0V to allow internal Reset function at next power-up.

2 An oscillator frequency above 1MHz is recommended for reliable A/D results.

3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.

200

2.7

800

2.8

2.2

400

3.2

850

8.2

5.9

3.6

2.8

Max.

800 f

OSC

5.8

3.5

900

9.8

4.3

3.4

Unit ms ms cycles years kHz

MHz

MHz kHz

MHz

MHz pF pF

67/83

ST6253C ST6263C ST6263B ST6260C ST6260B

6.5 A/D CONVERTER CHARACTERISTICS

= -40 to +125°C unless otherwise specified)

Symbol

Res

TOT t

ZIR

FSR

Parameter Test Conditions

Resolution

Total Accuracy

(1)

Conversion Time

(2)

Zero Input Reading

Full Scale Reading f f f

OSC f

OSC

> 1.2MHz

> 32kHz

= 8MHz (T

= 4 MHz

< 85°C)

Conversion result when

= V

Analog Input Current During

Conversion

= 4.5V

Analog Input Capacitance

Min.

Notes :

Noise at VDD, VSS <10mV

With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.

Value

Typ.

140

Max.

1.0

Unit

Bit

LSB

μ s

Hex

μ A pF

6.6 TIMER CHARACTERISTICS

= -40 to +125°C unless otherwise specified)

Symbol Parameter Test Conditions f

Input Frequency on TIMER Pin t

Pulse Width at TIMER Pin

= 3.0V

> 4.5V

6.7 SPI CHARACTERISTICS

= -40 to +125°C unless otherwise specified)

Symbol

CL t

SU t h

Parameter

Clock Frequency

Set-up Time

Hold Time

Test Conditions

Applied on Scl

Applied on Sin

Applied onSin

Min.

125

Min.

Value

Typ.

Value

Typ.

250

Max.

f INT

4

Max.

500

Unit

MHz

μ s ns

Unit kHz ns ns

6.8 ARTIMER ELECTRICAL CHARACTERISTICS

Obsolete Product(s) - Obsolete Product(s)

Symbol Parameter Test Conditions

Value

Unit

Min Typ Max f

Input Frequency on ARTIMin Pin

RUN and WAIT Modes

STOP mode 2

MHz

68/83

ST6253C ST6263C ST6263B ST6260C ST6260B

Figure 37. Vol versus Iol on all I/O port at Vdd=5V

0 10 20

Iol (mA)

This curves represents typical variations and is given for guidance only

Figure 38. Vol versus Iol on all I/O port at T=25°C

0 10 20

Iol (mA)

This curves represents typical variations and is given for guidance only

Figure 39. Vol versus Iol for High sink (30mA) I/Oports at T=25°C

T = -40°C

T = 25°C

T = 95°C

T = 125°C

Vdd = 3.0V

Vdd = 4.0V

Vdd = 5.0V

Vdd = 6.0V

Vdd = 3.0V

Vdd = 4.0V

2 Vdd = 5.0V

1 Obsolete Product(s) - Obsolete Product(s)

0 10 20 30 40

Vdd = 6.0V

Iol (mA)

This curves represents typical variations and is given for guidance only

69/83

ST6253C ST6263C ST6263B ST6260C ST6260B

Figure 40. Vol versus Iol for High sink (30mA) I/O ports at Vdd=5V

0 10 20

Iol (mA)

This curves represents typical variations and is given for guidance only

Figure 41. Voh versus Ioh on all I/O port at 25°C

T = -40°C

T = 25°C

T = 95°C

T = 125°C

-2

0 10 20

Ioh (mA)

This curves represents typical variations and is given for guidance only

Figure 42. Voh versus Ioh on all I/O port at Vdd=5V

-2

10 20

Ioh (mA)

This curves represents typical variations and is given for guidance only

Vdd = 3.0V

Vdd = 4.0V

Vdd = 5.0V

Vdd = 6.0V

T = -40°C

T = 25°C

T = 95°C

T = 125°C

70/83

ST6253C ST6263C ST6263B ST6260C ST6260B

Figure 43. Idd WAIT versus V

at 8 Mhz for OTP devices

2.5

1.5

0.5

3V 4V 5V

Vdd

This curves represents typical variations and is given for guidance only

Figure 44. Idd STOP versus V

for OTP devices

T = -40°C

T = 25°C

T = 95°C

T = 125°C

-2

3V 4V 5V

Vdd

This curves represents typical variations and is given for guidance only

T = -40°C

T = 25°C

T = 95°C

T = 125°C

Figure 45. Idd STOP versus V

for ROM devices

1.5

0.5

T = -40°C

T = 25°C

T = 95°C

T = 125°C

-0.5

Obsolete Product(s) - Obsolete Product(s)

Vdd

5V 6V

This curves represents typical variations and is given for guidance only

71/83

ST6253C ST6263C ST6263B ST6260C ST6260B

Figure 46. Idd WAIT versus V

at 8Mhz for ROM devices

2.5

1.5

0.5

3V 4V 5V

Vdd

This curves represents typical variations and is given for guidance only

Figure 47. Idd RUN versus V

at 8 Mhz for ROM and OTP devices

3V 4V 5V 6V

Vdd

This curves represents typical variations and is given for guidance only

Figure 48. LVD thresholds versus temperature

4.2

4.1

T = -40°C

T = 25°C

T = 95°C

T = 125°C

T = -40°C

T = 25°C

T = 95°C

T = 125°C

Vup

Vdn

3.9

Obsolete Product(s) - Obsolete Product(s)

3.8

3.7

-40°C 25°C 95°C 125°C

Temp

This curves represents typical variations and is given for guidance only

72/83

ST6253C ST6263C ST6263B ST6260C ST6260B

Figure 49. RC frequency versus V

for ROM ST626xB only

3 4

VDD (volts)]

This curves represents typical variations and is given for guidance only

Figure 50. RC frequency versus V

(Except for ST626xB ROM devices)

R=1OK

R=27K

R=67K

R=100K

R=47K

R=100K

R=470K

0.1

3 3.5

4 4.5

VDD (volts)

5 5.5

This curves represents typical variations and is given for guidance only

Obsolete Product(s) - Obsolete Product(s)

73/83

ST6253C ST6263C ST6263B ST6260C ST6260B

7 PACKAGE MECHANICAL DATA

In order to meet environmental requirements, ST offers these devices in different grades of ECO-

PACK

packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com

. ECOPACK

is an ST trademark.

Figure 51. 20-Pin Plastic Dual In-Line Package, 300-mil Width

1 b

D b2 e

E1 eB c

Dim.

mm inches

Min Typ Max Min Typ Max

A1 0.38

5.33

0.015

0.210

A2 2.92

3.30

4.95 0.115 0.130 0.195

b 0.36

0.46

0.56 0.014 0.018 0.022

b2 1.14

1.52

1.78 0.045 0.060 0.070

c 0.20

0.25

0.36 0.008 0.010 0.014

D 24.89 26.16 26.92 0.980 1.030 1.060

D1 e

0.13

2.54

0.005

0.100

eB 10.92

0.430

E1 6.10

6.35

7.11 0.240 0.250 0.280

L 2.92

3.30

3.81 0.115 0.130 0.150

Number of Pins

N 20

Figure 52. 20-Pin Ceramic Side-Brazed Dual In-Line Package

CDIP20W

Dim.

mm inches

Min Typ Max Min Typ Max

A1 0.38

3.63

0.015

0.143

B 3.56 0.46 0.56 0.140 0.018 0.022

B1 1.14 12.70 1.78 0.045 0.500 0.070

C 0.20 0.25 0.36 0.008 0.010 0.014

D 24.89 25.40 25.91 0.980 1.000 1.020

D1 22.86

0.900

E1 6.99 7.49 8.00 0.275 0.295 0.315

e 2.54

0.100

G 6.35 6.60 6.86 0.250 0.260 0.270

1.14

0.045

L 2.92 3.30 3.81 0.115 0.130 0.150

12.70

4.22

0.500

0.166

Number of Pins

74/83

ST6253C ST6263C ST6263B ST6260C ST6260B

PACKAGE MECHANICAL DATA (Cont’d)

Figure 53. 20-Pin Plastic Small Outline Package, 300-mil Width

B e

E H a

L h x 45× c

Dim.

mm inches

Min Typ Max Min Typ Max

A 2.35

A1 0.10

2.65 0.093

0.30 0.004

0.104

0.012

B 0.33

C 0.23

D 12.60

E 7.40

0.51 0.013

0.32 0.009

13.00 0.496

7.60 0.291

0.020

0.013

0.512

0.299

H 10.00

1.27

10.65 0.394

0.050

0.419

0.25

0°

0.40

0.75 0.010

8° 0°

1.27 0.016

Number of Pins

0.030

8°

0.050

N 20

Obsolete Product(s) - Obsolete Product(s)

75/83

ST6253C ST6263C ST6263B ST6260C ST6260B

8 ORDERING INFORMATION

8.1 OTP/EPROM VERSIONS

Table 23. OTP/EPROM version ordering information

Sales Type

ST62T53CB6

ST62T53CB3

ST62T53CM6

ST62T53CM3

ST62T60CB6

ST62T60CB3

ST62T60CM6

ST62T60CM3

ST62T63CB6

ST62T63CM6

ST62E60CF1

Program

Memory (Bytes)

1836 (OTP)

3884 (OTP)

1836 (OTP)

3884 (EPROM)

EEPROM (Bytes)

128

8.1.1 IMPORTANT NOTE

For OTP devices, data retention and programmability must be guaranteed by a screening procedure. Refer to Application Note AN886.

Temperature Range

-40 to + 85°C

-40 to + 125°C

-40 to + 85°C

-40 to + 125°C

-40 to + 85°C

-40 to + 125°C

-40 to + 85°C

-40 to + 125°C

-40 to + 85°C

0 to +70°C

Package

PDIP20

PSO20

PDIP20

PSO20

PDIP20

PSO20

CDIP20

Obsolete Product(s) - Obsolete Product(s)

76/83

ST6253C ST6263C ST6263B ST6260C ST6260B

8.2 FASTROM VERSIONS

The ST62P53C, ST62P60C and ST62P63C are the F actory A dvanced S ervice T echnique ROM

(FASTROM) versions of ST62T53C, ST6260B and ST62T63C OTP devices.

They offer the same functionality as OTP devices, selecting as FASTROM options the options defined in the programmable option byte of the OTP version. The following section deals with the procedure for transfer of customer codes to STMicroelectronics.

8.2.1 Transfer of Customer Code

Customer code is made up of the ROM contents and the list of the selected FASTROM options.

The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to FFh.

The selected options are communicated to STMicroelectronics using the correctly filled OPTION

LIST appended. See page 81 .

8.2.2 Listing Generation and Verification

When STMicroelectronics receives the user’s

ROM contents, a computer listing is generated from it. This listing refers exactly to the ROM contents and options which will be used to produce the specified MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agreement for the production of the specific customer

MCU.

The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.

Table 24. ROM Memory Map for ST62P60C

Device Address

0000h-007Fh

0080h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Description

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Table 25. ROM Memory Map: ST62P53C/P63C

Device Address

0000h-087Fh

0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Description

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Table 26. FASTROM version ordering information

Sales Type

ST62P53CB1/XXX

ST62P53CB6/XXX

ST62P53CB3/XXX (*)

ST62P53CM1/XXX

ST62P53CM6/XXX

ST62P53CM3/XXX (*)

ROM (Bytes) EEPROM (Bytes) Temperature Range

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

Package

PDIP20

1836 -

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

PSO20

ST62P60CB1/XXX

ST62P60CB6/XXX

ST62P60CB3/XXX (*)

ST62P60CM1/XXX

ST62P60CM6/XXX

ST62P60CM3/XXX (*)

3884 128

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

0 to + 70°C

PDIP20

PSO20 -40 to + 85°C

-40 to + 125°C

ST62P63CB1/XXX Obsolete Product(s) - Obsolete Product(s)

ST62P63CB3/XXX (*)

1836 64

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

0 to + 70°C

PDIP20

ST62P63CM1/XXX

ST62P63CM6/XXX -40 to + 85°C PSO20

ST62P63CM3/XXX (*) -40 to + 125°C

(*) Advanced information

77/83

ST6253C ST6263C ST6263B ST6260C ST6260B

8.3 ROM VERSIONS

Table 1. ROM Version Ordering Information

Sales Type

ST6253CB1/XXX

ST6253CB6/XXX

ST6253CB3/XXX

ST6253CM1/XXX

ST6253CM6/XXX

ST6253CM3/XXX

ST6260BB1/XXX

ST6260BB6/XXX

ST6260BB3/XXX

ST6260BM1/XXX

ST6260BM6/XXX

ST6260BM3/XXX

ST6263BB1/XXX

ST6263BB6/XXX

ST6263BB3/XXX

ST6263BM1/XXX

ST6263BM6/XXX

ST6263BM3/XXX

ROM (Bytes)

1836

3884

1836

EEPROM (Bytes)

128

Temperature Range

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

0 to + 70°C

-40 to + 85°C

-40 to + 125°C

Package

PDIP20

PSO20

PDIP20

PSO20

PDIP20

PSO20

The ST6253C, ST6260B and ST6263B are mask programmed ROM versions of ST62T53C,

ST6260B and ST62T63C OTP devices.

They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version, except the LVD & OSG options that are not available on the ST6260B/63B ROM device.

Obsolete Product(s) - Obsolete Product(s)

78/83

ST6253C ST6263C ST6263B ST6260C ST6260B

Figure 54. Programming wave form In case the user wants to blow this fuse, high voltage must be applied on the TEST pin.

Figure 55. Programming Circuit

0.5s min

TEST

5V 47mF

100nF 15

14V typ

TEST PROTECT

150 µs typ

14V TEST

100mA max

100nF

ZPD15

15V

VR02003

4mA typ

Note: ZPD15 is used for overvoltage protection t

VR02001

8.3.1 ROM READOUT PROTECTION

If the ROM READOUT PROTECTION option is selected, a protection fuse can be blown to prevent any access to the program memory content.

The following section deals with the procedure for transfer of customer codes to STMicroelectronics.

8.3.2 Transfer of Customer Code

Customer code is made up of the ROM contents and the list of the selected mask options. The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to

FFh.

The selected mask options are communicated to

STMicroelectronics using the correctly filled OP-

TION LIST appended. See page 81 .

8.3.3 Listing Generation and Verification

When STMicroelectronics receives the user’s ROM contents, a computer listing is generated from it.

This listing refers exactly to the mask which will be used to produce the specified MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelec Obsolete Product(s) - Obsolete Product(s) customer mask.

The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.

79/83

Table 27. ROM Memory Map for ST6260B

Device Address

0000h-007Fh

0080h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Description

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

ST6253C ST6263C ST6263B ST6260C ST6260B

Table 28. ROM Memory Map for ST6253C/63B

Device Address

0000h-087Fh

0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Description

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Obsolete Product(s) - Obsolete Product(s)

80/83

ST6253C ST6263C ST6263B ST6260C ST6260B

ST6253C/60B/63B/P53C/P60C/P63C MICROCONTROLLER OPTION LIST

Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact:

Phone:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STMicroelectronics references:

Device:

Package:

[ ] ST6253C (2 KB)

[ ] ST62P53C (2 KB)

Conditioning option:

Temperature Range:

[ ] ST6260B (4 KB)

[ ] ST62P60C (4 KB)

[ ] ST6263B (2 KB)

[ ] ST62P63C (2 KB)

[ ] Dual in Line Plastic

[ ] Small Outline Plastic with conditioning

[ ] Standard (Tube)

[ ] 0°C to + 70°C

[ ] - 40°C to + 125°C

[ ] Tape & Reel

[ ] - 40°C to + 85°C

Marking: [ ] Standard marking

[ ] Special marking (ROM only)

PDIP28 (10 char. max): _ _ _ _ _ _ _ _ _ _

PSO28 (8 char. max): _ _ _ _ _ _ _ _

Authorized characters are letters, digits, '.', '-', '/' and spaces only.

SSOP28 (11 char. max): _ _ _ _ _ _ _ _ _ _ _

Oscillator Safeguard*:

Oscillator Selection:

[ ] Enabled [ ] Disabled

[ ] Quartz crystal / Ceramic resonator

[ ] RC network

Reset Delay: [ ] 32768 cycle delay [ ] 2048 cycle delay

Watchdog Selection:

PB1:PB0 Pull-Up at RESET*:

PB3:PB2 Pull-Up at RESET*:

External STOP Mode Control:

[ ] Software Activation

[ ] Enabled

[ ] Hardware Activation

[ ] Disabled

Readout Protection: FASTROM:

[ ] Enabled

ROM:

[ ] Disabled

[ ] Enabled:

[ ] Fuse is blown by STMicroelectronics

[ ] Fuse can be blown by the customer

[ ] Disabled

Low Voltage Detector*: [ ] Enabled [ ] Disabled

NMI pull-up*: [ ] Enabled [ ] Disabled

ADC Synchro*:

*except on ST6260B/63B/53C

[ ] Enabled [ ] Disabled Obsolete Product(s) - Obsolete Product(s)

Comments:

Oscillator Frequency in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply Operating Range in the application:

Notes:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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9 REVISION HISTORY

Table 29. Document revision history

Date

Jul-2001

27-Mar-2009

Rev.

2.8

Main Changes

Modification of “Additional Notes for EEPROM Parallel Mode” (p.13)

In section 4.2 on page 43: vector #4 instead of vector #3 for the timer interrupt request.

Changed f

values in section 6.4 on page 68.

Changed Figure 49 on page 74.

Changed option list on page 82.

Updated part numbers on page 1 and section 8 on page 76

Replaced 255 by 256 in the formula for max resolution ARTIMout duty cycle in section 4.3.2 on page 45

Altered note in “Capture Mode With Reset Of Counter And Prescaler, and PWM generation” paragraph on

page 48

Added a note in the description of ARMC register in section 4.3.3 on page 49

Added ECOPACK information in section 7 on page 74

Added

Section 8.1.1 IMPORTANT NOTE on page 76

Obsolete Product(s) - Obsolete Product(s)

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ST6253C ST6263C ST6263B ST6260C ST6260B

Please Read Carefully:

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Obsolete Product(s) - Obsolete Product(s)

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Publicitate

STMicroelectronics ST6260C Datasheet

8-bit MCUs with A/D converter, safe reset, auto-reload timer, EEPROM and SPI

Table of Contents

Table of Contents

1 GENERAL DESCRIPTION

2 CENTRAL PROCESSING UNIT

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

4 ON-CHIP PERIPHERALS

–

5 SOFTWARE

6 ELECTRICAL CHARACTERISTICS

4

7 PACKAGE MECHANICAL DATA

8 ORDERING INFORMATION

9 REVISION HISTORY

8-bit MCUs with A/D converter, safe reset, auto-reload timer, EEPROM and SPI

Table of Contents

Table of Contents

1 GENERAL DESCRIPTION

2 CENTRAL PROCESSING UNIT

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

4 ON-CHIP PERIPHERALS

–

5 SOFTWARE

6 ELECTRICAL CHARACTERISTICS

4

7 PACKAGE MECHANICAL DATA

8 ORDERING INFORMATION

9 REVISION HISTORY

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