STMicroelectronics ST6208C Programming Manual
광고
광고
ST6 FAMILY
PROGRAMMING MANUAL
Rev. 2.0
October 2004
1
PROGRAMMING MANUAL
ST6 FAMILY
INTRODUCTION
This manual deals with the description of the instruction set and addressing modes of ST6 microcontroller series. The manual is divided in two main sections. The first one includes, after a general family description, the addressing modes description. The second section includes the detailed description of ST6 instruction set. Each instruction is described in detail with the differences between each ST6 series.
Table 1. ST6 Series Core Characteristics
Stack Levels
Interrupt Vectors
NMI
Flags Sets
Program ROM
Data RAM
Data ROM
Carry Flag SUB
Instruction
Carry Flag CP Instruction
ST6 Series
6
5
YES
3
2K + 2K
∗ n
20K Max
64 byte*m
64 byte pages in ROM
Reset if A > Source
Set if A < Source
October 2004
Rev. 2.0
2/45
1
Table of Contents
3/45
PROGRAMMING MODEL
1 PROGRAMMING MODEL
It is useful at this stage to outline the programming model of the ST6 series, by which we mean the available memory spaces, their relation to one another, the interrupt philosophy and so on.
Memory Spaces . The ST6 devices have three different memory spaces: data, program and stack. All addressing modes are memory space specific so there is no need for the user to specify which space is being used as in more complex systems. The stack space, which is used automatically with subroutine and interrupt management for program counter storage, is not accessible to the user.
Figure 1. ST6 Family Programming Model
INDEX
REGISTER b7 b7 b7 b7 b7
X REG. POINTER
Y REG. POINTER
V REGISTER
W REGISTER b0 b0 b0
SHORT
DIRECT
ADDRESSING
MODE b0
ACCUMULATOR b0 b11 PROGRAM COUNTER b0
SIX LEVELS
STACK REGISTER
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
C
C
C
Z
Z
Z
VA000423
4/45
1
PROGRAMMING MODEL
(Cont’d)
Figure 2. ST6 Data Space Example b7
NOT IMPLEMENTED
DATA ROM/EPROM WINDOW 64 BYTE
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
DATA RAM 60 BYTES
PORT A DATA REGISTER - DRA
PORT B DATA REGISTER - DRB
PORT C DATA REGISTER - DRC
RESERVED
PORT A DATA DIRECTION REGISTER - DDRA
PORT B DATA DIRECTION REGISTER - DDRB
PORT C DATA DIRECTION REGISTER - DDRC
RESERVED
INTERRUPT OPTION REGISTER - IOR
DATA ROM WINDOW REGISTER - DRWR
RESERVED
PORT A OPTION REGISTER - ORA
PORT B OPTION REGISTER -ORB
PORT C OPTION REGISTER - ORC
RESERVED
A/D DATA REGISTER - ADR
A/D CONTROL REGISTER - ADCR
TIMER PSC REGISTER - PSCR
TIMER COUNTER REGISTER - TCR
TIMER STATUS CONTROL REGISTER - TSCR
RESERVED
WATCHDOG REGISTER - WDGR
RESERVED
ACCUMULATOR
PROGRAMMING MODEL b0
0C8h
0C9h
0CAh
0CBh
0CCh
0CDh
0CEh
0CFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h
0D9h
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0BFh
0FEh
OFFh
5/45
PROGRAMMING MODEL
Figure 3. ST6 Program Memory Example b7 b0
NOT IMPLEMENTED
RESERVED
0000h
07FFh
0800h
087Fh
0880h
USER PROGRAM ROM
1828 BYTES
RESERVED
INTERRUPT VECTOR #4
A/D INTERRUPT
INTERRUPT VECTOR #3
TIMER INTERRUPT
INTERRUPT VECTOR #2
PORT B & C INTERRUPT
INTERRUPT VECTOR #1
PORT A INTERRUPT
0F9Fh
0FA0h
0FEFh
0FF0h
0FF1h
0FF2h
0FF3h
0FF4h
0FF5h
0FF6h
0FF7h
0FF8h
RESERVED
INTERRUPT VECTOR #0
NMI INTERRUPT
USER RESET VECTOR
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
On EPROM versions there are no re-served areas. These reserved bytes are present on ROM/OTP versions.
Data Memory Space . The following registers in the data space have fixed addresses which are hardware selected so as to decrease access times and reduce addressing requirements and hence program length.
The Accumulator is an 8-bit register in location 0FFh. The X, Y, V & W registers have the addresses 80h-
83h respectively. These are used for short direct addressing, reducing byte requirements in the program while the first two, X & Y, can also be used as index registers in the indirect addressing mode. These registers are part of the data RAM space. In the ST6 for data space ROM a 6-bit (64 bytes addressing) window multiplexing in program ROM is available through a dedicated data ROM banking register.
6/45
PROGRAMMING MODEL
PROGRAMMING MODEL
(Cont’d)
For data RAM and I/O expansion the lowest 64 bytes of data space (00h-03Fh) are paged through a data
RAM banking register.
Self-check Interrupt Vector FF8h & FF9h:jp (self-check interrupt routine)
A jump instruction to the reset and interrupt routines must be written into these locations.
ST6 Program Memory Space . The ST6 devices can directly address up to 4K bytes (program counter is
12 bits wide). A greater ROM size is obtained by paging the lower 2K of the program ROM through a dedicated banking register located in the data space. The higher 2K of the program ROM can be seen as static and contains the reset, NMI and interrupt vectors at the following fixed locations:
Reset Vector
NMI Interrupt Vector
Non user Vector
Non user Vector
Interrupt #1 Vector
Interrupt #2 Vector
Interrupt #3 Vector
Interrupt #4 Vector
FFEh & FFFh:jp (reset routine)
FFCh & FFDh:jp (NMI routine)
FFAh & FFBh
FF8h & FF9h
FF6h & FF7h jp (Int 1 routine)
FF4h & FF5h jp (Int 2 routine)
FF2h & FF3h jp (Int 3 routine)
FF0h & FF1h jp (Int 4 routine)
Program Counter & Stack Area . The program counter is a 12-bit counter register since it has to cover a direct addressing of 4K byte program memory space. When an interrupt or a subroutine occurs the current
PC value is forward "pushed" into a deep LIFO stacking area. On the return from the routine the top (last in) PC value is "popped" out and becomes the current PC value. The ST60/61 series offer a 4-word deep stack for program counter storage during interrupt and sub-routines calls. In the ST6 series the stack is 6word deep.
Status Flags . Three pairs of status flags, each pair consisting of a Zero flag and a Carry flag, are available. In the ST6 an additional third set is available. One pair monitors the normal status while the second monitors the state during interrupts; the third flags set monitors the status during Non Maskable interrupt servicing. The switching from one set to another is automatic as the interrupt requests (or NMI request for
ST6 only) are acknowledged and when the program returns after an interrupt service routine. After reset, the NMI set is active, until the first RETI instruction is executed.
ST6 Interrupt Description . The ST6 devices have 5 user interrupt vectors (plus one vector for testing purposes). Interrupt vector #0 is connected to the not maskable interrupt input of the core. Interrupts from
#1 to #4 can be connected to different on-chip and external sources (see individual datasheets for detailed information). All interrupts can be globally disabled through the interrupt option register. After the reset
ST6 devices are in NMI mode, so no other interrupts can be accepted and the NMI flags set is in use, until the RETI instruction is performed. If an interrupt is detected, a special cycle is executed. During this cycle, the program counter is loaded with the related interrupt vector address. NMI can interrupt other interrupt routines at any time while normal interrupt can't interrupt each other. If more than one interrupt is awaiting service, they will be accepted according to their priority. Interrupt #1 has the highest priority while interrupt
#4 the lowest. This priority relationship is fixed.
Figure 4. ST6 Stack Area
PROGRAM COUNTER
WHEN
RET OR RETI
OCCURS
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
WHEN CALL
OR
INTERRUPT REQUEST
OCCURS
VA000424
7/45
ADDRESSING MODES
2 ADDRESSING MODES
The ST6 core offers nine addressing modes, which are described in the following paragraphs. Three different address spaces are available: Program space, Data space, and Stack space. Program space contains the instructions which are to be executed, plus the data for immediate mode instructions. Data space contains the Accumulator, the X,Y,V and W registers, peripheral and Input/Output registers, the RAM locations and Data ROM locations (for storage of tables and constants). Stack space contains six 12-bit
RAM cells used to stack the return addresses for subroutines and interrupts.
Immediate . In the immediate addressing mode, the operand of the instruction follows the opcode location. As the operand is a ROM byte, the immediate addressing mode is used to access constants which do not change during program execution (e.g., a constant used to initialize a loop counter).
Direct . In the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. Direct addressing allows the user to directly address the
256 bytes in Data Space memory with a single two-byte instruction.
Short Direct . The core can address the four RAM registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. In this case, the instruction is only one byte and the selection of the location to be processed is contained in the opcode. Short direct addressing is a subset of the direct addressing mode. (Note that 80h and 81h are also indirect registers).
Extended . In the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant bits of the opcode with the byte following the opcode. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the
4K bytes Program space.
An extended addressing mode instruction is 2-bytes long.
Program Counter Relative . The relative addressing mode is only used in conditional branch instructions.
The instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the relative instruction. If the condition is not true, the instruction which follows the relative instruction is executed. The relative addressing mode instruction is one-byte long. The opcode is obtained by adding the three most significant bits which characterize the kind of the test, one bit which determines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to Fh) which must be added or subtracted to the address of the relative instruction to obtain the address of the branch.
Bit Direct . In the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the address of the byte in which the specified bit must be set or cleared.
Thus, any bit in the 256 locations of Data space memory can be set or cleared.
Bit Test & Branch . The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit test and branch instruction is three-byte long. The bit identification and the tested condition are included in the opcode byte. The address of the byte to be tested follows immediately the opcode in the Program space. The third byte is the jump displacement, which is in the range of -127 to +128. This displacement can be determined using a label, which is converted by the assembler.
Indirect . In the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the indirect registers, X or Y (80h,81h). The indirect register is selected by the bit 4 of the opcode. A register indirect instruction is one byte long.
Inherent . In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. These instructions are one byte long.
8/45
ST6 INSTRUCTION SET
3 ST6 INSTRUCTION SET
The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following paragraphs describe the different types.
All the instructions belonging to a given type are presented in individual tables.
Load & Store . These instructions use one, two or three bytes in relation with the addressing mode. One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one of the addressing modes.
For Load Immediate one operand can be any of the 256 data space bytes while the other is always immediate data.
Table 2. Load & Store Instructions
Flags
Instruction Addressing Mode Bytes Cycles
LD A, X
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
LD V, A
LD W, A
LD A, rr
LD rr, A
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Indirect
Indirect
Immediate
Immediate
1
1
1
1
2
3
1
1
2
2
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
Z
∆
∆
∆
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
C
*
*
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# .
Immediate data (stored in ROM memory) rr.
Data space register
∆
.
Affected
* .
Not Affected
9/45
ST6 INSTRUCTION SET
ST6 INSTRUCTION SET (Cont’d)
Arithmetic and Logic . These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulator while the other can be either a data space memory content or an immediate value in relation with the addressing mode. In CLR,
DEC, INC instructions the operand can be any of the 256 data space addresses. In COM, RLC, SLA the operand is always the accumulator.
Table 3. Arithmetic & Logic Instructions
Flags
Instruction Addressing Mode Bytes Cycles
CP A, rr
CPI A, #N
DEC X
DEC Y
DEC V
DEC W
DEC A
DEC rr
DEC (X)
DEC (Y)
INC X
INC Y
INC V
INC W
INC A
INC rr
ADD A, (X)
ADD A, (Y)
ADD A, rr
ADDI A, #N
AND A, (X)
AND A, (Y)
AND A, rr
ANDI A, #N
CLR A
CLR r
COM A
CP A, (X)
CP A, (Y)
INC (X)
INC (Y)
RLC A
SLA A
SUB A, (X)
SUB A, (Y)
SUB A, rr
SUBI A, #N
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
2
2
1
1
1
1
1
1
2
2
2
2
1
1
1
1
2
2
1
1
1
2
3
1
1
1
1
2
2
2
2
2
1
1
1
Direct
Immediate
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Direct
Immediate
Indirect
Indirect
Direct
Immediate
Short Direct
Direct
Inherent
Indirect
Indirect
Indirect
Indirect
Inherent
Inherent
Indirect
Indirect
Direct
Immediate
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
∆
∆
∆
∆
∆
Z
∆
∆
∆
∆
∆
*
*
*
*
*
∆
∆
∆
*
∆
∆
∆
*
*
*
*
*
*
*
*
∆
∆
∆
∆
C
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
∆
*
*
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory) rr. Data space register
∆
. Affected
* . Not Affected
10/45
ST6 INSTRUCTION SET
ST6 INSTRUCTION SET (Cont’d)
Conditional Branch . The branch instructions achieve a branch in the program when the selected condition is met.
Bit Manipulation Instructions . These instructions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations.
Control Instructions . The control instructions control the MCU operations during program execution.
Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutine calls inside the whole program space.
Table 4. Conditional Branch Instructions
Flags
Instruction Branch If Bytes Cycles
JRC e
JRNC e
JRZ e
JRNZ e
JRR b, rr, ee
JRS b, rr, ee
C = 1
C = 0
Z = 1
Z = 0
Bit = 0
Bit = 1
1
1
3
3
1
1
2
2
5
5
2
2 *
*
Z
*
*
*
*
*
*
C
*
*
∆
∆
Notes : b.
3-bit address e.
5-bit signed displacement in the range -15 to +16<F128M> ee.
8-bit signed displacement in the range -126 to +129
Table 5. Bit Manipulation Instructions rr. Data space register
∆
. Affected. The tested bit is shifted into carry.
* . Not Affected
Flags
Instruction Addressing Mode Bytes Cycles
SET b,rr
RES b,rr
Bit Direct
Bit Direct
2
2
4
4
Z
*
*
C
*
*
Notes: b.
3-bit address rr.
Data space register
Table 6. Control Instructions
* . Not Affected
Flags
Instruction Addressing Mode Bytes Cycles
NOP
RET
RETI
STOP (1)
WAIT
Notes:
1.
This instruction is deactivated and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
∆
.
Affected
*.
Not Affected
Table 7. Jump & Call Instructions
Instruction Flags
Addressing Mode Bytes Cycles
CALL abc
JP abc
Extended
Extended
2
2
4
4
Z
*
*
C
*
*
Notes: abc. 12-bit address
* .
Not Affected
Inherent
Inherent
Inherent
Inherent
Inherent
1
1
1
1
1
2
2
2
2
2
*
∆
*
*
Z
*
*
∆
*
*
C
*
11/45
ST6 INSTRUCTION SET
Opcode Map Summary.
The following table contains an opcode map for the instructions used by the ST6
LOW LOW
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
HI HI
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
2 JRNZ 4 e
1
2 pcr 2
JRNZ 4 e
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1 pcr 2
2 RNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e
1 pcr 2 e
JRNC 5 JRR 2 b0,rr,ee e pcr 3
JRNC 5 bt 1
JRS 2 b0,rr,ee e pcr 3
JRNC 5 b4,rr,ee bt 1
JRR 2 e pcr 3
JRNC 5 pcr 3 bt 1
JRS 2 b4,rr,ee e bt 1 e
JRNC 5 JRR 2 b2,rr,ee e pcr 3
JRNC 5 bt 1
JRS 2 b2,rr,ee e pcr 3
JRNC 5 b6,rr,ee bt 1
JRR 2 e pcr 3
JRNC 5 b6,rr,ee bt 1
JRS 2 e pcr 3
JRNC 5 b1,rr,ee bt 1
JRR 2 e pcr 3
JRNC 5 b1,rr,ee bt 1
JRS 2 e pcr 3
JRNC 5 b5,rr,ee bt 1
JRR 2 e pcr 3
JRNC 5 b5,rr,ee bt 1
JRS 2 e pcr 3
JRNC 5 b3,rr,ee bt 1
JRR 2 e pcr 3
JRNC 5 b3,rr,ee bt 1
JRS 2 e pcr 3
JRNC 5 b7,rr,ee bt 1
JRR 2 e pcr 3
JRNC 5 b7,rr,ee bt 1
JRS 2 pcr 3 bt 1 ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc ext 1
CALL 2 abc e e e e e e e e e e e e e e e
JRZ pcr
JRZ 4 pcr 1
JRZ pcr
JRZ 4 pcr 1
JRZ pcr
JRZ 4 pcr 1
JRZ pcr
JRZ 4 pcr 1
JRZ pcr
JRZ 4 pcr 1
JRZ pcr
JRZ 4 pcr 1
JRZ pcr
JRZ 4 pcr 1
JRZ pcr
JRZ 4 pcr 1
# x
# a,x
# y
# a,y
# v
# a,v
# w
# a,w
2
1
INC 2 sd 1
2
1
LD 2 sd 1
2
1
INC 2 sd 1
2
1
LD 2 sd 1
2
1
INC 2 sd 1
2
1
LD 2 sd 1
2
1
INC 2 sd 1
2
1
LD 2 sd 1 e e e e e e e e e e e e e e e e
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC prc
JRC 4 prc 1
JRC prc
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC prc a,(x)
AND ind
ANDI a,nn imm a,(x)
SUB ind
SUBI a,nn imm
DEC
(x) ind
LD a,(x) ind
LDI a,nn imm
CP a,(x) ind
CPI a,nn imm a,(x)
ADD ind
ADDI a,nn imm
INC
(x) ind
#
(x),a
#
#
LD ind
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Abbreviations for Addressing Modes: Legend: dir Direct sd Short Direct e 5-Bit Displacement imm Immediate inh bt
Inherent ext Extended b.d Bit Direct
Bit Test b 3-Bit rr 1byte dataspace address nn abc ee
1 byte immediate data
12-bit address
8-bit Displacement pcr Program Counter Relative ind Indirect
Cycle
Operand
Bytes
Addressing Mode
2
1 e
JRC prc
Mnemonic
12/45
ST6 INSTRUCTION SET
Opcode Map Summary (Continued)
LOW
8
1000
9
1001
A
1010
HI
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111 abc abc abc abc abc abc abc abc abc abc abc abc abc abc abc abc
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1
JP 2 ext 1 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4 pcr 2 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4 e pcr 2
JRNC 4
2 JRNZ 4 e
1
2 pcr 2
JRNZ 4 e
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1
2
1
2 pcr 2
JRNZ 4 e
1 pcr 2
2 RNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e pcr 2
JRNZ 4 e
1 pcr 2
B
1011 b5,rr b.d 1
RES 2 b5,rr b.d 1
SET 2 b3,rr b.d 1
RES 2 b3,rr b.d 1
SET 2 b7,rr b.d 1
RES 2 b7,rr b.d 1
SET 2 b.d 1 b0,rr
RES 2 b0,rr b.d 1
SET 2 b4,rr b.d 1
RES 2 b4,rr b.d 1
SET 2 e b.d 1 b2,rr
RES 2 b2,rr b.d 1
SET 2 b6,rr b.d 1
RES 2 b6,rr b.d 1
SET 2 b1,rr b.d 1
RES 2 b1,rr b.d 1
SET 2
C
1100 e e e e e e e e e e e e e e e
JRZ 4 pcr 3
JRZ 4 pcr 1
JRZ 4 pcr
JRZ 4 pcr 1
JRZ 2 pcr 1
JRZ 4 pcr 1
JRZ 2 pcr 1
JRZ 4 pcr 1
JRZ pcr
JRZ 4 pcr 1
JRZ 4 pcr 1
JRZ 4 pcr 1
JRZ 2 pcr 1
JRZ 4 pcr 1
JRZ 2 pcr 1
JRZ 4 pcr 1
D
1101 w,a
LDI 2 rr,nn imm 1
DEC 2 x sd 1
COM 2 a
1
LD 2 x,a sd 1
RETI 2 inh 1
DEC 2 y sd 1
STOP 2 inh 1
LD 2 y,a sd 1
2
#
1
DEC 2 v sd 1
RCL 2 a inh 1
LD 2 v,a sd 1
RET 2 inh 1
DEC 2 w sd 1
WAIT 2 inh 1
LD 2 sd 1
E
1110 e e e e e e e e e e e e e e e e
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
JRC 4 prc 1
JRC 4 prc 2
F
1111
LD a,(y) ind
LD a,rr dir
CP a,(y) ind
CP a,rr a,(y) dir
ADD a,rr ind
ADD dir
INC
(y) ind
INC rr dir
LD
(y),a ind
LD rr,a a,(y) dir
AND a,rr ind
AND a,(y) dir
SUB a,rr ind
SUB dir
DEC
(y) ind
DEC rr dir
LOW
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
HI
Abbreviations for Addressing Modes: Legend: dir Direct sd Short Direct e 5-Bit Displacement imm Immediate inh bt
Inherent ext Extended b.d Bit Direct
Bit Test b 3-Bit rr 1byte dataspace address nn abc ee
1 byte immediate data
12-bit address
8-bit Displacement pcr Program Counter Relative ind Indirect
Cycle
Operand
Bytes
Addressing Mode
2
1 e
JRC prc
Mnemonic
13/45
ST6 INSTRUCTION SET
ADD
Addition
ADD
Mnemonic : ADD
Function : Addition
Description : The contents of the source byte is added to the accumulator leaving the result in the accumulator. The source register remains unaltered.
Operation : dst
The destination must be the accumulator.
Instruction Format
ADD dst,src
ADD A,A
ADD A,X
ADD A,Y
ADD A,V
ADD A,W
ADD A,(X)
ADD A,(Y)
ADD A,rr
Opcode (Hex)
5F FF
5F 80
5F 81
5F 82
5F 83
47
4F
5F rr
Bytes
2
2
2
2
2
1
1
2
Cycles
4
4
4
4
4
4
4
4
∆
∆
∆
∆
∆
∆
Z
∆
∆
Flags
Notes : rr.
∆
:
1 Byte dataspace address.
Z is set if the result is zero. Cleared otherwise.
C is cleared before the operation and than set if there is an overflow from the 8-bit result.
∆
∆
∆
∆
∆
∆
C
∆
∆
Example : If data space register 22h contains the value 33h and the accumulator holds the value 20h then the instruction,
ADD A,22h will cause the accumulator to hold 53h (i.e. 33+20).
Addressing Modes : Source:
Destination: Accumulator
14/45
ST6 INSTRUCTION SET
ADDI
Addition Immediate
ADDI
Mnemonic : ADDI
Function : Addition Immediate
Description : The immediately addressed data (source) is added to the accumulator leaving the result in the accumulator.
Operation : dst
The destination must be the accumulator.
Instruction Format
ADDI dst,src
ADDI A,nn
Opcode (Hex)
57 nn
Bytes
2
Cycles
4
Z
∆
Flags
Notes: nn.
1 Byte immediate data
∆
: Z is set if result is zero. Cleared otherwise
C is cleared before the operation and than set if there is an overflow from the 8-bit result
C
∆
Example : If the accumulator holds the value 20h then the instruction,
ADDI A,22h will cause the accumulator to hold 42h (i.e. 22+20).
Addressing Modes : Source: Immediate
Destination: Accumulator
15/45
ST6 INSTRUCTION SET
AND
Logical AND
AND
Mnemonic : AND
Function : Logical
Description : This instruction logically ANDs the source register and the accumulator. The result is left in the destination register and the source is unaltered.
Operation : dst
The destination must be the accumulator.
Instruction Format
AND dst,src
AND A,A
AND A,X
AND A,Y
AND A,V
AND A,W
AND A,(X)
AND A,(Y)
AND A,rr
Opcode (Hex)
BF FF
BF 80
BF 81
BF 82
BF 83
A7
AF
BF rr
Notes : rr.
1 Byte dataspace address
*.
∆
.
C is unaffected
Z is set if the result is zero. Cleared otherwise.
Bytes
2
2
2
2
2
1
1
2
Cycles
4
4
4
4
4
4
4
4
∆
∆
∆
Z
∆
∆
∆
∆
∆
Flags
*
*
*
*
*
C
*
*
*
Example : If data space register 54h contains the binary value 11110000 and the accumulator contains the binary value 11001100 then the instruction,
AND A,54h will cause the accumulator to be altered to 11000000.
Addressing Modes : Source: Direct,
Destination: Accumulator
16/45
ST6 INSTRUCTION SET
ANDI
Logical AND Immediate
ANDI
Mnemonic :
Function :
ANDI
Logical AND Immediate
Description : This instruction logically ANDs the immediate data byte and the accumulator.
The result is left in the accumulator.
Operation : dst
The source is immediate data and the destination must be the accumulator.
Instruction Format
ANDI dst,src
ANDI A,nn
Opcode (Hex)
B7 nn
Notes : nn.
1 Byte immediate data
*.
C is unaffected
∆ . Z is set if the result is zero. Cleared otherwise.
Bytes
2
Cycles
4
Z
∆
Flags
C
*
Example : If the accumulator contains the binary value 00001111 then the instruction,
ANDI A,33h will cause the accumulator to hold the value 00000011.
Addressing Modes : Source: Immediate
Destination: Accumulator
17/45
ST6 INSTRUCTION SET
CALL
Call Subroutine
CALL
Mnemonic : CALL
Function : Call
Description : The CALL instruction is used to call a subroutine. It "pushes" the current contents of the program counter (PC) onto the top of the stack. The specified destination address is then loaded into the PC and points to the first instruction of a procedure. At the end of the procedure a RETurn instruction can be used to return to the original program flow. RET pops the top of the stack back into the PC.
Because the ST6 stack is 4 levels deep (ST60) and 6 levels deep (ST62,ST63), a maximum of four/six calls or interrupts may be nested. If more calls are nested, the latest stacked PC values will be lost. In this case returns will return to the PC values stacked first.
Operation : PC !
PC
Instruction Format
CALL dst
CALL abc
Opcode (Hex) c0001 ab
Bytes
2
Cycles
4
Notes : abc. the three half bytes of a 12-bit address, the start location of the subroutine.
*. C,Z not affected
Z
*
Flags
C
*
Example : If the current PC is 345h then the instruction,
CALL 8DCh
The current PC 345h is pushed onto the top of the stack and the PC will be loaded with the value 8DCh. The next instruction to be executed will be the instruction at
8DCh, the first instruction of the called subroutine.
Addressing Modes : Extended
18/45
CLR
Clear
Mnemonic : CLR
Function : Clear
Description : The destination register is cleared to 00h.
Operation : dst
Instruction Format
CLR dst
CLR A
CLR X
CLR Y
CLR V
CLR W
CLR rr
Notes : rr.
∆
.
1 Byte dataspace address
Z set,
∆
. C reset
*.
C,Z unaffected
Opcode (Hex)
DF FF
0D 80 00
0D 81 00
0D 82 00
0D 83 00
0D rr 00
Bytes
2
3
3
3
3
3
Example : If data space register 22h contains the value 33h,
CLR 22h will cause register 22h to hold 00h.
Addressing Modes : Direct
Cycles
4
4
4
4
4
4
ST6 INSTRUCTION SET
CLR
*
*
*
*
*
Z
∆
Flags
*
*
*
*
*
C
∆
19/45
ST6 INSTRUCTION SET
COM
Complement
COM
Mnemonic : COM
Function : Complement
Description : This instruction complements each bit of the accumulator; all bits which are set to
1 are cleared to 0 and vice-versa.
Operation : dst
The destination must be the accumulator.
Instruction Format
COM dst
COM A
Opcode (Hex)
2D
Bytes
1
Note :
∆
: Z is set if the result is zero. Cleared otherwise.
C will contain the value of the MSB before the operation.
Cycles
4
Z
∆
Flags
C
∆
Example : If the accumulator contains the binary value 10111001 then the instruction
COM A will cause the accumulator to be changed to 01000110 and the carry flag to be set
(since the original MSB was 1).
Addressing Modes : Inherent
20/45
ST6 INSTRUCTION SET
CP
Compare
CP
Mnemonic : CP
Function : Compare
Description : This instruction compares the source byte (subtracted from) with the destination byte, which must be the accumulator. The carry and zero flags record the result of this comparison.
Operation src
The destination must be the accumulator, but it will not be changed.
Instruction Format
CP dst,src
CP A,A
CP A,X
CP A,Y
CP A,V
CP A,W
CP A,(X)
CP A,(Y)
CP A,rr
Note : rr. 1 Byte dataspace address
ST60
ST62/63
Example :
Opcode (Hex)
3F FF
3F 80
3F 81
3F 82
3F 83
27
2F
3F rr
Bytes
2
2
1
1
2
2
2
2
Cycles
4
4
4
4
4
4
4
4
Z
∆
∆
∆
∆
∆
∆
∆
∆
Flags
∆
: Z is set if the result is zero. Cleared otherwise.
C is set if Acc
≥
src, cleared if Acc < src.
∆
: Z is set if the result is zero. Cleared otherwise.
C is set if Acc < src, cleared if Acc
≥
src.
If the accumulator contains the value 11111000 and the register 34h contains the value 00011100 then the instruction,
CP A,34h will clear the Zero flag Z and set the Carry flag C, indicating that Acc
≥
src (on
ST60)
∆
∆
∆
C
∆
∆
∆
∆
∆
Addressing Modes : Source: Direct,
Destination: Accumulator
21/45
ST6 INSTRUCTION SET
CPI
Compare Immediate
CPI
Mnemonic : CPI
Function : Compare
Description : This instruction compares the immediately addressed source byte (subtracted from) with the destination byte, which must be the accumulator. The carry and zero flags record the result of this comparison.
Operation src
The source must be the immediately addressed data and the destination must be the accumulator, that will not be changed.
Instruction Format
CPI dst,src
CPI A,nn
Note : nn.
1 Byte immediate data.
Opcode (Hex)
37 nn
Bytes
2
Cycles
4
Z
∆
Flags
C
∆
ST60
ST62/63
∆
: Z is set if the result is zero. Cleared otherwise.
C is set if Acc
≥
src, cleared if Acc < src.
∆
: Z is set if the result is zero. Cleared otherwise.
C is set if Acc < src, cleared if Acc
≥
src.
Example : If the accumulator contains the value 11111000 then the instruction,
CPI A,00011100B will clear the Zero flag Z and set the Carry flag C indicating that Acc
≥
src (on
ST60).
Addressing Modes : Source: Immediate
Destination: Accumulator
22/45
DEC
Decrement
ST6 INSTRUCTION SET
DEC
Mnemonic : DEC
Function : Decrement
Description : The destination register's contents are decremented by one.
Operation : dst
Instruction Format
DEC dst
DEC A
DEC X
DEC Y
DEC V
DEC W
DEC (X)
DEC (Y)
DEC rr
Opcode (Hex)
FF FF
1D
5D
9D
DD
E7
EF
FF rr
Notes : rr.
1 Byte dataspace address
*.
∆
.
C is unaffected
Z is set if the result is zero. Cleared otherwise.
Bytes
1
2
1
1
2
1
1
1
Cycles
4
4
4
4
4
4
4
4
Z
∆
∆
∆
∆
∆
∆
∆
∆
Flags
*
*
*
*
*
*
C
*
*
Example : If the X register contains the value 45h and the data space register 45h contains the value 16h then the instruction,
DEC (X) will cause data space register 45h to contain the value 15h.
Addressing Modes : Short direct, Direct, Indirect.
23/45
ST6 INSTRUCTION SET
INC
Increment
Mnemonic : INC
Function : Increment
Description : The destination register's contents are incremented by one.
Operation : dst
INC
Instruction Format
INC dst
INC A
INC X
INC Y
INC V
INC W
INC (X)
INC (Y)
INC rr
Notes : rr.
1 Byte dataspace address
Opcode (Hex)
7F FF
15
55
95
D5
67
6F
7F rr
Bytes
1
2
1
1
2
1
1
1
Cycles
4
4
4
4
4
4
4
4
Z
∆
∆
∆
∆
∆
∆
∆
∆
Flags
*
*
*
*
*
*
C
*
*
∆
.
Z is set if the result is zero. Cleared otherwise.
Example : If the X register contains the value 45h and the data space register 45h contains the value 16h then the instruction
INC (X) will cause data space register 45h to contain the value 17h.
Addressing Modes : Short direct, Direct, Indirect.
24/45
ST6 INSTRUCTION SET
JP
Jump
JP
Mnemonic : JP
Function : Jump
Description : The JP instruction replaces the PC value with a 12-bit value thus causing a simple jump to another location in the program memory. The previous PC value is lost, not stacked.
Operation : PC
Instruction Format
JP dst
JP abc
Opcode (Hex) c1001 ab
Notes : abc. the three half bytes of a 12-bit address.
*. C,Z not affected
Bytes
2
Cycles
4
Z
*
Flags
C
*
Example : The
JP 5CDh will cause the PC to be loaded with 5CDh and the program will continue from that location.
Addressing Modes : Extended
25/45
ST6 INSTRUCTION SET
JRC
Jump Relative on Carry Flag
JRC
Mnemonic : JRC
Function : Jump Relative on Carry Flag
Description :
Operation :
This instruction causes the carry (C) flag to be tested and if this flag is set then a jump is performed within the program memory. This jump is in the range -15 to
+16 and is relative to the PC value. The displacement e is of five bits. If C=0 then the next instruction is executed.
If C=1, PC !
PC + e where e= 5-bit displacement
Instruction Format
JRC e
Opcode (Hex) e110
Notes : e.
5-bit displacement in the range -15 to +16
*.
C,Z not affected
Bytes
1
Cycles
2
Z
*
Flags
C
*
Example : If the carry flag is set then the instruction,
JRC $+8 will cause a branch forward to PC+8. The user can use labels as identifiers and the assembler will automatically allow the jump if it is in the range -15 to +16.
Addressing Modes : Program Counter Relative
26/45
ST6 INSTRUCTION SET
JRNC
Jump Relative on Non Carry Flag
JRNC
Mnemonic : JRNC
Function : Jump Relative on Non Carry Flag
Description :
Operation :
This instruction causes the carry (C) flag to be tested and if this flag is cleared to zero then a jump is performed within the program memory. This jump is in the range -15 to +16 and is relative to the PC value. The displacement is of five bits.
If C=1 then the next instruction is executed.
If C=0, PC !
PC + e where e= 5-bit displacement
Instruction Format
JRNC e
Opcode (Hex) e010
Notes : e: 5-bit displacement in the range -15 to +16
*: C,Z not affected
Bytes
1
Cycles
2
Z
*
Flags
C
*
Example : If the carry flag is cleared then the instruction,
JRNC $-5 will cause a branch backward to PC-5. The user can use labels as identifiers and the assembler will automatically allow the jump if it is in the range -15 to +16.
Addressing Modes : Program Counter Relative
27/45
ST6 INSTRUCTION SET
JRNZ
Jump Relative on Non Zero Flag
JRNZ
Mnemonic : JRNZ
Function : Jump Relative on Non Zero Flag
Description : This instruction causes the zero (Z) flag to be tested and if this flag is cleared to zero then a jump is performed within the program memory. This jump is in the range -15 to +16 and is relative to the PC value. The displacement is of five bits.
If Z=1 then the next instruction is executed.
Operation PC where e= 5-bit displacement
Instruction Format
JRNZ e
Opcode (Hex) e000
Notes : e.
5-bit displacement in the range -15 to +16.
*.
C,Z not affected
Bytes
1
Cycles
2
Z
*
Flags
C
*
Example : If the zero flag is cleared then the instruction,
JRNZ $-5 will cause a branch backward to PC-5. The user can use labels as identifiers and the assembler will automatically allow the jump if it is in the range -15 to +16.
Addressing Modes : Program Counter Relative
28/45
ST6 INSTRUCTION SET
JRR
Jump Relative if Reset
JRR
Mnemonic : JRR
Function : Jump Relative if RESET
Description :
Operation :
This instruction causes a specified bit in a given dataspace register to be tested.
If this bit is reset (=0) then the PC value will be changed and a relative jump will be performed within the program. The relative jump range is -126 to +129. If the tested bit is not reset then the next instruction is executed.
If bit=0, PC !
PC + ee where ee= 8-bit displacement
Instruction Format
JRR b,rr,ee
Opcode (Hex) b00011 rr ee
Notes : b.
3-bit address rr.
1 Byte dataspace address ee.
8-bit displacement in the range -126 to +129
*.
∆
.
Z is not affected
The tested bit is shifted into carry.
Bytes
3
Cycles
5
Z
*
Flags
C
∆
Example : If bit 4 of dataspace register 70h is reset and the PC=110 then the instruction,
JRR 4, 70h, $-20 will cause the PC to be changed to 90 (110-20) and the instruction starting at that address in the program memory to be the next instruction executed.
The user is advised to use labels for conditional jumps. The relative jump will be calculated by the assembler. The jump must be in the range -126 to +129.
Addressing Modes : Bit Test
29/45
ST6 INSTRUCTION SET
JRS
Jump Relative if Set
JRS
Mnemonic : JRS
Function : Jump Relative if set
Description :
Operation :
This instruction causes a specified bit in a given dataspace register to be tested.
If this bit is set (=1) then the PC value will be changed and a relative jump will be performed within the program. The relative jump range is -126 to +129. If the tested bit is not set then the next instruction is executed.
If bit=1, PC !
PC + ee where ee= 8-bit displacement
Instruction Format
JRS b,rr,ee
Opcode (Hex) b10011 rr ee
Notes : b.
3-bit address rr.
1 Byte dataspace address ee.
8-bit displacement in the range -126 to +129
*.
∆
.
Z is not affected
The tested bit is shifted into carry.
Bytes
3
Cycles
5
Z
*
Flags
C
∆
Example : If bit 7 of dataspace register AFh is set and the PC=123 then the instruction,
JRS 7,AFh,$+25 will cause the PC to be changed to 148 (123+25) and the instruction starting at that address in the program memory to be the next instruction executed.
The user is advised to use labels for conditional jumps. The relative jump will be calculated by the assembler. The jump must be in the range -126 to +129.
Addressing Modes : Bit Test
30/45
JRZ
Mnemonic :
Function :
Description :
Operation :
ST6 INSTRUCTION SET
Jump Relative on Zero Flag
JRZ
JRZ
Jump Relative on Zero Flag
This instruction causes the zero (Z) flag to be tested and if this flag is set to one then a jump is performed within the program memory. This jump is in the range
-15 to +16 and is relative to the PC value. The displacement is of five bits. If Z=0 then next instruction is executed.
If Z=1, PC !
PC + e where e= 5-bit displacement
Instruction Format
JRZ e
Opcode (Hex) e100
Notes : e.
5-bit displacement in the range -15 to +16.
*.
C,Z not affected
Bytes
1
Cycles
2
Z
*
Flags
C
*
Example : If the zero flag is set then the instruction,
JRZ $+8 will cause a branch forward to PC+8. The user can use labels as identifiers and the assembler will automatically allow the jump if it is in the range -15 to +16.
Addressing Modes : Program Counter Relative
31/45
ST6 INSTRUCTION SET
LD
Load
LD
Mnemonic : LD
Function : Load
Description : The contents of the source register are loaded into the destination register. The source register remains unaltered and the previous contents of the destination register are lost.
Operation : dst
Either the source or the destination must be the accumulator.
Instruction Format
LD dst,src
LD A,X
LD A,Y
LD A,V
LD A,W
LD X,A
LD Y,A
LD V,A
LD W,A
LD A,(X)
LD (X), A
LD A,(Y)
LD (Y),A
LD A,rr
LD rr,A
Opcode (Hex)
BD
FD
07
87
0F
8F
1F rr
9F rr
35
75
B5
F5
3D
7D rr.
*.
∆
.
Notes :
1 Byte dataspace address
C not affected
Z is set if the result is zero. Cleared otherwise.
Bytes
1
2
2
1
1
1
1
1
1
1
1
1
1
1
Cycles
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
Flags
*
*
*
*
*
*
*
*
*
*
*
*
C
*
*
Example : If data space register 34h contains the value 45h then the instruction;
LD A,34h will cause the accumulator to be loaded with the value 45h. Register 34h will keep the value 45h.
Addressing Modes : Source: Direct, Short Direct, Indirect
Destination: Direct, Short Direct, Indirect
32/45
ST6 INSTRUCTION SET
LDI
Load Immediate
LDI
Mnemonic : LDI
Function : Load
Description : The immediately addressed data (source) is loaded into the destination data space register.
Operation : dst
The source is always an immediate data while the destination can be the accumulator, one of the X,Y,V,W registers or one of the available data space registers.
Instruction Format
LDI dst,src
LDI A,nn
LDI X,nn
LDI Y,nn
LDI V,nn
LDI W,nn
LDI rr,nn
Opcode (Hex)
17 nn
0D 80 nn
0D 81 nn
0D 82 nn
0D 83 nn
0D rr nn
Notes : rr.
1 Byte dataspace address nn.
1 Byte immediate value
*.
∆
.
Z, C not affected
Z is set if the result is zero. Cleared otherwise.
Bytes
3
3
3
3
2
3
Cycles
4
4
4
4
4
4
Z
∆
*
*
*
*
*
Flags
Example : The
LDI 34h, 45h will cause the value 45h to be loaded into data register at location 34h.
Addressing Modes : Source: Immediate
Destination: Direct
C
*
*
*
*
*
*
33/45
ST6 INSTRUCTION SET
NOP
No Operation
NOP
Mnemonic : NOP
Function : No Operation
Description : No action is performed by this instruction. It is typically used for timing delay.
Operation : No
Instruction Format
NOP
Note :
*. C,Z not affected
Opcode (Hex)
04
Addressing Modes : Program Counter Relative
Bytes
1
Cycles
2
Z
*
Flags
C
*
34/45
ST6 INSTRUCTION SET
RES
Reset Bit
RES
Mnemonic : RES
Function : Reset
Description :
Operation :
The RESET instruction is used to reset a specified bit in a given register in the dataspace.
dst (n) 0, 0
≤
n
≤
7
Instruction Format
RES bit,dst
RES b,A
RES b,rr
Notes : b.
3-bit address rr.
*.
1 Byte dataspace address
C,Z not affected
Opcode (Hex) b01011 FF b01011 rr
Bytes
2
2
Cycles
4
4
Z
*
*
Flags
Example : If register 23h of the dataspace contains 11111111 then the instruction,
RES 4,23h will cause register 23h to hold 11101111.
Addressing Modes : Bit Direct
C
*
*
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ST6 INSTRUCTION SET
RET
Return from Subroutine
RET
Mnemonic : RET
Function : Return From Subroutine
Description : This instruction is normally used at the end of a subroutine to return to the previously executed procedure. The previously stacked program counter
(stacked during CALL) is popped back from the stack. The next statement executed is that addressed by the new contents of the PC. If the stack had already reached its highest level (no more PC stacked) before the RET is executed, program execution will be continued at the next instruction after the RET.
Operation : PC
Instruction Format
RET
Note :
*. C,Z not affected
Opcode (Hex)
CD
Bytes
1
Cycles
2
Z
*
Flags
C
*
Example : If the current PC value is 456h and the PC value at the top of the stack is 3DFh then the instruction,
RET will cause the PC value 456h to be lost and the current PC value to be 3DFh.
Addressing Modes : Inherent
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ST6 INSTRUCTION SET
RETI
Return from Interrupt
RETI
Mnemonic : RETI
Function Interrupt
Description :
Operation :
This instruction marks the end of the interrupt service routine and returns the
ST60/62/63 to the state it was in before the interrupt. It "pops" the top (last in) PC value from the stack into the current PC. This instruction also causes the ST60/
62/63 to switch from the interrupt flags to the normal flags. The RETI instruction also applies to the end of NMI routine for ST62/63 devices; in this case the instruction causes the switch from NMI flags to normal flags (if NMI was acknowledged inside a normal routine) or to standard interrupt flags (if NMI was acknowledged inside a standard interrupt service routine).
In addition the RETI instruction also clears the interrupt mask (also NMI mask for
ST62/63) which was set when the interrupt occurred. If the stack had already reached its highest level (no more PC stacked) before the RETI is executed, program execution will be continued with the next instruction after the RETI.
Because the ST60 is in interrupt mode after reset (NMI mode for ST62/63), RETI has to be executed to switch to normal flags and enable interrupts at the end of the starting routine. If no call was executed during the starting routine, program execution will continue with the instruction after the RETI (supposed no interrupt is active).
Actual Flags Normal Flags (1)
PC !
Stacked PC
IM !
0
(1) Standard Interrupt flags if NMI was acknowledged inside a standard interrupt service (ST62/63 only).
Instruction Format
RETI
Opcode (Hex)
4D
Note :
∆
C,Z normal flag will be used from now on.
Bytes
1
Cycles
2
Z
∆
Flags
C
∆
Example : If the current PC value is 456h and the PC value at the top of the stack is 3DFh then the instruction
RETI will cause the value 456h to be lost and the current PC value to be 3DFh. The ST6 will switch from interrupt flags to normal flags and the interrupt mask is cleared.
Addressing Modes : Inherent
37/45
ST6 INSTRUCTION SET
RLC
Rotate Left Through Carry
RLC
Mnemonic : RLC
Function : Rotate Left through Carry
Description : This instruction moves each bit in the accumulator one place to the left (i.e.
towards the MSBit. The MSBit (bit 7) is moved into the carry flag and the carry
00000000000000 flag is moved into the LSBit (bit0) of the accumulator.
Operation : dst(0) !
C
C !
dst(7) dst(n+1) !
dst(n), 0
≤
n
≤
6
This instruction can only be performed on the accumulator.
Instruction Format
RLC A
Opcode (Hex)
AD
Bytes
1
Note :
∆
: Z is set if the result is zero. Cleared otherwise.
C will contain the value of the MSB before the operation.
Cycles
4
Z
∆
Flags
C
∆
Example : If the accumulator contains the binary value 10001001 and the carry flag is set to
0 then the instruction,
RLC A will cause the accumulator to have the binary value 00010010 and the carry flag to be set to 1.
Addressing Modes : Inherent
38/45
ST6 INSTRUCTION SET
SET
Set Bit
SET
Mnemonic : SET
Function : Set
Description : The SET instruction is used to set a specified bit in a given register in the data space.
Operation !
1, 0
≤
n
≤
7
Notes :
Instruction Format
SET bit,dst
SET b,A
SET b,rr
Opcode (Hex) b11011 FF b11011 rr
Bytes
2
2
Cycles
4
4
Z
*
*
Flags
C
*
* rr. 1 Byte dataspace address
*. C,Z not affected
Example : If register 23h of the dataspace contains 00000000 then the instruction,
SET 4,23h will cause register 23h to hold 00010000.
Addressing Modes : Bit Direct
39/45
ST6 INSTRUCTION SET
SLA
Shift Left Accumulator
SLA
Mnemonic : SLA
Function : Shift Left Accumulator
Description : This instruction implements an addition of the accumulator to itself (i.e a doubling of the accumulator) causing an arithmetic left shift of the value in the register.
Operation : ADD
This instruction can only be performed on the accumulator.
Instruction Format
SLA A
Opcode (Hex)
5F FF
Bytes
2
Note :
∆
: Z is set if the result is zero. Cleared otherwise.
C will contain the value of the MSB before the operation.
Cycles
4
Z
∆
Flags
C
∆
Example : If the accumulator contains the binary value 11001101 then the instruction,
SLA A will cause the accumulator to have the binary value 10011010 and the carry flag to be set to 1.
Addressing Modes : Inherent
40/45
ST6 INSTRUCTION SET
STOP
Stop Operation
STOP
Mnemonic : STOP
Function : Stop
Description : This instruction is used for putting the ST60/62/63 into a stand-by mode in which the power consumption is reduced to a minimum. All the on-chip peripherals and oscillator are stopped (for some peripherals, A/D for example, it is necessary to individually turn-off the macrocell before entering the STOP instruction). To restart the processor an external interrupt or a reset is needed.
Operation : Stop
Instruction Format
STOP
Note :
*: C,Z not affected
Addressing Mode : Inherent
Opcode (Hex)
6D
Bytes
1
Cycles
2
Z
*
Flags
C
*
41/45
ST6 INSTRUCTION SET
SUB
Subtraction
Mnemonic : SUB
Function : Subtraction
Description : This instruction subtracts the source value from the destination value.
Operation : dst
The destination must be the accumulator.
SUB
Instruction Format
SUB dst,src
SUB A,A
SUB A,X
SUB A,Y
SUB A,V
SUB A,W
SUB A,(X)
SUB A,(Y)
SUB A,rr
Note : rr.
1 Byte dataspace address
Opcode (Hex)
DF FF
DF 80
DF 81
DF 82
DF 83
C7
CF
DF rr
Bytes
2
1
2
2
2
2
1
2
Cycles
4
4
4
4
4
4
4
4
Z
∆
∆
∆
∆
∆
∆
∆
∆
Flags
ST60
ST62/63
Example :
∆
: Z is set if the result is zero. Cleared otherwise.
C is set if Acc
≥
src, cleared if Acc < src.
∆
: Z is set if the result is zero. Cleared otherwise.
C is set if Acc < src, cleared if Acc
≥
src.
If the Y register contains the value 23h, dataspace register 23h contains the value
53h and the accumulator contains the value 78h then the instruction,
SUB A,(Y) will cause the accumulator to hold the value 25h (i.e. 78-53). The zero flag is cleared and the carry flag is set (on ST60), indicating that result is > 0.
Addressing Modes : Source: Indirect,Direct
Destination: Accumulator
∆
∆
∆
∆
∆
∆
C
∆
∆
42/45
ST6 INSTRUCTION SET
SUBI
Subtraction Immediate
SUBI
Mnemonic : SUBI
Function : Subtraction
Description : This instruction causes the immediately addressed source data to be subtracted from the accumulator.
Operation : dst
The destination must be the accumulator.
Instruction Format
SUBI dst,src
SUBI A,nn
Note : nn.
1 Byte of immediate data
Opcode (Hex)
D7 nn
Bytes
2
Cycles
4
Z
∆
Flags
C
∆
ST60
ST62/63
Example :
∆
: Z is set if the result is zero. Cleared otherwise.
C is set if Acc
≥
src, cleared if Acc < src.
∆
: Z is set if the result is zero. Cleared otherwise.
C is set if Acc < src, cleared if Acc
≥
src.
If the accumulator contains the value 56h then the instruction,
SUBI A,25 will cause the accumulator to contain the value 31h. The zero flag is cleared and the carry flag is set (on ST60), indicating that the result is > 0.
Addressing Modes : Source: Immediate
Destination: Accumulator
43/45
ST6 INSTRUCTION SET
WAIT
Wait Processor
WAIT
Mnemonic : WAIT
Function : Wait
Description :
Operation :
This instruction is used for putting the ST60/62/63 into a stand-by mode in which the power consumption is reduced to a minimum. Instruction execution is stopped, but the oscillator and some on-chip peripherals continue to work. To restart the processor an interrupt from an active on-chip peripheral (e.g. timer), an external interrupt or reset is needed. For on-chip peripherals active during wait, see ST60/62/63 data sheets.
Put ST6 in stand-by mode
Instruction Format
WAIT
Note :
*.
C,Z not affected
Addressing Modes : Inherent
Opcode (Hex)
ED
Bytes
1
Cycles
2
Z
*
Flags
C
*
44/45
Notes
ST6 INSTRUCTION SET
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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