STMicroelectronics 16-bit MCU Datasheet
Reklam
Reklam
ST10F271B
ST10F271E
16-bit MCU with 128 Kbyte Flash memory and 8/12 Kbyte RAM
Features
■ 16-bit CPU with DSP functions
– 31.25ns instruction cycle time at 64MHz max CPU clock
– Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator
– Enhanced boolean bit manipulations
– Single-cycle context switching support
PQFP144 (28 x 28 x 3.4mm)
(Plastic Quad Flat Package)
TQFP144 (20 x 20 x 1.4mm)
(Thin Quad Flat Package)
■ On-chip memories
■ A/D converter
– 256 Kbyte Flash memory (32-bit fetch)
– Single voltage Flash memories with erase/program controller and 100K erasing/programming cycles.
■
– 24-channel 10-bit
– 3 µ s minimum conversion time
Serial channels
– Two synch. / asynch. serial channels – Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I
2
C)
– 2 Kbyte internal RAM (IRAM)
– Two high-speed synchronous channels
– One I
2
C standard interface
– 10/18 Kbyte extension RAM (XRAM)
■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN busses (64 or 2x32 message, C-CAN version) – Programmable external bus configuration & characteristics for different address ranges
■ Fail-safe protection
– Five programmable chip-select signals
– Programmable watchdog timer
– Hold-acknowledge bus arbitration support
– Oscillator watchdog
■ Interrupt
– 8-channel peripheral event controller for single cycle interrupt driven data transfer
■
■
On-chip bootstrap loader
Clock generation
– 16-priority-level interrupt system with 56 sources, sampling rate down to 15.6ns
– On-chip PLL with 4 to 8 MHz oscillator
– Direct or prescaled clock input
Timers
■ Real time clock and 32 kHz on-chip oscillator
■
■ Up to 111 general purpose I/O lines – Two multi-functional general purpose timer
■ units with 5 timers – Individually programmable as input, output or special function
■ 4-channel PWM unit + 4-channel XPWM
■
– Programmable threshold (hysteresis)
Obsolete Product(s) - Obsolete Product(s)
■ Single voltage supply: 5V ±10%
July 2006 Rev 1 1/180 www.st.com
1
ST10F271B/ST10F271E Contents
Contents
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
Flash non volatile write protection I register . . . . . . . . . . . . . . . . . . . . . 37
Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 38
Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 38
. . . . . . . . . . . . . . . Flash non volatile access protection register 1 high 39
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ST10F271B/ST10F271E Contents
XBus flash volatile temporary access unprotection register (XFVTAUR0) .
Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Selection among user-code, standard or selective bootstrap . . . . . . . . . . 45
Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Alternate and selective boot mode (ABM and SBM) . . . . . . . . . . . . . . . . 46
Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10 Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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Contents ST10F271B/ST10F271E
Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 70
ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 72
Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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ST10F271B/ST10F271E
Contents
Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Real time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Obsolete Product(s) - Obsolete Product(s)
Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
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Contents ST10F271B/ST10F271E
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 173
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
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List of tables ST10F271B/ST10F271E
List of tables
(Write operations or with ROMS1=’1’ or BootStrap mode)27
CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 59
CAPCOM timer input frequencies, resolutions and periods at 64 MHz . . . . . . . . . . . . . . . 59
Obsolete Product(s) - Obsolete Product(s)
ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 70
Obsolete Product(s) - Obsolete Product(s)
ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 71
ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 72
SSC synchronous baud rate and reload values (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . 73
SSC synchronous baud rate and reload values (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . 73
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List of tables ST10F271B/ST10F271E
= 5V ± 10%, V
SS
= 0V, T
A
= –40 to +125°C) . . . . . . . . . . . . . . 153
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List of figures ST10F271B/ST10F271E
List of figures
ST10F271 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value). . . . . 25
SW / WDT bidirectional RESET (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . . 98
Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 134
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
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List of figures ST10F271B/ST10F271E
External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE. . . . 159
External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. . 160
External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 161
External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS . 162
External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 165
Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE . . . . . . 166
External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS . . . . 167
External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 168
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
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ST10F271B/ST10F271E
1 Introduction
Introduction
The ST10F271B and ST10F271E devices are derivatives of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers.
These two derivatives slightly differ on the available RAM size and Analog Channel Input number. These points will be highlighted in the corresponding chapters.
For all information that is common to the 2 derivatives, the generic ST10F271 name will be used.
The ST10F271 combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL.
The ST10F271 is processed in 0.18mm CMOS technology. The MCU core and the logic is supplied with a 5V to 1.8V on-chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V.
The ST10F271 devices are based on the ST10F272 silicon, and 100% compatible, with the difference that only a reduced portion of the on-chip Flash and RAM memories are usable.
The available memories will be detailled in the
Chapter 4: Memory organization
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Introduction
Figure 1.
Logic symbol
XTAL1
XTAL2
XTAL3
XTAL4
RSTIN
RSTOUT
V
AREF
V
AGND
NMI
EA / V
STBY
READY
ALE
RD
WR / WRL
Port 5
16-bit
V
18
V
DD
V
SS
ST10F271
Port 0
16-bit
Port 1
16-bit
Port 2
16-bit
Port 3
15-bit
Port 4
8-bit
Port 6
8-bit
Port 7
8-bit
Port 8
8-bit
RPD
ST10F271B/ST10F271E
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Obsolete Product(s) - Obsolete Product(s)
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ST10F271B/ST10F271E
Figure 2.
Pin configuration (top view)
Pin data
P6.0 / CS0
P6.1 / CS1
P6.2 / CS2
P6.3 / CS3
P6.4 / CS4
P6.5 / HOLD / SCLK1
P6.6 / HLDA / MTSR1
P6.7 / BREQ / MRST1
P8.0 / XPOUT0 / CC16IO
P8.1 / XPOUT1 / CC17IO
P8.2 / XPOUT2 / CC18IO
P8.3 / XPOUT3 / CC19IO
P8.4 / CC20IO
P8.5 / CC21IO
P8.6 / RxD1 / CC22IO
P8.7 / TxD1 / CC23IO
VDD
VSS
P7.0 / POUT0
P7.1 / POUT1
P7.2 / POUT2
P7.3 / POUT3
P7.4 / CC28IO
P7.5 / CC29IO
P7.6 / CC30IO
P7.7 / CC31IO
P5.0 / AN0
P5.1 / AN1
P5.2 / AN2
P5.3 / AN3
P5.4 / AN4
P5.5 / AN5
P5.6 / AN6
P5.7 / AN7
P5.8 / AN8
P5.9 / AN9
26
27
28
29
30
21
22
23
24
25
31
32
33
34
35
36
16
17
18
19
20
11
12
13
14
15
6
7
8
9
10
1
2
3
4
5
ST10F271
83
82
81
80
79
88
87
86
85
84
78
77
76
75
74
73
93
92
91
90
89
98
97
96
95
94
108
107
106
105
104
103
102
101
100
99
P0H.0 / AD8
P0L.7 / AD7
P0L.6 / AD6
P0L.5 / AD5
P0L.4 / AD4
P0L.3 / AD3
P0L.2 / AD2
P0L.1 / AD1
P0L.0 / AD0
EA / VSTBY
ALE
READY
WR/WRL
RD
VSS
VDD
P4.7 / A23 / CAN2_TxD / SDA
P4.6 / A22 / CAN1_TxD / CAN2_TxD
P4.5 / A21 / CAN1_RxD / CAN2_RxD
P4.4 / A20 / CAN2_RxD / SCL
P4.3 / A19
P4.2 / A18
P4.1 / A17
P4.0 / A16
RPD
VSS
VDD
P3.15 / CLKOUT
P3.13 / SCLK0
P3.12 / BHE / WRH
P3.11 / RxD0
P3.10 / TxD0
P3.9 / MTSR0
P3.8 / MRST0
P3.7 / T2IN
P3.6 / T3IN
*: AN16 to AN23 are only available for the ST10F271E
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
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Pin data ST10F271B/ST10F271E
Table 1.
Symbol
Pin description
Pin Type Function
P6.0 - P6.7
P8.0 - P8.7
1 - 8
1
I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The following Port 6 pins have alternate functions:
O P6.0
CS0 Chip select 0 output
...
5
...
...
O P6.4
I P6.5
...
CS4
HOLD
...
Chip select 4 output
External master hold request input
6
7
I/O
O P6.6
I/O
SCLK1
HLDA
MTSR1
SSC1: master clock output / slave clock input
Hold acknowledge output
SSC1: master-transmitter / slave-receiver O/I
8
9-16
9
...
12
O P6.7
I/O
I/O
BREQ
MRST1
Bus request output
SSC1: master-receiver / slave-transmitter I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS).
The following Port 8 pins have alternate functions:
I/O P8.0
O
CC16IO
XPWM0
CAPCOM2: CC16 capture input / compare output
PWM1: channel 0 output
...
...
I/O P8.3
O
...
CC19IO
XPWM0
...
CAPCOM2: CC19 capture input / compare output
PWM1: channel 3 output
13
14
I/O P8.4
I/O P8.5
I/O P8.6
CC20IO
CC21IO
CC22IO
CAPCOM2: CC20 capture input / compare output
CAPCOM2: CC21 capture input / compare output
CAPCOM2: CC22 capture input / compare output
15
I/O RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous)
I/O P8.7
CC23IO CAPCOM2: CC23 capture input / compare output
16
O TxD1
ASC1: Clock / Data output
Obsolete Product(s) - Obsolete Product(s)
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ST10F271B/ST10F271E Pin data
Table 1.
Symbol
Pin description (continued)
Pin Type Function
P7.0 - P7.7
P5.0 - P5.9
P5.10 - P5.15
19-26
42
43
44
39
40
41
19
...
22
23
...
26
27-36
39-44
47-54
57-64
I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS).
The following Port 7 pins have alternate functions:
O P7.0
...
...
POUT0
...
PWM0: channel 0 output
...
O P7.3
I/O P7.4
...
...
POUT3
CC28IO
...
PWM0: channel 3 output
CAPCOM2: CC28 capture input / compare output
...
I/O P7.7
I
I
CC31IO CAPCOM2: CC31 capture input / compare output
16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be the analog input channels (up to 16) for the A/D converter, where P5.x equals
ANx (Analog input channel x), or they are timer inputs. The input threshold of
Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate functions:
I P5.10
T6EUD
I P5.11
T5EUD
I P5.12
T6IN
I P5.13
T5IN
I P5.14
T4EUD
GPT2: timer T6 external up/down control input
GPT2: timer T5 external up/down control input
GPT2: timer T6 count input
GPT2: timer T5 count input
GPT1: timer T4 external up/down control input
I P5.15
T2EUD
I/O
GPT1: timer T2 external up/down control input
16-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS).
The following Port 2 pins have alternate functions:
I/O P2.0
CC0IO CAPCOM: CC0 capture input/compare output 47
...
...
...
...
...
P2.0 - P2.7
54 I/O P2.7
CC7IO CAPCOM: CC7 capture input/compare output
P2.8 - P2.15
I/O P2.8
CC8IO CAPCOM: CC8 capture input/compare output
57
I EX0IN Fast external interrupt 0 input Obsolete Product(s) - Obsolete Product(s)
...
...
...
...
...
I/O P2.15
CC15IO CAPCOM: CC15 capture input/compare output Obsolete Product(s) - Obsolete Product(s)
64 I EX7IN Fast external interrupt 7 input
I T7IN CAPCOM2: timer T7 count input
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Pin data ST10F271B/ST10F271E
Table 1.
Symbol
P3.0 - P3.5
P3.6 - P3.13,
P3.15
Pin description (continued)
Pin
65-70,
73-80,
81
70
73
74
75
76
65
66
67
68
69
77
78
79
80
81
Type Function
I/O
I/O
I/O
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as pushpull or open drain drivers. The input threshold of Port 3 is selectable (TTL or
CMOS). The following Port 3 pins have alternate functions:
I P3.0
O P3.1
T0IN
T6OUT
CAPCOM1: timer T0 count input
GPT2: timer T6 toggle latch output
I P3.2
O P3.3
I P3.4
I P3.5
I P3.6
I P3.7
CAPIN
T3OUT
T3EUD
T4IN
T3IN
T2IN
GPT2: register CAPREL capture input
GPT1: timer T3 toggle latch output
GPT1: timer T3 external up/down control input
GPT1; timer T4 input for count/gate/reload/capture
GPT1: timer T3 count/gate input
GPT1: timer T2 input for count/gate/reload / capture
I/O P3.8
I/O P3.9
MRST0
MTSR0
O P3.10
TxD0
I/O P3.11
RxD0
BHE
O P3.12
WRH
I/O P3.13
SCLK0
O P3.15
CLKOUT
SSC0: master-receiver/slave-transmitter I/O
SSC0: master-transmitter/slave-receiver O/I
ASC0: clock / data output (asynchronous/synchronous)
ASC0: data input (asynchronous) or I/O (synchronous)
External memory high byte enable signal
External memory high byte write strobe
SSC0: master clock output / slave clock input
System clock output (programmable divider on CPU clock)
Obsolete Product(s) - Obsolete Product(s)
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ST10F271B/ST10F271E Pin data
Table 1.
Symbol
Pin description (continued)
Pin Type Function
P4.0 –P4.7
RD
85-92
85
86
87
88
89
90
91
92
95
I
O
O
O
O
I/O
O
I
I/O
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold is selectable (TTL or
CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open drain drivers.
In case of an external bus configuration, Port 4 can be used to output the segment address lines:
O P4.0
O P4.1
O P4.2
A16
A17
A18
Segment address line
Segment address line
Segment address line
O P4.3
O
I P4.4
A19
A20
CAN2_RxD
SCL
A21
Segment address line
Segment address line
CAN2: receive data input
I
2
C Interface: serial clock
Segment address line
P4.5
P4.6
CAN1_RxD
CAN2_RxD
A22
CAN1_TxD
CAN1: receive data input
CAN2: receive data input
Segment address line
CAN1: transmit data output
O
I/O
O
CAN2_TxD
A23
CAN2: transmit data output
Most significant segment address line
P4.7
CAN2_TxD
SDA
CAN2: transmit data output
I
2
C Interface: serial data
External memory read strobe. RD is activated for every external instruction or data read access.
WR/WRL 96 O
External memory write strobe. In WR-mode this pin is activated for every external data write access. In WRL mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See
WRCFG in the SYSCON register for mode selection.
Ready input. The active level is programmable. When the ready function is
READY/ enabled, the selected inactive level at this pin, during an external memory
READY
97 I access, will force the insertion of waitstate cycles until the pin returns to the Obsolete Product(s) - Obsolete Product(s)
ALE 98 O
Address latch enable output. In case of use of external addressing or of Obsolete Product(s) - Obsolete Product(s)
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Pin data ST10F271B/ST10F271E
Table 1.
Symbol
EA / V
STBY
Pin description (continued)
Pin
99
P0L.0 -P0L.7,
P0H.0
P0H.1 -
P0H.7
100-107,
108,
111-117
Type
I
I/O
Function
External access enable pin.
A low level applied to this pin during and after Reset forces the ST10F271 to start the program from the external memory space. A high level forces ST10F271 to start in the internal memory space. This pin is also used (when Stand-by mode is entered, that is ST10F271 under reset and main V
DD
turned off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference voltage for the lowpower embedded voltage regulator which generates the internal 1.8V supply for the RTC module (when not disabled) and to retain data inside the Stand-by portion of the XRAM (16Kbyte).
It can range from 4.5 to 5.5V (6V for a reduced amount of time during the device life, 4.0V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In running mode, this pin can be tied low during reset without affecting 32 kHz oscillator, RTC and XRAM activities, since the presence of a stable V
DD guarantees the proper biasing of all those modules.
Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold of Port 0 is selectable
(TTL or CMOS).
In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes
Data path width 8-bit 16-bi
P0L.0 – P0L.7:
P0H.0 – P0H.7:
D0 – D7
I/O
D0 - D7
D8 - D15
Multiplexed bus modes
Data path width 8-bit
P0L.0 – P0L.7:
P0H.0 – P0H.7:
AD0 – AD7
A 8 – A15
16-bi
AD0 - AD7
A D8 - AD15
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ST10F271B/ST10F271E Pin data
Table 1.
Symbol
Pin description (continued)
Pin Type Function
P1L.0 - P1L.7
P1H.0 -
P1H.7
XTAL1
XTAL2
XTAL3
XTAL4
RSTIN
118-125
128-135
132
133
134
135
138
137
143
144
140
I/O
Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16-bit address bus
(A) in demultiplexed bus modes: if at least BUSCONx is configured such the demultiplexed mode is selected, the pis of PORT1 are not available for general purpose I/O function. The input threshold of Port 1 is selectable (TTL or CMOS).
Only for the ST10F271E
– The pins of P1L also serve as the additional (up to 8) analog input channels for the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x + 16). This additional function have higher priority on demultiplexed bus function.
The following PORT1 pins have alternate functions:
I P1H.4
CC24IO CAPCOM2: CC24 capture input
I P1H.5
CC25IO
I P1H.6
CC26IO
I P1H.7
CC27IO
CAPCOM2: CC25 capture input
CAPCOM2: CC26 capture input
CAPCOM2: CC27 capture input
I XTAL1 Main oscillator amplifier circuit and/or external clock input.
O XTAL2 Main oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed.
I
I XTAL3 32 kHz oscillator amplifier circuit input
O XTAL4 32 kHz oscillator amplifier circuit output
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,
XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32 in RTCCON register shall be set. 32 kHz oscillator can only be driven by an external crystal, and not by a different clock source.
Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F271. An internal pull-up resistor permits power-on reset using only a capacitor connected to V
SS
. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence.
Internal Reset Indication Output. This pin is driven to a low level during hardware,
RSTOUT 141 O software or watchdog timer reset. RSTOUT remains low until the EINIT (end of Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
NMI 142 I
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F271 to go into power down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
V
AREF
V
AGND
37
38
A/D converter reference voltage and analog supply
A/D converter reference and analog ground
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Pin data ST10F271B/ST10F271E
Table 1.
Symbol
RPD
Pin description (continued)
Pin
84
Type
-
Function
Timing pin for the return from interruptible power down mode and synchronous / asynchronous reset selection.
V
DD
V
SS
17, 46,
72,82,93
, 109,
126, 136
18,45,
55,71,
83,94,
110,
127, 139
-
Digital supply voltage = + 5V during normal operation, idle and power down modes.
It can be turned off when Stand-by RAM mode is selected.
Digital ground
V
18
56 -
1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF) must be connected between this pin and nearest V
SS
pin.
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ST10F271B/ST10F271E Functional description
The architecture of the ST10F271 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the
ST10F271.
Figure 3.
Block diagram
IFLASH
128K
32
CPU-Core and MAC Unit
16
16
IRAM
2K
XRAM
2K
(PEC)
16
XRAM
4K/8K
(STBY)
16
16
XRTC
16
16
16 16
XI2C
16 16
XCAN1
XPWM
XASC
XSSC
XCAN2
16
16
Interrupt Controller
PEC
Watchdog
4-8MHz
Oscillator
32kHz
Oscillator
PLL
5V-1.8V
Voltage
Regulator
16
16
8
16
Port 6
8
Port 5
16
BRG BRG
Port 3
15
Port 7
8
Port 8
8
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Memory organization ST10F271B/ST10F271E
The memory space of the ST10F271 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Bytes. The entire memory space can be accessed Byte wise or Word wise.
Particular portions of the on-chip memory have additionally been made directly bit addressable.
IFLASH : 128K Bytes of on-chip Flash memory. It is divided in 6blocks (B0F0...B0F5) that constitute the Bank 0. When Bootstrap mode is selected, the Test-Flash Block B0TF
(8Kbyte) appears at address 00’0000h: refer to
Chapter 5: Internal Flash memory on page 26
for more details on memory mapping in boot mode. The summary of address range
for IFlash is the following:
Table 2.
Summary of IFLASH address range
Blocks User Mode
B0TF
B0F0
B0F1
B0F2
B0F3
B0F4
B0F5
B0F6
(1)
B0F7
(1)
Not visible
00’0000h - 00’1FFFh
00’2000h - 00’3FFFh
00’4000h - 00’5FFFh
00’6000h - 00’7FFFh
01’8000h - 01’FFFFh
02’0000h - 02’FFFFh
03’0000h - 03’FFFFh / RESERVED
04’0000h - 04’FFFFh / RESERVED
Size
8K
8K
8K
8K
8K
32K
64K
64K
64K
Note:
(1)
: The ST10F271 being based on the same silicon as the ST10F272, 256 KByte of Flash are implemented on the device. The blocks B0F6 and B0F7 are not physically disabled but
MUST be considered as reserved by the application software.
IRAM : 2K Bytes of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0 to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.
XRAM : 4K/8K+2K Bytes of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code.
The XRAM is divided into 2 areas, the first 2K Bytes named XRAM1 and the second 4K/8K
Obsolete Product(s) - Obsolete Product(s) memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (31.25ns access at 64MHz CPU clock). Byte and Word accesses are allowed.
Obsolete Product(s) - Obsolete Product(s)
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register), and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then any access in the address range 00’E000h - 00’E7FFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register.
The XRAM2 address range is the one selected programming XADRS3 register, if XPEN (bit
2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is
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ST10F271B/ST10F271E Memory organization cleared, then any access in the address range programmed for XRAM2 will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register.
After reset the XRAM2 is mapped from address 09’0000h.
XRAM2 represents also the Stand-by RAM, which can be maintained biased through EA /
V
STBY
pin when main supply VDD is turned off.
As the XRAM appears like external memory, it cannot be used as system stack or as register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable.
ST10F271B XRAM: 4K+2K Bytes of XRAM.
The XRAM1 (2K Bytes) address range is 00’E000h - 00’E7FFh if enabled.
The XRAM2 (4K Bytes) address range is after reset 09’0000h - 09’1FFFh and is mirrored every 16KByte boundary.
ST10F271E XRAM: 8K+2K Bytes of XRAM
The XRAM1 (2K Bytes) address range is 00’E000h - 00’E7FFh if enabled.
The XRAM2 (16K Bytes) address range is after reset 09’0000h - 09’3FFFh and is mirrored every 16KByte boundary.
SFR/ESFR: 1024 Bytes (2 x 512 Bytes) of address space is reserved for the special function register areas. SFRs are Wordwide registers which are used to control and to monitor the function of the different on-chip units.
CAN1 : Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access. The
CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit
0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 62.5ns at 64MHz CPU clock. No tri-state wait states are used.
CAN2 : Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. The
CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit
1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 62.5ns at 64MHz CPU clock. No tri-state wait states are used.
Note: If one or the two CAN modules are used, Port 4 cannot be programmed to output all 8 segment address lines. Thus, only 4 segment address lines can be used, reducing the external memory space to 5M Bytes (1M Byte per CS line).
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RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus Obsolete Product(s) - Obsolete Product(s)
CPU clock. No tristate waitstate is used.
PWM1 : Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 Module access.
The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the
XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16bit data bus (only word accesses are possible). Two waitstates give an access time of
62.5ns at 64MHz CPU clock. No tristate waitstate is used. Only word access is allowed.
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Memory organization ST10F271B/ST10F271E
ASC1 : Address range 00’E900h - 00’E9FFh is reserved for the ASC1 Module access. The
ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON register. Accesses to the ASC1 Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64MHz
CPU clock. No tristate waitstate is used.
SSC1 : Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The
SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON register. Accesses to the SSC1 Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz
CPU clock. No tristate waitstate is used.
I2C : Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The I2C is enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register.
Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz CPU clock.
No tristate waitstate is used.
●
●
●
●
●
●
●
●
X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON register and bit 10 of the XPERCON register. Accesses to this additional features use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz CPU clock. No tristate waitstate is used.
The following set of features are provided:
CLKOUT programmable divider
XBUS interrupt management registers
ADC multiplexing on P1L register ( only for ST10F271E
Port1L digital disable register for extra ADC channels
CAN2 multiplexing on P4.5/P4.6
CAN1-2 main clock prescaler
Main Voltage Regulator disable for power-down mode
)
TTL / CMOS threshold selection for Port0, Port1, and Port5.
In order to meet the needs of designs where more memory is required than is provided on chip, up to 16M Bytes of external memory can be connected to the microcontroller.
Visibility of XBUS peripherals
In order to keep the ST10F271 compatible with the ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for
X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the global enabling with XPEN bit in SYSCON register, the corresponding address space, port
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Chapter 23: Register set on page 112
.
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ST10F271B/ST10F271E Memory organization
Figure 4.
Segment
ST10F271 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value)
Page Segment Page RAM / SFR (4Kbyte)
FF FFFF
255
0
00 0000
1023
0
11 FFFF
17 Ext. Memory
11 0000
10 FFFF
16 Ext. Memory
10 0000
0F FFFF
15
0F 0000
0E FFFF
14
0E 0000
0D FFFF
13
0D 0000
0C FFFF
12
0C 0000
0B FFFF
11
0B 0000
0A FFFF
10
0A 0000
09 FFFF
9
09 0000
08 FFFF
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
Reserved 8
08 0000
07 FFFF
7 Reserved
07 0000
06 FFFF
Reserved
6
06 0000
05 FFFF
Reserved
5
05 0000
04 FFFF
4
04 0000
03 FFFF
3
Reserved
Reserved
03 0000
02 FFFF
2
02 0000
01 FFFF
1
01 0000
00 FFFF
0
00 0000
FLASH
FLASH
Ext. Memory
Ext. Memory
FLASH
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
31
30
29
28
27
26
25
35
34
33
32
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
4
3
2
1
6
5
0
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
67
66
65
64
67
00 FFFF
00 FE00
00 FDFF
00 F600
00 F5FF
00 F200
00 F1FF
00 F000
00 EFFF
00 E800
00 E7FF
00 E000
00 DFFF
00 C000
SFR
IRAM
Reserved
ESFR
XCAN1
XCAN2
XRTC
XPWM
XMiscellaneous
XI
2
C
XASC
XSSC
XRAM1
Ext. Memory
512
2K
1K
512
256
256
256
256
256
256
256
256
2K
8K
01 0000
00 FFFF
00 FE00
00 FDFF
00 F600
00 F5FF
00 F200
00 F1FF
00 F000
00 EFFF
SFR
IRAM
Reserved
ESFR
512
2K
1K
512
Address Area, where XRAM2 is mirrored every 16Kbytes boundary after reset
Bit-addressable Memory
16 MB FLASH + XRAM - 1Mbyte Data Page 3 (Segment 0) - 16Kbyte
* The first 32K of FLASH may be remapped from segment 0 to segment 1 by setting SYSCON-ROMS1 (before EINIT).
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Internal Flash memory
5 Internal Flash memory
ST10F271B/ST10F271E
5.1 Overview
The on-chip Flash is composed by one matrix module, 256 KBytes wide.
This module is on ST10 Internal bus, so it is called IFLASH
Figure 5.
Flash structure
IFLASH Control Section
Flash Control
Registers
HV and Ref.
Generator
Bank 0: 128 Kbyte
Program Memory
+
8 Kbyte Test-Flash
Program/Erase
Controller
I-BUS Interface
The programming operations of the flash are managed by an embedded Flash
Program/Erase Controller (FPEC). The High Voltages needed for Program/Erase operations are internally generated.
The Data bus is 32-bit wide for fetch accesses to IFLASH, while it is 16 bit wide for read accesses to IFLASH. Read/write accesses to IFLASH Control Registers area are 16 bit wide.
5.2.1 Structure
The following table shows the Address space reserved to the Flash module.
Table 3.
Address space reserved to the Flash module
IFLASH sectors
Description Addresses
0x00 0000 to 0x02 FFFF
Size
128 Kbyte
IFLASH reserved sector
1)
128 Kbyte 0x03 0000 to 0x04 FFFF Obsolete Product(s) - Obsolete Product(s)
Reserved IBUS area
2)
0x05 0000 to 0x07 FFFF 192 Kbyte
Registers and Flash internal reserved area 0x08 0000 to 0x08 FFFF 64 Kbyte
Note: 1 The ST10F271 being based on the same silicon as the ST10F272, 256 KByte of Flash are implemented on the device. The range 03’0000h - 04’FFFFh is not physically disabled even if not available for use. Therefore this address range MUST be reserved by the application
26/180
ST10F271B/ST10F271E Internal Flash memory
mapping. Accesses to this address range will send back the content of the Flash cell (by default FFFFh, blank value when the device is delivered)
2 Accesses to the area will send back the value 009Bh.
The IFLASH module is composed by a bank (Bank 0) of 256 Kbyte of Program Memory divided in 8 sectors (B0F0...B0F7). Bank 0 contains also a reserved sector named Test-
Flash. The Addresses from 0x08 0000 to 0x08 FFFF are reserved for the Control Register
Interface and other internal service memory space used by the Flash Program/Erase controller.
The following tables show the memory mapping of the Flash when it is accessed in read
Table 4: Flash modules sectorization (Read operations)
), and when accessed in write or erase mode (
Table 5: Flash modules sectorization (Write operations or with
ROMS1=’1’ or BootStrap mode)
): note that with this second mapping, the first four banks are remapped into code segment 1 (same as obtained setting bit ROMS1 in SYSCON register).
Table 4.
Bank
Flash modules sectorization (Read operations)
Description Addresses Size ST10 Bus size
Bank 0 Flash 0 (B0F0) 0x0000 0000 - 0x0000 1FFF 8 KB
Bank 0 Flash 1 (B0F1)
Bank 0 Flash 2 (B0F2)
Bank 0 Flash 3 (B0F3)
0x0000 2000 - 0x0000 3FFF 8 KB
0x0000 4000 - 0x0000 5FFF 8 KB
0x0000 6000 - 0x0000 7FFF 8 KB
B0 32-bit (I-BUS)
Bank 0 Flash 4 (B0F4)
Bank 0 Flash 5 (B0F5)
Bank 0 Flash 6 (B0F6)
Bank 0 Flash 7 (B0F7)
(1)
(1)
0x0001 8000 - 0x0001 FFFF
0x0002 0000 - 0x0002 FFFF
32 KB
64 KB
0x0003 0000 - 0x0003 FFFF 64 KB
0x0004 0000 - 0x0004 FFFF 64 KB
1.
IFlash sectors B0F6 and B0F7 are not physically disabled. The corresponding area must be reserved by the application mapping. Accesses to this area will send back the content of the Flash cell ( by default
FFFFh: the erased state, if not modified by user).
Table 5.
Bank
Flash modules sectorization
(Write operations or with ROMS1=’1’ or BootStrap mode)
Description Addresses Size ST10 Bus size
Bank 0 Test-Flash (B0TF) 0x0000 0000 - 0x0000 1FFF 8 KB
0x0001 0000 - 0x0001 1FFF 8 KB
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B0
Bank 0 Flash 1 (B0F1)
Bank 0 Flash 2 (B0F2)
0x0001 2000 - 0x0001 3FFF 8 KB
0x0001 4000 - 0x0001 5FFF 8 KB
32-bit (I-BUS) Bank 0 Flash 3 (B0F3) 0x0001 6000 - 0x0001 7FFF 8 KB
Bank 0 Flash 4 (B0F4)
Bank 0 Flash 5 (B0F5)
Bank 0 Flash 6 (B0F6)
(1)
Bank 0 Flash 7 (B0F7)
(1)
0x0001 8000 - 0x0001 FFFF 32 KB
0x0002 0000 - 0x0002 FFFF 64 KB
0x0003 0000 - 0x0003 FFFF 64 KB
0x0004 0000 - 0x0004 FFFF 64 KB
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Internal Flash memory ST10F271B/ST10F271E
1.
IFlash sectors B0F6 and B0F7 are not physically disabled. The corresponding area must be reserved by the application mapping. Accesses to this area will send back the content of the Flash cell ( by default
FFFFh: the erased state, if not modified by user).
The table above refers to the configuration when bit ROMS1 of SYSCON register is set.
When Bootstrap mode is entered:
●
●
●
Test-Flash is seen and available for code fetches (address 00’0000h)
User I-Flash is only available for read and write accesses
●
Write accesses must be made with addresses starting in segment 1 from 01'0000h, whatever ROMS1 bit in SYSCON value
Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
In Bootstrap mode, by default ROMS1 = 0, so the first 32KBytes of IFlash are mapped in segment 0.
Example:
In default configuration, to program address 0, user must put the value 01'0000h in the
FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must be performed.
Table 6: Control register interface
shows the Control Register interface composition: this set of registers can be addressed by the CPU.
Table 6.
Control register interface
Name Description Addresses Size
Bus size
FCR1-0
FDR1-0
FAR
FER
FNVWPIR
FNVAPR0
Flash Control Registers 1-0
Flash Data Registers 1-0
0x0008 0000 - 0x0008 0007
0x0008 0008 - 0x0008 000F
8 byte
8 byte
Flash Address Registers
Flash Error Register
Flash Non Volatile Protection I
Register
Flash Non Volatile Access Protection
Register 0
0x0008 0010 - 0x0008 0013 4 byte
0x0008 0014 - 0x0008 0015 2 byte
0x0008 DFB0 - 0x0008
DFB1
0x0008 DFB8 - 0x0008
DFB9
2 byte
2 byte
16-bit
FNVAPR1
Flash Non Volatile Access Protection
Register 1
0x0008 DFBC - 0x0008
DFBF
4 byte
XBus Flash Volatile Temporary
XFVTAUR0 0x0000 EB50 - 0x0000 EB51 2 byte
Access Unprotection Register 0
Obsolete Product(s) - Obsolete Product(s)
Note:
28/180 consumption is drastically reduced, but exiting this state can require a long time (t
PD
).
Recovery time from Power Down mode for the Flash modules is anyway shorter than the main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash, it is important to size properly the external circuit on RPD pin.
PWRDN instruction must not be executed while a Flash program/erase operation is in progress.
ST10F271B/ST10F271E Internal Flash memory
The Flash module have one single register interface mapped in the memory space of the
IBUS (0x08 0000 to 0x08 0015). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit registers are used to store Flash Address and Data for Program operations (FARH/L and
FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible with 8 and 16-bit instructions (since operates in 16-bit mode when in read/ write).
Before accessing the IFlash module (and consequently also the Flash register to be used for program/erasing operations), bit ROMEN in SYSCON register shall be set.
During a Flash write operation any attempt to read the flash itself, that is under modification, will output invalid data (software trap 009Bh). This means that the Flash is not fetchable when a programming operation is active: the write operation commands must be executed from another memory (internal RAM or external memory), as in ST10F269 device. In fact, due to IBUS characteristics, it is not possible to perform a write operation on IFLASH, when fetching code from IFLASH.
Direct addressing is not allowed for write accesses to IFLASH Control Registers.
During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the
Flash Control Registers.
Power supply drop
If during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the module is reset to Read mode. At following Power-on, the interrupted Flash write operation must be repeated.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
29/180
Internal Flash memory ST10F271B/ST10F271E
5.4.1 Flash control register 0 low
The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High
(FCR0H) is used to enable and to monitor all the write operations on the IFLASH. The user has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by the user in Bootstrap Mode only.
FCR0L (0x08 0000)
15 14 13 12 11 10 reserved
9
Table 7.
BSY0
LOCK
Bit
FCR
8 7 6 5 4
LOCK
R
Reset Value: 0000h :
3 2 1 0 res.
res.
BSY0 res.
R
Flash control register 0 low
Function
Bank 0 Busy (IFLASH)
This bit indicates that a write operation is running on Bank 0 (IFLASH). It is automatically set when bit WMS is set. Setting Protection operation sets bit BSY0
(since protection registers are in this Block). When this bit is set, every read access to Bank 0 will output invalid data (software trap 009Bh), while every write access to the Bank will be ignored. At the end of the write operation or during a
Program or Erase Suspend this bit is automatically reset and the Bank returns to read mode. After a Program or Erase Resume this bit is automatically set again.
Flash Registers Access Locked
When this bit is set, it means that the access to the Flash Control Registers
FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash: once it is found low, the rest of FCR0L and all the other Flash registers are accessible by the user as well.
Note that FER content can be read when LOCK is low, but its content is updated only when also BSY0 bit is reset.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
30/180
ST10F271B/ST10F271E Internal Flash memory
5.4.2 Flash control register 0 high
The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low
(FCR0L) is used to enable and to monitor all the write operations on the IFLASH. The user has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by the user in Bootstrap Mode only.
FCR0H (0x08 0002)
15 14 13 12 11 10 9 reserved WMS SUSP WPG DWPG SER
RW RW RW RW RW
FCR
8
SPR
RW
7 6 5 4 3 reserved
Reset value: 0000h
2 1 0
Flash control register 0 high Table 8.
Bit Function
SPR
SER
Set Protection
This bit must be set to select the Set Protection operation. The Set Protection operation allows to program 0s in place of 1s in the Flash Non Volatile Protection
Registers. The Flash Address in which to program must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L before starting the execution by setting bit WMS. A sequence error is flagged by bit
SEQER of FER if the address written in FARH/L is not in the range 0x0E8FB0-
0x08DFBF. SPR bit is automatically reset at the end of the Set Protection operation.
Sector Erase
This bit must be set to select the Sector Erase operation in the Flash modules. The
Sector Erase operation allows to erase all the Flash locations to value 0xFF. From
1 to all the sectors of the same Bank (excluded Test-Flash for Bank B0) can be selected to be erased through bits BxFy of FCR1H/L registers before starting the execution by setting bit WMS. It is not necessary to pre-program the sectors to
0x00, because this is done automatically. SER bit is automatically reset at the end of the Sector Erase operation.
DWPG
Double Word Program
This bit must be set to select the Double Word (64 bits) Program operation in the
Flash module. The Double Word Program operation allows to program 0s in place of 1s. The Flash Address in which to program (aligned with even words) must be written in the FARH/L registers, while the 2 Flash Data to be programmed must be written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word) before starting the execution by setting bit WMS. DWPG bit is automatically reset at the end of the Double Word Program operation.
Word Program Obsolete Product(s) - Obsolete Product(s)
WPG module. The Word Program operation allows to program 0s in place of 1s. The
Flash Address to be programmed must be written in the FARH/L registers, while Obsolete Product(s) - Obsolete Product(s) starting the execution by setting bit WMS. WPG bit is automatically reset at the end of the Word Program operation.
31/180
Internal Flash memory ST10F271B/ST10F271E
Table 8.
Bit
SUSP
WMS
Flash control register 0 high (continued)
Function
Suspend
This bit must be set to suspend the current Program (Word or Double Word) or
Sector Erase operation in order to read data in one of the Sectors of the Bank under modification or to program data in another Bank. The Suspend operation resets the Flash Bank to normal read mode (automatically resetting bit BSY0).
When in Program Suspend, the Flash module accepts only the following operations: Read and Program Resume. When in Erase Suspend the module accepts only the following operations: Read, Erase Resume and Program (Word or Double Word; Program operations cannot be suspended during Erase
Suspend). To resume a suspended operation, the WMS bit must be set again, together with the selection bit corresponding to the operation to resume (WPG,
DWPG, SER).
Note: It is forbidden to start a new Write operation with bit SUSP already set.
Write Mode Start
This bit must be set to start every write operation in the Flash module. At the end of the write operation or during a Suspend, this bit is automatically reset. To resume a suspended operation, this bit must be set again. It is forbidden to set this bit if bit ERR of FER is high (the operation is not accepted). It is also forbidden to start a new write (program or erase) operation (by setting WMS high) when bit
SUSP of FCR0 is high. Resetting this bit by software has no effect.
5.4.3 Flash control register 1 low
The Flash Control Register 1 Low (FCR1L), together with Flash Control Register 1 High
(FCR1H), is used to select the Sectors to Erase, or during any write operation to monitor the status of each Sector and Bank.
FCR1L (0x08 0004)
15 14 13 12 11 10 reserved
9
FCR
8 7 6 5 4 3
Reset value: 0000h
2 1 0
B0F7 B0F6 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0
RS RS RS RS RS RS RS RS
Flash control register 1 low Table 9.
Bit Function
Bank 0 IFLASH Sector 9:0 Status
These bits must be set during a Sector Erase operation to select the sectors to erase in Bank 0. Besides, during any erase operation, these bits are automatically set and give the status of the 8 sectors of Bank 0 (B0F7-B0F0). The meaning of
B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end Obsolete Product(s) - Obsolete Product(s)
32/180
ST10F271B/ST10F271E Internal Flash memory
5.4.4 Flash control register 1 high
The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low
(FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the status of each Sector and Bank.
FCR1H (0x08 0006)
15 14 13 12 11 10 reserved
9
FCR
8
B0S
RS
7 6 5 4 reserved
3
Reset value: 0000h
2 1 0
Table 10.
Flash control register 1 high
Bit
B0S
Function
Bank 0 Status (IFLASH)
During any erase operation, this bit is automatically modified and gives the status of the Bank 0. The meaning of B0S bit is given in the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. This bit is automatically reset at the end of a erase operation if no errors are detected.
During any erase operation, this bit is automatically set and gives the status of the Bank 0.
The meaning of B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of an erase operation if no errors are detected.
Table 11.
Banks (BxS) and sectors (BxFy) status bits meaning
ERR SUSP B0S = 1 meaning B0Fy = 1 meaning
1
0
0
-
1
0
Erase Error in Bank 0
Erase Suspended in Bank 0
Don’t care
Erase Error in Sector y of Bank 0
Erase Suspended in Sector y of Bank 0
Don’t care
5.4.5 Flash data register 0 low
The Flash Address Registers (FARH/L) and the Flash Data Registers (FDR1H/L-FDR0H/L) are used during the program operations to store Flash Address in which to program and
Data to program.
FDR0L (0x08 0008) FCR Reset value: FFFFh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Obsolete Product(s) - Obsolete Product(s) 0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Obsolete Product(s) - Obsolete Product(s)
Table 12.
Flash data register 0 low
Bit Function
DIN(15:0)
Data Input 15:0
These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
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Internal Flash memory ST10F271B/ST10F271E
5.4.7
FDR0H (0x08 000A)
15 14 13 12 11 10 9
FCR
8 7 6 5 4 3
Reset value: FFFFh
2 1 0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 13.
Flash data register 0 high
Bit
DIN(31:16)
Function
Data Input 31:16
These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
Flash data register 1 low
FDR1L (0x08 000C)
15 14 13 12 11 10 9
FCR
8 7 6 5 4 3
Reset value: FFFFh
2 1 0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 14.
Flash data register 1 low
Bit
DIN(15:0)
Function
Data Input 15:0
These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
FDR1H (0x08 000E)
15 14 13 12 11 10 9
FCR
8 7 6 5 4 3
Reset value: FFFFh
2 1 0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Data Input 31:16
Function Bit Obsolete Product(s) - Obsolete Product(s)
These bits must be written with the Data to program the Flash with the following
DIN(31:16) operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
34/180
ST10F271B/ST10F271E Internal Flash memory
5.4.9 Flash address register low
FARL (0x08 0010)
15 14 13 12 11 10 9
FCR
8 7 6 5 4 3
Reset value: 0000h
2 1 0
ADD15ADD14ADD13ADD12ADD11ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 reserved
RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 16.
Flash address register low
Bit
ADD(15:2)
Function
Address 15:2
These bits must be written with the Address of the Flash location to program in the following operations: Word Program (32-bit) and Double Word Program (64-bit). In
Double Word Program bit ADD2 must be written to ‘0’.
5.4.10 Flash address register high
FARH (0x08 0012)
15 14 13 12 11 10 reserved
9
FCR
8 7 6 5 4 3
Reset value: 0000h
2 1 0
ADD20 ADD19 ADD18 ADD17 ADD16
RW RW RW RW RW
Table 17.
Flash address register high
Bit
ADD(20:16)
Function
Address 20:16
These bits must be written with the Address of the Flash location to program in the following operations: Word Program and Double Word Program.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
35/180
Internal Flash memory ST10F271B/ST10F271E
5.4.11 Flash error register
Flash Error register, as well as all the other Flash registers, can be properly read only once
LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY0 bit is reset as well; for this reason, it is definitively meaningful reading FER register content only when LOCK bit and BSY0 bit are cleared.
FER (0x8 0014h)
15 14 13 12 11 10 reserved
9
FCR
8 7 6
WPF RESER SEQER
RC RC RC
5 4 reserved
3
Reset value: 0000h
2 1 0
10ER PGER ERER ERR
RC RC RC RC
Table 18.
Flash error register
Bit Function
ERR
ERER
PGER
10ER
Write Error
This bit is automatically set when an error occurs during a Flash write operation or when a bad write operation setup is done. Once the error has been discovered and understood, ERR bit must be software reset.
Erase Error
This bit is automatically set when an Erase error occurs during a Flash write operation. This error is due to a real failure of a Flash cell, that can no more be erased. This kind of error is fatal and the sector where it occurred must be discarded. This bit has to be software reset.
Program Error
This bit is automatically set when a Program error occurs during a Flash write operation. This error is due to a real failure of a Flash cell, that can no more be programmed. The word where this error occurred must be discarded. This bit has to be software reset.
1 over 0 Error
This bit is automatically set when trying to program at 1 bits previously set at 0
(this does not happen when programming the Protection bits). This error is not due to a failure of the Flash cell, but only flags that the desired data has not been written. This bit has to be software reset.
Sequence Error
SEQER
This bit is automatically set when the control registers (FCR1H/L-FCR0H/L,
FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to execute a valid Write
Operation. In this case no Write Operation is executed. This bit has to be software reset.
Obsolete Product(s) - Obsolete Product(s)
RESER
Resume Error
This bit is automatically set when a suspended Program or Erase operation is not resumed correctly due to a protocol error. In this case the suspended operation is Obsolete Product(s) - Obsolete Product(s)
Write Protection Flag
WPF
This bit is automatically set when trying to program or erase in a sector write protected. In case of multiple Sector Erase, the not protected sectors are erased, while the protected sectors are not erased and bit WPF is set. This bit has to be software reset.
36/180
ST10F271B/ST10F271E Internal Flash memory
The protection bits are stored in Non Volatile Flash cells inside IFLASH module, that are read once at reset and stored in 4 Volatile registers. Before they are read from the Non
Volatile cells, all the available protections are forced active during reset.
The protections can be programmed using the Set Protection operation (see Flash Control
Registers paragraph), that can be executed from all the internal or external memories except from the Flash itself.
Two kind of protections are available: write protections to avoid unwanted writings and access protections to avoid piracy. In next paragraphs all different level of protections are shown, and architecture limitations are highlighted as well.
5.5.2
The 4 Non Volatile Protection Registers are one time programmable for the user.
One register (FNVWPIR) is used to store the Write Protection fuses respectively for each sector IFLASH module. The other three Registers (FNVAPR0 and FNVAPR1L/H) are used to store the Access Protection fuses.
Flash non volatile write protection I register
FNVWPIR (0x08 DFB0)
15 14 13 12 11 10 reserved
9
NVR
8 7 6 5 4 3
Reset value: FFFFh
2 1 0
W0P7 W0P6W0P5W0P4W0P3W0P2 W0P1W0P0
RW RW RW RW RW RW RW RW
Table 19.
Flash non volatile write protection I register
Bit Function
W0P(9:0)
Write Protection Bank 0 / Sectors 9-0 (IFLASH)
These bits, if programmed at 0, disable any write access to the sectors of Bank 0
(IFLASH)
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
37/180
Internal Flash memory ST10F271B/ST10F271E
5.5.3 Flash non volatile access protection register 0
FNVAPR0 (0x08 DFB8)
15 14 13 12 11 10 9
NVR
8 reserved
7 6 5 4 3
Reset value: ACFFh
2 1 0
DBGP ACCP
RW RW
Table 20.
Flash non volatile access protection register 0
Bit Function
ACCP
DBGP
Access Protection
This bit, if programmed at 0, disables any access (read/write) to data mapped inside IFlash Module address space, unless the current instruction is fetched from
IFlash.
Debug Protection
This bit, if erased at 1, allows to by-pass all the protections using the Debug features through the Test Interface. If programmed at 0, on the contrary, all the debug features, the Test Interface and all the Flash Test Modes are disabled. Even
STMicroelectronics will not be able to access the device to run any eventual failure analysis.
5.5.4 Flash non volatile access protection register 1 low
FNVAPR1L (0x08 DFBC)
15 14 13 12 11 10 9
NVR
8 7 6 5 4
Delivery value:: FFFFh
3 2 1 0
PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 21.
Flash non volatile access protection register 1 low
Bit Function
PDS(15:0)
Protections Disable 15-0
If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit
PENx-1 has already been programmed at 0.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
38/180
ST10F271B/ST10F271E
5.5.5
5.5.6
Internal Flash memory
Flash non volatile access protection register 1 high
FNVAPR1H (0x08 DFBE)
15 14 13 12 11 10 9
NVR
8 7 6 5 4 3
Delivery value: FFFFh
2 1 0
PEN15PEN14PEN13PEN12PEN11PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 22.
Flash non volatile access protection register 1 high
Bit Function
PEN15-0
Protections Enable 15-0
If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit
ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0.
XBus flash volatile temporary access unprotection register (XFVTAUR0)
XFVTAUR0 (0x00 EB50)
15 14 13 12 11 10 9
NVR
8 reserved
7 6 5 4 3
Reset value: 0000h
2 1 0
TAUB
RW
Table 23.
XBus flash volatile temporary access unprotection register
Bit Function
TAUB
Temporary Access Unprotection bit
If this bit is set to 1, the Access Protection is temporary disabled.
This bit can be written only executing from IFlash.This fact guarantees that only a code executed in IFlash, can unprotect the IFlash, when it is Access Protected.
The I-Flash module has one level of access protection (access to data both in Reading and
Writing): if bit ACCP of FNVAPR0 is programmed at 0 and bit TAUB in XFVTAUR0 is set at
0, the I-Flash module becomes access protected: data in the I-Flash module can be read only if the current execution is from the I-Flash module itself.
To enable Access Protection, the following sequence of operations is recommended: execution from external memory or internal Rams
● program TAUB bit at 1 in XFVTAUR0 register
● Access Protection is active when both ACCP bit and TAUB bit are set to 0.
Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order to analyze rejects. Protection can be permanently enabled again by programming bit PEN0 of FNVAPR1L. The action to disable and enable again Access Protections in a permanent way can be executed a maximum of 16 times. To execute the above described operations, the Flash has to be temporary unprotected (See
Section 5.5.9: Temporary unprotection
)
39/180
Internal Flash memory ST10F271B/ST10F271E
Trying to write into the access protected Flash from internal RAM or external memories will be unsuccessful. Trying to read into the access protected Flash from internal RAM or external memories will output a dummy data (software trap 0x009Bh).
When the Flash module is protected in access, also the data access through PEC of a peripheral is forbidden. To read/write data in PEC mode from/to a protected Bank, first it is necessary to temporary unprotect the Flash module.
In the following table a summary of all levels of possible Access protection is reported: in particular, supposing to enable all possible access protections, when fetching from a memory as listed in the first column, what is possible and what is not possible to do (see column headers) is shown in the table.
Figure 6.
Summary of access protection level
Read IFLASH /
Jump to IFLASH
Read XRAMS or
Ext Mem / Jump to
XRAM or Ext Mem
Fetching from IFLASH
Fetching from IRAM
Fetching from XRAM
Fetching from External
Memory
Yes / Yes
No / Yes
No / Yes
No / Yes
Yes / Yes
Yes / Yes
Yes / Yes
Yes / Yes
Read FLASH
Registers
Yes
Yes
Yes
Yes
Write FLASH
Registers
No
No
No
No
When the Access Protection is enabled, Flash registers can not be written, so no program/erase operation can be run on I-Flash. To enable the access to registers again, the
Temporary Access Unprotection procedure has to be followed (see
Section 5.5.9
).
The Flash modules have one level of Write Protections: each Sector of each Bank of each
Flash Module can be Software Write Protected by programming at 0 the related bit W0Px in
FNVWPIRL register.
Bits W0Px of FNVWPIRL can be temporary unprotected by executing the Set Protection operation and by writing 1 into these bits.
To restore the write protection bits it is necessary to reset the microcontroller or to execute a
Set Protection operation and write 0 into the desired bits.
In reality, when a temporary write unprotection operation is executed, the corresponding
Obsolete Product(s) - Obsolete Product(s) a protection set operation), will continue to maintain the 0. For this reason, the User software must be in charge to track the current write protection status (for instance using a Obsolete Product(s) - Obsolete Product(s)
(a temporary unprotection cannot be detected).
To temporary unprotect the Flash when the Access Protection is active, it is necessary to set at 1 the bit TAUB in XFVTAUR0. This bit can be write at 1, only executing from Flash: in this way only an instruction executed from Flash can unprotect the Flash itself.
To restore the Access Protection, it is necessary to reset the microcontroller or to write at 0 the bit TAUB in XFVTAUR0.
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ST10F271B/ST10F271E Internal Flash memory
Note:
In the following, examples for each kind of Flash write operation are presented.
The write operation commands must be executed from another memory (internal RAM or external memory), as in ST10F269 device. In fact, due to IBus characteristics, it is not possible to perform write operation in Flash while fetching code from Flash.
Moreover, direct addressing is not allowed for write accesses to IFlash control registers.
This means that both address and data for a writing operation must be loaded in one of
ST10 GPR register (R0...R15).
Write operation on IBus registers is 16 bit wide.
Example of indirect addressing mode
MOV RWm, #ADDRESS; /*Load Add in RWm*/
MOV RWn, #DATA; /*Load Data in RWn*/
MOV [RWm], RWn; /*Indirect addressing*/
Word program
Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x025554
FCR0H|= 0x2000;
FARL = 0x5554;
FARH = 0x0002;
FDR0L = 0xAAAA;
FDR0H = 0xAAAA;
FCR0H|= 0x8000;
/*Set WPG in FCR0H*/
/*Load Add in FARL*/
/*Load Add in FARH*/
/*Load Data in FDR0L*/
/*Load Data in FDR0H*/
/*Operation start*/
Double word program
Example: Double Word Program (64-bit) of data 0x55AA55AA at address 0x035558 and data 0xAA55AA55 at address 0x03555C in IFLASH Module.
FCR0H |= 0x1000;
FARL = 0x5558;
FARH = 0x0003;
FDR0L = 0x55AA;
FDR0H = 0x55AA;
FDR1L = 0xAA55;
FDR1H = 0xAA55;
FCR0H |= 0x8000;
/*Set DWPG/
/*Load Add in FARL*/
/*Load Add in FARH*/
/*Load Data in FDR0L*/
/*Load Data in FDR0H*/
/*Load Data in FDR1L*/
/*Load Data in FDR1H*/
/*Operation start*/
Double Word Program is always performed on the Double Word aligned on a even Word: bit
ADD2 of FARL is ignored.
Obsolete Product(s) - Obsolete Product(s)
Sector erase
Obsolete Product(s) - Obsolete Product(s)
FCR0H |= 0x0800; /*Set SER in FCR0H*/
FCR1L |= 0x0003;
FCR0H |= 0x8000;
/*Set B0F1, B0F0*/
/*Operation start*/
41/180
Internal Flash memory ST10F271B/ST10F271E
Suspend and resume
Word Program, Double Word Program, and Sector Erase operations can be suspended in the following way:
FCR0H |= 0x4000; /*Set SUSP in FCR0H*/
Then the operation can be resumed in the following way:
FCR0H |= 0x0800;
FCR0H |= 0x8000;
/*Set SER in FCR0H*/
/*Operation resume*/
Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of
Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise the operation is aborted and bit RESER of FER is set.
Erase suspend, program and resume
A Sector Erase operation can be suspended in order to program (Word or Double Word) another Sector.
Example: Sector Erase of sector B0F1 of IFLASH Module.
FCR0H |= 0x0800;
FCR1L |= 0x0002;
FCR0H |= 0x8000;
/*Set SER in FCR0H*/
/*Set B0F1*/
/*Operation start*/
Example: Sector Erase Suspend.
FCR0H |= 0x4000; do
/*Set SUSP in FCR0H*/
/*Loop to wait for LOCK=0 and WMS=0*/
tmp2 = FCR0H;
} while ((tmp1 && 0x0010) || (tmp2 && 0x8000));
Example: Word Program of data 0x5555AAAA at address 0x045554 in IFLASH module.
FCR0H &= 0xBFFF; /*Rst SUSP in FCR0H*/
FCR0H|= 0x2000;/*Set WPG in FCR0H*/
FARL
FARH
= 0x5554;
= 0x0004;
/*Load Add in FARL*/
/*Load Add in FARH*/
FDR0L = 0xAAAA;
FDR0H = 0x5555;
FCR0H |= 0x8000;
/*Load Data in FDR0L*/
/*Load Data in FDR0H*/
/*Operation start*/
Once the Program operation is finished, the Erase operation can be resumed in the following way: Obsolete Product(s) - Obsolete Product(s)
FCR0H|= 0x8000;/*Operation resume*/
Obsolete Product(s) - Obsolete Product(s)
Word or Double Word Program during Erase Suspend cannot be suspended.
In summary:
42/180
ST10F271B/ST10F271E Internal Flash memory
●
●
A Sector Erase can be suspended by setting SUSP bit.
● To perform a Word Program operation during Erase Suspend, firstly bits SUSP and
SER must be reset, then bit WPG and WMS can be set.
To resume the Sector Erase operation bit SER must be set again.
In any case it is forbidden to start any write operation with SUSP bit already set.
Set protection
Example 1: Enable Write Protection of sectors B0F3-0 of Bank 0 in IFLASH module.
FCR0H |= 0x0100;
FARL = 0xDFB4;
FARH = 0x0008;
FDR0L = 0xFFF0;
FDR0H = 0xFFFF;
FCR0H |= 0x8000;
/*Set SPR in FCR0H*/
/*Load Add of register FNVWPIR in FARL*/
/*Load Add of register FNVWPIR in FARH*/
/*Load Data in FDR0L*/
/*Load Data in FDR0H*/
/*Operation start*/
Example 2: Enable Access and Debug Protection.
FCR0H |= 0x0100;
FARL = 0xDFB8;
FARH = 0x0008;
FDR0L = 0xFFFC;
FCR0H |= 0x8000;
/*Set SPR in FCR0H*/
/*Load Add of register FNVAPR0 in FARL*/
/*Load Add of register FNVAPR0 in FARH*/
/*Load Data in FDR0L*/
/*Operation start*/
Example 3: Disable in a permanent way Access and Debug Protection.
XFVTAUR0 = 0x0001;
FCR0H |= 0x0100;
FARL
FARH
= 0xDFBC;
= 0x0008;
FDR0L
FCR0H
= 0xFFFE;
|= 0x8000;
/*Set TAUB in XFVTAUR0*/
/*Set SPR in FCR0H*/
/*Load Add of register FNVAPR1L in FARL*/
/*Load Add of register FNVAPR1L in FARH*/
/*Load Data in FDR0L for clearing PDS0*/
/*Operation start*/
Example 4: Enable again in a permanent way Access and Debug Protection, after having disabled them.
XFVTAUR0 = 0x0001;
FCR0H |= 0x0100;
FARL
FARH
= 0xDFBC;
= 0x0008;
= 0xFFFE; FDR0H
PEN0*/
FCR0H |= 0x8000;
/*Set TAUB in XFVTAUR0*/
/*Set SPR in FCR0H*/
/*Load Add register FNVAPR1H in FARL*/
/*Load Add register FNVAPR1H in FARH*/
/*Load Data in FDR0H for clearing
/*Operation start*/
XFVTAUR0 = 0x0000; /*Reset TAUB in XFVTAUR0*/ Obsolete Product(s) - Obsolete Product(s) examples 3 and 4) can be done for a maximum of 16 times.
Obsolete Product(s) - Obsolete Product(s)
43/180
Internal Flash memory ST10F271B/ST10F271E
In general, each write operation is started through a sequence of 3 steps:
1.
The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register 0.
2. The second step is the definition of the Address and Data for programming or the
Sectors or Banks to erase.
3. The last instruction is used to start the write operation, by setting the start bit WMS in the FCR0.
Once selected, but not yet started, one operation can be canceled by resetting the operation selection bit.
A summary of the available Flash Module Write Operations are shown in the following
Table 24: Flash write operations
.
Table 24.
Flash write operations
Operation Select bit Start bit
Word Program (32-bit)
Double Word Program (64-bit)
Sector Erase
Set Protection
Program/Erase Suspend
WPG
DWPG
SER
SPR
SUSP
Address and data
FARL/FARH
FDR0L/FDR0H
FARL/FARH
FDR0L/FDR0H
FDR1L/FDR1H
FCR1L/FCR1H
FDR0L/FDR0H
None
WMS
WMS
WMS
WMS
None
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
44/180
ST10F271B/ST10F271E Bootstrap loader
6.1
ST10F271 implements Boot capabilities in order to:
●
●
Support bootstrap via UART or bootstrap via CAN for the standard bootstrap.
Support a Selective Bootstrap Loader, to manage the bootstrap sequence in a different way.
Selection among user-code, standard or selective bootstrap
The boot modes are triggered with a special combination set on Port0L[5...4]. Those signals, as other configuration signals, are latched on the rising edge of RSTIN pin.
● Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) will select the normal mode
(also called User Mode) and select the user Flash to be mapped from address
00’0000h.
● Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) will select ST10 standard bootstrap mode (Test-Flash is active and overlaps user Flash for code fetches from address 00'0000h; user Flash is active and available for read accesses).
● Decoding of reset configuration (P0L.5 = 0, P0L.4 = 1) will activate new verifications to select which bootstrap software to execute:
– if the User mode signature in the User Flash is programmed correctly, then a software reset sequence is selected and the User code is executed;
– if the User mode signature is not programmed correctly in the user Flash, then the
User key location is read again. Its value will determine which communication channel will be enabled for bootstraping
.
Table 25.
ST10F271 boot mode selection
P0.5
P0.4
ST10 decoding
1 1
1
0
0
0
1
0
User Mode: user Flash mapped at 00’0000h
Standard Bootstrap Loader: User Flash mapped from 00’0000h, code fetches redirected to Test-Flash at 00’0000h
Selective Boot Mode: User Flash mapped from 00’0000h, code fetches redirected to Test-Flash at 00’0000h (different sequence execution in respect of
Standard Bootstrap Loader)
Reserved
Standard bootstrap loader
interface, or a start condition from UART line.
Start condition on UART RxD: ST10F271 starts standard bootstrap loader. This bootstrap loader is identical to other ST10 devices (example: ST10F269, ST10F168).
Valid dominant bit on CAN1 RxD: ST10F271 start bootstrapping via CAN1.
45/180
Bootstrap loader
6.3
ST10F271B/ST10F271E
Alternate and selective boot mode (ABM and SBM)
6.3.2
Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of
RSTIN.
User mode signature integrity check
The behavior of the Selective Boot Mode is based on the computing of a signature between the content of 2 memory locations and a comparison with a reference signature. This requires that users who use Selective Boot have reserved and programmed the Flash memory locations.
When the user signature is not correct, instead of executing the Standard Bootstrap Loader
(triggered by P0L.4 low at reset), additional check is made.
●
●
●
Depending on the value at the User key location, following behavior will occur:
● A jump is performed to the Standard Bootstrap Loader
Only UART is enabled for bootstraping
Only CAN1 is enabled for bootstraping
The device enters an infinite loop.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
46/180
Central processing unit (CPU) ST10F271B/ST10F271E
7 Central processing unit (CPU)
The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Most of the ST10F271’s instructions can be executed in one instruction cycle which requires
31.25ns at 64 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted.
Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x
16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles.
The jump cache reduces the execution time of repeatedly performed jumps in a loop, from
2 cycles to 1 cycle.
The CPU uses a bank of 16 word registers to run the current context. This bank of General
Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area.
A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU.
The number of register banks is only restricted by the available Internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.
Figure 7.
CPU block diagram (MAC Unit not included)
16
CPU
MDH
MDL
R15
2K Byte
Internal
SP
STKOV
RAM
STKUN
Mul./Div.-HW
128K Byte Bit-Mask Gen.
Bank
Exec. Unit General
Flash n
Instr. Ptr Purpose memory
4-Stage
Registers
ALU
32
Pipeline
PSW
16-Bit
Obsolete Product(s) - Obsolete Product(s)
SYSCON
BUSCON 0
CP
Obsolete Product(s) - Obsolete Product(s)
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3 i
ADDRSEL 4 16
Bank
0
Data Pg. Ptrs Code Seg. Ptr.
47/180
Central processing unit (CPU)
7.1
ST10F271B/ST10F271E
Multiplier-accumulator unit (MAC)
The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms.
The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle.
This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a repeat unit.
The co-processor instructions extend the ST10 CPU instruction set with multiply, multiplyaccumulate, 32-bit signed arithmetic operations.
Figure 8.
MAC unit architecture
Operand 1
16 16
Operand 2
GPR Pointers *
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Register
QR1 GPR Offset Register
QX0 IDX Offset Register
QX1 IDX Offset Register
Concatenation
16 x 16 signed/unsigned
Multiplier
Interrupt
Controller
ST10 CPU
MRW
Repeat Unit
MCW
32 32
Mux
Sign Extend
Scaler
40
0h
40
Mux
40
08000h
40
0h
Mux
40 40
A B
40-bit Signed Arithmetic Unit
40
MSW
Flags MAE
40
MAH MAL
Control Unit
* Shared with standard ALU 40
8-bit Left/Right
Shifter
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
48/180
ST10F271B/ST10F271E Central processing unit (CPU)
7.2 Instruction set summary
The
Table 26
lists the instructions of the ST10F271. The detailed description of each
instruction can be found in the “ST10 Family Programming Manual”.
Table 26.
Standard instruction set summary
Mnemonic Description Bytes
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR
BSET
BMOV(N)
BAND, BOR, BXOR
BCMP
BFLDH/L
CMP(B)
CMPD1/2
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bit-wise AND, (word/byte operands)
Bit-wise OR, (word/byte operands)
Bit-wise XOR, (word/byte operands)
Clear direct bit
Set direct bit
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Compare direct bit to direct bit
Bit-wise modify masked high/low byte of bit-addressable direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
4
2 / 4
2 / 4
CMPI1/2
PRIOR
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR
2 / 4
2
SHL / SHR
ROL / ROR
Shift left/right direct word GPR Obsolete Product(s) - Obsolete Product(s)
Rotate left/right direct word GPR
2
2
Arithmetic (sign bit) shift right direct word GPR 2 ASHR Obsolete Product(s) - Obsolete Product(s)
MOV(B) Move word (byte) data 2 / 4
MOVBS
MOVBZ
Move byte operand to word operand with sign extension
Move byte operand to word operand with zero extension
2 / 4
2 / 4
JMPA, JMPI, JMPR
JMPS
Jump absolute/indirect/relative if condition is met
Jump absolute to a code segment
4
4
2
2
2
2 / 4
2 / 4
2 / 4
2 / 4
2 / 4
2 / 4
2 / 4
2
2
2
2
4
4
4
49/180
Central processing unit (CPU) ST10F271B/ST10F271E
RETI
SRST
IDLE
PWRDN
SRVWDT
DISWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
Table 26.
Standard instruction set summary (continued)
Mnemonic Description
J(N)B
JBC
JNBS
CALLA, CALLI,
CALLR
CALLS
Jump relative if direct bit is (not) set
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
PCALL
TRAP
PUSH, POP
SCXT
RET
RETS
RETP
Call absolute subroutine in any code segment
Push direct word register onto system stack and call absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack and update register with word operand
Return from intra-segment subroutine
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct word register from system stack
Return from interrupt service subroutine
Software Reset
Enter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
Bytes
4
4
4
4
4
4
2
2
2
2
4
2
4
4
4
2
4
4
4
2
2
2 / 4
2 / 4
2
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
50/180
ST10F271B/ST10F271E
7.3
Central processing unit (CPU)
MAC co-processor specific instructions
The
Table 27
lists the MAC instructions of the ST10F271. The detailed description of each
instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are encoded on 4 Bytes.
Table 27.
MAC instruction set summary
Mnemonic
CoABS
CoADD(2)
CoASHR(rnd)
CoCMP
CoLOAD(-,2)
CoMAC(R,u,s,-,rnd)
CoMACM(R)(u,s,-,rnd)
CoMAX / CoMIN
CoMOV
CoMUL(u,s,-,rnd)
CoNEG(rnd)
CoNOP
CoRND
CoSHL / CoSHR
CoSTORE
CoSUB(2,R)
Description
Absolute Value of the Accumulator
Addition
Accumulator Arithmetic Shift Right & Optional Round
Compare Accumulator with Operands
Load Accumulator with Operands
(Un)Signed/(Un)Signed Multiply-Accumulate & Optional Round
(Un)Signed/(Un)Signed Multiply-Accumulate with Parallel Data
Move & Optional Round
Maximum / Minimum of Operands and Accumulator
Memory to Memory Move
(Un)Signed/(Un)Signed multiply & Optional Round
Negate Accumulator & Optional Round
No-Operation
Round Accumulator
Accumulator Logical Shift Left / Right
Store a MAC Unit Register
Substraction
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
51/180
ST10F271B/ST10F271E External bus controller
8 External bus controller
All of the external memory accesses are performed by the on-chip external bus controller.
●
●
●
●
The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes:
16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed
16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed
16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed
16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed
In demultiplexed bus modes addresses are output on PORT1 and data is input / output on
PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use
PORT0 for input / output.
Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ALE and read / write delay) are programmable giving the choice of a wide range of memories and external peripherals.
Up to four independent address windows may be defined (using register pairs ADDRSELx /
BUSCONx) to access different resources and bus characteristics.
These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1.
All accesses to locations not covered by these four address windows are controlled by
BUSCON0. Up to five external CS signals (four windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a ‘Ready’ function.
A HOLD / HLDA protocol is available for bus arbitration which shares external resources with other bus masters.
The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to’1’ the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic.
For applications which require less external memory space, the address space can be restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an address space of 16M Bytes is used, otherwise four, two or no address lines.
Chip select timing can be made programmable. By default (after reset), the CSx lines
Obsolete Product(s) - Obsolete Product(s)
SYSCON register the CSx lines change with the rising edge of ALE.
Obsolete Product(s) - Obsolete Product(s) the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register.
52/180
ST10F271B/ST10F271E Interrupt system
The interrupt response time for internal program execution is from 78ns to 187.5ns at
64 MHz CPU clock.
The ST10F271 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment of either the PEC source or destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F271 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities.
An interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels.
Once starting to be processed by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.
Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).
Fast external interrupts may also have interrupt sources selected from other peripherals; for example the CANx controller receive signals (CANx_RxD) and I
2
C serial clock signal can be used to interrupt the system.
Table 28
shows all the available ST10F271 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
Table 28.
Interrupt sources
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number PEC Service Request
CC0IR CC0IE CC0INT 00’0040h 10h CAPCOM Register 0 Obsolete Product(s) - Obsolete Product(s)
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM Register 2
CAPCOM Register 3
CC2IR
CC3IR
CC2IE
CC3IE
CC2INT
CC3INT
00’0048h
00’004Ch
12h
13h
CAPCOM Register 4
CAPCOM Register 5
CC4IR
CC5IR
CC4IE
CC5IE
CC4INT
CC5INT
00’0050h
00’0054h
14h
15h
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Interrupt system ST10F271B/ST10F271E
Table 28.
Interrupt sources (continued)
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 6
CAPCOM Register 7
CAPCOM Register 8
CAPCOM Register 9
CAPCOM Register 10
CAPCOM Register 11
CAPCOM Register 12
CAPCOM Register 13
CAPCOM Register 14
CAPCOM Register 15
CAPCOM Register 16
CAPCOM Register 17
CAPCOM Register 18
CAPCOM Register 19
CAPCOM Register 20
CAPCOM Register 21
CAPCOM Register 22
CAPCOM Register 23
CAPCOM Register 24
CAPCOM Register 25
CAPCOM Register 26
CAPCOM Register 27
CAPCOM Register 28
CAPCOM Register 29
CAPCOM Register 30
CAPCOM Register 31
CC18IR
CC19IR
CC20IR
CC21IR
CC22IR
CC23IR
CC24IR
CC25IR
CC26IR
CC27IR
CC28IR
CC29IR
CC30IR
CC31IR
CC6IR
CC7IR
CC8IR
CC9IR
CC10IR
CC11IR
CC12IR
CC13IR
CC14IR
CC15IR
CC16IR
CC17IR
CC18IE
CC19IE
CC20IE
CC21IE
CC22IE
CC23IE
CC24IE
CC25IE
CC26IE
CC27IE
CC28IE
CC29IE
CC30IE
CC31IE
CC6IE
CC7IE
CC8IE
CC9IE
CC10IE
CC11IE
CC12IE
CC13IE
CC14IE
CC15IE
CC16IE
CC17IE
CC18INT
CC19INT
CC20INT
CC21INT
CC22INT
CC23INT
CC24INT
CC25INT
CC26INT
CC27INT
CC28INT
CC29INT
CC30INT
CC31INT
CC6INT
CC7INT
CC8INT
CC9INT
CC10INT
CC11INT
CC12INT
CC13INT
CC14INT
CC15INT
CC16INT
CC17INT
00’00C8h
00’00CCh
00’00D0h
00’00D4h
00’00D8h
00’00DCh
00’00E0h
00’00E4h
00’00E8h
00’00ECh
00’00F0h
00’0110h
00’0114h
00’0118h
00’0058h
00’005Ch
00’0060h
00’0064h
00’0068h
00’006Ch
00’0070h
00’0074h
00’0078h
00’007Ch
00’00C0h
00’00C4h
CAPCOM Timer 0
CAPCOM Timer 1
T0IR
T1IR
T0IE
T1IE
T0INT
T1INT
00’0080h
00’0084h
20h
21h
T7IR T7IE T7INT 00’00F4h 3Dh CAPCOM Timer 7 Obsolete Product(s) - Obsolete Product(s)
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh
GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h
GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h
GPT1 Timer 4
GPT2 Timer 5
T4IR
T5IR
T4IE
T5IE
T4INT
T5INT
00’0090h
00’0094h
24h
25h
38h
39h
3Ah
3Bh
3Ch
44h
45h
46h
32h
33h
34h
35h
36h
37h
1Ch
1Dh
1Eh
1Fh
30h
31h
16h
17h
18h
19h
1Ah
1Bh
54/180
ST10F271B/ST10F271E Interrupt system
Table 28.
Interrupt sources (continued)
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
GPT2 Timer 6
GPT2 CAPREL Register
A/D Conversion Complete
A/D Overrun Error
ASC0 Transmit
ASC0 Transmit Buffer
ASC0 Receive
ASC0 Error
SSC Transmit
SSC Receive
SSC Error
PWM Channel 0...3
See Paragraph
See Paragraph
See Paragraph
See Paragraph
T6IR
CRIR
ADCIR
ADEIR
S0TIR
S0TBIR
S0RIR
S0EIR
SCTIR
SCRIR
SCEIR
PWMIR
XP0IR
XP1IR
XP2IR
XP3IR
T6IE
CRIE
ADCIE
ADEIE
S0TIE
S0TBIE
S0RIE
S0EIE
SCTIE
SCRIE
SCEIE
PWMIE
XP0IE
XP1IE
XP2IE
XP3IE
Interrupt
Vector
T6INT
CRINT
ADCINT
ADEINT
S0TINT
S0TBINT
S0RINT
S0EINT
SCTINT
SCRINT
SCEINT
PWMINT
XP0INT
XP1INT
XP2INT
XP3INT
Vector
Location
00’0098h
00’009Ch
00’00A0h
00’00A4h
00’00A8h
00’011Ch
00’00ACh
00’00B0h
00’00B4h
00’00B8h
00’00BCh
00’00FCh
00’0100h
00’0104h
00’0108h
00’010Ch
Trap
Number
2Bh
2Ch
2Dh
2Eh
2Fh
3Fh
40h
41h
42h
43h
26h
27h
28h
29h
2Ah
47h
Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution. Hardware trap services cannot not be interrupted by standard interrupt or by PEC interrupts.
The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some constraints on the implementation of the new functionality. In particular, the additional X-
Peripherals SSC1, ASC1, I
2
C, PWM1 and RTC need some resources to implement interrupt
Obsolete Product(s) - Obsolete Product(s)
management is proposed. In the next
Figure 9
, the principle is explained through a simple
diagram, which shows the basic structure replicated for each of the four X-interrupt available Obsolete Product(s) - Obsolete Product(s)
It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each:
Byte High XIRxSEL[15:8] Interrupt Enable bits ●
● Byte Low XIRxSEL[7:0] Interrupt Flag bits
When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL register) define a mask which controls which sources will be associated with the unique
55/180
Interrupt system ST10F271B/ST10F271E available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also provide information about events which are not currently serviced by the interrupt controller
(since masked through the enable bits), allowing an effective software management also in absence of the possibility to serve the related interrupt request: a periodic polling of the flag bits may be implemented inside the user application.
Figure 9.
X-Interrupt basic structure
7 0
Flag[7:0] XIR x SEL[7:0] (x = 0, 1, 2, 3)
IT Source 7
IT Source 6
IT Source 5
IT Source 4
IT Source 3
IT Source 2
IT Source 1
IT Source 0
XP x IC .
XP x IR (x = 0, 1, 2, 3)
15
Enable[7:0]
8
XIR x SEL[15:8] (x = 0, 1, 2, 3)
The
Table 29
summarizes the mapping of the different interrupt sources which shares the
four X-interrupt vectors.
Table 29.
X-Interrupt detailed mapping
XP0INT
CAN1 Interrupt x
XP1INT XP2INT XP3INT x
CAN2 Interrupt
I2C Receive x x x x x
I2C Transmit x x x
I2C Error x
SSC1 Receive x x x Obsolete Product(s) - Obsolete Product(s)
SSC1 Transmit x x x
ASC1 Receive
ASC1 Transmit
ASC1 Transmit Buffer x x x x x x x x x
56/180
ST10F271B/ST10F271E
Table 29.
X-Interrupt detailed mapping (continued)
XP0INT XP1INT
ASC1 Error
PLL Unlock / OWD
PWM1 Channel 3...0
XP2INT x
Interrupt system
XP3INT x x x
9.2 Exception and error traps list
Table 30
shows all of the possible exceptions or error conditions that can arise during runtime.
Table 30.
Trap priorities
Exception Condition
Trap
Flag
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
MAC Interruption
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
NMI
STKOF
STKUF
UNDOPC
MACTRP
PRTFLT
ILLOPA
ILLINA
ILLBUS
Trap
Vector
RESET
RESET
RESET
NMITRAP
STOTRAP
STUTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
Software Traps
TRAP Instruction
Vector
Location
00’0000h
00’0000h
00’0000h
00’0008h
00’0010h
00’0018h
Trap
Number
00h
00h
00h
02h
04h
06h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
[002Ch - 003Ch] [0Bh - 0Fh]
Any
0000h – 01FCh in steps of 4h
Any
[00h - 7Fh]
Trap*
Priority
III
III
III
II
II
II
Current
CPU
Priority
I
I
I
I
I
I
Note: * - All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets.
Obsolete Product(s) - Obsolete Product(s)
second priority level.
Obsolete Product(s) - Obsolete Product(s)
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.
57/180
Capture / compare (CAPCOM) units
10 Capture / compare (CAPCOM) units
ST10F271B/ST10F271E
The ST10F271 has two 16-channel CAPCOM units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 125ns at 64 MHz CPU clock.
The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. In addition, external count inputs for
CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events.
Each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each of the 32 registers has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated.
Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture / compare register, specific actions will be taken based on the selected compare mode.
The input frequencies f
Tx
, for the timer input selector Tx, are determined as a function of the
CPU clocks. The timer input frequencies, resolution and periods which result from the selected pre-scaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in the
Table 32
Table 33
numbers may be rounded to 3 significant figures.
Obsolete Product(s) - Obsolete Product(s)
58/180
ST10F271B/ST10F271E Capture / compare (CAPCOM) units
Table 31.
Compare modes
Compare
Modes
Function
Mode 0
Mode 1
Interrupt-only compare mode; several compare interrupts per timer period are possible
Pin toggles on each compare match; several compare events per timer period are possible
Mode 2
Mode 3
Interrupt-only compare mode; only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.
Table 32.
CAPCOM timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection TxI f
CPU
= 40 MHz
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler for f
CPU
8 16 32 64 128 256 512 1024
Input Frequency
Resolution
Period
5MHz
200ns
13.1ms
2.5MHz 1.25MHz 625 kHz
400ns
26.2ms
0.8µs
52.4ms
312.5 kHz
3.2µs
156.25 kHz
6.4µs
78.125 kHz
39.1 kHz
12.8µs 25.6µs 1.6µs
104.8 ms
209.7ms 419.4ms
838.9ms
1.678s
Table 33.
CAPCOM timer input frequencies, resolutions and periods at 64 MHz
Timer Input Selection TxI f
CPU
= 64 MHz
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler for f
CPU
8 16 32 64 128 256 512 1024
Input Frequency 8MHz 4MHz 2MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz
Resolution 125ns 250ns 0.5µs 1.0µs 2.0µs 4.0µs 8.0µs 16.0µs
Period 8.2ms
16.4ms
32.8ms
65.5ms 131.1ms 262.1ms
524.3ms
1.049s
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Obsolete Product(s) - Obsolete Product(s)
59/180
General purpose timer unit
11 General purpose timer unit
ST10F271B/ST10F271E
The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module.
11.1 GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer , gated timer , counter mode and incremental interface mode .
In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler.
In counter mode, the timer is clocked in reference to external events.
Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input.
Table 34
Table 35
list the timer input frequencies, resolution and periods for each pre-
scaler option at 40MHz and 64MHz CPU clock respectively.
In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow / underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high resolution of long duration measurements.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3.
Obsolete Product(s) - Obsolete Product(s)
Timer Input Selection T2I / T3I / T4I f
CPU
= 40 MHz
Pre-scaler factor
8 16
Input frequency 5MHz 2.5MHz
32 64 128
1.25
MHz
625 kHz
312.5 kHz
256
156.25 kHz
512 1024
78.125 kHz
39.1 kHz
60/180
ST10F271B/ST10F271E General purpose timer unit
Table 34.
GPT1 timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection T2I / T3I / T4I f
CPU
= 40 MHz
000b 001b 010b 011b 100b 101b 110b 111b
200ns 400ns 0.8µs Resolution
Period maximum
13.1ms
26.2ms
52.4ms
1.6µs
104.8 ms
3.2µs 6.4µs 12.8µs 25.6µs
209.7ms
419.4ms
838.9ms
1.678s
Table 35.
GPT1 timer input frequencies, resolutions and periods at 64 MHz
Timer Input Selection T2I / T3I / T4I f
CPU
= 64 MHz
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor
Input Freq
Resolution
Period maximum
8 16
8MHz 4MHz
125ns 250ns
32
2MHz
0.5µs
64 128 256 512 1024
1 kHz 500 kHz 250 kHz 128 kHz 64 kHz
1.0µs 2.0µs 4.0µs 8.0µs 16.0µs
8.2ms
16.4ms
32.8ms
65.5ms
131.1ms
262.1ms
524.3ms
1.049s
Figure 10.
Block diagram of GPT1
T2EUD
U/D
GPT1 Timer T2
Interrupt
Request CPU Clock
2n n=3...10
T2IN
T2
Mode
Control
Reload
Capture
CPU Clock
2n n=3...10
T3OUT
T3IN
T3
Mode
Control
GPT1 Timer T3 T3OTL
U/D
T3EUD
Capture
T4IN
T4
Mode
Control
Reload Interrupt
Request
CPU Clock
2n n=3...10
GPT1 Timer T4
Interrupt
Request
T4EUD U/D
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
61/180
General purpose timer unit ST10F271B/ST10F271E
11.2 GPT2
The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin
(T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental
Interface Mode.
Table 36
Table 37
list the timer input frequencies, resolution and periods for each pre-
scaler option at 40MHz and 64MHz CPU clock respectively.
Table 36.
GPT2 timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection T5I / T6I f
CPU
= 40MHz
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor
4 8 16 32 64 128 256 512
Input Freq 10MHz 5MHz 2.5MHz
100ns 200ns 400ns
1.25
MHz
0.8µs
625 kHz
1.6µs
312.5 kHz
3.2µs
156.25 kHz
6.4µs
78.125 kHz
12.8µs Resolution
Period maximum
6.55ms
13.1ms
26.2ms
52.4ms
104.8ms 209.7ms
419.4ms
838.9ms
Table 37.
GPT2 timer input frequencies, resolutions and periods at 64 MHz
Timer Input Selection T5I / T6I f
CPU
= 64MHz
Pre-scaler
000b 001b 010b 011b 100b 101b 110b 111b
Obsolete Product(s) - Obsolete Product(s) factor
4 8 16 32 64 128 256 512
Obsolete Product(s) - Obsolete Product(s)
Resolution 62.5ns
125ns 250ns 0.5µs 1.0µs 2.0µs 4.0µs 8.0µs
Period maximum
4.1ms
8.2ms
16.4ms
32.8ms
65.5ms
131.1ms
262.1ms
524.3ms
62/180
ST10F271B/ST10F271E
Figure 11.
Block diagram of GPT2
T5EUD
CPU Clock
2n n=2...9
T5IN
T5
Mode
Control
Clear
U/D
GPT2 Timer T5
Capture
CAPIN
GPT2 CAPREL
General purpose timer unit
Interrupt
Request
Interrupt
Request
T6IN
CPU Clock
2n n=2...9
T6EUD
T6
Mode
Control
Reload
GPT2 Timer T6
U/D
Toggle FF
T60TL
Interrupt
Request
T6OUT to CAPCOM
Timers
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
63/180
PWM modules ST10F271B/ST10F271E
Two pulse width modulation modules are available on ST10F271: standard PWM0 and
XBus PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. The
Table 38
Table 39
show the PWM frequencies for different
resolutions. The level of the output signals is selectable and the PWM modules can generate interrupt requests.
Figure 12.
Block diagram of PWM module
PPx Period Register *
Match
Comparator
Clock 1
Clock 2
Input
Control
Run
PTx *
16-bit Up/Down Counter
Comparator
Shadow Register
Up/Down/
Clear Control
Match
Output Control
Enable
POUTx
Write Control
* User readable / writeable register
PWx Pulse Width Register *
Table 38.
PWM unit frequencies and resolutions at 40 MHz CPU clock
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit
39.1 kHz 9.77 kHz 2.44Hz
CPU Clock/1
CPU
Clock/64
Mode 1
25ns
1.6
µ s
Resolution
CPU Clock/1
CPU
Clock/64
25ns
1.6
µ s
156.25 kHz
2.44 kHz
8-bit
78.12 kHz
1.22 kHz
610Hz
10-bit
19.53 kHz
305.17Hz
152.6Hz
12-bit
4.88 kHz
76.29Hz
38.15Hz
14-bit
1.22 kHz
19.07Hz
16-bit
610Hz
9.54Hz
16-bit
305.2Hz
4.77Hz
Table 39.
PWM unit frequencies and resolutions at 64 MHz CPU clock
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit Obsolete Product(s) - Obsolete Product(s)
CPU Clock/1 15.6ns
250 kHz 62.5 kHz 15.63 kHz 3.91Hz
977Hz
1.0
µ s 3.91 kHz 976.6Hz
244.1Hz
61.01Hz
15.26Hz
Mode 1
CPU Clock/1
CPU
Clock/64
Resolution
15.6ns
1.0
µ s
8-bit
125 kHz
1.95 kHz
10-bit
31.25 kHz
488.28Hz
12-bit
7.81 kHz
122.07Hz
14-bit
1.95 kHz
30.52Hz
16-bit
488.3Hz
7.63Hz
64/180
ST10F271B/ST10F271E Parallel ports
13.1 Introduction
The ST10F271 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications.
●
●
●
●
●
●
ST10F271 has nine groups of I/O lines gathered as follows:
● Port 0 is a two time 8-bit port named P0L (Low as less significant byte) and P0H (high as most significant byte)
Port 1 is a two time 8-bit port named P1L and P1H
Port 2 is a 16-bit port
Port 3 is a 15-bit port (P3.14 line is not implemented)
Port 4 is a 8-bit port
Port 5 is a 16-bit port input only
Port 6, Port 7 and Port 8 are 8-bit ports
These ports may be used as general purpose bidirectional input or output, software controlled with dedicated registers.
For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bitwise) for push-pull or open drain operation using ODPx registers.
The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. The threshold is selected with PICON and XPICON registers control bits.
A write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A readmodify-write operation reads the value of the pin, modifies it, and writes it back to the output latch.
Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin.
I/O lines support an alternate function which is detailed in the following description of each port.
Obsolete Product(s) - Obsolete Product(s)
Some of the I/O ports of ST10F271 support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function.
This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx.
65/180
Parallel ports ST10F271B/ST10F271E
The standard inputs of the ST10F271 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds.
The Port Input Control registers PICON and XPICON are used to select these thresholds for each Byte of the indicated ports, this means the 8-bit ports P0L, P0H, P1L, P1H, P4, P7 and
P8 are controlled by one bit each while ports P2, P3 and P5 are controlled by two bits each.
All options for individual direction and output mode control are available for each pin, independent of the selected input threshold.
13.3 Alternate port functions
●
●
Each port line has one associated programmable alternate input or output function.
● PORT0 and PORT1 may be used as address and data lines when accessing external memory. Besides, PORT1 provides also:
– Input capture lines
– 8 additional analog input channels to the A/D converter
●
●
Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM0 module, of the PWM1 module and of the ASC1.
Port 2 is also used for fast external interrupt inputs and for timer 7 input.
Port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT).
● Port 4 outputs the additional segment address bit A23...A16 in systems where more than 64 Kbytes of memory are to be access directly. In addition, CAN1, CAN2 and I
2
C lines are provided.
Port 5 is used as analog input channels of the A/D converter or as timer control signals.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals and the SSC1 lines.
If the alternate output function of a pin is to be used, the direction of this pin must be programmed for output (DPx.y=‘1’), except for some signals that are used directly after reset and are configured automatically. Otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. The respective port latch should hold a
‘1’, because its output is ANDed with the alternate output data (except for PWM output
Obsolete Product(s) - Obsolete Product(s)
If the alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y=‘0’) if an external device is driving the pin. The input direction is the default Obsolete Product(s) - Obsolete Product(s) direction for this pin to output. In this case, the pin reflects the state of the port output latch.
Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch.
On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin.
66/180
ST10F271B/ST10F271E Parallel ports
This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function.
There are port lines, however, where the direction of the port line is switched automatically.
For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data.
Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled.
To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output.
There is one basic structure for all port lines with only an alternate input function. Port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode.
All port lines that are not used for these alternate functions may be used as general purpose
I/O lines.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
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A/D converter ST10F271B/ST10F271E
A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry.
The ST10F271B has 16 multiplexed input channels on Port 5.
The ST10F271E has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for a detailed description.
A different accuracy is guaranteed (Total Unadjusted Error) on Port 5 and Port 1 analog channels (with higher restrictions when overload conditions occur); in particular, Port 5 channels are more accurate than the Port 1 ones. Refer to
Chapter 24: Electrical characteristics
The A/D converter input bandwidth is limited by the achievable accuracy: supposing a maximum error of 0.5LSB (2mV) impacting the global TUE (TUE depends also on other causes), in worst case of temperature and process, the maximum frequency for a sine wave analog signal is around 7.5 kHz. Of course, to reduce the effect of the input signal variation on the accuracy down to 0.05LSB, the maximum input frequency of the sine wave shall be reduced to 800 Hz.
If static signal is applied during sampling phase, series resistance shall not be greater than
20k Ω (this taking into account eventual input leakage). It is suggested to not connect any capacitance on analog input pins, in order to reduce the effect of charge partitioning (and consequent voltage drop error) between the external and the internal capacitance: in case an RC filter is necessary the external capacitance must be greater than 10nF to minimize the accuracy impact.
Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than
16+8 analog input channels, the remaining channel inputs can be used as digital input port pins.
The A/D converter of the ST10F271 supports different conversion modes:
● Single channel single conversion : The analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT
● register.
Obsolete Product(s) - Obsolete Product(s)
Single channel continuous conversion : The analog level of the selected channel is repeatedly sampled and converted. The result of the conversion is stored in the ADDAT Obsolete Product(s) - Obsolete Product(s)
● Auto scan single conversion : The analog level of the selected channels are sampled once and converted. After each conversion the result is stored in the ADDAT register.
The data can be transferred to the RAM by interrupt software management or using the powerful Peripheral Event Controller (PEC) data transfer.
● Auto scan continuous conversion : The analog level of the selected channels are repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
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ST10F271B/ST10F271E A/D converter
●
● register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer.
Wait for ADDAT read mode : When using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated. Then, until the ADDAT register is read, the new result is stored in a temporary buffer and the conversion is on hold.
Channel injection mode : When using continuous modes, a selected channel can be converted in between without changing the current operating mode. The 10-bit data of the conversion are stored in ADRES field of ADDAT2. The current continuous mode remains active after the single conversion is completed.
A full calibration sequence is performed after a reset. This full calibration lasts up to 40.630
CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation.
No conversion can be performed during this time: the bit ADBSY shall be polled to verify when the calibration is over, and the module is able to start a convertion.
Obsolete Product(s) - Obsolete Product(s)
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Serial channels ST10F271B/ST10F271E
Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by up to four serial interfaces: two asynchronous / synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial channel (SSC0 and SSC1). Dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning. For transmission, reception and erroneous reception, separate interrupt vectors are provided for ASC0 and SSC0 serial channel. A more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and
SSC1 (XBus mapped).
15.1 Asynchronous / synchronous serial interfaces
The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F271 and other microcontrollers, microprocessors or external peripherals.
15.2 ASCx in asynchronous mode
In asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop bits can be selected. Parity framing and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. Fullduplex communication up to 2M Bauds (at 64 MHz of f
CPU
) is supported in this mode.
Table 40.
ASC asynchronous baud rates by reload value and deviation errors (f
CPU
= 40 MHz)
S0BRS = ‘0’, f
CPU
= 40 MHz S0BRS = ‘1’, f
CPU
= 40 MHz
Baud Rate (Baud) Deviation Error
Reload Value
(hex)
Baud Rate (Baud) Deviation Error
Reload Value
(hex)
1 250 000
112 000
56 000
38 400
19 200
0.0% / 0.0%
+1.5% / -7.0%
+1.5% / -3.0%
+1.7% / -1.4%
+0.2% / -1.4%
0000 / 0000
000A / 000B
0015 / 0016
001F / 0020
0040 / 0041
833 333
112 000
56 000
38 400
19 200
0.0% / 0.0%
+6.3% / -7.0%
+6.3% / -0.8%
+3.3% / -1.4%
+0.9% / -1.4%
0000 / 0000
0006 / 0007
000D / 000E
0014 / 0015
002A / 002B
9 600
4 800
+0.2% / -0.6%
+0.2% / -0.2%
0081 / 0082
0103 / 0104
9 600
4 800
+0.9% / -0.2%
+0.4% / -0.2%
0055 / 0056
00AC / 00AD
2 400
1 200
+0.2% / 0.0%
0.1% / 0.0%
0207 / 0208
0410 / 0411
2 400
1 200
+0.1% / -0.2%
+0.1% / -0.1%
015A / 015B
02B5 / 02B6
600 0.0% / 0.0% 0822 / 0823 600 +0.1% / 0.0% 056B / 056C
300
153
0.0% / 0.0%
0.0% / 0.0%
1045 / 1046
1FE8 / 1FE9
300
102
0.0% / 0.0%
0.0% / 0.0%
0AD8 / 0AD9
1FE8 / 1FE9
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ST10F271B/ST10F271E Serial channels
Table 41.
ASC asynchronous baud rates by reload value and deviation errors (f
CPU
= 64 MHz)
S0BRS = ‘0’, f
CPU
= 64 MHz S0BRS = ‘1’, f
CPU
= 64 MHz
Baud Rate (Baud) Deviation Error
2 000 000
112 000
56 000
38 400
19 200
9 600
4 800
2 400
1 200
600
300
245
0.0% / 0.0%
+1.5% / -7.0%
+1.5% / -3.0%
+1.7% / -1.4%
+0.2% / -1.4%
+0.2% / -0.6%
+0.2% / -0.2%
+0.2% / 0.0%
0.1% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
Reload Value
(hex)
Baud Rate (Baud) Deviation Error
0000 / 0000
0010 / 0011
0022 / 0023
0033 / 0034
0067 / 0068
00CF / 00D0
019F / 01A0
0340 / 0341
0681 / 0682
0D04 / 0D05
1A09 / 1A0A
1FE2 / 1FE3
1 333 333
112 000
56 000
38 400
19 200
9 600
4 800
2 400
1 200
600
300
163
0.0% / 0.0%
+6.3% / -7.0%
+6.3% / -0.8%
+3.3% / -1.4%
+0.9% / -1.4%
+0.9% / -0.2%
+0.4% / -0.2%
+0.1% / -0.2%
+0.1% / -0.1%
+0.1% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
Reload Value
(hex)
0000 / 0000
000A / 000B
0016 / 0017
0021 / 0022
0044 / 0045
0089 / 008A
0114 / 0115
022A / 015B
0456 / 0457
08AD / 08AE
115B / 115C
1FF2 / 1FF3
Note:
The deviation errors given in the Table 40 and
Table 41
are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency).
15.3 ASCx in synchronous mode
In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F271. Half-duplex communication up to 8M Baud (at 40 MHz of f
CPU
) is possible in this mode.
Table 42.
ASC synchronous baud rates by reload value and deviation errors (f
CPU
= 40 MHz)
S0BRS = ‘0’, f
CPU
= 40 MHz S0BRS = ‘1’, f
CPU
= 40 MHz
Baud Rate (Baud) Deviation Error
Reload Value
(hex)
Baud Rate (Baud) Deviation Error
Reload Value
(hex)
5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000
112 000
56 000
+1.5% / -0.8%
+0.3% / -0.8%
002B / 002C
0058 / 0059
112 000
56 000
+2.6% / -0.8%
+0.9% / -0.8%
001C / 001D
003A / 003B
38 400
19 200
+0.2% / -0.6%
+0.2% / -0.2%
0081 / 0082
0103 / 0104
38 400
19 200
+0.9% / -0.2%
+0.4% / -0.2%
0055 / 0056
00AC / 00AD
9 600 +0.2% / 0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015A / 015B
4 800
2 400
1 200
+0.1% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0410 / 0411
0822 / 0823
1045 / 1046
4 800
2 400
1 200
+0.1% / -0.1%
+0.1% / 0.0%
0.0% / 0.0%
02B5 / 02B6
056B / 056C
0AD8 / 0AD9
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Serial channels ST10F271B/ST10F271E
Table 42.
ASC synchronous baud rates by reload value and deviation errors (f
CPU
= 40 MHz)
S0BRS = ‘0’, f
CPU
= 40 MHz S0BRS = ‘1’, f
CPU
= 40 MHz
Baud Rate (Baud) Deviation Error
900
612
0.0% / 0.0%
0.0% / 0.0%
Reload Value
(hex)
15B2 / 15B3
1FE8 / 1FE9
Baud Rate (Baud) Deviation Error
600
407
0.0% / 0.0%
0.0% / 0.0%
Reload Value
(hex)
15B2 / 15B3
1FFD / 1FFE
Table 43.
ASC synchronous baud rates by reload value and deviation errors (f
CPU
= 64 MHz)
S0BRS = ‘0’, f
CPU
= 64 MHz S0BRS = ‘1’, f
CPU
= 64 MHz
Baud Rate (Baud) Deviation Error
8 000 000
112 000
56 000
38 400
19 200
9 600
4 800
2 400
1 200
977
0.0% / 0.0%
+0.6% / -0.8%
+0.6% / -0.1%
+0.2% / -0.3%
+0.2% / -0.1%
+0.0% / -0.1%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
Reload Value
(hex)
0000 / 0000
0046 / 0047
008D / 008E
00CF / 00D0
019F / 01A0
0340 / 0341
0681 / 0682
0D04 / 0D05
1A09 / 1A0A
1FFB / 1FFC
Baud Rate (Baud) Deviation Error
5 333 333
112 000
56 000
38 400
19 200
9 600
4 800
2 400
1 200
900
652
0.0% / 0.0%
+1.3% / -0.8%
+0.3% / -0.8%
+0.6% / -0.1%
+0.3% / -0.1%
+0.1% / -0.1%
0.0% / -0.1%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
Reload Value
(hex)
0000 / 0000
002E / 002F
005E / 005F
0089 / 008A
0114 / 0115
022A / 022B
0456 / 0457
08AD / 08AE
115B / 115C
1724 / 1725
1FF2 / 1FF3
Note:
The deviation errors given in the Table 42 and
Table 43
are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency)
15.4 High speed synchronous serial interfaces
The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible highspeed serial communication between the ST10F271 and other microcontrollers, microprocessors or external peripherals.
The SSCx supports full-duplex and half-duplex synchronous communication. The serial Obsolete Product(s) - Obsolete Product(s) external master (slave mode). Data width, shift direction, clock polarity and phase are
Obsolete Product(s) - Obsolete Product(s)
This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit Baud rate generator provides the SSCx with a separate serial clock signal. The serial channel SSCx has its own dedicated 16-bit Baud rate generator with
16-bit reload capability, allowing Baud rate generation independent from the timers.
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ST10F271B/ST10F271E Serial channels
Table 44
Table 45
list some possible Baud rates against the required reload values and the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is anyway limited to 8Mbaud.
Table 44.
SSC synchronous baud rate and reload values (f
CPU
= 40 MHz)
Baud Rate Bit Time Reload Value
--0000h Reserved
Can be used only with f
CPU
= 32 MHz (or lower)
6.6M Baud
5M Baud
2.5M Baud
1M Baud
100K Baud
10K Baud
1K Baud
306 Baud
---
150ns
200ns
400ns
1 µ s
10 µ s
100 µ s
1ms
3.26ms
0001h
0002h
0003h
0007h
0013h
00C7h
07CFh
4E1Fh
FF4Eh
Table 45.
SSC synchronous baud rate and reload values (f
CPU
= 64 MHz)
Baud Rate Bit Time Reload Value
Reserved
Can be used only with f
CPU
= 32 MHz (or lower)
Can be used only with f
CPU
= 48 MHz (or lower)
8M Baud
4M Baud
1M Baud
100K Baud
10K Baud
1K Baud
---
---
---
125ns
250ns
1 µ s
10 µ s
100 µ s
1ms
0000h
0001h
0002h
0003h
0007h
001Fh
013Fh
0C7Fh
7CFFh
489 Baud 2.04ms
FF9Eh
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I2C interface ST10F271B/ST10F271E
The integrated I
2
C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I
2
C Bus specification. The I
2
C Module can operate in slave mode, in master mode or in multi-master mode. It can receive and transmit data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s
(both Standard and Fast I
2
C bus modes are supported).
The module can generate three different types of interrupt:
●
●
●
Requests related to bus events, like start or stop events, arbitration lost, etc.
Requests related to data transmission
Requests related to data reception
These requests are issued to the interrupt controller by three different lines, and identified as
Error, Transmit, and Receive interrupt lines.
When the I
2
C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and
P4.7 (where SCL and SDA are respectively mapped as alternate functions) are automatically configured as bidirectional open-drain: the value of the external pull-up resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin configuration.
When the I
2
C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4.
The speed of the I
2
C interface may be selected between Standard mode (0 to 100 kHz) and
Fast I
2
C mode (100 to 400 kHz).
Obsolete Product(s) - Obsolete Product(s)
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ST10F271B/ST10F271E CAN modules
Note:
The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active). It is based on the C-CAN specification.
Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.
Because of duplication of the CAN controllers, the following adjustments are to be considered:
● Same internal register addresses of both CAN controllers, but with base addresses differing in address bit A8; separate chip select for each CAN module. Refer to
Chapter 4: Memory organization on page 22
.
● The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin.
●
●
The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin.
Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS interrupt lines together with other X-Peripherals sharing the four vectors.
●
●
The CAN modules must be selected with corresponding CANxEN bit of XPERCON register before the bit XPEN of SYSCON register is set.
The reset default configuration is: CAN1 enabled, CAN2 disabled.
If one or both CAN modules is used, Port 4 cannot be programmed to output all 8 segment address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line).
It is possible that both CAN controllers are working on the same CAN bus, supporting together up to 64 message objects. In this configuration, both receive signals and both transmit signals are linked together when using the same CAN transceiver. This configuration is especially supported by providing open drain outputs for the CAN1_Txd and
CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4: in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with
P4.7 (transmit lines configured to be configured as Open-Drain).
The user is also allowed to map internally both CAN modules on the same pins P4.5 and
P4.6. In this way, P4.4 and P4.7 may be used either as general purpose I/O lines, or used Obsolete Product(s) - Obsolete Product(s) register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON register.
Obsolete Product(s) - Obsolete Product(s)
Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F271 is able to support these two cases.
75/180
CAN modules ST10F271B/ST10F271E
Single CAN bus
The single CAN Bus multiple interfaces configuration may be implemented using two CAN
Figure 13
Figure 13.
Connection to single CAN bus via separate CAN transceivers
XMISC.CANPAR = 0
CAN1
RX TX
CAN2
RX TX
P4.5
CAN
P4.6
Transceiver
P4.4
P4.7
CAN
Transceiver
CAN_H
CAN_L
CAN bus
The ST10F271 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in
Figure 14
Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment.
Figure 14.
Connection to single CAN bus via common CAN transceivers
XMISC.CANPAR = 0
CAN1
RX TX
CAN2
RX TX
+5V
2.7kW
P4.5
P4.6
OD
P4.4
P4.7
OD
CAN
Transceiver
CAN_H
CAN bus
OD = Open Drain Output
CAN_L
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
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ST10F271B/ST10F271E CAN modules
Multiple CAN bus
The ST10F271 provides two CAN interfaces to support such kind of bus configuration as shown in
Figure 15
.
Figure 15.
Connection to two different CAN buses (e.g. for gateway application)
XMISC.CANPAR = 0
CAN1
RX TX
CAN2
RX TX
P4.5
CAN
P4.6
Transceiver
P4.4
P4.7
CAN
Transceiver
CAN_H
CAN_L
CAN bus 1 CAN bus 2
CAN_H
CAN_L
Parallel Mode
In addition to previous configurations, a parallel mode is supported. This is shown in
Figure 16
.
Figure 16.
Connection to one CAN bus with internal Parallel Mode enabled
XMISC.CANPAR = 1
(Both CAN enabled)
CAN1
RX TX
CAN2
RX TX
CAN_L
P4.5
P4.6
CAN
Transceiver
P4.4
P4.7
CAN bus
77/180
ST10F271B/ST10F271E Real time clock
18 Real time clock
●
●
●
●
The Real Time Clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can be kept on running even in Idle or Power down mode (if enabled to). Registers access is implemented onto the XBUS. This module is designed with the following characteristics:
Generation of the current time and date for the system
Cyclic time based interrupt, on Port2 external interrupts every ’RTC basic clock tick’ and after
n
’RTC basic clock ticks’ (
n
is programmable) if enabled
58-bit timer for long term measurement
Capability to exit the ST10 chip from Power down mode (if PWDCFG of SYSCON set) after a programmed delay
The real time clock is based on two main blocks of counters. The first block is a prescaler which generates a basic reference clock (for example a 1 second period). This basic reference clock is coming out of a 20-bit DIVIDER. This 20-bit counter is driven by an input clock derived from the on-chip CPU clock, pre-divided by a 1/64 fixed counter. This 20-bit counter is loaded at each basic reference clock period with the value of the 20-bit
PRESCALER register. The value of the 20-bit RTCP register determines the period of the basic reference clock.
A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The second block of the RTC is a 32-bit counter that may be initialized with the current system time. This counter is driven with the basic reference clock signal. In order to provide an alarm function the contents of the counter is compared with a 32-bit alarm register. The alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI), may be generated when the value of the counter matches the alarm register.
The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external interrupt via EXISEL register of port 2 and wake-up the ST10 chip when running power down mode. Using the RTCOFF bit of RTCCON register, the user may switch off the clock oscillator when entering the power down mode.
The last function implemented in the RTC is to switch off the main on-chip oscillator and the
32 kHz on chip oscillator if the ST10 enters the Power Down mode, so that the chip can be fully switched off (if RTC is disabled).
At power on, and after Reset phase, if the presence of a 32 kHz oscillation on XTAL3 /
XTAL4 pins is detected, then the RTC counter is driven by this low frequency reference clock: when Power Down mode is entered, the RTC can either be stopped or left running, and in both the cases the main oscillator is turned off, reducing the power consumption of Obsolete Product(s) - Obsolete Product(s) reference oscillator. This is valid also if Stand-by mode is entered (switching off the main
Obsolete Product(s) - Obsolete Product(s)
STBY oscillator drives the RTC counter, and since it is powered by the main power supply, it cannot be maintained running in Stand-by mode, while in Power Down mode the main oscillator is maintained running to provide the reference to the RTC module (if not disabled).
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ST10F271B/ST10F271E Watchdog timer
The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time.
The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed.
Therefore, the chip start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset.
Each of the different reset sources is indicated in the WDTCON register:
●
●
●
Watchdog Timer Reset in case of an overflow
Software Reset in case of execution of the SRST instruction
Short, Long and Power-On Reset in case of hardware reset (and depending of reset pulse duration and RPD pin configuration)
The indicated bits are cleared with the EINIT instruction. The source of the reset can be identified during the initialization phase.
The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high
Byte of the watchdog timer register can be set to a pre-specified reload value (stored in
WDTREL).
Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced
The
Table 46
Table 47
show the watchdog time range for 40 MHz and 64 MHz CPU
clock respectively.
Table 46.
WDTREL reload value (f
CPU
= 40 MHz)
Prescaler for f
CPU
= 40 MHz
Reload value in WDTREL
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)
FFh
00h
12.8
µ s
3.277ms
819.2
µ s
209.7ms
Table 47.
WDTREL reload value (f
CPU
= 64 MHz)
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)
Obsolete Product(s) - Obsolete Product(s)
00h 2.048ms
131.1ms
79/180
System reset ST10F271B/ST10F271E
System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in
Table 48
.
Table 48.
Reset event definition
Reset Source
Power-on reset
Asynchronous Hardware reset
Synchronous Long Hardware reset
Synchronous Short Hardware reset
Watchdog Timer reset
Software reset
Flag
PONR
LHWR
SHWR
WDTR
SWR
RPD
Status
Low
Low
High
High
3)
3)
Conditions
Power-on t
RSTIN
>
1) t
RSTIN
> (1032 + 12) TCL + max(4 TCL,
500ns) t
RSTIN
> max(4 TCL, 500ns) t
RSTIN
≤
500ns)
WDT overflow
SRST instruction execution
1)
RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
2)
for more details on minimum reset pulse duration.
3)
The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to
On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes shorter than 50ns. On the other side, a valid pulse shall be longer than 500ns to grant that
ST10 recognizes a reset command. In between 50ns and 500ns a pulse can either be filtered or recognized as valid, depending on the operating conditions and process variations.
For this reason all minimum durations mentioned in this Chapter for the different kind of reset events shall be carefully evaluated taking into account of the above requirements.
In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input reset pulse duration, the operating frequency is a key factor. Examples:
● For a CPU clock of 64 MHz, 4 TCL is 31.25ns, so it would be filtered. In this case the Obsolete Product(s) - Obsolete Product(s)
● For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula
Obsolete Product(s) - Obsolete Product(s)
80/180
ST10F271B/ST10F271E System reset
Note:
An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the ST10F271 is immediately (after the input filter delay) forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts all internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins.
If an asynchronous reset occurs during a read or write phase in internal memories, the content of the memory itself could be corrupted: to avoid this, synchronous reset usage is strongly recommended.
Power-on reset
Note:
The asynchronous reset must be used during the power-on of the device.
Depending on crystal or resonator frequency, the on-chip oscillator needs about 1ms to 10ms to stabilize (Refer to Electrical Characteristics Section), with an already stable V
DD
. The logic of the ST10F271 does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on Port0 is settled.
At Power-on it is important to respect some additional constraints introduced by the start-up phase of the different embedded modules.
In particular the on-chip voltage regulator needs at least 1ms to stabilize the internal 1.8V for the core logic: this time is computed from when the external reference (V
DD
) becomes stable (inside specification range, that is at least 4.5V). This is a constraint for the application hardware (external voltage regulator): the RSTIN pin assertion shall be extended to guarantee the voltage regulator stabilization.
A second constraint is imposed by the embedded FLASH. When booting from internal memory, starting from RSTIN releasing, it needs a maximum of 1ms for its initialization: before that, the internal reset (RST signal) is not released, so the CPU does not start code execution in internal memory.
This is not true if external memory is used (pin EA held low during reset phase). In this case, once RSTIN pin is released, and after few CPU clock (Filter delay plus 3...8 TCL), the internal reset signal RST is released as well, so the code execution can start immediately after. Obviously, an eventual access to the data in internal Flash is forbidden before its initialization phase is completed: an eventual access during starting phase will return FFFFh
(just at the beginning), while later 009Bh (an illegal opcode trap can be generated).
At Power-on, the RSTIN pin shall be tied low for a minimum time that includes also the startup time of the main oscillator (t
STUP
PSUP
= 200 µ
= 1ms for resonator, 10ms for crystal) and PLL
Obsolete Product(s) - Obsolete Product(s)
RSTIN pin could be released before the main oscillator and PLL are stable to recover some time in the start-up phase (FLASH initialization only needs stable V
18 stable system clock since an internal dedicated oscillator is used).
, but does not need Obsolete Product(s) - Obsolete Product(s)
Warning: It is recommended to provide the external hardware with a current limitation circuitry. This is necessary to avoid permanent damages of the device during the power-on transient, when the capacitance on V
18
pin is charged. For the on-chip voltage regulator functionality 10nF are
81/180
System reset
Note:
ST10F271B/ST10F271E sufficient: anyway, a maximum of 100nF on V
18
pin should not generate problems of over-current (higher value is allowed if current is limited by the external hardware).
External current limitation is anyway recommended also to avoid risks of damage in case of temporary short between
V
18
and ground: the internal 1.8V drivers are sized to drive currents of several tens of Ampere, so the current shall be limited by the external hardware. The limit of current is imposed by power dissipation considerations (Refer to
Electrical Characteristics Section).
In next Figures
17
and
18
Asynchronous Power-on timing diagrams are reported, respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded FLASH module when selected.
Never power the device without keeping RSTIN pin grounded: the device could enter in unpredictable states, risking also permanent damages.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
82/180
ST10F271B/ST10F271E System reset
Figure 17.
Asynchronous power-on RESET (EA = 1)
≤ (for resonator oscillation + PLL stabilization)
≤ (for crystal oscillation + PLL stabilization)
≥
1 ms (for on-chip VREG stabilization)
V
DD
≤
2 TCL
V
18
XTAL1
RPD
...
RSTIN
RSTF
(After Filter)
P0[15:13]
≤
≥ 50 ns
500 ns
3..4 TCL transparent not t.
not t.
P0[12:2] transparent not t.
P0[1:0]
IBUS-CS
(Internal)
FLARST
RST not transparent not t.
7 TCL
Latching point of Port0 for system start-up configuration
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
83/180
System reset ST10F271B/ST10F271E
Figure 18.
Asynchronous power-on RESET (EA = 0)
≥
1.2 ms (for resonator oscillation + PLL stabilization)
≥ 10.2 ms (for crystal oscillation + PLL stabilization)
≥ 1 ms (for on-chip VREG stabilization)
V
DD
V
18
XTAL1
RPD
RSTIN
RSTF
(After Filter)
P0[15:13]
P0[12:2]
P0[1:0]
ALE
...
3..8 TCL
1)
≥ 50 ns
500 ns
3..4 TCL transparent transparent not transparent not t.
not t.
not t.
8 TCL
RST
Latching point of Port0 for system start-up configuration
Note 1. 3 to 8 TCL depending on clock source selection.
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figures
30
31
32
It occurs when RSTIN is low and RPD is detected (or becomes) low as well.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
84/180
ST10F271B/ST10F271E System reset
Figure 19.
Asynchronous hardware RESET (EA = 1)
1) ≤
2 TCL
RPD
≤
≥
50 ns
500 ns
RSTIN
RSTF
(After Filter)
P0[15:13] not transparent
P0[12:2] not transparent
≤
≥ 50 ns
500 ns
3..4 TCL transparent transparent not t.
not t.
not t.
P0[1:0]
IBUS-CS
(internal)
FLARST not transparent not t.
7 TCL
RST
Latching point of Port0 for system start-up configuration
Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed)
Longer than 500ns to take into account of Input Filter on RSTIN pin
Obsolete Product(s) - Obsolete Product(s)
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85/180
System reset
Figure 20.
Asynchronous hardware RESET (EA = 0)
1)
RPD
≤
≥
50 ns
500 ns
RSTIN
RSTF
(After Filter)
P0[15:13] not transparent
P0[12:2] not transparent
P0[1:0]
ALE
ST10F271B/ST10F271E
3..8 TCL
2) transparent transparent
≤
≥ 50 ns
500 ns
3..4 TCL not t.
not t.
not transparent not t.
8 TCL
RST
Latching point of Port0 for system start-up configuration
Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed)
Longer than 500ns to take into account of Input Filter on RSTIN pin
Note 2. 3 to 8 TCL depending on clock source selection.
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts: as already mentioned, if internal
FLASH is used, the restarting occurs after the embedded FLASH initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F271 starts program execution from memory location
00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in
Figure 19
Figure 20
20.3 Synchronous reset (warm reset)
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to
Section 20.1
for Obsolete Product(s) - Obsolete Product(s)
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are cancelled and the current internal access cycle if any is completed. External bus cycle is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set by software. Note that this bit is always cleared on power-on or after a reset sequence.
86/180
ST10F271B/ST10F271E System reset
Short and long synchronous reset
Once the first maximum 16 TCL are elapsed (4+12 TCL), the internal reset sequence starts.
It is 1024 TCL cycles long: at the end of it, and after other 8 TCL the level of RSTIN is sampled (after the filter, see RSTF in the drawings): if it is already at high level, only Short
Chapter 19: Watchdog timer
for details on reset flags); if it is recognized still low, the Long reset is flagged as well. The major difference between Long and Short reset is that during the Long reset, also P0(15:13) become transparent, so it is possible to change the clock options.
Warning: In case of a short pulse on RSTIN pin, and when Bidirectional reset is enabled, the RSTIN pin is held low by the internal circuitry. At the end of the 1024 TCL cycles, the RTSIN pin is released, but due to the presence of the input analog filter the internal input reset signal (RSTF in the drawings) is released later (from 50 to 500ns). This delay is in parallel with the additional 8 TCL, at the end of which the internal input reset line (RSTF) is sampled, to decide if the reset event is Short or
Long. In particular:
Note:
●
●
If 8 TCL > 500ns (F
CPU
< 8 MHz), the reset event is always recognized as Short
If 8 TCL < 500ns (F
CPU
> 8 MHz), the reset event could be recognized either as Short or Long, depending on the real filter delay (between 50 and 500ns) and the CPU frequency (RSTF sampled High means Short reset, RSTF sampled Low means Long reset). Note that in case a Long Reset is recognized, once the 8 TCL are elapsed, the
P0(15:13) pins becomes transparent, so the system clock can be re-configured. The port returns not transparent 3-4 TCL after the internal RSTF signal becomes high.
The same behavior just described, occurs also when unidirectional reset is selected and
RSTIN pin is held low till the end of the internal sequence (exactly 1024 TCL + max 16 TCL) and released exactly at that time.
When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns); so it might happen that a short reset pulse is not filtered by the analog input filter, but on the other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would generate a FLASH reset but not a system reset. In this condition, the FLASH answers always with FFFFh, which leads to an illegal opcode and consequently a trap event is generated.
Exit from synchronous reset state
Obsolete Product(s) - Obsolete Product(s)
The reset sequence is extended until RSTIN level becomes high. Besides, it is internally prolonged by the FLASH initialization when EA=1 (internal memory selected). Then, the Obsolete Product(s) - Obsolete Product(s)
WR/WRL pins are driven to their inactive level. The ST10F271 starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of synchronous reset sequence are summarized
21
22
where a Short Reset event is shown, with particular highlighting on the fact that it can degenerate into Long Reset: the two figures show the behavior when booting
from internal or external memory respectively. Figures
23
24
typical synchronous Long Reset, again when booting from internal or external memory.
87/180
System reset ST10F271B/ST10F271E
Synchronous reset and RPD pin
Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a
Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance
(if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage level on RPD pin reaches the input low threshold (around 2.5V), the reset event becomes immediately asynchronous. In case of hardware reset (short or long) the situation goes immediately to the one illustrated in
Figure 19
. There is no effect if RPD comes again above the input threshold: the asynchronous reset is completed coherently. To grant the normal completion of a synchronous reset, the value of the capacitance shall be big enough to maintain the voltage on RPD pin sufficient high along the duration of the internal reset sequence.
For a Software or Watchdog reset events, an active synchronous reset is completed regardless of the RPD status.
It is important to highlight that the signal that makes RPD status transparent under reset is the internal RSTF (after the noise filter).
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
88/180
ST10F271B/ST10F271E
Figure 21.
Synchronous short / long hardware RESET (EA = 1)
4 TCL
4)
< 1032 TCL
RSTIN
RSTF
(After Filter)
≤
≥
50 ns
500 ns
1)
P0[15:13]
≤
≥
50 ns
500 ns
3)
≤
≥
50 ns
500 ns not transparent
≤ 2 TCL
P0[12:2] not t.
transparent
P0[1:0]
IBUS-CS
(Internal)
FLARST not transparent not t.
not t.
7 TCL
1024 TCL 8 TCL
RST
System reset
At this time RSTF is sampled HIGH or LOW so it is SHORT or LONG reset
RSTOUT
RPD
200
µ
A Discharge
2)
V
RPD
> 2.5V Asynchronous Reset not entered
Notes:
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software.
Bit BDRSTEN is cleared after reset.
4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1).
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
89/180
System reset ST10F271B/ST10F271E
Figure 22.
Synchronous short / long hardware RESET (EA = 0)
≤4 TCL5)
RSTIN
RSTF
(After Filter)
P0[15:13]
≥
50 ns
≤ 500 ns
1)
≥
50 ns
≤ 500 ns
4)
< 1032 TCL
≥
50 ns
≤ 500 ns not transparent
P0[12:2] not t.
transparent
P0[1:0] not transparent not t.
3..8 TCL3) not t.
8 TCL
ALE
1024 TCL 8 TCL
RST
At this time RSTF is sampled HIGH or LOW so it is SHORT or LONG reset
RSTOUT
RPD
200mA Discharge
2) VRPD > 2.5V Asynchronous Reset not entered
Notes:
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation) the asynchronous reset is then immediately entered.
3. 3 to 8 TCL depending on clock source selection.
4. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software.
Bit BDRSTEN is cleared after reset.
5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1).
Obsolete Product(s) - Obsolete Product(s)
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90/180
ST10F271B/ST10F271E
Figure 23.
Synchronous long hardware RESET (EA = 1)
2)
1024+8 TCL
RSTIN
RSTF
(After Filter)
≥
50 ns
500 ns
P0[15:13]
≥
50 ns
500 ns not transparent
≥
50 ns
500 ns
3..4 TCL transparent
≤
2 TCL not t.
System reset
P0[12:2]
P0[1:0]
IBUS-CS
(Internal)
FLARST not t.
transparent not transparent not t.
not t.
7 TCL
1024+8 TCL
RST
At this time RSTF is sampled LOW so it is definitely LONG reset
RSTOUT
RPD
200
µ
A Discharge
1)
V
RPD
> 2.5V Asynchronous Reset not entered
Notes:
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. Even if RPD returns above the threshold, the reset is defnitively taken as asynchronous.
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1).
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
91/180
System reset
Figure 24.
Synchronous long hardware RESET (EA = 0)
ST10F271B/ST10F271E
4 TCL
2)
12 TCL
RSTIN
RSTF
(After Filter)
≤
50 ns
P0[15:13]
≤
1024+8 TCL
50 ns not transparent
≤
50 ns
3..4 TCL transparent
P0[12:2]
P0[1:0]
ALE transparent
1024+8 TCL not t.
not t.
not transparent
3..8 TCL
3) not t.
8 TCL
RST
At this time RSTF is sampled LOW so it is LONG reset
RSTOUT
RPD
200 µ A Discharge
1)
V
RPD
> 2.5V Asynchronous Reset not entered
Notes:
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered.
2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1).
3. 3 to 8 TCL depending on clock source selection.
A software reset sequence can be triggered at any time by the protected SRST (software
Obsolete Product(s) - Obsolete Product(s) leave bootstrap loader mode, or on a hardware trap that reveals system failure.
Obsolete Product(s) - Obsolete Product(s)
P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits
P0.7...P0.2 are cleared (that is written at ‘1’).
A Software reset is always taken as synchronous: there is no influence on Software Reset behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected.
92/180
ST10F271B/ST10F271E System reset
Refer to next Figures
25
26
for unidirectional SW reset timing, and to Figures
27
28
29
20.5 Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after the programmed wait states.
When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared
(that is written at ‘1’).
A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected.
Refer to next Figures
25
26
for unidirectional SW reset timing, and to Figures
27
28
29
Figure 25.
SW / WDT unidirectional RESET (EA = 1)
RSTIN
≤
2 TCL
P0[15:13] not transparent transparent not t.
P0[12:8]
P0[7:2] not transparent
P0[1:0] not transparent not t.
7 TCL
IBUS-CS
(Internal)
Obsolete Product(s) - Obsolete Product(s)
1024 TCL
Obsolete Product(s) - Obsolete Product(s)
RSTOUT
93/180
System reset
Figure 26.
SW / WDT unidirectional RESET (EA = 0)
RSTIN
P0[15:13] not transparent
P0[12:8]
P0[7:2]
P0[1:0]
ALE transparent not transparent not transparent
1024 TCL
RST
RSTOUT
ST10F271B/ST10F271E not t.
not t.
8 TCL
As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed.
The Bidirectional Reset function is useful when external devices require a reset signal but cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialization. It is, for instance, the case of external memory running initialization routine before the execution of EINIT instruction.
Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It only can be enabled during the initialization routine, before EINIT instruction is completed.
When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal, for the duration of the internal reset sequence (synchronous/asynchronous hardware, synchronous software and synchronous watchdog timer resets). At the end of the internal reset sequence the pull down is released and: Obsolete Product(s) - Obsolete Product(s)
8 TCL periods after the internal reset sequence completion (refer to
Figure 21
● After a Software or Watchdog Bidirectional Reset, the device exits from reset. If RSTF remains still low for at least 4 TCL periods (minimum time to recognize a Short
Hardware reset) after the reset exiting (refer to
Figure 27
and
Figure 28
), the Software or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state.
94/180
ST10F271B/ST10F271E
Note:
System reset
The Bidirectional reset is not effective in case RPD is held low, when a Software or
Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset event is active and RPD becomes low, the RSTIN pin is immediately released, while the internal reset sequence is completed regardless of RPD status change (1024 TCL).
The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of
SYSCON is cleared). To be activated again it must be enabled during the initialization routine.
WDTCON flags
Similarly to what already highlighted in the previous section when discussing about Short reset and the degeneration into Long reset, similar situations may occur when Bidirectional reset is enabled. The presence of the internal filter on RSTIN pin introduces a delay: when
RSTIN is released, the internal signal after the filter (see RSTF in the drawings) is delayed, so it remains still active (low) for a while. It means that depending on the internal clock speed, a short reset may be recognized as a long reset: the WDTCON flags are set accordingly.
Besides, when either Software or Watchdog bidirectional reset events occur, again when the
RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal
(after the filter) remains low for a while, and depending on the clock frequency it is recognized high or low: 8TCL after the completion of the internal sequence, the level of
RSTF signal is sampled, and if recognized still low a Hardware reset sequence starts, and
WDTCON will flag this last event, masking the previous one (Software or Watchdog reset).
Typically, a Short Hardware reset is recognized, unless the RSTIN pin (and consequently internal signal RSTF) is sufficiently held low by the external hardware to inject a Long
Hardware reset. After this occurrence, the initialization routine is not able to recognize a
Software or Watchdog bidirectional reset event, since a different source is flagged inside
WDTCON register. This phenomenon does not occur when internal FLASH is selected during reset (EA = 1), since the initialization of the FLASH itself extend the internal reset duration well beyond the filter delay.
Next Figures
27
,
28
and
29
summarize the timing for Software and Watchdog Timer
Bidirectional reset events: In particular
Figure 29
shows the degeneration into Hardware reset.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
95/180
System reset
Figure 27.
SW / WDT bidirectional RESET (EA=1)
RSTIN
RSTF
(After Filter)
P0[15:13]
≤
≥
50 ns
500 ns
≤
≥
50 ns
500 ns not transparent
P0[12:8] transparent not transparent P0[7:2]
P0[1:0]
IBUS-CS
(Internal)
FLARST not transparent
1024 TCL
RST
RSTOUT
ST10F271B/ST10F271E not t.
≤
2 TCL not t.
7 TCL
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Obsolete Product(s) - Obsolete Product(s)
96/180
ST10F271B/ST10F271E
Figure 28.
SW / WDT bidirectional RESET (EA = 0)
RSTIN
RSTF
(After Filter)
P0[15:13]
≤
≥
50 ns
500 ns
P0[12:8]
P0[7:2]
P0[1:0]
ALE not transparent transparent not transparent not transparent
1024 TCL
RST
RSTOUT
≤
≥
50 ns
500 ns not t.
not t.
8 TCL
System reset
At this time RSTF is sampled HIGH so SW or WDT Reset is flagged in WDTCON
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
97/180
System reset ST10F271B/ST10F271E
Figure 29.
SW / WDT bidirectional RESET (EA=0) followed by a HW RESET
RSTIN
RSTF
(After Filter)
P0[15:13]
P0[12:8]
P0[7:2]
P0[1:0]
ALE
≤
≥
50 ns
500 ns not transparent transparent not transparent not transparent
≤
≥
50 ns
500 ns not t.
not t.
8 TCL
1024 TCL
RST
RSTOUT
At this time RSTF is sampled LOW so HW Reset is entered
Internal reset circuitry is described in
Figure 32
. The RSTIN pin provides an internal pull-up
resistor of 50k Ω to 250k Ω (The minimum reset time must be calculated using the lowest value).
It also provides a programmable (BDRSTEN bit of SYSCON register) pull-down to output internal reset state signal (synchronous reset, watchdog timer reset or software reset).
This bidirectional reset function is useful in applications where external devices require a reset signal but cannot be connected to RSTOUT pin.
This is the case of an external memory running codes before EINIT (end of initialization) instruction is executed. RSTOUT pin is pulled high only when EINIT is executed.
Obsolete Product(s) - Obsolete Product(s) capacitor at a typical rate of 200 µ A. If bit PWDCFG of SYSCON register is set, an internal
Obsolete Product(s) - Obsolete Product(s)
The simplest way to reset the ST10F271 is to insert a capacitor C1 between RSTIN pin and
V
SS
, and a capacitor between RPD pin and V
SS
(C0) with a pull-up resistor R0 between
RPD pin and V
DD
. The input RSTIN provides an internal pull-up device equalling a resistor of
50k Ω to 250k Ω (the minimum reset time must be determined by the lowest value). Select C1 that produce a sufficient discharge time to permit the internal or external oscillator and / or internal PLL and the on-chip voltage regulator to stabilize.
98/180
ST10F271B/ST10F271E System reset
To ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during power-up. For this reason, it is recommended to connect the external R0-C0 circuit shown in Figure 30 to the RPD pin. On power-up, the logical low level on RPD pin forces an asynchronous hardware reset when RSTIN is asserted low. The external pull-up
R0 will then charge the capacitor C0. Note that an internal pull-down device on RPD pin is turned on when RSTIN pin is low, and causes the external capacitor (C0) to begin discharging at a typical rate of 100-200
µ
A. With this mechanism, after power-up reset, short low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted longer than the time needed for C0 to be discharged by the internal pull-down device, then the device is forced in an asynchronous reset. This mechanism insures recovery from very catastrophic failure.
Figure 30.
Minimum external reset circuitry
RSTOUT
RSTIN
+
C1
External Hardware a) Hardware
Reset
V
CC
R0
RPD
+
C0
ST10F271 b) For Power-up
Reset
(and Interruptible
Power Down mode)
Figure 30
is not adequate when the RSTIN pin is driven from the ST10F271 itself during software or watchdog triggered resets, because of the capacitor
C1 that will keep the voltage on RSTIN pin above V
IL
after the end of the internal reset sequence, and thus will trigger an asynchronous reset sequence.
Figure 31
shows an example of a reset circuit. In this example, R1-C1 external circuit is only used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up reset and to exit from Power Down mode. Diode D1 creates a wired-OR gate connection to the reset pin and may be replaced by open-collector Schmitt trigger buffer. Diode D2 provides a faster cycle time for repetitive power-on resets.
Obsolete Product(s) - Obsolete Product(s)
99/180
System reset ST10F271B/ST10F271E
Figure 31.
System reset circuit
V
DD
V
DD
R2
RSTIN
V
DD
R0
RPD
+
C0
ST10F271
D1
External Hardware o.d.
Open Drain Inverter
External
Reset Source
D2
R1
+
C1
Figure 32.
Internal (simplified) reset circuitry
EINIT Instruction
Clr
Q
Set
Reset State
Machine
Clock
Internal
Reset
Signal
Trigger
Clr
SRST instruction watchdog overflow
Reset Sequence
BDRSTEN
(512 CPU Clock Cycles)
V
DD
RSTOUT
RSTIN
V
DD
Asynchronous
Reset
From/to Exit
Powerdown
Circuit
Weak Pulldown
(~200 µ A) Obsolete Product(s) - Obsolete Product(s)
100/180
ST10F271B/ST10F271E System reset
20.8 Reset application examples
Figure 33
Figure 34
) provides additional examples of bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to
Figure 31
for the external circuit scheme).
Figure 33.
Example of software or watchdog bidirectional reset (EA = 1)
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101/180
System reset ST10F271B/ST10F271E
Figure 34.
Example of software or watchdog bidirectional reset (EA = 0)
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102/180
ST10F271B/ST10F271E System reset
A summary of the different reset events is reported in the table below.
Table 49.
Reset event
RSTIN
Event min max
WDTCON Flags
Power-on Reset
Hardware Reset
(Asynchronous)
Short Hardware
Reset
(Synchronous)
(1)
0 0 N Asynch.
0 1 N Asynch.
1 x x x x Y
0 0 N Asynch.
0 1 N Asynch.
0 0 Y Asynch.
0 1 Y Asynch.
1 0 N Synch.
1 1 N Synch.
1 0 Y Synch.
1 1 Y Synch.
1 0 N Synch.
1 ms (VREG)
1.2 ms
(Reson. + PLL)
10.2 ms
(Crystal + PLL)
1ms (VREG)
500ns
500ns
500ns
500ns
FORBIDDEN
-
NOT APPLICABLE
-
max (4 TCL, 500ns) max (4 TCL, 500ns)
-
-
-
1032 + 12 TCL + max(4 TCL, 500ns)
1032 + 12 TCL + max(4 TCL, 500ns)
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0 max (4 TCL, 500ns)
1032 + 12 TCL + max(4 TCL, 500ns)
Activated by internal logic for 1024 TCL max (4 TCL, 500ns)
1032 + 12 TCL + max(4 TCL, 500ns)
Activated by internal logic for 1024 TCL
1032 + 12 TCL + max(4 TCL, 500ns)
-
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1032 + 12 TCL +
1 1 N Synch.
max(4 TCL, 500ns)
-
-
0 1 1 1 0
Obsolete Product(s) - Obsolete Product(s)
Reset
1 0 Y Synch.
max(4 TCL, 500ns)
1032 + 12 TCL +
Activated by internal logic only for 1024 TCL
0 1 1 1 0
(Synchronous)
Obsolete Product(s) - Obsolete Product(s)
1032 + 12 TCL +
-
1 1 Y Synch.
max(4 TCL, 500ns)
0 1 1 1 0
Activated by internal logic only for 1024 TCL
103/180
System reset ST10F271B/ST10F271E
Table 49.
Reset event (continued)
RSTIN WDTCON Flags
Event min max
Software Reset
Watchdog Reset
(2)
(2) x 0 N Synch.
x 0 N Synch.
0 1 Y Synch.
1 1 Y Synch.
x 0 N Synch.
x 0 N Synch.
0 1 Y Synch.
Not activated
Not activated
Not activated
Activated by internal logic for 1024 TCL
Not activated
Not activated
Not activated
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1 1 Y Synch.
Activated by internal logic for 1024 TCL 0 0 0 1 1
1.
It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3
for details).
2.
When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently
The start-up configurations and some system features are selected on reset sequences as
Table 50
and
Figure 35
Table 50
describes what is the system configuration latched on PORT0 in the six different
Figure 35
summarizes the state of bits of PORT0 latched in RP0H, SYSCON,
BUSCON0 registers.
Table 50.
PORT0 latched configuration for the different reset events
PORT0
X: Pin is sampled
-: Pin is not sampled
Sample event
Software Reset X X X X X X X -
X X X X X X X -
Synchronous Short Hardware Reset X X X X X X X X X X X X X
Obsolete Product(s) - Obsolete Product(s)
X
Asynchronous Hardware Reset X X X X X X X X X X X X X X X X
Asynchronous Power-On Reset X X X X X X X X X X X X X X X X
104/180
ST10F271B/ST10F271E
Figure 35.
PORT0 bits latched into the different registers after reset
PORT0
H.3
H.2
H.1
H.0
L.7
H.7
H.6
H.5
H.4
CLKCFG SALSEL CSSEL WRC
L.6
BUSTYP
L.5
L.4
BSL
L.3
Res.
L.2
L.1
L.0
ADP EMU
System reset
RP0H
CLKCFG SALSEL CSSEL WRC
Bootstrap Loader Internal Control Logic
Clock
Generator
Port 4
Logic
Port 6
Logic
2
P0L.7
P0L.7
10
ROMEN BYTDIS
9 8
7
WRCFG
SYSCON
10
BUS
ACT0
ALE
CTL0
9 7 6
BTYP
BUSCON0
EA / VSTBY
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105/180
Power reduction modes
21 Power reduction modes
Note:
ST10F271B/ST10F271E
Three different power reduction modes with different levels of power reduction have been implemented in the ST10F271. In Idle mode only CPU is stopped, while peripheral still operate. In Power Down mode both CPU and peripherals are stopped. In Stand-by mode the main power supply (V
DD
) can be turned off while a portion of the internal RAM remains powered via V
STBY
dedicated power pin.
Idle and Power Down modes are software activated by a protected instruction and are terminated in different ways as described in the following sections.
Stand-by mode is entered simply removing V
DD
, holding the MCU under reset state.
All external bus actions are completed before Idle or Power Down mode is entered.
However, Idle or Power Down mode is
not
entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access.
Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped and the peripherals still run.
Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not, the instruction following the IDLE instruction will be executed after return from interrupt
(RETI) instruction, then the CPU resumes the normal program.
21.2 Power down mode
Power Down mode starts by running PWRDN protected instruction. Internal clock is stopped, all MCU parts are on hold including the watchdog timer. The only exception could be the Real Time Clock if opportunely programmed and one of the two oscillator circuits as a consequence (either the main or the 32 kHz on-chip oscillator).
When Real Time Clock module is used, when the device is in Power Down mode a reference clock is needed. In this case, two possible configurations may be selected by the user application according to the desired level of power reduction:
● A 32 kHz crystal is connected to the on-chip low-power oscillator (pins XTAL3 / XTAL4) and running. In this case the main oscillator is stopped when Power Down mode is entered, while the Real Time Clock continue counting using 32 kHz clock signal as reference. The presence of a running low-power oscillator is detected after the Power Obsolete Product(s) - Obsolete Product(s) reference for the Real Time Clock counter and it will be maintained forever (unless
Obsolete Product(s) - Obsolete Product(s)
● Only the main oscillator is running (XTAL1 / XTAL2 pins). In this case the main oscillator is not stopped when Power Down is entered, and the Real Time Clock continue counting using the main oscillator clock signal as reference.
There are two different operating Power Down modes: protected mode and interruptible mode.
106/180
ST10F271B/ST10F271E Power reduction modes
Note:
Before entering Power Down mode (by executing the instruction PWRDN), bit VREGOFF in
XMISC register must be set.
Leaving the main voltage regulator active during Power Down may lead to unexpected behavior (ex: CPU wake-up) and power consumption higher than what specified.
21.2.1 Protected power down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The Protected
Power Down mode is only activated if the NMI pin is pulled low when executing PWRDN instruction (this means that the PWRD instruction belongs to the NMI software routine). This mode is only deactivated with an external hardware reset on RSTIN pin.
21.2.2 Interruptible power down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is set.
The Interruptible Power Down mode is only activated if all the enabled Fast External
Interrupt pins are in their inactive level.
This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt request applied to one of the Fast External Interrupt pins, or with an interrupt generated by the Real Time Clock, or with an interrupt generated by the activity on CAN’s and I
2
C module interfaces. To allow the internal PLL and clock to stabilize, the RSTIN pin must be held low according the recommendations described in
Chapter 20: System reset on page 80
An external RC circuit must be connected to RPD pin, as shown in the
Figure 36
Figure 36.
External RC circuitry on RPD pin
ST10F271
V
DD
R0
220k Ω minimum
RPD
+
C0
1 µ F Typical
To exit Power Down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be asserted for at least 40ns.
Obsolete Product(s) - Obsolete Product(s)
In Stand-by mode, it is possible to turn off the main V
DD
provided that V
STBY
is available through the dedicated pin of the ST10F271.
Obsolete Product(s) - Obsolete Product(s)
To enter Stand-by mode it is mandatory to held the device under reset: once the device is under reset, the RAM is disabled (see XRAM2EN bit of XPERCON register), and its digital interface is frozen in order to avoid any kind of data corruption.
A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65V in Stand-by mode) to bias all those circuits that shall remain active: the portion of XRAM (16Kbytes for ST10F271E), the RTC counters and 32 kHz onchip oscillator amplifier.
107/180
Power reduction modes ST10F271B/ST10F271E
In normal running mode (that is when main V
DD
is on) the V
STBY
pin can be tied to V
SS during reset to exercise the EA functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with V
STBY
(see in particular the 32 kHz oscillator used in conjunction with Real Time Clock module), is granted by the active main
V
DD
.
It must be noted that Stand-by Mode can generate problems associated with the usage of different power supplies in CMOS systems; particular attention must be paid when the
ST10F271 I/O lines are interfaced with other external CMOS integrated circuits: if V
DD
of
ST10F271 becomes (for example in Stand-by Mode) lower than the output level forced by the I/O lines of these external integrated circuits, the ST10F271 could be directly powered through the inherent diode existing on ST10F271 output driver circuitry. The same is valid for ST10F271 interfaced to active/inactive communication buses during Stand-by mode: current injection can be generated through the inherent diode.
Furthermore, the sequence of turning on/off of the different voltage could be critical for the system (not only for the ST10F271 device). The device Stand-by mode current (I
STBY
) may vary while V
DD
to V
STBY
(and vice versa) transition occurs: some current flows between V
DD and V
STBY
pins. System noise on both V phenomenon.
DD
and V
STBY
can contribute to increase this
As already said, to enter Stand-by Mode XRAM2EN bit in the XPERCON Register must be cleared: this allows to freeze immediately the RAM interface, avoiding any data corruption.
As a consequence of a RESET event, the RAM Power Supply is switched to the internal low-voltage supply V
18SB
(derived from V
STBY
through the low-power voltage regulator).
The RAM interface will remain frozen until the bit XRAM2EN is set again by software initialization routine (at next exit from main V
DD
power-on reset sequence).
Since V
18
is falling down (as a consequence of V
DD
turning off), it can happen that the
XRAM2EN bit is no longer able to guarantee its content (logic “0”), being the XPERCON
Register powered by internal V
18
. This does not generate any problem, because the Standby Mode switching dedicated circuit continues to confirm the RAM interface freezing, irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when internal V
18
comes back over internal stand-by reference V
18SB
.
If internal V
18
becomes lower than internal stand-by reference (V
18SB
) of about 0.3 to 0.45V with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a temporary drop on internal V
18
voltage versus internal V
18SB
during normal code execution, no spurious Stand-by Mode switching can occur (the RAM is not frozen and can still be accessed).
The ST10F271 Core module, generating the RAM control signals, is powered by internal
V
18
supply; during turning off transient these control signals follow the V
18 switched to V
18SB
, while RAM is Obsolete Product(s) - Obsolete Product(s) from ST10F271 Core (active low signal) is low enough to be recognized as a logic “0” by the
Obsolete Product(s) - Obsolete Product(s) interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism.
108/180
ST10F271B/ST10F271E Power reduction modes
Warning: During power-off phase, it is important that the external hardware maintains a stable ground level on RSTIN pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply.
21.3.2 Exiting stand-by mode
After the system has entered the Stand-by Mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V
18SB
internal reference (derived from V
STBY
pin external voltage).
It is recommended to held the device under RESET (RSTIN pin forced low) until external
V
DD voltage pin is stable. Even though, at the very beginning of the power-on phase, the device is maintained under reset by the internal low voltage detector circuit (implemented inside the main voltage regulator) till the internal V
18
becomes higher than about 1.0V, there is no warranty that the device stays under reset status if RSTIN is at high level during power ramp up. So, it is important the external hardware is able to guarantee a stable ground level on RSTIN along the power-on phase, without any temporary glitch.
The external hardware shall be responsible to drive low the RSTIN pin until the V
DD
is stable, even though the internal LVD is active.
Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to the main V
18
.
At this time, everything becomes stable, and the execution of the initialization routines can start: XRAM2EN bit can be set, enabling the RAM.
21.3.3 Real time clock and stand-by mode
When Stand-by mode is entered (turning off the main supply V
DD
), the Real Time Clock counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide the reference to the counter. This is not possible if the main oscillator is used as reference for the counter: Being the main oscillator powered by V
DD
, once this is switched off, the oscillator is stopped.
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109/180
Power reduction modes ST10F271B/ST10F271E
Table 51: Power reduction modes summary
, a summary of the different
Power reduction modes is reported.
Table 51.
Power reduction modes summary
Mode
Idle
Power Down
Stand-by on on on on on off off on on on on on on on off off off off off off off on on off off off off off off on off on on off on run run off on off off off off on off off on off on biased biased biased biased biased biased biased biased biased biased biased off biased off
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110/180
ST10F271B/ST10F271E
22
Programmable output clock divider
Programmable output clock divider
A specific register mapped on the XBUS allows to choose the division factor on the
CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range.
When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the
CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON, it is possible to program the clock prescaling factor: in this way on P3.15 a prescaled value of the CPU clock can be output.
When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15 does not output any clock signal, even though XCLKOUTDIV register is programmed.
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111/180
Register set ST10F271B/ST10F271E
This section summarizes all registers implemented in the ST10F271, ordered by name.
23.1 Special function registers
The following table lists all SFRs which are implemented in the ST10F271 in alphabetical order.
Bit-addressable SFRs are marked with the letter “ b ” in column “Name”.
SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “ E ” in column
“Physical Address”.
Table 52.
List of special function registers
Name
Physical address
8-bit address
Description
Reset value
ADCIC b FF98h
ADCON
ADDAT
ADDAT2
ADDRSEL1 b FFA0h
FEA0h
F0A0h
FE18h
ADDRSEL2
ADDRSEL3
ADDRSEL4
FE1Ah
FE1Ch
FE1Eh
ADEIC b FF9Ah
BUSCON0 b FF0Ch
BUSCON1 b FF14h
BUSCON2 b FF16h
BUSCON3 b FF18h
BUSCON4 b FF1Ah
CAPREL FE4Ah
FE80h
E
CCh
CDh
86h
8Ah
8Bh
8Ch
8Dh
25h
40h
D0h
50h
50h
0Ch
0Dh
0Eh
0Fh
A/D converter end of conversion interrupt control register
A/D converter control register
A/D converter result register
A/D converter 2 result register
Address select register 1
Address select register 2
Address select register 3
Address select register 4
A/D converter overrun error interrupt control register
Bus configuration register 0
Bus configuration register 1
Bus configuration register 2
Bus configuration register 3
Bus configuration register 4
GPT2 capture/reload register
CAPCOM register 0
- - 00h
CC0IC b FF78h BCh CAPCOM register 0 interrupt control register - - 00h
Obsolete Product(s) - Obsolete Product(s)
CC1IC b FF7Ah BDh CAPCOM register 1 interrupt control register - - 00h
CC2 FE84h 42h CAPCOM register 2 0000h
CC2IC
CC3
CC3IC b FF7Ch
FE86h b FF7Eh
BEh
43h
BFh
CAPCOM register 2 interrupt control register
CAPCOM register 3
CAPCOM register 3 interrupt control register
- - 00h
0000h
- - 00h
- - 00h
0xx0h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
112/180
ST10F271B/ST10F271E Register set
Table 52.
List of special function registers (continued)
Name
Physical address
8-bit address
Description
Reset value
CC10
CC10IC
CC11
CC11IC
CC12
CC12IC
CC13
CC13IC
CC14
CC14IC
CC15
CC15IC
CC16
CC16IC
CC7
CC7IC
CC8
CC8IC
CC9
CC9IC
CC4
CC4IC
CC5
CC5IC
CC6
CC6IC
FE94h b FF8Ch
FE96h b FF8Eh
FE98h b FF90h
FE9Ah b FF92h
FE9Ch b FF94h
FE9Eh b FF96h
FE60h b F160h
FE88h b FF80h
FE8Ah b FF82h
FE8Ch b FF84h
FE8Eh b FF86h
FE90h b FF88h
FE92h b FF8Ah
4Dh
C9h
4Eh
CAh
4Fh
CBh
30h
B0h
4Ah
C6h
4Bh
C7h
4Ch
C8h
47h
C3h
48h
C4h
49h
C5h
44h
C0h
45h
C1h
46h
C2h
CAPCOM register 4
CAPCOM register 4 interrupt control register
CAPCOM register 5
CAPCOM register 5 interrupt control register
CAPCOM register 6
CAPCOM register 6 interrupt control register
CAPCOM register 7
CAPCOM register 7 interrupt control register
CAPCOM register 8
CAPCOM register 8 interrupt control register
CAPCOM register 9
CAPCOM register 9 interrupt control register
CAPCOM register 10
CAPCOM register 10 interrupt control register
CAPCOM register 11
CAPCOM register 11 interrupt control register
CAPCOM register 12
CAPCOM register 12 interrupt control register
CAPCOM register 13
CAPCOM register 13 interrupt control register
CAPCOM register 14
CAPCOM register 14 interrupt control register
CAPCOM register 15
CAPCOM register 15 interrupt control register
CAPCOM register 16
CAPCOM register 16 interrupt control register E
CC17
CC17IC b
FE62h
F162h E
31h
B1h
CAPCOM register 17
CAPCOM register 17 interrupt control register
0000h
- - 00h
FE64h 32h CAPCOM register 18 0000h CC18 Obsolete Product(s) - Obsolete Product(s)
CC18IC b F164h E B2h CAPCOM register 18 interrupt control register - - 00h
CC19 FE66h 33h CAPCOM register 19 0000h
CC19IC b F166h E B3h CAPCOM register 19 interrupt control register - - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
CC20
CC20IC
FE68h b F168h
34h
B4h
CAPCOM register 20
CAPCOM register 20 interrupt control register
0000h
- - 00h E
113/180
Register set ST10F271B/ST10F271E
Table 52.
List of special function registers (continued)
Name
Physical address
8-bit address
Description
Reset value
CC27
CC27IC
CC28
CC28IC
CC29
CC29IC
CC30
CC30IC
CC31
CC31IC
CCM0
CCM1
CCM2
CCM3
CC21
CC21IC
CC22
CC22IC
CC23
CC23IC
CC24
CC24IC
CC25
CC25IC
CC26
CC26IC
FE76h b F176h
FE78h b F178h
FE7Ah b F184h
FE7Ch b F18Ch
FE7Eh b F194h b FF52h b FF54h b FF56h b FF58h
FE6Ah b F16Ah
FE6Ch b F16Ch
FE6Eh b F16Eh
FE70h b F170h
FE72h b F172h
FE74h b F174h
E
E
E
E
E
E
E
E
E
E
E
3Eh
C6h
3Fh
CAh
A9h
AAh
ABh
ACh
3Bh
BBh
3Ch
BCh
3Dh
C2h
38h
B8h
39h
B9h
3Ah
BAh
35h
B5h
36h
B6h
37h
B7h
CAPCOM register 21
CAPCOM register 21 interrupt control register
CAPCOM register 22
CAPCOM register 22 interrupt control register
CAPCOM register 23
CAPCOM register 23 interrupt control register
CAPCOM register 24
CAPCOM register 24 interrupt control register
CAPCOM register 25
CAPCOM register 25 interrupt control register
CAPCOM register 26
CAPCOM register 26 interrupt control register
CAPCOM register 27
CAPCOM register 27 interrupt control register
CAPCOM register 28
CAPCOM register 28 interrupt control register
CAPCOM register 29
CAPCOM register 29 interrupt control register
CAPCOM register 30
CAPCOM register 30 interrupt control register
CAPCOM register 31
CAPCOM register 31 interrupt control register
CAPCOM Mode Control register 0
CAPCOM Mode Control register 1
CAPCOM Mode Control register 2
CAPCOM mode Control register 3
CCM4
CCM5 b FF22h b FF24h
91h
92h
CAPCOM Mode Control register 4
CAPCOM Mode Control register 5
0000h
0000h b FF26h 93h CAPCOM Mode Control register 6 0000h CCM6 Obsolete Product(s) - Obsolete Product(s)
CCM7 b FF28h 94h CAPCOM Mode Control register 7 0000h
CP FE10h 08h CPU Context Pointer register FC00h
CRIC b FF6Ah B5h GPT2 CAPREL interrupt control register - - 00h
CSP
DP0L
FE08h b F100h E
04h
80h
CPU Code Segment Pointer register (read only)
P0L direction control register
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
0000h
- - 00h
114/180
ST10F271B/ST10F271E Register set
Table 52.
List of special function registers (continued)
Name
Physical address
8-bit address
Description
Reset value
DPP3
EMUCON
EXICON
EXISEL
IDCHIP
IDMANUF
IDMEM
IDPROG
IDX0
IDX1
MAH
MAL
MCW
MDC
DP6
DP7
DP8
DPP0
DPP1
DPP2
DP0H
DP1L
DP1H
DP2
DP3
DP4
FE06h
FE0Ah b F1C0h b F1DAh
F07Ch
F07Eh
F07Ah
F078h b FF08h b FF0Ah
FE5Eh
FE5Ch b FFDCh b FF0Eh b F102h b F104h b F106h b FFC2h b FFC6h b FFCAh b FFCEh b FFD2h b FFD6h
FE00h
FE02h
FE04h
E
E
E
E
E
E
E
E
E
3Dh
3Ch
84h
85h
2Fh
2Eh
EEh
87h
03h
05h
E0h
EDh
3Eh
3Fh
E7h
E9h
EBh
00h
01h
02h
81h
82h
83h
E1h
E3h
E5h
P0h direction control register
P1L direction control register
P1h direction control register
Port 2 direction control register
Port 3 direction control register
Port 4 direction control register
Port 6 direction control register
Port 7 direction control register
Port 8 direction control register
CPU data page pointer 0 register (10-bit)
CPU data page pointer 1 register (10-bit)
CPU data page pointer 2 register (10-bit)
CPU data page pointer 3 register (10-bit)
Emulation control register
External interrupt control register
External interrupt source selection register
Device identifier register (n is the device revision)
Manufacturer identifier register
On-chip memory identifier register
Programming voltage identifier register
MAC unit address pointer 0
MAC unit address pointer 1
MAC unit accumulator - high word
MAC unit accumulator - low word
MAC unit control word
CPU multiply divide control register
MDH
MDL
FE0Ch
FE0Eh
06h
07h
CPU multiply divide register – high word
CPU multiply divide register – low word
0000h
0000h b FFDAh EDh MAC unit repeat word 0000h MRW Obsolete Product(s) - Obsolete Product(s)
MSW b FFDEh EFh MAC unit status word 0200h
ODP2 b F1C2h E E1h Port 2 open drain control register 0000h
ODP3 b F1C6h E E3h Port 3 open drain control register 0000h
ODP4
ODP6 b F1CAh b F1CEh
E
E
E5h
E7h
Port 4 open drain control register
Port 6 open drain control register
- - 00h
- - 00h
0003h
- - XXh
0000h
0000h
110nh
0403h
3040h
0040h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
- - 00h
- - 00h
0000h
0001h
0002h
- - 00h
- - 00h
- - 00h
0000h
0000h
- - 00h
115/180
Register set ST10F271B/ST10F271E
Table 52.
List of special function registers (continued)
Name
Physical address
8-bit address
Description
Reset value
P7
P8
P5DIDIS
PECC0
PECC1
PECC2
PECC3
PECC4
PECC5
PECC6
PECC7
PICON
PP0
PP1
P4
P5
P6
P1H
P2
P3
ODP7
ODP8
ONES
P0L
P0H
P1L b FFD0h b FFD4h b FFA4h
FEC0h
FEC2h
FEC4h
FEC6h
FEC8h
FECAh
FECCh
FECEh b F1C4h
F038h
F03Ah b F1D2h b F1D6h b FF1Eh b FF00h b FF02h b FF04h b FF06h b FFC0h b FFC4h b FFC8h b FFA2h b FFCCh
E
E
E
E
E
63h
64h
65h
66h
67h
E2h
1Ch
1Dh
E8h
EAh
D2h
60h
61h
62h
83h
E0h
E2h
E4h
D1h
E6h
E9h
EBh
8Fh
80h
81h
82h
Port 7 open drain control register
Port 8 open drain control register
Constant value 1’s register (read only)
PORT0 low register (lower half of PORT0)
PORT0 high register (upper half of PORT0)
PORT1 low register (lower half of PORT1)
PORT1 high register (upper half of PORT1)
Port 2 register
Port 3 register
Port 4 register (8-bit)
Port 5 register (read only)
Port 6 register (8-bit)
Port 7 register (8-bit)
Port 8 register (8-bit)
Port 5 digital disable register
PEC channel 0 control register
PEC channel 1 control register
PEC channel 2 control register
PEC channel 3 control register
PEC channel 4 control register
PEC channel 5 control register
PEC channel 6 control register
PEC channel 7 control register
Port input threshold control register
PWM module period register 0
PWM module period register 1
PP2
PP3
F03Ch
F03Eh
E
E
1Eh
1Fh
PWM module period register 2
PWM module period register 3
0000h
0000h b FF10h 88h CPU program status word 0000h PSW Obsolete Product(s) - Obsolete Product(s)
PT0 F030h E 18h PWM module up/down counter 0 0000h
PT1 F032h E 19h PWM module up/down counter 1 0000h
PT2 F034h E 1Ah PWM module up/down counter 2 0000h
E PT3
PW0
F036h
FE30h
1Bh
18h
PWM module up/down counter 3
PWM module pulse width register 0
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
- - 00h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
XXXXh
- - 00h
- - 00h
- - 00h
FFFFh
- - 00h
- - 00h
- - 00h
116/180
ST10F271B/ST10F271E Register set
Table 52.
List of special function registers (continued)
Name
Physical address
8-bit address
Description
Reset value
QR0
QR1
QX0
QX1
RP0H
S0BG
PW1
PW2
PW3
FE32h
FE34h
FE36h
PWMCON0 b FF30h
PWMCON1 b FF32h
PWMIC b F17Eh
F004h
F006h
F000h
F002h b F108h
FEB4h
S0CON
S0EIC
S0RBUF
S0RIC
S0TBIC
S0TBUF b FFB0h b FF70h
FEB2h b FF6Eh b F19Ch
FEB0h
S0TIC
SP
SSCBR b FF6Ch
FE12h
F0B4h
SSCCON b FFB2h
SSCEIC b FF76h
SSCRB F0B2h
SSCRIC
SSCTB b FF74h
F0B0h
E
E
E
E
E
E
E
E
E
B6h
09h
5Ah
D9h
BBh
59h
BAh
58h
D8h
B8h
59h
B7h
CEh
58h
02h
03h
00h
01h
84h
5Ah
19h
1Ah
1Bh
98h
99h
BFh
PWM module pulse width register 1
PWM module pulse width register 2
PWM module pulse width register 3
PWM module control register 0
PWM module control register 1
PWM module interrupt control register
MAC unit offset register r0
MAC unit offset register R1
MAC unit offset register X0
MAC unit offset register X1
System start-up configuration register (read only)
Serial channel 0 baud rate generator reload register
Serial channel 0 control register
Serial channel 0 error interrupt control register
Serial channel 0 receive buffer register (read only)
Serial channel 0 receive interrupt control register
Serial channel 0 transmit buffer interrupt control reg.
Serial channel 0 transmit buffer register (write only)
Serial channel 0 transmit interrupt control register
CPU system stack pointer register
SSC Baud rate register
SSC control register
SSC error interrupt control register
SSC receive buffer (read only)
SSC receive interrupt control register
SSC transmit buffer (write only) E
SSCTIC
STKOV b FF72h
FE14h
B9h
0Ah
SSC transmit interrupt control register
CPU stack overflow pointer register
- - 00h
FA00h
FE16h 0Bh CPU stack underflow pointer register FC00h STKUN Obsolete Product(s) - Obsolete Product(s)
SYSCON b FF12h 89h CPU system configuration register 0xx0h 1)
T0 FE50h 28h CAPCOM timer 0 register 0000h
T01CON b FF50h A8h CAPCOM timer 0 and timer 1 control register 0000h
0000h
- - 00h
- - XXh
- - 00h
- - 00h
0000h
- - 00h
FC00h
0000h
0000h
- - 00h
XXXXh
- - 00h
0000h
0000h
0000h
0000h
0000h
- - XXh
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
T0IC
T0REL b FF9Ch
FE54h
CEh
2Ah
CAPCOM timer 0 interrupt control register
CAPCOM timer 0 reload register
- - 00h
0000h
117/180
Register set ST10F271B/ST10F271E
Table 52.
List of special function registers (continued)
Name
Physical address
8-bit address
Description
Reset value
T1
T1IC
T1REL
T2
T2CON
T2IC
T3
T3CON
T3IC
T4
T4CON
T4IC
T5
T5CON
T5IC
T6
T6CON
T6IC
FE46h b FF46h b FF66h
FE48h b FF48h b FF68h
T7 F050h
T78CON b FF20h
T7IC b F17Ah
T7REL
T8
T8IC
T8REL
TFR b b
F054h
F052h
F17Ch
F056h
FFACh
FE52h b FF9Eh
FE56h
FE40h b FF40h b FF60h
FE42h b FF42h b FF62h
FE44h b FF44h b FF64h
E
E
E
E
E
E
28h
90h
BDh
2Ah
29h
BEh
2Bh
D6h
23h
A3h
B3h
24h
A4h
B4h
21h
A1h
B1h
22h
A2h
B2h
29h
CFh
2Bh
20h
A0h
B0h
CAPCOM timer 1 register
CAPCOM timer 1 interrupt control register
CAPCOM timer 1 reload register
GPT1 timer 2 register
GPT1 timer 2 control register
GPT1 timer 2 interrupt control register
GPT1 timer 3 register
GPT1 timer 3 control register
GPT1 timer 3 interrupt control register
GPT1 timer 4 register
GPT1 timer 4 control register
GPT1 timer 4 interrupt control register
GPT2 timer 5 register
GPT2 timer 5 control register
GPT2 timer 5 interrupt control register
GPT2 timer 6 register
GPT2 timer 6 control register
GPT2 timer 6 interrupt control register
CAPCOM timer 7 register
CAPCOM timer 7 and 8 control register
CAPCOM timer 7 interrupt control register
CAPCOM timer 7 reload register
CAPCOM timer 8 register
CAPCOM timer 8 interrupt control register
CAPCOM timer 8 reload register
Trap Flag register
WDT
WDTCON b
FEAEh
FFAEh
57h
D7h
Watchdog timer register (read only)
Watchdog timer control register
0000h
00xxh
2)
F01Ch E 0Eh XPER address select register 3 800Bh XADRS3 Obsolete Product(s) - Obsolete Product(s)
XP0IC b F186h E C3h
- - 00h
3)
- - 00h
3)
XP1IC b F18Eh E C7h
- - 00h
3)
XP2IC b F196h E CBh
- - 00h
3)
XP3IC b F19Eh E CFh
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
0000h
- - 00h
0000h
- - 00h
0000h
0000h
0000h
- - 00h
118/180
ST10F271B/ST10F271E Register set
Table 52.
List of special function registers (continued)
Name
Physical address
8-bit address
Description
XPERCON b F024h
ZEROS b FF1Ch
E 12h
8Eh
XPER configuration register
Constant value 0’s register (read only)
Note:
Reset value
- - 05h
0000h
1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b.
2. Reset Value depends on different triggered reset event.
3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled interrupt requests may be generated by setting the
XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes.
Note:
The following table lists all XBus registers which are implemented in the ST10F271 ordered by their name.
The XBus registers are not bit-addressable.
Table 53.
List of XBus registers
Name
Physical address
Description
Reset value
CAN1BRPER
CAN1BTR
CAN1CR
CAN1EC
CAN1IF1A1
CAN1IF1A2
CAN1IF1CM
CAN1IF1CR
CAN1IF1DA1
CAN1IF1DA2
EF0Ch
EF06h
EF00h
EF04h
EF18h
EF1Ah
EF12h
EF10h
EF1Eh
EF20h
CAN1: BRP extension register
CAN1: Bit timing register
CAN1: CAN control register
CAN1: error counter
CAN1: IF1 arbitration 1
CAN1: IF1 arbitration 2
CAN1: IF1 command mask
CAN1: IF1 command request
CAN1: IF1 data A 1
CAN1: IF1 data A 2
CAN1IF1DB1
CAN1IF1DB2
EF22h
EF24h
CAN1: IF1 data B 1
CAN1: IF1 data B 2
0000h
0000h
CAN1IF1M1
CAN1IF1M2
EF14h
EF16h
CAN1: IF1 mask 1
CAN1: IF1 mask 2
FFFFh
FFFFh
CAN1IF1MC EF1Ch CAN1: IF1 message control 0000h
CAN1IF2A1 EF48h CAN1: IF2 arbitration 1 0000h
CAN1IF2A2
CAN1IF2CM
EF4Ah
EF42h
CAN1: IF2 arbitration 2
CAN1: IF2 command mask
0000h
0000h
0000h
2301h
0001h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
119/180
Register set ST10F271B/ST10F271E
Table 53.
List of XBus registers (continued)
Name
Physical address
Description
Reset value
CAN1MV2
CAN1ND1
CAN1ND2
CAN1SR
CAN1TR
CAN1TR1
CAN1TR2
CAN2BRPER
CAN2BTR
CAN2CR
CAN2EC
CAN2IF1A1
CAN2IF1A2
CAN2IF1CM
CAN1IF2CR
CAN1IF2DA1
CAN1IF2DA2
CAN1IF2DB1
CAN1IF2DB2
CAN1IF2M1
CAN1IF2M2
CAN1IF2MC
CAN1IP1
CAN1IP2
CAN1IR
CAN1MV1
EFB2h
EF90h
EF92h
EF02h
EF0Ah
EF80h
EF82h
EE0Ch
EE06h
EE00h
EE04h
EE18h
EE1Ah
EE12h
EF40h
EF4Eh
EF50h
EF52h
EF54h
EF44h
EF46h
EF4Ch
EFA0h
EFA2h
EF08h
EFB0h
CAN1: IF2 command request
CAN1: IF2 data A 1
CAN1: IF2 data A 2
CAN1: IF2 data B 1
CAN1: IF2 data B 2
CAN1: IF2 Mask 1
CAN1: IF2 mask 2
CAN1: IF2 message control
CAN1: interrupt pending 1
CAN1: interrupt pending 2
CAN1: interrupt register
CAN1: message valid 1
CAN1: message valid 2
CAN1: new data 1
CAN1: new data 2
CAN1: status register
CAN1: test register
CAN1: transmission request 1
CAN1: transmission request 2
CAN2: BRP extension register
CAN2: bit timing register
CAN2: CAN control register
CAN2: error counter
CAN2: IF1 arbitration 1
CAN2: IF1 arbitration 2
CAN2: IF1 command mask
CAN2IF1CR
CAN2IF1DA1
EE10h
EE1Eh
CAN2: IF1 command request
CAN2: IF1 data A 1
0001h
0000h
EE20h CAN2: IF1 data A 2 0000h CAN2IF1DA2 Obsolete Product(s) - Obsolete Product(s)
CAN2IF1DB1 EE22h CAN2: IF1 data B 1 0000h
CAN2IF1DB2 EE24h CAN2: IF1 data B 2 0000h
CAN2IF1M1 EE14h CAN2: IF1 mask 1 FFFFh
CAN2IF1M2
CAN2IF1MC
EE16h
EE1Ch
CAN2: IF1 mask 2
CAN2: IF1 message control
FFFFh
0000h
0000h
0000h
2301h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00x0h
0000h
FFFFh
0000h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
FFFFh
120/180
ST10F271B/ST10F271E Register set
Table 53.
List of XBus registers (continued)
Name
Physical address
Description
Reset value
CAN2IP2
CAN2IR
CAN2MV1
CAN2MV2
CAN2ND1
CAN2ND2
CAN2SR
CAN2TR
CAN2TR1
CAN2TR2
I2CCCR1
I2CCCR2
I2CCR
I2CDR
CAN2IF2A1
CAN2IF2A2
CAN2IF2CM
CAN2IF2CR
CAN2IF2DA1
CAN2IF2DA2
CAN2IF2DB1
CAN2IF2DB2
CAN2IF2M1
CAN2IF2M2
CAN2IF2MC
CAN2IP1
EEA2h
EE08h
EEB0h
EEB2h
EE90h
EE92h
EE02h
EE0Ah
EE80h
EE82h
EA06h
EA0Eh
EA00h
EA0Ch
EE48h
EE4Ah
EE42h
EE40h
EE4Eh
EE50h
EE52h
EE54h
EE44h
EE46h
EE4Ch
EEA0h
CAN2: IF2 arbitration 1
CAN2: IF2 arbitration 2
CAN2: IF2 command mask
CAN2: IF2 command request
CAN2: IF2 data A 1
CAN2: IF2 data A 2
CAN2: IF2 data B 1
CAN2: IF2 data B 2
CAN2: IF2 mask 1
CAN2: IF2 mask 2
CAN2: IF2 message control
CAN2: interrupt pending 1
CAN2: interrupt pending 2
CAN2: interrupt register
CAN2: message valid 1
CAN2: message valid 2
CAN2: new data 1
CAN2: new data 2
CAN2: status register
CAN2: test register
CAN2: transmission request 1
CAN2: Transmission request 2
I2C clock control register 1
I2C clock control register 2
I2C control register
I2C data register
I2COAR1
I2COAR2
EA08h
EA0Ah
I2C own address register 1
I2C own address register 2
0000h
0000h
EA02h I2C status register 1 0000h I2CSR1 Obsolete Product(s) - Obsolete Product(s)
I2CSR2 EA04h I2C status register 2 0000h
RTCAH ED14h RTC alarm register high byte XXXXh
RTCAL ED12h RTC alarm register low byte XXXXh
RTCCON
RTCDH
ED00H
ED0Ch
RTC control register
RTC divider counter high byte
000Xh
XXXXh
0000h
00x0h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
121/180
Register set ST10F271B/ST10F271E
Table 53.
List of XBus registers (continued)
Name
Physical address
Description
Reset value
XIR0SET
XIR1CLR
XIR1SEL
XIR1SET
XIR2CLR
XIR2SEL
XIR2SET
XIR3CLR
XIR3SEL
XIR3SET
XMISC
XP1DIDIS
XPEREMU
XPICON
RTCDL
RTCH
RTCL
RTCPH
RTCPL
XCLKOUTDIV
XEMU0
XEMU1
XEMU2
XEMU3
XIR0CLR
XIR0SEL
EB32h
EB44h
EB40h
EB42h
EB46h
EB36h
EB7Eh
EB26h
EB12h
EB24h
EB20h
EB22h
EB34h
EB30h
ED0Ah
ED10h
ED0Eh
ED08h
ED06h
EB02h
EB76h
EB78h
EB7Ah
EB7Ch
EB14h
EB10h
RTC divider counter low byte
RTC programmable counter high byte
RTC programmable counter low byte
RTC prescaler register high byte
RTC prescaler register low byte
CLKOUT divider control register
XBUS emulation register 0 (write only)
XBUS emulation register 1 (write only)
XBUS emulation register 2 (write only)
XBUS emulation register 3 (write only)
X-Interrupt 0 clear register (write only)
X-Interrupt 0 selection register
X-Interrupt 0 set register (write only)
X-Interrupt 1 clear register (write only)
X-Interrupt 1 selection register
X-Interrupt 1 set register (write only)
X-Interrupt 2 clear register (write only)
X-Interrupt 2 selection register
X-Interrupt 2 set register (write only)
X-Interrupt 3 clear selection register (write only)
X-Interrupt 3 selection register
X-Interrupt 3 set selection register (write only)
XBUS miscellaneous features register
Port 1 digital disable register
XPERCON copy for emulation (write only)
Extended port input threshold control register
XPOLAR
XPP0
EC04h
EC20h
XPWM module channel polarity register
XPWM module period register 0
0000h
0000h
EC22h XPWM module period register 1 0000h XPP1 Obsolete Product(s) - Obsolete Product(s)
XPP2 EC24h XPWM module period register 2 0000h
XPP3 EC26h XPWM module period register 3 0000h
XPT0 EC10h XPWM module up/down counter 0 0000h
XPT1
XPT2
EC12h
EC14h
XPWM module up/down counter 1
XPWM module up/down counter 2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
XXXXh
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
- - 00h
XXXXh
XXXXh
XXXXh
XXXXh
0000h
0000h
122/180
ST10F271B/ST10F271E Register set
Table 53.
List of XBus registers (continued)
Name
Physical address
Description
Reset value
E908h
E80Ah
E800h
E804h
E802h
E880h
E808h
E806h
E906h
E900h
E904h
E902h
E980h
E90Ah
EC16h
EC30h
EC32h
EC34h
EC36h
EC00h
EC08h
EC06h
EC02h
EC0Ch
EC0Ah
EC80h
XPT3
XPW0
XPW1
XPW2
XPW3
XPWMCON0
XPWMCON0CLR
XPWMCON0SET
XPWMCON1
XPWMCON1CLR
XPWMCON1SET
XPWMPORT
XS1BG
XS1CON
XS1CONCLR
XS1CONSET
XS1PORT
XS1RBUF
XS1TBUF
XSSCBR
XSSCCON
XSSCCONCLR
XSSCCONSET
XSSCPORT
XSSCRB
XSSCTB
XPWM module up/down counter 3
XPWM module pulse width register 0
XPWM module pulse width register 1
XPWM module pulse width register 2
XPWM module pulse width register 3
XPWM module control register 0
XPWM module clear control reg. 0 (write only)
XPWM module set control register 0 (write only)
XPWM module control register 1
XPWM module clear control reg. 0 (write only)
XPWM module set control register 0 (write only)
XPWM module port control register
XASC Baud rate generator reload register
XASC control register
XASC clear control register (write only)
XASC set control register (write only)
XASC port control register
XASC receive buffer register
XASC transmit buffer register
XSSC Baud rate register
XSSC control register
XSSC clear control register (write only)
XSSC set control register (write only)
XSSC port control register
XSSC receive buffer
XSSC transmit buffer
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
0000h
0000h
0000h
0000h
0000h
0000h
XXXXh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
123/180
Register set ST10F271B/ST10F271E
23.3 Flash registers ordered by name
Note:
The following table lists all Flash Control Registers which are implemented in the ST10F271 ordered by their name. These registers are physically mapped on the IBus, except for
XFVTAUR0, which is mapped on XBus.
These registers are not bit-addressable.
Table 54.
List of flash registers
Name
Physical address
FARH
FARL
FCR0H
FCR0L
FCR1H
FCR1L
FDR0H
FDR0L
FDR1H
FDR1L
FER
FNVAPR0
FNVAPR1H
FNVAPR1L
FNVWPIR
XFVTAUR0
Description
0x0008 0012 Flash address register - high
0x0008 0010 Flash address register - low
0x0008 0002 Flash control register 0 - high
0x0008 0000 Flash control register 0 - low
0x0008 0006 Flash control register 1 - high
0x0008 0004 Flash control register 1 - low
0x0008 000A Flash data register 0 - high
0x0008 0008 Flash data register 0 - low
0x0008 000E Flash data register 1 - high
0x0008 000C Flash data register 1 - low
0x0008 0014 Flash error register
0x0008 DFB8 Flash non volatile access protection reg.0
0x0008 DFBE Flash non volatile access protection reg.1 - high
0x0008 DFBC Flash non volatile access protection reg.1 - low
0x000E DFB0 Flash non volatile protection I register
0x0000 EB50
XBus Flash volatile temporary access unprotection register 0
Reset value
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
FFFFh
FFFFh
0000h
ACFFh
FFFFh
FFFFh
FFFFh
The ST10F271 have four Identification registers, mapped in ESFR space. These registers contain:
●
●
A manufacturer identifier Obsolete Product(s) - Obsolete Product(s)
●
●
A internal Flash and size identifier Obsolete Product(s) - Obsolete Product(s)
Note: As the ST10F271 device is supported with the silicon of the ST10F272 (commercial version of the same product), the identification registers provide the values corresponding to the
ST10F272 device.
124/180
ST10F271B/ST10F271E Register set
IDMANUF (F07Eh / 3Fh)
15 14 13 12 11 10
MANUF
R
9
ESFR
8 7 6 5 4
0
3
Reset Value: 0403h
2 1 0
0 0
R
1 1
Table 55.
IDMANUF
Bit
MANUF
Function
Manufacturer identifier
020h: STMicroelectronics manufacturer (JTAG worldwide normalization).
IDCHIP (F07Ch / 3Eh)
15 14 13 12 11 10 9
IDCHIP
R
ESFR
8 7 6 5 4 3
Reset Value: 110Xh
2 1 0
REVID
R
Table 56.
IDCHIP
Bit
IDCHIP
REVID
Device identifier
110h: ST10F271 identifier (272).
Device revision identifier
Xh: According to revision number.
IDMEM (F07Ah / 3Dh)
15 14 13 12 11 10
MEMTYP
R
9
Function
ESFR
8 7 6 5
MEMSIZE
R
4 3
Reset Value: 3040h
2 1 0
Table 57.
IDMEM
Bit
MEMSIZE
Function
Internal memory size
Internal memory size is 4 x (MEMSIZE) (in Kbyte)
040h for 256 Kbytes (ST10F272)
Internal memory type Obsolete Product(s) - Obsolete Product(s)
MEMTYP
‘1h’: (M) ROM memory
Obsolete Product(s) - Obsolete Product(s)
‘3h’: (H) High performance Flash memory (ST10F271)
‘4h...Fh’: Reserved
125/180
Register set
Note:
ST10F271B/ST10F271E
IDPROG (F078h / 3Ch)
15 14 13 12 11 10
PROGVPP
R
9
ESFR
8 7 6 5 4 3
Reset Value: 0040h
PROGVDD
R
2 1 0
Table 58.
IDPROG
Bit
PROGVDD
PROGVPP
Function
Programming V
DD
voltage
V
DD
voltage when programming EPROM or FLASH devices is calculated using the following formula: V
DD
= 20 x [PROGVDD] / 256 (volts) - 40h for ST10F271 (5V).
Programming V
PP
voltage (no need of external V
PP
) - 00h
All identification words are read only registers.
The values written inside different Identification Register bits are valid only after the Flash initialization phase is completed. When code execution is started from internal memory (pin
EA held high during reset), the Flash has certainly completed its initialization, so the bits of
Identification Registers are immediately ready to be read out. On the contrary, when code execution is started from external memory (pin EA held low during reset), the Flash initialization is not yet completed, so the bits of Identification Registers are not ready. The user can poll bits 15 and 14 of IDMEM register: when both bits are read low, the Flash initialization is complete, so all Identification Register bits are correct.
●
●
●
Before Flash initialization completion, the default setting of the different Identification
Registers are the following:
● IDMANUF 0403h
IDCHIP
IDMEM
IDPROG
110xh (x = silicon revision)
F040h
0040h
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
126/180
ST10F271B/ST10F271E Electrical characteristics
Table 59.
Absolute maximum ratings
Symbol Parameter
V
DD
V
STBY
V
AREF
V
AGND
V
IO
I
OV
I
TOV
T
ST
ESD
Voltage on V
DD
pins with respect to ground (V
SS
)
Voltage on V
STBY
pin with respect to ground (V
SS
)
Voltage on V
AREF
pins with respect to ground (V
SS
)
Voltage on V
AGND
pins with respect to ground (V
SS
)
Voltage on any pin with respect to ground (V
SS
)
Input current on any pin during overload condition
Absolute sum of all input currents during overload condition
Storage temperature
ESD Susceptibility (Human Body Model)
Note:
Values
-0.5 to +6.5
-0.5 to +6.5
-0.3 to V
DD
V
SS
-0.5 to V
DD
+ 0.5
± 10
| 75 |
-65 to +150
2000
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (V
IN
> V
DD
or V
IN
< V
SS
) the voltage on pins with respect to ground (V
SS
) must not exceed the values defined by the
Absolute Maximum Ratings.
During Power-on and Power-off transients (including Standby entering/exiting phases), the relationships between voltages applied to the device and the main V
DD
shall be always respected. In particular power-on and power-off of V
AREF
shall be coherent with V
DD
transient, in order to avoid undesired current injection through the on-chip protection diodes.
Unit
V
V mA
V
V
V mA
°C
V
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
127/180
Electrical characteristics ST10F271B/ST10F271E
Table 60.
Recommended operating conditions
Value
Symbol Parameter Unit
Min Max
V
DD
V
STBY
V
AREF
T
A
T
J
Operating supply voltage
Operationg stand-by supply voltage
Operating analog reference voltage
Ambient temperature under bias
Junction temperature under bias
(1)
(2)
4.5
4.5
-40
-40
5.5
5.5
+125
+150
V
V
°C
°C
1.
The value of the V
STBY
voltage is specified in the range 4.5 - 5.5 Volt. Nevertheless, it is acceptable to exceed the upper limit (up to 6.0 Volt) for a maximum of 100 hours over the global 300000 hours, representing the lifetime of the device
(about 30 years). On the other hand, it is possible to exceed the lower limit (down to 4.0 Volt) whenever RTC and 32kHz on-chip oscillator amplifier are turned off (only Stand-by RAM powered through VSTBY pin in Stand-by mode). When
VSTBY voltage is lower than main VDD, the input section of VSTBY/EA pin can generate a spurious static consumption on
VDD power supply (in the range of tenth of
µ
A).
2.
For details on operating conditions concerning the usage of A/D Converter refer to
.
The average chip-junction temperature, T
J
, in degrees Celsius, may be calculated using the following equation:
T
J
= T
A
+ (P
D
x Θ
JA
) (1)
Where:
T
A
is the Ambient Temperature in ° C,
Θ
JA
is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
P
D
is the sum of P
INT
and P
I/O
(P
D
= P
INT
+ P
I/O
),
P
INT
is the product of I
DD and V
DD
, expressed in Watt. This is the Chip Internal Power,
P
I/O
represents the Power Dissipation on Input and Output Pins; User Determined.
Most of the time for the applications P
I/O
< P
INT and may be neglected. On the other hand,
P
I/O
may be significant if the device is configured to drive continuously external modules and/or memories.
An approximate relationship between P
D
and T
J
(if P
I/O
is neglected) is given by:
Therefore (solving equations 1 and 2):
Obsolete Product(s) - Obsolete Product(s)
Where:
+ 273°C) + Θ
JA
x P
D
2
K is a constant for the particular part, which may be determined from equation (3) by measuring P
D
(at equilibrium) for a known T
A.
Using this value of K, the values of P
D
and T
J may be obtained by solving equations (1) and (2) iteratively for any value of T
A
.
128/180
ST10F271B/ST10F271E Electrical characteristics
Table 61.
Thermal characteristics
Symbol Description
Θ
JA
Thermal Resistance Junction-Ambient
PQFP 144 - 28 x 28 x 3.4 mm / 0.65 mm pitch
TQFP 144 - 20 x 20 mm / 0.5 mm pitch
TQFP 144 - 20 x 20 mm / 0.5 mm pitch on four layer
FR4 board (2 layers signals / 2 layers power)
Value (typical)
30
40
35
Unit
°C/W
Based on thermal characteristics of the package and with reference to the power consumption figures provided in next tables and diagrams, the following product classification can be proposed. Anyhow, the exact power consumption of the device inside the application must be computed according to different working conditions, thermal profiles, real thermal resistance of the system (including printed circuit board or other substrata), I/O activity, and so on.
Table 62.
Package characteristics
Package Ambient temperature range
PQFP 144
TQFP 144
–40 / +125
°
C
–40 / +125
°
C
–40 / +105
°
C
CPU frequency range
1 – 64MHz
1 – 40MHz
1 – 48MHz
The parameters listed in the following tables represent the characteristics of the ST10F271 and its demands on the system.
Where the ST10F271 logic provides signals with their respective timing characteristics, the symbol “ CC ” for Controller Characteristics, is included in the “Symbol” column. Where the external system must provide signals with their respective timing characteristics to the
ST10F271, the symbol “ SR ” for System Requirement, is included in the “Symbol” column.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
129/180
Electrical characteristics ST10F271B/ST10F271E
V
DD
= 5 V ± 10%, V
SS
= 0 V, T
A
= –40 to +125°C
Table 63.
DC characteristics
Limit values
Parameter Symbol min.
max.
Unit Test Condition
Input low voltage (TTL mode)
(except RSTIN, EA, NMI, RPD, XTAL1,
READY)
Input low voltage (CMOS mode)
(except RSTIN, EA, NMI, RPD, XTAL1,
READY)
V
V
IL
ILS
SR
SR
Input low voltage RSTIN, EA, NMI, RPD V
IL1
Input low voltage XTAL1 (CMOS only) V
IL2
Input low voltage READY (TTL only) V
IL3
Input high voltage (TTL mode)
(except RSTIN, EA, NMI, RPD, XTAL1)
V
IH
SR
SR
SR
SR
– 0.3
– 0.3
– 0.3
– 0.3
– 0.3
2.0
0.8
0.3 V
DD
0.3 V
DD
0.3 V
DD
0.8
V
DD
+ 0.3
V
V
V
V
V
V
–
–
–
Direct Drive mode
–
–
Input high voltage (CMOS mode)
(except RSTIN, EA, NMI, RPD, XTAL1)
V
IHS
SR
Input high voltage RSTIN, EA, NMI, RPD V
IH1
SR
Input high voltage XTAL1 (CMOS only) V
IH2
Input high voltage READY (TTL only) V
IH3
SR
SR
Input Hysteresis (TTL mode)
(except RSTIN, EA, NMI, XTAL1, RPD)
V
HYS
CC
0.7 V
DD
0.7 V
DD
0.7 V
DD
2.0
400
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
700
V
V
V
V mV
–
–
Direct Drive mode
–
(1)
Output low voltage RPD
V
HYSS
CC
V
OL2
CC –
V
DD
0.5 V
DD
0.3 V
DD
V
(1)
Input Hysteresis (CMOS mode)
(except RSTIN, EA, NMI, XTAL1, RPD)
750 1400 mV
Input Hysteresis RSTIN, EA, NMI
Input Hysteresis XTAL1
Input Hysteresis READY (TTL only)
V
HYS1
CC
V
HYS2
CC
V
HYS3
CC
750
0
400
1400
50
700 mV mV mV
(1)
(1)
(1)
Input Hysteresis RPD 500 1500 mV
(1)
V
HYS4
CC
Output low voltage
(P6[7:0], ALE, RD, WR/WRL, 0.4
I
OL
= 8 mA
CC –
0.05
V
BHE/WRH, CLKOUT, RSTIN,
Obsolete Product(s) - Obsolete Product(s)
Output low voltage
V
OL I
OL
= 1 mA
V
OL1
CC –
0.4
0.05
V
I
OL1
= 4 mA
I
OL1
= 0.5 mA
P8[7:0])
I
I
OL2
I
OL2
OL2
= 85 µ A
= 80 µ A
= 60 µ A
130/180
ST10F271B/ST10F271E Electrical characteristics
Table 63.
DC characteristics (continued)
Limit values
Parameter Symbol Unit Test Condition min.
max.
Output high voltage
(P6[7:0], ALE, RD, WR/WRL,
BHE/WRH, CLKOUT, RSTOUT)
Output high voltage
(2)
(P0[15:0], P1[15:0], P2[15:0],
P3[15,13:0], P4[7:0], P7[7:0],
P8[7:0])
V
OH
CC
V
OH1
CC
V
DD
– 0.8
V
DD
– 0.08
V
DD
– 0.8
V
DD
– 0.08
–
–
V
V
I
OH
= – 8 mA
I
OH
= – 1 mA
I
OH1
= – 4 mA
I
OH1
= – 0.5 mA
Output high voltage RPD V
OH2
CC
0
0.3 V
DD
0.5 V
DD
–
– V
I
OH2
= – 2 mA
I
OH2
I
OH2
= – 750 µ A
= – 150 µ A
– Input leakage current (P5[15:0])
(3) | I
OZ1
| CC
Input leakage current
(all except P5[15:0], P2[0], RPD, P3[12],
P3[15])
| I
OZ2
| CC –
±0.2
±0.5
µ A
µ A –
Input leakage current (P2[0])
(4) | I
OZ3
| CC –
+1.0
–0.5
µ A –
Input leakage current (RPD)
Input leakage current ( P3[12], P3[15])
Overload current (all except P2[0])
| I
OZ4
| CC
| I
OZ5
| CC
| I
OV1
| SR
–
–
–
±3.0
±1.0
±5
µ A
µ A mA
–
–
(1) (5)
Overload current (P2[0])
(4)
Idle mode supply current
(11)
| I
OV2
| SR
I
ID
–
+5
–1 mA
(1) (5)
RSTIN pull-up resistor
Read/Write inactive current
(6) (7)
Read/Write active current
(6) (8)
ALE inactive current
(6) (7)
ALE active current
(6) (8)
Port 6 inactive current (P6[4:0])
(6) (7)
Port 6 active current (P6[4:0])
(6) (8)
R
RST
CC
I
RWH
I
RWL
I
ALEL
I
ALEH
I
P6H
50
–
–500
20
–
–
–500
250
–40
–
–
300
–40
–
µ A
µ
A
µ A
µ A k Ω
µ A
µ A
100 k Ω nominal
V
OUT
= 2.4 V
V
OUT
= 0.4V
V
OUT
= 0.4V
V
OUT
= 2.4 V
V
OUT
= 2.4 V
I
P6L
V
OUT
= 0.4V
PORT0 configuration current
(6)
Pin Capacitance (Digital inputs / outputs) C
Run Mode Power supply current
(Execution from Internal RAM)
Run Mode Power supply current
(Execution from Internal Flash)
(9)
(1) (10)
I
P0H
6)
I
P0L
7)
IO
I
CC1
I
CC2
CC
–
–100
–
–
–
–10
–
10
15 + 1.5 f
CPU
15 + 1.5 f
CPU
µ A
µ A pF mA mA
V
IN
= 2.0V
V
IN
= 0.8V
(1) (6)
–
–
–
15 + 0.6 f
CPU mA –
131/180
Electrical characteristics ST10F271B/ST10F271E
Table 63.
DC characteristics (continued)
Limit values
Parameter Symbol Unit Test Condition min.
max.
Power Down supply current
(12)
(RTC off, Oscillators off,
Main Voltage Regulator off)
Power Down supply current
(12)
(RTC on, Main Oscillator on,
Main Voltage Regulator off)
Power Down supply current
(12)
(RTC on, 32kHz Oscillator on,
Main Voltage Regulator off)
I
PD1
I
PD2
I
PD3
–
–
–
200
400
Typical
Value
200
µ
A
µ A
µ A
T
A
= 25°C
T
A
= 25°C
T
A
= 25°C
Stand-by supply current
(12)
(RTC off, Oscillators off, V
DD
off, V
STBY on)
Stand-by supply current
(12)
(RTC on, 32kHz Oscillator on, main V
DD
off, V
STBY
on)
I
SB1
I
SB2
–
–
–
–
120
500
120
500
µ
A
µ A
µ A
µ A
V
STBY
= 5.5 V
T
A
= T
J
= 25°C
V
STBY
= 5.5 V
T
A
= T
J
= 125°C
V
STBY
= 5.5 V
T
A
= T
J
= 125°C
V
STBY
= 5.5 V
T
A
= T
J
= 125°C
Stand-by supply current
(1) (12)
(V
DD
transient condition)
I
SB3
– 2.5
mA –
1.
Not 100% tested, guaranteed by design characterization.
2.
This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is imposed by the external circuitry.
3.
Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default, after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
4.
The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes) implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits: failures in Flash reading may occur (sense amplifier perturbation). Refer to next
Figure 37: Port2 test mode structure
for a scheme of the input circuitry.
5.
Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. V
OV
> V
DD
+ 0.3 V or V
OV
< –0.3 V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The supply voltage must remain within the specified limits.
6.
This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled.
7.
The maximum current may be drawn while the respective signal line remains inactive.
8.
The minimum current must be drawn in order to drive the respective signal line active.
9.
The power supply current is a function of the operating frequency (f
CPU
illustrated in the Figure 38 below. This parameter is tested at V
disconnected and all inputs at V
IL doing the following:
or V
IH
, RSTIN pin at V
IH1min
DDmax
:
is expressed in MHz). This dependency is
Obsolete Product(s) - Obsolete Product(s)
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
132/180
ST10F271B/ST10F271E Electrical characteristics
10. The power supply current is a function of the operating frequency (f
CPU illustrated in the Figure 38 below. This parameter is tested at V disconnected and all inputs at V
IL doing the following:
or V
IH
, RSTIN pin at V
IH1min
is expressed in MHz). This dependency is
DDmax
and at maximum CPU clock frequency with all outputs
: this implies I/O current is not considered . The device is
- Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
11. The Idle mode supply current is a function of the operating frequency (f
CPU illustrated in the Figure 37
is expressed in MHz). This dependency is
below. These parameters are tested and at maximum CPU clock with all outputs disconnected and all inputs at V
IL
or V
IH
, RSTIN pin at V
IH1min
.
12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at V
DD
– 0.1 V to V
DD
, V
AREF
= 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
Regulator is assumed off: in case it is not, additional 1mA shall be assumed.
Figure 37.
Port2 test mode structure
P2.0
CC0IO
Output buffer
Clock
Alternate data input
Fast external interrupt input
Input latch
Test mode
Flash sense amplifier and column decoder
Obsolete Product(s) - Obsolete Product(s)
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Electrical characteristics ST10F271B/ST10F271E
Figure 38.
Supply current versus the operating frequency (RUN and IDLE modes)
150
I
CC1
= I
CC2
100
I
ID
50
0
0 10 20 30 40 f
CPU
[MHz]
50 60 70
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134/180
ST10F271B/ST10F271E Electrical characteristics
V
DD
= 5 V ± 10%, V
SS
= 0 V
Table 64.
Flash characteristics
Typical Maximum
Parameter T
A
= 25°C
0 cycles
(1)
T
A
= 125°C
0 cycles
(1)
100k cycles
Unit Notes
Word Program (32-bit)
(2)
Double Word Program (64-bit)
(2))
Bank 0 Program (256K)
(Double Word Program)
35
60
1.6
80
150
2.0
290
570
3.9
µ
µ s s s
–
–
–
Sector Erase (8K)
Sector Erase (32K)
0.6
0.5
1.1
0.8
0.9
0.8
2.0
1.8
1.0
0.9
2.7
2.5
s s not preprogrammed preprogrammed not preprogrammed preprogrammed
Sector Erase (64K)
1.7
1.3
3.7
3.3
5.1
4.7
s not preprogrammed preprogrammed
Bank 0 Erase (256K)
(3)
5.6
4.0
13.6
11.9
19.2
17.5
s not preprogrammed preprogrammed
(4)
Recovery from Power-Down (t
PD
Program Suspend Latency
Erase Suspend Latency
(4)
(4)
) –
–
–
40
10
30
40
10
30
µ s
µ s
µ s
Erase Suspend Request Rate
(4)
20 20 20 ms
Min delay between 2 requests
Set Protection
(4)
40 90 300 µ s
1.
The figures are given after about 100 cycles due to testing routines (0 cycles at the final customer).
2.
Word and Double Word Programming times are provided as average values derived from a full sector programming time: absolute value of a Word or Double Word Programming time could be longer than the average value.
3.
Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). As
ST10F271 implements only one bank, the Bank Erase operation is equivalent to Module and Chip Erase operations.
4.
Not 100% tested, guaranteed by Design Characterization.
Obsolete Product(s) - Obsolete Product(s)
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135/180
Electrical characteristics ST10F271B/ST10F271E
Table 65.
Flash data retention characteristics
Number of program / erase cycles
(-40°C
≤
T
A
≤
125°C)
Data retention time
(average ambient temperature 60°C)
256Kbyte (code store) 64Kbyte (EEPROM emulation)
(1)
0 - 100
1,000
10,000
100,000
> 20 years
-
-
-
> 20 years
> 20 years
10 years
1 year
1.
Two 64Kbyte Flash Sectors may be typically used to emulate up to 4, 8 or 16Kbyte of EEPROM. Therefore, in case of an emulation of a 16Kbyte EEPROM, 100,000 Flash Program / Erase cycles are equivalent to 800,000 EEPROM
Program/Erase cycles. For an efficient use of the EEPROM Emulation please refer to dedicated Application Note document
( AN2061 - “EEPROM Emulation with ST10F2xx” ). Contact your local field service, local sales person or STMicroelectronics representative to get copy of such a guideline document.
24.7 A/D converter characteristics
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= –40 to +125°C, 4.5V ≤
AREF
V
V
SS
≤
AGND
≤ V
SS
+ 0.2V
DD
,
Table 66.
A/D converter characteristics
Limit Values
Parameter Symbol Unit Test Condition min.
max.
Analog Reference voltage 1)
Analog Ground voltage
Analog Input voltage 2)
Reference supply current
Sample time
Conversion time
Differential Non Linearity
6)
Integral Non Linearity
6)
Offset Error
6)
V
AREF
SR
V
AGND
SR
V
AIN
SR
I
AREF
CC t
S t
C
CC
CC
DNL CC
INL CC
OFS CC
4.5
–
–
V
SS
V
AGND
1
3
–1
–1.5
–1.5
5
1
V
DD
V
V
SS
+ 0.2
V
V
AREF
V
–
–
+1 mA
µ A
µ s
µ s
LSB
+1.5
LSB
+1.5
LSB
Running mode
3)
Power Down mode
4)
5)
No overload
No overload
No overload
–2.0
Obsolete Product(s) - Obsolete Product(s)
–7.0
+2.0
LSB
Port5
Port1 - No overload
3)
+7.0
–
10
–6
3 pF
Port1 - Overload
3)
Obsolete Product(s) - Obsolete Product(s)
CC C
P1
Input Pin Capacitance
3) 8)
4 Port5
C
P2
CC – pF
6 Port1
Sampling Capacitance
3) 8)
C
S
CC – 3.5
pF
136/180
ST10F271B/ST10F271E Electrical characteristics
Table 66.
A/D converter characteristics
Limit Values
Parameter Symbol Unit Test Condition min.
max.
Analog Switch Resistance
3) 8)
R
SW
CC
–
–
–
600
1600
1300
W
Port5
Port1
R
AD
CC W
1.
V
AREF
can be tied to ground when A/D Converter is not in use: an extra consumption (around 200 main V
DD
µ
A) on
is added due to internal analogue circuitry not completely turned off: so, it is suggested to maintain the V
AREF
at V
DD
level even when not in use, and eventually switch off the A/D Converter circuitry setting bit ADOFF in ADCON register.
2.
V
AIN
may exceed V
AGND
or V
AREF
up to the absolute maximum ratings. However, the conversion result in these cases will be 0x000
H
or 0x3FF
H
, respectively.
3.
Not 100% tested, guaranteed by design characterization.
4.
During the sample time the input capacitance C
AIN
After the end of the sample time t result.
S
can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t
S
.
, changes of the analog input voltage have no effect on the conversion
Values for the sample clock t
S
depends on programming and can be taken from programming .
5.
This parameter includes the sample time t
S
, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock t
CC and can be taken from next
.
depend on programming
6.
DNL, INL, OFS and TUE are tested at V
AREF
= 5.0 V, V
AGND
= 0V, V
DD characterization for all other voltages within the defined voltage range.
= 5.0 V. It is guaranteed by design
‘LSB’ has a value of V
AREF
/1024.
For Port5 channels, the specified TUE (± 2LSB) is guaranteed also with an overload condition (see I
OV specification) occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all Port5 analog input pins does not exceed 10 mA.
For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins: when an overload condition occurs on maximum 2 not selected analog input pins of Port1 and the input positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static injection), the specified TUE is degraded (± 7LSB). To get the same accuracy, the negative injection current on Port1 pins shall not exceed -1mA in case of both dynamic and static injection.
7.
The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channels with the overload current within the different specified ranges (for both positive and negative injection current).
8.
Refer to scheme reported in Figure 40: A/D converter input pins scheme .
When a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as sample time. Next the sampled voltage is converted to a digital value several successive steps, which correspond to the 10-bit resolution of the ADC.
During these steps the internal capacitances are repeatedly charged and discharged via the
V
AREF
pin.
Obsolete Product(s) - Obsolete Product(s) depends on the time that each respective step takes, because the capacitors must reach
Obsolete Product(s) - Obsolete Product(s) maximum current, however, that a source can deliver, depends on its internal resistance.
The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the ST10F271 relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller. This allows adjusting the A/D converter of the
ST10F271 to the properties of the system:
137/180
Electrical characteristics ST10F271B/ST10F271E
Note:
Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however.
High internal resistance can be achieved by programming the respective times to a higher value, or the possible maximum. This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. The conversion rate in this case may be considerably lower, however.
The conversion times are programmed via the upper four bits of register ADCON. Bit fields
ADCTC and ADSTC are used to define the basic conversion time and in particular the partition between sample phase and comparison phases. The table below lists the possible combinations. The timings refer to the unit TCL, where f
CPU
= 1/2TCL. A complete conversion time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register.
Table 67.
A/D converter programming
ADCTC ADSTC Sample Comparison
11
00
01
10
11
00
01
10
11
00
01
10
11
10
10
10
10
00
00
00
00
11
11
11
TCL * 120
TCL * 140
TCL * 200
TCL * 400
TCL * 240
TCL * 280
TCL * 400
TCL * 800
TCL * 480
TCL * 560
TCL * 800
TCL * 1600
TCL * 240
TCL * 280
TCL * 280
TCL * 280
TCL * 480
TCL * 560
TCL * 560
TCL * 560
TCL * 960
TCL * 1120
TCL * 1120
TCL * 1120
Extra
TCL * 28
TCL * 16
TCL * 52
TCL * 44
TCL * 52
TCL * 28
TCL * 100
TCL * 52
TCL * 100
TCL * 52
TCL * 196
TCL * 164
Total conversion
TCL * 388
TCL * 436
TCL * 532
TCL * 724
TCL * 772
TCL * 868
TCL * 1060
TCL * 1444
TCL * 1540
TCL * 1732
TCL * 2116
TCL * 2884
The total conversion time is compatible with the formula valid for ST10F269, while the meaning of the bit fields ADCTC and ADSTC is no longer compatible: the minimum conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4.85
µ s (see
ST10F269).
24.7.2 A/D conversion accuracy Obsolete Product(s) - Obsolete Product(s)
The A/D Converter compares the analog voltage sampled on the selected analog input channel to its analog reference voltage (V
AREF
) and converts it into 10-bit digital data. The Obsolete Product(s) - Obsolete Product(s) the output digital value. It includes the following errors:
●
●
●
●
Offset error (OFS)
Gain Error (GE)
Quantization error
Non-Linearity error (Differential and Integral)
138/180
ST10F271B/ST10F271E
Note:
Electrical characteristics
These four error quantities are explained below using
Figure 39: A/D conversion characteristic
.
Offset error
Offset error is the deviation between actual and ideal A/D conversion characteristics when
the digital output value changes from the minimum (zero voltage) 00 to 01 (
Figure 39
, see
OFS).
Gain error
Gain error is the deviation between the actual and ideal A/D conversion characteristics when the digital output value changes from the 3FE to the maximum 3FF, once offset error is subtracted. Gain error combined with offset error represents the so-called full-scale error
(
Figure 39
, OFS + GE).
Quantization error
Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB.
Non-linearity error
Non-Linearity error is the deviation between actual and the best-fitting A/D conversion
Figure 39
●
●
Differential Non-Linearity error is the actual step dimension versus the ideal one (1
LSB
IDEAL
).
Integral Non-Linearity error is the distance between the center of the actual step and the center of the bisector line, in the actual characteristics. Note that for Integral Non-
Linearity error, the effect of offset, gain and quantization errors is not included.
Bisector characteristic is obtained drawing a line from 1/2 LSB before the first step of the real characteristic, and 1/2 LSB after the last step again of the real characteristic.
The Total Unadjusted Error specifies the maximum deviation from the ideal characteristic: the number provided in the Data Sheet represents the maximum error with respect to the entire characteristic. It is a combination of the Offset, Gain and Integral Linearity errors. The different errors may compensate each other depending on the relative sign of the Offset and
Gain errors. Refer to
Figure 39
, see TUE.
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Electrical characteristics ST10F271B/ST10F271E
Figure 39.
A/D conversion characteristic
Offset Error OFS Gain Error GE
3FF
3FE
3FD
3FC
3FB
3FA
Ideal Characteristic
(6)
(2)
Bisector Characteristic
Digital
Out
(HEX)
007
006
005
004
003
002
001
000
1 2 3 4
Offset Error OFS
(7)
(4)
(5)
(3)
(1)
1 LSB (ideal)
5 6 7 1018
V
AIN
(LSB
IDEAL
)
[LSB
IDEAL
= V
AREF
/ 1024]
1020
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential Non-Linearity Error (DNL)
(4) Integral Non-Linearity Error (INL)
(5) Center of a step of the actual transfer curve
(6) Quantization Error (1/2 LSB)
(7) Total Unadjusted Error (TUE)
1022 1024
The accuracy of the A/D converter depends on how accurate is its analog reference: a noise in the reference results in at least that much error in a conversion. A low pass filter on the
A/D converter reference source (supplied through pins V
AREF
and V
AGND
), is recommended in order to clean the signal, minimizing the noise. A simple capacitive bypassing may be sufficient in most of the cases; in presence of high RF noise energy, inductors or ferrite beads may be necessary.
In this architecture, V
AREF
and V
AGND
pins represents also the power supply of the analog circuitry of the A/D converter: there is an effective DC current requirement from the reference voltage by the internal resistor string in the R-C DAC array and by the rest of the analog circuitry.
Obsolete Product(s) - Obsolete Product(s) reasons, series resistance are not advisable, and more in general any series devices in the filter network should be designed to minimize the DC resistance.
Obsolete Product(s) - Obsolete Product(s)
Analog Input pins
To improve the accuracy of the A/D converter, it is definitively necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device, can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin;
140/180
ST10F271B/ST10F271E Electrical characteristics besides, it sources charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC Filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth).
Figure 40.
A/D converter input pins scheme
EXTERNAL CIRCUIT
Source
R
S
Filter
R
F
Current Limiter
R
L
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Sampling
R
SW
R
AD
V
A
C
F
C
P1
C
P2
C
S
R
S
R
F
C
F
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance R
L
R
SW
Channel Selection Switch Impedance
Sampling Switch Impedance R
AD
C
P
C
S
Pin Capacitance (two contributions, C
P1
Sampling Capacitance
and C
P2
)
Input Leakage and external circuit
The series resistor utilized to limit the current to a pin (see R
L
Figure 40
with a large source impedance can lead to a degradation of A/D converter accuracy when input leakage is present.
Data about maximum input leakage current at each pin are provided in the Data Sheet
(Electrical Characteristics section). Input leakage is greatest at high operating temperatures, and in general it decreases by one half for each 10° C decrease in temperature.
Considering that, for a 10-bit A/D converter one count is about 5mV (assuming V
AREF
= 5V), an input leakage of 100nA acting though an R
L
= 50k Ω of external resistance leads to an error of exactly one count (5mV); if the resistance were 100k Ω the error would become two counts.
Eventual additional leakage due to external clamping diodes must also be taken into account in computing the total leakage affecting the A/D converter measurements. Another contribution to the total leakage is represented by the charge sharing effects with the Obsolete Product(s) - Obsolete Product(s) equal to the conversion rate of a single channel (maximum when fixed channel continuous
Obsolete Product(s) - Obsolete Product(s) obtained (R
EQ
S
equal to 4pF, a resistance of 1M Ω is
= 1 / f
C
C
S
, where f
C
represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance
(sampled voltage on C
S
) and the sum of R
S
+ R
F
+ R must be designed to respect the following relation:
L
+ R
SW
+ R
AD
, the external circuit
R
V
A
⋅
+ R
F
+ R
L
+ R
SW
R
EQ
+ R
AD
<
1
--- LSB
2
141/180
Electrical characteristics ST10F271B/ST10F271E
The formula above provides a constraints for external network design, in particular on resistive path.
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C
F
, C
P1
and C
P2 initially charged at the source voltage V
A
(refer to the equivalent circuit reported in Figure 40), when the sampling phase is started (A/D switch close), a charge sharing phenomena is installed.
Figure 41.
Charge sharing timing diagram during sampling phase
V
CS
Voltage Transient on C
S
V
A
V
A2
∆ V < 0.5 LSB
1
2
V
A1
τ
1
< (R
SW
+ R
AD
) C
S
<< T
S
τ
2
= R
L
(C
S
+ C
P1
+ C
P2
)
T
S t
In particular two different transient periods can be distinguished (see Figure 41):
● A first and quick charge transfer from the internal capacitance C
P1
and C
P2
to the sampling capacitance C
S
occurs (C
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which
C
P2
is reported in parallel to C
P1
(call C
P
= C
P1
+ C
P2
), the two capacitance C
P
and C
S are in series, and the time constant is:
τ
1
= ( R
SW
+ R
AD
) ⋅
C
P
C
P
⋅
+
C
C
S
This relation can again be simplified considering only C
S
as an additional worst condition. In reality, the transient is faster, but the A/D Converter circuitry has been designed to be robust also in the very worst case: the sampling time T
S
is always much longer than the internal time constant:
τ
1
< ( R
SW
+ R
AD
) ⋅ C
S
< < T
S
The charge of C
P1
and C
P2
is redistributed also on C
S
, determining a new value of the voltage V
A1 on the capacitance according to the following equation:
V
A1
⋅ ( C
S
+ C
P1
+ C
P2
) = V
A
⋅ ( C
P1
+ C
P2
)
● A second charge transfer involves also C
F
(that is typically bigger than the on-chip Obsolete Product(s) - Obsolete Product(s)
P2 and C
S
were in parallel to C
P1
(since the time constant in reality would be faster), the time constant is: Obsolete Product(s) - Obsolete Product(s)
τ
2
< R
L
⋅ ( C
S
+ C
P1
+ C
P2
)
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time T
S
, a constraints on
142/180
ST10F271B/ST10F271E Electrical characteristics
R
L
sizing is obtained:
10 ⋅ τ
2
= 10 ⋅ R
L
⋅ ( C
S
+ C
P1
+ C
P2
) ≤ T
S
Of course, R
L
shall be sized also according to the current limitation constraints, in combination with R
S
(source impedance) and R
F
(filter resistance). Being C
F definitively bigger than C
P1
, C
P2
and C
S
, then the final voltage V
A2
(at the end of the charge transfer transient) will be much higher than V
A1
. The following equation must be respected (charge balance assuming now C
S
already charged at V
A1
):
V
A2
⋅ ( C
S
+ C
P1
+ C
P2
+ C
F
) = V
A
⋅ C
F
+ V
A1
⋅ ( C
P1
+ C
P2
+ C
S
)
The two transients above are not influenced by the voltage source that, due to the presence of the R
F
C
F
filter, is not able to provide the extra charge to compensate the voltage drop on
C
S
with respect to the ideal source V
A
; the time constant R
F
C
F
of the filter is very high with respect to the sampling time (T
S
). The filter is typically designed to act as anti-aliasing (see
Figure 42
).
Calling f
0
the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f
F
), according to Nyquist theorem the conversion rate f
C
must be at least 2f
0
; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (T
C
). Again the conversion period T
C
is longer than the sampling time
T
S
, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter R
F
C
F charge level on C
S
cannot be modified by the analog signal source during the time in which the sampling switch is closed.
is definitively much higher than the sampling time T
S
, so the
Figure 42.
Anti-aliasing filter and conversion rate
Analog Source Bandwidth (V
A
)
Noise
T
C
≤ 2 R
F
C
F
(Conversion Rate vs. Filter Pole) f
F
= f
0
(Anti-aliasing Filtering Condition)
2 f
0
≤ f
C
(Nyquist) f
0 f
Anti-Aliasing Filter (f
F
= RC Filter pole) Sampled Signal Spectrum (f
C
= conversion Rate) f
F f
C f
The considerations above lead to impose new constraints to the external circuit, to reduce
Obsolete Product(s) - Obsolete Product(s) above, it is simple to derive the following relation between the ideal and real sampled voltage on C
S
:
V
V
A2
=
C
P1
C
P1
+ C
P2
C
P2
+ C
F
------------------------------------------------------------
+ + C
F
+ C
S
143/180
Electrical characteristics ST10F271B/ST10F271E
From this formula, in the worst case (when V
A
is maximum, that is for instance 5V), assuming to accept a maximum error of half a count (~2.44mV), it is immediately evident a constraints on C
F
value:
C
F
> ⋅
S
In the next section an example of how to design the external network is provided, assuming some reasonable values for the internal parameters and making hypothesis on the characteristics of the analog signal to be sampled.
Example of external network sizing
●
●
●
●
●
●
●
●
●
●
●
The following hypothesis are formulated in order to proceed in designing the external network on A/D Converter input pins:
Analog Signal Source Bandwidth (f
0
): 10kHz conversion Rate (f
Sampling Time (T
C
S
):
):
25kHz
1 µ s
Pin Input Capacitance (C
P1
):
Sampling Capacitance (C
S
):
5pF
Pin Input Routing Capacitance (C
P2
): 1pF
4pF
Maximum Input Current Injection (I
INJ
): 3mA
Maximum Analog Source Voltage (V
AM)
:12V
Analog Source Impedance (R
S
): 100
Ω
Channel Switch Resistance (R
SW
Sampling Switch Resistance (R
):
AD
):
500 Ω
200
Ω
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
144/180
ST10F271B/ST10F271E Electrical characteristics
1.
Supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is:
R
C
C
F
= ------------
2
1
π f
0
= 15.9
µ s
2. Using the relation between C
F
and C
S
and taking some margin (4000 instead of 2048), it is possible to define C
F
:
C
F
=
S
= 16nF
3. As a consequence of step 1 and 2, RC can be chosen:
R
F
=
2 π f
1
0
C
F
= 995 Ω ≅ 1k Ω
4. Considering the current injection limitation and supposing that the source can go up to
12V, the total series resistance can be defined as:
R
S
+ R
F
+ R
L
=
V
I
AM
INJ
= 4k Ω from which is now simple to define the value of R
L
:
R
L
=
V
I
AM
– R
F
INJ
– R
S
= 2.9k
Ω
5. Now the three element of the external circuit R
F
, C
F
and R
L
are defined. Some conditions discussed in the previous paragraphs have been used to size the component, the other must now be verified. The relation which allow to minimize the accuracy error introduced by the switched capacitance equivalent resistance is in this case:
R
EQ
= f
C
1
= 10M Ω
C
S
So the error due to the voltage partitioning between the real resistive path and C
S
is less then half a count (considering the worst case when V
A
= 5V):
V
A
⋅
R
S
+ R
F
+ R
L
+ R
R
EQ
SW
+ R
AD
--------------------------------------------------------------------------= 2.35mV
<
1
---LSB
2
The other conditions to be verified is the time constants of the transients are really and significantly shorter than the sampling period duration T
S
:
10 ⋅ τ
τ
1
2
=
=
( R
SW
L
⋅
+
(
R
AD
C
S
)
C
⋅ C
P1
S
+
=
C
2.8ns
P2
) =
<< T
290ns
S
= 1
< T
µ
S s
= 1 µ s
Section 24.7: A/D converter characteristics on page 136
.
145/180
Electrical characteristics ST10F271B/ST10F271E
Figure 43.
Input / output waveforms
2.4V
2.0V
2.0V
Test Points
0.4V
0.8V
0.8V
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at V
IH
min. for a logic ‘1’ and V
IL
max for a logic ‘0’.
Figure 44.
Float waveforms
V
OH
Timing
Reference
Points
V
OH
- 0.1V
V
LOAD
V
LOAD
+ 0.1V
V
LOAD
- 0.1V
V
OL
+ 0.1V
V
OL
For timing purposes a port pin is no longer floating when V
LOAD
changes of ±100mV.
It begins to float when a 100mV change from the loaded V
OH
/V
OL
level occurs (I
OH
/I
OL
= 20m
The internal operation of the ST10F271 is controlled by the internal CPU clock f
CPU
. Both edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate f
CPU
. Obsolete Product(s) - Obsolete Product(s)
This influence must be regarded when calculating the timings for the ST10F271.
Obsolete Product(s) - Obsolete Product(s)
The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5).
146/180
ST10F271B/ST10F271E Electrical characteristics
Figure 45.
Generation mechanisms for the CPU clock
Phase locked loop operation f
XTAL f
CPU
Direct Clock Drive f
XTAL f
CPU
Prescaler Operation f
XTAL f
CPU
TCLTCL
TCLTCL
TCL TCL
Next
Table 68
associates the combinations of these three bits with the respective clock
generation mode.
Table 68.
On-chip clock generator selections
1
1
1
1
P0.15-13
(P0H.7-5)
1
1
0
0
1
0
1
0
CPU Frequency f
CPU
= f
XTAL
x F
F
XTAL
x 4
F
XTAL
x 3
F
XTAL
x 8
F
XTAL
x 5
External Clock
Input Range
1) 3)
4 to 8MHz
5.3 to 8MHz
4 to 8MHz
6.4 to 8MHz
Notes
Default configuration
0 1 1 1 to 64MHz
Direct Drive (oscillator bypassed)
2)
F
XTAL
x 1
0
0
1
0
0
1
F
XTAL
x 10
F
XTAL
/ 2
4 to 6.4MHz
4 to 8MHz CPU clock via prescaler
3)
F
XTAL
x 16 0 0 0 4MHz Obsolete Product(s) - Obsolete Product(s)
1.
The external clock input range refers to a CPU clock range of 1...64 MHz. Besides, the PLL usage is limited to 4-8MHz. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal oscillator amplifier (apart from Direct Drive): vice versa, the clock can be forced through an external Obsolete Product(s) - Obsolete Product(s) be used).
2.
The maximum depends on the duty cycle of the external clock signal: when 64MHz is used, 50% duty cycle shall be granted (low phase = high phase = 7.8ns); when 32MHz is selected a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 7.8ns).
3.
The limits on input frequency are 4-8MHz since the usage of the internal oscillator amplifier is required.
Also when the PLL is not used and the CPU clock corresponds to F
XTAL
/2, an external crystal or resonator shall be used: it is not possible to force any clock though an external clock source.
147/180
Electrical characteristics ST10F271B/ST10F271E
When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
CPU
is half the frequency of f
XTAL
and the high and low time of f
CPU
(i.e. the duration of an individual TCL) is defined by the period of the input clock f
XTAL
.
The timings listed in the AC Characteristics that refer to TCL therefore can be calculated using the period of f
XTAL
for any TCL.
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by the input clock signal on XTAL1 pin.
The frequency of CPU clock (f
CPU
) directly follows the frequency of f
XTAL
so the high and low time of f
CPU
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock f
XTAL
.
Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value can be calculated by the following formula:
TCL min
= 1 ⁄ f
XTAL l x l DC min
DC = duty cycle
For two consecutive TCLs, the deviation caused by the duty cycle of f
XTAL
is compensated, so the duration of 2TCL is always 1/f
XTAL
.
The minimum value TCL min
has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:
2TCL = 1 ⁄ f
XTAL
The address float timings in Multiplexed bus mode (t
11
and t
TCL (TCL max
= 1/f
XTAL
x DC max
) instead of TCL min
.
45
) use the maximum duration of
Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
safety operation with external crystal oscillator (available only when using direct drive mode
Obsolete Product(s) - Obsolete Product(s) frequency of the external crystal oscillator). This watchdog oscillator operates as following.
The reset default configuration enables the watchdog oscillator. It can be disabled by setting the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the watchdog counter. On each transition of external clock, the watchdog counter is cleared. If
148/180
ST10F271B/ST10F271E Electrical characteristics an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct clock input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct
Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply current.
24.8.7 Phase Locked Loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see
Table 68
). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (f
CPU
= f
XTAL
x F). With every F’th transition of f
XTAL
the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, so the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of f
CPU
is constantly adjusted so it is locked to f
XTAL
. The slight variation causes a jitter of f individual TCLs.
CPU
which also effects the duration of
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f
CPU
to keep it locked on f
XTAL
. The relative deviation of TCL is the maximum when it is referred to one TCL period.
This is especially important for bus cycles using wait states and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is
Section 24.8.9: PLL Jitter
24.8.8 Voltage Controlled Oscillator
The ST10F271 implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. In the following table, a detailed summary of the internal settings and VCO frequency is reported.
Table 69.
Internal PLL divider mechanism Obsolete Product(s) - Obsolete Product(s)
P0.15-13 XTAL Input
PLL
Output CPU Frequency
Frequency Prescaler
F
XTAL
/ 4
Multiply by Divide by
Prescaler f x F (P0H.7-5) Obsolete Product(s) - Obsolete Product(s)
1 1 1 4 to 8MHz 64 4 –
CPU
= f
XTAL
F
XTAL
x 4
1 1 0 5.3 to 8MHz
1)
F
XTAL
/ 4 48 4 – F
XTAL
x 3
64 2 – 1 0 1 4 to 8MHz
1 0 0 6.4 to 8MHz
1)
F
XTAL
/ 4
F
XTAL
/ 4
–
40 2 –
F
XTAL
x 8
F
XTAL
x 5
F
XTAL
x 1 0 1 1 1 to 64MHz PLL bypassed –
149/180
Electrical characteristics ST10F271B/ST10F271E
Table 69.
Internal PLL divider mechanism (continued)
PLL
P0.15-13
(P0H.7-5)
XTAL
Frequency
Input
Prescaler
Multiply by Divide by
0 1 0
0 0 1
0 0 0
4 to 6.4MHz
4 to 8MHz
1)
4MHz
F
XTAL
/ 2
–
F
XTAL
/ 2
40 2
PLL bypassed
64 2
Output
Prescaler
–
F
PLL
/ 2
–
CPU Frequency f
CPU
= f
XTAL
x F
F
XTAL
x 10
F
XTAL
/ 2
F
XTAL
x 16
The PLL input frequency range is limited to 1 to 3.5MHz, while the VCO oscillation range is
64 to 128MHz. The CPU clock frequency range when PLL is used is 16 to 64MHz.
Example 1
●
●
●
●
●
●
F
XTAL
= 4MHz
P0(15:13) = ‘110’ (Multiplication by 3)
PLL Input Frequency = 1MHz
VCO frequency = 48MHz
PLL Output Frequency = 12MHz
(VCO frequency divided by 4)
F
CPU
= 12MHz (no effect of Output Prescaler)
Example 2
●
●
●
●
●
●
F
XTAL
= 8MHz
P0(15:13) = ‘100’ (Multiplication by 5)
PLL Input Frequency = 2MHz
VCO frequency = 80MHz
PLL Output Frequency = 40MHz (VCO frequency divided by 2)
F
CPU
= 40MHz (no effect of Output Prescaler)
The following terminology is hereafter defined:
● Self referred single period jitter
Also called “Period Jitter”, it can be defined as the difference of the T where T max
is maximum time period of the PLL output clock and T max
and T min
, min
is the minimum time period of the PLL output clock.
● Self referred long term jitter
Obsolete Product(s) - Obsolete Product(s)
T max
is the maximum time difference between N+1 clock rising edges and T min
is the minimum time difference between N+1 clock rising edges. Here N should be kept Obsolete Product(s) - Obsolete Product(s) jitter.
Jitter at the PLL output can be due to the following reasons:
●
●
Jitter in the input clock
Noise in the PLL loop.
150/180
ST10F271B/ST10F271E Electrical characteristics
Jitter in the input clock
PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency jitter (frequency > PLL bandwidth) is attenuated @20dB/decade.
Noise in the PLL loop
●
●
This contribution again can be caused by the following sources:
Device noise of the circuit in the PLL
Noise in supply and substrate.
Device noise of the circuit in the PLL
The long term jitter is inversely proportional to the bandwidth of the PLL: the wider is the loop bandwidth, the lower is the jitter due to noise in the loop. Besides, the long term jitter is practically independent on the multiplication factor.
The most noise sensitive circuit in the PLL circuit is definitively the VCO (Voltage Controlled
Oscillator). There are two main sources of noise: thermal (random noise, frequency independent so practically white noise) and flicker (low frequency noise, 1/f). For the frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a 1/f
2 region in the output noise spectrum, while the flicker noise in a 1/f
3
. Assuming a noiseless
PLL input and supposing that the VCO is dominated by its 1/f
2
noise, the R.M.S. value of the accumulated jitter is
proportional to the square root of N
, where N is the number of clock periods within the considered time interval.
On the contrary, assuming again a noiseless PLL input and supposing that the VCO is dominated by its 1/f
3
noise, the R.M.S. value of the accumulated jitter is
proportional to N
, where N is the number of clock periods within the considered time interval.
The jitter in the PLL loop can be modelized as dominated by the i1/f
2
noise for N smaller than a certain value depending on the PLL output frequency and on the bandwidth characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f
3
noise component. Lastly, for N greater than a second value of N, a saturation effect is evident, so the jitter does not grow anymore when considering a longer time interval (jitter stable increasing the number of clock periods N). The PLL loop acts as a high pass filter for any noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation value corresponds to what has been called self referred long term jitter of the PLL. In
Figure 46
the maximum jitter trend versus the number of clock periods N (for some typical
CPU frequencies) is reported: the curves represent the very worst case, computed taking into account all corners of temperature, power supply and process variations: the real jitter is always measured well below the given worst case values.
Noise in supply and substrate
Obsolete Product(s) - Obsolete Product(s)
Digital supply noise adds deterministic components to the PLL output jitter, independent on multiplication factor. Its effects is strongly reduced thanks to particular care used in the Obsolete Product(s) - Obsolete Product(s) contribution of the digital noise to the global jitter is widely taken into account in the curves
Figure 46
.
151/180
Electrical characteristics
Figure 46.
ST10F271 PLL jitter
± 5
16MHz 24MHz 32MHz 40MHz
± 4
± 3
± 2
± 1
T
JIT
0
0
ST10F271B/ST10F271E
64MHz
200 400 600 800
N (CPU clock periods)
1000 1200 1400
24.8.10 PLL lock / unlock
Note:
During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the
CPU is generated, and the reference clock (oscillator) is automatically disconnected from the PLL input: in this way, the PLL goes into free-running mode, providing the system with a backup clock signal (free running frequency F free
). This feature allows to recover from a crystal failure occurrence without risking to go in an undefined configuration: the system is provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe mode.
The path between reference clock and PLL input can be restored only by a hardware reset, or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
The external RC circuit on RSTIN pin shall be properly sized in order to extend the duration of the low pulse to grant the PLL gets locked before the level at RSTIN pin is recognized high: bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitively not sufficient to get the PLL locked starting from free-running mode).
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
152/180
ST10F271B/ST10F271E Electrical characteristics
Table 70.
PLL characteristics (V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= –40 to +125°C)
Value
Symbol Parameter Conditions min.
max.
Unit
T
PSUP
T
LOCK
T
JIT
F free
PLL Start-up time
PLL Lock-in time
1)
Stable V
DD
and reference clock
Stable V
DD
and reference clock, starting from free-running mode
Single Period Jitter
1)
(cycle to cycle = 2 TCL)
6 sigma time period variation
(peak to peak)
PLL free running frequency
Multiplication Factors: 3, 4
Multiplication Factors: 5, 8, 10, 16
–
–
–500 +500
250
500
300
250
2000
4000
µ s
µ s ps kHz
1.
Not 100% tested, guaranteed by design characterization.
24.8.11 Main oscillator specifications
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= –40 to +125°C
Table 71.
Main oscillator characteristics
Value
Symbol Parameter Conditions min.
typ.
t g
V
V m
OSC
AV
STUP
Oscillator
Transconductance
Oscillation Amplitude
1)
Oscillation Voltage level
1)
Peak to Peak
Sine wave middle
Oscillator Start-up Time
1)
Stable V
DD
- Crystal
Stable V
DD
- Resonator
1.
Not 100% tested, guaranteed by design characterization.
1.4
–
–
–
–
Figure 47.
Crystal oscillator and resonator connection diagram
2.6
1.5
0.8
6
1 max.
4.2
–
–
10
2
Unit mA/V
V
V ms ms
ST10F271
ST10F271
Resonator
Obsolete Product(s) - Obsolete Product(s)
C
A
C
A
153/180
Electrical characteristics ST10F271B/ST10F271E
Table 72.
Main oscillator negative resistance (module)
C
A
= 15pF C
A
= 25pF min.
typ.
4 MHz 545 Ω 1035 Ω
8 MHz 240 Ω 450 Ω max.
–
– min.
typ.
550 Ω 1050 Ω
170 Ω 350 Ω max.
–
– min.
C
A
= 35pF typ.
max.
430 Ω
120 Ω
850 Ω
250 Ω
–
–
The given values of C
A
do not include the stray capacitance of the package and of the printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the table. The crystal shunt capacitance (C
0
) and the package capacitance between XTAL1 and XTAL2 pins is globally assumed equal to 10pF.
The external resistance between XTAL1 and XTAL2 is not necessary, since already present on the silicon.
24.8.12 32 kHz oscillator specifications
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= –40 to +125°C
Table 73.
32kHz oscillator characteristics
Value
Symbol Parameter Conditions Unit g m32
Oscillator Transconductance
1)
Start-up
Normal run
V
OSC32
Oscillation Amplitude
2)
V
AV32
Oscillation Voltage level
2) t
STUP32
Oscillator Start-up Time
2)
Peak to Peak
Sine wave middle
Stable V
DD min.
20
8
0.5
0.7
– typ.
31
17
1.0
0.9
1 max.
50
30
2.4
1.2
5
1.
At power-on a high current biasing is applied for faster oscillation start-up. Once the oscillation is started, the current biasing is reduced to lower the power consumption of the system.
2.
Not 100% tested, guaranteed by design characterization.
µ A/V
µ A/V
V
V s
Figure 48.
32kHz crystal oscillator connection diagram
ST10F271
Obsolete Product(s) - Obsolete Product(s)
C
A
C
A
154/180
ST10F271B/ST10F271E Electrical characteristics
Table 74.
Minimum values of negative resistance (module) for 32kHz oscillator
32kHz
C
A
= 6pF C
A
= 12pF C
A
= 15pF C
A
= 18pF C
A
= 22pF C
A
= 27pF C
A
= 33pF
150 k Ω 120 k Ω 90 kW
The given values of C
A
do not include the stray capacitance of the package and of the printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the table. The crystal shunt capacitance (C
0
) and the package capacitance between XTAL3 and XTAL4 pins is globally assumed equal to 4pF. The external resistance between XTAL3 and XTAL4 is not necessary, since already present on the silicon.
Warning: Direct driving on XTAL3 pin is not supported. Always use a
32kHz crystal oscillator.
24.8.13 External clock drive XTAL1
When Direct Drive configuration is selected during reset, it is possible to drive the CPU clock directly from the XTAL1 pin, without particular restrictions on the maximum frequency, since the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that targets a maximum CPU frequency of 64MHz.
In all other clock configurations (Direct Drive with Prescaler or PLL usage) the on-chip oscillator amplifier is not bypassed, so it determines the input clock speed limit. Then, when the on-chip oscillator is enabled it is forbidden to use any external clock source different from crystal or ceramic resonator.
Table 75.
External clock drive
Parameter Symbol
Direct drive f
CPU
= f
XTAL
Direct drive with prescaler f
CPU
= f
XTAL
/ 2
PLL usage f
CPU
= f
XTAL
x F
Unit min.
max.
min.
max.
min.
max.
XTAL1 period
1, 2
15.625
– 83.3
250 83.3
250 t
OSC
SR
High time
3
SR 6 – 3 – 6 – t
1
Low time
3
SR 6 – 3 – 6 – t
2
Rise time
3
SR – 2 – 2 – 2 t
3
Fall time
3 t
4
SR – 2 – 2 – 2 Obsolete Product(s) - Obsolete Product(s)
1.
The minimum value for the XTAL1 signal period shall be considered as the theoretical minimum. The real ns
2.
minimum value depends on the duty cycle of the input clock signal. external clock source only when Direct Drive mode is selected: in this case, the oscillator amplifier is bypassed so it does not limit the input frequency.
ns ns ns ns
3.
The input clock signal must reach the defined levels V
IL2
and V
IH2
.
155/180
Electrical characteristics ST10F271B/ST10F271E
Figure 49.
External clock drive XTAL1 t1
VIH2 t3 t4 t2
VIL2 t
OSC
Note: When Direct Drive is selected, an external clock source can be used to drive XTAL1. The maximum frequency of the external clock source depends on the duty cycle: when 64MHz is used, 50% duty cycle shall be granted (low phase = high phase = 7.8ns); when for instance
32MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 7.8ns).
24.8.14 Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed.
Table 76.
Memory cycle variables
Description Symbol
ALE Extension
Memory Cycle Time wait states
Memory Tri-state Time t
A t
C t
F
Values
TCL x [ALECTL]
2TCL x (15 - [MCTC])
2TCL x (1 - [MTTC])
24.8.15 External memory bus timing
The following sections include the External Memory Bus timings. The given values are computed for a maximum CPU clock of 40MHz.
Obviously, when higher CPU clock frequency is used (up to 64MHz), some numbers in the timing formulas become zero or negative which, in most cases is not acceptable or not meaningless at all. In these cases, it is necessary to relax the speed of the bus setting properly t
A
, t
C
and t
F
.
Note: All External Memory Bus Timings and SSC Timings reported in the following tables are granted by Design Characterization and not fully tested in production.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
156/180
ST10F271B/ST10F271E Electrical characteristics
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= –40 to +125°C, CL = 50pF,
ALE cycle time = 6 TCL + 2t
A
+ t
C
+ t
F
(75ns at 40MHz CPU clock without wait states)
Table 77.
Multiplexed bus timings
F
CPU
= 40 MHz
TCL = 12.5 ns
Variable CPU Clock
1/2 TCL = 1 to 64MHz
Symbol Parameter min.
max.
min.
max.
t
5 t
6 t
7 t
8 t
9 t
10 t
11 t
12 t
13 t
14 t
15
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD, WR
(with RW-delay)
ALE falling edge to RD, WR
(no RW-delay)
Address float after RD, WR
(with RW-delay) 1
Address float after RD, WR
(no RW-delay) 1
RD, WR low time
(with RW-delay)
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
RD to valid data in
(no RW-delay)
4 + t
A
1.5 + t
A
4 + t
A
4 + t
A
– 8.5 + t
A
–
–
15.5 + t
C
28 + t
C
–
–
–
–
–
–
–
6
18.5
–
–
6 + t
C
18.5 + t
C
TCL – 8.5 + t
A
TCL – 11 + t
A
TCL – 8.5 + t
A
TCL – 8.5 + t
A
– 8.5 + t
A
–
–
2TCL – 9.5 + t
C
3TCL – 9.5 + t
C
–
–
–
–
–
–
–
6
TCL + 6
–
–
2TCL – 19 + t
C
3TCL – 19 + t
C t
16 t
17
SR
SR
ALE low to valid data in
Address/Unlatched CS to valid data in
–
–
17.5 +
+ t
A
+ t
C
20 + 2t
A
+
+ t
C
–
–
3TCL – 20 +
+ t
A
+ t
C
4TCL – 30 +
+ 2t
A
+ t
C t
18
SR
Data hold after RD rising edge
0 – 0 –
Obsolete Product(s) - Obsolete Product(s) t
22
Data float after RD 1 – –
CC Data valid to WR 10 + t
C
– 2TCL – 15 + t
C
– ns ns
Obsolete Product(s) - Obsolete Product(s)
CC ALE rising edge after RD, WR – – ns ns t
25
15 + t
F
2TCL – 10 + t
F ns t
27
CC
Address/Unlatched CS hold after RD, WR
10 + t
F
– 2TCL – 15 + t
F
– ns ns ns t
38
CC ALE falling edge to Latched CS – 4 – t
A
10 – t
A
– 4 – t
A
10 – t
A ns ns ns ns ns ns ns ns ns ns ns ns
157/180
Electrical characteristics ST10F271B/ST10F271E
Table 77.
Multiplexed bus timings (continued)
F
CPU
= 40 MHz
TCL = 12.5 ns
Symbol Parameter min.
max.
t
39 t
40 t
42 t
43 t
44 t
45 t
46 t
47 t
48 t
49 t
50 t
51 t
52 t
54 t
56
SR
CC
CC
CC
CC
CC
SR
SR
CC
CC
CC
SR
SR
CC
CC
Latched CS low to Valid Data
In
–
Latched CS hold after RD, WR 27 + t
F
ALE fall. edge to RdCS, WrCS
(with RW delay)
7 + t
A
ALE fall. edge to RdCS, WrCS
(no RW delay)
Address float after RdCS,
WrCS (with RW delay) 1
– 5.5 + t
A
–
Address float after RdCS,
WrCS (no RW delay) 1
–
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS 1
Address hold after
RdCS, WrCS
Data hold after WrCS
–
–
15.5 + t
28 + t
10 + t
0
–
6 + t
6 + t
C
C
F
F
C
–
–
1.5
14
4 + t
C
16.5 + t
C
–
–
–
–
16.5 + t
F
–
–
Variable CPU Clock
1/2 TCL = 1 to 64MHz min.
16.5 + t
C
+
+ 2t
A
–
–
3TCL – 10.5 + t
F
TCL – 5.5 + t
A
– 5.5 + t
A
–
–
–
–
2TCL – 9.5 + t
C
3TCL – 9.5 + t
C
2TCL – 15 + t
C
0
–
2TCL – 19 + t
F
2TCL – 19 + t
F max.
3TCL – 21 +
+ t
C
+ 2t
A
–
–
–
1.5
TCL + 1.5
2TCL – 21 + t
C
3TCL – 21 + t
C
–
–
–
–
2TCL – 8.5 + t
F
–
– ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
158/180
ST10F271B/ST10F271E Electrical characteristics
Figure 50.
External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE t
5 t
16 t
25
ALE t
6 t
38 t
17 t
39 t
27 t
40
CSx t
6 t
17 t
27
A23-A16
(A15-A8)
BHE
Address
Read cycle
Address/data bus (P0) t
6
Address t
7 t
16
Data in t
1
Address
RD t
9 t
8 t
10 t
14 t
1 t
15 t
13 t
12
Address t
19
Write cycle
Address/data bus (P0)
Data out t
23 t
8 t
22
WR
WRL
WRH t
9 t
12 t
13
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
159/180
Electrical characteristics ST10F271B/ST10F271E
Figure 51.
External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE t
5 t
16 t
25
ALE t
6 t
38 t
17 t
39 t
27 t
40
CSx t
6 t
17
A23-A16
(A15-A8)
BHE
Address t
27
Read cycle t
6 t
7
Address Data in
Address/Data
Bus (P0) t
9 t
8 t
11 t
10 t
18 t
19 t
14
RD t
15 t
12 t
13
Write cycle
Address Data out
Address/Data
Bus (P0) t
23 t
8 t
9 t
11 t
10 t
22 WR
WRL
WRH t
13 t
12
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
160/180
ST10F271B/ST10F271E Electrical characteristics
Figure 52.
External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS
CLKOUT t
5 t
16 t
25
ALE t
6 t
27 t
17
A23-A16
(A15-A8)
BHE
Address t
6 t
7 t
16
Read Cycle
Address/Data
Bus (P0)
Address Data In t
51
Address t
42 t
52 t
44 t
46
RdCSx t
49 t
48 t
43 t
45 t
47 t
55
Write Cycle
Address/Data
Bus (P0)
Address Data Out t
42 t
50
WrCSx t
43 t
49 t
48
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
161/180
Electrical characteristics ST10F271B/ST10F271E
Figure 53.
External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS
CLKOUT t
16 t
5 t
25
ALE t
6
A23-A16
(A15-A8)
BHE t
17
Address t
54
Read cycle
Address/Data
Bus (P0)
RdCSx t
6
Address t
7 t
43 t
42 t
44 t
45 t
47 t
49 t
46 t
48
Data in t
18 t
19
Write cycle
Address/data bus (P0)
Address Data out t
42 t
56 t
43 t
45 t
44 t
50
WrCSx t
48 Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
162/180
ST10F271B/ST10F271E Electrical characteristics
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= –40 to +125°C, CL = 50pF,
ALE cycle time = 4 TCL + 2t
A
+ t
C
+ t
F
(50ns at 40MHz CPU clock without wait states).
Table 78.
Demultiplexed bus timings
Symbol Parameter
F
CPU
= 40 MHz
TCL = 12.5 ns
Variable CPU Clock
1/2 TCL = 1 to 64MHz min.
max.
min.
max.
t
5 t
6 t
80 t
81 t
12 t
13 t
14
CC ALE high time
CC Address setup to ALE
CC
CC
Address/Unlatched CS setup to RD, WR
(with RW-delay)
Address/Unlatched CS setup to RD, WR
(no RW-delay)
CC
CC
SR
RD, WR low time
(with RW-delay)
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
4 + t
A
1.5 + t
A
12.5 + 2t
A
0.5 + 2t
A
15.5 + t
C
28 + t
C
–
–
–
–
–
–
–
6 + t
C
TCL – 8.5 + t
A
TCL – 11 + t
A
2TCL – 12.5 +
+ 2t
A
TCL – 12 + 2t
A
2TCL – 9.5 + t
C
3TCL – 9.5 + t
C
–
–
–
–
–
–
–
2TCL – 19 + t
C t
15
SR
RD to valid data in
(no RW-delay)
– 18.5 + t
C
– 3TCL – 19 + t
C t
16 t
17
SR ALE low to valid data in
SR
Address/Unlatched CS to valid data in
–
–
17.5 + t
A
+
+ t
C
20 + 2t
A
+
+ t
C
–
–
3TCL – 20 +
+ t
A
+ t
C
4TCL – 30 +
+ 2t
A
+ t
C t
18
SR
Data hold after RD rising edge
0 – 0 – t
20 t
21
SR
SR
Data float after RD rising edge (with RW-delay)
3 1
Data float after RD rising edge (no RW-delay)
1
–
–
16.5 + t
F
4 + t
F
–
–
2TCL – 8.5 +
+ t
F
+ 2t
A
TCL – 8.5 +
+ t
F
+ 2t
A t
22 t
24
CC Data valid to WR
CC Data hold after WR
10 + t
C
4 + t
F
–
–
2TCL – 15 + t
C
TCL – 8.5 + t
F
–
– ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t
26
–10 + t
F
– –10 + t
F
– ns t
28
CC t
28h
CC
WR
Address/Unlatched CS hold after RD, WR
2
Address/Unlatched CS hold after WRH
0 + t
F
– 5 + t
F
–
–
0 + t
F
– 5 + t
F
–
– ns ns
163/180
Electrical characteristics ST10F271B/ST10F271E
Table 78.
Demultiplexed bus timings (continued)
F
CPU
= 40 MHz
TCL = 12.5 ns
Symbol Parameter min.
max.
t
38 t
39 t
41 t
82 t
83 t
46 t
47 t
48 t
49 t
50 t
51 t
53 t
68 t
55 t
57
CC
SR
CC
CC
CC
SR
SR
CC
ALE falling edge to Latched
CS
Latched CS low to Valid Data
In
Latched CS hold after RD,
WR
Address setup to RdCS,
WrCS
(with RW-delay)
Address setup to RdCS,
WrCS
(no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
CC
RdCS, WrCS Low Time
(no RW-delay)
CC Data valid to WrCS
SR Data hold after RdCS
SR
Data float after RdCS
(with RW-delay)
3
SR
CC
Data float after RdCS
(no RW-delay)
3
Address hold after
RdCS, WrCS
CC Data hold after WrCS
– 4 – t
A
–
2 + t
F
14 + 2t
A
2 + 2t
A
–
–
15.5 + t
C
28 + t
C
10 + t
C
0
–
–
– 8.5 + t
F
2 + t
F
6 – t
A
16.5 +
+ t
C
+ 2t
A
–
–
–
4 + t
C
16.5 + t
C
–
–
–
–
16.5 + t
F
4 + t
F
–
–
Variable CPU Clock
1/2 TCL = 1 to 64MHz min.
– 4 – t
A
–
TCL – 10.5 + t
F
2TCL – 11 + 2t
A
TCL –10.5 + 2t
A
–
–
2TCL – 9.5 + t
C
3TCL – 9.5 + t
C
2TCL – 15 + t
C
0
–
–
– 8.5 + t
F
TCL – 10.5 + t
F max.
6 – t
A
3TCL – 21 +
+ t
C
+ 2t
A
–
–
–
2TCL – 21 + t
C
3TCL – 21 + t
C
–
–
–
–
2TCL – 8.5 + t
F
TCL – 8.5 + t
F
–
–
1.
RW-delay and t
A
refer to the next following bus cycle.
Obsolete Product(s) - Obsolete Product(s)
3.
Partially tested, guaranteed by design characterization.
Obsolete Product(s) - Obsolete Product(s) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
164/180
ST10F271B/ST10F271E Electrical characteristics
Figure 54.
External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE
CLKOUT t
5 t
26 t
9
ALE t
6 t
38 t
17 t
39 t
41 t
41u
CSx
A23-A16
A15-A0 (P1)
BHE t
6 t
17
Address t
28
(or t
28h
)
Read cycle
Data bus (P0)
(D15-D8) D7-D0 t
81 t
80 t
14 t
15 t
18
Data in t
21 t
20
RD t
13 t
12
Write cycle
Data bus (P0)
(D15-D8) D7-D0
Data out t
81 t
80 t
22 t
24
WR Obsolete Product(s) - Obsolete Product(s)
WRH t
13 t
12 Obsolete Product(s) - Obsolete Product(s)
165/180
Electrical characteristics ST10F271B/ST10F271E
Figure 55.
Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE
CLKOUT
ALE t
16 t
26 t
5 t
6 t
38 t
17 t
39 t
28 t
41
CSx t
6 t
28
A23-A16
A15-A0 (P1)
BHE
Read cycle
Data bus (P0)
(D15-D8) D7-D0 t
81 t
80 t
17
Address t
14 t
15 t
18
Data in t
21 t
20
RD t
13 t
12
Write cycle
Data bus (P0)
(D15-D8) D7-D0 Data out t
81 t
80 t
22 t
24
Obsolete Product(s) - Obsolete Product(s) t
12 WRH
Obsolete Product(s) - Obsolete Product(s)
166/180
ST10F271B/ST10F271E Electrical characteristics
Figure 56.
External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS
CLKOUT t
5 t
26 t
16
ALE
A23-A16
A15-A0 (P1)
BHE t
6 t
17
Address t
55
Read cycle
Data bus (P0)
(D15-D8) D7-D0 t
83 t
82 t
46 t
47 t
5
Data in t
68 t
53
RdCSx t
49 t
48
Write cycle
Data bus (P0)
(D15-D8) D7-D0
Data out t
83 t
82 t
50 t
57
WrCSx t
48 t
49
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
167/180
Electrical characteristics ST10F271B/ST10F271E
Figure 57.
External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS
CLKOUT
ALE t
5 t
16 t
26 t
6 t
55
A23-A16
A15-A0 (P1)
BHE
Read cycle
Data bus (P0)
(D15-D8) D7-D0 t
83 t
82 t
17
Address t
47 t
46 t
51
Data in t
68 t
53
RdCSx t
49 t
48
Write cycle
Data bus (P0)
(D15-D8) D7-D0
Data out t
83 t
82 t
57 t
50
WrCSx t
49 t
48
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
168/180
ST10F271B/ST10F271E Electrical characteristics t
29 t
30 t
31 t
32 t
33
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to + 125°C, CL = 50pF
Table 79.
CLKOUT and READY timings
Symbol Parameter
F
CPU
= 40 MHz
TCL = 12.5 ns
Variable CPU Clock
1/2 TCL = 1 to 64MHz t
34 t
35 t
36 t
37 t
58 t
59 t
60
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Synchronous READY setup time to CLKOUT
Synchronous READY hold time after CLKOUT
Asynchronous READY low time
Asynchronous READY setup time
1
Asynchronous READY hold time
1
Async. READY hold time after
RD, WR high (Demultiplexed
Bus)
2 min.
25
9
10
–
–
– 2 + t
A
17
2
35
17
2
0 max.
25
–
–
4
4
8 + t
A
–
–
–
–
–
2t
A
+ t
C
+ t
F min.
2TCL
TCL – 3.5
TCL – 2.5
–
–
– 2 + t
A
17
2
2TCL + 10
17
2
0 max.
2TCL
–
–
4
4
8 + t
A
–
–
–
–
–
2t
A
+ t
C
+ t
F ns ns ns ns ns ns ns
1.
These timings are given for characterization purposes only, in order to assure recognition at a specific clock edge.
2.
Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.
This adds even more time for deactivating READY. 2t
A to the current bus cycle.
and t
C
refer to the next following bus cycle, t
F
refers ns ns ns ns ns
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
169/180
Electrical characteristics ST10F271B/ST10F271E
Figure 58.
CLKOUT and READY
CLKOUT
ALE t
32 t
30 t
34
Running cycle 1) t
33 t
31 t
29
READY wait state MUX / Tri-state 6)
7)
RD, WR
Synchronous
READY
Asynchronous t
58
READY
3) t
59
2) t
35 t
36 t
58
3) t
59
3) t
37
5) t
35 t
36
3) t
60 4)
6)
1.
Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2.
The leading edge of the respective command depends on RW-delay.
3.
READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
LOW at this sampling point terminates the currently running bus cycle.
4.
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5.
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t
37
in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4).
6.
Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus without MTTC wait state this delay is zero.
7.
The next external bus cycle may start here.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
170/180
ST10F271B/ST10F271E Electrical characteristics
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to +125°C, C
L
= 50pF
Table 80.
External bus arbitration timings
Symbol Parameter
F
CPU
= 40 MHz
TCL = 12.5 ns min.
max.
t t t
61
62
63 t
64 t
65 t
66 t
67
SR
CC
CC
CC
CC
CC
CC
HOLD input setup time to CLKOUT
CLKOUT to HLDA high or BREQ low delay
CLKOUT to HLDA low or BREQ high delay
CSx release
1)
CSx drive
Other signals release
1)
Other signals drive
18.5
–
–
–
– 4
–
– 4
1.
Partially tested, guaranteed by design characterization.
–
12.5
12.5
20
15
20
15
Figure 59.
External bus arbitration (releasing the bus)
Variable CPU Clock
1/2 TCL = 1 to 64MHz min.
max.
18.5
–
–
–
– 4
–
– 4
–
12.5
12.5
20
15
20
15 ns ns ns ns ns ns ns
CLKOUT t
61
HOLD t
63
1)
HLDA t
62
BREQ
3)
2) t
64
CSx
(P6.x) t
66 1)
Others
Obsolete Product(s) - Obsolete Product(s)
1.
The ST10F271 will complete the currently running bus cycle before granting bus access.
Obsolete Product(s) - Obsolete Product(s)
3.
The CS outputs will be resistive high (pull-up) after t
64
.
171/180
Electrical characteristics ST10F271B/ST10F271E
Figure 60.
External bus arbitration (regaining the bus)
2)
CLKOUT t
61
HOLD t
62
HLDA
BREQ t
62 t
62
1) t
63 t
65
CSx
(On P6.x) t
67
Other signals
1.
This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F271 requesting the bus.
2.
The next ST10F271 driven bus cycle may start here.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
172/180
ST10F271B/ST10F271E Electrical characteristics
24.8.20 High-speed synchronous serial interface (SSC) timing
Master mode
V
DD
= 5V ±10%, V
SS
= 0V, T
A
= -40 to +125°C, C
L
= 50pF
Table 81.
SSC master mode timings
Symbol Parameter
Max. Baudrate 6.6MBd
(1)
@F
CPU
= 40MHz
(<SSCBR> = 0002h)
Variable Baudrate
(<SSCBR> = 0001h -
FFFFh)
Unit min.
max.
min.
max.
t
300 t
301 t
302 t
303 t
304 t
305 t
306 t
307p t
308p t
307 t
308
CC SSC clock cycle time
(2))
CC SSC clock high time
CC SSC clock low time
CC SSC clock rise time
CC SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge
(3)
SR
Read data setup time before latch edge, phase error detection on
(SSCPEN = 1)
SR
Read data hold time after latch edge, phase error detection on
(SSCPEN = 1)
SR
Read data setup time before latch edge, phase error detection off
(SSCPEN = 0)
SR
Read data hold time after latch edge, phase error detection off
(SSCPEN = 0)
150
63
63
–
–
–
– 2
37.5
50
25
0
150
–
–
10
10
15
–
–
–
–
– t
300
/ 2 – 12 t
300
/ 2 – 12
–
–
–
– 2
2TCL + 12.5
–
–
10
10
15
–
–
4TCL –
2TCL
0
–
–
1.
Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with
48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only with CPU clock equal to (or lower than) 32MHz.
2.
Formula for SSC Clock Cycle time: t
300
= 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t
300
is 125ns (corresponding to 8Mbaud).
3.
Partially tested, guaranteed by design characterization.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s) ns ns ns ns ns ns ns ns ns ns
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Electrical characteristics
Figure 61.
SSC master timing
1) t
300 t
301 t
302
SCLK
MTSR
MRST t
305 t
304 t
305
1st out bit t
303 t
306
2nd out bit t
307 t
308
1st in bit 2nd In bit
2)
ST10F271B/ST10F271E t
305
Last out bit t
307 t
308
Last in bit
1.
The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b).
2.
The bit timing is repeated for all bits to be transmitted or received.
Slave mode
V
DD
= 5V ±10%, V
SS
= 0V, T
A
= -40 to +125°C, C
L
= 50pF
Table 82.
SSC slave mode timings
Symbol Parameter
Max. Baudrate
6.6 MBd
(1) )
@F
CPU
= 40MHz
(<SSCBR> = 0002h)
Variable Baudrate
(<SSCBR> = 0001h -
FFFFh) Unit min.
max.
min.
max.
t
310 t
311 t
312 t
313 t
314
SR SSC clock cycle time
(2)
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
150
63
63
–
–
150
–
–
10
10 t
310
/ 2 – 12 t
310
/ 2 – 12
–
–
–
–
10
10
CC Write data valid after shift edge – 55 – 2TCL + 30 t
315 t
316
CC Write data hold after shift edge
Read data setup time before latch
0 – 0 – Obsolete Product(s) - Obsolete Product(s) ns t
317p
Read data hold time after latch
62 – 4TCL + 12 – SR edge, phase error detection on Obsolete Product(s) - Obsolete Product(s) ns t
318p
SR 87 – 6TCL + 12 – ns edge, phase error detection on
(SSCPEN = 1) ns ns ns ns ns
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ST10F271B/ST10F271E Electrical characteristics
Table 82.
SSC slave mode timings
Symbol Parameter
Max. Baudrate
6.6 MBd
(1)
)
@F
CPU
= 40MHz
(<SSCBR> = 0002h)
Variable Baudrate
(<SSCBR> = 0001h -
FFFFh) Unit min.
max.
min.
max.
t t
317
318
SR
Read data setup time before latch edge, phase error detection off
(SSCPEN = 0)
SR
Read data hold time after latch edge, phase error detection off
(SSCPEN = 0)
6
31
–
–
6
2TCL + 6
–
–
1.
Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with
48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32MHz (after checking that resulting timings are suitable for the master).
2.
Formula for SSC Clock Cycle time: t
310
= 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
310
is 125ns (corresponding to 8Mbaud).
ns ns
Figure 62.
SSC slave timing
1) t
310 t
311 t
312
2)
SCLK
MRST t
315 t
314 t
315
1st out bit 2nd out bit t
313 t
316 t
317 t
318 t
315
Last out bit t
317 t
318
MTSR 1st in bit 2nd in bit Last in bit
1.
The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b).
2.
The bit timing is repeated for all bits to be transmitted or received.
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Package information ST10F271B/ST10F271E
Figure 63.
PQFP144 mechanical data and package dimension
E3
L
L1
K
DIM.
A
A1
A2
B mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
4.07
0.160
0.25
0.010
C
D
3.17
3.42
3.67
0.125
0.135
0.144
0.22
0.38
0.009
0.015
0.13
30.95
31.20
0.23
31.45
0.005
1.219
1.228
0.009
1.238
D1 27.90
28.00
28.10
1.098
1.102
1.106
D3 22.75
0.896
e 0.65
0.026
E 30.95
31.20
31.45
1.219
1.228
1.238
E1 27.90
28.00
28.10
1.098
1.102
1.106
22.75
0.896
0.65
0.80
0.95
0.026
0.031
0.037
1.60
0.063
0°
(min.), 7
°
(max.)
OUTLINE AND
MECHANICAL DATA
PQFP144
D
D1
D3
A1
A
A2
108
109
73
72
0.10mm
.004
Seating Plane
1 e
C Obsolete Product(s) - Obsolete Product(s)
K
PQFP144
176/180
ST10F271B/ST10F271E Package information
Figure 64.
TQFP144 mechanical data and package dimension
L
L1
K
E1
E3 e
E
C
D
D1
D3
DIM.
mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
A1
A2
B
0.05
1.35
0.17
0.09
1.40
0.22
1.60
0.15
1.45
0.27
0.002
0.053
0.007
0.20
0.003
0.055
0.009
0.063
0.006
0.057
0.011
0.008
22.00
20.00
17.50
0.866
0.787
0.689
0.45
0.50
22.00
20.00
17.50
0.60
1.00
0.75
0.018
0.020
0.866
0.787
0.689
0.024
0.0393
3.5˚ (min.), 7˚(max.)
0.030
OUTLINE AND
MECHANICAL DATA
TQFP144
(20x20x1.40mm)
Note 1: Exact shape of each corner is optional.
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Ordering information ST10F271B/ST10F271E pecific
Table 83.
Order codes
Part number Package
F271-AEA-P
F271-AEA-P-TR
F271-AEA-T
F271-AEA-T-TR
F271-AEA5-T-TR
F271-BAG-P
F271-BAG-T
F271-BAG-T-TR
F271-BAG5-T
F271-BAG5-T-TR
PQFP144
TQFP144
TQFP144
PQFP144
TQFP144
TQFP144
Packing
Tray
Tape and reel
Tray
Tape and reel
Tape and reel
Tray
Tray
Tape and reel
Tray
Tape and reel
B/E
Type
E
B
B
B
E
B
Temperature range (°C)
CPU frequency range (MHz)
-40 to +125
°
C 1 to 64
-40 to +125
°
C
-40 to +105
°
C
-40 to +125
°
C
-40 to +125
°
C
-40 to +105
°
C
1 to 40
1 to 48
1 to 64
1 to 40
1 to 48
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ST10F271B/ST10F271E
Table 84.
Document revision history
Date Revision
12-Jul-2006 1 Initial release.
Changes
Revision history
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ST10F271B/ST10F271E
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