System reset ST10F271B/ST10F271E
System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in
.
Table 48.
Reset event definition
Reset Source
Power-on reset
Asynchronous Hardware reset
Synchronous Long Hardware reset
Synchronous Short Hardware reset
Watchdog Timer reset
Software reset
Flag
PONR
LHWR
SHWR
WDTR
SWR
RPD
Status
Low
Low
High
High
3)
3)
Conditions
Power-on t
RSTIN
>
1) t
RSTIN
> (1032 + 12) TCL + max(4 TCL,
500ns) t
RSTIN
> max(4 TCL, 500ns) t
RSTIN
≤
500ns)
WDT overflow
SRST instruction execution
1)
RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
2)
Section 20.1
for more details on minimum reset pulse duration.
3)
The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to
Sections 20.4
,
20.5
and
20.6
).
On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes shorter than 50ns. On the other side, a valid pulse shall be longer than 500ns to grant that
ST10 recognizes a reset command. In between 50ns and 500ns a pulse can either be filtered or recognized as valid, depending on the operating conditions and process variations.
For this reason all minimum durations mentioned in this Chapter for the different kind of reset events shall be carefully evaluated taking into account of the above requirements.
In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input reset pulse duration, the operating frequency is a key factor. Examples:
● For a CPU clock of 64 MHz, 4 TCL is 31.25ns, so it would be filtered. In this case the Obsolete Product(s) - Obsolete Product(s)
● For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula
Obsolete Product(s) - Obsolete Product(s)
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