STMicroelectronics STWLC03 Datasheet

STWLC03

Dual mode Qi/PMA wireless power receiver

Datasheet - production data



Flip Chip 77 bumps (3.12x4.73 mm)

Applications



Cellular phones



Power banks



Navigation systems



Tablets



Medical and healthcare instrumentation

Features



1 W to 12 W output power



Qi 1.1 and PMA wireless standard communication protocols



Integrated high efficiency synchronous rectifier



800 kHz programmable step-down converter with input current and input voltage regulation loops



Step-down converter efficiency up to 90%



Simplified Li-Ion/Polymer charger function



32-bit, 16 MHz embedded microcontroller with 16 kB ROM and 2 kB RAM memory



2 kB NVM for customization



Integrated driver for external supply switch



Precise voltage and current measurements



I for received power calculation

2 C interface



Configurable GPIO output



Rx coil NTC protection



Thermal protection



Low power dissipative rectifier overvoltage clamp

Order code Description

Description

The STWLC03 is an integrated wireless power receiver solution suitable for portable applications. The STWLC03 is able to operate with Qi 1.1 or PMA communication protocol.

Thanks to the integrated low impedance synchronous rectifier and DC-DC step-down converter, the STWLC03 achieves high efficiency, low power dissipation and output power beyond 5 W. Digital control and precise analog control loops ensure stable operation. I 2 C interface allows many parameters to be customized in the device and this configuration can be stored in the embedded NVM.

The STWLC03 can deliver the output power in two modes: as a power supply with configured output voltage or as a simple CC/CV battery charger with configurable charging current.

The STWLC03 can detect an external (wired) power supply connection and drive an external power switch.

Table 1: Device summary

Package Packing

STWLC03JR 12 W output Flip Chip 77 bumps (3.12x4.73 mm) Tape and reel

March 2017 DocID029451 Rev 2

This is information on a product in full production.

1/56 www.st.com

Contents

Contents

STWLC03

1 Introduction ..................................................................................... 6

2 Pin configuration ............................................................................. 7

3 Maximum ratings ........................................................................... 10

4 Electrical characteristics .............................................................. 12

5 Device description ......................................................................... 17

5.1

5.2

5.3

5.4

5.5

5.6

Using the STWLC03 as a power supply .......................................... 17

Using the STWLC03 as a battery charger ....................................... 17

Wireless standard auto-detection .................................................... 18

Qi operation and flow chart ............................................................. 19

5.4.1

Received power calibration (FOD feature) ....................................... 21

PMA operation ................................................................................ 21

External power supply ..................................................................... 22

5.7

The device interface ........................................................................ 24

6 I 2 C register description ................................................................. 25

6.1

6.2

ADC measured values .................................................................... 31

Service registers ............................................................................. 33

7 Non-volatile memory ..................................................................... 35

7.1

NVM sector maps ............................................................................ 35

8 Application information ................................................................ 45

8.1

8.2

8.3

Application schematic and recommended external components..... 45

External passive component selection ............................................ 49

8.2.1

Input resonant circuit component selection (L1, C1, C2) ................. 49

8.2.2

Voltage clamp resistor selection (RCL1, RCL2) ............................... 49

8.2.3

Load modulation capacitors selection (CM1, CM2) ......................... 49

8.2.4

Feedback resistor divider components selection (RFB1, RFB2) ..... 49

8.2.5

Rx NTC circuit component selection (RNTC, R1) ............................ 49

8.2.6

Soft-start capacitor selection (C10) .................................................. 50

8.2.7

External supply transistor selection .................................................. 50

Reference PCB layout ..................................................................... 51

9 Package information ..................................................................... 53

9.1

Flip Chip 77 bumps (3.12x4.73 mm) package information .............. 53

10 Revision history ............................................................................ 55

2/56 DocID029451 Rev 2

STWLC03

List of tables

List of tables

Table 1: Device summary ........................................................................................................................... 1

Table 2: Pin description .............................................................................................................................. 7

Table 3: Absolute maximum ratings ......................................................................................................... 10

Table 4: Thermal data ............................................................................................................................... 11

Table 5: Electrical characteristics ............................................................................................................. 12

Table 6: Recommended VRECT and VRMIN values for various VOUT .................................................. 17

Table 7: EPT reasons in Qi ....................................................................................................................... 20

Table 8: EOC reasons in PMA .................................................................................................................. 22

Table 9: User register map ....................................................................................................................... 25

Table 10: Control register ......................................................................................................................... 25

Table 11: Target rectified voltage register (register address 02h) ............................................................ 26

Table 12: Input voltage threshold for output power limitation register (register address 03h) ................. 26

Table 13: Input current limit register (register address 05h) ..................................................................... 26

Table 14: Overload threshold register (register address 06h) .................................................................. 26

Table 15: Step-down output voltage register (register address 07h) ....................................................... 27

Table 16: Step-down converter feedback voltages .................................................................................. 27

Table 17: Buck current limit register ......................................................................................................... 27

Table 18: Chip overtemperature threshold register (register address 09h) .............................................. 27

Table 19: Interrupt mask L register (register address 0Ah) ...................................................................... 27

Table 20: Interrupt mask H register ( register address 0Bh) .................................................................... 28

Table 21: Interrupt status L register ( register address 0Ch) .................................................................... 28

Table 22: Interrupt status H register ......................................................................................................... 29

Table 23: Interrupt latch L register ............................................................................................................ 29

Table 24: Interrupt latch H register ........................................................................................................... 29

Table 25: Operation mode detection status register ................................................................................. 30

Table 26: Operation mode detection control register (register address 11h) ........................................... 30

Table 27: Qi charge status register (register address 12h) ...................................................................... 31

Table 28: Charger status register (register address 13h) ......................................................................... 31

Table 29: Charger control register ............................................................................................................ 31

Table 30: ADC measured value register map .......................................................................................... 31

Table 31: Rectified voltage (VRECT) ........................................................................................................ 32

Table 32: Rectified output current (IRECT) .............................................................................................. 32

Table 33: RX coil NTC voltage ................................................................................................................. 32

Table 34: VOUT voltage ........................................................................................................................... 32

Table 35: VDROP voltage ........................................................................................................................ 33

Table 36: Chip temperature ...................................................................................................................... 33

Table 37: Ground voltage ......................................................................................................................... 33

Table 38: RX_POWER ............................................................................................................................. 33

Table 39: Service register map ................................................................................................................. 34

Table 40: NVM control .............................................................................................................................. 34

Table 41: I2C registers corresponding to bytes in NVM sector ................................................................ 34

Table 42: Non-volatile memory sector map .............................................................................................. 35

Table 43: Map of NVM sector 04 .............................................................................................................. 35

Table 44: Byte 0 ........................................................................................................................................ 36

Table 45: Byte 1 ........................................................................................................................................ 36

Table 46: Byte 2 ........................................................................................................................................ 36

Table 47: Byte 3 ........................................................................................................................................ 36

Table 48: Byte 4 ........................................................................................................................................ 37

Table 49: Map of NVM sector 05 .............................................................................................................. 37

Table 50: Map of NVM sector 07 .............................................................................................................. 38

Table 51: Map of NVM sector 08 .............................................................................................................. 39

Table 52: Map of NVM sector 10 .............................................................................................................. 40

Table 53: Map of NVM sector 13 .............................................................................................................. 41

DocID029451 Rev 2 3/56

List of tables STWLC03

Table 54: Byte 0 Qi_EPT_threshold [7:0] ................................................................................................. 41

Table 55: Byte 1, Qi_EPT_Time [7:0] ....................................................................................................... 41

Table 56: Byte 2, Qi charger enable ......................................................................................................... 42

Table 57: Qi target voltage ....................................................................................................................... 42

Table 58: Byte 3, Q1_Precharge_Battery_overvoltage ............................................................................ 42

Table 59: Byte 4, Q1_Precharge and Fastcharge .................................................................................... 42

Table 60: Byte 8, PMA_EOC_theshold [7:0] ............................................................................................ 43

Table 61: Byte 9, PMA_EOC_Time [7:0] .................................................................................................. 43

Table 62: Byte 10, PMA_Target_Voltage [2:0] ......................................................................................... 43

Table 63: PMA target voltage vs charging voltage ................................................................................... 44

Table 64: Byte 11 ...................................................................................................................................... 44

Table 65: Byte 12 ...................................................................................................................................... 44

Table 66: STWLC03 recommended external components....................................................................... 46

Table 67: Flip Chip 77 bumps (3.12x4.73 mm) package mechanical data .............................................. 54

Table 68: Document revision history ........................................................................................................ 55

4/56 DocID029451 Rev 2

STWLC03

List of figures

List of figures

Figure 1: Simplified block diagram .............................................................................................................. 6

Figure 2: Pin configuration Flip Chip 77 bumps (3.12x4.73 mm) ............................................................... 7

Figure 3: Typical step-down converter efficiency ..................................................................................... 17

Figure 4: Typical charging profile .............................................................................................................. 18

Figure 5: Wireless standard detection flowchart ....................................................................................... 19

Figure 6: Qi simplified flow diagram .......................................................................................................... 20

Figure 7: PMA simplified flow diagram ..................................................................................................... 21

Figure 8: External power supply situation ................................................................................................. 23

Figure 9: External power supply situation 1 .............................................................................................. 23

Figure 10: STWLC03 application schematic ............................................................................................ 45

Figure 11: STWLC03 charger configuration ............................................................................................. 46

Figure 12: VIO and digital interface in standalone application schematic ................................................ 48

Figure 13: VIO and digital interface in platform application schematic ..................................................... 48

Figure 14: Top overlay .............................................................................................................................. 51

Figure 15: Top layer .................................................................................................................................. 51

Figure 16: Mid layer 1 ............................................................................................................................... 51

Figure 17: Mid layer 2 ............................................................................................................................... 51

Figure 18: Bottom layer............................................................................................................................. 52

Figure 19: Flip Chip 77 bumps (3.12x4.73 mm) package outline ............................................................. 53

Figure 20: Flip Chip 77 bumps (3.12x4.73 mm) recommended footprint ................................................. 54

DocID029451 Rev 2 5/56

Introduction

1

STWLC03

Introduction

The STWLC03 is a dual mode Qi/PMA wireless power receiver. It works as a voltage source with regulated output voltage, typically 5 V. It can be reconfigured into a simple battery charger mode (CC/CV) to charge directly Li-Ion or Li-Pol batteries. The STWLC03 can operate autonomously or can be controlled through I 2 C by the host system.

Figure 1: Simplified block diagram

6/56 DocID029451 Rev 2

STWLC03

2

Pin configuration

Pin configuration

Figure 2: Pin configuration Flip Chip 77 bumps (3.12x4.73 mm)

RMOD1

VRECT

BOOT1

BOOT2

BOOT

CLAMP

VSUP

VSUPS

Pin name

AC1

AC2

MOD1

MOD2

CLMP1

CLMP2

RMOD

Pin position

F6, F7, G7

E9, E10, E11

G6

F11

G5

F9

E7

G11

F10, G10

G8

E8

G9

F8

A8, B8, B7

A7, C6

Table 2: Pin description

Description

RX coil circuit terminal connection

RX coil circuit terminal connection

Load modulation capacitor 1 connection

Load modulation capacitor 2 connection

Clamping capacitor/resistor 1 connection

Clamping capacitor/resistor 2 connection

Modulation current sink connection, internally connected to

VRECT

Load modulation external resistor connection.

RM resistor is not necessary for most applications

Synchronous rectifier output

Bootstrap capacitor connection for the rectifier

Bootstrap capacitor connection for the rectifier

Bootstrap capacitor connection for the step-down converter

Low power clamp connection

Power supply input for the step-down converter

Sensing terminal of the external current sensing resistor

DocID029451 Rev 2 7/56

Pin configuration

Pin name

RESL

VOUT

VFB

FBGND

LX

NTCRX

VA

VCORE

V5V

VIO

SCL

SDA

GPIO0

GPIO1

GPIO2

GPIO3

RESET

INT

RPGND

BPGND

GND

AGND

VEXT

SWDRV

USBOK

COMP

GND

VCORE

Pin position

A6

D5

A5

B6

A11, B11, B10

A3

A4

F2

A9, B9

G1

D1

D4

D6

E5

STWLC03

Description

Sensing terminal of the external current sensing resistor

Step-down output voltage

Step-down feedback input

Ground connection of the resistor feedback divider for stepdown converter

Step-down converter coil connection

Comparator input for RX coil temperature sensing

NTC thermistor has to be placed close to RX coil

LDO1 output to filtering capacitor. ADC supply and sensitive analog circuitries are connected to this LDO; any external circuit cannot be connected to this node

LDO2 output to filtering capacitor. The microcontroller core and logic supply. VCORE voltage can be used as a reference voltage for the RX coil NTC divider

LDO3 output to filtering capacitor

VIO power supply for the digital interface. It can be connected to VCORE or provided externally

I 2 C clock input

I 2 C data

General purpose push-pull I/O pin. This function depends on firmware configuration

General purpose push-pull I/O pin. This function depends on firmware configuration

E4

E1

General purpose push-pull I/O pin. This function depends on firmware configuration

Open drain output pin only. This function depends on firmware configuration

D2

C3

Chip reset input, active low

Open drain interrupt output to the host platform

D8, D9, D10, D11 Rectifier power ground

C8, C9, C10, C11 Step-down converter power ground

G2, F3 Digital ground

B4, C4, B5, C5

A10

D7

Analog ground

Detection of the external power supply voltage – adapter/USB voltage. 30 V spike tolerant

External P-channel switch control for connecting adapter/USB voltage to VOUT

C2

C7

G4, F4

A1

Digital input for the USBOK signal from platforms

Step-down converter soft-start capacitor connection

Reserved. Connect to ground

Reserved. Connect to VCORE

8/56 DocID029451 Rev 2

STWLC03

Pin name

N/C

GND

N/C

GND

N/C

Pin position

G3

B1, E2, E6, F1

B2, B3, D3, E3

C1

A2, F5

Description

Reserved. Do not connect

Reserved. Connect to ground

Reserved. Do not connect

Reserved. Connect to ground

Reserved. Do not connect

Pin configuration

DocID029451 Rev 2 9/56

Maximum ratings

3 Maximum ratings

Pin

Table 3: Absolute maximum ratings

Parameter

AC1, AC2

MOD1, MOD2

CLMP1, CLMP2

BOOT1, BOOT2

BOOT

VRECT

VRESL, VSUPS

VRESL-VSUPS

VSUP

LX

RMOD, RMOD1

FBGND

VOUT

VFB

VEXT, SWDRW

NTCRX

VA, VCORE

V5V

VIO

SCL, SDA, USBOK,

INT, RESET

GPIO0, GPIO1,

GPIO2, GPIO3

T

STG

T

OP

T

J

ESD

Input AC voltage

Modulation transistor voltage

Clamp transistor voltage

Voltage on bootstraps

Value

-0.3 to 20

-0.3 to 20

-0.3 to 20

AC1, AC2 -0.3;

AC1, AC2 + 6

Voltage on bootstrap

Rectified voltage

Current sensing resistor connection voltage

Voltage on the current sensing resistor

VRECT-0.3;

VRECT + 6

-0.3 to 20

-0.3 to 20

-0.3 to 2

Input voltage of the buck converter

Buck converter switching node voltage

Resistive modulation current source and transistor voltage

Internal feedback transistor VDS voltage

Output voltage range

-0.3 to 20

-0.3 to 20

-0.3 to 20

-0.3 to 20

-0.3 to 20

-0.3 to 3 Buck converter feedback voltage

Detection pin for the external voltage and driver output for the external transistor

-0.3 to 30

RX coil NTC voltage

LDO1,2 voltages

LDO 3 voltage

VIO voltage

-0.3 to 2.3

-0.3 to 2.3

-0.3 to 6

-0.3 to 6

Digital interface voltage

General purpose I/O voltage

Storage temperature range

Operating ambient temperature range

Maximum junction temperature

Machine model

Charged device model

Human body model

-0.3 to VIO+0.3

-0.3 to VIO+0.3

-40 to 150

-40 to +85

+125

±100

±500

±2000

STWLC03

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

°C

°C

°C

Unit

V

V

V

V

10/56 DocID029451 Rev 2

STWLC03 Maximum ratings

Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

Package

Table 4: Thermal data

Symbol Parameter

Flip Chip 77 (3.12x4.73 mm) R

THJA

Junction-to-ambient thermal resistance (1)

Value Unit

35 °C/W

Notes:

(1)

This parameter corresponds to the PCB board, 4-layer with 1 inch

2

of cooling area.

DocID029451 Rev 2 11/56

Electrical characteristics

4 Electrical characteristics

STWLC03

-30 °C < T

A

< 85 °C; typical values are at T

A

= 25 °C, unless otherwise specified.

Symbol

Table 5: Electrical characteristics

Parameter Test conditions Min. Typ. Max. Unit

General section

V

IN

V

UVLO

AC input voltage

Undervoltage lockout threshold

Peak-to-peak voltage between

AC1- AC2 over the period

V

SUP

rising

V

SUP

falling 3.3

3.6

3.5

32

3.8

V

V

TIMEOUT

RESET

Reset time-out for shutdown mode

1 ms

IQ

Current consumption in the shutdown mode

RESET=0 (active low) duration>1 ms, measured at

VEXT

10 μA

I

RESET

I

CC

Current consumption in the RESET condition

Current consumption of the device

RESET=0 (active low) duration>1 ms, measured at

VRECT

RESET=0 (active low), duration<1 ms, GPIO 0 floating

RESET=1

(inactive), GPIO 0 floating

2

5

7

4 mA mA mA

LDO 1

V

A

LDO 1 output voltage

I

A

= 5 mA 1.8 V

I

ILIM

LDO 2

V

CORE

I

DDLIM

LDO 3

V

5V

Load current limit

LDO 2 output voltage

Load current limit

LDO 3 output voltage

I

ILIM

Load current limit

Synchronous rectifier

V

SUP

= 3.6 V to

11 V, I

CORE

= 5 mA

I

V5V

= 20 mA,

V

R

= 5.5 V

50

1.8

40

5

30 mA

V mA

V mA

12/56 DocID029451 Rev 2

STWLC03

R

Symbol

DS(on)

Parameter

Drain-source

NMOS on- resistance lowside

Drain-source

NMOS onresistance highside

I

Test conditions

RECT

V

= 1.4 A,

RECT

= 8 V

Efficiency Rectifier efficiency

I

RECT

= 0.8 A,

V

RECT

= 7 V, f

Rectifier

= 130 kHz

IRACTIVE

V

V

OVP

OVP hyst

Active mode rectifier threshold, voltage @ Rs

V

RECT

= 10 V, rising edge

V

RECT

= 10 V, falling edge f

RECTIFIER

V

CLAMP

Rectifier frequency range

Clamp of the rectified voltage

Active clamp drivers

R

DS(on)CLMP1,2

I

CLAMP

= 1 mA

Active clamp MOS

R

DS(on)

V

SUP

= 5 V

V

RECT

voltage threshold of active clamp

V

RECT

voltage active clamp hysteresis

Load modulation

R

DS(on)MOD1,2

I

MOD

I

MAXMOD1

Load modulation

MOS R

DS(on)

R

MOD

pin sink current range

Modulation current tolerance

V

SUP

= 5 V

V

SUP

= 5 V

V

SUP

= 5 to 12 V,

I

MOD

= 80 mA

V

SUP

= 5 V,

R

M

= 2 Ω

Protections

VLD

MAX.

TOL_VLD

MAX

Overcurrent protection threshold, voltage

@ R

S

VLD

MAX

= 04h

Tolerance of the

VLD

MAX

VLD

MAX

= 04h

VLD

MAX

= 0Fh

VLD

MAX

= 0Fh

Min.

Electrical characteristics

Typ. Max. Unit

50

15.4

15

-5

-10

90

70

91

8.75

3.25

17.4

1

15.9

600

1

10

2

1.7

0.875

500

16.4

410

+5

+10 mΩ

% mV kHz

V

Ω

V mV

Ω mA

%

A

V

%

DocID029451 Rev 2 13/56

Electrical characteristics

Symbol Parameter Test conditions

V

NTCTRIG

TOL_V

NTCTRIG

NTC trigger voltage for RX

NTC trigger voltage tolerance

Hyst_V

NTCTRIG t

SHDN t

SHDNHYST

NTC trigger voltage hysteresis

Thermal shutdown

Thermal shutdown hysteresis

Current-to-voltage converter

EOC_CURRENT

TOL

EOC_CURRENT

End-of-charge current threshold

Tolerance of the

EOC threshold

R

S

= 0.05 Ω 1%,

V

SUP

= 5 to 15 V

R

S

= 0.05 Ω 1%,

V

SUP

= 5 to 15 V,

EOC_CURRENT

= 50 mA

R

S

= 0.05 Ω 1%,

V

SUP

= 5 to 15 V,

EOC_CURRENT

= 200 mA

Step-down converter

V

VOUT

Output voltage range

Tol

VOUT

VOUT tolerance

VOUTreg = 011,

VOUT = 4.2 V

OVP

VOUT

I

VOUT

+ I

FB

I

FB

I

LIM

I

OVERCURR

DIV

VOUT f

SW

V

SUP

Overvoltage protection threshold

Output leakage current

Feedback pin bias current

Coil current limit

Coil current limit accuracy

Overcurrent/shortcircuit protection

Output voltage internal divider ratio

Switching frequency

Input voltage range

Step-down is off,

VOUT = 5 V,

CURRLIM reg =

1111

V

SUP

= 5 to 12 V

I

OUT

= 2 A

3

Min.

0

250

5.5

Typ.

0.6

3

100

150

20

STWLC03

Max. Unit

V

% mV

°C

°C

400 mA

20

10

0.5

7

8.5

1

10

4500

500

4000

6

0.8

12

%

%

V

%

V

µA nA mA

% mA nA

MHz

V

14/56 DocID029451 Rev 2

STWLC03

Symbol

N-R

DS(on)SW

Parameter

NMOS R

DS(on) high-side

Test conditions

Back-to-back connected transistors

N-R

DS(on)SW

NMOS R

DS(on)

lowside

POUT = 5 W

Efficiency

Step-down efficiency

POUT = 12 W

R

FBGND

VOUT feedback divider grounding switch resistance

I

FBGND

= 500 µA t

START

Buck converter soft-start time

C

10

= 1 µF,

P

LOAD

= 0 to 12 W

Input voltage loop for output power limiting

VRMIN = 00h

VRMIN

Minimum rectified voltage threshold for output power limitation

TOL

VRMIN

VRMIN threshold tolerance

Input current limitation loop

IRREG

Input current limitation threshold, voltage @ R s

VRMIN = 0Ah

IRREG = F6h

IRREG = 32h

TOL

IRREG

IRREG threshold tolerance

IRREG = F6h

IRREG = 32h

External voltage switch driver

V

V

EXTUVLO

EXTOVP

External supply undervoltage threshold

External supply overvoltage threshold

I

EXTCONS

V

SWDRV

Input consumption current

Switch driver voltage drop

VEXT = 5 V,

VRECT = 0 V,

RESET = 1 (active low)

VEXT = 5 V,

SWDRV low

GPIO pins

Min.

Electrical characteristics

Typ. Max. Unit

4.2

5.25

130

60

89

80

1

5

7

5

82.5

17.55

8

5

10

4.4

5.55

200

40

4.6

5.9 mΩ mΩ

%

Ω s

V

% mV

%

V

V mA mV

IOUT

GPIO0/1/2

GPIO pin current capability

GPIO0/1/2 high,

V

IO

= 1.8 V,

V

GPIO0/1/2

= 1.4 V

3 mA

DocID029451 Rev 2 15/56

Electrical characteristics

Symbol

V

GPIO0/1/2/3

Parameter

GPIO pin drop

Test conditions

GPIO0/1/2/3 low,

V

IO

= 1.8 V,

I

GPIO0/1/2

= 3 mA

Min.

V

IL

Low level input voltage

High level input voltage

V

IH

Microcontroller

Architecture

NVM

Clock generator

Memory size for customization f

OSC

TOL

FOSC

Clock generator frequency

Tolerance of the clock generator frequency

V

SUP

= 4.5 to 15 V

T

AMB

= 0 °C to 85 °C

0.7*VIO

-4

Typ.

STWLC03

Max. Unit

360

32

2

16

0.3*VIO V

+4 mV

V bit kbit

MHz

%

16/56 DocID029451 Rev 2

STWLC03

5

5.1

Device description

Device description

Using the STWLC03 as a power supply

The STWLC03 is configured as a power supply with 5 V output voltage by default. Output voltage can be adjusted in 8 steps in runtime through I 2 C or as a new default start-up configuration in NVM. Output voltage can be also slightly fixed in the range among the software steps, by tuning the resistor feedback divider.

When the output voltage changes, the related parameters have to be taken into account: rectified voltage V

RECT

and input voltage threshold for output limitation V

RMIN

. The table below shows the recommended values.

Table 6: Recommended VRECT and VRMIN values for various VOUT

Parameter Min. Typ. Max.

VOUT

VRECT

VRMIN

5 V

7 V

5.6 V

6 V

8 V

5.6 V

7 V

9 V

5.6 V

Input current limit and overload threshold should be fixed according to maximum expected peak load in the application.

The STWLC03 monitors continuously the rectifier current. If the current drops below the defined threshold for the defined time, the power transfer is over. This configuration is stored in NVM, values Qi_EPT_Threshold, Qi_EPT_Time, PMA_EOC_Threshold,

PMA_EOC_Time. This configuration is common for power supply mode and battery charger mode. To avoid power transfer termination, zero-current and maximum time have to be fixed.

Figure 3: Typical step-down converter efficiency

5.2 Using the STWLC03 as a battery charger

The STWLC03 is equipped with a software feature allowing the input current limitation loop to control the charging current. In this manner the STWLC03 can operate as a CC/CV

DocID029451 Rev 2 17/56

Device description STWLC03 charger without HW output current control loop. VOUT pin leakage is minimized to save battery operation time.

The STWLC03 can be switched to battery charger mode instantly by I 2 C register

(evaluation only, not recommended for production) or as a new default start-up configuration in NVM (safe recommended solution).

Figure 4: Typical charging profile

5.3

Thanks to very low leakage from VOUT pin, the STWLC03 can remain connected to the battery and does not cause any discharge.

Wireless standard auto-detection

The STWLC03 automatically detects the operating standard when it is placed on a wireless transmitter. Detection is based on combination of operating frequency and receiving FSK signaling from the transmitter.

18/56 DocID029451 Rev 2

STWLC03

Figure 5: Wireless standard detection flowchart

Device description

5.4

The STWLC03 can be also configured to skip the auto-detection and use directly the preconfigured wireless standard.

Qi operation and flow chart

The STWLC03 follows Qi 1.1.2 version.

When Qi state machine starts, it proceeds through ping and identification and configuration phases to power transfer phase according to Qi wireless power transfer, volume I: low power 1.1.2 specification.

DocID029451 Rev 2 19/56

Device description

Figure 6: Qi simplified flow diagram

STWLC03

20/56

End-power-transfer can be requested because of the following reasons:

Table 7: EPT reasons in Qi

Reason EPT code

I 2 C “Force EPT” bit set

Unknown (00h) VEXT above UVLO

USBOK digital input

Termination current reached Charge complete (01h)

Charger in unexpected state

Step-down overload

Step-down output overvoltage

Rx coil NTC above threshold

Chip temperature above threshold

Rectifier output overvoltage

Rectifier output overcurrent

Charger output voltage above threshold

I 2 C “Reconfigure” bit set

Internal fault (02h)

Overtemperature (03h)

Overvoltage (04h)

Overcurrent (05h)

Battery failure (06h)

Reconfigure (07h)

DocID029451 Rev 2

STWLC03

5.4.1 Received power calibration (FOD feature)

Device description

Although the STWLC03 is well-trimmed, inaccuracy in the received power estimation can be caused in the target application due to manufacturing different environment conditions.

Different serial resistances of used receiver coil or different shieldings of the receiver coil

(e.g. battery or ground plane in a near proximity of the coil) are the main issues. The

STWLC03 features dedicated adjustment options placed in NVM.

5.5 PMA operation

The STWLC03 follows PMA1 SR1 specification. When PMA state machine starts, it proceeds through ping and identification phase to power transfer phase according to PMA inductive wireless power and charging receiver specifications, system release 1.

Figure 7: PMA simplified flow diagram

End-of-charge can be requested due to the following reasons:

DocID029451 Rev 2 21/56

Device description

5.6

STWLC03

Table 8: EOC reasons in PMA

Reasons

I 2 C “Force EOC” bit set

VEXT above UVLO

USBOK digital input

Termination current reached

Charger in unexpected state

Step-down overload

Step-down output overvoltage

Rx coil NTC above threshold

Chip temperature above threshold

Rectifier output overvoltage

Rectifier output overcurrent

Charger output voltage above threshold

External power supply

Figure 8: "External power supply situation" illustrates the situation where the STWLC03

detects the external voltage presence and drives SWDRV (external voltage) to the output.

The STWLC03 also terminates the wireless power transfer.

Figure 9: "External power supply situation 1" illustrates the situation where the STWLC03 is

assembled in a system with another PMIC that serves multiple power supply inputs. PMIC uses digital line to let the STWLC03 know that there is a higher priority power supply available and the wireless power transfer should be terminated.

For proper operation, RESETn pin must be high. Connecting VEXT power supply, consumption from VIO increases if VIO supply is provided externally. (It has not effect if VIO is connected to VCORE).

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STWLC03

Figure 8: External power supply situation

Device description

Figure 9: External power supply situation 1

DocID029451 Rev 2 23/56

Device description

5.7 The device interface

STWLC03

The STWLC03 is equipped with I 2 C interface with an open-drain interrupt line to connect with the host system. If I 2 C connection is not used by the host platform, SDA and SCL lines should be pulled-up to VIO voltage. The STWLC03 contains RESETn input. The device under reset conditions has very low power consumption. If reset is not controlled by the host platform it should be pulled-up to VIO voltage. USBOK is a digital input, which terminates power transfer if another preferred power supply is available. The STWLC03 features GPIO pins. By default GPIO 0 only is active and detects power transfer state on wireless interface.

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STWLC03

6

I2C register description

I

2

C register description

The device I 2 C address is 14h (0010100b).

Address

Table 9: User register map

Register

00h

01h

02h

03h

Control

Reserved

Target rectified voltage

Input voltage threshold for output limitation

Reserved 04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

Input current limit

Overload threshold

Buck output voltage

Buck current limit

Chip overtemperature

Interrupt mask L

Interrupt mask H

Interrupt status L

0Eh

0Fh

10h

11h

12h

13h

Interrupt status H

Interrupt latch L

Interrupt latch H

Operation mode detection status

Operation mode detection control

Qi charge status packet content

Charger status

14h Charger control

Table 10: Control register b7 b6 b5 b4 b3 b2 b1

Force/EPT Disable/EPT on error Qi reconfigure - - - b0

- USBcon_cnf R/W

Loaded from NVM at startup Default

USBcon_cnf:

0: auto connect switch + disable buck + send EPT@VEXT/disable buck + send

EPT@USBOK

1: ignore VEXT/USBOK completely

Qi reconfigure:

0: no action

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I2C register description

1: send reconfigure packet (auto-clear)

Disable EPT on error:

0: automatically send EPT to OVP, overload, overtemperature or buck fault

1: do not send EPT automatically, wait for master

Force EPT:

STWLC03

0: no action

1: send EPT (auto-clear) b7 b6

Table 11: Target rectified voltage register (register address 02h) b5 b4 b3 b2 b1 b0

TARGET_VRECT[7:0]

Loaded from NVM at startup

R/W

Default

The target rectifier output voltage.

Rectified voltage = 0.25 V * TARGET_VRECT

Valid range 14h - 30h (5 V - 12 V).

Table 12: Input voltage threshold for output power limitation register (register address 03h)

b7 b6 b5 b4 b3 b2 b1 b0

- - VRMIN[5:0] R/W

Loaded from NVM at startup Default

VRMIN represents a VRECT voltage threshold where step-down converter applies output power limitation to prevent VRECT from dropping too low.

Threshold = 5.0 V + VRMIN * 0.2 V

Valid range from 00h to 0Ah (5.0 V – 7 V). Recommended value is 01h (5.2 V). b7 b6

Table 13: Input current limit register (register address 05h) b5 b4 b3 b2 b1 b0

INPUT_CURR_LIMIT[7:0]

Loaded from NVM at startup

R/W

Default

Output power does not exceed this input current limit. The current is sensed on the sensing resistor (R

S

).

Input current limit = (1.625 mV + INPUT_CURR_LIMIT * 0.325 mV) / R

S

.

Valid range from 00h to F6h (0.001625 V – 0.0816 V ~ 16.25 mA – 816 mA @ 100 mΩ R

S

). b7 b6

Table 14: Overload threshold register (register address 06h) b5 b4 b3 b2 b1 b0

- - - - OVERLOAD_THRD[3:0]

Loaded from NVM at startup

R/W

Default

This register configures overcurrent protection threshold, sensed on the sensing resistor

(R

S

). Voltage represents the voltage drop caused by current flowing through the sensing

26/56 DocID029451 Rev 2

STWLC03 I2C register description resistor. Overcurrent protection threshold = (6.25 mV + OVERLOAD_THRD * 6.25 mV) /

R

S

.

Valid range 00h – 0Fh (6.25 mV – 100 mV ~ 0.0625 A – 1 A @ 100 mΩ R

S

.

Table 15: Step-down output voltage register (register address 07h) b7 b6 b5 b4 b3 b2 b1 b0

- - - - - STEP_DOWN_OUTPUT_VOLT[2:0]

Loaded from NVM at startup

R/W

Default

This register sets step-down converter feedback reference voltage. Output voltage is derived from the feedback voltage through the feedback resistor divider.

Table below shows values of the reference voltage of the step-down converter for each setting and the VOUT voltage assuming the typical recommended feedback resistor divider.

Table 16: Step-down converter feedback voltages

BUCK_OUTPUT_VOLT STEP_DOWN FB REF [V] VOUT [V]

000

001

010

011

100

0.57

0.62

0.70

0.72

0.86

b7 b6 b5

Table 17: Buck current limit register

b4 b3 b2 b1 b0

- - - - BUCK_ILIM[3:0]

Loaded from NVM at startup

This register sets the peak coil current limit value of the buck converter.

3.30

3.60

4.10

4.20

5.00

R/W

Default

Peak current = 250 mA + BUCK_ILIM * 250 mA.

Valid range from 00h to 04h (250 mA – 1250 mA). b7

Table 18: Chip overtemperature threshold register (register address 09h) b6 b5 b4 b3 b2 b1 b0

CHIP_OVERTEMP_THRESHOLD[7:0] R/W

Loaded from NVM at startup Default

This threshold is compared to the value read by the AD converter from the chip temperature channel divided by 4. b7 b6

Table 19: Interrupt mask L register (register address 0Ah) b5 b4 b3 b2 b1 b0

INT_MASK_L

Loaded from NVM at startup

Interrupt mask register ( INT output only is masked, no effect on EPT):

R/W

Default

DocID029451 Rev 2 27/56

I2C register description b0: buck fault b1: overload b2: chip overtemperature b3: coil overtemperature b4: VRECT overvoltage b5: VEXT (external voltage connection) b6: USB OK (USB connection) b7: standard detection finished

0 = interrupt not masked

1 = interrupt masked

b7 b6

Table 20: Interrupt mask H register ( register address 0Bh)

b5 b4 b3 b2 b1 b0

INT_MASK_H

Loaded from NVM at startup

Interrupt mask register (INT output only is masked, no effect on EPT): b0: charging finished b1: charger internal fault b2: charger battery fail b3: not used b4: not used b5: not used b6: not used b7: not used

0 = interrupt not masked

1 = interrupt masked b7 b6

0

Table 21: Interrupt status L register ( register address 0Ch) b5 b4 b3 b2 b1 b0

INT_STATUS_L

0 0 0 0 0 0 0 b0: N/A b1: N/A b2: chip overtemperature b3: coil overtemperature b4: N/A b5: VEXT (external voltage connection) b6: USB OK (USB connection)

STWLC03

R/W

Default

Read only

Default

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STWLC03 b7: standard detection finished

Bit value 1 means valid, 0 means not valid. b7 b6 b5

Table 22: Interrupt status H register b4 b3 b2 b1 b0

INT_STATUS_H

0 0 0 0 0

I2C register description

Read only

Default 1 0 b0: charging finished

0 b1: charger internal fault b2: charger battery fail b3: N/A b4: N/A b5: N/A b6: N/A b7: N/A

Bit value 1 means valid, 0 means not valid. b7 b6 b5

Table 23: Interrupt latch L register b4 b3 b2 b1 b0

0

INT_LATCH_L

0 0 0 0 0 0 0 b0: buck fault b1: overload

Read/clear

Default b2: chip overtemperature b3: coil overtemperature b4: VRECT overvoltage b5: VEXT (external voltage connection) b6: USB OK (USB connection) b7: standard detection finished

Bit value 1 means valid, 0 means not valid. b7 b6 b5

Table 24: Interrupt latch H register b4 b3 b2 b1 b0

INT_LATCH_H

0 0 0 0 0

Read/clear

Default 0 0 0 b0: charging finished b1: charger internal fault b2: charger battery fail

DocID029451 Rev 2 29/56

I2C register description b3: N/A b4: N/A b5: N/A b6: N/A b7: power ON in I 2 C driven standard detection mode

Bit value 1 means valid, 0 means not valid. b7

Table 25: Operation mode detection status register b6 b5 b4 b3 b2 b1 b0

Wireless powered

0

Wireless powered:

0 0

Forced

0 0

OP_STANDARD

0 0 0

0: no wireless supply (i.e. USB supply)

1: the device is engaged with a wireless pad

FORCED:

0: standard is based on auto-detection

1: standard is forced by NVM configuration

OP_STANDARD:

0: unknown

1: PMA1

2: PMA4 (low frequency + advertising)

3: Qi 1.0 / Qi 1.1

4: reserved

STWLC03

Read only

Default

FORCED flag set + unknown standard means that standard has been detected but it is forbidden by detection configuration b7

Table 26: Operation mode detection control register (register address 11h) b6 b5 b4 b3 b2 b1 b0

- - - OP_STANDARD R/W -

0 0

OP_STANDARD:

0 0 0 0 0 0 Default

1: PMA1

2: PMA4 (low frequency + advertising)

3: Qi 1.0 / Qi 1.1

4: reserved

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STWLC03 I2C register description

This register is functional only in combination with “I 2 C master driven” detection configuration b7 b6

Table 27: Qi charge status register (register address 12h) b5 b4 b3 b2 b1 b0

1 1 1

Qi_CHARGE_PACKET

1 1 1 1 1

R/W

Default

Available in Qi mode only. It contains a value that is sent to the Qi charge status packet.

Values in the range from 0 to 100 provide percentage of the battery capacity. If there is no need to use the charge status packets, this register should be set to FFh. b7 b6

Table 28: Charger status register (register address 13h) b5 b4 b3 b2 b1 b0 x x x

CHARGER_STATUS x x x x x

R/W

Default

CHARGER_STATUS:

0: off

1: pre-charge

2: fast charge

3: termination counter running

4: battery OVP b7 b6 b5

Table 29: Charger control register b4 b3 b2 b1

CHARGER_CONTROL:

CHARGER_CONTROL

Loaded from NVM at startup

0: disabled

1: enabled b0

R/W

Default

6.1 ADC measured values

Address

Table 30: ADC measured value register map

Register

20-21h

22-23h

24-25h

26-27h

28-29h

2A-2Bh

Rectified voltage

Rectifier output current

Rx coil NTC voltage

Output voltage

Rectifier internal drop voltage

Chip temperature

DocID029451 Rev 2 31/56

I2C register description

Address

2C-2Dh

2E-2Fh

Register

ADC calibration channel

Received power (Qi only)

Address 20h

Table 31: Rectified voltage (VRECT)

Address 21h

STWLC03 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

- - - - - -

Rectified voltage VRECT is sensed on VRECT pin.

VRECT_MEAS[9:0]

V

RECT

= VRECT_MEAS * VRECT_Div * 1.46 mV.

Nominal VRECT_Div value is 11 but the real value is trimmed for each device to match internal analog parameters.

Table 32: Rectified output current (IRECT)

Address 22h Address 23h b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

- - - - - - LOAD_CURR_MEAS[9:0]

Load current I

LD

is measured as a voltage drop V

LD

on the current sensing resistor (R

S

).

V

LD

= (LOAD_CURR_MEAS – VLD_offset) / VLD_Gain * 1.46 mV.

Nominal VLD_Gain value is 12 but the real value is trimmed for each device to match internal analog parameters.

Nominal VLD_Offset value is 341 but the real value is trimmed for each device to match internal analog parameters.

I

LD

= V

LD

/R

S

Table 33: RX coil NTC voltage

Address 24h Address 25h b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

- - - - - -

NTC voltage V

NTC

is sensed on NTCRX pin.

V

NTC

= RX_NTC_MEAS * 1.46 mV.

RX_NTC__MEAS[9:0]

Voltage to temperature conversion depends on the used NTC and the R

1

divider.

Table 34: VOUT voltage

Address 26h Address 27h b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

- - - - - -

Output voltage VOUT is sensed on VOUT pin

VOUT__MEAS[9:0]

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STWLC03

VOUT = VOUT_MEAS * VOUT_Div * 1.46 mV

I2C register description

Nominal VOUT_Div value is 6 but the real value is trimmed for each device to match internal analog parameters.

Table 35: VDROP voltage

Address 28h Address 29h

- b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

- - - - - VDROP__MEAS[9:0]

Rectifier drop voltage V

DROP

is sensed internally on rectifier power stages.

V

DROP

= (VDROP_MEAS – VDROP_Offset) / VDROP_Gain * 1.46 mV.

Nominal VDROP_Gain value is 6 but the real value is trimmed for each device to match internal analog parameters.

Nominal VDROP_Offset value is 136 but the real value is trimmed for each device to match internal analog parameters.

Table 36: Chip temperature

Address 28h Address 29h b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

- - - - - - CHIP_TEMP_MEAS[9:0]

Chip temperature T

J

measured internally.

T

J

= CHIP_TEMP_MEAS * (-0.57) + 430

Table 37: Ground voltage

Address 2Ch Address 2Dh b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

- - - - - - GND_MEAS[9:0]

Ground voltage V

G

is sensed directly on internal ground node.

V

G

= GND_MEAS * 1.46 mV.

Table 38: RX_POWER

Address 2Eh Address 2Fh b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

RX_POWER[15:8] RX_POWER[7:0]

This value is valid in Qi mode only. It contains the last calculated received power.

RX_POWER[15:8] corresponds to the data sent, the 8-bit received, power packet sent during communication with Qi transmitter. RX_POWER[7:0] is a fraction of 256.

6.2 Service registers

These registers allow access the NVM and the firmware version number. Registers in address range 50h-5Fh are used as data buffer for operations with non-volatile memory

(NVM). Register at address 4Fh serves as a command register.

DocID029451 Rev 2 33/56

I2C register description

Address

40h

4Fh

50-5Fh

Table 39: Service register map

Register

Firmware version

NVM control

Data manipulation registers b7

NVM_WR

0 b6

NVM_RD

0

Table 40: NVM control b5 b4 b3

0 0 0 b2 b1

NVM_SECT[3:0]

0 0 0 b0

NVM_WR bit:

0: no action

1: write data into NVM sector (auto-clear)

NVM_RD bit:

STWLC03

R/W

Default

0: no action

1: read data from NVM sector (auto-clear)

NVM_SECT contains the address of the sector in the NVM, which should be used for reading or writing operations.

Data to write must be prepared in data manipulation registers before starting writing operation into the control register.

Byte 00 of the NVM sector is located in data manipulation register address 50h, byte 01 in register 51h etc. according to the following table:

Table 41: I2C registers corresponding to bytes in NVM sector

Data manipulation register

50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F

NVM byte 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

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STWLC03

7

7.1

Non-volatile memory

Non-volatile memory

Non-volatile memory (NVM) contains 2048 bits organized into 16 sectors. The first 15 sectors are available for the firmware. I 2 C access is through service registers.

NVM sector maps

Sector

Table 42: Non-volatile memory sector map

Content

00

01

Trimming and configuration data

Trimming and configuration data

Trimming and configuration data 02

03

04

05

06

07

08

Trimming and configuration data

Platform HW parameters (Resr, Rs, FOD offset)

Default values for user registers in Qi mode

Reserved for future use

Qi identification and configuration packet content (ID, vendor, power class)

09

0A

0B

0C

Reserved for future use

Reserved for future use

Reserved for future use

Reserved for future use

Reserved for future use

0D Termination current, charging parameters

0E Reserved for future use

Sector 00, 01, 02, 03

These sectors contain trimming and configuration data. Any modification could degrade the performance of the device.

Sector 04

This sector contains hardware parameters.

Byte

Table 43: Map of NVM sector 04

Parameter STWLC03 default value

00

01

02

03

04

05

Resr

RxPower offset

R

S

00h

01h

DCh

05h

33h

Not used

DocID029451 Rev 2 35/56

Non-volatile memory

Byte

06

Parameter STWLC03 default value

STWLC03

11

12

13

14

07

08

09

10

15 b7 b6 b5

Table 44: Byte 0

Byte 0 b4 b3

Resr [7:0] (LSB) b2 b1 b0 b7 b6 b5

Table 45: Byte 1

Byte 1 b7 b6 b5 b4 b3

Resr [15:8] (MSB) b2 b1 b0

Rx coil resistance. Resr is a 16 bit unsigned valued in Ohm multiplied by 1024. This value is used when power losses are estimated during RxPower calculation in Qi mode.

Table 46: Byte 2

Byte 2 b4 b3

RxPower offset [7:0] (LSB) b2 b1 b0

Table 47: Byte 3

Byte 3 b7 b6 b5 b4 b3

RxPower offset [15:8] (MSB) b2 b1 b0

RxPower offset is a 16-bit signed value that is added to the RxPower calculated in Qi mode. It tunes the accuracy and compensates potential additional losses in the magnetic field caused by a presence of other objects such as the PCB or battery.

36/56 DocID029451 Rev 2

STWLC03 Non-volatile memory b4

Table 48: Byte 4

Byte 4 b3 b7 b6 b5 b2 b1 b0

Rs[7:0]

This parameter represents the value of the current sensing resistor R

S

in Ohm multiplied by

1024. This value is necessary for RxPower calculation in Qi mode.

Sector 05

This sector contains default register values for Qi mode that are loaded into internal I 2 C registers after the startup of the microcontroller.

Byte

Table 49: Map of NVM sector 05

Target I 2 C register STWLC03 default value

08

09

10

11

12

04

05

06

07

00

01

02

03

13

14

15

Sector 06

This sector is reserved for future use.

Sector 07

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

01h

0Fh

18h

00h

01h

4Eh

05h

04h

04h

80h

00h

00h

Not used

This sector contains data used in identification and configuration packets in Qi mode.

37/56 DocID029451 Rev 2

Non-volatile memory

Byte

00

STWLC03

Table 50: Map of NVM sector 07

Parameter STWLC03 default value

Manufacturer code MSB 00h

01

02

03

04

05

06

07

08

09

10

11

Manufacturer code LSB

Basic device identifier MSB

Basic device identifier

Basic device identifier

Basic device identifier LSB

Extended device identifier MSB

Extended device identifier

Extended device identifier

Extended device identifier

Extended device identifier

Extended device identifier

16h

01h

02h

03h

04h

11h

12h

13h

14h

15h

16h

12

13

14

Extended device identifier

Extended device identifier LSB

Maximum power

17h

18h

0Ah

15 Unused 00h

Sector 08

This sector contains default register values for PMA mode that are loaded into internal I 2 C registers after start-up of the microcontroller.

38/56 DocID029451 Rev 2

STWLC03

05

06

07

08

09

10

11

Byte

00

01

02

03

04

Non-volatile memory

Table 51: Map of NVM sector 08

Target I 2 C register STWLC03 default value

00h 01h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

12

13

14

15

Sector 09

This sector is reserved for future use.

Sector 10

This sector contains PMA RXID and its CRC.

0Dh

7Ah

00h

00h

Not used

Not used

Not used

Not used

19h

1Dh

01h

0Ah

C3h

09h

04h

DocID029451 Rev 2 39/56

Non-volatile memory

05

06

07

08

09

10

11

Byte

00

01

02

03

04

Table 52: Map of NVM sector 10

Parameter

Preamble

Message ID

Certification version

RXID LSB

RXID

RXID

RXID

RXID

RXID MSB

CRC LSB

CRC MSB

Not used

12

13

14

Not used

Not used

Not used

15

Sector 11, 12

Not used

These sectors are reserved for future use.

Sector 13

Charging parameters are stored in this sector.

STWLC03

Default value

00h

AAh

10h

00h

00h

00h

25h

50h

02h

63h

25h

00h

00h

00h

00h

00h

40/56 DocID029451 Rev 2

STWLC03 Non-volatile memory

Byte

08

09

10

11

12

13

14

15

00

01

02

03

04

05

06

07

Table 53: Map of NVM sector 13

STWLC03 default value

26h

24h

03h

4Ch

CCh

Not used

Not used

Not used

4Dh

24h

03h

4Ch

CCh

Not used

Not used

Not used

Table 54: Byte 0 Qi_EPT_threshold [7:0]

Byte 0 b7 b6 b5 b4 b3

Qi_EPT_threshold [7:0] b2 b1 b0

It sets the threshold for charging termination. Current has not be sensed on the output but on R

S

sensing resistor.

Qi_EPT_threshold is directly compared with (LOAD_CURR_MEAS/2).

This parameter is active both in fixed output voltage mode and in charger mode.

Table 55: Byte 1, Qi_EPT_Time [7:0]

Byte 1 b7 b6 b5 b4 b3

Qi_EPT_Time [7:0] b2 b1 b0

Qi_EPT_Time is end-of-power transfer deglitch time in minutes. If the charging current is permanently lower than Qi_EPT_threshold for more than Qi_EPT_Time, the end-of-power transfer packet is sent to the transmitter.

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Non-volatile memory STWLC03

This parameter is active both in fixed output voltage mode and in charger mode. b7

Qi charger enable

Qi charger enable bit:

Table 56: Byte 2, Qi charger enable

Byte 2

- b6

- b5

- b4

0: charging algorithm is not active after startup

- b3 b2 b1

Qi target voltage [2:0] b0

1: charging algorithm is active after startup

Qi target voltage

Table 57: Qi target voltage

Charging voltage [V]

0

1

2

3

4

3.3

3.6

4.1

4.2

5.0

Table 58: Byte 3, Q1_Precharge_Battery_overvoltage

Byte 3 b7 b6

Qi_Precharge_voltage [1:0]

Qi_Precharge_voltage: b5 b4 b3 b2 b1

Qi_Battery_overvoltage [5:0]

00b: 2.5 V

01b: 2.7 V

10b: 2.9 V

11b: 3.1 V

Battery OVP threshold = (3.3 V + Qi_Battery_overvoltage * 100 mV) / 1024 * 1000

Table 59: Byte 4, Q1_Precharge and Fastcharge

Byte 4 b0 b7 b6

Qi_Precharge_current [1:0]

Qi_Precharge_current

00b: 2.5 mV / R

S

(50 mA @ 50 m Ω R

S

)

01b: 5 mV / R

S

(100 mA @ 50 m Ω R

S

)

10b: 7.5 mV / R

S

(150 mA @ 50 m Ω R

S

) b5 b4 b3 b2 b1

Qi_Fastcharge_current [5:0] b0

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STWLC03

11b: 10 mV / R

S

(200 mA @ 50 m Ω R

S

)

Non-volatile

Qi Fastcharge current = (Qi_Fastcharge_current * 2.5 mV + 5 mV) / R

S

Table 60: Byte 8, PMA_EOC_theshold [7:0]

Byte 8

memory b7 b6 b5 b4 b3

PMA_EOC_theshold [7:0] b2 b1 b0

It sets the threshold for charging termination. Current has not be sensed on the output but on R

S

sensing resistor.

PMA_EOC_threshold is directly compared with (LOAD_CURR_MEAS / 2).

This parameter is active both in fixed output voltage mode and in charger mode.

Table 61: Byte 9, PMA_EOC_Time [7:0]

Byte 9 b7 b6 b5 b4 b3 b2 b1 b0

PMA_EOC_Time [7:0]

PMA_EOC_Time is end-of-power transfer deglitch time in minutes. If the charging current is permanently lower than PMA_EOC_theshold for more PMA_EOC_Time, the end-ofcharging signal is sent to the transmitter.

This parameter is active both in fixed output voltage mode and in charger mode. b7

Table 62: Byte 10, PMA_Target_Voltage [2:0]

Byte 10 b6 b5 b4 b3

- b2 b1 b0

PMA_ Target_Voltage [2:0] PMA charger enable

PMA charger enable bit:

- - -

0: charging algorithm is not active after startup

1: charging algorithm is active after startup

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Non-volatile memory STWLC03

Table 63: PMA target voltage vs charging voltage

PMA target voltage Charging voltage

0 3.3

3

4

1

2

3.6

4.1

4.2

5.0

5

6

7

5.5

6.0

7.0 b7 b6

PMA_Precharge_ voltage[1:0]

PMA_Precharge_voltage:

00b: 2.5 V

01b: 2.7 V

Table 64: Byte 11

Byte 11 b5 b4 b3 b2

- - - b1 b0

PMA_ Battery_overvoltage [5:0]

10b: 2.9 V

11b: 3.1 V

Bat OVP threshold = (3.3 V + PMA_Battery_overvoltage * 100 mV) / 1024 * 1000

Table 65: Byte 12

Byte 12 b7 b6 b5 b4 b3 b2 b1

PMA_Precharge_ current[1:0]

PMA_Precharge_current:

00b: 2.5 mV / R

S

(50 mA @ 50 m Ω R

S

)

01b: 5 mV / R

S

(100 mA @ 50 m Ω R

S

)

10b: 7.5 mV / R

S

(150 mA @ 50 m Ω R

S

)

11b: 10 mV / R

S

(200 mA @ 50 m Ω R

S

)

PMA_ Fastcharge_current [5:0]

PMA Fastcharge current = PMA_Fastcharge_current * 2.5 mV + 5 mV

Sector 14

This sector is reserved for future use. b0

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STWLC03

8

8.1

Application information

Application information

Application schematic and recommended external components

Figure 10: STWLC03 application schematic

RM is an optional component and it is not needed for a typical application. If

VEXT detection is disabled, C8 and TRSWDRV are optional.

DocID029451 Rev 2 45/56

Application information

Figure 11: STWLC03 charger configuration

STWLC03

46/56

Component

L1

Table 66: STWLC03 recommended external components

Manufacturer Part Number Value

Wurth

TDK

760308103215

760308103202

14.3 uH

12 μH

TOKO DFE252012F-1R5

1.5 μH/3.8 A

L2

C1

C2

C3

C4

CBOOT1,

CBOOT2,

CBOOT

C5

Before connecting the battery, the STWLC03 has to be configured as a battery charger in NVM.

CYNTEC

TDK

MURATA

MURATA

MURATA

TDK

MURATA

MURATA

MURATA

PILE25201D-2R2MS-11 2.2 μH/3.1 A

PIME041B-2R2MS-11

SPM3010T-1R0

TFM1R0GHM

2.2 μH/4.3 A

1 μH/4.5 A

1 μH

3x GRM188R72A104KA35 100 nF/X7R

GRM155R71H332KA01 3.3 nF/C0G

2x GRM188R61C106KAAL

10 μF/16 V

2x C1608X5R1C106M

GRM188R61C106KAAL

10 μF/16 V

10 μF/16 V

GRM155R61H473KE14 47 nF/50 V

2x GRM188R61C106KAAL 10 µF/16 V

Size

48x32x1 mm

48x32x1 mm

2.5x2.0x1.2 mm

2.5x2.0x1.4 mm

4.4x4.2x1 mm

3x3.2x1mm

2x1.6x1 mm

0603

0603

0603

0603

0603

0402

0603

DocID029451 Rev 2

STWLC03

Component

C6, C7

CM1

CM2

RCL1, RCL2

RM (optional)

CFB

RS

R1

Manufacturer

MURATA

MURATA

MURATA

PANASONIC

MURATA

PANASONIC

RFB1

TE-

CONNECTIVITY

PANASONIC RFB2

RNTC MURATA

CCHG (filter) MURATA

DCHG (filter)

C8

STMICROELECT

RONICS

MURATA

TR

SWDRW

C10

C11

FAIRCHILD

TDK

TDK

Part Number

GRM155R61A105KE15

GRM155R71H563KE14

GRM155R71H393KE14

ERJ-PA2J150V

GRM1555C1H150GA01

ERJ-L03KF50MV

STPS3L45AF

Application information

Value

1 µF/10 V 0402

Size

56 nF/50 V

39 nF/50 V

15R

12 Ω

15 pF

0.05 Ω/1%

51 kΩ

0402

0402

0603

0603

0402

0603

0402

CPF0402B160KE 160 kΩ

ERA-2AEB3322X 33.2 kΩ

100 kΩ

4x GRM188R61C106KAAL

10 μF/16 V

3 A/45 V

0402

0402

0402

0603

SMA flat

GRM155R61E225KE11

FDMA1027P

2.2 µF/25 V 0402

20 V/3 A dual

P-channel FET

2x2x0.8 mm

GRM155R6YA474KE01 470 nF/35 V

GRM155R61H104KE19D 100 nF/50 V

0402

0402

DocID029451 Rev 2 47/56

Application information

Figure 12: VIO and digital interface in standalone application schematic

STWLC03

Figure 13: VIO and digital interface in platform application schematic

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STWLC03

8.2 External passive component selection

8.2.1

Application information

Input resonant circuit component selection (L1, C1, C2)

The selected RX coil should be optimized by the requested transferred power. The inductance of the coil together with C

1

and C

2

capacitors create an input resonant circuit.

Components have to be carefully selected both to keep the resonant frequency compliant with the wireless standard specification and to deliver the power. For more details please see wireless standard specifications.

The following equations show the resonant frequencies, where L1’ is self-inductance of L1 placed on the transmitter:

Equation 1: 𝑓 𝑠

=

1

2 ∗ 𝜋 ∗ √𝐿

1

′ ∗ 𝐶

1

Equation 2: 𝑓

𝐷

=

1

2 ∗ 𝜋 ∗ √𝐿

1

∗ (

1

𝐶

1

+

1

𝐶

2

)

−1

It is recommended to use high grade ceramic capacitors with C0G dielectrics type. X5R,

X7R capacitors can be used for 5 W output power applications.

8.2.2

8.2.3

8.2.4

8.2.5

Voltage clamp resistor selection (RCL1, RCL2)

The purpose of these resistors is to load the rectifier output by decreasing the rectified voltage below overvoltage threshold – hysteresis (V

OVP

-V

OVPHYST

), when V

OVP

is reached.

0.2 W resistors with pulse withstanding character are recommended for this application.

Load modulation capacitors selection (CM1, CM2)

These capacitors fulfill the backscatter modulation of the communication from the receiver to the transmitter. X5R dielectrics type capacitors are suitable for this purpose. Higher values of these capacitors help to comply to PMA standard, but increase the ripple in the system.

Feedback resistor divider components selection (RFB1, RFB2)

Feedback voltage divider gives the ratio between the desired step-down converter output voltage and the given feedback reference voltage. The R

FB1

and R

FB2

resistors should be

0.1% or 0.5% tolerance class.

Rx NTC circuit component selection (RNTC, R1)

To protect the receiver coil from overtemperature, the STWLC03 is equipped with a

comparator input. If the input voltage crosses certain level (see Table 4: "Thermal data" ),

the STWLC03 can react by terminating the power transfer and sending an interrupt to the host system – depending on the configuration. The input voltage given as a ratio from R

NTC thermistor and R

1

common resistor divider. The divider can be supplied from LDO1 (VA pin) filtering capacitor.

DocID029451 Rev 2 49/56

Application information

8.2.6 Soft-start capacitor selection (C10)

STWLC03

The soft-start capacitor C10 connected to COMP pin influences the ramp-up time of the step-down converter. The nominal V

REF

voltage is 1.2 V and the time needed to reach the nominal voltage is given by the following equation:

Equation 3:

Example: 470 nF ~ 560 ms 𝑡

𝑆𝑂𝐹𝑇𝑆𝑇𝐴𝑅𝑇

= 𝐶 ∙ 10 6 ∙ 𝑉𝑅𝐸𝐹[𝑠, 𝐹, −, 𝑉]

8.2.7 External supply transistor selection

The device contains the function of the connection external voltage supply directly to V

OUT by the external dual P-channel transistor back-to-back connected so to avoid the leakage from V

OUT

to the external voltage supply.

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STWLC03

8.3 Reference PCB layout

Figure 14: Top overlay

Application information

Figure 15: Top layer

Figure 16: Mid layer 1 Figure 17: Mid layer 2

DocID029451 Rev 2 51/56

Application information

Figure 18: Bottom layer

STWLC03

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STWLC03

9

9.1

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

Flip Chip 77 bumps (3.12x4.73 mm) package information

Figure 19: Flip Chip 77 bumps (3.12x4.73 mm) package outline

DocID029451 Rev 2 53/56

Package information

Dim.

Table 67: Flip Chip 77 bumps (3.12x4.73 mm) package mechanical data

STWLC03 mm

Min. Typ. Max. e

SD

SE fD fE

$ ccc

D

D1

E

E1

A

A1

A2 b

0.50

0.17

0.28

0.23

4.67

3.06

0.40

0.20

0.20

0.352

0.346

0.05

0.075

0.55

0.20

0.30

0.26

4.70

4.00

3.09

2.40

0.60

0.23

0.32

0.29

4.73

3.12

The terminal A1 on the bump side is identified by a distinguishing feature (for instance by a circular "clear area", typically 0.1 mm diameter) and/or a missing bump. The terminal A1 on the backside of the product is identified by a distinguishing feature (for instance by a circular "clear area", typically between 0.1 and 0.5 mm diameter, depending on the die size).

Figure 20: Flip Chip 77 bumps (3.12x4.73 mm) recommended footprint

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10

Revision history

Revision history

Date Revision

Table 68: Document revision history

Changes

09-Nov-2016

14-Mar-2017

1

2

Initial release.

Updated Section 8.2.1: "Input resonant circuit component selection

(L1, C1, C2)" .

DocID029451 Rev 2 55/56

STWLC03

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– All rights reserved

56/56 DocID029451 Rev 2