AMS AS3701 Power Management Datasheet

General Description

AS3701

Micro-PMIC

The AS3701 is a small compact PMU for small size and low power applications.

AS3701 features one 500mA DCDC buck converter operating from 1MHz up to 4MHz, two 200mA LDOs, two 40mA current sinks and offers additional GPIO functions. Further, the device contains an integrated linear battery charger with constant current and constant voltage operation. The wide charging current range going from 11mA up to 500mA and the integrated battery temperature monitoring with selectable NTC beta values make this device suitable for a great variety of applications.

The single supply voltage may vary from 2.7V to 5.5V and all functionalities of AS3701 can be controlled via the I²C interface.

Ordering Information

and

Content Guide appear at end of

datasheet.

Key Benefits & Features

The benefits and features of AS3701, Micro-PMIC are listed below:

Figure 1:

Added Value of Using AS3701

Benefits

•

Multiple rails in a compact design for low power applications

•

Self-contained Li-Ion battery charger with power path

•

Flexible multi-purpose IOs for general control tasks and for standalone operation without

I²C interface

Features

•

2 x 200mA universal LDO (1.2V to 3.3V)

•

500mA Step-down DCDC (0.6125V to 3.35V)

•

2 programmable current sources up to 40mA

•

Possible external PWM dimming input

•

Linear charger with internal transistor

•

500mA max charging current

•

Trickle-, constant current and constant voltage operation (3.82V to 4.44V)

•

Charger timeout and temperature supervision

•

NTC beta selection

•

Wake-up / Stand-by / Power-down input

•

PWM input/output

•

Interrupt input/output

•

Low battery and Power Good output

•

Charging and USB current setting input

•

Charger control input/output

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AS3701 −

General Description

Benefits

•

Flexible and fast adaptation to different processors/applications

•

Power saving control according to the processor’s needs

Features

•

OTP programmable boot sequence

•

Self-contained start-up and safety shutdown feature

•

Cost effective, small package optimized for

PCB cost or size

•

Stand-by function with programmable voltages

•

I²C control interface

•

ON-key with 4/8s emergency power-down

•

POR with Reset I/O

•

17-balls WL-CSP with 0.4mm pitch

•

20-balls WL-CSP with 0.4mm pitch

Applications

The device is a PMU for low power applications like sport watches, smart watches, handheld GPS devices, mobile phones and any other 1-cell Li+ powered devices.

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AS3701 −

General Description

Figure 2:

Functional Blocks of AS3701A

Block Diagram

The functional blocks of this device are shown below:

2.2uF

VSUP

VSUP_CHG

VBAT

XIRQ_NTC

ON

SCL

SDA

XRES

VUSB

AS3701A

Power Path &

Current Limiter

Linear

Charger

LOGIC &

CONTROL

PWM

GND

LDO1

1.2 – 3.3V

200mA

Iq = 5uA

LDO2

1.2 – 3.3V

200mA

Iq = 5uA

DCDC

500mA

0.6 – 3.4V

Iq = 30uA

Current

Sinks

LDO1

2.2uF

LDO2

2.2uF

VSUP_SD1

VSUP

2.2uF

LX_SD1

FB_SD1

VSS_SD1

1uH

VSUP

GPIO1_CURR1

GPIO2_CURR2

10uF

Block Diagram:

This figure shows the block diagram of the AS3701A

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General Description

Figure 3:

Functional Blocks of AS3701B

2.2uF

VSUP

VSUP_CHG

VBAT

XIRQ_NTC

ON

SCL

SDA

XRES

VUSB

AS3701B

Power Path &

Current Limiter

Linear

Charger

LOGIC &

CONTROL PWM

GPIO

GND

GPIO3..5

LDO1

1.2 – 3.3V

200mA

Iq = 5uA

LDO2

1.2 – 3.3V

200mA

Iq = 5uA

DCDC

500mA

0.6 – 3.4V

Iq = 30uA

Current

Sinks

LDO1

2.2uF

LDO2

2.2uF

VSUP_SD1

VSUP

2.2uF

LX_SD1

FB_SD1

VSS_SD1

1uH

VSUP

GPIO1_CURR1

GPIO2_CURR2

10uF

Block Diagram:

This figure shows the block diagram of the AS3701B

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AS3701 −

Pin Assignments

Pin Assignments

Pin Assignments:

Shows the top view pin assignment of the AS3701A

Figure 4:

17-balls WL-CSP Pin Assignment for AS3701A

Pin A1 indicator

A1

B1

C1

D1

A2 A3

B2 B3

D2 D3

A4

C4

D4

A5

B5

C5

D5

Pin Assignments:

Shows the top view pin assignment of the AS3701B

Figure 5:

20-balls WL-CSP Pin Assignment for AS3701B

Pin A1 indicator

A1

B1

C1

D1

B2

C2

A2 A3

D2

B3

C3

D3

A4

B4

C4

D4

A5

B5

C5

D5

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AS3701 −

Pin Assignments

Figure 6:

Pin Description

B5

-

C1

-

-

D1

B2

D4

D3

B3

D5

A1

D2

B1

A5

A4

A3

D1

B2

D4

D3

B3

D5

A1

D2

B1

A5

A4

A3

Pin Number

17

Balls

20

Balls

A2 A2

Pin

Name

I/O Description

VUSB

VSUP_CHG

VSUP_SD1

VBAT

GND

LDO1

LDO2

LX_SD1

FB_SD1

S

SIO

Wall adapter or USB Bus Power input

(before protection)

Current limiter output,

LDO1 & LDO2 pos. supply terminal

S

S

DCDC pos. supply terminal

Li-Ion Battery Terminal

AIO Reference GND

AO LDO1 Output

AO LDO2 Output

AIO

DCDC Step Down Switch Output to

Coil

AI DCDC Step Down Feedback Pin

XRES

ON

XIRQ_NTC

SCL

DIO Reset IO

DI Power Up Input

AIO Interrupt Output or NTC Input

DI 2-wire Serial IF Clock Input

Max.

Voltage

5.5V

5.5V

3.6V

VSUP

5.5V

VSUP

VSUP

VSUP

VSUP

5.5V

-

3.3V

3.3V

C4

C5

C4

C5

DIO 2-wire Serial IF Data I/O

DIO General Purpose IO1 or LED Channel 1

VSUP

VSUP

If Not

Used

Open

Pull-up to

VSUP

Open

Open

Pull-up to

VSUP

Pull-up to

VSUP

Open

Pull-down to

GND

Mandatory

Mandatory

Open

Mandatory

Open

Open

Open

B5

B4

C2

C3

C1

SDA

GPIO1_

CURR1

GPIO2_

CURR2

GPIO3

GPIO4

GPIO5

VSS_SD1

DIO General Purpose IO2 or LED Channel 2

DIO General Purpose IO3

DIO General Purpose IO4

DIO General Purpose IO5

AIO GND connector of DCDC

VSUP

VSUP

VSUP

VSUP

-

Open

Open

Open

Open

Mandatory

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AS3701 −

Absolute Maximum Ratings

Absolute Maximum Ratings

Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under

Electrical

Characteristics is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

Figure 7:

Absolute Maximum Ratings

Symbol

V

GND

V

GND

I

SCR

P

T

ESD

HBM

Parameter Min Max Units Comments

Electrical Parameters

Supply voltage to ground 5V pins

Supply voltage to ground 3V pins

-0.5

-0.5

7.0

5.0

V

V

Applicable for pins

VSUP_CHG, VSUP_SD1, VBAT,

VUSB, LX_SD1, SCL, SDA, ON,

XRES, XIRQ_NTC, GPIO3, GPIO4,

GPIO5, GPIO1_CURR1, GPIO2_

CURR2

Applicable for pins

LDO1, LDO2, FB_SD1

Applicable for pins

GND, VSS_SD1

Voltage difference between ground terminals

Input current

(latch-up immunity)

Electrostatic discharge

(human body model)

-0.5

-100

Continuous Power Dissipation (T

A

= 70°C)

Continuous power dissipation 0.96

W

P

T

(1)

for WL-CSP20

(

R

THJA

~ 57K/W

)

Electrostatic Discharge

±2

0.5

100

V mA kV

JEDEC JESD78

JEDEC JESD22-A114F

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AS3701 −

Absolute Maximum R atings

Symbol

T

A

R

THJA

T

J

T

STRG

T

BODY

RH

NC

MSL

Parameter Min Max Units Comments

Temperature Ranges and Storage Conditions

-40 85 °C Operating temperature

Junction to ambient thermal resistance

°C/W

R

THJA

typ. 57K/W

Junction temperature

Storage temperature range -55

125

125

°C

°C

260 °C

IPC/JEDEC J-STD-020

(2)

Package body temperature

Relative humidity

(non-condensing)

5 85 %

Moisture sensitivity level 1

Represents an unlimited floor life time

Note(s):

1. Depending on actual PCB layout and PCB used

2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity

Classification for Non hermetic Solid State Surface Mount Devices“

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AS3701 −

Electrical Characteristics

Electrical Characteristics

All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical

Quality Control) methods.

Figure 8:

Electrical Characteristics

Symbol

V

IN

I

Q_ACTIVE

Parameter

Input voltage range

Active mode quiescent current

Pin VSUP

Conditions

Normal operating current

I

Q_STAND-BY

Stand-by quiescent current

Normal operating current

(Oscillator ON)

Normal operating current

(Oscillator OFF)

I

POWEROFF

Shutdown current

power_off

= 1

Min Typ Max Unit

2.7

26

26

11.5

1.2

5.5

V

μ

A

Electrical Characteristics:

V

SUP

= 3.7V, V

OUT

< V

IN

– 0.5V, T

AMB

= -40°C to 85°C, typ. values @ T

AMB

= 25°C (unless otherwise specified)

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AS3701 −

Detailed Description – Power Management Functions

Detailed Description –

Power Management Functions

Step Down Converter

The step-down converter is a high-efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches, efficiency up to 95% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to the maximum output current, with an output capacitor of only 10μF. The implemented current limitation protects the DCDC Converter and the coil during overload condition.

Figure 9:

DCDC Step-Down Converter Block Diagram

Sd_low_noise

Clk

Ref + 8%

Overvoltage

Comparator

-

I

MIN

170mA

-

I

LIMIT

800mA

I

SENSEP

VSUP

2.2uF

1uH

LX_SD1

VOUT

10uF

Ref - 5%

Sd_lv

-

PWM

Comparator

Σ

+

Logic

Slope

Compensation

Zero

Comparator

Skip

Ref = 0.6V

I

SENSEN

VSS_SD1

FB_SD1 buck _v

Softstart

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Detailed Description – Power Management Functions

Mode Settings

To allow optimized performance in different applications, there are bit settings possible, to get the best compromise between high efficiency and low input/output ripple.

Figure 10:

DCDC Step-Down Converter Mode Settings

Mode Setting:

This graph shows the difference of the efficiency curves for high efficiency and low noise mode setting. V

SUP

= 3.7V, V

OUT

= 2.5V, f

SW

= 3MHz, T

AMB

= 25°C.

3

5

100

90

80

70

60

50

40

0.001

1

2 4

Vout = 2.5V, low noise

Vout = 2.5V

0.01

0.1

Output Current (A)

1

Low-Ripple, Low-Noise Operation

Low-ripple, low-noise operation can be enabled by setting the bit

sd_low_noise [SD_control1]

to 1.

In this mode there is no minimum coil current necessary before switching OFF the PMOS. As long as the load current is superior to the ripple current, the device operates in continuous mode.

When the load current gets lower, the discontinuous mode is triggered. Resultant the auto-zero comparator stops the NMOS conduction to avoid load discharger and the duty cycle is reduced down to t

MIN_ON to keep the regulation loop stable.

This results in a very low ripple and noise, but decreased efficiency at light loads, especially at low input to output voltage differences.

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Figure 11:

Switching Behavior at Operating Point 4

AS3701 −

Detailed Description – Power Management Functions

Operating Point 4:

These graphs show the switching behavior referring to the operating point 4 from figure10.

Here the mode is set to low noise/low ripple operation and the DCDC is continuously switching at 10mA load current.

Only in the case the load current gets so small, that less than the minimum on time of the PMOS would be needed to keep the loop in regulation, the regulator will enter low power mode operation.

Figure 12:

Switching Behavior at Operating Point 2

Operating Point 2:

These graphs show the switching behavior referring to the operating point 2 from figure10.

Here the mode is set to low noise/low ripple operation and the DCDC has already started to skip pulses, as the minimum PMOS ON time of 40ns has been reached and the load current is further decreasing down to 2mA.

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Detailed Description – Power Management Functions

Figure 13:

Switching Behavior at Operating Point 1

High-Efficiency Operation (Default Setting)

High-efficiency operation is enabled by setting the bit sd_low_ noise [SD_control1] to 0.

In this mode there is a minimum coil current necessary before switching OFF the PMOS. Resultant there are less pulses necessary at low output loads, and therefore the efficiency increases. As drawback, this mode increases the ripple up to a higher output current.

Operating Point 1:

These graphs show the switching behavior referring to the operating point 1 from figure10.

Here the mode is set to high efficiency operation and the DCDC is in skipping mode at 2mA load current. Here a minimum coil current during the PMOS ON time is needed, hence more energy can be stored, the duration between the bursts is longer and the efficiency increases.

Figure 14:

Output Voltage Ripple Measurement at Operating Point 3

Operating Point 3:

These graphs show the switching behavior referring to the operating point 3 from figure10.

Here the mode is set to high efficiency operation and comparing to operating point 4 the DCDC is still in skipping mode at 10mA load current and keeps the efficiency higher.

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AS3701 −

Detailed Description – Power Management Functions

Figure 15:

Output Voltage Ripple Measurement at Operating Point 5

Operating Point 5:

These graphs show the switching behavior referring to the operating point 5 from figure10.

Here the load current is 100mA and high enough to keep the DCDC always in a continuous switching operation regardless of the mode setting.

Low Power Mode Operation (Automatically Controlled)

As soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. Normal operation starts as soon as the output drops below the target value for a similar amount of time. To minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple.

Two addition guard bands, based on comparators, are set at

±5% of the target value to react quickly on large over/undershoots by immediately turning ON the output drivers without the normal time delays. This ensures a minimized ripple also in very extreme load conditions.

Dynamic Voltage Management

To minimize the over-/undershoot during a change of the output voltage, the DVM can be enabled with

dvm_enable [SD_ control2]

. With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. The DVM time can be chosen between 8

μ s and 16

μ s by setting the bit

dvm_time [SD_control2]

. Without DVM the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current.

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Detailed Description – Power Management Functions

Fast Regulation Mode

This mode can be used to react faster on sudden load changes and thus minimize the over-/undershoot of the output voltage.

This mode needs a 22

μ

F output capacitor instead the 10

μ

F one to guarantee the stability of the regulator.

The mode is enabled by setting the bit

sd_fast [SD_control1]

to 1.

Selectable Frequency Operation

Especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be reduced to achieve a higher efficiency. The frequency can be set to 1, 2, 3 or 4MHz and this mode is selected by setting

sd1_freq

[SD1Voltage]

and

sd1_fsel [SD_control1]

to the appropriate values.

Parameters

Figure 16:

DCDC Step-Down Converter Electrical Characteristics

Symbol

V

IN

V

OUT

V

OUT_TOL

I

LIMIT

R

PMOS

R

NMOS f

SW

I

LOAD

I

SUP_DCDC t

MIN_ON

Parameter Note

Input Voltage

Regulated Output Voltage

Pin VSUP

Output Voltage Tolerance min. 40mV

Current Limit

P-switch ON resistance

N-switch ON resistance

Switching Frequency

Load Current

Current Consumption

Operating Current without Load

Shutdown Current

Minimum ON Time

Min

2.7

0.6125

-3

1

800

0.36

0.33

3

500

Typ Max Unit

5.5

3.35

+3

1

1

4

V

V

% mA

Ω

Ω

MHz mA

27

0.1

40

μ

A ns

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Figure 17:

DCDC Step-Down Converter External Components

AS3701 −

Detailed Description – Power Management Functions

Symbol

C

FB_SD1

C

VSUP_SD1

L

SD1

Parameter

Output Capacitor

Input Capacitor

Inductor

Note

Ceramic X5R or X7R

Ceramic X5R or X7R

4MHz operation

3MHz operation

2MHz operation

1MHz operation

Min

8 10

2.2

1

2.2

1

1

Typ Max Unit

μF

μF

μH

Figure 18:

DCDC Step Down Converter Efficiency vs. Load Current at 1MHz

100

90

80

70

60

50

40

30

20

10

0.001

Vout = 0.6125V

Vout = 0.6125V, low noise

Vout = 1.2V, low noise

Vout = 1.2V

Vout = 1.8V, low noise

Vout = 1.8V

Vout = 3.0V, low noise

Vout = 3.0V

0.01

0.1

Output Current (A)

1

100

90

80

70

60

50

40

30

20

10

0.001

Vout = 1.0V, low noise

Vout = 1.0V

Vout = 1.5V, low noise

Vout = 1.5V

Vout = 2.5V, low noise

Vout = 2.5V

Vout = 3.35V, low noise

Vout = 3.35V

0.01

0.1

Output Current (A)

1

DCDC Efficiency vs. Output Current:

V

SUP

= 3.7V, f

SW

= 1MHz, Murata LQM2HPN2R2MG0L 2.2

μ

H coil,

T

AMB

= 25°C.

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Detailed Description – Power Management Functions

Figure 19:

DCDC Step Down Converter Efficiency vs. Load Current at 2MHz

100

90

80

70

60

50

40

30

20

10

0.001

Vout = 0.6125V, low noise

Vout = 0.6125V

Vout = 1.2V, low noise

Vout = 1.2V

Vout = 1.8V, low noise

Vout = 1.8V

Vout = 3.0V, low noise

Vout = 3.0V

0.01

0.1

Output Current (A)

1

100

90

80

70

60

50

40

30

20

10

0.001

Vout = 1.0V, low noise

Vout = 1.0V

Vout = 1.5V, low noise

Vout = 1.5V

Vout = 2.5V, low noise

Vout = 2.5V

Vout = 3.35V, low noise

Vout = 3.35V

0.01

0.1

Output Current (A)

1

DCDC Efficiency vs. Output Current:

V

SUP

= 3.7V, f

SW

= 2MHz, Murata LQM2HPN1R0MG0L 1

μ

H coil, T

AMB

= 25°C.

Figure 20:

DCDC Step Down Converter Efficiency vs. Load Current at 3MHz

100

90

80

70

60

50

40

30

20

10

0.001

Vout = 0.6125V, low noise

Vout = 0.6125V

Vout = 1.2V, low noise

Vout = 1.2V

Vout = 1.8V, low noise

Vout = 1.8V

Vout = 3.0V, low noise

Vout = 3.0V

0.01

0.1

Output Current (A)

1

100

90

80

70

60

50

40

30

20

10

0.001

Vout = 1.0V, low noise

Vout = 1.0V

Vout = 1.5V, low noise

Vout = 1.5V

Vout = 2.5V, low noise

Vout = 2.5V

Vout = 3.35V, low noise

Vout = 3.35V

0.01

0.1

Output Current (A)

1

DCDC Efficiency vs. Output Current:

V

SUP

= 3.7V, f

SW

= 3MHz, Murata LQM2HPN1R0MG0L 1

μ

H coil, T

AMB

= 25°C.

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AS3701 −

Detailed Description – Power Management Functions

Figure 21:

DCDC Step Down Converter Efficiency vs. Load Current at 4MHz

100

90

80

70

60

50

40

30

20

10

0.001

Vout = 0.6125V, low noise

Vout = 0.6125V

Vout = 1.2V, low noise

Vout = 1.2V

Vout = 1.8V, low noise

Vout = 1.8V

Vout = 3.0V, low noise

Vout = 3.0V

0.01

0.1

Output Current (A)

1

100

90

80

70

60

50

40

30

20

10

0.001

0.01

0.1

Output Current (A)

Vout = 1.0V, low noise

Vout = 1.0V

Vout = 1.5V, low noise

Vout = 1.5V

Vout = 2.5V, low noise

Vout = 2.5V

Vout = 3.35V, low noise

Vout = 3.35V

1

DCDC Efficiency vs. Output Current:

V

SUP

= 3.7V, f

SW

= 4MHz, Murata LQM2HPN1R0MG0L 1

μ

H coil, T

AMB

= 25°C.

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Detailed Description – Power Management Functions

Figure 22:

Universal IO LDO Regulator Block Diagram

Universal IO LDO Regulator

This LDO is a low-power and low-quiescent current linear-regulator specifically designed for space-limited applications. This device can supply loads up to 200mA and consist of an error amplifier, and a P-channel MOSFET pass transistor.

Vref

+ -

Error

Amplifier

VSUP

2.2uF

LDOx

2.2uF

Parameters

Figure 23:

Universal IO LDO Regulator Electrical Characteristics

Symbol

V

IN

Parameter

Input voltage

ΔV

OUT

Output voltage accuracy

Note

Pin VSUP

I

OUT

= 1mA, V

OUT

> 2V T

AMB

=

25°C

Guaranteed by design

I

OUT

= 100

μ

A to 200mA

V

OUT

> 2V

I

OUT

= 1mA, V

OUT

≤ 2V

T

AMB

= 25°C

Guaranteed by design

I

OUT

= 100

μ

A to 200mA

V

OUT

≤ 2V

Min Typ Max

2.7

5.5

Unit

V

-2.5

+2.5

%

-3 +3

-20

-50

+20

+50 mV

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AS3701 −

Detailed Description – Power Management Functions

Symbol Parameter Note

I

V

V

V

I

R

I

OUT

LNR

LDR

ON

OUT

LIMIT

I

Q

OFF eN

Output voltage range

Line regulation static

Line regulation dynamic

V

IN

= 2.7V to 5.5V

I

OUT

= 1mA

V

IN

= 2.7V to 5.5V within 15

μ s

I

OUT

= 1mA

Load regulation static

I

OUT

= 100

μ

A to 200mA

Load regulation dynamic

I

OUT

15

μ s

= 100

μ

A to 200mA within

ON resistance

Guaranteed load current

RMS

Short-circuit

Quiescent current

V

OUT

= 0V

No Load

I

OUT

= 100μA

I

OUT

= 200mA

Shutdown supply current

LDO disabled

Output noise

BW = 10Hz to 100Hz;

V

OUT

C

OUT

= 1.2V; I

= 2.2

μ

F

OUT

= 1mA;

BW = 10Hz to 100Hz;

V

OUT

C

OUT

= 3.3V; I

= 2.2

μ

F

OUT

= 1mA; t

START t

SHUTDOWN

Startup time

Shutdown time

Figure 24:

Universal IO LDO Regulator External Components

Min Typ Max

1.2

3.3

0.07

Unit

V

%/V

200

230

5

5

15

0.1

20

0.014

30

0.5

1

112

205

750

500

1 mV

%/mA mV

Ω mA mA

μ

A

μ

A

μ

Vrms

μ s

μ s

Symbol

C

LDOx

Parameter

Output capacitor

Note

Ceramic X5R or X7R

Min

2.2

Typ Max Unit

4.7

μF

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AS3701 −

Detailed Description – Power Management Functions

Figure 25:

LDO Output Voltage vs. Output Current 1/2

1.210

1.205

1.200

1.195

1.190

1.185

1.180

0.1

Vout = 1.2V

VSUP = 2.8V

VSUP = 3.7V

VSUP = 5.5V

1 10 100

Output Current (mA)

1000

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

0.1

Vout = 1.2V

1

VSUP = 2.8V

VSUP = 3.7V

VSUP = 5.5V

10 100

Output Current (mA)

1000

LDO Output Voltage vs. Output Current:

V

OUT

= 1.2V, T

AMB

= 25°C.

Figure 26:

LDO Output Voltage vs. Output Current 2/2

3.05

3.04

3.03

3.02

3.01

3

0.1

Vout = 3.0V

VSUP = 3.7V

VSUP = 5.5V

1 10 100

Output Current (mA)

1000

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

0.1

Vout = 3.0V

1

VSUP = 3.7V

VSUP = 5.5V

10 100

Output Current (mA)

1000

LDO Output Voltage vs. Output Current:

V

OUT

= 3.0V, T

AMB

= 25°C.

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LDO Load Transient Response:

V

SUP

= 3.7V, V

OUT

= 1.2V, t

RISE

= 15

μ s,

I

OUT

= 100

μ

A to 200mA, T

AMB

= 25°C.

(Blue channel: V

OUT

; Red channel: I

OUT

)

AS3701 −

Detailed Description – Power Management Functions

Figure 27:

LDO Load Transient Response 1/2

LDO Load Transient Response:

V

SUP

= 3.7V, V

OUT

= 3.0V, t

RISE

= 15

μ s,

I

OUT

= 100

μ

A to 200mA, T

AMB

= 25°C.

(Blue channel: V

OUT

; Red channel: I

OUT

)

Figure 28:

LDO Load Transient Response 2/2

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AS3701 −

Detailed Description – Power Management Functions

Linear Charger

This block can be used to charge Li-Ion batteries. Requiring less external components, a full-featured battery charger with a high degree of flexibility can easily be realized. The main features of the controller are:

•

Charge adapter detection

•

Power Path management for dead battery startup

•

Low current Trickle charging

•

Constant current charging

•

Constant voltage charging

•

Operation without battery

•

Battery presence indication

•

NTC temperature supervision

•

Input current limitation

Figure 29:

Linear Charger Block Diagram

VUSB

VSUP

VSUP

1uF

Pre-Regulator

&

Current Limiter

VBAT

10k/

100k

XIRQ_NTC

15k/

150k battery switch

15uA/

150uA ideal diode

Charger

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AS3701 −

Detailed Description – Power Management Functions

Figure 30:

Linear Charger Modes

USB input

USB

Power Path &

Current Limiter

I

SYS

System

VSUP

VSUP

1uF

Battery

VBAT

I

BAT

Linear

Charger

No charger is connected, all the power comes out of the battery.

USB input

USB

Power Path &

Current Limiter

I

USB

> 500mA

I

SYS

200mA

System

VSUP

VSUP

1uF

Battery

VBAT

I

CHG

300mA

Linear

Charger

Charging is active. All the power comes from the USB through the current limiter. If the system current exceeds the choosen USB current limit, the charging current get reduced automatically.

USB input

USB

I

SYS

200mA

System

VSUP

VSUP

1uF

Battery

VBAT

Power Path &

Current Limiter

I

USB

> 500mA

Linear

Charger

When battery is fully charged, the switch opens to disconnect the battery. All the power comes from the USB.

USB input

USB

Power Path &

Current Limiter

I

USB

> 500mA

I

SYS

700mA

System

VSUP

VSUP

1uF

Battery

VBAT

I

BAT

200mA

Linear

Charger

Charging is disabled. If the system current exceeds the choosen USB current limit, the additional needed current will be provided the battery.

Charging Modes:

This figure describes the 4 different charger modes.

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AS3701 −

Detailed Description – Power Management Functions

Charging Cycle Description

Charge Adapter Detection

The charge controller uses an integrated detection circuit to determine if an external charge adapter has been applied to the VUSB pin. If the adapter voltage exceeds the battery voltage at pin VBAT by V

CHDET

the

ChDet [ChargerStatus2]

will be set.

The detection circuit will reset the charge controller (bit

ChDet

is cleared) as soon as the voltage at the VUSB pin drops to only

V

CHMIN

above the battery voltage. In case the AS3701 device is reset the charge controller will also be reset, even if a charge adapter is applied to the VUSB pin. The Charger detection can be disabled by setting the bit

chdet_off [ChargerStatus2]

to “1”, which results in a further decrease of internal power consumption.

Low Current (Trickle) Charging

Trickle charge mode is started when an external charge adapter has been detected, the bit

bat_charging_enable

[ChargerControl]

is set and the battery voltage at pin VBAT is below the V

TRICKLE

threshold; bits

ChDet

and

Trickle

[ChargerStatus1]

will be set. In this mode the charge current will be limited to TrickleCurrent

[ChargerCurrentControl]

to prevent undue stress in case of deeply discharged batteries. Once

V

TRICKLE

has been exceeded, the charger will change over to constant current charging (Trickle is cleared).

Constant Current Charging

Constant current charging is initiated when

bat_charging_ enable [ChargerControl]

and the battery voltage at pin VBAT is above the V

TRICKLE

and below V

CHOFF

. The bit

CCM

[ChargerStatus1]

is set when the charger has started, and the charge current will be limited by the battery charge controller.

The current for the Constant Current Charging can be selected out of the range defined in

ConstantCurrent

[ChargerCurrentControl]

if the bit

cc_range_select

[ChargerControl]

is set to “0” or out of the range defined in

TrickleCurrent [ChargerCurrentControl]

if the bit

cc_range_select

[ChargerControl]

is set to “1”. When the battery approaches full charge, its voltage will reach the charge termination threshold

V

CHOFF

. V

CHOFF

depends on the

ChVoltEOC

[ChargerVoltageControl]

bits settings. Top-OFF charge will be started and the bit

CVM [ChargerStatus1]

will be set.

Constant Voltage Charging

Constant voltage charge mode is initiated and the bit

CVM

[ChargerStatus1]

will be set when the V

CHOFF

threshold has been reached. The charge current is monitored during constant voltage charging. It will be decreasing from its initial value during constant current charging and eventually drops below

5% or 50% of the Constant Current value (depends on the

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Figure 31:

Resume Voltage Levels

ChVoltResume

3.33%

5.56%

Figure 32:

Linear Charger States

3.82V

127mV

212mV

3.84V

128mV

213mV

AS3701 −

Detailed Description – Power Management Functions setting of the bit

eoc_current [ChargerCurrentControl]

). If the measured charge current is less than or equal to

eoc_current

, the charging cycle is terminated and

EOC [ChargerStatus1]

is set.

Resume

If EOC is reached and the bit

AutoResume [ChargerControl]

is set, the charging will immediately start again, if the battery voltage falls below the specified resume voltage

ChVoltResume

[ChargerConfig1]

. This voltage can be set either to 3.33% or

5.56% of

ChVoltEOC [ChargerVoltageControl]

.

…

…

…

ChVoltEOC

4.20V

140mV

233mV

…

…

…

4.42V

147mV

246mV

4.44V

148mV

247mV

V

CHDET

External Charger at pin VUSB

5.5V max

Trickle Current

2.9V

Battery Voltage

(VBAT)

Constant Current Constant Voltage EOC

3.82V – 4.44V

44mA – 493mA

Charging

Current

Regulator

Voltages

11mA – 130mA after enabling the charger

I

CHGOFF

5% of CC –

50% of CC

Resume

3.3% or

5.6% of

V

EOC

XRES

I2C communication possible t (not to scale)

Charging States:

This figure describes the characteristics of the charging current and the battery voltage for each different charging state.

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AS3701 −

Detailed Description – Power Management Functions

Stop Charging Conditions

There are multiple safety features implemented triggering a stop_charging condition.

These are the following:

•

Battery temperature is too high: If

ntc_high_on

[ChargerSupervision]

= 1 and the voltage at pin NTC

(GPIO3, GPIO4 or XIRQ_NTC) is below V

BATTEMP

.

•

Battery temperature is too low: If

ntc_low_on

[ChargerSupervision]

= 1 and the voltage at pin NTC

(GPIO3, GPIO4 or XIRQ_NTC) is above V

BATTEMP

.

•

Charging timeout timer expired: If

ch_timeout

[ChargerConfig2]

> 0 and charging time has been exceeded. (Can be reset by unplugging the charger, setting

bat_charging_enable [ChargerControl]

= 0 or writing

charging_tmax [ChargerConfig2]

= 0)

•

Die temperature > 140°C (

ov_temp_140

[OvertemperatureControl]

is set)

•

Reset is initiated (each Reset reason forces a stopping of the charging)

Battery Presence Indication

After EOC state is reached, a timer for NOBAT detection is started. If there is no battery present, the VBAT voltage will drop to VRESUME. Depending on the load on VBAT and the capacitor on VBAT this might take some milliseconds to 1 second. If

AutoResume [ChargerControl]

is enabled, the charger will restart charging (Constant Current Charging) after 100ms delay.

The 100ms dead time is necessary to get a battery oscillation frequency below 10Hz, if there is no battery present.

If the NOBAT detection timer is below 2 seconds after reaching the EOC state, and this happens 2 times in serial, the bit

NoBat

[ChargerStatus1]

is set. If a battery is inserted, the bit will be reset after the timer exceeds the 2 seconds.

NTC Supervision

Configuration

The AS3701 also features a supply for an external NTC resistor to measure the battery temperature while charging. For

AS3701A, the pin XIRQ_NTC can be used as the NTC input pin, whilst AS3701B additionally offers the GPIO3 and GPIO4. With the bit

NTC_input [ChargerSupervision]

the NTC Supervision can be configured.

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AS3701 −

Detailed Description – Power Management Functions

Figure 33:

NTC Supervision Configuration

NTC_input

0

0

1

1

0

1

0

1

NTC Supervision Configuration

No NTC supervision

(1)

XIRQ_NTC pin

GPIO3 pin

(2)

GPIO4 pin

(2)

Note(s):

1. If no NTC supervision is selected, all NTC relevant bits are ineffective

2. AS3701B only

NTC Resistor

Depending on the used resistor value of the NTC (10k or 100k) the internal NTC current (150

μ

A for 10k or 15

μ

A for 100k) can be selected via

ntc_10k [ChargerSupervision]

.

High/Low Temperature

The battery high temperature supervision is controlled with the bit

ntc_high_on

[

ChargerSupervision

] and this feature is enabled per default. If the temperature is higher than 45°C or 60°C

(depending on

ntc_mode

[

ChargerSupervision

]) the flag

temp_ cond

[

ChargerStatus1

] will be set and the charger will stop operation. When the battery temperature drops and the voltage on NTC pin rises above V

BATTEMP_HIGH_OFF

, the flag

temp_cond

will be reset and the charger will continue with the charging again.

The battery low temperature supervision is controlled with the bit

ntc_low_on

[

ChargerSupervision

] and this feature is disabled per default. If the temperature is lower than 0°C the flag

temp_ cond

[

ChargerStatus1

] will be set and the charger will stop operation. When the battery temperature rises and the voltage on NTC pin falls below V

BATTEMP_LOW_OFF

, the flag

temp_cond

will be reset and the charger will continue with the charging again.

The detection of a high or low battery temperature can also be indicated with a dedicated interrupt mask bit

bat_temp_m

[

InterruptMask2

].

For the high and low temperature supervision, a temperature hysteresis is included to avoid an oscillation of the charger.

The supply for the NTC will be on when either the

ntc_high_on

or the

ntc_low_on

bit is set, no matter if a charger is detected or not. Therefore the battery temperature supervision can be used for charging mode and also for discharging mode.

ams Datasheet

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AS3701 −

Detailed Description – Power Management Functions

NTC ß-Correction

To keep the voltage drop over the whole temperature range inside of the comparator threshold voltage range, a 15k (150k) parallel resistor to the 10k (100k) NTC is needed. With the bit

ntc_beta [ChargerSupervision]

4 different

ß

-values depending on the used NTC resistor can be selected.

Figure 34:

NTC

ß

Influence Over Temperature

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0 10 20 30 40

NTC_Temperature (

°

C)

50 60

ß = 3000

ß = 3500

ß = 4000

ß = 4500

NTC ß Influence Diagram:

Shows the voltage drop over the NTC resistor depending on the temperature for 4 different ß values using R

NTC

=10kΩ, R p

=15kΩ and I

NTC

=150

μ

A.

Figure 35:

NTC Threshold Voltages

ß

Temperature Unit

Low temperature

High temperature

0°C

45°C

60°C

3000

1.41

0.59

0.42

3500

1.49

0.54

0.37

4000

1.56

0.50

0.31

4500

1.63

0.46

0.27

V

V

V

NTC Supervision:

Comparator threshold voltages for different temperatures and ß using R

NTC and I

NTC

=150

μ

A.

=10kΩ, R p

=15kΩ

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Figure 36:

High/Low Temperature Supervision

AS3701 −

Detailed Description – Power Management Functions

Charger High/Low Temperature Supervision

Maximum Charge Current: 1C

44mA < Constant Current < 493mA

11mA < Trickle Current < 130mA

CHARGE

CURRENT

CHARGE

VOLTAGE

COLD

Charger is

OFF

TYPICAL

Typical Charge Voltage: Veoc(typ)

3.82V < ChVoltEOC < 4.44V

HOT

Charger is

OFF

T

LO W_OFF

0°C

T

LO W_ON

TEMPERATURE [°C]

T

HIGH_ON

T

HIGH_OFF

45°C / 60°C

Temperature Supervision Diagram:

Shows the voltage and current settings for the high and low temperature supervision.

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ams Datasheet

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AS3701 −

Detailed Description – Power Management Functions

Figure 37:

Linear Charger Electrical Characteristics

Parameters

Symbol

I

TRICKLE

V

TRICKLE

Parameter

Trickle current

Note

11 steps programmable

Trickle to constant current threshold

V

BAT

rising

cc_range_select

= 0

I

CHG

Constant current

V

EOC

I

EOC

Charge termination threshold

EOC current level

I

USB_limit

V

SUP_prereg

VUSB input current limit

Voltage supplied from

Preregulator

V

RESUME

Resume Voltage limit to start charger

cc_range_select

= 1

@ 70mA

Programmable in 20mV steps end of charge is true referring to I

CHG

(VSUP > 3V)

@470mA

Depending on the bit

vsup_voltage

VBAT falling threshold referring to V

EOC

(depending on bit

ChVoltResume

)

Min Typ Max

11..

130

-8%

4.15

420

2.9

44..

493

11..

130

70

3.82..

4.44

4.2

5..

50

470

4.4..

5.5

+8%

4.25

500

Unit

mA

V mA mA

V

V

V mA mA

%

3.3

5.6

%

VSUP

MIN

VSUP level for charging current reduction, to avoid voltage drop on VSUP

Trickle or constant current will be regulated down, if VSUP drops below this threshold

-6%

V

CHDET

V

CHMIN

I

REV_OFF

Charger detection hysteresis

V

USB

- V

BAT

Hysteresis is > 40mV

R

ON_BATSW

Reverse current shut down

VSUP = 5V, V

USB

open

Battery switch

ON-resistance

50

0

3.9

4.2

4.5

4.7

75

20

<1

0.4

+3%

105

35

V mV mV uA

Ω

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AS3701 −

Detailed Description – Power Management Functions

Figure 38:

Capacitor Selection for VUSB, VSUP_CHG and VBAT

Symbol

C

VUSB

C

VSUP_CHG

C

VBAT

Parameter

Input capacitor

Output capacitor

Output capacitor

Note

Ceramic X5R or X7R

Ceramic X5R or X7R

Ceramic X5R or X7R

Min Typ Max

10

10

10

Unit

μ

F

μ

F

μ

F

Selection of Bypass Capacitors for the Pins VUSB,

VSUP_CHG and VBAT

In most applications using the ideal capacitance values shown in the table and the application schematic are recommended.

After evaluation of the voltage signals on these pins with real system operational conditions at the user’s application circuit, the user can determine if this ideal capacitance values needs to be adjusted.

It must be kept in mind that the capacitance value depends strongly on the rated voltage, therefore a selection of the appropriate nominal capacitor value related to the capacitor size is mandatory to achieve best performance under the specific operational voltage and load current condition of the application system.

Current Sinks

The following description of the Current Sinks refers only to the pins GPIO1_CURR1 and GPIO2_CURR2. Hence the suffix “X” stands either for 1 or for 2.

The AS3701 contains 2 GPIO pins (GPIO1_CURR1 and GPIO2_

CURR2), providing general purpose current sinks when the register

gpioX_mode [GPIOXcontrol]

is set to CURRx input. Next to this setting, the register

gpioX_iosf [GPIOXcontrol]

must be set to one of the GPIO output functions (please see the GPIO section in the following chapter “Detailed Description – System

Functions”).

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AS3701 −

Detailed Description – Power Management Functions

Parameters

Figure 39:

Current Sinks Electrical Characteristics

Symbol Parameter

I

CURR

x

CURR1_current = 01h – FFh

CURR2_current = 01h – FFh

I

CURRx_TOL

CURR current accuracy

V

CURR

x

Voltage compliance

Note

Resolution = 156.86

μ

A

CURRx_current = 40h

During normal operation

V

PROTECT

Maximum voltage at pin

CURRx to protect driver transistor

I

SINK

> 20mA guaranteed by design

Min

0.16

9.3

0.5

Typ

10

V

BAT

+

2V

Max

40

10.7

5.5

Unit

mA mA

V

V

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AS3701 −

Detailed Description – System Functions

Detailed Description –

System Functions

Start-Up

Normal Start-Up

The following gives a brief description on a start-up from scratch (battery or charger insertion). More details can be found in the start-up flow chart.

A start-up can be activated from 5 different sources:

•

Battery insertion from scratch

•

Charger insertion from scratch (VBAT <

ResVoltFall

)

•

ON-key has been pulled high in power_off mode

•

Reset cycle

•

ResVoltRise

level was reached

During a normal reset cycle a normal startup happens:

•

Setting USB current limit and ResVoltRise

•

Startup State machine reads out the internal Boot-OTP.

The start-up sequence of SD Converter, LDOs and GPIOs are controlled by the Boot-OTP

•

Reset-Timer is set by the Boot-OTP

•

The reset is released when the Reset Timer expires

(external pin XRES)

Parameter

Figure 40:

Start-Up Condition

Symbol

V

ON_IL

Parameter

Low level voltage

V

ON_IH

High level voltage

I

ON_PD

(1)

Pull down current

Note

ON pin

ON pin

Bit

on_invert

= 0 (active high)

Min Typ Max

20% of

VSUP

60% of

VSUP

4 12

Unit

V

V

μ

A

Note(s):

1. The internal pull-down resistor is just active if the bit on_invert is set to "0" (active high configuration). If the ON-key works active low (on_invert = 1) the internal pull-down resistor is deactivated and an external pull-up resistor is needed in push-button configuration!

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AS3701 −

Detailed Description – System Functions

Figure 41:

Start-Up Flowchart

Start-Up

Batter y or Charger insertion

1. VS UP > VPOR

2. Readout ROM fuse

auto_off

= 1

Y

POWER OFF state

Quiescent curr ent ~1uA

N

Y

on_input

= 1 (level det)

(debo unce time = 20ms)

OR C harger insertio n

(ch g_pwr_off_en=0 (level det))

(ch g_pwr_off_en=1 (edge det))

N

N

OFF delay

off_delay = 8ms

Y

power_off

= 1 OR

(VSUP<ResVoltFall && power_off_at_vsuplow=1)

N

OFF delay

off_delay = 8ms

Y

Die temp > 110°C

(

tco_110_a

= 1)

VSUP debounce state

Measuring V SUP

Quiesent cur rent <30uA

N

N

Y

auto_off

= 1 OR

power_off_at_vsuplow

= 1

N

VSUP>

ResVoltRise

fo r more than 5ms

Y

on_input

= 1 (level det)

OR

ChDet = 1

N

VSUP <

ResVoltFall

fo r more than 500ms

Y

Y

Reset all Registers

Switch off Regulators reset r egister s and reload OTP registers expect:

pwr_off_at_vsupl ow

Y

Die temp > 140°C

(

tco_140_a

= 1)

N any state

RUN startup sequence regulator star tup sequence star tup delay program mable

General Settings pr ogramm able

RESET Timer regulator star tup executed waiti ng tim e t o rel ease XRES pin

10..150ms

ACTIVE state

XRES = 1

(OSC alway s on)

N

OFF delay wait

off_delay

Y

power_off

= 1 OR

fo rce_reset

= 1 OR

(XRES is lo w &&

stdby_reset_disable

= 1) OR

VSUP<

ResVoltFall

N

STAND-BY state al l regulators wi th

sdX_stby_on

= 1 or

ldoX_stby_on

= 1 enabled

(OSC is off, if

sdX_stby_on

= 0)

OFF delay wait

off_delay

OFF delay wait

off_delay

Y

Y

power_off

= 1 OR

fo rce_reset

= 1 OR

XRES is lo w O R

VSUP<

ResVoltFall

OR

ON lon g-press (edge det)

N

standby_mod e_on

= 1

OR GP IOx = 1 if

gpiox_iosf

= 6

(edge det)

N any

Interru pt app lied O R

on_input

= 1 (level det)

(debo unce time = 20ms)

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AS3701 −

Detailed Description – System Functions

Figure 42:

Start-Up Sequence Diagram 1/5

VSUP

Reset Voltage Rise level

PO R level reached

2ms oscillator stable

5ms debounce

VSUP >

ResVoltRise

Reg1_addr (b0:3 fuse aah)

Reg2_addr (b4:7 fuse aah)

Reg3_addr (b0:3 fuse adh)

Reg4_addr (b4:7 fuse adh)

0ms delay (if

Reg1_delay

= 0)

1ms delay (if

Reg1_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg1_delay

= 1 and

del_time

= 1)

reg1_V (b0:7 fuse abh)

0ms delay (if

Reg2_delay

= 0)

1ms delay (if

Reg2_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg2_delay

= 1 and

del_time

= 1)

reg2_V (b0:7 fuse ach)

0ms delay (if

Reg3_delay

= 0)

1ms delay (if

Reg3_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg3_delay

= 1 and

del_time

= 1)

reg3_V (b0:7 fuse aeh)

0ms delay (if

Reg4_delay

= 0)

1ms delay (if

Reg4_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg4_delay

= 1 and

del_time

= 1)

reg4_V (b0:7 fuse afh)

1ms delay between last timeslot (regulator) and

PWRGood signal going high

PWRGood

10..150ms set by

res_timer

in O TP

XRES

Start-Up Sequence:

This diagram shows the timing of a startup from scratch (battery or charger insertion)

Figure 43:

Start-Up Sequence Diagram 2/5

VBAT = VSUP > ResVoltRise

ON

2ms oscillator stable

20ms

ON debounce

5ms debounce

VSUP >

ResVoltRise

0ms delay (if

Reg1_delay

= 0)

1ms delay (if

Reg1_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg1_delay

= 1 and

del_time

= 1)

reg1_V (b0:7 fuse abh)

Reg1_addr (b0:3 fuse aah)

Reg4_addr (b4:7 fuse adh)

0ms delay (if

Reg4_delay

= 0)

1ms delay (if

Reg4_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg4_delay

= 1 and

del_time

= 1)

reg4_V (b0:7 fuse afh)

1ms delay between last timeslot (regulator) and

PWRGood signal going high

PWRGood

10..150ms set by

res_timer

in O TP

XRES

Start-Up Sequence:

This diagram shows the timing of a startup from power-off mode via ON key press (battery connected, VSUP >

ResVoltRise

)

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AS3701 −

Detailed Description – System Functions

Figure 44:

Start-Up Sequence Diagram 3/5

VBAT = VSUP > ResVoltRise

USB

USB charger detection (VUSB > VBAT)

2ms oscillator stable

4ms

USB detect debounce

5ms debounce

VSUP >

ResVoltRise

0ms delay (if

Reg1_delay

= 0)

1ms delay (if

Reg1_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg1_delay

= 1 and

del_time

= 1)

reg1_V (b0:7 fuse abh)

Reg1_addr (b0:3 fuse aah)

Reg4_addr (b4:7 fuse adh)

0ms delay (if

Reg4_delay

= 0)

1ms delay (if

Reg4_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg4_delay

= 1 and

del_time

= 1)

reg4_V (b0:7 fuse afh)

1ms delay between last timeslot (regulator) and

PWRGood signal going high

PWRGood

10..150ms set by

res_timer

in O TP

XRES

Start-Up Sequence:

This diagram shows the timing of a startup from power-off mode via USB charger detection event (battery connected, VSUP >

ResVoltRise

)

Figure 45:

Start-Up Sequence Diagram 4/5

VSUP > ResVoltRise

8ms

OFF delay

Reg1_addr

(b0:3 fuse aah)

Reg4_addr

(b4:7 fuse adh)

5ms debounce

VSUP >

ResVoltRise

0ms delay (if

Reg1_delay

= 0)

1ms delay (if

Reg1_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg1_delay

= 1 and

del_time

= 1)

reg1_V (b0:7 fuse abh)

0ms delay (if

Reg4_delay

= 0)

1ms delay (if

Reg4_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg4_delay

= 1 and

del_time

= 1)

reg4_V (b0:7 fuse afh)

1ms delay between last timeslot (regulator) and

PWRGood signal going high

PWRGood

I2C or internal reset command

XRES

0, 8, 16 or 32ms OFF delay

SDA

10..150ms set by

res_timer

in OTP

Start-Up Sequence:

This diagram shows the timing of a I2C or internal initiated reset command followed by a startup (battery and/or USB charger adapter connected, VSUP >

ResVoltRise

)

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AS3701 −

Detailed Description – System Functions

Figure 46:

Start-Up Sequence Diagram 5/5

VSUP > ResVoltRise

8ms

OFF delay

Reg1_addr

(b0:3 fuse aah)

Reg4_addr

(b4:7 fuse adh)

5ms debounce

VSUP >

ResVoltRise

0ms delay (if

Reg1_delay

= 0)

1ms delay (if

Reg1_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg1_delay

= 1 and

del_time

= 1)

reg1_V (b0:7 fuse abh)

0ms delay (if

Reg4_delay

= 0)

1ms delay (if

Reg4_delay

= 1 and

del_time

= 0)

4ms delay (if

Reg4_delay

= 1 and

del_time

= 1)

reg4_V (b0:7 fuse afh)

1ms delay between last timeslot (regulator) and

PWRGood signal going high ext ernal HW reset command

PWRGood

10..150ms set by

res_timer

in O TP

0, 8, 16 or 32ms OFF delay

XRES

Start-Up Sequence:

This diagram shows the timing of an external initiated reset command (forcing XRES to low) followed by a startup (battery and/or USB charger adapter connected, VSUP >

ResVoltRise

)

Reset

XRES is a low active bi-directional pin. An external pull-up to the periphery supply has to be added. During each reset cycle the following states are controlled by the AS3701:

•

Pin XRES is forced to GND

•

Normal startup with programmable power-ON sequence and regulator voltages

•

Reset is active until the programmable reset timer (set by res_timer [ResetTimer]) expires

•

All registers are set to their default values after power-ON, except the reset control- and status-registers.

•

XRES is pulled high by the external resistor and the whole system is leaving the reset state

Note(s):

Programming is controlled by the internal Boot-OTP

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AS3701 −

Detailed Description – System Functions

RESET Reasons

Reset can be activated from the below mentioned different sources:

•

VPOR has been reached (VSUP rising from the scratch)

•

ResVoltFall was reached (VSUP < ResVoltFall [Battery_ voltage_monitor])

•

Software forced reset (

force_reset [ResetControl]

= 1)

•

XRES is pulled to low

•

ON-key long press (on_tast_sw is set to "0")

•

Overtemperature

Voltage Detection

A Reset gets initiated, if VSUP rises from scratch and reaches the

V

POR

level. The pin XRES is only released if VSUP is above

ResVoltRise

.

V

XRES_fall

is only accepted if the reset condition is longer than

V

XRES_mask

. This guard time is used to avoid a complete reset of the system in case of short drops of VSUP.

Figure 47:

Voltage Detection Reset

SupResEn

0

1

power_off_at_vsuplow

= 0

A reset is initiated, if VSUP < 2.7V.

If enabled, an interrupt is executed at

ResVoltFall

.

Automatic restart, if VSUP >

ResVoltRise

.

A reset is initiated, if VSUP <

ResVoltFall

.

Automatic restart, if VSUP >

ResVoltRise

.

Software Forced Reset

Writing “1” into the register bit

force_reset [ResetControl]

immediately starts a reset cycle. The bit

force_reset

is automatically cleared by this reset.

External Triggered Reset

If the pin XRES is pulled from high to low by an external source

(e.g. microprocessor or button) a reset cycle is started as well.

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Figure 48:

ON-Key Long Press RESET Behavior onkey_ lpress_en onkey_ lpress_reset

0

1

X

1

1

1

1

1

on_ lpress_ delay

X

0

on_tast_sw

X

0

1

X

0

1

Long Press Behavior

No ON-key long press reset possible

8s long press on the ON-push-button forces a reset

4s long press on the ON-push- button forces a reset

No reset possible, if ON-key works as a switch

Overtemperature Reset

A reset cycle is getting started, if the overtemperature threshold is reached and the bit

ov_temp_140

[OvertemperatureControl]

is set.

Parameter

Figure 49:

XRES Input Characteristics

Symbol

V

XRES_IL

V

XRES_IH

Parameter

RESET low level voltage

RESET high level voltage

AS3701 −

Detailed Description – System Functions

Long ON-Key Press

For a reset initiated with a long ON-key press, this feature must be enabled by setting the bit

onkey_lpress_en [ResetControl]

to

“1”. When applying a high level on the ON input pin for 4s/8s

(depending on

on_lpress_delay [ReferenceControl]

) a reset gets initiated, if the bit

onkey_lpress_reset [ReferenceControl]

is set to “1”. This is thought as a safety feature when the SW hangs up.

A long ON key reset is just possible, if the ON key works as a push-button (

on_tast_sw [ReferenceControl]

is set to “0”)

Note Min

1.4

Typ Max

0.4

Unit

V

V

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AS3701 −

Detailed Description – System Functions

Figure 50:

Reset Levels

Symbol

V

POR

V

XRES_rise

RESET level for V

SUP

rising

V

XRES_fall

Parameter

Overall power on reset

RESET Level for V

SUP

falling

Note

Monitor on VSUPpower ON reset for all internal functions

Monitor voltage on VSUP rising level

Monitor voltage on

VSUP falling level

Min

1.5

Typ

2.0

ResVolt

Rise

(1)

2.7

Max

2.3

Unit

V

V

V if

SupResEn

= 1 only

ResVolt

Fall

(2)

3

V ms

V

XRES_mask

Mask time for VXRES_fall

Duration for

VBAT < ResVoltFall until a reset cycle is started

(3)

FastResEn

= 0

FastResEn

= 1 64

μ s

Note(s):

1. The selection of the range and level is done via OTP. It´s recommended to set the ResVoltRise level 200mV above the ResVoltFall level to have a hysteresis

2. 2.7V is the default value, other levels can be set via SW

3. XRES signal is debounced with the specific mask time for rising- and falling slope of V

BAT

ams Datasheet

[v1-11] 2016-Dec-14

Stand-By

Stand-by allows shutting down all rails or just a selected number and can be achieved by one of the following cases:

Enter Via GPIO

To enter the Stand-by mode via GPIO command, the following settings have to be done:

•

Enable just these interrupt sources which should lead to leave the stand-by mode

•

Make sure that the specified interrupt is inactive (clear the

Register

[InterruptStatus]

by register reading)

•

Set the

gpioX_mode [GPIOxcontrol]

to input and the

gpioX_iosf [GPIOxcontrol]

should be set to

Stand-by + vselect input

(

gpioX_iosf = 6)

•

Set

RegX_select [Reg_Control]

and

RegX_voltage [RegX_

Voltage]

if another voltage is needed during stand-by for up to 2 regulators

•

Define which regulators should be kept powered during

Stand-by mode (

sdX_stby_on

and

ldoX_stby_on [Reg_ standby_mod1]

)

•

Set the

off_delay [Startup_Control]

for going into stand-by after the GPIO command

•

Activate the selected GPIO

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AS3701 −

Detailed Description – System Functions

Enter Via SW

To enter the Stand-by mode via I²C command, the following settings have to be done:

•

Enable just these interrupt sources which should lead to leave the stand-by mode

•

Make sure that the specified interrupt is inactive (clear the

Register

[InterruptStatus]

by register reading)

•

Define which regulators should be kept powered during

Stand-by mode (

sdX_stby_on

and

ldoX_stby_on [Reg_ standby_mod1]

)

•

Set the

off_delay [Startup_Control]

for going into stand-by after the I²C command

•

Set

standby_mode_on [ReferenceControl]

to 1

During Stand-by all regulators are switched OFF, except those, which are selected either with

RegX_select [Reg_Control]

or with

sdX_stby_on

and

ldoX_stby_on [Reg_standby_mod1]

. XRES goes active (can be disabled with

standby_reset_disable [Sartup_

Control]

) and pwr_good goes inactive. Furthermore, to save power especially in this mode, the internal oscillator is just working, when it is needed.

Leaving Stand-By

Stand-by can be terminated by:

•

Any kind of interrupt (if it was defined right before going into Stand-by)

•

ON-key push-button press (

on_tast_sw

is set to “0”)

•

Reset

•

Power OFF

•

Overtemperature

ams Datasheet

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AS3701 −

Detailed Description – System Functions

Power OFF

During power OFF state all circuits are shut-OFF. Thus the current consumption of AS3701 is reduced to about 1

μ

A. Except the reset control registers, all other registers are set to their default value after power-ON.

The chip stays in power OFF mode until

•

The external pin ON is pulled high

•

The charger is inserted or

•

The VPOR level is touched to start a complete reset cycle.

The AS3701 can be set into Power OFF if one of the following conditions occur:

•

ResVoltFall

was reached (VSUP <

ResVoltFall [Battery_ voltage_monitor]

)

•

Software forced power OFF (

power_off [ResetControl]

= 1)

•

ON-key long press

•

auto_off [Startup_Control]

is enabled (VSUP rising from the scratch)

Voltage Detection

If VSUP falls below

ResVoltFall

for longer than 500ms and the bit

power_off_at_vsuplow [Startup_Control]

is set to “1”, the

PMIC enters the Power Off mode.

Figure 51:

Voltage Detection Power OFF

SupResEn

0

1

power_off_at_vsuplow

= 1

A power-down is initiated, if VSUP < 2.7V.

If enabled, an interrupt is executed at

ResVoltFall

.

Restart only possible with ON key or charger insertion, if VSUP >

ResVoltRise

.

A power-down is initiated, if VSUP <

ResVoltFall

.

Restart only possible with ON key or charger insertion, if VSUP >

ResVoltRise

.

Software Forced Power OFF

To put the chip into power off mode, write ‘1’ into

power_off

[ResetControl]

. In ON-key-switch configuration the AS3701 will startup immediately again, if the switch is in ON position.

The bit

power_off

bit is automatically cleared by a startup and its associated reset cycle.

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Figure 52:

ON-Key Long Press Power OFF Behavior

AS3701 −

Detailed Description – System Functions

Long ON-Key Press

For a power OFF asserted with a long ON-key press, this feature must be enabled by setting the bit

onkey_lpress_en

[ResetControl]

to “1”. When applying a high level on the ON input pin for 4s/8s (depending on

on_lpress_delay [ReferenceControl]

) a power off gets initiated, if the bit

onkey_lpress_reset

[ReferenceControl]

is set to “0”. A long ON key power off is possible, if the ON key works as a push-button or as a switch.

onkey_ lpress_en onkey_lpress_ reset on_reset_ delay on_tast_sw

0 X X X

1

1

1

1

0

0

0

0

0

1

0

1

0

0

1

1

Long Press Behavior

No ON-key long press power OFF is possible

8s long press on the ON-push-button forces a power OFF

(1)

4s long press on the ON-push-button forces a power OFF

(1)

Forces a power OFF after 8s, if

ON-switch is set to OFF position

(2)

Forces a power OFF after 4s, if

ON-switch is set to OFF position

(2)

Note(s):

1. If a USB charger adapter is connected, the ON-key push-button long press would only force a power-off, if the bit chg_pwr_off_en is set to "1"!

2. If a USB charger adapter is connected and the bit chg_pwr_off_en is set to "0" (level detection), the ON-key-switch OFF position has no influence. The PMIC will stay in Activemode as long as the USB adapter is present! If a USB adapter is connected and the bit chg_ pwr_off_en is set to "1" (edge detection), the PMIC can be set into Power-OFF via I²C, if the ON-key switch is also in OFF position!

Auto-OFF

If VSUP is rising from the scratch and the bit

auto_off [Startup_

Control]

is set to “1”, the PMIC enters immediately the

Power-OFF mode right after VSUP reaches the

ResVoltRise

.

If the ON-key is in switch configuration the Auto-OFF feature only works, when the switch is in OFF position during VSUP rising from scratch!

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ams Datasheet

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AS3701 −

Detailed Description – System Functions

Internal References

Description

The internal 2.0V reference and the oscillator are powered either via the VUSB input pin or via the VBAT input pin, depending on which level is higher. The internal oscillator is used for PWM, SD frequency and all timings, which are needed for the charger, the startup sequence and reset delays.

Parameter

Figure 53:

Reference Parameter

Symbol

f

CLK

Parameter Conditions

Accuracy of internal reference clock

Adjustable by serial interface register

clk_int

Min Typ Max Unit

-12 f

CLK

+12 %

Reference Parameter:

Shows the key electrical parameter of the on-chip oscillator

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AS3701 −

Detailed Description – System Functions

GPIO Pins

AS3701A contains 2 GPIO pins and AS3701B offers 5 GPIO pins.

Each of the pins can be configured as digital input, digital input

(with pull-up or pull-down), push-pull output or open drain output (with or without pull-up). When configured as output the output source can be a register bit, or the PWM generator.

Additional the GPIO1 and GPIO2 can be configured as a Current sink and the GPIO3 and GPIO4 (only available in AS3701B) can offer an input to connect a NTC for supervising the battery temperature.

The polarity of the input and output signals can be inverted with the corresponding

gpioX_invert [GPIOXcontrol]

bit, all further descriptions refer to normal (non-inverted) mode.

Figure 54:

GPIO Block Diagram

gpioX_out: 0

Interrupt output: 1

VSUP_low output: 2

Pwr_good output: 7

Charger active output: 10

EOC output: 11

PWM output: 14 gpioX_invert gpioX_in: 0

GPIO Interrupt input: 3

Current sink PWM input: 4 vselect input: 5

Stand-by + vselect input: 6

Charger Current Range1: 8

Charger Current Range2: 9

100/500mA USB current limit: 12

900/1400mA USB current limit: 13

Charger enable input: 15

VSUP gpioX_iosf gpioX_iosf

=1 gpioX_mode = 1

=1

& gpioX_mode = 0, 2, 4, 5 or 6

& gpioX_mode = 1, 2 or 6

& gpio3/4_mode = 3 (NTC) gpioX_out: 0

Interrupt output: 1

VSUP_low output: 2

Pwr_good output: 7

Charger active output: 10

EOC output: 11

PWM output: 14 gpioX_invert gpioX_iosf gpio1/2_mode = 7

=1 gpioX_mode = 4 or 6

300k

300k gpioX_mode = 5 gpio1/2_mode = 7

&

CURR1/2 curr1/2_current

GPIOx

GPIO Block Diagram:

Shows the internal structure of the IO pads

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AS3701 −

Detailed Description – System Functions

Figure 55:

GPIO Pin Characteristics

Symbol Parameter Note

V

GPIO_max

V

V

OL

OH

Max voltage on GPIOx pins

Low level output voltage

High level output voltage

Pin VSUP is used as supply for the GPIO pins

I

OL

=+1mA digital output

I

OH

=–1mA; digital push-pull output

V

IL

Low level input voltage digital input

Min

0.8*VSUP

Typ Max

VSUP + 0.3

+0.4

20% of

VSUP

V

IH

High level input voltage digital input

60% of

VSUP

I

LEAKAGE

Leakage current

R pull-up

Pull-up resistance

R pull-down

Pull-down resistance high impedance if enabled;

VSUP = 3.7V

if enabled;

VSUP = 3.7V

300

300

1

Unit

V

V

V

V

V

μA kΩ kΩ

GPIO Pins:

Shows the key electrical parameter of the GPIO pins. VSUP = 2.7 to 5.5V; unless otherwise mentioned

IO Functions

Normal IO Operation

If set to input, the logic level of the signal present at the GPIOx pin can be read from

gpioX_in [GPIOsignal_in]

. This mode is also used for the ON/OFF control of the DCDC and LDOs. The selection, which regulator is controlled by which GPIO, is done with the

gpio_ctrl_sdX [GPIO_ctrl2]

or

gpio_ctrl_ldoX [GPIO_ ctrl2]

bits.

The

gpioX_mode [GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

gpioX_in

.

If the output mode is chosen,

gpioX_out [GPIOsignal_out]

specifies the logic level of the GPIOx pin.

The

gpioX_mode [GPIOxcontrol]

should be set to output.

The

gpioX_iosf [GPIOxcontrol]

should be set to

gpioX_out

.

For GPIO1 and GPIO2, the logic level of the output signal can be visualized via the Current sinks. In this case the

gpioX_mode

[GPIOxcontrol]

should be set to CURRx.

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AS3701 −

Detailed Description – System Functions

Interrupt Output

GPIOx pin logic state is derived from the interrupt signal XIRQ.

Whenever an interrupt is present the GPIOx pin will be pulled high.

The

gpioX_mode [GPIOxcontrol]

should be set to output.

The

gpioX_iosf [GPIOxcontrol]

should be set to

Interrupt output

.

For GPIO1 and GPIO2, the Interrupt output signal can be visualized via the Current sinks. In this case the

gpioX_mode

[GPIOxcontrol]

should be set to CURRx.

VSUP_low Output

GPIOx pin will go high, if VSUP falls below ResVoltFall and

SupResEn [Battery_voltage_monitor]

= 0.

The

gpioX_mode [GPIOxcontrol]

should be set to output.

The

gpioX_iosf [GPIOxcontrol]

should be set to

VSUP_low output

.

For GPIO1 and GPIO2, the VSUP_low output signal can be visualized via the Current sinks. In this case the

gpioX_mode

[GPIOxcontrol]

should be set to CURRx.

PWRGOOD Output

This signal will go high at the end of the start-up sequence. This can be used as a second reset signal to the processor to e.g. start oscillators.

The

gpioX_mode [GPIOxcontrol]

should be set to output.

The

gpioX_iosf [GPIOxcontrol]

should be set to

Pwr_good output

.

For GPIO1 and GPIO2, the Pwr_good output signal can be visualized via the Current sinks. In this case the

gpioX_mode

[GPIOxcontrol]

should be set to CURRx.

Charger Active Output

When selected, the GPIOx will go high if the charger is active.

The

gpioX_mode [GPIOxcontrol]

should be set to output.

The

gpioX_iosf [GPIOxcontrol]

should be set to

Charger active output

.

For GPIO1 and GPIO2, the Charger active output signal can be visualized via the Current sinks. In this case the

gpioX_mode

[GPIOxcontrol]

should be set to CURRx.

EOC Output

When selected, the GPIOx will go high if the charger has reached the EOC state.

The

gpioX_mode [GPIOxcontrol]

should be set to output.

The

gpioX_iosf [GPIOxcontrol]

should be set to

EOC output

.

For GPIO1 and GPIO2, the EOC output signal can be visualized via the Current sinks. In this case the

gpioX_mode [GPIOxcontrol]

should be set to CURRx.

ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Detailed Description – System Functions

PWM Output

When selected, the GPIOx output provides the PWM signal generated by the internal programmable PWM generator. Its timing is defined by

pwm_h_time [pwm_control_h]

,

pwm_l_ time [pwm_control_l]

and

pwm_div [ReferenceControl]

.

The

gpioX_mode [GPIOxcontrol]

should be set to output.

The

gpioX_iosf [GPIOxcontrol]

should be set to

PWM output

.

For GPIO1 and GPIO2, the PWM output signal can be visualized via the Current sinks. In this case the

gpioX_mode [GPIOxcontrol]

should be set to CURRx.

GPIO Interrupt Input

A falling or rising edge will set the

gpio_int

bit.

The

gpioX_mode [GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

GPIO Interrupt input

.

Current Sink PWM Input

The GPIO is used as PWM input for the current sink to control the current. 100% PMW mode will set the current to the value set in

currX_current [currX_value]

register.

The gpioX_mode

[GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

Current sink PWM input

.

Vselect Input

As long as the GPIOx pin is low the DCDC/LDOs operate with the normal register settings. If the GPIOx pin goes high, the settings will change to the ones stored in

RegX_voltage [RegX_

Voltage]

.

The

gpioX_mode [GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

vselect input

.

GPIO1 and GPIO2 may be used to control two regulators separately.

Figure 56:

GPIO Vselect Modes gpio1_ iosf

≠5

gpio2_ iosf

≠5

5

≠5

5

≠5

5

5

gpio3_ iosf

≠5

gpio4_ iosf

≠5

≠5

≠5

≠5

≠5

≠5

≠5

gpio5_ iosf

≠5

≠5

≠5

≠5

Vselect Mode

No voltage select by GPIO for regulator

GPIO1 controls regulator selected by

reg1_select

and

reg2_select

GPIO2 controls regulator selected by

reg1_select

and

reg2_select

GPIO1 controls regulator selected by

reg1_select

GPIO2 controls regulator selected by

reg2_select

ams Datasheet

[v1-11] 2016-Dec-14

Page 49

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AS3701 −

Detailed Description – System Functions

gpio1_ iosf gpio2_ iosf gpio3_ iosf gpio4_ iosf gpio5_ iosf

Vselect Mode

≠5

≠5

≠5

≠5

≠5

≠5

5

≠5

≠5

≠5

5

≠5

≠5

≠5

5

GPIO3 controls regulator selected by

reg1_select

and

reg2_select

(1)

GPIO4 controls regulator selected by

reg1_select

and

reg2_select

(1)

GPIO5 controls regulator selected by

reg1_select

and

reg2_select

(1)

IO Functions:

Shows the different Vselect control modes, depending on the setting of the GPIO special function 5.

Note(s):

1. AS3701B only

Stand-By and Vselect Input

This mode is very similar to the Vselect mode described in the previous paragraph. The chip is set into stand-by mode when the GPIOx pin goes high and wakes up again when the pin is pulled low and the

gpio_restart_int_m [InterruptMask2]

has been set before going into stand-by. Additional to the stand-by feature, the voltage setting of 2 regulators can be changed with the same command. This requires the setting of the corresponding regulator (

sd1_stby_on

and/or

ldo1_stby_on

and/or

ldo2_stby_on [Reg_standby_mod1]

).

The

gpioX_mode [GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

Stand-by + vselect input

.

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ams Datasheet

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AS3701 −

Detailed Description – System Functions

Figure 57:

Stand-By and Vselect Modes gpio1

_iosf

≠6

gpio2

_iosf

≠6

6

≠6

≠6

≠6

≠6

≠6

6

≠6

≠6

≠6

gpio3

_iosf

≠6

gpio4

_iosf

≠6

≠6

≠6

6

≠6

≠6

≠6

≠6

≠6

6

≠6

gpio5

_iosf

≠6

≠6

≠6

≠6

≠6

6

Vselect Mode

No voltage select by GPIO for regulator

GPIO1 controls regulator selected by

reg1_select

and

reg2_select

GPIO2 controls regulator selected by

reg1_select

and

reg2_select

GPIO3 controls regulator selected by

reg1_select

and

reg2_select

(1)

GPIO4 controls regulator selected by

reg1_select

and

reg2_select

(1)

GPIO5 controls regulator selected by

reg1_select

and

reg2_select

(1)

Stand-By

Control

No

Yes

Yes

Yes

Yes

Yes

IO Functions:

Shows the different Vselect and stand-by control modes, depending on the setting of the GPIO special function 6.

Note(s):

1. AS3701B only

Charger Current Range 1

With this function the charging current (trickle current and constant current) can be set to 11mA(trickle) +

133mA(constant) or 22mA(trickle) + 223mA(constant).

The gpioX_mode

[GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

Charger Current

Range1

.

Charger Current Range 2

With this function the charging current (trickle current and constant current) can be set to 33mA(trickle) +

357mA(constant) or 45mA(trickle) + 493mA(constant).

The gpioX_mode

[GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

Charger Current

Range2

.

100/500mA Charger Input

With this function the charger input current limiter can be set to 100mA or 500mA.

The gpioX_mode

[GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

100/500mA USB current limit

.

ams Datasheet

[v1-11] 2016-Dec-14

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Figure 58:

Overtemperature Protection

Symbol

T

110

T

140

T

HYST

Parameter

ov_temp_110 rising threshold ov_temp_140 rising threshold ov_temp_110 and ov_temp_140 hysteresis

AS3701 −

Detailed Description – System Functions

800/1100mA Charger Input

With this function the charger input current limiter can be set to 800mA or 1100mA.

The gpioX_mode

[GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

800/1100mA USB current limit

.

Charging Enable Input

When pulling the GPIO to high the charger is being enabled and vice versa. This is to enable the charger without I²C communication.

The gpioX_mode

[GPIOxcontrol]

should be set to input.

The

gpioX_iosf [GPIOxcontrol]

should be set to

Charger enable input

.

Supervisor

The Step Down DCDC Converter has an integrated overcurrent protection. An overtemperature protection of the chip is also integrated which can be switched ON with the serial interface signal

temp_pmc_on [OvertemperatureControl]

(enabled by default; it is not recommended to disable the overtemperature protection).

Temperature Supervision

The chip has two signals for the serial interface:

ov_temp_110

and

ov_temp_140 [OvertemperatureControl]

.

The flag

ov_temp_110

is automatically reset if the overtemperature condition is removed, whereas

ov_temp_140

has to be reset by the serial interface with the signal

rst_ov_ temp_140 [OvertemperatureControl]

. If the flag

ov_temp_140

is set, an automatic reset of the complete chip is initiated. The chip will only start-up when the temperature falls below the

T110 level (including hysteresis). The flag

ov_temp_140

is not affected by this reset cycle allowing the software to detect the reason for this unexpected shutdown.

Note Min

95

Typ

110

Max

125

Unit

°C

125 155 140

5

°C

°C

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ams Datasheet

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AS3701 −

Detailed Description – System Functions

Interrupt Generation

The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the

InterruptMask registers are set by pulling low the pin XIRQ. All the interrupt sources can be enabled in the Interrupt Mask registers. If an interrupt occurs, the Interrupt Status registers get set and cleared automatically after the host controller has read them.

To prevent the AS3701 device from losing an interrupt event, the register that is read is captured before it is transmitted to the host controller via the serial interface. As soon as the transmission of the captured value is completed, a logical AND operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already been transmitted. Clearing the read interrupt bits takes 2 clock cycles, a read access to the same register, before the clearing process has completed, will yield a value of ‘0’. Note that an interrupt that has been present at the previous read access will be cleared as well in case it occurs again before the clearing process has completed.

Wire-Serial Control Interface

Feature List

•

Fast-mode capability (max. SCL-frequency is 400 kHz)

•

7+1-bit addressing mode

•

60h x 8-bit data registers (word address 0x00 - 0x60)

•

Write formats: Single-Byte-Write, Page-Write

•

Read formats: Current-Address-Read, Random-Read,

Sequential-Read

•

SDA input delay and SCL spike filtering by integrated

RC-components

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[v1-11] 2016-Dec-14

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AS3701 −

Detailed Description – System Functions

I²C Protocol

Figure 59:

I²C Symbol Definition

Symbol

S

Sr

DW

DR

WA

A

N reg_data data (n)

P

WA++

Definition

Start condition after Stop

Repeated Start

Device address for Write

Device address for Read

Word address

Acknowledge

No Acknowledge

Register data/write

Register data/read

Stop condition

Increment word address internally

RW

R

R

R

W

R

R

R

R

W

R

R

Note

1 bit

1 bit

1000 0000b (80h)

1000 0001b (81h)

8 bit

1 bit

1 bit

8 bit

8 bit

1 bit

During acknowledge

I²C Write Access

Byte Write and Page Write formats are used to write data to the slave.

Figure 60:

I²C Byte Write

S DW A WA A reg_data A P write register

WA++

Figure 61:

I²C Page Write

S DW A WA A reg_data 1 A reg_data 2 A write register

WA++ write register

WA++

...

reg_data n A P write register

WA++

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Detailed Description – System Functions

The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations.

For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated

START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally.

I²C Read Access

Random, Sequential and Current Address Read are used to read data from the slave.

Figure 62:

I²C Random Read

S DW A WA A Sr DR A data N P read register

WA++

Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master.

The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address.

In order to change the data direction a repeated START condition is issued on the 1 st

SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.

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AS3701 −

Detailed Description – System Functions

Figure 63:

I²C Sequential Read

S DW A WA A Sr DR A data A reg_data 2 A read register

WA++ read register

WA++ read register

WA++

...

reg_data n N P

Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.

Figure 64:

I²C Current Address Read

S DR A data A reg_data 2 A read register

WA++ read register

WA++ read register

WA++

...

reg_data n N P

Figure 65:

I²C Characteristics

Symbol

V

IL

V

IH

Parameter

SCL,SDA Low Level input voltage

SCL,SDA High Level input voltage

To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to

Random Read, a single byte transfer is terminated with a not-acknowledge after the 1 st

register byte. Analogous to

Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition.

I²C Parameter

Condition Min Typ Max Unit

1.6

0.4

V

V

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ams Datasheet

[v1-11] 2016-Dec-14

A S 3 7 0 1 −

Register Description

Register Description

Figure 66:

Register Overview

Addr

24h

25h

26h

20h

21h

22h

23h

0ah

0bh

0ch

0dh

01h

02h

03h

09h

30h

Name

SD1Voltage

LDO1Voltage

LDO2Voltage

GPIO1control

GPIO2control

GPIO3control

GPIO4control

GPIO5control

GPIOsignal_out

GPIOsignal_in

Reg1_Voltage

Reg2_Voltage

Reg_Control

GPIO_ctrl1

GPIO_ctrl2

SD_control1

D7 D6 D5 D4 D3 D2 D1 D0

sd1_frequ ldo1_on ldo2_on gpio1_invert gpio2_invert gpio3_invert gpio4_invert gpio5_invert

-

-

-

ldo1_ilimit ldo2_ilimit

-

sd1_vsel<6:0> ldo1_vsel<5:0> ldo2_vsel<5:0> gpio1_mode<6:4> gpio2_mode<6:4> gpio3_mode<6:4> gpio4_mode<6:4> gpio5_mode<6:4> gpio1_iosf<3:0> gpio2_iosf<3:0> gpio3_iosf<3:0> gpio4_iosf<3:0> gpio5_out gpio5_in gpio4_out gpio4_in

Reg1_voltage<6:0>

Reg2_voltage<6:0>

Reg2_select<5:4> gpio_ctrl_ldo2<6:4> gpio5_iosf<3:0> gpio3_out gpio2_out gpio3_in gpio2_in gpio1_out gpio1_in

Reg1_select<1:0> gpio_ctrl_ldo1<2:0>

-  gpio_ctrl_sd1<2:0> sd1_enable sd1_low_ noise sd1_fast sd1_fsel dvm_enable dvm_time

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A S 3 7 0 1 −

Register Description

41h

42h

43h

44h

73h

Addr

32h

33h

35h

36h

37h

39h

74h

75h

77h

78h

Name D7 D6 D5 D4 D3 D2 D1 D0

Battery_voltage_ monitor

FastResEn SupResEn ResVoltFall<5:3> ResVoltRise<2:0>

Startup_control

ReferenceControl

ResetControl

Overtemperature

Control

Reg_standby_ mod1 pwm_control_l pwm_control_h curr1_value curr2_value

RegStatus

InterruptMask1

InterruptMask2

InterruptStatus1

InterruptStatus2 chg_pwr_off_ en on_lpress_ delay tco_140_a

 -

LowBat_int_ m gpio5_int_m

LowBat_int_i gpio5_int_i power_off_ at_vsuplow on_tast_sw stby_reset_ disable onkey_ lpress_reset auto_off standby_ mode_on off_delay<3:2> clk_int<3:2> res_timer<1:0> pwm_div<1:0> reset_reason<7:4> tco_110_a

temp_test<5:4> onkey_ lpress_en rst_ov_temp_

140 on_input power_off ov_temp_140 ov_temp_110 disable_ regpd pwm_l_time<7:0> pwm_h_time<7:0> curr1_current<7:0> curr2_current<7:0> sd1_stby_on ldo2_stby_on force_reset temp_pmc_ on ldo1_stby_on curr2_lv curr1_lv  sd1_lv ovtmp_int_m gpio4_int_m ovtmp_int_i gpio4_int_i onkey_int_m gpio3_int_m onkey_int_i gpio3_int_i chdet_int_m gpio2_int_m chdet_int_i gpio2_int_i eoc_int_m gpio1_int_m eoc_int_i gpio1_int_i resume_int_ m gpio_restart_ int_m resume_int_i gpio_restart_ int_i nobat_int_m sd1_lv_int_m nobat_int_i sd1_lv_int_i trickle_int_m bat_temp_m trickle_int_i bat_temp_i

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ams Datasheet

[v1-11] 2016-Dec-14

A S 3 7 0 1 −

Register Description

86h

87h

8eh

90h

91h

Addr

80h

81h

82h

83h

84h

85h a5h a6h

Name

ChargerControl

D7

cc_range_ select

D6

AutoResume

D5

bat_ charging_ enable

D4

usb_chgEn

D3 D2 D1

usb_current<3:0>

D0

ChargerVoltageC ontrol

ChargerCurrentCo ntrol

ChargerConfig1

ChargerConfig2

Vsup_min<7:6> -

Charging_

1Hz_clk

TrickleCurrent<7:4>

ChVoltResum e eoc_current<7:5> temp_sel<5:4> charging_ tmax

Chargersupervisio n

ChargerStatus1

ChargerStatus2

LockRegister

ASIC_ID1

ASIC_ID2

Fuse5

  ntc_high_on

NoBat del_time

  ntc_low_on

-  sequ_on

 

-

 ntc_10k temp_cond<6:5> ntc_mode

EOC

-

CVM chdet_off

-

ID1<7:0>

  

 

ChVoltEOC<4:0>

ContantCurrent<3:0> vsup_voltage<3:1>

NTC_input<3:2> ch_timeout<3:0>

Trickle

ChDet charger_lock revision<3:0> ntc_beta<1:0>

Resume

-

CCM batsw_mode<1:0> reg_lock<1:0>

Fuse6

 

 

  on_tast_sw onkey_ lpress_reset on_invert

 

ams Datasheet

[v1-11] 2016-Dec-14

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Addr

a7h a8h a9h aah abh ach adh aeh afh

Name

Fuse7

 

Fuse8

 

Fuse9

 

Fuse10

 

Fuse11

 

Fuse12

 

Fuse13

 

Fuse14

 

Fuse15

 

Page 60

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A S 3 7 0 1 −

Register Description

D7

auto_off

 

D6

chg_pwr_off_ en

 

D5

usb_current<7:4> res_timer<5:4>

 

D4

Reg4_del

 

Reg3_del Reg2_del

 

Reg2_addr<7:4>

 

Reg1_del

 

D3 D2 D1 D0

sd1_fsel

 

 

SupResEn sd1_fast

 

ResVoltRise<3:1> power_off_ at_vsuplow

  i2c_deva_ bit1

  on_lpress_ delay

  onkey_ lpress_en

 

Reg1_addr<3:0>

 

NTC_input<1:0>

  reg1_V<7:0> reg2_V<7:0>

Reg4_addr<7:4> Reg3_addr<3:0> reg3_V<7:0> reg4_V<7:0>

ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Register Description

Detailed Register Description

Figure 67:

SD1Voltage

Addr:01h SD1Voltage

Bit Bit Name Default Access

7

6:0 sd1_frequ sd1_vsel b0 b0000000

RW

RW

Bit Description

Selects between high and low frequency

0 : 1 MHz if sd1_fsel=0, 2MHz if sd1_fsel=1

1 : 3 MHz if sd1_fsel=0, 4MHz if sd1_fsel=1

The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down.

00h : DC/DC powered down

01h-40h : V_SD1=0.6V+sd1_vsel*12.5mV

41h-70h : V_SD1=1.4V+(sd1_vsel-40h)*25mV

71h-7Fh : V_SD1=2.6V+(sd1_vsel-70h)*50mV

Figure 68:

LDO1Voltage

Bit

Addr:02h

Bit Name

7

6

5:0 ldo1_on ldo1_ilimit ldo1_vsel

LDO1Voltage

Default Access

b0 b0 b000000

RW

RW

RW

Bit Description

Switch ON of LDO1

0 : LDO OFF

1 : LDO ON

Sets current limit of LDO1

0 : 100mA operating range

1 : 200mA operating range

The voltage select bits set the LDO output voltage

00h-2Ah : V_LDO1=1.2V+ldo1_vsel*50mV

2Bh-3Fh : Do not use

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AS3701 −

Register Description

Figure 69:

LDO2Voltage

Addr:03h LDO2Voltage

Bit Bit Name Default Access

7

6

5:0 ldo2_on ldo2_ilimit ldo2_vsel b0 b0 b000000

RW

RW

RW

Bit Description

Switch ON of LDO2

0 : LDO OFF

1 : LDO ON

Sets current limit of LDO2

0 : 100mA operating range

1 : 200mA operating range

The voltage select bits set the LDO output voltage

00h-2Ah : V_LDO2=1.2V+ldo2_vsel*50mV

2Bh-3Fh : Do not use

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Register Description

Figure 70:

GPIO1control

Addr:09h GPIO1control

Bit Bit Name Default Access

7

3:0 gpio1_invert

6:4 gpio1_mode gpio1_iosf b0 b011 b0000

RW

RW

RW

Bit Description

Invert GPIO1 input/output

0 : Normal Mode

1 : Invert input or output

Selects the GPIO1 mode (I, I/O, Tri, Pulls)

0 : Input

1 : Output (push and pull)

2 : IO(open drain, only NMOS is active)

3 : Input (tristate)

4 : Input with pullup

5 : Input with pulldown

6 : IO(open drain(NMOS)with pullup)

7 : CURR1

Selects the GPIO1 special function

0 : Normal I/O operation

1 : Interrupt output

2 : VSUP_low output

3 : GPIO interrupt input

4 : Current sink PWM input

5 : Vselect input, (apply on reg1_select and reg2_select, if gpio2_iosf=5 then apply on reg1_select only)

6 : standby+Vselect+restart interrupt input

7 : pwr_good output

8 : 11mA(TrickleCurrent=0), 133mA(ConstantCurrent=2) /

23mA(TrickleCurrent=1), 223mA(ConstantCurrent=4)

9 : 35mA(TrickleCurrent=2), 358mA(ConstantCurrent=7) /

47mA(TrickleCurrent=3), 494mA(ConstantCurrent=10)

10 : Charger active output

11 : EOC output

12 : 100mA(usb_Current=0) / 500mA(usb_Current=8)

13 : 800mA(usb_Current=11) / 1100mA(usb_Current=13)

14 : PWM output

15 : Charger enable input

ams Datasheet

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AS3701 −

Register Description

Figure 71:

GPIO2control

Bit

7

Addr:0ah

Bit Name

6:4 gpio2_mode

3:0 gpio2_invert gpio2_iosf

GPIO2control

Default Access

b0 b011 b0000

RW

RW

RW

Bit Description

Invert GPIO2 input/output

0 : Normal Mode

1 : Invert input or output

Selects the GPIO2 mode (I, I/O, Tri, Pulls)

0 : Input

1 : Output (push and pull)

2 : IO(open drain, only NMOS is active)

3 : Input (tristate)

4 : Input with pullup

5 : Input with pulldown

6 : IO(open drain(NMOS)with pullup)

7 : CURR2

Selects the GPIO2 special function

0 : Normal I/O operation

1 : Interrupt output

2 : VSUP_low output

3 : GPIO interrupt input

4 : Current sink PWM input

5 : Vselect input, (apply on reg1_select and reg2_select, if gpio1_iosf=5 then apply on reg2_select only)

6 : standby+Vselect+restart interrupt input

7 : pwr_good output

8 : 11mA(TrickleCurrent=0), 133mA(ConstantCurrent=2) /

23mA(TrickleCurrent=1), 223mA(ConstantCurrent=4)

9 : 35mA(TrickleCurrent=2), 358mA(ConstantCurrent=7) /

47mA(TrickleCurrent=3), 494mA(ConstantCurrent=10)

10 : Charger active output

11 : EOC output

12 : 100mA(usb_Current=0) / 500mA(usb_Current=8)

13 : 800mA(usb_Current=11) / 1100mA(usb_Current=13)

14 : PWM output

15 : Charger enable input

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AS3701 −

Register Description

Figure 72:

GPIO3control

Bit

7

6:4

3:0

Addr:0bh

Bit Name

gpio3_invert gpio3_mode gpio3_iosf

GPIO3control

Default Access

b0 b011 b0000

RW

RW

RW

Bit Description

Invert GPIO3 input/output

0 : Normal Mode

1 : Invert input or output

Selects the GPIO3 mode (I, I/O, Tri, Pulls)

0 : Input

1 : Output (push and pull)

2 : IO(open drain, only NMOS is active)

3 : NTC input (tristate)

4 : Input with pullup

5 : Input with pulldown

6 : IO(open drain(NMOS)with pullup)

7 : NA

Selects the GPIO3 special function

0 : Normal I/O operation

1 : Interrupt output

2 : VSUP_low output

3 : GPIO interrupt input

4 : Current sink PWM input

5 : Vselect input, (apply on reg1_select and reg2_select)

6 : standby+Vselect+restart interrupt input

7 : pwr_good output

8 : 11mA(TrickleCurrent=0), 133mA(ConstantCurrent=2) /

23mA(TrickleCurrent=1), 223mA(ConstantCurrent=4)

9 : 35mA(TrickleCurrent=2), 358mA(ConstantCurrent=7) /

47mA(TrickleCurrent=3), 494mA(ConstantCurrent=10)

10 : Charger active output

11 : EOC output

12 : 100mA(usb_Current=0) / 500mA(usb_Current=8)

13 : 800mA(usb_Current=11) / 1100mA(usb_Current=13)

14 : PWM output

15 : Charger enable input

ams Datasheet

[v1-11] 2016-Dec-14

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Register Description

Figure 73:

GPIO4control

Bit

7

6:4 gpio4_mode

3:0

Addr:0ch

Bit Name

gpio4_invert gpio4_iosf

GPIO4control

Default Access

b0 b011 b0000

RW

RW

RW

Bit Description

Invert GPIO4 input/output

0 : Normal Mode

1 : Invert input or output

Selects the GPIO4 mode (I, I/O, Tri, Pulls)

0 : Input

1 : Output (push and pull)

2 : IO(open drain, only NMOS is active)

3 : NTC input (tristate)

4 : Input with pullup

5 : Input with pulldown

6 : IO(open drain(NMOS)with pullup)

7 : NA

Selects the GPIO4 special function

0 : Normal I/O operation

1 : Interrupt output

2 : VSUP_low output

3 : GPIO interrupt input

4 : Current sink PWM input

5 : Vselect input, (apply on reg1_select and reg2_select)

6 : standby+Vselect+restart interrupt input

7 : pwr_good output

8 : 11mA(TrickleCurrent=0), 133mA(ConstantCurrent=2) /

23mA(TrickleCurrent=1), 223mA(ConstantCurrent=4)

9 : 35mA(TrickleCurrent=2), 358mA(ConstantCurrent=7) /

47mA(TrickleCurrent=3), 494mA(ConstantCurrent=10)

10 : Charger active output

11 : EOC output

12 : 100mA(usb_Current=0) / 500mA(usb_Current=8)

13 : 800mA(usb_Current=11) / 1100mA(usb_Current=13)

14 : PWM output

15 : Charger enable input

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AS3701 −

Register Description

Figure 74:

GPIO5control

Bit

7

6:4 gpio5_mode

3:0

Addr:0dh

Bit Name

gpio5_invert gpio5_iosf

GPIO5control

Default Access

b0 b011 b0000

RW

RW

RW

Bit Description

Invert GPIO5 input/output

0 : Normal Mode

1 : Invert input or output

Selects the GPIO5 mode (I, I/O, Tri, Pulls)

0 : Input

1 : Output (push and pull)

2 : IO(open drain, only NMOS is active)

3 : Input (tristate)

4 : Input with pullup

5 : Input with pulldown

6 : IO(open drain(NMOS)with pullup)

7 : NA

Selects the GPIO5 special function

0 : Normal I/O operation

1 : Interrupt output

2 : VSUP_low output

3 : GPIO interrupt input

4 : Current sink PWM input

5 : Vselect input, (apply on reg1_select and reg2_select)

6 : standby+Vselect+restart interrupt input

7 : pwr_good output

8 : 11mA(TrickleCurrent=0), 133mA(ConstantCurrent=2) /

23mA(TrickleCurrent=1), 223mA(ConstantCurrent=4)

9 : 35mA(TrickleCurrent=2), 358mA(ConstantCurrent=7) /

47mA(TrickleCurrent=3), 494mA(ConstantCurrent=10)

10 : Charger active output

11 : EOC output

12 : 100mA(usb_Current=0) / 500mA(usb_Current=8)

13 : 800mA(usb_Current=11) / 1100mA(usb_Current=13)

14 : PWM output

15 : Charger enable input

ams Datasheet

[v1-11] 2016-Dec-14

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Register Description

Figure 75:

GPIOsignal_out

Addr:20h

Bit Bit Name

4 gpio5_out

3

2

1

0 gpio4_out gpio3_out gpio2_out gpio1_out

GPIOsignal_out

Default Access

b0 b0 b0 b0 b0

RW

RW

RW

RW

RW

Bit Description

This bit determines the output signal of the GPIO5 pin when selected as output source.

This bit determines the output signal of the GPIO4 pin when selected as output source.

This bit determines the output signal of the GPIO3 pin when selected as output source.

This bit determines the output signal of the GPIO2 pin when selected as output source.

This bit determines the output signal of the GPIO1 pin when selected as output source.

Figure 76:

GPIOsignal_in

Bit

Addr:21h

Bit Name

4 gpio5_in

3

2

1

0 gpio4_in gpio3_in gpio2_in gpio1_in

GPIOsignal_in

Default Access

b0 b0 b0 b0 b0

RO

RO

RO

RO

RO

Bit Description

This bit reflects the logic level of the GPIO5 pin when configured as digital input pin.

This bit reflects the logic level of the GPIO4 pin when configured as digital input pin.

This bit reflects the logic level of the GPIO3 pin when configured as digital input pin.

This bit reflects the logic level of the GPIO2 pin when configured as digital input pin.

This bit reflects the logic level of the GPIO1 pin when configured as digital input pin.

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Register Description

Figure 77:

Reg1_Voltage

Addr:22h Reg1_Voltage

Bit Bit Name Default Access

6:0 Reg1_voltage b0000000 RW

Bit Description

This register is mapped to the register address 0h+Reg1_ select , if gioX_iosf=5 or 6 (Vselect input), and input = 1.

This feature allows voltage switching of a predefined regulator with just one GPIO input

0 ..7Fh: Selects voltage and ilimit of LDO or DCDC

Figure 78:

Reg2_Voltage

Addr:23h Reg2_Voltage

Bit Bit Name Default Access

6:0 Reg2_voltage b0000000 RW

Bit Description

This register is mapped to the register address 0h+Reg1_ select , if gioX_iosf=5 or 6 (Vselect input), and input = 1.

This feature allows voltage switching of a predefined regulator with just one GPIO input

0 ..7Fh: Selects voltage and ilimit of LDO or DCDC

Figure 79:

Reg_Control

Bit

Addr:24h

Bit Name

5:4 Reg2_select

1:0 Reg1_select

Reg_Control

Default Access

b0000 b0000

RW

RW

Bit Description

Select regulator for mapping of Reg2_voltage;

0 : NA

1 : Select 01h SD1Voltage

2 : Select 02h LDO1Voltage

3 : Select 03h LDO2Voltage

Select regulator for mapping of Reg1_voltage;

0 : NA

1 : Select 01h SD1Voltage

2 : Select 02h LDO1Voltage

3 : Select 03h LDO2Voltage

ams Datasheet

[v1-11] 2016-Dec-14

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Register Description

Figure 80:

GPIO_ctrl1

Bit

Addr:25h

Bit Name

6:4 gpio_ctrl_ldo2

2:0 gpio_ctrl_ldo1

GPIO_ctrl1

Default Access

b000 b000

RW

RW

Bit Description

0 : No GPIO control

1 : Controlled by GPIO1

2 : Controlled by GPIO2

3 : Controlled by GPIO3

4 : Controlled by GPIO4

5 : Controlled by GPIO5

6 : NA

7 : NA

0 : No GPIO control

1 : Controlled by GPIO1

2 : Controlled by GPIO2

3 : Controlled by GPIO3

4 : Controlled by GPIO4

5 : Controlled by GPIO5

6 : NA

7 : NA

Figure 81:

GPIO_ctrl2

Bit

Addr:26h

Bit Name

2:0 gpio_ctrl_sd1

GPIO_ctrl2

Default Access

b000 RW

Bit Description

0 : No GPIO control

1 : Controlled by GPIO1

2 : Controlled by GPIO2

3 : Controlled by GPIO3

4 : Controlled by GPIO4

5 : Controlled by GPIO5

6 : NA

7 : NA

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Register Description

Figure 82:

SD_control1

Bit

7

6

5

4

1

0

Addr:30h

Bit Name

sd1_enable sd1_low_ noise sd1_fast sd1_fsel dvm_enable dvm_time

SD_control1

Default Access

b1 b0 b0 b0 b0 b0

RW

RW

RW_SM

RW_SM

RW

RW

Bit Description

Global stepdown SD1 enable

0 : SD1 disabled

1 : SD1 enabled

Enables low noise mode of SD1. If enabled smaller current pulses and output ripple is activated

0 : Normal mode. Minimum current pulses of >100mA applied in skip mode

1 : Low noise mode. Only minimum on time applied in skip mode

Selects a faster regulation mode for SD1 suitable for larger load changes.

0 : Normal mode, Cext=10

μ

F

1 : Fast mode, Cext=22

μ

F required

Selects between high and low frequency range

0 : 1 MHz if sd1_frequ=0, 3MHz if sd1_frequ=1

1 : 2 MHz if sd1_frequ=0, 4MHz if sd1_frequ=1

Enabling of Dynamic Voltage Management

If voltage of SD1 is changed during operation (sd1_vsel) voltage is de/increased by single steps

0 : DVM disabled

1 : DVM enabled

Time steps of DVM voltage change of SD1

0 : 8

μ sec time delay between steps

1 : 16

μ sec time delay between steps

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Register Description

Figure 83:

Battery_voltage_monitor

Bit

Addr:32h

Bit Name

7 FastResEn

6

5:3

SupResEn

ResVoltFall

2:0 ResVoltRise

Battery_voltage_monitor

Default Access

b0 b0 b000 b001

RW

RW_SM

RW_SM

RO

Bit Description

0 : Vresetfall debounce time = 3msec

1 : Vresetfall debounce time = 64

μ sec

0 : A reset is generated if VSUP falls below 2.7V

(1)

1 : A reset is generated if VSUP falls below ResVoltFall

This value determines the reset level ResVoltFall for falling VBAT.

It is recommended to set this value at least 200mV lower than ResVoltRise

0 : 2.7V

1 : 2.9V

2 : 3.1V

3 : 3.2V

4 : 3.3V

5 : 3.4V

6 : 3.5V

7 : 3.6V

This value determines the reset level ResVoltRise for rising VBAT.

It is recommended to set this value at least 200mV higher than ResVoltFall

0 : 2.7V

1 : 2.9V

2 : 3.1V

3 : 3.2V

4 : 3.3V

5 : 3.4V

6 : 3.5V

7 : 3.6V

Note(s):

1. If VBAT falls below ResVoltFall only an interrupt is generated (if enabled) and the uProcessor can shut down the system.

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Register Description

Figure 84:

Startup_Control

Addr:33h Startup_Control

Bit

7

6

5

4

3:2

1:0

Bit Name

chg_pwr_off_ en power_off_at_ vsuplow stby_reset_ disable auto_off off_delay res_timer

Default Access

b0 b0 b0 b0 b01 b00

RO

RW_SM

RW

RO

RW

RW_SM

Bit Description

Select charger detection in power OFF mode

Read only (OTP setting)

0 : Exit of Power OFF mode, if charger is detected (level detection)

1 : Exit of Power OFF mode, if charger insertion is detected

(rising edge detection)

Switch into Power OFF mode if low VSUP is detected during active or standby mode

(Pin ON = low and bit

auto_off

= 0)

0 : If low VSUP(

ResVoltFall

) is detected, enter VSUP

Debounce state, continuously monitor VSUP voltage and startup if VSUP voltage is above

ResVoltRise

1 : If low VSUP(

ResVoltFall

) is detected, enter power OFF mode

Disable Reset output signal (PIN XRES) in standby mode

0 : Normal mode, reset is active in standby mode

1 : No reset in standby mode and during exit of standby mode

Defines startup behavior at first battery insertion

0 : Startup of chip if VBAT>ResVoltRise

1 : Enter power OFF mode (Startup with ON key or charger insertion)

Set Delay between I²C command, GPIO or Reset signal for power_off, standby mode or reset and execution of that command

0 : No delay

1 : 8 ms (default)

2 : 16 ms

3 : 32 ms

Set RESTime, after the last regulator has started

0 : RESTIME=10ms (default)

1 : RESTIME=50ms

2 : RESTIME=100ms

3 : RESTIME=150ms

ams Datasheet

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Register Description

Figure 85:

ReferenceControl

Bit

7

6

5

4

3:2

1:0

Addr:35h

Bit Name

on_lpress_ delay on_tast_sw onkey_lpress_ reset standby_ mode_on clk_int pwm_div

ReferenceControl

Default Access

b0 b0 b0 b0 b00 b00

RW_SM

RO

RW_SM

RW_SM

R_PUSH

RW

Bit Description

Sets the ON reset delay time

0 : 8s (if onkey_lpress_en=1)

1 : 4s (if onkey_lpress_en=1)

Selects mode of ON input

0 : ON key works as push-button

1 : ON key works as switch

Selects behavior for ONKEY longpress

0 : Long onkey press forces change to power_off mode

(if on_tast_sw=0 and onkey_lpress_en=1)

1 : Long onkey press forces a reset

(if on_tast_sw=0 and onkey_lpress_en=1)

Setting to 1 sets the PMU into standby mode.

All regulators are disabled except those regulators enabled by Reg_standby_mod.

XRES will be pulled to low. A normal startup of all regulators will be done with any interrupt

(has to be enabled before entering standby mode).

Sets the internal CLK frequency fCLK used for DCDCs,

PWM, ...

0 : 4 MHz (default)

1 : 3.8 MHz

2 : 3.6 MHz

3 : 3.4 MHz

All frequencies, timings and delays in this datasheet are based on 4MHz clk_int

This bit defines the divider ratio of the prescaler for the

PWM generator

0 : Divide by 1

1 : Divide by 2

2 : Divide by 4

3 : Divide by 16

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AS3701 −

Register Description

Figure 86:

ResetControl

Bit

7:4

3

2

1

0

Addr:36h

Bit Name

reset_reason onkey_lpress_ en on_input power_off force_reset

ResetControl

Default Access

b0000 b0 b0 b0 b0

RW_SM

RW_SM

R_PUSH

RW_SM

RW

Bit Description

Flags to indicate to the software the reason for the last reset

0 : VPOR has been reached (battery or charger insertion from scratch)

1 : ResVoltFall was reached (battery voltage drop below

2.75V)

2 : Software forced by force_reset

3 : Software forced by power_off and ON was pulled high

4 : Software forced by power_off and charger was detected

5 : External triggered through the pin XRES

6 : Reset caused by overtemperature T140

7 : NA

8 : Reset caused by 4/8 seconds ON key press

9 : NA

10 : NA

11 : Reset caused by interrupt in standby mode

12 : Reset caused by ON pulled high in standby mode

0 : ONKEY longpress feature disabled

1 : ONKEY longpress feature enabled

Read:This flag represents the state of the ON pad directly

Write: Setting to 1 resets the 4/8s. Onkey longpress timer

Setting to 1 starts a reset cycle, but waits after the Reg_off state for a falling edge on the pin ON or until the charger is detected

Setting to 1 starts a complete reset cycle

ams Datasheet

[v1-11] 2016-Dec-14

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Register Description

Figure 87:

OvertemperatureControl

Addr:37h OvertemperatureControl

Bit

7

6

5:4

3

2

1

0

Bit Name

tco_140_a tco_110_a temp_test rst_ov_temp_140 ov_temp_140 ov_temp_110 temp_pmc_on

Default Access

b0 b0 b00

RO

RO

RW b0 b0 b0 b1

RW

RO

RO

RW

Bit Description

Only used for production test

Only used for production test

 

If the overtemperature threshold 2 has been reached, the flag ov_temp_140 is set and a reset cycle is started.

ov_temp_140 should be reset by writing 1 and afterwards 0 to rst_ov_temp_140

Flag that the overtemperature threshold 2 (T140) has been reached - this flag is not reset by a overtemperature caused reset and has to be reset by rst_ov_temp_140

Flag that the overtemperature threshold 1 (T110) has been reached

Switch ON/OFF of temperature supervision; default: ON - all other bits are only valid if set to 1

Leave at 1, do not disable

Figure 88:

Reg_standby_mod1

2

1

0

Bit

3

Addr:39h

Bit Name

disable_regpd sd1_stby_on ldo2_stby_on ldo1_stby_on

Reg_standby_mod1

Default Access

b0 b0 b0 b0

RW

RW

RW

RW

Bit Description

This bit disables the pulldown of all regulators

0 : Normal operation approx. 1kohm pulldown of all regulators

1 : Pulldown disabled >100kohm of all regulators

Enable Step down 1 in standby mode

Enable LDO2 in standby mode

Enable LDO1 in standby mode

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Register Description

Figure 89: pwm_control_l

Bit

7:0

Addr:41h

Bit Name

pwm_l_time

pwm_control_l

Default Access

b00000000 RW

Bit Description

This bit defines the low time of the pwm generator in

1MHz units

0 : pwm_div * 1

μ s

1 : pwm_div * 2

μ s

2 : pwm_div * 3

μ s

... : ...

255 : pwm_div * 256

μ s

Figure 90: pwm_control_h

Bit

Addr:42h

Bit Name Default

7:0 pwm_h_time b00000000

pwm_control_h

Access

RW

Bit Description

This bit defines the high time of the pwm generator in

1MHz units

0 : pwm_div * 1

μ s

1 : pwm_div * 2

μ s

2 : pwm_div * 3

μ s

... : ...

255 : pwm_div * 256

μ s

Figure 91: curr1_value

Addr:43h curr1_value

Bit Bit Name Default Access

7:0 curr1_current b00000000 RW

Bit Description

Defines the current into CURR1 if

gpio1_mode

= 7

0 : Power down (default state)

1 : 0.15686mA (LSB)

... : ...

255 : 40mA

ams Datasheet

[v1-11] 2016-Dec-14

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Register Description

Figure 92: curr2_value

Addr:44h curr2_value

Bit Bit Name Default Access

7:0 curr2_current b00000000 RW

Bit Description

Defines the current into CURR2 if

gpio2_mode

= 7

0 : Power down (default state)

1 : 0.15686mA (LSB)

... : ...

255 : 40mA

Figure 93:

RegStatus

Bit

Addr:73h

Bit Name

6 curr2_lv

5

0 curr1_lv sd1_lv

RegStatus

Default Access

b0 b0 b0

RO

RO

RO

Bit Description

Bit is set when voltage of current sink CURR2 drops below low voltage threshold (1ms debounce time default)

Bit is set when voltage of current sink CURR1 drops below low voltage threshold (1ms debounce time default)

Bit is set when voltage of step down1 drops below low voltage threshold (-5%) (1ms debounce time default)

Figure 94:

InterruptMask1

Addr:74h

Bit

1

0

3

2

5

4

7

6

Bit Name

LowBat_int_m ovtmp_int_m onkey_int_m chdet_int_m eoc_int_m resume_int_m nobat_int_m trickle_int_m

InterruptMask1

Default Access

b1 b1 b1 b1 b1 b1 b1 b1

RW

RW

RW

RW

RW

RW

RW

RW

Bit Description

Rising edge only

Rising edge only

Rising and falling edge

Rising and falling edge

Rising and falling edge

Rising and falling edge

Rising and falling edge

Rising and falling edge

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AS3701 −

Register Description

Figure 95:

InterruptMask2

Bit

1

0

3

2

5

4

7

6

Addr:75h

Bit Name

gpio5_int_m gpio4_int_m gpio3_int_m gpio2_int_m gpio1_int_m gpio_restart_int_m sd1_lv_int_m bat_temp_m

InterruptMask2

Default Access

b1 b1 b1 b1 b1 b1 b1 b1

RW

RW

RW

RW

RW

RW

RW

RW

Bit Description

Rising and falling edge

Rising and falling edge

Rising and falling edge

Rising and falling edge

Rising and falling edge

Falling edge only

Rising edge only

Rising and falling edge

Figure 96:

InterruptStatus1

Bit

1

0

3

2

5

4

7

6

Addr:77h

Bit Name

LowBat_int_i ovtmp_int_i onkey_int_i chdet_int_i eoc_int_i resume_int_i nobat_int_i trickle_int_i

InterruptStatus1

Default Access

b0 b0 b0 b0 b0 b0 b0 b0

RO

RO

RO

RO

RO

RO

RO

RO

Bit Description

 

 

 

 

 

 

Bit is set when VSUP drops below ResVoltFall

Bit is set when 110deg is exceeded

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Register Description

Figure 97:

InterrupStatus2

Addr:78h

Bit

1

0

3

2

5

4

7

6

Bit Name

gpio5_int_i gpio4_int_i gpio3_int_i gpio2_int_i gpio1_int_i gpio_restart_int_i sd1_lv_int_i bat_temp_i

Default Access

b0 b0 b0 b0 b0 b0 b0 b0

RO

RO

RO

RO

RO

RO

RO

RO

 

 

 

 

 

 

 

 

InterrupStatus2

Bit Description

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AS3701 −

Register Description

Figure 98:

ChargerControl

Bit

7

6

5

4

3:0

Addr:80h

Bit Name

cc_range_ select

AutoResume bat_charging_ enable usb_chgEn usb_Current

ChargerControl

Default Access

b0 b0 b0 b1 b0000

RW

RW

RW

RW

RW

Bit Description

Defines the charging current range for constant current mode

0 : High current range

1 : Low current range

0 : Charging does not restart automatically in EOC when bit Resume is set.

1 : Charging will restart automatically in EOC when bit

Resume is set and vbat is below resume level

0 : USB is supplying VSUP, battery switch is open, ideal diode operation. USB charger regulates to

vsup_voltage

1 : Normal battery charger operation from USB charger, battery switched is closed

0 : USB input is disconnected, battery switch is closed

1 : USB input is connected and supplying VSUP, battery switch is open, ideal diode operation. USB charger regulates

vsup_voltage

.

Sets the USB input current limit.

0 : 94mA (default)

1 : 141mA

2 : 189mA

3 : 237mA

4 : 285mA

5 : 332mA

6 : 380mA

7 : 428mA

8 : 470mA

9 : 517mA

10 : 600mA

11 : 764mA

12 : 889mA

13 : 1065mA

14 : NA

15 : NA

ams Datasheet

[v1-11] 2016-Dec-14

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Register Description

Figure 99:

ChargerVoltageControl

Addr:81h

Bit Bit Name

7:6 Vsup_min

4:0 ChVoltEOC

ChargerVoltageControl

Default Access

b01 b10011

RW

RW

Bit Description

Regulate down battery charging current on that level of

Vsup during trickle charging and constant current charging, to prevent voltage drop on vsup:

0 : 3.90V

1 : 4.20V (default)

2 : 4.50V

3 : 4.70V

Sets the end-of-charge voltage level VCHOFF.

0 : 3.82V

1 : 3.84V

...

19 : 4.20V (default)

...

31 : 4.44V

Page 82

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Register Description

Figure 100:

ChargerCurrentControl

Bit

Addr:82h

Bit Name

7:4 TrickleCurrent

3:0

Constant

Current

ChargerCurrentControl

Default Access

b0000 b0000

RW

RW

Bit Description

Sets the charging current limit in trickle current mode.

0 : 11mA (default)

1 : 23mA

2 : 35mA

3 : 47mA

4 : 59mA

5 : 70mA

6 : 82mA

7 : 94mA

8 : 106mA

9 : 118mA

10 : 130mA

11 : NA

12 : NA

13 : NA

14 : NA

15 : NA

Sets the charging current limit in constant current mode.

0 : 44mA if cc_range_select=0, 11mA if cc_range_select=1

(default)

1 : 88mA if cc_range_select=0, 23mA if cc_range_select=1

2 : 133mA if cc_range_select=0, 35mA if cc_range_ select=1

3 : 178mA if cc_range_select=0, 47mA if cc_range_ select=1

4 : 223mA if cc_range_select=0, 59mA if cc_range_ select=1

5 : 268mA if cc_range_select=0, 70mA if cc_range_ select=1

6 : 313mA if cc_range_select=0, 82mA if cc_range_ select=1

7 : 358mA if cc_range_select=0, 94mA if cc_range_ select=1

8 : 403mA if cc_range_select=0, 106mA if cc_range_ select=1

9 : 448mA if cc_range_select=0, 118mA if cc_range_ select=1

10 : 494mA if cc_range_select=0, 130mA if cc_range_ select=1)

11 : NA

12 : NA

13 : NA

14 : NA

15 : NA

ams Datasheet

[v1-11] 2016-Dec-14

Page 83

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AS3701 −

Register Description

Figure 101:

ChargerConfig1

Bit

7

6

5:4

3:1

Addr:83h

Bit Name

Charging_

1Hz_clk

ChVolt

Resume temp_sel vsup_voltage

ChargerConfig1

Default Access

b0 b0 b00 b100

RW

RW

RW

RW

Bit Description

Sets the mode for the charging output status

(

gpioX_iosf

= 10)

0 : Normal operation: charging=1, not charging=0

1 : 1Hz blinking operation: charging=1Hz, not charging=0

Sets the resume voltage level VCHRES

0 : 3.33% of ChVoltEOC (140mV default)

1 : 5.56% of ChVoltEOC (233mV default)

Selects temperature regulation of charging current

(die temp.)

0 : 120degC

1 : 130degC

2 : 110degC

3 : 90degC

Voltage regulation of VSUP of the input current limiter

0 : 4.4V

1 : 4.5V

2 : 4.6V

3 : 4.7V

4 : 4.8V (default)

5 : 4.9V

6 : 5.0V

7 : 5.5V

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Register Description

Figure 102:

ChargerConfig2

Addr:84h ChargerConfig2

Bit

7:5

4

3:0

Bit Name

eoc_current charging_tmax ch_timeout

Default Access

b001 b0 b0111

RW

R_PUSH

RW

Bit Description

Sets eoc current

0 : 5% of ConstantCurrent

1 : 10% of ConstantCurrent (default)

2 : 15% of ConstantCurrent

3 : 20% of ConstantCurrent

4 : 25% of ConstantCurrent

5 : 30% of ConstantCurrent

6 : 40% of ConstantCurrent

7 : 50% of ConstantCurrent

Write: reset charger timeout counter

0 : Read: No timeout reached

1 : Charging timeout reached and charging stopped

Charging timeout timer

0 : OFF

1 : 0.5h

2 : 1h

3 : 1.5h

4 : 2h

5 : 2.5h

6 : 3h

7 : 3.5h(default)

8 : 4h

9 : 4.5h

10 : 5h

11 : 5.5h

12 : 6h

13 : 6.5h

14 : 7h

15 : 7.5h

ams Datasheet

[v1-11] 2016-Dec-14

Page 85

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AS3701 −

Register Description

Figure 103:

ChargerSupervision

Bit

7

6

5

4

3:2

1:0

Addr:85h

Bit Name

ntc_high_on ntc_low_on ntc_10k ntc_mode

NTC_input ntc_beta

ChargerSupervision

Default Access

b1 b0 b0 b0 b00 b00

RW

RW

RW

RW

RW

RW

Bit Description

Enables the battery high temperature supervision via NTC resistor (depends on ntc_mode)

0 : NTC battery 45/60deg temp supervision disabled

1 : NTC battery 45/60deg temp supervision enabled

Enables the battery low temperature supervision via NTC resistor

0 : NTC battery 0deg temp supervision disabled

1 : NTC battery 0deg temp supervision enabled

Select NTC resistor

0 : 100k (ntc_current = 15

μ

A)

1 : 10k (ntc_current = 150

μ

A)

Defines the temperature level for the battery high temperature supervision

0 : 45deg

1 : 60deg

Defines the NTC input

0 : no NTC input

1 : XIRQ_NTC pin

2 : GPIO3 pin

3 : GPIO4 pin

Sets the ntc beta

0 : 3000 (0deg:1.41V & 45deg:0.59V/60deg:0.42V)

1 : 3500 (0deg:1.49V & 45deg:0.54V/60deg:0.37V)

2 : 4000 (0deg:1.56V & 45deg:0.50V/60deg:0.31V)

3 : 4500 (0deg:1.63V & 45deg:0.46V/60deg:0.27V)

Page 86

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Register Description

Figure 104:

ChargerStatus1

4

3

2

1

0

Bit

7

6:5

Addr:86h

Bit Name

NoBat temp_cond

EOC

CVM

Trickle

Resume

CCM

ChargerStatus1

Default Access

b0 b00 b0 b0 b0 b0 b0

R

R

R

R

R

R

R

Bit Description

Bit is set when battery detection circuit indicates that no battery is connected to the system.

Indicates temperature condition

0 : Battery is in typical condition (0deg < battemp <

45/60deg)

1 : Battery is in cold condition (battemp < 0deg)

2 : Battery is in hot condition (battemp > 45/60deg)

3 : NA

Bit is set if End of charge state has been reached

Bit is set if charger is operating in constant voltage mode

Bit is set, if charger is operating in trickle current.

Vbat<2.9V

Bit is set if Battery voltage is below resume level

Bit is set if charger is operating in constant current mode

Figure 105:

ChargerStatus2

Bit

3

2

1:0

Addr:87h

Bit Name

chdet_off

ChDet batsw_mode

ChargerStatus2

Default Access

b0 b0 b00

RW

R

R

Bit Description

SW can turn OFF charger detection circuit for power-OFF state

0 : Charger detection is always enabled

1 : Charger detection is disabled in power-OFF state

Bit is set when external charge adapter has been detected on pin USB

Bit indicates the status of the battery switch operation mode

0 : Battery switch is closed (charger disconnected or

(charger connected and

usb_chgEn

=0))

1 : Battery switch is open, ideal diode operation (charger connected but EOC reached)

2 : Battery switch is closed and acting as a voltage limited current source (charging)

ams Datasheet

[v1-11] 2016-Dec-14

Page 87

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AS3701 −

Register Description

Figure 106:

LockRegister

Bit

2

1:0

Addr:8eh

Bit Name

charger_lock reg_lock

LockRegister

Default Access

b0 b00

R

R

Bit Description

Enables lock of the charger registers 81h, 82h, 83h, 84h

Chargervoltagecontrol, Chargercurrentcontrol,

Chargerconfig1, Chargerconfig2 Bits can only be set. Reset only with full reset cycle

Enables lock of Regulator voltages Bits can only be set.

Reset only with full reset cycle Disable write to testmodes registers if LDO_lock>0 writing stepdown voltage to 0 should be possible all the time to allow switching ON the regulator. Writing a nonzero value after that should restore the old value

0 : No lock

1 : Lock of voltage of LDOs (LDOx_vsel) (all bits) and voltage of StepDownBits(sdx_vsel) [5:6] only

2 : Lock voltage of StepDownBits(sdx_vsel) [5:6] only

3 : Lock voltage of StepDown (all bits) and LDOs (all bits).

Figure 107:

ASIC_ID1

Bit

7:0

Addr:90h

Bit Name

ID1

Figure 108:

ASIC_ID2

Bit

3:0

Addr:91h

Bit Name

revision

Default

b00010001

Default

b0000

Access

RO

Access

RO  

 

ASIC_ID1

ASIC_ID2

Bit Description

Bit Description

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AS3701 −

Register Description

Figure 109:

Fuse5

Bit

7

6

Addr:a5h

Bit Name

del_time sequ_on

Figure 110:

Fuse6

Default

b0 b0

Access

RW

RW  

 

Fuse5

Bit Description

Bit

2

1

0

Addr:a6h

Bit Name

on_tast_sw onkey_lpress_ reset on_invert

Fuse6

Default Access

b0 b0 b0

RW

RW

RW

Bit Description

Selects mode of ON input

0 : ON key works as push-button

1 : ON key works as switch

Selects behavior for ONKEY longpress

0 : Long onkey press forces change to power_off mode

(if on_tast_sw=0 and onkey_lpress_en=1)

1 : Long onkey press forces a reset (if on_tast_sw=0 and onkey_lpress_en=1)

Inverts the ON input

0 : ON input is active high (default)

1 : ON input is active low

ams Datasheet

[v1-11] 2016-Dec-14

Page 89

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AS3701 −

Register Description

Figure 111:

Fuse7

Bit

7

6

5:4

3

2

1

0

Addr:a7h

Bit Name

auto_off chg_pwr_off_ en res_timer sd1_fsel sd1_fast power_off_at_ vsuplow i2c_deva_bit1

Fuse7

Default Access

b0 b0 b00 b0 b0 b0 b0

RW

RW

RW

RW

RW

RW

RW

Bit Description

Defines startup behavior at first battery insertion

0 : Startup of chip if VBAT>ResVoltRise

1 : Enter power OFF mode (Startup with ON key or charger insertion)

Enable power OFF mode, if charger is detected

0 : Exit of Power OFF mode, if charger is detected (level)

1 : Exit of Power OFF mode, if charger insertion is detected (rising edge only)

Set RESTime, after the last regulator has started

0 : RESTIME=10ms

1 : RESTIME=50ms

2 : RESTIME=100ms

3 : RESTIME=150ms

Selects between high and low frequency range

0 : 1 MHz if sd1_frequ=0, 3MHz if sd1_frequ=1

1 : 2 MHz if sd1_frequ=0, 4MHz if sd1_frequ=1

 

Selects a faster regulation mode for SD1 suitable for larger load changes.

0 : Normal mode, Cext=10

μ

F

1 : Fast mode, Cext=22

μ

F required

Switch into Power off mode if low VSUP is detected during active or standby mode

(Pin ON = low and bit

auto_off

= 0)

0 : If low VSUP(

ResVoltFall

) is detected, enter VSUP

Debounce state, continuously monitor VSUP voltage and startup if VSUP voltage is above

ResVoltRise

1 : If low VSUP(

ResVoltFall

) is detected, enter power OFF mode

Page 90

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Register Description

Figure 112:

Fuse8

Bit

7:4

3:1

0

Addr:a8h

Bit Name

usb_current

ResVoltRise on_lpress_delay

Fuse8

Default Access

b0000 b000 b0

RW

RW

RW

Bit Description

Sets the USB input current limit.

0 : 94mA (default)

1 : 141mA

2 : 189mA

3 : 237mA

4 : 285mA

5 : 332mA

6 : 380mA

7 : 428mA

8 : 470mA

9 : 517mA

10 : 600mA

11 : 764mA

12 : 889mA

13 : 1065mA

14 : NA (1065mA)

15 : NA (1065mA)

This value determines the reset level ResVoltRise for rising VBAT.

ResVoltFall is set to ResVoltRise-200mV by default

0 : 2.7V

1 : 2.9V

2 : 3.1V

3 : 3.2V

4 : 3.3V

5 : 3.4V

6 : 3.5V

7 : 3.6V

Selects default state of the bit on_lpress_delay

ams Datasheet

[v1-11] 2016-Dec-14

Page 91

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AS3701 −

Register Description

Figure 113:

Fuse9

Bit

5

4

7

6

3

2

Addr:a9h

Bit Name

Reg4_del

Reg3_del

Reg2_del

Reg1_del

SupResEn onkey_lpress_en

1:0 NTC_input

Fuse9

Default Access

b0 b0 b0 b0 b0 b0

RW

RW

RW

RW

RW

RW b00 RW

Bit Description

Define delay for timeslot4 (regulator 4)

Define delay for timeslot3 (regulator 3)

Define delay for timeslot2 (regulator 2)

Define delay for timeslot1 (regulator 1)

Presets that bit

Select default state of the onkey_lpress_en

Defines the NTC input

0 : No NTC input

1 : XIRQ_NTC pin

2 : GPIO3 pin

3 : GPIO4 pin

Page 92

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Register Description

Figure 114:

Fuse10

Bit

Addr:aah

Bit Name

7:4

3:0

Reg2_addr

Reg1_addr

Fuse10

Default Access

b0000 b0000

RW

RW

Bit Description

Define startup regulator 2

0 : NA (00h)

1 : SD1 (01h)

2 : LDO1 (02h)

3 : LDO2 (03h)

4 : NA (04h)

5 : NA (05h)

6 : NA (06h)

7 : NA (07h)

8 : NA (08h)

9 : GPIO1 (09h)

10 : GPIO2 (0ah)

11 : GPIO3 (0bh)

12 : GPIO4 (0ch)

13 : GPIO5 (0dh)

14 : NA (0eh)

15 : NA (0fh)

Define startup regulator 1

0 : NA (00h)

1 : SD1 (01h)

2 : LDO1 (02h)

3 : LDO2 (03h)

4 : NA (04h)

5 : NA (05h)

6 : NA (06h)

7 : NA (07h)

8 : NA (08h)

9 : GPIO1 (09h)

10 : GPIO2 (0ah)

11 : GPIO3 (0bh)

12 : GPIO4 (0ch)

13 : GPIO5 (0dh)

14 : NA (0eh)

15 : NA (0fh)

Figure 115:

Fuse11

Bit

7:0

Addr:abh

Bit Name

reg1_V

Default

b00000000

Access

RW

Fuse11

Bit Description

Define startup voltage for regulator 1

ams Datasheet

[v1-11] 2016-Dec-14

Page 93

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AS3701 −

Register Description

Figure 116:

Fuse12

Bit

7:0

Addr:ach

Bit Name

reg2_V

Figure 117:

Fuse13

Bit

Addr:adh

Bit Name

Fuse12

Default Access

b00000000 RW

Bit Description

Define startup voltage for regulator 2

7:4

3:0

Reg4_addr

Reg3_addr

Fuse13

Default Access

b0000 b0000

RW

RW

Bit Description

Define startup regulator 4

0 : NA (00h)

1 : SD1 (01h)

2 : LDO1 (02h)

3 : LDO2 (03h)

4 : NA (04h)

5 : NA (05h)

6 : NA (06h)

7 : NA (07h)

8 : NA (08h)

9 : GPIO1 (09h)

10 : GPIO2 (0ah)

11 : GPIO3 (0bh)

12 : GPIO4 (0ch)

13 : GPIO5 (0dh)

14 : NA (0eh)

15 : NA (0fh)

Define startup regulator 3

0 : NA (00h)

1 : SD1 (01h)

2 : LDO1 (02h)

3 : LDO2 (03h)

4 : NA (04h)

5 : NA (05h)

6 : NA (06h)

7 : NA (07h)

8 : NA (08h)

9 : GPIO1 (09h)

10 : GPIO2 (0ah)

11 : GPIO3 (0bh)

12 : GPIO4 (0ch)

13 : GPIO5 (0dh)

14 : NA (0eh)

15 : NA (0fh)

Page 94

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Register Description

Figure 118:

Fuse14

Bit

7:0

Addr:aeh

Bit Name

reg3_V

Figure 119:

Fuse15

Bit

7:0

Addr:afh

Bit Name

reg4_V

Default Access

b00000000 RW

Fuse14

Bit Description

Define startup voltage for regulator 3

Fuse15

Default Access

b00000000 RW

Bit Description

Define startup voltage for regulator 4

ams Datasheet

[v1-11] 2016-Dec-14

Page 95

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AS3701 −

Application Information

Application Information

Figure 120:

Application Schematic

ON

VSUP

VUSB VSUP VBAT

A2

XRES

1M0 10μF 10μF 10μF

A1

B1

GND

VSUP

10M

GND GND GND

XIRQ_NTC

XIRQ_NTC

ON

XRES

SDA

SCL

SDA

SCL

B3

D3

D4

C4

D5

A5

GND

VUSB

VSUP_CHG

VBAT

LDO1

AS3701

μPMIC

LDO1

LDO2

A4

A3

VSUP

GND

2.2μF

2.2μF

VSUP_SD1

LX_SD1

FB_SD1

VSS_SD1

D2

D1

B2

FB

LX

C1

XIRQ_NTC

ON

XRES

SDA

SCL

GPIO1_CURR1

GPIO2_CURR2

C5

B5

GPIO1

GPIO2

GPIO1

GPIO2

GND

GPIO3_NTC

GPIO4_NTC

GPIO5

B4

C2

C3

GPIO3

GPIO4

GPIO5

GPIO3

GPIO4

GPIO5

LDO2

GND

2.2μF

1μH

SD1

GND

10μF

GND

Page 96

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Application Information

Figure 121:

Layout Guidelines for AS3701A

GND

GND

GND GND

GND

SD1

(0805)

FB

L1

C

OUT

SD1

(0805)

(0805)

VSUP

(0402) (0402)

(0805)

VUSB

LDO2

LDO1

A1 A2 A3 A4 A5

VBAT

B1 B5

C1

GND

GND

D1 D2

VSUP

D3

C

IN

SD1

(0402)

D4

C5

D5

GND

XIRQ_NTC

ON

GPIO2_CURR2

GPIO3

GPIO1_CURR1

SDA

SCL

GPIO5

XRES

ams Datasheet

[v1-11] 2016-Dec-14

Page 97

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AS3701 −

Application Information

Figure 122:

Layout Guidelines for AS3701B

GND

GND

GND GND

GND

SD1

(0805)

FB

L1

C

OUT

SD1

(0805)

(0805)

VSUP

(0402) (0402)

(0805)

VUSB

LDO2

LDO1

A1 A2 A3 A4 A5

VBAT

B1 B2 B3 B5

C1

GND

GND

D1 D2

VSUP

D3

C

IN

SD1

(0402)

C4

D4

GND

C5

GPIO2_CURR2

SDA

GPIO1_CURR1

D5

SCL

ON

XRES

Page 98

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ams Datasheet

[v1-11] 2016-Dec-14

A S 3 7 0 1 −

Package Drawings & Markings

Package Drawings & Markings

Figure 123:

CSP-17 0.4mm Pitch Package Drawing

Note(s):

1. Pin 1 = A1

2. ccc Coplanarity

3. All dimensions are in

μ m

ams Datasheet

[v1-11] 2016-Dec-14

RoHS

Green

Page 99

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A S 3 7 0 1 −

Package Drawings & Markings

Figure 124:

CSP-20 0.4mm Pitch Package Drawing

Note(s):

1. Pin 1 = A1

2. ccc Coplanarity

3. All dimensions are in

μ m

ams Datasheet

[v1-11] 2016-Dec-14

RoHS

Green

Page 100

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AS3701 −

Package Drawings & Markings

AS3701A Marking:

Shows the package marking of the AS3701A product version

Figure 125:

AS3701A Marking

3701A

1V2-zz

XXXX

AS3701B Marking:

Shows the package marking of the AS3701B product version

Figure 126:

AS3701B Marking

3701B

1V2-zz

XXXX

Figure 127:

Package Code

XXXX

Trace code

ams Datasheet

[v1-11] 2016-Dec-14

Page 101

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AS3701 −

Pack age Drawings & Mark ings

Figure 128:

Start-Up Revision Code

1V1-zz Sequence

1V1-ES Engineering samples, no sequence programmed or sequence programmed on request

1V1-00 Standard programming (no sequence programmed)

1V1-??

Other customer specified sequence programmed during production test

(1)

Start-Up Revision Code:

Shows the coding of the different startup sequences

Note(s):

1. Dedicated OTP startup sequence settings available upon request. Please contact www.ams.com/Technical-Support.

Page 102

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Ordering & Contact Information

Ordering & Contact Information

Figure 129:

Ordering Information

Ordering Code

AS3701A-BWLW-ES

AS3701A-BWLM-??

AS3701A-BWLT-??

AS3701B-BWLW-ES

AS3701B-BWLM-00

AS3701B-BWLT-00

AS3701B-BWLM-??

AS3701B-BWLT-??

Package

17-Ball WL-CSP

17-Ball WL-CSP

17-Ball WL-CSP

20-Ball WL-CSP

20-Ball WL-CSP

20-Ball WL-CSP

20-Ball WL-CSP

20-Ball WL-CSP

Marking OTP Programming

Delivery

Form

Delivery

Quantity

3701B

1V2-00

3701B

1V2-00

3701B

1V2-??

3701B

1V2-??

3701A

1V2-ES

3701A

1V2-??

3701A

1V2-??

3701B

1V2-ES

Sequence programmable on request

Customer specified sequence

Customer specified sequence

Sequence programmable on request

Default sequence

Default sequence

Customer specified sequence

Customer specified sequence

Waffle Pack Max. 50 pcs

T & R

(mini reel)

T & R

12000 pcs/reel

Waffle Pack Max. 50 pcs

T & R

(mini reel)

T & R

T & R

(mini reel)

T & R

500 pcs/reel

500 pcs/reel

12000 pcs/reel

500 pcs/reel

12000 pcs/reel

Buy our products or get free samples online at: www.ams.com/ICdirect

Technical Support is available at: www.ams.com/Technical-Support

Provide feedback about this document at: www.ams.com/Document-Feedback

For further information and requests, e-mail us at: [email protected]

For sales offices, distributors and representatives, please visit: www.ams.com/contact

Headquarters

ams AG

Tobelbader Strasse 30

8141 Premstaetten

Austria, Europe

Tel: +43 (0) 3136 500 0

Website: www.ams.com

ams Datasheet

[v1-11] 2016-Dec-14

Page 103

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AS3701 −

RoHS Compliant & ams Green Statement

RoHS Compliant & ams Green

Statement

RoHS:

The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed

0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.

ams Green (RoHS compliant and no Sb/Br):

ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants

(Br or Sb do not exceed 0.1% by weight in homogeneous material).

Important Information:

The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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ams Datasheet

[v1-11] 2016-Dec-14

AS3701 −

Copyrights & Disclaimer

Copyrights & Disclaimer

Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,

Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.

Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of

Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.

ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.

ams Datasheet

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Document Status

Document Status

Document Status

Product Preview

Preliminary Datasheet

Datasheet

Datasheet (discontinued)

Product Status

Pre-Development

Pre-Production

Production

Discontinued

Definition

Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice

Information in this datasheet is based on products in the design, validation or qualification phase of development.

The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice

Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of

Trade

Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of

Trade, but these products have been superseded and should not be used for new designs

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ams Datasheet

[v1-11] 2016-Dec-14

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Revision Information

Revision Information

Changes from 1-08 (2016-Aug-17) to current revision 1-11 (2016-Dec-14)

1-08 (2016-Aug-17) to 1-09 (2016-Dec-05)

Updated Figure 23

Added Figure 38

Added Figure 47

Added Figure 51

Updated Figure 120

Updated Figure 121

Updated Figure 122

Updated Figure 126

1-09 (2016-Dec-05) to 1-10 (2016-Dec-08)

Updated Figure 24

1-10 (2016-Dec-08) to 1-11 (2016-Dec-14)

Updated Figure 129

Note(s):

1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.

2. Correction of typographical errors is not explicitly mentioned.

Page

20

103

96

97

98

103

19

32

39

43

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Content Guide

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Content Guide

1 General Description

1 Key Benefits & Features

2 Applications

3 Block Diagram

5 Pin Assignments

7 Absolute Maximum Ratings

9 Electrical Characteristics

10 Detailed Description –

Power Management Functions

10 Step Down Converter

11 Mode Settings

15 Parameters

19 Universal IO LDO Regulator

19 Parameters

23 Linear Charger

25 Charging Cycle Description

27 Stop Charging Conditions

27 Battery Presence Indication

27 NTC Supervision

31 Parameters

32 Selection of Bypass Capacitors for the Pins VUSB, VSUP_

CHG and VBAT

32 Current Sinks

33 Parameters

34 Detailed Description –

System Functions

34 Start-Up

34 Normal Start-Up

34 Parameter

38 Reset

39 RESET Reasons

40 Parameter

41 Stand-By

41 Enter Via GPIO

42 Enter Via SW

42 Leaving Stand-By

42 Power OFF

44 Internal References

44 Description

44 Parameter

45 GPIO Pins

46 IO Functions

51 Supervisor

51 Temperature Supervision

52 Interrupt Generation

52 Wire-Serial Control Interface

52 Feature List

53 I²C Protocol

56 I²C Parameter

ams Datasheet

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Content Guide

57 Register Description

61 Detailed Register Description

96 Application Information

99 Package Drawings & Markings

103 Ordering & Contact Information

104 RoHS Compliant & ams Green Statement

105 Copyrights & Disclaimer

106 Document Status

107 Revision Information

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[v1-11] 2016-Dec-14

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