STMicroelectronics SPC584B60E3 Datasheet

SAR ADC ground reference

SAR ADC voltage reference

1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 4.3:

SS_HV_ADR_S differential voltage

SS_HV_ADV differential voltage

—

Reference to

SS_HV_ADR_S

—

–0.3

—

0.3

6.0

0.3

TRIN

SR D

I/O input voltage

range

(2)(3)

(4)

—

Relative to V ss

Relative to

DD_HV_IO

and

DD_HV_ADV

—

–0.3

—

6.0

—

0.3

V ms

INJ

SR D

SR T

Digital Input pad transition time (5)

Maximum DC injection current for each analog/digital

PAD

(6)

— –5 — 5 mA

DS11701 Rev 4 15/142

Electrical characteristics SPC584Bx

Table 4. Absolute maximum ratings (continued)

Value

Symbol C Parameter Conditions Unit

Min Typ Max

STORAGE

STG

PAS

SDR

MSL

—

Maximum nonoperating

Storage temperature range

—

Maximum nonoperating temperature during passive lifetime

—

Maximum storage time, assembled part programmed in

ECU

No supply; storage temperature in range –40 °C to

60 °C

Maximum solder temperature Pbfree packaged

(8)

Moisture sensitivity level

(9)

—

–55

—

125

150

(7)

260

°C

°C years

°C

—

XRAY dose SR T

Maximum cumulated

XRAY dose

Typical range for

X-rays source during inspection:80 ÷

130 KV; 20 ÷

50  A

— — 1 grey

1. V

DD_LV

: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed

Operating conditions

2. V

DD_HV

: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative

time with the device in reset at the given temperature profile. Remaining time as defined in Section 4.3: Operating conditions

3. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal calculations.

4. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ).

5. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum limits to the transition time.

6. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in

Section 4.8.3: I/O pad current specifications .

7. 175 °C are allowed for limited time. Mission profile with passive lifetime temperature >150 °C have to be evaluated by ST to confirm that are granted by product qualification.

8. Solder profile per IPC/JEDEC J-STD-020D.

9. Moisture sensitivity per JDEC test method A112.

16/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

4.3 Operating conditions

Table 5 describes the operating conditions for the device, and for which all the specifications

in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded or the functionality of the device is not guaranteed.

Table 5. Operating conditions

Symbol C Parameter Conditions

Min

Value

(1)

Typ Max

Unit

SYS

A_125 Grade

(3)

J_125 Grade

A_105 Grade

J_105 Grade

SR P

SR D

SR P

SR D

SR P

Operating system clock frequency

(2)

Operating

Ambient temperature

Junction temperature under bias

Ambient temperature under bias

Operating

Junction temperature

Core supply voltage

(4)

—

= 125 °C

—

= 105 °C

—

–40

1.14

—

1.20

120

125

150

105

130

1.26

(5) (6)

MHz

°C

V V

DD_LV

DD_HV_IO_MAIN

DD_HV_IO_ETH

DD_HV_FLA

DD_HV_OSC

DD_HV_ADV

SR P

IO supply voltage

—

3.0

—

5.5

SS_HV_ADV

DD_HV_ADR_S

DD_HV_ADV

SS_HV_ADR_S

SR D

SR P

SR D

SR P

ADC supply voltage

ADC ground differential voltage

SAR ADC reference voltage

SAR ADC reference differential voltage

SAR ADC ground reference voltage

—

–25

3.0

—

SS_HV_ADV

5.5

25 mV

V mV

DS11701 Rev 4 17/142

Electrical characteristics SPC584Bx

Symbol

SS_HV_ADR_S

SS_HV_ADV

RAMP_HV

INJ1

INJ2

SR D

SR P

SR T

Table 5. Operating conditions (continued)

Value (1)

Parameter Conditions

Min Typ

SS_HV_ADR_S differential voltage

Slew rate on

HV power supply

I/O input voltage range

Injection current (per pin) without performance degradation

(8) (9)

(7)

—

Digital pins and analog pins

–25

—

–3.0

—

SR D

Dynamic

Injection current (per pin) with performance degradation

(10)

Section 5.5: Package thermal characteristics .

Digital pins and analog pins

–10 —

Max

100

5.5

3.0

Unit mV

V/ms

V mA mA

1. The ranges in this table are design targets and actual data may vary in the given range.

2. Maximum operating frequency is applicable to the cores and platform of the device. See the Clock Chapter in the

Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device.

3. In order to evaluate the actual difference between ambient and junction temperatures in the application, refer to

4. Core voltage as measured on device pin to guarantee published silicon performance.

5. Core voltage can exceed 1.26 V with the limitations provided in Section 4.2: Absolute maximum ratings

, provided that

HVD134_C monitor reset is disabled.

6. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to

1.236 V at the given temperature profile.

7. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See

Section 4.2: Absolute maximum ratings for maximum input current for reliability requirements.

8. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.

9. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in

Section 4.8.3: I/O pad current specifications .

10. Positive and negative Dynamic current injection pulses are allowed up to this limit. I/O and ADC specifications are not granted. See the dedicated chapters for the different specification limits. See the Absolute Maximum Ratings table for maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011),

Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3).

4.3.1 Power domains and power up/down sequencing

The following table shows the constraints and relationships for the different power domains.

Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as well as during normal device operation.

18/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Table 6. Device supply relation during power-up/power-down sequence

Supply2

DD_LV ok

DD_HV_IO_ETH

DD_HV_IO_MAIN

DD_HV_FLA

DD_HV_OSC not allowed

DD_HV_ADV ok V

DD_HV_IO_ ETH

DD_HV_IO_MAIN

DD_HV_FLA

DD_HV_OSC

DD_HV_ADV

DD_HV_ADR ok ok ok ok ok ok not allowed not allowed ok not allowed

DD_HV_ADR ok ok ok

During power-up, all functional terminals are maintained in a known state as described in the device pinout Microsoft Excel file attached to the IO_Definition document.

DS11701 Rev 4 19/142

Electrical characteristics SPC584Bx

4.4 Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device:

 All ESD testing are in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits.

 Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification requirements, which include the complete DC parametric and functional testing at room temperature and hot temperature, maximum DC parametric variation within 10 % of maximum specification”.

Parameter

ESD for Human Body Model (HBM) (1)

Table 7. ESD ratings

Conditions

All pins

Value

2000

ESD for field induced Charged Device Model (CDM)

(2)

All pins

Corner p ins

500

750

1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing.

2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level.

Unit

20/142 DS11701 Rev 4

SPC584Bx

4.5

Electrical characteristics

Electromagnetic compatibility characteristics

EMC measurements at IC-level IEC standards are available from STMicroelectronics on request.

DS11701 Rev 4 21/142

Electrical characteristics

4.6 Temperature profile

SPC584Bx

The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL

1,000 h and HTDR 1,000 hrs, T

= 150 °C.

22/142 DS11701 Rev 4

SPC584Bx

4.7 Device consumption

Table 8. Device consumption

Symbol C Parameter Conditions

DD_LKG

(2),(3)

DD_LV

DD_HV

DD_LV_GW

DD_HV_GW

DD_LV_BCM

DD_HV_BCM

DD_HSM_AC

DDHALT

(8)

DDSTOP

(9)

DDSTBY8

Leakage current on the

DD_LV

supply

Dynamic current on the V

DD_LV

supply, very high consumption profile

(4)

Total current on the

DD_HV

supply

Dynamic current on the V

DD_LV

supply, gateway profile (5)

Dynamic current on the V

DD_HV

supply, gateway profile

(5)

Dynamic current on the V

DD_LV

supply, body profile (6)

Dynamic current on the V

DD_HV

supply,

body profile

HSM platform dynamic operating current

(7)

Dynamic current on the V

DD_LV

supply

+Total current on the

DD_HV

supply

Dynamic current on the V

DD_LV

supply

+Total current on the

DD_HV

supply

Total standby mode current on V

DD_LV

and

DD_HV

supply, 8 KB

RAM

(10)

J f

= 40 °C

= 25 °C

= 55 °C

= 95 °C

= 120 °C

= 150 °C f

—

MAX

—

MAX

—

= 25 °C

= 40 °C

= 55 °C

= 120 °C

= 150 °C

Electrical characteristics

Min

—

Value

(1)

Typ

—

1.5

—

Max

Unit mA

—

— 125 mA

—

55 mA

98 mA

22 mA

79 mA

29 mA

15 mA

63 mA

24 mA

—

0.8

1.8

120

180

280

1.65

3.8

µA mA

DS11701 Rev 4 23/142

Electrical characteristics SPC584Bx

Table 8. Device consumption (continued)

Value (1)

Symbol C Parameter Conditions Unit

Min Typ Max

DDSTBY32

DDSTBY128

Total standby mode current on V

DD_LV

and

DD_HV

supply, 32 KB

RAM

Total standby mode current on V

DD_LV

and

DD_HV

supply,

128 KB RAM

= 25 °C

= 40 °C

= 55 °C

= 120 °C

= 150 °C

= 25 °C

= 40 °C

= 55 °C

= 120 °C

= 150 °C

—

1.2

2.8

µA mA

µA

µA mA

DDSSWU1

DDSSWU2

SSWU running over all

STANDBY period with

OPC/TU commands execution and keeping

ADC off

(11)

SSWU running over all

STANDBY period with

OPC/TU/ADC commands execution and keeping ADC on

(12)

= 40 °C

—

1.0

3.5

5.0

mA mA

1. The ranges in this table are design targets and actual data may vary in the given range.

2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered, and they are computed in the dynamic I

DD_LV

and I

DD_HV

parameters.

3. I

DD_LKG

(leakage current) and I

DD_LV

(dynamic current) are reported as separate parameters, to give an indication of the consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (I

DD_LKG the software profile used.

+ I

DD_LV

). The two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and

4. Use case: 1 x e200Z4 @120 MHz, HSM @60 MHz, all IPs clock enabled, Flash access with prefetch disabled, Flash consumption includes parallel read and program/erase, all SARADC in continuous conversion, DMA continuously triggered by ADC conversion, 2 DSPI / 8 CAN / 2 LINFlex transmitting, RTC and STM running, 1 x EMIOS running (4 channels in

OPWMT mode), FIRC, SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not include I/O toggling, which is highly dependent on the application. Details of the software configuration are available separately. The total device consumption is I

DD_LV

+ I

DD_HV

+ I

DD_LKG

for the selected temperature.

5. Gateway use case: One core running at 120 MHz, HSM 40 MHz, DMA, PLL, FLASH read only 25%, 8xCAN, 1xSARADC.

6. BCM use case: One Core running at 80 MHz, HSM 40 MHz, DMA, PLL, FLASH read only 25%, 1xCAN, 3xSARADC.

7. Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code

Book crypto algorithm on 1 block of 16 byte of shared RAM.

8. Flash in Low Power. Sysclk at 120 MHz, HSM 60 MHz, PLL0_PHI at 400 MHz, XTAL at 40 MHz, FIRC 16 MHz ON,

RCOSC1M off. FlexCAN: instances: 0, 1, 2, 3, 4, 5, 6, 7 ON (configured but no reception or transmission), Ethernet ON

(configured but no reception or transmission), ADC ON (continuously converting). All others IPs clock-gated.

9. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power down mode.

10. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on.

130

200

300

1.8

4.1

160

250

370

2.2

5.0

24/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

11. SSWU1 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC off. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature.

12. SSWU2 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC on in continuous conversion. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature.

DS11701 Rev 4 25/142

Electrical characteristics SPC584Bx

4.8 I/O pad specification

The following table describes the different pad type configurations.

Pad type

Table 9. I/O pad specification descriptions

Description

Weak configuration Provides a good compromise between transition time and low electromagnetic emission.

Medium configuration

Provides transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission.

Strong configuration Provides fast transition speed; used for fast interface.

Very strong configuration

Provides maximum speed and controlled symmetric behavior for rise and fall transition.

Used for fast interface including Ethernet interface requiring fine control of rising/falling edge jitter.

Differential configuration

Input only pads

Standby pads

A few pads provide differential capability providing very fast interface together with good

EMC performances.

These low input leakage pads are associated with the ADC channels.

These pads (LP pads) are active during STANDBY. They are configured in CMOS level logic and this configuration cannot be changed. Moreover, when the device enters the

STANDBY mode, the pad-keeper feature is activated for LP pads. It means that:

– if the pad voltage level is above the pad keeper high threshold, a weak pull-up resistor is automatically enabled

– if the pad voltage level is below the pad keeper low threshold, a weak pull-down resistor is automatically enabled.

For the pad-keeper high/low thresholds, consider(VDD_HV_IO_MAIN / 2) +/-20 %.

Note:

4.8.1

Each I/O pin on the device supports specific drive configurations. See the signal description table in the device reference manual for the available drive configurations for each I/O pin.

PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for each IO segment.

Logic level is configurable in running mode while it is CMOS not-configurable in STANDBY for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be configured as CMOS also in running mode in order to prevent device wrong behavior in

STANDBY.

I/O input DC characteristics

The following table provides input DC electrical characteristics, as described in

Figure 3 .

26/142 DS11701 Rev 4

SPC584Bx

INTERNAL

(SIUL register)

Electrical characteristics

Figure 3. I/O input electrical characteristics

HYS

Symbol

V ihttl

V ilttl

V hysttl

Table 10. I/O input electrical characteristics

Parameter Conditions

Min

Value

Typ

TTL

CC C

Input high level

TTL

Input low level

TTL

Input hysteresis

TTL

—

–0.3

0.3

—

CMOS

V ihcmos

V ilcmos

V hyscmos

CC C

Input high level

CMOS

Input low level

CMOS

Input hysteresis

CMOS

—

0.65 * V

–0.3

0.10 * V

—

LKG

CC P

Pad input leakage

COMMON

INPUT-ONLY pads

= 150 °C

STRONG pads

= 150 °C

VERY STRONG pads,

= 150 °C

—

Max

200

1,000

Unit

DD_HV_IO

+ 0.3

0.8

— V

DD_HV_IO

+ 0.3

0.35 * V

— V nA nA nA

DS11701 Rev 4 27/142

Electrical characteristics SPC584Bx

Symbol C

Table 10. I/O input electrical characteristics (continued)

Value

Parameter Conditions

Min Typ

Unit

Max

P1 drift

NFI

Pad capacitance

Input V il

/V ih temperature drift

Wakeup input filtered pulse

(1)

Wakeup input not filtered pulse

—

In a 1 ms period, with a temperature variation

<30 °C

—

400

—

100

—

1. In the range from W

(max) to W

NFI

(min), pulses can be filtered or not filtered, according to operating temperature and voltage. Refer to the device pinout IO definition excel file for the list of pins supporting the wakeup filter feature.

pF mV ns ns

Symbol

WPU

WPD

Table 11. I/O pull-up/pull-down electrical characteristics

Value

Parameter Conditions

Min Typ

CC D

Weak pull-up current absolute value

Weak Pull-up resistance

Weak pulldown current absolute value

= 1.1 V (1)

= 0.69 *

DD_HV_IO

(2)

DD_HV_IO

= 5.0 V ±

10%

DD_HV_IO

= 3.3 V ±

10%

= 0.69 *

DD_HV_IO

= 0.9 V

Figure 4 provides description of output DC electrical characteristics.

—

WPD

Weak Pulldown resistance

DD_HV_IO

10%

DD_HV_IO

= 5.0 V ±

= 3.3 V ±

10%

1. Maximum current when forcing a change in the pin level opposite to the pull configuration.

2. Minimum current when keeping the same pin level state than the pull configuration.

—

Note:

Max

130

—

130

—

Unit

 A

K 

 A

K 

When the device enters into standby mode, the LP pads have the input buffer switched-on.

As a consequence, if the pad input voltage VIN is V

DD_HV

, an additional consumption can be measured in the VDD_HV domain. The highest consumption can be seen around mid-range (VIN ~=VDD_HV/2), 2-3 mA depending on process, voltage and temperature.

28/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

4.8.2

This situation may occur if the PAD is used as a ADC input channel, and V

DD_HV

The applications should ensure that LP pads are always set to VDD_HV or VSS, to avoid the extra consumption. Refer to the device pinout IO definition excel file to identify the lowpower pads which also have an ADC function.

I/O output DC characteristics

Figure 4. I/O output DC electrical characteristics definition

INTERNAL

(SIUL register)

HYS t

SKEW20-80

V out

90%

80%

Note:

20%

10% t

R20-80 t

R10-90 t

(max) = MAX(t

R10-90

; t

F10-90

) t

(min) = MIN(t

R10-90

; t

F10-90

) t

F20-80 t

F10-90 t

TR20-80

(max) = MAX(t

R20-80

; t

F20-80

) t

TR20-80

(min) = MIN(t

R20-80

; t

F20-80

) t

SKEW20-80 t

SKEW10-90



 t t

R20-80

-t

R10-90

-t

F20-80



F10-90



The following tables provide DC characteristics for bidirectional pads:



Table 12 provides output driver characteristics for I/O pads when in WEAK/SLOW

configuration.



Table 13 provides output driver characteristics for I/O pads when in MEDIUM

configuration.



Table 14 provides output driver characteristics for I/O pads when in STRONG/FAST

configuration.



Table 15 provides output driver characteristics for I/O pads when in VERY

STRONG/VERY FAST configuration.

10 %/90 % is the default condition for any parameter if not explicitly mentioned differently.

DS11701 Rev 4 29/142

Electrical characteristics

Symbol

V ol_W

V oh_W

F max_W t

TR_W

DCMAX_W

CC D

CC P

CC T

 t

SKEW_W

 CC T

CC D

Table 12. WEAK/SLOW I/O output characteristics

Value

Parameter Conditions

Min Typ

Output low voltage for Weak type PADs

I ol

= 0.5 mA

= 5.0 V ± 10 %

= 3.3 V ± 10 %

Output high voltage for Weak type PADs

Output impedance for

Weak type PADs

Ioh = 0.5 mA

= 5.0 V ± 10 %

= 3.3 V ± 10 %

= 5.0 V ± 10 %

= 3.3 V ± 10 %

Maximum output frequency for

Weak type PADs

CL = 25 pF

= 5.0 V ± 10 %

= 3.3 V ± 10 %

CL = 50 pF

= 5.0 V ± 10 %

= 3.3 V ± 10 %

Transition time output pin weak configuration,

10%-90%

CL = 25 pF

= 5.0 V +

10 %

= 3.3 V +

10 %

CL = 50 pF

= 5.0 V ± 10 %

= 3.3 V ± 10 %

Difference between rise and fall time,

90%-10%

—

Maximum DC current

= 5.0 V ± 10 %

= 3.3 V ± 10 %

—

0.9*V

380

250

—

Symbol

V ol_M

V oh_M

CC D

Table 13. MEDIUM I/O output characteristics

Value

Parameter Conditions

Min Typ

Output low voltage for

Medium type

PADs

Output high voltage for

Medium type

PADs

I ol

= 2.0 mA

=5.0 V ± 10 %

=3.3 V ± 10 %

I oh

=2.0 mA

= 5.0 V ± 10 %

= 3.3 V ± 10 %

—

0.9*V

—

Max

0.1*V

Unit

—

1040

700



MHz

120

240

0.5

Unit

Max

0.1*V

—

SPC584Bx

MHz ns ns

30/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Symbol

F max_M t

TR_M

DCMAX_M

Table 13. MEDIUM I/O output characteristics (continued)

Value

Parameter Conditions

Min Typ

CC P

CC T

 t

SKEW_M

 CC T

CC D

Output impedance for

Medium type

PADs

= 5.0 V ± 10 %

= 3.3 V ± 10 %

Maximum output frequency for

Medium type

PADs

CL = 25 pF

= 5.0 V ± 10 %

= 3.3 V ± 10 %

CL = 50 pF

= 5.0 V ± 10 %

= 3.3 V ± 10 %

Transition time output pin

MEDIUM configuration,

10%-90%

CL = 25 pF

= 5.0 V ± 10 %

= 3.3 V ± 10 %

CL = 50 pF

= 5.0 V ± 10 %

= 3.3 V ± 10 %

Difference between rise and fall time,

90%-10%

—

Maximum DC current

= 5.0 V ± 10 %

= 3.3 V ± 10 %

—

Max

260

170

Unit



MHz

MHz ns ns

% mA

V ol_S

V oh_S

Symbol

CC D

CC P

Table 14. STRONG/FAST I/O output characteristics

Value

Parameter Conditions

Min Typ

Output low voltage for

Strong type

PADs

Output high voltage for

Strong type

PADs

I ol

= 8.0 mA

= 5.0 V ± 10 %

I ol

= 5.5 mA

=3 .3 V ± 10 %

I oh

= 8.0 mA

= 5.0 V ± 10 %

I oh

= 5.5 mA

= 3.3 V ± 10 %

= 5.0 V ± 10 % Output impedance for

Strong type

PADs

= 3.3 V ± 10 %

—

0.9*V

0.85*V

—

Max

0.1*V

Unit

0.15*V

— V

—



DS11701 Rev 4 31/142

Electrical characteristics

Symbol

F max_S t

TR_S

DCMAX_S

Table 14. STRONG/FAST I/O output characteristics (continued)

Value

C Parameter Conditions

Min Typ

CC T

CC D

 t

SKEW_S

 CC T

Maximum output frequency for

Strong type

PADs

CL = 25 pF

=5.0 V ± 10 %

CL = 50 pF

=5.0 V ± 10 %

CL = 25 pF

= 3.3 V ± 10 %

Transition time output pin

STRONG configuration,

10%-90%

CL = 50 pF

= 3.3 V ± 10 %

CL = 25 pF

= 5.0 V ± 10 %

CL = 50 pF

= 5.0 V ± 10 %

CL = 25 pF

= 3.3 V ± 10 %

CL = 50 pF

= 3.3 V ± 10 %

Maximum DC current

= 5 V ± 10 %

= 3.3 V ± 10 %

Difference between rise and fall time,

90 %-10 %

—

1.5

2.5

—

Max

12.5

5.5

SPC584Bx

Unit mA

MHz

MHz ns

Symbol

V ol_V

V oh_V

Table 15. VERY STRONG/VERY FAST I/O output characteristics

Value

C Parameter Conditions

Min Typ

CC D

CC P

Output low voltage for Very

Strong type

PADs

I ol

= 9.0 mA

=5.0 V ± 10 %

I ol

= 9.0 mA

=3.3 V ± 10 %

I oh

= 9.0 mA

= 5.0 V ± 10 %

Output high voltage for Very

Strong type

PADs

Output impedance for

Very Strong type

PADs

I oh

= 9.0 mA

= 3.3 V ± 10 %

= 5.0 V ± 10 %

= 3.3 V ± 10 %

—

0.9*V

0.85*V

—

Max

0.1*V

0.15*V

—

Unit



32/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Table 15. VERY STRONG/VERY FAST I/O output characteristics (continued)

Value

Symbol C Parameter Conditions

Min Typ Max

F max_V t

TR_V t

TR20-80_V t

TRTTL_V

 t

TR20-80_V

 t

SKEW_V

 CC T

DCMAX_V

CC T

CC D

Maximum output frequency for

Very Strong type

PADs

CL = 25 pF

= 5.0 V ± 10 %

CL = 50 pF

= 5.0 V ± 10 %

CL = 25 pF

= 3.3 V ± 10 %

10–90% threshold transition time output pin VERY

STRONG configuration

CL = 50 pF

= 3.3 V ± 10 %

CL = 25 pF

= 5.0 V ± 10 %

CL = 50 pF

= 5.0 V ± 10 %

CL = 25 pF

= 3.3 V ± 10 %

CL = 50 pF

= 3.3 V ± 10 %

20–80% threshold transition time output pin VERY

STRONG configuration

CL = 25 pF

= 5.0 V ± 10 %

CL = 15 pF

= 3.3 V ± 10 %

TTL threshold transition time for output pin in

VERY STRONG configuration

(Ethernet standard)

CL = 25 pF

= 3.3 V ± 10 %

CL = 25 pF

= 5.0 V ± 10 %

Sum of transition time

20–80% output pin VERY

STRONG configuration

Difference between rise and fall delay

CL = 15 pF

= 3.3 V ± 10 %

CL = 25 pF

= 5.0 V ± 10 %

Maximum DC current

= 5.0 V±10 %

= 3.3 V ± 10 %

—

1.5

0.8

0.88

—

4.5

1.2

Unit ns ns ns ns ns mA

MHz

DS11701 Rev 4 33/142

Electrical characteristics SPC584Bx

4.8.3

Symbol

I/O pad current specifications

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V

supply pair as described in the device pinout Microsoft Excel file attached to the IO_Definition document.

Table 16 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I

RMSSEG

maximum value.

In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the I

DYNSEG

maximum value.

Pad mapping on each segment can be optimized using the pad usage information provided on the I/O Signal Description table.

Table 16. I/O consumption

C Parameter Conditions

Value

(1)

Min Typ Max

Unit

RMSSEG

RMS_W

RMS_M

RMS_S

SR D

CC D

Average consumption

(2)

Sum of all the DC I/O current within a supply segment

—

RMS I/O current for WEAK configuration

RMS I/O current for MEDIUM configuration

RMS I/O current for STRONG configuration

= 25 pF, 2 MHz,

= 5.0 V ± 10 %

= 50 pF, 1 MHz,

= 5.0 V ± 10 %

= 25 pF, 2 MHz,

= 3.3 V ± 10 %

= 25 pF, 1 MHz,

= 3.3 V ± 10 %

= 25 pF, 12 MHz,

= 5.0 V ± 10 %

= 50 pF, 6 MHz,

= 5.0 V ± 10 %

= 25 pF, 12 MHz,

= 3.3 V ± 10 %

= 25 pF, 6 MHz,

= 3.3 V ± 10 %

= 25 pF, 50 MHz,

= 5.0 V ± 10 %

= 50 pF, 25 MHz,

= 5.0 V ± 10 %

= 25 pF, 25 MHz,

= 3.3 V ± 10 %

= 25 pF, 12.5 MHz,

= 3.3 V ± 10 %

—

80 mA

1.1

1.0

5.5

4.2

10 mA mA mA

34/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Table 16. I/O consumption (continued)

Symbol C Parameter Conditions

DYN_SEG

RMS_V

DYN_W

DYN_M

DYN_S

CC D

SR D

CC D

= 25 pF, 50 MHz,

= 5.0 V ± 10 %

= 50 pF, 25 MHz,

= 5.0 V ± 10 %

RMS I/O current for VERY

STRONG configuration

= 25 pF, 50 MHz,

= 3.3 V ± 10 %

= 25 pF, 25 MHz,

= 3.3 V ± 10 %

Dynamic consumption

(3)

Sum of all the dynamic and DC

I/O current within a supply segment

Dynamic I/O current for WEAK configuration

Dynamic I/O current for

MEDIUM configuration

Dynamic I/O current for

STRONG configuration

= 5.0 V ± 10 %

= 3.3 V ± 10 %

= 25 pF, V

10 %

= 5.0 V ±

= 50 pF, V

10 %

= 5.0 V ±

= 25 pF, V

10 %

= 3.3 V ±

= 50 pF, V

10 %

= 3.3 V ±

= 25 pF, V

10%

= 5.0 V ±

= 50 pF, V

10%

= 5.0 V ±

= 25 pF, V

10 %

= 3.3 V ±

= 50 pF, V

10 %

= 3.3 V ±

= 25 pF, V

10 %

= 5.0 V ±

= 50 pF, V

10 %

= 5.0 V ±

= 25 pF, V

10 %

= 3.3 V ±

= 50 pF, V

10 %

= 3.3 V ±

Value (1)

Min Typ Max

Unit

— — 23

—

195

150

16.7

16.8

12.9

18.2

18.4

14.3

16.4

63.5

33.5

mA mA mA mA mA

DS11701 Rev 4 35/142

Electrical characteristics SPC584Bx

Table 16. I/O consumption (continued)

Value (1)

Symbol C Parameter Conditions Unit

Min Typ Max

DYN_V

CC D

Dynamic I/O current for VERY

STRONG configuration

= 25 pF, V

10 %

= 5.0 V ±

= 50 pF, V

10 %

= 5.0 V ±

= 25 pF, V

10 %

= 3.3 V ±

= 50 pF, V

10 %

= 3.3 V ±

—

1. I/O current consumption specifications for the 4.5 V

VSIO[VSIO_xx] = 0 for 3.0 V  V

DD_HV_IO

 3.6 V.

 V

DD_HV_IO

 5.5 V range are valid for VSIO_[VSIO_xx] = 1, and

2. Average consumption in one pad toggling cycle.

3. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible (timed output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.

36/142 DS11701 Rev 4

SPC584Bx

4.9

Electrical characteristics

Reset pad (PORST) electrical characteristics

The device implements dedicated bidirectional reset pins as below specified. PORST pin does not require active control. It is possible to implement an external pull-up to ensure correct reset exit sequence. Recommended value is 4.7 K  .

Figure 5. Startup r eset requirements

DD_POR

PORST

PORST undriven device reset by internal power-on reset

PORST driven low by internal power-on reset device start-up phase device reset forced by external circuitry

Figure 6 describes device behavior depending on supply signal on PORST:

PORST low pulse has too low amplitude: it is filtered by input buffer hysteresis. Device remains in current state.

PORST low pulse has too short duration: it is filtered by low pass filter. Device remains in current state.

PORST low pulse is generating a reset: a) PORST low but initially filtered during at least WFRST. Device remains initially in current state.

b) PORST potentially filtered until WNFRST. Device state is unknown. It may either be reset or remains in current state depending on extra condition (temperature, voltage, device).

c) PORST asserted for longer than WNFRST. Device is under reset.

DS11701 Rev 4 37/142

Electrical characteristics

PORST

Figure 6. Noise filtering on reset signal

HYS

SPC584Bx internal reset filtered by

hysteresis

1 filtered by

lowpass filter

FRST

2 filtered by

lowpass filter unknown reset state device under hardware reset

FRST

NFRST

3a 3b 3c

Symbol

IHRES

ILRES

HYSRES

DD_POR

Table 17. Reset PAD electrical characteristics

Parameter Conditions

Input high level

TTL

Input low level

TTL

DD_HV

= 5.0 V ± 10 %

= 3.3 V ± 10 %

DD_HV

= 5.0 V ± 10 %

DD_HV

= 3.3 V ± 10 %

CC C Input hysteresis

TTL

DD_HV

= 5.0 V ± 10 %

DD_HV

= 3.3 V ± 10 %

CC D Minimum supply for strong pulldown activation

DD_HV

= 5.0 V ± 10 %

DD_HV

= 3.3 V ± 10 %

Min

-0.3

0.3

0.2

—

Value

Typ

—

Max

DD_HV_IO

+0.3

0.8

0.6

—

1.6

1.05

Unit

38/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Symbol C

Table 17. Reset PAD electrical characteristics (continued)

Value

Parameter Conditions

Min Typ

Unit

Max

OL_R

WPU

WPD

CC P Strong pull-down current

(1)

CC P

Weak pull-up current absolute value

CC P Weak pull-down current absolute value

DD_HV

= 5.0 V ± 10 %

DD_HV

= 3.3 V ± 10 %

DD_HV

= 1.1 V

(2)

= 5.0 V ± 10 %

DD_HV

= 1.1 V

= 3.3 V ± 10 %

= 0.69 *

DD_HV_IO

(3)

DD_HV

= 5.0 V ± 10 %

= 0.69 * V

DD_HV_IO

DD_HV

= 3.3 V ± 10 %

= 0.69 *

DD_HV_IO

DD_HV

= 5.0 V ± 10 %

= 0.69 *

DD_HV_IO

Figure 7 depicts the integration of the two PLLs. Refer to device Reference Manual for more

DD_HV

= 3.3 V ± 10 %

DD_HV

= 0.9 V

= 5.0 V ± 10 %

= 0.9 V

DD_HVDD_HV

± 10 %

= 3.3 V

—

130

—

130

—

— mA



FRST

NFRST

Input filtered pulse

Input not filtered pulse

DD_HV

= 5.0 V ± 10 %

DD_HV

= 3.3 V ± 10 %

DD_HV

= 5.0 V ± 10 %

DD_HV

= 3.3 V ± 10 %

—

2000

3000

—

500

600

—

1. I ol_r

applies to PORST: Strong Pull-down is active on PHASE0 for PORST. Refer to the device pinout IO definition excel file for details regarding pin usage.

2. Maximum current when forcing a change in the pin level opposite to the pull configuration.

3. Minimum current when keeping the same pin level state than the pull configuration.

ns ns

PAD

Table 18. Reset P AD state during power-up and reset

POWER-UP State RESET state DEFAULT state

(1)

STANDBY state

PORST Strong pull-down Weak pull-down Weak pull-down Weak pull-up

1. Before SW Configuration. Refer to the Device Reference Manual, Reset Generation Module (MC_RGM) Functional

Description chapter for the details of the power-up phases.

DS11701 Rev 4 39/142

Electrical characteristics SPC584Bx

4.10 PLLs

Two phase-locked loop (PLL) modules are implemented to generate system and auxiliary clocks on the device.

detailed schematic.

Figure 7. PLLs integration

IRCOSC

XOSC

PLL0

PLL0_PHI

PLL0_PHI1

PLL1_PHI

PLL1

4.10.1 PLL0

Table 19. PLL0 electrical characteristics t f f f f

 f

Symbol

PLL0IN

INFIN

PLL0VCO

PLL0PHI0

PLL0PHI1

PLL0LOCK



PLL0PHI0SPJ

(3)

C Parameter Conditions

SR — PLL0 input clock

(1)

SR —

PLL0 input clock duty

cycle

SR —

PLL0 PFD (Phase

Frequency Detector) input clock frequency

CC P PLL0 VCO frequency

CC D PLL0 output frequency

CC D PLL0 output clock PHI1

CC P PLL0 lock time

CC T

PLL0_PHI0 single period jitter f

PLL0IN

= 20 MHz

(resonator)

—

— f

PLL0PHI0

= 400 MHz,

6-sigma pk-pk

Min

600

4.762

—

Value

Typ

—

Max

—

1400

400

175

(2)

100

200

Unit

MHz

µs ps

40/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Table 19. PLL0 electrical characteristics (continued)

Value

Symbol C Parameter Conditions Unit

Min Typ Max



PLL0PHI1SPJ

CC D

PLL0_PHI1 single period jitter f

PLL0IN

= 20 MHz

(resonator) f

PLL0PHI1

= 40 MHz,

6-sigma pk-pk

— — 300

(4) ps



PLL0LTJ

CC D

PLL0 output long term jitter

PLL0IN

= 20 MHz

(resonator), VCO frequency = 800 MHz

10 periods accumulated jitter

(80 MHz equivalent frequency), 6-sigma pk-pk

16 periods accumulated jitter

(50 MHz equivalent frequency), 6-sigma pk-pk

—

±250

±300 ps ps long term jitter

(< 1 MHz equivalent frequency), 6-sigma pk-pk)

— — ±500 ps

PLL0

CC D PLL0 consumption FINE LOCK state — — 6 mA

1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using internal RCOSC or external oscillator is used in functional mode.

2. If the PLL0_PHI1 is used as an input for PLL1, then the PLL0_PHI1 frequency shall obey the maximum input frequency limit set for PLL1 (87.5 MHz, according to

Table 20

3. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to the output CLKOUT pin.

4. V filtered.

noise due to application in the range V

DD_LV

= 1.20 V±5 %, with frequency below PLL bandwidth (40 kHz) will be

DS11701 Rev 4 41/142

Electrical characteristics SPC584Bx

4.10.2 PLL1

PLL1 is a frequency modulated PLL with Spread Spectrum Clock Generation (SSCG) support.

Table 20. PLL1 electrical characteristics

Value

Symbol C Parameter Conditions Unit

Min Typ Max f

 f

PLL1IN

INFIN

SR — PLL1 input clock

(1)

SR —

PLL1 input clock duty

cycle

2. Refer to Section 4.3: Operating conditions for the maximum operating frequency.

SR —

PLL1 PFD (Phase

Frequency Detector) input clock frequency

—

37.5

—

87.5

MHz

MHz f

PLL1VCO f

PLL1PHI0 t

PLL1LOCK

PLL1 VCO frequency

PLL1 output clock PHI0

—

600

4.762

—

1400

SYS

(2)

MHz

MHz f

PLL1MOD

P PLL1 lock time

PLL1 modulation frequency

—

— 250

µs kHz





PLL1MOD

PLL1 modulation depth

(when enabled)

PLL1_PHI0 single period peak to peak jitter

Center spread

Down spread f

PLL1PHI0

(3)

200 MHz, 6-sigma

0.25

0.5

—

500

(5)

% ps

PLL1

CC D PLL1 consumption FINE LOCK state — — 5 mA

1. PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when using internal PPL0 or external oscillator is used in functional mode.

3. The device maximum operating frequency F

SYS

(max) includes the frequency modulation. If center modulation is selected, the FSYS must be below the maximum by MD (Modulation Depth Percentage), such that FSYS(max)=FSYS(1+MD %).

Refer to the Reference Manual for the PLL programming details.

4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to the output CLKOUT pin.

5. 1.25 V±5 %, application noise below 40 kHz at V

DD_LV

pin - no frequency modulation.

42/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

4.11 Oscillators

4.11.1 Crystal oscillator 40 MHz

Symbol f

XTAL t cst t rec

IHEXT

ILEXT

S_EXTAL

S_XTAL g m

EXTAL

Table 21. External 40 MHz oscillator electrical specifications

Value

C Parameter Conditions

CC D Crystal Frequency

Range

(1)

—

CC T Crystal start-up time

(3),(4)

CC D Crystal recovery time

(5)

CC D

EXTAL input high voltage (6) (External

Reference)

EXTAL input low

voltage

(External

Reference)

REF

= 150 °C

—

= 0.29 * V

DD_HV_OSC

Total on-chip stray capacitance on EXTAL pin

(7)

Total on-chip stray capacitance on XTAL pin

Figure 8 shows the input equivalent circuit for SARn and SARB channels.

Oscillator

Transconductance

—

CC P

CC D Oscillation Amplitude on the EXTAL pin after startup

(8) f

XTAL

 4  8 MHz freq_sel[2:0] = 000 f

XTAL

 5 - 10 MHz freq_sel[2:0] = 001 f

XTAL

 10  15 MHz freq_sel[2:0] = 010 f

XTAL

 15 - 20 MHz freq_sel[2:0] = 011 f

XTAL

 20 - 25 MHz freq_sel[2:0] = 100 f

XTAL

 25  30 MHz freq_sel[2:0] = 101 f

XTAL

 30 - 35 MHz freq_sel[2:0] = 110 f

XTAL

 35 - 40 MHz freq_sel[2:0] = 111

= –40 °C to 150 °C

Min

4 (2)

>20

—

REF

0.75

—

3.9

8.6

14.4

21.2

33.5

0.5

Max

0.5

—

REF

0.75

13.6

17.5

29.3

115

1.8

Unit

MHz ms ms

V pF pF mA/V

DS11701 Rev 4 43/142

Electrical characteristics SPC584Bx

Symbol

Table 21. External 40 MHz oscillator electrical specifications (continued)

Value

C Parameter Conditions

Min Max

Unit

HYS

XTAL

Comparator Hysteresis

XTAL current

(8),(9)

= –40 °C to 150 °C

0.1

—

1.0

V mA

1. The range is selectable by UTEST miscellaneous DCF client XOSC_FREQ_SEL.

2. The XTAL frequency, if used to feed the PPL0 (or PLL1), shall obey the minimum input frequency limit set for PLL0 (or

PLL1).

3. This value is determined by the crystal manufacturer and board design, and it can potentially be higher than the maximum provided.

4. Proper PC board layout procedures must be followed to achieve specifications.

5. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load capacitor value.

6. Applies to an external clock input and not to crystal mode.

7. See crystal manufacturer’s specification for recommended load capacitor (C

) values.The external oscillator requires external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (C /C

S_XTAL

) and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load capacitor value is selected via S/W to match the crystal manufacturer’s specification, while accounting for on-chip and PCB capacitance.

8. Amplitude on the EXTAL pin after startup is determined by the ALC block, that is the Automatic Level Control Circuit. The function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to reduce power, distortion, and RFI, and to avoid over driving the crystal. The operating point of the ALC is dependent on the crystal value and loading conditions.

9. I

XTAL

is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum current during startup of the oscillator.

4.11.2 Crystal Oscillator 32 kHz

Symbol f sxosc g msxosc

V sxosc

I sxoosc

T sxosc

Table 22. 32 kHz e xternal s low o scillator electrical specifications

Value

C Parameter Conditions

Min Typ

SR T — — 32768

CC P

CC T

CC D

CC T

Slow external crystal oscillator frequency

Slow external crystal oscillator transconductance

Oscillation

Amplitude

Oscillator consumption

Start up time

—

9.5

0.5

—

Max

—

1.7

Unit

µA/V

µA s

44/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

4.11.3 RC oscillator 16 MHz

Symbol

Table 23. Internal RC oscillator electrical specifications

Value

C Parameter Conditions

Min Typ

Unit

Max

 f



T f

 f start_noT

T var_noT f

Target var_T var_SW start_T

IRC target frequency

IRC frequency variation without temperature compensation

IRC frequency variation with temperature compensation

IRC software trimming accuracy

T Startup time to reach within f var_noT

T Startup time to reach within f var_T

—

T < 150 °C

Trimming temperature

Factory trimming already applied

After T start_T

—

–5

–3

–0.5

—

+0.3

—

0.5

120

MHz

µs

FIRC

CC T Current consumption on HV power supply

(1)

— — 1200 µA

1. The consumption reported considers the sum of the RC oscillator 16 MHz IP, and the core logic clocked by the IP during

Standby mode.

DS11701 Rev 4 45/142

Electrical characteristics

4.11.4 Low power RC oscillator

Symbol

F sirc

 f var_T

 f var_V

I sirc

T sirc

Table 24. 1024 kHz internal RC oscillator electrical characteristics

Value

C Parameter Conditions

Min Typ Max

CC T

CC P

CC T

Slow Internal

RC oscillator frequency

Frequency variation across temperature

Frequency variation across voltage

Slow Internal

RC oscillator current

Start up time, after switching

ON the internal regulator.

—

–40 °C < T <

150 °C

–40 °C < T <

150 °C

T = 55 °C

—

–9

–5

—

1024

—

SPC584Bx

Unit kHz

µA

µS

46/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

4.12 ADC system

4.12.1 ADC input description

Figure 8. Input equivalent circuit (Fast SARn and SARB channels)

INTERNAL CIRCUIT SCHEME

Channel

Selection

Sampling

SW1

EXT

SS_HV_ADR

SW1

: Channel Selection Switch Impedance

: Sampling Switch Impedance

Pin Capacitance (two contributions, C

Sampling Capacitance

and C

)

CMSW

: Common mode switch

CMRL

: Common mode resistive ladder

: Common mode voltage (~0.5 V

)

EXT

: External capacitance

The above scheme can be used as approximation circuitry for external filtering definition.

CMSW

CMRL

Common mode switch

Common mode resistive ladder

All specifications in the following table valid for the full input voltage range for the analog inputs.

20K 

LKG

INJ1

HV_ADC

Symbol

Table 25. ADC pin specification

Value

C Parameter Conditions Unit

Min Max

CC D

Internal voltage reference source impedance.

CC —

Input leakage current, two ADC channels on input-only pin.

SR —

Injection current on analog input preserving functionality at full or degraded performances.

—

See IO chapter

Table 10: I/O input electrical characteristics , parameter I

LKG

See Operating Conditions chapter

Operating conditions

, I

INJ1

Table 5:

parameter.

30 K 

SR D V

DD_HV_ADV

external capacitance.

CC D Pad capacitance

See Power Management chapter Table 33: External components integration , C

ADC

parameter.

See IO chapter Table 10: I/O input electrical characteristics , parameter C

DS11701 Rev 4 47/142

Electrical characteristics SPC584Bx

Table 25. ADC pin specification (continued)

Value

Symbol C Parameter Conditions Unit

Min Max

CC D Internal routing capacitance

SARB channels

SARn 10bit channels

SARn 12bit channels

—

0.5

1 pF

CC D SAR ADC sampling capacitance

SARn 12bit

SARn 10bit

SARB channels

SARn 10bit channels

—

1.8

0.8

SWn

CC D Analog switches resistance k 

CC D

ADC input analog switches resistance

SARn 12bit channels

SARn 12bit

SARn 10bit

—

1.8

0.8

3.2

k 

CMSW

CMRL

CC D Common mode switch resistance

CC D Common mode resistive ladder

CC D

Discharge resistance for ADC input-only pins (strong pull-down for safety)

CC D ADC digital bandgap accuracy

Sum of the two resistances

—

DD_HV_IO

= 5.0 V ± 10 % —

300 k  k 

SAFEPD

(1)

BGAP

EXT

SR —

External capacitance at the pad input pin

DD_HV_IO

= 3.3 V ± 10 % — 500 W

-1.5

+1.5

To preserve the accuracy of the ADC, it is necessary that analog input pins have low AC impedance.

Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible. This capacitor contributes to attenuating the noise present on the input pin. The impedance relative to the signal source can limit the ADC’s sample rate.

1. It enables discharge of up to 100 nF from 5 V every 300 ms. Refer to the device pinout Microsoft Excel file attached to the

IO_Definition document for the pads supporting it.

4.12.2 SAR ADC 12 bit electrical specification

Note:

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing.

The functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maximum may affect device reliability or cause permanent damage to the device.

48/142 DS11701 Rev 4

SPC584Bx Electrical characteristics f

ADCK t

ADCINIT t

ADCBIASINIT t

ADCPRECH

 V

PRECH

20K 

 V

INTREF

Symbol C

Table 26. SARn ADC electrical specification

Parameter Conditions

SR Clock frequency

SR — ADC initialization time

SR —

ADC BIAS initialization time

Standard frequency mode

High frequency mode

—

SR T ADC decharge time

Fast SAR

Slow SAR (SARDAC_B)

Decharge voltage precision

Internal voltage reference source impedance

< 150 °C

—

CC P

Internal reference voltage precision

Applies to all internal reference points

SS_HV_ADR

1/3 * V

DD_HV_ADR

2/3 * V

DD_HV_ADR

)

Min

7.5

>13.33

1.5

Value

Max

13.33

16.0

—

1/f

2/f

ADCK

—

0.25

 0.20

0.20

Unit

MHz

µs

K 

DS11701 Rev 4 49/142

Electrical characteristics SPC584Bx

Symbol

Table 26. SARn ADC electrical specification (continued)

Value

C Parameter Conditions

Min Max t

ADCSAMPLE t

ADCEVAL

ADCREFH

(5),(6)

ADCREFL

ADV_S

CC D

ADC sample time

ADC high reference current

ADC low reference current

DD_HV_ADV

power supply current

(1)

ADC evaluation time

Fast SAR – 12-bit configuration

Fast SAR – 10-bit configuration mode 1

(2)

(Standard frequency mode only)

Fast SAR – 10-bit configuration mode 2

(3)

(Standard frequency mode only)

Fast SAR – 10-bit configuration mode 3

(4)

(High frequency mode only)

Slow SAR (SARADC_B) –

12-bit configuration

Slow SAR (SARADC_B) –

10-bit configuration mode

(Standard frequency mode only)

Slow SAR (SARADC_B) –

10-bit configuration mode

2 (3)

(Standard frequency mode only)

Slow SAR (SARADC_B) –

10-bit configuration mode

(High frequency mode only)

Conversion of BIAS test channels through 20 k  input.

12-bit configuration

10-bit configuration

Run mode

(average across all codes)

Power Down mode

Run mode

DD_HV_ADR_S

 5.5 V

Power Down mode

DD_HV_ADR_S

 5.5 V

Run mode

Power Down mode

6/f

ADCK

6/f

ADCK

5/f

ADCK

6/f

ADCK

12/f

ADCK

12/f

ADCK

10/f

ADCK

12/f

ADCK

40/f

ADCK

12/f

ADCK

10/f

ADCK

—

4.0

0.04

Unit

µs

µA

µA mA

50/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Symbol

TUE

Table 26. SARn ADC electrical specification (continued)

Value

C Parameter Conditions

Min Max

Total unadjusted error in 12-bit configuration (7)

Total unadjusted error in 10-bit

configuration

the sampling window. Refer to Figure 8

< 150 °C,

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

< 150 °C,

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

< 150 °C,

DD_HV_ADV

> 3 V,

3 V > V

DD_HV_ADR_S

> 2 V

High frequency mode,

< 150 °C,

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

Mode 1, T

< 150 °C,

DD_HV_ADV

> 3 V

DD_HV_ADR_S

> 3 V

Mode 1, T

< 150 °C,

DD_HV_ADV

> 3 V,

3 V > V

DD_HV_ADR_S

> 2 V

Mode 2, T

< 150 °C,

DD_HV_ADV

> 3 V

DD_HV_ADR_S

> 3 V

Mode 3, T

< 150 °C,

DD_HV_ADV

> 3 V

DD_HV_ADR_S

> 3 V

–4

–6

–12

–1.5

–2.0

–3.0

–4.0

1.5

2.0

3.0

4.0

Unit

LSB

(12b)

LSB

(10b)

DS11701 Rev 4 51/142

Electrical characteristics SPC584Bx

Table 26. SARn ADC electrical specification (continued)

Value

Symbol C Parameter Conditions Unit

Min Max

 TUE

CC D

< V

DD_HV_ADV

DD_HV_ADR

 [0:25 mV]

 V

DD_HV_ADV



< V

DD_HV_ADV

DD_HV_ADR

 [25:50 mV]

 V

DD_HV_ADV



< V

DD_HV_ADV

DD_HV_ADR

 [50:75 mV]

 V

DD_HV_ADV



TUE degradation due to V

DD_HV_ADR with respect to offset

DD_HV_ADV

< V

DD_HV_ADV

DD_HV_ADR

 V

DD_HV_ADV



 [75:100 mV]

DD_HV_ADV

< V

DD_HV_ADR

 [0:25 mV]

 V

DD_HV_ADV



–1

–2

–4

–6

–2.5

2.5

LSB

(12b)

DD_HV_ADV

< V

DD_HV_ADR

 [25:50 mV]

 V

DD_HV_ADV



DD_HV_ADV

< V

DD_HV_ADR

 [50:75 mV]

 V

DD_HV_ADV



DD_HV_ADV

< V

DD_HV_ADR

 V

DD_HV_ADV



 [75:100 mV]

–4

–7

–12

DNL

(8)

Differential nonlinearity

Standard frequency mode,

DD_HV_ADV

> 4 V

DD_HV_ADR_S

> 4 V

High frequency mode,

DD_HV_ADV

> 4 V

DD_HV_ADR_S

> 4 V

–1

LSB

(12b)

1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within

for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration.

2. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz.

3. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz.

4. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz.

5. I

ADCREFH and I

ADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion.

6. Current parameter values are for a single ADC.

52/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

7. TUE is granted with injection current within the range defined in

, for parameters classified as T and D.

8. DNL is granted with injection current within the range defined in

, for parameters classified as T and D.

4.12.3 SAR ADC 10 bit electrical specification

Note:

The ADC comparators are 10-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing.

Symbol f

ADCK t

ADCINIT t

ADCBIASINIT t

ADCINITSBY t

ADCPRECH

 V

PRECH t

ADCSAMPLE t

ADCEVAL

ADCREFL

(4)

ADV_S

the sampling window. Refer to Figure 8

ADCREFH

(2),(3)

Table 27. ADC-Comparator electrical specification

Parameter Conditions

Clock frequency

SR — ADC initialization time

ADC high reference current

ADC low reference current

P V

DD_HV_ADV

power supply current

Standard frequency mode

High frequency mode

—

SR —

ADC BIAS initialization time

SR —

ADC initialization time in standby

Standby mode

—

Fast channel

SR T ADC precharge time

Standard channel

SR D

Precharge voltage precision

< 150 °C

P ADC sample time

(1)

ADC evaluation time

10-bit ADC mode

ADC comparator mode

10-bit ADC mode

ADC comparator mode

Run mode

(average across all codes)

Power down mode

ADC comparator mode

Run mode

DD_HV_ADR_S

 5.5 V

Power Down mode

DD_HV_ADR_S

 5.5 V

ADC comparator mode

Run mode

Power down mode

Value

Min

7.5

>13.33

1.5

Max

13.33

16.0

—

1/f

ADCK

2/f

ADCK

5/f

ADCK

2/f

ADCK

10/f

ADCK

2/f

ADCK

—

0.25

—

19.5

20.5

0.04

Unit

MHz

µs

µA

µA mA

µs

DS11701 Rev 4 53/142

Electrical characteristics SPC584Bx

Symbol

TUE

 TUE

Table 27. ADC-Comparator electrical specification (continued)

Value

C Parameter Conditions

Min Max

CC D

Total unadjusted error in 10-bit configuration

(5)

< 150 °C,

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

< 150 °C,

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

< 150 °C,

DD_HV_ADV

3 V > V

> 3 V,

DD_HV_ADR_S

> 2 V

High frequency mode,

< 150 °C,

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

< V

DD_HV_ADV

DD_HV_ADR

[0:25 mV]

 V

DD_HV_ADV



< V

DD_HV_ADV

DD_HV_ADR

[25:50 mV]

 V

DD_HV_ADV



TUE degradation due to V

DD_HV_ADR with respect to

DD_HV_ADV offset

< V

DD_HV_ADV

DD_HV_ADR

[50:75 mV]

 V

DD_HV_ADV



< V

DD_HV_ADV

DD_HV_ADR

[75:100 mV]

 V

DD_HV_ADV



DD_HV_ADV

< V

DD_HV_ADR

[0:25 mV]

 V

DD_HV_ADV



DD_HV_ADV

< V

DD_HV_ADR

[25:50 mV]

 V

DD_HV_ADV



DD_HV_ADV

< V

DD_HV_ADR

[50:75 mV]

 V

DD_HV_ADV



DD_HV_ADV

< V

DD_HV_ADR

[75:100 mV]

 V

DD_HV_ADV



–2

–3

–1.0

–2.0

–3.5

–6.0

–2.5

–4.0

–7.0

–12.0

1.0

2.0

3.5

6.0

2.5

4.0

7.0

12.0

Unit

LSB

(10b)

LSB

(10b)

54/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Symbol

Table 27. ADC-Comparator electrical specification (continued)

Value

C Parameter Conditions

Min Max

Unit

DNL

(6)

Standard frequency mode,

DD_HV_ADV

> 4 V

DD_HV_ADR_S

> 4 V

Differential non-linearity std. mode

High frequency mode,

DD_HV_ADV

> 4 V

DD_HV_ADR_S

> 4 V

–1

LSB

(10b)

for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration.

2. I

ADCREFH and I

ADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion.

3. Current parameter values are for a single ADC.

4. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC and the channel subject to current injection.

5. TUE is granted with injection current within the range defined in

, for parameters classified as T and D.

6. DNL is granted with injection current within the range defined in

, for parameters classified as T and D.

DS11701 Rev 4 55/142

Electrical characteristics SPC584Bx

4.13 Temperature sensor

The following table describes the temperature sensor electrical characteristics.

Symbol

—

SENS

ACC

Table 28. Temperature sensor electrical characteristics

Value

Parameter Conditions

CC — Temperature monitoring range

CC T Sensitivity

CC P Accuracy

—

< 150 ° C

Min

–40

—

–3

Typ

—

5.18

—

Unit

Max

150

—

°C mV/°C

°C

56/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

4.14 LFAST pad electrical characteristics

The LFAST(LVDS Fast Asynchronous Serial Transmission) pad electrical characteristics apply to high-speed debug serial interfaces on the device.

4.14.1 LFAST interface timing diagrams

Figure 9. LFAST LVDS timing definition

Signal excursions above this level NOT allowed

Max. common mode input at RX

1600 mV



VOD



Max Differential Voltage =

285 mV (LFAST)

PAD_P

Minimum Data Bit Time

Opening =

0.55 * T (LFAST)



VOD



Min Differential

Voltage =

100 mV (LFAST)

“No-Go” V

= 1.2 V +/- 10 %

TX common mode

PAD_N

 PER

EYE

ICOM

 PER

EYE

Data Bit Period

T = 1 /F

DATA

Min. common mode input at RX

Signal excursions below this level NOT allowed

150 mV

0 V

DS11701 Rev 4 57/142

Electrical characteristics

Figure 10. Power-down exit time lfast_pwr_down

Differential TX

Data Lines pad_p/pad_n t

PD2NM_TX

Data Valid

SPC584Bx

Figure 11. Rise/fall time

Differential TX

Data Lines pad_p/pad_n

|  VOD(min)|

|  VOD(min)| t

TR t

4.14.2 LFAST LVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.

Symbol

Table 29. LVDS pad startup and receiver electrical characteristics

(1),(2)

Value

C Parameter Conditions

Min Typ t

STRT_BIAS t

PD2NM_TX

CC T

STARTUP

(3),(4)

Bias current reference startup time

(5)

Transmitter startup time (power down to normal mode)

(6)

—

0.5

0.4

Max

2.75

Unit

 s

58/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Table 29. LVDS pad startup and receiver electrical characteristics (1),(2) (continued)

Value

Symbol C Parameter Conditions

Min Typ Max

Unit t t t

SM2NM_TX

PD2NM_RX

PD2SM_RX

LVDS_BIAS

DIFF

CC T

Transmitter startup time (sleep mode to normal mode)

(7)

Receiver startup time (power down to normal mode)

(8)

CC T

Receiver startup time (power down to sleep mode)

(9)

CC D LVDS bias current consumption

SR D

Not applicable to the

MSC/DSPI LVDS pad

—

Not applicable to the

MSC/DSPI LVDS pad

Tx or Rx enabled

—

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Transmission line characteristic impedance

— 47.5

Transmission line differential impedance

— 95

RECEIVER

SR T Common mode voltage —

0.15

(10)

0.4

—

100

0.6

0.95

52.5

105

µs ns ns mA



ICOM

— 1.6

(11)

| 

HYS

SR T

CC T

Differential input voltage

Input hysteresis

(12)

—

100

—

— mV mV

CC D Terminating resistance V

DD_HV_IO

= 5.0 V ±

10 %

-40 ° C < T

< 150 ° C

DD_HV_IO

= 3.3 V ±

10 %

-40 ° C < T

< 150 ° C

—

150

175



CC D Differential input capacitance

(13)

— 3.5

6.0

LVDS_RX

CC C

Receiver DC current consumption

Enabled — — 1.6

PIN_RX

CC D

Maximum consumption on receiver input pin



= 400 mV,

= 80 

— — 5 mA

1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed Debug

(HSD) LVDS pad.

2. All LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS control registers (LCR) of the LFAST and High-speed Debug modules. The value of the LCR bits for the LFAST/HSD modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for

MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding

SIUL2 MSCR ODC field.

4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter electrical characteristic tables.

5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being enabled.

6. Total transmitter startup time from power down to normal mode is t ods.

STRT_BIAS

+ t

PD2NM_TX

+ 2 peripheral bridge clock peri-

7. Total transmitter startup time from sleep mode to normal mode is t remains enabled in sleep mode.

SM2NM_TX

+ 2 peripheral bridge clock periods. Bias block

DS11701 Rev 4 59/142

Electrical characteristics SPC584Bx

8. Total receiver startup time from power down to normal mode is t

STRT_BIAS

+ t

PD2NM_RX

+ 2 peripheral bridge clock periods.

9. Total receiver startup time from power down to sleep mode is t mains enabled in sleep mode.

PD2SM_RX

+ 2 peripheral bridge clock periods. Bias block re-

10. Absolute min = 0.15 V – (285 mV/2) = 0 V

11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V

12. Value valid for LFAST mode. The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure proper LFAST receive timing.

13. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.

Symbol C

Table 30. LFAST transmitter electrical characteristics (1),(2),(3)

Value

Parameter Conditions

Min Typ

Unit

Max

I f

DATA

V t

| 

VOD

LVDS_TX

PIN_TX

SR D

CC P

CC T

Data rate

Common mode voltage

Differential output voltage swing

(terminated)

(4),(5)

Rise time from -|  VOD(min)| to

+|  VOD(min)|. Fall time from

+|  VOD(min)| to -|  VOD(min)|

—

1.08

110

0.26

SR D

External lumped differential load capacitance

CC C Transmitter DC current consumption

CC D

Transmitter DC current sourced through output pin

DD_HV_IO

= 4.5 V —

DD_HV_IO

= 3.0 V —

Enabled —

— 1.1

—

320

1.32

285

1.25

6.0

4.0

3.6

2.85

1. This table is applicable to LFAST LVDS pads used in LFAST configuration (SIUL2_MSCR_IO_n.ODC=101).

2. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance values shown in

Figure 12 .

3. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

4. Valid for maximum data rate f

Figure 12 .

DATA

. Value given is the capacitance on each terminal of the differential pair, as shown in

5. Valid for maximum external load C

Mbps

V mV ns pF mA mA

60/142 DS11701 Rev 4

SPC584Bx

GPIO Driver

LVDS Driver

Electrical characteristics

Figure 12. LVDS pad external load diagram

Die Package PCB

2.5pF

1pF C

100  terminator

GPIO Driver

1pF C

2.5pF

4.14.3 LFAST PLL electrical characteristics

The following table contains the electrical characteristics for the LFAST PLL.

Table 31. LFAST PLL electrical characteristics

(1)

Value

Symbol C Parameter Conditions f

RF_REF

ERR

REF

PN f

VCO t

LOCK

SR D PLL reference clock frequency (CLKIN)

CC D PLL reference clock frequency error

CC D PLL reference clock duty cycle (CLKIN)

CC D

CC P

Integrated phase noise

(single side band)

PLL VCO frequency

CC D PLL phase lock

—

— f

RF_REF

= 20 MHz

—

Min

(2)

-1

—

312

—

Typ

—

Unit

Max

30 MHz

-58 dBc

320 (3)

150

(4)

MHz

µs

DS11701 Rev 4 61/142

Electrical characteristics SPC584Bx

Symbol C

Table 31. LFAST PLL electrical characteristics (1) (continued)

Value

Parameter Conditions

Min Typ

Unit

Max

 PER

REF

Input reference clock jitter (peak to peak) f

Single period,

RF_REF

= 20 MHz f

Long term,

RF_REF

= 20 MHz

—

-500

—

350

500 ps ps

 PER

EYE

CC T Output Eye Jitter (peak to peak) (5) — — 400 ps

1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.

2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1.

3. The 320 MHz frequency is achieved with a 20 MHz reference clock.

4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral bridge clock that is connected to the PLL on the device (to set the PLL enable bit).

5. Measured at the transmitter output across a 100  termination resistor on a device evaluation board. See

Figure 12 .

62/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

4.15 Power management

The power management module monitors the different power supplies as well as it generates the required internal supplies. The device can operate in the following configurations:

Device

External regulator

Table 32. Power management regulators

Internal

SMPS regulator

—

Internal linear regulator external ballast

(2)

Internal linear regulator internal ballast

Auxiliary regulator

Clamp regulator

Internal standby regulator

(1)

SPC584Bx — X X

1. Standby regulator is automatically activated when the device enters standby mode.

2. For compatibility purpose with SPC584Cx/SPC58ECx, or for the optimization of the power dissipation, the operability of the device with external ballast can be used. The external ballast option is available only on specific devices, contact the local sales.

4.15.1 Power management integration

Use the integration schemes provided below to ensure the proper device function, according to the selected regulator configuration.

The internal regulators are supplied by V

DD_HV_IO_MAIN

DD_LV

supply.

supply and are used to generate

Place capacitances on the board as near as possible to the associated pins and limit the serial inductance of the board to less than 5 nH.

It is recommended to use the internal regulators only to supply the device itself.

DS11701 Rev 4 63/142

Electrical characteristics

9''B+9

Figure 13. Internal regulator with external ballast mode

)/$

(;7

SPC584Bx

(

9''B+9B,2

+9Q

0DLQ5HJ

966

9''B/9

$X[5HJ

/9Q

966

&ODPS5HJ

9''B+9B$'9 966B+9B$'9

$'&

64/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Figure 14. Internal regulator with internal ballast mode

)/$

(

/9Q

0DLQ5HJ

9''B+9B,2

966

9''B/9

$X[5HJ

966

966B+9B$'9

&ODPS5HJ

9''B+9B$'9

$'&

+9Q

DS11701 Rev 4 65/142

Electrical characteristics

9''B+9

(;7

Figure 15. Standby regulator with external ballast mode

)/$

SPC584Bx

(

9''B+9B,2

+9Q

6WDQGE\UHJ

966

9''B/9

/9Q

966

966B+9B$'9 9''B+9B$'9

$'&

66/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Figure 16. Standby regulator with internal ballast mode

)/$

(

9''B/9

6WDQGE\ 5HJ

9''B+9B,2

966

+9Q

/9Q

966

966B+9B$'9 9''B+9B$'9

$'&

Table 33. External components integration

Symbol

LVn

HVn

C Parameter Conditions

(1)

Min

Value

Typ Max

Unit

Common Components

SR D

Internal voltage regulator stability external capacitance

(2) (3)

Stability capacitor equivalent serial resistance

Internal voltage regulator decoupling external capacitance

(4) (5)

—

Total resistance including board track

Each V

DD_LV

pair

SR D

Stability capacitor equivalent serial resistance

—

SR D Bulk capacitance for HV supply

on one V

DD_HV_IO_MAIN

pair

SR D

Decoupling capacitance for

ballast and IOs

on all V

DD_HV_IO

DD_HV_ADR

and

pairs

1.1

—

2.2

—

4.7

100

3.0

—

µF m m

 nF



µF nF

DS11701 Rev 4 67/142

Electrical characteristics SPC584Bx

Table 33. External components integration (continued)

Symbol

FLA

ADC

C Parameter Conditions

(1)

Min

SR D

Decoupling capacitance for Flash supply

(6)

ADC supply external capacitance

—

DD_HV_ADV/ pair.

SS_HV_ADV

Internal Linear Regulator with External Ballast Mode

—

Value

Typ

Max

—

EXT

SR D

Recommended external NPN transistors

NJD2873T4, BCP68

SR D

External NPN transistor collector voltage

— 2.0

—

DD_

HV_IO

_MAIN

SR D

Internal voltage regulator stability external capacitance on ballast

base

The monitors and their associated levels for the device are given in Table 38

(7)

SR D

Stability capacitor equivalent serial resistance

—

Total resistance including board track

—

2.2

—

1. V

= 3.3 V ± 10 % / 5.0 V ± 10 %, T

= –40 / 150 °C, unless otherwise specified.

2. Recommended X7R or X5R ceramic –50 % / +35 % variation across process, temperature, voltage and after aging.

3. CE capacitance is required both in internal and external regulator mode.

4. For noise filtering, add a high frequency bypass capacitance of 10 nF.

5. For applications it is recommended to implement at least 5 C

capacitances.

6. Recommended X7R capacitors. For noise filtering, add a high frequency bypass capacitance of 100 nF.

7. CB capacitance is required if only the external ballast is implemented.

Unit nF

µF

µF m 

68/142 DS11701 Rev 4

SPC584Bx

4.15.2 Voltage regulators

Table 34. Linear regulator specifications

Symbol C Parameter Conditions

MREG

CC P

Main regulator output voltage

Power-up, before trimming, no load

After trimming, maximum load

Main regulator current provided to

DD_LV

domain

Internal ballast

IDD

 IDD

MREG

CLAMP

MREGINT

CC T

The maximum current supported is the sum of the Main Regulator and the Auxiliary Regulator maximum current both regulators are working in parallel.

External ballast

CC D

CC T

Main regulator rush current sinked from V

DD_HV_IO_MAIN domain during V

DD_LV loading

domain

Main regulator output current variation

D Main regulator current

D consumption

Power-up condition

20 µs observation window

MREG

= max

= 0 mA

Electrical characteristics

Min

Value

Typ Max

Unit

1.14

1.22

1.30

1.09

1.19

1.24

— — 325

—

— 450 mA

— 150 mA

-100

—

100 mA

— mA

Symbol

AUX

IDD

AUX

 IDD

AUX

AUXINT

Table 35. Auxiliary regulator specifications

C Parameter Conditions

Min

Value

Typ Max

Unit

CC P Aux regulator output voltage

After trimming, internal regulator mode

CC T

Aux regulator current provided to

DD_LV

domain

CC T Aux regulator current variation

D Aux regulator current

D consumption

—

20 µs observation window

MREG

= max

MREG

= 0 mA

1.09

—

-100

—

1.19

—

1.22

150

100

1.1

V mA mA mA

DS11701 Rev 4 69/142

Electrical characteristics SPC584Bx

Table 36. Clamp regulator specifications

Symbol C Parameter Conditions

Min

Value

Typ Max

Unit

1.18

1.22

1.33

V V

CLAMP

CC P Clamp regulator output voltage

 IDD

CLAMP

CC T Clamp regulator current variation

CLAMPINT

CC D

Clamp regulator current consumption

After trimming, internal regulator mode

20 µs observation window

MREG

= 0 mA

-100

—

100

0.7

mA mA

Symbol C

Table 37. Standby regulator specifications

Parameter Conditions

SBY

IDD

SBY

CC P Standby regulator output voltage

CC T

Standby regulator current provided to V

DD_LV

domain

After trimming, maximum load

External Ballast

Internal Ballast

Min

Value

Typ Max

Unit

1.02

1.06

1.26

—

V mA

4.15.3 Voltage monitors

Figure 17

illustrates the workings of voltage monitoring threshold.

70/142 DS11701 Rev 4

SPC584Bx

DD_xxx

HVD

LVD

HVD TRIGGER

(INTERNAL)

Electrical characteristics

Figure 17. Voltage monitor threshold definition

VMFILTER

LVD TRIGGER

(INTERNAL)

Symbol C

Table 38. Voltage monitor electrical characteristics

Supply/Parameter

(1)

Conditions

Min

Value

(2)

Typ Max

Unit

MVD270_C

MVD270_F

MVD270_SBY

POR200_C

LVD290_C

LVD290_F

LVD290_AS

LVD290_IF

LVD400_AS

PowerOn Reset HV

CC P V

DD_HV_IO_MAIN

—

Minimum Voltage Detectors HV

CC P V

DD_HV_IO_MAIN

CC P V

DD_HV_FLA

—

CC P V

DD_HV_IO_MAIN

(in Standby)

Low Voltage Detectors HV

—

— CC P V

DD_HV_IO_MAIN

CC P V

DD_HV_FLA

CC P V

DD_HV_ADV

(ADCSAR pad)

CC P V

DD_HV_IO_ETH

CC P V

DD_HV_ADV

(ADCSAR pad)

—

1.80

2.71

2.89

4.15

2.18

2.76

2.94

4.23

2.40

2.80

2.99

4.31

DS11701 Rev 4 71/142

Electrical characteristics SPC584Bx

Symbol

Table 38. Voltage monitor electrical characteristics (continued)

Value (2)

C Supply/Parameter

(1)

Conditions

Min Typ

Unit

Max

LVD400_IM

LVD400_IF

HVD400_IF

UVD600_F

UVD600_IF

POR031_C

MVD082_C

MVD094_C

MVD094_FA

MVD094_FB

CC P V

DD_HV_IO_MAIN

DD_HV_IO_ETH

DD_HV_FLA

DD_HV_IO_ETH

DD_LV

CC P V

DD_LV

CC P V

DD_LV

(Flash)

—

High Voltage Detectors HV

—

Upper Voltage Detectors HV

—

PowerOn Reset LV

—

Minimum Voltage Detectors LV

—

Low Voltage Detectors LV

—

4.15

3.68

5.72

0.29

0.85

0.98

1.00

4.23

3.75

5.82

0.60

0.88

1.00

1.02

4.31

3.82

5.92

0.97

0.91

1.02

1.04

LVD100_C

LVD100_SB

LVD100_F

HVD134_C

CC P V

DD_LV

CC P V

DD_LV

(In Standby)

CC P V

DD_LV

(Flash)

High Voltage Detectors LV

—

CC P V

DD_LV

—

Upper Voltage Detectors LV

1.06

0.99

1.08

1.28

1.08

1.01

1.10

1.31

1.11

1.03

1.12

1.33

UVD140_C

UVD140_F

CC P V

DD_LV

CC P V

DD_LV

(Flash)

—

1.34

1.37

1.39

Common

VMFILTER

CC D Voltage monitor filter

(3)

— 5 — 25

1. Even if LVD/HVD monitor reaction is configurable, the application ensures that the device remains in the operative condition range, and the internal LVDx monitors are disabled by the application. Then an external voltage monitor with minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented.

For HVDx, if the application disables them, then they need to grant that VDD_LV and VDD_HV voltage levels stay withing the limitations provided in

Section 4.2: Absolute maximum ratings .

2. The values reported are Trimmed values, where applicable.

3. See

Figure 17

. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be delayed by T

VMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to temperature, process and voltage variations.

 s

72/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

4.16 Flash

The following table shows the Wait state configuration.

APC

000

(1)

100

(2)

001

(3)

Table 39. Wait state configuration

RWSC Frequency range (MHz)

2 f < 30 f < 60 f < 90 f < 120 f < 30 f < 60 f < 90 f < 120

55  f < 80

55  f < 120

1. STD pipelined, no address anticipation.

2. No pipeline (STD + 1 Tck).

3. Pipeline with 1 Tck address anticipation.

Symbol

The following table shows the Program/Erase characteristics.

Table 40. Flash memory program and erase specifications

Value

Characteristics

(1)(2)

Typ

(3)

Initial max

25 °C

(6)

All temp

(7)

Lifetime max

(5)

Typical end of life

(4)

< 1 K cycles

< 250 K cycles

Unit t t dwprogram pprogram t pprogrameep t qprogram t qprogrameep

Double Word (64 bits) program time [Packaged part]

Page (256 bits) program time

Data Flash - EEPROM

(partition 1) [Packaged part]

Quad Page (1024 bits) program time

Quad Page (1024 bits) program time Data Flash -

EEPROM (partition 1)

[Packaged part]

130

240

264

—

140

240

276

220 C 1040 1200 P 850

245 C 1140 1320 P 978

500

1000

2000

C µs

DS11701 Rev 4 73/142

Electrical characteristics SPC584Bx

Symbol

Table 40. Flash memory program and erase specifications (continued)

Value

Characteristics

(1)(2)

Typ

(3)

Initial max

25 °C

(6)

All temp

(7)

Lifetime max

(5)

Typical end of life

(4)

< 1 K cycles

< 250 K cycles

Unit t t t t

16kpperase

32kpperase

64kpperase

128kpperase

16 KB block pre-program and erase time

32 KB block pre-program and erase time

64 KB block pre-program and erase time

128 KB block pre-program and erase time t

256kpperase t

16kprogram t

32kprogram t

64kprogram t

128kprogram t

256kprogram

256 KB block pre-program and erase time

16 KB block program time

32 KB block program time

64 KB block program time

128 KB block program time t

16kprogrameep

256 KB block program time

Program 16 KB Data Flash -

EEPROM (partition 1)

[Packaged part] t

16kprogrameep t t

16keraseeep

Erase 16 KB Data Flash -

EEPROM (partition 1)

[Packaged part]

Program 16 KB HSM Data

Flash - EEPROM (partition 1)

[Packaged part]

Erase 16 KB HSM Data Flash

- EEPROM (partition 1)

[Packaged part]

190

250

360

600

450

520

700

1300

500

600

750

1600

220

290

420

800

1050 C 1800 2400 P 1600 4000

100

200

400

220

175

350

700

495

100

200

430

850

550

150

300

590

400

1000

1200

1600

4000

1000

1200

1600

2000

4000

1750

3600

1750

3600

—

— t prr

Program rate

(8)

2.2

C 2.8

3.40

C 2.4

—

C ms

C ms t pr t tprfm t erfm t ffprogram

Erase rate

4.8

C 7.2

Program rate Factory Mode

1.12

C 1.4

Erase rate Factory Mode

Full flash programming time

(9)

4.0

C 5.2

3.45

C 6.0

9.6

1.6

5.8

7.3

6.4

—

5.1

—

C s/M

B s/M

C s/M

C s

C ms

74/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Table 40. Flash memory program and erase specifications (continued)

Value

Symbol Characteristics

(1)(2)

Typ

(3)

Initial max

25 °C

(6)

All temp

(7)

Lifetime max

(5)

Typical end of life

(4)

< 1 K cycles

< 250 K cycles

Unit t t t t t t t t t fferase

ESRT

PSRT

AMRT

PSUS

ESUS

AIC0S

AIC256KS t t

AIC0P

MR0S

MR256KS

Full flash erasing time

Erase suspend request rate

(10)

Program suspend request

rate

Array Integrity Check - Margin

Read suspend request rate

Program suspend latency (11)

Erase suspend latency

(11)

Array Integrity Check (2.0 MB, sequential)

(12)

Array Integrity Check (256

KB, sequential)

Array Integrity Check (2.0 MB, proprietary)

Margin Read (2.0 MB, sequential)

Margin Read (256 KB, sequential)

1. These specifications apply to JTAG boundary scan only. See Table 43 for functional specifications.

9.9

200

—

12.8

1.5

4.0

—

18.1

—

23.3

—

14.3

—

— µs

µs

— ms

— s

— ms

1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column.

2. Actual hardware operation times; this does not include software overhead.

3. Typical program and erase times assume nominal supply values and operation at 25 °C.

4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but not tested.

5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.

6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5 %) supply voltages.

7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5 %) supply voltages.

8. Rate computed based on 256 KB sectors.

9. Only code sectors, not including EEPROM.

10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.

11. Timings guaranteed by design.

12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the table is calculated at max frequency.

DS11701 Rev 4 75/142

Electrical characteristics SPC584Bx

All the Flash operations require the presence of the system clock for internal synchronization. About 50 synchronization cycles are needed: this means that the timings of the previous table can be longer if a low frequency system clock is used.

Symbol

Table 41. Flash memory life specification

Value

Characteristics

(1) (2)

Min C Typ C

Unit

CER16K

CER32K

CER64K

CER128K

CER256K

DER16K

DER16K t

DR1k

16 KB CODE Flash endurance

32 KB CODE Flash endurance

64 KB CODE Flash endurance

128 KB CODE Flash endurance

256 KB CODE Flash endurance

(3)

16 KB DATA EEPROM Flash endurance

16 KB HSM DATA EEPROM Flash endurance

Minimum data retention Blocks with 0 - 1,000 P/E cycles t

DR10k

Minimum data retention Blocks with 1,001 - 10,000

P/E cycles t t

DR100k

DR250k

Minimum data retention Blocks with 10,001 - 100,000

P/E cycles

Minimum data retention Blocks with 100,001 -

250,000 P/E cycles

100

—

100

—

— Kcycles

10 — 100 — Kcycles

1 — 100 — Kcycles

10 — 100 — Kcycles

250 — — — Kcycles

— Kcycles

—

Years

1. Program and erase cycles supported across specified temperature specifications.

2. It is recommended that the application enables the core cache memory.

3. 10K cycles on 4-256 KB blocks is not intended for production. Reduced reliability and degraded erase time are possible.

76/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

4.17 AC specifications

All AC timing specifications are valid up to 150 °C, except where explicitly noted.

4.17.1 Debug and calibration interface timing

4.17.1.1 JTAG interface timing

Table 42. JTAG pin AC electrical characteristics

Value

(1) , (2)

# Symbol C Characteristic Unit

Min Max

2 t

JCYC t

JDC

3 t

TCKRISE

4 t

TMSS, t

TDIS

5 t

TMSH, t

TDIH

6 t

TDOV

10 t

TDOI t

TDOHZ t

JCMPPW t

JCMPS

15 t

BSDV t

BSDVZ t

BSDHZ t

BSDST t

BSDHT

CC D TCK cycle time

CC T TCK clock pulse width

CC D TCK rise and fall times (40 %–70 %)

CC D TMS, TDI data setup time

CC D TMS, TDI data hold time

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

CC D TCK low to TDO high impedance

CC D JCOMP assertion time

CC D JCOMP setup time to TCK low

CC D TCK falling edge to output valid

CC D TCK falling edge to output valid out of high impedance

CC D TCK falling edge to output high impedance

CC D Boundary scan input valid to TCK rising edge

CC D TCK rising edge to boundary scan input invalid

100

—

100

—

(3)

—

600

(4)

600

—

— ns

% ns ns ns ns ns ns ns ns ns ns ns ns ns

2. JTAG timing specified at V

DD_HV_IO_JTAG datasheet.

= 4.0 to 5.5 V and max. loading per pad type as specified in the I/O section of the

3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

DS11701 Rev 4 77/142

101

Electrical characteristics

Figure 18. JTAG test clock input timing

SPC584Bx

TCK

1 3

Figure 19. JTAG test access port timing

TCK

TMS, TDI

7 8

TDO

78/142 DS11701 Rev 4

SPC584Bx

Figure 20. JTAG JCOMP timing

Electrical characteristics

TCK

JCOMP

TCK

Output

Signals

Output

Signals

Figure 21. JTAG boundary scan timing

Input

Signals

DS11701 Rev 4 79/142

101

Electrical characteristics SPC584Bx

4.17.1.2 Nexus interface timing

Table 43. Nexus debug port timing

14 t

16 t t

Symbol

7 t

EVTIPW

8 t

EVTOPW

TCYC

NTDIS

12 t

NTDIH

13 t

NTMSS

NTMSH

—

C Characteristic

CC D EVTI pulse width

CC D EVTO pulse width

CC D

TCK cycle time

Absolute minimum TCK cycle time (5)

(TDO sampled on posedge of TCK)

Absolute minimum TCK cycle time

(7)

(TDO sampled on negedge of TCK)

CC D TDI data setup time

CC D TDI data hold time

CC D TMS data setup time

CC D TMS data hold time

CC D TDO propagation delay from falling edge of TCK

(8)

CC D

TDO hold time with respect to TCK falling edge

(minimum TDO propagation delay)

Value

(1)

Min Max

(3),(4)

(6)

—

2.25

— t

—

— t

—

Unit

CYC

(2) ns

CYC

DSPI channel frequency support is shown in Table 45

ns ns

1. Nexus timing specified at V section of the data sheet.

DD_HV_IO_JTAG

= 3.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O

2. t

CYC

is system clock period.

3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number greater than or equal to that specified here.

4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute minimum TCK period specification.

5. This value is TDO propagation time 36 ns + 4 ns setup time to sampling edge.

6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used.

7. This value is TDO propagation time 16 ns + 4 ns setup time to sampling edge.

8. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

ns ns ns ns ns

80/142 DS11701 Rev 4

TCK

EVTI

EVTO

TCK

EVTI

EVTO

SPC584Bx

MCKO

MDO

MSEO

EVTO

Figure 22. Nexus output timing

Electrical characteristics

Output Data Valid

Figure 23. Nexus event trigger and test clock timings

9 7

DS11701 Rev 4 81/142

101

Electrical characteristics SPC584Bx

Figure 24. Nexus TDI, TMS, TDO timing

TCK

TMS, TDI

TDO

4.17.1.3 External interrupt timing (IRQ pin)

Characteristic

Table 44. External interrupt timing

Symbol Min

IRQ Pulse Width Low

IRQ Pulse Width High

IRQ Edge to Edge Time

(1) t

IPWL t

IPWH t

ICYC

1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

Max

—

Unit t cyc t cyc t cyc

82/142 DS11701 Rev 4

SPC584Bx

Figure 25. External interrupt timing

Electrical characteristics

IRQ

1 2

Figure 26. External interrupt timing

D_CLKOUT

IRQ

1 2

4.17.2 DSPI timing with CMOS pads

Timing specifications are shown in the tables below.

DS11701 Rev 4 83/142

101

Electrical characteristics SPC584Bx

Table 45. DSPI channel frequency support

DSPI use mode

(1)

Max usable frequency

(MHz) (2),(3)

CMOS (Master mode)

Full duplex – Classic timing (

Table 46

Full duplex – Modified timing (

)

Table 47 )

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

DSPI_5, DSPI_6,

DSPI_4

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

DSPI_5, DSPI_6,

DSPI_4

Output only mode (SCK/SOUT/PCS) ( Table 46 and

Table 47

)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

DSPI_5, DSPI_6,

DSPI_4

Output only mode TSB mode (SCK/SOUT/PCS)

CMOS (Slave mode Full duplex) (

Table 48

)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

DSPI_5, DSPI_6,

DSPI_4

—

1. Each DSPI module can be configured to use different pins for the interface. Refer to the device pinout Microsoft Excel file attached to the IO_Definition document for the available combinations. It is not possible to reach the maximum performance with every possible combination of pins.

2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

3. Maximum usable frequency does not take into account external device propagation delay.

4.17.2.1 DSPI master mode full duplex timing with CMOS pads

4.17.2.1.1 DSPI CMOS master mode – classic timing

Note: In the following table, all output timing is worst case and includes the mismatching of rise and fall times of the output pads.

Table 46. DSPI CMOS master classic timing (full duplex and output only)

MTFE = 0, CPHA = 0 or 1

Condition Value

(1)

Symbol C Characteristic

Pad drive

(2)

Load (C

) Min Max

1 t

SCK

CC D SCK cycle time

SCK drive strength

Very strong

Strong

Medium

25 pF

50 pF

59.0

80.0

200.0

—

Unit ns

84/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Table 46. DSPI CMOS master classic timing (full duplex and output only)

MTFE = 0, CPHA = 0 or 1 (continued)

Condition Value (1)

Symbol C Characteristic

Pad drive

(2)

Load (C

) Min Max

SCK and PCS drive strength

2 t

CSC

CC D

PCS to SCK delay

Very strong

Strong

Medium

25 pF

50 pF

(3)

× t

SYS

(4)

) –

—

3 t

ASC

4 t

SDC

5 t

PCSC

6 t

PASC

7 t

SUI

CC D After SCK delay

PCS medium and SCK strong

PCS = 50 pF

SCK = 50 pF

SCK and PCS drive strength

Very strong

Strong

Medium

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

CC D

SCK duty cycle

(6)

PCSx to PCSS time

(7)

PCS medium and SCK strong

PCS = 0 pF

SCK = 50 pF

SCK drive strength

Very strong

Strong

Medium

0 pF

PCS strobe timing

PCS and PCSS drive strength

Strong 25 pF

CC D

PCSS to PCSx time

PCS and PCSS drive strength

Strong 25 pF

SIN setup time

CC D

SIN setup time to

SCK

(8)

SCK drive strength

Very strong

Strong

25 pF

50 pF

Medium 50 pF

(5)

× t

) –

× t

) –

× t

) –

× t

) –

2 t

SCK

– 2

1 /

2 t

SCK

– 2

2 t

SCK

– 5

16.0

25.0

31.0

52.0

—

2 t

SCK

+ 2

1 /

2 t

SCK

+ 2

2 t

SCK

+ 5

—

Unit ns ns ns ns ns ns

DS11701 Rev 4 85/142

101

Electrical characteristics SPC584Bx

Table 46. DSPI CMOS master classic timing (full duplex and output only)

MTFE = 0, CPHA = 0 or 1 (continued)

Condition Value (1)

Symbol C Characteristic

Pad drive

(2)

Load (C

) Min Max

SIN hold time

Unit

8 t

CC D

SIN hold time from SCK

SCK drive strength

Very strong 0 pF

Strong

Medium

0 pF

–1.0

—

— ns

9 t

SUO

SOUT data valid time (after SCK edge)

SOUT and SCK drive strength

CC D

SOUT data valid time from SCK

(9)

Very strong

Strong

25 pF

50 pF

—

7.0

8.0

16.0

10 t

CC D

SOUT data hold time after SCK

Medium 50 pF

SOUT data hold time (after SCK edge)

SOUT and SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

–7.7

–11.0

–15.0

—

— ns

All timing values for output signals in this table are measured to 50 % of the output voltage.

Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

t t

SYS

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min

= 10 ns).

M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

SDC

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

PCSx and PCSS using same pad configuration.

Input timing assumes an input slew rate of 1 ns (10 % – 90 %) and uses TTL voltage thresholds.

SOUT Data v alid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

86/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Figure 27. DSPI CMOS master mode — classic timing, CPHA = 0 t

CSC t

ASC

PCSx t

SDC t

SCK

SCK Output

(CPOL = 0) t

SDC

SCK Output

(CPOL = 1) t

SUI t

SIN First Data

SOUT First Data

Data t

SUO

Data

Last Data t

Last Data

Figure 28. DSPI CMOS master mode — classic timing, CPHA = 1

3&6[

6&.2XWSXW

&32/

6&.2XWSXW

&3 2/

6,1

6287

68,

)LUVW'DWD

'DWD

682

'DWD

/DVW'DWD

DS11701 Rev 4 87/142

101

Electrical characteristics

Figure 29. DSPI PCS strobe (PCSS) timing (master mode) t

PCSC t

PASC

PCSS

PCSx

SPC584Bx

4.17.2.1.2 DSPI CMOS master mode — modified timing

Note: In the following table, all output timing is worst case and includes the mismatching of rise and fall times of the output pads.

Table 47. DSPI CMOS master modified timing (full duplex and output only)

MTFE = 1, CPHA = 0 or 1

Value

(1)

# Symbol C Characteristic

Condition

Pad drive

(2)

Load (C

) Min Max

1 t

SCK

2 t

CSC

3 t

ASC

CC D SCK cycle time

CC D

PCS to SCK delay

CC D After SCK delay

SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

SCK and PCS drive strength

Very strong 25 pF

Strong 50 pF

Medium

PCS medium and

SCK strong

50 pF

PCS = 50 pF

SCK = 50 pF

SCK and PCS drive strength

Very strong

PCS = 0 pF

SCK = 50 pF

Strong

Medium

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS medium and

SCK strong

PCS = 0 pF

SCK = 50 pF

33.0

80.0

200.0

(3)

× t

SYS

(4)

) – 16

SYS

SYS

SYS

(5)

× t

) – 35

) – 35

) – 35

) – 35

—

Unit ns ns ns

88/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Table 47. DSPI CMOS master modified timing (full duplex and output only)

MTFE = 1, CPHA = 0 or 1 (continued)

Condition Value (1)

# Symbol C Characteristic

Pad drive

(2)

Load (C

) Min Max

SCK drive strength

4 t

SDC

CC D SCK duty cycle

(6)

Very strong 0 pF

Strong 0 pF

Medium 0 pF

PCS strobe timing

2 t

SCK

– 2

2 t

SCK

– 2

2 t

SCK

– 5

2 t

SCK

+ 2

2 t

SCK

+ 2

2 t

SCK

+ 5

5 t

PCSC

6 t

PASC

7 t

SUI

8 t

CC D

PCSx to PCSS time

(7)

PCSS to PCSx

time

PCS and PCSS drive strength

Strong 25 pF

PCS and PCSS drive strength

Strong 25 pF

SIN setup time

CC D

SCK drive strength

SIN setup time to

SCK

CPHA = 0

(8)

Very strong 25 pF

Strong 50 pF

Medium 50 pF

SCK drive strength

SIN setup time to

SCK

CPHA = 1

Very strong

Strong

25 pF

50 pF

Medium 50 pF

SIN hold time

SIN hold time from SCK

CPHA = 0

SCK drive strength

Very strong 0 pF

Strong 0 pF

CC D

SIN hold time from SCK

CPHA = 1

Medium 0 pF

SCK drive strength

Very strong 0 pF

Strong

Medium

0 pF

16.0

25 – (P

(9)

× t

)

× t

)

× t

)

25.0

31.0

52.0

–1 + (P

× t

SYS

)

–1 + (P

× t

SYS

)

–1 + (P

× t

SYS

)

–1.0

—

Unit ns ns ns ns ns ns ns

DS11701 Rev 4 89/142

101

Electrical characteristics SPC584Bx

Table 47. DSPI CMOS master modified timing (full duplex and output only)

MTFE = 1, CPHA = 0 or 1 (continued)

Condition Value (1)

# Symbol C Characteristic

Pad drive

(2)

Load (C

) Min Max

SOUT data valid time (after SCK edge)

9 t

SUO

10 t

CC D

SOUT data valid time from SCK

CPHA = 0,

SOUT and SCK drive strength

Very strong

Strong

25 pF

50 pF

SOUT data valid time from SCK

CPHA = 1

Medium

Very strong

50 pF

SOUT and SCK drive strength

25 pF

Strong

Medium

50 pF

SOUT data hold time (after SCK edge)

—

SOUT and SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

CC D

SOUT data hold time after SCK

CPHA = 0

(10)

–7.7 + t

–11.0 + t

–15.0 + t

SYS

SOUT data hold time after SCK

CPHA = 1

SOUT and SCK drive strength

Very strong 25 pF

Strong 50 pF

Medium 50 pF

–7.7

–11.0

–15.0

7.0 + t

8.0 + t

16.0 + t

SYS

7.0

8.0

16.0

—

Unit ns ns ns ns

1. All timing values for output signals in this table are measured to 50 % of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

4. t t

SYS

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min

= 10 ns).

5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

6. t

SDC

7. PCSx and PCSS using same pad configuration.

8. Input timing assumes an input slew rate of 1 ns (10 % – 90 %) and uses TTL voltage thresholds.

9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_

MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1.

90/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

10.

SOUT Data v alid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

Figure 30. DSPI CMOS master mode — modified timing, CPHA = 0 t

CSC t

ASC

PCSx t

SDC t

SCK

SCK Output

(CPOL = 0) t

SDC

SCK Output

(CPOL = 1) t

SUI t

SIN

SOUT

First Data

Data t

SUO

Data

Last Data t

Last Data

Figure 31. DSPI CMOS master mode — modified timing, CPHA = 1

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

SOUT t

SUI t

First Data

First Data t

SUO

Data

Data t

Last Data t

Last Data

DS11701 Rev 4 91/142

101

Electrical characteristics

Figure 32. DSPI PCS strobe (PCSS) timing (master mode) t

PCSC t

PASC

PCSS

PCSx

SPC584Bx

4.17.2.2 Slave mode timing

Table 48. DSPI CMOS slave timing — full duplex — normal and modified transfer formats

(MTFE = 0/1)

Condition

Symbol C Characteristic Min Max Unit

Pad Drive Load

6 t

SCK t

CSC t

ASC t

SDC t

A t

DIS

CC D SCK Cycle Time

(1)

CC D

Slave Access Time

(2) (3)

(SS active to SOUT driven)

Slave SOUT Disable Time

(2) (3)

(SS inactive to SOUT High-

Z or invalid)

—

Very strong

Strong

Medium

Very strong

Strong

Medium

—

25 pF

50 pF

25 pF

50 pF

—

10 ns ns ns ns ns ns ns ns ns ns

10 t

SUI t

CC D

Data Setup Time for

Inputs

D Data Hold Time for Inputs

Refer to Section 5.1.1: Package mechanical drawings and data information

— —

—

— ns ns

11 t

SUO

12 t

CC D

SOUT Valid Time

(1) (2) (3)

(after SCK edge)

SOUT Hold Time

(1) (2) (3)

(after SCK edge)

—

Very strong

Strong

Medium

Very strong

Strong

Medium

25 pF

50 pF

25 pF

50 pF

—

2.5

—

— ns ns ns ns ns ns

1. Input timing assumes an input slew rate of 1 ns (10 % - 90 %) and uses TTL voltage thresholds.

2. All timing values for output signals in this table, are measured to 50 % of the output voltage.

3. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

92/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Figure 33. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 0 t

CSC t

ASC

SS t

SCK

SCK Input

(CPOL = 0) t

SDC t

SDC

SCK Input

(CPOL = 1) t

A t

SUO t

HO t

DIS

SOUT First Data t

SUI

Data Last Data

SIN First Data Data t

Last Data

Figure 34. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 1

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1) t

A t

SUO

SOUT

SIN

First Data t

SUI t

First Data

Data

Data t

Last Data t

DIS

Last Data

4.17.3 Ethernet timing

The Ethernet provides both MII and RMII interfaces. The MII and RMII signals can be configured for either CMOS or TTL signal levels compatible with devices operating at either

5.0 V or 3.3 V. Check the device pinout details to review the packages supporting MII and

RMII.

DS11701 Rev 4 93/142

101

Electrical characteristics SPC584Bx

4.17.3.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

Note:

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1 %.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency.

In the following table, all timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

Symbol C

Table 49. MII receive signal timing

Characteristic

CC D RXD[3:0], RX_DV, RX_ER to RX_CLK setup

CC D RX_CLK to RXD[3:0], RX_DV, RX_ER hold

CC D RX_CLK pulse width high

CC D RX_CLK pulse width low

Min

35 %

Value

Max

—

65 %

Unit ns ns

RX_CLK period

Figure 35. MII receive signal timing diagram

RX_CLK (input)

RXD[3:0] (inputs)

RX_DV

RX_ER

M1 M2

4.17.3.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

Note:

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1 %.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This option allows the use of non-compliant MII PHYs.

Refer to the SPC584Bx 32-bit Power Architecture microcontroller reference manual’s

Ethernet chapter for details of this option and how to enable it.

In the following table, all timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.

94/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Table 50. MII transmit signal timing

Value

(1)

Symbol C Characteristic Unit

Min Max

CC D TX_CLK to TXD[3:0], TX_EN, TX_ER invalid

CC D TX_CLK to TXD[3:0], TX_EN, TX_ER valid

CC D TX_CLK pulse width high

CC D TX_CLK pulse width low

—

35 %

—

65 %

65 % ns ns

TX_CLK period

1. Output parameters are valid for C

= 25 pF, where C

is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value

Figure 36. MII transmit signal timing diagram

TX_CLK (input)

TXD[3:0] (outputs)

TX_EN

TX_ER

4.17.3.3 MII async inputs signal timing (CRS and COL)

Symbol C

Table 51. MII async inputs signal timing

Value

Characteristic

CC D CRS, COL minimum pulse width

Min

1.5

Max

—

Figure 37. MII async inputs timing diagram

CRS, COL

Unit

TX_CLK period

DS11701 Rev 4 95/142

101

Electrical characteristics

4.17.3.4 MII and RMII serial management channel timing (MDIO and MDC)

The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.

Figure 38. MII serial management channel timing diagram

SPC584Bx

M14

M15

MDC (output)

M10

MDIO (output)

M11

MDIO (input)

M12

M13

4.17.3.5 MII and RMII serial management channel timing (MDIO and MDC)

Note:

The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.

In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50 % to 2.2 V/3.5 V input and output levels.

M12

M13

M14

M15

M10

M11

Symbol C

Table 52. MII serial management channel timing

Value

Characteristic

Min Max

CC D

MDC falling edge to MDIO output invalid

(minimum propagation delay)

CC D

MDC falling edge to MDIO output valid

(maximum propagation delay)

CC D MDIO (input) to MDC rising edge setup

CC D MDIO (input) to MDC rising edge hold

CC D MDC pulse width high

CC D MDC pulse width low

—

40 %

—

60 %

Unit ns ns ns ns

MDC period

96/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50 % to 2.2 V/3.5 V input and output levels.

M12

M13

M14

M15

M10

M11

Symbol C

Table 53. RMII serial management channel timing

Value

Characteristic

Min Max

CC D

MDC falling edge to MDIO output invalid

(minimum propagation delay)

CC D

MDC falling edge to MDIO output valid

(maximum propagation delay)

CC D MDIO (input) to MDC rising edge setup

CC D MDIO (input) to MDC rising edge hold

CC D MDC pulse width high

CC D MDC pulse width low

—

40 %

—

60 %

Unit ns ns ns ns

MDC period

Figure 39. MII serial management channel timing diagram

M14

M15

MDC (output)

M10

MDIO (output)

M11

MDIO (input)

M12

M13

4.17.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1 %.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency.

DS11701 Rev 4 97/142

101

Electrical characteristics SPC584Bx

Note: In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

Symbol C

Table 54. RMII receive signal timing

Characteristic

CC D RXD[1:0], CRS_DV to REF_CLK setup

CC D REF_CLK to RXD[1:0], CRS_DV hold

CC D REF_CLK pulse width high

CC D REF_CLK pulse width low

Min

35 %

Value

Max

—

65 %

Unit ns ns

REF_CLK period

Figure 40. RMII receive signal timing diagram

REF_CLK (input)

RXD[1:0] (inputs)

CRS_DV

R1 R2

4.17.3.7 RMII transmit signal timing (TXD[1:0], TX_EN)

Note:

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1 %.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK, and the timing is the same in either case. This option allows the use of non-compliant RMII PHYs.

In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.

RMII transmit signal valid timing specified is considering the rise/fall time of the ref_clk on the pad as 1ns.

98/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

Symbol C

Table 55. RMII transmit signal timing

Characteristic

CC D REF_CLK to TXD[1:0], TX_EN invalid

CC D REF_CLK to TXD[1:0], TX_EN valid

CC D REF_CLK pulse width high

CC D REF_CLK pulse width low

Min

—

35 %

Value

Max

—

65 %

Unit ns ns

REF_CLK period

Figure 41. RMII transmit signal timing diagram

REF_CLK (input)

TXD[1:0] (outputs)

TX_EN

4.17.4 CAN timing

The following table describes the CAN timing.

Table 56. CAN timing

Symbol C Parameter Condition t

P(RX:TX) t

PLP(RX:TX)

CC D

CAN controller propagation delay time standard pads

Medium type pads 25 pF load

Medium type pads 50 pF load

STRONG, VERY STRONG type pads

25 pF load

STRONG, VERY STRONG type pads

50 pF load

Medium type pads 25 pF load

CAN controller propagation delay time low power pads

Medium type pads 50 pF load

STRONG, VERY STRONG type pads

25 pF load

STRONG, VERY STRONG type pads

50 pF load

Min

—

Value

Typ

—

Max

100

Unit ns ns

DS11701 Rev 4 99/142

101

Electrical characteristics SPC584Bx

4.17.5 UART timing

UART channel frequency support is shown in the following table.

Table 57. UART frequency support

LINFlexD clock frequency LIN_CLK

(MHz)

Oversampling rate Voting scheme

100

3:1 majority voting

Limited voting on one sample with configurable sampling point

3:1 majority voting

Limited voting on one sample with configurable sampling point

Max usable frequency

(Mbaud)

13.33

6.25

12.5

16.67

4.17.6 I2C timing

The I 2 C AC timing specifications are provided in the following tables.

Note: In the following table, I2C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than 1 ns (10 % – 90 %).

No. Symbol C

Table 58. I2C input timing specifications – SCL and SDA

Value

Parameter

Min Max

Unit

1 — CC D Start condition hold time

2 — CC D Clock low time

3 — CC D Bus free time between Start and Stop condition

4.7

—

PER_CLK

Cycle

(1)

PER_CLK Cycle

µs

4 — CC D Data hold time

5 — CC D Clock high time

6 — CC D Data setup time

0.0

—

— ns

PER_CLK Cycle ns

7 — CC D Start condition setup time (for repeated start condition only)

8 — CC D Stop condition setup time

—

PER_CLK Cycle

1. PER_CLK is the SoC peripheral clock, which drives the I 2 device reference manual for more detail.

C BIU and module clock inputs. See the Clocking chapter in the

Note: In the following table:

100/142 DS11701 Rev 4

SPC584Bx Electrical characteristics

• All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

• Output parameters are valid for CL = 25 pF, where CL is the external load to the device

(lumped). The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value.

• Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

• Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register.

No. Symbol C

Table 59. I2C output timing specifications — SCL and SDA

Value

Parameter

Min Max

Unit

1 — CC D Start condition hold time

2 — CC D Clock low time

3 — CC D Bus free time between Start and Stop condition

4 — CC D Data hold time

5 — CC D Clock high time

4.7

—

PER_CLK

Cycle

(1)

— PER_CLK Cycle

—

µs

PER_CLK Cycle

6 — CC D Data setup time

7 — CC D Start condition setup time (for repeated start condition only)

— PER_CLK Cycle

8 — CC D Stop condition setup time 10 — PER_CLK Cycle

1. PER_CLK is the SoC peripheral clock, which drives the I 2 device reference manual for more detail.

C BIU and module clock inputs. See the Clocking chapter in the

Figure 42. I

C input/output timing

SCL

SDA

DS11701 Rev 4 101/142

101

Package information

5 Package information

SPC584Bx

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

ECOPACK is an ST trademark.

The following table lists the case numbers for SPC584Bx.

Table 60. Package case numbers

Package type Device type eTQFP64 eTQFP100 eTQFP144 eLQFP176

Production

5.1 eTQFP64 package information

for full description of below figures and table notes.

102/142 DS11701 Rev 4

SPC584Bx

Figure 43. eTQFP64 package outline

Package information

OLIH DXJPHQWHG

DS11701 Rev 4 103/142

122

Package information

Figure 44. eTQFP64 section A-A ș ș

SPC584Bx ș

Figure 45. eTQFP64 section B-B ș

104/142 DS11701 Rev 4

SPC584Bx

Symbol



 1

 2

 3

S aaa

bbb

ddd

Table 61. eTQFP64 package mechanical data

Dimensions

(7),(17)

Min.

0°

10°

—

0.05

0.95

0.17

0.09

—

4.10

—

4.10

0.45

0.08

0.20

Typ.

—

0.20

0.08

10 BSC

—

0.60

1 REF

0.22

0.20

—

12 BSC

10 BSC

—

0.50 BSC

12 BSC

3.5°

—

12°

—

1.00

Package information

Max.

7°

—

14°

1.20

0.15

1.05

0.27

0.23

0.20

0.16

5.85

—

5.85

—

0.75

—

0.20

—

DS11701 Rev 4 105/142

122

Package information

5.1.1 Package mechanical drawings and data information

SPC584Bx

The following notes are related to

Figure 43

, Figure 44 , Figure 45

and

Table 61 :

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.

3. Datums A-B and D to be determined at datum plane H.

4. To be determined at seating datum plane C.

5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.

6. Details of pin 1 identifier are optional but must be located within the zone indicated.

7. All dimensions are in millimeter except where explicitly noted.

8. No intrusion allowed inwards the leads.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.

Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

10. Exact shape of each corner is optional.

11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

12. A1 is defined as the distance from the seating plane to the lowest point on the package body.

13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad on SPC584Bx(variable) is as

Figure 46 .

End user should verify D2 and E2 dimensions according to the specific device application.

14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove.

15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.

16. “N” is the max number of terminal positions for the specified body size.

17. Critical dimensions: a) Stand-Off b) Overall Width c) Lead Coplanarity

18. For symbols, recommended values and tolerances, see Table 62

19. Notch may be present in this area (MAX 1.5mm square) if center top gate molding technology is applied. Resin gate residual not protruding out of package top surface.

106/142 DS11701 Rev 4

SPC584Bx

Figure 46. eTQFP64 leadframe pad design

Package information

5.2

Note: number, dimensions and positions of grooves are for reference only.

Symbol aaa bbb ccc ddd

Table 62. eTQFP64 symbol definitions

Definition Notes

The tolerance that controls the position of the terminal pattern with respect to Datum A and B. The center of the tolerance zone for each terminal is defined by basic dimension e as related to Datum A and B.

For flange-molded packages, this tolerance also applies for basic dimensions D1 and

E1. For packages tooled with intentional terminal tip protrusions, aaa does not apply to those protrusions.

The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E.

—

The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located.

This tolerance is commonly know as the

“coplanarity” of the package terminals.

The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension e.

This tolerance is normally compounded with tolerance zone defined by “b”.

eTQFP100 package information

Refer to Section 5.2.1: Package mechanical drawings and data information

for full description of below figures and table notes.

DS11701 Rev 4 107/142

122

Package information

Figure 47. eTQFP100 package outline

SPC584Bx

108/142 DS11701 Rev 4

OLIH DXJPHQWHG

SPC584Bx

Figure 48. eTQFP100 section A-A ș ș

Package information ș

Figure 49. eTQFP100 section B-B ș

DS11701 Rev 4 109/142

122

Package information

Symbol



 1

 2

 3

S aaa

bbb

ddd

Table 63. eTQFP100 package mechanical data

Dimensions

(7),(17)

0.05

0.95

0.17

Min.



—

0.09

—

5.10

—

5.10

0.45

0.08

0.20

14.00 BSC

—

0.60

1.00 REF

100

—

0.20

0.08

Typ.

3.5



—



—

1.00

0.22

0.20

—

16.00 BSC

14.00 BSC

—

0.50 BSC

16.00 BSC

SPC584Bx

0.15

1.05

0.27

0.23

0.20

0.16

Max.



—



1.20

6.77

—

6.77

—

0.75

—

0.20

—

110/142 DS11701 Rev 4

SPC584Bx

5.2.1

Package information

Package mechanical drawings and data information

The following notes are related to

Figure 47

, Figure 48 , Figure 49

and

Table 63 :

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.

3. Datums A-B and D to be determined at datum plane H.

4. To be determined at seating datum plane C.

6. Details of pin 1 identifier are optional but must be located within the zone indicated.

7. All dimensions are in millimeter except where explicitly noted.

8. No intrusion allowed inwards the leads.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.

Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

10. Exact shape of each corner is optional.

11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

12. A1 is defined as the distance from the seating plane to the lowest point on the package body.

13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions

from exposed pad itself. Type of exposed pad on SPC584Bx is as Figure 50 . End user

should verify D2 and E2 dimensions according to the specific device application.

14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove.

15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.

16. “N” is the max number of terminal positions for the specified body size.

17. Critical dimensions: a) Stand-Off b) Overall Width c) Lead Coplanarity

18. For symbols, recommended values and tolerances, see Table 64

DS11701 Rev 4 111/142

122

Package information

Figure 50. eTQFP100 leadframe pad design

SPC584Bx

Note: number, dimensions and positions of grooves are for reference only.

Symbol aaa bbb ccc ddd

Table 64. eTQFP100 symbol definitions

Definition Notes

For flange-molded packages, this tolerance also applies for basic dimensions D1 and E1. For packages tooled with intentional terminal tip protrusions, aaa does not apply to those protrusions.

The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E.

—

The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located.

The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension e.

This tolerance is commonly know as the

“coplanarity” of the package terminals.

This tolerance is normally compounded with tolerance zone defined by “b”.

5.3 eTQFP144 package information

Refer to Section 5.3.1: Package mechanical drawings and data information

for full description of below figures and table notes.

112/142 DS11701 Rev 4

SPC584Bx

Figure 51. eTQFP144 package outline

Package information

DS11701 Rev 4

OLIH DXJPHQWHG

113/142

122

Package information

Figure 52. eTQFP144 section A-A ș ș

SPC584Bx ș

Figure 53. eTQFP144 section B-B ș

114/142 DS11701 Rev 4

SPC584Bx

Symbol



 1

 2

 3

S aaa

bbb

ddd

Package information

Table 65. eTQFP144 package mechanical data

Dimensions

(7) , (17)

Min.

0.17

0.09

—

5.10

—

5.10

0.0°

10.0°

—

0.05

0.95

0.45

—

0.08

0.20

Typ.

—

0.20

0.08

—

0.50 BSC

0.60

1.00 REF

144

0.22

0.20

—

22.00 BSC

20.00 BSC

—

22.00 BSC

20.00 BSC

3.5°

—

12.0°

—

1.00

0.75

—

0.20

—

Max.

0.27

0.23

0.20

0.16

—

6.77

—

6.77

—

7.0°

—

14.0°

1.20

0.15

1.05

DS11701 Rev 4 115/142

122

Package information

5.3.1 Package mechanical drawings and data information

SPC584Bx

The following notes are related to

Figure 51

, Figure 52 , Figure 53

and

Table 65 :

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.

3. Datums A-B and D to be determined at datum plane H.

4. To be determined at seating datum plane C.

6. Details of pin 1 identifier are optional but must be located within the zone indicated.

7. All dimensions are in millimeter except where explicitly noted.

8. No intrusion allowed inwards the leads.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.

Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

10. Exact shape of each corner is optional.

11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

12. A1 is defined as the distance from the seating plane to the lowest point on the package body.

13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions

from exposed pad itself. Type of exposed pad on SPC584Bx is as Figure 54 . End user

should verify D2 and E2 dimensions according to the specific device application.

14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove.

15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.

16. “N” is the max number of terminal positions for the specified body size.

17. Critical dimensions: a) Stand-Off b) Overall Width c) Lead Coplanarity

18. For symbols, recommended values and tolerances, see Table 66

116/142 DS11701 Rev 4

SPC584Bx

Figure 54. eTQFP144 leadframe pad design

Package information

Note: number, dimensions and positions of grooves are for reference only.

Symbol aaa bbb ccc ddd

Table 66. eTQFP144 symbol definitions

Definition Notes

For flange-molded packages, this tolerance also applies for basic dimensions D1 and E1. For packages tooled with intentional terminal tip protrusions, aaa does not apply to those protrusions.

The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E.

—

The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located.

The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension e.

This tolerance is commonly know as the

“coplanarity” of the package terminals.

This tolerance is normally compounded with tolerance zone defined by “b”.

5.4 eLQFP176 package information

Refer to Section 5.4.1: Package mechanical drawings and data information

for full description of below figures and table notes.

DS11701 Rev 4 117/142

122

Package information

Figure 55. eLQFP176 package outline

SPC584Bx

118/142 DS11701 Rev 4

OLIH DXJPHQWHG

SPC584Bx

Figure 56. eLQFP176 section A-A ș ș

Package information ș

Figure 57. eLQFP176 section B-B ș

DS11701 Rev 4 119/142

122

Package information

Symbol



 1

 2

 3

S aaa

bbb

ccc

ddd

Table 67. eLQFP176 package mechanical data

Dimensions

(7),(17)

Min.

0°

10°

—

0.05

1.35

0.17

0.09

—

6.10

—

6.10

0.45

0.08

0.20

Nom.

24.00 BSC

—

0.60

1.00 REF

176

—

0.20

0.08

0.22

0.20

—

26.00 BSC

24.00 BSC

—

0.50 BSC

26.00 BSC

3.5°

—

12°

—

1.40

SPC584Bx

Max.

7°

—

14°

1.60

0.15

1.45

0.27

0.23

0.20

0.16

7.77

—

7.77

—

0.75

—

0.20

120/142 DS11701 Rev 4

SPC584Bx

5.4.1

Package information

Package mechanical drawings and data information

The following notes are related to

Figure 55

, Figure 56 , Figure 57

and

Table 67 :

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.

3. Datums A-B and D to be determined at datum plane H.

4. To be determined at seating datum plane C.

6. Details of pin 1 identifier are optional but must be located within the zone indicated.

7. All dimensions are in millimeter except where explicitly noted.

8. No intrusion allowed inwards the leads.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.

Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

10. Exact shape of each corner is optional.

11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

12. A1 is defined as the distance from the seating plane to the lowest point on the package body.

13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions

from exposed pad itself. Type of exposed pad on SPC584Bx is as Figure 58 . End user

should verify D2 and E2 dimensions according to the specific device application.

14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove.

15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.

16. “N” is the max number of terminal positions for the specified body size.

17. Critical dimensions: a) Stand-Off b) Overall Width c) Lead Coplanarity

18. For symbols, recommended values and tolerances, see Table 68

DS11701 Rev 4 121/142

122

Package information

Figure 58. eLQFP176 leadframe pad design

SPC584Bx

Note: number, dimensions and positions of grooves are for reference only.

Symbol aaa bbb ccc ddd

Table 68. eLQFP176 symbol definitions

Definition Notes

For flange-molded packages, this tolerance also applies for basic dimensions D1 and

E1. For packages tooled with intentional terminal tip protrusions, aaa does not apply to those protrusions.

The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E.

—

The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located.

This tolerance is commonly know as the

“coplanarity” of the package terminals.

The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension e.

This tolerance is normally compounded with tolerance zone defined by “b”.

122/142 DS11701 Rev 4

SPC584Bx Package information

5.5 Package thermal characteristics

The following tables describe the thermal characteristics of the device. The parameters in this chapter have been evaluated by considering the device consumption configuration reported in the

Section 4.7: Device consumption

5.5.1 eTQFP64

Symbol

Table 69. Thermal characteristics for 64 exposed pad eTQFP package

C Parameter

(1)

Conditions Value Unit

 JA

CC D Junction-to-Ambient, Natural Convection

(2)

Four layer board (2s2p) 30.8

°C/W

 JMA

CC D Junction-to-Moving-Air, Ambient

at 200 ft./min., four layer board (2s2p)

24.4

°C/W

 JB

 JCtop

 JCbottom



CC D

Junction-to-board

(3)

Junction-to-case top (4)

Junction-to-case bottom

(5)

Junction-to-package top

(6)

—

Natural convection

12.1

15.2

4.5

3.7

°C/W

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

5.5.2 eTQFP100

Symbol

Table 70. Thermal characteristics for 100 exposed pad eTQFP package

C Parameter (1) Conditions Value Unit

 JA

CC D Junction-to-Ambient, Natural Convection

(2)

Four layer board (2s2p) 28.9

°C/W

 JMA

CC D Junction-to-Moving-Air, Ambient

At 200 ft./min., four layer board (2s2p)

22.9

°C/W

 JB

 JCtop

 JCbottom



CC D

Junction-to-board

(3)

Junction-to-case top

(4)

Junction-to-case bottom

(5)

Junction-to-package top

(6)

—

Natural convection

14.1

4.4

3.7

°C/W

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

DS11701 Rev 4 123/142

127

Package information SPC584Bx

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

5.5.3 eTQFP144

Symbol

Table 71. Thermal characteristics for 144 exposed pad eTQFP package

C Parameter

(1)

Conditions Value Unit

 JA

CC D Junction-to-Ambient, Natural Convection

(2)

Four layer board (2s2p) 28.5

°C/W

 JMA

CC D Junction-to-Moving-Air, Ambient

At 200 ft./min., four layer board (2s2p)

22.1

°C/W

 JB

 JCtop

 JCbottom



CC D

Junction-to-board

(3)

Junction-to-case top (4)

Junction-to-case bottom

(5)

Junction-to-package top

(6)

—

Natural convection

14.5

13.7

4.4

3.7

°C/W

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

5.5.4 LQFP176

Symbol

Table 72. Thermal characteristics for 176 exposed pad LQFP package

C Parameter (1) Conditions Value Unit

 JA

CC D Junction-to-Ambient, Natural Convection

(2)

Four layer board (2s2p) 28 °C/W

 JMA

CC D Junction-to-Moving-Air, Ambient

Section 6: Ordering information :

at 200 ft./min., four layer board (2s2p)

21 °C/W

 JB

 JCtop

 JCbottom



CC D

Junction-to-board

(3)

Junction-to-case top

(4)

Junction-to-case bottom

(5)

Junction-to-package top

(6)

—

Natural convection

15.7

18.1

4.0

3.7

°C/W

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

124/142 DS11701 Rev 4

SPC584Bx Package information

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

5.5.5 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T

, can be obtained from the equation:

Equation 1

= T

+ (R

 JA

* P

) where:

= ambient temperature for the package (°C)

 JA

= junction-to-ambient thermal resistance (°C/W)

= power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The differences between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:

 Construction of the application board (number of planes)

 Effective size of the board which cools the component

 Quality of the thermal and electrical connections to the planes

 Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leaves the planes virtually disconnected, the thermal performance is also greatly reduced.

As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:

 One oz. (35 micron nominal thickness) internal planes

 Components are well separated

 Overall power dissipation on the board is less than 0.02 W/cm

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

DS11701 Rev 4 125/142

127

Package information SPC584Bx

Equation 2

= T

+ (R

 JB

* P

) where:

= board temperature for the package perimeter (°C)

 JB

= junction-to-board thermal resistance (°C/W) per JESD51-8

= power dissipation in the package (W)

When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance:

Equation 3

 JA

= R

 JC

+ R

 CA where:

 JA

= junction-to-ambient thermal resistance (°C/W)

 JC

= junction-to-case thermal resistance (°C/W)

 CA

= case to ambient thermal resistance (°C/W)

 JC

is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, R

 CA

. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where

90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required.

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be generated upon request.

To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter ( 

) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation:

Equation 4

= T

+ ( 

x P

) where:

= thermocouple temperature on top of the package (°C)



= thermal characterization parameter (°C/W)

= power dissipation in the package (W)

126/142 DS11701 Rev 4

SPC584Bx Package information

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.

When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter ( 

JPB

) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed pad) using the following equation:

Equation 5

= T

+ ( 

JPB

x P

) where:

= thermocouple temperature on bottom of the package (°C)



= thermal characterization parameter (°C/W)

= power dissipation in the package (W)

DS11701 Rev 4 127/142

127

Ordering information

6 Ordering information

Figure 59. Ordering information scheme

Example code:

SPC58

Product identifier

4 B

Core Product

Memory

E7 C

Package Frequency/

Tempertaure

Custom version

Security

Silicon revision

Packing

SPC584Bx

Y = Tray

X = Tape and Reel (pin 1 top right)

0 = 1st production version

1 = 2nd production version

0 = No security

C = Security HW (HSM)

0 = 4x std CAN

D = 4x ISO CAN FD

G = 8x std CAN

H = 8x ISO CAN FD

E = 8x std CAN / Ethernet

M = 8x ISO CAN FD / Ethernet

B = 64 MHz at 105

C = 80 MHz at 105

E = 120 MHz at 105

L = 64 MHz at 125

M = 80 MHz at 125

N = 120 MHz at 125

E7 = eLQFP176

E5 = eTQFP144

E3 = eTQFP100

E1 = eTQFP64

70 = 2 MB

64 = 1.5 MB

60 = 1 MB

B = SPC584Bx line

4 = Single computing e200z4 core

SPC58 = Power Architecture in 40 nm

Note: Contact your ST sales office to ask for the availability of a particular commercial product.

Features (for instance, flash, RAM or peripherals) not included in the commercial product cannot be used.

ST cannot be called to take any liability for features used outside the commercial product.

128/142 DS11701 Rev 4

SPC584Bx Ordering information

SPC584B70

(2M)

256

128

256

128

256

SPC584B64

(1.5M)

Table 73. Code Flash options

SPC584B60

(1M)

Partition Start address End address

256

128

256

0x00FC0000 0x00FC3FFF

0x00FC4000 0x00FC7FFF

0x00FC8000 0x00FCFFFF

0x00FD0000 0x00FD7FFF

0x00FD8000 0x00FDFFFF

0x00FE0000

0x01000000

0x00FFFFFF

0x0103FFFF

0x01040000

0x01080000

0x010C0000

0x01100000

0x01140000

0x01180000

0x0107FFFF

0x010BFFFF

0x010FFFFF

0x0113FFFF

0x0117FFFF

0x011BFFFF

SPC584B70

192

(1)

SPC584B64

160

(1)

Table 74. RAM options

SPC584B60

Type

128

(1)

PRAMC_2

(STBY)

PRAMC_2

(STBY)

PRAMC_2

(STBY)

PRAMC_2

(STBY)

PRAMC_2

(STBY)

D-MEM

CPU_2

1. RAM size is the sum of TCM and SRAM

Start address End address

0x400A8000 0x400A9FFF

0x400AA000 0x400AFFFF

0x400B0000 0x400B7FFF

0x400B8000 0x400BFFFF

0x400C0000 0x400C7FFF

0x52800000 0x5280FFFF

DS11701 Rev 4 129/142

129

Revision history

7 Revision history

Date

06-Oct-2016

13-Dec-2016

SPC584Bx

Revision

Table 75. Document revision history

Changes

Initial version.

Changed Microsoft Excel ® workbook attached to this document (was

SPC584Bx_IO_Definition_v1.xlsx dated July 26, 2016).

For details, refer to the sheet Revision History of the attached file

“SPC584Bx_IO_Definition_v2.xlsx”.

Section 3.2: Absolute maximum ratings :

Table 4: Absolute maximum ratings : For parameter “I

INJ from description.

”, text “DC” removed

Section 3.3: Operating conditions :

Table 5: Operating conditions :

– Footnote “1.260 V - 1.290 V range .. temperature profile” updated to Text “... average supply value below or equal to 1.236 V ...”

– In parameter “I

INJ1

” description, text “DC” removed.

Section 3.7: Device consumption :

Table 8: Device consumption :

– For parameter “I

DDSSWU1

”, typical value updated from “TBD” to “1 mA”

– For parameter “I

DDSSWU1 over...ADC off”

”, description updated to “SSWU running

– For parameter “I

DDSSWU2

”, typical value updated from “TBD” to “3.5 mA”

– For parameter “I

DDSSWU2 over...ADC on”

”, description updated to “SSWU running

– For parameter “I

DDSTOP

°C

”, typical value updated from “TBD” to “18” for T

=25

– For parameter “I

DDSTDBY8

=25 °C

”, typical value updated from “TBD” to “85” for

– For parameter “I

DDSTDBY32

=25 °C

”, typical value updated from “TBD” to “100” for

– For parameter “I

DDSTDBY128

=25 °C

”, typical value updated from “TBD” to “160” for

Section 3.8: I/O pad specification :

Section 3.8.2: I/O output DC characteristics :

– Updated “WEAK” to “WEAK/SLOW”

– Updated “STRONG” to “STRONG/FAST”

– Updated “VERY STRONG” to “VERY STRONG / VERY FAST”

Table 9: I/O pad specification descriptions :

– Added “Standby Pads”

Added footnote “Logic level is configurable in running mode while it is

CMOS...”

130/142 DS11701 Rev 4

SPC584Bx

Date

13-Dec-2016

Revision history

Table 75. Document revision history (continued)

Revision Changes

Table 12: WEAK/SLOW I/O output characteristics : Added “10%-90% in description of parameter “t

TR_W

”.

Table 13: MEDIUM I/O output characteristics : Added “10%-90% in description of parameter “t

TR_M

”.

Table 14: STRONG/FAST I/O output characteristics : Added “10%-90% in description of parameter “t

TR_S

”.

Table 10: I/O input electrical characteristics : Parameter “I

(P), TJ=150°C/360 mA) removed.

LKG

” (Medium Pads

Table 11: I/O pull-up/pull-down electrical characteristics : Added note “When the device enters into standby mode... an ADC function.”

(cont’d)

Section 3.11: Oscillators :

Removed figure “Test circuit”

Table 21: External 40 MHz oscillator electrical specifications :

– Footnote “I xatl

“I xatl

is the oscillator...Test circuit is shown in Figure 8” modified to

is the oscillator...startup of the oscillator”.

– Minimum value of parameter “V

IHEXT

“V

REF

+0.75”

” updated from “V

REF

+0.6” to

– Maximum value of parameter “V

ILEXT

0.75”

” updated from “V

REF

-0.6” to “V

REF

– Parameter “g m others.

”, value “D” updated to “P” for “f

XTAL

< 8 MHz”, and “D” for

– Footnote “This parameter is...100% tested” updated to “Applies to an...to crystal mode”. Also added to parameter “V

ILEXT

”.

– For parameters “V

IHEXT

* V

DD_HV_OSC

”

” and “V

ILEXT

”, Condition “–” updated to “V

REF

= 0.29

Table 23: 1024 kHz internal RC oscillator electrical characteristics : For parameter “  f var_V

”, minimum and maximum value updated from “-0.05” and

“+0.05” to “-5” and “+5”.

Section 3.12: ADC system :

Table 26: ADC-Comparator electrical specification : For parameter t

ADCSAMPLE

Standard channel, minimum value updated to “6/f

ADCK

”

Section 3.14: LFAST pad electrical characteristics :

Table 29: LFAST transmitter electrical characteristics,, : Footnote “The transition time is measured from...” removed.

Section 3.15: Power management :

Table 31: Power management regulators : Added option for “Internal linear regulator internal ballast” and added footnote “For compatibility purpose...local sales”.

Table 33: Linear regulator specifications : Updated description of IDD

MREG.

Table 35: Voltage monitor electrical characteristics : Added Parameter

UVD140_F.

Added Figure 13: Internal regulator with external ballast mode , Figure 15:

Standby regulator with external ballast mode , Figure 14: Internal regulator with internal ballast mode

DS11701 Rev 4 131/142

141

Revision history

Date

13-Dec-2016

16-Mar-2018

SPC584Bx

Table 75. Document revision history (continued)

Revision Changes

Section 3.17: AC Specifications :

Updated Figure 28: DSPI CMOS master mode — classic timing, CPHA = 1

(cont’d)

Section 4: Package information :

Updated Figure 43: eTQFP64 package outline

Updated Table 61: eTQFP64 package mechanical data

Updated Table 62: eTQFP100 package mechanical data

Updated Table 64: eLQFP176 package mechanical data

Updated

Figure 59: Ordering information scheme

Section : Features

Changed core name to e200z420 (was e200z4d)

Added first bullet “AEC-Q100 qualified”

Changed document classification “Target Specification” by “Production Data”

Removed ST Restricted watermark on all document

Section 1: Introduction

Section 2: Description

: Updated latest sentence with “one processor core”

(was two)

Table 2: Features list :

Updated MPU description

Added “Semaphores”

Updated “System SRAM”

Updated “DMA channels values”

Removed “Interrupt controller”

Figure 2: Periphery allocation

Removed SEMA42 block

Section 2.3: Features overview

Updated:

– 64 KB local data RAM for Core_2

– 8 KB I-Cache and 4 KB D-Cache for Core_2

– 128 KB on-chip general-purpose SRAM (+ 64 KB local data RAM: 64 KB included in the CPU)

– Multi channel direct memory access controllers

Section 3: Package pinouts and signal descriptions

Changed introduction sentence since the pin out excel file will no longer be attached to the datasheet

Section 3: Electrical characteristics

Section 4.1: Introduction

Removed text “The IPs and...for the details”

Removed the two notes applicable for preliminary data

132/142 DS11701 Rev 4

SPC584Bx

Date

16-Mar-2018

Revision history

Table 75. Document revision history (continued)

Revision Changes

Table 3: Parameter classifications :

Updated the description of classification tag “T”

(cont’d)

Section 4.2: Absolute maximum ratings :

Added text “Exposure to absolute ... reliability”

Added text “even momentarily”

Table 4: Absolute maximum ratings :

Updated values in conditions column

Added parameter T

TRIN

For parameter “T

STG

”, maximum value updated from “175” to “125”

Added new parameter “T

PAS

”

For parameter “I

INJ

DC...pad”

”, description updated from “maximum...PAD” to “maximum

Changed V

DD_HV_IO_FLEX

to V

DD_HV_IO_ETH

Section 4.3: Operating conditions

Table 5: Operating conditions :

For parameter “V

DD_LV

”, changed the classification from “D” to “P”

Removed note “Core voltage as ....”

Added parameter I

INJ2

Removed parameter “V

RAMP_LV

”

Changed parameter V

DD_HV_IO_FLEX

to V

DD_HV_IO_ETH

Updated the table footnote “Positive and negative Dynamic current....”

Table 6: Device supply relation during power-up/power-down sequence

Parameter “V

DD_LV

” removed

Changed parameter V

DD_HV_IO_FLEX to V

DD_HV_IO_ETH

Section 3.3.1: Power domains and power up/down sequencing :

Replaced reference to IO_definition excel file by "the device pin out IO definition excel file"

Section 4.7: Device consumption

Table 8: Device consumption :

Updated parameter “I

DDHALT

”

Updated parameter “I

DDSTOP

”

Added note to parameters I

DDHALT

and I

DDSTOP

Updated “I

DD_LKG

”: Classification “P” changed to “C” for all devices when <

TJ = 40 °C, added footnote “I

DD_LKG

and I

DD_LV

are reported as...”

Updated “I

DD_LV

”: added footnote “I

DD_LKG

and I

DD_LV

are reported as...”

Updated values of I

DD_LKG

DDSTBY128

, I

DDSSWU1

, I

and I

DDHALT

, I

DDSSWU2

DDSTOP

, I

DDSTBY8

, I

DDSTBY32

Updated “I

DD_HV

”: changed Max value “45” to “55”

Updated Max values of I

DDSTBY8

, I

DDSTBY32

, I

DDSTBY128

Updated table footnotes 4, 5, 6 and 8

Changed “mA” by “µA” for I

DDSTBY128

DS11701 Rev 4 133/142

141

Revision history

Date

16-Mar-2018

SPC584Bx

Table 75. Document revision history (continued)

Revision Changes

(cont’d)

Section 4.8: I/O pad specification

Removed note “The external ballast....”

Reformated note from introduction

Replaced all occurences of “50 pF load” with “CL=50pF”

Replaced all references to the IO_definitions excel file by “the device pinout IO definition excel file”

Section 4.8.2: I/O output DC characteristics : Added note “10%/90% is the....”

Table 9: I/O pad specification descriptions :

Description of “Standby pads” updated from “Some pads are active...weak-pull currents” to “These pads are active...CMOS threshhold”

Removed FlexRay at Very strong configuration description

Changed “the CMOS threshold” by “(VDD_HV_IO_MAIN / 2) +/-20%” at

Standby pads type

Table 12: WEAK/SLOW I/O output characteristics :

For parameter “F max_W

”, updated condition “25 pF load” to “CL=25pF”

For parameter “|t

SKEW_W

|”, changed max value from “30” to “25”

Table 14: STRONG/FAST I/O output characteristics

Parameter “I

DCMAX_S

” updated:

– Condition added “V

=5V+10%

– Condition added “V

=3.3V+10%

– Max value updated to 5.5mA

Updated values for t

TR_S

for condition CL = 25 pF and CL = 50 pF

Table 15: VERY STRONG/VERY FAST I/O output characteristics

“t

TR20-80

” replaced by “t

TR20-8_V

”

“t

TRTTL

” replaced by “t

TRTTL_V

”

“  tTR20-80” replaced by “  tTR20-80_V”

Removed FlexRay Standard in bracket at tTR20-80_V parameter

Table 16: I/O consumption :

Updated all the max values of parameters I

DYN_W

and I

DYN_M

Section 3.9: Reset pad (PORST) electrical characteristics :

Table 17: Reset PAD electrical characteristics

Replaced reference to IO_definition excel file by "Refer to the device pin out IO definition excel file"

Table 18: Reset Pad state during power-up and reset

: added this table

Section 3.10: PLLs

Table 19: PLL0 electrical characteristics :

For parameter “I

PLL0

”, classification changed from “C” to “T”

Footnote “Jitter values...measurement” added for parameters:

– 

PLL0PHI0SPJ

– 

PLL0PHI1SPJ

– 

PLL0LTJ

134/142 DS11701 Rev 4

SPC584Bx

Date

16-Mar-2018

Revision history

Table 75. Document revision history (continued)

Revision Changes

Updated footnote “Jitter values...contribution of pad used as CLKOUT for measurement” to “Jitter values...contribution of the divider and the path of the output CLKOUT pin” for parameters:

– 

PLL0PHI0SPJ

– 

PLL0PHI1SPJ

– 

PLL0LTJ

Added “f

INFIN

” for all devices

Symbol “f

INFIN

”: changed “C” by “—” in column “C”

Updated 

PLL0PHI0SPJ value

|: changed “T” by “D” and added pk-pk to Conditions

Updated 

PLL0PHI1SPJ

|: added pk-pk to Conditions value

Table 20: PLL1 electrical characteristics :

For parameter “I

PLL1

”, classification changed from “C” to “T”.

Footnote “Jitter values...measurement” added for parameter “ 

PLL1PHI0SPJ

|”

Updated footnote “Jitter values...contribution of pad used as CLKOUT for measurement” to “Jitter values...contribution of the divider and the path of the output CLKOUT pin” for parameter “ 

PLL1PHI0SPJ

|”

Added “f

INFIN

”

Symbol “f

INFIN

”: changed “C” by “—” in column “C”

(cont’d)

Section 4.11: Oscillators

Renamed the section “RC oscillator 1024 kHz” to

Section 4.11.4: Low power

RC oscillator

Table 21: External 40 MHz oscillator electrical specifications :

Classification for parameters “C

S_EXTAL

“D”

” and “C

S_XTAL

” changed from “T” to

Min and Max value of parameters C

S_EXTAL

and C

S_XTAL

updated to “3” (min) and “7” (max)

Updated classification, conditions, min and max values for parameter “gm”

Changed table footnote 3 by: This value is determined by the crystal manufacturer and board design, and it can potentially be higher than the maximum provided

Updated table footnote 1

Table 22: 32 kHz External Slow Oscillator electrical specifications

: Added this table

Table 23: Internal RC oscillator electrical specifications

For parameter “I

FIRC

”, replaced max value of 300 with 600

Added footnote to the description

Min, Typ and Max value of ”  f var_SW

” updated from “-1”, “-”, “1” to “-0.5”, “+0.3” and “0.5” respectively

Table 24: 1024 kHz internal RC oscillator electrical characteristics

For parameter “  f var_T

”, and “  f var_V

“: changed the classification to “P”.

Section 4.12: ADC system

Table 25: ADC pin specification

For I

LKG

, changed condition “C” to “—”.

For parameter C

, updated the max value to “1”.

DS11701 Rev 4 135/142

141

Revision history

Date

16-Mar-2018

SPC584Bx

Table 75. Document revision history (continued)

Revision Changes

Updated Max value for C

For parameter C

, updated the max value from “1” to “2”

Added electrical specification for R

20K 

symbol

Changed Max value = 1 by 2 for Cp2 SARB channels

Table 26: SARn ADC electrical specification :

Classification for parameter “I

ADCREFH

” changed from “C” to “T”.

For parameter f

ADCK

“> 13.33”

(High frequency mode), changed min value from “7.5” to

Deleted footnote “Values are subject to change (possibly improved to ±2 LSB) after characterization”

Added symbols t

ADCINIT

and t

ADCBIASINIT

Column “C” split and added “D” for I

ADV_S

Table 27: ADC-Comparator electrical specification

Classification for parameter “I

ADCREFH

” changed from “C” to “T”

Removed table footnote “Values are subject to change (possibly improved to

±2 LSB) after characterization”

Added new parameter “t

ADCINITSBY

”

Set min = 5/f

ADCK

µs for 10-bit ADC mode, min = 2/f

ADCK

” for ADC comparator mode, at symbol t

ADCSAMPLE

Column “C” split and added “D” for I

ADV_S

Figure 8: Input equivalent circuit (Fast SARn and SARB channels)

: updated

(cont’d)

Section 3.13: Temperature Sensor

Table 28: Temperature sensor electrical characteristics :

For “temperature monitoring range”: classification removed (was C)

Section 4.14: LFAST pad electrical characteristics

Introduction paragraph:

– 1st sentence: hidden text “both the SIPI and”

– all 2nd sentence hidden: “The same LVDS.. tables”

Figure 9: LFAST LVDS timing definition

Title changed to “LFAST LVDS timing definition”

Deleted:

– 400 mV p-p (MSC/DSPI)

– 0.50 * T (MSC/DSPI)

– (MSC/DSPI)

Table 29: LVDS pad startup and receiver electrical characteristics, :

For parameter I

LVDS_BIAS

, changed the characteristics to “C”

Table 31: LFAST PLL electrical characteristics

– Min and Max value of parameter “ERR

REF

” updated from “TBD” to “-1” and

“+1” respectively

– Max value of parameter “PN” updated from “TBD” to “-58”

– Frequency of parameter “  PER

REF

” updated from “10MHz” to “20MHz”

– Max value of parameter “  PER

REF from “TBD” to “350”

” for condition “Single period” updated

136/142 DS11701 Rev 4

SPC584Bx

Date

16-Mar-2018

Revision history

Table 75. Document revision history (continued)

Revision Changes

– Min and Max value of parameter “  PER

REF

” for condition “Long period” updated from “TBD” to “-500” and “+500” respectively

(cont’d)

Section 4.15: Power management

Section 4.15.1: Power management integration

Added sentence “It is recommended...device itself” for all devices

Figure 17: Voltage monitor threshold definition

: Updated figure

Table 32: Power management regulators

Removed text “In parts packaged with LQFP176, the auxiliary and clamp regulators cannot be enabled” from note 2

Table 33: External components integration

For PMOS, replaced “STT4P3LLH6” with “PMPB100XPEA”

For NMOS, replaced “STT6N3LLH6” with “PMPB55XNEA”

Added table footnote to typ value of C

Removed table footnote “External components number.......”

Updated Min and Max values at symbol C

to 1.1 and 3.0 respectively

Table 34: Linear regulator specifications

Classification of parameter “IDD

MREG

” changed from “P” to “T”

Classification of parameter “IDD

MREG

Updated values for symbol “  IDD

” changed from “T” to “P”

MREG

”:

– Min: added -100

– Max: added 100

Updated TBD values

Table 35: Auxiliary regulator specifications

: added table

Table 36: Clamp regulator specifications

: added table

Table 38: Voltage monitor electrical characteristics

POR031_C

: changed the max value from 0.85 to 0.97

VMFILTER

: replaced T with D

Min value of “V

POR200_C

” updated from “1.96” to “1.80”

Max value of “V

POR031_C

” updated from “.85” “0.97”

Changed the min value of parameter V

POR200_C from “1.96” to “1.80”

Changed the max value of parameter V

POR031_C from “0.85” to “0.97”

Changed the condition of parameter T

VMFILTER from “T” to “D”

In Supply/Parameter: Replaced “_FLEX” by “_ETH” for V

LVD290_IF

, V

LVD400_IF

HVD400_IF and V

UVD600_IF symbols

Added symbol V

UVD600_F

Section 3.16: Flash

Table 39: Wait state configuration

: added column for “APC” and table footnotes, other columns updated

Table 40: Flash memory program and erase specifications

: updated

Table 38: Flash memory Life Specification : updated

Section 4.17: AC specifications

Section 4.17.4: CAN timing : added section

DS11701 Rev 4 137/142

141

Revision history

Date

16-Mar-2018

SPC584Bx

Table 75. Document revision history (continued)

Revision Changes

Table 43: Nexus debug port timing : Classification of parameters “t

EVTIPW

” and

“t

EVTOPW

” changed from “P” to “D”

Table 45: DSPI channel frequency support

Added column to show slower and faster frequencies

Added DSPI_5 to lower frequency and removed it from higher frequency

Table 46: DSPI CMOS master classic timing (full duplex and output only)

MTFE = 0, CPHA = 0 or 1

Changed the Min value of t

SCK

(very strong) from 33 to 59

Table 56: CAN timing : Added columns for “CC” and “D”

(cont’d)

Section 4: Package information

Table 61: eTQFP64 package mechanical data

Deleted angle lines

Updated values for D2, D3, E2, E3 and ddd

Table 62: eTQFP100 package mechanical data

Deleted angle lines

Table 64: eLQFP176 package mechanical data

Updated values for D2 and E2

Figure 43: eTQFP64 package outline : Removed “6.2x6.2 mm” after “eTQFP

10x10x1.0”

Figure 44: eTQFP100 package outline

Removed “6.4x6.4 mm” after “eTQFP 14x14x1.0”

Table 69: Thermal characteristics for 64 exposed pad eTQFP package :

Updated all parameters values

Table 70: Thermal characteristics for 100 exposed pad eTQFP package

Updated all parameters values

Table 71: Thermal characteristics for 144 exposed pad eTQFP package

Updated all parameters values

Table 72: Thermal characteristics for 176 exposed pad LQFP package :

Updated all parameters values

Section 6: Ordering information

Figure 59: Ordering information scheme

Removed “R” value for the Packing options

Replaced “X” by “0” for Silicon revision

Added “”pin 1 top right” to “X” description in Packing

Table 73: Code Flash options and Table 74: RAM options : added these tables

138/142 DS11701 Rev 4

SPC584Bx

Date

10 -Sep-2019

Revision history

Table 75. Document revision history (continued)

Revision Changes

Section 1: Introduction

: Removed “Document overview” section title.

Section 2: Description

: Changed title type.

Section 4.2: Absolute maximum ratings

Table 4: Absolute maximum ratings

: Added cross reference to footnote