STMicroelectronics SPC572L64F2 Datasheet

SR P Input low level TTL

— C Input hysteresis TTL

— T Input V

IH temperature drift TTL

4.5 V < V

DD_HV_IO

< 5.5 V

4.5 V < V

DD_HV_IO

< 5.5 V

—

Unit

–0.3

—

0.275

—

— V

DD_HV_IO

0.3

—

0.8

—

100

V mV

IHAUT

(1)

ILAUT

(2)

HYSAUT

(4)

DRFTAUT

SR P Input high level

AUTOMOTIVE

SR P Input low level

AUTOMOTIVE

— C Input hysteresis

AUTOMOTIVE

— T Input V

IH temperature drift

AUTOMOTIVE

4.5 V < V

DD_HV_IO

< 5.5 V

4.5 V < V

DD_HV_IO

< 5.5 V

4.5 V < V

DD_HV_IO

< 5.5 V

4.5 V < V

DD_HV_IO

< 5.5 V

3.8

— V

DD_HV_IO

0.3

–0.3

— 2.1

(3)

0.4

—

— —

—

100 (5)

V mV

IHCMOS

(7)

SR P Input high level CMOS

(without hysteresis)

SR P Input high level CMOS

(with hysteresis)

)

SR P Input low level CMOS

(with hysteresis)

ILCMOS

(7)

SR P Input low level CMOS

(without hysteresis)

HYSCMOS

— C Input hysteresis CMOS

CMOS

3.0 V < V

DD_HV_IO

< 3.6 V

4.5 V < V

DD_HV_IO

< 5.5 V

3.0 V < V

DD_HV_IO

< 3.6 V

4.5 V < V

DD_HV_IO

< 5.5 V

3.0 V < V

DD_HV_IO

< 3.6 V

4.5 V < V

DD_HV_IO

< 5.5 V

3.0 V < V

DD_HV_IO

< 3.6 V

4.5 V < V

DD_HV_IO

< 5.5 V

3.0 V < V

DD_HV_IO

< 3.6 V

4.5 V < V

DD_HV_IO

< 5.5 V

(8)

DRFTCMOS

— T Input V

IH temperature drift CMOS

3.0 V < V

DD_HV_IO

< 3.6 V

4.5 V < V

DD_HV_IO

< 5.5 V

INPUT CHARACTERISTICS

(7)

0.65 *

DD_H

V_IO

— V

DD_HV_IO

+ 0.3

0.6 *

DD_H

V_IO

— V

–0.3

—

DD_HV_IO

0.35 *

+ 0

DD_HV_IO

–0.3

— 0.4 *

DD_HV_IO

— 0.1 *

DD_H

V_IO

—

— 100

requirement refer to NOTE on page 34

V mV

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Electrical characteristics SPC572Lx

Symbol

LKG

LKG_MED

Table 12. I/O input DC electrical characteristics (continued)

Value

Parameter Conditions

Min Typ Max

Digital input leakage 4.5 V < V

DD_HV

< 5.5 V

0.1*V

DD_HV

< V

< 0.9*V

DD_HV

TJ < 150 °C

C 4.5 V < V

DD_HV

< 5.5 V

SS_HV

< V

DD_HV

CC C Digital input leakage for

MEDIUM pad

4.5 V < V

DD_HV

0.1*V

DD_HV

< 5.5 V

< V

< 0.9*V

DD_HV

—

500

Unit

µA nA

CC D Digital input capacitance GPIO input pins

Ethernet input pins

—

1. A good approximation for the variation of the minimum value with supply is given by formula V

IHAUT

= 0.69 × V

DD_HV_IO.

2. A good approximation for the variation of the maximum value with supply is given by formula V

ILAUT

= 0.49 × V

DD_HV_IO.

3. Sum of V

ILAUT

and V

HYSAUT with 2.06 V limit at cold, T

is guaranteed to remain above 2.6 V in the 4.5 V < V

< 25 o

DD_HV_IO

< 5.5 V. Production test done

4. A good approximation of the variation of the minimum value with supply is given by formula V

HYSAUT

= 0.11 × V

DD_HV_IO.

5. In a 1 ms period, assuming stable voltage and a temperature variation of ±30 °C, V

shift is within ±50 mV. For SENT

6. Only for V

DD_HV_IO_JTAG

and V

VSIO[VSIO_xx] = 0 in the range 3.0 V < V

power segment. The TTL threshold are controlled by the VSIO bit.

DD_HV_IO

< 4.0 V, VSIO[VSIO_xx] = 1 in the range 4.5 V < V

DD_HV_IO

< 5.5 V.

7. For LFAST, microsecond bus and LVDS input characteristics, refer to dedicated communication module chapters.

8. Only for V

DD_HV_IO_JTAG

and V

DD_HV_IO_ETH

power segment.

Symbol

| I

WPU

| CC

WPU

Table 13 provides weak pull figures. Both pull-up and pull-down current specifications are

provided.

Table 13. I/O pull-up/pull-down DC electrical characteristics

Value

Parameter Conditions

Min Typ Max

Unit

T Weak pull-up current absolute value

(1)

D Weak pull-up resistance

= 0 V

DD_POR

< 3.0 V

(2)

(3)(4)

< V

DD_HV_IO

> V

= 1.1 V (TTL)

4.5 V < V

DD_HV_IO

< 5.5 V

= 0.69* V

DD_HV_IO

4.5 V < V

DD_HV_IO

< 5.5 V

= 0.49* V

DD_HV_IO

4.5 V < V

DD_HV_IO

< 5.5 V

0.49* V

DD_HVIO

DD_HV_IO

< V

4.5 V < V

DD_HV_IO

< 0.69*

< 5.5 V

10.6 * V

DD_HV

10.6

–

—

— 130

—

— µA

62 k Ω

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Symbol

Table 13. I/O pull-up/pull-down DC electrical characteristics (continued)

Value

C Parameter Conditions

Min Typ Max

Unit

| I

WPD

| CC

Weak pull-down current absolute value

Weak pull-down resistance

< V

= 0.9 V (TTL)

4.5 V < V

DD_HV_IO

< 5.5 V

= 0.69* V

DD_HV_IO

4.5 V < V

DD_HV_IO

< 5.5 V

= 0.49* V

DD_HV_IO

4.5 V < V

DD_HV_IO

< 5.5 V

0.49* V

DD_HV_IO

< V

4.5 V < V

DD_HV_IO

< 0.69*

< 5.5 V

—

130

—

1. Weak pull-up/down is enabled within t

WK_PU

= 1 µs after internal/external reset has been asserted. Output voltage will depend on the amount of capacitance connected to the pin.

2. V

DD_POR

is the minimum V

DD_HV_IO

supply voltage for the activation of the device pull-up/down, and is given in the Reset electrical characteristics table of Section Reset pad (PORST, ESR0) electrical characteristics in this Datasheet.

3. V

DD_POR

is defined in the

Table 19: Reset electrical characteristics

Section 3.10: Reset pad (PORST, ESR0) electrical characteristics in this Datasheet.

4. Weak pull-up behavior during power-up. Operational with V

DD_HV_IO

> V

DD_POR

µA k Ω

Figure 6. Weak pull-up electrical characteristics definition t

WK_PU t

WK_PU

DD_HV_IO

DD_POR

RESET

(INTERNAL) pull-up enabled

YES

PAD

(1)

POWER-UP Application defined RESET Application defined POWER-DOWN

1. Actual PAD slopes will depend on external capacitances and VDD_HV_IO supply.

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Electrical characteristics

3.8.2 I/O output DC characteristics

The figure below provides description of output DC electrical characteristics.

Figure 7. I/O output DC electrical characteristics definition

SPC572Lx

INTERNAL

(SIUL register)

50% t

PD10-90

(rising edge)

50%

HYS t

PD10-90

(falling edge) t

SKEW20-80

V out

90%

80%

Note:

20%

10% t

R20-80 t

R10-90 t

(max) = MAX(t

R10-90

F10-90

) t

(min) = MIN(t

R10-90

F10-90

) t

F20-80 t

F10-90 t

TR20-80

(max) = MAX(t

R20-80

F20-80

) t

TR20-80

(min) = MIN(t

R20-80

F20-80

) t

SKEW

= | t

R20-80

-t

F20-80

The following tables provide DC characteristics for bidirectional pads:

•

Table 14 provides output driver characteristics for I/O pads when in WEAK

configuration.

•

Table 15 provides output driver characteristics for I/O pads when in MEDIUM

configuration.

•

Table 16 provides output driver characteristics for I/O pads when in STRONG

configuration.

•

Table 17 provides output driver characteristics for I/O pads when in VERY STRONG

configuration.

Driver configuration is controlled by SIUL2_MSCRn registers. It is available within two

PBRIDGEA_CLK clock cycles after the associated SIUL2_MSCRn bits have been written.

Table 14 shows the WEAK configuration output buffer electrical characteristics.

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SPC572Lx Electrical characteristics

Symbol

Table 14. WEAK configuration output buffer electrical characteristics

Value

(2)

C Parameter Conditions (1)

Min Typ Max

Unit

OH_W

OL_W f

MAX_W t

TR_W

CC P PMOS output impedance weak configuration

CC P NMOS output impedance weak configuration

CC T Output frequency weak configuration

CC T Transition time output pin weak configuration

(4)

4.5 V < V

DD_HV_IO

< 5.5 V

Push pull, I

< 0.5 mA

4.5 V < V

DD_HV_IO

< 5.5 V

Push pull, I

< 0.5 mA

= 25 pF (3)

= 50 pF

= 200 pF

= 25 pF,

4.5 V < V

DD_HV_IO

< 5.5 V

= 50 pF,

4.5 V < V

DD_HV_IO

< 5.5 V

= 200 pF,

4.5 V < V

DD_HV_IO

< 5.5 V

= 25 pF,

3.0 V < V

DD_HV_IO

< 3.6 V

(5)

= 50 pF,

3.0 V < V

DD_HV_IO

< 3.6 V

= 200 pF,

3.0 V < V

DD_HV_IO

< 3.6 V

—

520

—

320

100

350

800

—

1040

0.25

120

240

820

150

300

1050

MHz ns

| t

SKEW_W

| CC T Difference between rise and fall time

DCMAX_W

PHL/PLH

Maximum DC current

Propagation delay

—

= 25 pF,

4.5 V < V

DD_HV_IO

< 5.9 V

= 25 pF,

3.0 V < V

DD_HV_IO

< 3.6 V

= 50 pF,

4.5 V < V

DD_HV_IO

< 5.9 V

= 50 pF,

3.0 V < V

DD_HV_IO

< 3.6 V

, defined in Table 12 ) are to be added to

—

120

150

240

300

1. All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid for VSIO[VSIO_xx] = 0

2. All values need to be confirmed during device validation.

3. C

is the sum of external capacitance. Device and package capacitances (C

TOT

= C

+ C

4. Transition time maximum value is approximated by the following formula:

0 pF < C

50 pF < C

< 50 pFt

TR_W

(ns) = 22 ns + C

(pF)

4.4 ns/pF

< 200 pFt

TR_W

(ns) = 50 ns + C

(pF)

3.85 ns/pF

5. Only for V

DD_HV_IO_JTAG

segment when VSIO[VSIO_IJ] = 0 or V

DD_HV_IO_ETH

segment when VSIO[VSIO_IF] = 0.

mA ns

Table 15 shows the MEDIUM configuration output buffer electrical characteristics.

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Electrical characteristics SPC572Lx

Symbol

Table 15. MEDIUM configuration output buffer electrical characteristics

Value

(2)

C Parameter Conditions

(1)

Min Typ

Unit

Max f

OH_M

OL_M

MAX_M t

TR_M

PMOS output impedance

MEDIUM configuration

NMOS output impedance

MEDIUM configuration

Output frequency

MEDIUM configuration

T Transition time output pin

MEDIUM configuration

(4)

4.5 V < V

DD_HV_IO

< 5.5 V

Push pull, I

< 2 mA

4.5 V < V

DD_HV_IO

< 5.5 V

Push pull, I

< 2 mA

= 25 pF (3)

= 50 pF

= 200 pF

= 25 pF

4.5 V < V

DD_HV_IO

< 5.5 V

= 50 pF

4.5 V < V

DD_HV_IO

< 5.5 V

= 200 pF

4.5 V < V

DD_HV_IO

< 5.5 V

= 25 pF,

3.0 V < V

DD_HV_IO

3.6 V

(5)

= 50 pF,

3.0 V < V

DD_HV_IO

3.6 V

= 200 pF,

3.0 V < V

DD_HV_IO

3.6 V

—

120

—

200

—

260

1.5

200

300

MHz ns

| t

SKEW_M

DCMAX_M

PHL/PLH

| CC T Difference between rise and fall time

CC D Maximum DC current

CC D Propagation delay

—

= 25 pF,

4.5 V < V

DD_HV_IO

< 5.9 V

= 25 pF,

3.0 V < V

DD_HV_IO

< 3.6 V

= 50 pF,

4.5 V < V

DD_HV_IO

< 5.9 V

= 50 pF,

3.0 V < V

DD_HV_IO

3.6 V

, defined in Table 12 ) are to be added to

—

1. All V

DD_HV_IO

conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid for VSIO[VSIO_xx] = 0

2. All values need to be confirmed during device validation.

3. C

is the sum of external capacitance. Device and package capacitances (C

TOT

= C

+ C

mA ns

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SPC572Lx Electrical characteristics

4. Transition time maximum value is approximated by the following formula:

0 pF < C

50 pF < C

< 50 pFt

TR_M

(ns) = 5.6 ns + C

(pF)

< 200 pFt

TR_M

(ns) = 13 ns + C

(pF)

1.11 ns/pF

0.96 ns/pF

5. Only for V

DD_HV_IO_JTAG

segment when VSIO[VSIO_IJ] = 0 or V

DD_HV_IO_ETH

segment when VSIO[VSIO_IF] = 0

Table 16 shows the STRONG configuration output buffer electrical characteristics.

Symbol

Table 16. STRONG configuration output buffer electrical characteristics

Value

(2)

C Parameter Conditions

(1)

Min Typ Max

30 50 65 f

MAX_S t

OH_S

OL_S

TR_S

PMOS output impedance

STRONG configuration

NMOS output impedance

STRONG configuration

Output frequency

STRONG configuration

Transition time output pin

STRONG configuration

(4)

DCMAX_S

CC D Maximum DC current

| t

SKEW_S

| CC T Difference between rise and fall time

4.5 V < V

DD_HV_IO

< 5.5 V

Push pull, I

< 8 mA

4.5 V < V

DD_HV_IO

< 5.5 V

Push pull, I

< 8 mA

= 25 pF (3)

= 50 pF

= 200 pF

= 25 pF

4.5 V < V

DD_HV_IO

< 5.5 V

= 50 pF

4.5 V < V

DD_HV_IO

< 5.5 V

= 200 pF

4.5 V < V

DD_HV_IO

< 5.5 V

= 25 pF,

3.0 V < V

DD_HV_IO

3.6 V

(5)

= 50 pF,

3.0 V < V

DD_HV_IO

3.6 V

= 200 pF,

3.0 V < V

DD_HV_IO

3.6 V

—

2.5

3.5

—

Unit

MHz ns mA

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Electrical characteristics SPC572Lx

Table 16. STRONG configuration output buffer electrical characteristics (continued)

Value (2)

Symbol C Parameter Conditions

(1)

Min Typ Max

Unit

PHL/PLH

CC D Propagation delay C

= 25 pF,

4.5 V < V

DD_HV_IO

< 5.9 V

= 25 pF,

3.0 V < V

DD_HV_IO

< 3.6 V

= 50 pF,

4.5 V < V

DD_HV_IO

< 5.9 V

= 50 pF,

3.0 V < V

DD_HV_IO

3.6 V

, defined in Table 12 ) are to be added to

—

36 ns

1. All V

DD_HV_IO

conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0 V to 3.6 V are valid for VSIO[VSIO_xx] = 0

2. All values need to be confirmed during device validation.

3. C

is the sum of external capacitance. Device and package capacitances (C

TOT

= C

+ C

4. Transition time maximum value is approximated by the following formula: t

TR_S

(ns) = 4.5 ns + C

(pF) x 0.23 ns/pF.

5. Only for V

DD_HV_IO_JTAG

segment when VSIO[VSIO_IJ] = 0 or V

DD_HV_IO_ETH

segment when VSIO[VSIO_IF] = 0

Table 17 shows the VERY STRONG configuration output buffer electrical characteristics.

Table 17. VERY STRONG configuration output buffer electrical characteristics

Value

(2)

Symbol C Parameter Conditions

(1)

Min Typ Max

OH_V

CC 20 40 60

OL_V f

MAX_V

P PMOS output impedance

VERY STRONG configuration

P NMOS output impedance

VERY STRONG configuration

Output frequency

VERY STRONG configuration

DD_HV_IO

= 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,

= 8 mA

DD_HV_IO

= 3.3 V ± 10%,

VSIO[VSIO_xx] = 0,

= 7 mA

(3)

DD_HV_IO

= 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,

= 8 mA

DD_HV_IO

= 3.3 V ± 10%,

VSIO[VSIO_xx] = 0,

= 7 mA

DD_HV_IO

= 25 pF

= 5.0 V ± 10%,

(4)

VSIO[VSIO_xx] = 1,

= 15 pF (3),(4)

—

Unit

50 MHz

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Table 17. VERY STRONG configuration output buffer electrical characteristics (continued)

Value (2)

Symbol C Parameter Conditions

(1)

Unit

Min Typ Max t t

TR_V

TR20-80

—

10–90% threshold transition time output pin

VERY STRONG configuration

20–80% threshold transition time output pin

VERY STRONG configuration

DD_HV_IO

= 5.0 V ± 10%,

DD_HV_IO

= 5.0 V ± 10%,

DD_HV_IO

= 5.0 V ± 10%,

= 200 pF

DD_HV_IO

= 5.0 V ± 10%,

DD_HV_IO

= 3.3 V ± 10%,

DD_HV_IO

= 3.3 V ± 10%,

2.5

0.8

—

5.3

5 ns ns t

TRTTL

CC — TTL threshold transition time

(5)

for output pin in

VERY STRONG configuration

1 — 5 ns

Σ t

T t

TR20-80

SKEW_V

PHL/PLH

—

Sum of transition time 20–

80% output pin VERY

STRONG configuration

Difference between rise and fall time at 20–80%

Propagation delay

DD_HV_IO

= 25 pF

= 5.0 V ± 10%,

DD_HV_IO

= 15 pF

= 3.3 V ± 10%,

DD_HV_IO

= 5.0 V ± 10%,

= 25 pF

electrical characteristics

= 25 pF,

4.5 V < V

DD_HV_IO

< 5.9 V

= 25 pF,

3.0 V < V

DD_HV_IO

< 3.6 V

= 50 pF,

4.5 V < V

DD_HV_IO

< 5.9 V

= 50 pF,

3.0 V < V

DD_HV_IO

< 3.6 V

—

10.5

12 ns ns ns

DCMAX_VS

CC D Maximum DC current — — 10 mA

1. All V

DD_HV_IO

conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0 V to 3.6 V are valid for VSIO[VSIO_xx] = 0.

2. All values need to be confirmed during device validation.

3. Only available on the V

DD_HV_IO_JTAG

and V

DD_HV_IO_ETH

segments.

4. C

is the sum of external capacitance. Add device and package capacitances (C

in this Datasheet) to calculate total signal capacitance (C

, defined in the Table 12: I/O input DC

TOT

= C

+ C

5. TTL transition time as for Ethernet standard.

3.9 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V

supply pair.

Table 18 provides I/O consumption figures.

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Electrical characteristics SPC572Lx

Note:

Symbol

RMS_SEG

RMS_W

In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I

AVGSEG

maximum value.

In order to ensure device functionality, the sum of the dynamic and static currents of the I/O on a single segment should remain below the I

DYNSEG

maximum value.

Pad mapping on each segment can be optimized using the pad usage information provided in the I/O Signal Description table. The sum of all pad usage ratios within a segment should remain below 100%.

In order to maintain the required input thresholds for the SENT interface, the sum of all I/O pad output percent IR drop as defined in the I/O Signal Description table, must be below

50 %. See the I/O Signal Description attachment.

The SPC572Lx I/O Signal Description and Input Multiplexing Tables are contained in a

Microsoft Excel

workbook file attached to this document. Locate the paperclip symbol on the left side of the PDF window, and click it. Double-click on the Excel file to open it and select the I/O Signal Description Table tab.

Table 18. I/O consumption (1)

C Parameter

D Sum of all the DC I/O current within a supply segment

D RMS I/O current for WEAK configuration

Conditions

Value

Min Typ Max

Unit

—

80 mA

1.1

RMS_M

CC D RMS I/O current for MEDIUM configuration

= 5.0 V ± 10%

= 3.3 V ± 10%

= 25 pF, 2 MHz

= 5.0 V ± 10%

= 50 pF, 1 MHz

= 5.0 V ± 10%

= 25 pF, 2 MHz

= 3.3 V ± 10%

= 50 pF, 1 MHz

= 3.3 V ± 10%

= 25 pF, 12 MHz

= 5.0 V ± 10%

= 50 pF, 6 MHz

= 5.0 V ± 10%

= 25 pF, 12 MHz

= 3.3 V ± 10%

= 50 pF, 6 MHz

= 3.3 V ± 10%

—

1.1

0.6

4.7

4.8

2.6

2.7

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Symbol

RMS_S

RMS_V

DYN_SEG

DYN_W

(2)

DYN_M

Table 18. I/O consumption (1) (continued)

Parameter Conditions C

RMS I/O current for STRONG configuration

RMS I/O current for VERY

STRONG configuration

= 25 pF, 50 MHz

= 5.0 V ± 10%

= 50 pF, 25 MHz

= 5.0 V ± 10%

= 25 pF, 50 MHz

= 3.3 V ± 10%

= 50 pF, 25 MHz

= 3.3 V ± 10%

= 25 pF, 50 MHz,

= 5.0V +/- 10%

= 50 pF, 25 MHz,

= 5.0V ± 10%

= 25 pF, 50 MHz,

= 3.3V ± 10%

= 25 pF, 25 MHz,

= 3.3V ± 10%

D Sum of all the dynamic and DC I/O current within a supply segment

= 5.0 V ± 10%

= 3.3 V ± 10%

D Dynamic I/O current for WEAK configuration

= 25 pF,

= 5.0 V ± 10%

= 50 pF,

= 5.0 V ± 10%

= 25 pF,

= 3.3 V ± 10%

= 50 pF,

= 3.3 V ± 10%

D Dynamic I/O current for MEDIUM configuration

= 25 pF,

= 5.0 V ± 10%

= 50 pF,

= 5.0 V ± 10%

= 25 pF,

= 3.3 V ± 10%

= 50 pF,

= 3.3 V ± 10%

Electrical characteristics

Value

Min Typ Max

Unit

— — 19 mA

— — 19

— — 10

— — 22 mA

— — 22

— — 11

—

— 195 mA

— 150

— 5.0

— — 5.1

— — 2.2

— — 2.3

— — 15 mA

— — 15.5

— — 7.0

— — 7.1

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Table 18. I/O consumption (1) (continued)

Symbol C Parameter Conditions

Value

Min Typ Max

Unit

DYN_S

DYN_V

D Dynamic I/O current for STRONG configuration

= 25 pF,

= 5.0 V ± 10%

= 50 pF,

= 5.0 V ± 10%

= 25 pF,

= 3.3 V ± 10%

D Dynamic I/O current for VERY

STRONG configuration

= 50 pF,

= 3.3 V ± 10%

= 25 pF,

= 5.0 V ± 10%

= 50 pF,

= 5.0 V ± 10%

= 25 pF,

= 3.3 V ± 10%

= 50 pF,

= 3.3 V ± 10%

—

1. I/O current consumption specifications for the 4.5 V <= V

VSIO[VSIO_xx] = 0 for 3.0 V <= V

DD_HV_IO

<= 3.6 V.

DD_HV_IO

<= 5.5 V range are valid for VSIO_[VSIO_xx] = 1, and

2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible (timed output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.

mA mA

3.10 Reset pad (PORST, ESR0) electrical characteristics

Note:

The device implements a dedicated bidirectional reset pin (PORST).

PORST pin does not require active control. It is possible to implement an external pull-up to ensure correct reset exit sequence. Recommended value is 4.7 k

Ω

36/112 DocID027866 Rev 5

SPC572Lx

Figure 8. Start-up reset requirements

Electrical characteristics

DDMIN

DD_POR

PORST

PORST undriven.

Device reset by internal power-on reset.

PORST driven low by internal power-on reset.

device start-up phase

Device reset forced by external circuitry.

Figure 9 describes device behavior depending on supply signal on PORST:

PORST low pulse amplitude is too low—it is filtered by input buffer hysteresis. Device remains in current state.

2. PORST low pulse duration is too short—it is filtered by a low pass filter. Device remains in current state.

3. PORST low pulse generates a reset: a) PORST low but initially filtered during at least W

FRST current state.

. Device remains initially in b) PORST potentially filtered until W

NFRST

. Device state is unknown: it may either be reset or remains in current state depending on other factors (temperature, voltage, device).

c) PORST asserted for longer than W

NFRST

. Device is under reset.

DocID027866 Rev 5 37/112

111

Electrical characteristics

PORST,

ESR0

Figure 9. Noise filtering on reset signal

HYS

SPC572Lx internal reset filtered by

hysteresis

1 filtered by

lowpass filter

FRST

2 filtered by

lowpass filter unknown reset state device under hardware reset

FRST

NFRST

3a 3b 3c

Symbol

Table 19. Reset electrical characteristics

Parameter Conditions

Min

2.0

SR P Input high level TTL

(Schmitt trigger)

SR P Input low level TTL

(Schmitt trigger)

HYS

DD_POR

CC C Input hysteresis TTL

(Schmitt trigger)

CC C Minimum supply for strong pull-down activation

—

–0.4

275

—

Value

Typ Max

— V

DD_HV_IO

+0.4

— 0.8

Unit

—

1.2

38/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Table 19. Reset electrical characteristics (continued)

Value

Symbol Parameter Conditions Unit

Min Typ Max

OL_R

NFRST

CC C Strong pull-down current

(1)

SR P PORST and ESR0 input not filtered pulse

Device under power-on reset

DD_HV_IO

= V

DD_POR

= 0.35 * V

DD_HV_IO

—

WPU

| CC P Weak pull-up current absolute value

ESR0 pin

= 0.69 * V

DD_HV_IO

ESR0 pin

= 0.49 * V

DD_HV_IO

WPD

| CC P Weak pull-down current absolute value

Device under power-on reset

3.0 V < V

DD_HV_IO

> 1.0 V

< 5.5 V,

FRST

SR P PORST and ESR0 input filtered pulse

PORST pin

= 0.69 * V

DD_HV_IO

PORST pin

= 0.49 * V

DD_HV_IO

—

0.2

—

2000

—

130

—

500

— mA

µA

µA ns ns

FNMI

NFNMI

P ESR1 input filtered pulse

P ESR1 input not filtered pulse

—

400

—

1. I

OL_R

applies to both PORST and ESR0: Strong pull-down is active on PHASE0 for PORST. Strong pull-down is active on

PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for ESR0.

ns ns

Note:

PORST must be connected to an external power-on supply circuitry. Minimum requested circuitry is external pull-up to ensure device can exit reset.

No restrictions exist on reset signal slew rate apart from absolute maximum rating compliance.

Single phase-locked loop (PLL) module with the reference PLL (PLL0) generating the system and auxiliary clocks from the main oscillator driver.

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Electrical characteristics SPC572Lx

Figure 10. PLL integration

IRCOSC

XOSC

PLL0

PLL0_PHI0

PLL0_PHI1

Table 20. PLL0 electrical characteristics

Value

Symbol C Parameter Conditions

Min Typ

|Δ f

PLL0IN

SR — PLL0 input clock

(1),(2)

SR — PLL0 input clock duty cycle

(1)

PLL0VCO f

PLL0PHI0

PLL0 VCO frequency

PLL0 output frequency f

PLL0PHI1

CC P PLL0 output frequency t

PLL0LOCK

CC P PLL0 lock time

|Δ

PLL0PHI0SPJ

| CC T PLL0_PHI0 single period jitter

—

— f

PLL0PHI0

= 400 MHz,

6-sigma pk-pk

PLL0PHI1SPJ f

PLL0LTJ

PLL0

PLL0FREE

| f

PLL0IN

= 20 MHz

(resonator)

CC T PLL0_PHI1 single period jitter f

PLL0PHI1

= 40 MHz, 6sigma pk-pk f

PLL0IN

= 20 MHz

(resonator)

CC T PLL0 output long term jitter

oscillator electrical specifications)

PLL0IN

= 20 MHz

(resonator), VCO frequency = 800 MHz

CC C PLL0 consumption

CC D VCO free running frequency

10 periods accumulated jitter

(80 MHz equivalent frequency), 6-sigma pk-pk

16 periods accumulated jitter

(50 MHz equivalent frequency), 6-sigma pk-pk long term jitter

(< 1 MHz equivalent frequency), 6-sigma pk-pk

FINE LOCK state

—

600 —

4.762

—

4.762

—

Max

300

(3)

± 250

± 300

± 500

400

1250

100

110

200

Unit

MHz

µs ps ps ps ps ps mA

MHz

40/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

1. PLL0IN clock retrieved directly from either Internal RC Oscillator (IRCOSC) or External Oscillator (XOSC) clock. Input characteristics are granted when using XOSC.

2. f

PLL0IN

frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range of

8 MHz-20 MHz.

3. V filtered.

noise due to application in the range V

DD_LV

= 1.25 V ± 5% with frequency below PLL bandwidth (40 kHz) is

Table 21. External oscillator electrical specifications

Value

Symbol C Parameter Conditions Unit

Min Max f

XTAL

CC D Crystal frequency range

(1)

—

> 8

MHz

> 20 40

C t cst t rec

IHEXT

ILEXT

S_XTAL

CC T Crystal start-up time

(2)(3)

CC T Crystal recovery time

(4)

CC D EXTAL input high voltage

(External Reference)

CC D EXTAL input low voltage

CC T Total on-chip stray capacitance on XTAL pin

(5)

S_EXTAL

CC T Total on-chip stray capacitance on EXTAL pin

REF

= 0.28 * V

—

DD_HV_IO_JTAG

—

REF

+ 0.6

—

0.5

— ms ms

REF

- 0.6

2.5 + value from

Table 22

2.5 + value from

Table 22

pF g m

XTAL

HYS

CC D Oscillator Transconductance T

= -40 °C to

150 °C

4.5 V <

DD_HV_IO

5.5 V

CC D XTAL current

(6)

J f f f

XTAL

= 150 °C

≤

8 MHz

20 MHz

≤

40 MHz

CC D Comparator Hysteresis T

= 150 °C

2.6

7.9

10.4

—

0.1

11.0

26.0

34.0

1.0

mA/V

1. The range is selectable by DCF record.

2. This value is determined by the crystal manufacturer and board design.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load capacitor value.

5. Applies to an external clock input and not to crystal mode.

6. I

XTAL

is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. Test circuit is shown in

Figure 11 .

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Electrical characteristics SPC572Lx

Table 22. Selectable load capacitance load_cap_sel[4:0] from DCF record

Capacitance offered on EXTAL/XTAL

(Cx and Cy)

(1),(2)

(pF)

00000

00001

00010

00011

00100

00101

00110

3.8

4.8

5.7

6.6

1.0

2.0

2.9

00111

01000

01001

01010

01011

01100

01101

01110

7.5

8.5

9.4

10.3

11.2

12.2

13.1

14.0

01111

10000–11111

(3)

15.0

Reserved

1. Values are determined from simulation across process corners and voltage and temperature variation. Capacitance values vary ±12% across process, 0.25% across voltage, and no variation across temperature.

2. Values in this table do not include the die and package capacitances given by C

S_XTAL

S_EXTAL

in Table 21 (External

3. Configurations 10000–11111 should not be used. Configurations 10000–11100 result in same capacitances of configurations 00011–01111. Configurations 11101, 11110, and 11111 select maximum capacitances.

42/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

VDDOSC

Figure 11. Test circuit

Bias

XTAL

EXTAL

VSSOSC

+ Comparator

Tester

VSS

PCB GND

Z = R + j ω L

Conditions

VEXTAL = 0 V

VXTAL = 0 V

ALC INACTIVE

Symbol C

Table 23. Internal RC oscillator electrical specifications

Parameter Conditions

Value

Min Typ Max

Unit

δ f t

δ f

Target var_noT start_noT t f f var_T var_SW start_T

CC D IRC target frequency

CC P IRC frequency variation without temperature compensation

CC T IRC frequency variation with temperature compensation

— T IRC frequency accuracy after software trimming accuracy

(1)

CC T Startup time to reach within f var_noT

CC D Startup time to reach within f var_T

—

< 150 °C

—

–8

–1.5

Trimming temperature –1

Factory trimming already applied

—

+1.5

120

MHz

µs

1. The typical user trim step size of δ f

TRIM

= 0.35 %

3.12.1 ADC input description

Figure 12

shows the input equivalent circuit for fast SARn channels.

DocID027866 Rev 5 43/112

111

Electrical characteristics

Figure 12. Input equivalent circuit (Fast SARn channels)

INTERNAL CIRCUIT SCHEME

Channel

Selection

Sampling

SW1

SPC572Lx

RSW1 Channel Selection Switch Impedance

RADSampling Switch Impedance

CP Pin Capacitance (two contributions, CP1 and CP2)

CS Sampling Capacitance

RCMSWCommon mode switch

RCMLCommon mode resistive ladder

This figure can be used as approximation circuitry for external filtering definition.It is also applicable for channel

AN16, AN17 and AN24 (Fast channels).

Common mode switch

Common mode resistive ladder

Figure 13

shows the input equivalent circuit for SARB channels.

44/112 DocID027866 Rev 5

SPC572Lx

Electrical characteristics

Figure 13. Input equivalent circuit (SARB channels)

INTERNAL CIRCUIT SCHEME

Channel

Selection

Extended

Switch

Sampling

SW1

SW2

Common mode switch

Common mode resistive ladder

RSW: Channel Selection Switch Impedance (two contributions

RSW1 and RSW2)

RAD: Sampling Switch Impedance

CP: Pin Capacitance (three contributions, CP1, CP2 and CP3)

CS: Sampling Capacitance

RCMSW: Common mode switch

RCML: Common mode resistive ladder

The above figure can be used as approximation circuitry for external filtering definition.

It is applicable for all SARB channels except AN 16, AN17 and

AN24 (Fast channels).

Symbol

LK_INUD

LK_INUSD

Table 24. ADC pin specification

(1)

Parameter

CC C Input leakage current, two ADC channels input with weak pull-up and weak pull-down

CC C Input leakage current, two ADC channels input with weak pull-up and strong pull-down

Conditions

< 40 °C, no current injection on adjacent pin

< 150 °C, no current injection on adjacent pin

< 40 °C, no current injection on adjacent pin

< 150 °C, no current injection on adjacent pin

Value

Min Max

— 70

Unit nA

—

220

250 nA

DocID027866 Rev 5 45/112

111

Electrical characteristics SPC572Lx

Table 24. ADC pin specification (1) (continued)

Value

Symbol C Parameter Conditions Unit

Min Max

LK_INREF

LK_INOUT

INJ

HV_ADC

SWn

CMSW

CMRL

SAFEPD

ADR

CC C Input leakage current, two ADC channels input with weak pull-up and weak pull-down and alternate reference

< 40 °C, no current injection on adjacent pin

CC C Input leakage current, two ADC channels input, GPIO output buffer with weak pull-up and weak pull-down

< 150 °C, no current injection on adjacent pin

< 40 °C, no current injection on adjacent pin

C T

< 150 °C, no current injection on adjacent pin

Applies to any analog pins

CC T Injection current on analog input preserving functionality

SR D V

DD_HV_ADV

external capacitance

(2)

CC D Pad capacitance

CC D Internal routing capacitance

D Internal routing capacitance

—

SARn channels

SARB channels

(3)

Only for SARB channels

— CC D SAR ADC sampling capacitance

CC D Analog switches resistance

CC D ADC input analog switches resistance

SARn channels

SARB channels

—

(4)

CC D Common mode switch resistance

CC D Common mode resistive ladder

CC D Discharge resistance for AN7 channels

(strong pull-down for safety)

CC C+

Sum of ADC and S/D reference consumption

ADC enabled

—

–3

—

1. All specifications in this table valid for the full input voltage range for the analog inputs.

2. For noise filtering, add a high frequency bypass capacitance of 0.1 µF between V

DD_HV_ADV

and V

SS_HV_ADV

3. Characteristics corresponding to fast SARn channels also apply to SARB fast channels (AN16, AN17 and AN24).

4. Safety pull-down is available for port pin PE[14]. It enables discharge of up to 100 nF from 5 V every 300 ms.

160 nA

400

140

380

3 nA mA

2.2

µF

10 pF

0.5

8.5

40 pF pF

1.1

k Ω

1.7

0.6

k Ω

2.6

k Ω

3.5

k Ω

300 W

µA

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing.

46/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Table 25. SARn ADC electrical specification (1)

Value

Symbol C Parameter Conditions

Min t f

ADCK

ADCPRECH

Δ V

INTREF t

ADCSAMPLE t

ALTREF

PRECH

ADCEVAL

SR P ADC alternate

C reference voltage

ALTREF

DD_HV_IO_MAIN

DD_HV_ADV

D ADC input signal

P Clock frequency

0 < V

< V

DD_HV_IO_MAIN

< 150 °C

SR T ADC precharge time Fast SAR—fast precharge

Fast SAR—full precharge

Slow SAR (SARADC_B)

(2)

— fast precharge

Slow SAR (SARADC_B)

— full precharge

SR D ADC precharge voltage Full precharge

PRECH

= V

DD_HV_ADR

< 150 °C

D Fast precharge

PRECH

= V

DD_HV_ADR

< 150 °C

CC P Internal reference voltage precision

SR P ADC sample time

(3)

Applies to all internal reference points

SS_HV_ADR

1/3 * V

DD_HV_ADR

2/3 * V

DD_HV_ADR

)

Fast SAR – 12-bit configuration

Fast SAR – 10-bit configuration

Slow SAR (SARADC_B)

–

12-bit configuration

Slow SAR (SARADC_B)

–

10-bit configuration

SR P ADC evaluation time 12-bit configuration (25 clock cycles)

D 10-bit configuration (21 clock cycles)

4.5

2.0

4.0

SS_HV_ADR

7.5

135

270

–0.25

−

540

–0.5

0.20

0.750

0.555

1.500

0.833

1.712

1.458

Max

5.5

4.0

5.9

DD_HV_ADR

14.6

—

0.25

0.5

0.20

—

Unit

MHz ns

µs

DocID027866 Rev 5 47/112

111

Electrical characteristics SPC572Lx

Symbol C

Table 25. SARn ADC electrical specification (1) (continued)

Value

Parameter Conditions

Min

(5)

(4),

CC T ADC high reference current

(6) t

Dynamic consumption conv

≥ 5 µs

(average across all codes)

—

ADCREFL

ADV_S

TUE

Dynamic consumption t conv

> 2.5 µs

(average across all codes)

Static consumption (Power

Down mode)

Bias Current

(9)

CC D ADC low reference

T current

Run mode t conv

≥ 5 µs

DD_HV_ADR

<= 5.5 V

Run mode t conv

= 2.5 µs

DD_HV_ADR

<= 5.5 V

Power Down mode

DD_HV_ADR

<= 5.5 V

Run mode

t conv

≥ 5 µs CC P V

DD_HV_ADV

power supply current

CC T (10) Total unadjusted error in

12-bit configuration

(11)

< 150 °C,

DD_HV_ADV

> 4 V,

DD_HV_ADR

, V

ALTREF

> 4 V

P T

< 150 °C,

DD_HV_ADV

> 4 V,

DD_HV_ADR

, V

ALTREF

> 4 V

< 150 °C,

DD_HV_ADV

> 4 V,

4 V > V

ALTREF

> 2 V

T T

< 150 °C,

4 V > V

DD_HV_ADV

> 3.5 V

CC T Total unadjusted error in

10-bit configuration

< 150 °C,

DD_HV_ADV

> 4 V

DD_HV_ADR

, V

ALTREF

> 4 V

T T

< 150 °C,

DD_HV_ADV

> 4 V,

4 V > V

DD_HV_ADR

ALTREF

> 2 V

—

–4

–6

–12

–1.5

–2.0

Max

3.5

(7)

(8)

4.0

1.5

2.0

Unit

µA

µA mA

LSB

(12b)

LSB

(10b)

48/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Symbol C

Table 25. SARn ADC electrical specification (1) (continued)

Value

Parameter Conditions

Min

Unit

Max

TUE12

CC D TUE degradation due to

DD_HV_ADR offset with respect to V

DD_HV_ADV

< V

DD_HV_ADV

DD_HV_ADR

∈ [0:25 mV]

− V

DD_HV_ADV

< V

DD_HV_ADV

DD_HV_ADR

∈ [25:50 mV]

− V

DD_HV_ADV

< V

DD_HV_ADV

DD_HV_ADR

∈ [50:75 mV]

− V

DD_HV_ADV

< V

DD_HV_ADV

DD_HV_ADR

− V

DD_HV_ADV

∈ [75:100 mV]

DD_HV_ADV

< V

DD_HV_ADR

∈ [0:25 mV]

− V

DD_HV_ADV

< V

DD_HV_ADR

∈ [25:50 mV]

− V

DD_HV_ADV

< V

DD_HV_ADR

∈ [50:75 mV]

− V

DD_HV_ADV

< V

DD_HV_ADR

− V

DD_HV_ADV

∈ [75:100 mV]

–2

–4

–6

–2.5

–4

–7

–12

2.5

LSB

(12b)

DNL CC P Differential non-linearity V

DD_HV_ADV

DD_HV_ADR

> 4 V

–1 2

2. Characteristics corresponding to SARB channels apply only for slow SAR channels i.e., all SARB channels except AN16,

AN17, and AN24.

3. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Please refer to

Figure 12

and

Figure 13

for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration.

4. I

ADCREFH and I

ADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion.

5. Current parameter values are for a single ADC.

6. Total consumption is given by the sum for all ADCs (associated to the reference pin) of their dynamic consumption and their static consumption.

7. Typical consumption is 2 µA.

8. Typical consumption is 4 µA.

LSB

(12b)

DocID027866 Rev 5 49/112

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Electrical characteristics SPC572Lx

9. Extra bias current is present only when BIAS is selected. Apply only once for all ADCs.

10. Extended bench validation performed on 3 samples for each process corner.

11. This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to ± 6

LSB.

The SDn ADCs are Sigma Delta 16-bit analog-to-digital converters with 333 Ksps maximum output rate.

Table 26. SDn ADC electrical specification (1)

Value

Symbol C Parameter Conditions Unit

Min Typ Max

SR P ADC input signal — 0

IN_PK2PK

(2) f f

ADCD_M f

ADCD_S

SR D Input range peak to peak

V = V

INP

(3)

– V

INM

Single ended

INM

= V

SS_HV_ADR

Single ended

INM

= 0.5*V

GAIN = 1

DD_HV_ADR

D Single ended

INM

= 0.5*V

DD_HV_ADR

GAIN = 2,4,8,16

SR P S/D modulator Input

Clock

Differential,

0 < V

< V

DD_HV_IO_MAIN

—

SR D Input signal

D frequency

SR D Output conversion rate f

SNR = 80 dB

ADCD_S

= 150 kHz f

SNR = 74 dB

ADCD_S

= 333 kHz

—

— CC D Oversampling ratio Internal modulator

External modulator

2’s complement notation RESOLUTION CC D S/D register resolution

(6)

GAIN SR D ADC gain Defined via ADC_SD[PGA] register. Only integer powers of 2 are valid gain values.

0.01

—

DD_HV_ADR

±0.5*V

±V

DD_HV_ADR

/GAIN

±V

DD_HV_ADR

/GAIN

14.4

—

DD_HV_ADR_

/GAIN

DD_HV_ADR

111

(5)

333

256

MHz kHz ksps

—

— bit

—

50/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Symbol

|δ

GAIN

OFFSET

Table 26. SDn ADC electrical specification (1) (continued)

Value

Parameter Conditions

Min Typ

— — CC C Absolute value of

D the ADC gain error

(7),(8)

Before calibration (applies to gain setting = 1)

CC P Input Referred

Offset Error

(7),(8),(9)

After calibration,

Δ V

DD_HV_ADR

Δ V

DD_HV_ADV

Δ T

< 50 °C

< 5%

< 10%

After calibration,

Δ V

DD_HV_ADR

Δ V

DD_HV_ADV

Δ T

< 100 °C

< 5%

< 10%

After calibration,

Δ V

DD_HV_ADR

Δ V

DD_HV_ADV

Δ T

< 150 °C

< 5%

< 10%

Before calibration (applies to all gain settings – 1, 2, 4, 8,

16)

D After calibration,

DD_HV_ADR

< 50 °C

< 10%

After calibration,

Δ V

DD_HV_ADV

Δ T

< 100 °C

< 10%

After calibration,

Δ V

DD_HV_ADV

Δ T

< 150 °C

< 10%

—

0.5

—

10*

( 1+1 /gain)

—

Max

1.5

7.5

Unit

% mV mV

DocID027866 Rev 5 51/112

111

Electrical characteristics

Symbol

SNR

DIFF150

SNR

DIFF333

Table 26. SDn ADC electrical specification (1) (continued)

Value

Parameter Conditions

Min Typ

CC P Signal to noise ratio in differential mode

150 ksps output rate

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 1

= V

< 5.5

DD_HV_ADV

< 150 °C

C 4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 2

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 4

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 8

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 16

= V

< 5.5

DD_HV_ADV

< 150 °C

CC P Signal to noise ratio in differential mode

333 ksps output rate

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 1

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 2

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 4

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 8

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 16

= V

< 5.5

DD_HV_ADV

< 150 °C

—

Max

—

SPC572Lx

Unit dBFS dBFS

52/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Symbol

SNR

SE150

SFDR

DIFF

(11)

Table 26. SDn ADC electrical specification (1) (continued)

Value

Parameter Conditions

Min Typ

— CC C Signal to noise ratio in single ended mode 150 ksps output rate

(10)

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 1

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 1

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 2

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 4

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 < V

DD_HV_ADV

DD_HV_ADR

GAIN = 8

= V

< 5.5

DD_HV_ADV

< 150 °C

4.5 <

DD_HV_ADV

DD_HV_ADR

GAIN = 16

< 5.5

DD_HV_ADV

< 150 °C

CC P Spurious free

C dynamic range

GAIN = 1

GAIN = 2

C GAIN = 4

CC D Differential input impedance

GAIN = 8

GAIN = 16

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

CC D Common mode input impedance

GAIN = 16

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

200

1400

1000

700

500

1000

600

300

200

—

250

1800

1300

950

650

—

1250

800

400

250

Max

—

300

2200

1600

1150

800

—

1500

1000

500

300

Unit dBFS dBc k Ω k Ω

DocID027866 Rev 5 53/112

111

Electrical characteristics SPC572Lx

Symbol

Δ V

INTCM

BIAS

δ V

BIAS

CMRR

Caaf f

PASSBAND

Table 26. SDn ADC electrical specification (1) (continued)

Value

Parameter Conditions

Min Typ

— -12% — CC D Common mode input reference voltage

CC D Bare bias resistance

CC D Bias voltage

—

110 144

— V

DD_HV_

ADR

–2.5

— CC D Bias voltage accuracy

SR D Common mode rejection ratio

—

SR D Anti-aliasing filter External series resistance

CC D

CC D Pass band

(12)

Filter capacitances

—

180

0.01

—

RIPPLE

F rolloff

CC D Pass band ripple

(13)

0.333 * f

ADCD_S

CC D Stop band attenuation

[0.5 * f

1.0 * f

ADCD_S

]

[1.0 * f

ADCD_S

1.5 * f

ADCD_S

]

[1.5 * f

ADCD_S

2.0 * f

ADCD_S

]

[2.0 * f

ADCD_S

2.5 * f

ADCD_S

]

[2.5 * f

ADCD_S

, f

ADCD_M

/2]

–1

—

Max

+12%

180

—

+2.5

—

0.333 * f

ADCD_S

—

Unit k Ω

% dB k Ω pF kHz

% dB

54/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Symbol

GROUP f

HIGH t

STARTUP t

LATENCY

Table 26. SDn ADC electrical specification (1) (continued)

Value

Parameter Conditions

Min Typ

CC D Group delay Within pass band – Tclk is f

ADCD_M

/ 2

OSR = 24

OSR = 28

OSR = 32

OSR = 36

OSR = 40

OSR = 44

OSR = 48

OSR = 56

OSR = 64

OSR = 72

OSR = 75

OSR = 80

OSR = 88

—

OSR = 96

OSR = 112

OSR = 128

OSR = 144

OSR = 160

OSR = 176

OSR = 192

OSR = 224

—

OSR = 256 —

Distortion within pass band –0.5/ f

ADCD

CC D High pass filter 3dB frequency

Enabled —

— — CC D Start-up time from power down state

CC D Latency between input data and converted data when input mux does not change

HPF = ON

HPF = OFF

—

10e-5* f

ADCD_S

—

Max

—

554.5

633.5

712.5

699

791.5

870.5

238.5

278

317.5

357

396.5

436

475.5

949.5

1107.5

1265.5

1423.5

1581.5

1739.5

1897.5

2213.5

2529.5

+0.5/ f

ADCD_S

—

100

GROUP

+ f

ADCD_S

GROUP

Unit

—

Tclk

—

µs

—

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Electrical characteristics SPC572Lx

Symbol C

Table 26. SDn ADC electrical specification (1) (continued)

Value

Parameter Conditions

Min Typ

Unit

Max t t

SETTLING

ODRECOVERY

S_D

IBIAS

ADV_D

CC D Settling time after mux change

Analog inputs are muxed

HPF = ON

HPF = OFF

CC D Overdrive recovery time

After input comes within range from saturation

HPF = ON

HPF = OFF

CC D S/D ADC sampling

D capacitance after sampling switch (14)

GAIN = 1, 2, 4, 8

GAIN = 16

CC D Bias consumption At least 1 ADCD enabled

CC P V

DD_HV_ADV

power supply current

(single S/D ADC)

S/D ADC Dynamic consumption

—

2* δ

GROUP

3*f

ADCD_S

2* δ

GROUP

2*f

ADCD_S

2* δ

GROUP

+ f

ADCD_S

2* δ

GROUP

75*GAIN

600

3.5

—

— mA mA

ADCS/D_REFH

CC T S/D ADC Reference

High Current

Dynamic consumption

(Conversion)

T Static consumption (Power down)

—

3.5

µA

2. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the signal will only be ‘clipped’.

3. V

INP

is the input voltage applied to the positive terminal of the SDADC.

4. V

INM

is the input voltage applied to the negative terminal of the SDADC.

5. Maximum input of 166.67 kHz supported with reduced accuracy. See SNR specifications.

6. When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. This gives an effective resolution of 15 bits.

7. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.

8. Calibration of gain is possible when gain = 1.

Offset Calibration should be done with respect to 0.5*V

DD_HV_ADR

for differential mode and single ended mode with negative input=0.5*V

DD_HV_ADR

Offset Calibration should be done with respect to 0 for "single ended mode with negative input=0".

Both offset and Gain Calibration is guaranteed for ±5% variation of V

°C temperature variation.

DD_HV_ADR

, ±10% variation of V

DD_HV_ADV

, and ± 50

9. Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred offset error.

10. This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to a value of 6 dB less.

11. Impedance given at f

DIFF

ADCD_M

) = 16 MHz/f

= 16 MHz. Impedance is inversely proportional to frequency:

ADCD_M

* Z

DIFF

12. SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the frequency range of f

ADCD_M

– f

ADCD_S

to f

ADCD_M

+ f

ADCD_S

, where f

ADCD_M

is the input sampling frequency, and f

ADCD_S is the output sample frequency. A proper external input filter should be used to remove any interfering signals in this frequency range.

13. The ±1% passband ripple specification is equivalent to 20 * log

(0.99) = 0.087 dB.

— fF fF

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14. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before sampling switch.

The following table describes the temperature sensor electrical characteristics.

—

SENS

ACC

TEMP_SENS

Symbol

Table 27. Temperature sensor electrical characteristics

Value

C Parameter Conditions

Min Typ

CC — Temperature monitoring range

Sensitivity

Accuracy

CC C V

DD_HV_ADV current

power supply

—

< 150 °C

—

–40

—

–3

—

5.18

—

Max

150

—

700

Unit

°C mV/°C

°C

µA

3.14 LVDS Fast Asynchronous Serial Transmission (LFAST) pad electrical characteristics

The LFAST pad electrical characteristics apply to both the SIPI and high-speed debug serial interfaces on the device. The same LVDS pad is used for the Microsecond Channel (MSC) and DSPI LVDS interfaces, with different characteristics given in the following tables.

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Electrical characteristics

3.14.1 LFAST interface timing diagrams

Figure 14. LFAST and MSC/DSPI LVDS timing definition

Signal excursions above this level NOT allowed

SPC572Lx

Max. common mode input at RX

|Δ

VOD

Max Differential Voltage =

285 mV p-p (LFAST)

400 mV p-p (MSC/DSPI)

1600 mV

Minimum Data Bit Time

Opening =

0.55 * T (LFAST)

0.50 * T (MSC/DSPI)

|Δ

VOD

Min Differential Voltage =

100 mV p-p (LFAST)

150 mV p-p (MSC/DSPI)

|Δ PER

EYE

“No-Go” Area V

= 1.2 V +/- 10%

TX common mode

ICOM

|Δ PER

EYE

Data Bit Period

T = 1 /F

DATA

Min. common mode input at RX

Signal excursions below this level NOT allowed

150 mV

0 V

58/112 DocID027866 Rev 5

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Differential TX

Data Lines pad_p/pad_n

Figure 15. Power-down exit time

Electrical characteristics t

PD2NM_TX

Data Valid

Figure 16. Rise/fall time

Differential TX

Data Lines

IH pad_p/pad_n V

10% t

90% t

3.14.2 LFAST and MSC/DSPI LVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.

Symbol

Table 28. LVDS pad startup and receiver electrical characteristics

(1)(2)

Value

C Parameter Conditions

Min Typ t

STRT_BIAS t

PD2NM_TX

STARTUP

(3),(4)

T Bias current reference startup time

(5)

T Transmitter startup time (power down to normal mode)

(6)

—

0.5

0.4

Max

Unit

4 µs

2.75

µs

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Electrical characteristics SPC572Lx

Table 28. LVDS pad startup and receiver electrical characteristics (1)(2) (continued)

Value

Symbol C Parameter Conditions

Min Typ Max

Unit t t

SM2NM_TX

PD2NM_RX

T Transmitter startup time (sleep mode to normal mode)

(7)

T Receiver startup time (power down to normal mode) (8)

Not applicable to the

MSC/DSPI LVDS pad

—

0.2

0.5

µs ns t

PD2SM_RX

CC T Receiver startup time (power down to sleep mode)

(9)

Not applicable to the

MSC/DSPI LVDS pad

T LVDS bias current consumption Tx or Rx enabled

— 20 50 ns

LVDS_BIAS

CC — — 0.95

SR D

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Transmission line characteristic impedance

— 47.5

50 52.5

DIFF

SR D Transmission line differential impedance

RECEIVER

— 95 100 105 Ω

ICOM

| Δ

HYS

P Differential input voltage

Common mode voltage

Input hysteresis

Terminating resistance

(12)

—

DD_HV_IO

5.0 V ± 10%

0.15

(10)

100

—

125

1.6

(11)

—

V mV

— mV

150 Ω

D V

DD_HV_IO

3.3 V ± 10%

80 115 150 Ω

LVDS_RX

Differential input capacitance (13)

Receiver DC current consumption Enabled

— —

—

3.5

—

6.0

0.5

1. The LVDS pad startup and receiver electrical characteristics in this table apply to the LFAST LVDS pad, and the MSC/DSPI

LVDS pad except where noted in the conditions.

2. All LVDS pad electrical characteristics are valid from –40 °C to 150 °C.

3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS control registers (LCR) of the LFAST and module. The value of the LCR bits for the LFAST/HSD modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding SIUL2 MSCR ODC field.

4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter electrical characteristic tables.

5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being enabled.

6. Total transmitter startup time from power down to normal mode is t periods.

STRT_BIAS

+ t

PD2NM_TX

+ 2 peripheral bridge clock

7. Total transmitter startup time from sleep mode to normal mode is t remains enabled in sleep mode.

SM2NM_TX

+ 2 peripheral bridge clock periods. Bias block

8. Total receiver startup time from power down to normal mode is t

STRT_BIAS

+ t

PD2NM_RX

+ 2 peripheral bridge clock periods.

9. Total receiver startup time from power down to sleep mode is t remains enabled in sleep mode.

PD2SM_RX

+ 2 peripheral bridge clock periods. Bias block

10. Absolute min = 0.15 V – (285 mV/2) = 0 V

11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V pF

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12. The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure proper LFAST receive timing.

13. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.

Table 29. LFAST transmitter electrical characteristics (1)(2)

Value

Symbol C Parameter Conditions Unit

Min Typ Max f

DATA

VOD

| t

D Data rate

P Common mode voltage

P Differential output voltage swing

(terminated)

(3)(4)

T Rise/Fall time (absolute value of the differential output voltage

swing)

(3),(4)

—

1.08

110

0.26

—

171

—

320

1.32

285

1.5

SR D External lumped differential load capacitance

1. The LFAST pad electrical characteristics are based on worst case internal capacitance values shown in Figure 17 .

DD_HV_IO

= 4.5 V —

DD_HV_IO

= 3.0 V —

T Transmitter DC current consumption Enabled —

—

9.0

8.5

LVDS_TX

CC — 3.2

2. All LFAST LVDS pad electrical characteristics are valid from –40 °C to 150 °C.

3. Valid for maximum data rate f

Figure 17 .

DATA

. Value given is the capacitance on each terminal of the differential pair, as shown in

4. Valid for maximum external load C

Mbps

V mV ns pF mA

Symbol

Table 30. MSC/DSPI LVDS transmitter electrical characteristics

(1)(2)

Value

C Parameter Conditions

Min Typ

Unit

Max f

DATA

VOD

Data Rate

SR D Data rate

CC P Common mode voltage

CC P Differential output voltage swing

(terminated)

(3)(4)

—

1.08

150

—

214

1.32

400

Mbps

V mV t

CC T Rise/Fall time (absolute value of the differential output voltage swing)

(3),(4)

— 0.8

— 4.0

SR D External lumped differential load capacitance

DD_HV_IO

= 4.5 V —

DD_HV_IO

= 3.0 V —

T Transmitter DC current consumption Enabled —

—

39 pF

LVDS_TX

— 4.0

1. The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst case internal capacitance values given in

Figure 17

2. All MSC and DSPI LVDS pad electrical characteristics are valid from –40 °C to 150 °C.

3. Valid for maximum data rate f

Figure 17 .

DATA

. Value given is the capacitance on each terminal of the differential pair, as shown in

4. Valid for maximum external load C

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Electrical characteristics SPC572Lx

Figure 17. LVDS pad external load diagram bond pad

GPIO Driver

1pF

2.5pF

100Ω terminator

LVDS Driver bond pad

GPIO Driver

1pF

2.5pF

Die Package PCB

3.15 Power management: PMC, POR/LVD, sequencing

The power management module monitors the different power supplies. It also generates the internal supplies that are required for correct device functionality. The power management is supplied by the V

DD_HV_PMC

supply, with voltage monitors ensuring safe state operation.

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DD_HV_IO_MAIN

Refer to the integration scheme provided below to ensure correct functionality of the device.

Figure 18. Voltage regulator capacitance connection

DECHV

DECBV

(regulator supply decoupling) (regulator supply decoupling)

DD_HV_PMC

REF

DD_HV_IO

DD_HV_PMC

DD_LV

DD_LVn

Voltage

Regulator V

DD_LV

DEVICE

SS V

DD_LV

DECREG2

(LV_COR)

REG

(LV_COR)

The internal voltage regulator requires external capacitance (C

REGn

) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH.

A decoupling capacitor must be placed between each V

DD_LV

supply pin and V

ground plane to ensure stable voltage. The capacitor should be placed as near as possible to the

DD_LV

supply pin.

3.15.2 Main voltage regulator electrical characteristics

Note:

The device implements an internal voltage regulator to generate the low voltage core supply

DD_LV

from the high voltage ballast supply V

DD_BV_PMC

DD_HV_PMC

. The regulator itself is supplied by

Both HV supplies, V

DD_HV_PMC package level.

and V

DD_BV_PMC

, are shorted with V

DD_HV_IO

supply at

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Electrical characteristics SPC572Lx

The following supplies are involved:

• HV—High voltage external power supply for voltage regulator module. It is shorted with

DD_HV_IO

• BV—High voltage external power supply for internal ballast module. It is shorted with

DD_HV_IO

• LV—Low voltage internal power supply for core, PLL and flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is split into three further domains to ensure noise isolation between critical

LV modules within the device:

– LV_COR—Low voltage supply for the core. It is also used to provide supply for

PLL through double bonding.

– LV_FLA—Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding.

– LV_PLL—Low voltage supply for PLL. It is shorted to LV_COR through double bonding.

Table 31. Voltage regulator electrical characteristics

Value (2)

Symbol Parameter Conditions

(1)

Unit

REG

DECREGn

DECBV

DECHV

SR Internal voltage regulator stability external capacitance

SR Stability capacitor equivalent serial resistance

SR Internal voltage regulator decoupling external capacitance

—

Total resistance including board track

—

— SR Stability capacitor equivalent serial resistance

SR Decoupling capacitance

(4)

ballast

SR Decoupling capacitance regulator supply

DD_HV_IO_MAIN

pair

Min

1.1

—

Typ

2.2

—

100

—

(3)

100

Max

2.97

135

—

µF m Ω nF m Ω

µF nF

DECFLA

MREG

SR Decoupling capacitance for flash

D supply

CC Main regulator output voltage

DD_HV_FLA

After trimming

Before trimming

pair 65

1.19

1.16

100 —

1.26

1.33

(5)

1.28

1.32

(6) nF

IDD

MREG

SR Main regulator current provided to

DD_LV

domain

SR Main regulator current variation

— — — 125 mA

Δ IDD

MREG

MREGINT

(7)

D Main regulator current consumption

20 µs observation window

—

–60

—

1.5

3.0

mA mA

1. V

= 5.0 V ± 10%, T

= –40 / 125 °C, unless otherwise specified.

2. All values need to be confirmed during device validation.

3. Recommended X7R or X5R ceramic –50% / +35% variation across process, temperature, voltage and after aging.

4. This capacitance value is driven by the constraints of the external voltage regulator supplying the V value is in the range of 470 nF.

DD_BV

voltage. A typical

5. At power-up condition before trimming at 27 °C, no load.

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6. Across the whole process, voltage and temperature range with full load.

7. By simulation.

3.15.3 Device voltage monitoring

Voltage monitoring thresholds are shown in the following figure.

Figure 19. Voltage monitor threshold definition

DD_xxx

LVD_290 t

VDRELEASE t

VDASSERT

LVD TRIGGER

(INTERNAL)

The LVDs for the device and their levels are given in the following table.

Symbol

LVD270_C

LVD400_A/IM

LVD108

Table 32. Voltage monitor electrical characteristics (1)

Parameter

CC P HV supply low voltage monitoring

LVD290_C/IJ/F/IF

CC P HV supply low voltage monitoring

CC P Core LV internal supply low voltage monitoring

Conditions

Pre-trimming

Trimmed

(3)

Pre-trimming

Trimmed

Trimmed

—

Value

(2)

Unit

Min Typ Max

2610 2760 2910 mV

2710 2760 2800 mV

2660 2820 2980 mV

2890 2940 2990 mV

3990 4230 4470 mV

4150 4230 4310 mV

1080 — 1170 mV

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Electrical characteristics SPC572Lx

Symbol

Table 32. Voltage monitor electrical characteristics (1) (continued)

Value (2)

C Parameter Conditions

Min Typ

Unit

Max t t

VDASSERT

VDRELEASE

CC D Voltage detector threshold crossing assertion

CC D Voltage detector threshold crossing de-assertion

—

0.1

—

1. For V

DD_LV

levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on the die. For other LVD, the IR drop is estimated by the multiplying the supply current by 0.5 Ω .

2. The threshold for all PORs and LVDs are defined when the output transits to 1, i.e., when the sense goes above the reference.

3. Across process, temperature and voltage range.

µs

The following table shows the constraints and relationships for the different power supplies.

Table 33. Device supply relation during power-up/power-down sequence

Supply 2

(1)

DD_LV

DD_HV_IO

DD_HV_ADV

DD_HV_ADR

ALTREF

(2)

DD_LV

DD_HV_IO

DD_HV_ADV

DD_HV_ADR

ALTREF

10 mA

(3)

5 mA

10 mA

1. Grey cells: Supply 1 (row) can exceed Supply 2 (column), granted that external circuitry ensures current flowing from supply1 is less than absolute maximum rating current value provided.

2. ALTREF are the alternate references for the ADC that can be used in place of the default reference (V the SARB.ALTREF.

DD_HV_ADR_*

). It is

3. ADC performance is not guaranteed with ALTREFn above V

DD_HV_IO

DD_HV_ADV.

During power-up, all functional terminals are maintained into a known state as described in the following table.

PORST

ESR0

(5)

TERMINAL

(1)

Table 34. Functional terminals state during power-up and reset

POWER-UP (2) pad state

RESET pad state

Default pad state

(3)

Comments

Weak pull-down Power-on reset pad Strong pulldown

(4)

Weak pull-down

Strong pull-down Strong pull-down Weak pull-up Functional reset pad

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Table 34. Functional terminals state during power-up and reset (continued)

TERMINAL

(1)

POWER-UP (2) pad state

RESET pad state

Default pad state

(3)

Comments

ESR1 High impedance Weak pull-down

TEST_MODE Weak pull-down Weak pull-down

(6)

Weak pull-down

—

GPIO

ANALOG

ERROR

TRST

TCK

TMS

TDI

TDO

Weak pull-up

Section 3.8.2, I/O output DC characteristics .

High impedance

Weak pull-up

High impedance

Weak pull-down

Weak pull-up

High impedance

Weak pull-up

High impedance

Weak pull-down

Weak pull-up

High impedance

—

1. Refer to pinout information for terminal type.

2. POWER-UP state is guaranteed from V

PORUP_LV

for LV supply, V

PORUP_HV

DD_HV_IO

> 1.1 V and maintained until supply crosses the power-on reset threshold:

for high voltage supply.

3. Before software configuration.

4. Pull-down and pull-up strength are provided as part of

5. As opposed to ESR0, ESR1 is provided via normal GPIO and implements weak pull-up during power-up.

6. TESTMODE pull-down is implemented to prevent device to enter TESTMODE. It is recommended to connect TESTMODE pin to V

SS_HV_IO

on the board.

3.16 Flash memory electrical characteristics

The flash array access time for reads is affected by the number of wait-states added to the minimum time, which is one cycle.

Wait states are set in the RWSC field of the Platform Flash Configuration Register 1 (PFCR1) to a value corresponding to the operating frequency of the flash memory controller and the actual read access time of the flash memory controller. Higher operating frequencies require non-zero settings for this field for proper flash operation.

Shown below are the maximum operating frequencies (f sys on specified access times at 150 °C:

) for legal RWSC settings based

Table 35. RWSC settings

Flash operating frequency range (MHz)

00 MHz < f sys

< 20 MHz

20 MHz < f sys

< 40 MHz

40 MHz < f sys

< 60 MHz

60 MHz < f sys

< 80 MHz

RWSC

Table 36 shows the estimated Program/Erase characteristics.

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Electrical characteristics SPC572Lx

Table 36. Flash memory program and erase specifications (pending silicon characterization) (1)

Value

Symbol Characteristics

(2)

Typ

(3)

Initial max

25 °C

(6)

All temp

(7)

Lifetime max (5)

Typical end of life

(4)

< 1 K cycles

< 100 K cycles

Unit t t t t dwprogram pprogram pprogrameep qprogram t t

MR0S

MR0P

Double Word (64 bits) program time [Packaged part]

Page (256 bits) program time

EEPROM (partition 2)

[Packaged part]

Quad Page (1024 bits) program time

274

150

300

330

1000

—

1500 —

214

250

802

500

1000

2000

µs

µs t t qprogrameep

256kpperase

Quad Page (1024 bits) program time EEPROM (partition 2)

[Packaged part]

256 KB block pre-program and erase time

315 C 1100 1650 P 925 2000

1800 C 2400 3400 P 1980 15000 —

584 C 760 1140 P 650 17000 —

37 C 48 72 P 69 1000 t

256kprogram

256 KB block program time t

16kprogrameep

Program 16 KB EEPROM

(partition 1) t

16keraseeep t t t t t tr pr ffprogram fferase

ESRT t

PSRT

Erase 16 KB EEPROM (partition

Program rate

(8)

Erase rate

(8)

Full flash programming time

(9)

Full flash erasing time

Erase suspend request rate

(10) t t

PSUS

ESUS t

AIC0S

Program suspend request rate

Program suspend latency

(11)

Erase suspend latency

Array Integrity Check Partition 0

(1.5 MB, sequential)

(12)

350

2.34

7.2

—

5.5

—

1200

3.04

14.4

12 C 24

—

1200

4.56

28.8

30 P

— —

—

600

2.60

7.92

—

5000

—

C s/MB

µs ms ms ms ms s

C s

T ms

T µs

— — ms t

AIC0P

Array Integrity Check Partition 0

(1.5 MB, proprietary)

(12)

Margin Read Partition 0 (1.5

MB, sequential)

Margin Read Partition 0 (1.5

MB, proprietary)

3.35

100 T

16.7

—

— —

—

— — s

—

— ms s

1. Characteristics are valid both for DATA Flash and CODE Flash, unless specified in the characteristics column.

68/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

2. Actual hardware programming times; this does not include software overhead.

3. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization.

4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but not tested.

5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.

6. Initial factory condition: < 100 program/erase cycles, 20 °C < T voltages. These values are verified at production testing.

< 30 °C junction temperature, and nominal (± 2%) supply

7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for less than or equal to 100 program or erase cycles, –40 °C < T voltages. These values are verified at production testing.

< 150 °C junction temperature, and nominal (± 2%) supply

8. Rate computed based on 256K sectors.

9. Only code sectors, not including EEPROM.

10. Time between erase suspend resume and next erase suspend.

11. Timings guaranteed by design.

12. AIC is done using system clock, thus all timing is dependant on system frequency and number of wait states. Timing in the table is calculated at 160 MHz.

Symbol

Table 37. Flash memory module extended life specification

(1)

Value

C Parameter Conditions

Min Typ

P/E

256

CC C Number of program/erase cycles per block for 16 KB

EEPROM emulation

(2)

CC C Number of program/erase cycles per block for 256 KB blocks

1. These specifications apply to JTAG boundary scan only. See Table 39 for functional specifications.

—

Data retention CC C Minimum data retention Blocks with 0 – 10000

P/E cycles

Blocks with 10001–

250000 P/E cycles.

Data Retention limited to 2, in total, 16 KB sectors within module 1

100,000

1000

—

100,000

—

1. All stated module life data are preliminary targets, and subject to change pending silicon characterization.

2. Program and Erase supported for standard operating temperature range.

Unit

Max

— P/E cycles

—

P/E cycles years

DocID027866 Rev 5 69/112

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Electrical characteristics SPC572Lx

3.17.1 Debug and calibration interface timing

Table 38. JTAG pin AC electrical characteristics (1)(2)

Value

# Symbol C Characteristic Unit

Min Max

4 t

TMSS, t

TDIS

5 t

TMSH, t

TDIH

9 t

TDOV t

TDOI t

TDOHZ t

JCMPPW

10 t

JCYC t

JDC t

TCKRISE

12 t

JCMPS t

BSDV t

BSDVZ

D TCK cycle time

T TCK clock pulse width

D TCK rise and fall times (40%–70%)

TMS, TDI data setup time

TMS, TDI data hold time

TCK low to TDO data valid

TCK low to TDO data invalid

TCK low to TDO high impedance

JCOMP assertion time

JCOMP setup time to TCK low

D TCK falling edge to output valid

D TCK falling edge to output valid out of high impedance

100

—

100

—

(3)

—

600

(4)

600 ns ns ns ns ns

% ns ns ns

15 t

BSDHZ t

BSDST t

BSDHT

TCK falling edge to output high impedance

Boundary scan input valid to TCK rising edge

TCK rising edge to boundary scan input invalid

—

600

—

2. JTAG timing specified at V section of the datasheet.

DD_HV_IO_JTAG

= 4.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O

3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

ns ns ns ns ns ns

70/112 DocID027866 Rev 5

SPC572Lx

TCK

Electrical characteristics

Figure 20. JTAG test clock input timing

1 3

Figure 21. JTAG test access port timing

TCK

TMS, TDI

7 8

TDO

DocID027866 Rev 5 71/112

111

Electrical characteristics

Figure 22. JTAG JCOMP timing

TCK

JCOMP

SPC572Lx

72/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Figure 23. JTAG boundary scan timing

TCK

11 13

Output

Signals

Output

Signals

Input

Signals

3.17.1.2 Nexus interface timing

Table 39. Nexus debug port timing

(1)

(8)

Symbol

8 t

EVTOPW

9 t

EVTIPW t t

TCYC t

TCYC

NTDIS

C Characteristic

CC D EVTI pulse width

CC D EVTO pulse width

CC D TCK cycle time

CC D Absolute minimum TCK cycle time (5) (TDO/TDOC sampled on posedge of TCK)

Absolute minimum TCK cycle time

(7)

(TDO/TDOC sampled on negedge of TCK)

CC D TDI/TDIC data setup time

Min

Value

(3),(4)

40 (6)

Unit

Max

— t

CYC

(2)

— ns

— t

CYC

— ns

DSPI channel frequency support is shown in Table 40

—

— ns

DocID027866 Rev 5 73/112

111

Electrical characteristics SPC572Lx

Table 39. Nexus debug port timing (1) (continued)

Value

# Symbol C Characteristic Unit

Min Max

(9)

(10)

16 t

NTDIH t

NTMSS t

NTMSH

—

CC D TDI/TDIC data hold time

CC D TMS/TMSC data setup time

CC D TMS/TMSC data hold time

CC D TDO/TDOC propagation delay from falling edge of TCK

(11)

CC D TDO/TDOC hold time with respect to TCK falling edge

(minimum TDO/TDOC propagation delay)

—

2.25

—

1. Nexus timing specified at V section of the datasheet.

DD_HV_IO_JTAG

= 4.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O

2. t

CYC

is system clock period.

3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number greater than or equal to that specified here.

4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute minimum TCK period specification.

5. This value is TDO/TDOC propagation time 36 ns + 4 ns setup time to sampling edge.

6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used.

7. This value is TDO/TDOC propagation time 16 ns + 4 ns setup time to sampling edge.

8. TDIC represents the TDI bit frame of the scan packet in compact JTAG 2-wire mode.

9. TMSC represents the TMS bit frame of the scan packet in compact JTAG 2-wire mode.

10. TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode.

11. Timing includes TCK pad delay, clock tree delay, logic delay and TDO/TDOC output pad delay.

ns ns ns ns ns

Figure 24. Nexus event trigger and test clock timings

TCK

EVTI

EVTO

74/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Figure 25. Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing

TCK

TMS/TMSC,

TDI/TDIC

TDO/TDOC

with CMOS and LVDS

(a)

pads

. Timing specifications are shown in

Table 41 ,

Table 42

and

Table 43 .

Table 40. DSPI channel frequency support

DSPI use mode

CMOS (Master mode)

LVDS (Master mode)

Full duplex – Classic timing ( Table 41

)

Full duplex – Modified timing (

Table 42 )

Output only mode (SCK/SOUT/PCS) ( Table 41 and

Table 42 )

Output only mode TSB mode (SCK/SOUT/PCS) (

Table 44

)

Output only mode TSB mode (SCK/SOUT/PCS) (

Table 43

)

1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

Max usable frequency (MHz)

(1),(2)

40 a. DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol.

DocID027866 Rev 5 75/112

111

Electrical characteristics SPC572Lx

2. Maximum usable frequency does not take into account external device propagation delay.

3.17.2.1 DSPI master mode full duplex timing with CMOS and LVDS pads

3.17.2.1.1 DSPI CMOS Master Mode – Classic Timing

Table 41. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or

1 (1)

Condition Value (2)

# Symbol C Characteristic Unit

Pad drive

(3)

Load (C

) Min Max

1 t

SCK

CC D SCK cycle time SCK drive strength

Very strong

Strong

25 pF

50 pF

33.0

80.0

—

— ns

200.0

—

2 t

CSC

Medium 50 pF

CC D PCS to SCK delay SCK and PCS drive strength

Very strong 25 pF — ns

Strong

Medium

50 pF

(4)

× t

SYS

(5)

) –

× t

) –

× t

) –

× t

) –

—

3 t

ASC

4 t

SDC

5 t

PCSC

6 t

PASC

PCS medium and SCK strong

PCS = 50 pF

SCK = 50 pF

CC D After SCK delay SCK and PCS drive strength

Very strong PCS = 0 pF

SCK = 50 pF

Strong

Medium

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

CC D SCK duty cycle (7)

PCS medium and SCK strong

PCS = 0 pF

SCK = 50 pF

SCK drive strength

CC D PCSx to PCSS time (8)

CC D PCSS to PCSx time

(8)

Very strong

Strong

Medium

0 pF

PCS strobe timing

PCS and PCSS drive strength

Strong 25 pF

PCS and PCSS drive strength

Strong 25 pF

(6)

× t

SYS

) –

× t

SYS

) –

× t

SYS

) –

× t

SYS

) –

2 t

SCK

– 2

1 /

2 t

SCK

– 2

2 t

SCK

– 5

12.0

—

2 t

SCK

+ 2 ns

1 /

2 t

SCK

+ 2

2 t

SCK

+ 5

—

— ns ns ns

76/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Table 41. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or

1 (1) (continued)

Condition Value (2)

# Symbol C Characteristic Unit

Pad drive

(3)

Load (C

) Min Max

SIN setup time

7 t

SUI

8 t

9 t

SUO

10 t

CC D SIN setup time to

SCK

(9)

SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

SIN hold time

CC D SIN hold time from

SCK

SCK drive strength

Very strong 0 pF

Strong 0 pF

Medium 0 pF

SOUT data valid time (after SCK edge)

CC D SOUT data valid time from SCK

SOUT and SCK drive strength

Very strong

Strong

Medium

25 pF

50 pF

50 pF time after SCK

SOUT data hold time (after SCK edge)

CC D SOUT data hold

(10)

SOUT and SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

25.0

31.0

52.0

–1.0

—

–7.7

–11.0

–15.0

7.0

9.0

25.0

—

— ns ns ns ns

1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

2. All timing values for output signals in this table are measured to 50% of the output voltage.

3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

5. t t

SYS

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 80 MHz (min

= 10 ns).

6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

7. t

SDC

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

8. PCSx and PCSS using same pad configuration.

9. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

DocID027866 Rev 5 77/112

111

Electrical characteristics

Figure 26. DSPI CMOS master mode – classic timing, CPHA = 0 t

CSC t

ASC

PCSx t

SDC t

SCK

SCK Output

(CPOL = 0) t

SDC

SCK Output

(CPOL = 1) t

SUI t

SPC572Lx

SIN First Data

SOUT First Data

Data t

SUO

Data

Last Data t

Last Data

Figure 27. DSPI CMOS master mode – classic timing, CPHA = 1

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

SOUT t

SUI t

First Data

Data t

SUO

Data

Last Data t

Last Data

78/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

PCSS

Figure 28. DSPI PCS strobe (PCSS) timing (master mode) t

PCSC t

PASC

PCSx

3.17.2.1.2 DSPI CMOS Master Mode – Modified Timing

Table 42. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 1 (1)

Condition Value

(2)

# Symbol C Characteristic Unit

Pad drive

(3)

Load (C

) Min Max

1 t

SCK

CC D SCK cycle time SCK drive strength

Very strong

Strong

25 pF

50 pF

33.0

80.0

—

— ns

200.0

—

2 t

CSC

3 t

ASC

4 t

SDC

Medium 50 pF

CC D PCS to SCK delay SCK and PCS drive strength

Very strong

Strong

25 pF

50 pF

D After SCK delay

D SCK duty cycle

(7)

Medium

PCS medium and SCK strong

50 pF

PCS = 50 pF

SCK = 50 pF

SCK and PCS drive strength

Very strong PCS = 0 pF

SCK = 50 pF

Strong

Medium

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS medium and SCK strong

PCS = 0 pF

SCK = 50 pF

SCK drive strength

Very strong 0 pF

Strong

Medium

0 pF

PCS strobe timing

(4)

× t

SYS

(5)

) – 16

(6)

× t

) –

× t

) –

× t

) –

× t

) –

2 t

SCK

– 2

2 t

SCK

– 2

2 t

SCK

– 5

—

— ns ns

2 t

SCK

+ 2 ns

2 t

SCK

+ 2

2 t

SCK

+ 5

DocID027866 Rev 5 79/112

111

Electrical characteristics SPC572Lx

Table 42. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 1 (1) (continued)

Condition Value (2)

# Symbol C Characteristic Unit

Pad drive

(3)

Load (C

) Min Max

5 t

PCSC

6 t

PASC

CC D PCSx to PCSS time

(8)

CC D PCSS to PCSx

time

(8)

PCS and PCSS drive strength

Strong 25 pF

PCS and PCSS drive strength

Strong 25 pF

SIN setup time

12.0

—

— ns ns

7 t

SUI

8 t

CC D SIN setup time to

SCK

CPHA = 0

(9)

SCK drive strength

Very strong

Strong

Medium

25 pF

50 pF

(10)

25 –

× t

SYS

)

31 –

× t

SYS

)

52 –

× t

SYS

)

SIN setup time to

SCK

CPHA = 1

SCK drive strength

Very strong

Strong

25 pF

50 pF

25.0

31.0

52.0

Medium 50 pF

SIN hold time

CC D SIN hold time from

SCK

CPHA = 0

SCK drive strength

Very strong 0 pF

Strong

Medium

0 pF

SIN hold time from

SCK

CPHA = 1

SCK drive strength

Very strong 0 pF

Strong 0 pF

Medium 0 pF

SOUT data valid time (after SCK edge)

1 + (P

–

× t

SYS

)

1 + (P

–

× t

SYS

)

1 + (P

–

× t

SYS

)

–1.0

—

— ns ns ns ns

80/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

Table 42. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 1 (1) (continued)

Condition Value (2)

# Symbol C Characteristic Unit

Pad drive

(3)

Load (C

) Min Max

9 t

SUO

CC D SOUT data valid time from SCK

CPHA = 0

SOUT and SCK drive strength

Very strong

Strong

Medium

25 pF

50 pF

—

7.0 + t

9.0 + t

25.0 + t

SYS

(

10 t

SOUT data valid time from SCK

CPHA = 1

SOUT and SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

SOUT data hold time (after SCK edge)

D SOUT data hold time after SCK

CPHA = 0

(11)

SOUT and SCK drive strength

Very strong 25 pF

Strong 50 pF

SOUT data hold time after SCK

CPHA = 1

Medium 50 pF

SOUT and SCK drive strength

Very strong

Strong

25 pF

50 pF

Medium 50 pF

—

–7.7 + t

–11.0 + t

–15.0 + t

SYS

SYS

7.0

9.0

25.0

—

— ns ns

–7.7

–11.0

–15.0

—

1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

2. All timing values for output signals in this table are measured to 50% of the output voltage.

3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

5. t t

SYS

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 80 MHz (min

= 10 ns).

7. t

SDC

8. PCSx and PCSS using same pad configuration.

9. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

10. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to

11. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

DocID027866 Rev 5 81/112

111

Electrical characteristics

Figure 29. DSPI CMOS master mode – modified timing, CPHA = 0 t

CSC t

ASC

PCSx t

SDC t

SCK

SCK Output

(CPOL = 0) t

SDC

SCK Output

(CPOL = 1) t

SUI t

SPC572Lx

SIN

SOUT

First Data

Data t

SUO

Data

Last Data t

Last Data

Figure 30. DSPI CMOS master mode – modified timing, CPHA = 1

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

SOUT t

SUI t

First Data

First Data t

SUO

Data

Data t

Last Data t

Last Data

82/112 DocID027866 Rev 5

SPC572Lx Electrical characteristics

PCSS

Figure 31. DSPI PCS strobe (PCSS) timing (master mode) t

PCSC t

PASC

PCSx

3.17.2.1.3 DSPI Master Mode – Output Only

Table 43. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,

CPOL = 0 or 1, continuous SCK clock

(1)(2)

Condition Value

Symbol C Characteristic Unit

Pad drive Load Min Max

5 t t t t t

SCK

CSV

CSH

SDC

SUO

D SCK cycle time LVDS

D PCS valid after

SCK

(3)

(SCK with 50 pF differential load cap.)

Very strong

Strong

D PCS hold after

SCK

(SCK with 50 pF differential load cap.)

Very strong

Strong

15 pF to 50 pF differential

25 pF

50 pF

0 pF

D SCK duty cycle

(SCK with 50 pF differential load cap.)

LVDS 15 pF to 50 pF differential

SOUT data valid time (after SCK edge)

D SOUT data valid time from SCK

SOUT and SCK drive strength

LVDS 15 pF to 50 pF differential

2 t

25.0

—

–4.0

SCK

—

– 2

2 t

—

6.0

10.5

—

SCK

8.0

+ 2 ns ns ns ns ns ns ns

6 t

SOUT data hold time (after SCK edge)

D SOUT data hold time after SCK

(4)

SOUT and SCK drive strength

LVDS 15 pF to 50 pF differential

0.0

— ns

1. All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad driver strength as defined. Timing may degrade for weaker output drivers.

2. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.

4. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

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Electrical characteristics SPC572Lx

Table 44. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,

CPOL = 0 or 1, continuous SCK clock (1)(2)

Value

(3)

# Symbol C Characteristic

Condition

Unit

Pad drive

(4)

Load (C

) Min Max

1 t

SCK

2 t

CSV

3 t

CSH

4 t

SDC

9 t

SUO

10 t

SCK cycle time

PCS valid after SCK

(5)

SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

SCK and PCS drive strength

Very strong 25 pF

Strong

Medium

PCS medium and SCK strong

50 pF

PCS = 50 pF

SCK = 50 pF

PCS hold after SCK

SCK duty cycle

(6)

Data Setup Time for Inputs

SCK and PCS drive strength

Very strong PCS = 0 pF

SCK = 50 pF

Strong

Medium

PCS medium and SCK strong

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

SCK drive strength

Very strong 0 pF

Strong

Medium

0 pF

SOUT data valid time (after SCK edge)

SOUT data valid time from SCK

CPHA = 1

(7)

SOUT and SCK drive strength

Very strong

Strong

25 pF

50 pF

Medium 50 pF

SOUT data hold time (after SCK edge)

D SOUT data hold time after SCK

CPHA = 1

(7)

SOUT and SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

33.0

80.0

200.0

–14

–33

–35

2 t

SCK

– 2

2 t

SCK

– 2

1 /

2 t

SCK

– 5

—

–7.7

–11.0

–15.0

—

7.0

9.0

25.0

—

— ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

2 t

SCK

+ 2 ns

2 t

SCK

+ 2 ns

1 /

2 t

SCK

+ 5 ns

1. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

2. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

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3. All timing values for output signals in this table are measured to 50% of the output voltage.

4. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

5. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.

6. t

SDC

7. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

Figure 32. DSPI LVDS and CMOS master timing – output only – modified transfer format MTFE = 1, CHPA = 1

PCSx t

CSV

SCK Output

(CPOL = 0) t

SDC t

SCK t

CSH

SOUT First Data t

SUO

Data t

Last Data

3.17.2.2 Slave Mode timing

10 t

SCK t

CSC t

ASC t

SDC t

Table 45. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)

(1)

Condition

Symbol C Characteristic Min Max

Pad Drive Load

D SCK Cycle Time

(2)

D SS to SCK Delay

D SCK to SS Delay

D SCK Duty Cycle

(SS active to SOUT driven)

—

— —

Very Strong 25 pF

—

Strong

Medium

50 pF

—

60 t

DIS t

SUI t

D Slave SOUT Disable

Time

(2),(3),(4)

(SS inactive to SOUT High-Z or invalid)

Very Strong 25 pF

Strong

Medium

50 pF

D Data Hold Time for Inputs

—

Unit ns ns ns ns ns ns ns ns ns ns ns ns

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Electrical characteristics SPC572Lx

Table 45. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1) (1) (continued)

Condition

Symbol C Characteristic Min Max Unit

Pad Drive Load

11 t

SUO

CC D

SOUT Valid Time

(2),(3),(4)

(after SCK edge)

Very Strong 25 pF — 30 ns

Strong

Medium

50 pF

—

55 ns ns

12 t

CC D

SOUT Hold Time

(2),(3),(4)

(after SCK edge)

Very Strong 25 pF

Strong 50 pF

2.5

—

— ns ns

Medium 50 pF 2.5

— ns

1. DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for that case only.

2. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.

3. All timing values for output signals in this table, are measured to 50% of the output voltage.

4. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

Figure 33. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) —

CPHA = 0 t

CSC t

ASC

SS t

SCK

SCK Input

(CPOL=0) t

SDC t

SDC

SCK Input

(CPOL=1) t

A t

SUO t

HO t

DIS

SOUT First Data Data Last Data t

SUI

SIN First Data Data t

Last Data

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Figure 34. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) —

CPHA = 1

SCK Input

(CPOL=0)

SCK Input

(CPOL=1) t

A t

SUO

SOUT

SIN t

SUI

First Data t

First Data

Data

Data t

Last Data t

DIS

Last Data

3.17.3.1 RMII serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

Symbol C

Table 46. RMII serial management channel timing (1)

Value

Characteristic

Min Max

Unit

M10

M11

M12

M13

M14

M15

CC D MDC falling edge to MDIO output invalid

(minimum propagation delay)

CC D MDC falling edge to MDIO output valid

(maximum propagation delay)

CC D MDIO (input) to MDC rising edge setup

D MDIO (input) to MDC rising edge hold

D MDC pulse width high

D MDC pulse width low

—

40%

—

60%

60% ns ns ns ns

MDC period

1. All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V

(TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.

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Electrical characteristics

Figure 35. RMII serial management channel timing diagram

SPC572Lx

M14

M15

MDC (output)

M10

MDIO (output)

M11

MDIO (input)

M12

M13

3.17.3.2 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency.

Table 47. RMII receive signal timing (1)

Value

Symbol C Characteristic Unit

Min Max

RXD[1:0], CRS_DV to REF_CLK setup

REF_CLK to RXD[1:0], CRS_DV hold

REF_CLK pulse width high

REF_CLK pulse width low

35%

—

65%

1. All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

ns ns

REF_CLK period

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Figure 36. RMII receive signal timing diagram

REF_CLK (input)

RXD[1:0] (inputs)

CRS_DV

R1 R2

3.17.3.3 RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK, and the timing is the same in either case. This options allows the use of non-compliant RMII PHYs.

Table 48. RMII transmit signal timing

(1)

Value

Symbol C Characteristic Unit

REF_CLK to TXD[1:0], TX_EN invalid

REF_CLK to TXD[1:0], TX_EN valid

REF_CLK pulse width high

REF_CLK pulse width low

1. RMII timing is valid only up to a maximum of 150 ° C junction temperature.

Min

—

35%

Max

—

65%

65% ns ns

REF_CLK period

Figure 37. RMII transmit signal timing diagram

REF_CLK (input)

TXD[1:0] (outputs)

TX_EN

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Electrical characteristics SPC572Lx

UART channel frequency support is shown in the following table.

Table 49. UART frequency support

LINFlexD clock frequency LIN_CLK

(MHz)

Oversampling rate Voting scheme

3:1 majority voting

100 16

Limited voting on one sample with configurable sampling point

3:1 majority voting

Limited voting on one sample with configurable sampling point

Max usable frequency

(Mbaud)

13.33

6.25

12.5

16.67

Symbol

The GPIO delay timing specification is provided in the following table.

Table 50. GPIO delay timing

C Parameter

IO_delay CC D Delay from MSCR bit update to pad function enable

Min

Value

Max

Unit ns

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4.1 ECOPACK

®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

DocID027866 Rev 5 91/112

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Package characteristics

4.2 eTQFP80 case drawing

SPC572Lx

Figure 38. eTQFP80 – STMicroelectronics package mechanical drawing

MECHANICAL PACKAGE DRAWINGS

92/112

PACKAGE CODE :A0R6

REFERENCE : 8384969

eTQFP80 BODY 10x10x1.0 mm

FOOT PRINT 1.0 mm EXPOSED PAD DOWN

JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-ACE-HD

DocID027866 Rev 5

SPC572Lx Package characteristics

Table 51. eTQFP80 – STMicroelectronics package mechanical data

Dimensions

Millimeters Inches

(1)

Symbol

Min Typ Max Min Typ Max q q1 q2 q3

(2)

(3)

(4) (5)

(4) c (4) c1

(6)

(7) (8)

(9)

(10) e

(11)

0°

10°

—

0.05

0.95

0.13

0.09

—

4.00

—

4.00

0.45

3.5°

—

12°

—

1.00

0.18

0.16

—

12.00 BSC

10.00 BSC

—

0.40 BSC

12.00 BSC

10.00 BSC

—

0.60

1.00 REF

7°

—

14°

1.20

0.15

1.05

0.23

0.19

0.20

0.16

5.83

—

5.83

—

0.75

0°

10°

—

0.002

0.037

0.005

0.004

—

0.157

—

0.157

0.018

3.5°

—

12°

—

0.039

0.007

0.006

—

0.472 BSC

0.394 BSC

—

0.016 BSC

0.472 BSC

0.394 BSC

—

0.024

0.039 REF

3.149

7°

—

14°

0.047

0.006

0.041

0.009

0.007

0.008

0.006

0.229

—

0.229

—

0.030

S aaa

(12)

bbb (12) ccc

(12) ddd

(12)

0.08

0.20

—

0.20

0.08

0.07

—

0.003

0.008

—

0.008

0.003

—

1. Values in inches are converted from millimeters (mm) and rounded to three decimal digits.

2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.

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Package characteristics SPC572Lx

3. A1 is defined as the distance from the seating plane to the lowest point on the package body.

4. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

6. To be determined at seating datum plane C.

7. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.

8. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side.

D1 and E1 are maximum plastic body size dimensions including mold mismatch.

9. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located

(if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad is variable depending on leadframe pad design (T1, T2, T3). End user should verify D2 and E2 dimensions according to specific device application.

10. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove.

11. “N” is the number of terminal positions for the specified body size.

12. Tolerance

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Figure 39. eTQFP100 – STMicroelectronics package mechanical drawing

MECHANICAL PACKAGE DRAWINGS eTQFP100 BODY 14x14x1.0 mm

FOOT PRINT 1.0 mm EXPOSED PAD DOWN

PACKAGE CODE :YE

REFERENCE : 7357321

JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-AED-HD

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Package characteristics SPC572Lx

Symbol

Table 52. eTQFP100 – STMicroelectronics package mechanical data

Dimensions

Millimeters Inches

(1)

Min Typ Max Min Typ Max q q1 q2 q3

(2)

(3) (4)

(4) c (4) c1

(5)

(6) (7)

(8)

(9) e

0°

10°

—

0.05

0.95

0.17

0.175

0.09

—

4.00

3.5°

—

12°

—

1.00

0.22

0.20

—

16.00 BSC

14.00 BSC

—

0.50 BSC

16.00 BSC

7°

—

14°

1.20

0.15

1.05

0.27

0.23

0.20

0.16

5.67

—

0°

10°

—

0.002

0.037

0.007

0.004

—

0.157

3.5°

—

12°

—

0.039

0.009

0.008

—

0.629 BSC

0.551 BSC

—

0.019 BSC

0.629 BSC

7°

—

14°

0.047

0.006

0.041

0.011

0.009

0.008

0.006

0.223

—

4.00

0.45

14.00 BSC

—

0.60

1.00 REF

100

5.67

—

0.75

—

0.157

0.018

0.551 BSC

—

0.024

0.039 REF

3.937

0.223

—

0.030

(10)

S aaa

(11) bbb

(11) ccc

ddd

0.08

0.20

—

0.15

0.20

0.05

0.07

—

0.003

0.008

—

0.006

0.008

0.002

0.003

—

1. Values in inches are converted from millimeters (mm) and rounded to three decimal digits.

2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.

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3. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

4. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

5. To be determined at seating datum plane C.

6. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.

7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side.

D1 and E1 are maximum plastic body size dimensions including mold mismatch.

8. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located

9. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove.

10. “N” is the number of terminal positions for the specified body size.

11. Tolerance

Table 53

and Table 54

describe the thermal characteristics of the device.

Symbol C

Table 53. Thermal characteristics for eTQFP80 (1)

Parameter Conditions Value Unit

θ JA

CC D Junction-to-ambient, natural convection

(2)

D Junction-to-moving-air, ambient

Junction-to-moving-air, ambient

Four layer board—2s2p 29.6

°C/W

θ JMA

CC At 200 ft./min., four layer board—2s2p

23.5

°C/W

θ JB

θ JCtop

θ JCbotttom

D Junction-to-board

(3)

D Junction-to-case top

(4)

D Junction-to-case bottom

(5)

D Junction-to-package top

(6)

Ring cold plate

Cold plate

Natural convection

9.6

13.2

1.0

0.4

°C/W

1. The values are based on simulation; actual data may vary in the given range. The specified characteristics are subject to change per final device design and characterization. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

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Package characteristics SPC572Lx

Symbol C

Table 54. Thermal characteristics for eTQFP100 (1)

Parameter Conditions Value Unit

θ JA

CC D Junction-to-ambient, natural convection (2)

Table 55 summarizes revisions to this document.

Four layer board—2s2p 27.9

°C/W

θ JMA

CC At 200 ft./min., four layer board—2s2p

22.8

°C/W

θ JB

θ JCtop

θ JCbotttom

D Junction-to-board

(3)

D Junction-to-case top

(4)

D Junction-to-case bottom

D Junction-to-package top

(5)

(6)

Ring cold plate

Cold plate

Natural convection

11.3

13.0

1.0

0.4

°C/W

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

4.4.1 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T

, can be obtained from the equation:

Equation 1 T

= T

+ (R

θ JA

* P

) where:

= ambient temperature for the package (°C)

θ JA

= junction-to-ambient thermal resistance (°C/W)

= power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:

• Construction of the application board (number of planes)

• Effective size of the board which cools the component

• Quality of the thermal and electrical connections to the planes

• Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.

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As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:

• One oz. (35 micron nominal thickness) internal planes

• Components are well separated

• Overall power dissipation on the board is less than 0.02 W/cm

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

Equation 2 T

= T

+ (R

θ JB

* P

) where:

= board temperature for the package perimeter (°C)

θ JB

= junction-to-board thermal resistance (°C/W) per JESD51-8

= power dissipation in the package (W)

When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance:

Equation 3 R

θ JA

= R

θ JC

+ R

θ CA where:

θ JA

= junction-to-ambient thermal resistance (°C/W)

θ JC

= junction-to-case thermal resistance (°C/W)

θ CA

= case to ambient thermal resistance (°C/W)

θ JC

is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, R

θ CA

. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required.

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics

(CFD) thermal models. More accurate compact Flotherm models can be generated upon request.

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Package characteristics SPC572Lx

To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter ( Ψ

) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation:

Equation 4 T

= T

+ ( Ψ

x P

) where:

= thermocouple temperature on top of the package (°C)

= thermal characterization parameter (°C/W)

= power dissipation in the package (W)

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package.

Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.

When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter ( Ψ

JPB

) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed pad) using the following equation:

Equation 5 T

= T

+ ( Ψ

JPB

x P

) where:

= thermocouple temperature on bottom of the package (°C)

= thermal characterization parameter (°C/W)

= power dissipation in the package (W)

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SPC572Lx

Figure 40. Product code structure

Example code:

SPC57

Product identifier

2 L

Core Family

Memory

Package

B C

Reserved Temperature

Frequency

Reserved

Packing

Ordering information

Y = Tray

R = Tape and Reel

6 = 80 MHz

4 = 64 MHz

C = 125 o

C Ta

F2 = eTQFP80, 0.4 mm pitch

E3 = eTQFP100, 0.5 mm pitch

64 = 1.5 MB

60 = 1 MB

L = SPC57L family

2 = Single Computing e200z2 core

SPC57 = Power Architecture in

55 nm

1. Order on 1 MB part numbers can be entered upon ST’s acceptance conditioned by volumes. Please contact your ST sales office to ask for the availability of a particular commercial product.

2. Features (e.g. flash, RAM or peripherals) not included in the commercial product cannot be used. ST cannot be called to take any liability for features used outside the commercial product.

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Revision history SPC572Lx

Date

18-Jul- 2012

Table 55. Document revision history

Revision Changes

03-Apr-2013 2

Initial release.

Formatting and editorial changes throughout document.

Table 2: SPC572Lx device feature summary :

Changed title (was SPC5726SPC572L64 device feature summary )

Figure 2 (Periphery allocation)

Removed BAR module from diagram.

Section 1.5, Features overview :

Added detail to PIT descriptions (2 bullets).

Added Saturation Instructions Extension...

feature item.

Figure 4 (100-pin QFP configuration (top view))

Changed pin 65 to “ESR1”

Table 3 (Power supply and reference pins)

For row V

DD_LV

: added pin 68 for 100 pin and 80 pin packages.

Section 2.2.1, Power supply and reference voltage pins

Added 2 sentences starting from “The Supply Pins Table contains...”

Table 5 (Port pins description):

From PC[10] to PC[15] - changed VDD_HV_IO_FLEX to VDD_HV_IO_ETH

Table 7 (Absolute maximum ratings) :

Added footnote VDD_HV_IO refers to..

Section 2.2.1, Power supply and reference voltage pins

Added 2 sentences starting from The Supply Pins Table contains...

Table 8 (ESD ratings,) :

Added classification column

Removed rows V

DD_HV_ADR_D

For row V

DD_HV_ADR:

and V

DD_HV_ADR_S

divided Value Min column data into “C” (3.0) and “P” (4.0) values and added the word reference to the Parameter description column

Changed row V

SS_HV_ADR

symbol (was V

SS_HV_ADR_D

)

Changed VDD_HV_ADV Value Min column data for P characteristic to 4.0 (was 4.2)

Table 10 (DC electrical specifications) :

For row V

DD_HV_ADR

: inverted the C and P Parameter Classification values.

Removed the following rows: V

DD_HV_IO

, V

DD_HV_ADR –

DD_HV_ADV

DD_HV_IO_JTAG,

DD_HV_IO_ETH,

DD_HV_ADV,

DD_HV_ADR,

Table 12 (I/O input DC electrical characteristics) :

In row V

IHTTL

condition changed to 4.5 V < V

DD_HV_IO

In row V

ILTTL

condition changed to 4.5 V < V

DD_HV_IO

< 5.5 V.

In row V

HYSTTL

condition changed to 4.5 V < V

DD_HV_IO

< 5.5 V.

In row V

IHCMOS_H

condition changed to 2.7 V < V

DD_HV_IO

4.0 V < V

DD_HV_IO

In row V

IHCMOS

< 4.5 V.

< 3.0 V and

< 3.0 V and condition changed to 2.7 V < V

DD_HV_IO

4.0 V < V

DD_HV_IO

In row V

ILCMOS_H

< 4.5 V.

In row V

HYSCMOS

condition changed to 2.7 V < V

DD_HV_IO

4.0 V < V

DD_HV_IO

< 4.5 V.

condition changed to 2.7 V < V

4.0 V < V

DD_HV_IO

< 4.5 V.

DD_HV_IO

< 3.0 V and

102/112 DocID027866 Rev 5

SPC572Lx Revision history

Date

03-Apr-2013

Revision

(cont.)

Table 55. Document revision history (continued)

Changes

Table 13 (I/O pull-up/pull-down DC electrical characteristics)

In row |I

WPU

In row |I

WPU

4.5 V < V

DD_HV_IO

In row |I

WPU

In row |I

WPD

In row |I

WPD

Deleted: |I

Added |I

WPU

| changed to

| (T) at V

Weak pull-up current absolute value

| (P) condition changed to V

< 5.5 V.

| (P) minimum changed to 23 µA; maximum value deleted.

| (P) condition changed to V

> V

= 0 V, 3.0 V < V

< V

> V

= 0.69*V

DD_HV_IO

| (P) minimum deleted; maximum value changed to 130 µA.

WPU

= 0.69*V

DD_HV_IO

DDE

< 4.0 V.

, 4.5 V < V

= 1.1 V (TTL), 4.5 V < V

< 5.5 V.

Added |I

WPU

Added R

WPU

Deleted: |I

Added |I

WPD

(Weak pull-up resistance).

WPD

Added |I

WPD

| (T) at V

> V

= 0.49*V

DDE

= V

DD_HV_IO

< V

= 0.49*V

DDE

< V

, 3.0 V < V

DD_HV_IO

, 4.5 V < V

= 0.9 V (TTL), 4.5 V < V

(Weak pull-down resistance).

< 4.0 V.

< 5.5 V.

Added R

WPD

Table 14 (WEAK configuration output buffer electrical characteristics) :

< 5.5 V.

Added footnote 4.

Specification changes:

In row R

OH_W

condition changed to 4.5 V < V

DD_HV_IO

In row R

OL_W

In row t

TR_W

In row t

TR_W

condition changed to 4.5 V < V

DD_HV_IO

condition C

4.5 V < V

DD_HV_IO

condition C

4.5 V < V

DD_HV_IO

= 25 pF, 4.0 V < V

DD_HV_IO

< 5.9 V

= 50 pF, 4.0 V < V

< 5.9 V

DD_HV_IO

< 5.9 V, Push pull, I

< 5.9 V changed to C

In row t

TR_W

condition C

= 200 pF, 4.0 V < V

< 5.9 V

DD_HV_IO

< 5.9 V changed to C

4.5 V < V

DD_HV_IO

Table 15 (MEDIUM configuration output buffer electrical characteristics)

< 0.5 mA.

= 25 pF,

= 50 pF,

= 200 pF,

Added footnote 4.

In R

OH_M

In R

OL_M

condition changed to 4.5 V < V

DD_HV_IO

condition changed to 4.5 V < V

DD_HV_IO

In t

TR_M

condition changed to C

< 5.9 V, Push pull, I

= 25 pF, 4.5 V < V

DD_HV_IO

= 50 pF, 4.5 V < V

DD_HV_IO

= 200 pF, 4.5 V < V

DD_HV_IO

< 5.9 V.

Table 16 (STRONG configuration output buffer electrical characteristics) :

Added footnote 4.

< 2 mA.

In R

OH_S

IN R

OL_S

condition changed to 4.5 V < V

DD_HV_IO

In t

TR_S

condition changed to 4.5 V < V

DD_HV_IO

condition changed to C

< 5.9 V, Push pull, I

= 50 pF, 4.5 V < V

DD_HV_IO

= 200 pF, 4.5 V < V

DD_HV_IO

< 5.9 V.

< 8 mA.

In t

TR_S

condition changed to C

In t

TR_S

condition C

= 50 pF, 4.5 V < V

DD_HV_IO

Table 17 (VERY STRONG configuration output buffer electrical characteristics)

Removed footnote: For specification per Electrical Physical Layer Specification 3.0.1.

Section 3.9, I/O pad current specification

Changed Note In order to ensure ... remain below 10% . changed to ...below 50% .

Table 19 (Reset electrical characteristics)

Added footnote to row I

OL_R

In row I

OL_R condition changed to

3.0 V < V

DD_HV_IO

In row I

OL_R

minimum for conditions Device under power-on reset,

3.0 V < V

DD_HV_IO

: I

OL_R

applies to both PORST and ESR0...

< 5.5 V, V

Device under power-on reset,

> 1.0 V

changed to12 mA.

Table 23 (Internal RC oscillator electrical specifications)

In row t start_T

Parameter Classification changed to D (was T ).

DocID027866 Rev 5 103/112

111

Revision history SPC572Lx

Date

03-Apr-2013

Revision

(cont.)

Table 55. Document revision history (continued)

Changes

Table 25 (SARn ADC electrical specification) :

Row V

DD_HV_ADR_S

In row V

In row TUE

removed.

Max Value cell changed to V

updated conditions

DD_HV_ADR

changed Characteristic for both conditions to T and updated conditions

In row V

ALTREF

(was V

DD_HV_ADR_S

) changed the Parameter Classification to C (was P ) .

Added phrase For parameters classified as T and D . to footnote TUE and DNL...

Table 26 (SDn ADC electrical specification)

In row f

- changed Parameter Classification for both conditions to D (was P )

Removed rows – V

For V

IN_PK2PK

In δ

GROUP

DD_HV_ADV,

SS_HV_ADR_D,

(Input range peak to peak V condition for Single ended – V

INM

IN_PK2PK

= 0.5*V

DD_HV_ADR_D

= V

INP

DD_HV_ADR_D

– V

INM

) corrected GAIN

GAIN = 2,4,8,16.

condition OSR = 75, changed Max Value to 596.

Added footnote V

INM

is the input voltage applied to the negative terminal of the SDADC.

For rows SNR

DIFF150

, SNR

DIFF333

3dB, in the range 3.6 V< V

and SNR

SE150

DD_HV_ADV

< 5.5 V .

added footnote SNR degradated by

Table 27 (Temperature sensor electrical characteristics) :

In row I

TEMP_SENS

changed description to VDD_HV_ADV power supply current .

Section 3.15.2, Main voltage regulator electrical characteristics

Changed HV and BV supply voltage descriptions.

Table 31 (Voltage regulator electrical characteristics)

Updated all values.

Figure 19 (Voltage monitor threshold definition) :

Reworked diagram

Table 32 (Voltage monitor electrical characteristics)

Refomatted table and updated all content.

Table 34 (Functional terminals state during power-up and reset) :

in TERMINAL ERROR row removed Comments.

Section 3.16, Flash memory electrical characteristics

Added content relating to Flash read wait states and added Table 35 (RWSC settings) .

Table 36 (Flash memory program and erase specifications (pending silicon characterization))

Updated footnotes, parameter classifications, Initial Max 25 °C values, Initial max parameter classifications and Typical end of life values.

Added rows t pprogrameep

In Rows t

16kprogrameep

and t qprogrameep

and t

16keraseeep

changed partition information to partition 1 .

Table 41 (DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0,

CPHA = 0 or 1)

Changed footnote Maximum frequency is 100 MHz to Maximum frequency is 80 MHz.

Table 42 (DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1,

CPHA = 0 or 1)

Changed footnote Maximum frequency is 100 MHz to Maximum frequency is 80 MHz.

Table 49 (DSPI LVDS slave timing – full duplex – modified transfer format

(MTFE = 0/1)):

Changed footnote Maximum frequency is 100 MHz to Maximum frequency is 80 MHz.

Table 49 (UART frequency support) :

Added row clock frequency 100.

Section 4.2: eTQFP80 case drawing

Added mechanical drawings.

Section 4.3: eTQFP100 case drawing

Added mechanical drawings.

Table 53 (Thermal characteristics for eTQFP80) :

104/112 DocID027866 Rev 5

SPC572Lx Revision history

Date

03-Apr-2013

Revision

(cont.)

Table 55. Document revision history (continued)

Changes

Updated table, added R

θ JA

Min and Max values

Table 54 (Thermal characteristics for eTQFP100)

Updated table, added R

θ JA

Min and Max values

Following are the changes in this version of the Datasheet:

Formatting and editorial changes throughout document.

18-May-2015 3

Table 2 (SPC572Lx device feature summary)

Replaced SIPI/LAST Interprocessor bus with Zipwire (SIPI/LAST) Interprocessor bus.

Updated the description of SENT bus.

Figure 1 (Block diagram)

Replaced LFAST & SIPI with Zipwire (LFAST & SIPI).

Section 1.5, Features overview

Reworded the PIT bullet points.

Replaced “two channel multiplexer” with “two channel multiplexers”

Removed “Port pins description” table since the table is included in the

JPC5726M_IO_Signal_Table.xlsx sheet.

Section 3.1, Introduction

Added V

DD_HV_PMC to the note section.

Table 7 (Absolute maximum ratings) :

In row V

DD_LV

added footnotes:

Allowed 1.375 – 1.45 V for 10 hours...

1.32 – 1.375 V range allowed periodically for supply...

In footnote: 1.32 – 1.375 V range allowed periodically... changed 1.275 V to 1.288 V

Removed V

DD_HV_FLA

row.

and V

DD_HV_IO_JTAG

rows.

Removed T

For I

MAXD, replaced minimum and maximum values of “-10” and “10” with “-11” and “11”.

Updated t

XRAY.

Added a note to V

DD_HV_ADV.

Table 9 (Radiated emissions testing specification) :

Added “36 dBµV” in all the rows of column “BISS radiated emissions limit”.

Table 10 (Conducted emissions testing specifications) :

Added “BISS limit” column.

Table 8 (ESD ratings,) :

Classification parameter for ESD for Human Body Model is now T.

DocID027866 Rev 5 105/112

111

Revision history SPC572Lx

Date

18-May-2015

Revision

Table 55. Document revision history (continued)

Changes

Table 10 (DC electrical specifications) :

Changed VRAMP to V

RAMP_LV pins”.

, changed parameter to “slew rate on core power supply

Added V

RAMP_HV

specification, parameter “Slew rate on HV power supply pins”, max value 100 V/ms.

Updated the classification of f

SYS

Updated the V

DD_HV_IO_MAIN

Updated the V

DD_HV_IO_JTAG

Added V

symbol.

to “C”.

classification, minimum, and maximum values.

Updated all the columns of the V

DD_HV_ADV symbol.

Replaced note below the table “Reduced output/input capabilities below 4.2 V. See performance ...” with “Reduced output/input capabilities below 4.2 V. See performance operating values in I/O pad electrical characteristics. Not all functionality are guaranteed below 4.2V. Please check ...”

(cont.)

Updated the maximum values of I

DD from “100” to “145”.

Changed the classification of I

DDPE

from “P” to “C”.

Updated the condition of I

DDAPP and the maximum value is updated to 125 mA.

Updated the parameter, conditions, and maximum values of I

DDAR.

Added another row to it.

Changed the classification of I SPIKE

from “C” to “T”.

Changed the classification of dl from “C” to “T”.

Replaced “20 us” with “< 20 us” in the conditions column of dl.

Changed the classification of I

from “C” to “D”.

Updated the parameter column of I

SR.

Deleted I

INACT_D

, I

, and T

Added V

REF_BG_T

, V

REF_BG_TC

to T

Replaced the maximum value of “90” with “60” for I

SPIKE

Replaced the maximum value of “120” with “165” for I

DDPE.

, and V

REF_BG_LR

symbols.

Table 11 (I/O pad specification descriptions)

In row Very Strong Configuration , removed reference to FlexRay.

Table 12 (I/O input DC electrical characteristics) :

For V

HYSTTL

For V

ILAUT

replaced “0.3” with “0.275” for minimum value.

replaced “2.2” with “2.1” for maximum value.

For V

HYSAUT

replaced “0.5” with “0.4” for minimum value.

Updated the I

LKG.

Updated the conditions of I

LKG_MED.

Added “GPIO input pins” to the conditions column of C

IN.

Updated Note 6 below the table.

For V

DRFTTT

, V

DRFTAUT

, and V

DRFTCMOS

replaced “C” with “T” in characteristics column.

Updated note in maximum value of V

IHAUT

Table 13 (I/O pull-up/pull-down DC electrical characteristics)

DDE

replaced by V

Updated I

WPU rows.

Updated I

WPD rows.

Added R

WPU

DD_HV_IO.

parameter.

Added conditions to R

WPD

parameter.

106/112 DocID027866 Rev 5

SPC572Lx Revision history

Date

18-May-2015

Revision

Table 55. Document revision history (continued)

Changes

Table 14 (WEAK configuration output buffer electrical characteristics) :

“4.5 V < V

DD_HV_IO

< 5.9 V” replaced by “4.5 V < V

DD_HV_IO

< 5.5 V” in R

OH_W and

OL_W rows.

Minimum values of R

OH_W and

Replaced “V

DD_HV_IO_FLEX

OL_W changed from “560” to “520”

” with “V

DD_HV_IO_ETH” in note below the table.

(cont.)

Table 15 (MEDIUM configuration output buffer electrical characteristics)

Added note to the conditions column.

“4.5 V < V

DD_HV_IO

< 5.9 V” replaced by “4.5 V < V

DD_HV_IO

OL_Mrows.

< 5.5 V” in R

OH_M and

Replaced “V

DD_HV_IO_FLEX

” with “V

DD_HV_IO_ETH” in note below the table.

Minimum values of R

OH_M and

OL_M changed from “140” to “120”

Table 16 (STRONG configuration output buffer electrical characteristics) :

Added note to the conditions column.

“4.5 V < V

DD_HV_IO

< 5.9 V” replaced by “4.5 V < V

DD_HV_IO

< 5.5 V” in R

OH_S and

OL_S rows.

Replaced “V

DD_HV_IO_FLEX

” with “V

DD_HV_IO_ETH” in note below the table.

Minimum values of R

OH_S and

OL_S changed from “35” to “30”

Updated the minimum values of t

TR_S

Table 17 (VERY STRONG configuration output buffer electrical characteristics)

Added note to the conditions column.

Updated R

OH_V and

Removed footnotes:

OL_V rows.

• Refer to FlexRay section for...

• 20–80% transition time...

Updated the minimum values of t

TR_V

Removed “EBI output driver electrical characteristics” table.

Table 18 (I/O consumption) :

Added a footnote to the table.

Removed footnote: Data based on simulation results...

Updated all the condition rows of the table.

Table 19 (Reset electrical characteristics) :

Replaced minimum value of “300” with “275” in the V

HYS row.

Replaced “0.9 V” with “1.0 V” in the in the condition column of I

OL_R row.

Replaced minimum value of “11” with “12” in the I

OL_R row.

Updated I

WPU and

WPD rows.

Table 20 (PLL0 electrical characteristics) :

Added f

PLL0PHI1 and f

PLL0FREE symbols.

Replaced maximum value of “100” with “80” in the f

PLL0PHI0 row.

In footnote: PLL0IN clock retrieved...

the second sentence now reads Input characteristics are granted when using XOSC.

In f

PLL0IN

added a second note to parameter column.

Updated maximum value of f

PLL0LOCK.

DocID027866 Rev 5 107/112

111

Revision history SPC572Lx

Date

18-May-2015

Revision

(cont.)

Table 55. Document revision history (continued)

Changes

Table 21 (External oscillator electrical specifications) :

Updated the minimum and maximum values of f

XTAL

Updated V

IHEXT

, V

ILEXT,

Added V

HYS.

g m, and

XTAL.

Table 22 (Selectable load capacitance) :

Updated the table.

Table 23 (Internal RC oscillator electrical specifications)

Removed I

AVDD5

, and I

DVDD12 rows.

Updated parameter column of δ f var_SW.

Table 24 (ADC pin specification) :

Removed I

LK_IN

symbol.

Added V

REF_BG_T

, V

REF_BG_TC

, and V

REF_BG_LR

symbols.

Updated conditions column of I

BG symbol.

Removed the table footnote “Leakage current is a....”

Added Σ I

ADR

Updated I

LK_INUD,

LK_INUSD,

LK_INREF, and

LK_INOUT.

Replaced maximum value of “6.5” with “8.5” for C

Table 25 (SARn ADC electrical specification) :

Updated conditions, minimum, and maximum columns of V

ALTREF.

Updated parameter, conditions, and maximum columns of I

ADCREFH.

Replaced the maximum value of “1” with “+8” in I

ADCREFH symbol (power down mode).

Replaced “I

ADCVDD”

with “I

ADV_S” and updated its conditions and maximum columns.

Updated minimum and maximum columns of DNL

Table 26 (SDn ADC electrical specification) :

In the f

ADCD_M

symbol replaced “S/D clock 3” with “S/D modulator Input clock”.

Added minimum value of “4”.

Updated the maximum values of |δ

GAIN

Replaced the unit values of “dB” with “dBFS” in the SNR

DIFF150

, SNR

DIFF333, and

SNR

SE150 symbols.

Replaced the unit values of “dB” with “dBc” in SFDR symbol.

Added CMRR symbol and replaced the minimum value of “20” with “54”.

Added R

Caaf

and F rolloff symbols.

Updated the maximum values of I

ADV_D and Σ I

ADR_D.

Removed Σ I

ADR_D.

Replaced maximum value of “2* δ

GROUP

” with “ δ

GROUP

” for t

LATENCY

Replaced maximum value of “15” with “ 16 ” for GAIN.

Added I

ADCS/D_REFH.

Updated the minimum, typical and maximum values of Z

Table 27 (Temperature sensor electrical characteristics) :

Added rows:

• temperature monitoring range

• temperature sensitivity (T

SENS

• temperature accuracy (T

ACC

)

108/112 DocID027866 Rev 5

SPC572Lx Revision history

Date

18-May-2015

Revision

Table 55. Document revision history (continued)

Changes

Table 28 (LVDS pad startup and receiver electrical characteristics) :

Replaced “C” with “T” in the characteristics column of I

LVDS_BIAS and

LVDS_RX.

Table 29 (LFAST transmitter electrical characteristics) , and Table 30 (MSC/DSPI LVDS transmitter electrical characteristics) :

Replaced “C” with “T” in the characteristics column of I

LVDS_TX.

Table 39 (Nexus debug port timing) :

Replaced “P” with “D” in the characteristics column of t

EVTIPW and tEVTOPW.

Figure 18 (Voltage regulator capacitance connection) :

Updated the figure.

(cont.)

Table 31 (Voltage regulator electrical characteristics)

Replaced R

DECREGn

with R

REG.

Updated the conditions column of C

DECBV and

Changed the classification of I

Added “- at 27 o

MREGINT

C , no load” to note 6.

DECHV.

from “P” to “D”.

Added “with full load” to note 7.

Table 36 (Flash memory program and erase specifications (pending silicon characterization))

For tESUS, replaced lifetime max value of “20” WITH “30”.

For tpsus, replaced lifetime max value of “10” WITH “15”.

Table 40 (DSPI channel frequency support) :

Removed “Full duplex” from LVDS (Master mode).

Table 41 (DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0,

CPHA = 0 or 1) :

Updated the minimum values of t

CSC

, t

PCSC

, and t

PASC

and maximum values of t

SUO

Table 42 (DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1,

CPHA = 0 or 1) :

Updated the minimum values of t

CSC

, t

PCSC

, and t

PASC

and maximum values of t

SUO

Removed section “DSPI LVDS Master Mode — Modified Timing.”

Table 44 (DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or

ITSB = 1, CPOL = 0 or 1, continuous SCK clock) :

Updated the minimum values of t

CSV and maximum values of t

SUO

Table 45 (DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1))

Updated the minimum and maximum values of t

DIS.

Replaced the maximum value of “50” with “55” in t

SUO (medium).

Table 48 (RMII transmit signal timing)

Replaced the maximum value of “14” with “16” for R6.

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111

Revision history SPC572Lx

Date

18-May-2015

15-Jun-2017

Revision

Table 55. Document revision history (continued)

Changes

Section 3.17.5, GPIO delay timing :

Added this section.

(cont.)

Replaced “four” with “three” in the table footnotes in Table 51 (eTQFP80 –

STMicroelectronics package mechanical data)

and Table 52 (eTQFP100 –

STMicroelectronics package mechanical data)

Table 51 (eTQFP80 – STMicroelectronics package mechanical data) :

Second note removed from E2 parameter and added to E3 parameter.

Table 53 (Thermal characteristics for eTQFP80) :

Updated the table and its values.

Table 54 (Thermal characteristics for eTQFP100)

Updated the table and its values.

Table 60 (Order codes (ST))

Updated the table.

Following are the changes in this version of the Datasheet:

Replaced eLQFP100 with eTQFP100 throughout the document.

Removed all requirement tagging from the document.

Replaced RPNs: SPC572L64F2B, SPC572L64E3B with SPC572Lx.

Replaced SPC572LxB with SPC572Lx.

Replaced bullet point “On-chip voltage...” with “Single 5V +/-10%....” on the cover page.

Table 1 (Device summary)

– Updated the table.

Table 2 (SPC572Lx device feature summary)

– Updated the notes of “External power supplies”

Section 3.4: Electromagnetic Compatibility (EMC) :

– Updated the section.