STMicroelectronics ST200-TOOLSET Reference Manual

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Belge

Reklam

STMicroelectronics

ST231 core and instruction set architecture

Reference manual

7645929 Rev N

September 2009

BLANK

Reference manual

ST231 core and instruction set architecture

Introduction

The 32-bit ST231 is a member of the ST200 family of cores.

This family of embedded processors uses a scalable technology that allows variation in instruction issue width, the number and capabilities of functional units and register files, and the instruction set.

●

The ST200 family includes the following features: parallel execution units, including multiple integer ALUs and multipliers architectural support for data prefetch predicated execution through select operations efficient branch architecture with multiple condition registers encoding of immediate operands up to 32 bits support for user and supervisor modes and memory protection

September 2009 7645929 Rev N 1/331 www.st.com

Contents

ST231

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ST200 document identification and control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ST200 documentation suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Conventions used in this guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Acknowledgements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.1

VLIW overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.2

ST231 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.3

Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1

Integer units (IU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2

Multiply units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3

Load/store unit (LSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Cache purging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Dismissible loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4

Branch unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.1

2.4.2

Idle mode macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

syncins macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Architectural state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2

3.2.1

Link register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3

Branch register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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3.4

Program status word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

USER_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DEBUG_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PSW access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Execution pipeline and latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1

Execution pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2

Operation latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3

Branch stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4

Interlocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5

Additional notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5.1

4.5.2

Flushing the pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Restrictions on link register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Traps (exceptions and interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1

Trap mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2

Exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3

Saved execution state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.5

Debug interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.6

Exception types and priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.6.1

Illegal instruction definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.7

Speculative load considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.7.1

Misaligned implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Memory translation and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1

TLB overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.2

Address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2.1

6.2.2

Physical addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Virtual addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3

Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.1

Instruction cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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6.3.2

Data cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TLB_INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TLB_ENTRY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TLB_ENTRY1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

TLB_ENTRY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

TLB_ENTRY3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

TLB_REPLACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

TLB_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.4.9

TLB_ASID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.4.10

TLB_EXCAUSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.5

TLB description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

UTLB arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Instruction accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Data accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.6

Speculative control unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.6.1

6.6.2

6.6.3

SCU_BASEx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SCU_LIMITx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Updates to SCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.1

Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2

I-side memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2.1

7.2.2

7.2.3

Instruction buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

I-side bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.3

D-side memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Load/store unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Data cache partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Speculative loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Cached loads and stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Uncached load and stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Prefetching data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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7.3.7

7.3.8

Purging data caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

D-side synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.3.9

D-side bus errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.3.10

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.3.11

Cache policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.3.12

Write buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.4

Core memory controller (CMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.5

Additional notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Memory ordering and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 59

Coherency between I-side and D-side . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Cached data in uncached region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Prefetch performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Streaming data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.1

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.1.1

Data width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.2

Communication channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.2.1

Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.3

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.3.1

8.3.2

8.3.3

Input channel memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Output channel memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.4

Interrupts, exceptions and restarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.4.1

8.4.2

8.4.3

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

SDI exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Restart (soft reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.1

Access operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.2

Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.3

Control register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

9.4

Data cache replacement state register . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9.5

Version register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.1

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.1.1

TIMEDIVIDEi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.1.2

TIMECOUNT

i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.1.3

TIMECONST

i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.1.4

TIMECONTROL i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2

Timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3

Programming the timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Peripheral addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11.1

Access to peripheral registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11.2

Peripheral addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11.2.1

Interrupt controller and timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.2.2

DSU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.2.3

DSU ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

12.1

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

12.2

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

12.2.1

Test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

12.2.2

Master interrupt input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

12.3

Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

12.3.1

Interrupt pending register (INTPENDING) . . . . . . . . . . . . . . . . . . . . . . . 81

12.3.2

Interrupt mask register (INTMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

12.3.3

Interrupt mask set and clear registers (INTMASKSET and INTMASKCLR)

12.3.4

Interrupt test register (INTTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

12.3.5

Interrupt set and clear registers (INTSET and INTCLR) . . . . . . . . . . . . 84

Debugging support (TAPLink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

13.1

Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

13.1.1

Debug interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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Contents

13.1.2

Hardware breakpoint support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

13.2

Debug support unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13.2.1

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13.2.2

Shared register bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.2.3

DSU control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.3

Debug ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

13.3.1

Debug initialization loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

13.3.2

Default debug handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

13.4

Host debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

13.4.1

Message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

13.4.2

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Debugging support (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.1

Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.1.1

Debug interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.1.2

Hardware breakpoint support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

14.2

Debug support unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

14.2.1

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

14.2.2

Shared register bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

14.2.3

DSU control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

14.3

Debug ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

14.3.1

Debug initialization loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

14.3.2

Default debug handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

14.3.3

User-defined debug handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

14.4

Host debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

14.4.1

Protocol and flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

14.4.2

Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

14.4.3

Handling events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Performance monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

15.1

Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

15.2

Access to registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

15.3

Control register (PM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

15.4

Event counters (PM_CNTi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

15.5

Clock counter (PM_PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

15.6

Recording events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7645929 7/331

Contents

ST231

Execution model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

16.1

Bundle fetch, decode, and execute . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

16.2

Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

16.2.1

Bundle decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

16.2.2

Operation execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

16.2.3

Exceptional cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Specification notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

17.1

Variables and types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

17.1.1

Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

17.1.2

Boolean . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

17.1.3

Bit-fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

17.1.4

Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

17.2

Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

17.2.1

Integer arithmetic operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

17.2.2

Integer shift operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

17.2.3

Integer bitwise operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

17.2.4

Relational operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

17.2.5

Boolean operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

17.2.6

Single-value functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

17.3

Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

17.3.1

Undefined behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

17.3.2

Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

17.3.3

Conditional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

17.3.4

Repetition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

17.3.5

Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

17.3.6

Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

17.4

Architectural state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

17.5

Memory and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

17.5.1

Support functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

17.5.2

Memory model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

17.5.3

Control register model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

17.5.4

Cache model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

17.5.5

Architectural state model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

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18 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

18.1

Bundle encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

18.1.1

Extended immediates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

18.1.2

Encoding restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

18.2

Operation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

18.3

Example operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

18.3.1

add Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

18.4

Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

18.5

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Appendix A Instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

A.1

Reserved bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

A.2

Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

A.3

Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

A.4

Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Appendix B STBus endian behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

B.1

Endianness of bytes and half-words within a word based memory. . . . . 320

B.2

Endianness of 64-bit accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

B.3

System requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

List of instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

7645929 9/331

Preface

Preface

ST231

ST200 document identification and control

Each book in the ST200 documentation suite carries a unique ADCS identifier of the form:

ADCS nnnnnnnx where nnnnnnn is the document number, and x is the revision.

Whenever making comments on an ST200 document, the complete identification

ADCS nnnnnnnx should be quoted.

ST200 documentation suite

The ST200 documentation suite comprises the following volumes:

ST231 Core and Instruction Set Architecture

(ADCS 7645929) This manual describes the architecture and the instruction set of the

ST231 core as used by STMicroelectronics.

ST200 User Manual

(ADCS 8063762) This manual describes the ST200 Micro Toolset and provides an introduction to OS21. It covers the various cross tools and libraries that are provided in the toolset, the target platform libraries, how to boot OS21 applications from ROM and how to port applications which use STMicroelectronics’ OS20 operating systems. Information is also given on how to build the open source packages that provide the compiler tools, base run-time libraries and debug tools and how to set up an ST Micro Connect.

ST200 Micro Toolset Compiler Manual

(ADCS 7508723) This manual provides a detailed guide to using the ANSI C and C++ compiler drivers for compiling and linking source code to produce an executable binary. The compiler drivers are introduced in terms of how they fit into the complete ST200 toolchain.

The manual then concentrates on the facilities provided by the compiler drivers to produce efficient code. It covers: command line options, predefined macros, supported pragmas, compiler optimization techniques, GNU C and C++ language extensions and asm construct, the assembly language and intrinsic functions.

ST200 Run-time Architecture Manual

(ADCS 7521848) This manual describes the common software conventions for the ST200 processor run-time architecture.

ST200 ELF Specification

(ADCS 7932400) This document describes the use of the ELF file format for the ST200 processor. It provides information needed to create and interpret ELF files and is specific to the ST200 processor.

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ST231 Preface

OS21 User Manual

( ADCS 7358306) This manual describes the royalty free, light weight, OS21 multitasking operating system.

OS21 for ST200 User Manual

(ADCS 7410372) This manual describes the use of OS21 on ST200 platforms. It describes how specific ST200 facilities are exploited by the OS21 API. It also describes the OS21 board support packages for ST200 platforms.

Conventions used in this guide

General notation

●

The notation in this document uses the following conventions: sample code , keyboard input and file names variables and code comments screens , instructions code variables

, windows and dialog boxes

Hardware notation

The following conventions are used for hardware notation:

●

PIN NAMES and SIGNAL NAMES

Software notation

●

Syntax definitions are presented in a modified Backus-Naur Form (BNF). Briefly:

● Terminal strings of the language, that is, strings not built up by rules of the language, are printed in teletype font. For example, void .

● Nonterminal strings of the language, that is, strings built up by rules of the language, are printed in italic teletype font. For example, name .

●

If a nonterminal string of the language starts with a nonitalicized part, it is equivalent to the same nonterminal string without that nonitalicized part. For example, vspacename .

Each phrase definition is built up using a double colon and an equals sign to separate the two sides (‘ ::= ’).

Alternatives are separated by vertical bars (‘ | ’).

Optional sequences are enclosed in square brackets (‘

Items which may be repeated appear in braces (‘ {

[

’ and ‘

} ’).

] ’).

7645929 11/331

Preface ST231

Acknowledgements

The ST231 core is based on technology jointly developed by Hewlett-Packard Laboratories and STMicroelectronics.

Microsoft

, Visual Studio

and Windows

are registered trademarks of Microsoft

Corporation in the United States and/or other countries.

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ST231

1 Overview

Overview

This chapter provides an introduction to the ST231 processor and to this reference manual.

VLIW (very long instruction word) processors use a technique where instruction level parallelism is explicitly exposed to the compiler, which must schedule operations to account for the operation latency. The hardware implementation of a VLIW processor is significantly simpler than a corresponding multiple issue superscalar CPU because of the simplicity of the grouping and scheduling hardware; the complexity is passed to the instruction scheduling software (compiler and assembler) which is responsible for scheduling the parallel operations for maximum efficiency.

RISC-like operations (syllables) are grouped into bundles (wide words). The operations in a bundle are issued simultaneously. In the ST200 family operations also complete simultaneously. While the delay between issue and completion is the same for all operations, some results are available for bypassing to subsequent operations prior to completion. This is discussed further in

Chapter 4: Execution pipeline and latencies on page 22

The ST231 includes the ST231 core and associated peripherals. Figure 1

shows the arrangement of these components in a block diagram.

Figure 1.

Block diagram of the ST231

ST231 core

SDI ports

ITLB

Mul Mul

ICache

Instruction buffer

8 read

4write)

DTLB

Load/ store unit

(LSU)

UTLB 4 x SDI

Control registers

Write buffer

DCache

SCU

STBus

CMC

64-bit

Prefetch cache

D-side memory subsystem

I-side memory subsystem

PC and branch unit

Branch register file

IU IU IU IU

Trap controller

Peripherals

Timers

Interrupt controller

Debug support unit

STBus

32-bit

61 interrupts Debuglink

7645929 13/331

Overview ST231

This manual describes the architecture and instruction set of the ST231 implementation.

This section gives an outline of the following document.

The processor is made up of a number of functional units described in

Chapter 2: Execution units which operate on data stored in the register files (

Chapter 3: Architectural state ).

These functional units are pipelined and subject to explicit observable latencies (

Chapter 4:

Execution pipeline and latencies ).

The handling of exceptions and interrupts are detailed in Chapter 5: Traps (exceptions and interrupts) .

The ST231 accesses memory through the memory subsystem ( Chapter 7: Memory subsystem ) which provides protection and address translation by means of a translation

lookaside buffer ( Chapter 5: Traps (exceptions and interrupts)

The ST231 has four SDI ports ( Chapter 8: Streaming data interface

) which allow it to communicate rapidly with other devices and avoid cache pollution when processing large amounts of data.

Control of the devices is performed using the memory mapped control registers defined within the relevant chapters. The address of the control registers and PSW are detailed in

Chapter 9: Control registers

The ST231 also provides a performance monitoring system to help with software

optimization and debugging ( Chapter 15: Performance monitoring

The following peripheral devices are also provided: timers ( Chapter 10: Timers ), interrupt

control ( Chapter 12: Interrupt controller ) and debug support

(a)

(

Chapter 13: Debugging support (TAPLink)

or Chapter 14: Debugging support (JTAG) ). The peripheral register

addresses are detailed in

Chapter 11: Peripheral addresses

The execution model is described in

Chapter 16: Execution model

. The execution of bundles is described in

Section 16.1: Bundle fetch, decode, and execute on page 116 , including the

behavior of the machine when exceptions or interrupts are encountered.

Chapter 18: Instruction set

describes the details of each operation, including the semantics.

The instruction set includes details of the instruction set encoding, syntax and semantics.

The encoding of bundles is defined in Section 18.1: Bundle encoding on page 137

The behavior of operations is specified using the notational language defined in

Chapter 17:

Specification notation on page 119

through Section 17.3: Statements on page 125

. The descriptions clearly identify where architectural state is updated and the latency of the operands.

A simple model of memory and control registers defined in Section 17.5.2: Memory model on page 130

and

Section 17.5.3: Control register model on page 134 is used when

specifying load and store operations.

14/331 a.

Only one of the debugging support chapters is applicable depending upon the version of the core implemented.

Please refer to the product datasheet for specific variant details.

7645929

ST231 Execution units

2.1

The functional core of ST231 comprises of a number of execution units working on two register files. The execution units include 4 integer units, 2 multiply units, a load/store unit and a branch unit which are all described in this chapter. The two register files, the branch

registers and the general purpose registers are described in Chapter 3: Architectural state on page 19

Integer units (IU)

The ST231 has four identical integer units. Each integer unit is capable of executing one operation per cycle. The results of the integer units can be used as operands of the next bundle. This is equivalent to a pipeline depth of one cycle.

Each operation can take up to three operands in the form of two 32-bit values and a single conditional bit. The IU then executes the appropriate operation and produces up to two results in the form of a 32-bit value and a 1-bit conditional value. The integer operations supported are detailed in the

Chapter 18: Instruction set on page 137

2.3

The ST231 has two identical multiply units. Each multiply unit is pipelined with a depth of three cycles, executing an operation every cycle.

Each multiply units takes two 32-bit operands and produces a single 32-bit result. The multiply operations supported are detailed in the

Chapter 18: Instruction set on page 137

Load/store unit (LSU)

The ST231 has a single load/store unit. The load/store unit is pipelined with a depth of three cycles, executing an operation every cycle.

The load store can take up to three 32-bit operands and may produce a single 32-bit result depending on the operation. The load store operations supported are detailed in the

Chapter 18: Instruction set on page 137 .

Memory access protection and translation is implemented by the TLB, this is part of the memory sub-system. The TLB also controls the cache behavior of data accesses,

Chapter 6: Memory translation and protection on page 31

Uncached accesses or accesses which miss the data cache cause the load/store unit to stall the pipeline to ensure correct operation.

7645929 15/331

Execution units ST231

Note:

The ST231 uses a single 32-bit address space to address the external memory system.

Peripheral devices and control registers are also mapped into the address space.

All cacheable memory transactions are made using the data cache. The data cache determines if an external memory access (using the STBus) is required to complete the request.

Cacheable STORE memory transactions that miss are written to the write buffer not the data cache.

Uncached accesses are performed directly on the memory system, see to

Section 7.3.5:

Uncached load and stores on page 53

The ST231 supports one addressing mode – the effective address is an immediate

(constant) plus a register.

2.3.3 Alignment

All LOAD and STORE instructions work on data stored on the natural alignment of the data type; that is, words on word boundaries, half-word on half word boundaries.

LOAD and STORE operations with misaligned addresses raise an exception which makes possible the implementation of misaligned LOAD s by trap handlers.

For a byte or half-word LOAD , the data from memory is loaded into the least significant part of a register and is either sign-extended or zero extended according to the instruction definition.

For a byte or half-word STORE , the data stored from the least significant part of a register.

The LSU maps a part of the address space that is devoted to control registers (see

Chapter 9: Control registers on page 67

for details). The LSU control register block intercepts LOAD s and STORE s to this area of memory so that it can process the operation.

No access to the data cache is made for control register operations. Transactions are made across the 32-bit control register bus to those control registers that live outside the LSU.

Cache purging (flush and invalidate) operations are provided on the ST231.

They allow for purging lines and sets from the data cache, and invalidating the entire instruction cache.

16/331

Dismissible LOAD s are used to support software load speculation. This allows the compiler to schedule a LOAD in advance of a condition that predicates its use.

Dismissible LOAD s are required to return the same value as a normal LOAD if such an operation can be executed without causing an exception. Otherwise dismissible LOAD s return zero.

7645929

ST231 Execution units

In the event that misaligned accesses are supported through a software trap handler, the

ST231 may be configured to trap non-aligned dismissible LOADs, see the Chapter 5: Traps

(exceptions and interrupts) on page 25

. The TLB can be configured to return zero for dismissible LOADs in cases where they can be executed without exception; this is to support peripherals which have destructive read behavior.

The ST231 has one branch unit. This unit supports both relative immediate branches (with and without condition code) and absolute and relative jumps and calls.

A conditional branch is performed using the BR and BRF instructions. These instructions have two operands, a condition code register and the immediate offset of the branch.

An unconditional branch is performed using the GOTO (immediate) instruction. This instruction has one operand containing the immediate offset of the branch.

An unconditional jump is performed using the GOTO (link register) instruction. This instruction causes a control transfer to the address stored in the link register, see

Section 3.2.1: Link register on page 19 .

An unconditional call is performed using the CALL (link register) and CALL (immediate) instructions. These instruction cause a control transfer to the address stored in the link

register (see Section 3.2.1: Link register on page 19

) or to the specified immediate offset.

After the call, the link register contains the return address.

Due to pipeline restrictions all branches and jumps incur a penalty of one cycle of stall.

The IDLE mode macro is encoded as a bundle containing a GOTO (immediate) to the same bundle. The IDLE mode macro must be alone in a bundle (otherwise it is treated as a normal GOTO ).

The IDLE mode macro is architecturally identical to the branch it is derived from. When an interrupt or debug interrupt occurs the core exits idle mode and jumps to the correct handler.

Implementation notes

●

When an IDLE mode macro is executed the ST231: empties the pipeline, completing any instructions issued before the idle, waits for all outstanding bus transactions to complete:

– all prefetches issued to the bus have completed (responses have come back)

– all writes issued to the bus have completed (responses have come back) waits for the SDI output buffer to be become empty enters idle mode

The core will not enter idle mode while the performance monitoring hardware is enabled.

When the core enters idle mode a bit is set in the PM_CR register, see

Section 15.3: Control register (PM_CR) on page 114

7645929 17/331

Execution units ST231

●

The core discontinues entry to idle mode and jumps to the correct handler on the following conditions:

STBus error exception external interrupt debug interrupt

The core exits idle mode and jumps to the correct handler on the following conditions:

●

● external interrupt debug interrupt

●

While in idle mode:

●

● timers continue to operate normally the SDI input ports do not accept data the SDI output ports do not send out data as they must be empty before the core enters idle mode the peripheral blocks accepts and responds to STBus transactions as normal the DSU continues to operate as normal (both using the TAPLink and using the STBus)

The syncins macro can be used to ensure that all previous instructions have completed and all new instructions have not yet started. The syncins macro ensures that the pipeline is empty and the instruction buffer is purged.

The syncins macro may only be executed in supervisor mode.

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ST231 Architectural state

3.1

●

This chapter describes the architectural state of the ST231 core, which consists of the following elements: program counter register file branch register file program status word control registers

Program counter (PC)

The PC contains a 32-bit byte address pointing to the beginning of the current bundle in memory. The two LSBs of the PC are always zero.

The general purpose register file contains 64 words of 32 bits each. These are named R0 to

R63.

Reading register zero (R0) always returns the value zero. Writing values to R0 has no effect on the processor state.

3.3

3.4

Register R63, the architectural link register, is used by the call and return mechanism. R63 is updated by explicit register writes and the call operation. Some restrictions apply to

accessing the link register, see Section 4.5.2: Restrictions on link register on page 24 .

Branch register file

The branch register file contains eight single bit branch registers, B0 to B7.

Program status word (PSW)

The program status word (PSW) contains control information that affects the operation of the ST231 processor.

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Architectural state ST231

Table 1.

Name

USER_MODE

INT_ENABLE

TLB_ENABLE

TLB_DYNAMIC

SPECLOAD_MALIGNTRAP_EN

Reserved

The PSW contains the bit fields listed in Table 1 .

PSW bit fields

DBREAK_ENABLE

IBREAK_ENABLE

DEBUG_MODE

Bit(s)

[31:13]

Writable Reset Comment

0x0

0: the core is in supervisor mode

1: the core is in user mode

0: external interrupts are disabled

1: external interrupts are enabled

0: address translation is disabled

1: address translation is enabled

0: speculative loads and purge address ignore “no mapping” violations.

1: speculative loads and purge address cause “no mapping” violations.

0: disables exceptions on speculative load misalignment errors.

1: enables exceptions on speculative load misalignment errors.

Reserved

0: data breakpoints are disabled

1: data breakpoints are enabled

0: instruction breakpoints are disabled

1: instruction breakpoints are enabled

Reserved

0: the core is not in debug mode

1: the core is in debug mode

Reserved

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ST231 Architectural state

3.4.2 USER_MODE

The USER_MODE bit indicates whether the machine is in user mode or supervisor mode.

When in user mode, the processor has restricted access:

● the TLB (see

Chapter 6: Memory translation and protection on page 31

level of access to memory in both user and supervisor modes

) defines the

●

in user mode there is limited access to control registers, see Chapter 9: Control registers on page 67

●

certain instructions can not be executed in user mode, see on page 137

Chapter 18: Instruction set

3.4.3 DEBUG_MODE

The DEBUG_MODE bit indicates whether the machine is in debug mode. For the effect of

writing to DEBUG_MODE, see Exiting debug mode on page 88 .

Note:

The PSW can be read as a control register, Section 3.5: Control registers on page 21 .

The pswset instruction is used to set any number of bits in the PSW atomically. The pswclr instruction is used to clear any number of bits in the PSW atomically.

The PSW can also be updated by means of an rfi operation. The required status word should be stored into the SAVED_PSW and the address of the code to be executed directly after the change should be stored in the SAVED_PC. Then executing an rfi atomically copies the SAVED_PSW into the PSW and the SAVED_PC into the PC.

Example : Procedure to write the PSW, (in ST231 assembler code),

_sys_set_psw

stw SAVED_PC[$r0] = $r63;; // Return address

stw SAVED_PSW[$r0] = $r4;; // New value

nop ;;

rfi ;;

Interrupts must be disabled during this sequence to prevent SAVED_PC and SAVED_PSW from being changed.

Additional architectural state is held in a number of memory mapped control registers,

Chapter 9: Control registers on page 67

. These registers include support for interrupts and exceptions, and memory protection.

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Execution pipeline and latencies

4 Execution pipeline and latencies

ST231

This chapter describes the architecturally visible pipeline and operation latencies for the

ST231.

●

The ST231 uses a pipelined execution scheme. This pipeline is architecturally visible in a number of areas: operation latencies branch stalls bypassing usage restrictions

The execution pipeline is three cycles long and comprises three stages E1, E2 and E3. All operations begin in E1. Operands are read or bypassed to an operation at the start of E1. All results are written at the end of E3.

This execution pipeline allows arithmetic and load / store operations to execute for up to three cycles. The results of operations which complete earlier than E3 are made available for bypassing as operands to subsequent operations, though strictly operations do not complete until the end of the E3 stage. This is when the architectural state is updated.

The pipeline is designed to efficiently implement the serial execution of the code, see

Chapter 16: Execution model on page 116

Note:

ST231 operations begin in E1 cycle and complete in either E1, E2 or E3. The time taken for an operation to produce a result is called the operation latency. For simple operations like add and subtract the latency is a single cycle. For operations like multiply and load the latency is three cycles.

Operational latencies may vary between different members of the ST200 processor family.

The ST231 has no penalty for not taken branches.

The ST231 stalls for one cycle when a branch is taken. There may be a further stall caused

by the destination bundle of a branch crossing an I-cache line boundary. See Section 7.2.1:

Instruction buffer on page 49

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4.4 Interlocks

●

The ST231 provides operation latency interlock checking. This enforces the latency between all operations by stalling the pipeline, with the following exceptions: store to SAVED_PSW to store to SAVED_PC to rfi rfi store to SAVED_SAVED_PSW to store to SAVED_SAVED_PC to rfi rfi

In the cases listed above, the software must ensure that the control register has been updated before executing the rfi

. See Section 3.4.4: PSW access on page 21

for further details of how to do this.

For all other cases, the ST231 automatically stalls the pipeline to uphold the internal latency constraints. As such there are no possible latency violations for the above cases.

For optimal machine usage, bundles containing useful operations should be inserted in order to respect the underlying latency between operations.

Additional information about flushing the pipeline and restrictions on the link register are provided in this section.

As state is stored within the pipeline, some changes require that state to be flushed out to ensure coherency. For example, the ST231 pipeline needs to be flushed to ensure that

UTLB updates take effect. (For the recommended sequence for UTLB updates, see

Coherency on page 40 ).

The following instructions cause the pipeline to be emptied:

●

● rfi pswset pswclr prgins prginspg

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Execution pipeline and latencies

4.5.2

ST231

Restrictions on link register

To optimize performance, the ST231 contains a speculative link register (SLR). This is a copy of possible future updates to R63. In the current implementation, this register is updated earlier in the pipeline than R63. The core uses SLR as the source for register indirect branch operations.

There are circumstances when SLR is not a true copy of R63. This occurs when an interrupt or exception is taken immediately before an update to R63 but after the SLR has been speculatively changed. The solution to this is to ensure that all interrupt and exception handlers write explicitly to R63 prior to the execution of an rfi , call $r63 or goto $r63 . This requirement can easily be met with a mov operation from R63 to R63 in one of the first bundles of the trap handler.

Register indirect call and goto operations also require R63 to be stable. If R63 is modified in the three bundles preceding one of these operations, an interlock stall occurs.

A number of operations cannot target R63 for efficiency reasons. These include multiply operations, byte and half-word load

operations, see Chapter 18: Instruction set on page 137

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5

Traps (exceptions and interrupts)

Traps (exceptions and interrupts)

In the ST231 architecture, exceptions and interrupts are jointly termed traps. This chapter describes the trap mechanism.

The ST231 defines two types of traps:

●

● external asynchronous traps (interrupts and bus errors), internal synchronous traps (exceptions resulting from operation execution).

A trap point is the point in the program execution where a trap occurs. All bundles executed before the trap point have finished updating the architectural state; no architectural state has been updated by subsequent bundles. For an exception, the trap point is the (start of the) bundle which caused the exception. For an interrupt, the trap point is (the start of) the bundle whose execution has been interrupted. Typically this is a bundle that had been executed shortly after the interrupt was raised or enabled.

The flow diagram,

Figure 16 on page 101 defines when a trap is taken. The aim of this

chapter is to define the steps that are carried out when a trap is to be taken.

In effect, taking a trap can be viewed as executing an operation that branches to the required handler, with a number of side effects. The side effects are defined by the statements below. An external interrupt is treated as an EXTERN_INT exception, with only debug interrupts being handled differently.

At the trap point, the ST231 transfers execution to the trap handler, starting at the address held in the HANDLER_PC control register, and saves the execution state as detailed in

Section 5.3: Saved execution state

. All operations issued before the trapping bundle are allowed to complete. All operations issued after and including the trapping bundle are discarded. The architectural state, with the exception of saved execution state, is exactly that at the trap point. Hence ST231 interrupts and exceptions can be considered precise.

Traps are handled strictly (in order), and indivisibly with respect to the bundle stream.

Due to the fact that more than one operation can execute at the same time, it is possible to have more than one exception thrown in a bundle. In this case, only the highest priority exception is passed to the handler.

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Traps (exceptions and interrupts)

5.3

ST231

Saved execution state

Directly following a trap the saved execution state defines the reason for the trap and the precise trap point in the execution flow of the processor. Control registers store these values for use by the handler routine.

Taking an exception can be summarized as:

NEXT_PC

←

// Branch to the exception handler

EXCAUSE

←

// Store information

EXADDRESS

←

// for the handler

SAVED_PSW

←

// Save the PSW and PC

SAVED_PC

←

PSW[USER_MODE]

←

// Enter supervisor mode

PSW[INT_ENABLE]

←

// Disable interrupts

PSW[IBREAK_ENABLE]

←

// Disable instruction breakpoints

PSW[DBREAK_ENABLE]

←

// Disable data breakpoints

Where the function HighestPriority returns the highest priority exception from those that have been thrown, refer to

Section 5.6

. The

ExceptAddress function defines the value that is stored into the EXADDRESS control register. Its return value is either 0 or the address of the data or instruction which has triggered the exception.

Therefore: variable

← is equivalent to:

IF ((exception = DBREAK) OR

(exception = MISALIGNED_TRAP) OR

(exception = CREG_NO_MAPPING) OR

(exception = CREG_ACCESS_VIOLATION) OR

(exception = DTLB) OR

(exception = ITLB)) THEN

variable

←

ELSE

variable

←

Where value

is the optional argument that is passed to THROW (see Section 17.3.5:

Exceptions on page 127 ) when the exception was generated.

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ST231 Traps (exceptions and interrupts)

The core uses a rfi (return from interrupt) operation to recommence execution at the trap point. An rfi operation causes the following state updates:

←

// Address execution control is

// transferred to by rfi. Can be

// altered during the exception

// handler routine.

PSW

←

// Restore saved_psw. Can be

// altered during the exception

// handler routine.

SAVED_PC

←

// Restore previous saved_pc

SAVED_PSW

←

// Restore previous saved_psw

5.4 Interrupts

All interrupts are effectively treated by the ST231 as an exception of type EXTERN_INT.

Individual interrupt lines are indicated by registers in the interrupt controller. See

Chapter 12: Interrupt controller on page 80 .

Refer to

Chapter 13: Debugging support (TAPLink) on page 87 .

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Traps (exceptions and interrupts)

5.6

ST231

Exception types and priorities

The EXCAUSENO control register gives the cause of the last exception. Since only one exception is thrown at a time, simultaneous exceptions are prioritized. The bit fields for this register are listed in

Table 2.

Table 2.

Name

EXCAUSENO

Reserved

EXCAUSENO bit fields

Bit(s) Writable

[4:0]

[31:5]

Reset Comment

0x0 Specifies the exception number.

0x0 Reserved.

For backward compatibility, the exception cause is also available as a bit-field by reading the EXCAUSE register. The EXCAUSE register is read only and always returns

1 << EXCAUSENO_EXCAUSENO .

Table 3 shows the possible exceptions and the value in the EXCAUSENO bitfield of the

EXCAUSENO control register that each corresponds to. The table is listed in exception priority order starting with the highest priority.

Table 3.

Name

EXCAUSENO_EXCAUSENO values

Value Comment

STBUS_IC_ERROR

STBUS_DC_ERROR

EXTERN_INT

IBREAK

ITLB

SBREAK

ILL_INST

SYSCALL

DBREAK

MISALIGNED_TRAP

CREG_NO_MAPPING

CREG_ACCESS_VIOLATION

DTLB

RESERVED

SDI_TIMEOUT

The instruction cache caused a bus error.

The data cache caused a bus error.

There was an external interrupt.

An instruction address breakpoint has occurred.

An instruction related TLB exception has occurred.

A software breakpoint was found.

The bundle could not be decoded into legal sequence of operations or a privileged operation is being issued in user mode.

System call.

A breakpoint on a data address has been triggered.

The address is misaligned and misaligned accesses are not supported.

The load or store address was in control register space, but no control register exists at that exact address.

A store to a control register was attempted whilst in user mode.

A data related TLB exception has occurred.

Reserved

One of the SDI interfaces timed out while being accessed.

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ST231 Traps (exceptions and interrupts)

5.7

An illegal instruction exception is caused when an illegal bundle is executed. A legal bundle

and all syllables contained in it must conform to the restrictions as detailed in Chapter 18:

Instruction set on page 137

●

In particular, a legal bundle and all the syllables it contains must conform to the following.

●

All syllables must be valid operations or an immediate extension.

A bundle must have a stop bit that is, four zero stop bits are illegal.

Unused opcode fields must be set to zero, including bit 30.

Any branch , call , rfi , pswset and pswclr operation must appear as the first syllable of a bundle.

Multiply operations must appear at odd word addresses.

Immediate extensions must appear at even word addresses.

●

Immediate extensions must associate with an operation that is in the same bundle and has an immediate format that can be extended.

There may be no more than one immediate extension associated with a single operation.

●

A privileged operation can only be executed in supervisor mode. This includes rfi , pswset , pswclr , prginspg and prgins .

There can only be one operation requiring the load/store unit in each bundle. This includes sync , prgset , prgadd , prginspg , pswset , pswclr , rfi , ldb , ldh , ldw , stb , sth and stw .

The

Destination registers in a bundle have to be unique, with the exception of R0.

ldb , sbrk ldh prgins operation must have the stop bit set.

and

and mul operations must not have R63 as a destination register.

syscall must be alone in a bundle.

Speculative load considerations

Speculative (or dismissible) loads execute as normal loads except in the following cases.

● The address is in a region where a speculative load may be destructive. In this case, the SCU (see

Section 6.6: Speculative control unit (SCU) on page 46 ) should be set up

to prevent speculation to this region. In this case, a zero is always returned and no access is made to the memory.

●

A normal load would cause an exception. Generally, in this case, the load is considered to have been incorrectly speculated and the data is not utilized in the correct execution of the program. Zero is returned by default.

If a dismissible load causes a bus error then a bus error exception is always thrown.

The TLB and/or SCU should always be set up to prevent dismissible loads from causing bus errors. See

Chapter 6: Memory translation and protection on page 31

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Traps (exceptions and interrupts) ST231

Application or system software may require misalignment support, with misaligned accesses being correctly interpreted by the exception handler. To improve speculative load support for misaligned addresses, a control value PSW[SPECLOAD_MALIGNTRAP_EN] can be set which causes speculative loads to trap on misaligned addresses rather than returning zero, see

Section 3.4: Program status word (PSW) on page 19

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ST231

6

Memory translation and protection

Memory translation and protection

The ST231 provides full memory translation and protection by means of a translation lookaside buffer (TLB).

The TLB enables the ST231 to run memory-managing operating systems (such as Linux). It also provides a level of backward compatibility for the instruction protection unit (IPU) and data protection unit (DPU) functions when running a non-memory managed OS (for example, OS21).

The ST231 memory management system allows multiple virtual address spaces. Each virtual address space has associated with it an address space identifier (ASID).

The ST231 memory management system allows memory pages to be marked with three

different policies: cached, uncached and write combining uncached, as defined in Table 9

The ST231 has a small instruction TLB (ITLB), a small data TLB (DTLB) and a larger unified

TLB (UTLB).

The ITLB performs instruction address translations and acts as a cache for address translations stored in the UTLB. When the ITLB misses it automatically updates from the

UTLB.

The DTLB performs data address translations and acts as a cache for address translations stored in the UTLB. When the DTLB misses it automatically updates from the UTLB.

When the UTLB is changed, the ITLB and DTLB are not updated. The ITLB and DTLB can be flushed under software control by means of the TLB_CONTROL register, see

Section 6.4.8: TLB_CONTROL on page 40 .

The ITLB and DTLB act as small caches that keep copies of the currently active translations. Only translations that are shared or match the current ASID are loaded into the

ITLB and DTLB.

Table 4 provides details of the TLB configuration of the ST231.

Table 4.

Item

DTLB

ITLB

UTLB

TLB information

Size

8 entries

4 entries

64 entries

Comment

Fully associative buffer with LRU replacement .

Fully associative buffer with LRU replacement.

Fully associative buffer which is managed by the software.

The UTLB size can be determined either by reading the core version register (using a lookup table) or reading the TLB_REPLACE register after reset.

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Memory translation and protection ST231

This section deals with physical and virtual addresses.

The ST231 TLB supports 32-bit addresses providing up to 4 Gbyte of physical address space. The layout of the TLB registers allows future variants to support up to 45 bits of physical address space.

Virtual addresses are 32-bits. The TLB performs the mapping from virtual to physical addresses using one of the following page sizes: 8 Kbyte, 4 Mbyte and 256 Mbyte.

Control registers are accessed by virtual addresses only; virtual addresses corresponding to control registers are not translated. The (virtual) addresses of the control registers are valid physical addresses; any access to these physical addresses will be made to the memory subsystem in the usual way. If the TLB is disabled then the untranslated address will access control registers.

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ST231 Memory translation and protection

6.3 Caches

The caches are virtually indexed and physically tagged. The cache tag RAM lookup occurs in parallel with the TLB lookup.

6.3.1 Instruction cache organization

Instruction cache addressing is illustrated in Figure 2

The instruction cache is 32 Kbytes direct mapped and built from 512 x 64 byte lines.

The virtual address bits [14:06] are used to index the instruction cache RAMs.

Virtual address bits [31:13] are sent to the ITLB for translation. The translated physical address bits [31:13] from the ITLB is then compared against the instruction cache tag.

Virtual address bits [05:00] are used to select the correct bytes from the cache line.

Figure 2.

Instruction cache addressing

Instruction cache accesses

Virtual address

15 14 13 12

Virtual page address Byte offset in page

Cache row index

6 5

Byte in line

ITLB Cache tag ram

Cache data ram

Physical address

15 14 13 12

Physical page address

6 5

Byte offset in page

31 15 14 13

Cache tag

Cache tag compare

Data out

Cache hit out

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Memory translation and protection

6.3.2

ST231

Data cache organization

Instruction cache addressing is illustrated in Figure 3

The data cache is 32 Kbytes four way set associate and built from 4 x 256 x 32 byte lines.

The virtual address bits [12:05] are used to index the data cache RAMs.

Virtual address bits [31:13] are sent to the DTLB for translation. The translated physical address bits [31:13] from the DTLB are then compared against the data cache tag.

Virtual address bits [04:00] are used to select the correct bytes from the cache line.

Figure 3.

Data cache addressing

Data cache accesses

Virtual address

15 14 13 12

Virtual page address Byte offset in page

Cache row index

5 4

Byte in line

DTLB

Physical address

31 15 14 13

Physical page address

Cache tag rams

Cache data rams

Byte offset in page

4 x

Cache tag compare

Way select

15 14 13

Data Mux

Cache hit out Data out

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ST231 Memory translation and protection

A full list of control registers is provided in

Chapter 9: Control registers on page 67

6.4.1 PSW

The TLB can be enabled and disabled by a bit in the PSW, see

Chapter 3: Architectural state on page 19 .

●

While address translation is disabled (TLB_ENABLE = 0): virtual addresses are not translated and are used directly as the physical address all data accesses are made uncached no TLB exceptions are thrown

6.4.2 TLB_INDEX

Table 5 shows the mapping for the TLB_INDEX register.

Table 5.

Name

TLB_INDEX bit fields

Bit(s) Writable Reset Comment

ENTRY [7:0] RW 0x0

Determines which of the 64 TLB entries is mapped to the TLB_ENTRYx registers. Writing a value to this register that is greater than the maximum UTLB entry available has no effect (the entry is not updated).

0x0 Reserved.

RESERVED [31:8] RO

When the TLB_INDEX register is written, subsequent read/writes to the TLB_ENTRYX registers are to the indicated UTLB entry.

6.4.3 TLB_ENTRY0

This register maps bits [31:00] of the TLB entry. The entry is chosen by writing to the

TLB_INDEX register.

Table 6 lists the fields of the TLB_ENTRY0 register; the fields are

described in subsequent tables.

Table 6.

Name

ASID

SHARED

TLB_ENTRY0 bit fields

Bit(s) Writable Reset Comment

PROT_SUPER

PROT_USER

[7:0]

[11:9]

[14:12]

0x0

Indicates which address space this page belongs to.

0x0 Page shared by multiple address spaces (ASIDs).

0x0

A three bit field that defines the protection of this region in supervisor mode.

A three bit field that defines the protection of this region in user mode.

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Memory translation and protection ST231

Table 6.

Name

DIRTY

POLICY

SIZE

PARTITION

RESERVED

TLB_ENTRY0 bit fields (continued)

Bit(s) Writable Reset Comment

[19:16]

[22:20]

[24:23]

[31:25]

0x0

Page is dirty. When this bit is 0 write accesses to this page (when write permission is allowed) cause a TLB_WRITE_TO_CLEAN exception. When this bit is 1 writes to this page (when write permission is allowed) are permitted.

0x0 Cache policy for this page.

0x0 Size of this page (also used to disable the page).

0x0 Data cache partition indicator.

0x0 Reserved.

Writing zero to this register disables the page.

Table 7 lists the possible values of the POLICY field.

Table 7.

Name

UNCACHED

CACHED

WCUNCACHED

Reserved

TLB_ENTRY0_POLICY values

Value Comment

Uncached mode. Reads and write that miss the cache are uncached.

Cached mode. Reads that miss the cache cause the cache to be filled. Writes that hit the cache are written into the cache. Writes that miss the cache are sent to the write buffer.

Write combining uncached. Writes that miss the cache are sent to the write buffer. Reads that miss the cache are uncached.

Reserved (on the ST230 reserved cache policies default to uncached).

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ST231 Memory translation and protection

Table 8 lists of the possible values of the SIZE field.

Table 8.

Name

DISABLED

4MB

256MB

Reserved

TLB_ENTRY0_SIZE values

Value Comment

Page is disabled.

8 KByte page.

4 MByte page.

256 MByte page.

Reserved (on the ST230 reserved page sizes disable the page).

Table 9 lists of the possible values of the PARTITION field:

Table 9.

Name

REPLACE

WAY1

WAY2

WAY3

TLB_ENTRY0_PARTITION values

Value Comment

Place in the way specified by the replacement counter and increment the counter.

Place in the way 1 only.

Place in the way 2 only.

Place in the way 3 only.

Table 10

lists of the possible values of the PROT_USER and PROT_SUPER fields:

Table 10.

TLB_PROT values

Name Value Comment

EXECUTE

READ

WRITE

Execute permission.

Read (prefetch and purge) permission.

Write permission.

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Memory translation and protection ST231

6.4.4 TLB_ENTRY1

This register allows access to bits [63:32] of the TLB entry. The entry is chosen by writing to

the TLB_INDEX register. The fields in this register are listed in Table 11.

Table 11.

TLB_ENTRY1 bit fields

Name Bit(s) Writable Reset Comment

VADDR

RESERVED

[18:0]

[31:19]

0x0

The upper 19 bits of the virtual address. For

4Mbyte pages only the upper 10 bits of this field are significant. For 256 Mbyte pages only the upper 4 bits of this field are significant.

0x0 Reserved.

6.4.5 TLB_ENTRY2

This register allows access to bits [95:64] of the TLB entry. The entry is chosen by writing to

the TLB_INDEX register. The fields in this register are listed in Table 12.

Table 12.

TLB_ENTRY2 bit fields

Name Bit(s) Writable Reset Comment

PADDR

Reserved

[18:0]

[31:19]

0x0

The upper 19 bits of the physical address. For

4 Mbyte pages only the upper 10 bits of this field are significant. For 256 Mbyte pages only the upper

4 bits of this field are significant.

0x0 Reserved.

6.4.6 TLB_ENTRY3

This register maps bits [127:96] of the TLB entry. The entry is chosen by writing to the

TLB_INDEX register. The fields in this register are listed in Table 13.

Table 13.

TLB_ENTRY3 bit fields

Name Bit(s) Writable Reset Comment

Reserved [31:0] RO 0x0 Reserved.

6.4.7 TLB_REPLACE

Table 14

shows the mapping of the TLB_REPLACE register.

Table 14.

TLB_REPLACE bit fields

Name Bit(s) Writable Reset Comment

LFSR

LIMIT

Reserved

[15:0]

[23:16]

[31:24]

0xFFFF

Random number used to determine which entry to replace next.

0x40 Number of TLB entries that can be replaced.

0x00 Reserved.

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ST231

Figure 4 shows the structure of the REPLACE register.

Figure 4.

REPLACE register

Memory translation and protection

Load from REPLACE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Note:

LFSR

Software uses the replacement register to randomly decide which TLB entry to replace. The value of the REPLACE field is generated in a pseudo-random manner using a 16-bit linear feedback shift register (LFSR) generating a maximum length sequence (taps on bits 3, 12,

14 and 15).

A read from the TLB_REPLACE register returns the current LFSR and LIMIT values, the

LFSR is then clocked to generate a new value. The current value of the LFSR field can be changed by writing to the TLB_REPLACE register.

The LIMIT field is reset to the number of entries in the TLB

(a)

. The LIMIT field can be changed by writing the TLB_REPLACE register. To reserve a number of entries for a fixed mapping, software sets the LIMIT field to less than the number of entries available to the

TLB.

The LIMIT field is not used by the hardware but is included to allow the software to quickly determine the next TLB entry to replace. A suggested replacement algorithm is as follows: unsigned replace, lfsr, limit, index;

// Read replace register to get LIMIT and LFSR replace = VOLUINT(LXTLB_REPLACE);

// Extract fields lfsr = LXTLB_REPLACE_LFSR(replace); limit = LXTLB_REPLACE_LIMIT(replace);

// Decide which entry to replace index = (lfsr * limit) >> 16;

// Select the correct entry

VOLUINT(LXTLB_INDEX) = index;

The mullhu instruction can be used to extract the LFSR and LIMIT fields from the

TLB_REPLACE register and perform the multiply. The result is then shifted right by 16 bits to obtain the entry number to replace.

This depends on which core is implemented.

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Memory translation and protection ST231

6.4.8 TLB_CONTROL

Table 15

shows the mapping of the TLB_CONTROL register.

Table 15.

TLB_CONTROL bit fields

Name Bit(s) Writable Reset Comment

ITLB_FLUSH

DTLB_FLUSH

Reserved

[31:2]

0x0

Writing a 1 to this bit flushes the entire ITLB.

Writing 0 to this bit has no effect. This bit always reads as zero.

Writing a 1 to this bit flushes the entire DTLB.

Writing 0 to this bit has no effect. This bit always reads as zero.

0x0 Reserved.

Before the ITLB or DTLB are flushed, the hardware ensures that all outstanding writes to the

UTLB have completed.

6.4.9 TLB_ASID

Table 16

shows the mapping of the TLB_ASID register.

Table 16.

TLB_ASID bit fields

Name Bit(s) Writable Reset Comment

ASID

Reserved

[7:0]

[31:8]

0x0

Address space identifier. Writes to this register also cause the ITLB and DTLB to be flushed.

0x0 Reserved.

Coherency

●

After making the following changes the software must ensure coherency by: changing the current ASID updating the UTLB

Changing the ASID

Changing the current ASID requires that all instructions that may be affected by the change are flushed from the execution pipeline and the instruction buffer. This should be achieved by: syncins;;

If it can be guaranteed that no instructions are affected by the change in ASID value for 8 bundles after the change then this may be omitted.

Updating the UTLB

Updating the UTLB requires 6 cycles for the change to take effect. Updating the UTLB does not automatically update the ITLB or DTLB.

If the meaning of a virtual address is changed (including mapping to a different physical address or changing other properties), instructions in the pipeline or instruction buffer using old translations could be incoherent. In this case the ITLB or DTLB must be flushed to ensure coherency. The execution pipeline and instruction buffer must also be flushed.

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Clearing the instruction buffer and the execution pipeline can be achieved with syncins .

If updating the UTLB in an exception handler, returning from the handler with an rfi clears the instruction buffer so syncins is not also necessary.

The recommended sequences for ensuring coherency are shown in

Table 17

. $r1 contains the value 1-3 depending on which of the ITLB and/or DTLB require flushing, see

Section 6.4.8: TLB_CONTROL on page 40 .

Table 17.

Ensuring coherency after UTLB updates

Properties of VA changed Properties of VA not changed

Normal stw TLB_CONTROL[$r0] = $r1;; nop;; syncins;;

Within exception handler stw TLB_CONTROL[$r0] = $r1;; rfi;; nop;; nop;; syncins;; nop;; rfi;;

The normal sequence allowing the properties of the virtual address to change may be used to ensure coherency in any case.

6.4.10 TLB_EXCAUSE

When the ST231 raises a TLB exception, the TLB_EXCAUSE register is updated. The

possible exceptions are listed in Table 18

Table 18.

TLB_EXCAUSE_CAUSE values

Name Value Comment

NO_MAPPING

PROT_VIOLATION

WRITE_TO_CLEAN

MULTI_MAPPING

No mapping was found. (The UTLB had no mapping for the virtual address. The given page is not in the

UTLB and the DTLB (for data accesses) or the ITLB

(for instruction accesses)

An attempt has been made to violate the permissions of a page. The given page may be in the ITLB, DTLB, UTLB or any combination of the above.

A write to a clean page has occurred. This allows the software managing the UTLB to update the master copy of the table kept in memory and to handle any shared pages.

There were multiple hits in the UTLB. The software managing the TLB should ensure that this does not happen.

When a PROT_VIOLATION or WRITE_TO_CLEAN exception is thrown for data accesses the given page may be in the ITLB, DTLB, UTLB or any combination of the above.

It is possible for a page to be held in the ITLB or DTLB but not in the UTLB if the software chose not to purge the ITLB/DTLB when a page was replaced.

When a MULTI_MAPPING exception is thrown, the virtual address maps to more than one page in the UTLB. In this case the IN_UTLB and INDEX fields of the TLB_EXCAUSE and

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Memory translation and protection ST231 the EXADDRESS registers contain the virtual address of the syllable or data which triggered the exception.

When a TLB exception is taken, the software can determine if the given page is in the UTLB by checking the IN_UTLB bit.

Table 19

describes the bit fields within the TLB_EXCAUSE register.

Table 19.

TLB_EXCAUSE bit fields

Name Bit(s) Writable Reset Comment

INDEX

Reserved

CAUSE

SPEC

WRITE

IN_UTLB

Reserved

[7:0]

[15:8]

[17:16]

[32:21]

0x0

TLB index of excepting page.

Reserved

Cause of current TLB exception.

When 1 indicates that this exception was caused by either a purge address or speculative load instruction.

When 1 indicates that this exception was caused by an attempted write to a page

(store). When 0 indicates that this exception was caused by an attempted read or purge of a page.

When 1 the exception address is in the UTLB and the INDEX field is valid. When 0 the exception address was not in the UTLB and the INDEX field is invalid.

Reserved.

The TLB functionality is controlled completely by accessing the provided control registers.

6.5.1 Reset

After reset, the contents of the UTLB are undefined. Before the TLB is enabled all entries must be programmed (or cleared) to prevent undefined behavior.

The DTLB, ITLB and TLB control registers have to arbitrate for access to the UTLB. The priority of UTLB accesses are as follows:

1 (highest)

3 (lowest)

TLB control register access.

DTLB.

ITLB.

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6.5.3 Exceptions

Note:

When the TLB throws an exception it jumps to the exception vector and updates the

TLB_EXCAUSE, EXADDRESS and EXCAUSENO registers.

When a DTLB exception is thrown, the EXADDRESS register contains the virtual effective address that caused the exception.

When an ITLB exception is thrown, the EXADDRESS register contains the virtual address of the syllable that caused the exception. In the case of possible multiple ITLB exceptions, the exception with the lowest syllable address is thrown.

The SAVED_PC and SAVED_PSW stack are also updated in the same way as other traps.

As noted above, the TLB_EXCAUSE register indicates the nature of the ITLB or DTLB exception.

Misaligned loads and control register violations are not considered TLB exceptions.

Details of the EXCAUSENO register can be found in

Section 5.6: Exception types and priorities on page 28

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Memory translation and protection ST231

Instruction accesses are always cached (the cache policy is ignored). The procedures for

accessing instructions are summarized in Figure 5

Figure 5.

Instruction access

Instruction access to virtual address (VA)

No PSW[TLB_ENABLE]?

Physical Address (PA) =

Virtual Address (VA)

Yes

ITLB hit?

UTLB hit?

PA = Translated VA

Protection violation?

Multiple hits?

Yes

TLB_EXCAUSE NO_MAPPING

THROW ITLB_EXCEPTION

TLB_EXCAUSE MULTI_MAPPING

THROW ITLB_EXCEPTION

TLB_EXCAUSE PROT_VIOLATION

THROW ITLB_EXCEPTION

Cached memory access to

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The procedures for reading and writing data are summarized in Figure 6

Figure 6.

Data access

Data access to virtual address (VA)

VA in control register space

Control register access and permissions

All other VAs

PSW[TLB_ENABLE]?

Yes

Physical Address (PA) =

Virtual Address (VA)

Yes

DTLB hit?

UTLB hit?

Yes No

No Multiple hits?

Yes

TLB_EXCAUSE NO_MAPPING

THROW DTLB_EXCEPTION

Access type

Protection violation?

Yes

TLB_EXCAUSE MULTI_MAPPING

THROW DTLB_EXCEPTION

Write

TLB_EXCAUSE PROT_VIOLATION

THROW DTLB_EXCEPTION

Read

Page clean?

Yes

TLB_EXCAUSE WRITE_TO_CLEAN

THROW DTLB_EXCEPTION

PA = Translated VA

Uncached memory access to PA

No Cached

Yes

Cached memory access to

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Memory translation and protection

6.6 Speculative control unit (SCU)

Figure 7.

ST231 instruction and data cache fetch

Instruction and data cache fetch

Cache miss address Speculative load/prefetch bit

ST231

Speculative abort

CMC

Speculative abort

SCU

Speculative control unit

The SCU filters physical speculative load addresses (both cached and uncached) and prefetches that miss the cache to ensure that speculative bus requests are not sent out to peripherals and unmapped memory regions.

The SCU supports four regions of memory aligned to the smallest TLB page size

(8 Kbyte). If the physical address of the speculative load/prefetch address falls within one of the four supported regions, the bus access is allowed, otherwise the SCU aborts the speculative load/prefetch and zero is returned or the prefetch is cancelled.

The regions are configured using the SCU_BASEx and SCU_LIMITx control registers. A region may be disabled by setting the base to be larger than the limit.

The SCU resets so each of the four regions cover the whole of memory. This allows speculative loads to be issued before the SCU has been initialized.

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6.6.1 SCU_BASEx

The SCU base register defines the physical start address of the region where speculative loads/prefetches are permitted. This region is aligned to the smallest page size (by virtue of the read only zero bits). The base address is inclusive, so setting BASE == LIMIT defines an

8 Kbyte region.The fields of the SCU base register are listed in

Table 20

Table 20.

SCU_BASE0 bit fields

Name Bit(s) Writable

BASE

RESERVED

[18:0]

[31:19]

Reset Comment

0x0

Upper 19 bits of the base of this region.

Reserved.

6.6.2 SCU_LIMITx

The SCU limit register defines the physical end address of the region where speculative loads are permitted. This region is aligned to the smallest page size (by virtue of the read only zero bits). The limit address is inclusive, so setting BASE == LIMIT defines an 8 Kbyte

region. The fields of the SCU limit register are listed in Table 21 .

Table 21.

SCU_LIMIT0 bit fields

Name Bit(s) Writable

LIMIT

RESERVED

[18:0]

[31:19]

Reset Comment

0x7FFFF Upper 19 bits of the limit of this region.

0x0 Reserved.

Any changes to SCU registers take effect for future bus transactions. To ensure that all

STBus transactions prior to an SCU change are made with the old settings, and all STBus transactions subsequent to an SCU change are made with the new settings, the program must execute a sync instruction before updating the SCU registers.

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Memory subsystem ST231

●

This chapter describes the operation of the ST231 processor memory subsystem. The memory subsystem includes the following components: caches protection units write buffer prefetch cache translation lookaside buffer (TLB) the core memory controller (CMC)

The memory subsystem is split broadly into two parts: the instruction side (I-side) and the data side (D-side). The CMC interfaces these two parts to the STBus port. The I-side, containing the instruction cache, supports the fetching of instructions. The D-side, containing the data cache, prefetch cache and write buffer, support the storing and loading of data.

The TLB performs memory address translation and protection. The function of the TLB is

detailed in Chapter 6: Memory translation and protection on page 31 .

The ST231 ensures that data accesses are coherent with other data accesses. There is no

guarantee of coherency between instruction and data accesses (see Section 7.5.2:

Coherency between I-side and D-side on page 59 ) or between the core and external

memory. To ensure coherency data must be purged from the core as described later in this chapter.

The function of the streaming data interface (SDI) is described in Chapter 8: Streaming data interface on page 61

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This section describes the memory subsystem shown in Figure 8

Figure 8.

Memory subsystem block diagram

Load

Store

Unit

(LSU)

Read/write/ flush/sync/prefetch request

Read word

Data cache

Uncached read/writes

& cache fill

Instruction cache

Read

4x32 bit

Instruction buffer

PC and branch unit

Busy

Writes &

(reads/prefetch/sync/flush)

Fetched data

Prefetches &

(reads/writes/flush)

Write buffer

Busy

Prefetch cache D-side memory subsystem

Read request

Read response cache line

Write data

Prefetch request

Prefetch data

CMC

STBUS

I-side memory subsystem

7.2 I-side memory subsystem

Within the ST231, the instruction buffer is responsible for issuing instructions to the processor core. The instruction cache uses the CMC to fetch cache lines from memory, and sends groups of up to four operations to the instruction buffer.

The instruction buffer attempts to fetch ahead in the instruction stream in order to keep its buffer full. When a branch is taken the instruction buffer is invalidated and a fetch started from the target address.

After a branch, the instruction buffer takes one cycle to fetch the next bundle from the cache, this means the ST231 stalls for one cycle. If the branch is to a bundle that spans two cache lines, then it takes two cycles to fetch the bundle and thus the ST231 stalls for two cycles.

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Note:

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Instructions are always cached; there is no support for uncached instruction fetching. Self modifying code (loaders for example) must invalidate the cache explicitly.

The instruction cache is a 32 Kbyte direct mapped cache. The cache is made up from 512 sets. Each set contains one 64-byte line.

When a virtual (byte) address is submitted to the cache the address bits are used as follows:

●

Bits [05:02] select the word offset within the line

Bits [14:06] select the set that could contain the required cache line

Bits [31:13] are translated by the TLB. The resulting physical tag is used to check if the required line is in the cache

The instruction cache receives fetch requests from the instruction buffer and returns a group of up to four 32-bit operations (16 bytes).

When syllables are requested from the cache it uses the address to determine whether they are already present in the cache. If the syllables are not in the cache, they are fetched from memory and stored into the cache, during which time the processor stalls. The requested instruction bundle is then returned to the instruction buffer.

Invalidating the entire instruction cache

To invalidate the instruction cache safely, the core must execute the following two operations.

● The first is prgins , which invalidates the whole instruction cache and causes any subsequent instruction fetches to be made from memory rather than from the cache.

● The second is syncins , which ensures that the next bundle is fetched with an invalidated cache, and therefore from memory; if this operation is not performed the subsequent bundle might have been prefetched into the instruction buffer and might not correspond to the instruction in memory. The syncins operation is a pseudo operation implemented as a pswset .

Both prgins and syncins are privileged operations (which means that they can only be executed in supervisor mode).

Invalidating the instruction cache by page

The instruction cache can also be invalidated in 8 Kbyte pages by means of the prginspg instruction.

The prginspg operation takes a base and an immediate offset. The base is added to the offset to produce the effective address (as for other load/store instructions). The effective address is then used by the instruction cache to perform the purge.

The effective address is split into two parts. Bits [31:13] specify the upper bits of the 8 Kbyte physical address of the page to be purged. In addition, bits [12:0] are used to specify any ambiguous address bits of the virtual cache address that may contain entries for the physical page. This ambiguity occurs when the instruction cache set(s) are larger than the purgeable page size.

The single way cache is 32 Kbyte and the purgable page size only 8 Kbyte. As a result, two bits of virtual address need to be specified to indicate the quadrant of the indexed cache in which physical page entries are scanned for. The bottom two bits of the effective address

(bits [14:13] of the virtual address) are used to specify the quadrant.

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ST231

Note:

7.2.3

Memory subsystem

We recommend that the software system should provide all 13 bits of a potentially ambiguous virtual address to ensure future compatibility.

To purge a physical page which has more than one virtual mapping, multiple purge pages need to be executed (except in the case where all the ambiguous address bits are the same).

prginspg is a privileged operation (which means that it can only be executed in supervisor mode).

I-side bus error

If the I-side memory subsystem causes a bus error, an STBUS_IC_ERROR exception is thrown. I-side bus errors are synchronous events which are thrown when trying to execute the bundle which causes the bus error.

A bus error invalidates the cache line.

7.3 D-side memory subsystem

All data accesses take place through the D-side memory subsystem which contains the data cache, the prefetch cache and the write buffer.

The data cache is 32 Kbyte 4-way associative with a 32-byte line. The cache is therefore made up of 256 sets. Each set contains 4 cache lines, one per way. It is operated with a fixed write-back, no allocate on write-miss policy.

●

When a virtual (byte) address is submitted to the cache its bits are used as follows.

Bits [4:0] select the byte offset within the cache line.

Bits [12:5] select the set (0-255) that could contain the required cache line.

Bits [31:13] are translated by the TLB. The resultant physical address form the tag that is used to check if the required line is in the cache.

At most one of the write buffer, the data cache or the prefetch cache can contain a copy of the data for a particular address.

The load/store unit (LSU) performs all data access operations. The cacheability is dependent on the address of the access and is determined by the TLB ,

see Chapter 6:

Memory translation and protection on page 31

. In addition to load and store there are operations which prefetch data, flush and synchronize the D-side memory subsystem.

The data cache sends write misses and dirty data to the write buffer, see Write buffer on page 58

The write buffer combines write transactions and sends them out to memory.

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Memory subsystem

7.3.2

ST231

Data cache partitioning

Data cache partitioning allows, in addition to the normal mode, the data cache to be split into a normal and either 1, 2 or 3 locked partitions, as three separate modes.

These modes allow the cache to be partitioned as:

●

32 Kbyte 4-way cache

24 Kbyte 3-way cache plus 8 Kbyte data RAM*

16 Kbyte 2-way cache plus 16 Kbyte data RAM*

8 Kbyte direct mapped cache plus 24 Kbyte data RAM*

Where * indicates special cases of the following:

●

24 Kbyte 3-way cache plus separate 8 Kbyte direct mapped cache

16 Kbyte 2-way cache plus 2 separate 8 Kbyte direct mapped caches

4 separate 8 Kbyte direct mapped caches

Control of partitioning is performed via two mechanisms. Firstly the machine state register

(see Section 9.4: Data cache replacement state register on page 71

) defines the number of data cache ways which are reserved (locked). Secondly a bit field in each TLB entry (see

Chapter 6: Memory translation and protection on page 31

) is used to indicate which of the sets misses are placed in (either the locked section or the rest of the cache).

7.3.4

Speculative loads are defined as returning the same data as normal loads except that when a normal load would cause an exception, speculative load returns 0.

Speculative loads are handled in the following way:

●

● speculative loads that would cause a PROT_VIOLATION exception return 0 if a speculative load misses the DTLB and maps to more than one entry in the UTLB, it causes a MULTI_MAPPING exception

●

● speculative loads that miss the UTLB cause a TLB_NO_MAPPING exception, if the

DYNAMIC bit is set in the PSW (if this bit is clear then speculative loads that miss the

UTLB return 0 without causing an exception) speculative loads that miss the cache are validated by the SCU, see

Section 6.6:

Speculative control unit (SCU) on page 46

, if the speculative load does not fall into one of the valid regions in the SCU then it returns 0

Cached loads and stores

Cached loads and stores are performed through the data cache. The memory subsystem can optimize these operations for performance. For example, the memory subsystem can transfer more data than specified by the load (that is, a loading cache line), aggregate accesses (combining writes in write buffer) and, or re-order accesses (cache causes word accesses to be re-ordered).

The memory subsystem presents a consistent view of cached memory to the ST231 programmer, that is, a store followed by a load to the same address always returns the stored data. To guarantee ordering of accesses to external memory in cached regions, purge and sync operations must be used.

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7.3.5

Memory subsystem

Uncached load and stores

Uncached loads and stores are issued to the STBus in program order. Data accessed through an uncached TLB entry or when the TLB is disabled is never brought into the data cache or the prefetch cache. See

Section 7.5.4: Cached data in uncached region on page 59

The precise amount of data specified in the access is transferred and the access is not aggregated with any other. The implementation does not optimize these accesses.

To guarantee that an uncached store has reached its STBus target, either a sync or an uncached load to the same bus target must be issued.

An STbus request arising from a cached (or a write-combining uncached) operation, and an

STbus request arising from an uncached operation, are not guaranteed to be issued to the

STbus in program order unless the operations target the same physical address. To guarantee ordering, a sync instruction should be inserted between the operations.

The prefetch cache prefetches and stores data from external memory and sends it to the data cache when (and if) it is required.

A pft operation is a hint to the memory subsystem that the given item of data may be accessed in the future. The operation specifies a virtual address which can be prefetched by the prefetch cache. A pft operation may be ignored.

●

Prefetches are ignored (treated as nops ) in the following cases: a prefetch that hits the cache a prefetch that does not map to a valid page in the TLB a prefetch to an uncached (or write combining uncached) page a prefetch to control register space a prefetch to a region that does not have read permission a prefetch that misses the cache but does not fall into one of the valid regions in the

SCU, see

Section 6.6: Speculative control unit (SCU) on page 46

● a prefetch that is issued when 8 other prefetches are outstanding (see below)

For this reason the only exception a prefetch can cause is a DTLB MULTI_MAPPING fault.

The prefetch cache contains eight entries. Each entry contains an entry valid bit, a prefetch address, a data valid bit and 32 bytes of data.

When a pft request is made and accepted, it enters the prefetch cache as an outstanding prefetch request, with the data valid bit clear. Older entries may be discarded if the prefetch cache is full. The prefetch cache attempts to access the memory system to fetch the line containing the prefetch address. When a fetch completes the data valid bit is set. The prefetch cache supports multiple outstanding memory requests.

Entries in the prefetch cache are tested when a data cache read miss occurs. If an entry match occurs and the data valid bit is set, the prefetched line is loaded into the data cache as if it were fetched from external memory. If the data valid bit is clear, the data cache stalls until the data is returned from external memory. The entry in the prefetch cache is then marked as empty and can be reused.

Entries in the prefetch cache are tested when a data cache write miss occurs. If an entry match occurs the prefetch cache entry is invalidated.

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Memory subsystem ST231

Note:

The purge (flush and invalidate) operations are used to ensure a copy of a particular data item is not cached in the D-side of the memory subsystem.

These operations flush out the specified data. Dirty lines are written to the write buffer and the line is invalidated. Purge addresses are treated as byte aligned.

Purging data by address

The prgadd operation purges the specified virtual address from the data cache.

If the DYNAMIC bit in the PSW is set, and the address is not present in the UTLB, a DTLB

NO_MAPPING exception is thrown.

If the DYNAMIC bit in the PSW is not set, and the address is not present in the UTLB, the purge is ignored.

If the address to be purged misses the DTLB, and it maps to more than one UTLB entry, it causes a DTLB MULTI_MAPPING exception.

If the address to be purged does not have read permission (protection fault), the prgadd is ignored and no exception is thrown.

Purging data by set

The prgset operation purges each of the four lines in the data cache set, indicated by the address operand, without checking for a cache hit. It also invalidates the entire prefetch cache.

prgset operates on a subset of the address bits. As such it can be used to purge both virtual and physical addresses.

The prgset operation also resets the replacement pointer in the set to way 0. This is not visible unless using data cache partitioning.

7.3.9

●

This is achieved by executing the sync operation. Once the bundle containing the sync operation has completed, the following conditions hold.

All previous load s, store s and pft s have completed.

No future memory operations have started.

The write buffer is empty, all pending writes to external memory have completed.

D-side bus errors

If the D-side memory subsystem causes a bus error, a STBUS_DC_ERROR exception is thrown. Bus errors are asynchronous events and are not associated with a particular operation.

In the case of writes the data has already been discarded and therefore the write is lost. The write may or may not have completed.

In the case of reads the cache line which has been allocated for the data is invalidated.

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7.3.10 Operations

Table 22

lists the operations supported by the data side memory subsystem.

Table 22.

Memory operations

Type Word aligned

Load

Store

Prefetch

Purge

Load word

Load dismissible Load word

Store word

Half word aligned

Load half unsigned

Store half

Load half signed

Load byte unsigned

Store byte

Prefetch

Purge address

Purge set

Sync

Byte aligned

Load byte signed

Sync

It is a requirement that half word load/stores are half word aligned (2 bytes) and word load/stores are word aligned (4 bytes). Misaligned accesses cause a MISALIGNED_TRAP exception.

Note:

Table 23

details the effect of each of the above memory operations on the ST231’s memory subsystem.

When a cache line is purged to the write buffer it is also invalidated in the cache.

Table 23.

Cache policy

Instruction Policy Cache

Write buffer

Prefetch SCU Result

Miss

Loads: ldb, ldh, ldw

Uncached

Hit clean

Hit dirty

Miss

Hit

Miss

Hit

Load uncached

Discard prefetch entry, Load uncached

Flush write-buffer entry, Load uncached

Invalidate cache line, Load uncached

Purge cache line to write buffer, flush write buffer, Load data uncached

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Memory subsystem ST231

Table 23.

Cache policy (continued)

Instruction Policy Cache

Write buffer

Prefetch SCU Result

Dismissable loads

Uncached ldb.d, ldh.d, ldw.d

Miss

Hit clean

Hit dirty

Miss

Stores : stb, sth, stw

Uncached

Hit clean

Hit dirty

Miss

Hit

Miss

Hit

Miss

Hit

Miss

Hit

Hit Load uncached

Miss Return 0

Hit

Discard prefetch entry, Load uncached

Miss Discard prefetch entry, return 0

Hit

Flush write-buffer entry, Load uncached

Miss

Hit

Flush write-buffer entry, return

Invalidate cache line, Load uncached

Miss Invalidate cache line, return 0

Hit

Purge cache line to write buffer, flush write buffer, Load data uncached

Miss

Purge cache line to write buffer, flush write buffer, return 0

Store uncached

Discard prefetch entry, Store uncached.

Flush write buffer entry, Store uncached.

Invalidate cache line, Store data uncached

Purge cache line to write buffer, flush line from write buffer,

Store data uncached

Loads: ldb, ldh, ldw, ldb.d, ldh.d, ldw.d

Uncached write combine

Same as uncached.

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Table 23.

Cache policy (continued)

Instruction Policy Cache

Write buffer

Prefetch SCU Result

Miss

Stores: stb, sth, stw

Uncached write combining

Hit clean

Loads: ldb, ldh, ldw,

Cached

Hit dirty

Miss

Hit

Miss

Hit

Miss

Hit

Miss

Hit

Store to write buffer

Discard prefetch entry, Store to write buffer

Store to write buffer

Invalidate cache line, Store to write buffer

Purge cache line to write buffer, flush line from write buffer,

Store data to write buffer

Fill cache line from RAM,

Load data from cache

Transfer data from prefetch cache to data cache, Load data from data cache.

Flush write buffer line, Fill cache line, Load data from cache

Hit clean

Hit dirty

Dimissable

Loads: ldb.d, ldh.d, ldw.d

Stores: stb, sth, stw

Cached

Miss

Hit clean

Hit dirty

Miss

Hit clean

Hit dirty

Miss

Hit

Miss

Hit

Miss

Hit

Miss

Hit

Load data from cache

Hit

Miss

Load data from cache

Fill cache line from ram, Load data from cache

Miss Return 0

Transfer data from prefetch cache to data cache, Load data from data cache.

Flush write buffer line, fill cache line, Load data from cache

Flush write buffer line, Return

Load data from cache

Store data to write buffer

Invalidate prefetch cache line,

Store data to write buffer

Store data to cache & dirty cache line

Store data to cache

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Memory subsystem ST231

Table 23.

Cache policy (continued)

Instruction Policy Cache

Write buffer

Prefetch SCU Result prgadd All

Miss

Hit

Miss

Hit

No effect

Invalidate prefetch cache line

No effect

Hit clean

Hit dirty prgset sync pft

All

Cached

Miss

Hit

Miss

Hit

Miss

Hit

Miss

Invalidate cache line

Purge cache line to write buffer

Purge cache lines in set (dirty data to write buffer) and invalidate entire prefetch cache.

Flush entire write buffer to memory, wait for all outstanding writes, prefetches and uncached writes to complete.

Prefetch sent to prefetch cache

Prefetch discarded (may use prefetch cache slot until SCU is checked)

Prefetch discarded

Prefetch discarded Uncached

Uncached write combining

Prefetch discarded

7.4

58/331

Stores that miss the data cache and dirty lines that are evicted from the cache are held in the write buffer, pending write back to external memory.

The write buffer is a write combining buffer that holds up to four entries. Each entry has 32 bytes of data, an address and 32 bits of byte masks. The write buffer is operated as an LRU

(least recently used) buffer.

Write combining allows individual close proximity writes to be merged into a single bus write.

Write combining improves performance significantly (for a no write allocate cache) when performing sequences of writes to blocks of data which have not been brought into the cache.

Core memory controller (CMC)

The CMC allows multiple masters to access the STBus though a single port. The CMC arbitrates between multiple requestors and correctly routes responses.

7645929

ST231 Memory subsystem

The memory subsystem requires some additional explanation of some key operations and methods of use. This section is intended to provide this information without filling out the previous sections.

Use a sync operation to enforce the completion and ordering of memory operations.

●

A sync operation ensures that: the write buffer is empty (by flushing it to memory) all outstanding writes have reached external memory (both cached and uncached) all outstanding prefetches have completed

After any purge operations have taken place a sync should be issued to ensure that dirty data that was sent to the write buffer is flushed to memory.

There is no coherency guaranteed between the external memory and the D-side and I-side memory subsystems. If coherency is desired then the memory subsystem has to be purged and synchronized.

This is achieved by the following sequence.

Flush the entire data cache by issuing prgset or prgadd operations.

2. Ensure all data is written back to memory by issuing a sync .

3. Invalidate the instruction cache by issuing prgins or prginspg operations.

4. Flush the instruction buffer by issuing a syncins .

7.5.4

After reset all lines in the instruction cache and data cache are marked as invalid. The write buffer and prefetch cache entries are marked as empty.

Cached data in uncached region

If data from an uncached region is in the cache, then accessing the data as uncached causes it to be purged from the cache. This ensures that uncached accesses are always performed directly on the memory.

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Memory subsystem ST231

The prefetch cache is intended to improve performance. This can be achieved by explicitly fetching data from external memory and hiding the associated latency. The following points must be considered to ensure the prefetch cache works effectively.

● Data must be prefetched well in advance of use. The latency of an external memory access needs to be hidden between the pft operation and the first load operation which uses data from the prefetched line. This latency is in the region of 80-120 cycles for stall free bundles.

● The prefetch cache size should be taken into account, such that the number of outstanding prefetches does not exceed the number of entries in the prefetch cache.

● Unused prefetches increase bandwidth and waste entries in the prefetch cache.

The first two points indicate a window for which prefetches might be considered.

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8

Streaming data interface

Streaming data interface

The ST231 streaming data interface (SDI) is designed to allow fast and easy connection of on-chip peripherals. Each SDI is unidirectional and includes handshakes to prevent data loss and improve data flow.

The ST231 implements four SDI interfaces, two input ports and two output ports.

Figure 9.

SDI overview

Data In

Data Out

SDI

Input

SDI

Input

SDI Output

Control

Registers

SDI Output

Execution unit

The SDIs:

●

● provide a mechanism for attaching streaming hardware to the processor core reduce STBus traffic and associated processor stall cycles reduce cache pollution and control complexity prevent deadlock through a timeout mechanism allow communication between clock domains without complex synchronization hardware

The SDI ports are accessed using control registers in the core.

Data is communicated through either an output port or an input port to the processor. Data is communicated in order, that is, the n th

data item communicated arrives after the (n - 1) th item and before the (n + 1) th

data item.

The SDI blocks writes (stores) to an output port if the SDI is full. Conversely, it blocks reads

(loads) from an input port if the channel is empty. The ST231 blocks execution by stalling the entire processor. No execution proceeds until the channel becomes ready for the requested communication or an interrupt or timeout exception occurs.

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Streaming data interface ST231

Note:

The SDI port data interface is 32-bits wide. External to the SDI port, however, the data width can be arbitrary. For example connecting to a DCT peripheral which consumes 16-bits, data could be sent from the ST231 as single 16-bit items. The ST231 can only write 32-bit data to control registers, so writing a pair of 16 bit values in a packed word would be twice as fast.

In this case the peripheral has to expect pairs of 16-bit values.

In its basic form the SDI acts as a communication channel to and from the processor. It is fully synchronized, allowing idealized input and output to be dealt with directly by the processor using load and store operations directly access the processor registers.

The SDI accesses can be initiated from C program code as accesses to volatile variables.

8.2.1 Timeouts

The timeouts operate as monitors to each individual SDI access. If an access remains stalled for too long, as defined by the control registers, an exception occurs.

8.3 Registers

The SDI interfaces directly to the ST231 load store unit. The interface is through a number of memory mapped registers in the control register address space.

The addresses of these registers are provided in

Chapter 9: Control registers on page 67 .

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8.3.1

Streaming data interface

Input channel memory mapping

SDI

SDI i_ i_

DATA

READY

The SDI i _DATA register is the location from which data is read from the input channel. The processor control and channel logic synchronize to ensure no data is lost. If the SDI i _DATA register is empty the processor stalls. Writing this register has no effect and the processor does not stall.

The SDI i _READY register is implementation specific. If non zero it indicates that the channel has data ready to be read.

This value indicates a minimum number of ready items. Returning the exact amount of data ready to be read from the channel may not be possible for a number of reasons, that is, clock boundary issues, propagation delays, hence the looser condition of the minimum number of ready items. In its simplest form this ready value can be 1, indicating at least one item is ready.

SDI i _CONTROL The SDI i _CONTROL register is used to reset the channel and the

SDI i _TIMEOUT register. The usage of the bits are defined in

Table 24

The definition of the privilege bits is given in

Section 8.3.3: Protection on page 64

SDI i _COUNT The SDI i _TIMEOUT register is reset to this value each time an SDI data value is successfully accessed. The value may be read or written. At reset it is set to a fixed value defined by the particular implementation.

Time-outs can be disabled via the SDI i _CONTROL register.

SDI i _TIMEOUT The number of cycles an SDI data access is allowed to stall before a timeout exception is thrown. The value may be read or written. This register is normally set to the value of SDI i _COUNT. Exceptions to this are when it has been specifically set to another value, or when an SDI access has taken a timeout exception or been interrupted. In the case of an SDI timeout the SDI i _TIMEOUT register contains the value zero.

Table 24.

SDI0_CONTROL bit fields

Name Bit(s) Writable Reset Comment

PRIV [1:0] RW

RESETINPUT

RESETOUTPUT

INPUTNOTOUTPUT

Reserved

MASTERNOTSLAVE

TIMEOUTENABLE

Reserved

[31:8]

0x0 Privilege bits.

0x0

RESETINPUT (read only) acts as

RESETREQUEST when slave,

RESETACK when master.

RESETOUTPUT, acts as

RESETREQUEST when master,

RESETACK when slave.

0x0 INPUTNOTOUTPUT (read only).

0x0 Reserved

0x0 MASTERNOTSLAVE (read only).

0x0

Timeout disable (set to 1 to disable timeout interrupts).

0x0 Reserved

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Streaming data interface ST231

8.3.2 Output channel memory mapping

SDI

SDI i i

_DATA

_READY

The SDI i _DATA register is the location from which data is written to the output channel. The processor control and channel logic synchronize to ensure no data is overwritten. If the SDI i _DATA register is full, the processor stalls. Reading this value has no effect and the processor does not stall and a value of zero is returned.

The SDI i _READY register is implementation specific. If non zero it indicates that the channel has space where data can be written.

This value indicates a minimum number of empty spaces where data can be written. In an implementation where the channel is connected to a FIFO this register could indicate, full, not full, the FIFO is half empty by returning (for example) the values 0, 1, 32. Returning the exact amount of data space available in the channel may not be possible for a number of reasons, that is, clock boundary issues, propagation delays, hence the looser condition of the minimum number of ready items. In the simplest form this ready value can be 1, indicating at least one item can be written.

SDI i _CONTROL

Bits defined as Section 8.3.1: Input channel memory mapping on page 63

SDI i _COUNT Defined as

Section 8.3.1: Input channel memory mapping on page 63

SDI i _TIMEOUT Defined as

Section 8.3.1: Input channel memory mapping on page 63

8.3.3 Protection

The SDI register space is protected from malicious usage via access permissions held in each SDIi_CONTROL register. The reset behavior is that accesses to the SDI registers are only allowed in supervisor mode.

The protection can be loosened to allow user access to an SDIi_DATA and SDIi_READY registers. This is achieved via the SDIi_CONTROL register, PRIV[1:0] two bit field, indicating the access allowed for each SDI.

Table 25

lists the SDI_CONTROL_PRIV values.

Table 25.

SDI_CONTROL_PRIV values

Name Value Comment

PRIV_NOUSER

PRIV_USER

Reserved

Access only allowed in supervisor mode

Allow user access to data and ready register

Reserved (defaults to privilege no user).

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ST231 Streaming data interface

8.4 Interrupts, exceptions and restarts

This section provides information about:

●

● interrupts, including returns from an interrupt and accesses to SDI registers

SDI exceptions restarts or soft resets

8.4.1 Interrupts

The processor can take any interrupt while stalled accessing the SDI. An interrupt would be taken as if it occurred just prior to the bundle accessing the SDI.

Note:

Return from interrupt

The rfi from the exception handler continues program execution at the point prior to the interrupt.

If the SDI is ready by the completion of the interrupt handler, the SDI i _TIMEOUT register is reset to the value in SDI i _COUNT.

If, however, the SDI is still not ready upon completion of the handler, the processor reverts to the stalled state. The processor continues to wait for the channel to become ready while counting down the SDI i _TIMEOUT register from the value held prior to the exception.

Access to SDI registers

The interrupt handler can access all the SDI registers.

Accessing the SDI i _DATA register may alter the state of the processor observed by the interrupted processor.

Note:

8.4.3

In this case the EXCAUSENO register indicates an SDI timeout exception. The exception address points to the SDI register on which the processor was waiting when the exception occurred.

A timeout exception occurs if the processor is actively waiting for a response from the interface for longer than the interface’s timeout period.

The exception handler, in the case of a SDI timeout exception, is able to restart the communicating process. This is achieved by executing an rfi to the instruction that caused the exception. This causes re-execution of the instruction accessing the SDI.

The SDI i _TIMEOUT register must be increased from the zero value that caused the exception, otherwise the exception is triggered again immediately.

The timeout exception is generated by the processor and not the channel.

Restart (soft reset)

A channel can only be restarted by the master of the channel.

A master may be either an input or an output channel. Figure 10

shows how the reset structure is connected.

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Streaming data interface ST231

A reset is initiated by the master by setting the resetrequest bit in the control register. This causes the channel to begin the reset process. Once acknowledged (that is RESETACK =

1) as having been received by the slave, and consequently the entire channel structure being reset, the reset is removed by the software (that is, RESETREQUEST = 0) is communicated to the slave port. Once acknowledged (that is, RESTACK = 0), this indicates that the entire channel has exited the reset state.

When the SDI channel is reset, any data buffered by the core is discarded. This has the effect of making an output channel ready (as the output buffers are empty) or making an input channel not ready (as the input buffer is empty) until more data is received.

During the reset sequence the READY and DATA registers should not be accessed as the results are implementation dependant. The reset sequence does not effect the contents of the TIMEOUT and COUNT registers.

The slave reset can be used to reset a slave subsystem.

Normally the output channel is the master. However in cases where the output channel is connected to a dumb peripheral it may be necessary to make the input channel the master, particularly where this is a processor interface.

The restart structure outlined works across asynchronous clock boundaries. The reset control structure is shown in

Figure 10

Figure 10.

Soft reset control structure

Slave

Data

Transport

Data

Transport

Control

Transport

Control

Transport

ResetReq

ResetAck

Master

66/331 t

ResetReques

ResetAck

Master requests reset: Subsystem resets itself and consumes all data presented at inputs.

RESETREQUEST is forwarded to other slave side subsystems.

All units in reset: After subsystem has reset itself AND all slave side subsystems have sent RESETACK,

RESETACK can be forwarded to master.

Master requests leave reset: Unit forwards removal of RESETREQUEST to all slave-side subsystems. Unit leaves reset and stops consuming data.

All units out of reset: On receipt of RESETACK from all subsystems, RESETACK is forwarded to master.

System can restart.

7645929

ST231 Control registers

The ST231 control registers contain processor state that is not typically accessed by application code. This includes accessing the TLB, PSW, exception registers and breakpoint registers.

Control registers

(a)

are mapped into the address space, allowing access through normal load and store operations.

All control register accesses are word (32-bit) operations. Byte and half word loads and stores to control registers are not supported and generate CREG_ACCESS_VIOLATION exceptions.

Dismissible loads to control register space always return zero. Control register loads or stores are executed within the LSU without reference to the TLB regions.

9.2 Exceptions

●

The control register unit generates an exception when a load or store tries to: access a control register that does not exist (CREG_NO_MAPPING) access to a control register without correct permissions

(CREG_ACCESS_VIOLATION)

● perform a byte or a half word access to control registers

(CREG_ACCESS_VIOLATION)

● perform a misaligned word access to a control register (CREG_NO_MAPPING)

For details of the exception cause register, see Section 5.6: Exception types and priorities on page 28 .

Control registers cannot be accessed from the STBus.

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Control registers

9.3

ST231

Control register addresses

Table 26

shows the addresses and access permissions of all control register addresses.

The control registers are all relative to 0xFFFF 0000. Offsets listed in the table are relative to this, refer to

Section 6.2.2: Virtual addresses on page 32

for further information regarding virtual addresses. Control registers cannot be accessed from translated addresses, see

Section 6.5.5: Data accesses on page 45

The access column shows the access rights in user and supervisor mode:

ROF

CFRO

No access (protection fault)

Read only, writes ignored.

Read only fault on write.

Read/write.

Configurable read/write or no access.

Configurable read only or no access.

Table 26.

Control registers - BASE: CREG_BASE

Name Offset Access (U/S) Comment

PSW 0xFFF8 NA/RO

SAVED_PSW

SAVED_PC

HANDLER_PC

EXCAUSE

EXADDRESS

SAVED_SAVED_PSW

SAVED_SAVED_PC

EXCAUSENO

STATE1

VERSION

PERIPHERAL_BASE

SCRATCH1

0xFFF0

0xFFE8

0xFFE0

0xFFD8

0xFFD0

0xFFC0

0xFFB8

0xFF88

0xFE00

0xFFC8

0xFFB0

0xFFA8

NA/RW

NA/RO

NA/RW

NA/RO

NA/RW

The program status word.

Saved PSW, written by hardware on exception.

Saved program counter, written by hardware on exception.

The address of the exception handler code.

A one hot vector of trap (exception/interrupt) types, indicating the cause of the last trap.

Written by the hardware on a trap.

This is the data effective address in the case of either a DPU, CREG, DBREAK, or

MISALIGNED_TRAP exception. For other exception types this register is zero.

PSW saved by debug unit interrupt.

PC saved by debug unit interrupt.

Exception cause as an integer, indicating the cause of the last trap.

Global machine state register. Controls cache locking.

The version number of the core.

Base address of peripheral registers. The top 12 bits of this register are wired to the peripheral base input pins.

Scratch register reserved for use by supervisor software.

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ST231 Control registers

Table 26.

Control registers - BASE: CREG_BASE (continued)

Name Offset Access (U/S) Comment

SCRATCH2

SCRATCH3

SCRATCH4

TLB_INDEX

TLB_ENTRY0

TLB_ENTRY1

TLB_ENTRY2

TLB_ENTRY3

TLB_EXCAUSE

TLB_CONTROL

TLB_REPLACE

TLB_ASID

SCU_BASE0

SCU_LIMIT0

SCU_BASE1

SCU_LIMIT1

SCU_BASE2

SCU_LIMIT2

SCU_BASE3

SCU_LIMIT3

DBREAK_LOWER

DBREAK_UPPER

DBREAK_CONTROL

IBREAK_LOWER

IBREAK_UPPER

IBREAK_CONTROL

PM_CR

PM_CNT0

PM_CNT1

PM_CNT2

PM_CNT3

PM_PCLK

0xFFA0

0xFF98

0xFF90

0xFF80

NA/RW

0xD028

0xD030

0xD038

0xFE80

0xFE78

0xFE70

0xFDD0

0xFDC8

0xFDC0

0xF800

0xF808

0xF810

0xF818

0xF820

0xF828

0xFF78

0xFF70

0xFF68

0xFF60

0xFF58

0xFF50

0xFF48

0xFF40

0xD000

0xD008

0xD010

0xD018

0xD020

NA/RW

Scratch register reserved for use by supervisor software.

Scratch register reserved for use by the debug interrupt handler.

Index of the TLB entry pointed to by

TLB_ENTRY0-3.

Bits [31:00] of the current TLB entry.

Bits [63:32] of the current TLB entry.

Bits [95:64] of the current TLB entry.

Bits [127:96] of the current TLB entry.

Case of the TLB related exception.

Control bits for TLB.

Replacement pointer.

Current address space ID.

Base address of speculative load region.

Limit address of speculative load region.

Base address of speculative load region.

Limit address of speculative load region.

Base address of speculative load region.

Limit address of speculative load region.

Base address of speculative load region.

Limit address of speculative load region.

Data breakpoint lower address.

Data breakpoint upper address.

Data breakpoint control.

Instruction breakpoint lower address.

Instruction breakpoint upper address.

Instruction breakpoint control.

Performance monitoring control.

Performance monitor counter 0 value.

Performance monitor counter 1 value.

Performance monitor counter 2 value.

Performance monitor counter 3 value.

Performance monitor core cycle counter.

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Control registers

0xEC00

0xEC08

0xEC10

0xEC18

0xEC20

0xFF38

0xFF30

0xFF28

0xFF20

0xFF18

0xFF10

0xFF08

0xFF00

0xFE40

0xFE38

0xFE30

0xFE28

0xFE20

0xFE18

0xE410

0xE418

0xE420

0xE800

0xE808

0xE810

0xE818

0xE820

0xE000

0xE008

0xE010

0xE018

0xE020

0xE400

0xE408

Table 26.

Control registers - BASE: CREG_BASE (continued)

Name Offset Access (U/S) Comment

SDI0_DATA

SDI0_READY

SDI0_CONTROL

SDI0_COUNT

SDI0_TIMEOUT

SDI1_DATA

SDI1_READY

SDI1_CONTROL

SDI1_COUNT

SDI1_TIMEOUT

SDI2_DATA

SDI2_READY

SDI2_CONTROL

SDI2_COUNT

SDI2_TIMEOUT

SDI3_DATA

SDI3_READY

SDI3_CONTROL

SDI3_COUNT

SDI3_TIMEOUT

RESERVEDFF38

RESERVEDFF30

RESERVEDFF28

RESERVEDFF20

RESERVEDFF18

RESERVEDFF10

RESERVEDFF08

RESERVEDFF00

RESERVEDFE40

RESERVEDFE38

RESERVEDFE30

RESERVEDFE28

RESERVEDFE20

RESERVEDFE18

CF/RW SDI 0 data.

CFRO/RO SDI 0 ready.

NA/RW SDI 0 control.

NA/RW

SDI 0 count.

SDI 0 timeout.

CF/RW SDI 1 data.

CFRO/RO SDI 1 ready.

NA/RW

CF/RW

SDI 1 control.

SDI 1 count.

SDI 1 timeout.

SDI 2 data.

CFRO/RO SDI 2 ready.

NA/RW

SDI 2 control.

SDI 2 count.

SDI 2 timeout.

CF/RW SDI 3 data.

CFRO/RO SDI 3 ready.

NA/RW SDI 3 control.

NA/RW

NA/RO

SDI 3 count.

SDI 3 timeout.

Reserved

NA/RO

Reserved

NA/RO

Reserved

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9.4

Control registers

Table 26.

Control registers - BASE: CREG_BASE (continued)

Name Offset Access (U/S) Comment

RESERVEDFE10

RESERVEDFE08

0xFE10

0xFE08

NA/RO

Reserved

Data cache replacement state register

The STATE1 register controls the global state of the data cache replacement logic.

Table 27

lists the fields in the STATE1 register.

Table 27.

STATE1 bit fields

Name Bit(s) Writable Reset Comment

PARTITION

Reserved

[1:0]

[31:2]

0x0

Sets the maximum value for the round robin data cache replacement pointers as (3 -

PARTITION).

00: Replace ways 0-3.

01: Replace ways 0-2.

10: Replace ways 0-1.

11: Replace way 0 only.

A full data cache purge using prgset operations is required following the update of the field .

0x0 Reserved.

When the partition field is changed, the current data in the cache is not altered in any way. If the software wishes to force data out of a particular partition following a change to this register, the data must be purged from the cache in the normal way ( prgadd or prgset ).

For more details on cache partitioning see Section 7.3.2: Data cache partitioning on page 52

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Control registers ST231

The VERSION register contains three fields which uniquely identify a particular release of

the core. Table 28

lists the fields in the VERSION register.

Table 28.

VERSION bit fields

Name Bit(s) Writable

PRODUCT_ID

CORE_VERSION

DSU_VERSION

[15:0]

[23:16]

[31:24]

Reset Comment

Refer to datasheet

Revision of the ST200 core specified by

CORE_VERSION below.

0x05

ST200 core type. 0x05 refers to the

ST231 core.

Refer to datasheet

Version of the debugging support unit.

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10 Timers

Timers

The ST231 provides three timers. These are controlled by registers mapped into the ST231

memory space, see Chapter 11: Peripheral addresses on page 76 .

10.1 Operation

For each of the three timers, the TIMECOUNT i register (where i = 0, 1, 2) is the current value of the timer. When a timer is enabled its TIMECOUNT i value is decremented on each timer tick until zero is reached. Upon the next tick, TIMECOUNT i is loaded with

TIMECONST i , the STATUS bit in TIMECONTROL i register is then set.

The ENABLE bit in the TIMECONTROL i register controls the enabling of interrupts for each timer. The STATUS bit in the TIMECONTROL i register is AND’ed with the interrupt enable to produce the timer interrupt line. When a value of 1 is written to the STATUS bit it is cleared (and thus the interrupt is cleared).

Timer counting is enabled by the ENABLE bit in the TIMECONTROL i register. Counters are not reset when disabled, hence initial values can be written using the TIMECOUNT i registers.

The frequency of timer ticks is controlled by programming the TIMEDIVIDE register.

These registers are covered in more detail in the following subsections.

10.1.1 TIMEDIVIDEi

The TIMEDIVIDE register sets the number of bus clock cycles between each timer tick. This register can be programmed with values between 0 and 65535 (using the bottom 16 bits only). The divide value is equal to the value of this register plus one. This register is reset to zero (divide by 1). Writing this register sets the divide value and reading it returns the current divide value.

It is recommended that the boot code sets up the TIMEDIVIDE register so that timer ticks occur every 1

μ s.

The bit fields for the TIMEDIVIDE register are listed in Table 29 .

Table 29.

TIMEDEVIDE bit fields

Name Bit(s) Writable Reset Comment

DIVIDE

Reserved

[15:0] RW

[31:16] RW

0x0

Number of clock cycles required to decrement the timers +1. A value of 0 causes the timers to decrement on every clock cycle.

Reserved.

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Timers ST231

10.1.2 TIMECOUNT i

The TIMECOUNT i register returns the current value of the timer counter i .

Write to these registers to set initial values for the counters.

The bit fields of the TIMECOUNT i

are listed in Table 30

Table 30.

TIMECOUNT i bit fields

Name Bit(s) Writable Reset Comment

COUNT [31:0] RW 0x0 Current value of timer counter.

10.1.3 TIMECONST i

The TIMECONST i register contains the value loaded into timer i when timer i reaches zero.

If interrupts are enabled, the value of TIMECONST i defines the number of ticks between interrupts.

The bit fields of the TIMECONST i

are listed in Table 31 .

Table 31.

TIMECONST i bit fields

Name Bit(s) Writable Reset Comment

CONST [31:0] RW 0x0

Value to be reloaded when timer reaches zero.

10.1.4 TIMECONTROL i

The TIMECONTROL i register enables the timer, enables timer interrupts and clears a timer interrupt.

The bit fields of the TIMECONTROL i are listed in

Table 32

Table 32.

TIMECONTROL i bit fields

Name Bit(s) Writable Reset Comment

ENABLE

INTENABLE

STATUS

Reserved

[31:3]

0x0 Enable the timer

0x0 Enable the timer interrupt.

0x0

Status of the timer interrupt. When 1 a timer has expired. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears it.

0x0 Reserved

The timer interrupt lines are connected to external interrupt bits 2:0, see Section 12.3:

Interrupt registers on page 81 .

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10.3 Programming the timers

The TIMECONST i registers set the value to be reloaded into the corresponding timer. The value is loaded on the timer tick after a zero is reached, such that, the duration between timers reaching zero is (TIMECONST i + 1). For example, setting the value to 99 causes a reload and timer interrupt (if enabled) every 100 ticks.

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Peripheral addresses ST231

On the ST231 the interrupt controller, debug support registers (DSU), DSU ROM and the timers are memory mapped peripherals. Under normal usage these peripherals should, with the exception of the DSU ROM, be mapped in an uncacheable region in the TLB.

11.1 Access to peripheral registers

Note:

Peripheral registers are accessed through an STBus port. On the ST231 writes to addresses on the STBus are posted (the processor does not wait for them to complete before continuing execution). In order to guarantee that a write to a peripheral register has completed it is necessary to issue a sync operation.

This is essential in order to guarantee that an interrupt handler has cleared an interrupt or disabled a timer before doing an rfi .

The ST231 peripheral registers only support word load and store transactions, other accesses result in a bus error. The DSU ROM can be accessed by word loads and instruction cache fills, word stores are ignored and other accesses result in a bus error.

The base address of the peripheral registers is the value of the PERIPHERAL_BASE

The access columns in

Table 33

and Table 34

list the access rights for the listed registers.

The abbreviations used in this column are:

ROF

CFRO

No access (protection fault).

Read only, writes ignored.

Read only fault on write.

Read/write.

Configurable read/write or no access.

Configurable read only or no access.

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The interrupt controller and timer registers are all relative to PERIPHERAL_BASE. They are listed in

Table 33

0x0050

0x0058

0x0060

0x0068

0x0070

0x0078

0x0080

0x0210

0x0218

0x0220

0x0228

0x0230

0x0238

0x0240

0x0248

0x0040

0x0048

0x0108

0x0110

0x0118

0x0120

0x0200

0x0208

0x0000

0x0008

0x0010

0x0018

0x0020

0x0028

0x0030

0x0038

Table 33.

Interrupt controller - BASE: INTCR_BASE

Name Offset

Access

(U/S)

Reset Comment

INTPENDING0

INTPENDING1

INTMASK0

INTMASK1

INTTEST0

INTTEST1

INTCLR0

INTCLR1

INTSET0

INTSET1

INTMASKCLR0

INTMASKCLR1

INTMASKSET0

INTMASKSET1

TIMECONST0

TIMECOUNT0

TIMECONTROL0

TIMECONST1

TIMECOUNT1

TIMECONTROL1

TIMECONST2

TIMECOUNT2

TIMECONTROL2

TIMEDIVIDE

RESERVED50

RESERVED58

RESERVED60

RESERVED68

RESERVED70

RESERVED78

RESERVED80

0x0

Timer constant.

Timer counter.

Timer control

Timer constant.

Timer counter.

Timer control.

Timer divide.

Reserved

Interrupt pending bits 31:0.

Interrupt pending bits 63:32.

Interrupt mask bits 31:0.

Interrupt mask bits 63:32.

Interrupt test register bits 31:0.

Interrupt test register bits 63:32.

Interrupt clear register bits 31:0.

Interrupt clear register bits 63:32.

Interrupt set register bits 31:0.

Interrupt clear register bits 63:32.

Interrupt mask clear bits 31:0.

Interrupt mask clear bits 63:32.

Interrupt mask set bits 31:0.

Interrupt mask set bits 63:32.

Timer constant.

Timer counter.

Timer control

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Peripheral addresses

Table 33.

Interrupt controller - BASE: INTCR_BASE (continued)

Name Offset

Access

(U/S)

Reset Comment

RESERVED88

RESERVED90

RESERVED98

RESERVED100

0x0088

0x0090

0x0098

0x0100

0x0

Reserved

ST231

78/331

The debug support unit registers are all relative to PERIPHERAL_BASE. They are listed in

Table 34

Table 34.

Debug support unit - BASE: DSU_BASE

Name Offset

Access

(U/S)

Reset

DSR0

DSR1

DSR2

DSR3

DSR4

DSR5

DSR6

DSR7

DSR8

DSR9

DSR10

DSR11

DSR12

DSR13

DSR14

DSR15

DSR16

DSR17

DSR18

DSR19

DSR20

DSR21

0x0000

0x0008

0x0048

0x0050

0x0058

0x0060

0x0068

0x0070

0x0078

0x0080

0x0010

0x0018

0x0020

0x0028

0x0030

0x0038

0x0040

0x0088

0x0090

0x0098

0x00a0

0x00a8

Comment

See Table 28 on page 72 .

DSU version.

See Table 54 on page 92 .

DSU status.

0x0

DSU output.

DSU communication.

0x0

DSU communication.

0x0 DSU communication.

0x0

DSU communication.

0x0

DSU communication.

0x0

DSU communication.

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ST231 Peripheral addresses

Table 34.

Debug support unit - BASE: DSU_BASE (continued)

Name Offset

Access

(U/S)

Reset Comment

DSR22

DSR23

DSR24

DSR25

DSR26

DSR27

DSR28

DSR29

DSR30

DSR31

0x00b0

0x00b8

0x00c0

0x00c8

0x00d0

0x00d8

0x00e0

0x00e8

0x00f0

0x00f8

0x0

DSU communication.

The DSU ROM starts from PERIPHERAL_BASE + 0x4000. See Chapter 13: Debugging support (TAPLink) on page 87 .

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Interrupt controller

The ST231 interrupt controller supports up to 64 interrupt sources. The system is programmed using three pairs of 32-bit memory-mapped control registers.

12.1 Architecture

The structure of the interrupt controller is shown in

Figure 11 .

Figure 11.

Interrupt controller

External events

(3 dedicated to the timer)

“OR”

64 lines

“ AND”

64 lines

Interrupt line to processor

ST231

64 bits

Master interrupt input

64 bits

12.2 Operation

Note:

An interrupting event takes an interrupt line high. This is then sampled, causing the corresponding bit in the INTPENDING register to be set. The INTPENDING register is then parallel ANDed with the INTMASK register. The masked interrupts are then ORed into a single interrupt line that is presented to the processor core.

This architecture ensures that:

●

● all external interrupts interrupt the processor interrupts can be individually enabled or disabled

Setting or clearing bits in the INTMASK registers enables or disables the corresponding interrupt lines.

The interrupt handling code is responsible for prioritization of interrupts. No hardware support is provided.

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External interrupts are ORed with the contents of the INTTEST register before being sampled by the INTPENDING register. This allows the programmer to simulate interrupts into the processor for test purposes.

12.2.2 Master interrupt input

An external interrupt controller can be added to the core through the IRQ_MASTER_IN port.

IRQ_MASTER_IN cannot be masked.

This is intended to be used instead of the internal interrupt controller. In this case, all interrupt inputs (IRQ) should be tied to zero, internal interrupts should be masked and timer interrupts outputs (IRQ_TIMER_OUT) should be connected to the external interrupt controller and dealt with through that.

For the addresses of these memory mapped registers see Chapter 11: Peripheral addresses on page 76

The INTPENDING registers are a pair of 32-bit registers that hold the current interrupt status. Bits in these registers are set by external interrupts or by the INTTEST registers.

Three bits in the INTPENDING registers are preassigned to the ST231 timer peripherals.

The remaining 60 bits can be assigned to other peripherals or external devices.

Table 35

and

Table 37 list the bit fields in the INTPENDING registers, which indicate the

pending interrupts.

INTPENDING0

Table 35.

INTPENDING0 bit fields

Name Bit(s) Writable Reset Comment

TIMER0

TIMER1

TIMER2

Reserved

[31:3]

0x0 Interrupt is pending from timer 0.

0x0 Interrupt is pending from timer 1.

0x0 Interrupt is pending from timer 2.

0x0

System defined interrupts 31:3 – refer to data sheet.

INTPENDING1

Table 36.

INTPENDING1 bit fields

Name Bit(s) Writable Reset Comment

Reserved [31:0] RO 0x0

System defined interrupts 63:32 – refer to data sheet.

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Interrupt controller ST231

The INTMASK registers are a pair of 32-bit registers whose contents are AND-ed with the corresponding INTPENDING register. They are used to enable and disable external interrupts.

Interrupts are enabled by setting, and disabled by clearing, the corresponding bits in the

INTMASK registers.

Table 37

and

Table 38 list the bits of the INTMASK register.

INTMASK0

Table 37.

INTMASK0 bit fields

Name Bit(s) Writable Reset Comment

TIMER0

TIMER1

TIMER2

Reserved

[31:3]

0x0 Mask bit for timer 0

0x0 Mask bit for timer 1

0x0 Mask bit for timer 2

0x0

Mask bits for system defined interrupts

31:3 – refer to data sheet.

INTMASK1

Table 38.

INTMASK1 bit fields

Name Bit(s) Writable Reset Comment

Reserved [31:0] RW 0x0

Mask bits for system defined interrupts

63:32 – refer to data sheet.

12.3.3 Interrupt mask set and clear registers (INTMASKSET and

INTMASKCLR)

These registers provide a mechanism for atomically setting or clearing bits in the INTMASK registers, and remove the requirement for an uninterruptible Read-Modify-Write sequence.

When a program stores a 32-bit value into either of the INTMASKSET registers, any bits that are set to 1 cause the corresponding bit in the corresponding INTMASK register to be set to 1. Those bits that are 0 have no effect on the corresponding bits in the corresponding

INTMASK register.

When a program stores a 32-bit value into either of the INTMASKCLR registers, any bits that are set to 1 cause the corresponding bit in the corresponding INTMASK register to be set to 0. Those bits that are 0 have no effect on the corresponding bits in the corresponding

INTMASK register.

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Table 39

shows the outcome of writing a value V to any of the four registers.

Table 39.

Action of interrupt mask set and clear registers

New value

Value “V” written to:

INTMASK0

INTMASKSET0

INTMASKSET1

INTMASKCLR0

INTMASKCLR1

INTMASK0 OR V

INTMASK0

INTMASK0 AND ~V

INTMASK0

INTMASK1

INTMASK1

INTMASK1 OR V

INTMASK1

INTMASK1 AND ~V

OR is a bitwise OR, AND is a bitwise AND and ~V is the bitwise complement of V.

Table 40 and Table 41 list the bits of the INTMASKCLR registers and Table 42 and

Table 43

list the bits of the INTMASKSET registers.

INTMASKCLR0

Table 40.

INTMASKCLR0 bit fields

Name Bit(s) Writable Reset Comment

TIMER0

TIMER1

TIMER2

Reserved

[31:3]

0x0 Mask clear bit for timer 0

0x0 Mask clear bit for timer 1

0x0 Mask clear bit for timer 2

0x0

Mask clear bits for system defined interrupts 31:3 – refer to data sheet.

INTMASKCLR1

Table 41.

INTMASKCLR1 bit fields

Name Bit(s) Writable Reset Comment

Reserved [31:0] WO 0x0

Mask clear bits for system defined interrupts 63:32 – refer to data sheet.

INTMASKSET0

Table 42.

INTMASKSET0 bit fields

Name Bit(s) Writable Reset Comment

TIMER0

TIMER1

TIMER2

Reserved

[31:3]

0x0 Mask set bit for timer 0

0x0 Mask set bit for timer 1

0x0 Mask set bit for timer 2

0x0

Mask set bits for system defined interrupts 31:3 – refer to data sheet.

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Interrupt controller ST231

INTMASKSET1

Table 43.

INTMASKSET1 bit fields

Name Bit(s) Writable Reset Comment

Reserved [31:0] WO 0x0

Mask set bits for system defined interrupts 63:32 – refer to data sheet.

The INTTEST registers are a pair of 32-bit registers whose contents are ORed with the assertion state of external interrupts. It provides a mechanism for simulating interrupts to the processor.

Setting bits in the INTTEST registers causes the corresponding bits in the corresponding

INTPENDING register to be set.

Table 44

and

Table 45 list the bits of the INTTEST register.

INTTEST0

Table 44.

INTTEST0 bit fields

Name Bit(s) Writable Reset Comment

TIMER0

TIMER1

TIMER2

Reserved

[31:3]

0x0 Interrupt test bit for timer 0

0x0 Interrupt test bit for timer 1

0x0 Interrupt test bit for timer 2

0x0

Interrupt test bits for system defined interrupts 31:3 – refer to data sheet.

INTTEST1

Table 45.

INTTEST1 bit fields

Name Bit(s) Writable

Reserved [31:0] RW

Reset Comment

0x0

Interrupt test bits for system defined interrupts 63:32 – refer to data sheet.

12.3.5 Interrupt set and clear registers (INTSET and INTCLR)

These registers provide a mechanism for atomically setting or clearing bits in the INTTEST registers, and remove the requirement for an uninterruptible Read-Modify-Write sequence.

When a program stores a 32-bit value into either of the INTSET registers, any bits that are set to 1 cause the corresponding bit in the corresponding INTTEST register to be set to 1.

Those bits that are 0 have no effect on the corresponding bits in the corresponding

INTTEST register.

When a program stores a 32-bit value into the INTCLR register, any bits that are set to 1 cause the corresponding bit in the corresponding INTTEST register to be set to 0. Those bits that are 0 have no effect on the corresponding bits in the corresponding INTTEST register.

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Table 46

shows the outcome of writing a value V to any of the four registers.

Table 46.

Action of interrupt set and clear registers

New value

Value “V” written to:

INTTEST0

INTSET0

INTSET1

INTCLR0

INTCLR1

INTTEST0 OR V

INTTEST0

INTTEST0 AND ~V

INTTEST0

INTTEST1

INTTEST1

INTTEST1 OR V

INTTEST1

INTTEST1 AND ~V

OR is a bitwise OR, AND is a bitwise AND and ~V is the bitwise complement of V.

Table 47

and

Table 48 list the bits of the INTCLR registers and Table 49

and Table 50 list the

bits of the INTSET registers.

INTCLR0

Table 47.

INTCLR0 bit fields

Name Bit(s) Writable Reset Comment

TIMER0

TIMER1

TIMER2

Reserved

[31:3]

0x0 Interrupt clear bit for timer 0

0x0 Interrupt clear bit for timer 1

0x0 Interrupt clear bit for timer 2

0x0

Interrupt clear bits for system defined interrupts 31:3 – refer to data sheet.

INTCLR1

Table 48.

INTCLR1 bit fields

Name Bit(s) Writable Reset Comment

Reserved [31:0] WO 0x0

Interrupt clear bits for system defined interrupts 63:32 – refer to data sheet.

INTSET0

Table 49.

INTSET0 bit fields

Name Bit(s) Writable Reset Comment

TIMER0

TIMER1

TIMER2

Reserved

[31:3]

0x0 Interrupt set bit for timer 0

0x0 Interrupt set bit for timer 1

0x0 Interrupt set bit for timer 2

0x0

Interrupt set bits for system defined interrupts 31:3 – refer to data sheet.

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Interrupt controller ST231

INTSET1

Table 50.

INTSET1 bit fields

Name Bit(s) Writable Reset Comment

Reserved [31:0] WO 0x0

Interrupt set bits for system defined interrupts 63:32 – refer to data sheet.

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13

Note:

Debugging support (TAPLink)

Debugging support (TAPLink)

The debugging support specified in this and the next chapter is implementation dependant.

Check the product datasheet for details as to which support is provided.

Debugging support on the ST231 is provided by 4 main components.

Core

DSU

The ST231 core includes a non-maskable debug interrupt, and additional state to support the taking of debug interrupts. The core also contains hardware breakpoint support.

Shared DSU registers and state machine which generates debug interrupts and send responses over debug interface.

Debug ROM Default program run in response to debug interrupt. This program uses the

DSU registers to send higher level protocols over the debug interface. This program implements the dsu_peek , dsu_poke , dsu_call_or_return and dsu_flush operations.

Host debug interface

The hardware link, using the TAPLink protocol, to any connected host target interface (HTI). Supports peek , poke , peeked and event messages.

13.1 Core

This section describes debug interrupts, including entering and exiting debug mode, and hardware breakpoint support.

The ST231 can accept and service interrupts from the DSU. Debug interrupts are higher priority than normal interrupts, cannot be masked, and place the ST231 in a debug state.

A debug interrupt can be triggered either by an event from the host (see Generating debug interrupts on page 97

) or by an external trigger, see DSU status register (DSR1) on page 91

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Debugging support (TAPLink) ST231

Entering debug mode

The ST231 handles a debug interrupt differently to other external interrupts. When a debug interrupt is taken, the TLB is disabled and the processor jumps to the start of the debug

ROM. As the TLB is disabled, memory accesses above 0xFFFF 0000 access control registers (see

Section 6.5.5: Data accesses on page 45

). If access to physical memory from

0xFFFF 0000 upwards is required, the TLB must be re-enabled.

Taking a debug interrupt can be summarized as:

NEXT_PC

←

Branch to handler

SAVED_SAVED_PSW

←

Save the SAVED_PSW and

SAVED_SAVED_PC

←

SAVED_PC

SAVED_PSW

←

Save the PSW and PC

SAVED_PC

←

PSW[USER_MODE]

←

PSW[INT_ENABLE]

←

PSW[TLB_ENABLE]

←

PSW[DEBUG_MODE]

←

PSW[DBREAK_ENABLE]

←

PSW[IBREAK_ENABLE]

←

Enter supervisor mode

Disable interrupts

Disables the TLB

Enter debug mode

Disable DBreak

// Disable IBreak

The EXCAUSENO and EXADDRESS registers are not updated when entering debug mode.

If the core accepts another debug interrupt whilst in debug mode, and if the debug interrupt is still pending when it leaves debug mode, the interrupt re-enters as normal.

The default debug ROM itself is not aware of virtual memory issues and provides the host with a physical view of memory. If address translation is in use, the operating system must install its own debug handler that is aware of virtual memory.

Exiting debug mode

When the DEBUG_MODE bit is cleared in the PSW, the ST231 exits debug mode and reenters normal mode. If a debug interrupt is pending when the core leaves debug mode, it is re-entered as normal, see Entering debug mode on page 88 .

Although clearing the DEBUG_MODE bit causes the ST231 to exit debug mode, attempting to set the DEBUG_MODE bit when it is not already set does not cause the core to enter debug mode and the DEBUG_MODE bit remains clear. The core can only enter debug mode by taking a debug interrupt from the DSU.

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Note:

Breakpoints are supported by:

●

● enable bits in the PSW address registers to define memory ranges control register to specify comparison operations

The safe way to use the breakpoint registers is to disable the breakpoints and then set the control and address registers before enabling the breakpoints again. This prevents spurious breaks due to inconsistent control and address registers.

Enable bits

Breakpoints are enabled though the PSW, one bit for instruction breakpoints and another

data breakpoints, see Section 3.4: Program status word (PSW) on page 19 .

Address registers

The ST231 uses two 32-bit registers to define addresses for the instruction and data breakpoints (IBREAK_LOWER, DBREAK_LOWER, IBREAK_UPPER, DBREAK_UPPER).

These registers are all reset to the value 0.

Control registers

The IBREAK_CONTROL and DBREAK_CONTROL registers determine the comparison operations performed on the breakpoint addresses. If the comparison is true, then a breakpoint exception (IBREAK or DBREAK) is signaled.

For instruction breakpoints, the currently executing bundle address (PC) is used for comparison.

For data breakpoints, the data effective address of load s (both standard and dismissible) and store s are used for comparison. Prefetches and purges do not trigger data breakpoints.

Table 51

and

Table 52 provide details of the comparison operations defined for the

instruction and data breakpoints.

As the PC does not contain bits 1:0, these bits are ignored in any instruction address comparisons.

Table 51.

DBREAK_CONTROL bit fields

Name Bit(s) Writable Reset Comment

BRK_IN_RANGE

BRK_OUT_RANGE

BRK_EITHER

BRK_MASKED

Reserved

[31:4]

0x0

Break if address >= lower && address

<=upper.

Break if address < lower || address > upper.

Break if address == lower || address == upper.

0x0 Break if address & upper == lower.

0x0 Reserved

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Debugging support (TAPLink) ST231

Table 52.

IBREAK_CONTROL bit fields

Name Bit(s) Writable Reset Comment

BRK_IN_RANGE

BRK_OUT_RANGE

BRK_EITHER

BRK_MASKED

Reserved

[31:4]

0x0

Break if address >= lower && address

<=upper.

Break if address < lower || address > upper.

Break if address == lower || address == upper.

0x0 Break if address & upper == lower.

0x0 Reserved

The DSU allows both software and hardware to be debugged from a host by providing direct access to the ST231 core.

13.2.1 Architecture

Figure 12

shows the architecture of the DSU.

Figure 12.

DSU architecture

Debug Support Unit

WRITEENABLE

Host

Host debug interface

Control block

Shared register bank

Debug

ROM

DEBUG_INTERRUPT

DEBUG_INTERRUPT_TAKEN

STBus port

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ST231 Debugging support (TAPLink)

The DSU is controlled by a host through the debug interface. The DSU control block interacts directly with the ST231 core through the DEBUG_INTERRUPT and

DEBUG_INTERRUPT_TAKEN signals, and the shared register block.

The shared registers can also be accessed through the STBus port.

13.2.2 Shared register bank

The 32 shared registers consists of 3 reserved registers (DSR0-2) and 29 general purpose registers (DSR3-31). These are used to implement communication between the host and the target by the debug handler.

The shared register bank is 32-bits wide and only supports 32-bit STBus operations.

Table 53

lists the DSU shared registers.

Table 53.

DSR_REG values

Name Value Comment

DSR0

DSR1

DSR2

DSR3-31

3-31

DSU version register, contains version number for DSU, core and chip.

DSU status register, contains DSU control and status bits.

DSU output register, supports message transfer from target to HTI.

General purpose registers.

The STBus addresses of the DSU registers are described in

Chapter 11: Peripheral addresses on page 76

Shared access conventions

The DSU shared registers are accessible independently from both the DSU and the STBus.

The ST231 and DSU have no hardware support for synchronizing writes, so software conventions are used to prevent write conflicts.

13.2.3 DSU control registers

This subsection describes the DSU control registers: DSU version register, DSU status register and DSU output register.

DSU version register (DSR0)

The DSU version register is a read-only ID register. The fields are identical to the version

DSU status register (DSR1)

The DSU status register contains the DSU status and control bits. See

Table 54 .

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Debugging support (TAPLink) ST231

Table 54.

DSR1 bit fields

Name

DEBUG_INTERRUPT_TAKEN

SUPERVISOR_WRITE_ENABLE

USER_WRITE_ENABLE

BIGENDIAN

Reserved

OUTPUT_PENDING

TRIGGER_IN

TRIGGER_OUT

TRIGGER_ENABLE

Reserved

SW_FLAGS

Bit(s) Writable Reset Comment

[15:9]

[31:16]

0x0

0x1

0x0

Value of

DEBUG_INTERRUPT_TAKE

N signal, active high.

STBus writes enabled if the core is in supervisor mode

(regardless of debug mode).

STBus writes enabled if the core is in user mode

(regardless of debug mode).

0x0

When 1 the core is in big endian mode. When 0 the core is in little endian.

0x0 Reserved

0x0

DSR2 contains a byte to be sent to the HTI which has not yet been sent.

Current value of the trigger in pin.

Current value of the trigger out pin.

0x0

Enables/disables debug interrupts on trigger in.

0x0 Reserved

0x0

Reserved for future software use.

DSU output register (DSR2)

The lower 8 bits of the DSU output register are sent to the TAPLink (to any attached host)

on being written. See Table 55

Table 55.

DSR2 bit fields

Name Bit(s)

DATA

Reserved

[7:0]

[31:8]

Writable

Reset

0x0

Comment

Output data.

Always zero.

If OUTPUT_PENDING is non-zero then the byte most recently written has not yet been sent to the host target interface (HTI) and additional writes to the DSR2 do not affect the byte being sent even if they change the contents of the register.

Messages sent using the DSR2 may be delayed if the DSU is busy.

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The 1024-byte debug ROM is an ST231 peripheral. This contains the debug initialization loop and the default debug handler.

Note:

On reset, the ST231 starts executing at the beginning of the boot ROM. However, if the

DEBUG_ENABLE signal is asserted execution starts at the debug initialization loop (this is the first word of the debug ROM). This word contains a single syllable bundle which loops back to the same location, allowing the DSU to intervene and configure the core before it executes any code.

Where the DEBUG_ENABLE signal cannot be asserted, the boot ROM should start with a tight loop, or perhaps just a delay loop, to allow time for the DSU to interrupt the processor before it takes any action.

13.3.2 Default debug handler

The default debug handler program starts at the second word of the debug ROM. It supports simple host-target debugging and the ability to install a more complex debug handler. The

STBus address of the ROM is given in

Chapter 11: Peripheral addresses on page 76

Operation

On taking a debug interrupt, the default debug handler is executed. This first tests if a user handler is installed (that is, DSR3 is non zero) and if so branches to this address. The default debug handler then sends an event message to the host. This occurs even if

DSU_COMMAND is 0. The handler then enters the command loop.

Command loop

The command loop reads and processes commands from a host, delivered via the TAPLink,

to the DSU shared registers. Usage of the designated registers is shown in Table 56 .

Table 56.

Command register usage

Register name Host use Target use

DSU_COMMAND Set with command

DSU_ARG1,2,3

Set with arguments for command, before setting DSU_COMMAND

DSU_RESPONSE Zeroed after being read

Zeroed when command accepted

Set with response arguments before setting DSU_RESPONSE

Set to indicate outcome of a command

When the command is complete, the default debug handler stores the results in the argument registers and sets a success code in the response register.

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Debugging support (TAPLink)

Note:

ST231

Default handler commands

There are four default handler commands:

● DSU_PEEK (DSU_COMMAND = 4)

Reads the 32-bit memory location addressed by DSU_ARG1 and returns the data in

DSU_ARG1. The address must be word aligned. If the operation is successful

DSU_RESPONSE is set to DSU_PEEKED (1) and a TAPLINK_EVENT_DEFAULT event is written to DSR2 causing an event with reason = 1 to be sent to the host.

Any code greater than 4 is interpreted as a DSU_PEEK command.

● DSU_POKE (DSU_COMMAND = 3)

Writes the 32-bit data word in DSU_ARG2 to the memory location addressed by

DSU_ARG1. The address must be word aligned. If the operation is successful

DSU_RESPONSE is set to DSU_POKED (2) and a TAPLINK_EVENT_DEFAULT event is written to DSR2 causing an event with reason = 1 to be sent to the host.

● DSU_CALL_OR_RETURN (DSU_COMMAND = 1)

Calls the routine addressed by DSU_ARG1. If the called routine does not return this is effectively a branch. If DSU_ARG1 is zero this is a return call. Just before calling the user routine, or returning from a call, DSU_RESPONSE is set to DSU_RETURNING

(3) and a TAPLINK_EVENT_DEFAULT event is written to DSR2 causing an event with reason = 1 to be sent to the host.

● DSU_FLUSH (DSU_COMMAND = 2)

Flushes the address range starting at the value in DSU_ARG1 and ending at the value in DSU_ARG2 from data and instruction caches. If a command was successful

DSU_RESPONSE is set to DSU_FLUSHED (4) and a TAPLINK_EVENT_DEFAULT event is written to DSR2 causing an event with reason = 1 to be sent to the host.

Trap handler

If a trap occurs while a command is being processed (for example, an invalid address is supplied on a peek or poke ), the core deals with it as follows.

● The operation in progress is completed by loading the PC of the offending bundle, the exception cause number, and the exception address into DSR_ARG1, DSR_ARG2 and DSR_ARG3 respectively.

●

DSU_RESPONSE is set to DSU_GOT_EXCEPTION (Code = 5) and a

TAPLINK_EVENT_DEFAULT (Reason = 7) event is sent to the HTI.

As with all exceptions, the SAVED_PC, SAVED_PSW, EXCAUSENO and

EXADDRESS registers are updated when the exception occurs. The debug handler restores the values of these registers upon exit.

Context restore

Prior to exit the default handler restores any state it has altered.

The context may have been further altered by commands issued.

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Default handler register usage

The following DSU registers are defined and used by the default debug handler program:

Table 57.

DSU command registers

DSR number

Designation Comment

DSR3 DSR_USER_DEBUG_HANDLER

Control switches to this address if content is non-zero

Not used in current debug handler DSR4-8

(1)

DSR9

(1)

DSU_ARG4-8

DSU_ARG3

DSR10

DSR11

DSR12

DSR13

(1)

DSU_ARG2

DSU_ARG1

DSU_COMMAND

DSU_RESPONSE

DSR14

DSR15

DSR16

DSR17

DSR18

DSR19

DSR20

DSR21

Context saving

DSR22

DSR23

DSR24

DSR25

Context saving

DSR26 Context saving

DSR27-30 Unused

DSR31 Context saving

Command argument 3

Command argument 2. Used by DSU_POKE and DSU_FLUSH

Command argument 1. Used by all DSU commands

Command register. Written by HTI, cleared by target when command accepted

Response register. Set by target to a completion code, cleared by HTI before issuing next command

Saves SCR4_REG (2)

Saves SCR1_REG (2)

Saves SCR2_REG

( 2)

Saves SCR3_REG (2)

Saves the branch bits

Saves LINK_REG (2)

Saves HANDLER_PC

Saves SAVED_SAVED_PSW

Saves SAVED_SAVED_PC

Saves SAVED_PSW

Saves SAVED_PC

Saves EXCAUSENO

Saves EXADDRESS

Unused

Saves DSR1

Argument registers are placed before the command register in the address space so that a command and its arguments can be loaded with a single poke operation.

As defined by the toolchain header files.

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13.4 Host debug interface

The exchange of information with the host is through an HTI adapter. The DSU connects to the HTI using a JTAG interface, and the HTI connects to the host using Ethernet or USB.

This is illustrated in Figure 13 .

All host-target communication is carried out using peek , poke , peeked and event messages, passed between the host and the DSU.

Figure 13.

DSU overview

Host

HTI adapter

JTAG

DSU ST200 core

Note:

Commands are sent to the DSU in TAPLink message format consisting of a bidirectional byte stream which is interpreted by the DSU as a stream of commands.

Figure 14

shows the

DSU commands in TAPLink message format.

Figure 14.

DSU commands

HTI initiated messages

Poke DSR address

Peek DSR address

First data word Second...

HTI or target initiated messages

Event

Response messages

Peeked First data word

Header byte

2nd byte

Second data word Third...

Messages are transmitted little endian, irrespective of the endianness of the ST231 core.

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Header bytes

Header bytes contain command-specific information such as the range of registers to be

accessed. Header byte formats for the 4 DSU commands are illustrated in Figure 15

Figure 15.

Header bytes

Poke

Peek

Peeked

Event

5 4 word count

6 channel

5 4

3 reason

Header byte

Subsequent bytes

Note:

Peek and poke operation

The peek and poke commands read and write the shared DSU registers. Each command uses a 6-bit count and one byte as a register address. The byte address references the first register in the range, and the count indicates how many registers are accessed. Counts greater than 32 have undefined results.

The result of a peek command is returned to the host using a PEEKED message.

PEEKED messages are not supported from the host to the target and their behavior is undefined.

13.4.2 Operation

The operation of the host debug interface operation.

Generating debug interrupts

To interrupt the core, the host sends an EVENT with reason = 1. The EVENT is decoded by the DSU and a DEBUG_INTERRUPT signal is sent to the ST231. When the ST231 takes the interrupt (as described in

Section 13.1.1: Debug interrupts on page 87 ), the

DEBUG_INTERRUPT_TAKEN signal goes high.

The functionality available to the host depends upon the debug handler program running.

The default handler uses designated shared registers to provide the higher level operations described in Default handler commands on page 94 .

Core initiated events

The core can also request service from the host by sending it an EVENT message. This is done by writing the EVENT to the DSR2 (the output register). The channel and reason fields of the event message are not examined by the hardware and can be used as desired by the software.

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14 Debugging support (JTAG)

Note:

ST231

The debugging support specified in this and the previous chapter is implementation specific.

Check the product datasheet for details as to which support is provided.

Debugging support on the ST231 is provided by 4 main components.

Core

DSU

Debug ROM

Host debug interface

The ST231 core includes a non maskable debug interrupt and additional state to support the taking of debug interrupts. The core also contains hardware breakpoint support.

Shared DSU registers and state machine which generates debug interrupts and send responses over debug interface.

Default program run in response to debug interrupt. This program uses the

DSU registers to send higher level protocols over the debug interface. This program implements the dsu_peek , dsu_poke , dsu_call_or_return and dsu_flush operations.

The hardware link, using the JTAG protocol, to a host via a host target interface (HTI). Supports peek , poke , peeked , poked , event , nop and event_ack messages.

14.1 Core

This section describes debug interrupts, including entering and leaving debug mode, and hardware breakpoints.

The ST231 can accept and service interrupts from the DSU. Debug interrupts are higher priority than normal interrupts, cannot be masked, and place the ST231 in a debug state.

A debug interrupt can be triggered either by an event from the host (see Host to DSU events on page 110 ) or by an external trigger, see

DSU status register (DSR1) on page 102

Entering debug mode

A debug interrupt is handled differently to other external interrupts. When a debug interrupt is taken, the TLB is disabled and the processor jumps to the start of the debug ROM. As the

TLB is disabled, memory accesses above 0xFFFF 0000 access control registers (see

Section 6.5.5: Data accesses on page 45

). If access to physical memory from

0xFFFF 0000 upwards is required, the TLB must be re-enabled.

Taking a debug interrupt can be summarized as:

NEXT_PC

←

Branch to handler

SAVED_SAVED_PSW

←

Save the SAVED_PSW and

SAVED_SAVED_PC

←

SAVED_PC

SAVED_PSW

←

Save the PSW and PC

SAVED_PC

←

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PSW[USER_MODE]

←

PSW[INT_ENABLE]

←

PSW[TLB_ENABLE]

←

PSW[DEBUG_MODE]

←

PSW[DBREAK_ENABLE]

←

PSW[IBREAK_ENABLE]

←

Enter supervisor mode

Disable interrupts

Disables the TLB

Enter debug mode

Disable DBreak

// Disable IBreak

The EXCAUSENO and EXADDRESS registers are not updated when entering debug mode.

If the core accepts another debug interrupt whilst in debug mode, and if the debug interrupt is still pending when it leaves debug mode, the interrupt re-enters as normal.

Exiting debug mode

Although clearing the DEBUG_MODE bit causes the ST231 to exit debug mode, attempting to set the DEBUG_MODE bit when it is not already set does not cause the core to enter debug mode and the DEBUG_MODE bit remains clear. Debug mode can only be entered by taking a debug interrupt from the DSU.

Breakpoints are supported by:

●

● enable bits in the PSW address registers to define memory ranges control register to specify comparison operations

Enable bits

Breakpoints are enabled though the PSW, one bit for instruction breakpoints and another

data breakpoints, see Section 3.4: Program status word (PSW) on page 19 .

Address registers

The ST231 uses two 32-bit registers to define addresses for the instruction and data breakpoints (IBREAK_LOWER, DBREAK_LOWER, IBREAK_UPPER, DBREAK_UPPER).

These registers are all reset to the value 0.

Control registers

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Note:

ST231

For instruction breakpoints, the currently executing bundle address (PC) is used for comparison.

For data breakpoints, the data effective address of loads (both standard and dismissible) and stores are used for comparison. Prefetches and purges do not trigger data breakpoints.

Table 58

and

Table 59 provide details of the comparison operations defined for the

instruction and data breakpoints.

As the PC does not contain bits 1:0, these bits are ignored in any instruction address comparisons.

Table 58.

DBREAK_CONTROL bit fields

Name Bit(s) Writable Reset Comment

BRK_IN_RANGE

BRK_OUT_RANGE

BRK_EITHER

BRK_MASKED

Reserved

[31:4]

0x0

Break if address >= lower && address

<=upper.

Break if address < lower || address > upper.

Break if address == lower || address == upper.

0x0 Break if address & upper == lower.

0x0 Reserved

Table 59.

IBREAK_CONTROL bit fields

Name Bit(s) Writable Reset Comment

BRK_IN_RANGE

BRK_OUT_RANGE

BRK_EITHER

BRK_MASKED

Reserved

[31:4]

0x0

Break if address >= lower && address

<=upper.

Break if address < lower || address > upper.

0x0

Break if address == lower || address == upper.

0x0 Break if address & upper == lower.

0x0 Reserved

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The DSU allows both software and hardware to be debugged from a host by giving direct access to the ST231 core.

14.2.1 Architecture

Figure 16

shows the architecture of the DSU.

Figure 16.

DSU architecture

Debug Support Unit

WRITEENABLE

Host

Host debug interface

Control block

Shared register bank

Debug

ROM

DEBUG_INTERRUPT

DEBUG_INTERRUPT_TAKEN

STBus port

The DSU is controlled by a host through the debug interface. The DSU control block interacts directly with the ST231 core through the DEBUG_INTERRUPT and

DEBUG_INTERRUPT_TAKEN signals, and the shared register block.

The shared registers can also be accessed via the STBus port.

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14.2.2 Shared register bank

The 32 shared registers consist of 3 reserved registers (DSR0-2) and 29 general purpose registers (DSR3-31). These are used to implement communication between the host and the target by the debug handler.

The shared register bank is 32-bits wide and only supports 32-bit STBus operations.

Table 60

lists the DSU shared registers.

Table 60.

DSR_REG values

Name Value Comment

DSR0

DSR1

DSR2

DSR3-31

3-31

DSU version register, contains version number for DSU, core and chip.

DSU status register, contains DSU control and status bits.

DSU output register, supports message transfer from target to HTI,

see Section 14.4 on page 107 .

General purpose registers.

The STBus addresses of the DSU registers are described in

Chapter 11: Peripheral addresses on page 76

Shared access conventions

The DSU shared registers are accessible independently from both the DSU and the STBus.

The ST231 and DSU have no hardware support for synchronizing writes, so software conventions are used to prevent write conflicts.

14.2.3 DSU control registers

This subsection describes the DSU control registers: the DSU version register, the DSU status register and the DSU output register.

DSU version register (DSR0)

The DSU version register is a read-only ID register. The fields are identical to the version

DSU status register (DSR1)

The DSU status register contains the DSU status and control bits. See

Table 61 .

Table 61.

DSR1 bit fields

Name

DEBUG_ INTERRUPT_ TAKEN

SUPERVISOR_ WRITE_ENABLE

Bit(s) Writable Reset Comment

0x0

0x1

Value of

DEBUG_INTERRUPT_TAKEN signal, active high.

STBus writes enabled if the core is in supervisor mode (regardless of debug mode).

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Table 61.

DSR1 bit fields (continued)

Name Bit(s) Writable Reset Comment

USER_WRITE_ ENABLE

BIGENDIAN

HOST_EVENT_ ACK_PENDING

OUTPUT_PENDING

TRIGGER_IN

TRIGGER_OUT

TRIGGER_ENABLE

Reserved

SW_FLAGS

[15:9]

[31:16]

0x0

STBus writes enabled if the core is in user mode (regardless of debug mode).

When 1 the core is in big endian mode. When 0 the core is in little endian.

The host is pending an event and an event_ack command is pending.

0x0

DSR2 contains a byte to be sent to the HTI which has not yet been sent.

0x0 Current value of the trigger in pin.

0x0

Current value of the trigger out pin.

Enables/disables debug interrupts on trigger in.

0x0 Reserved

0x0 Reserved for future software use.

DSU output register (DSR2)

A value written to DSR2 is sent to the host (using the HTI) by an EVENT message, which is handshaken with an EVENT_ACK message. See DSU to host events on page 111 for

details. Table 62 gives details of the DSR2 register.

Table 62.

DSR2 bit fields

Name Bit(s)

DATA [31:0]

Writable

Reset Comment

0x0 Output data.

The 1024-byte debug ROM is an ST231 peripheral. This contains the debug initialization loop and the default debug handler.

Note:

On reset, the ST231 starts executing at the beginning of the boot ROM. However, if the

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14.3.2 Default debug handler

The default debug handler program starts at the second word of the debug ROM. It supports simple host-target debugging and the ability to install a more complex debug handler. The

STBus address of the ROM is given in

Chapter 11: Peripheral addresses on page 76

The value in SCRATCH4 is overwritten when the default debug handler starts and is not restored.

Operation

On taking a debug interrupt, the default debug handler is executed. This first tests if a user handler is installed (that is, DSR3 is non zero) and if so branches to the given address. See

Section 14.3.3: User-defined debug handler on page 107

. The default debug handler then sends an event message to the host. This occurs even if DSU_COMMAND is 0. The handler then enters the command loop.

Command loop

The command loop reads and processes commands from a host, delivered over the JTAG connection, to the DSU shared registers. Usage of the designated registers is shown in

Table 63

Table 63.

Command register usage

Register name Host use

DSU_COMMAND

DSU_ARG1,2,3

DSU_RESPONSE

Target use

The host sets this register to the command.

Set with arguments for the command, before setting DSU_COMMAND

After reading the value the host must write zero prior to sending the next

command. See Table 64 on page 106

Zeroed when the command is accepted

Set with response arguments before setting DSU_RESPONSE

Set to indicate outcome of a command

When the command is complete, the default debug handler stores the results in the argument registers and sets a success code in the response register.

Default handler commands

There are four default handler commands:

● DSU_PEEK (DSU_COMMAND = 4)

Reads the 32-bit memory location addressed by DSU_ARG1 and returns the data in

DSU_ARG1. The address must be word aligned. If the operation is successful

DSU_RESPONSE is set to DSU_PEEKED (1).

The value 0x7 is written to DSR2 causing an event with reason = 1 to be sent to the host, see DSU to host events on page 111 .

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Any code greater than 4 is interpreted as a DSU_PEEK command.

● DSU_POKE (DSU_COMMAND = 3)

Writes the 32-bit data word in DSU_ARG2 to the memory location addressed by

DSU_ARG1. The address must be word aligned. If the operation is successful

DSU_RESPONSE is set to DSU_POKED (2).

The 0x7 is written to DSR2 causing an event with reason = 1 to be sent to the host, see

DSU to host events on page 111 .

● DSU_CALL_OR_RETURN (DSU_COMMAND = 1)

(3).

The 0x7 is written to DSR2 causing an event with reason = 1 to be sent to the host, see

DSU to host events on page 111 .

The user routine may overwrite the following state without the need to save and restore:

SCR1_REG , SCR2_REG , SCR3_REG

, DSU_BASE_REG (see Table 64

) and branch bit

B0.

● DSU_FLUSH (DSU_COMMAND = 2)

Flushes the address range starting at the value in DSU_ARG1 and ending at the value in DSU_ARG2 from data and instruction caches.

If a command was successful DSU_RESPONSE is set to DSU_FLUSHED (4).

The 0x7 is written to DSR2 causing an event with reason=1 to be sent to the host, see

DSU to host events on page 111 .

Trap handler

●

If a trap occurs while a command is being processed (for example, an invalid address is supplied on a peek or poke ), the core deals with it as follows.

● The operation in progress is completed by loading the PC of the offending bundle, the exception cause number, and the exception address into DSU_ARG1, DSU_ARG2 and

DSU_ARG3 respectively.

DSU_RESPONSE is set to DSU_GOT_EXCEPTION (Code = 5).

As with all exceptions, the SAVED_PC, SAVED_PSW, EXCAUSENO and

EXADDRESS registers are updated when the exception occurred; the debug handler restores the values of these registers upon exit

Context restore

Before exiting the default handler restores any state it has altered.

The context may have been further altered by commands issued.

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Default handler register usage

The DSU registers in Table 64

are defined and used by the default debug handler program.

Table 64.

DSU command registers

DSR number

Designation Comment

DSR3

DSR4-8

DSR9

(1)

DSR10

(1)

DSR11

(1)

DSR12

DSR13

(1)

DSR_USER_DEBUG_

HANDLER

DSU_ARG4-8

DSU_ARG3

DSU_ARG2

DSU_ARG1

DSU_COMMAND

DSU_RESPONSE

Control switches to this address if content is non-zero

Not used in current debug handler

Command argument 3

Command argument 2. Used by DSU_POKE and

DSU_FLUSH

Command argument 1. Used by all DSU commands

Command register. Written by host, cleared by target when command accepted

Response register. Set by target to a completion code, cleared by host before issuing next command

Saves DSU_BASE_REG (R13) DSR14

DSR15

DSR16

DSR17

DSR18

DSR19

DSR20

DSR21

DSR22

DSR23

DSR24

DSR25

DSR26

Context saving

Saves SCR1_REG (R9)

Saves SCR2_REG (R10)

Saves SCR3_REG (R11)

Saves branch bit B0

Saves LINK_REG

(2)

Saves HANDLER_PC

Saves SAVED_SAVED_PSW

Saves SAVED_SAVED_PC

Saves SAVED_PSW

Saves SAVED_PC

Saves EXCAUSENO

Saves EXADDRESS

DSR27-30

DSR31

Unused

Context saving

Unused

Saves DSR1

Argument registers are placed before the command register in the address space so that a command and its arguments can be loaded with a single poke operation.

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14.3.3 User-defined debug handler

●

A user-defined debug handler may be installed to replace the default debug handler. If

DSR3 is non-zero, the core executes the following sequence to jump to the user-defined debug handler.

● SCR1_REG , SCR2_REG , SCR3_REG , DSU_BASE_REG and R63 are saved as shown in

Table 64

Branch bit B0 is saved as shown in Table 64

SCRATCH4 is overwritten

DSUBASE_REG is replaced by the base address of the DSU register block.

A goto operation to the address in DSR3 is executed

There is no facility for reusing the state restoration routine in the default debug handler for completion of a user-defined debug handler.

14.4 Host debug interface

Exchange of information with the host is through an HTI (host target interface) adapter. The

DSU connects to the HTI through a JTAG interface, and the HTI connects to the host using

Ethernet or USB. This is illustrated in Figure 17

All host-target communication is done with peek , poke , peeked, poked, nop, event and event_ack commands sent between the host and the DSU.

Figure 17.

DSU overview

Host

HTI adapter

JTAG

DSU ST200 core

The JTAG interface provides access to the registers within the DSU only, as described in

Section 14.2.2: Shared register bank on page 102 .

Access is made to memory using a software convention with the ST200 CPU as described in

Section 14.3.2: Default debug handler on page 104

event messages can be sent in either direction to allow software on the CPU to synchronize with software on the host.

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14.4.1 Protocol and flow control

40-bit commands are exchanged between the host and the DSU using the JTAG port.

Whenever a command is sent to the DSU by the host, the DSU responds with a response from a previous command, or a nop if no response is pending.

●

A symmetrical protocol is employed where every action request is handshaken. Therefore, the DSU sends the following responses: for a for a peek poke for an

from the host, it sends a

from the host, it sends a event from the host, it sends an event_ack an event_ack from the host does not require a response; the DSU sends a nop if no other response is pending peeked poked

● a nop from the host does not require a response; the DSU sends a response is pending nop if no other

The DSU sends a response to the i th

command, either after the DSU receives the ( i + 1) command (in the initial state), or after it receives the ( i + 2) th

command (in the buffered th state).

In its initial state, the DSU responds to the i th

command when it receives the ( i + 1) th command, and continues to do so until the processor writes to DSR2, sending an event to the host. The sending of the event is prioritized over the sending of a response to the i th command, which is buffered.

In the state where there is a buffered response, DSU responds to the i receives the ( i + 2) th th

command when it

command. When the DSU receives an event_ack or a nop as a ( i + 2) th command, it sends the response to the (j + 1) th

command. Since neither the event_ack nor the nop require a response, the buffer is now empty, so the DSU re-enters the initial state.

As only one event can be outstanding to the host at a given time, the DSU is required to buffer one response only. As responses are not always sent immediately to incoming commands, the host must account for every peek and poke that is sent. The host must also poll the DSU with nops to receive events .

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Commands supported across the JTAG interface are as listed in

Table 65

. Commands are

40 bits long and consist of an 8-bit header and a 32-bit data field. The header is split into two fields. Commands are sent over the JTAG interface bit[0] first.

Table 65.

JTAG commands

Action / comment

Commands from the Host to the DSU nop peek poke event event_ack

0x0

0x1

0x2

0x3

0x4

0x0

Address

0x0

Data reason[10:8] channel[13:11]

0x0[39:14]

DSR2[31:0]

Yes

No action. No command is currently waiting to be sent. nops can be used to poll for event s.

Request to peek the DSU register specified by the address field. The DSU replies with peeked , address , value

(1)

Request to poke a DSU register specified by the address field with the value specified by the data field. The DSU replies with poked , address , 0 .

If reason = 1 and channel = 0 then raise a debug interrupt, otherwise a debug interrupt is not raised. The DSU replies with event_ack , reason , channel ,

0 .

An event from the DSU to the host has been processed. The original word in DSR2 is returned, but is not used.

Reserved commands are treated as nop s.

reserved

(2)

0x5-

0x7

Undefined

Commands from the DSU to the host nop 0x0 0x0

Undefined

0x0 peeked poked

0x1

0x2

Address

Value

0x0

No command is currently waiting to be sent.

Peeked data being returned to the host.

Response to a request to poke a DSU register.

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Table 65.

JTAG commands (continued)

ST231

Action / comment event event_ack reserved

(2)

0x3

0x4

0x5-

0x7

0x0

Undefined

DSR2[31:0] reason[10:8] channel[13:11]

0x0[39:14]

Undefined

Yes

DSR2 [31:0] is copied into the data field, and the use is defined by software. Must be eventually replied to by an event_ack .

An event has been processed

(i.e. a debug interrupt has been applied to the core, it may not have been processed yet). The data field from the incoming command is placed in the data field of the response command.

The behavior is defined by the host software.

The response may be delayed by one message if an event_ack is outstanding, as described in

Section 14.4.1 on page 108 .

Commands marked reserved are held for future development.

This section describes how the DSU handles events.

Host to DSU events

The DSU generates an event_ack in response to an event command. The response indicates that the DSU has signalled a debug interrupt to the processor; it does not indicate that the processor has taken a debug interrupt (for instance, interrupts may have been disabled or the processor may be servicing a cache miss). The host can determine whether the processor is in debug mode by peeking DSR1. Bit 0 is set on entering debug mode and is cleared on exiting.

If the processor has not returned from debug mode, a subsequent event command causes an additional debug interrupt. The controlling software must ensure that events are not sent until previous events have been completely processed.

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DSU to host events

Multiple events can be sent from the host to the DSU, but only one outstanding DSU-to-host event is permitted. Two bits in DSR1 give information about the current DSU-to-host event

status as shown in Table 66

Table 66.

Status of events and DSR1 bit fields

OUTPUT_ PENDING

DSR1[5]

HOST_EVENT_ACK_

PENDING DSR1[4]

Comment

No outstanding DSU to host event .

DSR2 has been written to, event has not been sent yet. Writes to DSR2 before DSR1[4] is set do not cause extra events, but update the value of DSR2 which is sent with the event .

This case does not occur. DSR1[5] and

DSR1[4] are mutually exclusive.

The event has been sent. Writes to DSR2 do not cause further events to be sent.

The event_ack has been received. Writes to

DSR2 cause event again.

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●

The ST231 provides a hardware instrumentation system which consists of the following: a control register ( PM_CR ) a core clock counter ( four event counters (

PM_PCLK

PM_CNT i , i

)

= 0, 1, 2, 3)

They are all mapped to addresses in the control register space as defined in

Section 9.3:

Control register addresses on page 68 .

15.1 Events

The programmable events supported by the ST231 are listed in

Table 67

Table 67.

PM_EVENT values

Name Value

PM_EVENT_DHIT

PM_EVENT_DMISS

PM_EVENT_DMISSCYCLES

PM_EVENT_PFTISSUED

PM_EVENT_PFTHITS

PM_EVENT_WBHITS

PM_EVENT_IHIT

PM_EVENT_IMISS

PM_EVENT_IMISSCYCLES

PM_EVENT_IBUFINVALID

PM_EVENT_BUNDLES

PM_EVENT_LDST

PM_EVENT_TAKENBR

PM_EVENT_NOTTAKENBR

PM_EVENT_EXCEPTIONS

Comment

Number of cached loads and stores that hit the cache.

Number of cached loads and stores that miss the cache. This includes stores that miss the cache and are sent to the write buffer.

Number of cycles the core is stalled waiting for load/store operations to complete (this includes

DTLB and uncached stalls).

Number of prefetches that are sent to the bus.

Number of cached loads that hit the prefetch buffer.

Number of writes that hit the write buffer.

Number of accesses the instruction buffer made that hit the instruction cache.

Number of accesses the instruction buffer made that missed the instruction cache.

Number of cycles the instruction cache was stalled for due to refill from the STBus.

Duration where IBuffer is not able to issue bundles to the pipeline.

Bundles executed.

Load/Store instructions executed. These include: stw, sth, stb, pft, prgadd, prgset, prginspg, pswset, pswclr, sync, ldb, ldb.d, ldbu, ldbu.d, ldh, ldh.d, ldhu, ldhu.d, ldw, ldw.d.

Number of taken branches, includes br, brf, rfi, goto and call.

Number of not taken branches (br and brf).

Number of exceptions and debug interrupts.

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Table 67.

PM_EVENT values (continued)

Name Value Comment

PM_EVENT_INTERRUPTS 15

PM_EVENT_BUSREADS

PM_EVENT_BUSWRITES

PM_EVENT_OPERATIONS

PM_EVENT_WBMISSES

PM_EVENT_NOPBUNDLES

PM_EVENT_LONGIMM

PM_EVENT_ITLBMISS

PM_EVENT_DTLBMISS

PM_EVENT_UTLBHIT

PM_EVENT_ITLBWAITCYCLES

PM_EVENT_DTLBWAITCYCLE

PM_EVENT_UTLB

ARBITRATIONCYCLES

Reserved

28-31

Number of interrupts.

Number of architectural read transactions issued to the bus. This is the number of uncached reads, I &

D cache refills and prefetches issued to the bus.

Number of architectural write transactions issued to the bus. This is the number of write buffer lines evicted and the number of uncached writes issued to the bus.

Number of completed operations. Includes nops in the instruction stream but not those added dynamically. This counter excludes long immediates.

Number of writes that missed the cache and missed the write buffer. This excludes cache line evictions.

Number of completed bundles that were empty or contained only nops. This includes nop bundles generated by instruction buffer stalls and interlocking stalls. It excludes pipeline stalls due to load/stores and control register/SDI accesses.

Number of long immediates in completed bundles.

Number of instruction cache reads that missed the

ITLB.

Number of load/store operations that missed the

DTLB when the TLB is enabled.

Number of accesses to the UTLB which were hits.

Number of cycles the instruction cache spends waiting for the ITLB to fill.

Number of cycles the data cache spends waiting for the DTLB to fill.

Number of cycles where the ITLB or DTLB was waiting for access to the UTLB because the UTLB was busy servicing a request.

Reserved for future use (on the ST230, counting reserved events has no effect, the counter does not increment).

All the events relating to the architectural state of the machine are sampled when bundles commit.

15.2 Access to registers

As all the performance monitoring registers are mapped into the control register space, access is only supported in supervisor mode. An attempt to read or write a register in user mode causes a CREG_ACCESS_VIOLATION exception.

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15.3 Control register (PM_CR)

The program uses this control register to reset and enable all the counters, and define the events of the four programmable count registers. The control register’s bit fields are listed in

Table 68

Note:

Table 68.

PM_CR bit fields

Name Bit(s)

ENB

RST

IDLE

Reserved

EVENT0

EVENT1

EVENT2

EVENT3

[11:3]

[16:12]

[21:17]

[26:22]

[31:27]

Writable

Reset Comment

0x0

0: counting is disabled.

1: counting is enabled.

0x0

When a 1 is written all the counters

(PM_CNT0-3 and PM_PCLK) are set to zero. If a 0 is written it is ignored. This field does not retain its value and so always reads as 0.

When the core enters idle mode, this bit is set to 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the bit.

0x0 Reserved

5-bit field specifying the event being monitored for this counter.

0x0

5-bit field specifying the event being monitored for this counter.

If counting is enable when the PM_CR register is written to any event that is triggered on the same bundle/cycle as the write is ignored. For example, if one of the event counters counts the load/store operations, a store to the PM_CR register is not included in the count.

When the performance monitoring counters are enabled, the core does not enter idle mode,

see Section 2.4.1: Idle mode macro on page 17 .

15.4 Event counters (PM_CNT

)

Each of the four event counters is incremented by one each time the countable event specified in the PM_CR occurs. The four programmable event counters can record any one

of the events specified in Table 67 on page 112

Reading from these registers returns the current event count. Writing changes the current count. If a counter is written at the same time as an event triggers the counter to increment, then the increment is ignored.

If counting is enabled, when the counter is read the value of the counter does not include any event that was triggered on the same bundle/cycle as the read itself. For example, if an event counter was counting load/stores, the load that reads the count is not included in the count (but the event is still counted and will be available next time the counter is read).

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15.5 Clock counter (PM_PCLK)

The PM_PCLK register is read/write. Reading the PM_PCLK register returns a 32-bit value.

Writes to PM_PCLK update its value. This counter silently wraps back to zero when it overflows.

To start recording, write the desired fields to an ST231 general purpose register. This can be achieved by first reading the PM_CR register, then modifying it as appropriate.

The ENB bit needs to be set to 1. The RST bit needs to be set to 1 if the counters are to be reset. The four programmable counter fields (EVENT i (where i = 0 to 3) of the PM_CR register) must be modified to the value representing the events to be counted. See the

Value column in

Table 67: PM_EVENT values on page 112 .

The value in the register is then written to the memory mapped PM_CR for the operation to begin.

To stop recording, read the value of PM_CR , set the ENB bit to zero, and then write back to

PM_CR . Do not change any other bits. If the RST bit is set to 1 then the PM_CNT i registers are reset.

Whilst counting events over a long period of time, the 32-bit counters may overflow. This overflow happens silently and the values wrap around to zero. To obtain a continuous profile, the counters must be read and reset at appropriate regular intervals (the exact interval depends upon the core clock frequency).

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This chapter defines how bundles are executed in terms of their component operations.

In the absence of traps, the core fetches a bundle from memory, decodes the operations within it and reads their operands. It then executes the operations in parallel and writes the results back to the architectural state of the machine. All operations in a bundle commit their results to the state of the machine at the same point in time. This is known as the commit point.

In the presence of traps, the core uses the commit point to distinguish between recoverable and non-recoverable traps.

Traps that are detected prior to the commit point are treated as recoverable. They are recoverable because the machine state has not been updated, which means that the state prior to the execution of the bundle can be recovered. In some cases, the cause of the trap can be corrected and the bundle restarted.

Traps detected after the commit point are unrecoverable. The machine state has been updated and in some cases it may not be clear which bundle caused the trap. Nonrecoverable traps are consequently of a serious nature and cannot be restarted. On the

ST231, the only class of non-recoverable trap is an error in the external memory system, which translates to a bus error exception.

16.1 Bundle fetch, decode, and execute

The fetching, decoding and executing of bundles is specified using an abstract sequential model to show the effects on the architectural state of the machine. In this abstract model, each bundle is executed sequentially with respect to other bundles. This means that all actions associated with one bundle are completed before any actions associated with the next are started.

Specific implementations of the ST231 are generally designed to deliver substantial optimizations on the scheme provided by this abstract model. However, for legal bundle sequences that permit execution latency, these effects are not visible architecturally. The behavior of illegal cases is defined by

Chapter 5: Traps (exceptions and interrupts) on page 25

The execution flow shown in

Figure 18

uses notation defined in Chapter 17: Specification notation on page 119 . There are additional functions that can be used to extract details from

bundles. These are described in Section 16.2: Functions on page 118

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Figure 18.

Execution model

Start

BUNDLE_PC ZeroExtend

(PC);

Yes

Debug interrupt?

Yes

Bus error?

Yes

Data Cache?

Interrupt?

Yes

THROW

STBUS_IC_ERROR

THROW

STBUS_DC_ERROR

Fetch bundle from memory

THROW

EXTERN_INT

NumWords(PC) > 4 Yes

THROW

ILL_INST

NUM_OPERS NumWords(PC) - NumExtImms(PC);

BUNDLE_SIZE NumWords(PC) x 4;

PC Register(BUNDLE_PC + BUNDLE_SIZE);

REPEAT oper FROM 1 FOR NUM_OPERS

Pre-commit(oper);

InitiateDebugIntHandler();

Exception detected?

Yes

REPEAT oper FROM 1 FOR NUM_OPERS

Commit(oper);

InitiateExceptionHandler();

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16.2 Functions

The flow chart in

Figure 18 includes a number of functions that abstract out some the

details. Those functions are described in this section. Starting with those used in the decode phase, then execution of operations, and finally the exceptional cases.

The ST231 uses the functions listed in Table 69

in the bundle decode phase.

Table 69.

Bundle decode functions

Function Description

NumWords(address)

NumExtImms(address)

Returns the number of words in the bundle. The return value is equal to the number of contiguous words, starting from address , without their stop bit set + 1.

Returns the number of extended immediates in the bundle starting at address .

The ST231 uses the functions listed in Table 70

in the operation execution phase.

Table 70.

Operation execution functions

Function Description

Pre-commit(n)

Commit(n)

For the operation n th

operation in the bundle, execute the Pre-commit phase (

Section 18.2 on page 138 )

(1)

For the operation n th

operation in the bundle, execute the Commit phase (

Section 18.2 on page 138 )

(

)

Where n is in the range [1 ... number of operations in the bundle] inclusive.

The ST231 uses the functions listed in Table 71

in exceptional cases.

Table 71.

Operation execution functions

Function Description

InitiateExceptionHandler()

InitiateDebugIntHandler()

Execute the statements defined in Section 5.3: Saved execution state on page 26

Execute the statements defined in Section 13.1.1: Debug interrupts on page 87 .

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●

This chapter describes the formal language used in this manual for describing operations, exceptions and interrupts. The language has the following features: a simple variable and type system, see

Section 17.1

expressions, see statements, see

Section 17.2

Section 17.3

notation for the architectural state of the machine, see

Section 17.4

Additional mechanisms are defined to model memory (

Section 17.5.2

), control registers

(

Section 17.5.3

), and cache instructions (

Section 17.5.4

Chapter 18: Instruction set on page 137 describes each instruction using informal text as

well as the formal language. Occasionally it is not appropriate for one of these descriptions to describe the full semantics of the instruction; in such cases, both descriptions must be taken into account to constitute the full specification. In the case of an ambiguity or conflict, the notational language takes precedence over the text.

Variables are used to hold state. The type of a variable determines the set of values that the variable can take and the operators that can be applied to it. The scalar types are integers, booleans and bit-fields. One-dimensional arrays of scalar types are also supported.

The architectural state of the machine is represented by a set of variables. Each of these variables has an associated type, which is either a bit-field or an array of bit-fields. Bit-fields are used to give a bit-accurate representation of the variables.

The formal language uses additional variables to hold temporary values. The type of a temporary variable is determined by its context rather than explicit declaration. The type of a temporary variable is an integer, a boolean or an array of integers or boolean.

17.1.1 Integer

An integer variable can take the value of any mathematical integer. No limits are imposed on the range of integers supported. Integers obey their standard mathematical properties.

Integer operations do not overflow. The integer operators are defined so that singularities do not occur. For example, no definition is given to the result of divide by zero; the operator is simply not available when the divisor is zero.

●

The representation of literal integer values is achieved using the following notations:

Unsigned decimal numbers are represented by the regular expression: [0-9]+

Signed decimal numbers are represented by the regular expression:

Hexadecimal numbers are represented by the regular expression:

Binary numbers are represented by the regular expression: 0b[0-1]+

-[0-9]+

0x[0-9a-fA-F]+

These notations are standard and map onto integer values in the obvious way. Underscore characters (‘ _ ’) can be inserted into any of the above literal representations. These do not change the represented value but can be used as spacers to aid readability.

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17.1.2 Boolean

A boolean variable can take two values:

●

● boolean false: the literal representation of boolean false is boolean true: the literal representation of boolean true is

FALSE

TRUE

17.1.3 Bit-fields

Bit-fields are provided to define ‘bit-accurate’ storage.

Bit-fields containing arbitrary numbers of bits are supported. A bit-field of b bits contains bits numbered from 0 (the least significant bit) up to b-1 (the most significant bit). Each bit can take the value 0 or the value 1 .

Bit-fields are mapped to, and from, unsigned integers in the usual way. If bit i of a b -bit bitfield, where i is in [0, b) , is set then it contributes 2 i

to the integral value of the bitfield. The integral value of the bit-field as a whole is an integer in the range [0, 2 b

) .

Bit-fields are mapped to, and from, signed integers using two’s complement representation.

This is as above, except that the bit b-1 of a b -bit bitfield contributes -2

(b-1)

to the integral value of the bitfield. The integral value of the bit-field as a whole is an integer in the range

[-2 b-1

, 2 b-1

] .

A bitfield may be used in place of an integer value. In this case the integral value of the bitfield is used. A bit-field variable may be used in place of an integer variable as the target of an assignment. In this case the integer must be in the range of values supported by the bit-field.

17.1.4 Arrays

One-dimensional arrays of the above types are also available. Indexing into an n -element array A is achieved using the notation A[i] where A is an array of some type and i is an integer in the range [0, n) . This selects the i th.

element of the array A . If i is zero this selects the first entry, and if i is n-1 then this selects the last entry. The type of the selected element is the base type of the array.

Multi-dimensional arrays are not provided.

17.2 Expressions

Expressions are constructed from monadic operators, dyadic operators and functions applied to variables and literal values.

There are no defined precedence and associativity rules for the operators. Parentheses are used to specify the expression unambiguously.

Sub-expressions can be evaluated in any order. If a particular evaluation order is required, then sub-expressions must be split into separate statements.

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17.2.1 Integer arithmetic operators

Since the notation uses straightforward mathematical integers, the set of standard mathematical operators is available and already defined.

The standard dyadic operators are listed in

Table 72

Table 72.

Standard dyadic operators

Operation Description i + j i - j i × j i / j

Integer addition

Integer subtraction

Integer multiplication

Integer division* i \ j Integer remainder*

* These operators are defined only for j <> 0

The division operator truncates towards zero. The remainder operator is consistent with this.

The sign of the result of the remainder operator follows the sign of the dividend. Division and remainder are not defined for a divisor of zero.

For a numerator (n) and a denominator (d), the following properties hold where d != 0: n = d X (n/d) + (n\d)

(-n)/d = -(n/d) = n/(-d)

(-n)\d = -(n\d) n\(-d) = n\d

0 <= (n\d) < d where n> = 0 and d> 0

The standard monadic operators are described in

Table 73 .

Table 73.

Standard monadic operators

Operator Description

- i

|i|

Integer negation

Integer modulus (absolute value)

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The available integer shift operators are listed in Table 74

Table 74.

Shift operators

Operation n << b n >> b

Description

Integer left shift

Integer right shift

The shift operators are defined on integers as follows where b >= 0: n « b = n

2 b n » b = n ⁄ 2 b

( n – 2 b

+ 1 ) ⁄ 2 b where where n ≥ 0 n < 0

Right shifting by b places is a division by 2 b

but with the result rounded towards minus infinity. This contrasts with division, which rounds towards zero, and is the reason why the right shift definition is separate for positive and negative n .

17.2.3 Integer bitwise operators

The available integer bitwise operators are listed in

Table 75 .

Table 75.

Bitwise operators

Operation Description i

∧

j i

∨

j i

⊕

~ i

Integer bitwise AND

Integer bitwise OR

Integer bitwise XOR

Integer bitwise NOT n

<b FOR m> n

<b>

Integer bit-field extraction: extract m bits starting at bit b from integer n

Integer bit-field extraction: extract 1 bit starting at bit b from integer n

In order to define bitwise operations all integers are considered as having an infinitely long two’s complement representation. Bit 0 is the least significant bit of this representation, bit 1 is the next higher bit, and so on. The value of bit b, where b >= 0, in integer n is given by:

BIT(n, b) = (n/2 b

)\2 where n >= 0

BIT(n, b) = 1 - BIT((-n - 1), b) where n < 0

Care must be taken whenever the infinitely long two’s complement representation of a negative number is constructed. This representation contains an infinite number of higher bits with the value 1 representing the sign. Typically, a subsequent conversion operation is used to discard these upper bits and return the result back to a finite value.

Bitwise AND ( ∧ ), OR ( ∨ ), XOR ( ⊕ ) and NOT ( ∼ takes all values such that b >= 0:

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Note:

Specification notation

(

∧ j , b ) = ( )

( )

(

∨ j

, b ) = (

∧ j

, b ) + (

⊕ j

, b )

(

⊕ j , b ) =

( BIT i b ) + (

)

) \2

) = 1 – ( )

Bitwise NOT of any finite positive i results in a value containing an infinite number of higher bits with the value 1 representing the sign.

Bitwise extraction is defined on integers as follows, where b ≥ 0 and m > 0 : n

⟨ b FOR m

⟩ n =

= n

⟨

( n » b ) ∧ ( 2 m

– 1 ) b FOR 1

⟩

The result of n

<b FOR m > is an integer in the range [0, 2 m

) .

Relational operators are defined to compare integral values and give a boolean result. See

Table 76

Table 76.

Relational operators

Operation Description i = j i ! = j i < j i > j i <= j i >= j

Result is TRUE if i is equal to j, otherwise FALSE

Result is TRUE if i is not equal to j, otherwise FALSE

Result is TRUE if i is less than j, otherwise FALSE

Result is TRUE if i is greater than j, otherwise FALSE

Result is TRUE if i is less than or equal to j, otherwise FALSE

Result is TRUE if i is greater than or equal to j, otherwise FALSE

Boolean operators are defined to perform logical AND , OR , XOR and NOT . These operators have boolean sources and result. Additionally, the conversion operator INT is

defined to convert a boolean source into an integer result. See Table 77 .

Table 77.

Boolean operators

Operation Description i AND j i OR j i XOR j

NOT i

INT i

Result is TRUE if i and j are both true, otherwise FALSE

Result is TRUE if either/both i and j are true, otherwise FALSE

Result is TRUE if exactly one of i and j are true, otherwise FALSE

Result is TRUE if i is false, otherwise FALSE

Result is 0 if i is false, otherwise 1

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In some cases it is inconvenient or inappropriate to describe an expression directly in the specification language. In these cases a function call is used to reference the undescribed behavior.

A single-value function evaluates to a single value (the result), which can be used in an expression. The type of the result value can be determined by the expression context from which the function is called. There are also multiple-value functions which evaluate to multiple values. These are only available in an assignment context, and are described in

Section 17.3.2: Assignment on page 125 .

Functions may generate side-effects.

Arithmetic functions

Table 78.

Arithmetic functions

Function Description

CountLeadingZeros( i )

Convert integer i to 32-bit bitfield and return the number of leading zeros in the bitfield. For example:

If i

<31>

is 1 then the return value is 0.

If all bits are 0 then the return value is 32 .

Scalar conversions

Two monadic functions are defined to support conversion from integers to bit-limited signed and unsigned number ranges. For a bit-limited integer representation containing n bits, the signed number range is [-2 n-1

, 2 n-1

] while the unsigned number range is [0, 2 n

] .

These functions are often used to convert between signed and unsigned bit-limited integers and between bit-fields and integer values.

Table 79.

Integer conversion operators

Function Description

ZeroExtend n

( i )

SignExtend n

( i )

Convert integer i to an n -bit 2’s complement unsigned range

Convert integer i to an n -bit 2’s complement signed range

These two functions are defined as follows, where n > 0 :

ZeroExtend n i = i

⟨

0 FOR n

⟩

SignExtend n

= i

⟨ i ⟨

0 FOR n

⟩

(

– 1 ) ⟩

– 2 n where i ⟨ n – 1

⟩ = 0 where i

⟨ n – 1 ⟩

= 1

For syntactic convenience, conversion functions are also defined for converting an integer or boolean to a single bit and to a value which can be stored as a 32-bit register.

Table 80

shows the additional functions provided.

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Table 80.

Conversion operators from integers to bit-fields

Operation Description

Bit(i)

If i is a boolean, then this is equivalent to Bit(INT i)

Otherwise, convert lowest bit of integer i to a 1-bit value

This is a convenient notation for i

<0>

If i is a boolean, then this is equivalent to Register(INT i)

Otherwise, convert lowest 32 bits of integer i to an unsigned 32-bit value

This is a convenient notation for i

<0 FOR 32>

17.3 Statements

An instruction specification consists of a sequence of statements. These statements are processed sequentially in order to specify the effect of the instruction on the architectural state of the machine. The available statements are discussed in this section.

Each statement has a semi-colon terminator. A sequence of statements can be aggregated into a statement block using ‘ { ’ to introduce the block and ‘ } ’ to terminate the block. A statement block can be used anywhere that a statement can.

The statement:

UNDEFINED(); indicates that the resultant behavior is architecturally undefined.

A particular implementation can choose to specify an implementation-defined behavior in such cases. It is very likely that any implementation-defined behavior varies from implementation to implementation. Exploitation of implementation-defined behavior should be avoided to allow software to be portable between implementations.

In cases where architecturally undefined behavior can occur in user mode, the implementation ensures that implemented behavior does not break the protection model.

Thus, the implemented behavior is some execution flow that is permitted for that user mode thread.

17.3.2 Assignment

The ‘ ← assignment statement is: variable

←

The expression can be constructed from variables, literals, operators and functions as

described in Section 17.2: Expressions on page 120 . The expression is fully evaluated

before the assignment takes place. The variable can be an integer, a boolean, a bit-field or an array of one of these types.

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Assignment to architectural state

This is where the variable is part of the architectural state, as described in Table 81: Scalar architectural state on page 128 . The type of the expression and the type of the variable must

match, or the type of the variable must be able to represent all possible values of the expression.

Assignment to a temporary

Alternatively, if the variable is not part of the architectural state, then it is a temporary variable. The type of the variable is determined by the type of expression. A temporary variable must be assigned to, before it is used in the instruction specification.

Assignment of an undefined value

An assignment of the following form results in a variable being initialized with an architecturally undefined value: variable

←

After assignment the variable holds a value which is valid for its type. However, the value is architecturally undefined. The actual value can be unpredictable; that is to say the value indicated by UNDEFINED can vary with each use of UNDEFINED. Architecturally-undefined values can occur in both user and privileged modes.

A particular implementation can choose to specify an implementation-defined value in such cases. It is very likely that any implementation-defined values vary from implementation to implementation. If software is intended to be portable between ST231 implementation, then exploitation of implementation-defined values should be avoided.

Assignment of multiple values

Multi-value functions are used to return multiple values, and are only available when used in a multiple assignment context. The syntax consists of a list of comma-separated variables, an assignment symbol followed by a function call. The function is evaluated and returns multiple results into the variables listed. The number of variables and the number of results of the function must match. The assigned variables must all be distinct, that is, no aliases.

For example, a two-valued assignment from a function call with 3 parameters can be represented as: variable1, variable2

←

17.3.3 Conditional

Conditional behavior is specified using IF , ELSE IF and ELSE .

Conditions are expressions that result in a boolean value. If the condition after an IF is true, then its block of statements is executed and the whole conditional is considered complete, ignoring any ELSE IF or ELSE clauses, if they exist. If the condition is false, then each of the ELSE IF clauses are processed, in turn, in the same manner. If no conditions are met and there is an ELSE clause then its block of statements is executed. Finally, if no conditions are met and there is no ELSE clause, then the statement has no effect apart from the evaluation of the condition expressions.

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The ELSE IF and ELSE clauses are optional. In ambiguous cases, the ELSE matches with the preceding IF or ELSE IF .

For example:

IF (condition1) block1

ELSE IF (condition2) block2

ELSE block3

17.3.4 Repetition

Repetitive behavior is specified using the following construct:

REPEAT i FROM m FOR n STEP s block

The block of statements is iterated n times, with the integer i taking the values: m, m + s, m + 2s, m + 3s, up to m + (n - 1) × s .

The behavior is equivalent to textually writing the block n times with i being substituted with the appropriate value in each copy of the block.

The value of n must be greater or equal to 0 , and the value of s must be non-zero. The values of the expressions for m , n and s must be constant across the iteration. The integer i must not be assigned to within the iterated block. The STEP s can be omitted in which case the step-size takes the default value of 1 .

17.3.5 Exceptions

Exception handling is triggered by a THROW statement. When an exception is thrown, no further statements are executed from the operation specification; no architectural state is updated. Furthermore, if any one of the operations in a bundle triggers an exception, none of the operations update the architectural state.

If any operation in a bundle triggers an exception then an exception is taken. The actions associated with the taking of an exception are described in

Section 5.2: Exception handling on page 25

There are two forms of throw statement:

THROW type; and:

THROW type, value; where type indicates the type of exception which is launched, and value is an optional argument to the exception handling sequence. If value is not given, then it is undefined.

The exception types and priorities are described in detail in Chapter 5: Traps (exceptions and interrupts) on page 25

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17.3.6 Procedures

Procedure statements contain a procedure name followed by a list of comma-separated arguments contained within parentheses followed by a semi-colon. The execution of procedures typically causes side-effects to the architectural state of the machine.

Procedures are generally used where it is difficult or inappropriate to specify the effect of an instruction using the abstract execution model. A fuller description of the effect of the instruction is given in the surrounding text.

An example procedure with two parameters is: proc(param1, param2);

Chapter 3: Architectural state on page 19 contains a full description of the visible state. The

notations used in the specification to refer to this state are summarized in

Table 81 and

Table 82

. Each item of scalar architectural state is a bit-field of a particular width. Each item of array architectural state is an array of bit-fields of a particular width.

Table 81.

Scalar architectural state

Architectural state

Type is a bit-field containing:

Description

PSW

SAVED_PC

SAVED_PSW

SAVED_SAVED_PC

SAVED_SAVED_PSW

R I where i is in [0, 63]

32 bits

1 bit

Program counter; address of the current bundle

Program status word

Copy of the PC used during interrupts

Copy of the PSW used during interrupts

Copy of the PC used during debug interrupts

Copy of the PSW used during debug interrupts

64 x 32-bit general purpose registers

R0 reads as zero

Assignments to R0 are ignored

Link register, synonym for R63

8 x 1-bit branch registers

B I where I is in [0, 7]

Table 82.

Array architectural state

Architectural state

Type is an array of bitfields each containing:

Description

CR i where i is index of the control register

32 bits

MEM[i] where i is in [0, 2

] 8 bits

Control registers, for which some specifications refer to individual control registers by their names as defined in the

Chapter 9: Control registers on page 67

bytes of memory

128/331 7645929

ST231 Specification notation

17.5 Memory and control registers

This section describes the formal language defined to model memory ( Section 17.5.2 on page 130

), for control registers (

Section 17.5.3 on page 134

) and cache instructions

(

Section 17.5.3 on page 134

The functions used in the memory and control register descriptions are listed in Table 83

Table 83.

Support functions

Function Description

DataBreakPoint( address )

Misaligned n

( address )

NoTranslation( address )

MultiMapping( address )

Result is TRUE if address is in the range defined by data breakpoint control mechanism

( Section 13.1.2:

Hardware breakpoint support on page 89 ),

otherwise FALSE

Result is TRUE if address is not n -bit aligned, otherwise FALSE

Result is TRUE if the TLB is enabled and has no mapping for address , otherwise FALSE

Results is TRUE if the TLB has more than one mapping for address , otherwise FALSE

Translate(

SCUHit( address paddress )

)

ReadAccessViolation( address

WriteAccessViolation(

IsCRegSpace( address

UndefinedCReg(

CRegIndex( address address )

) address

)

CRegReadAccessViolation(

)

) index )

Looks up address in the TLB and returns the associated physical address

Results is TRUE if the physical address, paddress , hit the SCU, otherwise FALSE

Result is TRUE if the TLB is enabled and a read access to address is not permitted by the TLB, otherwise

FALSE

Result is TRUE if the TLB is enabled and a write access to address is not permitted by the TLB, otherwise

FALSE

Result is TRUE if address is in the control register space, otherwise FALSE

Result is TRUE if address does not correspond to a defined control register, otherwise FALSE

Returns the index of the control register which maps to address

Result is TRUE if read access is not permitted to the given control register, otherwise FALSE

CRegWriteAccessViolation( index )

Result is TRUE if write access is not permitted to given control register, otherwise FALSE

BusReadError(

IsDBreakHit( paddress address )

)

Result is TRUE if reading from physical address, paddress , generates a Bus Error, otherwise FALSE

Result is TRUE if address triggers a data breakpoint, otherwise it is FALSE

7645929 129/331

Specification notation ST231

The instruction specification uses a simple model of memory access which defines the relationship between the content of a logical memory and the values manipulated by instructions. The simple model ignores any caches that may be present; their operation is defined by the text of the architecture manual.

The processor's view of logical memory is defined in terms of an array MEM[i] defined in

Table 82: Array architectural state on page 128 . The mapping between the logical memory

and a physical memory are described in Appendix B: STBus endian behavior on page 320

The notation MEM[s FOR n] is used to denote an 8* n bit bitfield produced from the concatenation of the n elements MEM[s] through MEM[s+i-1] , where i (the byte number) varies in the range [0, n) . The value of MEM[s FOR n] depends on the endianness of the processor.

● If the processor is operating in little endian mode then:

( ] )

⟨

8i FOR 8

⟩ =

[

+ i ]

This equivalence states that byte number i in the bit-field MEM[s FOR n] is the i th.

byte in memory counting upwards from MEM[s] .

If the processor is operating in big endian mode then: ●

( ] )

⟨

8 i FOR 8

⟩ = MEM [ ( s

+

–

1 )

–

i ]

This equivalence states that byte number i , using big endian byte numbering (that is, byte 0 is bits 8n-8 to 8n-1 ), in the bit-field MEM[s FOR n] is the i th.

byte in memory counting downwards from MEM[n] .

For syntactic convenience, functions and procedures are provided to read and write memory.

Support functions

The specification of the memory instructions relies on the support functions listed in

Table 83: Support functions on page 129 . These functions are used to model the behavior of

the TLB described in

Chapter 6: Memory translation and protection on page 31

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ST231 Specification notation

Reading memory

The functions provided to support the reading of memory are listed in Table 84 .

Table 84.

Memory read functions

Function Description

ReadCheckMemory n

( address )

PrefetchCheckMemory( address )

ReadMemory n

( address )

DisReadCheckMemory n

( address )

DisReadMemory n

( address )

ReadMemResponse()

Throws any non-BusError exception generated by an n -bit read from address .

Throws any BusError exceptions generated by a prefetch from address .

Issues an n -bit read to address (can generate BusError exception).

Throws any non-BusError exception generated by an n -bit dismissible read from address .

Returns either n -bits from address or 0 (can generate

BusError exception).

Returns the value of the read request issued.

The ReadCheckMemory n

procedure takes an integer parameter to indicate the address being accessed. The number of bits being read ( n ) is one of 8, 16, or 32. The procedure throws any alignment or access violation exceptions generated by a read access to that address.

ReadCheckMemory n

(a); is equivalent to:

IF (Misaligned n

(a))

THROW MISALIGNED_TRAP, a;

IF (PSW[TLB_ENABLE])

IF (NoTranslation(a) OR

ReadAccessViolation(a))

THROW DTLB, a;

Similarly, if the memory access is a dismissible read:

DisReadCheckMemory n

(a); is equivalent to:

IF (Misaligned n

(a) AND PSW[SPECLOAD_MALIGNTRAP_EN])

THROW MISALIGNED_TRAP, a;

IF (PSW[TLB_ENABLE]) {

IF (MultiMapping(a))

}

THROW DTLB, a;

IF (PSW[TLB_DYNAMIC] AND NoTranslation(a))

THROW DTLB, a;

7645929 131/331

Specification notation ST231

The ReadMemory n

procedure takes an integer parameter to indicate the address being accessed. The number of bits being read ( n ) is one of 8 , 16 , or 32 . The required bytes are read from memory, interpreted according to endianness, and the read bit-field value assigned to a temporary integer. If the read memory value is to be interpreted as signed, then a sign-extension should be used when accessing the result using ReadMemResponse .

The procedure call:

ReadMemory n

(a); is equivalent to: pa = Translate(a); width

←

IF (BusReadError(pa))

THROW BUS_DC_ERROR, a; // Non-recoverable mem_response

←

MEM[pa FOR width];

The DisReadMemory n performs the same functionality for a dismissible read from memory.

The procedure call:

DisReadMemory n

(a); is equivalent to: width

←

IF (NOT Misaligned n

(a) AND

NOT NoTranslation(a) AND

NOT ReadAccessViolation(a) {

pa = Translate(a);

THROW BUS_DC_ERROR, a; // Non-recoverable mem_response

←

MEM[pa FOR width];

}

ELSE mem_response

←

}

ELSE

mem_response

←

The function ReadMemResponse returns the data that has been read from memory. The assignment: result

← is equivalent to: result

←

132/331 7645929

ST231 Specification notation

Prefetching memory

Table 85

describes the procedure that is provided to denote memory prefetch.

Table 85.

Memory prefetch procedure

Function Description

PrefetchMemory( address ) Prefetch memory if possible.

This is used for a software-directed data prefetch from a specified effective address. This is a hint to give advance notice that particular data will be required. PrefetchMemory , performs the implementation-specific prefetch when the address is valid:

PrefetchMemory(a);

This is equivalent to:

IF (NOT NoTranslation(a) AND

NOT MultiMapping(a)

NOT ReadAccessViolation(a)) {

pa = Translate(a);

Prefetch(a);

} where Prefetch

is a cache operation defined in Section 17.5.4: Cache model on page 136

. Prefetching memory does not generate any exceptions.

Writing memory

Table 86

lists the procedures that are provided to write memory.

Table 86.

Memory write procedures

Function Description

WriteCheckMemory n

( address )

Throws any exception generated by an n -bit write to address

WriteMemory n

( address , value ) Aligned n -bit write to memory

The WriteCheckMemory n

procedure takes an integer parameter to indicate the address being accessed. The number of bits being written ( n ) is one of 8 , 16 , or 32 . The procedure throws any alignment or access violation exceptions generated by a write access to that address.

WriteCheckMemory n

(a);

This is equivalent to:

IF (Misaligned n

(a))

THROW MISALIGNED_TRAP, a;

IF (NoTranslation(a) OR

MultiMapping(a) OR

WriteAccessViolation(a))

THROW DTLB, a;

7645929 133/331

Specification notation ST231

The WriteMemory n

procedure takes an integer parameter to indicate the address being accessed, followed by an integer parameter containing the value to be written. The number of bits being written ( n ) is one of 8 , 16 , 32 or 64 bits. The written value is interpreted as a bitfield of the required size; all higher bits of the value are discarded. The bytes are written to memory, ordered according to endianness. The statement:

WriteMemory n

(a, value);

This is equivalent to: pa = Translate(a); width

←

MEM[pa FOR width]

← value

<0 FOR n>

;

17.5.3 Control register model

This section describes the control register model; how control registers are read and written to.

Note:

Reading control registers

The procedures listed in Table 87

are provided to read from control registers.

Only word (32-bit) control register accesses are supported.

Table 87.

Control register read functions

Function Description

ReadCheckCReg( address )

ReadCReg( address )

Throws any exception generated by reading from address in the control register space

Issues a read from the control register mapped to address

The ReadCheckCReg procedure takes an integer parameter to indicate the address being accessed. The procedure throws any alignment or non-mapping exception generated by reading from the control register space.

ReadCheckCReg(a);

This is equivalent to:

IF (UndefinedCReg(a))

THROW CREG_NO_MAPPING, a; index

←

CRegIndex(a);

IF (CRegReadAccessViolation(index))

THROW CREG_ACCESS_VIOLATION, a;

The control register file is denoted CR . The function ReadCReg is provided:

ReadCReg(a);

This is equivalent to: index

←

CRegIndex(a); mem_response

←

CR index

;

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ST231 Specification notation

Writing control registers

The procedures listed in Table 88 are provided to read from control registers. Note that only

word (32-bit) control register accesses are supported.

Table 88.

Control registers write procedures

Function Description

WriteCheckCReg( address )

Throws any exception generated by writing to the address in the control register space

WriteCReg( address , value ) Writes value to the control register mapped to address

The WRITECHECKCREG procedure takes an integer parameter to indicate the address being accessed. The procedure throws any alignment, non-mapping or access violation exceptions generated by writing to the control register space:

WriteCheckCReg(a); is equivalent to:

IF (UndefinedCReg(a))

THROW CREG_NO_MAPPING, a; index

←

CRegIndex(a);

IF (CRegWriteAccessViolation(index))

THROW CREG_ACCESS_VIOLATION, a;

A procedure called WRITECREG is provided to write control registers:

WriteCReg(a, value); is equivalent to: index

←

CRegIndex(a);

CR index

← value;

7645929 135/331

Specification notation ST231

The core uses cache operations to prefetch and purge lines in caches. The effects of these operations are beyond the scope of the specification language, and are therefore modelled

using procedure calls. The behavior of these procedure calls is elaborated in the Chapter 7:

Memory subsystem on page 48 .

Table 89.

Procedures to model cache operations

Procedure Description

PurgeIns()

Sync()

PurgeAddressCheckMemory( address )

PurgeAddress( address )

PurgeSet( address )

Prefetch( address )

PurgeInsPg( address )

Invalidate the entire instruction cache (see

Invalidating the entire instruction cache on page 50 ).

Data memory subsystem synchronization function

(see

Section 7.3.8: D-side synchronization on page 54 ).

Throws any exceptions generated by purging

addresses from the data cache (see Purging data by address on page 54

Purge address from the data cache (see

Purging data by address on page 54

Purge a set of lines from the data cache (see

Purging data by set on page 54 ).

Prefetch a data cache line if it is in cacheable memory

(see

Section 7.3.6: Prefetching data on page 53

Purges the given virtual/physical address combination

8 Kbyte page from the instruction cache (see

Invalidating the instruction cache by page on page 50 ).

17.5.5 Architectural state model

Architectural state such as the PC and PSW is modified by a number of procedures. These also have the effect of flushing the pipeline; this is beyond the scope of the specification language.

Table 90.

Procedures to model changing architectural state

Procedure Description

Rfi()

PswSet( value )

PswClr( value )

Return from interrupt. This flushes the pipeline (see

Section 5.3: Saved execution state on page 26 ).

PSW <- PSW | value . This flushes the pipeline (see

Section 3.4.4: PSW access on page 21

). If value is zero then this flushes out any unexecuted syllables so that the next bundle is guranteed to be fetched from the instruction cache.

PSW <- PSW & (~ value ) . This flushes the pipeline (see

Section 3.4.4: PSW access on page 21

136/331 7645929

ST231 Instruction set

This chapter contains descriptions of all the operations and macros (pseudo-operations) in

the ST231 instruction set. Section 18.1: Bundle encoding has been included in order to

describe how operations are encoded in the context of bundles.

An instruction bundle consists of between one and four consecutive 32-bit words, known as syllables. Each syllable encodes either an operation or an extended immediate. The most significant bit of each syllable (bit 31) is a stop bit which is set to indicate that it is the last in the bundle, as shown in

Figure 19

Figure 19.

Syllable

31 30 29

STOP bit Reserved OPERATION

Many operations have an Immediate form. In general only small (9-bit) immediates can be directly encoded in a single word syllable. In the event that larger immediates are required, an immediate extension is used. This extension is encoded in an adjacent word in the bundle, making the operation effectively a two-word operation.

●

These immediate extensions associate either with the operation to their left or their right in the bundle. Bit 23 is used to indicate the association.

0 indicates left association (word address - 1) ( imml )

1 indicates right association (word address + 1) ( immr )

The semantic descriptions of Immediate form operations use the following function to take into account possible immediate extensions, as shown in

Table 91 .

Table 91.

Extended immediate functions

Function

Imm( i )

Description

Given short immediate value i , returns an integer value that represents the full immediate.

7645929 137/331

Instruction set ST231

This function effectively performs the following:

If there is an immr word to the left (word address - 1) or an imml word to the right

(word address + 1) in the bundle, then Imm returns:

(ZeroExtend23(extension) << 9) + ZeroExtend9(i);

Where extension represents the lower 23 bits of the associated immr or imml .

Otherwise Imm returns:

SignExtend9(i);

●

There are a number of restrictions placed on the encoding of bundles. It is the duty of the assembler to ensure that these restriction are obeyed.

Long immediates must be encoded at even word addresses.

Multiply operations must be encoded at odd word addresses.

There may only be one control flow operation per bundle, and it must be the first syllable.

● There may only be one load or store operation per bundle.

●

The specification of each operation contains the following fields:

● Name: the name of the operation with an optional subscript. The subscript distinguishes between operations with different operand types. For example, integer operations can have either Register or Immediate formats. If no subscript exists for an operation, then there is only one format.

Syntax: presents the assembly syntax of the operation ( ST200 Programming Manual )

●

Encoding: the binary encoding is summarized in a table. It shows which bits are used for the opcode, which bits are reserved (empty fields) and which bit-fields encode the operands. The operands are either register designators or immediate constants.

Semantics: a table containing the statements ( Section 17.3: Statements on page 125

)

that define the operation. The notation used is defined in Chapter 17: Specification notation on page 119 . The table is divided into two parts by the commit point. (See

Chapter 16: Execution model on page 116

●

Pre-commit phase:

●

● No architectural state of the machine is updated.

● Any recoverable exceptions are thrown here.

Commit phase - executed if no exceptions have been thrown:

All architectural state is updated.

Any exceptions thrown here are non-recoverable

(1)

For the ST231 the only non-recoverable exception is a bus error.

Description: a brief textual description of the operation

← Commit point

138/331 7645929

ST231 Instruction set

●

Restrictions: contains any details of restrictions, these may be of the following types:

– Address/bundle: In encoding a bundle with the operation there are a number of possible restrictions which may apply, see

Section 18.1.2

– Latency: certain operands have latency constraints that must be observed

– Destination restrictions: certain operations are not allowed to use the Link Register

(LR) as a destination

Exceptions: if this operation is able to throw any exceptions, they are listed here. The semantics of the operation detail how and when they are thrown

The specification for this operation is shown in

Figure 20

Figure 20.

Example operation

add

Immediate add R

IDEST

= R

SRC1 ,

SRC2 s 00 1 0 00000 isrc2 idest src1

Semantics: operand1 ← SignExtend

SRC1

); operand2 ← SignExtend

(Imm(ISRC2)); result1 ←

IDEST

←

Description: Add

Restrictions: No address or bundle restrictions.

No latency constraints.

Exceptions: None.

The operation is given the subscript Immediate to indicate that one of its source operands is an immediate rather than both being registers.

The next line of the description shows the assembly syntax of the operation.

Just below is the binary encoding table with fields showing:

●

The opcode: Bits 29:21

The operands: An s in bit 31 represents the stop bit (

Section 18.1

)

– The 9-bit immediate constant, bits 20:1

– The destination register designator, bits 11:6

●

– The source register designator, bits 5:0

Unused bits: Bit 30

7645929 139/331

Instruction set ST231

The semantics table specifies the effects of the executing this operation. The table is divided into two parts. The first half containing statements which do not affect the architectural state of the machine. The second half containing statements that will not be executed if an exception occurs in the bundle.

The statements themselves are organized into 3 stages as follows:

The first two statements read the required source information: operand1 <- SignExtend32(RSRC1); operand2 <- Imm(ISRC2);

The first statement reads the value of the R

SRC 1

register, interprets it as a signed 32-bit value and assigns this to a temporary integer called operand1 . The second statement passes the value of ISRC 2 to the immediate handling function Imm

( Section 18.1.1

The result of the function is interpreted as a signed 32-bit value and assigned to a temporary integer called operand2 .

2. The next statement implements the addition: result <- operand1 + operand2;

This statement does not refer to any architectural state. It adds the 2 integers operand1 and operand2 together, and assigns the result to a temporary integer called result . Note that since this is a conventional mathematical addition, the result can contain more significant bits of information than the sources.

3. The final statement, executed if no exceptions have been thrown in the bundle, updates the architectural state:

IDEST

<- Register(result);

The function Register

( Section 17.2.6: Single-value functions on page 124

) converts the integer result back to a bit-field, discarding any redundant higher bits. This value is then assigned to the R

IDEST

After the semantic description is a simple textual description of the operation.

The restrictions section shows that this operation has no restrictions. This means that up to four of these operations can be used in a bundle, and that all operands are ready for use by operations in the next bundle.

Finally, this operation can not generate any exceptions.

140/331 7645929

ST231 Instruction set

18.4 Macros

Table 92

is a list of the currently implemented pseudo-operations or ‘macros’. Each macro is essentially a simplified synonym for another, less intuitive operation.

Table 92.

Macros convbi convib idle mfb mov bsrc mov bdest mov

Int3R mov

Int3I mtb nop return syncins zxtb s 01 1 001 scond slctf R

IDEST

= B

SCOND

, R

, 1 s 00 0 1 1 1100 orl B

BDEST2

= R

SRC1

, R

1 11 0 001 0 goto 0 s 01 1 001 scond slctf R

IDEST

= B

SCOND

, R

, 1 s 01 1 001 scond slctf R

IDEST

= B

SCOND

, R

, 1 s 00 0 1 1 1100 bdest orl B

BDEST

= R

SRC1

, R

0 s 00 0 0 00000

000000001

000000 bdest

11 10 9 8 7 6 5 idest

000000

00000000000000000000000

000000001

000000001 dest idest idest

000000 src2

000000

000000 src1 src1

000000 add R

DEST

= R

, R

SRC2 s 00 1 0 00000 add R

IDEST

= R

, ISRC2 s 00 0 1 1 1100 bdest orl B

BDEST

= R

SRC1

, R

0 s 00 0 0 00000 add R

= R

, R

0 s 11 0 001 1 btarg goto $r63 s 10 10010 pswset R

0 s 00 1 0 01001 and R

IDEST

= R

SRC1

, 255 isrc2

000000

011111111 idest

000000

000000 idest

000000 src1

000000 src1 src1

7645929 141/331

Instruction set ST231

18.5 Operations

Each operation is now specified. They are listed alphabetically for ease of use. The semantics of the operations are written using the notational language defined in

Chapter 17:

Specification notation on page 119 .

add

Register add R

DEST

= R

SRC1 ,

SRC2 s 00 0 0 00000 dest src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Add

No address or bundle restrictions.

No latency constraints.

None.

142/331 7645929

ST231

add

Immediate add R

IDEST

= R

SRC1 ,

SRC2 s 00 1 0 00000 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Add

No address or bundle restrictions.

No latency constraints.

None.

Instruction set idest src1

7645929 143/331

Instruction set

addcg

addcg R

DEST

, B

BDEST

= R

SRC1

, R

SRC2 ,

SCOND s 01 0010 scond bdest dest src2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

SRC2

); operand3 ←

SCOND

); result1

← result2 ←

DEST

←

BDEST

←

Add with carry and generate carry

No address or bundle restrictions.

No latency constraints.

None.

src1

ST231

144/331 7645929

ST231

and

Register and R

DEST

= R

SRC1 ,

SRC2 s 00 0 0 01001 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 ∧ operand2;

DEST

←

Bitwise and

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 145/331

Instruction set

and

Immediate and R

IDEST

= R

SRC1,

ISRC2 s 00 1 0 01001 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 ∧ operand2;

IDEST

←

Bitwise and

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

146/331 7645929

ST231

andc

Register andc R

DEST

= R

SRC1 ,

SRC2 s 00 0 0 01010 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (~operand1) ∧ operand2;

DEST

←

Complement and bitwise and

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 147/331

Instruction set

andc

Immediate andc R

IDEST

= R

SRC1 ,

ISRC2 s 00 1 0 01010 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (~operand1) ∧ operand2;

IDEST

←

Complement and bitwise and

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

148/331 7645929

ST231

andl

Register - Register andl R

DEST

= R

SRC1 ,

SRC2 s 00 0 1 0 1010 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 ! = 0) AND (operand2 ! = 0);

DEST

←

Logical and

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 149/331

Instruction set

andl

Branch Register - Register andl B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 1010 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 ! = 0) AND (operand2 ! = 0);

BDEST

←

Logical and

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

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ST231

andl

Register - Immediate andl R

IDEST

= R

SRC1 ,

ISRC2 s 00 1 1 0 1010 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 ! = 0) AND (operand2 ! = 0);

IDEST

←

Logical and

No address or bundle restrictions.

No latency constraints.

None.

idest

Instruction set src1

7645929 151/331

Instruction set

andl

Branch Register - Immediate andl B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 1010 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 ! = 0) AND (operand2 ! = 0);

IBDEST

←

Logical and

No address or bundle restrictions.

No latency constraints.

None.

ibdest src1

ST231

152/331 7645929

ST231

br

br B

BCOND

, BTARG s 11 1 0 bcond btarg

Semantics: operand1 ←

BCOND

); operand2

←

(BTARG)<< 2;

IF (operand1 ! = 0)

←

(BUNDLE_PC) + operand2);

Instruction set

Description:

Restrictions:

Exceptions:

Branch

Must be the first syllable of a bundle.

There is a latency of 2 bundles between an operation writing B

BCOND

and this operation being issued.

None.

7645929 153/331

Instruction set

break

break s 01 1111111

Semantics:

THROW ILL_INST;

Description:

Restrictions:

Exceptions:

Break

No address or bundle restrictions.

No latency constraints.

ILL_INST

ST231

154/331 7645929

ST231

brf

brf B

BCOND

, BTARG s 11 1 1 bcond btarg

Semantics: operand1 ←

BCOND

); operand2

←

(BTARG)<< 2;

IF (operand1 = 0)

←

(BUNDLE_PC) + operand2);

Instruction set

Description:

Restrictions:

Exceptions:

Branch false

Must be the first syllable of a bundle.

There is a latency of 2 bundles between an operation writing B

BCOND

and this operation being issued.

None.

7645929 155/331

Instruction set

bswap

bswap R

IDEST

= R

SRC1 s 00 1 0 01110 000000010 idest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); byte0

←

operand1

<0 FOR 8>

; byte1 ← operand1

<8 FOR 8>

; byte2

←

operand1

<16 FOR 8>

; byte3 ← operand1

<24 FOR 8>

; result1

←

((byte0 << 24)

∨

(byte1 << 16))

∨

((byte2 << 8)

∨

byte3);

IDEST

←

Byte swap

No address or bundle restrictions.

No latency constraints.

None.

src1

ST231

156/331 7645929

ST231

call

Immediate call $r63 = BTARG s 11 0 000 0 btarg

Semantics: operand1 ←

(BTARG)<< 2;

NEXT_PC

←

PC ←

(BUNDLE_PC) + operand1);

←

Description:

Restrictions:

Exceptions:

Jump and link

Must be the first syllable of a bundle.

No latency constraints.

None.

Instruction set

7645929 157/331

Instruction set

call

Link Register call $r63 = $r63 s 11 0 000 1 00000000000000000000000

Semantics:

NEXT_PC ←

←

(LR));

LR ←

ST231

Description:

Restrictions:

Exceptions:

Jump (using Link Register) and link

Must be the first syllable of a bundle.

There are no latency constraints between an call uprating the LR and this operation.

There is a latency of 4 bundles between a load writing to the LR and this operation.

There is a latency of 2 bundles between any other operation updating the LR and this operation.

None.

158/331 7645929

ST231

clz

clz R

IDEST

= R

SRC1 s 00 1 0 01110 000000100

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); result1

←

IDEST

←

Count leading zeros

No address or bundle restrictions.

No latency constraints.

None.

Instruction set idest src1

7645929 159/331

Instruction set

cmpeq

Register - Register cmpeq R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 0000 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Test for equality

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

160/331 7645929

ST231

cmpeq

Branch Register - Register cmpeq B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 0000 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

BDEST

←

Test for equality

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 161/331

Instruction set

cmpeq

Register - Immediate cmpeq R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 0000 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Test for equality

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

162/331 7645929

ST231

cmpeq

Branch Register - Immediate cmpeq B

IBDEST

= R

SRC1

, I

SRC2 s 00 1 1 1 0000 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IBDEST

←

Test for equality

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 163/331

Instruction set

cmpge

Register - Register cmpge R

DEST

= R

SRC1,

SRC2 s 00 0 1 0 0010 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 ≥ operand2;

DEST

←

Signed compare equal or greater than

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

164/331 7645929

ST231

cmpge

Branch Register - Register cmpge B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 0010 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 ≥ operand2;

BDEST

←

Signed compare equal or greater than

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 165/331

Instruction set

cmpge

Register - Immediate cmpge R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 0010 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 >= operand2;

IDEST

←

Signed compare equal or greater than

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

166/331 7645929

ST231

cmpge

Branch Register - Immediate cmpge B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 0010 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 >= operand2;

IBDEST

←

Signed compare equal or greater than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 167/331

Instruction set

cmpgeu

Register - Register cmpgeu R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 0011 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

SRC2

); result1 ← operand1 >= operand2;

DEST

←

Unsigned compare equal or greater than

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

168/331 7645929

ST231

cmpgeu

Branch Register - Register cmpgeu B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 0011 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 >= operand2;

BDEST

←

Unsigned compare equal or greater than

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 169/331

Instruction set

cmpgeu

Register - Immediate cmpgeu R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 0011 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

(Imm(ISRC2)); result1 ← operand1 >= operand2;

IDEST

←

Unsigned compare equal or greater than

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

170/331 7645929

ST231

cmpgeu

Branch Register - Immediate cmpgeu B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 0011 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 >= operand2;

IBDEST

←

Unsigned compare equal or greater than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 171/331

Instruction set

cmpgt

Register - Register cmpgt R

DEST

= R

SRC1,

SRC2 s 00 0 1 0 0100 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Signed compare greater than

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

172/331 7645929

ST231

cmpgt

Branch Register - Register cmpgt B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 0100 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2 ←

SRC2

); result1 ←

BDEST

←

Signed compare greater than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 173/331

Instruction set

cmpgt

Register - Immediate cmpgt R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 0100 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Signed compare greater than

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

174/331 7645929

ST231

cmpgt

Branch Register - Immediate cmpgt B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 0100 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IBDEST

←

Signed compare greater than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 175/331

Instruction set

cmpgtu

Register - Register cmpgtu R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 0101 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Unsigned compare greater than

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

176/331 7645929

ST231

cmpgtu

Branch Register - Register cmpgtu B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 0101 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

SRC2

); result1 ←

BDEST

←

Unsigned compare greater than

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 177/331

Instruction set

cmpgtu

Register - Immediate cmpgtu R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 0101 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Unsigned compare greater than

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

178/331 7645929

ST231

cmpgtu

Branch Register - Immediate cmpgtu B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 0101 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

(Imm(ISRC2)); result1 ←

IBDEST

←

Unsigned compare greater than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 179/331

Instruction set

cmple

Register - Register cmple R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 0110 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 <= operand2;

DEST

←

Signed compare equal or less than

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

180/331 7645929

ST231

cmple

Branch Register - Register cmple B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 0110 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 <= operand2;

BDEST

←

Signed compare equal or less than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 181/331

Instruction set

cmple

Register - Immediate cmple R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 0110 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 <= operand2;

IDEST

←

Signed compare equal or less than

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

182/331 7645929

ST231

cmple

Branch Register - Immediate cmple B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 0110 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 <= operand2;

IBDEST

←

Signed compare equal or less than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 183/331

Instruction set

cmpleu

Register - Register cmpleu R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 0111 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

SRC2

); result1 ← operand1 <= operand2;

DEST

←

Unsigned compare equal or less than

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

184/331 7645929

ST231

cmpleu

Branch Register - Register cmpleu B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 0111 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

SRC2

); result1 ← operand1 <= operand2;

BDEST

←

Unsigned compare equal or less than

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 185/331

Instruction set

cmpleu

Register - Immediate cmpleu R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 0111 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

(Imm(ISRC2)); result1 ← operand1 <= operand2;

IDEST

←

Unsigned compare equal or less than

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

186/331 7645929

ST231

cmpleu

Branch Register - Immediate cmpleu B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 0111 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 <= operand2;

IBDEST

←

Unsigned compare equal or less than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 187/331

Instruction set

cmplt

Register - Register cmplt R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 1000 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Signed compare less than

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

188/331 7645929

ST231

cmplt

Branch Register - Register cmplt B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 1000 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

BDEST

←

Signed compare less than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 189/331

Instruction set

cmplt

Register - Immediate cmplt R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 1000 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Signed compare less than

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

190/331 7645929

ST231

cmplt

Branch Register - Immediate cmplt B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 1000 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IBDEST

←

Signed compare less than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 191/331

Instruction set

cmpltu

Register - Register cmpltu R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 1001 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Unsigned compare less than

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

192/331 7645929

ST231

cmpltu

Branch Register - Register cmpltu B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 1001 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

BDEST

←

Unsigned compare less than

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 193/331

Instruction set

cmpltu

Register - Immediate cmpltu R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 1001 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Unsigned compare less than

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

194/331 7645929

ST231

cmpltu

Branch Register - Immediate cmpltu B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 1001 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IBDEST

←

Unsigned compare less than

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 195/331

Instruction set

cmpne

Register - Register cmpne R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 0001 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 ! = operand2;

DEST

←

Test for inequality

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

196/331 7645929

ST231

cmpne

Branch Register - Register cmpne B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 0001 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 ! = operand2;

BDEST

←

Test for inequality

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 197/331

Instruction set

cmpne

Register - Immediate cmpne R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 0001 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2 ←

(Imm(ISRC2)); result1 ← operand1 ! = operand2;

IDEST

←

Test for inequality

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

198/331 7645929

ST231

cmpne

Branch Register - Immediate cmpne B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 0001 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 ! = operand2;

IBDEST

←

Test for inequality

No address or bundle restrictions.

No latency constraints.

None.

Instruction set ibdest src1

7645929 199/331

Instruction set

divs

divs R

DEST

, B

BDEST

= R

SRC1

, R

SRC2

, B

SCOND s 01 0100 scond bdest dest src2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); operand3 ←

SCOND

); temp

←

(operand1

∨

(operand3

∧

1);

IF (operand1 < 0)

{ result1 ← result2

←

}

ELSE

{ result1

← result2 ←

}

DEST

←

BDEST

←

Non-restoring divide stage

No address or bundle restrictions.

No latency constraints.

None.

src1

ST231

200/331 7645929

ST231

goto

Immediate goto BTARG s 11 0 001 0 btarg

Semantics: operand1 ←

(BTARG)<< 2;

←

(BUNDLE_PC) + operand1);

Description:

Restrictions:

Exceptions:

Jump

Must be the first syllable of a bundle.

No latency constraints.

None.

Instruction set

7645929 201/331

Instruction set

goto

Link Register goto $r63 s 11 0 001 1 00000000000000000000000

Semantics:

PC ←

(LR));

ST231

Description:

Restrictions:

Exceptions:

Jump (using Link Register)

Must be the first syllable of a bundle.

There are no latency constraints between an call uprating the LR and this operation.

There is a latency of 4 bundles between a load writing to the LR and this operation.

There is a latency of 2 bundles between any other operation updating the LR and this operation.

None.

202/331 7645929

ST231

imml

s imml IMM

01 01010 imm

Semantics: extension ←

(IMM);

Description:

Restrictions:

Exceptions:

Long immediate for previous syllable

Must be encoded at an even word address.

No latency constraints.

None.

Instruction set

7645929 203/331

Instruction set

immr

immr IMM s 01 01011 imm

Semantics: extension ←

(IMM);

Description:

Restrictions:

Exceptions:

Long immediate for next syllable

Must be encoded at an even word address.

No latency constraints.

None.

ST231

204/331 7645929

ST231

ldb

Instruction set ldb R

NLIDEST

= ISRC2[R

SRC1

] s 10 0011 0 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (IsCRegSpace(ea))

THROW CREG_ACCESS_VIOLATION;

ELSE

ReadCheckMemory

(ea);

ReadMemory

(ea); result1 ←

(ReadMemResponse());

NLIDEST

←

Signed load byte

Cannot write the link register ($r63).

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

DBREAK, CREG_ACCESS_VIOLATION, DTLB

7645929 205/331

Instruction set

ldb.d

ldb.d R

NLIDEST

= ISRC2[R

SRC1

] s 10 0011 1 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (NOT (IsCRegSpace(ea)))

DisReadCheckMemory

(ea);

IF (NOT (IsCRegSpace(ea)))

DisReadMemory

(ea);

IF (IsCRegSpace(ea)) result1 ←

ELSE result1 ←

(ReadMemResponse());

NLIDEST

←

Signed load byte dismissable

Cannot write the link register ($r63).

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

DBREAK, DTLB

ST231

206/331 7645929

ST231

ldbu

Instruction set ldbu R

NLIDEST

= ISRC2[R

SRC1

] s 10 0100 0 isrc2 nlidest src1

Semantics:

Description:

Restrictions

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (IsCRegSpace(ea))

THROW CREG_ACCESS_VIOLATION;

ELSE

ReadCheckMemory

(ea);

ReadMemory

(ea); result1 ←

(ReadMemResponse());

NLIDEST

←

Unsigned load byte

Cannot write the link register ($r63).

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

DBREAK, CREG_ACCESS_VIOLATION, DTLB

7645929 207/331

Instruction set

ldbu.d

ldbu.d R

NLIDEST

= ISRC2[R

SRC1

] s 10 0100 1 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (NOT (IsCRegSpace(ea)))

DisReadCheckMemory

(ea);

IF (NOT (IsCRegSpace(ea)))

DisReadMemory

(ea);

IF (IsCRegSpace(ea)) result1 ←

ELSE result1 ←

(ReadMemResponse());

NLIDEST

←

Unsigned load byte dismissable

Cannot write the link register ($r63).

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

DBREAK, DTLB

ST231

208/331 7645929

ST231

ldh

Instruction set ldh R

NLIDEST

= ISRC2[R

SRC1

] s 10 0001 0 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (IsCRegSpace(ea))

THROW CREG_ACCESS_VIOLATION;

ELSE

ReadCheckMemory

(ea);

ReadMemory

(ea); result1 ←

(ReadMemResponse());

NLIDEST

←

Signed load half-word

Cannot write the link register ($r63).

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

DBREAK, CREG_ACCESS_VIOLATION, DTLB, MISALIGNED_TRAP

7645929 209/331

Instruction set

ldh.d

ldh.d R

NLIDEST

= ISRC2[R

SRC1

] s 10 0001 1 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (NOT (IsCRegSpace(ea)))

DisReadCheckMemory

(ea);

IF (NOT (IsCRegSpace(ea)))

DisReadMemory

(ea);

IF (IsCRegSpace(ea)) result1 ←

ELSE result1 ←

(ReadMemResponse());

NLIDEST

←

Signed load half-word dismissable

Cannot write the link register ($r63).

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

DBREAK, DTLB, MISALIGNED_TRAP

ST231

210/331 7645929

ST231

ldhu

Instruction set ldhu R

NLIDEST

= ISRC2[R

SRC1

] s 10 0010 0 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (IsCRegSpace(ea))

THROW CREG_ACCESS_VIOLATION;

ELSE

ReadCheckMemory

(ea);

ReadMemory

(ea); result1 ←

(ReadMemResponse());

NLIDEST

←

Unsigned load half-word

Cannot write the link register ($r63).

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

DBREAK, CREG_ACCESS_VIOLATION, DTLB, MISALIGNED_TRAP

7645929 211/331

Instruction set

ldhu.d

ldhu.d R

NLIDEST

= ISRC2[R

SRC1

] s 10 0010 1 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (NOT (IsCRegSpace(ea)))

DisReadCheckMemory

(ea);

IF (NOT (IsCRegSpace(ea)))

DisReadMemory

(ea);

IF (IsCRegSpace(ea)) result1 ←

ELSE result1 ←

(ReadMemResponse());

NLIDEST

←

Unsigned load half-word dismissable

Cannot write the link register ($r63).

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

DBREAK, DTLB, MISALIGNED_TRAP

ST231

212/331 7645929

ST231

ldw

Instruction set ldw R

IDEST

= ISRC2[R

SRC1

] s 10 0000 0 isrc2 idest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (IsCRegSpace(ea))

ReadCheckCReg(ea);

ELSE

ReadCheckMemory

(ea);

IF (IsCRegSpace(ea))

ReadCReg(ea);

ELSE

ReadMemory

(ea); result1

←

(ReadMemResponse());

IDEST

←

Load word

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

IDEST

is available for reading.

If writing the LR ($r63), there is a latency of 3 bundles before a call LR or goto LR is issued.

DBREAK, DTLB, MISALIGNED_TRAP, CREG_ACCESS_VIOLATION,

CREG_NO_MAPPING

7645929 213/331

Instruction set

ldw.d

ldw.d R

IDEST

= ISRC2[R

SRC1

] s 10 0000 1 isrc2

ST231 idest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (NOT (IsCRegSpace(ea)))

DisReadCheckMemory

(ea);

IF (NOT (IsCRegSpace(ea)))

DisReadMemory

(ea);

IF (IsCRegSpace(ea)) result1 ←

ELSE result1 ←

(ReadMemResponse());

IDEST

←

Load word dismissable

Uses the ld/st unit for which only one operation is allowed per bundle.

There is a latency of 2 bundles before R

IDEST

is available for reading.

If writing the LR ($r63), there is a latency of 3 bundles before a call LR or goto LR is issued.

DBREAK, DTLB, MISALIGNED_TRAP, CREG_ACCESS_VIOLATION,

CREG_NO_MAPPING

214/331 7645929

ST231

max

Register max R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 10000 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

);

IF (operand1 > operand2) result1

←

ELSE result1

←

DEST

←

Signed maximum

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 215/331

Instruction set

max

Immediate max R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 10000 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2));

IF (operand1 > operand2) result1

←

ELSE result1

←

IDEST

←

Signed maximum

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

216/331 7645929

ST231

maxu

Register maxu R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 10001 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

);

IF (operand1 > operand2) result1

←

ELSE result1

←

DEST

←

Unsigned maximum

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 217/331

Instruction set

maxu

Immediate maxu R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 10001 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2));

IF (operand1 > operand2) result1

←

ELSE result1

←

IDEST

←

Unsigned maximum

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

218/331 7645929

ST231

min

Register min R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 10010 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← SignExtend

SRC1

); operand2

←

SignExtend

SRC2

);

IF (operand1 < operand2) result1

←

ELSE result1

←

DEST

←

Signed minimum

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 219/331

Instruction set

min

Immediate min R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 10010 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2));

IF (operand1 < operand2) result1

←

ELSE result1

←

IDEST

←

Signed minimum

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

220/331 7645929

ST231

minu

Register minu R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 10011 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

);

IF (operand1 < operand2) result1

←

ELSE result1

←

DEST

←

Unsigned minimum

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 221/331

Instruction set

minu

Immediate minu R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 10011 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2));

IF (operand1 < operand2) result1

←

ELSE result1

←

IDEST

←

Unsigned minimum

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

222/331 7645929

ST231

mulh

Register mulh R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 10111 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 × (operand2 >> 16);

NLDEST

←

Word by upper-half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 223/331

Instruction set

mulh

Immediate mulh R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 10111 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 × (operand2 >> 16);

NLIDEST

←

Word by upper-half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

224/331 7645929

ST231

mulhh

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 11101 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 >> 16) × (operand2 >> 16);

NLDEST

←

Upper-half-word by upper-half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 225/331

Instruction set

mulhh

Immediate mulhh R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 11101 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 >> 16) × (operand2 >> 16);

NLIDEST

←

Upper-half-word by upper-half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

226/331 7645929

ST231

mulhhs

Register mulhhs R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 10100 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 × (operand2 >> 16)) >> 16;

NLDEST

←

Word by upper-half-word signed multiply, returns top 32 bits of 48 bit result

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 227/331

Instruction set

mulhhs

Immediate mulhhs R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 10100 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 × (operand2 >> 16)) >> 16;

NLIDEST

←

Word by upper-half-word signed multiply, returns top 32 bits of 48 bit result

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

228/331 7645929

ST231

mulhhu

Register mulhhu R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 11110 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

(operand1 >> 16) × ZeroExtend

(operand2 >> 16);

NLDEST

←

Upper-half-word by upper-half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 229/331

Instruction set

mulhhu

Immediate mulhhu R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 11110 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

(operand1 >> 16) × ZeroExtend

(operand2 >> 16);

NLIDEST

←

Upper-half-word by upper-half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

230/331 7645929

ST231

mulhs

Register mulhs R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 11111 nldest

Instruction set src2 src1

Semantics:

Description:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 × ZeroExtend

(operand2 >> 16)) << 16;

NLDEST

←

Restrictions:

Sign extended word by zero extended upper-half-word signed multiply. Result is left shifted 16 places.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 231/331

Instruction set

mulhs

Immediate mulhs R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 11111 isrc2

ST231 nlidest src1

Semantics:

Description:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 × ZeroExtend

(operand2 >> 16)) << 16;

NLIDEST

←

Restrictions:

Sign extended word by zero extended upper-half-word signed multiply. Result is left shifted 16 places.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

232/331 7645929

ST231

mulhu

Register mulhu R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 11000 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 × ZeroExtend

(operand2 >> 16);

NLDEST

←

Word by upper-half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 233/331

Instruction set

mulhu

Immediate mulhu R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 11000 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 × ZeroExtend

(operand2 >> 16);

NLIDEST

←

Word by upper-half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

234/331 7645929

ST231

mull

Register mull R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 10101 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 × operand2;

NLDEST

←

Word by half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 235/331

Instruction set

mull

Immediate mull R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 10101 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 × operand2;

NLIDEST

←

Word by half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

236/331 7645929

ST231

mullh

Register mullh R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 11011 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 × (operand2 >> 16);

NLDEST

←

Half-word by upper-half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 237/331

Instruction set

mullh

Immediate mullh R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 11011 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 × (operand2 >> 16);

NLIDEST

←

Half-word by upper-half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

238/331 7645929

ST231

mullhu

Register mullhu R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 11100 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 × ZeroExtend

(operand2 >> 16);

NLDEST

←

Half-word by upper-half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 239/331

Instruction set

mullhu

Immediate mullhu R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 11100 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 × ZeroExtend

(operand2 >> 16);

NLIDEST

←

Half-word by upper-half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

240/331 7645929

ST231

mullhus

Register mullhus R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 01111 nldest

Instruction set src2 src1

Semantics:

Description:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 × operand2) >> 32;

NLDEST

←

Restrictions:

Sign extended word by zero extended lower-half-word signed multiply. Returns top

16 bits of 48 bit result, sign extended.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 241/331

Instruction set

mullhus

Immediate mullhus R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 01111 isrc2

ST231 nlidest src1

Semantics:

Description:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 × operand2) >> 32;

NLIDEST

←

Restrictions:

Sign extended word by zero extended lower-half-word signed multiply. Returns top

16 bits of 48 bit result, sign extended.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

242/331 7645929

ST231

mulll

Register mulll R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 11001 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 × operand2;

NLDEST

←

Half-word by half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 243/331

Instruction set

mulll

Immediate mulll R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 11001 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 × operand2;

NLIDEST

←

Half-word by half-word signed multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

244/331 7645929

ST231

mulllu

Register mulllu R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 11010 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

SRC2

); result1 ← operand1 × operand2;

NLDEST

←

Half-word by half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 245/331

Instruction set

mulllu

Immediate mulllu R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 11010 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

);

(Imm(ISRC2)); result1 ← operand1 × operand2;

NLIDEST

←

Half-word by half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

246/331 7645929

ST231

mullu

Register mullu R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 0 10110 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 × operand2;

NLDEST

←

Word by half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 247/331

Instruction set

mullu

Immediate mullu R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 0 10110 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 × operand2;

NLIDEST

←

Word by half-word unsigned multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

248/331 7645929

ST231

mul32

Register mul32 R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 1 01110 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 × operand2;

NLDEST

←

32 by 32 multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 249/331

Instruction set

mul32

Immediate mul32 R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 1 01110 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 × operand2;

NLIDEST

←

32 by 32 multiply

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

250/331 7645929

ST231

mul64h

Register mul64h R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 1 01111 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 × operand2) >> 32;

NLDEST

←

32 by 32 signed multiply, return the top 32 bits of the 64 bit result.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 251/331

Instruction set

mul64h

Immediate mul64h R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 1 01111 isrc2 nlidest src1

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 × operand2) >> 32;

NLIDEST

←

32 by 32 signed multiply, return the top 32 bits of the 64 bit result.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

252/331 7645929

ST231

mul64hu

Register mul64hu R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 1 11110 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 × operand2) >> 32;

NLDEST

←

32 by 32 unsigned multiply, return the top 32 bits of the 64 bit result.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 253/331

Instruction set

mul64hu

Immediate mul64hu R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 1 11110 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 × operand2) >> 32;

NLIDEST

←

32 by 32 unsigned multiply, return the top 32 bits of the 64 bit result.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

254/331 7645929

ST231

mulfrac

Register mulfrac R

NLDEST

= R

SRC1

, R

SRC2 s 00 0 1 11111 nldest

Instruction set src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

);

IF (((-operand1) = 0x80000000) AND ((-operand2) = 0x80000000))

{ result1 ←

}

ELSE

{ result1 ← operand1 × operand2; result1

← result1 ←

}

NLDEST

← Register(result1); fractional multiply.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLDEST

is available for reading.

None.

7645929 255/331

Instruction set

mulfrac

Immediate mulfrac R

NLIDEST

= R

SRC1

, ISRC2 s 00 1 1 11111 isrc2 nlidest src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2));

IF (((-operand1) = 0x80000000) AND ((-operand2) = 0x80000000))

{ result1 ←

}

ELSE

{ result1 ← operand1 × operand2; result1

← result1 ←

}

NLIDEST

← fractional multiply.

Cannot write the link register ($r63).

Must be encoded at an odd word address.

There is a latency of 2 bundles before R

NLIDEST

is available for reading.

None.

ST231

256/331 7645929

ST231

nandl

Register - Register nandl R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 1011 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← NOT ((operand1 ≠ 0) AND (operand2 ≠ 0));

DEST

←

Logical nand

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 257/331

Instruction set

nandl

Branch Register - Register nandl B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 1011 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← NOT ((operand1 ≠ 0) AND (operand2 ≠ 0));

BDEST

←

Logical nand

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

258/331 7645929

ST231

nandl

Register - Immediate nandl R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 1011 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← NOT ((operand1 ≠ 0) AND (operand2 ≠ 0));

IDEST

←

Logical nand

No address or bundle restrictions.

No latency constraints.

None.

idest

Instruction set src1

7645929 259/331

Instruction set

nandl

Branch Register - Immediate nandl B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 1011 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← NOT ((operand1 ≠ 0) AND (operand2 ≠ 0));

IBDEST

←

Logical nand

No address or bundle restrictions.

No latency constraints.

None.

ibdest src1

ST231

260/331 7645929

ST231

norl

Register - Register norl R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 1101 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← NOT ((operand1 ≠ 0) OR (operand2 ≠ 0));

DEST

←

Logical nor

No address or bundle restrictions.

No latency constraints.

None.

src2

Instruction set src1

7645929 261/331

Instruction set

norl

Branch Register - Register norl B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 1101 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← NOT ((operand1 ≠ 0) OR (operand2 ≠ 0));

BDEST

←

Logical nor

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

262/331 7645929

ST231

norl

Register - Immediate norl R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 1101 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← NOT ((operand1 ≠ 0) OR (operand2 ≠ 0));

IDEST

←

Logical nor

No address or bundle restrictions.

No latency constraints.

None.

idest

Instruction set src1

7645929 263/331

Instruction set

norl

Branch Register - Immediate norl B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 1101 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← NOT ((operand1 ≠ 0) OR (operand2 ≠ 0));

IBDEST

←

Logical nor

No address or bundle restrictions.

No latency constraints.

None.

ibdest src1

ST231

264/331 7645929

ST231

or

Register or R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 01011 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 ∨ operand2;

DEST

←

Bitwise or

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 265/331

Instruction set

or

Immediate or R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 01011 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 ∨ operand2;

IDEST

←

Bitwise or

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

266/331 7645929

ST231

orc

Register orc R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 01100 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (~operand1) ∨ operand2;

DEST

←

Complement and bitwise or

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 267/331

Instruction set

orc

Immediate orc R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 01100 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (~operand1) ∨ operand2;

IDEST

←

Complement and bitwise or

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

268/331 7645929

ST231

orl

Register - Register orl R

DEST

= R

SRC1

, R

SRC2 s 00 0 1 0 1100 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 ≠ 0) OR (operand2 ≠ 0);

DEST

←

Logical or

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 269/331

Instruction set

orl

Branch Register - Register orl B

BDEST

= R

SRC1

, R

SRC2 s 00 0 1 1 1100 bdest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← (operand1 ≠ 0) OR (operand2 ≠ 0);

BDEST

←

Logical or

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

270/331 7645929

ST231

orl

Register - Immediate orl R

IDEST

= R

SRC1

, ISRC2 s 00 1 1 0 1100 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 ≠ 0) OR (operand2 ≠ 0);

IDEST

←

Logical or

No address or bundle restrictions.

No latency constraints.

None.

Instruction set idest src1

7645929 271/331

Instruction set

orl

Branch Register - Immediate orl B

IBDEST

= R

SRC1

, ISRC2 s 00 1 1 1 1100 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← (operand1 ≠ 0) OR (operand2 ≠ 0);

IBDEST

←

Logical or

No address or bundle restrictions.

No latency constraints.

None.

ibdest src1

ST231

272/331 7645929

ST231

pft

Instruction set pft ISRC2[R

SRC1

] s 10 01101 isrc2 000000 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

PrefetchCheckMemory(ea);

PrefetchMemory(ea);

Prefetch

Uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

None.

7645929 273/331

Instruction set

prgadd

prgadd ISRC2[R

SRC1

] s 10 01110 isrc2 000000 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

PurgeAddressCheckMemory(ea);

PurgeAddress(ea);

Purge the address given from the data cache

Uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

DTLB

ST231

274/331 7645929

ST231

prgins

prgins s 01 1111100

Semantics:

Description:

Restrictions:

Exceptions:

IF (PSW[USER_MODE])

THROW ILL_INST;

PurgeIns();

Purge the instruction cache

Must be in a bundle by itself

No latency constraints.

ILL_INST

Instruction set

7645929 275/331

Instruction set

prginspg

prginspg ISRC2[R

SRC1

] s 10 10001 isrc2 000000 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

);

IF (PSW[USER_MODE])

THROW ILL_INST; ea ←

(operand1 + operand2);

PurgeInsPg(ea);

Purge a 8kb page from the instruction cache

Uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

ILL_INST

ST231

276/331 7645929

ST231

prgset

prgset ISRC2[R

SRC1

] s 10 01111 isrc2

Instruction set

000000 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); ea ←

(operand1 + operand2);

PurgeSet(ea);

Purge a set of four cache lines from the data cache

Uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

None.

7645929 277/331

Instruction set

pswclr

pswclr R

SRC2 s 10 10011

ST231 src2 000000

Semantics:

Description:

Restrictions:

Exceptions: operand2 ←

SRC2

);

IF (PSW[USER_MODE])

THROW ILL_INST;

PswClr(operand2);

Atomic psw clear.

Must be the first in a bundle and uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

ILL_INST

278/331 7645929

ST231

pswset

pswset R

SRC2 s 10 10010

Instruction set src2 000000

Semantics:

Description:

Restrictions:

Exceptions: operand2 ←

SRC2

);

IF (PSW[USER_MODE])

THROW ILL_INST;

PswSet(operand2);

Atomic PSW set.

Must be the first in a bundle and uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

ILL_INST

7645929 279/331

Instruction set

rfi

rfi s 11 0 010 0 00000000000000000000000

ST231

Semantics:

Description:

Restrictions:

Exceptions:

IF (PSW[USER_MODE])

THROW ILL_INST;

PC ←

(SAVED_PC));

PSW

←

SAVED_PC ← SAVED_SAVED_PC;

SAVED_PSW

←

SAVED_SAVED_PSW;

Rfi();

Return from interrupt

Must be the first in a bundle and uses the ld/st unit for which only one operation is allowed per bundle.

Instructions writing SAVED_PC must be followed by 4 bundles before this instruction can be issued.

Instructions writing SAVED_PSW must be followed by 4 bundles before this instruction can be issued.

Instructions writing SAVED_SAVED_PC must be followed by 4 bundles before this instruction can be issued.

Instructions writing SAVED_SAVED_PSW must be followed by 4 bundles before this instruction can be issued.

Instructions writing PSW must be followed by 4 bundles before this instruction can be issued.

ILL_INST

280/331 7645929

ST231

sbrk

sbrk SBRKNUM

1 01 1111101 sbrknum

Semantics: operand1 ←

(SBRKNUM);

THROW SBREAK;

Description:

Restrictions:

Exceptions:

Software breakpoint

No address or bundle restrictions.

No latency constraints.

SBREAK

Instruction set

7645929 281/331

Instruction set

sh1add

Register sh1add R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 00101 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Shift left one and accumulate

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

282/331 7645929

ST231

sh1add

Immediate sh1add R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 00101 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Shift left one and accumulate

No address or bundle restrictions.

No latency constraints.

None.

idest

Instruction set src1

7645929 283/331

Instruction set

sh2add

Register sh2add R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 00110 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Shift left two and accumulate

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

284/331 7645929

ST231

sh2add

Immediate sh2add R

IDEST

= RS

RC1

, ISRC2 s 00 1 0 00110 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Shift left two and accumulate

No address or bundle restrictions.

No latency constraints.

None.

idest

Instruction set src1

7645929 285/331

Instruction set

sh3add

Register sh3add R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 00111 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Shift left three and accumulate

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

286/331 7645929

ST231

sh3add

Immediate sh3add R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 00111 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Shift left three and accumulate

No address or bundle restrictions.

No latency constraints.

None.

idest

Instruction set src1

7645929 287/331

Instruction set

sh4add

Register sh4add R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 01000 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Shift left four and accumulate

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

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ST231

sh4add

Immediate sh4add R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 01000 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Shift left four and accumulate

No address or bundle restrictions.

No latency constraints.

None.

idest

Instruction set src1

7645929 289/331

Instruction set

shl

Register shl R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 00010 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

);

IF (operand2 > 31) result1

←

ELSE result1

←

DEST

←

Shift left

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

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ST231

shl

Immediate shl R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 00010 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2));

IF (operand2 > 31) result1

←

ELSE result1

←

IDEST

←

Shift left

No address or bundle restrictions.

No latency constraints.

None.

Instruction set idest src1

7645929 291/331

Instruction set

shr

Register shr R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 00011 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Arithmetic shift right

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

292/331 7645929

ST231

shr

Immediate shr R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 00011 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Arithmetic shift right

No address or bundle restrictions.

No latency constraints.

None.

Instruction set idest src1

7645929 293/331

Instruction set

shru

Register shru R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 00100 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ← operand2

←

SRC1

SRC2

); result1 ←

);

DEST

←

Logical shift right

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

294/331 7645929

ST231

shru

Immediate shru R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 00100 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Logical shift right

No address or bundle restrictions.

No latency constraints.

None.

Instruction set idest src1

7645929 295/331

Instruction set

slct

Register slct R

DEST

= B

SCOND

, R

SRC1

, R

SRC2 s 01 0 000 scond dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SCOND

); operand2

←

SRC1

); operand3 ←

SRC2

);

IF (operand1

≠

0) result1 ←

ELSE result1 ←

DEST

←

Conditional select

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

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ST231

slct

Immediate slct R

IDEST

= B

SCOND

, R

SRC1

, ISRC2 s 01 1 000 scond isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SCOND

); operand2

←

SRC1

); operand3 ←

(Imm(ISRC2));

IF (operand1

≠

0) result1 ←

ELSE result1 ←

IDEST

←

Conditional select

No address or bundle restrictions.

No latency constraints.

None.

idest

Instruction set src1

7645929 297/331

Instruction set

slctf

Register slctf R

DEST

= B

SCOND

, R

SRC1

, R

SRC2 s 01 0 001 scond dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SCOND

); operand2

←

SRC1

); operand3 ←

SRC2

);

IF (operand1 = 0) result1 ←

ELSE result1 ←

DEST

←

Conditional select

No address or bundle restrictions.

No latency constraints.

None.

src2 src1

ST231

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ST231

slctf

Immediate slctf R

IDEST

= B

SCOND

, R

SRC1

, ISRC2 s 01 1 001 scond isrc2 idest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SCOND

); operand2

←

SRC1

); operand3 ←

(Imm(ISRC2));

IF (operand1 = 0) result1 ←

ELSE result1 ←

IDEST

←

Conditional select

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src1

7645929 299/331

Instruction set

stb

stb ISRC2[R

SRC1

] = R

SRC2 s 10 01100 isrc2 src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); operand3 ←

SRC2

); ea

←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (IsCRegSpace(ea))

THROW CREG_ACCESS_VIOLATION;

WriteCheckMemory

(ea);

WriteMemory

(ea, operand3);

Store byte

Uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

DBREAK, CREG_ACCESS_VIOLATION, DTLB

ST231

300/331 7645929

ST231

sth

Instruction set sth ISRC2[R

SRC1

] = R

SRC2 s 10 01011 isrc2 src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); operand3 ←

SRC2

); ea

←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (IsCRegSpace(ea))

THROW CREG_ACCESS_VIOLATION;

WriteCheckMemory

(ea);

WriteMemory

(ea, operand3);

Store half-word

Uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

DBREAK, CREG_ACCESS_VIOLATION, DTLB, MISALIGNED_TRAP

7645929 301/331

Instruction set

stw

stw ISRC2[R

SRC1

] = R

SRC2 s 10 01010 isrc2 src2 src1

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(Imm(ISRC2)); operand2

←

SRC1

); operand3 ←

SRC2

); ea

←

(operand1 + operand2);

IF (IsDBreakHit(ea))

THROW DBREAK;

IF (IsCRegSpace(ea))

WriteCheckCReg(ea);

ELSE

WriteCheckMemory

(ea);

IF (IsCRegSpace(ea))

WriteCReg(ea, operand3);

ELSE

WriteMemory

(ea, operand3);

Store word

Uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

DBREAK, DTLB, MISALIGNED_TRAP, CREG_ACCESS_VIOLATION,

CREG_NO_MAPPING

ST231

302/331 7645929

ST231

sub

Register sub R

DEST

= R

SRC2

, R

SRC1 s 00 0 0 00001 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ←

DEST

←

Subtract

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 303/331

Instruction set

sub

Immediate sub R

IDEST

= ISRC2, R

SRC1 s 00 1 0 00001 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ←

IDEST

←

Subtract

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

304/331 7645929

ST231

sxtb

sxtb R

IDEST

= R

SRC1 s 00 1 0 01110 000000000

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(R result1

←

SRC1

);

IDEST

←

Sign extend byte

No address or bundle restrictions.

No latency constraints.

None.

Instruction set idest src1

7645929 305/331

Instruction set

sxth

sxth R

IDEST

= R

SRC1 s 00 1 0 01110 000000001

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

(R result1

←

SRC1

);

IDEST

←

Sign extend half

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

306/331 7645929

ST231

sync

sync s 10 10000

Semantics:

000000

Description:

Restrictions:

Exceptions:

Sync();

Ensure synchronization

Uses the ld/st unit for which only one operation is allowed per bundle.

No latency constraints.

None.

Instruction set

000000

7645929 307/331

Instruction set

syscall

syscall SBRKNUM s 01 1111110 sbrknum

Semantics: operand1 ←

(SBRKNUM);

THROW SYSCALL;

Description:

Restrictions:

Exceptions:

System call

Must be in a bundle by itself

No latency constraints.

SYSCALL

ST231

308/331 7645929

ST231

xor

Register xor R

DEST

= R

SRC1

, R

SRC2 s 00 0 0 01101 dest

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

SRC2

); result1 ← operand1 ⊕ operand2;

DEST

←

Bitwise exclusive-or

No address or bundle restrictions.

No latency constraints.

None.

Instruction set src2 src1

7645929 309/331

Instruction set

xor

Immediate xor R

IDEST

= R

SRC1

, ISRC2 s 00 1 0 01101 isrc2

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); operand2

←

(Imm(ISRC2)); result1 ← operand1 ⊕ operand2;

IDEST

←

Bitwise exclusive-or

No address or bundle restrictions.

No latency constraints.

None.

idest src1

ST231

310/331 7645929

ST231

zxth

zxth R

IDEST

= R

SRC1 s 00 1 0 01110 000000011

Semantics:

Description:

Restrictions:

Exceptions: operand1 ←

SRC1

); result1

←

IDEST

←

Zero extend half

No address or bundle restrictions.

No latency constraints.

None.

Instruction set idest src1

7645929 311/331

Instruction encoding

Appendix A Instruction encoding

This appendix describes the ST231 instruction encoding.

ST231

Any bits that are not defined are reserved. These bits must be set to 0.

A.2 Fields

Each instruction encoding is composed of a number of fields representing the operands.

These are listed in

Table 93 .

Table 93.

Operand fields

Operand field Description

BCOND

BDEST

BDEST2

BTARG

DEST

NLDEST

IBDEST

IDEST

NLIDEST

ISRC2

IMM

SCOND

SRC1

SRC2

SBRKNUM

Branch register containing the branch condition.

Destination branch register for register format operations.

Destination branch register.

Branch offset value from PC.

Destination general purpose register for register format operations.

Destination general purpose register for multiply operations ($r63 cannot be used).

Destination branch register for immediate format operations.

Destination general purpose register for immediate format operations.

Destination general purpose register for immediate format multiplies ($r63 cannot be used).

9-bit short immediate value.

23-bit value used to extend a short immediate.

Source branch register used for select condition or carry.

General purpose source register.

21-bit immediate operand for sbrk

312/331 7645929

ST231

A.3 Formats

Table 94.

Formats

Instruction encoding

Int3R

Int3I

Monadic s

Cmp3R_Reg s s s

Cmp3R_Br s

Cmp3I_Reg s

Cmp3I_Br

Imm s s

SelectR

SelectI cgen

SysOp

SBreak

System s s s s s s

Load

Store

Psw

Call

Branch

Mul64R

Mul64I s

AsmR_Reg s

AsmI_Reg s s s s s s s

00 0 0

00 1 0

00 0 1

01 OPC

10 1111

OPC

01110

0 OPC

0 1

1 1

OPC

01 0 OPC

01 1 OPC

01 OPC

1 OPC

0 OPC

1 OPC

IMM

SCOND

111

ISRC2

OPC

BDEST

ISRC2

DEST

ISRC2

BDEST DEST

10 OPC

SBRKNUM

OPC

ISRC2

11 0 OPC LNK BTARG

11 1 OPC BCOND BTARG

00 0 1 OPC

ISRC2 00 1 1

10 1 1

OPC

OPC ISRC2

NLDEST

DEST

SRC2

IDEST

SRC2

SRC1

SRC2

IDEST

SRC1

IBDEST SRC1

SRC2

IDEST

SRC2

SRC1

SRC2

IDEST

SRC2

NLIDEST

SRC2

IDEST

SRC1

7645929 313/331

Instruction encoding ST231

●

Important points to note.

The stop bit indicates the end of bundle and is set in the last syllable of the bundle.

The format bits are used to decode the class of operation. There are four formats:

Integer arithmetic, comparison

●

Specific

Memory immediate extension, selects, extended arithmetic load, store

Control transfer branch, call, rfi, goto

Additional decoding is performed using the most significant instruction bits.

Int3 operations have two base formats, register ( Int3R ) and immediate ( Int3I ). Bit 27 specifies the Int3 format, 0=register format, 1=immediate format. In register format, the operation consists of R

DEST

= R

SRC

SRC 1

Op IMMEDIATE .

Op RSRC2 . Immediate format consists of R

DEST

Cmp3 format is similar to Int3 except it can have as a destination either a general purpose register or a branch register ( BBDEST ). In register format, the target register specifier occupies bits 12 to 17, while the target branch register bits 18 to 20. In immediate format, bits 6 to 11 specify either the target general purpose register or target branch register (bits 6 to 8).

Load operations follow R

DEST

= Mem[ R

SRC 1

+ IMMEDIATE ] semantics, while store s follow Mem[ R

SRC 1

+ IMMEDIATE ] = R

SRC 2

. Thus bits 6 to 11 specify either the target destination register ( R

DEST

) or the second operand source register ( R

SRC 2

), depending on whether the operation is a load or store .

A.4 Opcodes

Table 95.

Instruction encoding add sub shl shr shru sh1add sh2add sh3add sh4add and andc or orc xor mullhus s s s s s s s s s s s s s s s

00 0 0 00000

00 0 0 00001

00 0 0 00010

00 0 0 00011

00 0 0 00100

00 0 0 00101

00 0 0 00110

00 0 0 00111

00 0 0 01000

00 0 0 01001

00 0 0 01010

00 0 0 01011

00 0 0 01100

00 0 0 01101

00 0 0 01111

DEST

NLDEST

SRC2

SRC1

314/331 7645929

ST231

Table 95.

Instruction encoding (continued) cmpne cmpge cmpgeu cmpgt cmpgtu cmple cmpleu cmplt cmpltu andl nandl orl mulh mulhu mulll mulllu mullh mullhu mulhh mulhhu mulhs cmpeq max maxu min minu mulhhs mull mullu norl mul32 mul64h cmpeq cmpne cmpge

00 0 0 10000

00 0 0 10001

00 0 0 10010

00 0 0 10011

00 0 0 10100

00 0 0 10101

00 0 0 10110

00 0 0 10111

00 0 0 11000

00 0 0 11001

00 0 0 11010

00 0 0 11011

00 0 0 11100

00 0 0 11101

00 0 0 11110

00 0 0 11111

00 0 1 0 0000

00 0 1 0 0001

00 0 1 0 0010

00 0 1 0 0011

00 0 1 0 0100

00 0 1 0 0101

00 0 1 0 0110

00 0 1 0 0111

00 0 1 0 1000

00 0 1 0 1001

00 0 1 0 1010

00 0 1 0 1011

00 0 1 0 1100

00 0 1 0 1101

00 0 1 01110

00 0 1 01111

00 0 1 1 0000

00 0 1 1 0001

00 0 1 1 0010 s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s

BDEST

DEST

NLDEST

DEST

NLDEST

DEST

7645929

SRC2

Instruction encoding

315/331

SRC1

00 0 1 1 0011

00 0 1 1 0100

00 0 1 1 0101

00 0 1 1 0110

00 0 1 1 0111

00 0 1 1 1000

00 0 1 1 1001

00 0 1 1 1010

00 0 1 1 1011

00 0 1 1 1100

00 0 1 1 1101

00 0 1 11110

00 0 1 11111

00 1 0 00000

00 1 0 00001

00 1 0 00010

00 1 0 00011

00 1 0 00100

00 1 0 00101

00 1 0 00110

00 1 0 00111

00 1 0 01000

00 1 0 01001

00 1 0 01010

00 1 0 01011

00 1 0 01100

00 1 0 01101

00 1 0 01110

00 1 0 01111

00 1 0 10000

00 1 0 10001 s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s andc or orc xor sxtb sxth shru sh1add sh2add sh3add sh4add and cmpgeu cmpgt cmpgtu cmple cmpleu cmplt cmpltu andl nandl orl norl mul64hu mulfrac add sub shl shr bswap zxth clz mullhus max maxu

Instruction encoding

Table 95.

Instruction encoding (continued)

BDEST

NLDEST

ISRC2

000000000

000000001

000000010

000000011

000000100

ISRC2

316/331 7645929

IDEST

SRC2

IDEST

SRC2

IDEST

NLIDEST

IDEST

SRC1

ST231

Table 95.

Instruction encoding (continued) cmpltu andl nandl orl norl mul32 cmpgeu cmpgt cmpgtu cmple cmpleu cmplt mulll mulllu mullh mullhu mulhh mulhhu mulhs cmpeq cmpne cmpge min minu mulhhs mull mullu mulh mulhu mul64h cmpeq cmpne cmpge cmpgeu cmpgt

ISRC2

00 1 0 10010

00 1 0 10011

00 1 0 10100

00 1 0 10101

00 1 0 10110

00 1 0 10111

00 1 0 11000

00 1 0 11001

00 1 0 11010

00 1 0 11011

00 1 0 11100

00 1 0 11101

00 1 0 11110

00 1 0 11111

00 1 1 0 0000

00 1 1 0 0001

00 1 1 0 0010

00 1 1 0 0011

00 1 1 0 0100

00 1 1 0 0101

00 1 1 0 0110

00 1 1 0 0111

00 1 1 0 1000

00 1 1 0 1001

00 1 1 0 1010

00 1 1 0 1011

00 1 1 0 1100

00 1 1 0 1101

00 1 1 01110

00 1 1 01111

00 1 1 1 0000

00 1 1 1 0001

00 1 1 1 0010

00 1 1 1 0011

00 1 1 1 0100 s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s

7645929

Instruction encoding

IDEST

NLIDEST

IDEST

NLIDEST

IDEST

NLIDEST SRC1

IBDEST SRC1

SRC1

317/331

Instruction encoding

Table 95.

Instruction encoding (continued) ldw ldw.d

ldh ldh.d

ldhu ldhu.d

slct slctf prgins sbrk syscall break ldb ldb.d

ldbu ldbu.d

stw sth cmpgtu cmple cmpleu cmplt cmpltu andl nandl orl norl mul64hu mulfrac slct slctf addcg divs imml immr s s s s s s s s s

1 s s s s s s s s s s s s s s s s s s s s s s s s s

00 1 1 1 0101

00 1 1 1 0110

00 1 1 1 0111

00 1 1 1 1000

00 1 1 1 1001

00 1 1 1 1010

00 1 1 1 1011

ISRC2

00 1 1 1 1100

00 1 1 1 1101

00 1 1 11110

00 1 1 11111

01 0 000

01 0 001

01 0010

01 0100

01 01010

01 01011

1 000

1 001

01 1111100

ISRC2

SCOND

DEST

SCOND BDEST DEST

IMM

SCOND ISRC2

SBRKNUM

01 1111101

01 1111110

01 1111111

10 0000

10 0001

10 0010

ISRC2

10 0011

10 0100

10 01010

10 01011

ISRC2

318/331 7645929

IBDEST SRC1

NLIDEST

IBDEST SRC1

SRC1

SRC2

SRC1

IDEST

SRC1

IDEST

NLIDEST

SRC2

SRC1

ST231

Table 95.

Instruction encoding (continued) s s s s s s s s s s s s s s s goto rfi br brf pswclr call call goto stb pft prgadd prgset sync prginspg pswset

10 01100

10 01101

10 01110

10 01111

10 10000

10 10001

10 10010

ISRC2

10 10011

11 0 000

11 0 001

0 BTARG

1 00000000000000000000000

0 BTARG

11 0 001

11 0 010

1 00000000000000000000000

0 00000000000000000000000

11 1 0 BCOND BTARG

11 1 1 BCOND BTARG

SRC2

000000

SRC2

Instruction encoding

SRC1

000000

SRC1

000000

7645929 319/331

STBus endian behavior

Appendix B STBus endian behavior

ST231

The processor behaves in a different manner depending on whether the ST231 is operating

in big endian or in little endian mode. Section 17.5.2: Memory model on page 130

introduces the notation used in this appendix and defines the processor's operation in terms of a logical view of memory. This appendix describes the mapping between that logical memory and an actual physical memory attached to an STBus.

B.1 Endianness of bytes and half-words within a word based memory

The STBus views memory as being constructed from an array of 32-bit words. The notation

WMEM[i] is used to represent 32-bit words in memory where i varies in the range [0, 2

) , and MEM[s] represents a byte indexed within WMEM[i] .

For a little endian memory system:

MEM[ s ] = WMEM[ s /4]

<8( s \4) FOR 8>

For a big endian memory system:

MEM[ s ] = WMEM[ s /4]

<8(3s \4) FOR 8>

Half-word accesses are made by pairing byte accesses using the equations given above.

Considering two processors of different endianness connected to the same memory system, and representing the logical memory as seen by them as MEM

[i] for the little endian processor and MEM

[i] for the big endian processor:

MEM

[ i ] = MEM

[ i ⊕ 3] and:

WMEM

[ i ] = WMEM

[ i ]

As an example given the word WMEM[i] , which stores the value 0xAABBCCDD. In either endianness the word will read the same, but when read as bytes by a little endian processor:

MEM

[ i ] = 0xDD

MEM

[ i +1] = 0xCC

MEM

[ i +2] = 0xBB

MEM

[ i +3] = 0xAA

When read by a big endian processor:

MEM

[ i ] = 0xAA

MEM

[ i +1] = 0xBB

MEM

[ i +2] = 0xCC

MEM

[ i +3] = 0xDD

320/331 7645929

ST231

B.2

STBus endian behavior

Endianness of 64-bit accesses

The ST231 has a 64-bit STBus initiator port. The data presented to the STBus is determined differently depending upon the endianness mode. The STBus also interprets the information differently.

DMEM[i] refers to a double word in memory where i varies in the range [0, 229). When a little endian processor accesses a word address s:

WMEM

[ s ] = DMEM

[ s /2]

<32( s \2) FOR 32> and for a big-endian processor:

WMEM

[ s ] = WMEM

[ s /2]

<32(1s \2) FOR 32>

For example, if

WMEM[ s ]=0xaaaaaaaa

WMEM[ s +1]=0xbbbbbbbb then the contents of DMEM are:

DMEM

[ s ] = 0xbbbbbbbb_aaaaaaaa

DMEM

[ s ] = 0xaaaaaaa_bbbbbbbb therefore the order of words within the double word has changed.

Systems operating purely in a single mode are straightforward. All accesses as seen by the processor are consistent and behave as would be expected for a processor of that endianness.

Issues can arise where the memory system can be observed in both little-endian and bigendian modes. A correctly implemented system behaves according to the definitions given in this document. To ensure a correct implementation, the following points must be addressed in the system.

● The STBus and all devices with 64-bit target ports must be aware of the endianness of an access.

● Size convertors must be correctly configured for the endianness of the system. The correct operation of any size convertors ensure that 32-bit target ports do not need to be aware of endianness.

●

If a system is NOT properly configured then the following problems may be observed.

● The peripheral registers of the ST231 may appear at the wrong address; bit 2 of the address could be inverted. This can be caused by a size convertor not being aware of endianness.

Pairs of words may be swapped in memory.

Words may be written to the wrong address; bit[2] could be inverted.

7645929 321/331

Glossary

Glossary

ST231

Branch registers The set of eight 1-bit registers that encode the condition for conditional branches and carry bits.

Bundle

Cache set

Commit point

Wide instruction of multiple operations always issued during the same cycle and executed in parallel.

A set of a cache refers to all cache lines which may contain data at a given address. For a direct mapped cache the size of the set is 1, and for an n -way set associative cache the size of the set is n .

The point at which the results of operations are written to the architectural state of the ST231.

Control register

Half-word, word, long word

Level-1 I-cache

One of a set of address mapped registers maintained by the hardware

(or operating system or user). These registers may have side effects and may require supervisor access permissions.

Core The core is the ST231 processor core excluding peripherals.

Dyadic operation An operation on two operands.

General-purpose registers

The set of directly addressed fixed-point registers. ST200 contains one

GR file organized as a bank of 64 32-bit registers. The compiler is responsible for explicitly scheduling data transfers among GRs.

Half-word relates to a 16-bit data item. Word relates to a 32-bit data item. Long word relates to a 64-bit data item.

Long word

LRU

Level-1 instruction cache also referred as the “closest” or “lowest” cache. Similar notations apply to the Level-1 data cache. ST200 supports multiple Level-1 data caches.

See half-word definition.

Least Recently Used. A replacement policy for caches and buffers. An

LRU policy will replace the oldest entry whenever there is insufficient space for a new entry.

Main memory

Misaligned

This is the system-accessible memory, cached.

A memory access is misaligned if the access does not fit the natural alignment width of the word being accessed, and the access is illegal.

Monadic operation An operation on one operand.

Operation An operation is an atomic ST200 action, in general considered roughly equivalent to a typical instruction of a traditional 32-bit RISC machine.

Predication

Round robin

Set

The operation of selectively quashing an operation according to the value of a register (called predicate). One of the simplest forms of predication is a select operation, which is supported in ST200.

A replacement policy for caches and buffers. A round robin policy replaces entries in turn whenever there is insufficient space for a new entry.

See cache set definition.

322/331 7645929

ST231

Speculative

ST231

Superscalar

Syllable

VLIW

Word

Glossary

A speculative operation (also known as “eager”) is an operation executed prior to the resolution of the branch under which the operation would normally execute. Special attention must be paid to speculative memory load operations to handle the possible resulting exceptions.

Speculative memory load operation are sometimes called “dismissible” as any exception deriving from the operation has to be ignored

(“dismissed”) by the system.

The ST231 is the processor core as described in this manual including the associated peripherals. Also see “core” definition.

An architecture with multiple functional units in which instructions are scheduled dynamically by the hardware at run-time.

Encoded component of a bundle that specifies one operation to be executed by the machine functional units. Syllables are composed of register and/or immediate fields and opcode specifiers. A bundle in

ST200 may contain multiple syllables, each of them 32-bit wide.

Very long instruction word: instructions (called “bundles” in ST200 terminology) potentially encode multiple, independent operations, and are fully scheduled at compile time.

See half-word definition.

7645929 323/331

ST231

List of instructions

Immediate

Immediate

Immediate

Branch Register - Immediate

andl

Branch Register - Register

Branch Register - Immediate

cmpeq

Branch Register - Register

cmpeq

cmpge

Branch Register - Immediate

cmpge

Branch Register - Register

cmpge

cmpgeu

Branch Register - Immediate

cmpgeu

Branch Register - Register

cmpgeu

cmpgt

Branch Register - Immediate

cmpgt

Branch Register - Register

cmpgt

cmpgtu

Branch Register - Immediate

cmpgtu

Branch Register - Register

cmpgtu

cmple

Branch Register - Immediate

cmple

Branch Register - Register

cmple

cmpleu

Branch Register - Immediate

cmpleu

Branch Register - Register

cmpleu

cmplt

Branch Register - Immediate

cmplt

Branch Register - Register

List of instructions

139

143

142

144

146

145

148

147

152

150

151

149

157

158

159

187

185

186

184

191

189

179

177

178

176

183

181

182

180

171

169

170

168

175

173

174

172

163

161

162

160

167

165

166

164

cmplt

cmpltu

Branch Register - Immediate

cmpltu

Branch Register - Register

cmpltu

cmpne

Branch Register - Immediate

cmpne

Branch Register - Register

Immediate

Immediate

Immediate

7645929

201

202

250

249

252

251

254

253

256

255

216

215

218

217

220

219

222

221

224

223

226

225

228

227

230

229

190

188

195

193

194

192

199

197

198

196

200

324/331

List of instructions

Immediate

Immediate

Immediate

Branch Register - Immediate

nandl

Branch Register - Register

nandl

norl

Branch Register - Immediate

norl

Branch Register - Register

Immediate

Branch Register - Immediate

orl

Branch Register - Register

Immediate

Immediate

Immediate

Immediate

Immediate

325/331

263

261

266

265

268

267

272

270

271

248

247

260

258

259

257

264

262

240

239

242

241

244

243

246

245

232

231

234

233

236

235

238

237

269

283

282

285

284

287

286

289

288

291

Immediate

Immediate

Immediate

7645929

ST231

304

303

310

309

311

290

293

292

295

294

297

296

299

298

300

301

302

Revision history

Revision history

ST231

Table 96.

Document revision history

Date Revision

07-Sep-2009

03-Mar-2009

26-Jun-2008

12-Sep-2007

28-Mar-2007

30-Jan-2007

Changes

Chapter 14: Debugging support (JTAG)

made the following changes:

–

Table 61 on page 102

updated HOST_EVENT_ACK_PENDING

–

Section 14.3.2: Default debug handler reworded section Command loop on page 104 and Table 63 and in section Default handler commands on page 104

, changed “TAPLINK_EVENT_DEFAULT event” to “value 0x7 ” throughout.

–

Table 65 on page 109

updated event command (sent from host)

Made a number of changes throughout the manual to bring this manual in line with the layout of the ST240 core and instruction set reference manual (ADCS 8059133).

Updated

Section 7.3.5: Uncached load and stores on page 53 .

Updated

Chapter 12: Interrupt controller on page 80 .

Updated

Section 18.4: Macros on page 141 .

Corrected minor errors throughout.

Added

List of instructions on page 324

Updated the preface to reflect the current documentation suite.

No technical changes.

Miscellaneous updates to:

Chapter 6: Memory translation and protection on page 31

Chapter 5: Traps (exceptions and interrupts) on page 25

Chapter 9: Control registers on page 67

Chapter 14: Debugging support (JTAG) on page 98

Chapter 17: Specification notation on page 119

Chapter 18: Instruction set on page 137

Update into new corporate template.

326/331 7645929

ST231

Index

Index

A add

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

address space

. . . . . . . . . . . . . . . . . . . . . . . . .32

AND

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

architecture

. . . . . . . . . . . . . . . . . . . . . . . . . .323

Arrays

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Backus-Naur Form

. . . . . . . . . . . . . . . . . . . . . .11

Bit-fields

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

BNF. See Backus-Naur Form.

Boolean

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Boolean operators

. . . . . . . . . . . . . . . . . . . . .123

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

branch

. . . . . . . . . . . . . . . . . . . . . . . . . . .29

, 323

breakpoint registers

. . . . . . . . . . . . . . . . . . . . .67

brf

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

bundle

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

Bundle decode

. . . . . . . . . . . . . . . . . . . . . . . .118

bus errors

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

bypassing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

C cache

. . . . . . . . . . . . . . . . . . . . . . . . . . . .33

, 322

Cache set

. . . . . . . . . . . . . . . . . . . . . . . . . . . .322

call

. . . . . . . . . . . . . . . . . . . . . . . . 17 ,

19 ,

24 ,

carry

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

CMC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Commit point

. . . . . . . . . . . . . . . . 116

, 138

, 322

compiler

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

conditional

. . . . . . . . . . . . . . . . . . . . . . . . . . .322

control registers

. . . . . . . . . . . . . . . . . . . . . . . .68

Control transfer

. . . . . . . . . . . . . . . . . . . . . . .314

Core

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

core memory controller

. . . . . . . . . . . . . . .48

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

CREG_ACCESS_VIOLATION

. . . . . . . . . . . . .67

CREG_NO_MAPPING

. . . . . . . . . . . . . . . . . . .67

Data cache

. . . . . . . . . . . . . . . . . . . . . . . . .34

DBREAK_CONTROL

. . . . . . . . . . . . . . . . .89

DBREAK_LOWER

. . . . . . . . . . . . . . . . . . .89

DBREAK_UPPER

. . . . . . . . . . . . . . . . . . .89

debug interrupt

. . . . . . . . . . . . . . . . . . . . . . 17

debug ROM (JTAG)

. . . . . . . . . . . . . . . . . . . 103

debug ROM (TAPLink)

. . . . . . . . . . . . . . . . . . 93

debug support unit

. . . . . . . . . . . . . . . . . . . . . . 90

debug support unit (JTAG)

. . . . . . . . . . . . . . 101

DEBUG_ENABLE

. . . . . . . . . . . . . . . . . . 93 ,

103

DEBUG_INTERRUPT

. . . . . . . . . . . . . . . 91 ,

101

DEBUG_INTERRUPT_TAKEN

. . . . . . . . 91 ,

101

DEBUG_MODE

. . . . . . . . . . . . . . . . . . . . . 88

, 99

decode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

dismissible

. . . . . . . . . . . . . . . . . . . . . . . . . . . 323

dismissible loads

. . . . . . . . . . . . . . . . . 16

, 29

, 67

DSR0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ,

102

DSR1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ,

102

DSR2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ,

103

DSU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ,

101

DSU control registers (JTAG)

. . . . . . . . . . . . 102

output register

. . . . . . . . . . . . . . . . . . . . . . 103

status register

. . . . . . . . . . . . . . . . . . . . . . . 102

version register

. . . . . . . . . . . . . . . . . . . . . . 102

DSU control registers (TAPLink)

. . . . . . . . . . . 91

output register

. . . . . . . . . . . . . . . . . . . . . . . 92

status register

. . . . . . . . . . . . . . . . . . . . . . . . 91

version register

. . . . . . . . . . . . . . . . . . . . . . . 91

DSU_CALL_OR_RETURN

DSU_FLUSH

. . . . . . . . . . . . . . . . 87

, 94 ,

98 ,

105

DSU_PEEK

. . . . . . . . . . . . . . . . . 87

, 94 ,

98 ,

104

DSU_POKE

. . . . . . . . . . . . . . . . . 87

, 94 ,

98 ,

105

DTLB

. . . . . . . . . . . . . . . . . . . . . . . . . . 31

, 34

, 54

Dyadic operation

. . . . . . . . . . . . . . . . . . . . . . 322

DYNAMIC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

ELSE

. . . . . . . . . . . . . . . . . . . . . . . . . . . 126

127

encoding

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

event

. . . . . . . . . . . . . . . . . . . . . . . . . 87 ,

98 ,

107

EXADDRESS

. . . . . . . . . . . . . . . . . . . . . . . . . 26

EXCAUSE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EXCAUSENO

. . . . . . . . . . . . . . . . . . . . . . 28

, 65

ExceptAddress

. . . . . . . . . . . . . . . . . . . . . . . . 26

exception

. . . . . . . . . . . . . . . . . . . . . . 25 ,

29 ,

323

exception registers

. . . . . . . . . . . . . . . . . . . . . 67

execute

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

execution pipeline

. . . . . . . . . . . . . . . . . . . . . . 22

expressions

. . . . . . . . . . . . . . . . . . . . . . 119

120

extended immediates

. . . . . . . . . . . . . . . . . . 137

EXTERN_INT

. . . . . . . . . . . . . . . . . . . . . . 25

, 27

external interrupt

. . . . . . . . . . . . . . . . . . . . . . . 18

7645929 327/331

Index ST231

F fetch

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Fields

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312

flush

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

FOR

FROM

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Function

Bit(i)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

BusReadError(address)

. . . . . . . . . . . . . . .129

Commit(n)

. . . . . . . . . . . . . . . . . . . . . . . . . .118

ControlRegister(address)

. . . . . . . . . . . . . .129

CregReadAccessViolation(index)

. . . . . . . .129

CregWriteAccessViolation(index)

. . . . . . . .129

DataBreakPoint(address)

. . . . . . . . . . . . . .129

DisReadCheckMemory(address)

. . . . . . . .131

DisReadMemory(address)

. . . . . . . . . . . . .131

DPUNoTranslation(address)

. . . . . . . . . . . .129

Imm(i)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

InitiateDebugIntHandler()

. . . . . . . . . . . . . .118

InitiateExceptionHandler()

. . . . . . . . . . . . . .118

IsControlSpace(address)

. . . . . . . . . . . . . .129

IsDBreakHit(address)

. . . . . . . . . . . . . . . . .129

Misaligned(address)

. . . . . . . . . . . . . . . . . .129

NumExtImms(address)

. . . . . . . . . . . . . . . .118

NumWords(address)

. . . . . . . . . . . . . . . . . .118

Pre-commit(n)

. . . . . . . . . . . . . . . . . . . . . . .118

Prefetch(address)

. . . . . . . . . . . . . . . . . . . .136

PrefetchMemory(address)

. . . . . . . . . . . . . .133

PurgeAddress(address)

. . . . . . . . . . . . . . .136

PurgeIns( )

. . . . . . . . . . . . . . . . . . . . . . . . .136

PurgeSet(address)

. . . . . . . . . . . . . . . . . . .136

ReadAccessViolation(address)

. . . . . . . . . .129

ReadCheckControl(address)

. . . . . . . . . . . .134

ReadCheckMemory(address)

. . . . . . . . . . .131

ReadControl(address)

. . . . . . . . . . . . . . . . .134

ReadMemory(address)

. . . . . . . . . . . . . . . .131

. . . . . . . . . . . . . . . . . . . . . . . . . .125

SignExtend(i)

. . . . . . . . . . . . . . . . . . . . . . . .124

Sync( )

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

UndefinedControlRegister(address)

. . . . . .129

WriteAccessViolation(address)

. . . . . . . . . .129

WriteCheckControl(address)

. . . . . . . . . . . .135

WriteCheckMemory(address)

. . . . . . . . . . .133

WriteControl(address, value)

. . . . . . . . . . .135

WriteMemory(address, value)

. . . . . . . . . . .133

ZeroExtend(i)

. . . . . . . . . . . . . . . . . . . . . . .124

G goto

. . . . . . . . . . . . . . . . . . . . . . . . . 17

, 314

Half word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

HANDLER_PC

. . . . . . . . . . . . . . . . . . . . . . . . 25

HighestPriority

. . . . . . . . . . . . . . . . . . . . . . . . . 26

Host debug interface

. . . . . . . . . . . . . . . . . . . 107

host debug interface

. . . . . . . . . . . . . . . . . . . . 96

host target interface

. . . . . . . . . . . . . . . . . 96 ,

107

HTI

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

, 98

IBREAK_CONTROL

. . . . . . . . . . . . . . . . . 89

, 99

IBREAK_LOWER

. . . . . . . . . . . . . . . . . . . 89

, 99

IBREAK_UPPER

. . . . . . . . . . . . . . . . . . . . 89

, 99

idle

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

. . . . . . . . . . . . . . . . . . . . . . . . . . 126

127 ,

132

illegal bundle

. . . . . . . . . . . . . . . . . . . . . . . . . . 29

illegal instruction exception

. . . . . . . . . . . . . . . 29

Imm

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Immediate

. . . . . . . . . . . . . . . . . . . . . . . 137

138

immediate

. . . . . . . . . . . . . . . . . . . . . . . . . . . 323

imml

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

immr

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

instruction

. . . . . . . . . . . . . . . . . . . . . . . . . . . 322

instruction buffer

. . . . . . . . . . . . . . . . . . . . . . . 49

instruction cache

. . . . . . . . . . . . . . . . . . . . 33

, 50

INT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Int3I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Int3R

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

INTCLR

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

INTCLR0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

INTCLR1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

integer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Integer arithmetic operators

. . . . . . . . . . . . . 121

Integer bitwise operators

. . . . . . . . . . . . . . . . 122

Integer shift operators

. . . . . . . . . . . . . . . . . . 122

integer variable

. . . . . . . . . . . . . . . . . . . . . . . 119

interrupt

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

interrupt clear register

. . . . . . . . . . . . . . . . . . . 84

interrupt controller

. . . . . . . . . . . . . . . . . . . . . . 80

interrupt mask clear register

. . . . . . . . . . . . . . 82

Interrupt mask register

. . . . . . . . . . . . . . . . . . 82

interrupt mask set register

. . . . . . . . . . . . . . . . 82

interrupt pending register

. . . . . . . . . . . . . . . . 81

interrupt set register

. . . . . . . . . . . . . . . . . . . . 84

interrupt test register

. . . . . . . . . . . . . . . . . . . . 84

interrupts

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

INTMASK0

. . . . . . . . . . . . . . . . . . . . . . . . . . . 82

INTMASK1

. . . . . . . . . . . . . . . . . . . . . . . . . . . 82

INTMASKCLR

. . . . . . . . . . . . . . . . . . . . . . . . . 82

INTMASKCLR0

. . . . . . . . . . . . . . . . . . . . . . . . 83

INTMASKCLR1

. . . . . . . . . . . . . . . . . . . . . . . . 83

328/331 7645929

ST231 Index

INTMASKSET

. . . . . . . . . . . . . . . . . . . . . . . . .82

INTMASKSET0

. . . . . . . . . . . . . . . . . . . . . . . .83

INTMASKSET1

. . . . . . . . . . . . . . . . . . . . . . . .84

INTPENDING0

. . . . . . . . . . . . . . . . . . . . . . . . .81

INTPENDING1

. . . . . . . . . . . . . . . . . . . . . . . . .81

INTSET

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

INTSET0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

INTSET1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

INTTEST

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

INTTEST0

. . . . . . . . . . . . . . . . . . . . . . . . . . . .84

INTTEST1

. . . . . . . . . . . . . . . . . . . . . . . . . . . .84

ITLB

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

L ldb

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

ldh

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

ldw

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Least recently used

. . . . . . . . . . . . . . . . . . . .322

legal bundle

. . . . . . . . . . . . . . . . . . . . . . . . . . .29

LFSR

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

LIMIT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Link register

. . . . . . . . . . . . . . . . . . . . . . . . . . .19

load

load/store

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

load/store unit

. . . . . . . . . . . . . . . . . . . 15 ,

29 ,

loads

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

long immediates

. . . . . . . . . . . . . . . . . . . . . . .138

Long word

. . . . . . . . . . . . . . . . . . . . . . . . . . .322

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

LRU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

MEM

. . . . . . . . . . . . . . . . . . . 128 ,

130

, 132

, 134

memory

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

Misaligned

. . . . . . . . . . . . . . . . . . . . . . . . . . .322

Monadic operation

. . . . . . . . . . . . . . . . . . . . .322

mov

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

mul

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

mullhu

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

multiply

. . . . . . . . . . . . . . . . . . . . . . . . . . . .22

multiply operations

. . . . . . . . . . . . . . . . . . . . .138

multiply units

. . . . . . . . . . . . . . . . . . . . . . . . . .15

NO_MAPPING

. . . . . . . . . . . . . . . . . . . . . . . . .54

nops

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

NOT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Opcodes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

operation execution

. . . . . . . . . . . . . . . . . 25 ,

118

operation latencies

. . . . . . . . . . . . . . . . . . . . . 22

operations

. . . . . . . . . . . . . . . . . . . . . . . 322

323

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

P parallel

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

PARTITION

. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ,

128

peek

. . . . . . . . . . . . . . . . . . . . . . . . . . 87 ,

98 ,

107

peeked

. . . . . . . . . . . . . . . . . . . . . . . . 87 ,

98 ,

107

PERIPHERAL_BASE

. . . . . . . . . . . . . . . . . . . 76

pft

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

, 60

physical addresses

. . . . . . . . . . . . . . . . . . . . . 32

PM_CNTi

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

PM_CR

. . . . . . . . . . . . . . . . . . . . . . . . . . 17 ,

114

poke

. . . . . . . . . . . . . . . . . . . . . . . . . . 87 ,

98 ,

107

POLICY

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

prefetch

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

prgadd

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

, 59

prgins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

, 59

prginspg

. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

, 59

prgset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

, 59

Program counter

. . . . . . . . . . . . . . . . . . . . . . . 19

PROT_SUPER

. . . . . . . . . . . . . . . . . . . . . . . . 37

PROT_USER

. . . . . . . . . . . . . . . . . . . . . . . . . 37

PROT_VIOLATION

. . . . . . . . . . . . . . . . . . . . . 52

PSW

psw

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

pswclr

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

pswset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

R63

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

. . . . . . . . . . . . . . . . . . . . . . . . . 322

323

Relational operators

. . . . . . . . . . . . . . . . . . . 123

REPEAT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

REPLACE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

RESETACK

. . . . . . . . . . . . . . . . . . . . . . . . . . . 66

RESETREQUEST

. . . . . . . . . . . . . . . . . . . . . . 66

return

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

return from interrupt

. . . . . . . . . . . . . . . . . . . . . 27

rfi

. . . . . . . . . . . . . . . . . . . . . . . . . . 21

, 27

, 29

Round robin

. . . . . . . . . . . . . . . . . . . . . . . . . . 322

7645929 329/331

Index ST231

SAVED_PC

. . . . . . . . . . . . . . . . . . . . . . .21

, 128

SAVED_PSW

. . . . . . . . . . . . . . . . . . . . . .21

, 128

SAVED_SAVED_PC

. . . . . . . . . . . . . . . . . . .128

SAVED_SAVED_PSW

. . . . . . . . . . . . . . . . . .128

sbrk

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

SCU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

SCU_BASEx

. . . . . . . . . . . . . . . . . . . . . . . . . .47

SCU_LIMITx

. . . . . . . . . . . . . . . . . . . . . . . . . . .47

SDI

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

SDI interface

. . . . . . . . . . . . . . . . . . . . . . . . . .62

SDI ports

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

SDI_CONTROL_PRIV

. . . . . . . . . . . . . . . . . . .64

SDIi_CONTROL

. . . . . . . . . . . . . . . . . . . . . 63

SDIi_COUNT

. . . . . . . . . . . . . . . . . . . . . . . 63

SDIi_DATA

. . . . . . . . . . . . . . . . . . . . . . . . . 63

SDIi_READY

. . . . . . . . . . . . . . . . . . . . . . . 63

SDIi_TIMEOUT

. . . . . . . . . . . . . . . . . . . . . 63

select

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

semantics

. . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Set

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

single-value functions

. . . . . . . . . . . . . . . . . . .124

SIZE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

SLR

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

specific

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

SPECLOAD_MALIGNTRAP_EN

. . . . . . . . . . .30

speculation

. . . . . . . . . . . . . . . . . . . . . . . . . . .323

speculative link register

. . . . . . . . . . . . . . . . . .24

speculative loads

. . . . . . . . . . . . . . . . . . . . . . .52

ST231

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

STATE1 register

. . . . . . . . . . . . . . . . . . . . . . . .71

statements

. . . . . . . . . . . . . . . . . . . . . . .119

, 125

STATUS bit

. . . . . . . . . . . . . . . . . . . . . . . . . . .73

stb

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

STBus

. . . . . . . . . . . . . . . . . 53 ,

61 ,

, 104

STBUS_DC_ERROR

. . . . . . . . . . . . . . . . . . . .54

STBUS_IC_ERROR

. . . . . . . . . . . . . . . . . . . . .51

STEP

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

sth

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

stop bit

. . . . . . . . . . . . . . . . . . . . . . . . . .118

, 137

store

. . . . . . . . . . . . . . . . . . . . . . . . . 14

, 138

streaming data interface

. . . . . . . . . . . . . . . . . .61

stw

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

subtract

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

supervisor

. . . . . . . . . . . . . . . . . . . . . . . . . .21

sync

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

syncins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

syscall

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

THROW

. . . . . . . . . . . . . . . . . . . . . 26

, 127

, 132

TIMECONSTi

. . . . . . . . . . . . . . . . . . . . . . . . . 74

TIMECONTROLi

. . . . . . . . . . . . . . . . . . . . . . . 74

TIMECOUNTi

. . . . . . . . . . . . . . . . . . . . . . . . . 74

TIMEDIVIDE

. . . . . . . . . . . . . . . . . . . . . . . . . . 73

TLB

. . . . . . . . . . . . . . . . . . . . . . . . 15

, 35

, 67

TLB_ASID

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

TLB_CONTROL

. . . . . . . . . . . . . . . . . . . . . . . 40

TLB_ENABLE

. . . . . . . . . . . . . . . . . . . . . . . . . 35

TLB_ENTRY0

. . . . . . . . . . . . . . . . . . . . . . . . . 35

TLB_ENTRY1

. . . . . . . . . . . . . . . . . . . . . . . . . 38

TLB_ENTRY2

. . . . . . . . . . . . . . . . . . . . . . . . . 38

TLB_ENTRY3

. . . . . . . . . . . . . . . . . . . . . . . . . 38

TLB_INDEX

. . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TLB_NO_MAPPING

. . . . . . . . . . . . . . . . . . . . 52

TLB_REPLACE

. . . . . . . . . . . . . . . . . . . . . . . . 38

trap handler

. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

trap point

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

traps

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

types

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

UNDEFINED

. . . . . . . . . . . . . . . . . . . . . 125

126

usage restrictions

. . . . . . . . . . . . . . . . . . . . . . 22

user

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

, 64

USER_MODE

. . . . . . . . . . . . . . . . . . . . . . . . . 21

UTLB

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

, 52

V variables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

VERSION register

. . . . . . . . . . . . . . . . . . . . . . 72

virtual addresses

. . . . . . . . . . . . . . . . . . . . . . . 32

VLIW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

XYZ

XOR

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

330/331 7645929

ST231

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