The ST6208C, 09C, 10C and 20C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals.

The ST62E20C is the erasable EPROM version of the ST62T08C, T09C, T10C and T20C devices, which may be used during the development phase for the ST62T08C, T09C, T10C and T20C target devices, as well as the respective ST6208C, 09C,

10C and 20C ROM devices.

OTP and EPROM devices are functionally identical. OTP devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required.

The ROM based versions offer the same functionality, selecting the options defined in the program-

Figure 1. Block Diagram mable option bytes of the OTP/EPROM versions

in the ROM option list (See Section 11.6 on page

96 ).

The ST62P08C/P09C/P10C/P20C are the F actory

A dvanced S ervice T echnique ROM (FASTROM) versions of ST62T08C, T09C, T10C and T20C

OTP devices.

They offer the same functionality as OTP devices, but they do not have to be programmed by the customer (See

Section 11 on page 90 ).

These compact low-cost devices feature a Timer comprising an 8-bit counter with a 7-bit programmable prescaler, an 8-bit A/D Converter with up to

8 analog inputs (depending on device) and a Digital Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications.

For easy reference, all parametric data are located in

Section 11 on page 90 .

8-BIT *

A/D CONVERTER PORT A

PA0..PA3 (20mA Sink)

NMI INTERRUPTS

PORT B PB0..PB7 / Ain*

MEMORY

(1K, 2K or 4K Bytes)

DATA ROM

USER

SELECTABLE

DATA RAM

64 Bytes

TIMER TIMER

WATCHDOG

TIMER

STACK LEVEL 1 Obsolete Product(s) - Obsolete Product(s)

STACK LEVEL 3

8-BIT CORE

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

POWER

SUPPLY

OSCILLATOR RESET

OSCin OSCout RESET

* Depending on device. Please refer to I/O Port section.

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ST6208C/ST6209C/ST6210C/ST6220C

2 PIN DESCRIPTION

Figure 2. 20-Pin Package Pinout

TIMER

OSCin

OSCout

NMI

RESET

Ain*/PB7

Ain*/PB6

Ain*/PB5 itX associated interrupt vector

* Depending on device. Please refer to I/O Port section.

2 it2 it1 it2

PA0/20mA Sink

PA1/20mA Sink

PA2/20mA Sink

PA3/20mA Sink

PB0/Ain*

PB1/Ain*

PB2/Ain*

PB3/Ain*

PB4/Ain*

Table 1. Device Pin Description

Pin n° Pin Name

1 V

2 TIMER

3 OSCin

4 OSCout

5 NMI

6 V

7 RESET

PB7/Ain*

PB6/Ain*

10 PB5/Ain*

11 PB4/Ain*

12 PB3/Ain*

14 PB1/Ain*

15 PB0/Ain*

16 PA3/ 20mA Sink

17 PA2/ 20mA Sink

18 PA1/ 20mA Sink

Main Function

(after Reset)

Alternate Function

S Main power supply

I/O Timer input or output

I External clock input or resonator oscillator inverter input

O Resonator inverter output or resistor input for RC oscillator

Must be held at Vss for normal operation, if a 12.5V level is applied to the pin during the reset phase, the device enters EPROM programming mode.

I/O Top priority non maskable interrupt (active low)

I/O Pin B7 (IPU)

I/O Pin B6 (IPU)

Analog input

I/O Pin B5 (IPU)

I/O Pin B4 (IPU)

I/O Pin B3 (IPU)

Analog input

I/O Pin B2 (IPU)

I/O Pin B1 (IPU)

I/O Pin B0 (IPU)

I/O Pin A3 (IPU)

I/O Pin A2 (IPU)

I/O Pin A1 (IPU)

Analog input

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ST6208C/ST6209C/ST6210C/ST6220C

Pin n° Pin Name

Main Function

(after Reset)

Alternate Function

19 PA0/ 20mA Sink

20 V

I/O Pin A0 (IPU)

S Ground

Legend / Abbreviations for

Table 1

* Depending on device. Please refer to

Section 7 "I/O PORTS" on page 37

I = input, O = output, S = supply, IPU = input with pull-up

The input with pull-up configuration (reset state) is valid as long as the user software does not change it.

Refer to Section 7 "I/O PORTS" on page 37

for more details on the software configuration of the I/O ports.

Obsolete Product(s) - Obsolete Product(s)

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ST6208C/ST6209C/ST6210C/ST6220C

3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES

3.1 MEMORY AND REGISTER MAPS

3.1.1 Introduction

The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs.

Figure 3. Memory Addressing Diagram

Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodates six levels of stack for subroutine and interrupt service routine nesting.

000h

PROGRAM SPACE

PROGRAM

MEMORY

(see

Figure 4 on page 10 )

0FF0h

0FFFh

INTERRUPT &

RESET VECTORS

DATA SPACE

000h

RESERVED

03Fh

040h

07Fh

080h

081h

082h

083h

084h

0BFh

0C0h

0FFh

DATA ROM

WINDOW

X REGISTER

Y REGISTER

V REGISTER

W REGISTER

RAM

HARDWARE

CONTROL

REGISTERS

(see

Table 2

)

ACCUMULATOR

Obsolete Product(s) - Obsolete Product(s)

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ST6208C/ST6209C/ST6210C/ST6220C

MEMORY MAP (Cont’d)

Figure 4. Program Memory Map

ST6208C, 09C

0000h 0000h

ST6210C

NOT IMPLEMENTED

0000h

07Fh

080h

ST6220C

RESERVED

NOT IMPLEMENTED

07FFh

0800h

087Fh

0880h

RESERVED

0AFFh

0B00h

0B9Fh

0BA0h

RESERVED

USER

PROGRAM MEMORY

1024 BYTES

0F9Fh

0FA0h

0FEFh

0FF0h

0FF7h

0FF8h

0FFBh

0FFCh

0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

RESERVED

NMI VECTOR

USER RESET VECTOR

USER

PROGRAM MEMORY

1824 BYTES

0F9Fh

0FA0h

0FEFh

0FF0h

0FF7h

0FF8h

0FFBh

0FFCh

0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

RESERVED

NMI VECTOR

USER RESET VECTOR

USER

PROGRAM MEMORY

3872 BYTES

0F9Fh

0FA0h

0FEFh

0FF0h

0FF7h

0FF8h

0FFBh

0FFCh

0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

RESERVED

NMI VECTOR

USER RESET VECTOR

10/104

ST6208C/ST6209C/ST6210C/ST6220C

MEMORY MAP (Cont’d)

3.1.2 Program Space

Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register

(PC register). Thus, the MCU is capable of addressing 4K bytes of memory directly.

3.1.3 Readout Protection

The Program Memory in OTP, EPROM or ROM devices can be protected against external readout of memory by setting the Readout Protection bit in the option bytes (

Section 3.3 on page 16

In the EPROM parts, Readout Protection option can be desactivated only by U.V. erasure that also results in the whole EPROM context being erased.

Note: Once the Readout Protection is activated, it is no longer possible, even for STMicroelectronics, to gain access to the OTP or ROM contents. Returned parts can therefore not be accepted if the

Readout Protection bit is set.

3.1.4 Data Space

Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in OTP/

EPROM.

3.1.4.1 Data ROM

All read-only data is physically stored in program memory, which also accommodates the Program

Space. The program memory consequently contains the program code to be executed, as well as the constants and look-up tables required by the application.

The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM.

3.1.4.2 Data RAM

The data space includes the user RAM area, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register (DRWR register).

3.1.5 Stack Space

Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents.

Obsolete Product(s) - Obsolete Product(s)

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ST6208C/ST6209C/ST6210C/ST6220C

MEMORY MAP (Cont’d)

Table 2. Hardware Register Map

Address Block

Register

Label

Register Name

Reset

Status

Remarks

0C9h

0CAh

0CBh

0CCh

0CDh

0CEh

0CFh

0D0h

0D1h

080h to 083h

0C0h

0C1h

0C2h

0C3h

0C4h

0C5h

0C6h

0C7h

0C8h

CPU

I/O Ports

CPU

ROM

I/O Ports

X,Y,V,W

DRA

1) 2) 3)

DRB

1) 2) 3)

DDRA

DDRB

IOR

DRWR

ORA

ORB

X,Y index registers

V,W short direct registers

Port A Data Register

Port B Data Register

Reserved (2 Bytes)

Port A Direction Register

Port B Direction Register

Reserved (2 Bytes)

Interrupt Option Register

Data ROM Window register

Reserved (2 Bytes)

Port A Option Register

Port B Option Register

Reserved (2 bytes) xxh

00h

00h xxh xxh

00h

R/W

Write-only

R/W

0D2h

0D3h

0D4h

ADC

Timer1

ADR

ADCR

PSCR

TCR

TSCR

A/D Converter Data Register

A/D Converter Control Register

Timer 1 Prescaler Register

Timer 1 Downcounter Register

Timer 1 Status Control Register xxh

40h

7Fh

0FFh

00h

Read-only

Ro/Wo

R/W

0D5h to 0D7h

Reserved (3 Bytes)

0D8h

Watchdog

Timer

WDGR Watchdog Register 0FEh R/W

0D9h to 0FEh

Reserved (38 Bytes)

Obsolete Product(s) - Obsolete Product(s)

0FFh CPU A Accumulator xxh R/W

Legend : x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s) in the register.

Notes :

1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always be kept at their reset value.

3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured in input mode (refer to

Section 7 "I/O PORTS" on page 37

for more details)

4. Depending on device. See device summary on page 1.

12/104

ST6208C/ST6209C/ST6210C/ST6220C

MEMORY MAP (Cont’d)

3.1.6 Data ROM Window

The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh.

There are 64 blocks of 64 bytes in a 4K device:

– Block 0 is related to the address range 0000h to

003Fh.

– Block 1 is related to the address range 0040h to

007Fh.

and so on...

All the program memory can therefore be used to store either instructions or read-only data. The

Data ROM window can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the Data ROM Window Register (DRWR).

Figure 5. Data ROM Window

0000h

PROGRAM

SPACE

000h

DATA SPACE

3.1.6.1 Data ROM Window Register (DRWR)

The DRWR can be addressed like any RAM location in the Data Space.

This register is used to select the 64-byte block of program memory to be read in the Data ROM window (from address 40h to address 7Fh in Data space). The DRWR register is not cleared on reset, therefore it must be written to before accessing the Data read-only memory window area for the first time.

Address: 0C9h — Write Only

Reset Value = xxh (undefined)

DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0

64-BYTE

040h

ROM

07Fh

DATA ROM

WINDOW

Bits 7:6 = Reserved , must be cleared.

Bit 5:0 = DRWR[5:0] Data read-only memory Window Register Bits.

These are the Data read-only memory Window bits that correspond to the upper bits of the data read-only memory space.

Caution: This register is undefined on reset, it is write-only, therefore do not read it nor access it using Read-Modify-Write instructions (SET, RES,

INC and DEC).

0FFFh 0FFh

Obsolete Product(s) - Obsolete Product(s)

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ST6208C/ST6209C/ST6210C/ST6220C

MEMORY MAP (Cont’d)

3.1.6.2 Data ROM Window memory addressing

In cases where some data (look-up tables for example) are stored in program memory, reading these data requires the use of the Data ROM window mechanism. To do this:

1. The DRWR register has to be loaded with the

64-byte block number where the data are located

(in program memory). This number also gives the start address of the block.

2. Then, the offset address of the byte in the Data

ROM Window (corresponding to the offset in the

64-byte block in program memory) has to be loaded in a register (A, X,...).

When the above two steps are completed, the data can be read.

To understand how to determine the DRWR and the content of the register, please refer to the example shown in

Figure 6 . In any case the calcula-

Figure 6. Data ROM Window Memory Addressing tion is automatically handled by the ST6 development tools.

Please refer to the user manual of the correspoding tool.

3.1.6.3 Recommendations

Care is required when handling the DRWR register as it is write only. For this reason, the DRWR contents should not be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register’s previous contents. If it is impossible to avoid writing to the DRWR during the interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to the

DRWR, it must also write to the image register.

The image register must be written first so that, if an interrupt occurs between the two instructions, the DRWR is not affected.

DATA SPACE

000h

PROGRAM SPACE

0000h

DATA

040h

061h

07Fh

OFFSET

21h

0400h

OFFSET

0421h

64 bytes

DATA

10h

0FFh

07FFh

DATA address in Program memory : 421h

DRWR content : 421h / 3Fh (64) = 10H data is located in 64-bytes window number 10h

64-byte window start address : 10h x 3Fh = 400h

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ST6208C/ST6209C/ST6210C/ST6220C

3.2 PROGRAMMING MODES

3.2.1 Program Memory

EPROM/OTP programming mode is set by a

+12.5V voltage applied to the TEST/V

pin. The programming flow of the ST62T08C,T09C,T10C,

T20C and E20C is described in the User Manual of the EPROM Programming Board.

Table 3. ST6208C/09C Program Memory Map

Device Address

0000h-0B9Fh

0BA0h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Description

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Table 4. ST6210C Program Memory Map

Device Address

0000h-087Fh

0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Description

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

STMicroelectronics (please refer to Section 12 on page 99

3.2.2 EPROM Erasing

The EPROM devices can be erased by exposure to Ultra Violet light. The characteristics of the MCU are such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlight and some types of fluorescent lamps have wavelengths in the range 3000-4000Å.

It is thus recommended that the window of the

MCU packages be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment.

The recommended erasure procedure is exposure to short wave ultraviolet light which have a wavelength 2537Å. The integrated dose (i.e. U.V. intensity x exposure time) for erasure should be a minimum of 30W-sec/cm

. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000µW/cm

power rating.

The EPROM device should be placed within

2.5cm (1inch) of the lamp tubes during erasure.

Table 5. ST6220C Program Memory Map

Device Address

0000h-007Fh

0080h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

Description

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Note : OTP/EPROM devices can be programmed

Obsolete Product(s) - Obsolete Product(s)

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ST6208C/ST6209C/ST6210C/ST6220C

3.3 OPTION BYTES

Each device is available for production in user programmable versions (OTP) as well as in factory coded versions (ROM). OTP devices are shipped to customers with a default content (00h), while

ROM factory coded parts contain the code supplied by the customer. This implies that OTP devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured.

The two option bytes allow the hardware configuration of the microcontroller to be selected.

The option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard ST6 programming tool).

In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see

Section

11.6.2 "ROM VERSION" on page 98 ). It is there-

fore impossible to read the option bytes.

The option bytes can be only programmed once. It is not possible to change the selected options after they have been programmed.

In order to reach the power consumption value indicated in

Section 10.4

, the option byte must be programmed to its default value. Otherwise, an over-consumption will occur.

LSB OPTION BYTE

Bit 7 = PROTECT Readout Protection.

This option bit enables or disables external access to the internal program memory.

0: Program memory not read-out protected

1: Program memory read-out protected

Bit 6 =

Bit 3 =

OSC Oscillator selection

NMI PULL NMI Pull-Up on/off.

This option bit enables or disables the internal pullup on the NMI pin.

0: Pull-up disabled

1: Pull-up enabled

This option bit selects the main oscillator type.

0: Quartz crystal, ceramic resonator or external clock

1: RC network

Bit 5 =

Bit 4 =

Reserved

, must be always cleared.

, must be always set.

MSB OPTION BYTE

Bits 15:10 = Reserved , must be always cleared.

Bit 2 = TIM PULL TIMER Pull-Up on/off.

This option bit enables or disables the internal pullup on the TIMER pin.

0: Pull-up disabled

1: Pull-up enabled

Bit 9 = EXTCNTL External STOP MODE control .

0: EXTCNTL mode not available. STOP mode is not available with the watchdog active.

1: EXTCNTL mode available. STOP mode is available with the watchdog active by setting NMI pin to one.

Bit 1 = WDACT Hardware or software watchdog.

This option bit selects the watchdog type.

0: Software (watchdog to be enabled by software)

1: Hardware (watchdog always enabled)

Bit 8 = LVD Low Voltage Detector on/off .

Bit 0 = OSGEN Oscillator Safeguard on/off.

This option bit enables or disables the oscillator

Safeguard (OSG) feature.

0: Oscillator Safeguard disabled

1: Oscillator Safeguard enabled

0: Low Voltage Detector disabled

1: Low Voltage Detector enabled

MSB OPTION BYTE

Reserved

Default

Value

X X X X X X

EXT

CTL

LVD

LSB OPTION BYTE

PRO-

TECT

OSC Res.

Res.

NMI

PULL

TIM

PULL

ACT

OSG

X X X X X X X X X X

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ST6208C/ST6209C/ST6210C/ST6220C

4 CENTRAL PROCESSING UNIT

4.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the

I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses.

4.2 MAIN FEATURES

■

40 basic instructions

9 main addressing modes

Two 8-bit index registers

Two 8-bit short direct registers

Low power modes

Maskable hardware interrupts

6-level hardware stack tions. The accumulator can be addressed in Data

Space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data Space.

Index Registers (X, Y). These two registers are used in Indirect addressing mode as pointers to memory locations in Data Space. They can also be accessed in Direct, Short Direct, or Bit Direct addressing modes. They are mapped in Data

Space at addresses 80h (X) and 81h (Y) and can be accessed like any other memory location.

Short Direct Registers (V, W).

These two registers are used in Short Direct addressing mode.

This means that the data stored in V or W can be accessed with a one-byte instruction (four CPU cycles). V and W can also be accessed using Direct and Bit Direct addressing modes. They are mapped in Data Space at addresses 82h (V) and

83h (W) and can be accessed like any other memory location.

Note : The X and Y registers can also be used as

Short Direct registers in the same way as V and W.

Program Counter (PC) . The program counter is a

12-bit register which contains the address of the next instruction to be executed by the core. This

ROM location may be an opcode, an operand, or the address of an operand.

4.3 CPU REGISTERS

The ST6 Family CPU core features six registers and three pairs of flags available to the programmer.

These are described in the following paragraphs.

Accumulator (A) . The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipula-

Figure 7. CPU Registers

7 0

ACCUMULATOR

RESET VALUE = xxh

7 0

SIX LEVEL

STACK

X INDEX REGISTER

RESET VALUE = xxh

7 CN ZN 0 NORMAL FLAGS

Y INDEX REGISTER

RESET VALUE = xxh

INTERRUPT FLAGS Obsolete Product(s) - Obsolete Product(s)

7 0

V SHORT INDIRECT

NMI FLAGS

CI ZI

CNMI ZNMI

RESET VALUE = xxh

7 0

W SHORT INDIRECT

RESET VALUE = xxh

11 0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh x = Undefined value

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ST6208C/ST6209C/ST6210C/ST6220C

CPU REGISTERS (Cont’d)

The 12-bit length allows the direct addressing of

4096 bytes in Program Space.

However, if the program space contains more than

4096 bytes, the additional memory in program space can be addressed by using the Program

ROM Page register.

Z : Zero flag

This flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared.

0: The result of the last operation is different from zero

1: The result of the last operation is zero

The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways:

Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instruction occurs. As NMI mode is automatically selected after the reset of the MCU, the

ST6 core uses the NMI flags first.

– JP (Jump) instruction

– CALL instruction

– Relative Branch InstructionPC = PC +/- offset

– Interrupt

– Reset

– RET & RETI instructions PC = Pop (stack)

– Normal instruction

PC = Jump address

PC = Call address

PC = Interrupt vector

PC = Reset vector

PC = PC + 1

Stack.

The ST6 CPU includes a true LIFO (Last In

First Out) hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next level down, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level.

Flags (C, Z) . The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation:

Normal mode, Interrupt mode and Non Maskable

Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZN-

MI).

Figure 8. Stack manipulation

PROGRAM

COUNTER

The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6

CPU uses the Interrupt flags (or the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maska-

ON RETURN

FROM

INTERRUPT,

SUBROUTINE

LEVEL 1

LEVEL 2

LEVEL 3

LEVEL 4

LEVEL 5

INTERRUPT,

SUBROUTINE

CALL ble Interrupt, Normal Interrupt or Main routine).

LEVEL 6

The flags are not cleared during context switching Obsolete Product(s) - Obsolete Product(s)

C : Carry flag.

Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine.

This bit is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared.

The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction.

0: No carry has occured

1: A carry has occured

Caution: The stack will remain in its “deepest” position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost.

It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed.

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ST6208C/ST6209C/ST6210C/ST6220C

5 CLOCKS, SUPPLY AND RESET

5.1 CLOCK SYSTEM

The main oscillator of the MCU can be driven by any of these clock sources:

– external clock signal

– external AT-cut parallel-resonant crystal

– external ceramic resonator

– external RC network (R

NET

In addition, an on-chip Low Frequency Auxiliary

Oscillator (LFAO) is available as a back-up clock system or to reduce power consumption.

An optional Oscillator Safeguard (OSG) filters spikes from the oscillator lines, and switches to the

LFAO backup oscillator in the event of main oscillator failure. It also automatically limits the internal clock frequency (f

INT

) as a function of V

, in order to guarantee correct operation. These functions are illustrated in Figure 10 , and Figure 11 .

Table 6 illustrates various possible oscillator configurations using an external crystal or ceramic resonator, an external clock input, an external resistor (R

NET the LFAO.

), or the lowest cost solution using only

For more details on configuring the clock options, refer to the Option Bytes section of this document.

The internal MCU clock frequency (f

INT

) is divided by 12 to drive the Timer, the Watchdog timer and the A/D converter, by 13 to drive the CPU core and the SPI and by 1 or 3 to drive the ARTIMER, as shown in Figure 9 .

With an 8 MHz oscillator, the fastest CPU cycle is therefore 1.625µs.

A CPU cycle is the smallest unit of time needed to execute any operation (for instance, to increment the Program Counter). An instruction may require two, four, or five CPU cycles for execution.

Figure 9. Clock Circuit Block Diagram

OSCILLATOR SAFEGUARD (OSG) f

OSC

OSG filtering

: 13

SPI

CORE

8-BIT TIMER

MAIN

OSCILLATOR

Oscillator

Divider f

INT

: 12

WATCHDOG

ADC

LFAO

: 1

8-BIT ARTIMER OSCOFF BIT

(ADCR REGISTER)

: 3

8-BIT ARTIMER

Obsolete Product(s) - Obsolete Product(s)

OSG ENABLE OPTION BIT (See OPTION BYTE SECTION)

* Depending on device. See device summary on page 1.

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CLOCK SYSTEM (Cont’d)

5.1.1 Main Oscillator

The oscillator configuration is specified by selecting the appropriate option in the option bytes (refer to the Option Bytes section of this document).

When the CRYSTAL/RESONATOR option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the OSCin pin. When the RC NETWORK option is selected, the system clock is generated by an external resistor (the capacitor is implemented internally).

The main oscillator can be turned off (when the

OSG ENABLED option is selected) by setting the

OSCOFF bit of the ADC Control Register (not available on some devices). This will automatically start the Low Frequency Auxiliary Oscillator

(LFAO).

The main oscillator can be turned off by resetting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. When the main oscillator starts there is a delay made up of the oscillator start-up delay period plus the duration of the software instruction at a clock frequency f

LFAO

Caution: It should be noted that when the RC network option is selected, the accuracy of the frequency is about 20% so it may not be suitable for some applications (For more details, please refer to the Electrical Characteristics Section).

Table 6. Oscillator Configurations

Hardware Configuration

External Clock

OSCin

ST6

OSCout

EXTERNAL

CLOCK

LOAD

CAPACITORS

RC Network

ST6

OSCin OSCout

NET

Crystal/Resonator Clock

ST6

OSCin OSCout

LFAO

ST6

OSCin OSCout Obsolete Product(s) - Obsolete Product(s)

Notes:

1. To select the options shown in column 1 of the above table, refer to the Option Byte section.

2.This schematic are given for guidance only and are subject to the schematics given by the crystal or ceramic resonator manufacturer.

3. For more details, please refer to the Electrical Characteristics Section.

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CLOCK SYSTEM (Cont’d)

5.1.2 Oscillator Safeguard (OSG)

The Oscillator Safeguard (OSG) feature is a means of dramatically improving the operational integrity of the MCU. It is available when the OSG

ENABLED option is selected in the option byte (refer to the Option Bytes section of this document).

The OSG acts as a filter whose cross-over frequency is device dependent and provides three basic functions:

– Filtering spikes on the oscillator lines which would result in driving the CPU at excessive frequencies

– Management of the Low Frequency Auxiliary

Oscillator (LFAO), (useable as low cost internal clock source, backup clock in case of main oscillator failure or for low power consumption)

– Automatically limiting the f

INT

clock frequency as a function of supply voltage, to ensure correct operation even if the power supply drops.

5.1.2.1 Spike Filtering

Spikes on the oscillator lines result in an effectively increased internal clock frequency. In the absence of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The

OSG filters out such spikes (as illustrated in Figure

10 ). In all cases, when the OSG is active, the maxf imum internal clock frequency, f

INT

OSG

, is limited to

, which is supply voltage dependent.

5.1.2.2 Management of Supply Voltage

Variations

Over-frequency, at a given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock frequency of the device is kept within the range the particular device can stand (depending on V

DD and below f

OSG cy with OSG enabled.

: the maximum authorised frequen-

5.1.2.3 LFAO Management

When the OSG is enabled, the Low Frequency

Auxiliary Oscillator can be used (see Section

5.1.3

Note: The OSG should be used wherever possible as it provides maximum security for the application. It should be noted however, that it can increase power consumption and reduce the maximum operating frequency to f

OSG

Characteristics section).

(see Electrical

Caution: Care has to be taken when using the

OSG, as the internal frequency is defined between a minimum and a maximum value and may vary depending on both V

and temperature. For precise timing measurements, it is not recommended to use the OSG.

Figure 10. OSG Filtering Function f

OSC> f

OSG f

OSC f

OSG f

OSC< f

OSG f

INT

Figure 11. LFAO Oscillator Function Obsolete Product(s) - Obsolete Product(s)

MAIN OSCILLATOR MAIN OSCILLATOR

STOPS RESTARTS f

OSC f

LFAO f

INT

INTERNAL CLOCK DRIVEN BY LFAO

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CLOCK SYSTEM (Cont’d)

5.1.3 Low Frequency Auxiliary Oscillator

(LFAO)

The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines.

Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a backup oscillator in case of main oscillator failure.

This oscillator is available when the OSG ENA-

BLED option is selected in the option byte (refer to the Option Bytes section of this document). In this case, it automatically starts one of its periods after the first missing edge of the main oscillator, whatever the reason for the failure (main oscillator defective, no clock circuitry provided, main oscillator switched off...). See Figure 11 .

User code, normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced f

LFAO

frequency. The A/D converter accuracy is decreased, since the internal frequency is below 1.2 MHz.

At power on, until the main oscillator starts, the reset delay counter is driven by the LFAO. If the main oscillator starts before the 2048 cycle delay has elapsed, it takes over.

The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts.

5.1.4 Register Description

ADC CONTROL REGISTER (ADCR)

Address: 0D1h — Read/Write

Reset value: 0100 0000 (40h)

ADCR

OSC

OFF

ADCR

Bit 7:3, 1:0 = ADCR[7:3], ADCR[1:0] ADC Control

Register .

These bits are used to control the A/D converter (if available on the device) otherwise they are not used.

Bit 2 = OSCOFF Main Oscillator Off.

0: Main oscillator enabled

1: Main oscillator disabled

Note: The OSG must be enabled using the OS-

GEN option in the Option Byte, otherwise the OS-

COFF setting has no effect.

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5.2 LOW VOLTAGE DETECTOR (LVD)

The on-chip Low Voltage Detector is enabled by setting a bit in the option bytes (refer to the Option

Bytes section of this document).

The LVD allows the device to be used without any external RESET circuitry. In this case, the RESET pin should be left unconnected.

If the LVD is not used, an external circuit is mandatory to ensure correct Power On Reset operation, see figure in the Reset section. For more details, please refer to the application note AN669.

The LVD generates a static Reset when the supply voltage is below a reference value. This means that it secures the power-up as well as the powerdown keeping the ST6 in reset.

The V

IT-

reference value for a voltage drop is lower than the V

IT+

reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

Figure 12. Low Voltage Detector Reset

The LVD Reset circuitry generates a reset when

is below:

– V

IT+

when V

is rising

– V

IT-

when V

is falling

The LVD function is illustrated in Figure 12 .

If the LVD is enabled, the MCU can be in only one of two states:

– Over the input threshold voltage, it is running under full software control

– Below the input threshold voltage, it is in static safe reset

In these conditions, secure operation is guaranteed without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

V hyst

IT+

IT-

RESET

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5.3 RESET

5.3.1 Introduction

The MCU can be reset in three ways:

■ A low pulse input on the RESET pin

■

Internal Watchdog reset

Internal Low Voltage Detector (LVD) reset

5.3.2 RESET Sequence

The basic RESET sequence consists of 3 main phases:

■ Internal (watchdog or LVD) or external Reset event

■

A delay of 2048 clock (f

INT

) cycles

RESET vector fetch

The reset delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.

Figure 13. RESET Sequence

IT+

IT-

The RESET vector fetch phase duration is 2 clock cycles.

When a reset occurs:

– The stack is cleared

– The PC is loaded with the address of the Reset vector. It is located in program ROM starting at address 0FFEh.

A jump to the beginning of the user program must be coded at this address.

– The interrupt flag is automatically set, so that the

CPU is in Non Maskable Interrupt mode. This prevents the initialization routine from being interrupted. The initialization routine should therefore be terminated by a RETI instruction, in order to go back to normal mode.

WATCHDOG

RESET

WATCHDOG UNDERFLOW

LVD

RESET

RESET PIN

INTERNAL

RESET

RUN Obsolete Product(s) - Obsolete Product(s)

RESET

RUN

RESET

RUN

RESET

RUN

2048 CLOCK CYCLE (fINT) DELAY

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RESET (Cont’d)

5.3.3 RESET Pin

The RESET pin may be connected to a device on the application board in order to reset the MCU if required. The RESET pin may be pulled low in

RUN, WAIT or STOP mode. This input can be used to reset the internal state of the MCU and ensure it starts-up correctly. The pin, which is connected to an internal pull-up, is active low and features a Schmitt trigger input. A delay (2048 clock cycles) added to the external signal ensures that even short pulses on the RESET pin are accepted as valid, provided V

has completed its rising phase and that the oscillator is running correctly

(normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low.

Figure 14. Reset Block Diagram

If the RESET pin is grounded while the MCU is in

RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the I/O ports are configured as inputs with pull-up resistors and the main oscillator is restarted. When the level on the RESET pin then goes high, the initialization sequence is executed at the end of the internal delay period.

If the RESET pin is grounded while the MCU is in

STOP mode, the oscillator starts up and all the I/O ports are configured as inputs with pull-up resistors. When the RESET pin level then goes high, the initialization sequence is executed at the end of the internal delay period.

A simple external RESET circuitry is shown in Figure 15 . For more details, please refer to the application note AN669.

INT

INTERNAL

RESET

ESD

WATCHDOG RESET

LVD RESET

1) Resistive ESD protection.

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RESET (Cont’d)

5.3.4 Watchdog Reset

The MCU provides a Watchdog timer function in order to be able to recover from software hangups. If the Watchdog register is not refreshed before an end-of-count condition is reached, a

Watchdog reset is generated.

After a Watchdog reset, the MCU restarts in the same way as if a Reset was generated by the RE-

SET pin.

Note: When a watchdog reset occurs, the RESET pin is tied low for very short time period, to flag the reset phase. This time is not long enough to reset external circuits.

For more details refer to the Watchdog Timer chapter.

5.3.5 LVD Reset

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

During an LVD reset, the RESET pin is pulled low when V

DD edge).

IT+

(rising edge) or V

IT-

(falling

For more details, refer to the LVD chapter.

Caution: Do not externally connect directly the

RESET pin to V

, this may cause damage to the component in case of internal RESET (Watchdog or LVD).

Figure 15. Simple External Reset Circuitry

Figure 16. Reset Processing

RESET

2048

CLOCK CYCLE

DELAY

INTERNAL

RESET

NMI MASK SET

INT LATCH CLEARED

(IF PRESENT)

SELECT

NMI MODE FLAGS

PUT FFEh

ON ADDRESS BUS

YES

IS RESET STILL

PRESENT?

LOAD PC

FROM RESET LOCATIONS

FFEh/FFFh

FETCH INSTRUCTION

RESET

Typical: R = 10K

C = 10nF

R > 4.7 K

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5.4 INTERRUPTS

The ST6 core may be interrupted by four maskable interrupt sources, in addition to a Non Maskable Interrupt (NMI) source. The interrupt processing flowchart is shown in

Figure 18 .

Maskable interrupts must be enabled by setting the GEN bit in the IOR register. However, even if they are disabled (GEN bit = 0), interrupt events are latched and may be processed as soon as the

GEN bit is set.

Each source is associated with a specific Interrupt

Vector, located in Program space (see Table 8

). In the vector location, the user must write a Jump in-

Figure 17. Interrupts Block Diagram

VDD struction to the associated interrupt service routine.

When an interrupt source generates an interrupt request, the PC register is loaded with the address of the interrupt vector, which then causes a Jump to the relevant interrupt service routine, thus servicing the interrupt.

Interrupt are triggered by events either on external pins, or from the on-chip peripherals. Several events can be ORed on the same interrupt vector.

On-chip peripherals have flag registers to determine which event triggered the interrupt.

VECTOR #0

NMI LATCH

PA0...PA3

I/O PORT REGISTER

“INPUT WITH INTERRUPT”

CONFIGURATION

CLEARED BY H/W

AT START OF VECTOR #0 ROUTINE

LATCH

CLEARED BY H/W

AT START OF

VECTOR #1 ROUTINE

LES BIT

(IOR REGISTER)

VECTOR #1

EXIT FROM

STOP/WAIT

PB0...PB7

I/O PORT REGISTER

“INPUT WITH INTERRUPT”

CONFIGURATION

LATCH

VECTOR #2

ESB BIT

(IOR REGISTER)

CLEARED

BY H/W AT START OF

TIMER

TMZ BIT

VECTOR #2 ROUTINE Obsolete Product(s) - Obsolete Product(s)

VECTOR #3

ETI BIT

(TSCR REGISTER)

A/D CONVERTER *

EAI BIT

EOC BIT

(ADCR REGISTER)

VECTOR #4

GEN BIT

(IOR REGISTER)

* Depending on device. See device summary on page 1.

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5.5 INTERRUPT RULES AND PRIORITY

MANAGEMENT

■

A Reset can interrupt the NMI and peripheral interrupt routines

The Non Maskable Interrupt request has the highest priority and can interrupt any peripheral interrupt routine at any time but cannot interrupt another NMI interrupt.

No peripheral interrupt can interrupt another. If more than one interrupt request is pending, these are processed by the processor core according to their priority level: vector #1 has the highest priority while vector #4 the lowest. The priority of each interrupt source is fixed by hardware (see Interrupt Mapping table ).

5.6 INTERRUPTS AND LOW POWER MODES

All interrupts cause the processor to exit from

WAIT mode. Only the external and some specific interrupts from the on-chip peripherals cause the processor to exit from STOP mode (refer to the

“Exit from STOP“ column in the Interrupt Mapping

Table).

5.7 NON MASKABLE INTERRUPT

This interrupt is triggered when a falling edge occurs on the NMI pin regardless of the state of the

GEN bit in the IOR register. An interrupt request on NMI vector #0 is latched by a flip flop which is automatically reset by the core at the beginning of the NMI service routine.

5.8 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the peripheral control registers are able to cause an interrupt when they are active if both:

– The GEN bit of the IOR register is set

– The corresponding enable bit is set in the peripheral control register.

Peripheral interrupts are linked to vectors #3 and

#4. Interrupt requests are flagged by a bit in their corresponding control register. This means that a request cannot be lost, because the flag bit must be cleared by user software.

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5.9 EXTERNAL INTERRUPTS (I/O Ports)

External interrupt vectors can be loaded into the

PC register if the corresponding external interrupt occurred and if the GEN bit is set. These interrupts allow the processor to exit from STOP mode.

The external interrupt polarity is selected through the IOR register.

External interrupts are linked to vectors #1 and #

Interrupt requests on vector #1 can be configured either as edge or level-sensitive using the LES bit in the IOR Register.

Interrupt requests from vector #2 are always edge sensitive. The edge polarity can be configured using the ESB bit in the IOR Register.

In edge-sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started.

So, an interrupt request can be stored until completion of the currently executing interrupt routine, before being processed. If several interrupt requests occurs before completion of the current interrupt routine, only the first request is stored.

Storing of interrupt requests is not possible in level sensitive mode. To be taken into account, the low level must be present on the interrupt pin when the

MCU samples the line after instruction execution.

5.9.1 Notes on using External Interrupts

ESB bit Spurious Interrupt on Vector #2

If a pin associated with interrupt vector #2 is configured as interrupt with pull-up, whenever vector

#2 is configured to be rising edge sensitive (by setting the ESB bit in the IOR register), an interrupt is latched although a rising edge may not have occured on the associated pin.

This is due to the vector #2 circuitry.The workaround is to discard this first interrupt request in the routine (using a flag for example).

Masking of One Interrupt by Another on Vector

#2.

When two or more port pins (associated with interrupt vector #2) are configured together as input with interrupt (falling edge sensitive), as long as one pin is stuck at '0', the other pin can never generate an interrupt even if an active edge occurs at this pin. The same thing occurs when one pin is stuck at '1' and interrupt vector #2 is configured as rising edge sensitive.

To avoid this the first pin must input a signal that goes back up to '1' right after the falling edge. Otherwise, in the interrupt routine for the first pin, deactivate the “input with interrupt” mode using the port control registers (DDR, OR, DR). An active edge on another pin can then be latched.

I/O port Configuration Spurious Interrupt on

Vector #2

If a pin associated with interrupt vector #2 is in ‘input with pull-up’ state, a ‘0’ level is present on the pin and the ESB bit = 0, when the I/O pin is configured as interrupt with pull-up by writing to the

DDRx, ORx and DRx register bits, an interrupt is latched although a falling edge may not have occurred on the associated pin.

In the opposite case, if the pin is in interrupt with pull-up state , a 0 level is present on the pin and the ESB bit =1, when the I/O port is configured as input with pull-up by writing to the DDRx, ORx and

DRx bits, an interrupt is latched although a rising edge may not have occurred on the associated pin.

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5.10 INTERRUPT HANDLING PROCEDURE

The interrupt procedure is very similar to a call procedure, in fact the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred. As a result, the user should save all Data space registers which may be used within the interrupt routines.

The following list summarizes the interrupt procedure:

When an interrupt request occurs, the following actions are performed by the MCU automatically:

– The core switches from the normal flags to the interrupt flags (or the NMI flags).

– The PC contents are stored in the top level of the stack.

– The normal interrupt lines are inhibited (NMI still active).

– The internal latch (if any) is cleared.

– The associated interrupt vector is loaded in the PC.

When an interrupt request occurs, the following actions must be performed by the user software:

– User selected registers have to be saved within the interrupt service routine (normally on a software stack).

– The source of the interrupt must be determined by polling the interrupt flags (if more than one source is associated with the same vector).

– The RETI (RETurn from Interrupt) instruction must end the interrupt service routine.

Figure 18. Interrupt Processing Flow Chart

YES

INSTRUCTION

FETCH

INSTRUCTION

EXECUTE

INSTRUCTION

WAS

THE INSTRUCTION

A RETI?

YES

IS THE CORE

ALREADY IN

NORMAL MODE?

ENABLE

MASKABLE INTERRUPTS

SELECT

NORMAL FLAGS

“POP”

THE STACKED PC

LOAD PC FROM

INTERRUPT VECTOR

CLEAR

INTERNAL LATCH

DISABLE

MASKABLE INTERRUPT

PUSH THE

PC INTO THE STACK

SELECT

INTERRUPT FLAGS

After the RETI instruction is executed, the MCU returns to the main routine.

NO IS THERE AN

AN INTERRUPT REQUEST

AND INTERRUPT MASK?

Caution: When a maskable interrupt occurs while the ST6 core is in NORMAL mode and during the execution of an “ldi IOR, 00h” instruction (disabling all maskable interrupts): if the interrupt request occurs during the first 3 cycles of the “ldi” instruction

(which is a 4-cycle instruction) the core will switch

YES

If a latch is present on the interrupt source line

Table 7. Interrupt Response Time to interrupt mode BUT the flags CN and ZN will

NOT switch to the interrupt pair CI and ZI.

Obsolete Product(s) - Obsolete Product(s)

This is defined as the time between the moment

Minimum

Maximum

6 CPU cycles

11 CPU cycles when the Program Counter is loaded with the interrupt vector and when the program has jump to the interrupt subroutine and is ready to execute the code. It depends on when the interrupt occurs while the core is processing an instruction.

One CPU cycle is 13 external clock cycles thus 11

CPU cycles = 11 x (13 /8M) = 17.875 µs with an 8

MHz external quartz.

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5.11 REGISTER DESCRIPTION

INTERRUPT OPTION REGISTER (IOR)

Address: 0C8h — Write Only

Reset status: 00h

LES ESB GEN -

1: Low level sensitive mode is selected for interrupt vector #1

Bit 5 = ESB Edge Selection bit .

0: Falling edge mode on interrupt vector #2

1: Rising edge mode on interrupt vector #2

Caution: This register is write-only and cannot be accessed by single-bit operations (SET, RES,

DEC,...).

Bit 4 = GEN Global Enable Interrupt .

0: Disable all maskable interrupts

1: Enable all maskable interrupts

Note: When the GEN bit is cleared, the NMI interrupt is active but cannot be used to exit from STOP or WAIT modes.

Bit 7 =Reserved, must be cleared.

Bit 6 = LES Level/Edge Selection bit .

0: Falling edge sensitive mode is selected for interrupt vector #1

Table 8. Interrupt Mapping

Bits 3:0 = Reserved, must be cleared.

Vector number

Source

Block

RESET

Vector #0 NMI

Description

Reset

Non Maskable Interrupt

Register

Label

N/A

NOT USED

Vector #1 Port A

Vector #2 Port B

Vector #3 TIMER

Vector #4 ADC*

Ext. Interrupt Port A

Ext. Interrupt Port B

Timer underflow

End Of Conversion

N/A

TSCR

ADCR

* Depending on device. See device summary on page 1.

Flag

N/A

TMZ

EOC

Exit from

STOP yes yes yes yes yes no

Vector

Address

FFEh-FFFh

FFCh-FFDh

FFAh-FFBh

FF8h-FF9h

FF6h-FF7h

FF4h-FF5h

FF2h-FF3h

FF0h-FF1h

Priority

Order

Highest

Priority

Lowest

Priority

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6 POWER SAVING MODES

6.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST6 (see

Figure 19 ).

In addition, the Low Frequency Auxiliary Oscillator

(LFAO) can be used instead of the main oscillator to reduce power consumption in RUN and WAIT modes.

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency.

From Run mode, the different power saving modes may be selected by calling the specific ST6 software instruction or for the LFAO by setting the relevant register bit. For more information on the

LFAO, please refer to the Clock chapter.

Figure 19. Power Saving Mode Transitions

High

RUN

LFAO

WAIT

STOP

Low

POWER CONSUMPTION

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6.2 WAIT MODE

The MCU goes into WAIT mode as soon as the

WAIT instruction is executed. This has the following effects:

– Program execution is stopped, the microcontroller software can be considered as being in a “frozen” state.

– RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage.

– The oscillator is kept running to provide a clock to the peripherals; they are still active.

WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods, while not losing track of time or the ability to monitor external events. WAIT mode places the

MCU in a low power consumption mode by stopping the CPU. The active oscillator (main oscillator or LFAO) is kept running in order to provide a clock signal to the peripherals.

If the power consumption has to be further reduced, the Low Frequency Auxiliary Oscillator

(LFAO) can be used in place of the main oscillator, if its operating frequency is lower. If required, the

LFAO must be switched on before entering WAIT mode.

Exit from Wait mode

The MCU remains in WAIT mode until one of the following events occurs:

– RESET (Watchdog, LVD or RESET pin)

– A peripheral interrupt (timer, ADC,...),

– An external interrupt (I/O port, NMI)

The Program Counter then branches to the starting address of the interrupt or RESET service routine. Refer to Figure 20 .

7 I/O PORTS

7.1 INTRODUCTION

Each I/O port contains up to 8 pins. Each pin can be programmed independently as digital input

(with or without pull-up and interrupt generation), digital output (open drain, push-pull) or analog input (when available).

The I/O pins can be used in either standard or alternate function mode.

All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The interrupt trigger modes (falling edge, rising edge and low level) can be configured by software for each port as described in the Interrupt section.

7.2.2 Analog Inputs

Standard I/O mode is used for:

– Transfer of data through digital inputs and outputs (on specific pins):

Some pins can be configured as analog inputs by programming the OR and DR registers accordingly, see Table 9 . These analog inputs are connected to the on-chip 8-bit Analog to Digital Converter.

– External interrupt generation

Alternate function mode is used for:

– Alternate signal input/output for the on-chip peripherals

Caution: ONLY ONE pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively shorted.

7.2.3 Output Modes The generic I/O block diagram is shown in Figure

23 .

7.2 FUNCTIONAL DESCRIPTION

Each port is associated with 3 registers located in

Data space:

– Data Register (DR)

The output configuration is selected by setting the corresponding DDR register bit. In this case, writing to the DR register applies this digital value to the I/O pin through the latch. Then, reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: push-pull and open-drain.

– Data Direction Register (DDR)

DR register value and output pin status: – Option Register (OR)

Each I/O pin may be programmed using the corresponding register bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port. Table

9 illustrates the various port configurations which can be selected by user software.

During MCU initialization, all I/O registers are cleared and the input mode with pull-up and no interrupt generation is selected for all the pins, thus avoiding pin conflicts.

Push-pull

Open-drain

Floating

Note : The open drain setting is not a true open drain. This means it has the same structure as the push-pull setting but the P-buffer is deactivated.

To avoid damaging the device, please respect the

OUT

absolute maximum rating described in the

Electrical Characteristics section.

7.2.1 Digital Input Modes

The input configuration is selected by clearing the Obsolete Product(s) - Obsolete Product(s)

In this case, reading the DR register returns the

7.2.4 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function (timer input/output...) is not systematically selected but has to be configdigital value applied to the external I/O pin.

ured through the DDR, OR and DR registers. Re-

Different input modes can be selected by software fer to the chapter describing the peripheral for through the DR and OR registers, see Table 9 .

more details.

External Interrupt Function

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ST6208C/ST6209C/ST6210C/ST6220C

I/O PORTS (Cont’d)

Figure 23. I/O Port Block Diagram

RESET

DATA

DIRECTION

DATA

ST6

INTERNAL

BUS

OPTION

PULL-UP

P-BUFFER

N-BUFFER

CLAMPING

DIODES

Pxx I/O Pin

TO INTERRUPT

TO ADC

* Depending on device. See device summary on page 1 .

CMOS

SCHMITT

TRIGGER

Table 9. I/O Port Configurations

Mode

Input

Option DDR

With pull-up, no interrupt

No pull-up, no interrupt

0 1 0 Input With pull-up and with interrupt

1 x

Input

Output

Analog input (when available)

Open-drain output (20mA sink when available)

1 1 x Output Push-pull output (20mA sink when available)

Note: x = Don’t care

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ST6208C/ST6209C/ST6210C/ST6220C

I/O PORTS (Cont’d)

7.2.5 Instructions NOT to be used to access

Port Data registers (SET, RES, INC and DEC)

DO NOT USE READ-MODIFY-WRITE INSTRUC-

TIONS (SET, RES, INC and DEC) ON PORT

DATA REGISTERS IF ANY PIN OF THE PORT IS

CONFIGURED IN INPUT MODE.

These instructions make an implicit read and write back of the entire register. In port input mode, however, the data register reads from the input pins directly, and not from the data register latches. Since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins.

As a general rule, it is better to only use single bit instructions on data registers when the whole (8bit) port is in output mode. In the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data register:

SET bit, datacopy

LD a, datacopy

LD DRA, a

7.2.6 Recommendations

1. Safe I/O State Switching Sequence

Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recommended safe transitions are illustrated in Figure 24

The Interrupt Pull-up to Input Analog transition

(and vice-vesra) is potentially risky and should be avoided when changing the I/O operating mode.

2. Handling Unused Port Bits

On ports that have less than 8 external pins connected:

– Leave the unbonded pins in reset state and do not change their configuration.

– Do not use instructions that act on a whole port register (INC, DEC, or read operations). Unavailable bits must be masked by software (AND instruction). Thus, when a read operation performed on an incomplete port is followed by a comparison, use a mask.

3. High Impedance Input

On any CMOS device, it is not recommended to connect high impedance on input pins. The choice of these impedance has to be done with respect to the maximum leakage current defined in the datasheet. The risk is to be close or out of specification on the input levels applied to the device.

7.3 LOW POWER MODES

The WAIT and STOP instructions allow the

ST62xx to be used in situations where low power consumption is needed. The lowest power consumption is achieved by configuring I/Os in output push-pull low mode.

Mode Description

WAIT

STOP

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts cause the device to exit from STOP mode.

7.4 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with

DDR, DR and OR registers (see Table 9 ) and the

GEN-bit in the IOR register is set.

Figure 24. Diagram showing Safe I/O State Transitions

Interrupt

010* 011

Input Obsolete Product(s) - Obsolete Product(s)

Input pull-up (Reset state)

000 001 Input

Output

Open Drain

100 101

Output

Open Drain

Output

Push-pull

110

Note *. xxx = DDR, OR, DR Bits respectively

111

Output

Push-pull

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ST6208C/ST6209C/ST6210C/ST6220C

I/O PORTS (Cont’d)

Table 10. I/O Port Option Selections

MODE AVAILABLE ON (1)

Input

PA0-PA3

PB0-PB7

DDRx

ORx

Reset state

Input with pull up

DRx

PA0-PA3

PB0-PB7

DDRx

ORx

Input with pull up with interrupt

DRx

PA0-PA3

PB0-PB7

DDRx

ORx

DRx

DDRx

Analog Input

ORx

DRx

PB0-PB3

(ST6210C/20C only)

PB4-PB7

(All devices, except ST6208C)

Open drain output (5mA) PB0-PB7

SCHEMATIC

ADC

Data in

Interrupt

Data in

Interrupt

Data in

Interrupt

Open drain output (20 mA) PA0-PA3

ORx

DRx

0/1

Push-pull output (5mA) PB0-PB7

Push-pull output (20 mA) PA0-PA3

DDRx

ORx

DRx

0/1

Note 1 . Provided the correct configuration has been selected (see

Table 9 ).

P-buffer disconnected

Data out

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ST6208C/ST6209C/ST6210C/ST6220C

I/O PORTS (Cont’d)

7.5 REGISTER DESCRIPTION

DATA REGISTER (DR)

Port x Data Register

DRx with x = A or B.

Address DRA: 0C0h - Read/Write

Address DRB: 0C1h - Read/Write

Reset Value: 0000 0000 (00h)

D7 D6 D5 D4 D3 D2 D1

Bits 7:0 = DD[7:0] Data direction register bits.

The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software.

0: Input mode

1: Output mode

Bits 7:0 = D[7:0] Data register bits.

Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input).

Caution: In input mode, modifying this register will modify the I/O port configuration (see

Table 9 ).

Do not use the Single bit instructions on I/O port data registers. See (

Section 7.2.5

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register

DDRx with x = A or B.

Address DDRA: 0C4h - Read/Write

Address DDRB: 0C5h - Read/Write

Reset Value: 0000 0000 (00h)

7 0

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

OPTION REGISTER (OR)

Port x Option Register

ORx with x = A or B.

Address ORA: 0CCh - Read/Write

Address ORB: 0CDh - Read/Write

Reset Value: 0000 0000 (00h)

7 0

O7 O6 O5 O4 O3 O2 O1 O0

Bits 7:0 = O[7:0] Option register bits.

The OR register allows to distinguish in output mode if the push-pull or open drain configuration is selected.

Output mode:

0: Open drain output(with P-Buffer deactivated)

1: Push-pull Output

Input mode: See Table 9

Each bit is set and cleared by software.

Caution: Modifying this register, will also modify

the I/O port configuration in input mode. (see Table 9 ).

Table 11. I/O Port Register Map and Reset Values

Address Register

7 6 5 4 3 2 1 Obsolete Product(s) - Obsolete Product(s)

Reset Value

0 0 0 0 0 0 0 0 of all I/O port registers

0C0h DRA

MSB LSB

0C1h DRB

0C4h

0C5h

0CCh

0CDh

DDRA

DDRB

ORA

ORB

MSB

LSB

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ST6208C/ST6209C/ST6210C/ST6220C

8 ON-CHIP PERIPHERALS

8.1 WATCHDOG TIMER (WDG)

8.1.1 Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the SR bit becomes cleared.

Figure 25. Watchdog Block Diagram

8.1.2 Main Features

■ Programmable timer (64 steps of 3072 clock cycles)

■

Software reset

Reset (if watchdog activated) when the SR bit reaches zero

Hardware or software watchdog activation selectable by option bit (Refer to the option bytes section)

RESET f int /12

T0 bit 7

WATCHDOG REGISTER (WDGR)

T1 T2 T3 T4

7-BIT DOWNCOUNTER

T5 SR C bit 0

CLOCK DIVIDER

256

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ST6208C/ST6209C/ST6210C/ST6220C

WATCHDOG TIMER (Cont’d)

8.1.3 Functional Description

The watchdog activation is selected through an option in the option bytes:

– HARDWARE Watchdog option

After reset, the watchdog is permanently active, the C bit in the WDGR is forced high and the user can not change it. However, this bit can be read equally as 0 or 1.

– SOFTWARE Watchdog option

After reset, the watchdog is deactivated. The function is activated by setting C bit in the WDGR register. Once activated, it cannot be deactivated.

The counter value stored in the WDGR register

(bits SR:T0), is decremented every 3072 clock cycles. The length of the timeout period can be programmed by the user in 64 steps of 3072 clock cycles.

If the watchdog is activated (by setting the C bit) and when the SR bit is cleared, the watchdog initiates a reset cycle pulling the reset pin low for typically 500ns.

The application program must write in the WDGR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the WDGR register must be between

FEh and 02h (see Table 12 ). To run the watchdog function the following conditions must be true:

– The C bit is set (watchdog activated)

– The SR bit is set to prevent generating an immediate reset mode availability (refer to the description of the

WDACT and EXTCNTL bits on the Option Bytes).

When STOP mode is not required, hardware activation without EXTERNAL STOP MODE CON-

TROL should be preferred, as it provides maximum security, especially during power-on.

When STOP mode is required, hardware activation and EXTERNAL STOP MODE CONTROL should be chosen. NMI should be high by default, to allow STOP mode to be entered when the MCU is idle.

The NMI pin can be connected to an I/O line (see

Figure 26 ) to allow its state to be controlled by software. The I/O line can then be used to keep NMI low while Watchdog protection is required, or to avoid noise or key bounce. When no more processing is required, the I/O line is released and the device placed in STOP mode for lowest power consumption.

Figure 26. A typical circuit making use of the

EXERNAL STOP MODE CONTROL feature

SWITCH

NMI

I/O

– The T[5:0] bits contain the number of decrements which represent the time delay before the watchdog produces a reset.

VR02002

Table 12. Watchdog Timing (f

OSC

= 8 MHz)

2. When software activation is selected (WDACT

WDGR Register WDG timeout period bit in Option byte) and the Watchdog is not activatinitial value (ms) ed, the downcounter may be used as a simple 7-

Max.

FEh 24.576

Min.

02h 0.384

Obsolete Product(s) - Obsolete Product(s)

8.1.3.1 Software Reset bit timer (remember that the bits are in reverse order).

The software activation option should be chosen only when the Watchdog counter is to be used as

The SR bit can be used to generate a software rea timer. To ensure the Watchdog has not been unset by clearing the SR bit while the C bit is set.

expectedly activated, the following instructions should be executed: 8.1.4 Recommendations jrr 0, WDGR, #+3 ; If C=0,jump to next 1. The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices, and should be used wherever possible. Watchdog related options should be selected on the basis of a trade-off between application security and STOP ldi WDGR, 0FDH ; SR=0 -> reset next :

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ST6208C/ST6209C/ST6210C/ST6220C

WATCHDOG TIMER (Cont’d)

These instructions test the C bit and reset the

MCU (i.e. disable the Watchdog) if the bit is set

(i.e. if the Watchdog is active), thus disabling the

Watchdog.

For more information on the use of the watchdog, please read application note AN1015.

Note: This note applies only when the watchdog is used as a standard timer. It is recommended to read the counter twice, as it may sometimes return an invalid value if the read is performed while the counter is decremented (counter bits in transient state). To validate the return value, both values read must be equal. The counter decrements every 384 µs at 8 MHz f

OSC

8.1.5 Low Power Modes

Mode Description

WAIT No effect on Watchdog.

STOP Behaviour depends on the EXTCNTL option in the Option bytes:

1. Watchdog disabled:

The MCU will enter Stop mode if a STOP instruction is executed.

2. Watchdog enabled and EXTCNTL option disabled:

If a STOP instruction is encountered, it is interpreted as a WAIT.

3. Watchdog and EXTCNTL option enabled:

If a STOP instruction is encountered when the NMI pin is low, it is interpreted as a WAIT. If, however, the

STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU enters STOP mode.

When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity.

8.1.6 Interrupts

None.

Obsolete Product(s) - Obsolete Product(s)

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ST6208C/ST6209C/ST6210C/ST6220C

WATCHDOG TIMER (Cont’d)

8.1.7 Register Description

WATCHDOG REGISTER (WDGR)

Address: 0D8h - Read/Write

Reset Value: 1111 1110 (FEh)

T0 T1 T2 T3 T4 T5 SR

Bits 7:2 = T[5:0] Downcounter bits

Caution: These bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the

LSB of the Watchdog downcounter and bit-2 (T5) is the MSB.

Bit 1 = SR : Software Reset bit

Software can generate a reset by clearing this bit while the C bit is set. When C = 0 (Watchdog deactivated) the SR bit is the MSB of the 7-bit timer.

0: Generate (write)

1: No software reset generated, MSB of 7-bit timer

Bit 0 = C Watchdog Control bit .

If the hardware option is selected (WDACT bit in

Option byte), this bit is forced high and cannot be changed by the user (the Watchdog is always active). When the software option is selected

(WDACT bit in Option byte), the Watchdog function is activated by setting the C bit, and cannot then be deactivated (except by resetting the

MCU).

When C is kept cleared the counter can be used as a 7-bit timer.

0: Watchdog deactivated

1: Watchdog activated

Obsolete Product(s) - Obsolete Product(s)

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ST6208C/ST6209C/ST6210C/ST6220C

8.2 8-BIT TIMER

8.2.1 Introduction

The 8-Bit Timer on-chip peripheral is a free running downcounter based on an 8-bit downcounter with a 7-bit programmable prescaler, giving a maximum count of 2

. The peripheral may be configured in three different operating modes.

8.2.2 Main Features

■ Time-out downcounting mode with up to 15-bit accuracy

■

External counter clock source (valid also in

STOP mode)

Interrupt capability on counter underflow

■

Output signal generation

External pulse length measurement

Event counter

The timer can be used in WAIT and STOP modes to wake up the MCU.

Figure 27. Timer Block Diagram

TIMER

PIN f

INT/12

7 8-BIT DOWN COUNTER 0

TCR

TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 f

COUNTER f

EXT LATCH

TMZ ETI TOUT DOUT PSI PS2 PS1

PS0

TSCR

INTERRUPT f

PRESCALER

Obsolete Product(s) - Obsolete Product(s)

7 PSCR REGISTER 0

PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1 PSCR0

/128 /64 /32 /16 /8 /4 /2

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PROGRAMMABLE PRESCALER

ST6208C/ST6209C/ST6210C/ST6220C

8-BIT TIMER (Cont’d)

8.2.3 Counter/Prescaler Description

Counter

The free running 8-bit downcounter is fed by the output of the programmable prescaler, and is decremented on every rising edge of the f

COUNTER clock signal coming from the prescaler.

It is possible to read or write the contents of the counter on the fly, by reading or writing the timer counter register (TCR).

When the downcounter reaches 0, it is automatically reloaded with the value 0FFh.

caler and the counter run at the rate of the selected clock source.

Prescaler

The prescaler input can be the internal frequency f

INT

divided by 12 or an external clock applied to the TIMER pin. The prescaler decrements on the rising edge, depending on the division factor programmed by the PS[2:0] bits in the TSCR register.

The state of the 7-bit prescaler can be read in the

PSCR register.

When the prescaler reaches 0, it is automatically reloaded with 7Fh.

Counter and Prescaler Initialization

After RESET, the counter and the prescaler are initialized to 0FFh and 7Fh respectively.

The 7-bit prescaler can be initialized to 7Fh by clearing the PSI bit. Direct write access to the prescaler is also possible when PSI =1. Then, any value between 0 and 7Fh can be loaded into it.

The 8-bit counter can be initialized separately by writing to the TCR register.

8.2.3.1 8-bit Counting and Interrupt Capability on Counter Underflow

Whatever the division factor defined for the prescaler, the Timer Counter works as an 8-bit downcounter. The input clock frequency is user selectable using the PS[2:0] bits.

When the downcounter decrements to zero, the

TMZ (Timer Zero) bit in the TSCR is set. If the ETI

(Enable Timer Interrupt) bit in the TSCR is also set, an interrupt request is generated.

The Timer interrupt can be used to exit the MCU from WAIT or STOP mode.

Counter Clock and Prescaler

The counter clock frequency is given by: f

COUNTER

= f

PRESCALER

/ 2

PS[2:0] where f

PRESCALER can be:

The TCR can be written at any time by software to define a time period ending with an underflow event, and therefore manage delay or timer functions.

– f

INT

/12 however, it may also be set by writing 00h in the – f

EXT

(input on TIMER pin)

TCR register or by setting bit 7 of the TSCR register.

– f

INT

/12 gated by TIMER pin

The timer input clock feeds the 7-bit programmable prescaler. The prescaler output can be pro-

The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service grammed by selecting one of the 8 available presroutine. caler taps using the PS[2:0] bits in the Status/Control Register (TSCR). Thus the division factor of the prescaler can be set to 2 n

(where n equals 0, to

Note : A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a TCR register decrement to 00h 7). See Figure 27 .

The clock input is enabled by the PSI (Prescaler Obsolete Product(s) - Obsolete Product(s) set, the counter is frozen and the prescaler is loadoccur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter underflows again.

ed with the value 7Fh. When PSI is set, the pres-

TMZ is set when the downcounter reaches zero;

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ST6208C/ST6209C/ST6210C/ST6220C

8-BIT TIMER (Cont’d)

8.2.4 Functional Description

There are three operating modes, which are selected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the 7-bit prescaler (f

INT

÷ 12 or TIMER pin signal), and to the output mode.

The settings for the different operating modes are summarized Table 13 .

Table 13. Timer Operating Modes

TOUT DOUT

Timer

Function

Event Counter

(input)

Gated input

(input)

Output “0”

(output)

Output “1”

(output)

Application

External counter clock source

External Pulse length measurement

Output signal generation

8.2.4.1 Gated Mode

(TOUT = “0”, DOUT = “1”)

In this mode, the prescaler is decremented by the

Timer clock input, but only when the signal on the

TIMER pin is held high (f

INT

/12 gated by TIMER pin). See Figure 28 and Figure 29 .

This mode is selected by clearing the TOUT bit in the TSCR register (i.e. as input) and setting the

DOUT bit.

Note: In this mode, if the TIMER pin is multiplexed, the corresponding port control bits have to be set in input with pull-up configuration through the DDR, OR and DR registers. For more details, please refer to the I/O Ports section.

Figure 28. f

TIMER

Clock in Gated Mode f

INT

/12 f

PRESCALER

TIMER f

EXT

Figure 29. Gated Mode Operation

COUNTER VALUE xx1

VALUE 1 xx2

TIMER PIN

TIMER CLOCK

PULSE LENGTH

VALUE 2

Obsolete Product(s) - Obsolete Product(s)

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ST6208C/ST6209C/ST6210C/ST6220C

8-BIT TIMER (Cont’d)

8.2.4.2 Event Counter Mode

(TOUT = “0”, DOUT = “0”)

In this mode, the TIMER pin is the input clock of the Timer prescaler which is decremented on every rising edge of the input clock (allowing event count). See Figure 30 and Figure 31 .

This mode is selected by clearing the TOUT bit in the TSCR register (i.e. as input) and clearing the

DOUT bit.

Note: In this mode, if the TIMER pin is multiplexed, the corresponding port control bits have to be set in input with pull-up configuration.

Figure 30. f

TIMER

Clock in Event Counter Mode bit transition is used to latch the DOUT bit in the

TSCR and, if the TOUT bit is set, DOUT is transferred to the TIMER pin. This operating mode allows external signal generation on the TIMER pin. See

Figure 33 .

This mode is selected by setting the TOUT bit in the TSCR register (i.e. as output) and setting the

DOUT bit to output a high level or clearing the

DOUT bit to output a low level.

Note: As soon as the TOUT bit is set, The timer pin is configured as output push-pull regardless of the corresponding I/O port control registers setting

(if the TIMER pin is multiplexed).

Figure 32. Output Mode Control

TIMER f

PRESCALER TIMER

LATCH

Figure 31. Event Counter Mode Operation

COUNTER VALUE

XX1

VALUE 1

XX2

TIMER PIN

VALUE 2

TMZ TOUT DOUT

Figure 33. Output Mode Operation

Counter

FFh

TIMER PIN

At each zero event

DOUT has to be copied to the TIMER

8.2.4.3 Output Mode

(TOUT = “1”, DOUT = “data out”) Obsolete Product(s) - Obsolete Product(s)

In Output mode, the TIMER pin is connected to the

DOUT latch, hence the Timer prescaler is clocked

1 by the prescaler clock input (f

INT

/12). See Figure 32 .

The user can select the prescaler division ratio using the PS[2:0] bits in the TSCR register. When TCR decrements to zero, it sets the TMZ bit in the TSCR.

The TMZ bit can be tested under program control to perform a timer function whenever it goes high and has to be cleared by the user. The low-to-high TMZ

1 st

downcount:

Default output value is 0

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ST6208C/ST6209C/ST6210C/ST6220C

8-BIT TIMER (Cont’d)

8.2.5 Low Power Modes

Mode Description

WAIT

STOP

No effect on timer.

Timer interrupt events cause the device to exit from WAIT mode.

Timer registers are frozen except in Event

Counter mode (with external clock on TIM-

ER pin).

8.2.6 Interrupts

Interrupt Event

Timer Zero

Event

Event

Flag

TMZ

Enable

Bit

ETI

Exit from

Wait

Yes

Exit from

Stop

Yes

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ST6208C/ST6209C/ST6210C/ST6220C

8-BIT TIMER (Cont’d)

8.2.7 Register Description

PRESCALER COUNTER REGISTER (PSCR)

Address: 0D2h - Read/Write

Reset Value: 0111 1111 (7Fh)

7 0

PSCR

Bit 7 = PSCR7:

Bits 6:0 =

Not used, always read as “0”.

PSCR[6:0] Prescaler LSB.

ETI=0 the timer interrupt is disabled. If ETI=1 and

TMZ=1 an interrupt request is generated.

0: Interrupt disabled (reset state)

1: Interrupt enabled

Bit 5 = TOUT Timer Output Control .

When low, this bit selects the input mode for the

TIMER pin. When high the output mode is selected.

0: Input mode (reset state)

1: Output mode, the TIMER pin is configured as push-pull output

TIMER COUNTER REGISTER (TCR)

Address: 0D3h - Read / Write

Reset Value: 1111 1111 (FFh)

7 0

Bit 4 = DOUT Data Output.

Data sent to the timer output when TMZ is set high

(output mode only). Input mode selection (input mode only).

TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0

Bits 7:0 = TCR[7:0] Timer counter bits.

TIMER STATUS CONTROL REGISTER (TSCR)

Address: 0D4h - Read/Write

Reset Value: 0000 0000 (00h)

7 0

Bit 3 = PSI : Prescaler Initialize bit.

Used to initialize the prescaler and inhibit its counting. When PSI=“0” the prescaler is set to 7Fh and the counter is inhibited. When PSI=“1” the prescaler is enabled to count downwards. As long as

PSE=“1” both counter and prescaler are not running

0: Counting disabled

1: Counting enabled

TMZ

Bit 7 =

ETI TOUT DOUT PSI

TMZ Timer Zero bit.

A low-to-high transition indicates that the timer count register has underflowed. It means that the

TCR value has changed from 00h to FFh.

This bit must be cleared by user software.

0: Counter has not underflowed

1: Counter underflow occurred

PS2 PS1 PS0

When set, enables the timer interrupt request. If

Bits 1:0 = PS[2:0] Prescaler Mux. Select.

These bits select the division ratio of the prescaler register.

Table 14. Prescaler Division Factors

PS2

PS1

PS0

Divided by

128

Table 15. 8-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register Label 7 6 5

0D2h

0D3h

0D4h

PSCR

Reset Value

TCR

Reset Value

TSCR

Reset Value

PSCR7

TCR7

TMZ

PSCR6

TCR6

ETI

PSCR5

TCR5

TOUT

4 3

PSCR4

TCR4

DOUT

PSCR3

TCR3

PSI

PSCR2

TCR2

PS2

PSCR1

TCR1

PS1

PSCR0

TCR0

PS0

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8.3 A/D CONVERTER (ADC)

8.3.1 Introduction

The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources.

The result of the conversion is stored in a 8-bit

Data Register. The A/D converter is controlled through a Control Register.

8.3.2 Main Features

■ 8-bit conversion

■ Multiplexed analog input channels

■

Linear successive approximation

Data register (DR) which contains the results

End of Conversion flag

On/Off bit (to reduce consumption)

Typical conversion time 70 µs (with an 8 MHz crystal)

The block diagram is shown in Figure 34 .

Figure 34. ADC Block Diagram f

INT f

ADC

DIV 12

EAI EOC STA PDS

CR3

OSC

OFF

CR1

CR0

ADCR

I/O PORT

AIN0

AIN1

PORT

MUX

ANALOG TO DIGITAL

CONVERTER

AINx

DDRx

ORx

DRx

ADR

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

Obsolete Product(s) - Obsolete Product(s)

Note: ADC not present on some devices. See device summary on page 1.

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A/D CONVERTER (Cont’d)

8.3.3 Functional Description

8.3.3.1 Analog Power Supply

The high and low level reference voltage pins are internally connected to the V

and V

pins.

Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines.

8.3.3.4 Software Procedure

Refer to the Control register (ADCR) and Data register (ADR) in Section 8.3.7

for the bit definitions.

Analog Input Configuration

The analog input must be configured through the

Port Control registers (DDRx, ORx and DRx). Refer to the I/O port chapter.

8.3.3.2 Digital A/D Conversion Result ADC Configuration

In the ADCR register: The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not.

If the input voltage (V

AIN to V

DDA

) is greater than or equal

(high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication.

– Reset the PDS bit to power on the ADC. This bit must be set at least one instruction before the beginning of the conversion to allow stabilisation of the A/D converter.

– Set the EAI bit to enable the ADC interrupt if needed.

If input voltage (V

AIN

SSA

) is lower than or equal to

(low-level voltage reference) then the conversion result in the DR register is 00h.

ADC Conversion

In the ADCR register:

The A/D converter is linear and the digital result of the conversion is stored in the ADR register. The accuracy of the conversion is described in the parametric section.

– Set the STA bit to start a conversion. This automatically clears (resets to “0”) the End Of Conversion Bit (EOC).

When a conversion is complete

– The EOC bit is set by hardware to flag that conR

AIN

is the maximum recommended impedance for an analog input signal. If the impedance is too version is complete and that the data in the ADC high, this will result in a loss of accuracy due to data conversion register is valid. leakage and sampling not being completed in the

– An interrupt is generated if the EAI bit was set allocated time. Refer to the electrical characteris-

Setting the STA bit will start a new count and will tics chapter for more details.

clear the EOC bit (thus clearing the interrupt con-

With an oscillator clock frequency less than dition)

1.2MHz, conversion accuracy is decreased.

Note:

8.3.3.3 Analog Input Selection

Setting the STA bit must be done by a different in-

Selection of the input pin is done by configuring struction from the instruction that powers-on the the related I/O line as an analog input via the Data

ADC (setting the PDS bit) in order to make sure

Direction, Option and Data registers (refer to I/O the voltage to be converted is present on the pin.

ports description for additional information).

Each conversion has to be separately initiated by

Caution: Only one I/O line must be configured as writing to the STA bit.

an analog input at any time. The user must avoid any situation in which more than one I/O pin is se-

The STA bit is continuously scanned so that, if the

Obsolete Product(s) - Obsolete Product(s) pleting the previous one. The start bit (STA) is a write only bit, any attempt to read it will show a logical “0”.

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A/D CONVERTER (Cont’d)

8.3.4 Recommendations

The following six notes provide additional information on using the A/D converter.

1.The A/D converter does not feature a sample and hold circuit. The analog voltage to be measured should therefore be stable during the entire conversion cycle. Voltage variation should not exceed ±1/2 LSB for optimum conversion accuracy.

A low pass filter may be used at the analog input pins to reduce input voltage variation during conversion.

2. When selected as an analog channel, the input pin is internally connected to a capacitor C ad

of typically 9pF. For maximum accuracy, this capacitor must be fully charged at the beginning of conversion. In the worst case, conversion starts one instruction (6.5 µs) after the channel has been selected. The impedance of the analog voltage source (ASI) in worst case conditions, is calculated using the following formula:

6.5µs = 9 x C ad

x ASI

(capacitor charged to over 99.9%), i.e. 30 k

including a 50% guardband.

The ASI can be higher if C ad

has been charged for a longer period by adding instructions before the start of conversion (adding more than 26 CPU cycles is pointless).

bances and power supply variations due to output switching. Nevertheless, the WAIT instruction should be executed as soon as possible after the beginning of the conversion, because execution of the WAIT instruction may cause a small variation of the V

voltage. The negative effect of this variation is minimized at the beginning of the conversion when the converter is less sensitive, rather than at the end of conversion, when the least significant bits are determined.

The best configuration, from an accuracy standpoint, is WAIT mode with the Timer stopped. In this case only the ADC peripheral and the oscillator are then still working. The MCU must be woken up from WAIT mode by the ADC interrupt at the end of the conversion. The microcontroller can also be woken up by the Timer interrupt, but this means the Timer must be running and the resulting noise could affect conversion accuracy.

Caution: When an I/O pin is used as an analog input, A/D conversion accuracy will be impaired if negative current injections (V

INJ

< V

) occur from adjacent I/O pins with analog input capability. Refer to Figure 35 . To avoid this:

– Use another I/O port located further away from the analog pin, preferably not multiplexed on the

A/D converter

3. Since the ADC is on the same chip as the microprocessor, the user should not switch heavily loaded output signals during conversion, if high precision is required. Such switching will affect the supply voltages used as analog references.

– Increase the input resistance R

IN J

(to reduce the current injections) and reduce R

ADC conversion accuracy).

(to preserve

Figure 35. Leakage from Digital Inputs

4. Conversion accuracy depends on the quality of the power supplies (V

and V

). The user must take special care to ensure a well regulated reference voltage is present on the V

and V

pins

(power supply voltage variations must be less than

0.1V/ms). This implies, in particular, that a suitable decoupling capacitor is used at the V

The converter resolution is given by:

pin.

– V

--------------------------------

256 V

INJ

Digital

Input

INJ

PBy/AINy

I/O Port

(Digital I/O) Obsolete Product(s) - Obsolete Product(s)

Leakage Current if V

INJ

< V

SS The Input voltage (Ain) which is to be converted must be constant for 1µs before conversion and remain constant during conversion.

Analog

Input

PBx/AINx

5. Conversion resolution can be improved if the power supply voltage (V

DD is lowered.

) to the microcontroller

ADC A/D

Converter

AIN

6. In order to optimize the conversion resolution, the user can configure the microcontroller in WAIT mode, because this mode minimises noise distur-

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A/D CONVERTER (Cont’d)

8.3.5 Low Power Modes

Mode Description

WAIT

STOP

No effect on A/D Converter. ADC interrupts cause the device to exit from Wait mode.

A/D Converter disabled.

cally cleared when the STA bit is set. Data in the data conversion register are valid only when this bit is set to “1”.

0: Conversion is not complete

1: Conversion can be read from the ADR register

Note : The A/D converter may be disabled by clearing the PDS bit. This feature allows reduced power consumption when no conversion is needed.

8.3.6 Interrupts

Interrupt Event

End of Conversion

Event

Flag

EOC

Enable

Bit

EAI

Exit from

Wait

Yes

Exit from

Stop

Note: The EOC bit is cleared only when a new conversion is started (it cannot be cleared by writing 0). To avoid generating further EOC interrupt, the EAI bit has to be cleared within the ADC interrupt subroutine.

8.3.7 Register Description

A/D CONVERTER CONTROL REGISTER (AD-

CR)

Address: 0D1h - Read/Write (Bit 6 Read Only, Bit

5 Write Only)

Reset value: 0100 0000 (40h)

Bit 5 = STA : Start of Conversion. Write Only .

0: No effect

1: Start conversion

Note: Setting this bit automatically clears the EOC bit. If the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. This bit is write only, any attempt to read it will show a logical zero.

Bit 4 = PDS Power Down Selection.

0: A/D converter is switched off

1: A/D converter is switched on

Bit 3 =

Bit 2 =

ADCR3

OSCOFF Main Oscillator off.

0: Main Oscillator enabled

1: Main Oscillator disabled

Note: This bit does not apply to the ADC peripheral but to the main clock system. Refer to the Clock

System section.

Reserved , must be cleared.

7 0

Bits 1:0 = ADCR[1:0] Reserved , must be cleared.

EAI EOC STA PDS

ADCR

OSC

OFF

ADCR

Bit 7 = EAI Enable A/D Interrupt.

0: ADC interrupt disabled

1: ADC interrupt enabled

A/D CONVERTER DATA REGISTER (ADR)

Address: 0D0h - Read only

Reset value: xxxx xxxx (xxh)

7 0

Bit 6 = EOC End of conversion.

Read Only

Obsolete Product(s) - Obsolete Product(s) ated if the EAI bit is set. The EOC bit is automati-

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

Bits 7:0 = ADR[7:0] : 8 Bit A/D Conversion Result.

Table 16. ADC Register Map and Reset Values

Address

(Hex.)

0D0h

0D1h

Register

Label

ADR

Reset Value

ADCR

Reset Value

ADR7

EAI

ADR6

EOC

ADR5

STA

ADR4

PDS

3 2 1 0

ADR3

ADCR3

ADR2

OSCOFF

ADR1

ADCR1

ADR0

ADCR0

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9 INSTRUCTION SET

9.1 ST6 ARCHITECTURE

The ST6 architecture has been designed for maximum efficiency while keeping byte usage to a minimum; in short, to provide byte-efficient programming. The ST6 core has the ability to set or clear any register or RAM location bit in Data space using a single instruction. Furthermore, programs can branch to a selected address depending on the status of any bit in Data space.

9.2 ADDRESSING MODES

The ST6 has nine addressing modes, which are described in the following paragraphs. Three different address spaces are available: Program space, Data space, and Stack space. Program space contains the instructions which are to be executed, plus the data for immediate mode instructions. Data space contains the Accumulator, the X,

Y, V and W registers, peripheral and Input/Output registers, the RAM locations and Data ROM locations (for storage of tables and constants). Stack space contains six 12-bit RAM cells used to stack the return addresses for subroutines and interrupts.

tended addressing mode are able to branch to any address in the 4 Kbyte Program space.

Extended addressing mode instructions are two bytes long.

Program Counter Relative . Relative addressing mode is only used in conditional branch instructions. The instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations next to the address of the relative instruction. If the condition is not true, the instruction which follows the relative instruction is executed. Relative addressing mode instructions are one byte long. The opcode is obtained by adding the three most significant bits which characterize the test condition, one bit which determines whether it is a forward branch (when it is 0) or backward branch (when it is 1) and the four least significant bits which give the span of the branch (0h to Fh) which must be added or subtracted from the address of the relative instruction to obtain the branch destination address.

Immediate . In immediate addressing mode, the operand of the instruction follows the opcode location. As the operand is a ROM byte, the immediate addressing mode is used to access constants which do not change during program execution

(e.g., a constant used to initialize a loop counter).

Direct . In direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. Direct addressing allows the user to directly address the 256 bytes in Data Space memory with a single two-byte instruction.

Bit Direct . In bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the address of the byte in which the specified bit must be set or cleared. Thus, any bit in the 256 locations of Data space memory can be set or cleared.

Bit Test & Branch . Bit test and branch addressing mode is a combination of direct addressing and relative addressing. Bit test and branch instructions are three bytes long. The bit identification and the test condition are included in the opcode byte. The address of the byte to be tested is given in the next byte. The third byte is the jump displacement, which is in the range of -127 to +128.

This displacement can be determined using a label, which is converted by the assembler.

Short Direct . The core can address the four RAM registers X, Y, V, W (locations 80h, 81h, 82h, 83h) in short-direct addressing mode. In this case, the instruction is only one byte and the selection of the Obsolete Product(s) - Obsolete Product(s) code. Short direct addressing is a subset of direct

Indirect . In indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed to by the content of one of the indirect registers, X or Y (80h, 81h). The indirect addressing mode. (Note that 80h and 81h are also indirect registers).

Extended . In extended addressing mode, the 12bit address needed to define the instruction is obtained by concatenating the four least significant bits of the opcode with the byte following the opcode. The instructions (JP, CALL) which use ex-

Inherent . In inherent addressing mode, all the information necessary for executing the instruction is contained in the opcode. These instructions are one byte long.

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9.3 INSTRUCTION SET

The ST6 offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following paragraphs describe the different types.

All the instructions belonging to a given type are presented in individual tables.

Table 17. Load & Store Instructions

Instruction

LD A, X

LD A, Y

LD A, V

LD A, W

LD X, A

LD Y, A

LD V, A

LD W, A

LD A, rr

LD rr, A

LD A, (X)

LD A, (Y)

LD (X), A

LD (Y), A

LDI A, #N

LDI rr, #N

Legend:

X, Y Index Registers,

V, W Short Direct Registers

# Immediate data (stored in ROM memory) rr Data space register

Affected

Addressing Mode

Short Direct

Direct

Indirect

Immediate

Load & Store . These instructions use one, two or three bytes depending on the addressing mode.

For LOAD, one operand is the Accumulator and the other operand is obtained from data memory using one of the addressing modes.

For Load Immediate, one operand can be any of the 256 data space bytes while the other is always immediate data.

Bytes

Cycles

Flags

Obsolete Product(s) - Obsolete Product(s)

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INSTRUCTION SET (Cont’d)

Arithmetic and Logic . These instructions are used to perform arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulator while, depending on the addressing mode, the other can be either a data space memory location or an immediate value. In CLR, DEC, INC instructions the operand can be any of the 256 data space addresses. In COM, RLC, SLA the operand is always the accumulator.

Table 18. Arithmetic & Logic Instructions

Flags

Instruction

ADD A, (X)

ADD A, (Y)

ADD A, rr

ADDI A, #N

AND A, (X)

AND A, (Y)

AND A, rr

ANDI A, #N

CLR A

Addressing Mode

Indirect

Direct

Immediate

Indirect

Direct

Immediate

Short Direct

Bytes

Cycles

4 rr Data space register

CLR r

COM A

CP A, (X)

CP A, (Y)

CP A, rr

CPI A, #N

DEC X

DEC Y

DEC V

DEC W

DEC A

DEC rr

DEC (X)

DEC (Y)

INC X

INC Y

Direct

Inherent

Indirect

Direct

Immediate

Short Direct

Direct

Indirect

Short Direct

INC V Short Direct 1 4 *

INC W Short Direct 1 4 *

INC A

INC rr

Direct

INC (X) Indirect 1 4

INC (Y) Indirect 1 4 *

Δ Δ

RLC A Inherent 1 4

SLA A

SUB A, (X)

SUB A, (Y)

SUB A, rr

Inherent

Indirect

Direct

SUBI A, #N Immediate 2 4

Notes:

X,Y Index Registers

V, W Short Direct Registers

Affected

# Immediate data (stored in ROM memory)

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INSTRUCTION SET (Cont’d)

Conditional Branch . Branch instructions perform a branch in the program when the selected condition is met.

Control Instructions . Control instructions control microcontroller operations during program execution.

Bit Manipulation Instructions . These instructions can handle any bit in Data space memory.

One group either sets or clears. The other group

(see Conditional Branch) performs the bit test branch operations.

Table 19. Conditional Branch Instructions

Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutine calls to any location in the whole program space.

Flags

Instruction Branch If

JRC e

JRNC e

JRZ e

JRNZ e

JRR b, rr, ee

JRS b, rr, ee

C = 1

C = 0

Z = 1

Z = 0

Bit = 0

Bit = 1

Notes

: b 3-bit address e 5 bit signed displacement in the range -15 to +16 ee 8 bit signed displacement in the range -126 to +129

Bytes

Cycles

5 rr Data space register

Affected. The tested bit is shifted into carry.

* Not Affected

Table 20. Bit Manipulation Instructions

Flags

Instruction

SET b,rr

RES b,rr

Addressing Mode

Bit Direct

Bytes

Cycles

Notes: b 3-bit address * Not Affected rr Data space register

Bit Manipulation Instructions should not be used on Port Data Registers and any registers with read only and/or write only bits (see I/O port chapter)

Table 21. Control Instructions

Flags

Instruction Addressing Mode Bytes Cycles

Z C

NOP Inherent 1 2 * *

RET Inherent 1 2 *

RETI Inherent 1 2

STOP

(1)

Obsolete Product(s) - Obsolete Product(s)

Notes:

Inherent

This instruction is deactivated and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.

Affected *Not

Table 22. Jump & Call Instructions

Flags

Instruction Addressing Mode Bytes Cycles

CALL abc

JP abc

Notes: abc 12-bit address

Extended

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Opcode Map Summary.

The following table contains an opcode map for the instructions used by the ST6

LOW LOW

0000

0001

0010

0011

0100

0101

0110

0111

HI HI

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1111

1 e e e e e e e e e e e e e e e e

JRNZ 4 pcr 2

JRNZ 4 pcr 2 e

JRNC 5 JRR 2 b0,rr,ee e pcr 3

JRNC 5 bt 1

JRS 2 b0,rr,ee e pcr 3

JRNC 5 b4,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 pcr 3 bt 1

JRS 2 b4,rr,ee e bt 1 e

JRNC 5 JRR 2 b2,rr,ee e pcr 3

JRNC 5 bt 1

JRS 2 b2,rr,ee e pcr 3

JRNC 5 b6,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 b6,rr,ee bt 1

JRS 2 e pcr 3

JRNC 5 b1,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 b1,rr,ee bt 1

JRS 2 e pcr 3

JRNC 5 b5,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 b5,rr,ee bt 1

JRS 2 e pcr 3

JRNC 5 b3,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 b3,rr,ee bt 1

JRS 2 e pcr 3

JRNC 5 b7,rr,ee bt 1

JRR 2 e pcr 3

JRNC 5 b7,rr,ee bt 1

JRS 2 pcr 3 bt 1 ext 1

CALL 2 abc ext 1

CALL 2 abc

JRZ e NOP pcr

JRZ 4 e pcr 1

JRZ e pcr

JRZ 4 e e e e e e e e e e e e pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

# x

# a,x

# y

# a,y

# v

# a,v

# w

# a,w

INC 2 sd 1

LD 2 sd 1

INC 2 sd 1

LD 2 sd 1

INC 2 sd 1

LD 2 sd 1

INC 2 sd 1

LD 2 sd 1 e e e e e e e e e e e e e e e e

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC prc

JRC 4 prc 1

JRC prc

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC prc a,(x)

AND ind

ANDI a,nn imm a,(x)

SUB ind

SUBI a,nn imm

DEC

(x) ind

LD a,(x) ind

LDI a,nn imm

CP a,(x) ind

CPI a,nn imm a,(x)

ADD ind

ADDI a,nn imm

INC

(x) ind

(x),a

LD ind

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Abbreviations for Addressing Modes: Legend: dir Direct sd Short Direct e 5-bit Displacement imm Immediate inh bt

Inherent ext Extended b.d Bit Direct

Bit Test b 3-bit rr 1-byte Data space address nn abc ee

1-byte immediate data

12-bit address

8-bit displacement pcr Program Counter Relative ind Indirect

Cycles

Operands

Bytes

Addressing Mode

1 e

JRC prc

Mnemonic

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Opcode Map Summary (Continued)

LOW

1000

1001

1010

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1111

1 e e e e e e e e e e e e e e e e

JRNZ 4 pcr 2

JRNZ 4 pcr 2 abc abc abc abc abc abc abc abc abc abc abc abc abc abc abc abc

JP 2 ext 1

JP 2 ext 1 e pcr 2

JRNC 4 e pcr 2

JRNC 4 pcr 2 e pcr 2

JRNC 4 e pcr 2

JRNC 4 e

JRNC 4 e pcr 2

JRNC 4

1011 b5,rr b.d 1

RES 2 b5,rr b.d 1

SET 2 b3,rr b.d 1

RES 2 b3,rr b.d 1

SET 2 b7,rr b.d 1

RES 2 b7,rr b.d 1

SET 2 b.d 1 b0,rr

RES 2 b0,rr b.d 1

SET 2 b4,rr b.d 1

RES 2 b4,rr b.d 1

SET 2 e b.d 1 b2,rr

RES 2 b2,rr b.d 1

SET 2 b6,rr b.d 1

RES 2 b6,rr b.d 1

SET 2 b1,rr b.d 1

RES 2 b1,rr b.d 1

SET 2

1100 e e e e e e e e e e e e e e e

JRZ 4 pcr 3

JRZ 4 pcr 1

JRZ 4 pcr

JRZ 4 pcr 1

JRZ 2 pcr 1

JRZ 4 pcr 1

JRZ 2 pcr 1

JRZ 4 pcr 1

JRZ pcr

JRZ 4 pcr 1

JRZ 2 pcr 1

JRZ 4 pcr 1

JRZ 2 pcr 1

JRZ 4 pcr 1

1101 w,a

LDI 2 rr,nn imm 1

DEC 2 x sd 1

COM 2 a

LD 2 x,a sd 1

RETI 2 inh 1

DEC 2 y sd 1

STOP 2 inh 1

LD 2 y,a sd 1

DEC 2 v sd 1

RCL 2 a inh 1

LD 2 v,a sd 1

RET 2 inh 1

DEC 2 w sd 1

WAIT 2 inh 1

LD 2 sd 1

1110 e e e e e e e e e e e e e e e e

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

JRC 4 prc 1

JRC 4 prc 2

1111

LD a,(y) ind

LD a,rr dir

CP a,(y) ind

CP a,rr a,(y) dir

ADD a,rr ind

ADD dir

INC

(y) ind

INC rr dir

(y),a ind

LD rr,a a,(y) dir

AND a,rr ind

AND a,(y) dir

SUB a,rr ind

SUB dir

DEC

(y) ind

DEC rr dir

LOW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Abbreviations for Addressing Modes: Legend: dir Direct sd Short Direct e 5-bit Displacement imm Immediate inh bt

Inherent ext Extended b.d Bit Direct

Bit Test b 3-bit rr 1-byte Data space address nn abc ee

1-byte immediate data

12-bit address

8-bit Displacement pcr Program Counter Relative ind Indirect

Cycles

Operands

Bytes

Addressing Mode

1 e

JRC prc

Mnemonic

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10 ELECTRICAL CHARACTERISTICS

10.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are referred to V

10.1.1 Minimum and Maximum Values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T

A and T

A range).

=25°C max (given by the selected temperature

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3

10.1.2 Typical Values

Unless otherwise specified, typical data are based on T

≤

=25°C, V

=5V (for the 4.5V

voltage range) and V

≤

6.0V

=3.3V (for the

≤

3.6V voltage range). They are given only as design guidelines and are not tested.

10.1.3 Typical Curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

10.1.4 Loading Capacitor

The loading conditions used for pin parameter measurement is shown in Figure 36 .

Figure 36. Pin Loading Conditions

ST6 PIN

10.1.5 Pin Input Voltage

The input voltage measurement on a pin of the device is described in Figure 37 .

Figure 37. Pin Input Voltage

ST6 PIN

Obsolete Product(s) - Obsolete Product(s)

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ST6208C/ST6209C/ST6210C/ST6220C

10.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi-

10.2.1 Voltage Characteristics tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

- V

OUT

ESD(HBM)

Ratings

Supply voltage

Input voltage on any pin

1) & 2)

Output voltage on any pin

1) & 2)

Electro-static discharge voltage (Human Body Model)

10.2.2 Current Characteristics

Maximum value

-0.3 to V

+0.3

-0.3 to V

+0.3

3500

Unit

Symbol

VDD

VSS

INJ(PIN)

2) & 4)

Ratings

Total current into V

power lines (source)

Total current out of V

ground lines (sink)

Output current sunk by any standard I/O and control pin

Output current sunk by any high sink I/O pin

Output current source by any I/Os and control pin

Injected current on RESET pin

Injected current on any other pin

Maximum value

100

± 5

Unit mA

10.2.3 Thermal Characteristics

Symbol

STG

Ratings

Storage temperature range

Maximum junction temperature

( see THERMAL CHARACTERISTICS section )

Value

-60 to +150

Unit

°C

Notes:

1. Directly connecting the RESET and I/O pins to V

or V

SS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k

Ω for RESET, 10k

for I/Os). Unused I/O pins must be tied in the same way to V

DD figuration.

or V

according to their reset con-

2. When the current limitation is not possible, the V

absolute maximum rating must be respected, otherwise refer to

INJ(PIN)

specification. A positive injection is induced by V

while a negative injection is induced by V

3. Power (V

) and ground (V

) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout Obsolete Product(s) - Obsolete Product(s) is lower than the specified limits).

- Pure digital pins must have a negative injection less than 1mA. In addition, it is recommended to inject the current as far as possible from the analog input pins.

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ST6208C/ST6209C/ST6210C/ST6220C

10.3 OPERATING CONDITIONS

10.3.1 General Operating Conditions

Symbol

DD f

OSC

Supply voltage

Parameter

Oscillator frequency

Operating Supply Voltage

Ambient temperature range

Conditions see Figure 38

=3.0V, 1 & 6 Suffix

=3.0V, 3 Suffix

=3.6V, 1 & 6Suffix

=3.6V, 3 Suffix f

OSC

=4MHz, 1 & 6 Suffix f

OSC

=4MHz, 3 Suffix f

OSC

=8MHz, 1 & 6 Suffix f

OSC

=8MHz, 3 Suffix

1 Suffix Version

6 Suffix Version

3 Suffix Version

Min

4.5

-40

3.0

3.6

Max

6.0

125

Unit

MHz

°C

Notes:

1. An oscillator frequency above 1.2MHz is recommended for reliable A/D results.

2. Operating conditions with T

=-40 to +125°C.

Figure 38. f

OSC

Maximum Operating Frequency Versus V

Supply Voltage for OTP & ROM devices f

OSC

[MHz]

1 & 6 suffix version

3 suffix version

3 f

OSG

2 f

OSG

Min

SUPPLY

) 2.5

3 3.6

4 4.5

1. In this area, operation is guaranteed at the quartz crystal frequency.

5.5

6 VOLTAGE (V

Obsolete Product(s) - Obsolete Product(s)

2. When the OSG is disabled, operation in this area is guaranteed at the crystal frequency. When the

OSG is enabled, operation in this area is guaranteed at a frequency of at least f

OSG

Min.

3. When the OSG is disabled, operation in this area is guaranteed at the quartz crystal frequency. When the OSG is enabled, access to this area is prevented. The internal frequency is kept at f

OSG

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OPERATING CONDITIONS (Cont’d)

10.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for V

, f

OSC

, and T

Symbol Parameter Conditions Min Typ

Max Unit

IT+

IT-

V hys

POR t g(VDD)

Reset release threshold

rise)

Reset generation threshold

fall)

LVD voltage threshold hysteresis

rise time rate

Filtered glitch delay on V

IT+

-V

IT-

Not detected by the LVD

3.9

3.6

4.1

3.8

300

4.3

700

V mV mV/s ns

Notes:

LVD typical data are based on T

=25°C. They are given only as design guidelines and are not tested.

2. The minimum V

rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.

3. Data based on characterization results, not tested in production.

Figure 39. LVD Threshold Versus V

and f

OSC

3) f

OSC

[MHz]

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

DEVICE UNDER

RESET

IN THIS AREA

2.5

3 3.5

IT-

≥

3.6

4 4.5

5 5.5

FUNCTIONAL AREA

SUPPLY

VOLTAGE [V]

Figure 40. Typical LVD Thresholds Versus

Temperature for OTP devices

Figure 41. Typical LVD thresholds vs.

Temperature for ROM devices

Thresholds [V]

4.2

Thresholds [V]

4.2

4 4

Obsolete Product(s) - Obsolete Product(s)

3.8

V 3.8

3.6

-40°C

3.6

-40°C 25°C

T [°C]

95°C 125°C 25°C

T [°C]

95°C 125°C

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10.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST6 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total de-

10.4.1 RUN Modes

Symbol Parameter

Supply current in RUN mode

(see Figure 42 & Figure 43 )

Supply current in RUN mode

(see Figure 42 & Figure 43 ) vice consumption, the two current values must be added (except for STOP mode for which the clock is stopped).

Conditions f f f f

OSC f

OSC

=32kHz

=1MHz

=2MHz

=4MHz

=8MHz f f f f

OSC f

OSC

=32kHz

=1MHz

=2MHz

=4MHz

=8MHz

Typ

Max

0.3

0.6

0.9

1.0

1.8

0.5

1.3

1.6

2.2

3.3

0.4

0.8

1.2

1.5

2.3

0.7

1.7

2.4

3.3

4.8

Unit mA

Notes:

Typical data are based on T

=25°C, V

=5V (4.5V

≤

6.0V range) and V

=3.3V (3V

≤

3.6V range).

Data based on characterization results, tested in production at V

max. and f

OSC

max.

3. CPU running with memory access, all I/O pins in input with pull-up mode (no load), all peripherals in reset state; clock input (OSC

) driven by external square wave, OSG and LVD disabled, option bytes not programmed.

Figure 42. Typical I

in RUN vs. f

CPU

IDD [mA]

8MHz

4MHz

2MHz

1MHz

32KHz

Figure 43. Typical I

= 5V)

in RUN vs. Temperature

IDD [mA]

3.5

2.5

8MHz

4MHz

2MHz

1MHz

32KHz

3 4

VDD [V]

5 6

1.5

0.5

-40 25

T[°C]

95 125

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

10.4.2 WAIT Modes

Symbol Parameter

Supply current in WAIT mode

Option bytes not programmed

(see Figure 44 )

Supply current in WAIT mode

Option bytes programmed to 00H

(see Figure 45 )

Supply current in WAIT mode

(see Figure 46

(see Figure 44 )

)

Supply current in WAIT mode

Option bytes not programmed

Supply current in WAIT mode

Option bytes not programmed

(see Figure 46 )

Option bytes programmed to 00H

(see Figure 45 )

Conditions f f f f

OSC f

OSC

=32kHz

=1MHz

=2MHz

=4MHz

=8MHz f f f f

OSC f

OSC

=32kHz

=1MHz

=2MHz

=4MHz

=8MHz f f f f

OSC f

OSC

=32kHz

=1MHz

=2MHz

=4MHz

=8MHz f f f f

OSC f

OSC

=32kHz

=1MHz

=2MHz

=4MHz

=8MHz f f f f

OSC f

OSC

=32kHz

=1MHz

=2MHz

=4MHz

=8MHz f f f f

OSC f

OSC

=32kHz

=1MHz

=2MHz

=4MHz

=8MHz

Unit

µA

Notes:

Typical data are based on T

=25°C, V

=5V (4.5V

≤

6.0V range) and V

=3.3V (3V

≤

3.6V range).

Data based on characterization results, tested in production at V

max. and f

OSC

max.

3. All I/O pins in input with pull-up mode (no load), all peripherals in reset state; clock input (OSC

IN square wave, OSG and LVD disabled.

) driven by external

Max

120

180

200

550

600

650

700

800

100

120

140

150

200

250

300

350

400

500

600

100

110

120

150

210

Typ

330

350

370

410

480

100

120

150

190

210

240

280

350

100

130

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

Figure 44. Typical I

DD programmed

in WAIT vs f

CPU

and Temperature for OTP devices with option bytes not

IDD [µA] IDD [µA]

800 700

700

8MHz

4MHz

2MHz

32KHz

600

8MHz

4MHz

2MHz

1MHz

32KHz

600

500

400

500

400

300

200

100

300

0 200

3 4 5 6 -40 25 95 125

VDD [V] T[°C]

Figure 45. Typical I

DD programmed to 00H

in WAIT vs f

CPU

and Temperature for OTP devices with option bytes

IDD [µA] IDD [µA]

120 90

100

8MHz

4MHz

2MHz

32KHz 80

8MHz

4MHz

2MHz

1MHz

32KHz

60 50

40 Obsolete Product(s) - Obsolete Product(s)

0 10

3 4

VDD [V]

5 6 -20 25

T[°C]

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ST6208C/ST6209C/ST6210C/ST6220C

SUPPLY CURRENT CHARACTERISTICS (Cont’d)

Figure 46. Typical I

in WAIT vs f

CPU

and Temperature for ROM devices

IDD [µA] IDD [µA]

600 450

500

8MHz

4MHz

2MHz

32KHz

400

350

400

300

250

200

100

150

3 4

VDD [V]

5 6

100

-20

8MHz

4MHz

2MHz

T[°C]

1MHz

32KHz

125

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

10.4.3 STOP Mode

Symbol Parameter

Supply current in STOP mode

(see Figure 47 & Figure 48 )

OTP devices

ROM devices

Conditions Typ

0.3

0.1

Max

Unit

Notes:

Typical data are based on V

=5.0V at T

=25°C.

2. All I/O pins in input with pull-up mode (no load), all peripherals in reset state, OSG and LVD disabled, option bytes programmed to 00H. Data based on characterization results, tested in production at V

max. and f

CPU

max.

3. Maximum STOP consumption for -40°C<Ta<90°C

4. Maximum STOP consumption for -40°C<Ta<125°C

Figure 47. Typical I

DD for OTP devices

IDD [nA]

1200

1000

Ta=-40°C

Ta=25°C

in STOP vs Temperature

Ta=95°C

Ta=125°C

Figure 48. Typical I

DD for ROM devices

in STOP vs Temperature

IDD [nA]

1500

Ta=-40°C

Ta=25°C

Ta=95°C

Ta=125°C

800

600

1000

400

200

3 4

VDD [V]

5 6

500

3 4

VDD [V]

5 6

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

10.4.4 Supply and Clock System

The previous current consumption specified for the ST6 functional operating modes over temperature range does not take into account the clock

Symbol

DD(CK)

DD(LFAO)

DD(OSG)

DD(LVD)

Parameter

Supply current of RC oscillator

Supply current of resonator oscillator

LFAO supply current

OSG supply current

LVD supply current

5) source current consumption. To get the total device consumption, the two current values must be added (except for STOP mode).

Typ

Max

Unit Conditions f

OSC

=32 kHz, f

OSC

=1 MHz f f

OSC f

OSC

=2 MHz

=4 MHz

=8 MHz f

OSC

=32 kHz, f

OSC

=1 MHz f f

OSC

=2 MHz

=4 MHz f

OSC

=8 MHz f

OSC

=32 kHz, f f

OSC f

OSC

=1 MHz

=2 MHz

=4 MHz f

OSC

=8MHz f

OSC

=32 kHz, f f

OSC f

OSC

=1 MHz

=2 MHz

=4 MHz f

OSC

=8 MHz

5.0 V

3.3 V

5.0 V

3.3 V

230

260

340

480

120

102

110

180

320

900

280

240

140

170

10.4.5 On-Chip Peripherals

Symbol Parameter

DD(TIM)

8-bit Timer supply current

DD(ADC)

ADC supply current when converting

7) f f

OSC

Conditions

=8 MHz

5.0 V

3.3 V

5.0 V

3.3 V

Typ

170

100

Unit

µA

Notes:

Obsolete Product(s) - Obsolete Product(s)

2. Data based on characterization results, not tested in production.

3. Data based on a differential I

measurement between reset configuration (OSG and LFAO disabled) and LFAO running (also includes the OSG stand alone consumption).

4. Data based on a differential I

measurement between reset configuration with OSG disabled and OSG enabled.

5. Data based on a differential I

measurement between reset configuration with LVD disabled and LVD enabled.

6. Data based on a differential I

measurement between reset configuration (timer disabled) and timer running.

7. Data based on a differential I

measurement between reset configuration and continuous A/D conversions.

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ST6208C/ST6209C/ST6210C/ST6220C

10.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for V

, f

OSC

, and T

10.5.1 General Timings

Symbol Parameter Conditions t c(INST) t v(IT)

Instruction cycle time t

Interrupt reaction time v(IT)

Δ t c(INST)

+ 6

2) f

CPU

=8 MHz f

CPU

=8 MHz

Min

3.25

9.75

Typ

6.5

Max

8.125

17.875

Unit t

CPU

μ s t

CPU

μ s

10.5.2 External Clock Source

Symbol

OSCINH

OSCINL

Parameter

OSC

input pin high level voltage

OSC

input pin low level voltage

OSCx Input leakage current

Conditions

See Figure 49

≤

Min

0.7xV

Typ Max

0.3xV

± 2

Unit

Notes:

Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch.

Δ t c(INST) the current instruction execution.

is the number of t

CPU

cycles needed to finish

Figure 49. Typical Application with an External Clock Source

OSCINH

90%

10%

OSCINL

OSC

OUT

Not connected f

OSC

EXTERNAL

CLOCK SOURCE L

OSC

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ST6208C/ST6209C/ST6210C/ST6220C

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

10.5.3 Crystal and Ceramic Resonator Oscillators

The ST6 internal clock can be supplied with several different Crystal/Ceramic resonator oscillators.

Only parallel resonant crystals can be used. All the information given in this paragraph are based on characterization results with specified typical external components. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).

Symbol

Parameter Conditions

Feedback resistor

Recommended load capacitances versus equivalent crystal or ceramic resonator frequency f f f f

OSC f

OSC

=32 kHz,

=1 MHz

=2 MHz

=4 MHz

=8 MHz

Typ

120

Unit

Ω pF

Oscillator

Typical Crystal or Ceramic Resonators

Reference Freq.

Characteristic

CSB455E 455KHz

Δ f

OSC

=[±0.5KHz

tolerance

,±0.3% Δ

±0.5% aging

]

CSB1000J 1MHz

Δ f

OSC

=[±0.5KHz

tolerance

,±0.3% Δ

±0.5% aging

]

CSTCC2.00MG0H6

2MHz

Δ f

OSC

=[±0.5% tolerance

,±0.5% Δ

±0.3% aging

]

CSTCC4.00MG0H6

4MHz

Δ f

OSC

=[±0.5% tolerance

,±0.3% Δ

±0.3% aging

]

CSTCC8.00MG

8MHz

Δ f

OSC

=[±0.5% tolerance

,±0.3% Δ

±0.3% aging

]

[pF]

[pF] t

SU(osc)

[ms]

220 220

100 100

47 47

15 15

Notes:

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

SU(OSC)

is the typical oscillator start-up time measured between V quick V

ramp-up from 0 to 5V (<50

μ s).

=2.8V and the fetch of the first instruction (with a

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

Refer to crystal/ceramic resonator manufacturer for more details.

value.

Figure 50. Typical Application with a Crystal or Ceramic Resonator

OSC

RESONATOR R

F F

OSC

OUT Obsolete Product(s) - Obsolete Product(s)

ST62XX

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

10.5.4 RC Oscillator

The ST6 internal clock can be supplied with an external RC oscillator. Depending on the R

NET

value, the accuracy of the frequency is about 20%, so it may not be suitable for some applications.

Symbol Parameter Unit f

OSC

NET

RC oscillator frequency

RC Oscillator external resistor

Conditions

NET

=22 k

=47 k

=100 k

=220 k

=470 k

NET

=22 k

=47 k

NET

=100 k

=220 k

=470 k

Ω see Figure 52 & Figure 53

3.7

2.8

1.8

0.5

Min

7.2

5.1

3.2

1.8

0.9

Typ

8.6

5.7

3.4

1.9

0.95

4.3

1.9

1.1

0.55

4.9

3.3

1.2

0.6

870

Max

6.5

3.8

1.1

MHz k

Notes:

1. Data based on characterization results, not tested in production. These measurements were done with the OSCin pin unconnected (only soldered on the PCB).

2. R

NET

must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.

Figure 51. Typical Application with RC Oscillator

EXTERNAL RC

OSC

OUT

MIRROR

CURRENT

NET

DD f

OSC

NC Obsolete Product(s) - Obsolete Product(s)

~9pF DISCHARGE

ST62XX

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ST6208C/ST6209C/ST6210C/ST6220C

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

Figure 52. Typical RC Oscillator frequency vs.

DD fosc [MHz]

Rnet=22KOhm

Rnet=47KOhm

Rnet=100KOhm

Rnet=220KOhm

Rnet=470KOhm

3 4 5 6

VDD [V]

Figure 53. Typical RC Oscillator frequency vs.

Temperature (V

= 5V) fosc [MHz]

Rnet=22KOhm

Rnet=47KOhm

Rnet=100KOhm

Rnet=220KOhm

Rnet=470KOhm

-40 25 95 125

Ta [°C]

10.5.5 Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO)

Symbol f

LFAO f

OSG

Parameter

Low Frequency Auxiliary Oscillator

Frequency

Internal Frequency with OSG enabled

Conditions

25° C, V

5.0 V

25° C, V

3.3 V

4.5 V

25° C, V

3.3 V

Min

200

Typ

350

150

Max

800

340

Figure 54. Typical LFAO Frequencies fosc [kHz]

600

500

400

300

Ta=-40°C

Ta=25°C

Ta=125°C

200

100

4 5 6

VDD [V]

Note:

1. Data based on characterization results.

Unit kHz

MHz

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ST6208C/ST6209C/ST6210C/ST6220C

10.6 MEMORY CHARACTERISTICS

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

10.6.1 RAM and Hardware Registers

Symbol

Parameter

Data retention

Conditions Min

0.7

Typ Max

10.6.2 EPROM Program Memory

Symbol t ret

Parameter

Data retention

Conditions

=+55°C

Figure 55. EPROM Retention Time vs. Temperature

Min

Typ Max

Retention time [Years]

100000

10000

1000

100

0.1

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120

Temperature [°C]

Unit

Unit years

Notes:

1. Minimum V

supply voltage without losing data stored in RAM (in STOP mode or under RESET) or in hardware registers (only in STOP mode). Guaranteed by construction, not tested in production.

2. Data based on reliability test results and monitored in production. For OTP devices, data retention and programmability must be guaranteed by a screening procedure. Refer to Application Note AN886.

The data retention time increases when the T

decreases, see Figure 55 .

Obsolete Product(s) - Obsolete Product(s)

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10.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample basis during product characterization.

10.7.1 Functional EMS

(Electro Magnetic Susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).

Symbol

FESD

FFTB

■

ESD : Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.

FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

and V

through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-

4 standard.

A device reset allows normal operations to be resumed.

Neg

Pos

Unit Parameter

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100pF on V

and V

DD pins to induce a functional disturbance

Conditions

5V, T

+25°C, f

OSC conforms to IEC 1000-4-2

8MHz

5V, T

+25°C, f

OSC

8MHz conforms to IEC 1000-4-4

-2

-2.5

3 kV

Notes:

1. Data based on characterization results, not tested in production.

2. The suggested 10 µF and 0.1 µF decoupling capacitors on the power supply lines are proposed as a good price vs.

EMC performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommendations are given in other sections (I/Os, RESET, OSCx pin characteristics).

Figure 56. EMC Recommended Star Network Power Supply Connection

ST62XX

POWER

SUPPLY

SOURCE

ST6

DIGITAL NOISE

FILTERING

(close to the MCU)

10 µF 0.1 µF

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EMC CHARACTERISTICS (Cont’d)

10.7.2 Absolute Electrical Sensitivity

Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the AN1181 application note.

10.7.2.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). Two models are usually simulated:

Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard.

See Figure 57 and the following test sequences.

Human Body Model Test Sequence

– C

is loaded through S1 by the HV pulse generator.

Absolute Maximum Ratings

Symbol

ESD(HBM)

ESD(MM)

Ratings

Electro-static discharge voltage

(Human Body Model)

Electro-static discharge voltage

(Machine Model)

+25°C

– S1 switches position from generator to R.

– A discharge from C

L to the ST6 occurs.

through R (body resistance)

– S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST6 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse.

Machine Model Test Sequence

– C

is loaded through S1 by the HV pulse generator.

– S1 switches position from generator to ST6.

– A discharge from C

to the ST6 occurs.

– S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST6 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse.

– R (machine resistance), in series with S2, ensures a slow discharge of the ST6.

Conditions Maximum value

Unit

2000

200

Notes:

1. Data based on characterization results, not tested in production.

Figure 57. Typical Equivalent ESD Circuits

S1 R=1500

HIGH VOLTAGE

100pF

HIGH VOLTAGE

PULSE

GENERATOR

ST6

PULSE

GENERATOR

ST6

Obsolete Product(s) - Obsolete Product(s)

200pF

HUMAN BODY MODEL MACHINE MODEL

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EMC CHARACTERISTICS (Cont’d)

10.7.2.2 Static and Dynamic Latch-Up

■ LU : 3 complementary static tests are required on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample. This test conforms to the EIA/

JESD 78 IC latch-up standard. For more details, refer to the AN1181 application note.

■ DLU : Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards and is described in Figure 58 . For more details, refer to the AN1181 application note.

Electrical Sensitivities

Symbol

DLU

Parameter

Static latch-up class

Dynamic latch-up class

Conditions

+25°C

+85°C

5V, f

OSC

4MHz, T

+25°C

Class

Notes:

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the

JEDEC criteria (international standard).

2. Schaffner NSG435 with a pointed test finger.

Figure 58. Simplified Diagram of the ESD Generator for DLU

=50M

ESD

GENERATOR

150pF

=330

DISCHARGE TIP

HV RELAY

DISCHARGE

RETURN CONNECTION

ST6

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EMC CHARACTERISTICS (Cont’d)

10.7.3 ESD Pin Protection Strategy

To protect an integrated circuit against Electro-

Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. The elements to be protected must not receive excessive current, voltage or heating within their structure.

An ESD network combines the different input and output ESD protections. This network works, by allowing safe discharge paths for the pins subjected to ESD stress. Two critical ESD stress cases are presented in Figure 59 and Figure 60 for standard pins.

Figure 59. Positive Stress on a Standard Pad vs. V

Standard Pin Protection

To protect the output structure the following elements are added:

– A diode to V

(3a) and a diode from V

(3b)

– A protection device between V

and V

(4)

To protect the input structure the following elements are added:

– A resistor in series with the pad (1)

– A diode to V

(2a) and a diode from V

(2b)

– A protection device between V

and V

(4)

(3a) (2a)

(1)

OUT

Main path

Path to avoid

(3b)

Figure 60. Negative Stress on a Standard Pad vs. V

(4) IN

(2b)

(3a) (2a)

(1)

OUT (4) IN

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10.8 I/O PORT PIN CHARACTERISTICS

10.8.1 General Characteristics

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Symbol

V hys

Parameter

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis

Input leakage current

Conditions

=5V

=3.3V

≤

(no pull-up configured)

Min

0.7xV

200

Typ

400

0.1

Max

0.3xV

OUT t f(IO)out t r(IO)out t w(IT)in

Weak pull-up equivalent resistor

I/O input pin capacitance

I/O output pin capacitance

Output high to low level fall time

Output low to high level rise time

External interrupt pulse time

=5V

=3.3V

=50pF

Between 10% and 90%

110

230

350

700

Figure 61. Typical R

vs. V

with V

= V

Rpu [Khom]

350

300

250

200

Ta=-40°C

Ta=25°C

Ta=95°C

Ta=125°C

Unit

V mV

A k

Ω pF pF ns t

CPU

150

100

3 4 5 6

VDD [V]

Notes:

Unless otherwise specified, typical data are based on T

=25°C and V

=5V.

2. Data based on characterization results, not tested in production.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

Obsolete Product(s) - Obsolete Product(s) not tested in production.

5. Data based on characterization results, not tested in production.

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.

Figure 62. Two typical Applications with unused I/O Pin

10k

ST62XX

UNUSED I/O PORT

10k

UNUSED I/O PORT

ST62XX

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I/O PORT PIN CHARACTERISTICS (Cont’d)

10.8.2 Output Driving Current

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Symbol

Parameter

Output low level voltage for a standard I/O pin

(see Figure 63 and Figure 66 )

Output low level voltage for a high sink I/O pin

(see Figure 64 and Figure 67 )

Output high level voltage for an I/O pin

(see Figure 65 and Figure 68 )

Conditions Min

=+10µA, T

≤ 125°C

=+3mA, T

≤ 125°C

=+5mA, T

≤ 85°C

=+10mA, T

≤ 85°C

=+10µA, T

≤ 125°C

=+7mA, T

≤ 125°C

=+10mA, T

≤ 85°C

=+15mA, T

≤ 125°C

=+20mA, T

≤ 85°C

=+30mA, T

≤ 85°C

=-10

A, T

≤ 125°C V

-0.1

=-3mA, T

≤ 125°C V

-1.5

=-5mA, T

≤ 85°C V

-1.5

0.1

0.8

1.3

Max

0.1

0.8

1.2

Unit

Notes:

1. The I

current sunk must always respect the absolute maximum rating specified in Section 10.2.2

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. The I

current source must always respect the absolute maximum rating specified in Section 10.2.2

and the sum of

(I/O ports and control pins) must not exceed I

VDD

. True open drain I/O pins does not have V

Figure 63. Typical V

at V

= 5V (standard)

Vol [mV] at Vdd=5V

1000

800

600

400

200

Ta=-40°C

Ta=25°C

Ta=95°C

Ta=125°C

2 4

Iio [mA]

6 8 10

Figure 64. Typical V

at V

= 5V (high-sink)

Vol [V] at Vdd=5V

Ta=-40°C

0.8

Ta=95°C

Ta=25°C Ta=125°C

0.6

0.4

0.2

0 4 8

Iio [mA]

12 16 20

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 65. Typical V

at V

= 5V

Voh [V] at Vdd=5V

4.5

3.5

-8 -6

Ta=-40°C Ta=95°C

Ta=25°C Ta=125°C

-4

Iio [mA]

-2 0

Figure 66. Typical V

vs V

(standard I/Os)

Vol [mV] at Iio=2mA

350

Ta=-40°C Ta=95°C

Ta=25°C Ta=125°C

300

250

200

150

3 4

VDD [V]

Figure 67. Typical V

vs V

(high-sink I/Os)

Vol [mV] at Iio=5mA

700

600

500

400

300

Ta=-40°C

Ta=25°C

VDD [V]

Ta=95°C

Ta=125°C

Vol [V] at Iio=8mA Vol [V] at Iio=20mA

0.55

Obsolete Product(s) - Obsolete Product(s)

0.45

Ta=-40°C

Ta=25°C

Ta=95°C

Ta=125°C

1.8

1.4

Ta=-40°C

Ta=25°C

Ta=95°C

Ta=125°C

0.4

1.2

0.35

0.3

0.25

0.8

0.6

0.2

0.4

3 4 5 6 3 4 5 6

VDD [V] VDD [V]

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 68. Typical V

vs V

Voh [V] at Iio=-2mA

3 4

Ta=-40°C Ta=95°C

Ta=25°C Ta=125°C

5 6

Voh [V] at Iio=-5mA

3 4

VDD [V] VDD [V]

Ta=-40°C Ta=95°C

Ta=25°C Ta=125°C

5 6

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10.9 CONTROL PIN CHARACTERISTICS

10.9.1 Asynchronous RESET Pin

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Symbol

V hys

Parameter

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis

Conditions Min

0.7xV

200

Typ

400

Max

0.3xV

ESD t w(RSTL)out

Weak pull-up equivalent resistor

ESD resistor protection

Generated reset pulse duration

=5V

=3.3V

=5V

=3.3V

External pin or internal reset sources

150

300

350

730

2.8

900

1900 t h(RSTL)in t g(RSTL)in

External reset pulse hold time

Filtered glitch duration

Unit

V mV k

Ω k

Ω t

CPU

μ s

μ s ns

Notes:

Unless otherwise specified, typical data are based on T

=25°C and V

=5V.

2. Data based on characterization results, not tested in production.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The R

pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, not tested in production.

5. All short pulse applied on RESET pin with a duration below t h(RSTL)in

can be ignored.

6. The reset network protects the device against parasitic resets, especially in a noisy environment.

7. The output of the external reset circuit must have an open-drain output to drive the ST6 reset pad. Otherwise the device can be damaged when the ST6 generates an internal reset (LVD or watchdog).

Figure 69. Typical R

vs V

with V

Ron [Kohm]

1000

900

800

700

600

500

400

Ta=-40°C

Ta=25°C

Ta=95°C

Ta=125°C

300

Obsolete Product(s) - Obsolete Product(s)

3 4 5 6

VDD [V]

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CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 70. Typical Application with RESET pin

OPTI

EXTERNAL

RESET

CIRCUIT

0.1

F 4.7k

0.1

RESET

ESD

PU f

INT

STOP MODE

INTERNAL

RESET

WATCHDOG RESET

LVD RESET

10.9.2 NMI Pin

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Symbol

V hys

Parameter

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis

Conditions Min

0.7xV

200

Typ

400

Max

0.3xV

R pull-up

Weak pull-up equivalent resistor

=5V

=3.3V

100

200

350

700

Unit

V mV k

Notes:

Unless otherwise specified, typical data are based on T

=25°C and V

=5V.

2. Data based on characterization results, not tested in production.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The R pull-up

equivalent resistor is based on a resistive transistor. This data is based on characterization results, not tested in production.

Figure 71. Typical R pull-up

vs. V

with V

Rpull-up [Kohm]

300

Ta=-40°C

Ta=25°C

Ta=95°C

Ta=125°C

200

150

100

3 4

VDD [V]

5 6

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CONTROL PIN CHARACTERISTICS (Cont’d)

10.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for V

DD f

OSC

, and T

unless otherwise specified.

10.10.1 Watchdog Timer

Symbol Parameter

Refer to I/O port characteristics for more details on the input/output alternate function characteristics

(TIMER).

Conditions Typ t w(WDG)

Watchdog time-out duration f

CPU

=4MHz f

CPU

=8MHz

Min

3,072

0.768

0.384

Max

196,608

49.152

24.576

Unit t

INT ms ms

10.10.2 8-Bit Timer

Symbol f

EXT

Parameter

Timer external clock frequency t w

Pulse width at TIMER pin

Conditions

VDD>4.5V

VDD=3V

Min

125

Typ Max f

INT

Unit

MHz ns

µs

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10.11 8-BIT ADC CHARACTERISTICS

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Symbol Parameter Conditions Min Typ

Max f

OSC

AIN

Clock frequency

Conversion range voltage

External input resistor

1.2

SS f

OSC

3) t

ADC t

STAB

Total convertion time

Stabilization time

4) f f

OSC

=8MHz

=4MHz f

OSC

=8MHz

140

3.25

6.5

Analog input current during conversion

Analog input capacitance 2

1.0

µA pF

Notes:

1. Unless otherwise specified, typical data are based on T

=25°C and V

=5V.

2. The ADC refers to V

DD and V

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

). Data based on characterization results, not tested in production.

4. As a stabilization time for the AD converter is required, the first conversion after the enable can be wrong.

Figure 72. Typical Application with ADC

Unit

MHz

V k

μ s t

CPU

µs

AIN AINx

AIN r

≈

150

10pF 10M

ADC

ST62XX

Note: ADC not present on some devices. See device summary on page 1.

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ST6208C/ST6209C/ST6210C/ST6220C

8-BIT ADC CHARACTERISTICS (Cont’d)

ADC Accuracy

Symbol

Parameter

Total unadjusted error

Conditions Min Typ.

1.2

Max

2, fosc>1.2MHz

4, fosc>32KHz

Unit

Offset error

Gain Error

=5V

2) f

OSC

=8MHz

0.72

-0.31

LSB

| Differential linearity error

0.54

Notes:

Integral linearity error

1. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:

- Analog input pins must have a negative injection less than 1mA (assuming that the impedance of the analog voltage is lower than the specified limits).

- Pure digital pins must have a negative injection less than 1mA. In addition, it is recommended to inject the current as far as possible from the analog input pins.

2. Data based on characterization results over the whole temperature range, monitored in production.

Figure 73. ADC Accuracy Characteristics

Digital Result ADCDR

255

254

253

1LSB

IDEAL

DDA

– V

SSA

-----------------------------------------

256

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

(2)

(3)

(1)

=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

=Offset Error: deviation between the first actual transition and the first ideal one.

=Gain Error: deviation between the last ideal transition and the last actual one.

=Differential Linearity Error: maximum deviation between actual steps and the ideal one.

=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

1 LSB

IDEAL

V in

(LSB

IDEAL

)

SSA

1 2 3 4 5 6 7 253 254 255 256

DDA

Obsolete Product(s) - Obsolete Product(s)

Note: ADC not present on some devices. See device summary on page 1.

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11 GENERAL INFORMATION

11.1 PACKAGE MECHANICAL DATA

Figure 74. 20-Pin Plastic Dual In-Line Package, 300-mil Width

D1 b

D b2 e

E1 eB c

Dim.

mm inches

Min Typ Max Min Typ Max

A1 0.38

5.33

0.015

0.210

A2 2.92

3.30

4.95 0.115 0.130 0.195

b 0.36

0.46

0.56 0.014 0.018 0.022

b2 1.14

1.52

1.78 0.045 0.060 0.070

c 0.20

0.25

0.36 0.008 0.010 0.014

D 24.89 26.16 26.92 0.980 1.030 1.060

D1 0.13

0.005

e eB

2.54

10.92

0.100

0.430

E1 6.10

6.35

7.11 0.240 0.250 0.280

L 2.92

3.30

3.81 0.115 0.130 0.150

Number of Pins

Figure 75. 20-Pin Ceramic Side-Brazed Dual In-Line Package mm inches

Dim.

Min Typ Max Min Typ Max

A1 0.38

3.63

0.015

0.143

B 3.56 0.46 0.56 0.140 0.018 0.022

B1 1.14 12.70 1.78 0.045 0.500 0.070

C 0.20 0.25 0.36 0.008 0.010 0.014

D 24.89 25.40 25.91 0.980 1.000 1.020

D1 22.86

0.900

E1 6.99 7.49 8.00 0.275 0.295 0.315

2.54

0.100

Obsolete Product(s) - Obsolete Product(s)

G1 9.47 9.73 9.98 0.373 0.383 0.393

CDIP20W

G2 1.14

0.045

L 2.92 3.30 3.81 0.115 0.130 0.150

12.70

4.22

0.500

0.166

Number of Pins

90/104

ST6208C/ST6209C/ST6210C/ST6220C

PACKAGE MECHANICAL DATA (Cont’d)

Figure 76. 20-Pin Plastic Small Outline Package, 300-mil Width

B e

E H a

L h x 45× c

Dim.

A 2.35

2.65 0.093

inches

Min Typ Max Min Typ Max

0.104

A1 0.10

B 0.33

C 0.23

D 12.60

E e

7.40

1.27

0.30 0.004

0.51 0.013

0.32 0.009

13.00 0.496

7.60 0.291

0.050

0.012

0.020

0.013

0.512

0.299

H 10.00

h 0.25

0°

L 0.40

10.65 0.394

0.75 0.010

8° 0°

1.27 0.016

Number of Pins

0.419

0.030

8°

0.050

Figure 77. 20-Pin Plastic Shrink Small Outline Package b

D e

A h

L c

Dim.

mm inches

Min Typ Max Min Typ Max

A 2.00

0.079

A1 0.05

0.002

A2 1.65

1.75

1.85 0.065 0.069 0.073

b 0.22

0.38 0.009

0.015

c 0.09

0.25 0.004

0.010

D 6.90

7.20

7.50 0.272 0.283 0.295

E 7.40

7.80

8.20 0.291 0.307 0.323

E1 5.00

5.30

5.60 0.197 0.209 0.220

E1 E e

0°

0.65

4° 8° 0°

0.026

4° 8°

L 0.55

0.75

0.95 0.022 0.030 0.037

Number of Pins

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ST6208C/ST6209C/ST6210C/ST6220C

11.2 THERMAL CHARACTERISTICS

Symbol

R thJA

Jmax

Ratings

Package thermal resistance (junction to ambient)

DIP20

SO20

SSOP20

Power dissipation

Maximum junction temperature

Value

115

500

150

Unit

°C/W mW

°C

Notes:

1. The power dissipation is obtained from the formula P

D and P

PORT

= P

INT

+ P

PORT

where P

INT

is the chip internal power (I

is the port power dissipation determined by the user.

)

2. The average chip-junction temperature can be obtained from the formula T

= T

+ P

x RthJA.

Obsolete Product(s) - Obsolete Product(s)

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11.3 ECOPACK INFORMATION

In order to meet environmental requirements, ST offers these devices in different grades of ECO-

PACK

packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com. ECOPACK

is an ST trademark.

ST6208C/ST6209C/ST6210C/ST6220C

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ST6208C/ST6209C/ST6210C/ST6220C

11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL

Table 23. Suggested List of DIP20 Socket Types

Package / Probe

DIP20 TEXTOOL

Adaptor / Socket Reference

220-33-42

Table 24. Suggested List of SO20 Socket Types

Package / Probe

SO20

EMU PROBE

Programming

Adapter

Adaptor / Socket Reference

ENPLAS OTS-20-1.27-04

YAMAICHI IC51-0202-714

Adapter from SO20 to DIP20 footprint

(delivered with emulator)

Logical Systems PA20SO1-08H-6

Table 25. Suggested List of SSOP20 Socket Types

Package / Probe

SSOP20

Programming

Adapter

ENPLAS

Logical Systems

Adaptor / Socket Reference

OTS-20-0.65-01

PA20SS-OT-6

Same

Footprint

Socket Type

Textool

Same

Footprint

Socket Type

Open Top

Clamshell

SMD to DIP

X Open Top

Same

Footprint

Socket Type

Open Top

X Open Top

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11.5 ORDERING INFORMATION

The following section deals with the procedure for transfer of customer codes to STMicroelectronics

Figure 78. ST6 Factory Coded Device Types and also details the ST6 factory coded device type.

ST62T20CB6/CCC

ROM code

Temperature code:

1: Standard 0 to +70 °C

3: Automotive -40 to +125 °C

6: Industrial -40 to +85 °C

Package type:

B: Plastic DIP

D: Ceramic DIP (EPROM devices only)

M: Plastic SOP

N: Plastic SSOP

T: Plastic TQFP

Revision index:

B,C: Product Definition change

L: Low Voltage Device

ST6 Sub family

Version Code:

No char: ROM

E: EPROM

P: FASTROM

T: OTP

Family

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ST6208C/ST6209C/ST6210C/ST6220C

11.6 TRANSFER OF CUSTOMER CODE

Customer code is made up of the ROM contents and the list of the selected FASTROM options.

The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to FFh.

The selected options are communicated to

STMicroelectronics using the correctly filled OP-

TION LIST appended. See

page 97 .

The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.

Listing Generation and Verification.

When

STMicroelectronics receives the user’s ROM contents, a computer listing is generated from it. This listing refers exactly to the ROM contents and options which will be used to produce the specified

MCU. The listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agreement for the production of the specific customer MCU.

11.6.1 FASTROM version

The ST62P08C/P09C/P10C and P20C are the

F actory A dvanced S ervice T echnique ROM (FAS-

TROM) versions of ST62T08C, T09C, T10C and

T20C OTP devices.

They offer the same functionality as OTP devices, but they do not have to be programmed by the customer. The customer code must be sent to

STMicroelectronics in the same way as for ROM devices. The FASTROM option list has the same options as defined in the programmable option byte of the OTP version. It also offers an identifier option. If this option is enabled, each FASTROM device is programmed with a unique 5-byte number which is mapped at addresses 0F9Bh-

0F9Fh. The user must therefore leave these bytes blanked.

The identification number is structured as follows:

0F9Bh

0F9Ch

0F9Dh

0F9Eh

0F9Fh

Test ID with T0, T1, T2, T3 = time in seconds since 01/01/

1970 and Test ID = Tester Identifier.

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TRANSFER OF CUSTOMER CODE (Cont’d)

ST6208C/09C/10C/20C/P08C/P09C/P10C/P20C MICROCONTROLLER OPTION LIST

Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact:

Phone:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STMicroelectronics references:

Device:

Package:

Conditioning option:

Temperature Range:

[ ] ST6208C (1 KB)

[ ] ST6210C (2 KB)

[ ] ST62P08C (1 KB)

[ ] ST62P10C (2 KB)

[ ] ST6209C (1 KB)

[ ] ST6220C (4 KB)

[ ] ST62P09C (1 KB)

[ ] ST62P20C (4 KB)

[ ] Dual in Line Plastic

[ ] Small Outline Plastic with conditioning

[ ] Shrink Small Outline Plastic with conditioning

[ ] Standard (Tube)

[ ] 0°C to + 70°C

[ ] - 40°C to + 125°C

[ ] Tape & Reel

[ ] - 40°C to + 85°C

Marking: [ ] Standard marking

[ ] Special marking (ROM only):

PDIP20 (10 char. max): _ _ _ _ _ _ _ _ _ _

SO20 (8 char. max): _ _ _ _ _ _ _ _

SSOP20 (11 char. max): _ _ _ _ _ _ _ _ _ _ _

Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Oscillator Safeguard:

Watchdog Selection:

Timer pull-up:

NMI pull-up:

Oscillator Selection:

[ ] Enabled

[ ] Software Activation

[ ] Enabled

[ ] Disabled

[ ] Hardware Activation

[ ] Disabled

[ ] Quartz crystal / Ceramic resonator

[ ] RC network

Readout Protection:

External STOP Mode Control:

Identifier (FASTROM only):

FASTROM:

[ ] Enabled

ROM:

[ ] Disabled

[ ] Enabled:

[ ] Fuse is blown by STMicroelectronics

[ ] Fuse can be blown by the customer

[ ] Disabled

[ ] Enabled

[ ] Disabled

Comments:

Oscillator Frequency in the application:

Supply Operating Range in the application:

Notes:

Date:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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11.6.2 ROM VERSION

The ST6208C, 09C, 10C and 20C are mask programmed ROM version of ST62T08C, T09C,

T10C and T20C OTP devices.

They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version.

ROM Readout Protection. If the ROM READOUT

PROTECTION option is selected, a protection fuse can be blown to prevent any access to the program memory content.

In case the user wants to blow this fuse, high voltage must be applied on the V

pin.

Figure 80. Programming wave form

Figure 79. Programming Circuit

0.5s min

100 µs max

5V 4.7µF

100nF

14V typ

150 µs typ

PROTECT

14V

100nF

ZPD15

15V

VR02003

400mA max

4mA typ t

VR02001

Note: ZPD15 is used for overvoltage protection

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12 DEVELOPMENT TOOLS

STMicroelectronics offers a range of hardware and software development tools for the ST6 microcontroller family. Full details of tools available for the ST6 from third party manufacturers can be obtain from the STMicroelectronics Internet site:

➟

http://www.st.com.

Table 26. Dedicated Third Parties Development Tools

Third Party

ACTUM

CEIBO

RAISONANCE

SOFTEC

Designation ST Sales Type

ST-REALIZER II: Graphical Schematic based Development available from

STMicroelectronics.

Low cost emulator available from CEI-

BO.

STREALIZER-II

This tool includes in the same environment: an assembler, linker, C compiler, debugger and simulator. The assembler package (plus limited C compiler) is free and can be downloaded from raisonance web site. The full version is available both from STMicroelectronics and Raisonance.

ST6RAIS-SWC/

High end emulator available from

SOFTEC.

Gang programmer available from

SOFTEC.

ADVANCED EQUIPMENT

ADVANCED TRANSDATA

BP MICROSYSTEMS

DATA I/O

DATAMAN

EE TOOLS

ELNEC

HI-LO SYSTEMS

ICE TECHNOLOGY

LEAP

LLOYD RESEARCH

Single and gang programmers

Web site address http://www.actum.com/ http://www.ceibo.com/ http://www.raisonance.com/ http://www.softecmicro.com/ http://www.aec.com.tw/ http://www.adv-transdata.com/ http://www.bpmicro.com/ http://www.data-io.com/ http://www.dataman.com/ http://www.eetools.com/ http://www.elnec.com/ http://www.hilosystems.com.tw/ http://www.icetech.com/ http://www.leap.com.tw/ http://www.lloyd-research.com/

LOGICAL DEVICES http://www.chipprogrammers.com/

MQP ELECTRONICS

NEEDHAMS http://www.mqp.com/

Obsolete Product(s) - Obsolete Product(s)

ELECTRONICS http://www.needhams.com/

STAG PROGRAMMERS http://www.stag.co.uk/

SYSTEM GENERAL CORP

TRIBAL MICROSYSTEMS

XELTEK http://www.sg.com.tw

http://www.tribalmicro.com/ http://www.xeltek.com/

Note 1: For latest information on third party tools, please visit our Internet site: ➟ http://www.st.com.

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DEVELOPMENT TOOLS (Cont’d)

STMicroelectronics Tools

Four types of development tool are offered by ST, all of them connect to a PC via a parallel or serial port:

see Table 27 and Table 28

for more details.

Table 27. STMicroelectronics Tool Features

ST6 Starter Kit

ST6 HDS2 Emulator

ST6 EPROM

Programmer Board

Emulation Type

Device simulation (limited emulation as interrupts are not supported)

In-circuit powerful emulation features including trace/ logic analyzer

Programming Capability

Yes (DIP packages only)

No Yes

Software Included

MCU CD ROM with:

– Rkit-ST6 from Raisonance

– ST6 Assembly toolchain

– WGDB6 powerful Source Level

Debugger for Win 3.1, Win 95 and NT

– Various software demo versions.

– Windows Programming Tools for Win 3.1, Win 95 and NT

Table 28. Dedicated STMicroelectronics Development Tools

Supported Products

ST6208C, ST6209C, ST6210C and ST6220C

ST6 Starter Kit

ST622XC-KIT

ST6 HDS2 Emulator

Complete:

ST62GP-EMU2

Dedication board:

ST62GP-DBE

ST6 Programming Board

ST62E2XC-EPB

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13 ST6 APPLICATION NOTES

IDENTIFICATION

MOTOR CONTROL

AN392

AN414

AN416

DESCRIPTION

MICROCONTROLLER AND TRIACS ON THE 110/240V MAINS

CONTROLLING A BRUSH DC MOTOR WITH AN ST6265 MCU

SENSORLESS MOTOR DRIVE WITH THE ST62 MCU + TRIAC

AN422

AN863

IMPROVES UNIVERSAL MOTOR DRIVE

IMPROVED SENSORLESS CONTROL WITH THE ST62 MCU FOR UNIVERSAL MOTOR

BATTERY MANAGEMENT

AN417

AN433

AN859

HOME APPLIANCE

AN674

FROM NICD TO NIMH FAST BATTERY CHARGING

ULTRA FAST BATTERY CHARGER USING ST6210 MICROCONTROLLER

AN INTELLIGENT ONE HOUR MULTICHARGER FOR Li-Ion, NiMH and NiCd BATTERIES

MICROCONTROLLERS IN HOME APPLIANCES: A SOFT REVOLUTION

AN885

GRAPHICAL DESIGN

ST62 MICROCONTROLLERS DRIVE HOME APPLIANCE MOTOR TECHNOLOGY

AN676 BATTERY CHARGER USING THE ST6-REALIZER

AN677

AN839

AN840

AN841

AN842

PAINLESS MICROCONTROLLER CODE BY GRAPHICAL APPLICATION DESCRIPTION

ANALOG MULTIPLE KEY DECODING USING THE ST6-REALIZER

CODED LOCK USING THE ST6-REALIZER

A CLOCK DESIGN USING THE ST6-REALIZER

7 SEGMENT DISPLAY DRIVE USING THE ST6-REALIZER

COST REDUCTION

AN431

AN594

USING ST6 ANALOG INPUTS FOR MULTIPLE KEY DECODING

DIRECT SOFTWARE LCD DRIVE WITH ST621X AND ST626X

AN672

AN673

OPTIMIZING THE ST6 A/D CONVERTER ACCURACY

REDUCING CURRENT CONSUMPTION AT 32KHZ WITH ST62

DESIGN IMPROVEMENTS

AN420 EXPANDING A/D RESOLUTION OF THE ST6 A/D CONVERTER

AN432 USING ST62XX I/O PORTS SAFELY

AN434

AN435

AN669

MOVEMENT DETECTOR CONCEPTS FOR NOISY ENVIRONMENTS

DESIGNING WITH MICROCONTROLLERS IN NOISY ENVIRONMENTS

SIMPLE RESET CIRCUITS FOR THE ST6

AN670

AN671

OSCILLATOR SELECTION FOR ST62 Obsolete Product(s) - Obsolete Product(s)

AN911 ST6 MICRO IS EMC CHAMPION

AN975 UPGRADING FROM ST625X/6XB TO ST625X/6XC

AN1015 SOFTWARE TECHNIQUES FOR IMPROVING ST6 EMC PERFORMANCE

PERIPHERAL OPERATIONS

AN590 PWM GENERATION WITH ST62 AUTO-RELOAD TIMER

AN591 INPUT CAPTURE WITH ST62 AUTO-RELOAD TIMER

AN592

AN593

AN678

PLL GENERATION USING THE ST62 AUTO-RELOAD TIMER

ST62 IN-CIRCUIT PROGRAMMING

LCD DRIVING WITH ST6240

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IDENTIFICATION

AN913

AN914

AN1016

AN1050

AN1127

GENERAL

AN683

AN886

AN887

AN898

AN899

AN900

AN901

AN902

AN912

AN1181

DESCRIPTION

PWM GENERATION WITH ST62 16-BIT AUTO-RELOAD TIMER

USING ST626X SPI AS UART

ST6 USING THE ST623XB/ST628XB UART

ST6 INPUT CAPTURE WITH ST62 16-BIT AUTO-RELOAD TIMER

USING THE ST62T6XC/5XC SPI IN MASTER MODE

MCUS - 8/16-BIT MICROCONTROLLERS (MCUS) APPLICATION NOTES ABSTRACTS BY

TOPICS

SELECTING BETWEEN ROM AND OTP FOR A MICROCONTROLLER

MAKING IT EASY WITH MICROCONTROLLERS

EMC GENERAL INFORMATION

SOLDERING RECOMMENDATIONS AND PACKAGING INFORMATION

INTRODUCTION TO SEMICONDUCTOR TECHNOLOGY

EMC GUIDE-LINES FOR MICROCONTROLLER - BASED APPLICATIONS

QUALITY AND RELIABILITY INFORMATION

A SIMPLE GUIDE TO DEVELOPMENT TOOLS

ELECTROSTATIC DISHARGE SENSITIVITY MEASUREMENT

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14 SUMMARY OF CHANGES

Description of the changes between the current release of the specification and the previous one.

Revision

3.3

Main Changes

Removed references to 32768 clock cycle delay in Section 5

and Section 6

Changed note 2 in Section 10.6.2 on page 76

: added text on data retention and program-

mability.

Updated device summary on page 1

Replaced soldering information by ECOPACK

information in Section 11.3 on page 93

Updated disclaimer on last page

Date

October 03

January 2009

15 TO GET MORE INFORMATION

To get the latest information on this product please use the STMicroelectronics web server.

➟

http://www.st.com/

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Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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Obsolete Product(s) - Obsolete Product(s)

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