STMicroelectronics ST25R3916 Datasheet

and

Operation control register . At power-on all its bits are set to 0, the ST25R3916/7 is in Power-down mode. In

must be properly configured.

2. The internal voltage regulators have to be configured. It is recommended to use direct command Adjust regulators to improve the system PSRR.

3. If AAT is used the tuning procedure must be performed.

After the sequence of events mentioned above the devices are ready to operate.

The ST25R3916/7 operating mode is defined by the contents of the

this mode, the AFE static power consumption is minimized, as only the POR and part of the bias are active. The regulator itself is disabled.

The SPI/I2C is still functional in this mode and all required settings on the configuration registers can be done. The PT_memory and FIFO are not accessible in this mode.

Bit en (bit 7 of the

Operation control register ) is controlling the quartz crystal oscillator,

regulators and AAT control output pins. When this bit is set, the device enters in Ready mode and the quartz crystal oscillator and regulators are enabled. An interrupt is sent to inform the microcontroller when the oscillator amplitude and frequency is stable. The

PT_memory and FIFO are accessible in this mode.

The enable of the receiver and the transmitter block are separated, it is possible to operate one without switching on the other (control bits rx_en and tx_en). This feature can be used when the reader field has to be maintained while no response from a tag is expected.

Another example is NFCIP-1 active communication in receive mode configuration. The RF field is generated by the initiator on one side while the other side is only in receive operation.

Asserting the

Operation control register bit wu while the other bits are set to 0 puts the

ST25R3916/7 into the Wake-up mode that is used to perform low power detection of card presence. In this mode the low power RC oscillator and register configurable wake-up timer are used to schedule periodic measurement(s). When a difference to the predefined reference is detected an interrupt is sent to wake-up the MCU. Capacitive sensor, phase and amplitude measurement are available to trigger the wake-up.

4.2.1 Transmitter

The transmitter contains two identical push-pull driver blocks connected to pins RFO1 and

RFO2. These drivers are differentially driving the external antenna LC tank. It is also

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possible to operate only one of the two drivers by setting the IO configuration register 1 bit

single and selecting which RFO/RFI to be use on bit rfo2.

Output resistance

Each driver is composed of eight segments having binary weighted output resistance. The

MSB segment typical ON resistance is 4 Ω . When all segments are turned on, the output resistance is typically 2 Ω . Usually all segments are turned on to define the normal transmission (non-modulated) level. It is also possible to switch off certain MSB segments when driving the non-modulated level to drive the circuitry with a higher impedance driver.

The bits d_res<3:0> in the TX driver register

define the resistance during the normal transmission. The default setting is minimum available resistance.

When using the single driver mode, the number and therefore the cost of the antenna LC tank components is halved, but also the output power is reduced. In single mode it is possible to connect two antenna LC tanks to the two RFO outputs and multiplex between them by controlling the

Mode definition register .

bit rfo2.

To transmit data, the transmitter output level needs to be modulated. AM and OOK modulation principles are supported. The type of modulation is defined by setting bit tr_am in the

Driver TX modulation

During the OOK modulation (e.g. for ISO14443A) the transmitter drivers stop driving the carrier frequency. As a consequence the amplitude of the antenna LC tank oscillation decays, the time constant of the decay is defined with the LC tank Q factor.

AM modulation (for example ISO14443B) is done via an additional regulator providing the supply voltage V

DD_AM

, used as the driver supply voltage during the modulation state.

The AM modulation level is set by am_mod3:0 bits in the TX driver register

AM modulation has to be manually enabled and the level to be set correctly for the following protocols:

 ISO14443B

 FeliCa

 ISO15693 (if not OOK)

 NFCIP-1 212 and 424 kb/s initiator or active target.

Depending on the applicable standard the modulation index can be set in a range between

5 and 30% in the

TX driver register .

Passive load modulation

The ST25R3916/7 enable passive load modulation using two different methods

 Internal driver load modulation

 Load modulation with an external MOS transistor and a diode that directly loads the antenna circuit

The driver load modulation is selected by bit lm_dri and the external MOS modulation is selected by lm_ext option bits.

Normally, the internal driver or the external load modulation should be used exclusively, but the device also allows simultaneous modulation.

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The driver load modulation is based on the change of driver impedance. Typically, a high impedance during non-modulated state and a lower impedance for the modulated state is used. This yields modulation phase equal to passive tag modulation. It is also possible to reverse the polarity of the driver load modulation by using low impedance during non-modulated state and higher impedance for the modulated state.

During the non-modulated state the output impedance is defined by pt_res3:0 option bits.

During modulation the output impedance is defined by ptm_res3:0 option bits.

Load modulation through an external MOS transistor and a diode is selected by the lm_ext option bit. In this case the EXT_LM pin is driven by the digital representation of the load modulation signal (848 kHz subcarrier or 424 / 212 kHz modulation signal). The EXT_LM is used to drive a gate of the external modulation MOS. The bit lm_ext_pol sets inverse polarity for the external load modulation.

The pt_res3:0 and ptm_res3:0 bits must be set prior entering passive target mode (reg 03h), because in passive target mode the resistance value propagates through the TX driver only when the extracted clock is available.

Driver load modulation is based on change of the driver impedance. Typically high impedance is used during non-modulated state, and decreased for modulated state, resulting in modulation phase equal to Passive tag modulation.

It is also possible to set inverse polarity driver load modulation by using low impedance during non-modulated state and higher impedance for the modulated state.

During non-modulated / modulated state the output impedance is defined, respectively, by pt_res3:0 / ptm_res3:0 option bits.

An external MOS transistor and a diode modulation is selected by lm_ext option bit. In this case the EXT_LM pin is driven by digital representation of the load modulation signal

(848 kHz subcarrier or 424 / 212 kHz modulation signal). The EXT_LM is used to drive a gate of the external modulation MOS.

Bit lm_ext_pol sets inverse polarity for the External load modulation.

Bits pt_res<3:0> and ptm_res<3:0> must be set before entering Passive target mode (reg

03h), as in Passive target mode the resistance value propagates through the TX driver only when extracted clock is available (during PT data transmission, including FDT).

Slow transmitter ramping

When the transmitter is enabled it starts to drive the antenna LC tank with full power, the ramping of field emitted by antenna is defined by antenna LC tank Q factor.

However there are some reader systems where the reader field has to ramp up with a longer transition time when it is enabled. The STIF (Syndicat des transports d'Ile de France) specification requires a transition time from 10 to 90% of field longer than or equal to 10 μ s.

The ST25R3916/7 supports slow transmitter ramping by collapsing VDD_RF regulated voltage when transmitter is disabled and ramping it when transmitter is enabled. Typical transition time is 15 μ s at 3 V supply and 20 μ s at 5 V supply.

Procedure to implement the slow transition:

When transmitter is disabled set IO configuration register 2 bit slow_up to 1. Keep this

state at least 2ms to allow discharge of V

DD_RF

3. Before sending any command set the bit slow_up back to 0.

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4.2.2 Receiver

The receiver performs demodulation of the tag subcarrier modulation that is superimposed on the 13.56 MHz carrier frequency. It performs AM/PM or I/Q demodulation, amplification, band-pass filtering and digitalization of subcarrier signals. It also performs RSSI measurement, automatic gain control (AGC) and Squelch function.

The reception chain has two separate channels for AM and PM demodulation. When both channels are active the selection for reception framing is done automatically by the receiver logic. The receiver is switched on when

Operation control register bit rx_en is set to 1.

The

Receiver configuration register 2 bit

contains bits rx_chn and rx_man, which define whether only one or both demodulation channels are active:

 bit rx_man defines the channel selection mode when both channels are active

(automatic or manual)

 bit ch_sel defines which channel is used for decoding.

rx_chn

Table 4. RX channel selection rx_man ch_sel Selected reception channel

1 x x x

Automatic selection

AM or I channel

PM or Q channel

AM or I channel

PM or Q channel

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Figure 7. Receiver block diagram

Application information

Demodulation stage

The first stage performs demodulation of the tag subcarrier response signal, superimposed on the HF field carrier. Two different blocks are implemented for the AM demodulation:

 peak detector

 AM/I or PM/Q demodulator mixer.

The choice of the used demodulator is made by the

amd_sel.

The peak detector performs AM demodulation using a peak follower. Both the positive and negative peaks are tracked to suppress any common mode signals. Its demodulation gain is

G = 0.7 and the input is taken from RFI1 demodulator input only.

The AM demodulator mixer uses synchronous rectification of both receiver inputs (RFI1 and

RFI2). Its gain is G = 0.55. The PM demodulation is also done by a mixer. The PM demodulator mixer has differential outputs with 60 mV differential signal for 1% phase change (16.67 mV / °).

The I/Q demodulation is composed of two mixer circuits, driven with a 90° shifted local oscillator (LO) signals derived from the crystal oscillator. The outputs of the two mixers are connected to two equal base band reception chains and to the decoding logic.

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Filtering and gain stages

The receiver chain has band pass filtering characteristics. The filtering is optimized to pass subcarrier frequencies while rejecting carrier frequency, low frequency noise and DC component. Filtering and gain is implemented in three stages, the first and the last stage have first order high pass characteristics while the mid stage has second order low-pass characteristic.

The gain and filtering characteristics can be optimized depending on the application by

writing the Receiver configuration register 1

(filtering),

Receiver configuration register 3

(primarily gain in first stage) and Receiver configuration register 4

(gain in second and third stage).

The gain of first stage is around 20 dB and can be reduced in six 2.5 dB steps. There is also a special boost mode available, which increases the max gain by additional 5.5 dB. The first

stage gain can only be modified by writing Receiver configuration register 3

. The default setting of this register is the minimum gain. Default first stage zero is located at 60 kHz, it can also be lowered to 40 or 12 kHz by writing option bits in the

Receiver configuration register 1

. The first stage can be reconfigured to second order high-pass at 600 kHz by option bit z600k. The control of the first and third stage zeros is done with common control bits (see

Table 6

rec1<5>lp2

Table 5. Low-pass control rec1<4>lp1 rec1<3>lp0

Others

-1 dB point

1200 kHz

600 kHz

300 kHz

2 MHz

7 MHz

Not used

Table 6. First and third zero setting rec1<3>z600k rec1<2>h200 rec1<1>h80 rec1<0>z12k First stage zero Third stage zero

60 kHz

40 kHz

12 kHz

600 kHz

400 kHz

200 kHz

80 kHz

200 kHz

80 kHz

200 kHz

400 kHz

200 kHz

Others Not used

The gain in the second and third stage is 23 dB and can be reduced in six 3 dB steps. Gain of these two stages is included in AGC and Squelch loops or can be manually set in

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Receiver configuration register 4 . Sending of direct command Reset RX Gain is necessary

to initialize the AGC, Squelch and RSSI block. Sending this command clears the current

Squelch setting and loads the manual gain reduction from Receiver configuration register 4 .

Second stage has a second order low-pass filtering characteristic, the pass band is adjusted according to subcarrier frequency using the bits lp2 to lp0 of the

Receiver configuration register 1

. See

Table 5

for -1 dB cut-off frequency for different settings.

Digitizing stage

The digitizing stage produces a digital representation of the sub-carrier signal coming from the receiver. This digital signal is then processed by the receiver framing logic. The digitizing stage consists of a window comparator with adjustable digitizing window (five possible settings, 3 dB steps, adjustment range from ±33 to ±120 mV). The adjustment of the digitizing window is included in the AGC and Squelch loops. The digitizing window can also

be set manually in the Receiver configuration register 4 .

AGC, Squelch and RSSI

As mentioned above, the second and third gain stage gain and the digitizing stage window are included in the AGC and Squelch loops. Eleven settings are available. The default state features minimum digitizer window and maximum gain. The first four steps increase the digitizer window in 3 dB steps, the next six steps reduce the gain in the second and third gain stage, again in 3 dB steps. The initial start setting for Squelch and AGC is defined in

Receiver configuration register 4 . The

Gain reduction state register

displays the actual state of gain resulting from Squelch, AGC and initial settings in

Receiver configuration register 4

Squelch

This feature is designed for operation in noisy environments. The noise may be misinterpreted as the start of tag response, resulting in decoding errors.

Automatic squelch is enabled by option bit sqm_dyn in the

Receiver configuration register 2

It is activated automatically 18.88 µs after end of TX and is terminated at the moment the

Mask receive timer (MRT) reaches the value defined in the

Squelch timer register . This

mode is primarily intended to suppress noise generated by tag processing during the time when the tag response is not expected (covered by MRT).

Squelch can operate in two modes, namely with ratios 1 and 6, selectable by pulz_61 bit in the

Receiver configuration register 2 .

Squelch ratio 1 means that system observes the subcarrier signal from the main digitizer and decrease the system gain to decrease the frequency of transitions. If there are more than two transitions on this output in a 50 μ s time period, gain is reduced by 3 dB and output is observed during the following 50 μ s. This procedure is repeated until number of transitions in 50 μ s is lower or equal to 2 or until the maximum gain reduction is reached.

This mode is intended for protocols where digitized subcarrier outputs are used.

Squelch ratio 6 means the system similarly observes and decreases the frequency seen at the window comparator set to 6 times the digitizing window. This mode is intended for protocols where output from correlators are used (ISO-A, ISO-B correlated reception).

The gain setting acquired by squelch is cleared by sending direct command Reset RX gain .

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AGC

The AGC (automatic gain control) can reduce the gain to keep the receiver chain and input to the digitizing stage out of saturation. The demodulation process is also less influenced by system noise when the gain is properly adjusted.

The AGC logic starts operating when the signal rx_on is asserted to high and is reset when it is reset to low. The state of the receiver gain is stored in the

Gain reduction state register

during a high to low transition of bit rx_on. Reading this register later on gives information of the gain setting used during the last reception.

The AGC system comprises a window comparator and an AGC ratio that can be set to 3 or to 6. As an example, when the AGC ratio is set to 6 the window is six times larger than the data digitalization window comparator. When the AGC function is enabled the gain is reduced until there are no transitions on its output. Such procedure assures that the input to digitalization window comparator is up to 6 times larger than its window.

If the AGC ratio is set to three, the input to the digitalization window comparator is set to be up to 3 times larger than its window.

The AGC operation is controlled by the control bits agc_en, agc_m, agc_alg, and agc6_3 in

Receiver configuration register 2 .

The bit agc_m defines the AGC mode when two AGC modes are available. The AGC can operate during the complete RX process as long as the signal rx_on is high and it can be enabled only during first eight subcarrier pulses.

There are two AGC algorithms to choose from bit agc_alg. The AGC can start either by pre-setting (maximum digitizer window and maximum gain) or by resetting (minimum digitizer window and maximum gain) it. The algorithm with preset is faster and therefore recommended for protocols with short SOF (like ISO14443A at 106 kbps).

Correlator

The correlators correlate the incoming filtered subcarrier with 848 kHz. The aim of the correlation is to maximize the system sensitivity at 848 kHz, while rejecting other frequencies. There are two correlators in the system for AM (or I) channel and PM (or Q) channel.

Correlator settings are defined in

Correlator configuration register 1

and Correlator configuration register 2

RSSI

The receiver also performs the RSSI (received signal strength indicator) measurement for both channels. The RSSI measurement is started after the rising edge of rx_on. It stays active while the signal rx_on is high and frozen while rx_on is low. It is a peak hold system where the value can only increase from initial 0 value. Every time the AGC reduces the gain the RSSI measurement is reset and starts from 0. The result of RSSI measurements is a

4-bit value that can be observed by reading the

RSSI display register . The LSB step is

2.8 dB, the maximum value is Dh (13d).

Since the RSSI measurement is of peak hold type, the result does not follow any variations in the signal strength (the highest value will be kept). To follow RSSI variation it is possible to reset RSSI bits and restart the measurement by sending direct command

Clear RSSI .

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Clock extractor

The clock extractor observes the RFI1 and RFI2 differential signal and provides a clock signal synchronous with the incoming RF field. The extracted clock is used for synchronous demodulation, for correct frame delay time and for correct data timing during passive transmission. The clock extractor is active down to 60 mV

input signal.

The ST25R3916/7 support antenna tuning through external variable capacitors. The variable capacitor is connected on its position in the matching network, and the tuning control voltage is connected to one of the control output pins (AAT_A, AAT_B).

The variable capacitors can be connected in series and parallel configurations in the matching network. Further information on the various configuration options can be found in the application note AN5322, available on www.st.com

The phase and amplitude detector block is used for resonance frequency checking. The algorithm in the MCU evaluates the result and adjusts the tuning voltages at AAT_A and

AAT_B output pins via the Antenna tuning control register 1 and Antenna tuning control register 2

according to the procedure in the MCU firmware.

The AAT_A/B pin voltages are actively set according to

Antenna tuning control register 1 and Antenna tuning control register 2 when en and aat_en option bits are both set.

If aat_en=1 and en=0, the AAT_A/B voltages are set to a fixed value between 1.5 and 2.2 V

(typically 1.9 V).

The capacitive sensor enables measuring a capacitance between two pads, it can be used. as an example, for Wake-up mode / Low power card detection.

The capacitive measurement system comprises two electrodes, one is the excitation electrode emitting an electrical field of a fixed frequency in the range of a few hundred kHz

(CSO), and the second one is the sensing electrode (CSI). The amount of charge generated in the sensing electrode represents the capacitance between the two electrodes. The capacitive sensor electrodes are tolerant to parasitic capacitance to ground (up to 25 pF) and to input leakage (up to 1 M Ω ).

As the charge on the sensing electrode is generated with the frequency of the excitation electrode, a synchronous rectifier is used to detect it. This ensures good rejection of interference and high tolerance to parasitic capacitances (to all nodes except the excitation electrode). The synchronous rectifier output is a DC voltage linearly proportional to the capacitance between the excitation and sensing electrode. The output DC voltage is converted by the A/D converter in absolute mode. The result is stored in the

A/D converter output register (see also

Section 2.2.5: A/D converter ).

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Figure 8. Capacitive sensor block diagram

CSO

Oscillator

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A/D converter

Synchronous rectifier

CSI

MS42418V1

Any conductive object (human hand or tag) approaching the two electrodes changes the capacitance between the excitation and sensing electrode as it 'shortens' the distance between the two by providing conductance on the part of the path between the two electrodes.

The capacitance measurement is started by sending the direct command Measure capacitance . The ST25R3916/7 can also be configured to automatically wake-up and

perform periodic capacitance measurements. The result is compared to a stored reference or to an average of previous measurements, and if the difference is greater than a

predefined value an IRQ is triggered to wake-up the controller (see also Section 4.2.5

The capacitive sensor gain can be adjusted in Capacitive sensor control register . The

default gain is 2.8 V / pF (typical value), the maximum gain is 6.5 V / pF (typical value).

Since the LSB of the A/D converter corresponds to approximately 7.8 mV, the default gain results in a sensitivity of 2.8 fF / LSB (1.2 fF / LSB in case of maximum gain).

The duration of the capacitance measurement is 200 μ s, and the current consumption during the measurement is 1.1 mA (typical value). As an example, if the capacitive measurement is performed every 100 ms in Wake-up mode, then the resulting average current consumption is 5.8 μ A (3.6 μ A is the standby consumption in Wake-up mode).

Capacitive sensor calibration

The capacitive sensor comprises a calibration unit that internally compensates the parasitic capacitances between CSI and CSO, thus leaving full measurement range for information about capacitance variation. Five bits are used to control the calibration. The minimum calibration step and the available calibration range are, respectively, 0.1 and 3.1 pF. The

calibration can be done manually by writing to the Capacitive sensor control register or

automatically by sending the direct command

Calibrate capacitive sensor

. The status of this command and the resulting calibration value are stored in the

Capacitive sensor display register .

To avoid interference of the capacitive sensor with the Xtal oscillator and the reader magnetic field and to assure repetitive results it is strongly recommended to perform capacitance measurement and calibration in Power-down mode only.

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Asserting the

Operation control register bit wu while the other bits are set to 0 puts the

ST25R3916/7 into the Wake-up mode, used to perform low power detection of card presence. The ST25R3916/7 features three possibilities, namely capacitive sensor, phase and amplitude measurement. An integrated low power 32 kHz RC oscillator and register configurable Wake-up timer are used to schedule periodic detection.

Usually the presence of a card is detected by a so-called polling. In this process the reader field is periodically turned on and the controller checks whether a card is present using RF commands. This procedure consumes a lot of energy since reader field has to be turned on for 5 ms before a command can be issued.

Low power detection of card presence is performed by detecting a change in the reader environment, produced by a card. When a change is detected, an interrupt is sent to the controller. As a result, the controller can perform a regular polling loop.

In Wake-up mode the ST25R3916/7 periodically performs the configured reader environment measurements and sends an IRQ to the controller when a difference to the configured reference value is detected.

Card detection

The presence of a card close to the reader antenna coil produces a change of the antenna

LC tank signal phase and amplitude. The reader field activation time needed to perform the phase or the amplitude measurement is extremely short (~20 μ s) compared to the activation time needed to send a protocol activation command.

The power level during the measurement can be lower than that during normal operation as the card does not have to be powered to produce a coupling effect. The emitted power can be reduced by changing the RFO driver resistance.

The capacitive sensor detects a change of the parasitic capacitance between the two excitation electrodes. This change in capacitance can be caused by a card antenna or a hand holding the card (see

Section 2.2.6: Capacitive sensor ).

Registers from 32h to 3Eh are dedicated to Wake-up configuration and display. The Wakeup timer control register

is the main Wake-up mode configuration register. The timeout period between the successive detections and the measurements which are going to be used are selected in this register. Timeouts in the range from 10 to 800 ms are available,

100 ms being the default value.

Registers from 33h to 3Dh configure the possible detection measurements and store the results, four registers are used for each method.

An IRQ is sent when the difference between a measured value and reference value is larger than configured threshold value. There are two possibilities how to define the reference value:

 the ST25R3916/7 can calculate the reference based on previous measurements

(auto-averaging)

 the controller determines the reference and stores it in a register.

The first register in the series of four is the

Amplitude measurement configuration register .

The difference to reference which triggers the IRQ, the method of reference value definition and the weight of last measurement result in case of auto-averaging are defined in this register. The next register is storing the reference value in case the reference is defined by

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Application information ST25R3916/7 the controller. The following two registers are display registers. The first one stores the auto-averaging reference, the second one stores the result of the last measurement.

Wake-up mode configuration registers have to be configured before Wake-up mode is actually entered. Any modification of Wake-up mode configuration while it is active may result in unpredictable behavior.

Auto-averaging

In case of auto-averaging the reference value is recalculated after every measurement. The last measurement value, the old reference value and the weight are used in this calculation.

The following formula is used to calculate the new reference value: new_reference = old_reference - (old_reference - measured_value) / weight

The calculation is done on 10 bits to have sufficient precision.

The auto-averaging process is initialized when Wake-up mode is first time entered after initialization (power-up or using

Set default

command). The initial value is taken from the measurement reference register (for example

Amplitude measurement reference register ) if

the content of this register is not 0. If content of this register is 0, the result of first measurement is taken as initial value.

Every measurement configuration register contains a bit defining whether the measurement that causes an interrupt is taken in account for the average value calculation (for example bit am_aam of

Amplitude measurement reference register

4.2.6 Quartz crystal oscillator

The quartz crystal oscillator operates with 27.12 MHz crystals; its operation is enabled when the

stable (see Main interrupt register

bit en is set to 1. An interrupt is sent to inform the microcontroller when the oscillator amplitude is sufficiently high, meaning the frequency is

The status of oscillator can be observed by checking the Auxiliary display register

bit osc_ok. This bit is set to 1 when oscillator frequency is stable.

The oscillator is based on an inverter stage supplied by a controlled current source. A feedback loop is controlling the bias current in order to regulate amplitude on XTI pin to

1 V

. To enable a fast reader start-up an interrupt is sent when oscillator amplitude exceeds 750 mV

Division by two assures that 13.56 MHz signal has a duty cycle of 50%, which is better for the transmitter performance (no PW distortion).

The oscillator output is also used to drive a clock signal output pin MCU_CLK, which can be

used by the external microcontroller. The MCU_CLK pin is configured in the IO configuration register 2

4.2.7 Timers

Several timers are integrated in the device, to eliminate the need to run counters in the controller, thus reducing the effort of code implementation and improve its portability to different controllers.

Every timer has one or more associated configuration registers in which the timeout duration and different operating modes are defined. These configuration registers have to

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All timers are stopped by the direct command

Stop all activities .

Mask receive timer (MRT)

In Reader mode this timer is blocking the receiver and reception process in framing logic by keeping the rx_on signal low after the end of TX during the time the tag reply is not expected. While Mask Receive timer is running the Squelch is automatically turned on when enabled. The MRT does not produce an IRQ.

The MRT timeout is configured in the Mask receive timer register

and is automatically started at the end of data transmission (at the end of EOF).

The MRT can be triggered by direct command Start Mask-receive timer. In this case the

squelch is enabled, according to the Squelch timer register

In the NFCIP-1 Active Initiator, Active and Passive Target communication modes the MRT is started when the other device turns on its field and the external field detector signals I_eon.

MRT supports a longer timing needed for NFCIP1 by setting option bit mrt_step. The bit switches between fc / 64 and fc / 512 step size.

The MRT starts also in the low power Initial NFC target mode. After the initiator field has been detected the controller turns on the 27 kHz RC oscillator, regulator, crystal oscillator, receiver and MRT. After the MRT expires the receiver output starts to be observed to detect start of the initiator message.

For correct operation in the low power Initial NFC target mode the mrt_step = 1 must be used. The 27 kHz RC oscillator is used as a MRT clock source for the time before the crystal oscillator stabilises. This enables that the actual MRT time is a good approximation to the targeted time, also in case the crystal oscillator is not running yet.

No-response timer (NRT)

The purpose of this timer is intended to observe whether a response is detected during a

configured time started by end of transmission. The I_nre flag in the Timer and NFC interrupt register

is signaling interrupt events resulting from this timer timeout.

The NRT is configured by writing

No-response timer register 1 and No-response timer register 2

). Operation options are defined by setting bits nrt_emv and nrt_step in the

Timer and EMV control register .

The NRT is automatically started at the end of transmission.

Bit nrt_step configures the time step of the No-response timer. Two steps are available,

64/fc (4.72 μ s) and 4096/fc, covering, respectively, the range up to 309 ms and up to 19.8 s.

Bit nrt_emv controls the timer operation mode.

 When this bit is set to 0 (default mode) the IRQ is produced if the NRT expires before a start of a response is detected. The rx_on is set low to disable the receiver. In the opposite case, when the start of a tag reply is detected before timeout, the timer is stopped, and no IRQ is produced.

 When this bit is set to 1 the timer unconditionally produces an IRQ when it expires, it is also not stopped by direct command Stop all activities. This means that the IRQ is independent from whether or not a tag reply was detected. When a tag reply is being processed during a timeout, no other action is taken and the reply is normally received.

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In the opposite case, when no tag response is being processed, the receiver is disabled.

The NRT can also be started using direct command Start No-response timer. The intention of this command is to extend the No-response timer timeout beyond the range defined in the

No-response timer control registers. If this command is sent while the timer is running, it is reset and restarted.

The NRT can be terminated using direct command Stop No-response Timer or Stop all activities

. The timer is terminated and no IRQ is sent. It is expected to be used in the nrt_emv mode, when the incoming reception does not stop the No-response timer.

In the NFCIP-1 active communication mode the NRT role is similar to operation in the normal Reader mode. If the NRT expires before the start of a response is detected an IRQ is produced and the receiver is disabled. There are two modes available:

 nrt_nfc = 0

– The timer is started when the device TX field is switched off, using a general purpose timer.

– The operation is valid for active initiator and target modes as well as for bit rate detection mode.

 nrt_nfc = 1

– The timer is started when the peer field is turned on.

– Operation is valid for Active initiator and Active target modes.

For Bit rate detection mode the timer is not started at peer field on as, in case of migration from Bit rate detection mode to Active target mode, the MCU has to reconfigure the device to Active target mode prior field on.

In the NFCIP-1 Passive target the No-response timer has no task and is not automatically started.

PPON2 timer

This timer is not used in Reader mode.

In NFCIP-1 mode this timer is automatically started when the transmitter is turned off after the message has been sent. If this timer expires before the peer NFC device

FADT

+ n*T

RFW

) field-on is detected, an I_ppon2 IRQ is sent.

If the external RF field is detected on time, the timer is stopped and no IRQ is sent.

Time is defined in the

PPON2 field waiting register

General purpose (GP) timer

The triggering of the this timer is configured by setting the

Timer and EMV control register

. It can be used to survey the duration of reception process (triggering by start of reception, after SOF) or to time out the PCD to PICC response time (triggered by end of reception, after EOF).

In the NFCIP-1 active communication mode it is used to timeout the field switching off. In all cases an IRQ is sent when it expires.

The GP timer can also be started by sending the direct command Start General purpose timer. If this command is sent while the timer is running, it is reset and restarted.

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Wake-up (WU) timer

This timer is primarily used in the Wake-up mode, it can be used by sending the direct command Start Wake-up Timer. This command is accepted in any operation mode except

Wake-up mode. When this command is sent the RC oscillator, which is used as clock

source for wake-up timer is started, timeout is defined by setting the Wake-up timer control register . When the timer expires, an IRQ with the I_wt flag in the

Error and wake-up interrupt register is sent.

The WU timer is used in the Power-down mode, in which other timers cannot be used because the crystal oscillator, which is the clock source for the other timers, is not running.

Note that the tolerance of wake-up timer timeout is defined by tolerance of the RC oscillator.

In NFCIP-1 passive target mode the WU timer is used for time out the temporary device enable after the initial peer field on was detected.

4.2.9

The ST25R3916/7 contains an 8-bit successive approximation A/D converter. Inputs can be multiplexed from different sources to be used in several direct commands and adjustment

procedures. The result of the last conversion is stored in the A/D converter output register .

Typical conversion time is 224/fc (16.5 µs).

The A/D converter has two operating modes, absolute and relative.

 In absolute mode the low reference is 0 V and the high reference is 2 V. This means that A/D converter input range is from 0 to 2V, 00h code means input is 0 V or lower,

FFh means that input is 2 V - 1 LSB or higher, LSB being 7.8125 mV.

 In relative mode low reference is 1/11 of V

DD_A so the input range is from 1/11 V

DD_A

to 10/11 V

and high reference is 10/11 of V

DD_A

Relative mode is only used in phase measurement (phase detector output is proportional to power supply). In all other cases absolute mode is used.

Phase and amplitude detector

This block is used to provide inputs to the A/D converter to perform measurements of amplitude and phase, expected by direct commands

Measure amplitude

and

Measure phase .

Phase detector

The phase detector observes phase difference between the transmitter output signals

(RFO1 and RFO2) and the receiver input signals RFI1 and RFI2, proportional to the signal on the antenna LC tank. These signals are first passed by digitizing comparators. Digitized signals are processed by a phase detector with a strong low-pass filter characteristics to get the average phase difference. The phase detector output is inversely proportional to the phase difference between the two inputs. The 90° phase shift results in V

DD_A voltage, if both inputs are in phase the output voltage is V

DD_A

/2 output

, if they are in opposite phase the output voltage is 0 V. During execution of direct command

Measure phase this output is

multiplexed to the A/D converter input (A/D converter is in relative mode during the execution of this command). Since the A/D converter range is from 1/11 V

DD_A

the actual phase detector range is from 17º to 163º.

Figure 9 and

to 10/11

Figure 10 show the

two inputs and output of phase detector in case of 90º and 135º phase shift, respectively.

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Application information ST25R3916/7

Figure 9. Phase detector inputs and output in case of 90º phase shift

SP_A

Input 1

SP_A

Input 2

Output

SP_A

Figure 10. Phase detector inputs and output in case of 135º phase shift

MS42426V1

SP_A

Input 1

SP_A

Input 2

Output

SP_A

MS42427V1

Amplitude detector

Signals from pins RFI1 and RFI2 are used as inputs to the self-mixing stage. The output of this stage is a DC voltage proportional to the amplitude of signals on pins RFI1 and RFI2.

During execution of direct command Measure amplitude

this output is multiplexed to the A/D converter input.

This block is used to detect the presence of an external device generating an RF field. It is used in NFCIP-1 Active communication and Passive target modes. It is enabled by en_fd_c<1:0> option bits. The external field detector supports two different detection thresholds, namely Peer detection and Collision avoidance. The two thresholds can be independently set by writing the

External field detector activation threshold register . The

actual state of the detector output can be checked by reading the

Auxiliary display register .

Input to this block is the signal from the RFI1 pin.

For both thresholds there is a possibility to separately set the activation and deactivation levels.

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If the External field level is not detected yet, the Activation threshold is used. If the External field level is detected, the Deactivation threshold is used.

The Activation threshold must be set higher than or equal to the Deactivation threshold.

If the Activation is higher than the Deactivation, the hysteresis is given by the difference between the two levels.

If the Activation and Deactivation levels are equal, there is no the hysteresis in the system and multiple field-on/off events can verify if the actual field level persists in proximity of the selected threshold.

Peer detection threshold

This threshold is used to detect the field emitted by peer NFC device with whom NFC communication is going on. It can be selected in the range from 75 to 800 mV

. When this threshold is enabled the detector is in low power mode. An interrupt is generated when an external field is detected and also when it is switched off. With such implementation it can also be used to detect the moment when the external field disappears. This can be used to detect the moment when the peer NFC device (either an initiator or a target) has stopped emitting an RF field.

The External Field Detector is enabled in low power Peer Detection mode by setting bits en_fd_c,1:0> in the

Section 4.4.5: NFC field ON commands

Collision avoidance threshold

This threshold is used during the RF collision avoidance sequence, which is executed by sending NFC Field ON commands (see

). It can be selected in the range from 25 to 800 mV

4.2.11 Power supply system

The ST25R3916/7 features three positive supply pins, VDD, VDD_TX and VDD_IO:

 VDD is the main power supply pin. It supplies the ST25R3916/7 blocks through two regulators (V

DD_A

, V

DD_D

)

 VDD_TX is the transmitter supply pin. It supplies the transmitter via two regulators

DD_RF

, V

DD_AM

). V

range from 2.4 to 5.5 V is supported. VDD and VDD_TX must be connected to the same power supply.

 V

DD_IO

is used to define supply level for digital communication pins (BSS, MISO,

MOSI, SCLK, IRQ, MCU_CLK). Digital communication pins interface to the

ST25R3916/7 logic through level shifters, therefore the internal supply voltage can be either higher or lower than V

DD_IO

. V

DD_IO

range from 1.65 to 5.5 V is supported.

Figure 11

details the building blocks of the ST25R3916/7 power supply system. It contains three regulators, a power-down support block, a block generating analogue reference voltage (AGDC) and a block performing automatic power supply adjustment procedure. The three regulators are providing supply to analogue blocks (V transmitter (V

DD_RF

). The use of V

DD_A

and V

DD_D

DD_A

), logic (V

DD_D

) and

regulators is mandatory at 5 V power supply to provide regulated voltage to analogue and logic blocks, which only use 3.3 V. The use of V

DD_A

and V

DD_D

regulators at 3 V supply and V

DD_RF

regulator at any supply voltage is recommended to improve system PSRR.

Regulated voltage can be adjusted automatically to have maximum possible regulated voltage while still having good PSRR. All regulator pins also have corresponding negative supply pins externally connected to ground potential (V

). Figure 1

and

Figure 2 show

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Application information ST25R3916/7 typical application schematics with all regulators used. For regulators recommended blocking capacitors are 2.2 μ F in parallel with 10 nF, for pin AGDC 1 μ F in parallel with 10 nF is suggested.

Figure 11. ST25R3916/7 power supply system

VDD_TX

VDD

EN sup3v VDD_DR

Power-down support

DD_D regulator

DD_A regulator

DD_RF regulator

VDD_RF

DD_AM regulator

BGR and

AGD

50Ω

VDD_AM

AGDC

VDD_D

VDD_A rege<3:0>

Adjust regulators

Autoreg reg<3:0>

MS52437V1

Regulators have two basic operation modes depending on supply voltage, 3.3 V supply mode (max. 3.6 V) and 5 V supply mode (max 5.5 V). The supply mode is set by writing bit

sup3V in the IO configuration register 2 . Default setting is 5 V so this bit has to be set to 1

after power-up in case of 3.3 V supply.

In 3.3 V mode all regulators are set to the same regulated voltage in range from 2.4 to 3.4 V, while in 5 V only the V are fixed to 3.4 V.

DD_RF

can be set in range from 3.6 to 5.1 V, while V

DD_A

and V

DD_D

Figure 11

also shows the signals controlling the power supply system. The regulators are

operating when signal en is high (en is configuration bit in Operation control register ). When

signal en is low the ST25R3916/7 is in low power Power-down mode. In this mode consumption of the power supply system is also minimized.

V

DD_RF

regulator

The purpose of this regulator is to improve the PSRR of the transmitter (the noise of the transmitter power supply is emitted and fed back to the receiver). The V

DD_RF

regulator operation is controlled and observed by writing and reading two regulator registers:



Regulator voltage control register controls the regulator mode and regulated voltage.

Bit reg_s controls regulator mode. If it is set to 0 (default state) the regulated voltage is set using direct command

Adjust regulators

. When bit reg_s is asserted to 1 regulated voltage is defined by bits rege_3 to rege_0 of the same register. The regulated voltage adjustment range depends on the power supply mode. In case of 5 V supply mode the adjustment range is between 3.6 and 5.1 V in steps of 120 mV, in case of 3.3 V supply mode the adjustment range is from 2.4 to 3.6 V with 100 mV steps.



Regulator display register is a read only register that displays actual regulated voltage

when regulator is operating. It is especially useful in case of automatic mode, since the

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actual regulated voltage, which is result of direct command Adjust regulators , can be

observed.

The V

DD_RF

regulator includes a current limiter that limits the regulator current to

350 mArms in normal operation. The i_lim in the

Regulator display register is set when the

DD_RF

regulator is in current limiting mode.

If a transmitter output current higher than 350 mArms is required the V

DD_RF

regulator cannot be used to supply the transmitter. VDD_RF and VDD_DR have to be externally connected to VDD_TX (connection of VDD_RF to supply voltage higher than V

DD_TX allowed).

is not

The voltage drop of the transmitter current is the main source of the ST25R3916/7 power dissipation. This voltage drop is composed of a drop in the transmitter driver and of a drop in the V

DD_RF

regulator. Due to this it is recommended to set the regulated voltage using direct command Adjust Regulators. It results in good power supply rejection ratio with relatively low dissipated power due to regulator voltage drop.

In Power-down mode the V

DD_RF

regulator is not operating. VDD_RF pin is connected to

VDD_TX through a 1 k Ω resistor. Connection through resistors assures smooth power-up of the system and a smooth transition from Power-down mode to other operating modes.

V

DD_AM

regulator

This regulator is used to support the transmitter AM modulation. Its output voltage is used as transmitter supply during modulation phase. The output is internally connected to the transmitter. It requires decoupling capacitors (2.2 µF + 1 nF) at VDD_AM pin.

DD_DR

is used as reference voltage, resulting in correct V

DD_AM

voltage and modulation index at supply voltage between 2.4 and 5.5 V.

The output voltage and thus modulation setting is controlled by am_mod<3:0> option bits from 5 to 30% in 16 steps.

In Power-down mode the V

DD_AM

regulator is not operating. VDD_AM pin is connected to

VDD_TX through 1 k Ω resistor, as in the V

DD_RF

regulator.

V

DD_A

and V

DD_D

regulators

DD_A

and V

DD_D

regulators are used to supply the ST25R3916/7 analog and digital blocks respectively. In 3.3 V mode V

DD_A voltage as the V

3.4 V.

DD_RF

and V

DD_D

regulator are set to the same regulated

regulator, in 5 V mode V

DD_A

and V

DD_D

regulated voltage is fixed to

The use of V

DD_A

and V

DD_D

regulators is mandatory in 5 V mode since analog and digital blocks supplied with these two pins contain low voltage transistors which support maximum supply voltage of 3.6 V. In 3.3 V supply mode the use of regulators is strongly recommended to improve PSRR of analog processing.

For low cost applications it is possible to disable the V

DD_D blocks through external short between V

Using direct command Measure power supply

DD_A

and V

DD_D

regulator and to supply digital

(configuration bit vspd_off in the

Power-down support block

In the Power-down mode the regulators are disabled to save current. In this mode a low power Power-down support block that keeps V

DD_D

and V

DD_A

below 3.6 V is enabled.

Typical regulated voltage in this mode is 3.1 V at 5 V supply and 2.2 V at 3 V supply. When

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Application information ST25R3916/7

3.3 V supply mode is set this block is disabled, its output is connected to VDD through a

1 k Ω resistor.

Typical consumption of Power-down support block is 600 nA at 5 V supply.

Measurement of supply voltages

it is possible to measure V

DD voltages V

DD_A

, V

DD_D

and V

DD_RF

and regulated

The overshoot / undershoot protection mechanism makes it possible to control the transmitting waveform during challenging test conditions. This is accomplished by setting bit patterns in the corresponding registers that produce additional signals during the transition phase from modulated to unmodulated state or vice versa.

The operation of this protection is explained by using the overshoot registers. The overshoot mechanism is only effective when bits are written in ov_pattern<13:0>. Setting ov_pattern<13:0> to 0 implicitly disables the overshoot protection, as the configuration from

Mode definition register and

TX driver register

is applied for all clock cycles after the transition.

The overshoot mode has to be set in control bits ov_tx_mode<1:0> and defines the drive level for the complete bit pattern. Three modes are available.

 ov_tx_mode<1:0> = 00b: the transmitter outputs are driven with V

DD_DR respective ov_pattern bit is 1.

when the

 ov_tx_mode<1:0> = 01b: the transmitter outputs are driven with V

DD_AM respective ov_pattern bit is 1.

when the

 ov_tx_mode<1:0> = 10b: the transmitter outputs are stopped (like Type A pause) when the respective ov_pattern bit is 1.

The overshoot protection pattern ov_pattern<13:0> is applied LSB first. For the first 14 clock cycles after the transition from modulated to unmodulated state, each of the 14 bits of the overshoot protection pattern specifies the driver configuration to apply. So ov_pattern<0> defines which driver configuration to apply for the first clock cycle after the transition from modulated to unmodulated state, and ov_pattern<9> defines which driver configuration to apply for the tenth clock cycle after the transition from modulated to unmodulated state.

From the 15th clock cycle on the settings from

TX driver register are used.

The undershoot protection works in a similar manner for transitions from unmodulated state of the carrier to modulated state of the carrier.

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The Ready mode has to be entered by setting the bit en of the

The operation mode and data rate must be then configured by writing the Mode definition register

. In this mode the oscillator is started and the regulators are enabled. When the oscillator operation is stable an interrupt is sent and bit osc_ok indicates it.

and Bit rate definition register

. The receiver and transmitter operation options related to operation mode have to be defined too. If the selected operation mode uses AM modulation for communication reader to tag the modulation depth must be configured.

Before sending any command to a transponder the transmitter and receiver have to be enabled by setting the bits rx_en and tx_en. Several NFC standards define a guard time

DS12484 Rev 4

ST25R3916/7 Application information

(5 ms for ISO14443) requiring that the reader field must be turned on for some time before first command is sent. General purpose timer can be used to count this time or NFC Field

On command with a defined time by the NFC field on guard timer register .

Preparation and execution of a transceive sequence:



Execute the direct command Stop all activities



Execute the direct command Reset RX gain

 Configure the timers accordingly



Define the number of transmitted bytes in the Number of transmitted bytes register 1 and Number of transmitted bytes register 2

 Write the bytes to be transmitted in the FIFO (not in the case of direct commands

REQA and WUPA)

 Send one of the commands Transmit with CRC, Transmit without CRC, Transmit

REQA or Transmit WUPA

 When all the data is transmitted an interrupt is sent to inform the microcontroller that the transmission is finished (IRQ due to end of transmission)

After the transmission is executed, the ST25R3916/7 receiver automatically starts to observe the RFI inputs to detect a transponder response. The RSSI and AGC (in case it is enabled) are started. The framing block processes the subcarrier signal from receiver and fills the FIFO with data. When the reception is finished and all the data is in the FIFO an

interrupt is sent to the microcontroller (IRQ due to end of receive), and the FIFO status register 1

and

FIFO status register 1 display the number of bytes in the FIFO so the

microcontroller can proceed with data download.

If an error or bit collision is detected during reception, an interrupt with appropriate flag is sent, and the microcontroller must take appropriate action.

When data packets longer than FIFO have to be transmitted the sequence detailed above changes.

The FIFO is prepared with data before the transmission starts. An interrupt is sent during the transmission to signal when the remaining number of bytes is lower than the water level

(IRQ due to FIFO water level). The microcontroller then adds more data in the FIFO. When all the data are transmitted an interrupt is sent to inform the microcontroller that the transmission is finished.

The situation during reception time is similar. When the FIFO is loaded with more data than the receive water level, an interrupt is sent and the microcontroller reads the data from the

FIFO. When the reception is finished an interrupt is sent to the microcontroller (IRQ due to

end of receive) the FIFO status register 1

and

FIFO status register 1 display the number of

bytes in the FIFO still to be read.

The ST25R3916/7 listen/target mode is activated by setting to 1 bit targ in the Mode definition register

. There are various target or listening modes implemented depending on setting of the om<3:0> bits, refer to

Table 24: Target operation modes .

The main modes are

 NFCIP-1 active target

 Passive target used for Card mode and NFCIP-1 passive target

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Application information ST25R3916/7

Fixed listen communication mode

Fixed communication mode is active when one of the target modes with om3=0 is selected.

The other om bits control the type of communication.

Passive target

Communication can be performed by the host (through FIFO) or also by using automatic responses as referred in

NFCIP-1 passive target definition register .

These automatic responses include for NFC-A the complete anti-collision including SAK.

Handling of RATS and HLTA is up to the host. For NFC-F only the SENSF_REQ is handled by sending SENSF_RES.

States of NFC-A can be handled by observing Passive target display register

and

Passive target interrupt register bits I_wu_a, I_wu_a*. Direct commands Go to sense and Go to

sleep let the host influence the passive target states.

Responses to SENSF_REQ can be observed by thanks to bit I_wu_f.

The content of the automatic responses is defined by content of PT_Memory.

NFCIP-1 active target

When operating in NFCIP-1 active target mode the following settings are relevant.

 Enable external field detector by setting bit en_fd_c in the

Mode definition register

Using the field detector allows the ST25R3916/7 to turn on a response field depending on nfc_ar setting in the

Bits nfc_n<1:0> of the

Auxiliary definition register influence the timing of Response

collision avoidance sequence.

 The General purpose timer defines the time until RF field off after data transmission. Its trigger sourcehas to be set to the end of transmit, according to

Table 52: Trigger sources

(gptc<2:0> = 011).

 After T

ARFG

either I_cat or I_cac is flagged. T

timer register

ARFG

is defined by NFC field on guard

 MRT starts at external field-on. NRT can be tailored by using nrt_nfc.

 After switching off its field the ST25R3916/7 start the PPON2 timer and observe the

External field detector output to detect the response field. If no external field is detected before PPON2 timer timeout, an IRQ with I_ppon2 flag is signaled.

Bit rate detection mode

The Listen mode can also be started from the so-called Bit rate detection mode. In this mode the communication mode is not fixed. This mode is activated in case of Target mode together with bit om3 set to 1.

The other om bits define the technologies to be recognized. It is an extension of the Fixed listen communication mode.

Once the reception of the first frame starts, the Bit rate detection mode signals an IRQ I_nfct indicating that the bit rate has been identified and the host can retrieve the related information by reading nfc_rate on

Bit rate definition register

When the first frame has been fully received, the host can exit the Bit rate detection mode by setting the corresponding mode on om<3:0> bits in the

Mode definition register

to the corresponding fixed listen communication mode.

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Bit d_ac_ap2p allows filtering of NFCIP-1 active frames.

Low power field detection

The Fixed listen communication and Bit rate detection modes can be enhanced in terms of power consumption by using the field detector in Low-power mode, putting the

ST25R3916/7 in power-down mode (en = 0) while waiting for an external field from a peer/reader.

For this mode the Bit rate detection mode or the Fixed listen communication mode have to be selected, and bits en, rx_en and tx_en in the

need to be cleared to 0.

In this mode the field detector has to be configured to automatic or manual peer detection threshold.

On detection of external field (I_eon) the ST25R3916/7 temporarily enable the oscillator and the receiver. The host needs to confirm it by setting en and rx_en option bits in the

2. NFC-212/424k SENS_RES format, see Table 8 . The last two bytes in SENSF_RES are transmitted based

within 10 ms.

From this point on normal bit rate detection or normal target communication can be performed.

PT memory

The PT_Memory is used to store data for NFCIP-1 passive target and NFC-A card/listen mode. It is loaded via the host interface as described in

Section 4.3

Location

Table 7. PT_Memory address space

Description Data usage

0-9 NFCID1 (4/7/RFU bytes)

10,11 SENS_RES2:1

4 bytes: locations 0-3

7 bytes: locations 0-6

SENS_REQ response

SELR_L1

SELR_L2

SEL Level 1 response.

SEL Level 2 response

14 SELR_L3

15,16 NFCF_SC

RFU

System code (SC) in SENSF_REQ

17-35 212/424 polling response SENSF_RES format (2)

(1)

NFC-A anticollision

NFC-F anticollision

36-47 TSN - Random numbers

Slot selection, 24 4-bit random numbers are stored

(3) (4)

1. SENSF_RES is transmitted in case received SC=NFCF_SC or SC=0xFFFF.

on the RC bytes in the SENSF_REQ.

3. The 4-bit slot numbers are sequentially used in the NFC212/424 Polling response. When only four TSN numbers remain unused, an IRQ with I_sl_wl bit is sent.

4. Depending on the number of slots in the Polling request, appropriate number of the MSB bits in the slot number is used.

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Application information ST25R3916/7

Table 8. NFC-212/424k SENS_RES format

Byte 1 Bytes 2-9 Bytes 10-11 Bytes 12-14 Byte 15 Byte 16

01h NFCID2 PAD0 PAD1 MRTICHECK MRTIUPDATE

Byte 17 Bytes 18-19

PAD2 [RD]

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4.3

Application information

Communication with an external microcontroller

The ST25R3916/7 communicate with a microcontroller either via an SPI interface or via an

I2C interface. On both interfaces the ST25R3916/7 act as slave devices, relying on the microcontroller to initiate all communication. To notify the microcontroller of completed commands or external events (e.g. peer device field on) the ST25R3916/7 signal an interrupt on the IRQ pin. The ST25R3916/7 can also provide a configurable clock signal to the microcontroller on the MCU_CLK pin.

Note:

There are four interrupt registers implemented in the ST25R3916/7:



Main interrupt register



Timer and NFC interrupt register



Error and wake-up interrupt register



Passive target interrupt register

When an interrupt condition is met the source of interrupt bit is set and the IRQ pin transitions to high. The microcontroller then reads the

Main interrupt register to distinguish

between different interrupt sources. After a particular interrupt register is read, its content is reset to 0.

The IRQ pin transitions to low after the interrupt bit(s) that caused its transition to high has

(have) been read.

There may be more than one interrupt bit set if the microcontroller does not immediately read the interrupt registers after the IRQ signal is set and another event causing an interrupt occurs. In this case the IRQ pin transitions to low after the last bit causing interrupt is read.

If an interrupt from a certain source is not required it can be disabled by setting the corresponding bit in the Mask interrupt registers. In case of masking a certain interrupt source the IRQ line is not set high, but the interrupt status bit is still set in IRQ status registers.

Reading the IRQ status registers presents and clears also the masked interrupt bits.

If some interrupts are masked, and set to 1 because of an IRQ event, and later on one of them unmasks the IRQ status bit that is already set, the IRQ line is immediately set to high.

This notifies the host system that there are some interrupt events not yet read out.

Name

IRQ

Table 9. IRQ output

Signal Level

Digital output CMOS

Description

Interrupt output pin

IRQ line and IRQ status bits are cleared at:

 Set default

 Reading the IRQ status

 Stop all activities

 Clear FIFO.

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Application information

4.3.2

4.3.3

ST25R3916/7

FIFO water level and FIFO status registers, FIFO reset

The ST25R3916/7 features a 512 byte FIFO. The control logic shifts the data during transmission, which was previously loaded by the external microcontroller to the framing block and further to the transmitter. During reception, the demodulated data is stored in the

FIFO and the external microcontroller can receive data at a later moment.

The

FIFO status register 2 also contains two bits that indicate that the FIFO was not

correctly served during TX/RX process (FIFO overflow and FIFO underflow).

A FIFO overflow is set when too many data are written into the FIFO. When this bit is set during RX the external controller did not react on time on the water level IRQ and more than

512 bytes were written into the FIFO (including received CRC bytes). Consequently, the received data is corrupted. When an overflow happens during TX, it means that the controller has written more data than the FIFO size. The data to be transmitted is corrupted.

A FIFO underflow is set when data were read from an empty FIFO. When this bit is set during RX the external controller read more data than was actually received. When an underflow happens during TX, it means that the controller has failed to provide the quantity of data defined in the number of transmitted bytes registers on time.

FIFO pointers and FIFO status are reset at the start of each data reception (at I_rxs). They are also reset at Power-up and at commands Set Default and Clear FIFO. Reading out data from empty/cleared fifo shows data = 0.

MCU_CLK

The pin MCU_CLK may be used as clock source for the external microcontroller. Depending on the operation mode either a low frequency clock (32 kHz) from the RC oscillator or the clock signal derived from crystal oscillator is available on pin MCU_CLK. The MCU_CLK output pin is controlled by bits out_c<1:0> and lf_clk_off in the

Table 10 provides an overview of the SPI signals.

Bits out_c<1:0> enable the use of pin MCU_CLK as clock source and define the division when the crystal oscillator is running (13.56, 6.78 and 3.39 MHz are available). Bit lf_clk_off controls the use of low frequency clock (32 kHz) when the crystal oscillator is not running.

By default configuration, which is defined at power-up, the 3.39 MHz clock is selected and the low frequency clock is enabled.

If the Transparent mode (see

Section 4.4.13

) is used the use of MCU_CLK is mandatory since a clock synchronous with the field carrier frequency is needed to implement receive and transmit framing in the external controller. The use of MCU_CLK is recommended also when the internal framing is used. Using MCU_CLK as the microcontroller clock source generates noise, synchronous with the reader carrier frequency and therefore filtered out by the receiver, while using some other incoherent clock source may produce noise that perturbs the reception. Use of MCU_CLK is also better for EMC compliance.

Communication interface selection

The active communication interface is selected via the I2C_EN pin. If this pin is pulled to

GND, the ST25R3916/7 operate in SPI mode. If this pin is pulled to V

DD_D

ST25R3916/7 operate in I2C mode.

, the

Serial peripheral interface (SPI)

The ST25R3916/7 have a standard serial peripheral interface with clock polarity of 0, a clock phase of 1, and an active low slave select signal. Communication starts with the MCU pulling BSS low. The MOSI pin is samples on the falling edge of SCLK, and the state of the

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ST25R3916/7 Application information

MISO pin is updated on the rising edge of the SCLK signal. Data is transferred byte-wise, most significant bit first. Read and Write commands support an address auto increment to reduce communication time.

Name

Table 10. Serial data interface (4-wire interface) signal lines

Signal

I2C_EN

BSS

Digital input

Digital input with pull-up

MOSI Digital input

MISO Digital output with tristate

SCLK

IRQ

Digital input

Digital output

Signal level

CMOS

Description

Pull to GND for SPI operation

Active low - Slave select

Master out - Slave in (MCU → ST25R3916/7)

Master in - Slave out (ST25R3916/7 → MCU)

Serial clock

Active high - Interrupt output pin

The MISO output is in tristate as long as no output data is available. Due to this the MOSI and the MISO can be externally shorted to create a three-wire SPI. During the time the

MISO output is in tristate, it is also possible to switch on a 10 k Ω pull down by activating option bits miso_pd1 and miso_pd2 in the

Table 11 shows available SPI operation modes. Register read and write operations are

Figure 12. Exchange of signals with a microcontroller

Separate SPI input and output signals to MCU

Bidirectional data

IO signal to MCU

MOSI MOSI MOSI

I/O

MISO MISO MISO

MS51643V2

The first two bits of the first byte transmitted after the BSS high to low transition define the

SPI operation mode. All Read and Write modes support address auto incrementing, which means that if, after the address and first data byte some additional data bytes are sent (or read), they are written to (or read from) addresses incremented by 1.

possible in all ST25R3916/7 operation modes. FIFO and PT_memory operations are possible in case en (bit 7 of the

Operation control register ) is set and the crystal oscillator is

stable.

Some direct commands are accepted in all operation modes, others require en (bit 7 of the

Figure 13 and Figure 14 show cases of writing, respectively, a single byte and multiple bytes

) to be set and the crystal oscillator to be stable (see

Table 13 ).

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Application information

Mode

FIFO load

PT_memory load

A-config

PT_memory load

F-config

PT_memory load

TSN data

PT_memory read

FIFO read

Direct command

ST25R3916/7

Table 11. SPI operation modes

Pattern (communication bits)

Mode Trailer Related data

M1 M0 C5 C4 C3 C2 C1 C0

0 0 A5 A4 A3 A2 A1 A0 Data byte (or more bytes in case of

0 1 A5 A4 A3 A2 A1 A0 auto-incrementing)

1 0 0 0 0 0 0 0 One or more bytes of FIFO data

1 0 1 0 0 0 0 0 Passive target memory, locations from 0 on.

1 0 1 0 1 0 0 0 Passive target memory, locations from 15 on.

Passive target memory, locations from 36 on.

The additional address allows reload of the

TSN random numbers without rewriting the whole PT_memory

Passive target memory, locations from 0 on.

A 0 byte is presented to the passive target memory to support reading at all SPI speeds.

1 0 0 1 1 1 1 1 One or more bytes of FIFO data

1 1 C5 C4 C3 C2 C1 C0 -

Writing data to addressable registers (Write mode)

with auto-incrementing address. After the SPI operation mode bits, the address of register to be written is provided. Then one or more data bytes are transferred from the SPI, always

MSB to LSB. The data byte is written in register on falling edge of its last clock. If the register on the defined address does not exist or it is a read only register no write is performed.

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BSS

SCLK

Application information

Figure 13. SPI communication: writing a single byte

Raising edge indicates end of

Write mode

MOSI

X 0 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X

Two leading bits indicate mode

SCLK rising edge

Data transferred from MCU

SCLK falling edge

Data is sampled

Data is moved to address <A5-A0>

MS51644V1

Figure 14. SPI communication: writing multiple bytes

BSS

BSS raising edge indicates end of

Write mode

SCLK

MOSI X 0 0 A5

Two leading 0s indicate Write mode

SCLK falling edge

Data moved to address <A5-A0>

SCLK falling edge

Data moved to address <A5-A0> + 1

SCLK falling edge

Data moved to address <A5-A0> + (n-1)

SCLK falling edge

Data moved to address <A5-A0> + n

MS51645V1

Reading data from addressable registers (Read register mode)

The SPI operation mode bits are followed by the address of the register to be read. Then one or more data bytes are transferred to MISO output (MSB first) for as long as SCLK is present. This mode also supports address auto-incrementing. If there is no register at a certain address, then all 0 data is sent to MISO.

Figure 15

is an example of reading a single byte.

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Application information

Figure 15. SPI communication: reading a single byte

BSS

SCLK

ST25R3916/7

BSS raising edge indicates end of

Read mode

MOSI

X 0 1 A5 A4 A3 A2 A1 A0 X

MISO tristate D7 D6 D5 D4 D3 D2 D1 D0

Two leading bits indicate Mode

SCLK rising edge

Data moved from

Address A5-A0

SCLK rising edge

Data transferred from MCU

SCLK falling edge

Data is sampled

SCLK falling edge

Data transferred to MCU

MS51646V1

Read or write access to register space-B

To access the register space-B the register read or write SPI sequence has to be prefixed with the byte FBh. Access to register space-B remains active until the rising edge of BSS.

Loading transmitting data into FIFO

Loading the transmitting data into the FIFO is similar to writing data into an addressable registers. The SPI sequence starts with SPI operation mode bits ‘10’ to indicate a FIFO operation followed by bits <C5:C0> set to 000000b. After the FIFO mode byte at least one and up to 512 data bytes must be sent.

Figure 16

shows how to load the transmitting data into the FIFO.

Figure 16. SPI communication: FIFO loading

BSS

SCLK

MOSI

X 1 0 0 0 0 0 0 0

1 to 512 bytes tristate

BSS raising edge indicates end of FIFO mode

10 pattern indicates

FIFO mode

Start of paylod data

SCLK rising edge

Data transferred from MCU

SCLK falling edge

Data is sampled

MS51647V1

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Reading received data from FIFO

Reading received data from the FIFO is similar to reading data from an addressable registers. The SPI sequence starts with SPI operation mode bits ‘10’ to indicate a FIFO operation followed by <C5:C0> set to 011111b. After the mode byte the ST25R3916/7 will output the data from the FIFO as long as SCLK is present and BSS is kept low.

Figure 17. SPI communication: FIFO reading

BSS

BSS raising edge indicates end of FIFO mode

SCLK

MOSI

X 1 0 0 1 1 1 1 1 X

MISO tristate

1 to 512 bytes tristate

10 pattern indicates

FIFO mode

SCLK rising edge

Data moved from FIFO

SCLK rising edge

Data transferred from MCU

SCLK falling edge

Data is sampled

SCLK falling edge

Data transferred to MCU

MS53128V1

Direct command mode

Direct command mode has no arguments, so a single byte is sent. The byte starts with the

SPI operation mode bits ‘11’ to indicate Direct Command Mode followed by the direct command code (see

Table 13 ) in <C5:C0>, MSB first. Execution of the direct command

starts with the rising edge of BSS (see Figure 18 ).

While the execution of some direct commands is immediate, there are others that start a process of certain duration (e.g. calibration, measurements). During the execution of such commands it is not allowed to start another activity over the SPI interface, an IRQ is sent. when the execution is terminated.

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Figure 18. SPI communication: direct command

/SS

SCLK

ST25R3916/7

/SS raising edge indicates start of command execution

MOSI

X 1 1 C5 C4 C3 C2 C1 C0 X

Two leading 1s indicate

Command Mode

SCLK rising edge

Data transferred from MCU

SCLK falling edge

Data is sampled

MS42466V1

Direct command chaining

As shown in

Figure 19

, direct commands with immediate execution can be followed by another SPI mode (Read, Write or FIFO) without deactivating the BSS signal in between.

Figure 19. SPI communication: direct command chaining

BSS

Direct command Read, Write or FIFO mode

MS51649V1

Loading data in the PT_Memory (PT_Memory load)

Loading data into the PT_Memory is similar to loading data into the FIFO. There are three mode patterns available to load data into three different parts of the PT_memory, as indicated in

Table 11 . The first byte following the mode/address pattern is stored in the location detailed in Table 11

, for consecutive bytes the address is automatically incremented and data are stored to consecutive addresses.

The user must take care that the number of loaded bytes fits the size of the selected

PT_memory area, not to overwrite data in the following PT_memory areas.

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The I2C address is 50h.This interface supports:

 Standard mode (100 kHz)

 Fast mode (400 kHz)

 Fast mode Plus (1 MHz)

 High speed mode (3.4 MHz).

Table 12 summarizes the I2C interface signals.

DS12484 Rev 4

ST25R3916/7 Application information

Name

I2C_EN

MISO (SDA)

SCLK (SCL)

IRQ

Table 12. I2C interface and interrupt signal lines

Signal Signal level Description

Digital input

Digital output

Digital input

Digital output

CMOS

Pull to VDD_D for I2C operation

I2C data line

I2C clock

Active high - Interrupt output pin

Writing data to addressable registers (Register Write mode)

After the I2C slave address the address of the register to be written is sent using the same

Register Write mode byte as for SPI register write access. The Register Write mode byte is then followed by one or more data bytes. If more than one data byte is sent, the data is stored in subsequent registers starting form the initial register address by incrementing the target address by one for each new data byte.

Figure 20

and

Figure 21 show, respectively, how to write a single byte into a register and

how to write multiple bytes into subsequent registers using address auto-incrementing.

Figure 20. Writing a single register

SCL

SDA

0 0

Slave address Register address Data

MS51653V2

Figure 21. Writing register data with auto-incrementing address

SCL

SDA S

0 0

Slave address Register address

Data moved to address

<R5-R0> + 0

Data moved to address

<R5-R0> + n

MS51654V3

Reading data from addressable registers (Register Read mode)

After the I2C slave address the address of the register to be read is sent using the same

Register Read mode byte of the SPI register read access. After the Register Read mode byte the ST25R3916/7 sends data bytes to the SDA output as long as the MCU keeps SCL.

The Register Read mode also supports address auto-incrementing. If the addressed register does not exist, all 0 data is sent to SDA.

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Figure 22

shows how to read a single byte from a register.

Figure 22. Reading a single byte from a register

ST25R3916/7

SCL

SDA S

0 1

Slave address Register address Slave address Data

MS51655V2

Loading data into FIFO or PT_Memory (FIFO/PT_Memory load)

Loading data into FIFO or PT_Memory is similar to writing data into addressable registers.

After the I2C slave address the mode byte to trigger a load of the FIFO or selected

PT_Memory area is sent (see

Table 11 ) followed by the data bytes to be loaded.

Figure 23

shows how to load data into the FIFO.

Figure 23. FIFO load

SCL

SDA

1 0 0 0 0 0 0 0

Slave address FIFO load Data Data

MS51656V1

Reading data from the FIFO

Reading data from the FIFO is similar to reading data from addressable registers. After the

I2C slave address the mode byte to trigger a read of the FIFO is sent. After receiving the

FIFO read mode byte the ST25R3916/7 sends data bytes from the FIFO for as long as the

MCU keeps reading the bus.

Figure 24. FIFO read

SCL

SDA

1 0 0 1 1 1 1 1

Slave address FIFO read

Slave address Data

MS51657V1

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ST25R3916/7 Application information

Direct command mode

After the I2C slave address the mode byte to trigger a direct command is sent. As for SPI some direct commands take some time to execute and no I2C access to the ST25R3916/7 must be performed until the execution of the direct command is completed. All such direct commands send an interrupt upon completion to notify the MCU that the I2C bus can be used again.

Figure 25. Sending a direct command

SCL

SDA

1 1

Slave address Direct command byte

MS51658V1

I2C access to register space-B

To access the register space-B, byte FBh has to be inserted between the I2C slave address and the register read or write mode byte. Access to register space-B remains active until an

I2C Stop Condition is received.

Figure 26. Read and Write mode for register space-B access

Write to register space B

Slave address W

A FBh

A Data 0 A Data 1 A ...

Data N A P

Read from register space B

Slave address W

A FBh

A Sr

Slave address R

A Data 0

Legend: S: Start, Sr: repeated Start, A: ACK, N: NAK, P: Stop.

A Data 1 A ...

Data N N P

I2C: transition to and termination of the Transparent mode

When the transparent mode command is received via I2C, the chip interface lines are switched to the Analogue front end as described in

Section 4.4.13: Transparent mode .

Once in transparent mode the BSS signal is used to distinguish between I2C communication and transparent mode data as follows:

the BSS line must be set high before entering the transparent mode, and then kept high during the Transparent mode

2. the Transparent mode is terminated when the BSS line is set to low, followed by at least one SCL clock pulse

3. after the termination of the transparent mode the I2C interface can be used again.

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I2C: master reads slave immediately after the first byte

If the I2C master omits the mode byte and reads the ST25R3916/7 immediately after the slave address, then, as shown in

Figure 27 , it will first output the byte FFh, followed by a

Figure 27. I2C master reads slave immediately after the first byte

S Slave address R A Data FFh A Data register 01h A ...

Data register n N P

Legend: S: Start, A: ACK, N: NAK, P: Stop.

This mode is incorporated for an easier the detection of I2C devices, but is not intended to be used in normal operation.

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ST25R3916/7 Application information

Code

(hex)

C0, C1 Set default

Name

C2, C3 Stop all activities

C4 Transmit with CRC

C5 Transmit without CRC

C6 Transmit REQA

C7 Transmit WUPA

C8 NFC initial field ON

C9 NFC response field ON

CD Go to sense (Idle)

CE Go to sleep (Halt)

D0 Mask receive data

D1 Unmask receive data

Change AM modulation state

D3 Measure amplitude

D5 Reset RX gain

D6 Adjust regulators

D8 Calibrate driver timing

D9 Measure phase

Table 13. List of direct commands

Comments Chaining

Interrupt after termination

Operation mode

(1)

Puts the ST25R3916/7 into powerup state

Stops all activities: transmission, reception, direct command execution, timers

Starts a transmit sequence with automatic CRC generation

Starts a transmit sequence without automatic CRC generation

Transmits REQA command

(ISO14443A mode only)

Transmits WUPA command

(ISO14443A mode only)

Performs Initial RF Collision avoidance and switches on the field

Performs Response RF Collision avoidance and switches on the field

Puts the passive target logic into

Sense (Idle) state

Puts the passive target logic into

Sleep (Halt) state

Stops receivers and RX decoders

Starts receivers and RX decoders

Yes

All en en en en, tx_en en, tx_en

Yes en

Yes

No en en, rx_en en, rx_en

All

Yes No en, tx_en Changes AM modulation state

Measures the amplitude of the signal present on RFI inputs and

stores the result in the A/D converter output register

Resets receiver gain to the value in

the Receiver configuration register 4

Adjusts supply regulators according to the current supply voltage level

Starts the driver timing calibration according to the setting in the

TX driver timing display register

Measures the phase difference between the signal on RFO and RFI

Yes

All

(2) en en en

All

(2)

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Code

(hex)

Name

Table 13. List of direct commands (continued)

Comments

Clears the RSSI bits in the

RSSI display register and restarts the

measurement

DB Clear FIFO Clears FIFO

DC Enter Transparent mode Enters in Transparent mode

Clear RSSI

Calibrate capacitive sensor

Calibrates capacitive sensor

DE Measure capacitance

Measures capacitance between

CSO and CSI pin

DF Measure power supply

Start General purpose timer

Chaining

Interrupt after termination

Operation mode

(1)

Yes

No en en en

All

All en en

E1 Start Wake-up timer Yes No

All except wu

Start Mask-receive timer

Start No-response timer

E4 Start PP

ON2

timer

E8 Stop No-response timer

RFU

Starts the mask-receive timer and squelch operation

Not used

Enables R/W access to register

Space-B

Enable R/W access to Test register

Yes

FC Test access

Other codes

RFU Not used

Yes

1. Defines which Operation control register

bits have to be set in order to accept a particular command.

2. Measure amplitude and Measure phase can be used directly from power down mode. In this case the command temporarily enables the oscillator.

en en en en

all

All

This direct command puts the ST25R3916/7 in the same state as power-up initialization:



performs Stop all activities command

 resets all registers to their default state

 clears all collision bits

Results of previous calibration and adjust commands are lost. No IRQ due to termination of direct command is produced.

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ST25R3916/7 Application information

This direct command stops any ongoing activities:



performs Clear FIFO

command

 stops data transmission and reception

 stops all timers, including FDT timer

 clears IRQ line an IRQ status bits

 stops Field ON commands

If Stop All Activities is received during RF collision avoidance, the field detection is terminated and field is not set, consequently no interrupts are sent

 stops automatic field ON (same as above)

 stops automatic field OFF

If Stop All Activities is received during waiting for automatic field off via GPT, the field remains on

 nfc_ar is set to 01b, then it clears the awareness that there was a previous reception

 stops Temporary Enable

This command does not update any register apart from the FIFO status registers. Therefore it does not disable the field detector in CE mode (if it was enabled), and it does not switch off the field (if it was enabled).

This direct command clears the FIFO and the FIFO status registers. It does not clear the

IRQ line or IRQ status bits.

To prepare a transmission send this command first before writing data into the FIFO. If a

Clear FIFO command is sent during an ongoing data transmission, then the data transmission is aborted and FIFO and FIFO status registers are cleared.

The transmit direct commands are used to start a data transmission from the ST25R3916/7.

They switch the device to reception mode after the transmission is completed.

Before sending commands Transmit with CRC and Transmit without CRC, direct command

Clear FIFO has to be sent, followed by the definition of the number of transmitted bytes and writing data to be transmitted in FIFO.

Use the direct commands Transmit REQA and Transmit WUPA to transmit ISO14443A short frame commands REQA and WUPA respectively. It is not necessary to send the direct command Clear FIFO before these two commands.

If the antcl bit is set, then the number of valid bits in the last byte must be set to 0 (nbtx<2:0> in the

Number of transmitted bytes register 2 ) prior to the direct command Transmit REQA

or Transmit WUPA.

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Application information

4.4.5

ST25R3916/7

The direct commands Transmit REQA and Transmit WUPA automatically disable the CRC check of the response frame. The CRC check is enabled again after any of the below conditions:

 Transmit with CRC direct command

 Mask receive data direct command

 No Response timer expires

If the direct command Transmit without CRC is used in Felica™ mode the Length and CRC bytes are skipped. After the preamble and Sync bytes the raw FIFO content is transmitted.

A transmit length nbtx<2:0> ≥ 1 must be used.

NFC field ON commands

The NFC field ON direct commands are used to perform RF Collision Avoidance. The external field detector must be enabled for these commands to work correctly.

To determine whether an external field is present the ST25R3916/7 compares the RF voltage level on the RFI1 pin with the collision avoidance threshold defined in the

External field detector activation threshold register

If no external field is detected, then the ST25R3916/7 transmitter is switched on

automatically (bit tx_en in the Operation control register

is set) and an I_apon IRQ is

signaled. After the RF guard time defined in the NFC field on guard timer register has

passed an I_cat IRQ is signaled. At this point the controller can initiate a data transmission using a transmit command.

If an external field is detected a I_cac IRQ is signaled, and the ST25R3916/7 transmitter stays off.

The direct command NFC initial field ON performs an Initial collision avoidance according to

NFCIP-1 standard, and the direct command NFC response field ON performs a Response collision avoidance according to NFCIP-1 standard. See

Figure 28

, Figure 29 and Table 14

for details on the timing of these commands.

Figure 28. Direct command NFC initial field ON

RF on

RFW

Start

IDT n x T

RFW

IRFG

MS42450V1

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ST25R3916/7 Application information

Figure 29. Direct command NFC response field ON

RF on

RFW

Start

ADT n x T

RFW

ARFG

MS42451V1

Parameter

Initial delay time

RF waiting time

Initial guard time

Active delay time

Active guard time

Table 14. Timing parameters of NFC field ON commands

Symbol Value Unit Notes

IDT

RFW

IRFG

ADT

ARFG

4096

512

75 µs +

NFC field on guard time

768

75 µs +

NFC field on guard time

/ fc NFC initial field ON

/ fc n = 0…3 based on nfc_n<1:0> in

Auxiliary definition register

NFC field on guard time defined in the NFC field on guard timer register .

NFCIP-1 T

IRFG

requirement: 5 to 35 ms

/ fc NFC response field ON s

NFC field ON guard time defined in the NFC field on guard timer register

NFCPIP-1 T

ARFG

requirement:

> 75 µs + NFC field ON guard times (1024 / fc)

4.4.7

The direct command Mask receive data disables processing of the receiver output by the

RX decoders, RSSI measurement, and AGC operation.

The direct command Unmask receive data enables processing of the received data by the

RX decoders, RSSI measurement and AGC operation. A common use of this command is to re-enable the receiver operation after it was masked by the command Mask receive data.

If the Mask receive timer is still running while the direct command Unmask receive data is received, reception is enabled, and the Mask receive timer is reset.

In passive target (card emulation) mode, the Unmask receive data command prepares the

RX decoders for a new data reception and clears the internal FDT timer. In passive target mode, this direct command must be used only if no further transmission from the

ST25R3916/7 is planned and the device has to wait for the next command to be received.

Change AM modulation state

This command changes the AM modulation state from unmodulated to modulated, and vice versa. This can be used to measure the AM modulation index with the direct command

Measure amplitude

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Application information ST25R3916/7

Note:

4.4.9

This command measures the amplitude of the RF signal on the RFI inputs and stores the result in the

A/D converter output register

This command enables the transmitter and amplitude detector. The transmitter drives the antenna, and the amplitude detector converts the differential RF signal received back between RFI1 and RFI2 into a proportional DC voltage. This DC voltage is converted with

the A/D converter in absolute conversion mode into an 8-bit value and stored in the A/D converter output register

The amplitude detector conversion gain is 0.6 V inPP

/ V out

referenced to the RF signal on a single RFI pin. Thus, one LSB of the A/D converter output represents 13.02 mV

PP of the RFI inputs.

on either

The maximum allowed voltage level on an RFI pin is 3 V

. This results in 1.8 V output DC voltage of the amplitude detector and produces a value of E6h after A/D conversion.

Duration time: 25 μ s max.

Reset RX gain

This command initializes the AGC, Squelch and RSSI block and resets the gain reduction to the value set in

Receiver configuration register 4 . Sending this command also stops any

ongoing squelch process.

When this command is sent, then the transmitter and receiver are enabled to ensure a high current draw and the regulated voltage V

DD_RF of V

DD_TX

is set 250 mV below the power supply level

. Before sending the adjust regulator command it is required to toggle the bit reg_s by setting it first to 1 and then reset it to 0. After the adjustment is completed the state of the transmitter and receiver prior to the command execution is restored (either enabled or disabled).

Duration time: 5 ms max.

This command is not accepted if external definition of the regulated voltage is selected in the

Regulator voltage control register (bit reg_s is set to 1).

This command measures the phase difference between the signals on the RFO outputs and the signals on the RFI inputs and stores the result in the

A/D converter output register .

This command enables the transmitter and phase detector, and performs an A/D conversion of the output of the phase detector with the A/D converter in relative mode. The phase measurement results can be calculated using the following formulas:

 0 ≤ Φ ≤ 17º: result = 255

 17 < Φ < 163º: angle [º] = 17 + (1 -result / 255) * 146

 163 ≥ Φ ≥ 180º: result = 0

Duration time: 25 μ s max.

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ST25R3916/7 Application information

The receiver automatically clears the RSSI bits in the

RSSI display register

and starts a new measurement of the RSSI when a new reception is started (e.g. after a Transmit direct command). Since the RSSI bits store the peak value (peak-hold type) eventual variation of the receiver input signal will not be followed (this may happen in case of a long message or test procedure).

The direct command Clear RSSI clears the RSSI bits in the

RSSI display register , and

restarts the RSSI measurement. This allows to obtain multiple RSSI measurements during a single reception.

This command sets the receiver and transmitter into the transparent mode. The device enters the transparent mode on the rising edge of the BSS signal of the SPI frame used to send the direct command. The transparent mode is maintained as long as signal BSS is kept high, that is, the following SPI command sent from the microcontroller will automatically stop the transparent mode.

4.4.14 Calibrate capacitive sensor

This command calibrates the capacitive sensor.

It is strongly recommended to use this command in power-down mode only to avoid interference with the crystal oscillator or reader magnetic field. Interrupt I_dct is only generated in Ready mode. The measurement status is indicated by status bits in the

Capacitive sensor display register

Duration time: 3 ms max.

This command is executed only if the capacitive sensor automatic calibration mode is set

(all bits cs_mcal in the

Capacitive sensor control register

are set to 0).

This command performs the capacitance measurement.

It is strongly recommended to use this command in power-down mode only to avoid interference with the crystal oscillator or reader magnetic field.

Duration time: 250 μ s max.

This command measures the power supply. The bits mpsv<2:0> in the Regulator voltage control register

select which signal is measured. The result of the measurement is stored in the

A/D converter output register .

For power supply measurements the selected supply input voltage is divided by three and measured with the A/D converter in absolute mode. This leads to a resolution of 23.4 mV per LSB for all power supply measurements.

Duration time: 25 μ s max.

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Bit

The devices do not have dedicated test pins. A direct command Test Access is used to enable RW access of test registers and entry in different test modes. Pins CSI and CSO are used as test pins.

Test mode entry and access to test registers

Test registers are not part of the normal register address space. After sending direct command Test Access, test registers can be accessed using normal Read/Write register command. Access to test registers is possible in a chained command sequence where command Test Access is sent first, followed by read/write access to test registers using auto increment feature. Test register are set to default state at power-up.

Analog test and observation register 1

Address: 01h

Type: RW

Name tana7 tana6 tana5

tana3 tana2 tana1 tana0

Table 15. Analog test and observation register 1

Default Function Comments

Reserved

See Table 16

These test modes are also intended for observation in normal mode. Other modes of this register are also available when analog test mode is not set.

Table 16. Test access register - Signal selection of CSI and CSO pins

Pin CSI Pin CSO tana3:0

(hex)

Type Functionality Type Functionality Comment

Analog output of AM channel (before digitizer)

Analog output of PM channel (before digitizer)

Analog output of AM channel (before digitizer)

Analog output of AM correlation signal

Tag demodulator analog

Digital output of AM channel (after digitizer)

Digital output of PM channel (after digitizer)

Analog output of PM channel (before digitizer)

Analog output of PM correlation signal

Tag demodulator OOK digital out

Tag demodulator ASK digital out

Normal operation

(reader)

Normal operation

(tag)

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ST25R3916/7 Application information

Table 16. Test access register - Signal selection of CSI and CSO pins (continued)

Pin CSI Pin CSO tana3:0

(hex)

Type Functionality Type Functionality Comment

Digital output of AM correlation data signal

Digital output of PM correlation data signal

Analog output of AM correlation signal

Analog output of PM correlation signal

Digital output of AM correlation collision/start detection signal

Digital output of PM correlation collision/start detection signal

Correlation digitizing threshold for AM channel

Correlation digitizing threshold for PM channel

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4.5 Registers

The ST25R3916/7 have two register spaces, each of them consists of up to 64 registers with address ranging from 00h to 3Fh:

Table 17

2. register space B (Rs-B), see Table 18

There are two types of registers implemented in the ST25R3916/7:

configuration registers: used to configure the device, can be written and read through the SPI or I2C interfaces

2. display registers: read only (RO), contain information about the state of the device.

Registers are set to their default value at power-up and after sending the direct command

Set default .

Type

IO configuration

Operation control and mode definition

Protocol configuration

Receiver configuration

Timer definition

Table 17. List of registers - Space A

Address (hex) Register space A (Rs-A)

Mode definition register

Bit rate definition register

ISO14443A and NFC 106kb/s settings register

ISO14443B settings register 1

ISO14443B and FeliCa settings register

NFCIP-1 passive target definition register

Stream mode definition register

Auxiliary definition register

Receiver configuration register 1

Receiver configuration register 2

Receiver configuration register 3

Receiver configuration register 4

Mask receive timer register

No-response timer register 1

No-response timer register 2

Timer and EMV control register

General purpose timer register 1

General purpose timer register 2

PPON2 field waiting register

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Type

Interrupt and associated reporting

Definition of number of transmitted bytes

A/D converter output

Antenna calibration

Antenna driver and modulation

External field detector threshold

Regulator

Receiver state display

Capacitive sensor

Auxiliary display

Table 17. List of registers - Space A (continued)

Address (hex) Register space A (Rs-A)

Mask main interrupt register

Mask timer and NFC interrupt register

Mask error and wake-up interrupt register

Mask passive target interrupt register

Main interrupt register

Timer and NFC interrupt register

Error and wake-up interrupt register

Passive target interrupt register

FIFO status register 1

FIFO status register 2

Collision display register

Passive target display register

Number of transmitted bytes register 1

Number of transmitted bytes register 2

Bit rate detection display register

A/D converter output register

Antenna tuning control register 1

Antenna tuning control register 2

TX driver register

Passive target modulation register

External field detector activation threshold register

External field detector deactivation threshold register

Regulator voltage control register

RSSI display register

Gain reduction state register

Capacitive sensor control register

Capacitive sensor display register

Auxiliary display register

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Application information

Wake-up

Type

ST25R3916/7

Table 17. List of registers - Space A (continued)

Address (hex) Register space A (Rs-A)

Wake-up timer control register

Amplitude measurement configuration register

Amplitude measurement reference register

Amplitude measurement auto-averaging display register

Amplitude measurement display register

Phase measurement configuration register

Phase measurement reference register

Phase measurement auto-averaging display register

Phase measurement display register

Capacitance measurement configuration register

Capacitance measurement reference register

Capacitance measurement auto-averaging display register

Capacitance measurement display register

IC identity register

IC identity

Protocol configuration

Receiver configuration

Timer definition

Antenna driver and modulation

External field detector threshold

Regulator

Protection

Type

Table 18. List of registers - Space B

Address (hex) Register space B (Rs-B)

EMD suppression configuration register

Subcarrier start timer register

P2P receiver configuration register 1

Correlator configuration register 1

Correlator configuration register 2

Squelch timer register

NFC field on guard timer register

Auxiliary modulation setting register

TX driver timing register

Resistive AM modulation register

TX driver timing display register

Regulator display register

Overshoot protection configuration register 1

Overshoot protection configuration register 2

Undershoot protection configuration register 1

Undershoot protection configuration register 2

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Bit

Address: 00h

Type: RW

Name single rfo2 i2c_thd1 i2c_thd0

RFU out_cl1 out_cl0 lf_clk_off

Default

Table 19. IO configuration register 1

Function

0: LF clock on MCU_CLK

1: No LF clock on MCU_CLK

Comments

0: Differential antenna driving

1: Only one RFO driver will be used

0: RFO1, RFI1

1: RFO2, RFI2

Chooses between single and differential antenna driving.

Chooses which output driver and which input will be used in case of single driving.

I2C t

: non hs-modes / hs-modes

00: 380 ns / 160 ns

01: 180 ns / 160 ns

10: 180 ns / 70 ns

11: 100 ns / 70 ns

out_cl1 out_cl0 MCU_CLK

3.39 MHz

6.78 MHz

13.56 MHz

Selection of clock frequency on

MCU_CLK output in case Xtal oscillator is running. With “11”

MCU_CLK output is permanently low.

Disabled

By default the 32 kHz LF clock is present on MCU_CLK output when

Xtal oscillator is not running and the

MCU_CLK output is not disabled.

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Bit

Address: 01h

Type: RW

Name sup3V vspd_off aat_en miso_pd2 miso_pd1 io_drv_lvl am_ref_rf slow_up

Default

Table 20. IO configuration register 2

0: 5 V supply

1: 3.3 V supply

Function

0: Enable V

DD_D

regulator

1: Disable V

DD_D

regulator

0: Disable AAT D/A

1: Enable AAT D/A

Comments

Set to 0 for 3.6 V < V

≤ 5.5 V

Set to 1 for 2.4 V ≤ V

≤ 3.6 V

Used for low cost applications. When this bit is set:

– at 3 V or 5 V supply VDD_D and VDD_A must be shorted externally

The AAT D/A converters are enabled if both aat_en and en are set. If only aat_en is set and en is cleared, then the AAT outputs are set to a fixed value.

Note that for the fixed value to operate, en must have been set to 1 at least once, prior to having en = 0.

1: Pull-down on MISO, when BSS is low and MISO is not driven by the

ST25R3916/7.

1: Pull-down on MISO when BSS is high

Valid only in SPI mode.

0: Normal IO driver level

1: Increase IO driving level

Increases IO driver strength of MISO,

MCU_CLK an IRQ.

Recommended to set to 1 for all I2C operation, and for SPI operation if

DD_IO

< 3.3 V.

0: V

DD_AM

regulator reference from

DD_DR

1: V

DD_AM

regulator reference from

DD_RF

1: Slow ramp at Tx on

Selects non modulated RF voltage level reference of the V

DD_AM

voltage regulator.

≥ 10 µs, 10% to 90%, for B

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4.5.3 Operation control register

Address: 02h

Type: RW

Bit Name Default

Table 21. Operation control register

(1)

Function Comments

0 en rx_en rx_chn rx_man tx_en wu en_fd_c1 en_fd_c0

1: Enables oscillator and regulator

(Ready mode)

1: Enables Rx operation

0: Both, AM and PM, channels enabled

1: One channel enabled

0: Automatic channel selection

1: Manual channel selection

1: Enables Tx operation

1: Enables Wake-up mode

If only one Rx channel is enabled, selection is

done by the Receiver configuration register 1

bit ch_sel.

If both Rx channels are enabled, chooses the method of channel selection, manual selection is

done by the Receiver configuration register 1

bit ch_sel.

This bit is automatically set by NFC Field ON commands and reset in NFC active communication modes after transmission is finished.

According to settings in Wake-up timer control register .

00: External field detector off.

01: Manually enable external field detector with collision avoidance detection threshold.

10: Manually enable external field detector with peer detection threshold.

11: Enable external field detector automatically.

11: External field detector with peer detection/collision avoidance threshold activated automatically (used for NFCIP-1 P2P modes).

en_fdc1:0>0 and other bits in this register are set to 0 put device in a low power initial NFC mode.

1. Default setting takes place at power-up only.

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4.5.4 Mode definition register

Address: 03h

Type: RW

Bit Name Default

Table 22. Mode definition register

(1)

Function Comments

7 targ 0

0: Initiator

1: Target

3 om3 om2 om1 om0

Refer to Table 23 and Table 24

Selection of operation mode.

Different for initiator and target modes.

0 tr_am nfc_ar1 nfc_ar0

0: OOK

1: AM

00: Off

01: Automatic field on after any reception (including errors)

10: Always after peer field-off

11: RFU

Selects RF modulation mode.

Automatically starts the Response RF collision avoidance.

1. Register can be written only in case crystal clock is present and stable (oscok = 1).

om3 om2

Table 23. Initiator operation modes (1) om1 om0 Comments

NFCIP-1 active communication

ISO14443A

ISO14443B

FeliCa

™

NFC Forum Type 1 tag (Topaz)

Sub-carrier stream mode

1 1 1

Other combinations

1 BPSK stream mode

RFU

1. If a non supported operation mode is selected the Tx/Rx operation is disabled.

om3

0 om2

Table 24. Target operation modes

(1)(2) om1 om0 Comments

ISO14443A passive target mode

FeliCa

™

passive target mode

NFCIP-1 active communication mode

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Table 24. Target operation modes (1)(2) (continued) om1 om0 Comments

1 x x x

Bit rate detection mode

– om2: enable FeliCa

™

bit rate detection mode

– om1: RFU

– om0: enable ISO14443A bit rate detection mode

Not allowed Other combinations

1. The nfc_f0 = 1 must not be set in Bit rate detection mode (see

Table 26

2. When in Passive target and Bit rate detection modes, the pt_res setting is used to generate the RF field

(high ohmic setting of pt_res can prevent RF field generation).

Bit

4.5.5

Name

RFU

RFU tx_rate1 tx_rate0

RFU

RFU rx_rate1 rx_rate0

Bit rate definition register

Address: 04h

Type: RW

Default

Table 25. Bit rate definition register

Function

Refer to

Table 26

Comments

Selects bit rate for Tx.

Selects bit rate for Rx.

rate3 rate2 rate1 rate0

Table 26. Bit rate coding (1)

Bit rate (kbit/s)

0 1

Other combinations

1 fc / 128 (~106) fc / 64 (~212) fc / 32 (~424) fc / 16 (~848)

1. If a non supported bit rate is selected the Tx/Rx operation is disabled.

Not used

Comments

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4.5.6 ISO14443A and NFC 106kb/s settings register

Address: 05h

Type: RW

Bit Name

Table 27. ISO14443A and NFC 106kb/s settings register

Default Function Comments

5 no_tx_par no_rx_par nfc_f0

1: No parity bit is generated during Tx

1: Receive and put in FIFO also the parity bit

Data stream is taken from FIFO, transmit to be done using command Transmit Without CRC

(1)

When set to 1 received bit stream is put in the

FIFO, no parity and CRC detection is done

(1)

Supported only for 106 kbit/s data rate.

1: Support of NFCIP-1 Transport

Frame format

Adds SB (F0) and LEN bytes during Tx and skip

SB (F0) byte during Rx.

Must not be set in bit rate detection mode.

1 p_len3 p_len2 p_len1 p_len0

Refer to Table 28

Modulation pulse width, defined in number of

13.56 MHz clock periods.

0 antcl 0

0: Standard frame

1: ISO14443 anticollision frame

Must be set to 1 for reception of ISO14443A bit oriented anticollision frames in reader mode.

Must be set to 0 for all other frames and modes.

1. Supported in reader modes only, not supported in card emulation modes.

Table 28. ISO14443A modulation pulse width

Pulse width in number of 1 / fc for different bit rates p_len3 p_len2 p_len1 p_len0 fc / 128 fc / 64 fc / 32 fc / 16

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Table 28. ISO14443A modulation pulse width (continued)

Pulse width in number of 1 / fc for different bit rates p_len3 p_len2 p_len1 p_len0 fc / 128 fc / 64 fc / 32 fc / 16

4.5.7

Bit

ISO14443B settings register 1

Address: 06h

Type: RW

Name Default egt2 egt1

0 egt2

Table 29. ISO14443B settings register 1

Function egt1

0 egt0 Number of etu

0 0

1 1

Comments

EGT defined in number of etu

1 egt0 sof_0 sof_1 eof half

0 rx_st_om

0: 10 etu

1: 11 etu

0: 2 etu

1: 3 etu

0: 10 etu

1: 11 etu

0: SOF and EOF defined by sof_0, sof_1, and eof bit

1: SOF 10.5 etu logic 0, 2.5 etu logic 1,

EOF: 10.5 etu logic 0

SOF, number of etu with logic 0

SOF, number of etu with logic 1

EOF, number of etu with logic 0

Sets SOF and EOF settings in middle of specification.

0: Start/stop bit must be present for Rx

1: Start/stop bit omission for Rx

SOF fixed to 10 low and 2 etu high, EOF not defined, put in FIFO last full byte .

CRC is not checked in this mode.

Supported only in a coherent reception mode.

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4.5.8

Bit

Name tr1_1 tr1_0

RFU

RFU f_p1

ISO14443B and FeliCa settings register

Address: 07h

Type: RW no_sof no_eof f_p0

Default

Table 30. ISO14443B and FeliCa settings register

Function Comments

Refer to

Table 31

1: No SOF PICC to PCD

1: No EOF PICC to PCD

According to ISO14443-3 chapter 7.10.3.3.

Support of B’.

According to ISO14443-3 chapter 7.10.3.3.

Supported only in coherent reception mode.

00: 48

01: 64

10: 80

11: 96

FeliCa

™

preamble length (valid also for NFCIP-1 active communication bit rates 212 and 424 kb/s) tr1_1

Table 31. Minimum TR1 codings

Minimum TR1 for a PICC to PCD bit rate tr1_0 fc / 128 >fc / 128

80 / fs

64 / fs

Not used

32 / fs

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4.5.9 NFCIP-1 passive target definition register

Address: 08h

Type: RW

Bit

Name fdel3 fdel2 fdel1 fdel0 d_ac_ap2p

2 d_212/424_1r

1 RFU

0 d_106_ac_a

Table 32. NFCIP-1 passive target definition register

Default Function Comments

PCD to PICC FDT compensation.

Frame compensation defined as fdel<3:0>*1 / fc

Valid for NFC-A CE mode

– fdel = 0: Nominal FDT time in produced in logic.

– fdel > 0: Shortens the FDT provided by logic.

Due to signal processing delays fdel<3:0> = 2 is expected to be a good setting (best value dependents also on filter and antenna).

0: Enable AP2P frame recognition

1: Disable AP2P frame recognition

0: Enable automatic SENSF_RES

1: Disable automatic SENSF_RES

RFU

0: Enable automatic anti-collision in NFC-A

1: Disable automatic anti-collision in NFC-A

Disables the automatic responses in passive target mode, and completely operates via

FIFO.

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4.5.10 Stream mode definition register

Address: 09h

Type: RW

Bit

Name Default scf1 scf0

Table 33. Stream mode definition register

Function

Refer to

Table 34

Comments

Sub-carrier frequency definition for

Sub-carrier and BPSK stream mode.

scp1 scp0

0 scp1

1 scp0 Number of pulses

0 1 (BPSK only)

1 2 (BPSK only)

Number of sub-carrier pulses in report period for Sub-carrier and BPSK stream mode.

8 stx2 stx1 stx0

0 Refer to

Table 35

Definition of time period for Tx modulator control (for Sub-carrier and BPSK stream mode).

Table 34. Sub-carrier frequency definition for Sub-carrier stream mode scf1 scf0 Sub-carrier mode BPSK mode

1 fc / 64 (212 kHz) fc / 32 (424 kHz) fc / 16 (848 kHz) fc / 8 (1695 kHz) fc / 16 (848 kHz)

RFU

Table 35. Definition of time period for Stream mode Tx modulator control stx2 stx1 stx0 Time period

X fc / 128 (106 kHz) fc / 64 (212 kHz) fc / 32 (424 kHz) fc / 16 (848 kHz)

RFU

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4.5.11 Auxiliary definition register

Address: 0Ah

Type: RW

Bit Name Default

Table 36. Auxiliary definition register

Function Comments

7 no_crc_rx 0

0: Receive with CRC check

1: Receive without CRC check

Valid for all protocols, for ISO14443A REQA,

WUPA and anticollision receive without CRC is done automatically

(1)

RFU nfc_id1 nfc_id0 mfaz_cl90

00: 4 bytes NFCID1

01: 7 bytes NFCID1

1x: RFU

0: 0° shifted clock for phase measurement

1: 90° shifted clock for phase measurement

Refer to Table 37

Selects NFCID1 size.

Affects also PM demodulation.

Should be set to 0 for PM demodulation.

0 dis_corr nfc_n1 nfc_n0

Selects RW receiver operation.

Value of n for direct commands NFC Initial Field

ON and NFC Response Field ON (0...3)

1. Receive without CRC is done automatically when REQA and WUPA commands are sent using, respectively, direct commands Transmit REQA and Transmit WUPA, and in case anticollision is performed setting bit antcl.

2. The value of nfc_n<1:0> must be set prior to the NFC Initial Field ON and NFC Response Field ON operations.

(2) .

Mode

ISO-A (106 to 848 kHz)

ISO-B (106 to 848 kHz)

Felica™ (212 to 424 kHz)

NFC Forum Type 1 Tag (Topaz)

Stream modes

(scf<1:0> = 01, scp<1:0> = 11)

Stream modes - Others

Table 37. RW receiver operation dis_corr = 0

Correlator reception dis_corr = 1

Pulse reception (coherent)

Pulse reception

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4.5.12 EMD suppression configuration register

Address: 05h

Type: RW

Bit

6 rx_start_emv

Name emd_emv

RFU

RFU emd_thld3 emd_thld2 emd_thld1 emd_thld0

Table 38. EMD suppression configuration register

Default Function Comments

0: Disable EMD suppression

1: Enable EMD suppression according to EMVCo

Bits no_rx_par and no_crc_rx must be set to 0, and bit nrt_emv must be set to 1 when emd_emv is enabled

0: Reception is enabled (I_rxs) only if the first 4 bits of the frame are error free

1: Reception is enabled (I_rxs) also if there is an error in the first four bits of the frame

Applies to ISO-A 106k only.

Must be set to 1 for EMVCo compliance.

If the received frame is less than emd_thld<3:0> bytes long then

EMD suppression will trigger on reception errors

Must be set to 4 for EMVCo compliance.

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Bit

7:5

4:0

Address: 06h

Type: RW

Name

RFU sst<4:0>

Default

Table 39. Subcarrier start timer register

Function

Subcarrier start time

Step: 0.25 etu

Range: 0 etu to 7.75 etu

Comments

Applies to ISO-B, 106 kb/s.

If the time from the end of the MRT timer to the detection of a subcarrier is shorter than sst<4:0>, then a soft error interrupt is generated.

If emd_emv = 1 the frame will be suppressed as

EMD and a restart interrupt will be generated.

Note that corr_s3 defines the length of subcarrier start detection and affects the correct sst<4:0> setting.

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Bit

7 lp2 lp1 lp0 z600k h200 h80 z12k

Address: 0Bh

Type: RW

Name ch_sel

Default

Table 40. Receiver configuration register 1

Function Comments

0: Enable AM channel

1: Enable PM channel

If only one Rx channel is enabled in the

Low-pass control (see Table 5 )

defines which channel is enabled.

If both channels are enabled and manual channel selection is active defines which channel is used for receive framing.

First and third stage zero setting

(see

Table 6

)

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Address: 0Ch

Type: RW

Bit

7 demod_mode

Name amd_sel sqm_dyn pulz_61 agc_en agc_m agc_alg agc6_3

Default

Table 41. Receiver configuration register 2

Function Comments

0: AM/PM demodulation

1: I/Q demodulation

0: peak detector

1: mixer

0: Squelch disabled

1: Automatic squelch activation after end of TX

Selects demodulator operation mode.

I/Q demodulation requires amd_sel = 1.

Selects AM demodulator.

Squelch is activated 18.88 µs after end of TX, and stops when the Mask receive timer reaches the sqt<7:0> setting.

0: Squelch ratio 1

1: Squelch ratio 6/3

Select squelch trigger level.

Squelch triggers on signals that are 1 or 6/3 times larger than the digitizing threshold.

– Ratio 1: recommended for ISO-A 106k correlator, ISO-A HBR/ISO-B pulse decoder,

ISO-15693, and FeliCa™

– Ratio 6/3: recommended for ISO-A HBR/ISO-B correlator

0: AGC disabled

1: AGC enabled

0: AGC operates on first eight sub-carrier pulses

1: AGC operates during complete receive period

0: Algorithm with preset is used

1: Algorithm with reset is used

0: AGC ratio 3

1: AGC ratio 6

Algorithm with preset is recommended for protocols with short SOF (like ISO14443A fc / 128).

Select AGC trigger level.

AGC triggers on signals 3 or 6 times above the minimum detectable signal level.

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Bit

Name rg1_am2 rg1_am1 rg1_am0 rg1_pm2 rg1_pm1 rg1_pm0

Address: 0Dh

Type: RW lf_en lf_op

Default

Table 42. Receiver configuration register 3

Function Comments

Gain reduction/boost in first gain stage of AM channel.

0: Full gain

1-6: Gain reduction 2.5 dB per step (15 dB total)

7: Boost + 5.5 dB

Gain reduction/boost in first gain stage of PM channel.

0: Full gain

1-6: Gain reduction 2.5 dB per step (15 dB total)

7: Boost + 5.5 dB

0: HF signal on receiver input

1: LF signal on receiver input

0: differential LF operation

1: LF input split (RFI1 to AM channel, RFI2 to PM channel)

Address: 0Eh

Type: RW

Name Default

Table 43. Receiver configuration register 4

(1)

Function Comments Bit

6 rg2_am3 rg2_am2 rg2_am1 rg2_am0

AM channel: gain reduction in second and third stage and digitizer

Only values from 0h to Ah are used:

– settings 1h to 4h reduce gain by increasing the digitizer window in 3 dB steps

– values from 5h to Ah additionally reduce the gain in second and third gain stage, always in

3 dB steps.

0 rg2_pm3 rg2_pm2 rg2_pm1 rg2_pm0

PM channel: gain reduction in second and third stage and digitizer

Only values from 0h to Ah are used:

– settings 1h to 4h reduce gain by increasing the digitizer window in 3 dB steps

– values from 5h to Ah additionally reduce the gain in second and third gain stage, always in

3 dB steps.

1. Direct command

Reset RX gain

is necessary to load the value of this register into AGC, Squelch, and RSSI block.

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ST25R3916/7 Application information

4.5.18 P2P receiver configuration register 1

Address: 0Bh

Type: RW

Bit

Name ook_fd ook_rc1 ook_rc0 ook_thd1 ook_thd0 ask_rc1 ask_rc0 ask_thd

Default

Table 44. P2P receiver configuration register 1

Function Comments

OOK fast decay

00 = 1.4 µs

01 = 1.0 µs

10 = 0.6 µs

11 = 0.2 µs

OOK RC time constant

Refer to Table 45

OOK threshold level, depends on ook_rc<1:0> configuration.

00 = 8.4 µs

01 = 6.8 µs

10 = 4.4 µs

11 = 2.4 µs

0: 97%

1: 95%

ASK RC time constant

ASK threshold level ook_thd<1:0>

Table 45. OOK threshold level settings ook_rc<1:0> = 0

55%

45%

35%

25% ook_rc<1:0> > 0

80%

75%

70%

65%

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Application information ST25R3916/7

Address: 0Ch

Type: RW

Bit Name Default

Table 46. Correlator configuration register 1

Function Comments

7 corr_s7 1 AGC = max |AM, PM| -

6 corr_s6 0

ISO-A

106k

BPSK

(1)

0: Collision detection level defined by corr_s<1:0>

1: Collision detection level equal to data slicer level

Selecting the collision detection level with corr_s<1:0> gives better detection of weak collisions. Setting the collision detection level equal to the data slicer gives better noise immunity.

0: Correlator phase correction applied during the complete reception

1: No correlator phase correction after the first data bytes

No phase correction after start recommended for ISO-B 424 kb/s and

848 kb/s operation.

0 corr_s5 corr_s4 corr_s3 corr_s2 corr_s1 corr_s0

0: V ref

-50 mV setting, first squelch step -100 mV

1: V ref

-100 mV setting,first squelch step -200 mV

0: AM and PM correlation signals digitized separately

1: AM and PM correlation signals summed before digitizing (summation mode)

Summation mode is recommended for all correlation operations

0: RX bit rate 106kb/s = 17, RX bit rates 212 to

848 kb/s = 9

1: RX bit rate 106kb/s = 33, RX bit rates 212 to

848 kb/s = 17

BPSK start length setting (delay from the start of a tags subcarrier signal to the moment when a subcarrier start is detected). Then circuit starts observing for the first phase transition (9/17/33 ±

2 pilot pulses). At this moment the sst<4:0> check for TR0 is done.

ISO-A

106k

0: Normal data slicer

1: Fast data slicer

BPSK

(

0: Normal reference time constant

1: Long reference time constant

(1.5x normal)

ISO-A

106k

Collision level setting MSB

BPSK

(

Subcarrier end detection level

0: 100%

1: 66%

ISO-A

106k

BPSK

(

Collision level setting LSB

0: Subcarrier end detector disabled

1: Subcarrier end detector enabled

1. BPSK options apply to ISO-A HBR and ISO-B (all bit rates).

Collision detection level, compared to data detection level:

– 00: 16%

– 01: 28%

– 10: 41%

– 11: 53%

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ST25R3916/7 Application information

Address: 0Dh

Type: RW

Table 47. Correlator configuration register 2

Function Comments Bit Name Default

RFU

1 corr_s9

0 corr_s8

0: Sleep mode disable set by timer

1: Sleep mode disable only on rx_on = 1

Correlator sleep mode option.

Sleep start: 18 µs no output pulse.

Stop with timer:

– takes 18 µs (ISO-A/B, F424)

– takes 42 µs (stream 15693, F212)

0: All other standards

1: 424 kHz subcarrier stream mode

Must be set to 1 for 424 kHz subcarrier stream mode.

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Application information ST25R3916/7

Bit

Name mrt7 mrt6 mrt5 mrt4 mrt3 mrt2 mrt1 mrt0

Address: 0Fh

Type: RW

Default

Table 48. Mask receive timer register

Function mrt_step = 0:

Step: 64 / fc (4.72 μ s)

Range: 256 / fc (~18.88 μ s) to

16320 / fc (~1.2 ms) mrt_step = 1:

Step: 512 / fc (37.78 μ s)

Range: 2048 / fc (151 μ s) to

130560 / fc (9.62 ms)

Comments

Set time after end of TX during which the receiver output is ignored (masked).

The minimum mask receive time of 18.88 μ s covers the transients in receiver after end of transmission.

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DS12484 Rev 4

ST25R3916/7 Application information

Bit

4.5.22 No-response timer register 1

Address: 10h

Type: RW

Name Default nrt15 nrt14 nrt13 nrt12 nrt11 nrt10 nrt9 nrt8

Table 49. No-response timer register 1

Function

No-response timer definition

MSB bits nrt_step = 0:

Step: 64 / fc (4.72 μ s),

Range: 309 ms nrt_step = 1:

Step: 4096 / fc (302 µs)

Range: 19.8 s.

Comments

Defines timeout after end of Tx. If this timeout expires without detecting a response a

No-response interrupt is sent.

In NFC mode the No-response timer is started only when external field is detected. In the

NFCIP-1 active communication mode the

No-response timer is automatically started when the transmitter is turned off after the message has been sent.

All 0: No-response timer is not started.

No-response timer is reset and restarted with

Start No-response timer direct command.

Bit

4.5.23 No-response timer register 2

Address: 11h

Type: RW

Name Default nrt7 nrt6 nrt5 nrt4 nrt3 nrt2 nrt1 nrt0

Table 50. No-response timer register 2

Function

No-response timer definition

LSB bits

Comments

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Bit

4.5.24 Timer and EMV control register

Address: 12h

Type: RW

Name Default gptc2 gptc1 gptc0

RFU

0 mrt_step nrt_nfc nrt_emv nrt_step

Table 51. Timer and EMV control register

Function

General purpose timer trigger source.

Refer to

Table 52

Comments

0: 64 / fc

1: 512 / fc

0: NRT starts at end of TX (own field off)

1: NRT starts at peer field-on event

1: No-response timer EMV mode

0: 64 / fc

1: 4096 / fc

No-response timer start condition in AP2P initiator and target mode.

Mask receive timer step size

No-response timer step size.

gptc2 gptc1 gptc0

Table 52. Trigger sources

Trigger source

X The timer starts always with direct command Start General purpose timer.

0 No additional trigger source.

1 Additionally starts at End of RX (after EOF).

0 Additionally starts at Start of RX.

Additionally starts at End of TX.

In AP2P modes the timer is used to switch the field off.

In AP2P modes enables NRT start according to nrt_nfc description.

RFU

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Bit

5 gpt15 gpt14 gpt13 gpt12 gpt11 gpt10 gpt9 gpt8

Address: 13h

Type: RW

Name Default

Table 53. General purpose timer register 1

Function Comments

General purpose timeout definition MSB bits

Defined in steps of 8 / fc (590 ns)

Range from 590 ns to 38,7 ms

Bit

0 gpt7 gpt6 gpt5 gpt4 gpt3 gpt2 gpt1 gpt0

Address: 14h

Type: RW

Table 54. General purpose timer register 2

Name Default Function Comments

General purpose timeout definition LSB bits

Defined in steps of 8 / fc (590 ns)

Range from 590 ns to 38,7 ms

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Application information ST25R3916/7

Bit

4.5.27 PPON2 field waiting register

Name ppt7 ppt6 ppt5 ppt4 ppt3 ppt2 ppt1 ppt0

Address: 15h

Type: RW

Default

Table 55. PP

ON2

field waiting register

Function

ON2

timer

Step: 64 / fc (4.72 µs)

Range: 1.204 ms

Comments

Maximum time the system waits for the peer device field on in AP2P mode.

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ST25R3916/7 Application information

Bit

Name sqt7 sqt6 sqt5 sqt4 sqt3 sqt2 sqt1 sqt0

Address: 0Fh

Type: RW

Default

Table 56. Squelch timer register

Function Comments

Squelch Timer

Step, Range: same as

Mask receive timer register , including

mrt_step selection

Squelch is enabled ~20 μ s after the end of reader data transmission

– sqt<7:0> > 5:

Squelch stops after the time defined by sqt<7:0>. Gain reduction due to squelch is locked and used as a starting point for AGC.

– Sqt<7:0> ≤ 5 or sqt<7:0> ≥ mrt<7:0>:

Squelch is enabled until the MRT expires.

4.5.29 NFC field on guard timer register

Bit

Address: 15h

Type: RW

Table 57. NFC field on guard timer register

Name Default Function Comments nfc_gt7 nfc_gt6 nfc_gt5 nfc_gt4 nfc_gt3 nfc_gt2 nfc_gt1 nfc_gt0

NFC field on guard timer

Step: 2048 / fc (151 μ s)

Range: 38.66 ms

Used by NFC field on commands.

The value nfc_gt<7:0> is added to the initial

75 μ s in T

IRFG

and T

ARFG

Set to 33 for T

IRFG

(75 μ s + 4.984 ms= 5.06 ms)

Set to 0 for T

ARFG

(75 μ s + 0 ms = 75 μ s)

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Application information

4.5.30 Mask main interrupt register

Bit

Name

M_osc

M_wl

M_rxs

M_rxe

M_txe

M_col

M_rx_rest

RFU

Address: 16h

Type: RW

Default

Table 58. Mask main interrupt register

Function

1: Mask IRQ when oscillator frequency is stable

1: Mask IRQ due to FIFO water level

1: Mask IRQ due to start of receive

1: Mask IRQ due to end of receive

1: Mask IRQ due to end of transmission

1: Mask IRQ due to bit collision

1: Mask IRQ due to automatic reception restart

Not used

ST25R3916/7

Comments

Bit

Address: 17h

Type: RW

Table 59. Mask timer and NFC interrupt register

Name Default Function

M_dct

M_nre

M_gpe

M_eon

M_eof

M_cac

M_cat

M_nfct

1: Mask IRQ due to termination of direct command

1: Mask IRQ due to No-response timer expire

1: Mask IRQ due to general purpose timer expire

1: Mask IRQ due to detection of external field higher than Target activation level

1: Mask IRQ due to detection of external field drop below Target activation level

1: Mask IRQ due to detection of collision during RF

Collision Avoidance

1: Mask IRQ after minimum guard time expire

1: Mask IRQ when in target mode the initiator bit rate has been recognized

Comments

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Bit

4.5.32 Mask error and wake-up interrupt register

Address: 18h

Type: RW

Name

Table 60. Mask error and wake-up interrupt register

Default Function

M_crc

M_par

M_err2

M_err1

M_wt

M_wam

M_wph

M_wcap

1: Mask IRQ due to CRC error

1: Mask IRQ due to parity error

1: Mask IRQ due to soft framing error

1: Mask IRQ due to hard framing error

1: Mask IRQ due to wake-up timer interrupt

1: Mask Wake-up IRQ due to amplitude measurement

1: Mask Wake-up IRQ due to phase measurement.

1: Mask Wake-up IRQ due to capacitance measurement

Application information

Comments

4.5.33 Mask passive target interrupt register

Bit

Address: 19h

Type: RW

Table 61. Mask passive target interrupt register

Name Default Function

M_ppon2

M_sl_wl

M_apon

M_rxe_pta

M_wu_f

RFU

M_wu_a*

M_wu_a

1: Mask IRQ from PPON2 field on waiting timer

1: Mask IRQ for Passive target slot number water level

1: Mask IRQ due to Active PP Field on event

1: Mask IRQ due to end of receive when the device is handling the response

1: Mask IRQ NFC 212/424 kb/s passive target active

1: Mask IRQ NFC 106 kb/s passive target Active*

1: Mask IRQ NFC 106 kb/s passive target Active

Comments

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4.5.34 Main interrupt register

Bit

Name Default

I_osc

I_wl

I_rxs

I_rxe

I_txe

2 I_col

1 I_rx_rest

0 RFU

Address: 1Ah

Type: R

Table 62. Main interrupt register

Function

IRQ when oscillator frequency is stable

IRQ due to FIFO water level

IRQ due to start of receive

IRQ due to end of receive

IRQ due to end of transmission

IRQ due to bit collision

IRQ due to automatic reception restart

Comments

Set after oscillator is started by setting

Operation control register bit en.

Set during receive, if more than 300 bytes are in the FIFO.

Set during transmit, if less than 200 bytes are in the FIFO.

Set when a frame is suppressed as EMD

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4.5.35 Timer and NFC interrupt register

Address: 1Bh

Type: R

Bit Name Default

Table 63. Timer and NFC interrupt register

(1)

Function Comments

I_dct

I_nre

I_gpe

I_eon

I_eof

I_cac

IRQ due to termination of direct command

IRQ due to No-response timer expire

IRQ due to general purpose timer expire

IRQ due to detection of external field higher than Target activation level

IRQ due to detection of external field drop below Target activation level

IRQ due to detection of collision during

RF Collision Avoidance

1 I_cat IRQ after minimum guard time expire

An external field was not detected during RF collision avoidance, field was switched on, IRQ sent after minimum guard time according to

NFCIP-1.

0 I_nfct -

IRQ when in target mode the initiator bit rate was recognized

1. After register has been read, its content is set to 0.

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4.5.36 Error and wake-up interrupt register

Address: 1Ch

Type: R

Name Default

Table 64. Error and wake-up interrupt register

(1)

Function Comments Bit

I_crc

I_par

I_err2

I_err1

I_wt

CRC error

Parity error

Soft framing error

Hard framing error

Wake-up timer interrupt

I_wam

I_wph

I_wcap -

Wake-up interrupt due to amplitude measurement

Wake-up interrupt due to phase measurement.

Wake-up interrupt due to capacitance measurement

1. After Main interrupt register has been read, its content is set to 0.

Framing error that does not result in corrupted

Rx data.

Framing error that results in corrupted Rx data.

Timeout after execution of Start Wake-Up Timer command in case option with IRQ at every timeout is selected.

Result of amplitude measurement ∆ am larger than reference.

Result of phase measurement ∆ pm larger than reference.

Result of capacitance measurement ∆ cm larger than reference.

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Address: 1Dh

Type: R

Name Default

Table 65. Passive target interrupt register

(1)

Function Comments Bit

I_ppon2

I_sl_wl

I_apon

I_rxe_pta

I_wu_f -

PPON2 field on waiting timer interrupt

IRQ for passive target slot number water level

IRQ due to active P2P field on event

IRQ due to end of receive, the device is handling the response

RFU

I_wu_a*

I_wu_a

1. After register has been read, its content is set to 0.

Sent if four unused slot numbers (TSN) remain in

PT_memory.

Sent after RF collision avoidance, if there was no collision and field was turned on.

Sent in passive target mode when NFC-A anti-collision or NFC-F SENSF_RES is automatically sent (MCU action required).

NFC 212/424kb/s passive target

‘Active’ interrupt

Sent after NFC 212/424 kb/s automatic response to SENSF_REQ was sent.

RFU -

Passive target Active* interrupt Sent when Active* state is reached.

Passive target Active interrupt Sent when Active state is reached.

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Application information

Bit

4.5.38 FIFO status register 1

Address: 1Eh

Type: R

Name fifo_b7 fifo_b6 fifo_b5 fifo_b4 fifo_b3 fifo_b2 fifo_b1 fifo_b0

Default

Table 66. FIFO status register 1

Function

Number of bytes in the FIFO

(LSB)

Comments

Valid range is from 0 to 512.

ST25R3916/7

Bit

4.5.39 FIFO status register 2

Address: 1Fh

Type: R

Name fifo_b9 fifo_b8 fifo_unf fifo_ovr fifo_lb2 fifo_lb1 fifo_lb0 np_lb

Default

Table 67. FIFO status register 2

Function Comments

Number of bytes in the FIFO

(MSB)

1: FIFO underflow

1: FIFO overflow

Number of bits in the last FIFO byte if it was not complete

The received bits are stored in the LSB part of the last byte in the FIFO.

If I_err1 is set then fifo_lb<2:0> dos not contain valid data.

1: Parity bit is missing in the last byte

The bit is set if the last received byte is complete with 8 data bits but he parity bit is missing.

If I_err1 is set then np_lb does not contain valid data.

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Bit

4.5.40 Collision display register

Address: 20h

Type: R

Name c_byte3 c_byte2 c_byte1 c_byte0 c_bit2 c_bit1 c_bit0 c_pb

Default

Table 68. Collision display register

Function

Number of full bytes before the bit collision happened.

Number of bits before the collision in the byte where the collision happened

Comments

The Collision display register range covers

ISO14443A anticollision command. If collision (or framing error interpreted as collision) happens in

a longer message, the Collision display register

is not set.

If I_err1 is set then c_byte<3:0> and c_bit<2:0> do not contain valid data.

1: Collision in parity bit

0: no collision

This error is reported if the first detected collision is in a parity bit.

If I_err1 is set then c_pb dos not contain valid data.

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Application information ST25R3916/7

Bit

Address: 21h

Type: R

Name Default

Table 69. Passive target display register

Function

RFU

RFU pta_state3 pta_state2 pta_state1 pta_state0 -

0000: POWER OFF

0001: IDLE

0010: READY_L1

0011: READY_L2

0100: RFU

0101:ACTIVE

0110: RFU

1001: HALT

1010: READY_L1*

1011: READY_L2*

1100: RFU

1101: ACTIVE*

Comments

ISO-A passive target states.

In ACTIVE or ACTIVE* state, the MCU must handle all commands, including SENSE/IDLE and SLEEP/HALT.

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Bit

4.5.42 Number of transmitted bytes register 1

Address: 22h

Type: RW

Name ntx12 ntx11 ntx10 ntx9 ntx8 ntx7 ntx6 ntx5

Default

Table 70. Number of transmitted bytes register 1

Function Comments

Number of full bytes to be transmitted, MSB bits

Maximum supported number of bytes is 8191.

4.5.43 Number of transmitted bytes register 2

Address: 23h

Type: RW

Bit Name

Table 71. Number of transmitted bytes register 2 (1) (2)

Default Function Comments

3 ntx4 ntx3 ntx2 ntx1 ntx0

Number of full bytes to be transmitted, MSB bits

Maximum supported number of bytes is 8191.

0 nbtx2 nbtx1 nbtx0

Number of bits to transmit after the last full byte.

Set to 000 to transmit only full bytes.

Bit transmission starts from LSB. Applicable for

ISO14443A:

– bit oriented anticollision frame in case last byte is a split byte

– Tx is done without parity bit generation

– passive target: 4-bit ACK, NACK

1. If anctl bit is set while card is in idle state and nbtx is not 000, then i_par will be triggered during REQA and WUPA direct command is issued.

2. Transmission of short or incomplete messages only works for ISO-A/B using the command Transmit without CRC.

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Application information ST25R3916/7

Bit

4.5.44 Bit rate detection display register

RFU

RFU nfc_rate1 nfc_rate0 ppt2_on gpt_on nrt_on mrt_on

Address: 24h

Type: R

Name Default

Table 72. Bit rate detection display register

Function

Comments

Refer to

Table 26

Result of automatic bit rate detection in the bit rate detection target mode.

1: PP

ON2

timer is running

1: General purpose timer is running

1: No-response timer is running

1: Mask receive timer is running

State of internal timers.

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Bit

Name ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0

Address: 25h

Type: R

Default

Table 73. A/D converter output register

Function

Displays the result of the last

A/D conversion.

Comments

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Application information ST25R3916/7

Bit

4.5.46 Antenna tuning control register 1

Address: 26h

Type: RW

Name aat_A_7 aat_A_6 aat_A_5 aat_A_4 aat_A_3 aat_A_2 aat_A_1 aat_A_0

Default

Table 74. Antenna tuning control register 1

Function

AAT-A D/A converter input.

Comments

AAT-A voltage (in V) =

(0.044 + 0.868 * aat_A<7:0> / 255) * V

DD_A

Bit

4.5.47 Antenna tuning control register 2

Address: 27h

Type: RW

Name aat_B_7 aat_B_6 aat_B_5 aat_B_4 aat_B_3 aat_B_2 aat_B_1 aat_B_0

Default

Table 75. Antenna tuning control register 2

Function

AAT-B D/A converter input.

Comments

AAT-B voltage (in V) =

(0.044 + 0.868 * aat_B<7:0> / 255) * V

DD_A

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Bit

4.5.48 TX driver register

Address: 28h

Type: RW

Name am_mod3 am_mod2 am_mod1 am_mod0 d_res3 d_res2 d_res1 d_res0

Default

Table 76. TX driver register

Function

AM modulation index

(see

Table 77 )

RFO driver resistance

(see

Table 78 )

Application information

Comments

am_mod<3:0>

Table 77. AM modulation index

Modulation (%)

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Application information ST25R3916/7 d_res<3:0>

Table 78. RFO driver resistance

Driver output resistance (normalized)

(1)

3-4

5-14

1.0

2.0

4.1

8.3

17.1

High Z

1. The value has to be multiplied by the RFO resistance from

Section 5.4: Electrical characteristics

to obtain the driver output resistance for the corresponding d_res setting.

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Bit

Address: 28h

Type: RW

Name Default

Table 79. Auxiliary modulation setting register

Function Comments

7 dis_reg_am

6 lm_ext_pol

0 lm_ext lm_dri res_am

RFU

0: Regulator AM enabled

1: Regulator AM disabled

0: Normal polarity

1: Inverse polarity

Uses am_mod<3:0> to set the modulation index for regulator based AM modulation.

Logic of this bit is inverted. Set to 0 to enable regulator AM.

Normal polarity: LM_EXT pin load modulation signal is active high.

Inverse polarity: LM_EXT pin load modulation signal is active low.

0: External load modulation disabled

1: External load modulation enabled

Enables output of load modulation signal on

LM_EXT pin.

0: Driver load modulation disabled

1: Driver load modulation enabled

0: Resistive AM modulation disabled

1: Resistive AM modulation enabled

Uses Passive target modulation register to set

driver load modulation resistance.

Uses md_res<6:0> to configure resistive AM modulated driver resistance.

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Application information ST25R3916/7

Bit

Address: 29h

Type: RW

Name Default

Table 80. Passive target modulation register

Function Comments ptm_res3 ptm_res2 ptm_res1 ptm_res0 pt_res3 pt_res2 pt_res1 pt_res0

Refer to Table 81

RFO resistance during passive load modulation, modulated state.

ptm_res<3:0> must be set before the Mode definition register is set to passive target mode.

RFO resistance during passive load modulation, unmodulated state.

pt_res<3:0> must be set before the

Mode definition register is set to passive target mode.

Table 81. Passive target modulated and unmodulated state driver output resistance ptm_res<3:0> pt_res<3:0>

Driver output resistance R

RFO

(normalized)

(1)

1.0

2.0

4.1

8.3

12.2

17.1

25.6

32.0

36.6

42.7

51.2

64.0

85.3

128.0

256.0

High Z

1. The value has to be multiplied by the RFO resistance from

Section 5.4: Electrical characteristics

to obtain the driver output resistance for the corresponding ptm/pt_res setting.

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Bit

Name d_rat_t3 d_rat_t2 d_rat_t1

Address: 29h

Type: RW d_rat_t0

3 d_tim_man

2 d_tim_m2

1 d_tim_m1

0 d_tim_m0

Default

Table 82. TX driver timing register

Function Comments

Driver transient ratio target

(in number of non-overlap times in one RF period)

The value presents the target ratio between one RF period and whole non-overlap time (both sides L to

H and H to L).

The system starts with the slowest available transient and measures the ratio. If this is lower than targeted the system switches to faster transient. The procedure is repeated until the target ratio is reached (or exceeded for the first time).

There are five steps available, procedure can take up to ten RF periods.

0: Use automatically acquired timing setting

1: Use manual timing setting

000: Slow

001: Medium slow

010: Nominal

011: Medium fast

1xx: Fast

Manual driver timing, used if d_tim_man is set to 1.

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Application information

Bit

RFU trg_l2 trg_l1 trg_l0 rfe_t3 rfe_t2 rfe_t1 rfe_t0

Address: 2Ah

Type: RW

Table 83. External field detector activation threshold register

Name Default Function Comments

Not used -

Peer detection threshold.

Refer to Table 87 .

Collision avoidance threshold.

Refer to Table 88 .

ST25R3916/7

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Bit

6 md_res6

5 md_res5

4 md_res4

3 md_res3

2 md_res2

1 md_res1

0 md_res0

Address: 2Ah

Type: RW

Name Default

Table 84. Resistive AM modulation register

Function Comments fa3_f 0

0: Use normal non-overlap

1: Use minimum non-overlap

Refer to Table 85

Resistive AM modulated state driver output resistance.

md_res<6:0>

Table 85. Resistive AM modulated state driver output resistance

Driver output resistance R

RFO

(normalized)

(1) md_res<6:0>

Driver output resistance R

RFO

(normalized)

(1)

1.169

1.191

1.213

1.237

1.261

1.286

1.313

1.340

1.004

1.020

1.036

1.053

1.071

1.089

1.108

1.128

1.148

4.741

4.830

4.923

5.020

5.120

5.224

5.333

5.447

4.063

4.129

4.197

4.267

4.339

4.414

4.491

4.571

4.655

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156

Application information ST25R3916/7

Table 85. Resistive AM modulated state driver output resistance (continued) md_res<6:0>

Driver output resistance R

RFO

(normalized)

(1) md_res<6:0>

Driver output resistance R

RFO

(normalized)

(1)

2.485

2.535

2.586

2.639

2.695

2.753

2.151

2.226

2.306

2.349

2.393

2.438

2.813

2.876

2.943

3.012

3.084

1.610

1.652

1.695

1.741

1.790

1.842

1.896

1.954

2.016

2.081

1.369

1.399

1.430

1.463

1.497

1.533

1.571

104

105

106

107

108

109

100

101

102

103

110

111

112

113

114

11.13

11.64

12.19

12.80

13.47

14.22

8.828

9.143

9.481

9.846

10.24

10.67

15.06

16.00

17.07

18.29

19.69

6.564

6.737

6.919

7.111

7.314

7.529

7.758

8.000

8.258

8.533

5.565

5.689

5.818

5.953

6.095

6.244

6.400

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DS12484 Rev 4

ST25R3916/7 Application information

Table 85. Resistive AM modulated state driver output resistance (continued) md_res<6:0>

Driver output resistance R

RFO

(normalized)

(1) md_res<6:0>

Driver output resistance R

RFO

(normalized)

(1)

3.160

3.241

3.325

3.413

3.507

3.606

3.657

3.710

3.765

3.821

3.879

3.938

4.000

115

116

117

118

119

120

121

122

123

124

125

126

127

21.3

23.3

25.6

28.4

32.0

36.6

42.7

51.2

64.0

85.3

128

256

High Z

1. The value has to be multiplied by the RFO resistance from

Section 5.4: Electrical characteristics to obtain the driver output

resistance for the corresponding md_res setting.

Bit

Address: 2Bh

Type: RW

Name

Table 86. External field detector deactivation threshold register

Default Function Comments

RFU trg_ld2 trg_ld1 trg_ld0 rfe_td3 rfe_td2 rfe_td1 rfe_td0

Not used

Deactivation peer detection threshold (see

Table 87

Deactivation collision avoidance threshold (see

Table 88

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156

Application information trg_I2

ST25R3916/7

Table 87. Peer detection threshold as seen on RFI1 input trg_I1 trg_I0 Peer detection threshold voltage (mV pp

) on RFI1

290

400

560

800

105

150

205 rfe_3

Table 88. Collision avoidance threshold as seen on RFI1 input rfe_2

0 rfe_1

0 rfe_0 Collision avoidance threshold voltage (mV pp

) on RFI1

0 75

800

105

150

205

290

400

560

125

175

250

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DS12484 Rev 4

ST25R3916/7 Application information

4.5.55 TX driver timing display register

Address: 2Bh

Type: R

Name Default

Table 89. TX driver timing display register

Function Comments Bit

5 d_rat_r3 d_rat_r2 d_rat_r1

3 d_rat_r0

RFU

2 d_tim_r2

1 d_tim_1 d_tim_0

Driver Transient ratio readout

(in number of non-overlap times in one RF period)

Driver transient ratio readout

000: Slow

001: Medium slow

010: Nominal

011: Medium fast

1xx: Fast

Driver timing readout

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156

Application information ST25R3916/7

Bit

Address: 2Ch

Type: RW

Name Default

Table 90. Regulator voltage control register

Function reg_s 0

0: Regulated voltages are defined by result of Adjust Regulators command

1: Regulated voltages are defined by rege_x bits written in this register

Comments

Defines mode of regulator voltage setting.

rege_3 rege_2 rege_1 rege_0

External definition of regulated voltage

(see Table 92

In 5 V mode V

DD_D

and V regulators are set to 3.4 V

DD_A

In 5 V mode V

DD_D are set to 3.4 V.

and V

DD_A

regulators

In 3.3 V mode V

DD_D

and V

DD_A

regulators are set to the same value as V

DD_RF

mpsv2 mpsv1 mpsv0

000: V

001: V

DD_A

010: V

DD_D

011: V

DD_RF

100: V

DD_AM

101: RFU

110: RFU

111: RFU

Defines source of direct command Measure power supply .

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DS12484 Rev 4

ST25R3916/7 Application information reg_3 rege_3

Bit

Name reg_3 reg_2 reg_1 reg_0

RFU

Address: 2Ch

Type: R i_lim

Default

Table 91. Regulator display register

Function

Voltage regulator setting after

Adjust regulators command.

Refer to Table 92 for definition.

1: V

DD_RF limit mode

regulator in current

Comments

reg_2 rege_2

Table 92. Regulated voltages reg_1 reg_0 rege_1

0 rege_0

Typical regulated voltage (V)

5 V mode

4.0

3.9

3.8

3.7

3.6

4.3

4.2

4.1

5.1

5.0

4.9

4.8

4.7

4.6

4.5

4.4

3.3 V mode

2.6

2.5

2.4

3.4

3.3

3.2

3.1

3.0

2.9

2.8

2.7

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156

Application information ST25R3916/7

Bit

Name rssi_am_3 rssi_am_2 rssi_am_1 rssi_am_0 rssi_pm_3 rssi_pm_2 rssi_pm_1 rssi_pm_0

Address: 2Dh

Type: R

Default

Table 93. RSSI display register

Function

AM channel RSSI peak value.

Refer to Table 94 for definition.

PM channel RSSI peak value.

Refer to Table 94 for definition.

Comments

Stores the AM channel RSSI peak value until the

start of the next reception, or until the Clear RSSI

command is sent.

Stores the PM channel RSSI peak value until the

start of the next reception, or until the Clear RSSI

command is sent.

rssi_2

1 rssi_3

1 rssi_1

Table 94. RSSI rssi_0

Typical signal on RFI1 (mV rms

)

≤ 20

>72

>99

>136

>190

>262

>357

>20

>27

>37

>52

>500

>686

>950

>1150

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DS12484 Rev 4

ST25R3916/7 Application information

Bit

4.5.59 Gain reduction state register

Name gs_am_3 gs_am_2 gs_am_1 gs_am_0 gs_pm_3 gs_pm_2 gs_pm_1 gs_pm_0

Address: 2Eh

Type: R

Default

Table 95. Gain reduction state register

Function Comments

Refer to rg2_am<3:0> for value explanation.

Overall AM channel second and third stage gain reduction (includes register gain reduction, squelch and AGC).

Refer to rg2_pm<3:0> for value explanation.

Overall PM channel second and third stage gain reduction (includes register gain reduction, squelch and AGC).

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156

Application information ST25R3916/7

Bit

Address: 2Fh

Type: RW

Name Default

Table 96. Capacitive sensor control register

Function Comments cs_mcal4 cs_mcal3 cs_mcal2 cs_mcal1 cs_mcal0 cs_g2 cs_g1 cs_g0

1.6 pF

0.8 pF

0.4 pF

0.2 pF

0.1 pF

000: 2.8 V / pF

001: 6.5 V / pF

010: 1.1 V / pF

100: 0.5 V / pF

110: 0.35 V / pF

Others: Not used

Manual capacitive sensor calibration value

(binary weighted).

Sets cs_mcal<4:0> to 0 to enable automatic calibration mode.

Capacitor sensor gain.

Bit

Address: 30h

Type: R

Name Default

Table 97. Capacitive sensor display register

Function cs_cal4 cs_cal3 cs_cal2 cs_cal1 cs_cal0 cs_cal_end cs_cal_err

RFU -

1.6 pF

0.8 pF

0.4 pF

0.2 pF

0.1 pF

1: Calibration ended

1: Calibration error

Comments

Capacitive sensor calibration value (binary weighted).

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DS12484 Rev 4

ST25R3916/7 Application information

Bit

Address: 31h

Type: R

Name a_cha efd_o tx_on osc_ok rx_on rx_act en_peer en_ac

Default

Table 98. Auxiliary display register

Function Comments

0: AM

1: PM

1: External field detected

1: Transmission is active

1: Xtal oscillation is stable

1: Receive decoder is enabled

1: Receive decoder is receiving a message

1: External field detector is active in

Peer detection mode

1: External field detector is active in RF collision avoidance mode

Receiver channel used in ongoing/last reception.

External field detector output.

Data transmission due to automatic handling of CE mode collision avoidance are not indicated.

Indication that Xtal oscillator is active and its output is stable.

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156

Application information ST25R3916/7

Bit

Address: 30h

Type: RW

Table 99. Overshoot protection configuration register 1

Name Default Function Comments ov_tx_mode1 ov_tx_mode0 ov_pattern13 ov_pattern12 ov_pattern11 ov_pattern10 ov_pattern9 ov_pattern8

00: Drive with V

DD_DR

01: Drive with V

DD_AM

10: Driver stop (at GND / V

DD_DR

)

11: RFU

Selects RF drive level to apply when ov_patternX is set to 1.

Bit

Address: 31h

Type: RW

Table 100. Overshoot protection configuration register 2

Name Default Function Comments ov_pattern7 ov_pattern6 ov_pattern5 ov_pattern4 ov_pattern3 ov_pattern2 ov_pattern1 ov_pattern0

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DS12484 Rev 4

ST25R3916/7 Application information

Bit

Address: 32h

Type: RW

Table 101. Undershoot protection configuration register 1

Name Default Function Comments un_tx_mode1 un_tx_mode0 un_pattern13 un_pattern12 un_pattern11 un_pattern10 un_pattern9 un_pattern8

00: Drive with V

DD_DR

01: Drive with V

DD_AM

10: Driver stop (at GND / V

DD_DR

)

11: RFU

Selects RF drive level to apply when un_patternX is set to 1.

Bit

Address: 33h

Type: RW

Table 102. Undershoot protection configuration register 2

Name Default Function Comments un_pattern7 un_pattern6 un_pattern5 un_pattern4 un_pattern3 un_pattern2 un_pattern1 un_pattern0

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156

Application information ST25R3916/7

Bit

Address: 32h

Type: RW

Name Default

Table 103. Wake-up timer control register

Function wur 0

0: 100 ms

1: 10 ms

Comments

Wake-up timer range wut2 wut1 wut0 wto

Refer to Table 104

Wake-up timer timeout value wam wph wcap

1: IRQ at every timeout

1: At timeout perform amplitude measurement

1: At timeout perform phase measurement

1: At timeout perform capacitance measurement

Generates I_wam interrupt if amplitude difference is larger than ∆ am.

Generates I_wph interrupt if phase difference islarger than ∆ pm.

Generates I_wcap interrupt if capacitance difference is larger than ∆ cm.

wut2

0 wut1

Table 104. Typical wake-up time wut0 100 ms range (wur = 0)

100 ms

200 ms

300 ms

400 ms

500 ms

600 ms

700 ms

800 ms

10 ms range (wur = 1)

10 ms

20 ms

30 ms

40 ms

50 ms

60 ms

70 ms

80 ms

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DS12484 Rev 4

ST25R3916/7 Application information

Bit

Address: 33h

Type: RW

Table 105. Amplitude measurement configuration register

Name Default Function Comments am_d3 am_d2 am_d1 am_d0

Definition of ∆ am (difference vs. reference that triggers interrupt)

am_aam am_aew1 am_aew2 am_ae

0: Exclude the IRQ measurement

1: Include the IRQ measurement

Includes/excludes the measurement that causes IRQ (having difference > ∆ am to reference) in auto-averaging.

00: 4

01: 8

10: 16

11: 32

0: Use Amplitude measurement reference register

Weight of last measurement result for auto-averaging.

Selects reference value for amplitude measurement Wake-up mode.

Bit

Address: 34h

Type: RW

Name

Table 106. Amplitude measurement reference register

Default Function Comments am_ref7 am_ref6 am_ref5 am_ref4 am_ref3 am_ref2 am_ref1 am_ref0

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156

Application information

Bit

Address: 35h

Type: R

Table 107. Amplitude measurement auto-averaging display register

Name Default Function Comments amd_aad7 amd_aad6 amd_aad5 amd_aad4 amd_aad3 amd_aad2 amd_aad1 amd_aad0

ST25R3916/7

Bit

Address: 36h

Type: R

Table 108. Amplitude measurement display register

Name Default Function Comments am_amd7 am_amd6 am_amd5 am_amd4 am_amd3 am_amd2 am_amd1 am_amd0

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DS12484 Rev 4

ST25R3916/7 Application information

Bit

Address: 37h

Type: RW

Name

Table 109. Phase measurement configuration register

Default Function Comments pm_d3 pm_d2 pm_d1 pm_d0

Definition of ∆ pm (difference to reference that triggers interrupt)

pm_aam 0

0: Exclude the IRQ measurement

1: Include the IRQ measurement

Includes/excludes the measurement value that triggered the I_wph interrupt in the auto-averaging.

pm_aew1 pm_aew0 pm_ae

00: 4

01: 8

10: 16

11: 32

0: Use Phase measurement reference register

1: Use phase measurement auto-averaging as reference

Weight of last measurement result for auto-averaging.

Selects reference value for phase measurement Wake-up mode.

Bit

4.5.73 Phase measurement reference register

Address: 38h

Type: RW

Name

Table 110. Phase measurement reference register

Default Function Comments pm_ref7 pm_ref6 pm_ref5 pm_ref4 pm_ref3 pm_ref2 pm_ref1 pm_ref0

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156

Application information

Bit

Address: 39h

Type: R

Table 111. Phase measurement auto-averaging display register

Name Default Function Comments pm_aad7 pm_aad6 pm_aad5 pm_aad4 pm_aad3 pm_aad2 pm_aad1 pm_aad0

ST25R3916/7

Bit

Address: 3Ah

Type: R

Table 112. Phase measurement display register

Name Default Function Comments pm_amd7 pm_amd6 pm_amd5 pm_amd4 pm_amd3 pm_amd2 pm_amd1 pm_amd0

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DS12484 Rev 4

ST25R3916/7 Application information

Bit

Address: 3Bh

Type: RW

Table 113. Capacitance measurement configuration register

Name Default Function Comments cm_d3 cm_d2 cm_d1 cm_d0

Definition of ∆ cm (difference to reference that triggers interrupt)

cm_aam cm_aew1 cm_aew0 cm_ae

0: Exclude the IRQ measurement

1: Include the IRQ measurement

Includes/excludes the measurement that causes IRQ (having difference > ∆ cm to reference) in auto-averaging.

00: 4

01: 8

10: 16

11: 32

Weight of last measurement result for auto-averaging.

0: Use

Capacitance measurement reference register

1: Use capacitance measurement auto-averaging as reference

Selects reference value for capacitance measurement Wake-up mode.

4.5.77 Capacitance measurement reference register

Bit

Address: 3Ch

Type: RW

Table 114. Capacitance measurement reference register

Name Default Function Comments cm_ref7 cm_ref6 cm_ref5 cm_ref4 cm_ref3 cm_ref2 cm_ref1 cm_ref0

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156

Application information

Bit

Address: 3Dh

Type: R

Table 115. Capacitance measurement auto-averaging display register

Name Default Function Comments cm_aad7 cm_aad6 cm_aad5 cm_aad4 cm_aad3 cm_aad2 cm_aad1 cm_aad0

ST25R3916/7

Bit

Address: 3Eh

Type: R

Table 116. Capacitance measurement display register

Name Default Function Comments cm_amd7 cm_amd6 cm_amd_ cm_amd_ cm_amd3 cm_amd2 cm_amd1 cm_amd0

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DS12484 Rev 4

ST25R3916/7 Application information

Bit

Name ic_type4 ic_type3 ic_type2 ic_type1 ic_type0 ic_rev2 ic_rev1 ic_rev0

Address: 3Fh

Type: R

Default

Table 117. IC identity register

Function

IC type code

00101: ST25R3916/7

IC revision code

010: rev 3.1

5-bit IC type code

Comments

3-bit IC revision code

DS12484 Rev 4

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Electrical characteristics ST25R3916/7

5.1

136/157

Absolute maximum ratings

Any stress beyond the limits listed in

Table 118 may cause permanent damage to the

device. These are stress ratings only.

Functional operation of the device at these or any other conditions beyond those indicated in

Table 118 is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

∆

VDD-VDD_TX

(1)

Symbol

, V

VDD_LDO

VDD_EXT

(5)

ESD voltage

DD_TX

(1)

DD_IO

pIO

p5V

p3V

scr

P t strg body

, V

DD_TX

(1)(2)

Table 118. Absolute maximum ratings

Parameter

Positive supply voltage

Positive supply voltage when option bit sup3V is set

Difference between V

and V

DD_TX

Peripheral communication supply voltage

Negative supply voltage

Voltage for peripheral IO communication pins (27 to 32)

(3)

Voltage for other pins (9, 11, 13, 14, 15 and 17)

(3) in the 5 V domain

Voltage for other pins (2 to 5, 7, 18, 19, 20 and 22 to 25)

(3) in the 3 V domain

Input current (latch-up immunity) according to JESD78

Maximum driver current using internal voltage regulator

Peak current supplied from an external source, internal voltage regulator bypassed

Electrostatic discharge voltage according to JS-001, human body model

Total power dissipation (all supplies and outputs)

Storage temperature

Package body temperature according to IPC/JEDEC

J-STD-020

(7)

Junction temperature

Humidity non-condensing

Min

-0.3

6.0

0.3

-100 100 mA

-65

Max

350

(4)

500

(6)

2000

300

150

260

Unit

V mA

V mW

°C

Jun

-40

125

1. Referenced to V

2. Bit sup3V set to 1 in IO configuration register 2

3. Refer to Table 2

for the corresponding WLCSP balls.

4. Provide good thermal management to ensure that junction temperature remains below the specified value.

5. VDD_RF is connected to VDD_TX to bypass the internal voltage regulator.

6. Peak current with RF driver externally supplied. Provide good thermal management to ensure that junction temperature remains below the specified value.

7. Reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020

“Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices”.

DS12484 Rev 4

ST25R3916/7 Electrical characteristics

All defined tolerances for external components in this specification need to be ensured over the whole operation conditions range and also over lifetime.

Symbol

Table 119. Operating conditions

Parameter Min Max Unit

, V

DD_TX

(1) (2)

Positive supply voltage (pins 8 and 10),

T amb

= -40 to 105 °C, rege <3:0> ≥ 07h

Positive supply voltage (pins 8 and 10),

T amb

= -20 to 105 °C

Positive supply voltage when option bit sup3V is set

(3)

T amb

= -40 to 105 °C, rege <3:0> ≥ 07h

Positive supply voltage when option bit sup3V is set (3)

T amb

= -20 to 105 °C

Difference between V

and V

DD_TX

Peripheral communication supply voltage (pin 1)

(4)

Negative supply voltage (pins 6, 12, 16 and 26)

(4)

2.6

2.4

2.6

2.4

5.5

3.6

∆

GND

-0.2

1.65

0.2

5.5

V pIO

(1) p5V

(1) p3V

(1)

Voltage for peripheral IO communication pins

(27 to 32) (4)

Voltage for other pins (9, 11, 13, 14, 15 and 17)

(4) in the 5 V domain

Voltage for other pins (2 to 5, 7, 18 to 20 and 22 to 25) in the 3 V domain

(4)

5.5

3.6

(amb, VFQFPN32)

(5)

(amb, WLCSP36)

(5)

RFI_A

Ambient temperature range for VFQFPN32 package

Ambient temperature range for WLCSP36 package

RFI input amplitude

(6)

-40

0.15

105

1. Referenced to V

2. If power supply is lower than 2.6 V, PSSR cannot be improved using internal regulators (minimum regulated voltage is 2.4 V).

3. Bit sup3V set to 1 in IO configuration register 2

4. Refer to Table 2

for the corresponding WLCSP balls.

5. The device must be mounted on a PCB with sufficient heat dissipation.

6. The minimum RFI input signal definition is meant for NFC active P2P reception and NFC passive target reception. In HF reader mode and NFC transmit mode the recommended signal level is 2.5 V

°C

DS12484 Rev 4

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156

Electrical characteristics ST25R3916/7

5.3 DC/AC characteristics for digital inputs and outputs

Type Symbol

Table 120. Characteristics of CMOS I/Os (1)

Parameter Conditions Min Typ Max Unit

Inputs

Output

(2)

LEAK

High level input voltage

Low level input voltage

Input leakage current

High level output voltage

Low level output voltage

0.8 * V

DD_IO

= 5.5 V

I source

DD_IO

= 1 mA

= 3.3 to

5.5 V, io_drv_lvl=0

-1

I source

= 0.5 mA

DD_IO

= 1.65 to 3.3 V io_drv_lvl = 1

I source

DD_IO

= 1 mA

= 3.3 to

5.5 V, io_drv_lvl=0

0.9 * V

DD_IO

I source

= 0.5 mA

DD_IO

= 1.65 to 3.3 V io_drv_lvl = 1

0.2 * V

DD_IO

0.1 * V

DD_IO

µA

Capacitive load

Output resistance

Pull-down resistance pin MISO

(3)

DD_IO

= 3.3 V

DD_IO

= 3.3 V

250

500

1. Minimum and maximum values tested in production at 25 °C, other temperature values evaluated from characterization.

2. Pins BSS, MOSI and SCLK.

3. Use bits miso_pd1 and miso_pd2 in the

to control the optional pull down on the MISO pin.

Ω k Ω

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DS12484 Rev 4

ST25R3916/7 Electrical characteristics

Symbol

Table 121. ST25R3916/7 electrical characteristics (V

= 3.3 V) (1)(2)

Parameter Conditions Min Typ Max Unit

NFCT

AL-AM

AL1

RFO

RFI

POR

AGDC

REG

Supply current in Power-down mode

Supply current in Initial NFC target mode

Supply current in Wake-up mode

(logic and RC oscillator)

Capacitive sensor supply current

Supply current in Ready mode

Supply current all active

Supply current all active, AM

Supply current all active single RX channel

RFO1 and RFO2 driver output resistance

RFI input sensitivity

RFI input resistance

Power on reset voltage

AGDC voltage

Regulated voltage

Jun

= -40 °C to 25 °C

(3)

Jun

= 85 °C

(3)

Jun

= 125 °C

(3)

Jun

= -40 °C to 25 °C

(4)

Jun

= 85 °C

(4)

Jun

= 125 °C

(4)

Jun

= -40 °C to 25 °C

(5)

Jun

= 85 °C

(5)

Jun

= 125 °C

(5)

(6)

(7)

(8)

(9)

(10)

RFO

(11)

(7)

(13)

= 10 mA

(12)

1.0

1.4

2.65

0.8

3.5

3.0

2.8

1.1

4.5

1.7

0.5

1.45

1.5

3.00

2.5

7.0

6.3

2.0

7.5

2.0

1.6

3.20

µA

µA mA mA

Ω mV k rms

Ω

1. 3.3 V supply mode with V connected to XTO and XTI.

= 3.3 V, unless specified otherwise. Regulated voltages are set at 3.0 V, 27.12 MHz Xtal

2. Minimum and maximum values tested in production at 25 °C, other temperature values evaluated from characterization.

3. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), other registers in default state.

4. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 03h (external field detector enable),

03h to E8h (enable NFC Target mode), other registers in default state.

5. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 04h (enable Wake-up mode), 32h to

08h (100 ms timeout, IRQ at every timeout), other registers in default state.

6. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), Test register 02h to 0Eh (tdana<3:0>=0Eh;

CS analog test mode 14), other registers in default state.

7. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to 80h (en = 1), 2Ch to

D8h (3.0 V regulator), other registers in default state, short VDD_A and VDD_D.

8. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to D8h (3.0 V regulator), other registers in default state, short

VDD_A and VDD_D.

9. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 03h to 14h (AM modulation), 28h to 7Fh (RFO segments disabled), 2Ch to D8h (3.0 V regulator), other registers in default state, short VDD_A and VDD_D.

10. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to E8h (enable RX, 1

RX channel, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to D8h (3.0 V regulator), other registers in default state, short VDD_A and VDD_D.

DS12484 Rev 4

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156

Electrical characteristics ST25R3916/7

11. f

SUB

= 848 kHz, AM channel with peak detector input stage selected.

12. Specified by design, not tested in production.

13. Manual regulator mode, V

= 3.6 V, regulated voltage set to 3.0 V, measured on pin VDD_RF: register 00h set to 0Fh, register 01h set to 80h (3 V supply mode), register 02h set to E8h (one channel RX, enable TX), 2Ch to D8h (3.0 V regulator), other registers in default state.

Symbol

NFCT

Table 122. ST25R3916/7 electrical characteristics (V

= 5.5 V)

(1) (2)

Parameter Conditions Min Typ Max

Supply current in

Power-down mode

Supply current in initial NFC target mode

Supply current in Wake-up mode

(logic and RC oscillator)

Capacitive sensor supply current

Jun

= -40 to 25 °C

(3)

Jun

= 125 °C

(3)

Jun

= 85 °C

Jun

= -40 to 25 °C

(4)

Jun

= 125 °C

(4)

Jun

= 85 °C

Jun

= -40 to 25 °C

(5)

Jun

= 125 °C

(5)

Jun

= 85 °C

(6)

2.5

3.4

1.1

2.0

(7)

Supply current in Ready mode

Supply current all active

Supply current all active, AM

(8)

(9)

5.6

15.0

16.0

7.5

23.0

26.0

Unit

µA

AL-AM mA mA

AL1

Supply current all active single RX channel

(10)

11.0

16.0

RFO

RFO1 and RFO2 driver output resistance

RFO

= 10 mA

(11)

1.7

4 Ω

RFI

POR

AGDC

REG

RFI input resistance

Power on reset voltage

AGDC voltage

Regulated voltage

(11)(12)

(8)

(11)

1.00

1.40

4.3

1.45

1.50

4.6

2.00

1.60

5.0

k Ω

1. Minimum and maximum values tested in production at 25 °C, other temperature values evaluated by characterization.

2. 5.0 V supply mode with V to XTO and XTI.

= 5.5 V unless specified otherwise. Regulated voltages set to 5.1

V, 27.12 MHz Xtal connected

3. Registers 00h to 07h (no clock on MCU_CLK), 01h to 00h (5 V supply mode), other registers in default state.

4. Registers 00h to 07h (no clock on MCU_CLK), 01h to 00h (5 V supply mode), 02h to 03h (external field detector enable),

03h to E8h (enable NFC Target mode), other registers in default state.

5. Registers 00h to 07h (no clock on MCU_CLK), 01h to 00h (5 V supply mode), 02h to 04h (enable Wake-up mode), 32h to

08h (100 ms timeout, IRQ at every timeout), other registers in default state.

6. Registers 00h to 07h (no clock on MCU_CLK), 01h to 00h (5 V supply mode), Test register 02h to 0Eh (tdana<3:0>=0Eh;

CS analog test mode 14), other registers in default state.

7. Registers 00h to 07h (no clock on MCU_CLK), 01h to 40h (5 V supply mode, disable VDD_D), 02h to 80h (en = 1), 2Ch to

F8h (5.1 V regulator), other registers in default state, short VDD_A and VDD_D.

8. Registers 00h to 07h (no clock on MCU_CLK), 01h to 40h (5 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to F8h (5.1 V regulator), other registers in default state, short

VDD_A and VDD_D.

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DS12484 Rev 4

ST25R3916/7 Electrical characteristics

9. Registers 00h to 07h (no clock on MCU_CLK), 01h to 40h (5 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 03h to 14h (AM modulation), 28h to 7Fh (RFO segments disabled), 2Ch to F8h (5.1 V regulator), other registers in default state, short VDD_A and VDD_D.

10. Registers 00h to 07h (no clock on MCU_CLK), 01h to 40h (5 V supply mode, disable VDD_D), 02h to E8h (enable RX, 1

RX channel, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to D8h (4.7 V regulator), other registers in default state, short VDD_A and VDD_D.

11. Evaluated by characterization, not tested in production.

12. f

SUB

= 848 kHz, AM channel with peak detector input stage selected.

Symbol

Table 123. ST25R3916/7 electrical characteristics (V

= 2.4 V) (1) (2)

Parameter Conditions Min Typ Max Unit

NFCT

AL-AM

Supply current in

Power-down mode

Supply current in initial NFC target mode

Supply current in Wake-up mode

(logic and RC oscillator)

Capacitive sensor supply current

Supply current in Ready mode

Supply current all active

Supply current all active, AM

Jun

= -40 to 25 °C

(3)

Jun

= 85 °C (3)

Jun

= 125 °C

(3)

Jun

= -40 to 25 °C (4)

Jun

= 85 °C

(4)

Jun

= 125 °C

(4)

Jun

= -40 to 25 °C

(5)

Jun

= 85 °C (5)

Jun

= 125 °C

(5)

(6)

(7)

(8)

(9)

0.5

1.5

7.0

1.5

1.8

2.7

0.7

3.4

12.5

2.2

2.0

7.5

µA mA mA

AL1

Supply current all active single RX channel

(10)

10 16

RFO

RFO1 and RFO2 driver output resistance

RFO

= 10 mA

(11)

1.7

4 Ω

RFI

POR

AGDC

REG

RFI input resistance

Power on reset voltage

AGDC voltage

Regulated voltage

(11)(12)

(8)

(11)

1.00

1.40

2.20

1.45

1.50

2.40

2.00

1.60

2.45

k Ω

1. Minimum and maximum values tested in production at 25 °C, other temperature values evaluated by characterization.

2. 3.3 V supply mode with V to XTO and XTI.

= 2.4 V unless specified otherwise. Regulated voltages set to 2.4 V, 27.12 MHz Xtal connected

3. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), other registers in default state.

4. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 03h (external field detector enable),

03h to E8h (enable NFC Target mode), other registers in default state.

5. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), 02h to 04h (enable Wake-up mode), 32h to

08h (100 ms timeout, IRQ at every timeout), other registers in default state.

6. Registers 00h to 07h (no clock on MCU_CLK), 01h to 80h (3 V supply mode), Test register 02h to 0Eh (tdana<3:0>=0Eh;

CS analog test mode 14), other registers in default state.

7. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to 80h (en = 1), 2Ch to

A8h (2.4 V regulator), other registers in default state, short VDD_A and VDD_D.

DS12484 Rev 4

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156

Electrical characteristics ST25R3916/7

8. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to A8h (2.4 V regulator), other registers in default state, short

VDD_A and VDD_D.

9. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to C8h (enable RX, enable TX), 03h to 14h (AM modulation), 28h to 7Fh (RFO segments disabled), 2Ch to A8h (2.4 V regulator), other registers in default state, short VDD_A and VDD_D.

10. Registers 00h to 07h (no clock on MCU_CLK), 01h to C0h (3 V supply mode, disable VDD_D), 02h to E8h (enable RX,

1 RX channel, enable TX), 28h to 7Fh (RFO segments disabled), 2Ch to A8h (2.4 V regulator), other registers in default state, short VDD_A and VDD_D.

11. Evaluated by characterization, not tested in production.

12. f

SUB

= 848 kHz, AM channel with peak detector input stage selected.

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DS12484 Rev 4

ST25R3916/7 Electrical characteristics

Operation Symbol

General

SCLK

SCLKL

SCLKH

SSH

NCSL

NCSH

DIS

DIH

Read

DOD

Table 124. SPI characteristics (5 MHz) (1)

Parameter

SCLK period

SCLK low

SCLK high

SPI reset (BSS high)

BSS falling to SCLK rising

SCLK falling to BSS rising

Data in setup time

Data in hold time

Data out delay

Conditions

SCLK

= T

SCLKL

+ T

SCLKH

First SCLK pulse

Last SCLK pulse

C load

DD_IO

≤ 50 pF,

= 1.65 to 3.0 V

C load

DD_IO

≤ 50 pF,

= 3.0 to 5.5 V

DOHZ

Data out to high impedance delay

1. Evaluated by characterization, not tested in production.

C load

≤ 50 pF

Min

100

Table 125. SPI characteristics (5 MHz < 1 / T

SCLK

< 10 MHz)

(1)

Operation Symbol Parameter Conditions Min Typ

General

Read

SCLK

SCLKL

SCLKH

SSH

NCSL

NCSH

DIS

DIH

DOD

DOHZ

SCLK period

SCLK low

SCLK high

SPI reset (BSS high)

BSS falling to SCLK rising

SCLK falling to BSS rising

Data in setup time

Data in hold time

Data out delay

Data out to high impedance delay

1. Evaluated by characterization, not tested in production.

SCLK

= T

SCLKL

+ T

SCLKH

First SCLK pulse

Last SCLK pulse

C load

≤ 50 pF

C load

≤ 50 pF

100

Typ

200

Max Unit

DS12484 Rev 4

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156

Electrical characteristics

BSS

SCLK

MOSI

ST25R3916/7

Figure 30. SPI timing diagram - General operation t

NCSL t

SCLKH t

SCLKL t

DIS t

DIH

DATAI DATAI

...

NCSH

...

DATAI

...

MISO

MS49945V1

Figure 31. SPI timing diagram - Read operation

BSS

...

SCLK

MOSI DATAI

...

MISO t

DOD

DATAO

...

DATAO t

DOHZ

MS49946V1

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DS12484 Rev 4

ST25R3916/7

5.6

Electrical characteristics

I2C interface characteristics

Timing according to I2C protocol. Drivers for up to 3.4 MHz operation.

Transition from 100 kHz / 400 kHz / 1 MHz mode to 3.4 MHz mode (High speed mode) is done via Master code 00001XXX, as described in the I2C specification.

Symbol

BUS

Table 126. AC measurement conditions

Parameter Min

Load capacitance

SCL input rise/fall time, SDA input fall time -

100

Max

Unit pF ns

Mode

Table 127. AC measurement conditions - I2C configuration

Rate Setting

F+

100 kHz

400 kHz

1000 kHz

3400 kHz i2c_thd = 00b, io_drv_lvl = 1b i2c_thd = 01b, io_drvl_lvl = 1b i2c_thd = 11b, Io_drv_lvl = 1b i2c_thd = 11b, io_drv_lvl = 1b

Symbol

Table 128. Input parameters

(1)

Parameter Conditions

Input capacitance (SDA)

Input capacitance (SCL)

1. Evaluated by characterization, not tested in production.

Min

Max

Unit pF

Symbol Parameter

Table 129. DC characteristics (1)

Conditions (in addition to those

in Table 126 and Table 127

)

Input leakage current (SCL, SDA)

Output leakage current

Input low voltage

(SCL, SDA)

Input high voltage

(SCL, SDA)

= V

or V

Standby mode

, device in

SDA in Hi-Z, external voltage applied on SDA: V

or V

Output low voltage

DD_IO

= 1.65 V, I

= 1.0 mA

DD_IO

= 2.4 V, I

= 2.1 mA

DD_IO

= 3.3 V, I

= 8 mA

DD_IO

= 5.5 V, I

= 8 mA

1. Evaluated by characterization, not tested in production.

Min

-0.4

0.8 V

DD_IO

Max

± 10

0.2 V

DD_IO

+ 0.4

0.1 V

DD_IO

0.1 V

DD_IO

0.1 V

DD_IO

0.1 V

DD_IO

Unit

µA

DS12484 Rev 4

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156

Electrical characteristics

Symbol Alt.

Table 130. 100 kHz AC characteristics (1)

Parameter f

C t

CHCL t

CLCH t

QL1QL2 t

DXCH t

CLDX

X t

CLQX t

CLQV t

CHDL t

DLCL t

CHDH t t

DHDL

(2) t t t f

SCL t

HIGH t

LOW t

F t

SU:DAT t

HD:DAT t

DH t

SU:STA

HD:STA

SU:STO t

BUF

Clock frequency

Clock pulse width high

Clock pulse width low

SDA (out) fall time

Data in set up time

Data in hold time

Data out hold time

Clock low to next data valid (access time)

Start condition setup time

Start condition hold time

Stop condition set up time

Time between Stop condition and next

Start condition

Pulse width ignored (input filter on SCL and SDA), single glitch

1. Conditions in addition to those specified in

2. Evaluated by characterization, not tested in production.

Min

4700

4000

4700

250

5000

4700

4000

Symbol Alt.

Table 131. 400 kHz AC characteristics

(1) (2)

Parameter f

C t

CHCL t

CLCH t

QL1QL2 t

DXCH t

CLDX

X t

CLQX t

CLQV t

CHDL t

DLCL t

CHDH t

DHDL t

NS f

SCL t

HIGH t

LOW t

F t

SU:DAT t

HD:DAT t

DH t

AA t

SU:STA t

HD:STA t

SU:STO t

BUF

Clock frequency

Clock pulse width high

Clock pulse width low

SDA (out) fall time

Data in set up time

Data in hold time

Data out hold time

Clock low to next data valid (access time)

Start condition setup time

Start condition hold time

Stop condition set up time

Time between Stop condition and next

Start condition

Pulse width ignored (input filter on SCL and SDA), single glitch

1. Conditions in addition to those specified in

2. Evaluated by characterization, not tested in production.

Min

1300

600

1300

100

600

ST25R3916/7

Max

3450

100

300

Unit kHz ns

Max

400

300

900

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DS12484 Rev 4

ST25R3916/7 Electrical characteristics

Symbol Alt.

Table 132. 1 MHz AC characteristics (1)(2)

Parameter t f

C t

CHCL t

CLCH t

QL1QL2

DHDL t

NS t t f

SCL

HIGH

LOW t

F t

DXCH t

SU:DAT t

CLDX

X t

HD:DAT t

CLQX t

CLQV t

CHDL t

DLCL t

CHDH t

DH t

AA t

SU:STA t

HD:STA t

SU:STO t

BUF

Clock frequency

Clock pulse width high

Clock pulse width low

SDA (out) fall time

Data in set up time

Data in hold time

Data out hold time

Clock low to next data valid (access time)

Start condition setup time

Start condition hold time

Stop condition set up time

Time between Stop condition and next Start condition

Pulse width ignored (input filter on SCL and SDA), single glitch

1. Conditions in addition to those specified in

2. Evaluated by characterization, not tested in production.

Min

260

500

250

500

Symbol Alt.

Table 133. 3.4 MHz AC characteristics

(1)(2)(3)

Parameter t t t f

C t

CHCL t

CLCH

QL1QL2 t t

DXCH t

CLQV t

CHDL

DLCL

CHDH

NS t t t f

SCL t

HIGH t

LOW t

SU:DAT t

CLDX

X t

HD:DAT t

CLQX t

DH t

AA t

SU:STA

HD:STA

SU:STO

Clock frequency

Clock pulse width high

Clock pulse width low

SDA (out) fall time (10-100 pF)

Data in set up time

Data in hold time

Data out hold time

Clock low to next data valid

Start condition setup time

Start condition hold time

Stop condition set up time

Pulse width ignored (input filter on SCL and SDA), single glitch

1. Conditions in addition to those specified in

Figure 5: ST25R3917 QFN32 pinout (top view)

2. Evaluated by characterization, not tested in production.

3. V

DD_IO

supply must not exceed V

Min Max Unit

160

150

3.4

MHz

41 ns

Max

450

120

Unit

MHz ns

DS12484 Rev 4

147/157

156

Electrical characteristics

Figure 32. R

Pmin

vs. V

, f c

= 3.4 MHz

ST25R3916/7

148/157

8000

7000

6000

5000

4000

3000

2000

1000

Figure 33. Maximum R bus

value vs. bus parasitic capacitance, f c

= 3.4 MHz

SCL

I2C bus master

SDA

R bus

C bus

ST25R39xx

10 20 30

Bus parasitic capacitance (pF)

40 50

MS53555V3

DS12484 Rev 4

ST25R3916/7 Electrical characteristics

SCLK/SCL

Figure 34. I2C AC waveforms

Start condition t

XH1XH2 t

XL1XL2 t

CHCL t

CLCH t

CHDL

MISO/SDA in t

CHDL t

XH1XH2

SDA input t

CLDX

SDA change t

DHCX

Stop condition

SCLK/SCL

MISO/SDA in t

CHDH t

CHCL t

Write cycle

SCLK/SCL

MISO/SDA out t

CHQV

Data valid t

CLQX

Data valid t

QL1QL2 t

XL1XL2

Stop condition

Start condition t

CHDH t

DHDL

Start condition t

CHDL

MS51627V1

Figure 35. I2C AC measurements

Input voltage levels

0.8VCC

Input and output

Timing reference levels

0.7VCC

0.3VCC

0.2VCC

MS19774V1

DS12484 Rev 4

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156

Package information ST25R3916/7

6.1

150/157

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com

ECOPACK is an ST trademark.

VFQFPN32 package information

VFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch, very thin fine pitch quad flat no lead package.

Figure 36. VFQFPN32 outline

Pin #1 ID

Chamfer 0.35

16 e

BOTTOM VIEW

L b

32x bbb M C A B

A D

TOP VIEW

SIDE VIEW

Detail A

Terminal length

0.05 Ref.

SLP1 PLATED AREA

Terminal thickness

Detail A ccc C

32x eee C

SIDE VIEW

B04R_ME_V1

1. Drawing is not to scale.

2. Coplanarity applies to the exposed pad as well as the terminal.

Symbol

L b

Min

0.800

0.300

0.180

Table 134. VFQFPN32 mechanical data millimeters inches

(1)

Typ

0.900

0.200

0.400

0.250

Max

1.000

0.050

0.500

0.300

Min

0.0315

0.0118

0.0071

Typ

0.0354

0.0079

0.0157

0.0098

Max

0.0394

0.0020

0.0197

0.0118

DS12484 Rev 4

ST25R3916/7 Package information

Table 134. VFQFPN32 mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

E2 e

S1 bbb

E ccc eee

3.400

5.000

3.500

5.000

3.500

0.500

0.350

0.100

0.080

3.600

0.1339

1. Values in inches are converted from mm and rounded to four decimal digits.

Typ

0.1969

0.1378

0.1969

0.1378

0.0197

0.0138

0.0039

0.0031

Figure 37. VFQFPN32 recommended footprint

3.50

0.80

Max

0.1417

0.25

0.50

3.50

B04R_FP_V1

1. Dimensions are expressed in millimeters.

DS12484 Rev 4

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156

Package information

6.2 WLCSP36 package information

ST25R3916/7

WLCSP36 is a 36-ball, 3.213x3.203 mm, 0.5 mm pitch, wafer level chip scale package.

Orientation reference

TOP VIEW

Figure 38. WLCSP36 outline

(2X) aaa

DETAIL A

(2X) aaa b

SIDE VIEW

6 5 e1

4 e

3 2 1

Orientation reference

BOTTOM VIEW e

F e1

Symbol

(2) b

E e e1

A1 eee Z b (36x) ccc M Z X Y ddd M Z

Seating plane

DETAIL A

1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.

4. Bump position designation per JESD 95-1, SPP-010.

B078_WLCSP36_ME_V1

Min

0.550

3.193

3.183

Table 135. WLCSP36 mechanical data millimeters inches

(1)

Typ

0.590

0.235

0.330

0.025

0.330

3.213

3.203

0.500

2.500

0.347

Max

0.630

3.233

3.223

Min

0.0217

0.1257

0.1253

Typ

0.0232

0.0093

0.013

0.001

0.013

0.1265

0.1261

0.0197

0.0984

0.0137

Max

0.0248

0.1273

0.1269

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DS12484 Rev 4

ST25R3916/7 Package information

Table 135. WLCSP36 mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

G aaa bbb ccc ddd eee

0.352

0.100

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating

Typ

0.0139

0.0039

0.002

Figure 39. WLCSP36 recommended footprint

2.5

0.5

Max

0.5

2.5

36 bumps x 0.330

B078_WLCSP36_FP_V1

1. Dimensions are expressed in millimeters.

DS12484 Rev 4

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156

Ordering information ST25R3916/7

Note:

Example:

Device type

ST25 = NFC/RFID tags and readers

Product type

R = NFC/HF reader

ST25 R 3916 -A QW T

Product feature

3916 = High performance NFC universal device and EMVCo reader

3917 = High performance NFC Forum reader

Ambient temperature range

A = -40 °C to 105 °C

B = -40 °C to 85 °C

Package/Packaging

QW = 32-pin VFQFPN (5 x 5 mm) with wettable flanks

WL = WLCSP

Tape and reel

T = 4000 pcs/reel (VFQFPN), 5000 pcs/reel (WLCSP)

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

154/157

DS12484 Rev 4

ST25R3916/7 Revision history

Date

30-Jan-2019

05-Dec-2019

Revision

Table 136. Document revision history

Changes

Initial release.

Introduced ST25R3917, hence added

Table 1: List of features

and Table 3: ST25R3917 -

VFQFPN32 pin assignment

Updated image on cover page, Figure 3: ST25R3916/7 block diagram

Figure 6: ST25R3916 WLCSP36 (top view) ,

Figure 17: SPI communication: FIFO reading ,

Figure 26: Read and Write mode for register space-B access

and Figure 27: I2C master reads slave immediately after the first byte .

Updated

Features

Section 2: Description ,

Section 4.3.4: I2C interface ,

Section 4.5.23: No-response timer register 2 ,

Section 4.5.46: Antenna tuning control register 1 , Section 4.5.47: Antenna tuning control register

, and Section 7: Ordering information .

Updated

Table 11: SPI operation modes

Table 13: List of direct commands

Table 18: List of registers - Space B ,

Table 24: Target operation modes ,

Table 20: IO configuration register 2 ,

Table 21: