®
SG2525A
SG3525A
.
.
.
.
.
.
8 TO 35 V OPERATION
REGULATING PULSE WIDTH MODULATORS
5.1 V REFERENCE TRIMMED TO
±
1 %
100 Hz TO 500 KHz OSCILLATOR RANGE
SEPARATE OSCILLATOR SYNC TERMINAL
ADJUSTABLE DEADTIME CONTROL
INTERNAL SOFT-START
.
.
PULSE-BY-PULSE SHUTDOWN
INPUT UNDERVOLTAGE LOCKOUT WITH .
HYSTERESIS
LATCHING PWM TO PREVENT MULTIPLE .
PULSES
DUAL SOURCE/SINK OUTPUT DRIVERS
DIP16 16(Narrow)
DESCRIPTION
The SG3525A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to
±
1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the C
T
and the discharge terminals provide a wide range of dead time ad- justment.
These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The
SG3525A output stage features NOR logic, giving a
LOW output for an OFF state.
PIN CONNECTIONS AND ORDERING NUMBERS (top view)
Type
SG2525A
SG3525A
Plastic DIP
SG2525AN
SG3525AN
SO16
SG2525AP
SG3525AP
June 2000 1/12
SG2525A-SG3525A
ABSOLUTE MAXIMUM RATINGS
Symbol
V i
V
C
I
OSC
I o
I
R
I
T
P tot
T j
T stg
T op
Supply Voltage
Collector Supply Voltage
Oscillator Charging Current
Parameter
Output Current, Source or Sink
Reference Output Current
Current through C
T
Terminal
Logic Inputs
Analog Inputs
Total Power Dissipation at T amb
= 70
°
C
Junction Temperature Range
Storage Temperature Range
Operating Ambient Temperature : SG2525A
SG3525A
Value
40
40
5
500
50
5
– 0.3 to + 5.5
– 0.3 to V i
1000
– 55 to 150
– 65 to 150
– 25 to 85
0 to 70
Unit
V
V mA mA mA mA
V
V mW
°
C
°
C
°
C
°
C
THERMAL DATA
Symbol
R th j-pins
R th j-amb
R th j-alumina
Parameter
Thermal Resistance Junction-pins Max
Thermal Resistance Junction-ambient Max
Thermal Resistance Junction-alumina (*) Max
SO16
50
DIP16
50
80
Unit
°
C/W
°
C/W
°
C/W
* Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 ×
20 mm ; 0.65 mm thickness with infinite heatsink.
BLOCK DIAGRAM
2/12
SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS
(V# i = 20 V, and over operating temperature, unless otherwise specified)
SG2525A SG3525A
Symbol Parameter Test
Min. Typ. Max. Min. Typ. Max.
Unit
REFERENCE SECTION
V
REF
∆
V
REF
Output Voltage
Line Regulation
∆
V
REF
Load Regulation
∆
V
REF
/
∆
T* Temp. Stability
I
T
V
L j i
= 25
°
C
= 8 to 35 V
= 0 to 20 mA
Over Operating Range
5.05
5.1
10
20
20
5.15
20
50
50
5 5.1
10
20
20
5.2
20
50
50
V mV mV mV
*
*
∆
V
REF
*
Total Output Variation Line, Load and
Temperature
Short Circuit Current
Output Noise Voltage
Long Term Stability
V
REF
= 0 T j
= 25
°
C
10 Hz
≤ f
≤
10 kHz,
T j
= 25
°
C
T j
= 125
°
C, 1000 hrs
OSCILLATOR SECTION * *
*,
•
*,
•
Initial Accuracy
Voltage Stability
∆ f/
∆
T* Temperature Stability
T
V j i
= 25
°
C
= 8 to 35 V f f
MIN
MAX
Minimum Frequency
Maximum Frequency
Over Operating Range
R
T
= 200 K
Ω
C
T
= 0.1
µ
F
R
T
= 2 K
Ω
C
T
= 470 pF
Current Mirror I
RT
= 2 mA
*,
•
*,
•
Clock Amplitude
Clock Width T j
= 25
°
C
Sync Threshold
Sync Input Current Sync Voltage = 3.5 V
ERROR AMPLIFIER SECTION (V
CM
= 5.1 V)
V
OS
I b
I os
*
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain R
L
≥
10 M
Ω
G v
= 0 dB T j
= 25
°
C
*, ❚
Gain Bandwidth
Product
DC Transconduct.
30 K
T j
Ω ≤
R
= 25
°
C
L
≤
1 M
Ω
Output Low Level
CMR
PSR
Output High Level
Comm. Mode Reject.
Supply Voltage
Rejection
V
V i
CM
= 1.5 to 5.2 V
= 8 to 35 V
5
400
1.7
3
0.3
1.2
60
1
1.1
3.8
60
50
80
40
20
±
2
±
6
±
0.3
±
1
±
3
±
6
120
2
3.5
0.5
2
1
0.5
1
75
2
1.5
0.2
5.6
75
60
5.2
100
200
50
2.2
1
2.8
2.5
5
10
1
0.5
4.95
400
1.7
3
0.3
1.2
60
1
1.1
3.8
60
50
80
40
20
±
2
±
1
±
3
2
3.5
0.5
2
1
2
1
75
2
1.5
0.2
5.6
75
60
5.25
100
200
µ
Vrms
50
±
6
±
2
±
6
120
2.2
1
2.8
2.5
10
10
1
0.5
V mA mV mV
µ
A
µ
A dB
MHz ms
V
V dB dB mA
V
µ s
V mA
%
%
%
Hz
KHz
3/12
SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS (continued)
SG2525A SG3525A
Symbol Parameter Test
Min. Typ. Max. Min. Typ. Max.
Unit
PWM COMPARATOR
Minimum Duty-cycle
•
•
Maximum Duty-cycle
Input Threshold
* Input Bias Current
SHUTDOWN SECTION
Zero Duty-cycle
Maximum Duty-cycle
45
0.7
49
0.9
3.3
0.05
0
3.6
1
45
0.7
49
0.9
3.3
0.05
0
3.6
1
%
%
V
V
µ
A
25
0.6
50
0.4
0.8
80
0.7
1
25
0.6
50
0.4
0.8
80
0.7
1
µ
A
V
V
Soft Start Current
Soft Start Low Level
Shutdown Threshold
V
SD
= 0 V, V
SS
= 0 V
V
SD
= 2.5 V
To outputs, V
SS
T j
= 25
°
C
= 5.1 V
*
Shutdown Input Current V
SD
= 2.5 V
Shutdown Delay V
SD
= 2.5 V T j
= 25
°
C
OUTPUT DRIVERS (each output) (V
C
= 20 V)
I s
Output Low Level I sink
= 20 mA
Output High Level
I sink
= 100 mA
I source
= 20 mA
I t r
C
* t f
*
Under-Voltage Lockout V comp
and V ss
= High
Collector Leakage
Rise Time
Fall Time
TOTAL STANDBY CURRENT
I source
= 100 mA
V
C
= 35 V
C
L
= 1 nF, T j
= 25
°
C
C
L
= 1 nF, T j
= 25
°
C
Supply Current V i
= 35 V
18
17
6
0.4
0.2
0.2
1
19
18
7
100
50
14
1
0.5
0.4
2
8
200
600
300
20
18
17
6
0.4
0.2
0.2
1
19
18
7
100
50
14
1
0.5
0.4
2
8
200
600
300
20 mA
µ
V
V
V
V
V s
µ
A ns ns mA
Tested at f osc
= 40 KHz (R
T
= 3.6 K
Ω
, C
T
= 10nF, R
D
= 0
Ω
). Approximate oscillator frequency is defined by : f =
1
C
T
(0.7 R
T
+ 3 R
D
)
.
DC transconductance (g
M
) relates to DC open-loop voltage gain (G v
) according to the following equation : G v
= g
M
R
L
where R
L
is the resistance from pin 9 to ground. The minimum g
M
specification is used to calculate minimum G v
when the error amplifier output is loaded.
4/12
TEST CIRCUIT
SG2525A-SG3525A
5/12
SG2525A-SG3525A
RECOMMENDED OPERATING CONDITIONS (
•
)
•
Parameter
Input Voltage (V i
)
Collector Supply Voltage (V
C
)
Sink/Source Load Current (steady state)
Sink/Source Load Current (peak)
Reference Load Current
Oscillator Frequency Range
Oscillator Timing Resistor
Oscillator Timing Capacitor
Dead Time Resistor Range
(
⋅
) Range over which the device is functional and parameter limits are guaranteed.
Figure 1 : Oscillator Charge Time vs. R
T
and C
T
.
Value
8 to 35 V
4.5 to 35 V
0 to 100 mA
0 to 400 mA
0 to 20 mA
100 Hz to 400 KHz
2 K
Ω
to 150 K
Ω
0.001
µ
F to 0.1
µ
F
0 to 500
Ω
Figure 2 : Oscillator Discharge Time vs. R
D
and C
T
.
Figure 3 : Output Saturation
Characteristics.
Figure 4 : Error Amplifier Voltage Gain and
Phase vs. Frequency.
6/12
Figure 5 : Error Amplifier.
SG2525A-SG3525A
PRINCIPLES OF OPERATION
SHUTDOWN OPTIONS (see Block Diagram)
Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100
µ
A to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions : the PWM latch is immediately set providing the fastest turn-off signal to the outputs ; and a 150
µ
A current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting.
Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release.
Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation.
7/12
SG2525A-SG3525A
Figure 6 : Oscillator Schematic.
Figure 7 : Output Circuit (1/2 circuit shown).
8/12
Figure 8.
Figure 9.
SG2525A-SG3525A
For single-ended supplies, the driver outputs are grounded. The V
C
terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles.
Figure 10.
In conventional push-pull bipolar designs, forward base drive is controlled by R
1
- R
3
. Rapid turn-off times for the power devices are achieved with speed-up capacitors C
1
and C
2
.
Figure 11.
The low source impedance of the output drivers provides rapid charging of Power Mos input capacitance while minimizing external components.
Low power transformers can be driven directly.
Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground.
9/12
SG2525A-SG3525A
F
I
L
E e e3
Z a1
B b
DIM.
mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.51
0.77
1.65
0.020
0.030
0.065
0.5
0.25
0.020
0.010
b1
D 20 0.787
8.5
2.54
17.78
0.335
0.100
0.700
3.3
7.1
5.1
1.27
0.130
0.280
0.201
0.050
OUTLINE AND
MECHANICAL DATA
DIP16
10/12
SG2525A-SG3525A
DIM.
D (1)
E e e3
F (1)
G
L
M
S
A a1 a2 b b1
C c1 mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.1
1.75
0.25
0.004
0.069
0.009
0.35
0.19
1.6
0.46
0.014
0.25
0.007
0.063
0.018
0.010
0.5
0.020
9.8
5.8
45˚ (typ.)
10 0.386
6.2
0.228
0.394
0.244
1.27
8.89
0.050
0.350
3.8
4.6
0.4
4 0.150
5.3
0.181
1.27
0.016
0.62
8˚(max.)
0.157
0.209
0.050
0.024
OUTLINE AND
MECHANICAL DATA
SO16 Narrow
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
11/12
SG2525A-SG3525A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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