STMicroelectronics STIPQ5M60T-HL Datasheet
โฆษณา
โฆษณา
STIPQ5M60T-HL, STIPQ5M60T-HZ
Datasheet
SLLIMM™-nano 2
nd
series IPM, 3-phase inverter, 5 A, 1.0 Ω max., 600 V,
N
‑
channel MDmesh™ DM2 Power MOSFET
N2DIP-26L type L
N2DIP-26L type Z
Product status links
STIPQ5M60T-HL
STIPQ5M60T-HZ
Order code
Marking
Product summary
STIPQ5M60T-HL
STIPQ5M60T-HL
IPQ5M60T-HL
Package N2DIP-26L type L
Packing Tube
STIPQ5M60T-HZ
Order code
Marking
Package
Packing
STIPQ5M60T-HZ
IPQ5M60T-HZ
N2DIP-26L type Z
Tube
Features
• IPM 5 A, 600 V, R
DS(on)
= 1.0 Ω, 3-phase Power MOSFET inverter bridge including control ICs for gate driving
• Optimized for low electromagnetic interference
• 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pull-down/ pull-up resistors
• Undervoltage lockout
• Internal bootstrap diode
• Interlocking function
• Shutdown function
• Comparator for fault protection against overtemperature and overcurrent
• Op-amp for advanced current sensing
• Optimized pinout for easy board layout
• NTC for temperature control (UL 1434 CA 2 and 4)
• Isolation ratings of 1500 Vrms/min.
• UL recognition: UL 1557, file E81734
Applications
• 3-phase inverters for motor drives
• Dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps
Description
This SLLIMM (small low-loss intelligent molded module)-nano provides a compact, high-performance AC motor drive in a simple, rugged design. It is composed of six Nchannel MDmesh™ DM2 Power MOSFETs with intrinsic fast-recovery diode and three half-bridge HVICs for gate driving, providing low electromagnetic interference
(EMI) characteristics with optimized switching speed. The package is designed to allow a better and easy screw on heatsink. It is optimized for thermal performance and compactness in built-in motor applications, or other low-power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM™ is a trademark of STMicroelectronics.
DS11999 - Rev 4 - March 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
STIPQ5M60T-HL, STIPQ5M60T-HZ
Internal schematic diagram and pin configuration
1
Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
GND(1 )
T/SD/OD (2)
VccW(3 )
HinW(4 )
LinW(5 )
OP+(6 )
OPOUT(7 )
OP-(8 )
VccV(9 )
HinV(10)
LinV(11 )
Cin(12)
VccU(13 )
HinU(14)
T/SD/OD(15)
LinU(16 )
NTC
GND
HVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
GND
OPOUT
OP-
OP+
HVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
GND
CIN
HVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
(26)N W
(25)W,OUT W
(24)Vboot W
(23)N V
(22)V,OUT V
(21)Vboot V
(20)N U
(19)U,OUT U
(18) P
(17)Vboot U
GIPD120120170806SA
DS11999 - Rev 4 page 2/24
DS11999 - Rev 4
7
8
9
5
6
3
4
10
11
12
13
14
15
20
21
22
23
16
17
18
19
24
25
26
Pin
1
2
Symbol
GND
T/SD/OD
V
CC
W
HIN W
LIN W
OP+
OP
OUT
OP-
V
CC
V
HIN V
LIN V
CIN
V
CC
U
HIN U
T/SD/OD
LIN U
V boot
U
P
U, OUT
U
N
U
V boot
V
V, OUT
V
N
V
V boot
W
W, OUT
W
N
W
STIPQ5M60T-HL, STIPQ5M60T-HZ
Internal schematic diagram and pin configuration
Table 1. Pin description
Description
Ground
NTC thermistor terminal/shutdown logic input (active low)/open-drain
(comparator output)
Low-voltage power supply W phase
High-side logic input for W phase
Low-side logic input for W phase
Op-amp non-inverting input
Op-amp output
Op-amp inverting input
Low-voltage power supply V phase
High-side logic input for V phase
Low-side logic input for V phase
Comparator input
Low-voltage power supply for V phase
High-side logic input for V phase
NTC thermistor terminal/shutdown logic input (active low)/open-drain
(comparator output)
Low-side logic input for U phase
Bootstrap voltage for U phase
Positive DC input
U phase output
Negative DC input for U phase
Bootstrap voltage for V phase
V phase output
Negative DC input for V phase
Bootstrap voltage for W phase
W phase output
Negative DC input for W phase page 3/24
DS11999 - Rev 4
STIPQ5M60T-HL, STIPQ5M60T-HZ
Internal schematic diagram and pin configuration
Exposed pin not connected
PIN 26
Figure 2. Pin layout (top view) - N2DIP-26L type L
* *
PIN 17
PIN 1
* Dummy pins internally connected to P (positive DC input)
Figure 3. Pin layout (top view) - N2DIP-26L type Z
Exposed pin internally connected to GND
PIN 16
GADG181220181209IG
* *
PIN 17
Exposed pin not connected
PIN 26
PIN 1 PIN 16
Exposed pin internally connected to GND
* Dummy pins internally connected to P (positive DC input)
GADG181220181216IG page 4/24
2
2.1
STIPQ5M60T-HL, STIPQ5M60T-HZ
Electrical ratings
Electrical ratings
T
J
= 25 °C unless otherwise specified
Absolute maximum ratings
Table 2. Inverter part
Symbol
V
DSS
± I
D
± I
DP
P
TOT
Parameter
MOSFET blocking voltage (or drain-source voltage) for each MOSFET
(V
IN
= 0)
Continuous drain current for each MOSFET
Peak drain current for each MOSFET (less than 1 ms)
Total power dissipation for each MOSFET (T
C
1. Applied among HINx, LINx and GND for x = U, V, W.
2. Pulse width limited by maximum junction temperature
= 25 °C)
Symbol
V
CC
V boot
V
OUT
V
CIN
V op+
V op-
V
IN
V
T/SD/OD dV out
/dt
Table 3. Control part
Parameter
Low voltage power supply
Bootstrap voltage
Output voltage applied among OUT
U
,
OUT
V
, OUT
W
- GND
Comparator input voltage
Op-amp non-inverting input
Op-amp inverting input
Logic input voltage applied among HINx,
LINx and GND
Open-drain voltage
Allowed output slew rate
Min.
-0.3
-0.3
V boot
- 21
-0.3
-0.3
-0.3
-0.3
-0.3
Symbol
V
ISO
T
J
T
C
Table 4. Total system
Parameter
Isolation withstand voltage applied on each pin and heatsink plate
(AC voltage, t = 60 s)
Power chip operating junction temperature
Module case operation temperature
Value
600
5
10
12.8
Unit
V
A
A
W
Max.
21
620
V boot
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
15
15
50
Unit
V
V
V
V
V
V/ns
V
V
V
Value
1500
-40 to 150
-40 to 125
Unit
Vrms
°C
°C
DS11999 - Rev 4 page 5/24
2.2
STIPQ5M60T-HL, STIPQ5M60T-HZ
Thermal data
Thermal data
Symbol
R th(j-c)
Table 5. Thermal data
Parameter
Thermal resistance junction-case single MOSFET
Value
9.8
Unit
°C/W
DS11999 - Rev 4 page 6/24
3
3.1
STIPQ5M60T-HL, STIPQ5M60T-HZ
Electrical characteristics
Electrical characteristics
T
J
= 25 °C unless otherwise noted.
Inverter part
Table 6. Static
Symbol
V
I
DSS
(BR)DSS
R
DS(on)
V
SD
Static drain source turn-on resistance
Parameter
Zero-gate voltage drain current
Drain-source breakdown voltage
Test conditions
V
DS
= 600 V, V
CC
= 15 V,
V boot
= 15 V
V
CC
= V boot
= 15 V, V
IN
= 0 V,
I
D
= 1 mA
V
CC
= V boot
= 15 V, V
IN
= 0 to 5 V,
I
D
= 2.5 A
Drain-source diode forward voltage
V
IN
= 0 “logic state”, I
D
= 5 A
1. Applied among HINx, LINx and GND for x = U, V, W.
Min.
600
Typ.
Max.
Unit
1 mA
0.8
1.25
1.0
1.8
V
Ω
V
Table 7. Inductive load switching time and energy
Symbol t on
t c(on)
t off
t c(off)
t rr
E on
E off
Parameter
Turn-on time
Crossover time (on)
Turn-off time
Crossover time (off)
Reverse recovery time
Turn-on switching energy
Turn-off switching energy
V
DD
V
Test conditions
= 300 V, V
CC
IN
(see
= V boot
C
= 15 V,
= 2.5 A
Figure 5. Switching time definition
)
Min.
-
-
-
-
-
-
-
Typ.
325
113
380
37
140
88
9
Max.
-
-
-
-
-
-
-
Unit ns
µJ
1. t
ON
and t
OFF
include the propagation delay time of the internal drive. t itself under the internally given gate driving conditions.
C(ON)
and t
C(OFF)
are the switching times of MOSFET
2. Applied among HINx, LINx and GND for x = U, V, W.
DS11999 - Rev 4 page 7/24
DS11999 - Rev 4
STIPQ5M60T-HL, STIPQ5M60T-HZ
Inverter part
+Vcc
Figure 4. Switching time test circuit
Input
5V
0V
+5V
RSD
LIN
SD/OD
HIN
VCC
Vboot
HVG
OUT
LVG
GND
++
--
Vboot>Vc c
++
Vds
--
L
I c
C
+
Vdd
-
GIPD161120151702RV
V
Figure 5. Switching time definition
100% I D 100% I D t rr
DS
I
D
I
D
V
DS
V
IN
V
IN(ON) t
ON t
C(ON)
10% I
D
90% I
D
10% V
DS
V
IN t
OFF
V
IN(OFF)
(a) turn-on
Figure 5. Switching time definition refers to HIN, LIN inputs (active high).
10% V
DS t
C(OFF)
10% I
D
(b) turn-off
AM09223V2 page 8/24
3.2
STIPQ5M60T-HL, STIPQ5M60T-HZ
Control part
Control part
Symbol
V
CC_hys
V
CC_thON
V
CC_thOFF
I qccu
I qcc
V ref
Table 8. Low-voltage power supply (V
CC
= 15 V unless otherwise specified)
Test conditions Parameter
V
CC
UV hysteresis
V
CC
UV turn-ON threshold
V
CC
UV turn-OFF threshold
Undervoltage quiescent supply current
Quiescent current
V
CC
= 10 V, T/SD/OD = 5 V,
LIN = HIN = CIN = 0 V
V
CC
= 10 V, T/SD/OD = 5 V,
LIN = HIN = CIN = 0 V
Min.
1.2
11.5
10
Typ.
1.5
12
10.5
Internal comparator (CIN) reference voltage
0.51
0.54
Max.
1.8
12.5
11
150
1
0.56
Unit
V
V
V
µA mA
V
Symbol
V
BS_hys
V
BS_thON
V
BS_thOFF
I
QBSU
I
QBS
R
DS(on)
Table 9. Bootstrapped voltage (V
CC
= 15 V unless otherwise specified)
Test conditions Parameter
V
BS
UV hysteresis
V
BS
UV turn-ON threshold
V
BS
UV turn-OFF threshold
Min.
1.2
11.1
9.8
Typ.
1.5
11.5
10
Undervoltage V
BS current
quiescent
V
BS
quiescent current
Bootstrap driver on-resistance
V
BS
< 9 V, T/SD/OD = 5 V,
LIN = 0 V and HIN = 5 V,
CIN = 0
V
BS
= 15 V, T/SD/OD = 5 V,
LIN = 0 V and HIN = 5 V,
CIN = 0
LVG ON
70
200
120
Max.
1.8
12.1
10.6
Unit
V
V
V
110
300
µA
µA
Ω
Symbol
I
LINI
I
LINh
I
SDh
I
SDI
V il
V ih
I
HINh
I
HINI
Dt
Table 10. Logic inputs (V
CC
= 15 V unless otherwise specified)
Test conditions Min.
Parameter
Low logic level voltage
High logic level voltage
HIN logic “1” input bias current
HIN logic “0” input bias current
LIN logic “1” input bias current
LIN logic “0” input bias current
SD logic “0” input bias current
SD logic “1” input bias current
Dead time
HIN = 15 V
HIN = 0 V
LIN = 15 V
LIN = 0 V
SD = 15 V
SD = 0 V
See
Section 3.3 Waveform definitions
2.25
20
20
210
Typ.
40
40
350
180
100
1
100
1
477
3
Max.
0.8
µA
µA
µA
µA
µA
µA
Unit
V
V ns
DS11999 - Rev 4 page 9/24
DS11999 - Rev 4
STIPQ5M60T-HL, STIPQ5M60T-HZ
Control part
Symbol
V io
I io
I ib
V
OL
V
OH
I o
SR
Table 11. Op-amp characteristics (V
CC
= 15 V unless otherwise specified)
Parameter
Input offset voltage
Input offset current
Input bias current
Low-level output voltage
High-level output voltage
Test conditions
V ic
= 0 V, V o
= 7.5 V
V ic
= 0 V, V o
= 7.5 V
Min.
Typ.
Output short-circuit current
Slew rate
GBWP
A vd
SVR
CMRR
Gain bandwidth product
Large signal voltage gain
Supply voltage rejection ratio
Common mode rejection ratio
1. The direction of the input current is out of the IC.
R
L
= 10 kΩ to V
CC
R
L
= 10 kΩ to GND
Source, V id
= +1 V, V o
= 0 V
Sink, V id
= -1 V, V o
= V
CC
V i
= 1 to 4 V, C
L
= 100 pF, unity gain
V o
= 7.5 V
R
L
= 2 kΩ vs. V
CC
8
70
60
55
14
16
50
2.5
4
100
75
14.7
30
80
3.8
12
85
75
70
Max.
6
40
200
150
V/µs
MHz dB dB dB
Unit mV nA nA mV
V mA mA
Table 12. Sense comparator characteristics (V
CC
= 15 V unless otherwise specified)
Symbol
R
V
I ib od
ON_OD
Parameter
Input bias current
Open-drain low level output voltage
Open-drain low level output resistance
I
I
V
CIN od od
Test conditions
= 1 V
= 3 mA
= 3 mA
R
PD_SD t d_comp
SR t sd
Comparator delay
Slew rate
Shutdown to high-/low-side driver propagation delay
T/SD/OD pulled to 5 V through
100 kΩ resistor
C
L
= 180 pF, R pu
= 5 kΩ
V
OUT
= 0, V boot
= V
CC
,
V
IN
= 0 to 3.3 V t isd
Comparator triggering to high-/ low-side driver turn-off propagation delay
Measured applying a voltage step from 0 V to 3.3 V to pin CIN
1. Equivalent values are the result of the resistances of three drivers in parallel.
Min.
50
50
Typ.
166
125
90
60
125
200
Max.
1
0.5
130
200
250
Unit
µA
V ns
Ω kΩ ns
V/µs page 10/24
STIPQ5M60T-HL, STIPQ5M60T-HZ
Control part
3.2.1
Conditions
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
0 “logic state” half-bridge tri-state
1 “logic state” low-side direct driving
1 “logic state” high-side direct driving
1. X: do not care.
NTC thermistor
Table 13. Truth table
T/SD/OD
L
H
H
H
H
Logic input (V
I
)
LIN
H
L
H
L
HIN
L
H
H
L
Vbias
Figure 6. Internal structure of SD and NTC
V
T/SD/OD
R SD
C SD NTC
LIN
SD/OD
HIN
VCC
Vboot
HVG
RPD_SD
OUT
LVG
GND CIN
LVG
L
H
L
L
L
Output
HVG
L
L
H
L
L
RPD_SD: equivalent value as result of resistances of three drivers in parallel.
Figure 7. Equivalent resistance (NTC//R
PD_SD
)
140
120
100
80
60
40
20
0
-40 -20 0 20 40
Temperature (°C)
60 80 100 120
DS11999 - Rev 4 page 11/24
DS11999 - Rev 4
STIPQ5M60T-HL, STIPQ5M60T-HZ
Control part
14
12
10
8
6
4
2
0
70
Figure 8. Equivalent resistance (NTC//R
PD_SD
) zoom
80 90 100
Temperature (°C)
110 120
Figure 9. Voltage of T/SD/OD pin according to NTC temperature
5.0
SD/OD: high
4.5
R
V
Bias
SD
= 5 V
= 2.2 kΩ
4.0
3.5
3.0
2.5
2.0
25
V
Bias
R
SD
= 3.3 V
= 1.0 kΩ
50 75
Temperature (°C)
100 125 page 12/24
3.3
STIPQ5M60T-HL, STIPQ5M60T-HZ
Waveform definitions
Waveform definitions
Figure 10. Dead time and interlocking waveform definitions
G
DS11999 - Rev 4 page 13/24
4
HIN or LIN
HVG or LVG
SD/OD or
T/SD/OD
U
STIPQ5M60T-HL, STIPQ5M60T-HZ
Shutdown function
Shutdown function
The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection.
The comparator has an internal voltage reference V
REF
connected to the inverting input, while the non-inverting input pin (CIN) can be connected to an external shunt resistor for current monitoring.
Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs, whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which fixes the disabling time.
For an effective design of the shutdown circuit, please refer to Application note AN4966.
Figure 11. Shutdown timing waveforms
GADG250120171515FSR
V
REF
CI N
V, W
PROTECT ION open -drain gate
(interna l)
A
B
A B
∗
∗
∗
∗
≅
_
R
SD
and C
SD
external circuitry must be designed to ensure
Please refer to AN4966 for further details.
∗
∗
* R
NTC
to be considered only when the NTC is internally connected to the T/SD/OD pin.
DS11999 - Rev 4 page 14/24
5
STIPQ5M60T-HL, STIPQ5M60T-HZ
Application circuit example
Application circuit example
Figure 12. Application circuit example
DS11999 - Rev 4
MICROCONTROLLE R
GADG100620160912FSR
Application designers are free to use a different scheme according to the specifications of the device.
page 15/24
STIPQ5M60T-HL, STIPQ5M60T-HZ
Guidelines
5.1
Guidelines
•
•
•
•
•
•
•
•
•
•
•
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC filters (R
1
, C
1
) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins.
The use of a bypass capacitor C
VCC
(aluminum or tantalum) can reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C
2
(100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the V cc
pin and in parallel with the bypass capacitor.
The use of an RC filter (R
SF
, C
SF
) is recommended to prevent protection circuit malfunction. The time constant (R
SF
x C
SF
) should be set to 1 μs and the filter must be placed as close as possible to the C
IN
pin.
The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally connected between the SD pin and GND. The voltage V
SD
-GND decreases as the temperature increases, due to the pull-up resistor R
SD
. In order to keep the voltage always higher than the high-level logic threshold, the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The capacitor C
SD
of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation time τ
A
≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin.
The decoupling capacitor C
3
C boot
(from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each
, filters high-frequency disturbance. Both C possible to the U, V, W and V boot boot
and C
3
(if present) should be placed as close as
pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
To avoid overvoltage on the V cc
pin, a Zener diode (Dz1) can be used. Similarly on the V boot
pin, a Zener diode (Dz2) can be placed in parallel with each C boot
.
The use of the decoupling capacitor C
4
(100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor C vdc
is useful to prevent surge destruction. Both capacitors C placed as close as possible to the IPM (C
4
has priority over C vdc
).
4
and C vdc
should be
By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-couplers is possible.
Low-inductance shunt resistors have to be used for phase leg current sensing.
In order to avoid malfunctions, the wiring on N pins, the shunt resistor and P
WR_GND
should be as short as possible.
The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation.
These guidelines ensure the specifications of the device for application designs. For further details, please refer to the relevant application note.
Symbol
V
PN
V
CC
V
BS t dead f
PWM
T
C
Table 14. Recommended operating conditions
Parameter
Supply voltage
Test conditions
Applied among P-Nu, Nv, Nw
Control supply voltage
High-side bias voltage
Applied to V
CC
-GND
Applied to V
BOOTx
V, W
-OUT for x = U,
Blanking time to prevent arm-short For each input signal
PWM input signal
-40 °C < T
C
< 100 °C
-40 °C < T
J
< 125 °C
Case operation temperature
Min.
13.5
13
1
Typ.
300
15
Max.
500
18
18
Unit
V
V
V
µs
25
100 kHz
°C
DS11999 - Rev 4 page 16/24
STIPQ5M60T-HL, STIPQ5M60T-HZ
Electrical characteristics (curves)
6
Electrical characteristics (curves)
Figure 13. Output characteristics
I
D
(A) V
CC
= 15 V
GADG261020181155OCH
8
T
J
= 25 °C
6
4
T
J
= 150 °C
2
0
0 2 4 6 8 10 V
DS
(V)
I
D
(A)
Figure 15. I
D
vs case temperature
GADG261020181157CCT
5
4
3
2
1
V
CC
≥ 15 V, T
J
≤ 150 °C
0
0 25 50 75 100 125 T
C
(°C)
Figure 17. E
OFF
switching energy vs drain current
E
OFF
(mJ)
GADG261020181159EFC
V
DD
= 300 V, V
CC
= 15 V
0.05
0.04
0.03
0.02
0.01
0
0 2
T
J
= 150 °C
4 6
T
J
= 25 °C
8 I
D
(A)
Figure 14. Diode V
SD
vs drain current
V
SD
(V)
1.4
V
CC
= 15 V
1.2
1.0
T
J
= 25 °C
0.8
0.6
0.4
0.2
0
0 2 4
GADG261020181156DVF
T
J
= 150 °C
6 8 I
D
(A)
Figure 16. E
ON
switching energy vs drain current
E
ON
(mJ)
GADG261020181159ENC
1.25
V
DD
= 300 V, V
CC
= 15 V
1.00
T
J
= 150 °C 0.75
0.50
0.25
0
0 2 4 6
T
J
= 25 °C
8 I
D
(A)
Figure 18. Thermal impedance for MOSFET
K Zthjc N2DIP-26L
10 -1
10 -2
10 -3
10 -5 10 -4 10 -3 10 -2 10 -1 10 0 t p
(s)
DS11999 - Rev 4 page 17/24
7
7.1
STIPQ5M60T-HL, STIPQ5M60T-HZ
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
N2DIP-26L type L package information
Figure 19. N2DIP-26L type L package outline
DS11999 - Rev 4
8558322_typeL_rev3 page 18/24
DS11999 - Rev 4
Dim.
A6 b b2 c
D
D1
D2
A
A1
A2
A3
A4
A5 e1 eB1
L
Dia
D3
E e
STIPQ5M60T-HL, STIPQ5M60T-HZ
N2DIP-26L type L package information
30.65
12.35
1.70
2.40
14.25
0.85
3.10
0.83
0.46
32.05
2.10
1.85
1.70
1.70
8.10
1.75
0.53
Min.
4.80
0.80
4.00
Table 15. N2DIP-26L type L mechanical data
4.10
1.80
1.80
8.40
mm
Typ.
5.10
1.00
32.15
30.75
12.45
1.80
2.50
14.55
1.05
3.20
Max.
5.40
1.20
4.20
1.90
1.90
8.70
0.72
1.02
0.59
32.25
30.85
12.55
1.90
2.60
14.85
1.25
3.30
page 19/24
7.2
STIPQ5M60T-HL, STIPQ5M60T-HZ
N2DIP-26L type Z package information
N2DIP-26L type Z package information
Figure 20. N2DIP-26L type Z package outline
DS11999 - Rev 4
8558322_typeZ_rev3 page 20/24
DS11999 - Rev 4
Dim.
D3
E e e1 eB1 eB2
L
Dia
A6 b b2 c
D
D1
D2
A
A1
A2
A3
A4
A5
STIPQ5M60T-HL, STIPQ5M60T-HZ
N2DIP-26L type Z package information
30.65
12.35
1.70
2.40
16.10
0.83
0.46
32.05
2.10
1.85
21.18
0.85
3.10
1.70
1.70
8.10
1.75
0.53
Min.
4.80
0.80
4.00
Table 16. N2DIP-26L type Z mechanical data
4.10
1.80
1.80
8.40
mm
Typ.
5.10
1.00
32.15
30.75
12.45
1.80
2.50
16.40
21.48
1.05
3.20
Max.
5.40
1.20
4.20
1.90
1.90
8.70
0.72
1.02
0.59
32.25
30.85
12.55
1.90
2.60
16.70
21.78
1.25
3.30
page 21/24
7.3
STIPQ5M60T-HL, STIPQ5M60T-HZ
N2DIP-26L packing information
N2DIP-26L packing information
Figure 21. N2DIP-26L tube (dimensions are in mm)
DS11999 - Rev 4 page 22/24
STIPQ5M60T-HL, STIPQ5M60T-HZ
Revision history
Date
17-Jan-2017
09-Jun-2017
07-Nov-2018
06-Mar-2019
2
3
4
Table 17. Document revision history
Revision
1
Changes
Initial release.
Modified features on cover page.
Datasheet promoted from preliminary data to production data.
Updated Section 6: "Package information" .
Minor text changes.
Updated Section 2 Electrical ratings and Section 3 Electrical characteristics .
Updated Section 4 Shutdown function .
Added Section 6 Electrical characteristics (curves) .
Minor text changes
Updated Section 1 Internal schematic diagram and pin configuration ,
Figure 11. Shutdown timing waveforms
and
Table 14. Recommended operating conditions
.
Minor text changes
DS11999 - Rev 4 page 23/24
STIPQ5M60T-HL, STIPQ5M60T-HZ
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS11999 - Rev 4 page 24/24
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