STMicroelectronics STGIPQ8C60T-HZ Datasheet
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STGIPQ8C60T-HZ
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STGIPQ8C60T-HZ
GIPQ8C60T-HZ
N2DIP-26L type Z
Tube
STGIPQ8C60T-HZ
Datasheet
SLLIMM™ nano - 2
nd
series IPM, 3-phase inverter, 8 A, 600 V, short
‑
circuit rugged IGBTs
Features
• IPM 8 A, 600 V, 3-phase IGBT inverter bridge including 3 control ICs for gate driving and freewheeling diodes
• 3.3 V, 5 V, 15 V TTL/CMOS input comparators with hysteresis and pull-down/ pull-up resistors
• Internal bootstrap diode
• Optimized for low electromagnetic interference
• Undervoltage lockout
• Short-circuit rugged TFS IGBTs
• Shutdown function
• Interlocking function
• Op-amp for advanced current sensing
• Comparator for fault protection against overcurrent
• Isolation ratings of 1500 V rms
/min.
• UL recognition: UL 1557, file E81734
• NTC (UL 1434 CA 2 and 4)
Applications
• 3-phase inverters for motor drives
• Dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps
Description
This second series of SLLIMM (small low-loss intelligent molded module)-nano provides a compact, high-performance AC motor drive in a simple, rugged design. It is composed of six improved short-circuit rugged trench gate fieldstop IGBTs with freewheeling diodes and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed.
The package is designed to allow a better and more easily screwed-on heatsink, and is optimized for thermal performance and compactness in built-in motor applications or other low power applications where assembly space is limited. This IPM includes a completely uncommitted operational amplifier and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM™ is a trademark of
STMicroelectronics.
DS11492 - Rev 4 - January 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
1
GND (1)
T/ SD / OD (2)
Vcc W (3)
HIN W (4)
LIN W ( 5)
OP+ (6)
OPOUT (7)
OP- (8)
Vcc V (9)
HIN V (10)
LIN V (11)
CIN (12)
Vcc U (13)
HIN U (14)
T / SD / OD (15)
LIN U (16)
STGIPQ8C60T-HZ
Internal schematic diagram and pin configuration
Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
NTC
N W (26)
W, OUT W (25)
Vboot W (24)
GND
HVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
GND
OPOUT
OP+
OPHVG
VCC
HIN
SD/OD
LIN
OUT
LVG
Vboot
GND
CIN
HVG
OUT
VCC
HIN LVG
SD/OD
LIN Vboot
N V (23)
V, OUT V (22)
Vboot V (21)
N U (20)
U, OUT U (19)
P (18)
Vboot U (17)
GIPG300720141542SMD
DS11492 - Rev 4 page 2/25
DS11492 - Rev 4
7
8
9
5
6
3
4
10
11
12
13
14
15
20
21
22
23
16
17
18
19
24
25
26
Pin
1
2
Symbol
GND
T/SD/ OD
V
CC
W
HIN W
LIN W
OP+
OP
OUT
OP-
V
CC
V
HIN V
LIN V
CIN
V
CC
U
HIN U
T/SD/ OD
LIN U
V boot
U
P
U, OUT
U
N
U
V boot
V
V, OUT
V
N
V
V boot
W
W, OUT
W
N
W
STGIPQ8C60T-HZ
Internal schematic diagram and pin configuration
Table 1. Pin description
Description
Ground
NTC thermistor terminal/shutdown logic input (active low)/open-drain
(comparator output)
Low-voltage power supply W phase
High-side logic input for W phase
Low-side logic input for W phase
Op-amp non-inverting input
Op-amp output
Op-amp inverting input
Low-voltage power supply V phase
High-side logic input for V phase
Low-side logic input for V phase
Comparator input
Low-voltage power supply for V phase
High-side logic input for V phase
NTC thermistor terminal/shutdown logic input (active low)/open-drain
(comparator output)
Low-side logic input for U phase
Bootstrap voltage for U phase
Positive DC input
U phase output
Negative DC input for U phase
Bootstrap voltage for V phase
V phase output
Negative DC input for V phase
Bootstrap voltage for W phase
W phase output
Negative DC input for W phase page 3/25
Exposed pin not connected
PIN 26
STGIPQ8C60T-HZ
Internal schematic diagram and pin configuration
Figure 2. Pin layout (top view) - N2DIP-26L type Z
* *
PIN 17
PIN 1 PIN 16
Exposed pin internally connected to GND
* Dummy pins internally connected to P (positive DC input)
GADG181220181216IG
DS11492 - Rev 4 page 4/25
2
2.1
STGIPQ8C60T-HZ
Electrical ratings
Electrical ratings
T
J
= 25 °C unless otherwise specified
Absolute maximum ratings
Table 2. Inverter part
Symbol
V
CES
I
C
I
CP
P
TOT
Parameter
Collector-emitter voltage for each IGBT (V
IN
= 0)
Continuous collector current for each IGBT (T
C
= 25 °C)
Peak collector current for each IGBT (less than 1 ms) t
SCW
Total power dissipation for each IGBT (T
C
= 25 °C)
Short-circuit withstand time (V
CE
= 300 V, T
J
= 125 °C, V
CC
= V boot
= 15 V,
V
IN
= 0 to 5 V)
1. Pulse width limited by maximum junction temperature.
2. Applied among HIN x
, LIN x and
GND for x = U, V, W
Symbol
V
CC
V boot
V
OUT
V
CIN
V op+
V op-
V
IN
V
T/SD/OD dV out
/dt
Table 3. Control part
Parameter
Low voltage power supply
Bootstrap voltage
Output voltage applied among OUT
U
,
OUT
V
, OUT
W
- GND
Comparator input voltage
Op-amp non-inverting input
Op-amp inverting input
Logic input voltage applied among HINx,
LINx and GND
Open-drain voltage
Allowed output slew rate
Min.
-0.3
-0.3
V boot
- 21
-0.3
-0.3
-0.3
-0.3
-0.3
Max.
21
620
V boot
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
15
15
50
Value
600
8
16
19.2
5
Symbol
V
ISO
T
J
T
C
Table 4. Total system
Parameter
Isolation withstand voltage applied to each pin and heatsink plate
(AC voltage, t = 60 s)
Power chip operating junction temperature
Module case operation temperature
Value
1500
-40 to 150
-40 to 125
Unit
V rms
°C
°C
Unit
V
V
V
V
V
V/ns
V
V
V
Unit
V
A
A
W
µs
DS11492 - Rev 4 page 5/25
2.1.1
Thermal data
Symbol
R th(j-c)
Table 5. Thermal data
Parameter
Thermal resistance junction-case single IGBT
Thermal resistance junction-case single diode
STGIPQ8C60T-HZ
Absolute maximum ratings
Value
6.5
10
Unit
°C/W
DS11492 - Rev 4 page 6/25
3
3.1
STGIPQ8C60T-HZ
Electrical characteristics
Electrical characteristics
T
J
= 25 °C unless otherwise noted.
Inverter part
Table 6. Static
Symbol
I
CES
Parameter
Collector cut-off current
(V
IN
= 0 “logic state”)
V
CE
Test conditions
= 550 V, V
CC
= V
Boot
= 15 V
V
CE(sat)
V
F
Collector-emitter saturation voltage
Diode forward voltage
V
CC
= V boot
= 15 V, V
IN
I
C
= 8 A
V
IN
= 0 “logic state”, I
C
= 8 A
1. Applied among HIN x
, LIN x
and G
ND
for x = U, V, W
Min.
-
Typ.
Max.
250
Unit
μA
-
2.0
2.4
2.4
V
V
Table 7. Inductive load switching time and energy
Symbol t on
t c(on)
t off
t c(off)
t rr
E on
E off
Parameter
Turn-on time
Crossover time (on)
Turn-off time
Crossover time (off)
Reverse recovery time
Turn-on switching energy
Turn-off switching energy
V
V
DD
Test conditions
= 300 V,V
IN
CC
= V
= 0 to 5 V, I
C boot
= 8 A
= 15 V,
Figure 4. Switching time definition )
Min.
-
-
-
-
-
-
-
Typ.
290
145
515
90
110
200
95
Max.
-
-
-
-
-
-
-
Unit ns
µJ
1. t
ON
and t
OFF
include the propagation delay times of the internal drive. t itself under the internally given gate driving conditions.
C(ON)
and t
C(OFF)
are the switching times of IGBT
2. Applied among HIN x
, LIN x
and G
ND
for x = U, V, W.
DS11492 - Rev 4 page 7/25
Figure 3. Switching time test circuit
STGIPQ8C60T-HZ
Inverter part
V
Figure 4. Switching time definition
100% I
C t rr
100% I
C
CE
I
C
I
C
V
CE
AM06019v2
DS11492 - Rev 4
V
IN
V
IN(ON) t
ON
10% I
C t
C(ON)
90% I
C
10% V
CE
(a) turn-on
V
IN t
OFF
V
IN(OFF)
10% V
CE t
C(OFF)
10% I
C
(b) turn-off
AM09223V1 page 8/25
3.2
STGIPQ8C60T-HZ
Control part
Control part
(V
CC
= 15 V unless otherwise specified)
Symbol
V
CC_hys
V
CC_thON
V
CC_thOFF
I qccu
I qcc
V ref
Quiescent current
Table 8. Low-voltage power supply
Parameter
V
CC
UV hysteresis
V
CC
UV turn-ON threshold
V
CC
UV turn-OFF threshold
Undervoltage quiescent supply current
Test conditions
V
CC
= 10 V, V
T/SD/OD
= 5 V,
LIN = HIN = CIN = 0 V
V
CC
= 10 V, V
T/SD/OD
= 5 V,
LIN = HIN = CIN = 0 V
Internal comparator (CIN) reference voltage
Min.
1.2
11.5
10
Typ.
1.5
12
10.5
Max.
1.8
12.5
11
150
Unit
V
V
V
µA
0.51
0.54
1
0.56
mA
V
Symbol
V
BS_hys
V
BS_thON
V
BS_thOFF
I
QBSU
I
QBS
R
DS(on)
Parameter
V
BS
UV hysteresis
V
BS
UV turn-ON threshold
V
BS
UV turn-OFF threshold
Table 9. Bootstrapped voltage
Test conditions
Undervoltage V
BS current
quiescent
V
BS
quiescent current
Bootstrap driver on-resistance
V
BS
< 9 V, V
T/SD/OD
= 5 V,
LIN = 0 V and HIN = 5 V,
CIN = 0 V
V
BS
= 15 V, V
T/SD/OD
= 5 V,
LIN = 0 V and HIN = 5 V,
CIN = 0 V
LVG ON
Min.
1.2
11.1
9.8
Typ.
1.5
11.5
10
Max.
1.8
12.1
10.6
Unit
V
V
V
70 110 µA
150 210 µA
120 Ω
Symbol
I
LINl
I
LINh
I
SDh
I
SDl
V il
V ih
I
HINh
I
HINl
Dt
Parameter
Low logic level voltage
High logic level voltage
HIN logic “1” input bias current
HIN logic “0” input bias current
LIN logic “0” input bias current
LIN logic “1” input bias current
SD logic “0” input bias current
SD logic “1” input bias current
Dead time
Table 10. Logic inputs
Test conditions
HIN = 15 V
HIN = 0 V
LIN = 0 V
LIN = 15 V
SD = 15 V
SD = 0 V
See
Figure 9. Dead time and interlocking waveform definitions
Min.
2.25
20
20
210
Typ.
Max.
0.8
40
40
350
180
100
1
1
100
477
3
µA
µA
µA
µA
µA
Unit
V
V
µA ns
DS11492 - Rev 4 page 9/25
DS11492 - Rev 4
STGIPQ8C60T-HZ
Control part
Table 11. Op-amp characteristics
Symbol
V io
I io
I ib
V
OL
V
OH
I o
SR
GBWP
A vd
SVR
CMRR
Parameter Test conditions
Input offset voltage
Input offset current V ic
= 0 V, V o
= 7.5 V
Low level output voltage
High level output voltage
Output short-circuit current
Slew rate
Gain bandwidth product
R
L
= 10 kΩ to V
CC
R
L
= 10 kΩ to GND
Source, V id
= + 1 V; V o
= 0 V
Sink, V id
= -1 V; V o
= V
CC
V i
= 1 - 4 V; C
L
= 100 pF; unity gain
V o
= 7.5 V
Large signal voltage gain R
L
= 2 kΩ
Supply voltage rejection ratio vs V
CC
Common mode rejection ratio
1. The direction of input current is out of the IC.
14
16
50
2.5
8
70
60
55
Min.
14.7
30
80
3.8
12
85
75
70
4
100
75
Typ.
Max.
6
40
200
150
V mA mA
V/µs
MHz
Unit mV nA nA mV dB dB dB
Table 12. Sense comparator characteristics
Symbol
V
I ib od
R
ON_OD
R
PD_SD
Parameter
Input bias current
Open-drain low level output voltage
Open-drain low level output
SD pull-down resistor
I
I
V
CIN od od
Test conditions
= 1 V
= 3 mA
= 3 mA t d_comp t
SR t sd isd
Comparator delay
Slew rate
Shutdown to high-/low-side driver propagation delay
Comparator triggering to high-/ low-side driver turn-off propagation delay
V
T/SD/OD
pulled to 5 V through 100 kΩ resistor
C
L
= 180 pF, R pu
= 5 kΩ
V
V
OUT
IN
= 0, V boot
= 0 to 3.3 V
= V
CC
,
Measured applying a voltage step from 0 V to 3.3 V to pin CIN
1. Equivalent values as a result of the resistances of three drivers in parallel.
Min.
-
-
-
50
50
-
-
-
Typ.
Max.
1
0.5
166
125
90
60
125
130
200
Unit
µA
V
Ω kΩ ns
V/µs ns
200 250 page 10/25
STGIPQ8C60T-HZ
Control part
3.2.1
Conditions
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
0 “logic state” half-bridge tri-state
1 “logic state” low-side direct driving
1 “logic state” high-side direct driving
1. X: don’t care.
NTC thermistor
Table 13. Truth table
T/SD/OD
L
H
H
H
H
Logic input (V
I
)
LIN
H
L
H
L
HIN
L
H
H
L
Vbias
Figure 5. Internal structure of SD and NTC
V
T/SD/OD
R SD
C SD NTC
LIN
SD/OD
HIN
VCC
Vboot
HVG
RPD_SD
OUT
LVG
GND CIN
LVG
L
H
L
L
L
Output
HVG
L
L
H
L
L
RPD_SD: equivalent value as result of resistances of three drivers in parallel.
Figure 6. Equivalent resistance (NTC//R
PD_SD
)
140
120
100
80
60
40
20
0
-40 -20 0 20 40
Temperature (°C)
60 80 100 120
DS11492 - Rev 4 page 11/25
DS11492 - Rev 4
STGIPQ8C60T-HZ
Control part
14
12
10
8
6
4
2
0
70
Figure 7. Equivalent resistance (NTC//R
PD_SD
) zoom
80 90 100
Temperature (°C)
110 120
Figure 8. Voltage of T/SD/OD pin according to NTC temperature
5.0
SD/OD: high
4.5
R
V
Bias
SD
= 5 V
= 2.2 kΩ
4.0
3.5
3.0
2.5
2.0
25
V
Bias
R
SD
= 3.3 V
= 1.0 kΩ
50 75
Temperature (°C)
100 125 page 12/25
3.3
Waveform definitions
Figure 9. Dead time and interlocking waveform definitions
G
STGIPQ8C60T-HZ
Waveform definitions
DS11492 - Rev 4 page 13/25
4
STGIPQ8C60T-HZ
Shutdown function
Shutdown function
The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection.
The comparator has an internal voltage reference V
REF
connected to the inverting input, while the non-inverting input pin (CIN) can be connected to an external shunt resistor for current monitoring.
Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs, whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which fixes the disabling time.
For an effective design of the shutdown circuit, please refer to Application note AN4966.
DS11492 - Rev 4 page 14/25
DS11492 - Rev 4
STGIPQ8C60T-HZ
Shutdown function
Figure 10. Shutdown timing waveforms
CI N
V
REF
HIN or LIN
HVG or LVG
SD/OD or
T/SD/OD
U V, W
PROTECT ION open -drain gate
(interna l)
A
B
A B
∗
∗
∗
∗
_
≅
∗
∗
R
SD
and C
SD
external circuitry must be designed to ensure
Please refer to AN4966 for further details.
* R
NTC
to be considered only when the NTC is internally connected to the T/SD/OD pin.
GADG250120171515FSR page 15/25
5
Application circuit example
Figure 11. Application circuit example
STGIPQ8C60T-HZ
Application circuit example
DS11492 - Rev 4
MICROCONTROLLER
GAD250720161156FSR
Application designers are free to use a different scheme according to the specifications of the device.
page 16/25
STGIPQ8C60T-HZ
Guidelines
5.1
Guidelines
•
•
•
•
•
•
•
•
•
•
•
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC filters (R
1
, C
1
) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins.
The use of a bypass capacitor C
VCC
(aluminum or tantalum) can reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C
2
(100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the V cc
pin and in parallel with the bypass capacitor.
The use of an RC filter (R
SF
, C
SF
) is recommended to prevent protection circuit malfunction. The time constant (R
SF
x C
SF
) should be set to 1 μs and the filter must be placed as close as possible to the C
IN
pin.
The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally connected between the SD pin and GND. The voltage V
SD
-GND decreases as the temperature increases, due to the pull-up resistor R
SD
. In order to keep the voltage always higher than the high-level logic threshold, the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The capacitor C
SD
of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation time τ
A
≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin.
The decoupling capacitor C
3
C boot
(from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each
, filters high-frequency disturbance. Both C possible to the U, V, W and V boot boot
and C
3
(if present) should be placed as close as
pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
To avoid overvoltage on the V cc
pin, a Zener diode (Dz1) can be used. Similarly on the V boot
pin, a Zener diode (Dz2) can be placed in parallel with each C boot
.
The use of the decoupling capacitor C
4
(100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor C vdc
is useful to prevent surge destruction. Both capacitors C placed as close as possible to the IPM (C
4
has priority over C vdc
).
4
and C vdc
should be
By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-couplers is possible.
Low-inductance shunt resistors have to be used for phase leg current sensing.
In order to avoid malfunctions, the wiring on N pins, the shunt resistor and P
WR_GND
should be as short as possible.
The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation.
These guidelines ensure the specifications of the device for application designs. For further details, please refer to the relevant application note.
Symbol
V
PN
V
CC
V
BS t dead f
PWM
T
C
Table 14. Recommended operating conditions
Parameter
Supply voltage
Test conditions
Applied among P-Nu, Nv, Nw
Control supply voltage
High-side bias voltage
Applied to V
CC
-GND
Applied to V
BOOTx
V, W
-OUT for x = U,
Blanking time to prevent arm-short For each input signal
PWM input signal
-40 °C < T
C
< 100 °C
-40 °C < T
J
< 125 °C
Case operation temperature
Min.
13.5
13
1
Typ.
300
15
Max.
500
18
18
Unit
V
V
V
µs
25
100 kHz
°C
DS11492 - Rev 4 page 17/25
STGIPQ8C60T-HZ
Electrical characteristics (curves)
6
Electrical characteristics (curves)
Figure 12. Output characteristics (T
J
= 25°C)
I
C
(A)
IGBT250720161421OC25
V
GE
= 13 - 18 V
8
6
4
2
0
0 0.6
1.2
1.8
V
CE
(V)
1.0
0.5
0
0
2.5
2.0
1.5
Figure 14. Diode V
F
vs forward current
V
F
(V)
3.0
IGBT260620151410DVF
T
J
= 25 °C
T
J
= 150 °C
4 8 12 I
F
(A)
Figure 16. E on
switching energy vs collector current
E on
(mJ)
IGBT250720161523SLC
V
DD
= 300 V, V
CC
= V boot
= 15 V
0.36
T
J
= 150 °C
0.27
0.18
0.09
0
0 2 4 6
T
J
= 25 °C
8 I
C
(A)
Figure 13. V
CE(sat)
vs collector current
V
CE(SAT)
(V)
IGBT161220161058VCEC
V
CC
= 15 V
2.4
T
J
= 150 °C
2
T
J
= 25 °C
1.6
1.2
0.8
0 2 4 6 8 I
C
(A)
I
C
(A)
Figure 15. I
C
vs case temperature
GADG28012019945CD
8.0
6.0
4.0
2.0
0.0
0
V
CC
≥ 15 V, T
J
≤ 150 °C
50 100 125 T
C
(°C)
Figure 17. E off
switching energy vs collector current
E off
(mJ)
IGBT250720161533SLC
V
DD
= 300 V, V
CC
= V boot
= 15 V
0.12
0.06
T
J
= 150 °C
T
J
= 25 °C
0
0 2 4 6 8 I
C
(A)
DS11492 - Rev 4 page 18/25
Figure 18. Thermal impedance for IGBT
K Zthjc N2DIP-26L IGBT
10 -1
10 -2
10 -3
10 -5 10 -4 10 -3 10 -2 10 -1 10 0 t p
(s)
STGIPQ8C60T-HZ
Electrical characteristics (curves)
DS11492 - Rev 4 page 19/25
7
7.1
STGIPQ8C60T-HZ
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
N2DIP-26L type Z package information
Figure 19. N2DIP-26L type Z package outline
DS11492 - Rev 4
8558322_typeZ_rev3 page 20/25
DS11492 - Rev 4
Dim.
D3
E e e1 eB1 eB2
L
Dia
A6 b b2 c
D
D1
D2
A
A1
A2
A3
A4
A5
STGIPQ8C60T-HZ
N2DIP-26L type Z package information
30.65
12.35
1.70
2.40
16.10
0.83
0.46
32.05
2.10
1.85
21.18
0.85
3.10
1.70
1.70
8.10
1.75
0.53
Min.
4.80
0.80
4.00
Table 15. N2DIP-26L type Z mechanical data
4.10
1.80
1.80
8.40
mm
Typ.
5.10
1.00
32.15
30.75
12.45
1.80
2.50
16.40
21.48
1.05
3.20
Max.
5.40
1.20
4.20
1.90
1.90
8.70
0.72
1.02
0.59
32.25
30.85
12.55
1.90
2.60
16.70
21.78
1.25
3.30
page 21/25
7.2
N2DIP-26L packing information
Figure 20. N2DIP-26L tube (dimensions are in mm)
STGIPQ8C60T-HZ
N2DIP-26L packing information
DS11492 - Rev 4 page 22/25
STGIPQ8C60T-HZ
Revision history
Date
22-Jan-2016
26-Jul-2016
16-Dec-2016
30-Jan-2019
2
3
4
Table 16. Document revision history
Revision
1
Changes
Initial release.
Document status promoted from target to preliminary data.
Updated features in cover page, Section 3: Electrical characteristics, Section 3.2: Control part, Section 5: Application circuit example and Section 6: Guidelines.
Added Section 7: Electrical characteristics (curves).
Document status promoted from preliminary to production data.
Updated Figure 12: V
CE(sat)
vs. collector current.
Updated N2DIP-26L type Z cover image silhouette and Section Features
.
Added
Figure 2. Pin layout (top view) - N2DIP-26L type Z
and
.
Updated Section 3.2 Control part
.
Minor text changes.
DS11492 - Rev 4 page 23/25
STGIPQ8C60T-HZ
Contents
Contents
DS11492 - Rev 4 page 24/25
STGIPQ8C60T-HZ
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS11492 - Rev 4 page 25/25
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