STMicroelectronics SUPERH ST40 SYSTEM ARCHITECTURE VOLUME 3: VIDEODEVICES Reference Manual

DENC_DAC_IF.DATA1

DAC CPU interface data register 1, see

Section 3.3.3:

DENC_DAC_IF.CONTROL2

DAC interface control register 2, see

Section 3.3.2:

DENC_DAC_IF.DATA2

DAC CPU interface data register

Section 3.3.3:

DENC_DAC_IF.TIMING on page 109

DENC_DAC_IF_TIMING Minimum NUMBEr of cycles allowed between falling edges of the NOTCS signal to the

DENC, see

Section 3.3.4:

Table 6: Address map

Type

Address offset

0x000

Access size

0x010

0x018

0x020

0x028

0x800

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Register descriptions

3.3 Register descriptions

3.3.1 DENC_DAC_IF.VCR

DENC_DAC_IF.VCR

is the version control register for the DAC unit.

DENC_DAC_IF.VCR

Field Bits Size

MVERS 16-31 16 operation

Read

Write

HARD reset

0x000

Volatile Synopsis no Module version

Used to indicate module version number

Returns 0x0000 ignored

Type

105

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106 Register descriptions

3.3.2 DENC_DAC_IF.CONTROL[n]

DENC_DAC_IF.CONTROL[ N } is the DAC interface control register.

DENC_DAC_IF.CONTROL[n] where n= 1 or 2

Field

REG_EN 0

Bits

Size

ENABLE 1

SET operation read write hard reset operation read write hard reset

2 operation read write hard reset

0x0[n]0

Volatile Synopsis Type no Enable register access to DAC

If bit set then DAC inputs from the register interface, if not set then DAC inputs from DENC.

returns current value updates current value

0 no DAC ENABLE RW

This bit is driven to the DAC enable pin when REG_EN bit is set returns current value updates current value

0 no DAC SET RW

This bit is driven to the DAC set pin when REG_EN bit is set returns current value updates current value

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Register descriptions 107

DENC_DAC_IF.CONTROL[n] where n= 1 or 2

Field Bits

RESET

CLK

3 operation read write

1 hard reset

4 1 operation read write hard reset

COMPO 5 1

Size operation read write hard reset

0x0[n]0

Volatile Synopsis Type no DAC RESET RW

This bit is driven to the DAC reset pin when REG_EN bit is set returns current value updates current value

0 no DAC CLK RW

This bit is driven to the DAC clock pin when REG_EN bit is set returns current value updates current value

0 no DAC inputs from

RGB/YUV or CVBS

This bit selects between the RGB/YUV and the CVBS outputs from the DENC to the DAC.

1: CVBS composite input

0: RGB/YUV input returns current value updates current value

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108 Register descriptions

3.3.3 DENC_DAC_IF.DATA[n]

DENC_DAC_IF.DATA[ N ] is the DAC CPU interface data register.

DENC_DAC_IF.DATA[n] where n = 1 or 2

Field Bits Size

UPIN_DATA 0-9 operation

VPIN_DATA

WPIN_DAT

A read write hard reset

10-19 operation read write hard reset

20-29 operation read write hard reset

0x0[n]8

Volatile Synopsis no DAC YDATA

This is driven to DAC YDATA when REG_EN in

DAC.CONTROL is set returns current value updates current value

0 no DAC UDATA

This is driven to DAC UDATA when REG_EN in

DAC.CONTROL is set returns current value updates current value

0 no DAC VDATA

This is driven to DAC VDATA when REG_EN in

DAC.CONTROL is set returns current value updates current value

Type

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Register descriptions 109

3.3.4 DENC_DAC_IF.TIMING

DENC_DAC_IF.TIMING

is the DAC timing register.

DENC_DAC_IF.TIMING

0x800

Field

VSG_DENC

_TIMING

Bits Size Volatile

[0:3] 4 operation read write hard reset

Synopsis Type

No Minimum cycles between falling edges of NOTCS signal

Determines the minimum number of cycles allowed between falling edges of the NOTCS signal to the DENC

The DENC documentation specifies 80 ns, which is more than 8.9 clock cycles at 111 MHz.

0000: Reserved

0001: 5 cycles delay

0010: 6 cycles delay

0011: 7 cycles delay

0100: 8 cycles delay

0101: 9 cycles delay

0110: 10 cycles delay

0111: 11 cycles delay

1000: 12 cycles delay

1001: 13 cycles delay

1010: 14 cycles delay

1011: 15 cycles delay

1100: 16 cycles delay

1101: 17 cycles delay

1110: 18 cycles delay

1111: 19 cycles delay

Returns current value

Updates current value

0110

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110

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Register descriptions

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Digital encoder

(DENC)

4.1 Overview

The digital encoder (DENC) is a high performance PAL/SECAM/NTSC digital encoder. It converts a 4:2:2 or 4:4:4 digital video stream into a standard analog baseband PAL/SECAM/NTSC signal and into RGB and YPrPb (also known as YUV) analog components.

It can handle interlaced mode (in all standards) and non-interlaced mode in PAL and NTSC. It can perform closed-captions, CGMS, WSS, VPS and teletext encoding and allows Macrovision



7.01/6.1 copy protection. Six analog output pins are available, on which it is possible to output either S-VHS(Y/C)+ CVBS+ RGB or

S-VHS(Y/C)+ CVBS+ Pr+ Y+ Pb or Y1+ C1+ CVBS1+ C2+ Y2+ CVBS2.

The encoder can operate in master mode or in one of several slave modes, where it locks onto incoming synchronous signals. An autotest mode is also provided.

The main functions are controlled using an 8-bit register interface with the CPU.

The registers are described at the end of this chapter.

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112 Features

4.2 Features

• NTSC-M, PAL-BDGHI, N, M, SECAM plus NTSC-4.43 encoding

• 6 simultaneous analog outputs through 10-bit DACs:

S-VHS (Y/C) + CVBS + RGB,

Y1 + C + CVBS + Pr + Y2+ Pb,

Y1 + C1 + CVBS1+ C2 + Y2 + CVBS2

• Macrovision

7.01/6.1 copy protection process in NTSC, PAL and SECAM

• closed captioning, CGMS, WSS, VPS encoding and teletext encoding with included sequencer and shaping

• dual mode ITU-R(CCIR)601/square pixel encoding in PAL and NTSC (except in

SECAM)

• digital line and frame sync input/output (ODDEV/ VSYNC ), programmable polarity and relative position

• digital line or frame sync extraction from ITU-R/CCIR656 / D1 data

• master operation mode, plus 6 slave modes

• programmable access via parallel port

• 4:4:4 input can be encoded on both RGB(YPrPb) and CVBS(S-VHS) outputs

(programmable)

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Address map 113

Register name

DEN_CFG0

DEN_CFG1

DEN_CFG2

DEN_CFG3

DEN_CFG4

DEN_CFG5

DEN_CFG6

DEN_CFG7

DEN_CFG8

DEN_STA

DEN_IDFS[1:3]

4.3 Address map

DEN_PDFS[1:2]

DEN_WSS[1:2]

DEN_DAC13

Description

Configuration register 0, see

DEN_CFG0 on page 158

Configuration register 1, see

DEN_CFG1 on page 159

Configuration register 2, see

DEN_CFG2 on page 161

Configuration register 3, see

DEN_CFG3 on page 163

Configuration register 4, see

DEN_CFG4 on page 165

Configuration register 5, see

DEN_CFG5 on page 166

Configuration register 6, see

DEN_CFG6 on page 167

Configuration register 7, see

DEN_CFG7 on page 168

Configuration register 8, see

DEN_CFG8 on page 170

Status, see

DEN_STA on page 172

Increment for digital frequency synthesizer, see DEN_IDFS[1:3] on page 174

Static phase offset for digital frequency synthesizer, see

DEN_PDFS[1:2] on page 176

WSS data registers, see

DEN_WSS[1:2] on page 178

DAC1 and DAC3 multiplying factors, see

DEN_DAC13 on page 179

Table 7: Address map

Type Address offset

RW 0x000

Access size

0x008

0x010

0x018

0x020

0x028

0x030

0x038

0x040

0x048

0x050, 0x058,

0x060

0x068, 0x070

0x078, 0x080

0x088

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114 Address map

Register name

DEN_DAC45

DEN_DAC6C

Reserved

DEN_CID

DEN_VPS[1:6]

DEN_CGMS[1:3]

DEN_TTX[1:5]

DEN_CCF1

DEN_CCF2

DEN_CLF1

DEN_CLF2

Reserved

DEN_REG_64

Description Type Address offset

RW 0x090

Access size

32 DAC4 and DAC5 multiplying factors, see

DEN_DAC45 on page 180

DAC6 and C multiplying factors, see

DEN_DAC6C on page 181

RW 0x098 32

0x0A0, 0x0A8,

0x0B0, 0x0B8

0x0C0

32 DENC version identification number, see

DEN_CID on page 183

VPS data registers, see

DEN_VPS1 on page 183

RW 32

CGMS data registers (20 bits only), see

DEN_CGMS[1:3] on page 184

Teletext block definition, see

DEN_TTX[1:5] on page 185

0x0C8, 0x0D0,

0x0D8, 0x0E0,

0x0E8, 0x0F0

0x0F8, 0x100,

0x108

0x110, 0x118,

0x120, 0x128,

0x130

0x138, 0x140

32 Closed caption characters extended data for field 1, see DEN_CCF1 on page 187

Closed caption characters extended data for field 2, see

DEN_CCF2 on page 188

Closed caption extended data line insertion for field 1, see

DEN_CLF1 on page 189

Closed caption extended data line insertion for field 2, see

DEN_CLF2 on page 190

0x148, 0x150

0x158

0x160

0x168 to 0x1F8 -

0x200 32 Teletext configuration, see

DEN_REG_64 on page 191

Table 7: Address map

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Address map 115

Register name

DEN_REG_65

Reserved

DEN_REG_69

DEN_REG_70

DEN_REG_71

DEN_CFCOEF[0:8]

DEN_CFG9

DEN_LFCOEF[0:9]

Description

DAC2 multiplying factors, teletext mask and brightness, contrast and saturation control, see

DEN_REG_65 on page 192

Type Address offset

RW 0x208

Access size

0x210 to 0x220 -

0x228 32 Brightness, see

DEN_REG_69 on page 193

Contrast, see

DEN_REG_70 on page 194

Saturation, see

DEN_REG_71 on page 195

Chroma filter coefficient, see

DEN_CFCOEF[0:8] on page 196

0x230

0x238

32 0x240, 0x248,

0x250, 0x258,

0x260, 0x268,

0x270, 0x278,

0x280

0x288 32 Chroma delay and luma filter control, see

DEN_LFCOEF[0:9] on page 201

Luma coefficient, see

RW 0x290, 0x298,

0x2A0, 0x2A8,

0x2B0, 0x2B8,

0x2C0, 0x2C8,

0x2D0, 0x2D8

Table 7: Address map

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116 Video timing

4.4 Video timing

The burst sequences are internally generated, subcarrier generation being performed numerically with CKREF, the principal DENC clock, as reference.

4-frame bursts are generated for PAL or 2-frame bursts for NTSC. Rise and fall times of synchronization tips and burst envelope are internally controlled according to the relevant ITU-R and SMPTE recommendations. The 6-frame subcarrier phase sequence is generated in SECAM (see

Section 4.10: Subcarrier insertion (SECAM) on page 137 ).

Figure 27 , Figure 28 ,

Figure 29 , Figure 30

Figure 31 and Figure 32 depict typical

vertical blanking interval (VBI) waveforms.

It is possible to encode incoming YCrCb data on those lines of the VBI that do not bear line synchronization, pre-equalization or post-equalization pulses (see Figures

Figure 27 , Figure 28

Figure 29 , Figure 30

and

Figure 31 ). This mode of operation is

referred to as partial blanking and is the default set-up. It allows the encoded waveform to keep any VBI data present in digitized form in the incoming YCrCb stream (for example supplementary closed-caption lines or StarSight data). In

SECAM mode, only Y data are encoded, Cr and Cb are ignored. Alternatively, the complete VBI may be fully blanked, so no incoming YCrCb data is encoded on these lines. Full or partial blanking is set by register bit DEN_CFG1.BLKLI

For 525/60 systems, with the SMPTE line numbering convention:

• complete VBI consists of lines one to nineteen and the second half of lines 263 to

282,

• partial VBI consists of lines one to nine and the second half of lines 263 to 272,

• line 282 is either fully blanked or fully active.

For 625/50 systems, with the CCIR line numbering convention:

• complete VBI consists of the second half of lines 623 to 22 and lines 311 to 335,

• partial VBI consists of the second half of lines 623 to 5 and lines 311 to 318,

• line 23 is always fully active.

In an ITU-R656-compliant digital TV line, the active portion of the digital line is the portion included between the start of active video (SAV) and end of active video

(EAV) words. However, this digital active line starts somewhat earlier and may end slightly later than the active line usually defined by analog standards.

The DENC allows two approaches.

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Video timing 117

• Encode the full digital line (720 pixels / 1440 clock cycles). In this case, the output waveform will reflect the full YCrCb stream included between SAV and

EAV.

• Drop some YCrCb samples at the extremities of the digital line so that the encoded analog line fits within the analog ITU-R/SMPTE specifications.

In all cases, the transitions between horizontal blanking and active video are shaped to avoid too steep edges within the active video.

Figure 33

gives typical timings concerning the horizontal blanking interval and the active video interval.

The burst envelope shown indicates the location from which the first subcarrier positive zero crossing is sought (with respect to the 0

H always starts with a positive zero crossing.

reference). The normal burst

NTSC, PAL M

PAL B, G, H, I, N

SECAM

128T

137T

146T (PAL M)

128T

151T (145T in SECAM)

1716T

1728T

1440T

Digital active line

1440T

Digital active line

Square pixel

525 / 60 system

115T

131T

1560T

1280T

Digital active line

Square pixel

625 / 50 system

139T

1536T

Digital active line

1888T

169T

T = clock period

PAL, NTSC and SECAM: 37.037 ns

Square pixel PAL: 33.898 ns

Square pixel NTSC: 40.75 ns

Figure 25: Input data format (ITU-R656 /D1 4:2:2)

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Video timing

The diagrams in

Figure 26 are valid when the contents of the delay and

synchro-delay register fields are set to the default values.

If on-the-fly format changing is required, clock switching must be synchronized onto the start of frame as shown in the waveforms in the diagram. Internally, the

DEN_CFG7.SQPIX

and DEN_CFG2.NINTRL

bits update is taken into account on the beginning of a new frame.

Master mode

ODDEVEN

(output)

CKREF

HSYNC

(output)

Field2

Slave mode by ODDEVEN and HSYNC

ODDEVEN

(input)

HSYNC

(input)

CKREF

Field1

Slave mode by ODDEVEN only

ODDEVEN

(input)

CKREF

Field1

Clock period change if square pixel mode switch

Update of SQPIX and NINTRL bits

Clock period change if square pixel mode switch

Update of SQPIX and NINTRL bits

Clock period change if square pixel mode switch

Update of SQPIX and NINTRL bits

Figure 26: Square pixel and/or non-interlaced mode switch

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Video timing 119

A B

308 309 310 311 312 313 314

Partial VBI1

315

Full VBI1

316 317 318 319

320

621 622 623 624 625 1 2 3

Partial VBI2

Full VBI2

4 5 6

7 22 23

308 309 310 311 312 313 314

III

315 316 317 318

317

335 336

621 622 623 624 625 1

III

I, II, III, IV :

A :

B :

C :

Frame synchronization reference

1 st and 5 th , 2 nd and 6 th , 3 rd and 7 th , 4 th and 8 th fields

Burst phase : nominal value +135°

Burst phase : nominal value -135°

Burst suppression internal

3 4 5 6 7 8

Figure 27: PAL-BDGHI, PAL-N typical VBI waveform, interlaced mode (ITU-R625 line numbering)

Full VBI

Partial VBI

A B

308 309

Burst phase toggles every line

310 311 312 1 2 3 4 5 6 7 8 22

Figure 28: PAL-BDGHI, PAL-N typical VBI waveform, non-interlaced mode (CCIR-like line numbering)

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120 Video timing

1 2 3 4

Partial VBI1

5 6

Full VBI1

7 8 9 10

262 263 264

265 266

Partial VBI2

267 268 269

Full VBI2

270 271

0.5H

272 273

0.5H

525 1 2 3 4 5 6 7

VBI3

18 19

282

18 19

263 264 265 266 267 268 269

VBI4

270 271 272 273 282

Figure 29: NTSC-M typical VBI waveforms, interlaced mode (SMPTE-525 line numbering)

262 1

2 3 4

Partial VBI

5 6 7

Full VBI

8 9 10 18 19

H H H 0.5H

Figure 30: NTSC-M typical VBI waveforms, non-interlaced mode (SMPTE-like line numbering)

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Video timing 121

F' F F' F

Partial VBI1

Full VBI1

519

520

521

522 523 524 525 1 2

Partial VBI2

Full VBI2

4 5 6

A B

7 8

16 17

257

258

259 260 261 262 263 264 265

III

266 267 268 269 270

271 279

280

519

520

521 522 523 524 525 1 2

3 4 5 6 7

257 258 259 260 261 262 263 264

III

265 266 267 268 269 270 271 272

I, II, III, IV :

A :

B :

C :

Frame synchronization reference

1 st and 5 th , 2 nd and 6 th , 3 rd and 7 th , 4 th and 8 th fields

Burst phase : nominal value +135°

Burst phase : nominal value -135°

Burst suppression internal

Figure 31: PAL-M typical VBI waveforms, interlaced mode (ITU-R/CCIR-525 line numbering)

Full VBI

256 257

Burst phase toggles every line

258 259 260 261 262 1

Partial VBI

2 3 4 5 6 7 8

A B

9 10 16 17

Figure 32: PAL-M typical VBI waveforms, non-interlaced mode (ITU-R/CCIR-like line numbering)

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122 Video timing

Horizontal blanking interval d

Active video b1 (bit aline = 0)

0H b2 (bit aline = 1) a

Full digital line encoding

(720 pixels - 1440 T)

‘Analog’ line encoding c1 (bit aline = 0) c2 (bit aline = 1)

Figure 33: Horizontal blanking interval and active video timings b1 b2 c1 c2 d a

NTSC-M

5.38

µ s (even lines)

5.52

µ s (odd lines)

1.56

µ s

1.56

µ s

8.8

µ s

9.41

µ s

PAL-BDGHI

5.54

5.66

1.3

µ s s (A-type) s (B-type)

1.52

µ s

9.6

µ s

10.48

µ s

9 cycles of 3.58MHz

10 cycles of

4.43MHz

PAL-N

5.54

µ s (A-type)

5.66

µ s (B-type)

1.3

µ s

1.52

µ s

9.6

µ s

10.48

µ s

9 cycles of

3.58MHz

PAL-M

5.73

µ s (A-type)

5.87

µ s (B-type)

1.56

µ s

1.56

µ s

8.8

µ s

9.41

µ s

9 cycles of

3.58MHz

SECAM

5.60

µ s

1.0

µ s

1.52

µ s

9.9

µ s

10.48

µ s

Table 8: Typical timing values from

Figure 32

A. These are typical values, actual values will depend of the static offset programmed for subcarrier generation.

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Reset procedure 123

4.5 Reset procedure

A hardware reset sets the DENC in HSYNC and ODDEVEN (line-based sync) slave mode. NTSC-M, interlaced ITU-R601 encoding, closed-captioning, WSS, VPS, teletext and CGMS encoding are all disabled.

The configuration can then be customized by writing into the appropriate registers.

A few registers are never reset, their contents are unknown until the first loading

(see

Section 4.22: Register descriptions on page 158 ).

It is also possible to perform a software reset by setting the seventh bit in the

DEN_CFG6 register. The device responds in a similar way as after a hardware reset except that the configuration registers and a few other registers are not altered.

4.6 Slave modes

4.6.1 Introduction

The following slave modes are available:

• ODDEVEN (VSYNC)+HSYNC based (line-based sync),

• ODDEVEN (VSYNC) only based (frame-based sync),

• sync-in-data based (line locked or frame locked).

ODDEVEN refers to an ODDEVEN field flag, also known as BOTTOMTOP .

HSYNC is a line sync signal and VSYNC is a vertical synchronous signal. Their waveforms are depicted in

Figure 34 . The polarities of

HSYNC and ODDEVEN (VSYNC) are independently programmable in all slave modes. In all slave modes, ODDEVEN

(VSYNC) and HSYNC signals must be related to CKREF , the principal DENC clock.

In other words, there is no genlocking performed by the DENC.

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124 Slave modes

4.6.2 Line-based synchronization

ODDEVEN+HSYNC based synchronization

Synchronization is performed on a line-by-line basis by locking onto incoming

ODDEVEN and HSYNC signals. Refer to

Figure 34 for waveforms and timings. The

polarities of the active edges of HSYNC and ODDEVEN are programmable and independent. The first active edge of ODDEVEN initializes the internal line counter but encoding of the first line does not start until an HSYNC active edge is detected

(at the earliest, an HSYNC transition may be at the same time as ODDEVEN ). At that point, the internal sample counter is initialized and encoding of the first line starts. Then, encoding of each subsequent line is individually triggered by HSYNC active edges. The phase relationship between HSYNC and the incoming YCrCb data is normally such that the first clock rising edge following the HSYNC active edge samples Cb (that is a blue chroma sample within the YCrCb stream). It is however possible to internally delay the incoming synchronous signals ( HSYNC and

ODDEVEN) by up to three clock cycles to cope with different data/sync phases, using configuration bits DEN_CFG4.SYNCIN_AD

. The DENC is thus fully slaved to the HSYNC signal, which means that lines may contain more or less samples than usual.

• If the digital line is shorter than its nominal value, the sample counter is re-initialized when the early HSYNC arrives and all internal synchronization signals are re-initialized.

• If the digital line is longer than its nominal value, the sample counter is stopped when it reaches its nominal end-of-line value and waits for the late HSYNC before re-initializing.

Figure 34 is valid when bits

DEN_CFG4.SYNCIN_AD[1:0] are set to the default.

CKREF

ODDEVEN (in)

HSYNC (in)

Active edge (programmable polarity)

YCrCb Cb Y Cr Y'

Figure 34: HSYNC + ODDEVEN based slave mode synchronous signals

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Slave modes 125

HSYNC+VSYNC based synchronization

Synchronization is performed on a line-by-line basis by locking onto incoming

VSYNC and HSYNC signals. Refer to

Figure 36 for waveforms and timings. The

polarities of HSYNC and VSYNC are programmable and independent.

The incoming VSYNC signal is immediately transformed into a waveform identical to the odd/even waveform of an ODDEVEN signal, therefore, the behavior with this synchronization is identical to that described above for ODDEVEN + HSYNC based synchronization. Again, the phase relationship between HSYNC and the incoming

YCrCb data is normally such that the first clock rising edge following the HSYNC active edge samples Cb (that is a blue chroma sample within the YCrCb stream). It is however possible to internally delay the incoming synchronous signals

( HSYNC + VSYNC ) by up to three clock cycles to cope with different data or synchronous phasing, using configuration bits DEN_CFG4.SYNCIN_AD

4.6.3 Frame-based synchronization

Genlocking using external sync extraction

The genlock slave mode is used when the OSD (generated externally to the DENC and output via RGB outputs) is mixed with analog video from which the vertical and horizontal synchronization signals are extracted by ROHM’s BA7046.

A software-based control loop locks the 27 MHz system clock to the analog video signal. The vertical synchronous signal from the ROHM sync extractor is connected to a capture port on the mother device (for example STi55xx) and generates an equivalent of the programmable clock reference (PCR) for the analog signal. The

ST40 controls an external VCXO through a PCM output port.

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126 Slave modes

Voltage controlled oscillator

27 MHz mother device

(e.g. STi55xx)

PWM

HSYNC (internal)

To the display

Time-base generator

DENC

Genlock module

ODDEVEN

Capture port

Analog video

SYNC extractor

(ROHM)

CVBS

OSD active

(fast switch)

CVBS

Figure 35: Genlock system using a SCART

VDSYNC and HDSYNC signals are provided by the external ROHM sync extractor

(BA7046). The DENC regenerates the signal ODDEVEN (the device internal vertical synchronization signal) from these inputs by locking onto VDSYNC with the internal clock.

HSYNC is generated internally by the sample counter and is not locked to HDSYNC . These HSYNC and ODDEVEN signals are then used inside the

DENC and are also output to drive display and video parts of the device. The DENC behaves in the same way as for ODDEVEN-only based synchronization, see

ODDEVEN-only based synchronization on page 127 . Register

DEN_CFG0 should be programmed as for ODDEVEN -only based synchronization.

The polarities of HSYNC and ODDEVEN are programmable and independent.

VDSYNC and HDSYNC are both falling edge active.

The DENC analog RGB output is delayed by one line vertically and by 25 pixels horizontally, compared to the analog video source. This must be taken into account for OSD, YDO and XDO programming. Refer to register DEN_CFG7 for genlock mode programming.

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ODDEVEN-only based synchronization

Synchronization is performed on a frame-by-frame basis by locking onto an incoming ODDEVEN signal. A line sync signal is derived internally and is also issued to the outside as HSYNC . Refer to

Figure 37

for waveforms and timings. The phase relationship between ODDEVEN and the incoming YCrCb data is normally such that the first clock rising edge following the ODDEVEN active edge samples Cb

(that is a blue chroma sample within the YCrCb stream). It is however possible to internally delay the incoming ODDEVEN signal by up to three clock cycles to cope with different data/sync phasing, using configuration bits DEN_CFG4.SYNCIN_AD

Figure 36 is valid when bits

SYNCIN_AD[1:0] are set to the default.

CKREF

VSYNC (in)

Active edge (programmable polarity)

HSYNC (in)

YCrCb Cb Y Cr Y' Cb

Figure 36: HSYNC and VSYNC based slave mode synchronous signals

The active edges of HSYNC and VSYNC should normally be simultaneous. It is permissible that HSYNC transitions before VSYNC , but VSYNC must not transition before HSYNC .

Figure 37 is valid when bits

SYNCIN_AD[1:0] are set to the default.

CKREF

ODDEVEN (in)

YCrCb Cb Y Cr

Figure 37: ODDEVEN-based slave mode synchronous signals

Y’

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The first active edge of ODDEVEN triggers generation of the analog synchronous signals and encoding of the incoming video data. Frames being supposed to be of constant duration, the next ODDEVEN active transition is expected at a precise time after the last ODDEVEN detected.

So, once an active ODDEVEN edge has been detected, checks that the following

ODDEVEN are present at the expected instants are performed.

Encoding and analog sync generation carry on unless three successive fails of these checks occur.

In that case, three behaviors are possible, according to the configuration programmed in registers DEN_CFG[1:2] .

• If FREERUN is enabled, the DENC carries on outputting the digital line sync

HSYNC and generating analog video just as though the expected ODDEVEN edge had been present. However, it will re-synchronize onto the next ODDEVEN active edge detected, whatever its location.

• If FREERUN is disabled but bit SYNCOK is set in the configuration registers, the

DENC sets the active portion of the TV line to black level but carries on outputting the analog sync tips (on Ys and CVBS) and the digital line sync signal

HSYNC . When programmed, Macrovision

pseudosynchronous pulses and

AGC pulses are also present in the analog sync waveform.

• If FREERUN is disabled and bit SYNCOK is not set, all analog video is at black level and neither analog sync tips nor digital line sync are output.

This mode is a frame-based sync mode, as opposed to a field-based sync mode. This means that only one type of edge (rising or falling, according to programming) is of interest to the DENC. The other one is ignored.

VSYNC-only based synchronization

Synchronization is performed on a frame-by-frame basis by locking onto an incoming VSYNC signal.

An auxiliary line sync signal HSYNC must also be fed to the DENC, which uses it to reconstruct from VSYNC and HSYNC information an internal odd/even waveform identical to that of an ODDEVEN signal. Therefore, the behavior with this synchronization is identical to that described above for ODDEVEN -only based synchronization (except that nothing is output on the HSYNC pin since it is an input port in this mode).

Note that HSYNC is an input but has no other use than allowing the DENC to decide whether an incoming VSYNC pulse flags an odd or an even field. In other

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The phase relationship between VSYNC and the incoming YCrCb data is normally such that the first clock rising edge following the VSYNC active edge samples Cb

(that is a blue chroma sample within the YCrCb stream). It is however possible to internally delay the incoming synchronous signals ( VSYNC and HSYNC ) by up to three clock cycles to cope with different data/sync phasing, using configuration bits

DEN_CFG4.SYNCIN_AD

CKREF

YCrCb

FF 00

EAV

ODDEV

(out)

HSYNC

(out)

B6 Cb Y

46TCLKREF

1TCLKREF

HSYNC duration = 128 TCLKREF

Figure 38: Data-based (EAV) slave mode synchronous signals

4.6.4 Sync-in-data based synchronization

End-of-frame word-based synchronization

Synchronization is performed by extracting the 1 to 0 transitions of the end of frame flag (F flag) from the end of active video (EAV) sequence embedded within

ITU-R656/D1 compliant digital video streams. Both a frame sync signal and a line sync signal are derived and are made available externally as ODDEVEN and

HSYNC . Refer to

Figure 38 for waveforms and timings.

The first successful detection of the F flag triggers generation of the analog synchronous signals and encoding of the incoming video data. Because frames are of constant duration, the next EAV word containing the F flag is expected at a precise time after the latest detection.

So, once an active F flag has been detected, checks that the following flags are present at the expected times within the incoming video stream are performed.

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Slave modes

Encoding and analog sync generation carry on unless there are three successive fails of these checks. Then, depending on the programmed configuration, one of the following three events occurs:

• If DEN_CONF0.FREE-RUN is enabled, the DENC carries on generating the digital frame and line syncs (ODDEV and HSYNC ) and generating analog video just as though the expected F flag were present. However, it will re-synchronize onto the next F flag detected within the incoming ITU-R656/D1 video stream.

• If FREE-RUN is disabled but the bit DEN_CONF0.SYNCOK

is set in the configuration registers, the DENC sets the active portion of the TV line to black level but carries on outputting the analog sync tips (on Ys and CVBS) and the digital frame and line sync signals ODDEVEN and HSYNC . (When programmed,

Macrovision

pseudosynchronous pulses and AGC pulses are also present in the analog sync waveform).

• If FREE-RUN is disabled and the bit SYNCOK is not set, all analog video is at black level and neither analog sync tips nor digital frame/line sync are output.

The SAV and EAV words are Hamming-decoded.

After detection of two successive errors, a bit is set in the status register to inform the microcontroller of the poor transmission quality.

End-of-line word-based synchronization

Synchronization is performed by extracting the F and H flags from the start of active video (SAV) and end of active video (EAV) words embedded within ITU-R656/

D1 compliant digital video streams. A line sync signal and a frame sync signal are derived from these flags and are issued to the outside on the HSYNC and ODDEVEN /

VSYNC pins in output mode. These signals are also used by the DENC, which treats them as incoming ODDEVEN and HSYNC signals in HSYNC and ODDEVEN based synchronization.

Autotest mode

An autotest mode is available, which causes the DENC to produce a color bar pattern, in the appropriate standard, independently from the video input.

The autotest mode is started by setting the 3-bit field SYNC in the register

DEN_CFG0 to seven. As this mode sets the DENC in master mode, VSYNC ,

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ODDEVEN and HSYNC signals are in output mode. In

Table 9 , the decimal values of

Y, Cr and Cb are shown corresponding to the autotest color bar.

Black

Blue

Red

Magenta

Green

Cyan

Yellow

White

112

136

160

236

128

116

212

200

140

128

Table 9: Autotest colors

156

128

212

100

184

The corresponding decimal output values just before the DACs are shown in

Figure 39 and

Figure 40

. Both figures show the static values corresponding to the input values in

Table 9 .

800

Blank level 240

Black

Sync level

608

546

486

414

362

290

240

Black

Figure 39: Luminance output levels in autotest for NTSC without set-up

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816

Blank level 256

Black

Sync level

624

562

502

430

378

306

256

Black

Figure 40: Luminance output levels in autotest for PAL (BGHI) and SECAM

4.7 Input demultiplexor

The incoming YCrCb data, as well as Y4 and CrCb in 4:4:4 mode, is demultiplexed into a blue-difference chroma information stream, a red-difference chroma information stream and a luma information stream. Incoming data bits are treated as blue, red or luma samples according to their relative position with respect to the synchronous signals in use and the contents of configuration bits

DEN_CFG4.SYNCIN_AD

(slave modes) or DEN_CFG4.SYNCOUT_AD

(master mode). Brightness, saturation and contrast are then performed on demultiplexed data, refer to registers DEN_REG_69 , DEN_REG_70 and DEN_REG_71 .

The ITU-R601 recommendation defines the black luma level as Y = 16 and the maximum white luma level as Y = 235. Similarly, it defines 225 quantification levels for the color difference components (Cr, Cb), centered around 128. After the saturation, brightness and contrast stage, the incoming YCrCB samples can be saturated in the input multiplexer with the following rules:

• for Cr or Cb samples:

Cr,Cb > 240 => Cr,Cb saturated at 240,

Cr,Cb < 16 => Cr,Cb saturated at 16,

• for Y samples:

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Y > 235 => Y saturated at 235,

Y < 16 => Y saturated at 16.

Using the input multiplexor ensures there are no overflow errors in the codes driving the DACs. Overflow errors occur if erroneous or unrealistic YCrCb samples are input to the encoder. Usually this is avoided by heavily saturating the composite video codes before analog to digital conversion, but the risk is that a distorted output waveform may be generated.

However, in some applications, it may be desirable to let extreme YCrCb codes pass through the demultiplexor. This is controlled using bit MAXDYN in register

DEN_CFG6 . In this case, only codes 0x00 and 0xFF are overridden. If such codes are found in the active video samples, they are forced to 0x01 and 0xFE.

YCrCb codes are not overridden for the EAV/SAV decoder.

4.8 Subcarrier generation

A direct digital frequency synthesizer (DDFS) generates the required color subcarrier frequency using a 24-bit phase accumulator. This oscillator feeds a quadrature modulator which modulates the base-band chrominance components.

The subcarrier frequency is obtained from the following equation:

Fsc = ([ increment_word ] / 2

) x CKREF where increment _word is a 24-bit value.

Hard-wired increment _word values are available for each standard and can be automatically selected. Alternatively (according to bit SELRST_INC in DEN_CFG5 ), the frequency can be fully customized by programming other values into a dedicated increment word register, DEN_IDFS . This allows, for instance, the encoding of

NTSC-4.43 or PAL-M-4.43.

This is done with the following procedure.

1 In the DEN_IDFS register, program the required increment.

2 Set bit DEN_CFG5.SELRST_INC

to 1.

3 Perform a software reset using register DEN_CFG6 . This sets all bits in all

DENC registers except DEN_CFG[N] to their default value.

Alternatively, set DEN_CFG8.PH_RST_MODE[1:0] to 01 so that the frequency and phase update is done on the beginning of the next video line.

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Subcarrier generation

Note that if a standard change occurs after the software reset, the increment value is automatically re-initialized with the hard wired or loaded value, according to bit

SELRST .

The reset phase of the color subcarrier can also be software-controlled by register

DEN_PDFS .

The subcarrier phase can be periodically reset to its nominal value to compensate for any drift introduced by the finite accuracy of the calculations. In PAL and NTSC subcarrier phase adjustment can be performed every line, every eight fields, every four fields, or every two fields ( DEN_CFG2.VALRST[1:0] ). If SECAM is performed, the subcarrier phase is reset every line. When performing external genlocking, the reference frequency of the regenerated clock may slightly deviate depending on the line length measurement. To prevent this drift from corrupting the colors, the color frequency control line ( CFC pin) can be used to update the 24-bit increment of the

DDFS and keep the color subcarrier stable (see Figure 41 ). Note that if this feature is not used, the CFC pin must be grounded. The DENC can also detect phase reset information coming up to ten clock cycles after transmission of the CFC ’s LSB (see

DEN_CFG8.PH_RST_MODE[1:0] ). It can also automatically reset the phase after

CFC loading (see DEN_CFG8 description) .

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135

Figure 41: Color subcarrier frequency control (CFC) transmission format

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Burst insertion (PAL and NTSC)

4.9 Burst insertion (PAL and NTSC)

The color reference burst is inserted so as to always start with a positive zero crossing of the subcarrier sine wave. The first and last half-cycles have a reduced amplitude so that the burst envelope starts and ends smoothly.

The burst contains nine or ten sine cycles of 4.43361875 MHz or 3.579545 MHz

(depending on the standard programmed in the register DEN_CFG0 ) as follows:

• NTSC-M: 9 cycles of 3.579545 MHz,

• PAL-BDGHI: 10 cycles of 4.43361875 MHz,

• PAL-M: 9 cycles of 3.579545 MHz,

• PAL-N: 9 cycles of 3.579545 MHz.

The burst can be turned off so there is no burst insertion by setting

DEN_CFG2.BURSTEN

to 0.

Burst insertion is performed by always starting the burst with a positive-going zero crossing. This guarantees a smooth start and end of burst with a maximum of undistorted burst cycles and can only be beneficial to chroma decoders.

Burst insertion avoids an uncontrolled initial burst phase, and guarantees a start on a positive-going zero crossing so that two burst start locations are visible over successive lines, according to the line parity. This is normal and explained below.

In NTSC, in the horizontal sync the relation between subcarrier frequency and line length creates a 180 o subcarrier phase difference between lines according to the line parity. If the burst always starts with the same positive-going zero crossing phase, the burst is inserted at time X or at time X+T

NTSC

/2 after the horizontal sync tip according to the line parity, where T

NTSC

is the duration of one cycle of the NTSC burst.

With PAL, a similar rationale holds, and again there are two possible burst start locations. The subcarrier phase difference in the horizontal sync between lines is either 0 or 180 o

. Using the following series: A-A-B-B-A-A- and so on, where A denotes A-type bursts and B denotes B-type bursts A-type and B-type are 180 o out of phase with respect to the horizontal sync. So two locations are possible, one for

A-type, the other for B-type.

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137

This assumes that a periodic reset of the subcarrier is automatically performed (see bits DEN_CFG2.VALRST[1:0] ). Otherwise, over several frames, the start of burst drifts within an interval of half a subcarrier’s cycle. This is normal and means the burst is correctly locked to the colors encoded. The equivalent effect with a gated burst approach is that the start location is fixed but the start phase for the horizontal sync would be drifting.

4.10 Subcarrier insertion (SECAM)

The subcarrier frequency in SECAM mode depends on Cr and Cb values (frequency modulation). The color subcarrier frequency is 4.25 MHz for Cb = 128 on blue lines and 4.406249 MHz for Cr = 128 on red lines. Frequency clipping values are 3.9 MHz and 4.75625 MHz.

The insertion point of the non-modulated subcarrier is shown in

Figure 42

cvbs

400

350

300

250

200 5.6

µ s

150

100

2.1

2.11

2.12

2.13

2.14

2.15

x 10

Figure 42: SECAM color bar pattern (blue line)

In odd fields the phase of subcarrier follows the sequence 0, 0,

π,

0, 0,

π,

0, 0,

π, and so on. This compares to a sine wave starting at the same point -5.6

µ s after the horizontal sync pulse inverted on one line out of every three and also at each frame.

The sequence begins from line 1 or line 23 of the first field, see

DEN_CFG7.GEN_SECAM

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Luminance encoding

DEN_CFG7.INV_PHI_SECAM

allows the inversion of this sequence ( π , π , 0, π , π , 0 instead of 0, 0, π , 0, 0, π ), in odd fields. In even fields the sequence of subcarrier is always inverted compared to the odd field.

To enable SECAM mode, set DEN_CFG7.SECAM

(MSB) to 1 and then perform a soft-reset or loading of DEN_CFG0 .

4.11 Luminance encoding

The demultiplexed Y samples are band-limited and interpolated at CKREF clock rate. The resulting luminance signal is properly scaled before insertion of any closed-captions, CGMS, VPS, teletext or WSS data and synchronization pulses.

The interpolation filter compensates for the sin(x) / x attenuation inherent in digital to analog conversion and greatly simplifies the output stage filter. See

Figure 43

Figure 44 and

Figure 45

for characteristic curves.

In addition, the luminance that is added to the chrominance to create the composite

CVBS signal can be trap-filtered at 3.58 MHz (NTSC) or 4.43 MHz (PAL). This supports applications oriented towards low-end TV sets which are subject to cross-color if the digital source has a wide luminance bandwidth (for example some

DVD sources). Note that the trap filter does not affect the S-VHS luminance output nor the RGB outputs. If SECAM is performed, enable the trap filter with 4.43 MHz cut-off frequency on the luma part of the CVBS signal using the DEN_CFG3 bits

ENTRAP and TRAP_4.43

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A 7.5 IRE pedestal can be programmed if needed with all standards using registers

DEN_CFG1 and DEN_CFG7 . In particular this allows the encoding of Argentinian and non-Argentinian PAL-N, or Japanese NTSC, that is NTSC with no set-up.

-5

-10

-15

-20

-25

-30

-35

-40

1 2 3 4 5 6 7 8 9 10 11 12 13

Frequency (MHz)

Figure 43: Luma filtering including DAC attenuation

-5

-10

-15

-20

-25

-30

-35

-40

1 2 3 4 5 6 7 8 9 10 11 12 13

Frequency (MHz)

Figure 44: Luma filtering with 3.58 MHz trap, including DAC attenuation

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140 Chrominance encoding

-5

-10

-15

-20

-25

-30

-35

-40

1 2 3 4 5 6 7 8 9 10 11 12 13

Frequency (MHz)

Figure 45: Luma filtering with 4.43 MHz trap, including DAC attenuation

The luma channel has a nineteenth order filter with coefficients programmable by registers DEN_LFCOEF[0:9] . This filter is described in

Section 4.12: Chrominance encoding on page 140

selects either the register or the hard-wired values for the filter coefficients.

The luma processing as well as line and field timings in SECAM mode are identical to PAL BDGHI.

4.12 Chrominance encoding

U, V (PAL and NTSC) and Dr, Db (SECAM) chroma components are computed from demultiplexed Cb, Cr samples. Before modulating the subcarrier, these are band-limited and interpolated at CKREF clock rate. This processing eases the filtering following digital to analog conversion and allows more accurate encoding.

A set of four different filters is available in PAL and NTSC for chroma filtering to fit a wide variety of applications in the different standards and include filters recommended by ITU-R 624-4 and SMPTE170-M.

The available 3-dB bandwidths are 1.1, 1.3, 1.6 or 1.9 MHz. See

Figure 48

Figure 49 , Figure 50 ,

Figure 51 and Figure 52 for the various frequency responses

and register DEN_CFG1 for programming. The narrower bandwidths are useful against cross-luminance artifacts, the wider bandwidths allow higher chroma contents.

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Alternatively, a filter with programmable coefficients (see registers

DEN_CFCOEF[0:8] ) can be used. This is necessary for clocks having frequencies of

24.545454 and 29.5 MHz in square pixel mode, or when another frequency response for a specific application is needed. The order of chroma filter is seventeen with symmetric coefficients, and this works at the same frequency as CKREF, the default being 27 MHz.

If the 4:2:2 input format is used on CVBS and S-VHS outputs, then the first upsampling by 2 repeats the samples. For example a 6.75 to 13.5 MHz sampling frequency with 27 MHz CKREF, gives 10 20 30 at 6.75 MHz and 10 10 20 20 30 30 at

13.5 MHz clock frequency. This is equivalent to filtering by cos(

*f/(2*fck)), where fck is the CKREF clock frequency.

The second upsampling, 13.5 to 27 MHz with 27 MHz CKREF, is done by padding with zeros.

selects either the register or the hard-wired values for the filter coefficients.

In SECAM, 1.3 MHz low-pass and pre-emphasis filtering are performed on Dr and

Db chroma components, before the frequency modulation according to ITU-R

Rec624-4.

Refer to

Figure 46 for the frequency response of these filters. Bell filtering is

performed at the end of the frequency modulation stage.

The peak to peak amplitude of the modulated chrominance signal at the central frequency of 4279.7 kHz is 22.88% of the black-white interval (22.88 IRE).

The chrominance path can be delayed, in relation to the luma path, for S-VHS and

CVBS outputs. Register bit DEN_CFG3.DEL_EN

selects either the default delays or the programmable delay. The default delays are pre-programmed for the PAL,

SECAM and NTSC modes in 4:2:2 and 4:4:4 format on CVBS.

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Chrominance encoding

Refer to

Figure 47 for the frequency response of the bell filter with subcarrier

frequencies and clipping values.

-5

-10

-15

10-1

Frequency (MHz)

100

Figure 46: SECAM chroma filtering (pre-emphasis and 1.3 MHz low pass filtering)

Filtrage anti−cloche du SECAM (avec les DACs)

3.8

3.9

4 4.1

4.2

4.3

4.4

Frequence (MHz)

4.5

Frequency (MHz)

4.6

4.7

4.8

hi h f b i h i (B ll filt i

Figure 47: SECAM high-frequency subcarrier pre-emphasis (Bell filtering), including DAC attenuation

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-1

-2

-3

-4

-5 f-3=1.1

f-3=1.6

RGB f-3=1.3

f-3=1.9

-6

-7

-8

-9

0 0.5

1 1.5

2 2.5

3 3.5

Frequency (MHz)

Figure 48: Various chroma filters available and RGB filter

4.13 Composite video signal generation

The composite video signal is created by adding the luminance and the chrominance components. Luminance is usually added after trap filtering, but in PAL and NTSC trap filtering is optional, see register DEN_CFG3 . A saturation function is included in the adder to avoid overflow errors should extreme luminance levels be modulated with highly saturated colors. This does not occur with natural colors but may be generated by computers or graphics engines.

A color killing function is available, whereby the composite signal contains no chrominance and so replicates the trap-filtered luminance. This function does not suppress the chrominance on VHS and S-VHS outputs, but suppressing the S-VHS chrominance is possible using bit BKDAC[N] in DEN_CFG5 , where the chrominance signal is outputted on DAC[n].

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Composite video signal generation

-5

-10

-15

-20

-25

-30

-35

-40

0 2 4 6 8 10 12 14

Frequency (MHz)

Figure 49: 1.1 MHz chroma filter

-5

-10

-15

-20

-25

-30

-35

-40

0 2 4 6 8 10 12 14

Frequency (MHz)

Figure 50: 1.3 MHz chroma filter

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-5

-10

-15

-20

-25

-30

-35

-40

0 2 4 6 8 10 12 14

Frequency (MHz)

Figure 51: 1.6 MHz chroma filter

-5

-10

-15

-20

-25

-30

-35

-40

0 2 4 6 8 10 12 14

Frequency (MHz)

Figure 52: 1.9 MHz chroma filter

145

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4.14 RGB and UV encoding

After demultiplexing, the Cr and Cb samples feed a four times interpolation filter.

The resulting base-band chroma signal has a 2.45 MHz bandwidth ( Figure 53

) and is combined with the filtered luma component to generate R,G,B or U,V samples at

27 MHz.

If Y4 and CrCb inputs are used, the filtering identical to luma filtering (see

Figure 43 ) is performed on all components (Y4, Cr and Cb). In this case DAC5

output data encoded from Y4 input if YUV configuration is used (see DEN_CFG8 bits CONF_OUT1 and CONF_OUT0 ).

-5

-10

-15

-20

-25

-30

-35

-40

0 2 4 6 8 10 12 14

Frequency (MHz)

Figure 53: RGB: chroma filtering

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4.15 Closed captioning

Closed-captions (or data from an extended data service as defined by the closed-captions specification) can be encoded by the circuit. The closed caption data is delivered to the circuit through the register interface. Two dedicated pairs of bytes

(2 bytes per field), each pair preceded by a clock run-in and a start bit can be encoded and inserted on the luminance path on a selected TV line. The clock run-in and start code are generated by the DENC.

Closed-caption data registers are double-buffered so that loading can be performed anytime, even during line 21/284 or any other selected line.

User register DEN_CCF1 and DEN_CCF2 each contain the first and second byte to send (LSB first) after the start bit on the appropriate TV line, where DEN_CCF1 refers to field 1 and DEN_CCF2 to field 2. The TV line number where data is to be encoded is programmable using registers DEN_CLF1 and DEN_CLF2 . Lines that may be selected include those used by the StarSight data broadcast system.

Closed-caption data has priority over any CGMS signals programmed for the same line.

The internal clock run-in generator is based on a direct digital frequency synthesizer. The nominal instantaneous data rate is 503.496 kHz, that is 32 times the NTSC line rate). Data low corresponds nominally to 0 IRE, data high corresponds to 50 IRE at the DAC outputs.

When closed-captioning is on (bits CC1 and CC2 in DEN_CFG1 ), the CPU should load DEN_CCF1 or DEN_CCF2 once every frame at most, although there is some margin due to double-buffering. Two bits are set in the DEN_STA register in case there are attempts to load the closed-caption data registers too frequently. These can be used to regulate the loading rate.

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148 CGMS encoding

300

250

200

150

100

10µs

27.35µs

13.9µs

7 cycles of 504kHz

Transition

Time : 220ns

61µs t

Figure 54: Example of closed-caption waveform

The closed caption encoder considers that closed caption data has been loaded and is valid on completion of the write operation into DEN_CCF1 for field 1, or DEN_CCF2 for field 2. If closed caption encoding has been enabled and no new data bytes have been written into the closed caption data registers when the closed caption window starts on the appropriate TV line, then the circuit outputs two US-ASCII null characters with odd parity after the start bit.

4.16 CGMS encoding

CGMS stands for copy generation management system, is also known as VBID, and is described by standard CPX-1204 of EIAJ. CGMS data can be encoded by the digital encoder.

Three bytes, containing 20 significant bits, are delivered to the chip using the register interface. Two reference bits (1 then 0) are encoded first, followed by 20 bits of CGMS data. This includes a cyclic redundancy check sequence, which is not computed by the device but is supplied as part of the 20 data bits. The reference bits are generated locally by the DENC.

Figure 55

shows a typical CGMS waveform.

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CGMS encoding 149

300

250

200

150

100

11µs

Bit 1

48.7µs

Word 0

6 bits

Word 1 Word 2

4 bits 4 bits

CRCC

6 bits

Bit 20 t

Figure 55: Example of CGMS waveform

CGMS encoding is enabled by setting bit ENCGMS in register DEN_CFG3 . When enabled, the CGMS waveform is present once in each field, on lines 20 and 283, using SMPTE-525 line numbering.

The CGMS data register is double-buffered, which means that it can be loaded at any time, even during line 20/283, without any risk of corrupting any CGMS data being encoded. The CGMS encoder considers that new CGMS data has been loaded and is valid on completion of the write operation into register DEN_CGMS .

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150 WSS encoding

4.17 WSS encoding

The digital encoder allows wide screen signalling (WSS) in 625-line format, complying with the ETS 300 294 standard. Two bytes are delivered to the circuit through the register interface into two dedicated registers (see register DEN_WSS ).

WSS encoding is enabled using bit ENWSS in register DEN_CFG3 . When WSS encoding is enabled, a waveform is present on the first half of line 23 of each frame.

Data is preceded by a run-in sequence and a start code generated locally by the

DENC.

4.18 VPS encoding

VPS data encoding is defined by ETS 300 231 communication, June 1993 . VPS data can be encoded by the DENC on line 16 (CCIR) for 625-line PAL and SECAM television systems. The VPS data is delivered to the circuit using registers

DEN_VPS . The data transmission is preceded by a clock run-in and a start code generated by the DENC. The clock frequency is 5 MHz. This feature is enabled by setting the ENVPS bit of register DEN_CFG7 .

Figure 56 shows an example of VPS

waveform.

Run-In Start -Code Data

Figure 56: Example of VPS waveform

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Teletext encoding 151

4.19 Teletext encoding

The DENC can encode teletext according to the CCIR/ITU-R broadcast teletext system B specification (also known as world system teletext), and North American basic teletext specification (NABTS) EIA-516.

In DVB applications, teletext data is embedded within DVB streams as MPEG data packets. The transport layer processing IC (ST40) sorts incoming data packets and stores teletext packets in a buffer. It then passes them to the DENC on request.

Signal exchange

The DENC and the teletext buffer exchange two signals, teletext synchronization

(TTXS) going from the DENC to the teletext buffer and teletext data (TTXD) going from the teletext buffer to the DENC.

The TTXS signal is a request signal generated on selected lines. In response to this signal, the teletext buffer is expected to send teletext bits to the DENC for insertion of a teletext line into the analog video signal. The number of teletext bits sent depends on the teletext system being used. The teletext system is determined by register bit DEN_REG_64.

TTXT_ABCD .

360 bits are sent for teletext B, that is WST in PAL and SECAM, or 288 for teletext C, that is NABTS in NTSC.

The duration of the TTXS window corresponds to the number of bits being sent. See

Transmission protocol .

• For teletext B and 625 line systems, the TTXS window duration is 1402 reference clock periods (corresponding to 360 bits).

• For teletext C and 525 line systems (NABTS), the TTXS window duration is 1121 master clock periods.

Following the TTXS rising edge, the encoder expects data from the teletext buffer after a programmable number (two to nine) of 27 MHz master clock periods. Data is transmitted synchronously with the master clock at an average rate of

6.9375 Mbit/s according to the protocol described below. In order of transmission, it consists of sixteen clock run-in bits, eight framing code bits and one teletext packet of 336 or 228 bits, depending on the teletext system being used. If more than one packet of 336 or 228 bits are transmitted, these are ignored by the DENC. By default, register bit DEN_REG_65.

TTX_MASK_OFF masks the two bits of teletext framing code, allowing the code to be set by the DENC according to the selected teletext standard.

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Teletext encoding

Transmission protocol

To transmit the teletext data bits at an average rate of 6.9375 Mbit/s, which is about

1 / 3.89 times the master clock frequency, the following scheme is adopted:

The 360-bit packet is regarded as nine 37-bit sequences plus one 27-bit sequence.

In every sequence, the 10th, 19th, 28th and 37th bits are transmitted as a succession of three identical samples at 27 Msample/s. Each of the remaining teletext data bits is transmitted as a succession of four identical samples at 27

Msample/s.

Programming TTXS rising to first valid sample

The encoder expects the teletext buffer to clock-out the first teletext data sample on the (2 + n) th

rising edge of the master clock following the rising edge of TTXS.

Figure 57 depicts this graphically for n = 0.

CKREF

TTXS

TTXD

(TXDL[2:0] + 2) TCKREF

Not Valid Bit 1 Bit 2

Figure 57: TTXT rising to first valid sample delay for TXDEL[2:0] = 0

N is programmable from zero to seven by register bits DEN_TTX1.TTXDEL[2:0] . The value written in TXDEL[2:0] is two less than the overall delay in CKREF cycles, so a value of zero for TXDEL[2:0] corresponds to an overall delay of two cycles, and a value of seven corresponds to a delay of nine cycles.

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Teletext encoding 153

Programming teletext line selection

Five dedicated registers, DEN_TTX[1:5] , program teletext encoding in various lines in the vertical blanking interval (VBI) of each field. In this way, each line in VBI can be selected independently.

Full-page teletext encoding is set by register bit DEN_TTX1.FP_TTXT

. Teletext is encoded on lines 24 to 311 and 336 to 623, using ITU-R line numbering. This is in addition to the lines already programmed in the VBI. When full page teletext is performed, no video data is encoded and YCrCb, Y4 and CrCb input streams are ignored.

Teletext pulse shape

The shape and amplitude of a single teletext pulse is shown in

Figure 58 . Its relative

power spectral density is shown in

Figure 59

and

Figure 60

It is zero at frequencies above 5 MHz, as required by the world system teletext specification.

-100 -50

-144 ns

0 50 100

+144 ns

Figure 58: Shape and amplitude of a single teletext symbol

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0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0 1 2 3 4 5 6 7 8

Frequency (MHz)

Figure 59: Linear PSD scale

-40

-50

-60

-70

-10

-20

-30

-80

0 1 2 3 4 5 6 7 8

Frequency (MHz)

Normalized power spectral density (PSD) of a single teletext pulse

Figure 60: Logarithmic PSD scale

Teletext encoding

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Line skip and line insert capability 155

4.20 Line skip and line insert capability

This patented feature of the DENC offers the possibility to cut the cost of the application by suppressing the need for a VCXO.

Ideally, the master clock used on the application board and fed to the MPEG decoding IC would have exactly the same frequency as the clock used when the

MPEG data was encoded. Obviously this is not realistic. Up to now a solution commonly used was to dynamically adjust the clock on the board as close to the ideal clock as possible, with the help of time stamps embedded within the MPEG stream.

Such tracking often involves the use of a VCXO. When the MPEG data buffer fills to more than one threshold the clock frequency increases, when it empties to another threshold the clock frequency is lowered.

The DENC offers an alternative, cost-saving solution. By programming two bits in register DEN_CFG6 , the DENC is able to reduce or increase the length of some frames in a way that does not introduce visible artifacts, even if comb-filtering is used. These bits should be set according to the level of the MPEG data buffer.

Operation with the DENC as sync master is as shown below.

• If the MPEG data buffers fill, set bit JUMP to 1 and bit DEC_NINC to 1.

The DENC reduces the length of the current frame and bit JUMP resets to 0.

• If the MPEG data buffers empty, set bit JUMP to 1 and bit DEC_NINC to 0.

The DENC increases the length of the current frame and bit JUMP resets to 0.

These operations can be repeated until the MPEG data buffer is inside its fixed limits.

It is also possible to use line skip and line repeat in non-interlaced mode.

Line skip and line insert can be used in slave mode. The synchronous signals supplied to the DENC must be in accordance with the programmed frame lengths.

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CVBS, S-VHS, RGB and UV outputs

4.21 CVBS, S-VHS, RGB and UV outputs

Six out of eight video signals can be directed to six analog output pins through a

10-bit digital to analog converter operating at the reference clock frequency. The available combinations are:

• S-VHS (Y/C), CVBS and RGB,

• S-VHS (Y/C), CVBS, U, Y2 and V,

• Y1, C1, CVBS1, C2, Y2 and CVBS2.

These combinations are controlled by bits CONF_OUT1 and CONF_OUT0 in register

DEN_CFG8 , as shown in

Table 10.

CONF_OUT1 CONF_OUT0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6

1 x

CVBS

Table 10: Encoding of CONF_OUT

CVBS

Notes

Default

The register bits DEN_CFG2.SET4:4:4 and DEN_CFG9.SET444_CVBS

select the outputs CVBS/S-VHS or RGB/YUV for each of the two encoded input formats.

The C to Y peak to peak amplitude ratio can be modified in both CVBS and VHS (Y/

C) outputs using MULT_RGB_C .

For the 100/0/100/0 color bar pattern the default peak to peak amplitude of UV and

RGB outputs is set to 70% of Y or CVBS peak to peak amplitude. This can be modified using the multiplying factors in registers DEN_DAC45 and DEN_DAC6C .

If the DEN_CFG7[2] bit UV_LEV has the default value of 0, the U and V outputs have 0.7 V peak to peak amplitude when the 100/0/100/0 color bar pattern is input.

If UV_LEV is 1, the U and V outputs are those defined by ITU-R 624-4 for the PAL and NTSC standards (Vpp/Upp = 1.4). In that case the U peak to peak amplitude is

0.61 V, or 0.57 V if the DEN_CFG7 bit SETUPYUV is set, and the V peak to peak amplitude is 0.86 V, or 0.80 V if the register DEN_CFG7 bit SETUPYUV is set. In all these cases UV outputs can be multiplied by 0.75 to 1.22, the factor according to register bits DEN_DAC45.DAC4_MULT

and DEN_DAC6C.DAC6_MULT

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CVBS, S-VHS, RGB and UV outputs 157

A single external analog power supply pair is used for all DACs, but two independent pairs of current and voltage references are needed. An 11 Kbytes resistor must be connected between each I_REF and V_REF pin.

The internal current sources are independent from the positive supply, and the consumption of the DACs is constant whatever the codes converted.

Any unused DAC may be independently disabled by software, in which case its output is at neutral level (blanking for luma and composite outputs, no color for chroma output, black for RGB and UV outputs). For applications where a single

CVBS output is required, the RGB/CVBS and S-VHS/UV triple DAC should be disabled, pin I_REF_DAC_RGB should be tied to analog power supply and pin

V_REF_DAC_RGB should be left unconnected.

Due to the 3.3 V power supply used, the output swing of the DACs is about 1 Vp-p.

Therefore some external gain may be required, which, combined with the recommended output filtering stage, means active filtering. For this active filtering stage to be very simple, it is possible to invert the DAC outputs by programming a bit of DEN_CFG5 . Code N becomes code 1024-N, that is the resulting waveform undergoes a symmetry around the mid-swing code.

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158

4.22 Register descriptions

Register descriptions

DEN_CFG0 Configuration0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x000

10010010

Description

Bitfield

FREERUN

POLV

POLH

STD[1:0]

Description

Bit FREERUN is taken into account in ODDEV-only, VSYNC-only or F-based slave modes. It is irrelevant to other synchronization modes.

Synchro: active edge of ODDEV/VSYNC selection (when input)

0: Disabled

1: Enabled

Synchro: active edge of ODDEV/VSYNC selection (when input)

0: Falling edge of ODDEV flags start of field1 (odd field) or VSYNC is active low

1: Rising edge of ODDEV flags start of field1 (odd field) or VSYNC is active high

Synchro: active edge of HSYNC selection (when input) or polarity of HSYNC (when output)

0: HSYNC is a negative pulse (128 TCKREF wide) or falling edge is active

1: HSYNC is a positive pulse (128 TCKREF wide) or rising edge is active

Standard

0 0: PAL BDGHI

0 1: PAL N (see bit set-up)

1 0: NTSC M

A B

1 1: PAL M

A. The standard on hardware reset is NTSC; any standard modification automatically selects the right parameters for correct subcarrier generation.

B. If DEN_CFG7.SECAM is set, the STD1 and STD0 bits are not taken into account.

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DEN_CFG1 Configuration 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x008

01000100

Description

Bitfield Description

CC[2:1]

00:

01:

10:

11:

No closed caption/extended data encoding

Closed caption/extended data encoding enabled in field 1 (odd)

Closed caption/extended data encoding enabled in field 2 (even)

Closed caption/extended data encoding enabled in both fields

SETUP Pedestal enable

A Blanking level and black level are identical on all lines (ex: Arg. PAL-N, Japan

NTSC-M, PAL-BDGHI)

1: Black level is 7.5 IRE above blanking level on all lines outside VBI (ex: Paraguayan and Uruguayan PAL-N). In all cases, gain factor is adjusted to obtain the required chrominance levels.

COKI Color killer

A Color ON

1: Color suppressed on CVBS output signal (CVBS=YS) but color still present on C output

For color suppression on chroma DAC ‘C’, see register DEN_CFG5 .BKDAC2.

SYNCOK Synchronous signal availability (analog & digital) for input synchronization loss with free-run inactive freerun=0

A No synchro output signals

FLT[1:0] 00:

01:

Output synchros available on YS, CVBS and, when applicable, HSYNC (if output port), ODDEV (if output port),: i.e same behavior as free-run except that video outputs are blanked in the active portion of the line f -3dB =1.1MHz low def NTSC filter f -3dB =1.3MHz low def PAL filter

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160 Register descriptions

Bitfield

BLKLI

Description

10:

A f -3dB =1.6MHz high def. NTSC filter (ATSC compliant) & PAL M/N (ITU-R 624.4

compliant)

11: f -3dB =1.9MHz high def. PAL filter: Rec 624 - 4 for PAL BDG/I compliant

Vertical Blanking Interval selection for active video lines area.

(‘partial blanking’) Only the following lines inside the vertical interval are blanked:

NTSC-M: lines [1:9], [263(half):272] (525-SMPTE), PAL-M: lines [523:6],

[260(half):269] (525-CCIR) other PAL: lines [623(half):5], [311:318] (625-CCIR)

This mode preserves embedded VBI data within the incoming YCrCb, e.g. teletext

(lines [7:22] and [320:335]), Wide Screen signalling (full line 23), Video Programing

Service (line16), etc.).

(‘full blanking’) All lines inside VBI are blanked

NTSC-M: lines [1:19], [263(half):282] (525-SMPTE), PAL-M: lines [523:16],

[260(half):279] (525-CCIR) other PAL: lines [623(half):22], [311:335] (625-CCIR)

A. Default mode when DENC_NRST pin is active (low level)

B. BLKLI must be set to 0 when closed captions are to be encoded on the following lines: in the 525/60 system, before line 20 (SMPTE) or before line 283 (SMPTE), in 625/50 system, before line 23 (CCIR) or before line 336 (CCIR).

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Register descriptions 161

DEN_CFG2 Configuration 2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x010

00100000

Description

Bitfield Description

VALRST[1:0]

RSTOSC_BUF

SELRST

SET4:4:4

BURSTEN

00:

01:

Automatic reset of the oscillator every line

Automatic reset of the oscillator every 2 nd

field

10:

Automatic reset of the oscillator every 4 th

field

11:

Automatic reset of the oscillator every 8 th

field

Software phase reset of DDFS (Direct Digital Frequency Synthesizer) buffer

No reset

When a 0-to-1 transition occurs, either the hard-wired default phase value, or the value loaded in the DEN_PDFS1/2 register (according to bit SELRST), is put to phase buffer. This value is loaded into accumulator (phase of subcarrier) when bits PH_RST_OSC from DEN_CFG8 are programmed, or when the standard changes or soft reset occurs.

Selects reset values for Direct Digital Frequency Synthesizer

Hardware reset values for subcarrier oscillator phase (see register descriptions for values)

DEN_PDFS1/2

1: Loaded reset values selected (see contents of the DEN_PDFS1/2 registers)

Selects the 4:2:2 or 4:4:4 video input from the mixing unit

YCrCb (4:2:2) input:

The presence of OSD on the DENC output can be selected or deselected by

OSD block header field S.

YCrCb (4:4:4) input: In this mode OSD is always present on the DENC output.

Chrominance burst control

0: Burst is turned off on CVBS, chrominance output is not affected

Burst is enabled

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162 Register descriptions

Bitfield

ENRST

NINTRL

Description

Cyclic update of DDFS phase

No cyclic subcarrier phase reset

1: Cyclic subcarrier phase reset depending of valrst1 and valrst0 (see above)

Non-interlaced mode select

Interlaced mode (625/50 or 525/60 system)

Non-interlaced mode(2x312/50 or 2x262/60 system)

A. VALRST[1:0] is taken into account only if bit ENRST is set. Resetting the oscillator means here forcing the value of the phase accumulator to its nominal value to avoid accumulating errors due to the finite number of bits used internally. The value to which the accumulator is reset is either the hard-wired default phase value or the value loaded in the DEN_PDFS[1:2] registers (according to bit SELRST), to which a 0

, 90

, 180

, or 270

correction is applied according to the field and line on which the reset is performed.

If SECAM is performed the oscillator is reset every line.

B. This is the default mode when DENC_NRST pin is active (low level).

C. RSTOSC_BUF is automatically set back to 0 after the buffer is loaded.

D. NINTRL update is internally taken into account at the beginning of the next frame. In

SECAM mode, only the interlaced mode is available.

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Register descriptions 163

DEN_CFG3 Configuration 3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x018

00000000

Description

Bitfield

ENWSS

DEL_EN

CK_IN_PHASE

ENCGMS

TRAP_4.43

Description

WSS encoding enable

A Disabled

1: Enabled

Select delay on chroma path with reference to luma one on S-VHS and CVBS

0: Use default delays:

-0.5 pixel delay for PAL/NTSC in 4:2:2 format on CVBS)

+0.5 pixel delay for SECAM in 4:4:4 format on CVBS)

0.0 pixel delay for PAL/NTSC in 4:4:4 format or SECAM in 4:2:2 format on CVBS)

1: Use chroma programmed delays (described in register

DEN_CFG1 bit BLKI = 1) overwrites VPS or teletext, and no VPS or teletext data is

)

Choice of active edge of CKREF (master clock) that samples incoming YCrCb data.

This bit can be used to analyze the cause of application synchronization problems.

A CKREF falling edge

1: CKREF rising edge

CGMS encoding enable

A Disabled

1: Enabled

Enable trap filter: Trap_4.43 is taken into account only if bit ENTRAP is set

A Select the trap filter centered around 3.58 MHz

1: Select the trap filter centered around 4.43 MHz

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164 Register descriptions

Bitfield Description

ENTRAP

D Enable trap filter

A Trap filter disabled

1: Trap filter enabled

YCRCB_REF_CLK_S Select whether the clock and data comes from the system or the pad

0: Internal clock and video data

1: Clock from PIO1[2] and data from yc[0:7]

A. Default mode when DENC_NRST pin is active (low level)

B. This bit is typically used when synchronization problems appear in application.

C. When ENCGMS is set to 1, closed-captions/extended data services should not be programmed on lines 20 and 283 (525/60, SMPTE line number convention).

D. When SECAM is performed the trap filter is always enabled (ENTRAP = 1).

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Register descriptions 165

DEN_CFG4 Configuration 4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x020

00000000

Description

Bitfield Description

DEL4[2:0] Delay on luma path w.r.t chroma path on YUV and RGB outputs when 4:4:4 input is used

0 1 0: + 2 pixel delay on luma

0 0 1:

0 0 0:

1 1 1:

+ 1 pixel delay on luma

+ 0 pixel delay on luma

- 1 pixel delay on luma

1 1 0: - 2 pixel delay on luma

Other configurations: + 0 pixel delay on luma

ALINE Video active line duration control

Full digital video line encoding (720 pixels - 1440 clock cycles)

1: Active line duration follows ITU-R/SMPTE ‘analog’ standard requirements

SYNCOUT_AD[1:0] Adjustment of outgoing synchronous signals. Used to ensure correct interpretation of incoming video samples as Y, Cr or Cb when the encoder is master and supplies synchronous signals

SYNCIN_AD[1:0]

00:

01:

10:

Nominal

+1 ckref

+2 ckref

11:

Adjustment of incoming synchronous signals. Used to ensure correct interpretation of incoming video samples as Y, Cr or Cb when the encoder is slaved to incoming synchronous signals (incl. ‘F/H’ flags stripped off ITU-R656/D1 data)

00:

01:

+3 ckref

Nominal

+1 ckref

10:

11:

+2 ckref

+3 ckref

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A. Default mode when DENC_NRST pin is active (low level)

DEN_CFG5 Configuration 5

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x028

00000000

Description

Bitfield

DACINV

BKDACN

SELRST_INC

Description

‘Inverts’ DAC codes to compensate for an inverting output stage in the application

A Non inverted DAC inputs (outputs)

1: Inverted DAC inputs (outputs)

Blanking of DACs (N = 1,2,3,4,5 or 6)

DAC N in normal operation

1: DAC N input code forced to black level (if RGB, UV or C) or blanking level (if Y or CVBS) depending on CONF_OUT bits of the DEN_CFG8 register.

Choice of Digital Frequency Synthesizer increment after soft-reset or when

PH_RST_MODE = ‘01’ (see the DEN_CFG8 register)

Hard wired value (depending on TV standard)

Soft (value from DEN_IDFS1/2/3 registers)

A. Default mode when DENC_NRST pin is active (low level)

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Register descriptions 167

DEN_CFG6 Configuration 6

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x030

00010000

Description

Bitfield

MAXDYN

TTX_EN

CFC[1:0]

SOFTRESET

Description

Max dynamic magnitude allowed on YCrCb inputs for encoding

B 10hex to EBhex for Y, 10hex to E0hex for chrominance (Cr,Cb)

1: 01hex to FEhex for Y, Cr and Cb

Teletext enable bit

B Disabled

1: Enabled

Color frequency control via CFC line

0 0:

0 1:

Update mode disabled (update is carried out by loading registers)

DEN_IDFS1/2/3

Update of increment for DDFS just after serial loading via CFC

1 0:

1 1:

Update of increment for DDFS on next active edge of HSYNC

Update of increment for DDFS just before next color burst

Software reset

B No reset

1: Software reset

A. EAV and SAV words are replaced by blanking values before being fed to the luminance and chrominance processing.

B. Default mode when DENC_NRST pin is active (low level)

C. Bit SOFTRESET is automatically reset after internal reset generation. Software reset is active for four CKREF periods. When soft reset is activated, all the device is reset as with hardware reset except for the first nine user registers (DEN_CFG[0:8]).

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DEN_CFG7 Configuration 7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x038

00000000

Description

SQPIX

Bitfield

ENVPS

UV_LEV

SETUPYUV

Description

Square pixel mode enable: This mode is not available in secam standard.

Disable

1: Enable

VPS encoding enable

Disable

Enable

UV output level

Same peak to peak amplitude for both U and V (default value - 0.7 Vpp for

100/0/100/0 color bar pattern)

Pedestal enable on YUV outputs:

This bit is significant only if register DEN_CFG8 bit CONF_OUT[1:0] = 01’ (YUV outputs). If this is the case, the Y output on DAC5_G_Y has a 7.5 IRE pedestal.

Furthermore, if UV_LEV = 1 then the U and V levels also depend on the value of

SETUPYUV.

U and V outputs as defined by ITU-R624-4

Disable

Enable

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Register descriptions 169

Bitfield Description

INV_PHI_SECAM Inversion of subcarrier phase

0, 0,

,... in odd fields and

, 0 in even fields

, 0 in odd fields and 0, 0,

,... in even fields

GEN_SECAM

/SECAM

Where the bit order is SECAM - GEN_SECAM:

01:

10:

11:

Standard selected by STD1 and STD0 bits of DEN_CFG0 (PAL or NTSC)

Genlock slave mode using external synchronous extraction

SECAM standard, the subcarrier phase sequence start-point is line1

SECAM standard, the subcarrier phase sequence start-point is line23

If master mode is performed in the SECAM standard, bit SECAM must be set before

SYNC2, SYNC1 and SYNC0 bits of DEN_CFG0 . If DEN_CFG0 is not programmed, then a soft reset must be performed after programming SECAM. In SECAM, the trap filter should always be enabled (see DEN_CFG3 register).

A. Default value

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170 Register descriptions

DEN_CFG8 Configuration 8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x040

00100000

Description

Bitfield

TTX_NOTMV

BLK_ALL

CONF_OUT[1:0]

Description

After reset, the default value of this bit is zero, however, for devices using teletext, this bit must then be reprogrammed to 1. This is to avoid the occurrence of teletext glitches in SECAM mode and loss of teletext data in all modes.

Priority of ancillary data on a VBI line. Note, higher priority data overwrites lower priority data.

0: priority is: CGMS > closed caption > Macrovision

> WSS > VPS > teletext

1: priority is: teletext > CGMS > closed caption > WSS > VPS > Macrovision

Blanking of all video lines

Disabled

Enabled (all inputs ignored - 0x80 instead of Cr and Cb and 10hex instead of Y and Y4)

DENC output configuration

0 0

0 1

DAC1

DAC2

DAC3

CVBS

DAC4

DAC5

DAC6

CVBS

Y C CVBS R G B

If CONF_OUT[1:0] = 01 and register DEN_CFG2 bit SET_4:4:4 = 1, then the dac5 output Y comes from the Y4 input.

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Register descriptions 171

Bitfield Description

PH_RST_MODE[1:0] Subcarrier phase reset mode.

In modes “01” and “10”, this bit is automatically reset to “00” after oscillator reset.

Disabled

Enabled - phase is updated with value from phase buffer register (see

DEN_CFG2 bit rstosc_buf) on the beginning of the next video line.

Increment is updated with hard or soft value depending on selreg_inc value (see DEN_CFG5 )

Enabled - phase is updated with value from the DEN_IDFS1/2/3 registers on the next increment updating by CFC (depending on CFC loading moment and DEN_CFG6 CFC[1:0] bits.

11 Enabled - phase is reset after detecting of rst bit on cfc line, up to 9

CKREF after loading of CFC’s LSB.

A. If there is no Macrovision programmed on the line, then VBI line blanking (when register

encoded.

B. Default value

C. Default value

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172 Register descriptions

DEN_STA Status

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x048

Undefined

Description

Bitfield

JUMP

FIELDCT[2:0]

BUF1_FREE

BUF2_FREE

Description

Indicates whether a frame length modification has been programmed at ‘1’ from programming of bit ‘jump’ to end of frame(s) concerned default = 0 Refer to DEN_CFG6 register

Digital field identification number

000

...

111

Indicates field 1

Indicates field 8

NOTE: fieldct[0] also represents the odd/even information (odd='0', even='1')

Closed caption registers access condition for field 1

Same as buf2_free but concerns field 1.

Reset value:= 1 (access authorized)

Closed caption registers access condition for field 2

Closed caption data for field 2 is buffered before being output on the relevant TV line; buf2_free is reset if the buffer is temporarily unavailable. If the micro controller can guarantee that the DEN_CCF2 registers are never written more than once between two frame reference signals, then bit ‘buf2_free’ will always be true (set). Otherwise, closed caption field2 registers ( DEN_CCF2 ) access might be temporarily forbidden by resetting bit ‘buf2_free’ until the next field2 closed caption line occurs.

Note that this bit is false (reset) when 2 pairs of data bytes are awaiting to be encoded, and is set back immediately after one of these pairs has been encoded (so at that time, encoding of the last pair of bytes is still pending)

Reset value:= 1 (access authorized)

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Register descriptions

ATFR

Bitfield

HOK

Description

Frame synchronization flag

A Encoder not synchronized

1 In slave mode: encoder synchronized

Hamming decoding of frame sync flag embedded within ITU-R656 / D1 compliant

YCrCb streams

0 Consecutive errors

A A single or no error

A. Default mode when DENC_NRST pin is active (low level)

B. Signal quality detector is issued from Hamming decoding of EAV, SAV from YCrCb

173

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174 Register descriptions

DEN_IDFS[1:3] Increment for digital frequency synthesizer

These three registers contain the 24-bit increment used by the DDFS, only if bit

SELRST_INC (register DEN_CFG5 ) equals 1. They generate the phase of the subcarrier, that is the address that is supplied to the sine ROM. It, therefore, customizes the synthesized subcarrier frequency of 1 LSB ~ 1.6 Hz

To validate use of these registers instead of the hard-wired values use this procedure.

1 Load the registers with the required value.

2 Set bit DEN_CFG5.SELRST_INC

to 1.

3 Using register DEN_CFG6 perform a software reset.

The values loaded in DEN_IDFS[1:3] are taken into account after a software reset, and only if bit DEN_CFG5.SELRST_INC

= 1. These registers are never reset and must be explicitly written, to ensure that they contain sensible information.

On hardware or software reset the DDFS is initialized with a hardwired increment, independent of DEN_IDFS[1:3] . These hardwired values cannot be read out of the

DENC.

0x050

0x058

0x060

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Reserved D7 D6 D5 D4 D3 D2 D1 D0

Address:

Type:

Reset value:

DENC base address+ 0x050( DEN_IDFS1) , 0x058 ( DEN_IDFS2) ,

0x060( DEN_IDFS3)

Undefined

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Register descriptions 175

Description

Bitfield

DEN_IDFS[1:3]

Description

Value

D[23:0]: 21F07C hexa for NTSC M

D[23:0]: 2A098B hexa for PAL BGHIN

D[23:0]: 21F694 hexa for PAL N

D[23:0]: 21E6F0 hexa for PAL M

D(23:0]: 255554 hexa for NTSC M square pixel

D[23:0]: 26798C hexa for PAL BGHIN square pixel

D[23:0]: 1F15C0 hexa for PAL N square pixel

D[23:0]: 254AD4 hexa for PAL M square pixel

Frequency synthesized Ref.Clock

f=3.5795452 MHz 27 MHz f=4.43361875MHz

f=3.5820558 MHz f=3.57561149 MHz f=3.5795434 MHz

27 MHz

24.545454 MHz f=4.43361867 MHz f=3.58205605 MHz f=3.57561082 MHz

29.5 MHz

24.545454 MHz

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176 Register descriptions

DEN_PDFS[1:2] Phase DFS

These registers are never reset and must be explicitly written.

If bit SELRST = 0, for example after a hardware reset, the phase offset used every time the DDFS is re-initialized is a hard-wired value. The hard-wired values cannot be read out of the DENC. These are:

• D9C000hex for PAL BDGHI, N, M,

• 1FC000hex for NTSC-M,

• 000000hex (blue lines),

• 43C000hex (red lines) for SECAM.

When DEN_CFG7.SECAM = 0

Static phase offset for digital frequency synthesizer (10 bits only)

0x068

0x070

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Address:

Type:

Reset value:

DENC base address + 0x068 ( DEN_PDFS1) , 0x070 ( DEN_PDFS2)

Undefined

Under certain circumstances detailed below, these registers contain the 10 MSBs of the value with which the phase accumulator of the DDFS is initialized after a 0 to 1 transition of bit DEN_CFG2.RSTOSC

, or after a standard change, or when cyclic phase readjustment has been programmed (see bits VALRST[1:0] of DEN_CFG2 ).

The fourteen remaining LSBs loaded into the accumulator in these cases are all zeroes, defining the phase reset value with a 0.35

accuracy.

To validate use of these registers instead of the hard-wired values use the following procedure.

1 Load the registers with the required value.

2 Set bit SELRST to 1 ( DEN_CFG2 )

3 Perform a software reset using DEN_CFG6 , or set DEN_CFG6 .

RSTOSC_BUF to

1. This puts the soft-phase value into a temporary register and sets register

DEN_CFG8 bit PH_RST_MODE[1:0] to put this value into an accumulator at the beginning of the next line.

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Register descriptions 177

When DEN_CFG7.SECAM = 1

Static phase offset for digital frequency synthesizer for two SECAM subcarriers

(eight MSB only) (blue lines in DEN_PDFS1 and red lines in DEN_PDFS2)

0x068

0x070

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Address:

Type:

Reset value:

DENC base address + 0x068 ( DEN_PDFS1) , 0x070 ( DEN_PDFS2) ,

Undefined

These registers contain the eight bits (21 to 14) of the value with which the phase accumulator of the DDFS is initialized on every line in SECAM mode. The phase is calculated with 1.4˚ accuracy as:

• blue lines DEN_PDFS1 * 16384 (dec), or DEN_PDFS1 * 4000 (hex),

• red lines (256 + DEN_PDFS1 + DEN_PDFS2) * 16384 (dec), or (100 +

DEN_PDFS1 + DEN_PDFS2) * 4000 (hex)

To validate use of these registers instead of the hard-wired values, follow the PAL and NTSC mode.

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178 Register descriptions

0x078

DEN_WSS[1:2] WSS_BIT[15:0]: WSS data registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x080

Address:

Type:

Reset value:

DENC base address + 0x078 ( DEN_WSS1) , 0x080 ( DEN_WSS2)

Undefined

Description

Bit field

WSS[15:13,7:5,1,0]

WSS[2]

WSS[4:3]

WSS[11:8]

WSS[12]

Description reserved = 0

0 0:

No subtitles within teletext

Subtitles within teletext

No open subtitles

0 1:

1 0:

1 1:

1 0 0 0:

0 0 0 1:

0 0 1 0:

1 0 1 1:

0 1 0 0:

1 1 0 1:

1 1 1 0:

0 1 1 1:

Subtitles in active image area

Subtitles out of image area reserved full format 4:3 box 14:9 center box 14:9 top box 16:9 center box 16:9 top

> box 16:9 center full format 4:3 (shoot and protect 14:9 center) full format 16:9 (anamorphic)

Camera mode

Film mode

A. WSS11 is an odd parity bit

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Register descriptions 179

DEN_DAC13 DAC1 and DAC3 multiplying factors

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x088

10001000

Description

Bit field Description

DAC3_MULT[3:0] multiplying factor on dac3_cvbs digital signal before the digital to analog converters with 3.125% step

0 0 0 0: 75.00% dac3_cvbs value compared to default

0 0 0 1:

0 0 1 0:

0 0 1 1:

.. .. .. ..

1 0 0 0:

78.125% dac3_cvbs value compared to default

81.25% dac3_cvbs value compared to default

84.375% dac3_cvbs value compared to default

...

100% dac3_cvbs value compared to default

.. .. .. ..

1 1 1 1: 121.875% dac3_cvbs value compared to default

DAC1_MULT[3:0] multiplying factor on dac1_y digital signal before the digital to analog converters with

3.125% step

0 0 0 0: 75.000% dac1_y value compared to default

0 0 0 1:

0 0 1 0:

0 0 1 1:

.. .. .. ..

1 0 0 0:

.. .. .. ..

1 1 1 1:

78.125% dac1_y value compared to default

81.250% dac1_y value compared to default

84.375% dac1_y value compared to default

...

100% dac1_y value compared to default

...

121.875% dac1_y value compared to default

A. Default value

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DEN_DAC45 DAC4 and DAC5 multiplying factors

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x090

10001000

Description

Bitfield

DAC5_MULT[3:0]

DAC4_MULT[3:0]

Description

Multiplying factor on dac5_g_y digital signal before the digital to analog converters: dac5_g_y value (in% of default value)

Value if G(conf_out=1x) if Y(conf_out=0x)

0 0 0 0:

0 0 0 1:

0 0 1 0:

0 0 1 1:

.. .. .. ..

80.49%

82.93%

85.37%

87.81%

75.000%

78.125%

81.250%

84.375%

1 0 0 0:

.. .. .. ..

...

100%

...

100%

1 1 1 1: 117.07% 121.875%

Multiplying factor on dac4_r_v_c digital signal before the digital to analog converters: dac4_r_v_c value (in% of default value)

Value

0 0 0 0:

0 0 0 1:

0 0 1 0:

0 0 1 1:

.. .. .. ..

1 0 0 0:

.. .. .. ..

1 1 1 1: if R (conf_out=1x)

80.49%

82.93%

85.37%

87.81%

...

100%

117.07% if V or C (conf_out=0)

75.000%

78.125%

81.250%

84.375%

...

100%

121.875%

Default mode when DENC_NRST pin is active (low level)

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Register descriptions 181

DEN_DAC6C DAC6 and C multiplying factors

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x098

10000000

Description

Bitfield Description

C_MULT[3:0] Multiplying factor on C digital output (before digital to analog convertors) and on color part of CVBS signal:

Value Factor value (C_MULT)

0 0 0 0:

0 0 0 1:

1.000000 (1.000000

dec)

1.000001 (1.015625

dec)

0 0 1 0:

0 0 1 1:

1.000010 (1.031250

dec)

1.000011 (1.046875

dec)

...

.. .. .. ..

1 1 1 1: 1.001111 (1.234375

dec)

DAC6_MULT[3:0] Multiplying factor on dac6_b_cvbs digital signal before the digital to analog converters:

DAC6_B_CVBS value (in% of default value)

Value

0 0 0 0:

0 0 0 1:

0 0 1 0:

0 0 1 1:

.. .. .. ..

1 0 0 0:

.. .. .. ..

1 1 1 1:

If B(conf_out=1x)

80.49%

82.93%

85.37%

87.81%

...

100%

117.07%

If CVBS (conf_out=01)

75.000%

78.125%

81.250%

84.375%

...

100%

121.875%

Default mode when DENC_NRST pin is active (low level)

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Register descriptions

The default peak to peak amplitude of U and V outputs corresponds to 70% of default Y or CVBS peak to peak amplitude if the 100/0/100/0 color bar pattern is inputted. In other words, when IREF is set to deliver 1 Vpp for CVBS on DAC3 and

DAC3_MULT = 1000, when switched to U DAC6 delivers 0.7 Vpp. If bit UV_LEV from register DEN_CFG7 is set, the default peak to peak amplitude is 86% (80% if

SETUPYUV = 1) for V output and 67% (57% if SETUPYUV = 1) for U output. If the

100/0/100/0 color bar pattern is inputted the default is the Y or CVBS peak to peak amplitude, according to the ITU-R 624-4 definition of UV signals.

The default peak to peak amplitude of RGB outputs corresponds to 70% of the default Y or CVBS peak to peak amplitude if the 100/0/75/0 color bar pattern is inputted. In other words, when IREF is set to deliver 1 Vpp for CVBS on DAC3 and

DAC3_MULT = 1000), when switched to B, DAC6 delivers 0.7 Vpp.

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Register descriptions 183

DEN_CID CHIPID: DENC version ID number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved CHIPID

Address:

Type:

Reset value:

DENC base address + 0x0C0

Undefined

Description

Bit field Description

CHIPID 1010 0000

0x0C8

DEN_VPS1 VPS data registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x0D0

0x0D8

0x0E0

0x0E8

0x0F0

Address:

Type:

Reset value:

DENC base address + 0x0C8 (DEN_VPS1), 0x0D0 (DEN_VPS2),

0x0D8 (DEN_VPS3), 0x0E0 (DEN_VPS4), 0x0E8 (DEN_VPS5),

0x0F0 (DEN_VPS6)

Undefined

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184 Register descriptions

Description

Bit field

PT[7:0]

NP[5:0]

C[3:0]

MIN[5:0]

H [4:0]

M[3:0]

D[4:0]

NP[7:6]

CNI[3:0]

S[1:0]

Description

Program type, binary

Network or program CNI (Country and Network Identification)

Country, binary

Minute, binary

Hour, binary

Month, binary

Day, binary

Network or program CNI

4 bits of CNI Reserved for enhancement of VPS

Sounds

0 0: don’t know

0 1: mono

10: stereo

1 1: dual sound

DEN_CGMS[1:3] CGMS data registers (20 bits only)

0x0F8

0x100

0x108

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

Reserved

B1 B2 B3 B4

B5 B6 B7 B8 B9

DENC base address + 0x0F8 (DEN_CGMS1), 0x100

(DEN_CGMS2), 0x108 (DEN_CGMS3)

Undefined

Description

Bit field

B15 to B20

B11 to B14

B7 to B10

B4 to B6

B1 to B3

Description

CRC (not internally computed)

Word2

Word1

Word0B

Word0A

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0x110

DEN_TTX[1:5] TTX_[1:5]_DEF teletext block definition

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x118

0x120

0x128

0x130

Address:

Type:

Reset value:

DENC base address + 0x110 (DEN_TTX1), 0x118 (DEN_TTX2),

0x120 (DEN_TTX3), 0x128 (DEN_TTX4), 0x130 (DEN_TTX5)

Undefined

Description

Bitfield Description

TTX_LX Each of these bits enables teletext on line X (ITU-R line numbering and 625 line systems).

Teletext line selections for other standards refer to the table below:

TTXDEL[2:0] Teletext data latency: The encoder clocks the first teletext data sample on the (2+txdl[2:0]) th rising edge of the master clock, following the rising edge of TTXS (teletext synchronization signal, supplied by the encoder). 1 0 0: default value

FP_TTXT Full page teletext mode enable

A Disabled

Enabled

A. Default mode when DENC_NRST pin is active (low level).

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TTX__[1:4]_DEF Bit field

TTX_L20

TTX_L21

TTX_L22

TTX_L23

TTX_L318

TTX_L319

TTX_L320

TTX_L321

TTX_L322

TTX_L323

TTX_L324

TTX_L325

TTX_L326

TTX_L327

TTX_L328

TTX_L6

TTX_L7

TTX_L8

TTX_L9

TTX_L10

TTX_L11

TTX_L12

TTX_L13

TTX_L14

TTX_L15

TTX_L16

TTX_L17

TTX_L18

TTX_L19

322

323

324

325

326

327

328

318

319

320

321

PAL BDGHIN line

(CCIR 625 line numbering)

268

269

270

271

272

273

274

275

276

277

278

PAL M line

(CCIR 525 line numbering)

NTSC M line

(SMPTE 525 line numbering)

Table 11: Teletext block definition for PAL and NTSC standards

275

276

277

278

279

280

281

271

272

273

274

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0x138

TTX__[1:4]_DEF Bit field

TTX_L329

TTX_L330

TTX_L331

TTX_L332

TTX_L333

TTX_L334

TTX_L335

329

330

331

332

333

334

335

PAL BDGHIN line

(CCIR 625 line numbering)

(CCIR 525 line numbering)

279

280

281

282

283

284

285

PAL M line

282

283

284

285

286

287

288

NTSC M line

(SMPTE 525 line numbering)

Table 11: Teletext block definition for PAL and NTSC standards

DEN_CCF1 extended data for field 1

CCCF1: closed caption characters

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x140

Address:

Type:

Reset value:

DENC base address + 0x138 ( DEN_CCF11) , 0x140 ( DEN_CCF12)

Undefined

Description

C11[7:1]

OPC11

C12[7:1]

OPC12

Bit field Description

First byte to encode in field1

Odd-parity bit of US-ASCII 7-bit character c11[7:1]

Second byte to encode in field1

Odd-parity bit of US-ASCII 7-bit character c12[7:1]

• Default value: none, but closed captions enabling without loading these registers issue a null character.

• DEN_CCF1 registers are never reset.

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0x148

DEN_CCF2 extended data for field 2

CCCF2: closed caption characters,

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x150

Address:

Type:

Reset value:

DENC base address + 0x148 (DEN_CCF21), 0x150 (DEN_CCF22)

Undefined

Description

C21[7:1]

OPC21

C12[7:1]

OPC22

Bit field Description

First byte to encode in field2

Odd-parity bit of US-ASCII 7-bit character c21[7:1]

Second byte to encode in field2

Odd-parity bit of US-ASCII 7-bit character c22[7:1]

• Default value: none, but closed captions enabling without loading these registers issue a null character.

• DEN_CCF2 registers are never reset.

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DEN_CLF1 insertion for field 1

CCLIF1: closed caption, extended data line

This register programs the TV line number of the closed caption and extended data encoded in field 1:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x158

00001111

525/60 system: (525-SMPTE line number convention)

Only lines 10 to 22 should be used for closed caption or extended data services. Lines one to nine contain the vertical synchronous pulses with equalizing pulses.

Bit field

L1[4:0] 0 0 0 0 0:

0 0 0 x x:

....

i code line (i+6)

....

11111:

Description

No line selected for closed caption encoding

Do not use these codes

(SMPTE) selected for encoding line 37 (SMPTE) selected

625/50 system: (625-CCIR/ITU-R line number convention)

Only lines 7 to 23 should be used for closed caption or extended data services.

Bit field

L1[4:0] 0 0 0 0 0:

....

i code line (i+6)

....

11111:

Description

No line selected for closed caption encoding

(CCIR) selected for encoding (i>0) line 37 (CCIR) selected

Default value = 01111 line 21 (525/60, 525-SMPTE line number convention), which corresponds to line 21 in l625/50 system,(625-CCIR line number convention)

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190 Register descriptions

DEN_CLF2 insertion for field 2

CCLIF2: closed caption/extended data line

This register programs the TV line number of the closed caption and extended data encoded in field 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

525/60 system: (525-SMPTE line number convention)

Only lines 273 to 284 should be used for closed caption or extended data services although it is possible to program over a wider range. Preceding lines contain the vertical synchronous pulses with equalizing pulses. If CGMS is allowed on lines 20 and 283 (525/60, 525-SMPTE line number convention), closed captions should not be programmed on these lines.

Bit field

L2[4:0] 0 0 0 0 0:

0 0 0 x x: i line (269 +i)

....

01111:

11111:

DENC base address + 0x160

00001111

Description

No line selected for closed caption encoding

Do not use these codes

(SMPTE) selected for encoding

Line 284 (SMPTE) selected for encoding

Line 289 (SMPTE)

625/50 system: (625-CCIR line number convention)

Only lines 319 to 336 should be used for closed caption or extended data services although it is possible to program over a wider range. Preceding lines contain the vertical synchronous pulses with equalizing pulses,

Bit field l2[4:0] 0 0 0 0 0: i line (318 +i)

....

10010:

11111:

Description

No line selected for closed caption encoding

(CCIR) selected for encoding

Line 336 (CCIR) selected for encoding

Line 349 (CCIR)

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Register descriptions 191

Default value = 01111 line 284 (525/60, 525-SMPTE line number convention, which corresponds to line 333 in 625/50 system, (625-CCIR line number convention)

DEN_REG_64 TTX_CONF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x200

01010000

Description

Do not change the value of bits 4 to 0.

Bit field

TTXT_ABCD[1:0]

TTXT100IRE

Description

Teletext standard selection

0 0

0 1

Teletext A

Teletext B teletext B in 625 line systems is known as World System

Teletext

1 0

1 1

Teletext C teletext C in 525 line systems is known as NABTS

Teletext D

Teletext waveform amplitude

70 IRE

1 100 IRE

A. Default mode when DENC_NRST pin is active (low level)

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192 Register descriptions

DEN_REG_65 DAC2MULT and TTXS

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x208

10000010

Description

Bitfield Description

BCS_EN_2

BCS_EN_4

Brightness, Contrast and Saturation control by registers DEN_REG_69 to

DEN_REG_71 on 4:2:2 input

A Disable

1: Enable

Brightness, Contrast and Saturation control by registers DEN_REG_69 to

DEN_REG_71 on 4:4:4 input

0: Disable

Enable

TTX_MASK_OFF Masking of 2 bits in teletext framing code, depending on selected teletext standard

Enable

1: Disable

DAC2_MULT[3:0] Multiplying factor on dac1_c digital signal before the digital to analog converters with

3.125% step

Bitvalue dac2_c value compared to default

0 0 0 0: 75.000%

0 0 0 1: 78.125%

0 0 1 0: 81.250%

0 0 1 1: 84.375%

...

1 0 0 0:

100%

...

1 1 1 1: 121.875%

A. Default mode when DENC_NRST pin is active (low level)

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Register descriptions 193

DEN_REG_69 Brightness

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved B[7:0]

Address:

Type:

Reset value:

DENC base address + 0x228

10000000

The register contents are used by the following formula to adjust the luminance intensity of the display video image:

Y out

= Y in

+ b – 128

Where:

• Y in

is 8-bit input luminance,

• Y out

is the result of the brightness operation (still on 8 bits), saturated at 235

(16) or 254 (1) according to DEN_CFG6 bit MAXDYN ,

• b is brightness, an unsigned value with center at 128, default 128.

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194 Register descriptions

DEN_REG_70 Contrast

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved C[7:0]

Address:

Type:

Reset value:

DENC base address + 0x230

00000000

The register contents are used by the following formula to adjust the relative difference between the display image higher and lower intensity luminance values:

Y out

(

Y in

– 128

) ( c + 128

)

--------------------------------------------------

128

+ 128

Where ,

• Y in

is 8-bit input luminance,

• Y out

is the result of the contrast operation (still on 8 bits ), saturated at 235 (16) or 254 (1) according to DEN_CFG6 bit MAXDYN ,

• c is contrast, two’s complement value from -128 to 127, default 0.

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Register descriptions 195

DEN_REG_71 Saturation

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved S[7:0]

Address:

Type:

Reset value:

DENC base address + 0x238

10000000

The register contents are used by the following formula to adjust the color intensity of the displayed video image:

Crout = s Crin –

128

)

+ 128

Cbout = s Cbin –

128

)

+ 128

Where:

• Crin and Cbin are the 8-bit input chroma,

• Crout and Cbout are the result of the saturation operation (still on 8 bits), saturated at 240 (16) or 254 (1) according to DEN_CFG6 bit MAXDYN ,

• s is the saturation value, unsigned value with centre at 128, default 128.

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196 Register descriptions

DEN_CFCOEF[0:8]Chroma filter coefficient 0 to 8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

0x240

(DEN_

CFCOEF0)

0x248

(DEN_

CFCOEF1)

0x250

(DEN_

CFCOEF2)

0x258

(DEN_

CFCOEF3)

0x260

(DEN_

CFCOEF4)

0x268

(DEN_

CFCOEF5)

0x270

(DEN_

CFCOEF6)

0x278

(DEN_

CFCOEF7)

0x280

(DEN_

CFCOEF8)

Address:

Reserved

Type:

Reset value:

FLT

6 5 4 3 2 1 0

PLG_

DIV1

PLG_

DIV0

CH_

COEF0

[4:0]

CH_

COEF

8[8]

CH_COEF1[5:

CH_COEF2[6:0]

CH_COEF3[6:0]

CH_COEF4[7:0]

CH_COEF5[7:0]

CH_COEF6[7:0]

CH_COEF7[7:0]

CH_COEF8[7:0]

DENC base address + 0x240 (DEN_CFCOEF0), 0x248,

0x250,....0x280 (DEN_CFCOEF8)

RW see table below

Description

These registers contain the nine coefficients and three control bits for the chroma filter, which are described in the table below. The coefficients are chosen to give the

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Register descriptions 197 required filter response for a specific application according to the symmetrical RIF filter equation:

H z = c

+ c

1 z

– 1

+ c

2 z

– 2

˙˙˙

+ c

– 7

+ c

8 z

– 8

+ c

7 z

– 9

˙˙˙

+ c

– 14

+ c

1 z

– 15

+ c

0 z

– 16

The register reset, or default, values give the coefficients for the SECAM square pixel mode.

Each register value is calculated by adding an offset value to the desired coefficient value, according to the relationship: register value = offset + actual coefficient value.

For instance, to obtain a coefficient value of five for c4, which has an offset of 32, the register DEN_CFCOEF4 must contain the value 100101, which is the binary equivalent of 32 + 5. The offset values for each coefficient are listed in the table below.

The sampling frequency of the filter is CKREF (27 MHz., 24.5454 MHz. or

29.5 MHz.).

Bitfield

CH_COEF8[7:0]

CH_COEF7[7:0]

CH_COEF6[7:0]

CH_COEF5[7:0]

CH_COEF4[7:0]

CH_COEF3[6:0]

CH_COEF2[6:0]

Description (offset & coefficient values in decimal)

Coefficient number 8 (ch_coef8); offset value = 0, reset value = 10000000, corresponding to c8 = 128

Coefficient number 7 (ch_coef7); offset value = 0, reset value = 01111011, corresponding to c7 = 123

Coefficient number 6 (ch_coef6); offset value = 0, reset value = 01101100, corresponding to c6 = 108

Coefficient number 5 (ch_coef5); offset value = 32, reset value = 01110111, corresponding to c5 = 87

Coefficient number 4 (ch_coef4); offset value = 32, reset value = 01011111, corresponding to c4 = 63

Coefficient number 3 (ch_coef3); offset value = 32, reset value = 1000111, corresponding to c3 = 39

Coefficient number 2 (ch_coef2); offset value = 64, reset value = 1010100, corresponding to c2 = 20

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198 Register descriptions

Bitfield Description (offset & coefficient values in decimal)

CH_COEF1[5:0]

CH_COEF8[8]

CH_COEF0[4:0]

PLG_DIV[1:0]

FLT_S

Coefficient number 1 (ch_coef1); offset value = 32, reset value = 100111, corresponding to c1 = 7

Coefficient number 8 (ch_coef8) bit 8; reset value = 0, see ch_coef8[7:0] below

Coefficient number 0 (ch_coef0); offset value = 16, reset value = 10001, corresponding to c0 = 1

00: When sum of coefficients = 512 (dec.)

01: When sum of coefficients = 1024 (dec. reset value)

10: When sum of coefficients = 2048 (dec.)

11: When sum of coefficients = 4096 (dec.)

Use hard-wired coefficients for the chroma filter

Use register DEN_CFCOEF[0:8] values, default (reset) or programmed, to determine coefficients

Reserved Reset value: 0

A. The MSB of this coefficient value can be found in the DEN_CFCOEF1 register.

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Register descriptions 199

DEN_CFG9 Chroma delay and luma filter control

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address:

Type:

Reset value:

DENC base address + 0x288

00100010

Description

This register contains the chroma path delay, referenced to luma one on S-VHS and

CVBS outputs, selection of input format mode, and three bits to control the luma filter. The following table describes the register’s functions.

Bitfield

FLT_YS

PLG_DIV_Y[1:0]

SET444_CVBS

Description

00:

01:

Use hard-wired coefficients for the luma filter

Use register DEN_LFCOEF[0:9] values, default (reset) or programmed, to determine coefficients

When sum of coefficients = 256 (dec.)

When sum of coefficients = 512 (dec. reset value)

10:

11:

When sum of coefficients = 1024 (dec.)

When sum of coefficients = 2048 (dec.)

Select input format to DENC for S-VHS and CVBS outputs:

4:2:2 input format (default)

4:4:4 input format

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200 Register descriptions

Bitfield Description

DEL[3:0]

A Delay on chroma path with reference to luma path encoding (1 pixel = 2 periods of frequency f

CKREF

0010: -0.5 pixel delay (default for PAL/NTSC in 4:2:2 format on CVBS)

0011: -1.0 pixel delay

0100: -1.5 pixel delay

0101: -2.0 pixel delay

1100: +2.5 pixel delay

1101: +2.0 pixel delay

1110: +1.5 pixel delay

1111: +1.0 pixel delay

0000: +0.5 pixel delay (default for SECAM in 4:4:4 format on CVBS)

0110, 1000, 1010: +0.5 pixel delay

0001: 0.0 pixel delay (default for PAL/NTSC in 4:4:4 format or SECAM in 4:2:2 format on CVBS)

0111, 1001, 1011: 0.0 pixel delay

A. Bit DEN_CFG3.DEL_EN selects either default or programmed delays.

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Register descriptions 201

DEN_LFCOEF[0:9]Luma filter coefficient 0 to 9

0x290

(DEN_

LFCOEF

0x298

(DEN_

LFCOEF

0x2A0

(DEN_

LFCOEF

0x2A8

(DEN_

LFCOEF

0x2B0

(DEN_

LFCOEF

0x2B8

(DEN_

LFCOEF

0x2C0

(DEN_

LFCOEF

0x2C8

(DEN_

LFCOEF

0x2D0

(DEN_

LFCOEF

0x2D8

(DEN_

LFCOEF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

Reserved

LU_

COEF8

[8]

LU_

COEF0

[4:0]

LU_

COEF9

[9:8]

LU_COEF1[5:0]

LU_

COE

6[8]

LU_

COE

F7[8]

6 5 4 3 2 1 0

LU_COEF2[6:0]

LU_COEF3[6:0]

LU_COEF4[7:0]

LU_COEF5[7:0]

LU_COEF6[7:0]

LU_COEF7[7:0]

LU_COEF8[7:0]

LU_COEF9[7:0]

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202

PRELIMINARY DATA

Register descriptions

Address:

Type:

Reset value:

DENC base address + 0x290 (DEN_LFCOEF0), 0x298,

0x2A0,....0x2D8 (DEN_LFCOEF9)

RW see table below

Description

These registers contain the ten coefficients for the luma filter, which are described in the table below. The coefficients give the required filter response for a specific application according to the symmetrical RIF filter equation: z

)

= l

+ l

1 z

– 1

+ l

2 z

– 2

˙˙˙

+ l

8 z

– 8

+ l

9 z

– 9

+ l

8 z

– 10

˙˙˙

+ l

2 z

– 16

+ l

1 z

– 17

+ l

0 z

The values of the coefficients lu_coef0 through to lu_coef7 must be entered in two’s complement form and the remainder as normal positive values.

The sampling frequency of the filter is CKREF (27 MHz, 24.5454 MHz or 29.5 MHz.)

The control bits for this filter are in register

Section 5.6: DVP module architecture on page 214

Bitfield

LU_COEF9[7:0]

LU_COEF8[7:0]

LU_COEF7[7:0]

LU_COEF6[7:0]

LU_COEF5[7:0]

LU_COEF4[7:0]

LU_COEF3[6:0]

Description (coefficient values in decimal)

Coefficient number 9 (LU_COEF9); reset value = 11111000, corresponding to l9 =

+504

Coefficient number 8 (LU_COEF8); reset value = 00111101, corresponding to l8 =

+317

Coefficient number 7 (LU_COEF7); reset value = 00000111, corresponding to l7 =

Coefficient number 6 (LU_COEF6); reset value = 10101100, corresponding to l6 =

-84

Coefficient number 5 (LU_COEF5); reset value = 11111011, corresponding to l5 = -5

Coefficient number 4 (LU_COEF4); reset value = 00011111, corresponding to l4 =

+31

Coefficient number 3 (LU_COEF3); reset value = 0000011, corresponding to l3 = +3

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Register descriptions 203

Bitfield Description (coefficient values in decimal)

LU_COEF7[8]

LU_COEF2[6:0]

LU_COEF6[8]

LU_COEF1[5:0]

LU_COEF9[9:8]

LU_COEF0[4:0]

LU_COEF8[8]

Coefficient number 7 (LU_COEF7) bit 8; reset value = 0, see lu_coef7[7:0] below

Coefficient number 2 (LU_COEF2); reset value = 1110111, corresponding to l2 = -9

Coefficient number 6 (LU_COEF6) bit 8; reset value = 1, see lu_coef6[7:0] below

Coefficient number 1 (LU_COEF1); reset value = 111111, corresponding to l1 = -1

Coefficient number 9 (LU_COEF9) bits 8 & 9, reset value = 01, see lu_coef9[7:0] below

Coefficient number 0 (LU_COEF0); reset value = 00001, corresponding to l0 = +1

Coefficient number 8 (LU_COEF8) bit 8; reset value = 1, see lu_coef8[7:0] below

Reserved Reset value: 0

A. The MSB(s) of these coefficient values can be found in one of the above DEN_LFCOEF registers.

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Register descriptions

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Video front end (VFE)

5.1 Overview

The video front end (VFE) extracts embedded synchronization signals, ancillary data and video data from 2 YCbCr streams in the digital video port (DVP). Ancillary data is fully decoded and is sent to DRAM when the DECODING ENABLE ancillary data signal is enabled. Video data is also decoded and sent to DRAM after horizontal and vertical filtering when the DECODING ENABLE video signal is enabled. The samples are inside windows separately defined for the top and bottom field.

If the YCbCr stream is not 601_656 compliant, external horizontal and vertical synchronization signals are supported.

The video front end also includes the video timing generator which must be the slave of one DVP or used in master mode.

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206 System configuration

5.2 System configuration

This sections provides a view of a gamma-based architecture, as implemented in an

ST40 device.

RGB888

Digital

BLITTER

ENGINE capture bkg color

GDP

GDP cursor

HSYNC, VSYNC, BNOTT

GAMMA

External

Memory system

Interconnect

YCbCr 4:2:2

(Raster storage)

+ VBI data

VFE

DVP (1) D1

(1)

DVP (2) D1

(2) syncs

VTG

Audio

Capture

Port

Audio player

PCM

OUT

Figure 61: ST40 gamma architecture

Each DVP module can capture a video input stream in the local memory, with an optional resizing operation (downsize only).

The video buffers, once stored in the external memory, can be displayed using a GDP pipeline, or handled by the blitter under the CPU’s control.

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VFE module 207

Ancillary data such as close caption or teletext which is included in the input stream can be captured in a separate buffer for post-processing by the ST40 CPU.

The video input sync may be used as a master sync reference for the device. The external VSYNC event can optionally generate an interrupt to the ST40 CPU.

5.3 VFE module

The VFE module regroups two DVP submodules described in

of this document and the VTG submodule described in

Section 5.7: Video timing generator (VTG) on page 222 . A block diagram

of the VFE is shown in

Figure 62 .

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CPU_CK

DIN_I_REG_DATA_IN[31:0]

DIN_I_REG_OPC[7:0]

DIN_I_REG_REQ

DIN_I_REG_ADDRESS[13:2]

DIN_I_REG_BE[3:0]

DIN_O_REG_R_DATA[31:0]

DIN_O_REG_R_REQ

DIN_O_REG_R_OPC

DIN_O_DVP0_VID_REQ

DIN_O_DVP0_VID_ADD [31:4

DIN_O_DVP0_VID_BYTE_EN [15:0]

DIN_O_DVP0_VID_DATA [127:0]

DIN_O_DVP0_VID_OPC [7:0]

DIN_O_DVP0_VID_EOP

DIN_O_DVP0_VID_TID4

DIN_I_DVP0_VID_GRANT

DIN_I_DVP0_VID_VALID

DIN_O_DVP0_ANC_REQ

DIN_I_DVP0_ANC_GRANT

DIN_O_DVP0_ANC_ADD [31:4]

DIN_O_DVP0_ANC_BYTE_EN [15:0]

DIN_O_DVP0_ANC_DATA [127:0]

DIN_O_DVP0_ANC_OPC [7:0]

DIN_O_DVP0_ANC_EOP

DIN_O_DVP0_VID_TID4

DIN_I_DVP0_ANC_VALID

DIN_O_DVP1_VID_REQ

DIN_O_DVP1_VID_ADD [31:4

DIN_O_DVP1_VID_BYTE_EN [15:0]

DIN_O_DVP1_VID_DATA [127:0]

DIN_O_DVP1_VID_OPC [7:0]

DIN_O_DVP1_VID_EOP

DIN_O_DVP1_VID_TID4

DIN_I_DVP1_VID_GRANT

DIN_I_DVP1_VID_VALID

DIN_O_DVP1_ANC_REQ

DIN_I_DVP1_ANC_GRANT

DIN_O_DVP1_ANC_ADD [31:4]

DIN_O_DVP1_ANC_BYTE_EN [15:0]

DIN_O_DVP1_ANC_DATA [127:0]

DIN_O_DVP1_ANC_OPC [7:0]

DIN_O_DVP1_ANC_EOP

DIN_O_DVP1_VID_TID4

DIN_I_DVP1_ANC_VALID

PRELIMINARY DATA

Register summary 209

5.4 Register summary

Table 12 and

Table 13 provide a summary of the VFE registers for the DVP and

VTG submodules. The addresses are given from a base address:

• DVP0 = 0x000,

• DVP1 = 0x100,

• VTG = 0x200.

Register name where n = 0 to 1

DVP[N]_CTL

DVP[N]_TFO

DVP[N]_TFS

DVP[N]_BFO

DVP[N]_BFS

DVP[N]_VTP

DVP[N]_VBP

DVP[N]_VMP

DVP[N]_CVS

Description Type

Control register, see

DVP[n]_CTL on page 230

Top field offset (h & v, with respect to

(0,0)), see

DVP[n]_TFO on page 233

Top field stop (h & v, with respect to

(0,0)), see

DVP[n]_TFS on page 233

Bottom field offset (h & v, with respect to (0,0)), see

DVP[n]_BFO on page 234

Bottom field stop (h & v, with respect to (0,0)), see

DVP[n]_BFS on page 234

Video top pointer (memory location for top-left pixel), see

DVP[n]_VTP on page 235

Video bottom pointer (memory location for top-left pixel), see

DVP[n]_VBP on page 235

Video memory pitch, see

DVP[n]_VMP on page 236

Captured video size, see

DVP[n]_CVS on page 237

Table 12: DVP address map

Address offset

0x[n]00

0x[n]04

0x[n]08

0x[n]0C

0x[n]10

0x[n]14

0x[n]18

0x[n]1C

0x[n]20

Access size

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Register summary

Register name where n = 0 to 1

DVP[N]_VSD

DVP[N]_HSD

DVP[N]_HLL

DVP[N]_HSRC

DVP[N]_HFC

DVP[N]_VSRC

DVP[N]_VFC

DVP[N]_ITM

DVP[N]_ITS

DVP[N]_STA

DVP[N]_LNSTA

DVP[N]_HLFLN

DVP[N]_ABA

Description Type

Vertical synchro delay, see

DVP[n]_VSD on page 238

Horizontal synchro delay, see

DVP[n]_HSD on page 239

Half line length, see

DVP[n]_HLL on page 240

Horizontal sample rate converter configuration, see

DVP[n]_HSRC on page 241

Horizontal filter coefficients (10 addresses), see

DVP[n]_HFC on page 242

Vertical sample rate converter configuration, see

DVP[n]_VSRC on page 243

Vertical filter coefficients (6 addresses), see

DVP[n]_VFC on page 244

DVP interrupt mask, see

DVP[n]_ITM on page 245

DVP interrupt status, see

DVP[n]_ITS on page 245

DVP interrupt register, see

DVP[n]_STA on page 246

Line number status, see

DVP[n]_LNSTA on page 246

Half lines per field, see

DVP[n]_HLFLN on page 247

Ancillary data base address, see

DVP[n]_ABA on page 247

Table 12: DVP address map

Address offset

0x[n]24

0x[n]28

0x[n]2C

0x[n]30

0x[n]34 to

0x[n]58

0x[n]60

0x[n]64 to

0x[n]78

0x[n]98

0x[n]9C

0x[n]A0

0x[n]A4

0x[n]A8

0x[n]Ac

Access size

32 each

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Register summary 211

Register name where n = 0 to 1

DVP[N]_AEA

Description Type

Address offset

DVP[N]_APS

DVP[N]_PKZ

Ancillary data end address, see

DVP[n]_AEA on page 248

Ancillary data page size, see

DVP[n]_APS on page 248

Packet size on SuperHyway protocol, see

DVP[n]_PKZ on page 249

Table 12: DVP address map

0x[n]B0

0x[n]B4

0x[n]FC

Table 13 provides a summary of the VFE registers for the VTG module.

Access size

Register name

VTG_MOD

VTG_CLKLN

VTG_H_HD

VTG_TOP_V_VD

VTG_BOT_V_VD

VTG_TOP_V_HD

Description

Video timing generator mode of operation, see

VTG_MOD on page 250

Number of samples per line, see

VTG_CLKLN on page 250

HSYNC output rising edge, see

VTG_H_HD on page 251

VSYNC delay from line counter clear for output rising edge on top field in line units, see

VTG_TOP_V_VD on page 252

VSYNC delay from line counter clear for output rising edge on bottom field in line units, see

VTG_BOT_V_VD on page 253

VSYNC delay from sample counter clear for output rising edge in sample units on top field, see

VTG_TOP_V_HD on page 254

Table 13: VTG address map

Type

Addres s offset

0x224

Access size

0x228

0x22C

0x230

0x234

0x238

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PRELIMINARY DATA

Register summary

Register name

VTG_BOT_V_HD

VTG_HLFLN

VTG_DRST

VTG_ITM

VTG_ITS

VTG_STA

Description

VSYNC delay from sample counter clear for output rising edge in sample units on bottom field, see

VTG_BOT_V_HD on page 255

Half lines per field, see

VTG_HLFLN on page 255

VTG soft reset, see

VTG_DRST on page 256

Interrupt mask, see

VTG_ITM on page 256

Interrupt status, see

VTG_ITS on page 257

Status register, see

VTG_STA on page 257

Table 13: VTG address map

Type

Addres s offset

0x23C

Access size

0x240

0x248

0x298

0x29C

0x2A0

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VFE phase relations

5.5 VFE phase relations

The outputs of VTG are related to PIX2_CK as shown below. The derived PIX_CK must be phased to take into account the relative position of the signals.

213

PIX2_CK

VTG_O_VREF

VTG_O_HREF

VTG_O_BNOTT

VTG_O_PIX_CNT clk_per_line/2-1

0 top field

PIX2_CK

VTG_O_VREF

VTG_O_HREF

VTG_O_BNOTT

VTG_O_PIX_CNT bottom field clk_per_line/4-1 clk_per_line/4 clk_per_line/4+1

PIX_CK to generate

Figure 63: Outputs of VTG

31 32 clk_per_line/4+32

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214 DVP module architecture

5.6 DVP module architecture

5.6.1 List of features

DVP main features are:

• ITU-R BT.601/656 compliance, 525/60i 720 x 480, 625/50i 720 x 576 nominal formats,

• support for SQ pixel video, 525/60i 640 x 480, 625/50i 768 x 576,

• external sync support for video streams that do not provide embedded code words (SAV/EAV protocol),

• video data is captured into the system local memory, in YCbCr4:2:2 raster format (compatible with gamma 2D-blitter as well as with the GDP display),

• user-defined capture window to select a subregion within the active area of the incoming video,

• continuous resampling capability from x1 to x0.1, both horizontally and vertically, using a 5-taps horizontal filter, and a 3-taps vertical filter,

• generic ancillary data capture processor (SMPTE291M, ITU-RBT-1364), in a paged circular buffer, for post-processing by a host CPU,

• the extracted (or separately provided) video timebase is provided to the system to become the master reference.

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DVP module architecture

PRELIMINARY DATA

5.6.2 DVP block diagram

DVP_I_HSI

DVP_I_VSI

DVP_I_

YCBCR[7:0]

PIX2_CK protocol

VIDEO_DATA

ANC_DATA protocol

601/656 decoder

Delay

Line

Delay

Line

5-taps

H-SRC

HF rd wr

REQ, OPC, BE, EOP, TID

GRANT, R_REQ, R_OPC,

R_EOP

Video

capture

FIFO

VIDEO_ADDRESS

ANC_ADDRESS

REQ, OPC, BE, EOP, TID

Ancillary Data

Capture

FIFO

DVP reg module

215

DIN_I_DVP0_HSI

VTG CPU

Figure 64: DVP module functional block diagram

The design is a modular architecture, similar to the one used in the gamma blitter engine. It must be split into a chain of independent sub-blocks, that are compliant with the in/out protocol defined for the blitter.

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5.6.3 Operation

5.6.3.1 DVP submodule overview

Ancillary data, when enabled, is systematically detected and sent on the ANC_DATA bus with protocol signals ( FIRST_PIXEL , LAST_PIXEL and NEXT_VALID_ANC ). The first mode reads the number of words present in the detected packet to enable detection of two successive ancillary packets. The second mode stores a fixed number of bytes after the detected header ignoring the real length of packet. If the fixed number is greater than the effective length, one or more headers occurring inside the fixed number are not taken into account.

Video data, when enabled, is detected into the window given by registers loaded by

CPU. The VIDEO_DATA bus is sent with protocol associated (that is

NEXT_VALID_VIDEO , FIRST_LINE , FIRST_PIXEL , LAST_LINE and LAST_PIXEL ) to be processed before sending to DRAM.

5.6.3.2 Bandwidth considerations

The general formula to estimate the bandwidth requirement (BR) of the DVP system is:

BR (in MByte/s) = (Pixel frequency in MHz) x 2 x horizontal resampling factor

Examples:

• 601 rate / x1: BR = 13.5 x 2 x 1 = 27 MByte/s

• PAL SQ rate / x1: BR = 14.75 x 2 x 1 = 29.5 MByte/s

• 601 rate / x0.4: BR = 13.5 x 2 x 0.4 = 10.8 MByte/s

The vertical resizing factor does not impact the peak bandwidth, but only the average bandwidth.

5.6.4 Description of unitary functions

5.6.4.1 SuperHyway interface

The DVP SuperHyway interface includes:

• an initiator interface to capture the video data into the external memory. The data is buffered into a x128 FIFO,

• an initiator interface to capture the ancillary data into the external memory,

• a target interface so that the CPU can access its registers.

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217

5.6.4.2 Description of the video decoder.

The frame architecture for an ITU-R BT.656 compliant video is shown in

Figure 65

Y, Cb,Cr are multiplexed at twice the pixel rate on an 8-bit bus, according to a 4:2:2 sampling pattern.

External HSI (optional)

Embedded H flag

EAV SAV

TF_VBLK

Top Field Blanking

HBLK

TF_VAV

HAV

Top Field Active Video

BF_VBLK

Bottom Field Blanking

BF_VAV

Bottom Field Active Video

EAV...........

SAV...........

HBLK........

HAV..........

TF_VBLK.

TF_VAV.....

BF_VBLK..

BF_VAV....

End of Active Video

Start of Active Video

Horizontal Blanking

Horizontal Active Video

Top Field Vertical Blanking

5.7 Video timing generator (VTG)

The video timing generator is either master or slave of the digital video port (DVP).

As master it delivers HSYNC (horizontal synchronization signal) and VSYNC

(vertical synchronization signal) starting from hard or soft reset and calibrated by register information such as the number of samples per line and the number of half lines in a field).

As a slave, HSYNC and VSYNC are generated from incoming signals HSYNC_IN and

VSYNC_IN ; the line length is not fixed and the number of half lines per field depends on the interval between two VSYNC_IN signals.

5.7.1 List of features

The main features of the VTG are:

• in master mode, it automatically generates synchronization signals and associated counters values,

• in slave mode, it re-generates synchronization signals and associated counter values dependant upon the incoming synchronization signals.

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Video timing generator (VTG)

PRELIMINARY DATA

5.7.2 Block diagram

dvp0_hsync dvp1_hsync pix2_ck0 pix2_ck1 dvp0_vsync dvp1_vsync hardreset

13 vtg_sample_cnt pix2clk vtg_hsync vtg_pix_cnt[11:0] vref vsync hdo, hds, clk_per_line[12:0], vtg_mode hardreset href_pulse halfline hardreset href hsync vtg_IRQ vtg_vsync halflinecnt[11:0] vref_pulse ext_bnott vtg_halflinecnt halflinecnt[11:0] bnott hardreset pix2clk vdo, vds, halflines_per_vert[11:0], vtg_mode vtg_reg_module

223

Figure 67: VTG functional block diagram

CPU

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Video timing generator (VTG)

5.7.3 Description of unitary functions

5.7.3.1 Master mode

In this mode HSYNC_IN and VSYNC_IN are not taken into account. When a hard or soft reset occurs SAMPLECNT and HALFLINECNT are cleared, at the same time

HREF and VREF are made activate, SAMPLECNT counts until CLK_PER_LINE is reached and then cleared, a new HREF is activated and so on. The counter halflinecnt is incremented each time SAMPLECNT equals CLK_PER_LINE/2 and

CLK_PER_LINE (half line signal). When this counter reaches

HALFLINES_PER_VERT minus one ( HLFLN - 1 in the following diagram) a new

VREF is activated and HALFLINECNT is cleared.

The counter LINECNT is set to one when HREF and VREF occur at the same time and cleared when VREF occurs without HREF and incremented by HREF .

pix2clk reset href vref bnott halfline hsync reset href halfline vref bnott vsync

0 1

2 3

4 5 6

5 (hlfln-1)/2

(hlfln+1)/2 0

(hlfln-1) 0 1

VDO

VDS

0 1 2 31 32 reference edge

HDO

HDS

Figure 68: Unitary functions in master mode

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225

5.7.3.2 Slave mode

In slave mode the VTG is driven by external synchronization signals ( HSYNC_IN and VSYNC_IN ) coming from the DVP module. These signals are delivered synchronously using the VTG clock.

The coincidence of HSYNC_IN and VSYNC_IN at the beginning of the top field is considered perfect. The VTG operates the same as in master mode, except that the signals HREF and VREF are derived from the incoming synchronization instead of being determined by the values of the SAMPLECNT , HALFLINECNT and LINECNT counters.

pix2clk vsync_in hsync_in href vref bnott halfline hsync vsync_in hsync_in href halfline vref bnott vsync

0 1

2 3

4 5 6

VDO

VDS

0 1 2 31 32 reference edge

5 n-1

HDO

HDS

Figure 69: Unitary functions in slave mode n 0

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PRELIMINARY DATA

YCbCr 422 memory storage

5.8 YCbCr 422 memory storage

128-bit word address

BIT 127

Y Cr Y Cb

PIXEL X+6

PIXEL X+7

BYTE ADDRESS INCREASES

Y Cr Y Cb

31 24 23 16 15 8 7

Y Cr Y Cb

BIT 0

PIXEL X+4

PIXEL X+5

PIXEL X+2

PIXEL X+3

16-BIT PIXEL ADDRESS INCREASES

PIXEL X

PIXEL X+1

- Memory address for pixel (0,0) must be aligned on a 32-bit word address boundary

- The pitch value must be a multiple of 4 bytes

- X is even on that diagram

Figure 70: YCbCr 4:2:2 (16 bpp)

5.9 Clocks and resets

5.9.1 Clock description

CPU_CK is the clock used for the register interface. It runs at 100 MHz

ST-CK is the clock used for the interconnect interface. It runs at 111 MHz.

PIX_2X_CK is the pixel 2X clock. It runs at up to 30 MHz.

5.9.2 Reset generation

The hard reset is resynchronized to each clock and generates a reset active low synchronous to the falling edge of the clock. This reset is used as an asynchronous reset on all the FF.

To buffer this net, a clock tree is inserted with relaxed conditions for skew.

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Interface description 227 hard_reset tst_mux_nrst

0 block_nrst clock tree block_ck en tst_nrst_mux

Figure 71: Reset generation

5.10 Interface description

5.10.1 Ancillary data SuperHyway initiator

This initiator performs fixed burst size equal to half FIFO size. The FIFO size is calculated by taking into consideration all the real process of the ST40.

5.10.2 Video data SuperHyway initiator

This initiator performs fixed burst size equal to half FIFO size except for the first and last burst.The FIFO size is calculated by taking into consideration all the real process of the ST40.

Half FIFO size = sub multiple of the memory Page

Page frontier line start address line stop address nice boundary

ADCS 7225754C

1st Burst 2nd Burst 3rd Burst 4th Burst 5th Burst 6th Burst

Figure 72: Video data SuperHyway initiator

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5.10.3 CPU interface SuperHyway target

The width of the address bus is only 13:2 because all the registers are 32-bit registers and because at the top level of ST40, the request is sent to the digital input subsystem only if the CPU wants to speak to a digital input subsystem register. It means a predecoding of the address is needed to filter the request.

cpu_ck req r_req opc/add/be/data r_datar_opc

Figure 73: CPU timing interface

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Register mapping

5.11 Register mapping

Video Front End subsytem_start_Address

DVP0 Base Address

DVP1 Base Address

VTG Base Address

0x000

0x100

0x200

0x300

0x400

0x500

0x600

DVP0

DVP1

VTG unused unused unused unused

32-bit BYTE ADDRESS

31 24 23 16 15

Base Address selection

32-bit Register selection

Figure 74: VFE register map

8 7 0

Unused

64 x 32-bit

229

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230

5.12 Register descriptions

Register descriptions

DVP[n]_CTL DVP control register

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00

Address:

Type:

Reset value:

Table 16: DVP control register

DVP[n] base address + 0x00

Description

The DVP control register provides the operating mode of the DVP pipe, for the current viewport display.

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Register descriptions 231

ENA_VIDEO

ENA_ANCILLARY_DATA

EXT_SYNC_POLARITY

PHASE

Field Description

0:No video data are captured

1:Video data are captured into the device local memory validated by vertical synchronous signal

0:No ancillary data are captured

1:Ancillary data are captured into the device local memory validated by vertical synchronous signal

0:negative for both horizontal and vertical, no meaning if bit[4] = 0

1:positive for both horizontal and vertical non double-buffered (taken into account when loaded by CPU) first pixel signification of capture window

00: first sample is CB

01: first sample is Y

10: first sample is CR

11: first sample is Y validated by vertical synchronous signal

VSYNC_BOT_HALF_LINE_EN 0:VSOUT starts at the beginning of the last top field line

1:VSOUT starts at the middle of the last top field line

EXTERNAL_SYNC

REF

_POLARITY validated by vertical synchronous signal

0:Extract the H/V/F reference sync flags from embedded EAV/SAV codes

(H becomes H ref

, V becomes V ref

)

1:Use external HSI/VSI signals as sync reference

(HSI becomes H ref

, VSI becomes V ref

) non double-buffered (taken into account when loaded by CPU)

0:The negative edge of H ref the horizontal counter reset.

(as defined by bit[4]) is taken as reference for

1:The positive edge of H ref the horizontal counter reset

(as defined by bit[4]) is taken as reference for

Note: In EAV/SAV mode, 0 means SAV is the reference, 1 means EAV is the reference.

REF

_POLARITY 0:The negative edge of V ref

(as defined by bit[4]) is taken as reference for the vertical counter reset.

1:The positive edge of V ref

(as defined by bit[4]) is taken as reference for the vertical counter reset non double-buffered (taken into account when loaded by CPU)

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232 Register descriptions

Field

ENA_H-RESIZE

SYNCHRO_PHASE_NOTOK

MIX_CAPT_EN

Description

0:The horizontal resize engine is disabled

1:The horizontal resize engine is enabled

ENA_V-RESIZE validated by vertical synchronous signal

0:The vertical resize engine is disabled

1:The vertical resize engine is enabled validated by vertical synchronous signal

VALID_ANC_PAGE_SIZE_EXT 0 ANC_PAGE_SIZE extracted from ancillary data bit[5:0] from header sixth bit

1 ANC_PAGE_SIZE given by DVP[n]_APS register validated by vertical synchronous signal

0: external vertical and horizontal synchronization signals are presumed to be in phase to initialize a top field

1: external vertical and horizontal synchronization signals may be out of phase (in this case the vertical synchronization signal must be earlier or later than horizontal synchronization signal with a maximum of 1/4 of line length non double-buffered (taken into account when loaded by CPU) mixer data capture enable

MIX_CAPT_PREREQUEST loaded by VTG_VREF once MIX_CAPT_PREREQUEST set to 1 validated by vertical synchronous signal

DVP is configured to capture mixer data. This non double-buffered bit allows VTG_REF to load MIX_CAPT_EN into DVP, then data for mixer are captured directly non double-buffered (taken into account when loaded by CPU)

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Register descriptions 233

DVP[n]_TFO DVP top field offset

0x4

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

YDO XDO

Address:

Type:

Reset value:

DVP[n] base address + 0x4

Description

The DVP top field offset register provides the x,y location of the viewport top-left pixel, with respect to the current video timebase (one pixel = two samples).

Field Bit(s) Description

XDO [12:0] X location for the first pixel of the viewport (left), in sample unit

YDO [26:16] Y location for the first line of the viewport (top), with respect to field numbering

DVP[n]_TFS DVP top field stop

0x8

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

YDS XDS

Address:

Type:

Reset value:

DVP[n] base address + 0x8

Description

The DVP top field stop register provides the x,y location of the viewport top right pixel, with respect to the current video timebase (one pixel = two samples).

Field Bit(s) Description

XDS [12:0] X location for the last pixel of the viewport (right), in sample unit

YDS [26:16] Y location for the last line of the viewport (bottom), with respect to field numbering

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DVP[n]_BFO DVP bottom field offset

0xC

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

YDO XDO

Address:

Type:

Reset value:

DVP[n] base address + 0xC

Description

The DVP bottom field offset register provides the x,y location of the viewport bottom-left pixel, with respect to the current video timebase (one pixel = two samples).

Field Bit(s) Description

XDO [12:0] X location for the first pixel of the viewport (left), in sample unit

YDO [26:16] Y location for the first line of the viewport (top), with respect to field numbering

DVP[n]_BFS DVP bottom field stop

0x10

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

YDS XDS

Address:

Type:

Reset value:

DVP[n] base address + 0x10

Description

The DVP bottom field stop register provides the x,y location of the viewport bottom-right pixel, with respect to the current video timebase (one pixel = two samples).

Field Bit(s) Description

XDS [12:0] X location for the last pixel of the viewport (right), in sample unit

YDS [26:16] Y location for the last line of the viewport (bottom), with respect to field numbering

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Register descriptions 235

DVP[n]_VTP DVP video top field pointer

0x14

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BANK POINTER

Address:

Type:

Reset value:

DVP[n] base address + 0x14

Description

The DVP video top field pointer register is a 32-bit register containing the memory location for the top field first pixel to be stored, that is the top-left corner.

Field

POINTER

BANK

Bit(s) Description

[25:0] Top field first pixel byte address, in the selected 64 MByte bank (note that the whole captured video frame must be totally included into the same bank)

[31:26] 64-MByte bank number

DVP[n]_VBP DVP video bottom field pointer

0x18

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BANK POINTER

Address:

Type:

Reset value:

DVP[n] base address + 0x18

Description

The DVP video bottom field pointer register is a 32-bit register containing the memory location for the bottom field first pixel to be stored, that is the top-left corner.

Field

POINTER

BANK

Bit(s) Description

[25:0] Bottom field first pixel byte address, in the selected 64 MByte bank

(note that the whole captured video frame must be totally included into the same bank)

[31:26] 64 MByte bank number

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236 Register descriptions

DVP[n]_VMP DVP video memory pitch

0x1C

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PITCH VALUE

Address:

Type:

Reset value:

DVP[n] base address + 0x1C

Description

The DVP video memory pitch register contains the memory pitch for the captured video, as stored in the memory.

Field Bit(s) Description

PITCH_VALUE [12:0] Memory pitch for the captured video (Note: the pitch is the distance inside the memory, in byte unit, between two vertically adjacent pixels within a field)

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Register descriptions 237

DVP[n]_CVS DVP captured video size

0x20

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 1514131211 10 9 8 7 6 5 4 3 2 1 0

BOT_SIZE

RELATION

TOP_VIDEO_WINDOW_HEIGHT PIXMAP_WIDTH

Address:

Type:

Reset value:

DVP[n] base address + 0x20

Description

The DVP captured video size register provides the size of the displayed pixmap attached to the viewport.

Field Bit(s) Description

PIXMAP_WIDTH

TOP_VIDEO_WINDOW

_HEIGHT

[10:0] Pixmap width, in pixel unit

[26:16] Pixmap height, in line unit, being defined as the number of lines that must be read from memory for the current FIELD

IN AN INTERLACED DISPLAY

BOT_SIZE_RELATION [31:30 00: bottom size equal top size

01: bottom size equal top size plus 1

10: bottom size equal top size minus 1

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238 Register descriptions

DVP[n]_VSD DVP vertical synchronization delay

0xC

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

V_DELAY H_DELAY

Address:

Type:

Reset value:

DVP[n] base address + 0x24

Description

The DVP vertical synchronization delay register provides the size of the delay of

VSOUT :

Top field:

• H_DELAY is the delay of VSOUT from sample counter clear,

• V_DELAY is the delay from line counter clear,

• The total delay from sample counter clear is:

H_DELAY + V_DELAY * samples per line .

Bottom field:

• external synchros or (internal synchros with

DVP[N]_CTL.VSYNC_BOT_HALF_LINE_EN

= 0):

H_DELAY is the delay of VSOUT in samples units from external vertical synchro input,

V_DELAY is the delay from line counter clear,

• the total number of samples delay from vertical synchronization input is:

H_DELAY + V_DELAY * samples per line ,

• internal synchros with DVP[N]_CTL.VSYNC_BOT_HALF_LINE_EN

= 1 this delay becomes:

H_DELAY + V_DELAY * samples per line +

DVP[n]_HLL.HALF_LINE_LENGTH

to provide VSOUT on the bottom field at the middle of the last line of the top field.

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Register descriptions 239

The H_DELAY and V_DELAY values must be strictly lower than the number of samples per line.

Field

H_DELAY

V_DELAYT

Bit(s)

[12:0]

[26:16]

Description horizontal delay, in sample unit vertical delay, in line units

DVP[n]_HSD DVP horizontal synchronization delay

0xC

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved H_DELAY

Address:

Type:

Reset value:

DVP[n] base address + 0x28

Description

The DVP horizontal synchronization delay register provides the size of the delay of

HSOUT .

H_DELAY is the delay of hsout in sample units from the sample counter clear signal. The H_DELAY value must be strictly lower than the number of samples per line.

Field

H_DELAY

Bit(s)

[12:0]

Description horizontal delay, in sample unit

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240 Register descriptions

DVP[n]_HLL DVP half line length

0x20

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HALF_LINE_LENGTH

Address:

Type:

Reset value:

DVP[n] base address + 0x2C

Description

The DVP half line length register provides the number of samples necessary to have

VSOUT shifted one half line after HSOUT is in internal synchros mode and when

DVP[N]_CTL.VSYNC_BOT_HALF_LINE_EN

= 1.

Field Bit(s) Description

HALF_LINE_LENGTH [11:0] half line length, in sample unit

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Register descriptions 241

DVP[n]_HSRC DVP horizontal sample rate converter

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x30

Address:

Type:

Reset value:

DVP[n] base address + 0x30

Description

The DVP horizontal sample rate converter register provides the configuration for the horizontal sample rate converter.

Field Bit(s) Description

HSRC_INCREMENT [9:0] The horizontal sample rate converter state-machine increment, in 2.8 format

HSRC_INITIAL_PHASE [18:16] The horizontal sample rate converter state-machine initial phase on top field [0:7]

ENABLE_H_FILTER [24] 0: h filter disabled

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PRELIMINARY DATA

242 Register descriptions

DVP[n]_HFC DVP horizontal filter coefficients (register

file)

0x44

0x48

0x4C

0x50

0x54

0x34

0x38

0x3C

0x40

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

K 0.3

K 0.2

K 0.1

K 0.0

K 1.2

K 2.1

K 3.0

K 1.1

K 2.0

K 2.4

K 1.0

K 1.4

K 2.3

K 0.4

K 0.3

K 2.2

K 3.4

K 4.3

K 5.2

K 6.1

K 7.0

K 3.3

K 4.2

K 5.1

K 6.0

K 6.4

K 3.2

K 4.1

K 5.0

K 5.4

K 6.3

K 3.1

K 4.0

K4.4

K 5.3

K 6.2

0x58 K 7.4

Address:

Type:

Reset value:

K 7.3

K 7.2

DVP[n] base address + 0x30 to 0x58

K 7.1

Description

The DVP horizontal filter coefficients register file consists of ten registers. It contains the 40 coefficients used for the 8-phase 5-tap digital filter of the horizontal sample rate converter. The CPU sees these registers as a group of ten 32-bit registers.

Field

K[i].[j]

Bit(s) Description

8 bits Coefficient j of subfilter i (subposition i)

Format S1.6: 8 bit signed with 1.0 encoded as 0x40

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Register descriptions 243

DVP[n]_VSRC DVP vertical sample rate converter

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x60 VSRC_INCREMENT

Address:

Type:

Reset value:

DVP[n] base address + 0x60

Description

The DVP vertical sample rate converter register provides the configuration for the vertical sample rate converter.

Field Bit(s) Description

VSRC_INCREMENT [9:0] The vertical sample rate converter state-machine increment, in

2.8 format

VSRC_INITIAL_PHASE [18:16] The vertical sample rate converter state-machine initial phase on top field, [0:7]

ENABLE_V_FILTER [24] 0: v filter disabled

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DVP[n]_VFC DVP vertical filter coefficients (register file)

0x64

0x68

0x6C

0x70

0x74

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

K 1.0

K 0.2

K 0.1

K 0.0

K 2.1

K 3.2

K 5.0

K 6.1

K 2.0

K 3.1

K 4.2

K 6.0

K 1.2

K 3.0

K 4.1

K 5.2

K 1.1

K 2.2

K 4.0

K 5.1

0x78 K 7.2

Address:

Type:

Reset value:

K 7.1

K 7.0

DVP[n] base address + 0x64 to 0x78

K 6.2

Description

The DVP vertical filter coefficients register file contains the 24 coefficients used for the 8-phase 3-tap digital filter of the vertical sample rate converter. The CPU sees these registers as a group of six 32-bit registers.

K[i].[j]

Field Bit(s) Description

8 bits Coefficient j of subfilter i (subposition i)

Format S1.6: 8 bit signed with 1.0 encoded as 0x40

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Register descriptions 245

DVP[n]_ITM DVP interrupt mask

0x98

3130292828262524232221201918171615141312111098 7 6

Reserved

Address:

Type:

Reset value:

DVP[n] base address + 0x98

5 4

VST

VSB

2 1

Reserved

Description

Any bit set in this register enables the corresponding interrupt in the DVP interrupt output line. An interrupt is generated.

Whenever a bit in the DVP[N]_STA register changes from 0 to 1 and the corresponding mask bit is set.

DVP[n]_ITS DVP interrupt status

0x9C

3130292828262524232221201918171615141312111098 7 6

Reserved

Address:

Type:

Reset value:

DVP[n] base address + 0x9C

5 4

VST

VSB

2 1

Reserved

Description

When a bit in the DVP_STA register changes from 0 to 1, the corresponding bit in the DVP_ITS register is set, independent of the state of DVP[N]_ITM . If any set

DVP[N]_ITS bit is unmasked, the line DVP interrupt output line is asserted. The reading of DVP[N]_ITS clears all bits in that register. When DVP[N]_ITS is zero the

DVP interrupt output line returns de-asserted.

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DVP[n]_STA DVP status register

0xA0

3130292828262524232221201918171615141312111098 7 6

Reserved

Address:

Type:

Reset value:

DVP[n] base address + 0xA0

5 4

VST

VSB

2 1

Reserved

Description

This register contains a set of bits which represents the status of the DVP. Any change from 0 to 1 of any of these bits sets the corresponding bit of the DVP[N]_ITS register, and can thus potentially cause an interrupt on the DVP interrupt output line. VST and VSB are pulses and are unlikely ever to be read as 1.

Field

VSB

VST

Description

VSYNC bottom Set for a short time at the beginning of the bottom field, corresponding to the rising edge of the internal BNOTT signal.

VSYNC top Set for a short time at the beginning of the top field, corresponding to the falling edge of the internal BNOTT signal.

DVP[n]_LNSTA Line number status

0xA4

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LINE_NUMBER_STATUS

[10:0]

Address:

Type:

Reset value:

VTG base address + 0xA4

Description

This register is loaded on the VTG VREF output signal (vertical synchronization) with the value of the DVP line counter.

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DVP[n]_HLFLN DVP half lines per vertical

0xA8

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HLFLN[11:0]

Address:

Type:

Reset value:

DVP[n] base address + 0xA8

Description

This register specifies the number of half lines per vertical period.

This value is used when the bit DVP[N]_CTL.SYNCHRO_PHASE_NOTOK

is set, then the vertical synchronization is forced to be in phase with the horizontal synchronization signal to generate a top field. The external vertical signal is ignored.

DVP[n]_ABA DVP ancillary data base address

0xAC

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BANK ADDRESS Write 0

Address:

Type:

Reset value:

DVP[n] base address + 0xAC

Description

The DVP ancillary data base address register is a 32-bit register containing the memory location for the first ancillary data page. The buffer must be aligned on a

128-bit word address boundary.

Field

ADDRESS

BANK

Bit(s) Description

[25:0] Base address for the ancillary data buffer, in the selected 64 MByte bank

[31:26] 64 MByte bank number

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DVP[n]_AEA DVP ancillary data end address

0xB0

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BANK ADDRESS Write 0

Address:

Type:

Reset value:

DVP[n] base address + 0xB0

Description

The DVP ancillary data end address register is a 32-bit register containing the last memory location for the ancillary data buffer. For a 128-bit word address the address counter wraps to the base address location.

Field

ADDRESS

BANK

Bit(s) Description

[25:0] Base address for the ancillary data buffer, in the selected 64 MByte bank

[31:26] 64 MByte bank number (programmed value must match the

DVP[N]_ABA bank)

DVP[n]_APS DVP ancillary data page size

0xB4

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PAGE_SIZE Write 0

Address:

Type:

Reset value:

DVP[n] base address + 0xB4

Description

The DVP ancillary data page size register provides the size in bytes of the memory page used for a single ancillary data packet. The size granularity is 16 bytes, the maximum size is 4096 bytes.

Field Bit(s) Description

PAGE_SIZE [11:0] Memory size allocated to an ancillary data packet

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DVP[n]_PKZ DVP maximum packet size

0xFC

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PACKET_S

IZE

Address:

Type:

Reset value:

DVP[n] base address + 0xFC

Description

The DVP[N]_PKZ register is a 3-bit register for controlling the maximum size of a data packet during a SuperHyway transaction.

Field Bit(s)

PACKET_SIZE [2:0]

Description

Maximum packet size during a SuperHyway transaction

000: Message size

001: 16 SuperHyway words

010: 8 SuperHyway words

011: 4 SuperHyway words

100: 2 SuperHyway words

101: 1 SuperHyway words

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250 Register descriptions

VTG_MOD VTG mode of operation

0x40

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODE

Address:

Type:

Reset value:

VTG base address + 0x24

Description

The DVP captured video size register provides the size of the displayed pixmap attached to the viewport.

Field

MODE 1:0

Bit(s) Description

00 master mode

01 slave by dvp_0

10 slave by dvp_1

VTG_CLKLN Clocks per line

0x28

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CLKLN[12:0]

Address:

Type:

Reset value:

VTG base address + 0x28

Description

This register specifies the total number of sample clock cycles per horizontal period, that is the horizontal complete line length.

If the frequency of VTG clock is twice the pixel frequency then CLKLN is 13 bits wide.

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VTG_H_HD VTG HSYNC output falling and rising edge

0x2C

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HD_HS[12:0] HD_HO[12:0]

Address:

Reset value:

VTG base address + 0x2C

Description

This register determines the rising sample position of the HSYNC signal pin output pulse relative to the sample counter clear.

The HSYNC output rises from 0 to 1 level when the sample counter is equal to

VTG_H_HD.HD_HO

and falls from 1 to 0 when the sample counter is equal to

VTG_H_HD.HD_HS

Note that the order of HD_HO and HD_HS determines the polarity of the HSYNC signal pin.

If the frequency of VTG clock is twice the pixel frequency then HDO is 13 bits width.

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VTG_TOP_V_VD VTG VSYNC vertical top field line number output falling and rising edge

0x30

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VD_TOP_VS[10:0] VD_TOP_VO[10:0]

Address:

Reset value:

VTG base address + 0x30

00000000

Description

This register determines the line position edges of the VSYNC signal pin output pulse relative to line counter clear.

The VSYNC output will rise from 0 to 1 level when the line counter is equal to

VD_TOP_VO and will fall from 1 to 0 when the line counter is equal to VD_TOP_VS .

Note that the order of VD_TOP_VO and VD_TOP_VS determines the polarity of the

VSYNC signal pin, if VD_TOP_VO = VD_TOP_VS it is the order of VD_TOP_HO and

VD_TOP_HS which determines this polarity.

If the frequency of VTG clock is twice the pixel frequency then HDS is 13 bits width.

Note that the minimum value of VD_TOP_VO is 001h.

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VTG_BOT_V_VD VTG vertical bot field line number output falling and rising edge

0x34

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VD_BOT_VS[10:0] VD_BOT_VO[10:0]

Address:

Type:

Reset value:

VTG base address + 0x34

Description

This register determines the line position edges of the VSYNC signal pin output pulse relative to line counter clear.

The VSYNC output will rise from 0 to 1 level when the line counter is equal to

VD_BOT_VO and will fall from 1 to 0 when the line counter is equal to VD_BOT_VS .

Note that the order of VD_BOT_VO and VD_BOT_VS determines the polarity of the

VSYNC signal pin, if VD_BOT_VO = VD_BOT_VS it is the order of

VTG_BOT_V_HD.VD_BOT_HO

and VTG_BOT_V_HD.VD_BOT_HS

which determines this polarity.

Note that the min value of VD_TOP_VO is 000h.

If the frequency of VTG clock is twice the pixel frequency then HDS is 13 bits width.

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254 Register descriptions

VTG_TOP_V_HD VTG VSYNC vertical top field sample number output rising and falling edge

0x38

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VD_TOP_HS[12:0] VD_TOP_HO[12:0]

This register determines the line position edges of the VSYNC signal pin output pulse relative to sample counter clear.

The VSYNC output will rise from 0 to 1 level when the line counter is equal to

VD_TOP_HO and will fall from 1 to 0 when the line counter is equal to VD_TOP_HS .

Note that the order of VD_TOP_HO and VD_TOP_HS determines the polarity of the

VSYNC signal pin, if VTG_TOP_V_VD.VD_TOP_VO

VTG_TOP_V_VD.VD_TOP_VS

, else the order of VD_TOP_VO and VD_TOP_VS determines the polarity of the VSYNC signal pin.

If the frequency of VTG clock is twice the pixel frequency then HDS is 13 bits width.

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Register descriptions 255

VTG_BOT_V_HD VTG VSYNC vertical bottom field sample number output rising and falling edge

0x3C

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VD_BOT_HS[12:0] VD_BOT_HO[12:0]

This register determines the line position edges of the VSYNC signal pin output pulse relative to sample counter clear.

The VSYNC output will rise from 0 to 1 level when the line counter is equal to

VD_BOT_HO and will fall from 1 to 0 when the line counter is equal to VD_BOT_HS .

Note that the order of VD_BOT_HO and VD_BOT_HS determines the polarity of the

VSYNC signal pin if VTG_BOT_V_VD.VD_BOT_VO

VTG_BOT_V_VD.VD_BOT_VS

, else the order of VD_BOT_VO and VD_BOT_VS determines the polarity of the VSYNC signal pin.

If the frequency of VTG clock is twice the pixel frequency then HDS is 13 bits width.

The value given to VD_BOT_HDO allows the rising edge of VSYNC to be adjusted between two HSYNC signals to be able to start an analog bottom field. The normal value is VTG_H_HD.HD_HO

+ CLKLN /2.

If HD_HO is 0 and VD_BOT_VO is 0 take care that line counter is cleared when sample count = CLKLN/2-1 and the first value of sample counter is CLKLN /2 when line counter is 0, then the correct value for VD_BOT_HDO must be CLKLN /2, under this value VSYNC does not start for bottom field.

VTG_HLFLN VTG half lines per vertical

0x40

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HLFLN[11:0]

This register specifies the number of half lines per vertical period.

An odd value in this register indicates interlaced output and an even value indicates progressive output.

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256 Register descriptions

VTG_DRST Video timing generator reset

Address:

Type:

Reset value:

VTG base address + 0x48

Description

Writing to this register resets the sample counter and line counter of the VTG. The reset is just activated once on writing.

When activated, this reset activates VREF and HREF . If VTG is in interlaced mode, that is the half lines per vertical number is odd, a top field is generated.

VTG_ITM VTG interrupt mask

0x98

3130292828262524232221201918171615141312111098 7 6

Reserved

Address:

Type:

Reset value:

VTG base address + 0x98

5 4

VST

VSB

2 1

Reserved

Description

Any bit set in this register will enable the corresponding interrupt in VTG_IRQ line.

An interrupt is generated whenever a bit in the VTG_STA register changes from 0 to

1 and the corresponding mask bit is set.

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VTG_ITS VTG interrupt status

0x9C

3130292828262524232221201918171615141312111098 7 6

Reserved

Address:

Type:

Reset value:

VTG base address + 0x9c

5 4

VST

VSB

2 1

Reserved

Description

When a bit in the VTG_STA register changes from 0 to 1, the corresponding bit in the VTG_ITS register is set, independent of the state of VTG_ITM . If any set

VTG_ITS bit is unmasked, the line VTG_IRQ is asserted. The reading of VTG_ITS clears all bits in that register. When VTG_ITS is zero the VTG_IRQ line returns de-asserted.

VTG_STA VTG status register

0xA0

3130292828262524232221201918171615141312111098 7 6

Reserved

Address:

Type:

Reset value:

VTG base address + 0xa0

5 4

VST

VSB

2 1

Reserved

Description

This register contains a set of bits which represents the status of the VTG. Any change from 0 to 1 of any of these bits sets the corresponding bit of the VTG_ITS register, and can thus potentially cause an interrupt on the VTG_IRQ line.

VST and

VSB are pulses and are unlikely ever to be read as 1.

Field

VSB

VST

Description

VSYNC bottom Set for a short time at the beginning of the bottom field, corresponding to the rising edge of the internal BNOTT signal.

vsync top Set for a short time at the beginning of the top field, corresponding to the falling edge of the internal BNOTT signal.

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Register descriptions

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Pixel clock controller (PIXCLK)

6.1 Overview

This register interface allows SuperHyway control of:

• pixel clock enable,

• CLOCKGENB PLL2 as the source for internal generated pixel clock,

• teletext data source.

6.2 Register overview

Register name Description Type

Address offset

0x000 PIXCLKCON.VCR

Version control register, see

Table 18 on page 260

PIXCLKCON.CONTROL

Pixel clock control register, see

Table 19 on page 260

Table 17: Address map

RW 0x008

Access size

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6.3 Register definitions

6.3.1 PIXCLKCON.VCR

PIXCLKCON.VCR

0x00

Field Bits Size Volatile

MVERS [16:31] 16

Operation

Read

Write

Hard reset

Module version

Synopsis

Used to indicate module version

Returns current value

Ignored

See datasheet

Table 18: PIXCLKCON.VCR

Register definitions

Type

6.3.2 PIXCLKCON.CONTROL

This register controls the selection of pixel clock and associated signals.

PIXCLKCON.CONTROL

pixel clock control register

Field

CLKEN

Bits Size Volatile

0x08

Synopsis

Operation

Read

Write

Hard reset

1 Enable the pixclock2x and pixclock to the video subsystem

0: Clock held low to video subsystem

1: Clock active to video subsystem

Returns current value

Updates current value

See datasheet

Table 19: PIXCLKCON.CONTROL

Type

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Register definitions 261

PIXCLKCON.CONTROL

pixel clock control register

Field

TTXTSRC

Bits

Read

Write

Hard reset

[2:31]

Operation

Read

Write

Size

Operation

HARD reset

Volatile

0x08

Synopsis

Teletext control signal source

Table 19: PIXCLKCON.CONTROL

Type

0: Teletext data source from Teletext DMA unit.

1: Teletext source from external pins (use when operating from DVP clock only).

Returns current value

Updates current value

See datasheet

Reserved

Undefined

Write 0

See datasheet

Res

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Register definitions

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Appendices

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Register address list

Module

Blitter

Register name

GAM_BLT_ACK

GAM_BLT_CCO

Blitter

GAM_BLT_CML

GAM_BLT_CTL

GAM_BLT_CWO

GAM_BLT_CWS

GAM_BLT_FF0

GAM_BLT_FF1

GAM_BLT_FF2

GAM_BLT_FF3

Description

ALU and color key control, see

GAM_BLT_ACK on page 45

CLUT color conversion operators, see

GAM_BLT_CCO on page 39

CLUT memory location, see

GAM_BLT_CML on page 39

Blitter control, see

GAM_BLT_CTL on page 17

Clipping window offset, see

GAM_BLT_CWO on page 37

Clipping window stop, see

GAM_BLT_CWS on page 38

Flicker filter 0, see

GAM_BLT_FF0 on page 43

Flicker filter 1, see

GAM_BLT_FF1 on page 44

Flicker filter 2, see

GAM_BLT_FF2 on page 44

Flicker filter 3, see

GAM_BLT_FF3 on page 45

Address offset

0x80

0x58

0x5C

0x00

0x50

0x54

0x70

0x74

0x78

0x7C

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Module

Blitter

Register name

GAM_BLT_HFC[1:10]

GAM_BLT_HFP

Blitter

GAM_BLT_INS

GAM_BLT_KEY1

GAM_BLT_KEY2

GAM_BLT_NIP

GAM_BLT_PKZ

GAM_BLT_PMK

GAM_BLT_RSF

GAM_BLT_RST

GAM_BLT_RZC

GAM_BLT_S1BA

GAM_BLT_S1CF

GAM_BLT_S1SZ

GAM_BLT_TSZ

GAM_BLT_S1TY

Description

Horizontal coefficients, see

GAM_BLT_HFC1-10 on page 52

Horizontal filter coefficients pointer, see

GAM_BLT_HFP on page 42

Instruction register, see

GAM_BLT_INS on page 21

Color key 1, see

GAM_BLT_KEY1 on page 48

Color key 2, see

GAM_BLT_KEY2 on page 49

Next instruction pointer, see

GAM_BLT_NIP on page 20

Packet size control, see

GAM_BLT_PKZ on page 51

Plane mask, see

GAM_BLT_PMK on page 49

Resize scaling factor, see

GAM_BLT_RSF on page 43

Raster scan trigger, see

GAM_BLT_RST on page 50

2D resize control, see

GAM_BLT_RZC on page 41

Source 1 base address, see

GAM_BLT_S1BA on page 24

Source 1 color fill, see

GAM_BLT_S1CF on page 29

Source 1 target window size, see

GAM_BLT_S1SZ/GAM_BLT_TSZ on page 28

Source 1 type, see

GAM_BLT_S1TY on page 25

Address offset

0x00 to 0x24

0x64

0x18

0x84

0x88

0x10

0xFC

0x8C

0x6C

0x90

0x60

0x1C

0x2C

0x28

0x20

STMicroelectronics

SH-4, ST40 System Architecture, Volume 3: Video Devices ADCS 7225754C

Blitter

Module

Blitter

Register name

GAM_BLT_S1XY

GAM_BLT_S2BA

Blitter

GAM_BLT_S2CF

GAM_BLT_S2SZ

GAM_BLT_S2TY

GAM_BLT_S2XY

GAM_BLT_STA1

GAM_BLT_STA2

GAM_BLT_STA3

GAM_BLT_TBA

GAM_BLT_TTY

GAM_BLT_TXY

GAM_BLT_USR

GAM_BLT_VFC[1:10]

GAM_BLT_VFP

GAM_BLT_XYL

PRELIMINARY DATA

267

Description

Source 1 XY location, see

GAM_BLT_S1XY on page 27

Source 2 base address, see

GAM_BLT_S2BA on page 29

Source 2 color fill, see

GAM_BLT_S2CF on page 33

Source 2 window size, see

GAM_BLT_S2SZ on page 33

Source 2 type, see

GAM_BLT_S2TY on page 30

Source 2 XY location, see

GAM_BLT_S2XY on page 32

Blitter status register 1, see

GAM_BLT_STA1 on page 17

Blitter status register 2, see

GAM_BLT_STA2 on page 18

Blitter status register 3, see

GAM_BLT_STA3 on page 19

Target base address, see

GAM_BLT_TBA on page 33

Target type, see

GAM_BLT_TTY on page 34

Target XY location, see

GAM_BLT_TXY on page 36

User specific register, see

GAM_BLT_USR on page 20

Vertical coefficients, see

GAM_BLT_VFC1-10 on page 53

Vertical filter coefficients pointer, see

GAM_BLT_VFP on page 42

XYL control, see

GAM_BLT_XYL on page 50

Address offset

0x24

0x30

0x40

0x3C

0x34

0x38

0x04

0x08

0x0C

0x44

0x48

0x4C

0x14

0x30 to 0x54

0x68

0x94

ADCS 7225754C

STMicroelectronics

SH-4, ST40 System Architecture, Volume 3: Video Devices

PRELIMINARY DATA

268

Module

Blitter

Register name

GAM_BLT_XYP

Compositor

(Cursor)

Compositor

(Cursor)

Compositor

(DVP)

Compositor

(Mixer)

Compositor

(Mixer)

Compositor

(Mixer)

Compositor

(Mixer)

Compositor

(Mixer)

Compositor

(Cursor)

Compositor

(Cursor)

Compositor

(Cursor)

Compositor

(Cursor)

Compositor

(Cursor)

Compositor

(Cursor)

Compositor

(Cursor)

GAM_CUR_AWE

GAM_CUR_AWS

GAM_CUR_CML

GAM_CUR_CTL

GAM_CUR_PKZ

GAM_CUR_PML

GAM_CUR_PMP

GAM_CUR_SIZE

GAM_CUR_VPO

GAM_DVP_CTL

GAM_MIX_AVO

GAM_MIX_AVS

GAM_MIX_BCO

GAM_MIX_BCS

GAM_MIX_BKC

Description

XY subinstruction pointer, see

GAM_BLT_XYP on page 51

Active window end, see

GAM_CUR_AWE on page 85

Active window start, see

GAM_CUR_AWS on page 85

CLUT memory location, see

GAM_CUR_CML on page 84

Cursor control, see

GAM_CUR_CTL on page 82

Packet size control, see

GAM_CUR_PKZ on page 86

First pixel memory location, see

GAM_CUR_PML on page 83

Pixmap memory pitch, see

GAM_CUR_PMP on page 83

Pixmap memory size, see

GAM_CUR_SIZE on page 84

Viewport offset, see

GAM_CUR_VPO on page 82

DVP control register, see

GAM_DVP_CTL on page 79

Active video offset, see

GAM_MIX_AVO on page 77

Active video stop, see

GAM_MIX_AVS on page 78

Background color offset, see

GAM_MIX_BCO on page 75

Background color stop, see

GAM_MIX_BCS on page 76

Background color, see

GAM_MIX_BKC on page 74

0x000

0x528

0x52C

0x50C

0x014

0x018

0x01C

0x00C

0x510

0x504

Address offset

0x98

0x02C

0x028

0x020

0x000

0x0FC

STMicroelectronics

SH-4, ST40 System Architecture, Volume 3: Video Devices ADCS 7225754C

Module

Compositor

(Mixer)

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

Register name

GAM_MIX_CTL

GDP[ N ]_AGC

GDP[ N ]_CTL

GDP[ N ]_HFC[0:9]

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

Compositor

(GDP)

GDP[ N ]_HFP

GDP[ N ]_HSRC

GDP[ N ]_KEY1

GDP[ N ]_KEY2

GDP[ N ]_NVN

GDP[ N ]_PKZ

GDP[ N ]_PML

GDP[ N ]_PMP

GDP[ N ]_SIZE

GDP[ N ]_VPO

GDP[ N ]_VPS

PRELIMINARY DATA

269

Description

Mixer control register, see

GAM_MIX_CTL on page 73

Alpha gain constant, see

GDP[n]_AGC on page 90

GDP control register, see

GDP[n]_CTL on page 87

GDP HF Coefficient register 0 to 9, see

GDP_HFC0 on page 99 to

GDP_HFC9 on page 102

Horizontal filter pointer, see

GDP[n]_HFP on page 99

Horizontal sample rate converter, see

GDP[n]_HSRC on page 91

Key 1, see

GDP[n]_KEY1 on page 97

Key 2, see

GDP[n]_KEY2 on page 98

Next viewport node, see

GDP[n]_NVN on page 96

Maximum packet size, see

GDP[n]_PKZ on page 102

Pixmap memory location, see

GDP[n]_PML on page 94

Pixmap memory pitch, see

GDP[n]_PMP on page 94

Pixmap size, see

GDP[n]_SIZE on page 95

Viewport offset, see

GDP[n]_VPO on page 93

Viewport stop, see

GDP[n]_VPS on page 93

Address offset

0x500

0x[n]04

0x[n]00

0x[n]40 to 0x[n]64

0x[n]30

0x[n]08

0x[n]28

0x[n]2C

0x[n]24

0x[n]FC

0x[n]14

0x[n]18

0x[n]1C

0x[n]0C

0x[n]10

ADCS 7225754C

STMicroelectronics

SH-4, ST40 System Architecture, Volume 3: Video Devices

PRELIMINARY DATA

270

Module

Compositor

(GDP)

DAC

DENC

Register name Description

GDP[ N ]_VSRC Vertical sample rate converter, see

GDP[n]_VSRC on page 92

DENC_DAC_IF.CONTROL1

DAC interface control register 1, see

DENC_DAC_IF.CONTROL2

DAC interface control register 2, see

DENC_DAC_IF.DATA1

DENC_DAC_IF.DATA2

DAC CPU interface data register 1, see

DAC CPU interface data register 2, see

DENC_DAC_IF.VCR on page 105

DENC_DAC_IF.VCR

DENC_DAC_IF_TIMING

DEN_CCF1

Version control register, see

Minimum number of cycles allowed between falling edges of the

NOTCS signal to the DENC, see

DENC_DAC_IF.TIMING on page 109

Closed caption characters extended data for field 1, see

DEN_CCF1 on page 187

DEN_CCF2

DEN_CFCOEF[0:8]

Closed caption characters extended data for field 2, see

DEN_CCF1 on page 187

Chroma filter coefficient, see

DEN_CFCOEF[0:8] on page 196

Address offset

0x[n]20

0x10010

0x10020

0x10018

0x10028

0x10000

0x00800

0x00138,

0x00140

0x00148,

0x00150

0x00240,

0x00248,

0x00250,

0x00258,

0x00260,

0x00268,

0x00270,

0x00278,

0x00280

STMicroelectronics

SH-4, ST40 System Architecture, Volume 3: Video Devices ADCS 7225754C

Module

DENC

Register name

DEN_CFG0

DEN_CFG1

DENC

DEN_CFG2

DEN_CFG3

DEN_CFG4

DEN_CFG5

DEN_CFG6

DEN_CFG7

DEN_CFG8

DEN_CFG9

DENC

DEN_CGMS[1:3]

DEN_CID

DEN_CLF1

DEN_CLF2

PRELIMINARY DATA

271

Description

Configuration register 0, see

DEN_CFG0 on page 158

Configuration register 1, see

DEN_CFG1 on page 159

Configuration register 2, see

DEN_CFG2 on page 161

Configuration register 3, see

DEN_CFG3 on page 163

Configuration register 4, see

DEN_CFG4 on page 165

Configuration register 5, see

DEN_CFG5 on page 166

Configuration register 6, see

DEN_CFG6 on page 167

Configuration register 7, see

DEN_CFG7 on page 168

Configuration register 8, see

DEN_CFG8 on page 170

Chroma delay and luma filter control, see