STMicroelectronics SUPERH SH-4, ST40 SYSTEM ARCHITECTURE VOLUME 1 Reference Manual

State associated with channel

2, see

State associated with channel

3, see

State associated with channel

4, see

Type Address offset Size

0x200 to 0x2F8 -

0x300 to 0x3F8

0x400 to 0x4F8

0x500 to 0x4F8 -

0x600 to 0xFF8 -

Table 19: DMAC registers

2 types of DMA channels are specified for the DMAC, channel 0 supports a number of multiplexed subchannels, whilst channels 1 to 4 support a single channel which is able to interpret linked lists.

This is achieved by mapping part of the control state for the DMA channel into structures stored in main memory. The tables below show the organisation of the registers for each DMA channel, and where appropriate the organisation of the state which is stored as a structure in main memory. In each case the location of the register is shown as an offset from a base address.

Registers in channels 0 to 4 are referred to in this document as

DMA.CHAN[ N ].REGISTERNAME

where [n] refers to the channel number and is an integer between 0 and 4.

A description of each register and its operation is included later in this document.

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Address map 47

4.2.1 Channel 0: multiplexed DMA channel

Register name

IDENTITY

ENABLE

DISABLE

STATUS

ACTION

POINTER

SUBBASE

SUBENABLE

SUBDISABLE

SUBINT_ENB

SUBINT_DIS

Local state

Description Type

Address offset

Memory offset

Access size

0x00 32 Channel identity, see

Table 31 on page 71

Enable a control bit associated with this channel, see

Table 32 on page 75

Disable a control bit associated with this channel, see

Status of a control bit associated with this channel, see

Cause action on a control bit associated with this channel, see

Pointer to the current or last register memory image, see

Table 36 on page 85

Base pointer to the table of register images in main memory, see

Table 38 on page 88

Subchannel enable, see

Table 39 on page 89

Subchannel disable, see

Table 40 on page 90

Subchannel interrupt enable, see

Table 41 on page 90

Subchannel interrupt disable, see

Table 42 on page 91

Table 20: Channel 0 registers

0x08

0x10

0x18

0x20

0x28

0x30

0x38

0x40

0x48

0x50 -

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48 Address map

Register name

SUBINT_STAT Local

Reserved

SUBINT_ACT

CONTROL

COUNT

SAR

DAR state

Description

Subchannel interrupt status, see

Table 43 on page 91

Type

Address offset

Memory offset

Access size

0x58 32

0x70 to

0x78

0x60 32

Memory mapped state

Subchannel interrupt action, see

Table 44 on page 92

Channel control,

Channel count, see

Channel source address, see

Channel destination address, see

Channel identity, see Table 31 on page 71

0x80

0x88

0x90

0x98

0x00

0x04

0x08

0x0c

Reserved 0x60 to

0xf8

Table 20: Channel 0 registers

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Address map

4.2.2 Channels 1 to 4: linked list DMA channel

Register name

IDENTITY

ENABLE

DISABLE

STATUS

ACTION

POINTER

REQUEST

Reserved

CONTROL

COUNT

SAR

Description Type

Register offset

Memory offset

Size

0x00 32 Local state

Enable or set a control bit associated with this channel,

see Table 32 on page 75

Disable or reset a control bit associated with this channel, see

Status of a control bit associated with this channel, see

Cause action on a control bit associated with this channel, see

register set, see Table 36 on page 85

Pointer to the current or last

The number of the request associated with this channel, see

Table 37 on page 86

0x08

0x10

0x18

0x20

0x28

0x30

Memory mapped state

Channel control, see

Channel count, see

Channel source address, see

Table 21: Channels 1 to 4 registers

0x38 to

0x78

0x80

0x88

0x90

0x00

0x04

0x08

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Register name

DAR

NEXT_PTR

SRC_LENGTH

SRC_STRIDE

DST_LENGTH

DST_STRIDE

Reserved

Description Type

Register offset

Memory offset

Size

0x98 0x0c 32 Memory mapped state

Channel destination address, see

Table 54 summarizes the PIO registers.

Pointer to the next register set, see

Table 49 on page 102

2D source line length, see

Table 50 on page 103

2D source line stride, see

Table 51 on page 104

2D destination line length, see

Table 52 on page 105

2D destination line stride, see

Table 53 on page 106

0xA0

0xA8

0xB0

0xB8

0xC0

0x10

0x14

0x18

0x1c

0x20

0xC8 to

0xF8

Table 21: Channels 1 to 4 registers

The DMAC supports up to 32 independent request sources. The peripheral to request number allocation is described in the relevant product datasheet.

The user may associate any request number with a specific DMA channel by programming the associated control state. This association is automatic for channel

0 and can be set by programming DMA.CHAN[ N ].REQUEST

for channels 1 to 4.

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4.4.1 DMA transfer procedure

All DMA channels use the same basic transfer model and are able to transfer units of data from a source data structure to a destination data structure via an internal de-coupling buffer. This is shown in

Figure 9

Is DMAC enabled?

Pace condition?

Check count and address alignment

Load source data unit

Push data unit into channel buffer

Update source count,

Update address

Source count

≠

Source state machine

Idle

Is DMAC enabled?

Trigger condition?

Is DMAC enabled?

Pace condition?

Check count and address alignment

If data available, pop destination data unit

Store data unit

Update destination count, and address

Destination count

≠

Destination state machine

Generate interrupt

Update registers

Figure 9: DMA operation

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DMA operation

The DMA operation is begun when all registers associated with the channel are programmed, and all enables associated with that channel are set.

Depending on the timing model associated with the DMA channel, the transfer may self-start or wait for a peripheral to assert a request before commencing a transfer.

The transfer of data occurs from a source memory structure to a destination memory structure via an internal de-coupling buffer using a specified data unit size. As the source and destination unit sizes may differ the DMAC may be required to load multiple units from the source for every destination unit or vice-versa.

A transfer will continue until 1 of the following conditions occurs.

Stall

When a stall condition occurs the register DMA.CHAN[

].ENABLE.STALL

is set. All transfers on this channel are suspended until the stall condition is cleared and software has reset the DMA.CHAN[ N ].CONTROL.STALL

Error

An error may occur if the DMAC attempts an access which is unalignable with the specified transfer unit (address or unit size) with alignment checks enabled or the system indicates that a memory operation has failed. This will force the DMA channel to stop until the error is cleared and the DMA channel reprogrammed.

Disable

The channel may be disabled at any time by a write to DMA.DISABLE[ N ] ,

DMA.CHAN[

].DISABLE

. The channel will be stopped until re-enabled by a second write to DMA.ENABLE

or DMA.CHAN[

].ENABLE.

Completion

Completion occurs when DMA.CHAN[

].COUNT

reaches 0 , and the last transfer has completed. On completion the DMAC may interrupt the CPU or trigger an update function refreshing the DMA register state from memory and starting a subsequent transfer.

If an interrupt occurs the CPU is required to intervene before the DMA may continue or a further DMA begin on the same channel.

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4.4.2 DMA transfer units

The DMAC is able to transfer data between the source and destination using units of specific size. Supported unit sizes include 1, 2, 4, 8 16 or 32 bytes. This is defined as the SRC_UNIT and DST_UNIT fields of in the DMA.CHAN[ N ].CONTROL

registers for linked list channels, and SRC_UNIT for channel 0.

All transfers are aligned and of a specific size, the DMAC will not generate part word accesses. If the transfer if not alignable to the selected transfer unit, the

DMAC will either indicate an alignment error or use the largest alignable transfer unit equal to or smaller than the selected unit.

If the alignment error interrupt is enabled the channel will be stalled until the error condition is cleared. This is indicated by asserting the associated error and setting the bits with the DMA.VCR.STATUS

and DMA.ERROR

registers.

As channels 1 to 4 support differing unit sizes for the source and destination structures, the DMA channel will segment and assemble the appropriate number of smaller data units to allow the larger unit to be transferred. Channel 0 will use the same transfer unit for both the source and destination transfers.

4.4.3 DMA timing model

The DMAC is able support 3 timing modes. This is selected for each channel by asserting the appropriate value into the DMA.CHAN[ N ].CONTROL.TIMING

These are described below.

Free-running

If a channel is free-running, the DMA will occur without requiring a request to begin or control the timing of the transfer. It will continue to operate without further intervention until disabled, complete or an abnormal condition occurs.

This is the model generally used for memory-to-memory moves.

Triggered

A channel is triggered, if a request is required to start the DMA operation.

Following the triggering request the DMA continues as if it were free-running until disabled, complete or an abnormal condition occurs.

This is typically used to communicate between devices, or start a memory-to- memory transfer which needs to be dependent on an external request.

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Paced

A channel is paced, if a single data unit is transferred per request. The request may be associated with either the source or destination memory location. The size of the data unit to be transferred is determined by the information associated with the source if the transfer is source-paced, and the destination if the transfer is destination-paced.

This is typically used by peripheral modules which require low data rate transfers such as UARTs.

4.4.4 DMA requests

The DMAC supports up to 32 physical request channels which may be used to trigger or pace any DMA channel. The association between the DMA channel and request is defined by the DMA.CHAN[ N ].REQUEST

and

DMA.CHAN[ N ].SUBCHAN_ENB

registers and allows 1 request to be associated with

1 DMA channel or subchannel.

2 request protocols are supported:

• DREQ,

• DREQ/DRACK.

The first protocol uses the SuperHyway response to determine when a DMA unit (if paced) or complete DMA (if triggered) transfer has completed. This is assumed to be the cycle the final response packet received plus an offset period. The DMAC is able to begin sampling for the request pending the next transfer after this period.

The second protocol uses the DRACK signal to determine that the device has committed to a transfer, may re-sample the DREQ signal when the offset has passed following the acknowledgment.

Devices which support DRACK may choose to improve the efficiency of the DMA transfer to that device by reasserting req before the current data transfer to that device has completed allowing pipelining of multiple data units.

Each request associated with a peripheral is independent and may be mapped onto any DMA channel, and therefore more than 1 request may occur in a single cycle, or a single request may be mapped onto multiple DMA channels.

If a request is associated with multiple DMA channels, the request will be serviced by the lowest numbered channel, which means channel[n] has priority over channel[n + 1]. If multiple requests are associated with a single DMA channel

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(channel 0) then the lowest number request will be serviced first, that is request[n] has priority over request[n + 1].

4.4.5 DMA data organization

The DMA is able to transfer data which is organized in a number of different ways.

These include:

• single location (0D),

• incrementing or decrementing linear arrays (1D),

• incrementing or decrementing rectangular arrays (2D).

The data organization for the source and destination structures is defined by

DMA.CHAN[ N ].CONTROL.SRC_TYPE

, and DMA.CHAN[ N ].CONTROL.DST_TYPE

respectively.

All data structures are specified with respect to an origin or initial byte address and the address of subsequent transfers is calculated from this origin using the information defined for that channel.

Single location/0D

If the data structure is fixed or single location, the same address is used throughout the transfer and no further information is needed.

Incrementing/1D

If the data structure is 1D, this address is incremented or decremented by the number of bytes in the data transfer unit until DMA.CHAN[ N ].COUNT

bytes are transferred.

In an incrementing transfer from address ADDR of COUNT bytes, the following bytes at the following addresses will be transferred:

ADDR to ADDR + (COUNT - 1).

In a decremented transfer from address ADDR of COUNT bytes, the following bytes at the following addresses will be transferred:

ADDR to ADDR - (COUNT - 1).

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DMA operation

Rectangular array/2D

If the data structure is 2D, 2 additional parameters are defined, LENGTH and

STRIDE. The transfer may be considered as a series of line or 1D transfers each of length bytes, each line separated by STRIDE - LENGTH bytes of unused data.

In the case of an incrementing structure the address defines the bottom left corner

(lowest address), and the DMA transfers a series of data units, first transferring a line containing LENGTH bytes, before incrementing the address by STRIDE bytes and continuing for the next line. This operation is repeated until the required number of bytes is transferred. For a decrementing structure, the address defines the top right corner (highest address), and all addresses are decremented.

The bytes transferred for an incrementing transfer as follows:

IF (COUNT - total number of bytes transfer) > LENGTH, transfer the bytes at addresses:

ADDR to (ADDR + LENGTH - 1)

(ADDR + STRIDE) to (ADDR + STRIDE + LENGTH - 1)

....

(ADDR + (n - 1) * STRIDE) to (ADDR + (n - 1) * STRIDE + LENGTH -

UNTIL (COUNT - total number of bytes transferred) <= LENGTH, transfer the bytes at addresses:

(ADDR + n * STRIDE) to (ADDR + n * STRIDE + (COUNT - number of bytes transferred))

The transfer is now completed.

The bytes transferred during a decrementing 2D transfer are:

IF (COUNT - total number of bytes transfer) > LENGTH, transfer the bytes at addresses:

ADDR to (ADDR - (LENGTH - 1))

(ADDR - STRIDE) to (ADDR - STRIDE - (LENGTH - 1))

....

(ADDR - (n - 1) * STRIDE) to (ADDR - (n - 1) * STRIDE - (LENGTH -

1))

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UNTIL (COUNT - total number of bytes transferred) <= LENGTH, transfer the bytes at addresses:

(ADDR - n * STRIDE) to (ADDR + n * STRIDE - (COUNT - number of bytes transferred)

The transfer is now completed.

4.4.6 Endianness

The DMAC is able to operate in systems which use 1 of 2 possible data organizations, little or big endian. This is determined by sampling a control signal following reset, and which may be considered static during operation.

The DMA is responsible for ensuring that all data has the correct organisation and that the software model of the DMA is independent of this signal.

4.4.7 DMA channel arbitration

The DMA contains a number of independent channels which compete for a single memory port for access to the system, both for control and data information.

To ensure that no channel monopolizes access to the system and excludes all other channels, the DMA implements a least recently used (LRU) algorithm for access to this port.

If DMA channel[n] gains ownership of the memory port for a request packet in cycle m, then channel[n] will become the lowest priority channel in the subsequent cycle, guaranteeing preferential access to other channels in subsequent cycles.

Arbitration is per packet, and ensures in the worst case scenario that each DMA channel is guaranteed to pass 1 request packet in every 5 passed to the system.

4.4.8 Extension to basic DMA operations

The DMAC supports extension to the basic DMA operation using memory mapped register sets. Channel 0 uses this to support a table of independent subchannels from which a request selects a specific register set, whilst channels 1 to 4 support a linked list of DMA operations store in memory.

The organization of each structure is detailed below.

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DMA operation

Single linked list

This considers the DMA channel as a series of register sets each corresponding to a single DMA operation, stored in memory.

DMA channel

IDENTITY

Current pointer

CONTROL

COUNTER

SAR

DAR

POINTER

SRC_LENGTH

SRC_STRIDE

DST_LENGTH

DST_STRIDE

COUNTER = 0 causes fetch of next

DMA register set

Linked DMA list in memory

CONTROL

COUNTER

SAR

DAR

POINTER

SRC_LENGTH

SRC_STRIDE

DST_LENGTH

DST_STRIDE

CONTROL

COUNTER

SAR

DAR

POINTER

SRC_LENGTH

SRC_STRIDE

DST_LENGTH

DST_STRIDE

CONTROL

COUNTER

SAR

DAR

POINTER

SRC_LENGTH

SRC_STRIDE

DST_LENGTH

DST_STRIDE

Figure 10: Organization of tables in memory for a single linked list

Typically the CPU would set up a linked list structure in memory, set the associated pointer register within the DMAC, enable the DMAC and begin the transfer by a write to DMA.CHAN[ N ].ACTION.UPDATE

. This bootstraps the list, loading the first entry and continuing until completion of all the DMAs in the list.

On completion of each DMA operation (as indicated by COUNT = 0) the channel may do one or more of the following operations:

• generate an interrupt indicating completion,

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DMA operation 59

• trigger a channel update,

• terminate.

A channel update causes the information which defines the DMA channel to be updated from memory. The location of this structure in memory is given by a pointer which is itself updated, allowing a linked list to be maintained. Each channel may support 1 such linked list.

This may be used to extend the channel’s operation to support features such as scatter gather sequences, or building DMA sequences with only the final completion requiring CPU intervention via an interrupt.

Multiplexed channels

These share a single physical DMA channel across up to 32 subchannels each with its own register sets. Each subchannel corresponds to a single DMA and has an associated request channel.

Event

DMA channel

IDENTITY

Current pointer

Base address

CONTROL

COUNTER

SAR

DEST

Event causes

Table of DMA register states fetch of DMA register set from offset event number

CONTROL

COUNTER

SAR

DEST

CONTROL

COUNTER

SAR

DEST

CONTROL

COUNTER

SAR

DEST

Subchannel

Figure 11: Organization of tables in memory for a multiplexed channel

Subchannel

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60 Interfaces

A unit transfer occurs when the request associated with the subchannel is asserted, this causes the information defining that channel’s operation to be loaded from memory.

Depending on the information in the new register set, 1 or more data units will be transferred before the copy of the register set stored in memory is updated and the

DMA channel returns to a quiescent status.

On completion of all transfers on a specific subchannel, (as defined by no more data being available to be transferred) the DMAC marks the subchannel as inactive and may signal an interrupt. No further data is transferred on this subchannel.

Completion is non-blocking and other subchannels associated with this DMA channel will continue to operate unchanged.

4.5 Interfaces

Clock

Reset

Test signals

DMAC

Global control and register decode

DREQ[31:0]

DRACK[31:0]

DMA_STALL

LITTLE_NOT_BIG

Device

channels

DMA

DMA channel N

SuperHyway

Interrupt per

DMA channel plus error

DMA_INT[4:0]

DMA_ERR

SuperHyway

target

SuperHyway

initiator

Figure 12: DMAC interfaces

The DMAC communicates with the system using a number of major interfaces:

• system services such as clock and reset,

• 32 event channels giving flow control information for pacing and triggering with allocation of these channels depending on the system implementation,

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• 6 interrupts which comprise error plus 1 interrupt per DMA channel,

• SuperHyway target giving access to local registers,

• SuperHyway initiator giving access to memory, and 2 sets of control signals:

• LITTLE_NOT_BIG if asserted means SuperHyway data organisation is little endian,

• DMA_STALL if asserted, and DMA channel[n] has stall enabled, then all new memory requests on channel[n] are disabled until DMA_STALL is de-asserted.

Each DMA channel may be considered as an independent element communicating using a number of shared interfaces.

All registers are 32 bits and are placed on 64-bit boundaries. They may be accessed either as 64-bit quantities at the register address with the upper 4 bytes reserved, or as 32-bit quantities at the register with all 4 bytes defined.

Accesses to undefined registers or using unsupported access types (or part word accesses) will lead to an error being flagged in the DMA.VCR.STATUS

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62 Register descriptions

4.6.1 Global registers

DMA.VCR.STATUS

DMA.VCR. STATUS defines information available to the system, specifically debug, to determine how this module has interacted with the system, and, if any erroneous requests have occurred during operation of that module.

This information is generally used to allow debug software to determine which modules in the system have caused the system to fail, and supply a little information about how that failure occurred.

DMA.VCR.STATUS

0x0000

Field Bits Size

PERROR [0:7]

Operation

Read

Write

Hard reset

Volatile Synopsis

Yes SuperHyway/Shwy error RW

Each bit of this register corresponds to an erroneous

SuperHyway operation being detected.

The meaning of each bit is as follows:

0: Error response received

1: Error response returned

2: Access to an undefined location accepted

3: Unsolicited response received

4: Reserved, write 0, read undefined

5: Unsupported operation accepted

Returns current value

0: No action

1: Reset bit[n]

Type

Table 22: DMA.VCR.STATUS

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Register descriptions 63

DMA.VCR.STATUS

0x0000

Field Bits Size

MERROR [8:15]

Operation

MOD_ID

Read

Write

Hard reset

[16:31] 16

Operation

Read

Write

Hard Reset

Volatile Synopsis Type

Yes Module error RW

Each bit of this register corresponds to an erroneous module operation being detected.

0: Alignment error

An alignment error will occur if a channel is mis-programming with an unalignable transfer on a channel which enforces alignment checks.

1 to 7: Reserved

Returns current value

0: No action

1: Reset bit[n]

0x00

No Module identity

Used to indicate the module type

Returns module ID

Ignored

Reserved

Table 22: DMA.VCR.STATUS

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Register descriptions

DMA.VCR.VERSION

DMA.VCR.VERSION

defines the module type and revision number.

DMA.VCR.VERSION

Field Bits

MOD_VER [0:15]

Operation

Read

Write

MOD_SIZ

Hard reset

[16:31]

Operation

Read

Write

Hard reset

0x0008

Size

Volatile Synopsis

No Module version

Used to indicate the module type

Returns module version

Ignored

No Module size RO

Module size defined in blocks of 64 Kbytes

Reads 0x0001

Ignored

0x0001

Type

Table 23: DMA.VCR.VERSION

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Register descriptions 65

DMA.ENABLE

DMA.ENABLE

defines a global mechanism for software to enable one or more channels

rapidly .

DMA.ENABLE

Field Bits

CHANNEL [0:4]

Operation

Read

Size

Write

Hard reset

[6:31] 26

Operation

Read

Write

Hard reset

Volatile Synopsis

Yes DMA enable

Bit[n] is used to enable channel[n]

1: DMA channel[n] enabled

0: DMA channel[n] disabled

1: Enable DMA channel[n]

0: No action

0x00

Reserved -

Reserved

Undefined

Table 24: DMA.ENABLE

0x0010

Type

1. A channel is enabled only when both the channel and global enables are set

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Register descriptions

DMA.DISABLE

DMA.DISABLE

may be used to disable 1 or more DMA channels using a single global register.

DMA.DISABLE

Field Bits

CHANNEL [0:4]

Operation

Read

Write

Size

Hard reset

[6:31]

Operation

Read

Write

Hard reset

Volatile Synopsis

DMA disable

Bit[n] is used to disable channel[n]

Reserved

0: No action

1: Disable DMA channel[n]

0x00

Reserved

Undefined

Table 25: DMA.DISABLE

0x0018

Type

The disable register provides an override mechanism to stall or disable 1 or more channels simultaneously. This is typically used to disable all channels, fine level control is generally achieved via the local control state.

After this register is accessed, it may take a number of cycles for outstanding accesses to complete on each DMA channel and the user should check the

DMA.STATUS

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Register descriptions 67

DMA.STATUS

DMA.STATUS

defines the status of the DMA channels.

Field

CHANNEL

DMA.STATUS

0x0020

Bits

[0:4]

Operation

Read

Size

Write

Hard reset

[6:31]

Operation

Read

Write

Hard reset

Volatile Synopsis Type

Yes DMA disable

Bit[n] indicates the status of channel[n]

0: Channel[n] inactive, that is disabled, and all memory accesses associated with this channel completed

1: Channel[n] active, that is enabled, or memory accesses outstanding on this channel

Ignored

0x00

Reserved -

Reserved

Undefined

Table 26: DMA.STATUS

The user should not assume the DMAC and associated volatile registers or memory images are stable until a read to this register or to the associated channel register indicates the DMAC is inactive.

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Register descriptions

DMA.INTERRUPT

DMA.INTERRUPT

summarizes the interrupt status of all channels. It may be read to determine which channel caused an interrupt to be asserted.

Field

CHANNEL

DMA.INTERRUPT

0x0028

Bits

[0:4]

Operation

Size

Read

Write

Hard reset

[6:31] 26

Operation

Read

Write

Hard reset

Volatile Synopsis Type

Yes DMA interrupt status RO

If bit[n] is set, an unserviced DMA interrupt occurred on channel[n]

0: No outstanding interrupts on channel[n]

1: Unserviced interrupt on channel[n]

Ignored

0x00

Reserved

Undefined

Reserved -

Table 27: DMA.INTERRUPT

To clear or determine the cause of the interrupt on a specific channel, the associated channel register DMA.CHAN[ N ].STATUS

and DMA.CHAN[ N ].CONTROL

registers should be accessed.

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Register descriptions

DMA.ERROR

DMA.ERROR

summarizes the error status of all channels. It may be read to determine which channel caused an error condition to occur.

Field

ERROR

DMA.ERROR

Bits

[0:4]

Operation

Size

Read

Write

Hard reset

[6:31]

Operation

Read

Write

Hard reset

0x0030

Volatile Synopsis Type

Yes DMA error status RO

If bit[n] is set, an unserviced error interrupt occurred on channel[n]

Returns current value

Ignored

0x00

Reserved -

Reserved

Undefined

Table 28: DMA.ERROR

To clear or determine the cause of the interrupt on a specific channel, the associated channel register DMA.CHAN[ N ].STATUS

and DMA.CHAN[ N ].CONTROL

registers should be accessed.

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Register descriptions

DMA.DEFINED

DMA.DEFINED is a five channel implementation of the DMAC, future variants which implement different numbers or types of channel.

Field

DEFINED

DMA.DEFINED

Bits Size

[0:31] 32

Operation

Read

Write

Hard reset

0x0038

Volatile Synopsis

No DMA channel defined

If bit[n] set, channel[n] is implemented

0x0000001F

Ignored

0x0000001F

Table 29: DMA.DEFINED

Type

DMA.HANDSHAKE

DMA.HANDSHAKE defines the protocol for a request from a peripheral.

Field

CHANNEL

DMA.HANDSHAKE

0x0040

Bits Size

[0:31] 32

Operation

Read

Write

Hard reset

Volatile Synopsis Type

No RW

If bit[n] is set, DMA request channel[n] implements DREQ /

DRACK protocol.

If bit[n] is not set, it implements DREQ only.

Returns current value

Updates current value

0x00

DMA request handshake

Table 30: DMA.HANDSHAKE

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PRELIMINARY DATA

Register descriptions

4.6.2 Channel-specific registers

DMA.CHAN[n].IDENTITY

DMA.CHAN

[ N ] .IDENTITY describes the type and facilities of a DMA channel.

Field

TYPE

DMA.CHAN[n].IDENTITY

(n = 0 to 4)

((n + 1) * 0x100) + 0x00

Bits Size

[0:3]

Operation

Read

Write

Hard reset

Volatile Synopsis

No Channel DMA type RO

Identifies DMA channel type. Valid values are:

0000: No channel

0001: Reserved

0010: Single linked list, list of basic DMAs

0011: Reserved

0100: Table of multiplexed single DMAs

0100 to 1111: Reserved

Channel 0: 0x4

Channel[1:4] = 0x2

Ignored

Channel 0: 0x4

Channel[1:4] = 0x2

Type

Table 31: DMA.CHAN[n].IDENTITY

ADCS 7153464G

STMicroelectronics

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PRELIMINARY DATA

Register descriptions

Field

TIMING

DMA.CHAN[n].IDENTITY

(n = 0 to 4)

((n + 1) * 0x100) + 0x00

Bits Size

[4:7]

Operation

Read

Write

Hard reset

Volatile Synopsis Type

No Channel timing model RO

Identifies supported timings models on this channel.

Valid values are:

0000: Free running only

0001= Triggered (on hardware event, complete DMA)

0010: Paced (on hardware event, transfer single data unit and wait for next event)

0011: Both triggering and pacing supported on this channel

0100 to1111 Reserved

Channel[0:4] = 0x3

Ignored

Channel[0:4] = 0x3

Table 31: DMA.CHAN[n].IDENTITY

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PRELIMINARY DATA

Register descriptions 73

UNIT

Field

DMA.CHAN[n].IDENTITY

(n = 0 to 4)

((n + 1) * 0x100) + 0x00

Bits Size

[8:15]

Operation

Read

Write

Hard reset

Volatile Synopsis Type

No DMA data units RO

Identifies the data units supported by the channel, valid values are:

Bit 8 set: Support for single byte units

Bit 9 set: Support for 2 byte units

Bit 10 set: Support for 4 byte units

Bit 11 set: Support for 8 byte units

Bit 12 set: Support for 16 byte units

Bit 13 set: Support for 32 byte units

Bit 14 to 15: Reserved

Channel[0:4]: 0x3F

Ignored

Channel[0:4]: 0x3F

DATA [16:23]

Operation

Read

Write

Hard reset

8 No Channel data structures RO

Defines the data structures supported by this channel.

Bit 16 set: Support for fixed address (0D)

Bit 17 set: Support for 1D incrementing

Bit 18 set: Support for 1D decrementing

Bit 19 set: Support for 2D incrementing

Bit 20 set: Support for 2D decrementing

Bit 21 to 23: Reserved

Channel[0:4]: 0x1F

Ignored

Channel[0:4]: 0x1F

Table 31: DMA.CHAN[n].IDENTITY

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STMicroelectronics

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PRELIMINARY DATA

Register descriptions

Field

ALIGNMENT

DMA.CHAN[n].IDENTITY

(n = 0 to 4)

Bits

[24:27]

Operation

Read

Write

Hard reset

[28:31]

Operation

Read

Write

Hard reset

((n + 1) * 0x100) + 0x00

Size

Volatile Synopsis Type

No Channel alignment model

Defines the alignment model supported by this channel.

Bit 24 set: Unaligned source units supported

Bit 25 set: Unaligned destination units supported

Bit 26 set: Source and destination units must be equal

Bit 27 set: Source and destination units must have same alignment

Channel 0: 0xC

Channel[1:4]: 0x3

Ignored

Channel 0: 0xC

Channel[1:4]: 0x3

Reserved -

Reserved

Undefined

Table 31: DMA.CHAN[n].IDENTITY

This register is defined for all channels.

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SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G

PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].ENABLE

DMA.CHAN

[n] .ENABLE controls the behavior of a channel.

DMA.CHAN[n].ENABLE

(n = 0 to 4)

((n + 1) * 0x100) + 0x08

Field Bits Size Volatile Synopsis

CHANNEL

COMPLETE

[0]

Operation

Read

Write

Hard reset

[1]

Operation

Read

Write

Hard reset

BUS_ERROR [2] 1

Operation

Read

Write

Hard reset

Yes Enable DMA channel

Enables this DMA channel

If set, channel is enabled

0: No action

1: Enable

Yes Enable DMA complete

Enables the channel complete interrupt

If set, DMA complete interrupt enabled

0: No action

1: Enable

Yes Enable bus errors

Enables DMA bus error interrupts

If set, DMA error interrupt enabled

0: No action

1: Enable

Table 32: DMA.CHAN[n].ENABLE

Type

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STMicroelectronics

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PRELIMINARY DATA

Register descriptions

Field

ALIGNMENT

STALL

ERROR

DMA.CHAN[n].ENABLE

(n = 0 to 4)

Bits Size Volatile

((n + 1) * 0x100) + 0x08

Synopsis Type

[3]

Operation

Read

Write

Hard reset

[4] 1

Operation

Read

Write

Hard reset

[5] 1

Operation

Read

Write

Hard reset

Yes Enable alignment errors RW

Enables alignment checks and associated interrupt

If set, DMA alignment error interrupts enabled

0: No action

1: Enable

Yes Enable stall

Enable stall on external signal

If set, external stalls enabled

0: No action

1: Enable

No error mode RW

Selects interrupt error mode

If set, errors flagged on both the channel interrupt and error interrupt signals

If not set, errors flagged on just the error interrupt

0: No action

1: Enable error on channel interrupt

Table 32: DMA.CHAN[n].ENABLE

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SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G

PRELIMINARY DATA

Register descriptions

Field

DMA.CHAN[n].ENABLE

(n = 0 to 4)

((n + 1) * 0x100) + 0x08

Bits Size

[6:31] 26

Operation

Read

Write

Hard reset

Volatile

Reserved

Undefined

Synopsis

Channel DMA type

Table 32: DMA.CHAN[n].ENABLE

Type

DMA.CHAN[n].DISABLE

DMA.CHAN

[n] .DISABLE disables control functionality for a channel.

Field

CHANNEL

DMA.CHAN[n].DISABLE

(n = 0 to 4)

((n + 1) * 0x100) + 0x10

Bits

[0]

Operation

Read

Write

Size

Hard reset

Volatile Synopsis

Disable DMA channel

Disables the DMA channel

Reserved

0: No action

1: Disable

Table 33: DMA.CHAN[n].DISABLE

Type

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STMicroelectronics

SH-4, ST40 System Architecture, Volume 1: System

PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].DISABLE

(n = 0 to 4)

((n + 1) * 0x100) + 0x10

Field

COMPLETE

BUS_ERROR

ALIGNMENT

Bits

[1]

Operation

Read

Write

Size

Hard reset

[2]

Operation

Read

Write

Hard reset

[3]

Operation

Read

Write

Hard reset

Volatile Synopsis Type

Disable DMA complete

Disables interrupts on DMA complete

Reserved

0: No action

1: Disable

Disable bus errors

Disables interrupts on channel’s bus errors

Reserved

0: No action

1: Disable

Disable alignment errors WO

Disables interrupt on misaligned accesses on the channel

Reserved

0: No action

1: Disable

Table 33: DMA.CHAN[n].DISABLE

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SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G

PRELIMINARY DATA

Register descriptions

Field

STALL

ERROR

DMA.CHAN[n].DISABLE

(n = 0 to 4)

((n + 1) * 0x100) + 0x10

Bits

[4]

Operation

Read

Write

Size Volatile Synopsis

Hard reset

[5]

Operation

Read

Write

Hard reset

[6:31] 26

Operation

Read

Write

Hard reset

Disable stall

Disables stall on signal

Reserved

0: No action

1: Disable

Error mode

Reserved error mode

0: No action

1: Disable error on channel interrupt

Reserved

Undefined

Reserved

Table 33: DMA.CHAN[n].DISABLE

Type

ADCS 7153464G

STMicroelectronics

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PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].STATUS

DMA.CHAN

[n] .STATUS defines the status of the current channel.

Field

CHANNEL

COMPLETE

DMA.CHAN[n].STATUS

(n = 0 to 4)

((n + 1) * 0x100) + 0x18

Bits Size Volatile Synopsis Type

[0]

Operation

Read

Write

Hard reset

[1]

Operation

Read

Write

Hard reset

Yes DMA channel status

Indicates the status of the DMA channel

0: Channel[n] inactive, that is disabled and all memory accesses associated with this channel completed

1: Channel[n] active, that is enabled, or memory accesses outstanding on this channel

Ignored

Yes DMA complete status

Status of the DMA operation on the channel

0: DMA operation not completed

1: DMA operation completed and, if enabled, interrupt associated with DMA complete asserted

A DMA operation is completed when COUNT = 0 and all accesses have finished.

Ignored

Table 34: DMA.CHAN[n].STATUS

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PRELIMINARY DATA

Register descriptions

Field

BUS_ERROR

ALIGNMENT

STALL

DMA.CHAN[n].STATUS

(n = 0 to 4)

Bits Size Volatile

((n + 1) * 0x100) + 0x18

Synopsis Type

[2]

Operation

Read

Write

Hard reset

[3]

Operation

Read

Write

Hard reset

[4]

Operation

Read

Yes

Bus error status

Indicates the status of the bus errors on this channel

0: No outstanding bus errors on the channel

1: Memory access from the channel returned an outstanding bus error to this device and, if enabled, interrupt associated with errors on channel is asserted

Ignored

Alignment status

Status of alignment errors on the channel

0: No unaligned accesses occurred

1: Unit transfer size and address cannot be aligned and, if enabled, interrupt associated with errors on the channel is asserted

Ignored

Yes

Ignored

Stall status

Status of stall on the channel

0: Channel not stalled

1: Channel stalled by external stall request

Write

Hard reset

Table 34: DMA.CHAN[n].STATUS

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PRELIMINARY DATA

Register descriptions

Field

UPDATE

DMA.CHAN[n].STATUS

(n = 0 to 4)

((n + 1) * 0x100) + 0x18

Bits Size Volatile Synopsis

[6]

Operation

Read

Write

Hard reset

[5]

[7:31]

Operation

Read

Write

Hard reset

Yes Update status

Status of link list update request

0: No request outstanding

1: Linked list update request outstanding

Ignored

Reserved

Undefined

Table 34: DMA.CHAN[n].STATUS

Type

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PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].ACTION

DMA.CHAN

[n] .ACTION causes an action associated with a channel.

DMA.CHAN[n].ACTION

(n = 0 to 4)

((n + 1) * 0x100) + 0x20

Field Bits Size Volatile Synopsis Type

CHANNEL

COMPLETE

[0]

Operation

Read

Write

Hard reset

[1] 1

Operation

Read

Write

Hard reset

BUS_ERROR [2] 1

Operation

Read

Write

Hard reset

Reserved

Undefined

DMA complete status

Change status of DMA complete on channel

Undefined

0: No action

1: Reset DMA complete status bit and associated interrupt

Bus error status

Change status of bus error on channel

Undefined

0: No action

1: Reset DMA bus error status bit and associated interrupt

Table 35: DMA.CHAN[n].ACTION

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STMicroelectronics

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PRELIMINARY DATA

Register descriptions

Field

ALIGNMENT

STALL

UPDATE

DMA.CHAN[n].ACTION

(n = 0 to 4)

Bits Size Volatile

((n + 1) * 0x100) + 0x20

Synopsis Type

[3]

Operation

Read

Write

Hard reset

[4] 1

Operation

Read

Write

Hard reset

[6] 1

Operation

Read

Write

Hard reset

Alignment error status WO

Change status of alignment errors on channel

Undefined

0: No action

1: Reset DMA alignment status bit and associated interrupt

Stall status

Change status of stall on channel

Undefined

0: No action

1: Clear stall condition on channel

Update status

Trigger linked list update

Undefined

0: No action

1: Update DMA channel register set from linked list

Table 35: DMA.CHAN[n].ACTION

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PRELIMINARY DATA

Register descriptions 85

Field

DMA.CHAN[n].ACTION

(n = 0 to 4)

((n + 1) * 0x100) + 0x20

Bits Size Volatile Synopsis

[5],

[7:31]

Operation

Read

Write

Hard reset

Reserved

Undefined

Table 35: DMA.CHAN[n].ACTION

Type

DMA.CHAN[n].POINTER

DMA.CHAN

[n] .POINTER contains the value of the pointer used to fetch the current control information.

DMA.CHAN[n].POINTER

(n = 0 to 4)

Field

ADDRESS

Bits Size Volatile

((n + 1) * 0x100) + 0x28

Synopsis

[3:31]

Operation

Read

Write

Hard reset

Yes Current channel pointer

Indicates location of last register update

Returns current value

Ignored

Table 36: DMA.CHAN[n].POINTER

Type

ADCS 7153464G

STMicroelectronics

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PRELIMINARY DATA

Register descriptions

Field

DMA.CHAN[n].POINTER

(n = 0 to 4)

((n + 1) * 0x100) + 0x28

Bits

[0:2]

Operation

Read

Write

Hard reset

Size Volatile Synopsis

Reserved

Undefined

Reserved

Table 36: DMA.CHAN[n].POINTER

Type

DMA.CHAN[n].REQUEST

DMA.CHAN[ N ].REQUEST associates the DMA channel and request number..

DMA.CHAN[n].REQUEST

(n= 1 to 4)

Field

NUMBER

Bits Size Volatile

((n + 1) * 0x100) + 0x30

Synopsis Type

[0:5]

Operation

Read

Write

Hard reset

No Request channel number RW

Indicates which request, if enabled, is associated with the channel

Returns current value

Update value

Table 37: DMA.CHAN[n].REQUEST

1. This is only defined for channels 1 to 4

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PRELIMINARY DATA

Register descriptions 87

Field

OFFSET

DMA.CHAN[n].REQUEST

(n= 1 to 4)

Bits

[8:15]

Operation

Size Volatile

((n + 1) * 0x100) + 0x30

Synopsis Type

Read

Write

Hard reset

[6:7]

[16:31]

Operation

Read

Write

Hard reset

No subchannel interrupt RW

Minimum offset between acknowledgment of request, and subsequent sampling of same request

Returns current state

Updates current state

Reserved

Undefined

Table 37: DMA.CHAN[n].REQUEST

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PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].SUBBASE

For channel 0, DMA.CHAN[

].SUBBASE points to the base address of the channel table stored in memory.

Field

ADDRESS

DMA.CHAN[n].SUBBASE

(n = 0)

((n + 1) * 0x100) + 0x30

Bits Size

[8:31]

Operation

Read

Write

Hard reset

[0:7] 8

Operation

Read

Write

Hard reset

Volatile

Reserved

Undefined

Synopsis

Table base address

Pointer to base address of subchannel table

Returns current value

Updates current value

Reserved

Table 38: DMA.CHAN[n].SUBBASE

Type

1. Only defined for channel 0

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PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].SUBENABLE

For channel 0 DMA.CHAN[

].SUBENABLE defines which subchannel is enabled.

DMA.CHAN[n].SUBENABLE

(n = 0)

Field

SUBCHANNEL

Bits Size Volatile

((n + 1) * 0x100) + 0x38

Synopsis

[0:31]

Operation

Read

Write

32 Yes Enable subchannel

Enables DMA subchannel

If set, current subchannel enabled

0: No action

1: Enables subchannel[i]

0 Hard reset

Table 39: DMA.CHAN[n].SUBENABLE

Type

If subchannel[i] is enabled and request[i] is asserted then the following actions occur:

1 The information is stored in memory for subchannel[i] to be loaded in the register state.

2 1 or more transfer units are completed on subchannel[i].

3 The information is stored in memory for subchannel[i] to be updated with new register state.

If channel 0 is enabled and subchannel[i] is not enabled then events on request[i] will be ignored.

1. Only defined for channel 0

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PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].SUBDISABLE

DMA.CHAN[

].SUBDISABLE disables a subchannel. If channel 0 is not enabled, all subchannels are also disabled.

DMA.CHAN[n].SUBDISABLE

(n = 0)

Field

CHANNEL

Bits Size Volatile

((n + 1) * 0x100) + 0x40

Synopsis

[0:31]

Operation

Read

Write

Hard reset

Disable subchannel WO

Disables interrupt associated with subchannel

Reserved

0: No action

1: Disable interrupt associated with channel

Table 40: DMA.CHAN[n].SUBDISABLE

Type

DMA.CHAN[n].SUB_INTENB

DMA.CHAN[ N ].SUB_INTENB enables interrupts channels associated with a subchannel.

DMA.CHAN[n].SUBINT_ENB

(n = 0)

Field

CHANNEL

Bits

Hard reset

Size

[0:31]

Operation

Read

Write

Volatile

((n + 1) * 0x100) + 0x48

Synopsis

Yes Enable subchannel RW

Enables interrupt associated with subchannel

If set, current subchannel interrupt enabled

0: No action

1: Enables subchannel[i] interrupt

Table 41: DMA.CHAN[n].SUB_INTENB

Type

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Register descriptions

DMA.CHAN[n].SUBINT_DIS

DMA.CHAN[

].SUBINT_DIS disables interrupts associated with a subchannel.

Field

DISABLE

DMA.CHAN[n].SUBINT_DIS

(n = 0)

Bits Size Volatile

((n + 1) * 0x100) + 0x50

Synopsis

[0:31]

Operation

Read

Write

Hard reset

Subchannel interrupt WO

Disables interrupt associated with subchannel

Reserved

0: No action

1: Disables interrupt associated with channel[n]

Table 42: DMA.CHAN[n].SUBINT_DIS

Type

DMA.CHAN[n].SUBINT_STAT

DMA.CHAN[ N ].SUBINT_STAT defines the status of interrupts associated with a subchannel.

Field

STATUS

DMA.CHAN[n].SUBINT_STAT

(n = 0)

Bits

Write

Hard reset

Size

[0:31]

Operation

Read

Volatile

((n + 1) * 0x100) + 0x58

Synopsis

Yes Subchannel interrupt

Status of subchannel interrupts

0: No unserviced interrupts on subchannel[i]

1: Unserviced interrupt on subchannel[i]

Ignored

Table 43: DMA.CHAN[n].SUBINT_STAT

Type

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PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].SUBINT_ACT

DMA.CHAN[

].SUBINT_ACT clears interrupt status associated with a subchannel.

DMA.CHAN[n].SUBINT_ACT

(n = 0)

Field

CONTROL

Bits Size Volatile

((n + 1) * 0x100) + 0x60

Synopsis

[0:31]

Operation

Read

Write

Hard reset

Subchannel interrupt

Clear interrupt associated with subchannel

Reserved

0: No action

1: Clear interrupt status associated with bit[i]

Table 44: DMA.CHAN[n].SUBINT_ACT

Type

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PRELIMINARY DATA

Register descriptions 93

4.6.3 Memory-mapped channel registers

DMA.CHAN[n].CONTROL

DMA.CHAN[ N ].CONTROL defines the behavior of the DMA channel, including features such as transfer data units, transfer direction, the association between the

DMA channel and device channels.

Field

TIMING

DMA.CHAN[n].CONTROL

(n = 0 to 4)

((n + 1) * 0x100) + 0x80

Bits

[0:1]

Operation

Read

Write

Hard reset

Size

Volatile Synopsis Type

No Channel timing model RW

00: Free running

01: Trigger, start free running DMA on request

10: Paced SRC, read single unit from source on request

11: Paced DEST, write single unit to destination on request

Returns current state

Updates current State

Table 45: DMA.CHAN[n].CONTROL

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PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].CONTROL

(n = 0 to 4)

((n + 1) * 0x100) + 0x80

Field

LIST_ENB

Bits Size

[7]

Operation

SUB_OFFSET

Read

Write

Hard reset

[8:15] 8

Operation

Read

Write

Hard reset

Volatile Synopsis Type

No link list enable RW

Defines whether the DMA is part of a linked list, and if so the behavior on normal DMA completion (channels 1 to 4 only)

0: Not part of, or is the final element of, the linked list

The DMAC asserts the channel complete interrupt if the associated interrupt is enabled.

1: An element within a list

The DMAC does not assert the channel complete and updates the memory mapped register from the linked list.

Returns current state

Updates current state

Undefined

No Subchannel offset RW

Minimum offset between acknowledgment of a request, and subsequent sampling of the same event

Returns current state

Updates current state

Table 45: DMA.CHAN[n].CONTROL

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PRELIMINARY DATA

Register descriptions

Field

SRC_TYPE

SRC_UNIT

DMA.CHAN[n].CONTROL

(n = 0 to 4)

Bits Size Volatile

((n + 1) * 0x100) + 0x80

Synopsis

[16:18]

Operation

Read

Write

Hard reset

[19:21]

Operation

Read

Write

Hard reset

No Source data type

Defines the source data structure:

000: Constant source

001: Linear incrementing source

010: Linear decrementing source

011: 2D incrementing source

100: 2D decrementing source

101 to 111: Reserved

Returns current state

Updates current state

No Source transfer unit

Defines the source transfer unit:

000: Byte

001: 2 bytes

010: 4 bytes

011: 8 bytes

100: 16 bytes

101: 32 bytes

110 to 111: Reserved

Returns current state

Updates current state

Table 45: DMA.CHAN[n].CONTROL

Type

ADCS 7153464G

STMicroelectronics

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PRELIMINARY DATA

Register descriptions

Field

SRC_UPDATE

DST_TYPE

DMA.CHAN[n].CONTROL

(n = 0 to 4)

Bits

[22]

Operation

Read

Write

Hard reset

[24:26]

Operation

Read

Write

Hard reset

Size

Volatile

((n + 1) * 0x100) + 0x80

Synopsis Type

No Disable source update RW

Defines whether the addressing information associated with a source data structure is updated when reading from a linked list

0: Source update enabled

1: Source update disabled

The information which may be updated includes SAR,

SRC_STRIDE, SRC_LENGTH and the 2D transfer offset.

Returns current state

Updates current state

Undefined

No Destination data type RW

Defines the destination data structure

000: Constant source

001: Linear incrementing source

010: Linear decrementing source

011: 2D incrementing source

100: 2D decrementing source

101 to 111: Reserved

Returns current state

Updates current state

Table 45: DMA.CHAN[n].CONTROL

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PRELIMINARY DATA

Register descriptions 97

Field

DST_UNIT

DMA.CHAN[n].CONTROL

(n = 0 to 4)

DST_UPDATE

Bits

[27:29]

Operation

Read

Write

Hard reset

[30]

Operation

Read

Write

Hard reset

Size

Volatile

Updates current state

((n + 1) * 0x100) + 0x80

Synopsis

No Destination transfer unit RW

Defines the destination transfer unit

000: byte

001: 2 bytes

010: 4 bytes

011: 8 bytes

100: 16 bytes

101: 32 bytes

110 to 111: Reserved

Returns current state

Type

No Disable destination update

Defines whether the addressing information associated with a destination data structure is updated when reading from a linked list

0: Destination update enabled

The information which may be updated includes DAR,

DST_STRIDE, DST_LENGTH and the 2D transfer offset.

1: Destination update disabled

Returns current state

Updates current state

Undefined

Table 45: DMA.CHAN[n].CONTROL

ADCS 7153464G

STMicroelectronics

SH-4, ST40 System Architecture, Volume 1: System

PRELIMINARY DATA

Register descriptions

DMA.CHAN[n].CONTROL

(n = 0 to 4)

((n + 1) * 0x100) + 0x80

Field Bits Size

[2:6]

[23]

[31]

Operation

Read

Write

Hard reset

Volatile

Reserved

Undefined

Synopsis

Reserved

Type

Table 45: DMA.CHAN[n].CONTROL

A. Channel 0: source and destination pacing are equivalent

B. Channel 0: defined, channel 1 to 4 reserved

C. Channel 0: source and destination units are the same, DST_UNIT must be equal to SRC_UNIT

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Register descriptions

DMA.CHAN[n].COUNT

DMA.CHAN[

].COUNT defines the number of bytes to be transferred before this

DMA channel completes.

Field

BYTES

DMA.CHAN[n].COUNT

(n = 0 to 4)

((n + 1) * 0x100) + 0x88

Bits Size Volatile Synopsis Type

[0:31]

Operation

Read

Write

Hard reset

Yes Transfer count RW

Number of bytes remaining to be transferred on this channel

Returns current value

Updates current value

Table 46: DMA.CHAN[n].COUNT

If alignment checks are available and enabled, then this must be an integer multiple of larger of the 2 data units as defined in the DMA.CHAN[ N ].CONTROL

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Register descriptions

DMA.CHAN[n].SAR

DMA.CHAN[

].SAR defines the starting address of the data source.

DMA.CHAN[n].SAR

(n = 0 to 4)

((n + 1) * 0x100) + 0x90

Field Bits Size

ADDRESS [0:31]

Operation

Read

Write

Hard reset

Volatile Synopsis Type

Yes Source address RW

Indicates the address from which the next transfer unit is fetched

This address is incremented or decremented as DMA channel[n] proceeds in accordance with the setting of

DMA.CHAN[ N ].CONTROL.

A write to this register causes internal address state associated with the source data transfer within the DMA to be reset.

Returns current value

Updates current value

Table 47: DMA.CHAN[n].SAR

If alignment checks are available and enabled, then this must be an integer multiple of larger of the source data unit as defined in the DMA.CHAN[

].CONTROL register. If an alignment error occurs, this channel will be disabled and no further transfers will occur.

If alignment checks are disabled, then the DMA channel will use the largest alignable data unit equal to or smaller than that defined in the

DMA.CHAN[ N ].CONTROL

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Register descriptions 101

DMA.CHAN[n].DAR

DMA.CHAN[

].DAR defines the starting address of the data destination

DMA.CHAN[n].DAR

(n = 0 to 4)

((n + 1) * 0x100) + 0x98

Field Bits Size

ADDRESS [0:31] 32

Operation

Read

Write

Hard reset

Volatile Synopsis Type

Yes Destination address RW

Indicates the address from which the next transfer unit is written

This address is incremented or decremented as DMA channel[n] proceeds in accordance with the setting of

DMA.CHAN[ N ].

CONTROL .

A write to this register causes internal address state associated with the destination data transfer within the DMA to be reset.

Returns current value

Updates current value

Table 48: DMA.CHAN[n].DAR

If alignment checks are available and enabled, then this must be an integer multiple of destination data unit as defined in the DMA.CHAN[

].CONTROL

If alignment checks are disabled, then the DMA channel will use the largest alignable data unit equal to or smaller than that defined in the

DMA.CHAN[ N ].CONTROL

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Register descriptions

DMA.CHAN[n].NEXT_PTR

DMA.CHAN[

].NEXT_PTR defines the location of channel information used to update the channel on completion of the current transfer if the appropriate control status is set.

DMA.CHAN[n].NEXT_PTR

(n = 1 to 4)

((n + 1) * 0x100) + 0xA0

Field Bits Size

ADDRESS [3:31] 29

Operation

Read

Write

Hard reset

[0:2] 3

Operation

Read

Write

Hard reset

Volatile Synopsis

Yes Updates pointer value RW

Pointer to next DMA operation in memory

Returns current value

Updates current value

Reserved -

Reserved

Undefined

Table 49: DMA.CHAN[n].NEXT_PTR

Type

1. This is only defined for channels which support linked lists.

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Register descriptions 103

DMA.CHAN[n].SRC_LENGTH

DMA.CHAN[

].SRC_LENGTH defines the length of a line for a 2D data structure.

Field

COUNT

DMA.CHAN[n].SRC_LENGTH

(n = 1 to 4)

((n + 1) * 0x100) + 0xA8

Bits Size Volatile Synopsis

[0:15]

Operation

Read

Write

Hard reset

[16:31] 16

Operation

Read

Write

Hard reset

Yes Transfer count

Length of a line in a source 2D data type

Returns current value

Updates current value

Reserved

Undefined

Reserved

Table 50: DMA.CHAN[n].SRC_LENGTH

Type

If alignment checks are available and enabled, then this must be an integer multiple of the source unit as defined in the DMA.CHAN[ N ].CONTROL

If alignment is not enabled, the DMAC module is responsible for selecting the largest datum size appropriate for the address and length values which is equal to or smaller than that defined in the DMA.CHAN[

].CONTROL

1. This is only defined for channels which support 2D transfer structures

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Register descriptions

DMA.CHAN[n].SRC_STRIDE

DMA.CHAN[

].SRC_STRIDE defines the amount to increment the address between lines.

Field

BYTES

DMA.CHAN[n].SRC_STRIDE,

(n = 1 to 4)

Bits Size

[0:15]

Operation

Read

Write

Hard reset

[16:31] 16

Operation

Read

Write

Hard reset

Volatile

((n + 1) * 0x100) + 0xB0

Synopsis Type

Yes Source stride RW

Stride between lines in source 2D data structures

Returns current value

Updates current value

Reserved

Undefined

Reserved -

Table 51: DMA.CHAN[n].SRC_STRIDE

If alignment checks are available and enabled, then this must be an integer multiple of source unit as defined in the DMA.CHAN[ N ].CONTROL

If alignment is not enabled, the DMA module is responsible for selecting the largest datum size appropriate for the address and length values which is equal to or smaller than that defined in the DMA.CHAN[

].CONTROL

1. This is only defined for channels which support 2D transfer structures

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Register descriptions

DMA.CHAN[n].DST_LENGTH

DMA.CHAN[

].DST_LENGTH defines the length of a line for a 2D data structure.

Field

COUNT

DMA.CHAN[n].DST_LENGTH

(n = 1 to 4)

((n + 1) * 0x100) + 0xB8

Bits Size Volatile Synopsis

[0:15]

Operation

Read

Write

Hard reset

[16:31] 16

Operation

Read

Write

Hard reset

Yes Transfer count RW

Length of a line in a destination 2D data type

Returns current value

Updates current value

Reserved

Undefined

Reserved

Table 52: DMA.CHAN[n].DST_LENGTH

Type

105

If alignment checks are available and enabled, then this must be an integer multiple of the destination data unit as defined in the DMA.CHAN[ N ].CONTROL

].CONTROL

1. This is only defined for channels which support 2D transfer structures

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Register descriptions

DMA.CHAN[n].DST_STRIDE

DMA.CHAN[

].DST_STRIDE

defines the amount to increment or decrement the address between lines.

Field

BYTES

DMA.CHAN[n].DST_STRIDE

(n = 1 to 4)

((n + 1) * 0x100) + 0xC0

Bits Size

[0:15]

Operation

Read

Write

Hard reset

[16:31] 16

Operation

Read

Write

Hard reset

Volatile

Yes

Synopsis

Destination stride

Stride between lines in destination 2D structures

Returns current value

Updates current value

Reserved

Undefined

Reserved

Table 53: DMA.CHAN[n].DST_STRIDE

Type

If alignment checks are available and enabled, then this must be an integer multiple of the destination unit as defined in the DMA.CHAN[ N ].CONTROL

If an alignment error occurs, this channel will be disabled and no further transfers will occur.

].CONTROL

1. This is only defined for channels which support 2D transfer structures

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Parallel input/ output (PIO)

The ST40 has 24 bits of parallel input/output (PIO), configured in three 8-bit groups

(ports). Each bit is programmable as an output, an input, a bidirectional pin, or as an alternate function output pin. The alternate function connects signals from device peripherals to the pins of the device through the PIO.

Each 8-bit group can also be compared against a register and an interrupt generated when the value is not equal.

Output drivers for the PIO pins, both in PIO mode and the alternate function mode, can be programmed to be push-pull, open drain, or weak pull-up. The weak pull-up configuration avoids the need for pull-up resistors on unused pins while still allowing them to be driven for test purposes.

Each of the 8-bit groups operates as described in the following section.

5.1 PIO ports 0 to 2

Each of the 8 bits of a PIO port has a corresponding bit in the PIO registers associated with each port. These registers hold:

• output data for the port ( POUT ),

• the input data read from the pin ( PIN ),

• PIO bit configuration registers ( PC0 , PC1 and PC2 ),

• the 2 input compare function registers ( PCOMP and PMASK ).

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PIO ports 0 to 2

Register name

(n = 0 to 2)

Description

PIO.POUT[

PIO.PIN[

PIO.PC0[

PIO.PC1[

]

] Output data, see

Table 55 on page 109

Input data, see

Table 58 on page 112

Configuration, see

Table 59 on page 113

Configuration, see

Table 60 on page 114

PIO.PC2[ N ] Configuration, see

Table 61 on page 115

PIO.PCOMP[

] Compare data, see

Table 63 on page 117

PIO.PMASK[ N ] Compare mask, see

Table 64 on page 117

Type

Address offset

0x1B010000 +

(0x10000 * n)

0x1B010010 +

(0x10000 * n)

0x1B010020 +

(0x10000 * n)

0x1B010030 +

(0x10000 * n)

0x1B010040 +

(0x10000 * n)

0x1B010050 +

(0x10000 * n)

0x1B010060 +

(0x10000 * n)

Table 54: PIO registers

Size

Reset value

All of the registers, except the PIO.PIN

registers, are each associated with 2 additional write-only pseudoregisters which enable bits to be set or cleared individually. These pseudoregisters are described in

Section 5.2.5: Pseudoregisters on page 118

. All registers should be accessed only as aligned 32-bit loads and stores.

The result of any other type of access is undefined.

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PRELIMINARY DATA

109

5.2.1 Output registers

The 3 PIO.POUT

registers are used to specify the data to be output from the port.

Field

POUT

PIO.POUT[n]

(n = 0 to 2)

Bits

[0:7]

Operation

Read

Write

Size

Hard reset

[8:31] 24

Operation

Read

Write

Hard reset

0x1B010000 + (0x10000 * n)

Volatile Synopsis

No Output data for the port

Specifies the output of the port[n]

Returns the current value

0: De-assert pin[i] of port[n]

1: Assert pin[i] of port[n]

If bit[i] is written, pin[i] is affected.

0x00

Reserved -

Reserved

Undefined

Table 55: PIO.POUT[n]

Type

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Register descriptions

The 3 PIO.SET_POUT

pseudoregisters are used to set individual bits in the

PIO.POUT

Registers.

Field

PIO.SET_POUT[n]

(n = 0 to 2)

0x1B010004 + (0x10000 * n)

Bits

[0:7]

Operation

Read

Write

Hard reset

[8:31] 24

Operation

Read

Write

Hard reset

Size Volatile Synopsis

No Sets output data for the port

Sets the output data for port[n]

Undefined

0: Leave bit[i] unchanged

1: Set bit[i] in the POUT[ N ] register

Reserved -

Reserved

Undefined

Table 56: PIO.SET_POUT[n]

Type

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Register descriptions 111

The 3 PIO.CLEAR_POUT[ N ] pseudoregisters are used to clear individual bits in the

P OUT

Field

PIO.CLEAR_POUT[n]

(n = 0 to 2)

0x1B010008 + (0x10000 * n)

Bits

[0:7]

Operation

Read

Write

Hard reset

[8:31] 24

Operation

Read

Write

Hard reset

Size Volatile Synopsis Type

No Clears output data for the port

Clears the output data for port[n]

Undefined

1: Clear bit[i] in the corresponding PIO.POUT[ N ] register

0: Leave bit[i] unchanged

Reserved -

Reserved

Undefined

Table 57: PIO.CLEAR_POUT[n]

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112 Register descriptions

5.2.2 Input registers

The data read from any of these 3 registers will give the logic level present on an input pin of the associated port at the start of the read cycle to the register. The read data will be the last value written to the register regardless of the pin configuration selected

Field

PIO.PIN[n]

(n = 0 to 2)

Bits Size

[0:7]

Operation

Read

Write

Hard reset

[8:31] 24

Operation

Read

Write

Hard reset

0x1B010010 + (0x10000 * n)

Volatile Synopsis

Yes Input data from the port RO

Indicates the logic level present on the input pins bit[i] = logic level of pin[i] of port[n]

Ignored

0x00

Reserved

Undefined

Reserved

Type

Table 58: PIO.PIN[n]

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Register descriptions 113

5.2.3 Configuration registers

There are 3 configuration registers for each of the 3 ports ( PIO.PC0

, PIO.PC1

and

PIO.PC2

) which are used to configure each of the PIO port bits as an input, output, bidirectional, or alternate function pin (if any), with options for the output driver configuration .

Field

PC0

PIO.PC0[n]

(n = 0 to 2)

Bits Size

[0:7]

Operation

Read

Write

Hard reset

[8:31] 24

Operation

Read

Write

Hard reset

0x1B010020 + (0x10000 * n)

Volatile Synopsis

No Configuration register 0

Specifies the configuration of the port[n]

Returns the current value

See

Table 62 on page 116

0x00

Reserved -

Reserved

Undefined

Table 59: PIO.PC0[n]

Type

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Register descriptions

Field

PC1

PIO.PC1[n]

(n = 0 to 2)

Bits Size

[0:7] 8

Operation

Read

Write

Hard reset

[8:31] 24

Operation

Read

Write

Hard reset

0x1B010030 + (0x10000 * n)

Volatile Synopsis

No Configuration register 1

Specifies the configuration of the port[n]

Returns the current value

See

Table 62 on page 116

0x00

Reserved

Undefined

Reserved

Table 60: PIO.PC1[n]

Type

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Register descriptions

Field

PC2

PIO.PC2[n]

(n = 0 to 2)

Bits Size

[0:7] 8

Operation

Read

Write

Hard reset

[8:31] 24

Operation

Read

Write

Hard reset

0x1B010040 + (0x10000 * n)

Volatile Synopsis

No Configuration register 2

Specifies the configuration of the port[n]

Return the current value.

See Table 62 on page 116

0x00

Reserved

Undefined

Reserved

Table 61: PIO.PC2[n]

Type

115

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116 Register descriptions

The selections made by the bits in registers PIO.PC0

, PIO.PC1

and PIO.PC2

for each

I/O bit in each port are given in

Table 62 below.

PIO bit configuration

Bidirectional

Output

Bidirectional

Input

Alternate function output

Alternate function bidirectional

PIO bit output

Weak pull-up

Open drain

Push-pull

Open drain

Hi-Z

Push-pull

Open drain

PC2

Table 62: PIO port bits configuration

PC1

PC0

5.2.4 PIO input compare and compare mask registers

The input compare register ( PCOMP ) holds the value to which the input data from the PIO ports pins will be compared. If any of the input bits are different from the corresponding bits in the PCOMP register and the corresponding bit position in the

PIO Compare mask register ( PMASK ) is set to 1, then the internal interrupt signal for the port will be set to 1.

The compare function is sensitive to changes in levels on the pins and so the change in state on the input pin must be greater in duration than the interrupt response time for the compare to be seen as a valid interrupt by an interrupt service routine.

Note: The compare function is operational in all configurations for a PIO bit including the alternate function modes.

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Register descriptions

Field

PCOMP

PIO.PCOMP[n]

(n = 0 to 2)

Bits Size

[0:7]

Operation

Read

Write

Hard reset

[8:31] 24

Operation

Read

Write

Hard reset

0x1B010050 + (0x10000 * n)

Volatile Synopsis

Yes Input data from the port RO

Indicates the logic level present on the input pins bit[i] = logic level of pin[i] of port[n]

Ignored

0x00

Reserved

Undefined

Reserved

Table 63: PIO.PCOMP[n]

Type

Field

PMask

PIO.PMASK[n]

(n = 0 to 2)

Bits

[0:7] 8

Operation

Read

Write

Hard reset

Size

0x1B010060 + (0x10000 * n)

Volatile Synopsis

Yes Input data from the port RO

Indicates the logic level present on the input pins bit[i] = logic level of pin[i] of port[n]

Ignored

0x00

Table 64: PIO.PMASK[n]

Type

117

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118 Register descriptions

Field

PIO.PMASK[n]

(n = 0 to 2)

Bits Size

[8:31] 24

Operation

Read

Write

Hard reset

0x1B010060 + (0x10000 * n)

Volatile

Reserved

Undefined

Synopsis

Reserved

Table 64: PIO.PMASK[n]

Type

5.2.5 Pseudoregisters

Except for the PIO. PIN[ N ] register, all the PIO registers are each associated with a pair of pseudoregisters, at separate addresses, which allow individual bits within the register to be set or cleared.

These pseudoregisters are all of size 32-bits and write-only.

The PIO.SET

pseudoregister allows bits to be set individually. Writing a 1 in this register sets the corresponding bit in the associated register, a 0 leaves the bit unchanged. The PIO.SET

register is offset 4 bytes from its associated register.

The PIO.CLEAR

pseudoregister allows bits to be cleared individually. Writing a 1 in this register resets the corresponding bit in the associated register, a 0 leaves the bit unchanged. The PIO.CLEAR

register’s address is offset 8 bytes from its associated register’s address. These registers may only be accessed with aligned 32-bit loads and stores. The result of other accesses is undefined.

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Register descriptions 119

Register name

(n = 0 to 2)

PIO.SET_POUT[

]

Description Address offset

PIO.CLEAR_POUT[

PIO.SET_PC0[ N ]

PIO.CLEAR_PC0[

PIO.SET_PC1[

PIO.SET_PC2[

]

PIO.CLEAR_PC1[

]

PIO.CLEAR_PC2[

PIO.SET_PCOMP[

]

PIO.CLEAR_PCOMP[

PIO.SET_PMASK[ ]

PIO.CLEAR_PMASK[

]

N ]

]

Set output data bits

Clear output data bits

Set configuration bits

Clear configuration bits

Set configuration bits

Clear configuration bits

Set configuration bits

Clear configuration bits

Set compare data bits

Clear compare data bits

Set compare mask bits

Clear compare mask bits

0x1B010004 +

(0x10000 * n)

0x1B010008 +

(0x10000 * n)

0x1B010024 +

(0x10000 * n)

0x1B010028 +

(0x10000 * n)

0x1B010034 +

(0x10000 * n)

0x1B010038 +

(0x10000 * n)

0x1B010044 +

(0x10000 * n)

0x1B010048 +

(0x10000 * n)

0x1B010054 +

(0x10000 * n)

0x1B010058 +

(0x10000 * n)

0x1B010064 +

(0x10000 * n)

0x1B010068 +

(0x10000 * n)

Table 65: PIO pseudoregisters

Type

Size

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Register descriptions

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Clock and power management

6.1 Overview

Each ST40 system contains a clock controller macro which is used to control the clocking, power-down and watchdog timers in the system.

These are organized as below.

• One or more clock generators (CPG/CLOCKGEN) each of which supports up to ten clock domains derived from two independently controllable PLLs.

• A power management unit (PMU) used to control the power and clocking status for on-chip modules or systems which may be used to disable clocks to specific modules.

• A watchdog timer (WDT) which triggers specific functions following periods of inactivity such as frequency resynchonizations or soft reset conditions.

The first clock controller block, referred to as CLOCKGEN A, controls the PMU and

WDT features in addition to its own clock domains. The clocks associated with this block are labelled A11 though A15, A2M and A21 through A25 respectively.

Further CLOCKGEN blocks, if present, are referred to as CLOCKGEN B,C,D and so on. Each block has control clock domains labelled from 11 through 25, as for

CLOCKGEN A. The blocks may also be allocated some PMU functionality.

This chapter discusses the general organization and architecture common to all

ST40 systems. However, specific details may vary on some platforms, and the information presented here may be superseded by the product datasheet.

Details of a specific system’s clock and power management organization are available in the product datasheet.

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122 Address map

The address map is divided into a number of regions, a single CPG region which is always associated with CLOCKGEN A, and one or more CLKGEN regions associated with each CLOCKGEN bank. These are labeled CLKGEN[n] where n refers to the bank number A, B, C and so on.

A single bank of four registers controls the CPG block with a separate register bank for each CLOCKGEN block. The base addresses for each register bank is shown in the datasheet.

Some instances of a CLOCKGEN block may not use the full functionality available, so some registers may be reserved and some functions restricted. See the product

datasheet for details.

6.2.1 CPG bank

CPG bank registers are mapped in the ST40 CPU core area starting at the base address given in the system address map.

Name Description Type

Address offset

0x00 CPG.FRQCR

Frequency control register, see

Section 6.3.4.1

CPG.STBCR

Standby control register, see

Section 6.5.4.1

CPG.WTCNT

Watchdog timer counter, see

Section 6.4.3.1

CPG.WTCSR

Watchdog timer status register, see

Section 6.4.3.2

CPG.STBCR2

Standby control register 2, see

Section 6.5.4.2

CPG.FRQCR

Frequency control register 2 is not implemented on ST40 devices.

Table 66: CPGL bank registers

0x04

0x08

0x0C

0x10

0xC0

Access size

R:8, W:16

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Address map 123

These registers except for CPG.FRQCR2

are common to all ST40 and SH-4 variants produced by Hitachi and ST and control features with a direct impact on the CPU such as the CPU clock frequency, and system watchdog behavior.

6.2.2 CLKGEN bank

Each CLOCKGEN block has a dedicated register bank to control its function. If there is more than one CLOCKGEN block in an ST40 implementation then each block and registers functions independently.

Each register is offset from the base address of the CLOCKGEN bank given in the system address map.

Register name where n = [A:Z]

CLKGEN[

].PLL1CR1

].PLL1CR2

].PLL2CR

].STBREQCR

].STBREQCR_SET

].STBREQCR_CLR

].STBACKCR

].CLK4CR

Description Type

Address offset

bank [ N ]

Access size

32 PLL1 control reg 1, see

Section 6.3.4.2

PLL1 control reg2, see

Section 6.3.4.3

PLL2 control register, see

Section 6.3.4.4

Other

0x00

0x08

0x10

0x18 Standby module req, see

Section 6.5.4.1

Set Standby module req, see Section 6.5.4.3

Clear Standby module req, see Section 6.5.4.3

0x20

0x28

Standby module ack, see

Section 6.5.4.4

Clk4 control register selects the proper ratio for pll1_clk4, see

Section 6.3.4.5

0x30

0x38

Table 67: CLOCKGEN bank registers

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Address map

Register name where n = [A:Z]

Description

CLKGEN[ N ].CPG_BYPASS

CLKGEN[

] .

PLL2_MUXCR

].CLK1CR

].CLK2CR

].CLK3CR

].CLK_SELCR

when 1 set by-pass of ratio hardware filtering inside CLOCKGEN, see

Section 6.3.4.6

Pll2_mux_clk control reg

Selects the proper ratio for pll2_mux_clk, see

Section 6.3.4.7

Clk1 control register selects the proper ratio for pll1_clk1 when

CPG_BYPASS is set to

1, see Section 6.3.4.8

Clk2 control register selects the proper ratio for pll1_clk2 when

CPG_BYPASS is set to

1, see Section 6.3.4.9

Clk3 control register selects the proper ratio for pll1_clk3 when

CPG_BYPASS is set to

1, see Section 6.3.4.10

External mux clock selection Control reg.

(Control to CLOCKCON) see Section 6.3.4.11

Table 67: CLOCKGEN bank registers

Type

Address offset

bank [ N ]

Access size

0x40 32

0x48

0x50

0x58

0x60

0x68

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125

6.3.1 Internal organization

The internal organization of each clock controller is shown in

Figure 14 .

XTAL in

27 MHz

CPGL

Bank

FRQCR

FRQCR2

STBCR

STBCR2

B u s pwr_down_ack[7:0]

PLL1

ST40-CLOCKGEN div 1/2

Dividers bank1 x1 x2 x2/3 x3 x4 x6 x8 main_1clk clkstop

RATIO

FILTER

CLOCKGEN A only

PLL1CR1

PLL1CR2

CLK1CR

CLK2CR

CLK3CR ratio

CPG_BYPASS

CLOCKGEN bank

STBREQCR

STBACKCR

CLK4CR

CLK_SELCR

PLL2_MUXCR

PLL2CR

GCK

Clock domain A11

Clock domain A12

Clock domain A13

Clock domain A14 pwr_down_req [7:0] clk_sel [7:0]

PLL2 main_2clk

: 11

: 4

: 8

: 16

: 21

Dividers bank 2

Figure 13: CLOCKGEN architecture

Clock Domain A2M

Clock Domain A21

Clock Domain A22

Clock Domain A23

Clock Domain A24

Clock Domain A25

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Clock functionality

If two or more clock controllers are implemented, the area controlled by the CPG registers is only available on CLOCKGEN A.

Figure 14 shows how they are

organized.

27 MHz

CPGL

SuperHyway

ST40-CLOCKGEN A

PLL1

DIV bank1 sel ratio filt clk domain A11 clk domain A12 clk domain A13 clk domain A14

Control

Low Power

PLL2

DIV bank2

:11

:16

:21 clockgena_clk_sel[7:0] clockgena_stb_req[7:0] clk domain A2M clk domain A21 clk domain A22 clk domain A23 clk domain A24 clk domain A25

ST40-CLOCKGEN B

PLL1

DIV bank1 sel clk domain B11 clk domain B12 clk domain B13 clk domain B14 ratio filt

PPC

Control clockgenb_clk_sel[7:0] clockgenb_stb_req[7:0]

Low Power

PLL2

DIV bank2 clk domain B2M clk domain B21 clk domain B22 clk domain B23 clk domain B24 clk domain B25

Figure 14: ST40 clock architecture

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Clock functionality

The correspondence between clock domains and peripherals is tabulated in the

product datasheet.

6.3.2 PLL1 control

Diagram

127 external-clock x2 _p ll1e na

1 cpg _b ypa ss sin ch _sh _p ll1e n sin ch_ stb _p ll1e n sinc h_ sh_ pll1 en x2_istp

Clockin

PLL1

PLL Config

Clock

Lock en clk deglitcher

GBUF en

PLLclock en clk deglitcher en clk deglitcher

1 en clk deglitcher

Mdiv Ndiv Pdiv PllSetup PllPowerOn

PLL1CR1

PllOutEn Lock sin ch_ stb _p ll1e n

STBpllen STBPllensel STBfastsel STBmode

PLL1CR2 note: this symbol means a synchronization stage that can cause a delay of two stage.

2*main clk

Figure 15: Configuration and control of PLL1 using the PLL1CR1 and PLL1CR2 registers

Introduction

The frequency and behavior of clocks associated with PLL1 may be controlled using three methods:

• by enabling or disabling PLL1 and bypassing the PLL function,

• by changing the frequency division ratio of each clock domain,

• by changing the configuration of PLL1.

To ensure that a stable clock is delivered whilst a change is occurring, the PLL control logic should follow only those state transactions shown

Figure 16 . You

should take care when changing PLL frequencies or relative clock ratios that:

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Clock functionality

• the PLL is stable before re-enabling clocks,

• there is no communications traffic between semi-synchronous domains when changing relative clock ratios.

The PLL frequency is defined by the contents of the MDIV, NDIV and PDIV in the

CLKGEN.PLL1CR1

Allowable transitions start-up (mode 6 & 7) sh_run_slow ratio encoded cpg_bypass=0

CLOCKGEN PLL1 valid states

(related to PLL1) sh2st_slow st2sh_slow program PLL1CR1

(PLL dividers) and CPGL-WDT st_run_slow ratio encoded cpg_bypass=0 no ratio encoded cpg_bypass=1 program PLL1CR1

(PLL dividers) st_leaving_slow after PLL locked sh_run_fast ratio encoded cpg_bypass=0 start-up (mode 0 to 5) sh2st_fast st2sh_fast

_fast: clock source is PLL1

_slow: clock source is external xosc @ 27 MHz sh_: control by FRQCR st_: control by PLL1CR2

Figure 16: CLOCKGEN A PLL1 valid states st_run_fast ratio encoded cpg_bypass=0 no ratio encoded cpg_bypass=1

States labelled sh_xxx are available for CLOCKGEN A only,

States labeled st_xxx are available for all CLOCKGEN macros.

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Clock functionality 129

State definitions

Register fields sh_run slow sh_run fast st_run slow st_run fast st_leaving slow sh2st slow sh2st fast st2sh slow st2sh fast

1 1 0 1 1 PLL1CR1.

PLLOUTEN

PLL1CR2.

STBPLLEN

PLL1CR2.

STBPLLENSEL

PLL1CR2.

STFASTSEL

PLL1CR2.

STBMODE

(CPGL)FRQCR.

PLL1EN

CPG_BYPASS

0 -

Table 68: Allowed configurations for CLOCKGEN A and CPGL.FRQCR registers

A. - don’t care

Enabling and disabling PLL1

Software may enable or disable the CLOCKGEN A PLL1 by changing the clock source from PLL1 to the external xosc clock directly. The internal clock is then preset to the xosc frequency/2.

This is achieved by placing the CLOCKGEN PLL in either the SH_RUN_SLOW or

ST_RUN_SLOW state.

Changing PLL1 divide ratios (clk1 to 3)

The frequency of a CLOCKGEN output clock may be changed by updating its divide ratio.

For clocks 11 through 13, CLOCKGEN ensures a safe transition between the two frequencies, whilst for clock 14, the user is responsible for stopping the clock before modifying the ratios.

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Whilst the transition is guaranteed for clocks 11 through 13, the user must ensure the target module functions correctly during this period. Some modules such as

UARTs require stable frequencies during operation. Others are associated with more than one clock and are unable to function correctly if the ratio between those clocks changes whilst the module is active.

Restrictions may apply. As an example, in some ST40 systems, the CPU has direct dependencies on two clock domains, I-Clk and P-Clk. Changes in relative frequency between these clocks whilst the CPU is active may lead to undefined behavior. For the ST40 CPU, I-Clk must be an integer multiple of the P-Clk frequency. The maximum supported frequencies are in the product datasheet.

Two methods are supported for changing PLL1 divide ratios.

• CPGL mode (allowed only for CLOCKGEN A clocks)

If CLKGEN.CPG_BYPASS

is inactive (set to 0), CLOCKGEN A is in CPGL mode.

The frequency of clocks 11 through 13 may be changed by reprogramming

CPG.FRQCR

. CPGL mode is the default for CLOCKGEN A clocks.

• ST mode

If CLKGEN.CPG_BYPASS

is active (set to 1), the CLOCKGEN macro is in ST mode.

The frequency of clocks 11 through 13 may be changed by programming

CLKGEN.CLK1CR

, CLKGEN.CLK2CR

and CLKGEN.CLK3CR

respectively.

Changing the PLL1 divide ratio for clock 14

The frequency of clock 14 may be changed by updating the CLKGEN.CLK4CR

1 Stop clock 14 by asserting (setting to 1) CLKGEN.CLK4CR.CLKSTOP

2 Change the field ratio of CLKGEN.CLK4CR

3 Restart clock 14 by de-asserting (setting to 0) CLKGEN.CLK4CR.CLKSTOP

Changing PLL1 lock frequency

The ST40 CLOCKGEN macro includes a highly flexible PLL which may be programmed to output a range of frequencies. This is achieved by updating the

MDIV, NDIV and PDIV fields of CLKGEN.PLL1CR1

. However whilst the PLL is locking-on the new frequency, the clock outputted by the macro is unstable.

Software should ensure there is no activity in parts of the system associated with the PLL. There are two methods of handling this. You can either put the system to

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Clock functionality 131 sleep, and use the watchdog to restart the system when the PLL clocks are stable, or bypass the PLL and use an external clock during the period of instability.

Examples of these procedures are described below.

SH procedure: CLOCKGENA only

1 Move CLOCKGEN to state sh_run_slow.

This action disables the PLL1 and sets the CLOCKGEN clock source to the external crystal (27 MHz).

Note: the maximum clock rate is half of the input clock rate (see

Figure 14 and

Figure 15 ).

2 Update PLL1 using the MDIV, NDIV and PDIV fields of CLKGEN.PLL1CR1

Only values defined in the datasheet are valid, other values may lead to undefined behavior.

3 Program the WDT to provide the specified oscillation stabilization time before timing out.

The WDT should have the following settings:

CPG.WTCSR

CPG.WTCNT

4 Move CLOCKGEN to STATE sh_run_fast.

This puts the CPU in a suspend state until the WDT countdown completes, at which point the PLL is re-enabled and clocks 11 through 14 are restarted using the new

PLL frequency.

ST procedure

1 Move CLOCKGEN to state st_run_slow.

This action disables PLL1 and selects the external crystal clock as the input to the system bypassing PLL1. The internal clock frequency is a divisor of half the external clock ratio as determined by the clock 11 through 14 divide ratios.

2 Update PLL1 using the MDIV, NDIV and PDIV fields of CLKGEN.PLL1CR1

Only values defined in the datasheet are valid, other values may lead to undefined behavior.

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132 Clock functionality

3 Move CLOCKGEN to state st_leaving_slow.

PLL1 is enabled, but is still bypassed.

for to reach 1.

This indicates the PLL has stabilized.

5 Move CLOCKGEN to state st_run_fast.

The clock source for clocks 11 through 14 to the PLL is changed rather than the external x-tal clock.

Note: no clocks are stopped using the ST procedure.

PLL frequency calculation

Details of the relationship between CLKGEN.PLL1CR1.[MDIV, NDIV, PDIV] and the

PLL frequency are available in the product datasheet.

6.3.3 Configuring PLL2

Introduction pci_host pci_clkin external-clock

Clockin

PLL2

PLL Config

Clock

Lock

GBUF en PLLclock

PCIclock

Mdiv Ndiv Pdiv PllSetup PllPowerOn PllOutEn LockSelect Lock

Figure 17: Configuration and control of PLL2 using the PLL2CR registers

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There are two ways of changing the frequency of clocks associated with the PLL2 clock:

• enabling or disabling PLL2,

• changing the configuration of PLL2.

The procedures are discussed below, for details on specific PLL settings refer to the datasheet for that device.

Procedure to enable and disable PLL2

CLOCKGEN PLL2 is disabled by writing 0 to CLKGEN.PLL2CR.PLLOUTEN

and

CLKGEN.PLL2CR.LOCKSELECT.

It is enabled by writing 1 to CLKGEN.PLL2CR.PLLOUTEN

and

CLKGEN.PLL2CR.LOCKSELECT.

In some systems it may be possible to bypass PLL2, see datasheet for details.

Changing the frequency of PLL2

The PLL2 derived clocks are generated by CLOCKGEN using PLL2 which is a programmable PLL.

PLL2 takes the input frequency from the external qx_xtalout27 clock, which runs at

27 MHz. It is possible to change the output frequency of this PLL by changing the value of its MDIV, NDIV and PDIV. This can be achieved programming the corresponding fields of the configuration register PLL2CR .

To change the PLL2 output frequency to a value different from at start up, use the following procedure.

1 Write 0 in the PLL2CR register fields PLLOUTEN and LOCKSELECT.

This allows CLOCKGEN to stop the PLL2 clockout (PLL2 clock = 0).

2 Disable PLL2 by setting PLL2CR.PLLPOWERON

to 0.

3 Change the division and multiply ratios of PLL2 by updating the values of the

MDIV, NDIV and PDIV fields of the PLL2CR register, as defined by the datasheet.

4 Restart PLL2 by setting PLL2CR.PLLPOWERON

to 1.

5 Set the LOCKSELECT field of PLL2CR to 1 to enable output of the PLL2 clock when the lock is achieved.

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134 Clock functionality

This is the recommended way to enable the output of the PLL clock. However alternatively you can poll CLKGEN.PLL2CR.LCK

until active and then select the

PLL2 clockout by setting CLKGEN.PLL2CR.PLLOUTEN

to 1.

6.3.4 Register description

Frequency control register 1 (CPG.FRQCR)

The clock frequency division ratios are controlled by the FRQCR register in the CPG bank.

Field

RATIO

CPG.FRQCR

0x00

Bits

Read

Write

Hard reset

Size Volatile

[0:8]

Operation

9 No

Synopsis

Clock frequency division ratios

Type

Specifies the frequency ratios with respect to the Output of

PLL circuit 1 output frequency

Refer to the product datasheet for details

Use of invalid values may lead to undefined behavior

Returns current value

Updates current value

Set by MD0,MD1 and MD2 pins

See product datasheet for details

No Reserved RW 9

Operation

Read

Write

Hard reset

Returns current value

Updates current value

Table 69: CPG.FRQCR

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Field

PLL1EN

CPG.FRQCR

0x00

Bits Size Volatile

Operation

Read

Write

1 No PLL Circuit 1 enable

Returns current value

0: PLL 1 is not used

1: PLL1 is used

Synopsis

Specifies whether PLL 1 is used

Type

Reserved RW

Hard reset

11 1

Operation

Read

Write

Hard reset

[12:15] 4

Operation

Read

Write

Hard reset

Returns current value

Updates current value

Reserved

Returns 0

Ignored

Reserved Res

Table 69: CPG.FRQCR

Valid FRQCR values and the associated ratios are defined for each product and listed in the product datasheet.

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CLKGEN.PLL1CR1

This register defines the behavior of PLL 1.

Field

MDIV

NDIV

CLOCKGEN.PLL1CR1

PLL1 control Register

0x00

Bits

[0:7]

Operation

Read

Write

Hard reset

[8:15]

Operation

Read

Write

Hard reset

Size Volatile

Pre-divider

Returns current value

Synopsis

Parameter for programming PLL1

Type

Other

Updates current value

Note: this register has a write lock

Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.

See datasheet

Feedback divider

Parameter for programming PLL1

Returns current value

Other

Updates current value

Note: this register has a write lock

Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.

See the product datasheet

Table 70: CLOCKGEN.PLL1CR1

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Field

PDIV

SETUP

CLOCKGEN.PLL1CR1

PLL1 control Register

POWERON

0x00

Bits Size Volatile

[16:18] 3

Operation

Read

Write

Hard reset

[19:27]

Operation

Read

Write

Hard reset

Operation

Read

Write

Hard reset

Post divider

Returns current value

Synopsis

Parameter for programming PLL1

Type

Other

Updates current value

Note: this register has a write lock

Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.

See datasheet

Loop characteristics

Parameter for programming PLL1

Other

Returns current value

Updates current value

Note: this register has a write lock

Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.

See datasheet

PLL1 Power On

Specifies the power setting of PLL1

1: power on

0: power off

Ignored

See the product datasheet

Table 70: CLOCKGEN.PLL1CR1

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CLOCKGEN.PLL1CR1

PLL1 control Register

0x00

Field

OUTENABLE 29

Operation

Read

Write

LOCK

Bits

Read

Write

Size Volatile

Hard reset

30 1

Operation

Hard reset

Operation

Read

Write

Hard reset

Synopsis

Enable output of PLL clock

Allows s/w control of PLL1 output clock

Type

Other

Returns current value

Updates current value

1: PLL1 out Enabled

0: PLL1 out not Enabled

Note: this register has a write lock

Yes PLL Circuit 1 Lock achieved RO

Specifies whether PLL 1 output has achieved lock and the output is stable

0: PLL 1 Lock not achieved

1: PLL1 is Locked

Updates current value.

Note: this register has a write lock

Res -

Reserved

Returns 0

Ignored

Table 70: CLOCKGEN.PLL1CR1

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A. CLOCKGEN.PLL1CR1 is writable if

(PLL1CR2.STBPLLENSEL = 0 and FRQCR.PLL1EN = 0) or

(PLL1CR2.STBPLLENSEL= 1 and

PLL1CR2.STBPLLEN = 0)

139

CLKGEN.PLL1CR2

This register defines the behavior of PLL 1.

Field

STBPLLEN

CLOCKGEN.PLL1CR2

PLL1 control Register

Bits

Read

Write

Hard reset

Size

Operation

1 -

Volatile

0x08

Synopsis

PLL1 enable

Table 71: CLOCKGEN.PLL1CR2

Type

Alternative enable to the FRQCR.PLL1EN field See

This field specifies whether PLL1 is enabled when

STBPLLENSEL is 1, otherwise it has no effect

Returns current value

1: enabled

0: not enabled AND selected the external-clock as input clock

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STBFASTSE

CLOCKGEN.PLL1CR2

PLL1 control Register

Field

STBPLLENS

Bits Size Volatile

0x08

Synopsis Type

Operation

Read

Write

Hard reset

Operation

Read

Write

Hard reset

PLL1 enable selector.

Selects if PLL1 is enabled by FRQCR.PLL1EN or

STBPLLEN.

See

Returns current value

Updates current value

0: FRQCR.PLL1EN specifies enabling

1: STBPLLEN specifies enabling

Clock selector RW

Select if 2*main clock is set to PLL1_CLOCK (fast) or to external clock from the xtal.

The switch is synchronized

Note: Selection take place only if STBMODE field is set to

1 see

Returns current value

Updates current value

1: 2*main_clock equal to PLL1 clock (fast clock)

0: 2*main_clock equal to external clock

Table 71: CLOCKGEN.PLL1CR2

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CLOCKGEN.PLL1CR2

PLL1 control Register

0x08

Field Bits Size Volatile Synopsis Type

STBMODE 3

Operation

Read

Write

Hard reset

[4:31]

Operation

Read

Write

Hard reset

Clock selector

Select if 2*main_clock is controlled by

PLL1CR.STBFASTSEL or FRQCR.PLL1EN see

Figure 18 shows a block diagram of the WDT.

Returns current value

Updates current value

1: control given to PLL1CR.STBFASTSET

0: control given to FRQCR.PLL1EN

Reserved

Returns 0

Ignored

Reserved

Table 71: CLOCKGEN.PLL1CR2

Res

A. Write lock operation

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CLKGEN.PLL2CR

This register defines the behavior of PLL 2.

Field

MDIV

NDIV

CLOCKGEN.PLL2CR

PLL2 control Register

0x10

Bits

Hard reset

[8:15]

Operation

Read

Write

Hard reset

Size Volatile

[0:7]

Operation

Read

Write

Pre-divider

Returns current value

Synopsis

Parameter for programming PLL2

Type

Updates current value

Note: Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.

See product datasheet

RW Feedback divider

Parameter for programming PLL2

Returns current value

Updates current value

Note: Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.

See product datasheet

Table 72: CLOCKGEN.PLL2CR

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CLOCKGEN.PLL2CR

PLL2 control Register

0x10

Field Bits Size Volatile Synopsis Type

PDIV

SETUP

[16:18] 3

Operation

Read

Write

Hard reset

[19:27] 9

Operation

Read

Write

Hard reset

POWERON 28 1

Operation

Read

Write

Hard reset

Post divider

Parameter for programming PLL2

Returns current value

Updates current value

Note: Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.

See product datasheet

Loop characteristics

Parameter for programming PLL2

Other

Returns current value

Updates current value

Note: Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.

See product datasheet

PLL2 Power On

Specifies the power setting of PLL2

1: power on

0: power off

Ignored

See product datasheet

Table 72: CLOCKGEN.PLL2CR

143

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CLOCKGEN.PLL2CR

PLL2 control Register

0x10

Field Bits Size Volatile Synopsis Type

PLLOUTEN 29

Operation

Read

Write

LOCKSELE

LOCK

Hard reset

Operation

Read

Write

Hard reset

Operation

Read

Write

Hard reset

Enable output of PLL2 clock

Allows s/w control of PLL2 output clock

Returns current value

Updates current value

1: PLL out Enabled

0: PLL out not Enabled

See product datasheet

Yes Selects how the PLL2 is enabled RW

Specifies whether PLL2 output should be enabled when lock is achieved or as indicated by PLLOUTEN field

Returns current value

0: PLLOUTEN setting governs PLL2 output

1: Lock setting governs PLL PCIoutput

See product datasheet

Yes PLL2 Lock achieved RO

Specifies whether PLL2 output has achieved lock and the output is stable

0: PLL2 Lock not achieved

1: PLL2 is Locked

Updates current value

See product datasheet

Table 72: CLOCKGEN.PLL2CR

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Clock functionality

CLOCKGEN.CLK4CR

CLK4CR allows software to change the division ratio of this clock.

CLOCKGEN.CLK4CR

PLL1 Clock 4 control register

Field

RATIO

CLKSTOP

0x38

Bits

[0:2]

Size Volatile

3 -

Synopsis Type

Division ratio of PLL1CLK4 clock

with respect of output of PLL1 div 2

Operation

Read

Write

Hard reset

3 1

Operation

Read

Write

Hard reset

Returns current value

000: ratio 1:1

001: ratio 1:2

010: ratio 1:3

011: ratio 2:3

100: ratio 1:4

101: ratio 1:6

110: ratio 1:8

111: ratio 1:8.

see datasheet

PLL1 enable selector.

This bit allows stopping of the PLL1CLK4 clock

Returns current value

Updates current value

0: PLL1CLK4 clock active

1: PLL1CLK4 clock stopped

Table 73: CLOCKGEN.CLK4CR

145

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CLOCKGEN.CLK4CR

PLL1 Clock 4 control register

Field

0x38

Bits Size Volatile

[4:31]

Operation

Read

Write

Hard reset

Reserved

Returns 0

Ignored

Reserved

Synopsis

Table 73: CLOCKGEN.CLK4CR

Type

Res

To safely change the value of the division ratio of the PLL1CLK4 clock the following sequence should be followed:

1 Stop PLL1CLK4 clock by setting CLK4CR.CLKSTOP = 0

2 Write the new setting in CLK4CR.RATIO

3 Restart PLL1CLK4 clock by setting PLL1CLK4.CLKSTOP

= 1

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Clock functionality

CLOCKGEN.CPGBYPASS

Field

BYPASS

Bits

[0]

Operation

Read

Write

Hard reset

[1:31]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis Type

No master control source for clocks 11 -

0: PLL1 clocks 1, 2, 3 controlled by CPG.FRQCR

1= PLL1 clocks controlled as below

CLKGEN.CLK1CR controls clock 11

CLKGEN.CLK2CR controls clock 12

CLKGEN.CLK3CR controls clock 13

Returns current value

Updated

See product datasheet

—

Reserved

Reserved Res

Reserved

0: ignored, other values undefined

Table 74: CLOCKGEN.CPGBYPASS

147

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Clock functionality

CLKGEN.PLL2_MUXCR

CLOCKGEN.PLL2_MUXCR

Field

MUXCTRL

Bits

[1:0]

Operation

Read

Write

Hard reset

[2:31] 28

Operation

Read

Write

Hard reset

Size Volatile

Synopsis

No Controls division ratio of clock 2M with respect to the output of PLL2

00: Ratio 1:8

01: Ratio 1:16

10: Ratio 1:21

11: Ratio 1:1

Returns current value

Updates current value

See product datasheet

— Reserved

Reserved

0: ignored, other values undefined

Table 75: CLOCKGEN.PLL2_MUXCR

Type

Res

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CLKGEN.CLK1CR

Field

RATIO

CLKSTOP

CLOCKGEN.CLK1CR

Bits

[2:0]

Operation

Read

Write

Hard reset

[3]

Operation

Read

Write

Hard reset

[2:31] 28

Operation

Read

Write

Hard reset

Size Volatile

Synopsis Type

No clock ratio control when

CLKGEN.CPG_BYPASS active

Controls the ratio of clock with respect to PLL1 division 2

000: 1:1 100: 1:4

001: 1:2

010: 1:3

011: 2:3

101: 1:6

110: 1:8

111: 1:8

Returns current value

Updated

See product datasheet

No Clock 11 enable override

1: clock 11 disabled

0: clock 11 enabled

Returns current value

Updated

See product datasheet

Reserved

0: ignored, other values undefined

Res

Table 76: CLOCKGEN.CLK1CR

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Clock functionality

CLKGEN.CLK2CR

Field

RATIO

CLKSTOP

CLOCKGEN.CLK2CR

Bits

[2:0]

Operation

Read

Write

Hard reset

[3]

Operation

Read

Write

Hard reset

[2:31] 28

Operation

Read

Write

Hard reset

Size Volatile

Synopsis Type

No clock ratio control when

CLKGEN.CPG_BYPASS active

Controls the ratio of clock with respect to PLL1 division 2

000: 1:1 100: 1:4

001: 1:2

010: 1:3

011: 2:3

101: 1:6

110: 1:8

111: 1:8

Returns current value

Updated

See product datasheet

No Clock 12 enable override

1: clock 11 disabled

0: clock 11 enabled

Returns current value

Updated

See product datasheet

Reserved

0: ignored, other values undefined

Res

Table 77: CLOCKGEN.CLK2CR

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Clock functionality 151

CLKGEN.CLK3CR

Field

RATIO

CLKSTOP

CLOCKGEN.CLK3CR

Bits

[2:0]

Operation

Read

Write

Hard reset

[3]

Operation

Read

Write

Hard reset

[2:31] 28

Operation

Read

Write

Hard reset

Size Volatile

Synopsis Type

No clock ratio control when

CLKGEN.CPG_BYPASS active

Controls the ratio of clock with respect to PLL1 division 2

000: 1:1 100: 1:4

001: 1:2

010: 1:3

011: 2:3

101: 1:6

110: 1:8

111: 1:8

Returns current value

Updated

See product datasheet

No Clock 13 enable override

1: clock 11 disabled

0: clock 11 enabled

Returns current value

Updated

See product datasheet

Reserved

0: ignored, other values undefined

Res

Table 78: CLOCKGEN.CLK3CR

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CLKGEN.CLK_SELCR

CLOCKGEN.CLK_SELCR

Field Bits Size Volatile

EXTCLKSEL [7:0]

Operation

Read

Write

Hard reset

[2:31] 28

Operation

Read

Write

Hard reset

Synopsis

No Clock mux control

See product datasheet

Returns current value

Updates current value see product datasheet

Reserved

0: ignored, other values undefined

Table 79: CLOCKGEN.CLK_SELCR

Clock functionality

Type

Res

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Watchdog timer

6.4.1 Block diagram

WDT

Standby release

Internal reset request

Standby control

Reset control

Interrupt request

Interrupt control

Frequency divider

WTCSR

Clock selection

Overflow

WTCNT

Clock selector

Clock

Bus interface

Standby mode

Frequency divider 2 × 1 clock

WTCSR: Watchdog timer control/status register

WTCNT: Watchdog timer counter

Figure 18: Block diagram of WDT

153

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154 Watchdog timer

6.4.2 Register configuration

The WDT has the two registers summarized in

Table 80 . These registers control

clock selection and timer mode switching.

Name

Watchdog timer counter

Watchdog timer control/ status register

Abbreviation Type

Initial value

CPG.WTCNT

RW* 0x00

CPG.WTCSR

RW* 0x00

Area 7 address

Access size

0x1FC00008 R: 8, W:

16*

0x1FC0000C R: 8, W:

16*

Table 80: WDT registers

Note: Use word-size access when writing. Perform the write with the upper byte set to 0x5A or 0xA5, respectively. Byte-size and longword-size writes cannot be used.

Use byte access when reading.

6.4.3 Register descriptions

Watchdog timer counter (CPG.WTCNT)

The watchdog timer counter ( CPG.WTCNT

is an 8-bit read/write counter that counts up on the selected clock. When CPG.WTCNT

overflows, a reset is generated in watchdog timer mode, or an interrupt in interval timer mode. CPG.WTCNT

is initialized to 0x00 only by a power-on reset via the NOT_RESET pin.

To write to the CPG.WTCNT

counter, use a word-size access with the upper byte set to 0x5A. To read CPG.WTCNT

, use a byte-size access.

Bit 7 6 5 4 3 2 1 0

Initial value

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Watchdog timer control and status register (CPG.WTCSR)

The watchdog timer control and status register ( CPG.WTCSR

) is an 8-bit read/write register containing bits for selecting the count clock and timer mode, and overflow flags.

CPG.WTCSR

is initialized to 0x00 only by a power-on reset via the NOT_RESET pin.

It retains its value in an internal reset due to WDT overflow. When used to count the clock stabilization time when exiting standby mode, CPG.WTCSR

retains its value after the counter overflows.

To write to the CPG.WTCSR

, use a byte-size access.

Bit

Initial value

TME

6 5

WT/

NOT_IT

RSTS

WOV

IOVF CKS2 CKS1 CKS0

Bit 7: timer enable (TME)

Bit 7 specifies the starting and stopping of timer operation. Clear this bit to 0 when using the WDT in standby mode or to change a clock frequency.

Bit 7: TME Description

Up-count stopped, WTCNT value retained

Up-count started

(Initial value)

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Bit 6: timer mode select (WT/NOT_IT)

Bit 6 specifies whether the WDT is used as a watchdog timer or interval timer.

Note: the up-count may not be performed correctly if WT/NOT_IT is modified while the

WDT is running.

Description

Bit 6: WT/NOT_IT

Interval timer mode

Watchdog timer mode

(Initial value)

Bit 5: reset select (RSTS)

Bit 5 specifies the kind of reset to be performed when CPG.WTCNT

overflows in watchdog timer mode. This setting is ignored in interval timer mode.

Bit 5: RSTS Description

Power-on reset

Manual reset

(Initial value)

Bit 4: watchdog timer overflow flag (WOVF)

Bit 4 indicates that CPG.WTCNT

has overflowed in watchdog timer mode. This flag is not set in interval timer mode.

Bit 4: WOVF

Description

No overflow

CPG.WTCNT has overflowed in watchdog timer mode

(Initial value)

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Watchdog timer 157

Bit 3: interval timer overflow flag (IOVF)

Bit 3 indicates that CPG.WTCNT

has overflowed in interval timer mode. This flag is not set in watchdog timer mode.

Bit 3: IOVF

Description

No overflow

CPG.WTCNT has overflowed in interval timer mode

(Initial value)

Bits 2 to 0: clock select 2 to 0 (CKS2 to CKS0)

These bits select the clock used for the CPG.WTCNT

count from eight clocks obtained by dividing the frequency divider two input clock. The overflow periods shown in the following table are based on a 150 MHz X1 output from the main clock divider. The up-count may not be performed correctly if bits CKS2 to CKS0 are modified while the WDT is running. Always stop the WDT before modifying these bits.

Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0

Description

Clock division ratio

1/32

1/64

1/128

1/256

1/512

1/1024

1/2048

1/4096

Overflow period

µ s

109

µ s

219

µ s

437

µ s

874

µ s

1.75 ms

3.5 ms

6.99 ms

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Watchdog timer

Writing to CPG.WTCNT and CPG.WTCSR

The watchdog timer counter ( CPG.WTCNT

) and watchdog timer control and status register ( CPG.WTCSR

) differ from other registers in being more difficult to write to.

These registers must be written to with a word transfer instruction. They cannot be written to with a byte or longword transfer instruction.

When writing to CPG.WTCNT

, perform the transfer with the upper byte set to 0x5A and the lower byte containing the write data.

When writing to CPG.WTCSR

, perform the transfer with the upper byte set to 0xA5 and the lower byte containing the write data.

This transfer procedure writes the lower byte data to CPG.WTCNT

or CPG.WTCSR

The write formats are shown in

Figure 19 .

WTCNT write

Address: H'FFC00008

(H'1FC00008)

H'5A

8 7

Write data

WTCSR write

Address: H'FFC0000C

(H'1FC0000C)

H'A5

8 7

Figure 19: Writing to WTCNT and WTCSR

Write data

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Watchdog timer 159

6.4.4 Using the WDT

Standby clearing procedure

The WDT is used when clearing standby mode by means of an NMI or other interrupt. The procedure is shown below. As the WDT does not operate when standby mode is cleared with a reset, the NOT_RESET pin should be held low until the clock stabilizes.

1 Be sure to set the TME bit in the CPG.WTCSR

register to 0 before making a transition to standby mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows.

2 Select the count clock to be used with bits CKS2 to CKS0 in the CPG.WTCSR

counter. Make these settings so that the time until the count overflows is at least as long as the clock oscillation stabilization time.

3 Make a transition to standby mode, and stop the clock, by executing a SLEEP instruction.

4 The WDT starts counting on detection of an NMI signal transition edge or an interrupt.

5 When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the CPG.WTCSR

6 The counter stops at a value of 0x000x01. The value at which the counter stops depends on the clock ratio.

Frequency changing procedure

The WDT is used in a frequency change using the PLL. It is not used when the frequency is changed simply by making a frequency divider switch.

1 Be sure to set the TME bit in the CPG.WTCSR

register to 0 before making a frequency change. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows.

2 Select the count clock to be used with bits CKS2 to CKS0 in the CPG.WTCSR

counter. Make these settings so that the time until the count overflows is at least as long as the clock oscillation stabilization time.

3 When the frequency control register ( CPG.FRQCR

) is modified, the clock stops, and the standby state is entered temporarily. The WDT starts counting.

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Watchdog timer

4 When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the CPG.WTCSR

5 The counter stops at a value of 0x00-0x01. The value at which the counter stops depends on the clock ratio.

Using watchdog timer mode

1 Set the WT/NOT_IT bit in the CPG.WTCSR

register to 1, select the type of reset with the RSTS bit, and the count clock with bits CKS2-CKS0, and set the initial value in the CPG.WTCNT

counter.

2 When the TME bit in the CPG.WTCSR

3 During operation in watchdog timer mode, write 0x00 to the counter periodically so that it does not overflow.

4 When the counter overflows, the WDT sets the WOVF flag in the CPG.WTCSR

Using interval timer mode

When the WDT is operating in interval timer mode, an interval timer interrupt is generated each time the counter overflows. This enables interrupts to be generated at fixed intervals.

1 Set the WT/NOT_IT bit in the CPG.WTCSR

counter.

2 When the TME bit in the CPG.WTCSR

3 When the counter overflows, the WDT sets the IOVF flag in the CPG.WTCSR

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6.5 Power management unit (PMU)

The power management unit is responsible for controlling clock shutdown and startup for each of the on-chip modules. The power states are organized into a number of power down modes, each of which specify which modules are operating and which are halted. There are two sets of registers in the power management

Clock domains (From CPG/CLOCKGEN)

STATUS0

STATUS1

CPG

STBCR

STBCR2

PMU

CLOCKGEN

STBREQCR

STBACKCR

...

Module 1 Module 2 Module 3 Module n

Figure 20: Power management module function unit. The CPG bank registers STBCR and STBCR2 control the power down modes and also the individual power-down state of legacy SH peripherals. The

CLOCKGEN bank registers controls the power-down state of the ST40RA peripherals (PCI, DMAC, LMI and FMI).

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Power management unit (PMU)

6.5.1 Types of power-down modes

The following power-down modes and functions are provided:

• sleep mode,

• deep sleep mode,

• standby mode,

• module standby function (for individual power-down of on-chip peripheral modules).

Table 81 shows the conditions for entering these modes from the program execution

state, the status of the CPU and peripheral modules in each mode, and the method of exiting each mode.

Power down mode

Sleep

Deep sleep

Status

Entering conditions

CPG

SLEEP instruction executed while STBY bit is 0 in

STBCR

DMAC module is put into standby

Followed by the memory interface(s) being put into standby.

Then the

SLEEP instruction is executed while STBY bit is 0 in

STBCR.

Operating

CPU

Onchip memory

Halted

(registers held)

Held

Halted

(registers held)

Held

On-chip peripheral modules

Operating

Pins

Held

Operating

(DMA halted)

Held

External memory

Refreshing

Self- refreshing

Table 81: Status of CPU and peripheral modules in power-down modes

Exiting method

Interrupt

Reset

Interrupt

Reset

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Power management unit (PMU) 163

Status

Power down mode

Entering conditions

CPG CPU

Onchip memory

On-chip peripheral modules

Pins

External memory

Exiting method

Standby

Module standby

SLEEP instruction is executed while STBY bit is 0 in

STBCR.

SLEEP instruction executed while STBY bit is 1 in

STBCR

Setting

MSTP bit to 1 in STBCR or setting a bit in the

STBREQCR.

Halted

Operating

Halted

(registers held)

Operating

Held

Halted*

Specified modules halted*

Held

All external memory

Self- refreshing

Refreshing

Interrupt

Reset

Clearing

MSTP bit/

STBRE

QCR bit to 0

Reset

Table 81: Status of CPU and peripheral modules in power-down modes

Note: The RTC operates when the START bit in RTC.RCR2

is 1 (see chapter about

Real-time clock).

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Power management unit (PMU)

6.5.2 Register configuration

Table 82 and Table 83 show the registers used for power-down mode control.

Description

Standby control register

Register name

CPG.STBCR

Type

Initial value

0x00

CPG offset

0x04

0x10

Table 82: CPG bank power down registers

Access size

Description Register name Type

Initial value

CLOCKGE

N offset

Standby module request CLOCKGEN.STBREQCR

Set Standby module req CLOCKGEN.STBREQCR_SET

Clear Standby module req

CLOCKGEN.STBREQCR_CLR

Standby module acknowledge

CLOCKGEN.STBACKCR

0x00

Table 83: CLOCKGEN bank power-down registers

0x18

0x20

0x28

0x30

Acces s size

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Power management unit (PMU)

6.5.3 Pin configuration

Table 84 shows the pins used for power-down mode control.

Pin Name

Processor status 1

Processor status 0

Abbreviation I/O Function

STATUS1

STATUS0

Output Indicate the processors operating status

HH: Reset

HL: Sleep mode

LH: Standby mode

LL: Normal operation

Table 84: Power-down mode pins

A. H: high level

L: low level

165

6.5.4 Register descriptions

Standby control register

(CPG.STBCR)

The standby control register ( CPG.STBCR

) is an 8-bit read/write register that specifies the power- down mode status. It is initialized to 0x00 by a power- on reset via the NOT_RESET pin or due to watchdog timer overflow.

Bit 7 6

STBY PHZ

Initial value 0

RW RW

5 4 3 2 1 0

PPU MSTP4 MSTP3 MSTP2 MSTP1 MSTP0

1. Please Check the product datasheet to determine which STBCR bits are implemented for your device.

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Power management unit (PMU)

Bit 7: standby (STBY)

Bit 7 specifies a transition to standby mode.

Bit 7: STBY

Description

Transition to sleep mode on execution of SLEEP instruction

Transition to standby mode on execution of SLEEP instruction

(Initial value)

Bit 6: peripheral module pin high impedance control (PHZ)

Bit 6 controls the state of peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module related pins go to the high-impedance state in standby mode.

For the relevant pins, see,

Section 6.5.3: Pin configuration on page 165

Bit 6: PHZ Description

Peripheral module related pins are in normal state

Peripheral module related pins go to high-impedance state

(Initial value)

Bit 5: peripheral module pin pull-up control (PPU)

Bit 5 controls the state of peripheral module related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral module related pins in the input or high-impedance state.

For the relevant pins, see

Section : Peripheral module pin pull-up control on page 168

Bit 5: PPU Description

Peripheral module related pin pull-up resistors are on

Peripheral module related pin pull-up resistors are off

(Initial value)

Bit 4: unused

This bit has no functional use.

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Bit 3: module stop 3 (MSTP3)

Bit 3 specifies stopping of the clock supply to serial communication interface channel 2 (SCIF2) among the on-chip peripheral modules. The clock supply to the

SCIF2 is stopped when the MSTP3 bit is set to 1.

Bit 3:

MSTP3

SCIF2 operates

SCIF2 clock supply is stopped

Description

(Initial value)

Bit 2: module stop 2 (MSTP2)

Bit 2 specifies stopping of the clock supply to the timer unit (TMU) among the on-chip peripheral modules. The clock supply to the TMU is stopped when the

MSTP2 bit is set to 1.

Bit 2:

MSTP2

TMU operates

TMU clock supply is stopped

Description

(Initial value)

Bit 1: module stop 1 (MSTP1)

Bit 1 specifies stopping of the clock supply to the realtime clock (RTC) among the on- chip peripheral modules. The clock supply to the RTC is stopped when the MSTP1 bit is set to 1. When the clock supply is stopped, RTC registers cannot be accessed but the counters continue to operate.

Bit 1:

MSTP1

RTC operates

RTC clock supply is stopped

Description

(Initial value)

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Power management unit (PMU)

Bit 0: module stop 0 (MSTP0)

Bit 0 specifies stopping of the clock supply to serial communication interface channel 1 (SCIF1) among the on-chip peripheral modules. The clock supply to

SCIF1 is stopped when the MSTP0 bit is set to 1.

Bit 0:

MSTP0

SCIF1 operates

SCIF1 clock supply is stopped

Description

(Initial value)

Peripheral module pin pull-up control

When bit 5 in the standby control register ( CPG.STBCR

) is set to 0, peripheral module related pins are pulled up when in the input or high-impedance state.

SCIF1 related pins

DMA related pins

TMU related pin

MD0/SCK

MD7/TXD

MD1/TXD2

MD8/RTS2

RXD CTS2

NOT_DREQ0 DACK0

NOT_DREQ1 DACK1

TCLK

Table 85: Relevant pins

MD2/RXD2

SCK2/NOT_ MRESET

DRAK0

DRAK1

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Standby control register 2

(CPG.STBCR2)

Standby control register 2 ( CPG.STBCR2

) is an 8-bit read/write register that specifies additional standby behavior. It is initialized to 0x00 by a power-on reset via the NOT_RESET pin or due to watchdog timer overflow.

Bit

Initial value

6 5

STHZ

1 0

MSTP6 MSTP5

Bit 7: unused

Bit 6: status pin high-impedance control (STHZ)

This bit selects whether the STATUS0 and STATUS1 pins are set to high-impedance when in hardware standby mode.

Bit 6: STHZ

Description

Sets STATUS0/1 Pins to high Impedance when in hardware standby mode

Drives STATUS0/1 Pins to LH when in hardware standby mode.

(Initial value)

Bits 5 to 2: reserved

Only zero should only be written to these bits; operation cannot be guaranteed if one is written. These bits are always read as zero.

1. Please check the datasheet to determine which bits are implemented for your device

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Power management unit (PMU)

Bit 1: module stop 6 (MSTP6)

Bit 1 specifies that the clock supply to the store queue (SQ) in the cache controller

(CCN) is stopped. Setting the MSTP6 bit to 1 stops the clock supply to the SQ, and the SQ functions are therefore unavailable.

Bit 1: MSTP6

Description

SQ operating

Clock supply to SQ is stopped

(Initial value)

Bit 0: module stop 5 (MSTP5)

Specifies that. of the internal modules, the clock supply to the user break controller

(UBC) is stopped.

Bit 0: MSTP5

Description

UBCoperating

Clock supply to UBC is stopped

(Initial value)

Standby control request register (CLOCKGEN.STBREQCR)

Standby control may be effected by the use of the STBREQCR (standby request) and

STBACK (standby acknowledge) registers. These registers implement the power down protocol for ST modules. Each bit of these registers corresponds to an

SuperHyway module. A module may be requested to be powered down by writing a

1 to the appropriate bit in the STBREQCR register. When that module has completed its power down sequence, and the clock to it has been stopped, the corresponding bit in the STBACKCR is set. This procedure allows precise software control of putting modules into standby.

To enable independent setting and clearing of the STBREQCR bits two auxiliary pseudo registers are provided. The STBREQCR_SET pseudo register allows

STBREQCR bits to be set independently. Writing 1 in STBREQCR_SET sets the corresponding bit in STBREQCR , a 0 leaves the bit unchanged. The

STBREQCR_CLR pseudo register allows bits to be cleared individually. Writing a 1 in STBREQCR_CLR resets the corresponding bit in STBREQCR , a 0 leaves the bit unchanged. See the product datasheet for details of these registers.

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Functionality 171

Standby control acknowledge register (CLOCKGEN.STBACKCR)

See the datasheet for details of this register.

6.6 Functionality

6.6.1 Sleep mode

Transition to sleep mode

If a SLEEP instruction is executed when the STBY bit in CPG.STBCR

is cleared to

0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained. The on-chip peripheral modules continue to operate, and the clock continues to be output from the CLKOUT pin.

In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin.

Exit from sleep mode

Sleep mode is exited by means of an interrupt ( NMI , IRL , or on-chip peripheral module) or a reset. In sleep mode, interrupts are accepted even if the BL bit in the

SR register is 1. If necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction.

Exit by interrupt

When an NMI , IRL , or on-chip peripheral module interrupt is generated, sleep mode is exited and interrupt exception handling is executed. The code corresponding to the interrupt source is set in the INTEVT register.

Exit by reset

Sleep mode is exited by means of a power-on or manual reset via the NOT_RESET pin, or a power-on or manual reset executed when the watchdog timer overflows.

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172 Functionality

6.6.2 Deep sleep mode

Deep sleep mode is similar to sleep mode except that additionally DMAC and the memory interfaces are in a low power state.

Transition to deep sleep mode

To enter deep sleep mode first power down the DMAC then power down the memory interfaces. This is accomplished using the module standby procedure described in

Section 6.7.2

. Then if a SLEEP instruction is executed when the STBY bit in

CPG.STBCR

is cleared to 0 the chip switches from the program execution state to deep sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained.

Except for the powered down modules, on-chip peripheral modules continue to operate, and the clock continues to be output from the CLKOUT pin.

In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin.

Exit from deep sleep mode

As with sleep mode, deep sleep mode is exited by means of an interrupt ( NMI , IRL , or on-chip peripheral module or a reset. Software can then power up the modules which were powered down when deep sleep was entered. See Section 6.7.4

for the procedure for powering up these modules.

6.6.3 Standby mode

Transition to standby mode

If a SLEEP instruction is executed when the STBY bit in CPG.STBCR

is set to 1, the chip switches from the program execution state to standby mode. In standby mode, the on-chip peripheral modules halt as well as the CPU. Clock output from the

CLKOUT pin is also stopped.

The CPU and cache register contents are retained. Some on-chip peripheral module registers are initialized. The state of the peripheral module registers in standby mode is shown in

Table 86

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Module

Initialized registers

Interrupt controller -

User break controller -

FMI/LMI -

CPG/CLOCKGEN

Timer unit

Realtime clock -

TMU.TSTR register*

Direct memory access controller

Serial communication interface -

Registers that retain their

All registers

All registers content

All registers except TMU.TSTR

All registers

Table 86: State of registers in standby mode

Note:

* Not initialized when the real-time clock (RTC) is in use (see Chapter 8: Timer unit

(TMU) on page 227 ).

Note: DMA transfer should be terminated before making a transition to standby mode.

Transfer results are not guaranteed if standby mode is entered during transfer.

The procedure for a transition to standby mode is shown below.

1 Set the TME bit in the WDT timer control register ( CPG.WTCSR

) to 0, and stop the WDT. Set the initial value for the up-count in the WDT timer counter

( CPG.WTCNT

), and set the clock to be used for the up-count in bits CKS2 to

CKS0 in the CPG.WTCSR

2 Set the STBY bit in the STBCR register to 1, then execute a SLEEP instruction.

3 When standby mode is entered and the chip’s internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin.

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Exit from standby mode

Standby mode is exited by means of an interrupt ( NMI , IRL , or on-chip peripheral module or a reset via the NOT_RESET pin.

Exit by interrupt

A hot start can be performed by means of the on-chip WDT. When an NMI , IRL

, or on- chip peripheral module (except interval timer)

interrupt is detected, the WDT starts counting. After the count overflows, clocks are supplied to the entire chip, standby mode is exited, and the STATUS1 and STATUS0 pins both go low. Interrupt exception handling is then executed, and the code corresponding to the interrupt source is set in the INTEVT register. In standby mode, interrupts are accepted even if the BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction.

The phase of the CLKOUT pin clock output may be unstable immediately after an interrupt is detected, until standby mode is exited.

Exit by reset

Standby mode is exited by means of a reset (power-on manual) via the NOT_RESET pin. The NOT_RESET pin should be held low until clock oscillation stabilizes. The internal clock continues to be output at the CLKOUT pin.

6.6.4 Clock pause function

In standby mode, it is possible to stop or change the frequency of the clock input from the EXTAL pin. This function is used as follows.

1 Enter standby mode following the transition procedure described above.

2 When standby mode is entered and the chip’s internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin.

3 The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the STATUS0 pin high.

1. Only when the RTC clock (32.768 kHz) is operating (see Chapter 3: Interrupt controller (INTC) on page 15 ), standby mode can be exited by means of

IRL3–IRL0 (when the IRL3–IRL0 level is higher than the SR register I3–I0 mask level).

2. Standby mode can be exited by means of an RTC interrupt.

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Module standby function 175

4 When the frequency is changed, input an NMI or IRL interrupt after the change.

When the clock is stopped, input an NMI or IRL interrupt after applying the clock.

5 After the time set in the WDT, clock supply begins inside the chip, the STATUS1 and STATUS0 pins both go low, and operation is resumed from interrupt exception handling.

6.7.1 Transition to module standby function

(CPG modules)

Setting the MSTP4 to MSTP0 bits in the standby control register to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced.

In the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules.

MSTP3

MSTP2

MSTP1

MSTP0

Bit

Description

SCIF2 operates

Clock supplied to SCIF2 is stopped

TMU operates

Clock supplied to TMU is stopped, and register is initialized*

RTC operates

Clock supplied to RTC is stopped*

SCIF1 operates

Clock supplied to SCIF1 is stopped

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Note: 1. The register initialized is the same as in standby mode, but initialization is not performed if the RTC clock is not in use (see

Chapter 8: Timer unit (TMU) on page 227

2. The counter operates when the START bit in RCR2

is 1 (see Chapter 7: Real-time clock (RTC) on page 179

6.7.2 Transition to module standby function

(CLOCKGEN modules)

The modules controlled by the CLOCKGEN register bank use a different method for entering and exiting the power down state from those controlled by the CPG register bank. The CLOCKGEN controlled modules employ a software handshake mechanism which allows software to control the order in which the clock used by each module is started and stopped.

The FMI, LMI, DMAC and PCI modules can be stopped (that is powered down) by setting the appropriate bit of the CLOCKGEN.STBREQCR

to 1 indicating that the clock to the module has been stopped. The time delay between these events depends on the particular module being requested to stop and its state at the time of the request. Software should normally stop modules one by one, checking that a module has stopped before requesting that the next module is stopped taking care to avoid any potential deadlock condition.

6.7.3 Exit from module standby function

(CPG modules)

The module standby function is exited by setting the MSTP4 to MSTP0 bits to 0, or by a power-on reset via the NOT_RESET pin or a power-on reset caused by watchdog timer overflow.

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6.7.4 Exit from module standby function

(CLOCKGEN modules)

The FMI, LMI, DMAC and PCI modules can be started (that is powered up) by writing a 0 into the appropriate field of the CLOCKGEN.STBREQCR

. Sometime later the hardware will set the corresponding bit in the CLOCKGEN.STBACKCR

to 0 indicating that the clock to the module has been re-started. The time delay between these events depends on the particular module being requested to start and its state at the time it was stopped. Software should normally start modules one by one, checking that a module has started before requesting the next module is started.

6.8 STATUS pin change timing

The STATUS1 and STATUS0 pin change timing is shown below.

The meaning of the STATUS pin settings is as follows:

Pin setting Meaning

Reset

Sleep

Standby

Normal

STATUS1 pin

High

Low

Table 87: STATUS pin settings

STATUS0 pin

High

Low

High

Low

The meaning of the clock units is as follows:

• Bcyc: Bus clock cycle,

• Pcyc: Peripheral clock cycle.

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STATUS pin change timing

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Real-time clock (RTC)

7.1 Overview

The system includes an on-chip real-time clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC.

7.1.1 Features

The RTC has the following features:

• clock and calendar functions (BCD display), counts:

seconds,

minutes,

hours,

day of the week,

days,

months,

years,

• 1 to 64 Hz timer (binary display),

the 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider,

• start and stop functions,

• 30 second adjustment function,

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Overview

• alarm interrupts,

comparison with second, minute, hour, day-of-week, day, or month can be selected as the alarm interrupt condition,

• periodic interrupts,

an interrupt period of 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds can be selected,

• carry interrupt,

carry interrupt function indicating a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read,

• automatic leap year adjustment.

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7.1.2 Block diagram

Figure 21 shows a block diagram of the RTC.

RTCCLK

16.384 kHz

Prescaler

128 Hz

32.768 kHz

RTC crystal oscillator

ATI

PRI

CUI

RESET, STBY, etc

RTC operation control unit

RCR1

RCR2

Counter unit

R64CNT

Interrupt control unit

181

RSECCNT RMINCNT RHRCNT RDAYCNT RWKCNT RMONCNT RYRCNT

RSECAR RMINAR RHRAR RDAYAR

To registers

RWKAR RMONAR

Bus interface

Internal peripheral module bus

Figure 21: Block diagram of RTC

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7.1.3 Pin configuration

Table 88 shows the

RTC pins.

Pin name

Abbreviatio n

I/O Function

RTC oscillator crystal pin EXTAL2

RTC oscillator crystal pin XTAL2

Clock input/clock output TCLK

Input

Output

I/O

Connects crystal to RTC oscillator

External clock input pin

Input capture control input pin

RTC output pin (shared with TMU)

RTC oscillator power supply pin* Dedicated RTC power supply

VCC RTC

Dedicated RTC GND pin VSS (RTC)

RTC oscillator GND pin

Table 88: RTC pins

A. Power must be supplied to the RTC power supply pins even when the RTC is not used. When the RTC is used, power should be supplied to all power supply pins including these pins. In standby mode, also, power should be supplied to all power supply pins including these pins.

7.1.4 Register configuration

Table 89 summarizes the

RTC registers.

The register addresses are offset from RTCBASE . Refer to the system address map for the value of RTCBASE .

Register name

RTC.R64CNT

RTC.RSECCNT

Description

64 Hz counter, see

Table 90 on page 185

Second counter, see

Table 91 on page 186

Table 89: RTC registers

Type

Address offset

Size

0x00 8

RW 0x04 8

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Register name

RTC.RMINCNT

RTC.RHRCNT

RTC.RWKCNT

RTC.RDAYCNT

RTC.RMONCNT

RTC.RYRCNT

RTC.RSECAR

RTC.RMINAR

RTC.RHRAR

RTC.RWKAR

RTC.RDAYAR

RTC.RMONAR

RTC.RCR1

Description

Minute counter, see

Table 92 on page 188

Hour counter, see

Table 93 on page 190

Day of week counter, see

Table 94 on page 192

Day counter, see

Table 95 on page 194

Month counter, see

Table 96 on page 196

Year counter, see

Table 97 on page 198

Second alarm register, see

Table 98 on page 200

Minute alarm register, see

Table 99 on page 202

Hour alarm register, see

Table 100 on page 204

Day of week alarm register, see

Table 101 on page 206

Day alarm register, see

Table 102 on page 208

Month alarm register, see

Table 103 on page 210

RTC control register 1, see

Table 104 on page 212

Table 89: RTC registers

183

Type

Address offset

Size

0x08 8

RW 0x0C 8

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

RW 0x2C

RW 0x30

RW 0x34

RW 0x38

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7.1.5 Register initialization

Register name

RTC.R64CNT

RTC.RSECCNT

RTC.RMINCNT

RTC.RHRCNT

RTC.RWKCNT

RTC.RDAYCNT

RTC.RMONCNT

RTC.RYRCNT

RTC.RSECAR

RTC.RMINAR

RTC.RHRAR

RTC.RWKAR

RTC.RDAYAR

RTC.RMONAR

RTC.RCR1

RTC.RCR2

RTC.R64CNT

RTC.RSECCNT

Counts

Initialized

Power-on reset Manual reset Standby mode Initial value

Counts

Held

Counts

Held

Initialized

Counts

Held

Initialized

Counts

Held

Counts

RTC.RMINCNT

Counts Counts Counts

A. The ENB bit in each register is initialized.

B. The value of the CF bit and AF bit is undefined.

C. Bits other than the RTCEN bit and START bit are initialized.

D. The value of the PEF bit is undefined.

Undefined

0x00

0x09

Undefined

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7.2.1 64 Hz counter (RTC.R64CNT)

RTC.R64CNT

is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider.

If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC CONTROL REGISTER 1 ( RTC.RCR1

) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read. In this case, the read value is not valid, and so RTC.R64CNT

must be read again after first writing 0 to the CF bit in RTC.RCR1

to clear it.

When the RESET bit or ADJ bit in RTC CONTROL REGISTER 2 ( RTC.RCR2

) is set to 1, the RTC frequency divider is initialized and RTC.R64CNT

is initialized to 0x00.

RTC.R64CNT

is not initialized by a power-on or manual reset, or in standby mode.

A carry occurs when the counter increments from 63 to 64.

Bit 7 is always read as 0 and cannot be modified.

Field r64cnt

RTC.R64CNT

0x0

Bits Size Volatile

[0:6]

Operation

Read

Write

Hard reset

Operation

Read

Write

Hard reset

Synopsis

Yes 64 Hz Counter

Holds a counter value which increments at 64Hz

Returns current value

Ignored

Undefined

Yes

Reserved

Ignored

Table 90: RTC.R64CNT

Type

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7.2.2 Second counter (RTC.RSECCNT)

RTC.RSECCNT

is an 8-bit read/write register used as a counter for setting and counting the BCD-coded second value in the RTC. It counts on the carry generated once per second by the 64 Hz counter.

The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RTC.RCR2

, or by using the carry flag.

RTC.RSECCNT

is not initialized by a power-on or manual reset, or in standby mode.

Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0.

Field units tens

RTC.RSECCNT

0x4

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

[4:6]

Operation

Read

Write

Hard reset

Synopsis

Yes Second counter

Counts up 1 second units

Reads current value

Updates current value

Undefined

Yes 10 second counter

Counts up 10 seconds

Reads current value

Updates current value

Undefined

Table 91: RTC.RSECCNT

Type

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Register descriptions

Field

RTC.RSECCNT

0x4

Bits Size Volatile

Operation

Read

Write

Hard reset

Yes

Reserved

Ignored

Reserved

Synopsis

Table 91: RTC.RSECCNT

187

Type

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7.2.3 Minute counter (RTC.RMINCNT)

RTC.RMINCNT

is an 8-bit read/write register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter.

The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RTC.RCR2

, or by using the carry flag.

RTC.RMINCNT

is not initialized by a power-on or manual reset, or in standby mode.

Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0.

Field units tens

RTC.RMINCNT

0x8

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

[4:6]

Operation

Read

Write

Hard reset

Synopsis

Yes Minute counter

Counts up 1 minute units

Reads current value

Updates current value

Undefined

Yes 10 minute counter

Counts up 10 Minutes

Reads current value

Updates current value

Undefined

Table 92: RTC.RMINCNT

Type

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Register descriptions

Field

RTC.RMINCNT

0x8

Bits Size Volatile

Operation

Read

Write

Hard reset

Yes

Reserved

Ignored

Reserved

Synopsis

Table 92: RTC.RMINCNT

189

Type

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7.2.4 Hour counter (RTC.RHRCNT)

RTC.RHRCNT

is an 8-bit read/write register used as a counter for setting and counting the BCD-coded hour value in the RTC. It counts on the carry generated once per hour by the minute counter.

The setting range is decimal 00 to 23. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RTC.RCR2

, or by using the carry flag.

RTC.RHRCNT

is not initialized by a power-on or manual reset, or in standby mode.

Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0.

Field units tens

RTC.RHRCNT

0x0C

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

[4:5]

Operation

Read

Write

Hard reset

Synopsis

Yes Hour counter

Counts up 1 hour units

Reads current value

Updates current value

Undefined

Yes 10 hour counter

Counts up 10 hours

Reads current value

Updates current value

Undefined

Table 93: RTC.RHRCNT

Type

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Register descriptions

Field

RTC.RHRCNT

0x0C

Bits Size Volatile

[6:7]

Operation

Read

Write

Hard reset

Yes

Reserved

Ignored

Reserved

Table 93: RTC.RHRCNT

Synopsis Type

191

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7.2.5 Day-of-week counter (RTC.RWKCNT)

RTC.RWKCNT

is an 8-bit read/write register used as a counter for setting and counting the BCD-coded day-of- week value in the RTC. It counts on the carry generated once per day by the hour counter.

The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the

START bit in RTC.RCR2

, or by using the carry flag.

RTC.RWKCNT

is not initialized by a power-on or manual reset, or in standby mode.

Bits 7 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0.

Field units

RTC.RWKCNT

0x10

Bits

Write

Hard reset

Size Volatile

[0:2]

Operation

Read

Yes Day of week

Indicates day of week

Synopsis

Returns day of week code:

0: Sunday

1: Monday

2: Tuesday

3: Wednesday

4: Thursday

5: Friday

6: Saturday

Updates current value

Undefined

Table 94: RTC.RWKCNT

Type

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Register descriptions

Field

RTC.RWKCNT

0x10

Bits Size Volatile

[3:7]

Operation

Read

Write

Hard reset

Yes

Reserved

Ignored

Reserved

Synopsis

Table 94: RTC.RWKCNT

Type

193

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7.2.6 Day counter (RTC.RDAYCNT)

RTC.RDAYCNT

is an 8-bit read/write register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter.

The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RTC.RCR2

, or by using the carry flag. RTC.RDAYCNT

is not initialized by a power-on or manual reset, or in standby mode.

The setting range for RTC.RDAYCNT

depends on the month and whether the year is a leap year, so care is required when making the setting. Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0.

Field units tens

RTC.RDAYCNT

0x14

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

[4:5] 2

Operation

Read

Write

Hard reset

Synopsis

Yes Day counter

Counts up 1 day units

Reads current value

Updates current value

Undefined

Yes 10 day counter

Counts up 10 days

Reads current value

Updates current value

Undefined

Table 95: RTC.RDAYCNT

Type

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Register descriptions

Field

RTC.RDAYCNT

0x14

Bits Size Volatile

[6:7]

Operation

Read

Write

Hard reset

Yes

Reserved

Ignored

Reserved

Synopsis

Table 95: RTC.RDAYCNT

Type

195

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7.2.7 Month counter (RTC.RMONCNT)

RTC.RMONCNT

is an 8-bit read/write register used as a counter for setting and counting the BCD-coded month value in the RTC. It counts on the carry generated once per month by the day counter.

The setting range is decimal 01 to 12. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RTC.RCR2

, or by using the carry flag.

RTC.RMONCNT

is not initialized by a power-on or manual reset, or in standby mode.

Bits 7 to 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0

Field units tens

RTC.RMONCNT

0x18

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

4 1

Operation

Read

Write

Hard reset

Synopsis

Yes Month counter

Counts up 1 month units

Reads current value

Updates current value

Undefined

Yes 10 month Counter

Counts up 10 Months

Reads current value

Updates current value

Only values 0 to 9 are defined.

Undefined

Table 96: RTC.RMONCNT

Type

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Register descriptions

Field

RTC.RMONCNT

0x18

Bits Size Volatile

[5:7]

Operation

Read

Write

Hard reset

Yes

Reserved

Ignored

Reserved

Synopsis

Table 96: RTC.RMONCNT

Type

197

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7.2.8 Year counter (RTC.RYRCNT)

RTC.RYRCNT

is a 16-bit read/write register used as a counter for setting and counting the BCD-coded year value in the RTC. It counts on the carry generated once per year by the month counter.

The setting range is decimal 0000 to 9999. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RTC.RCR2

, or by using the carry flag.

RTC.RYRCNT

is not initialized by a power-on or manual reset, or in standby mode.

units

Field tens

RTC.RYRCNT

0x1C

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

[4:7] 4

Operation

Read

Write

Hard reset

Synopsis

Yes Year Counter

Counts up 1 year units

Reads current value

Updates current value

Undefined

Yes 10 year Counter

Counts up 10 years

Reads current value

Updates current value

Only values 0 to 9 are defined.

Undefined

Table 97: RTC.RYRCNT

Type

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Register descriptions

Field hundreds thousands

RTC.RYRCNT

0x1C

Bits

[8:11]

Operation

Read

Write

Hard reset

[12:15]

Operation

Read

Write

Hard reset

Size Volatile

Yes

Synopsis

100 year Counter

Counts up 100 years

Reads current value

Updates current value

Only values 0 to 9 are defined.

Undefined

Yes 1000 year Counter

Counts up 1000 years

Reads current value

Updates current value

Undefined

Table 97: RTC.RYRCNT

Type

199

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7.2.9 Second alarm register (RTC.RSECAR)

RTC.RSECAR

is an 8-bit read/write register used as an alarm register for the RTC’s

BCD-coded second value counter, RTC.RSECCNT

. When the ENB bit is set to 1, the

RTC.RSECAR

value is compared with the RTC.RSECCNT

value. Comparison between the counter and the alarm register is performed for those registers among

RTC.RSECAR

, RTC.RMINAR

, RTC.RHRAR

, RTC.RWKAR

, RTC.RDAYAR

, and

RTC.RMONAR

in which the ENB bit is set to 1, and the RTC.RCR1

alarm flag is set when the respective values all match.

The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set.

The ENB bit in RTC.RSECAR

is initialized to 0 by a power-on reset. The other fields in RTC.RSECAR

are not initialized by a power-on or manual reset, or in standby mode.

Field units tens

RTC.RSECAR

0x20

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

[4:6]

Operation

Read

Write

Hard reset

Synopsis

No Second value

1 second value for comparison

Reads current value

Updates current value

Undefined

No 10 Second Value

10 second value for comparison

Reads current value

Only values

Undefined

Table 98: RTC.RSECAR

Type

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Register descriptions 201

Field enb

RTC.RSECAR

0x20

Bits Size Volatile

Operation

Read

Write

Hard reset

Synopsis

Comparison enable bit

Type

Sets this bit to 1 to enable second comparison for alarm

Returns current value

Updates current value

Table 98: RTC.RSECAR

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7.2.10 Minute alarm register (RTC.RMINAR)

RTC.RMINAR

is an 8-bit read/write register used as an alarm register for the RTC’s

BCD-coded minute value counter, RTC.RMINCNT

. When the ENB bit is set to 1, the

RTC.RMINAR

value is compared with the RTC.RMINCNT

value. Comparison between the counter and the alarm register is performed for those registers among

RTC.RSECAR

, RTC.RMINAR

, RTC.RHRAR

, RTC.RWKAR

, RTC.RDAYAR

, and

RTC.RMONAR

in which the ENB bit is set to 1, and the RTC.RCR1

alarm flag is set when the respective values all match.

The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set.

The ENB bit in RTC.RMINAR

is initialized by a power-on reset. The other fields in

RTC.RMINAR

are not initialized by a power-on or manual reset, or in standby mode.

Field units tens

RTC.RMINAR

0x24

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

[4:6]

Operation

Read

Write

Hard reset

Synopsis

No Minute value

1 minute comparison value

Reads current value

Updates current value

Undefined

No 10 minute value

1 minute comparison value

Reads current value

Updates current value

Undefined

Table 99: RTC.RMINAR

Type

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Register descriptions

Field

ENB

RTC.RMINAR

0x24

Bits Size Volatile

Operation

Read

Write

Hard reset

Synopsis

Comparison enable bit

Enables comparison for alarm

Returns current value

1: Enable minute comparison

Table 99: RTC.RMINAR

203

Type

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204 Register descriptions

7.2.11 Hour alarm register (RTC.RHRAR)

RTC.RHRAR

is an 8-bit read/write register used as an alarm register for the RTC’s

BCD-coded hour value counter, RTC.RHRCNT

. When the ENB bit is set to 1, the

RTC.RHRAR

value is compared with the RTC.RHRCNT

value. Comparison between the counter and the alarm register is performed for those registers among

RTC.RSECAR

, RTC.RMINAR

, RTC.RHRAR

, RTC.RWKAR

, RTC.RDAYAR

, and

RTC.RMONAR

in which the ENB bit is set to 1, and the RTC.RCR1

alarm flag is set when the respective values all match.

The setting range is decimal 00 to 23 + ENB bit. The RTC will not operate normally if any other value is set.

The ENB bit in RTC.RHRAR

is initialized by a power-on reset. The other fields in

RTC.RHRAR

are not initialized by a power-on or manual reset, or in standby mode.

Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0.

Field units tens

RTC.RHRAR

0x28

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

[4:5] 2

Operation

Read

Write

Hard reset

No Hour Value

1 Hour comparison value

Reads current value

Updates current value

Undefined

No 10 Hour Value

10 Hour comparison value

Reads current value

Updates current value

Undefined

Synopsis

Table 100: RTC.RHRAR

Type

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Register descriptions

Field enb

RTC.RHRAR

0x28

Bits

Operation

Read

Write

Hard reset

7 1

Operation

Read

Write

Hard reset

Size Volatile Synopsis

Yes

Reserved

Ignored

No Comparison enable bit

Enables hour comparison for alarm

Returns current value

1: Enables hour comparison

Table 100: RTC.RHRAR

Type

205

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206 Register descriptions

7.2.12 Day-of-week alarm register (RTC.RWKAR)

RTC.RWKAR

is an 8-bit read/write register used as an alarm register for the RTC’s

BCD-coded day-of-week value counter, RTC.RWKCNT

. When the ENB bit is set to 1, the RTC.RWKAR

value is compared with the RTC.RWKCNT

value. Comparison between the counter and the alarm register is performed for those registers among

RTC.RSECAR

, RTC.RMINAR

, RTC.RHRAR

, RTC.RWKAR

, RTC.RDAYAR

, and

RTC.RMONAR

in which the ENB bit is set to 1, and the RTC.RCR1

alarm flag is set when the respective values all match.

The setting range is decimal 0 to 6 + ENB bit. The RTC will not operate normally if any other value is set.

The ENB bit in RTC.RWKAR

is initialized by a power-on reset. The other fields in

RTC.RWKAR

are not initialized by a power-on or manual reset, or in standby mode.

Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0.

Field units

RTC.RWKAR

0x2C

Bits

Write

Hard reset

Size Volatile

[0:2]

Operation

Read

3 No Week value

Synopsis

Day of week comparison value

Returns day of week code:

0=Sunday

1=Monday

2=Tuesday

3=Wednesday

4=Thursday

5=Friday

6=Saturday

Updates current value

Undefined

Table 101: RTC.RWKAR

Type

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Register descriptions

Field enb

RTC.RWKAR

0x2C

Bits

[3:6]

Operation

Read

Write

Hard reset

7 1

Operation

Read

Write

Hard reset

Size Volatile Synopsis

Reserved

Ignored

No Comparison enable bit

Enables day of week comparison for alarm

Returns current value

1: Enable day of week comparison

Table 101: RTC.RWKAR

207

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208 Register descriptions

7.2.13 Day alarm register (RTC.RDAYAR)

RTC.RDAYAR

is an 8-bit read/write register used as an alarm register for the RTC’s

BCD-coded day value counter, RTC.RDAYCNT

. When the ENB bit is set to 1, the

RTC.RDAYAR

value is compared with the RTC.RDAYCNT

value. Comparison between the counter and the alarm register is performed for those registers among

RTC.RSECAR

, RTC.RMINAR

, RTC.RHRAR

, RTC.RWKAR

, RTC.RDAYAR

, and

RTC.RMONAR

in which the ENB bit is set to 1, and the RTC.RCR1

alarm flag is set when the respective values all match.

The setting range is decimal 01 to 31 + ENB bit. The RTC will not operate normally if any other value is set. The setting range for RTC.RDAYAR

depends on the month and whether the year is a leap year, so care is required when making the setting.

The ENB bit in RTC.RDAYAR

is initialized by a power-on reset. The other fields in

RTC.RDAYAR

are not initialized by a power-on or manual reset, or in standby mode.

Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0

Field units tens

RTC.RDAYAR

0x30

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

[4:5]

Operation

Read

Write

Hard reset

Synopsis

No Day alarm value

1 day comparison value

Reads current value

Updates current value

Undefined

No 10 day value

10 day comparison value

Reads current value

Updates current value

Undefined

Table 102: RTC.RDAYAR

Type

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Register descriptions

Field enb

RTC.RDAYAR

0x30

Bits

Operation

Read

Write

Hard reset

7 1

Operation

Read

Write

Hard reset

Size Volatile Synopsis

Yes

Reserved

Ignored

No Comparison enable bit

Enables day comparison for alarm

Returns current value

1: Enable day comparison

Table 102: RTC.RDAYAR

Type

209

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210 Register descriptions

7.2.14 Month alarm register (RTC.RMONAR)

RTC.RMONAR

is an 8-bit read/write register used as an alarm register for the RTC’s

BCD-coded month value counter, RTC.RMONCNT

. When the ENB bit is set to 1, the

RTC.RMONAR

value is compared with the RTC.RMONCNT

value. Comparison between the counter and the alarm register is performed for those registers among

RTC.RSECAR

, RTC.RMINAR

, RTC.RHRAR

, RTC.RWKAR

, RTC.RDAYAR

, and

RTC.RMONAR

in which the ENB bit is set to 1, and the RTC.RCR1

alarm flag is set when the respective values all match.

The setting range is decimal 01 to 12 + ENB bit. The RTC will not operate normally if any other value is set.

The ENB bit in RTC.RMONAR

is initialized by a power-on reset. The other fields in

RTC.RMONAR

are not initialized by a power-on or manual reset, or in standby mode.

Bits 6 and 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0

Field units tens

RTC.RMONAR

0x34

Bits Size Volatile

[0:3]

Operation

Read

Write

Hard reset

Operation

Read

Write

Hard reset

Synopsis

No Month alarm value

1 month comparison value

Reads current value

Updates current value

Undefined

No 10 Month Alarm Value

10 month comparison value

Reads current value

Updates current value

Undefined

Table 103: RTC.RMONAR

Type

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Register descriptions

Field

ENB

RTC.RMONAR

0x34

Bits

[5:6]

Operation

Read

Write

Hard reset

7 1

Operation

Read

Write

Hard reset

Size Volatile Synopsis

Yes

Reserved

Ignored

No Comparison enable bit

Enables month comparison for alarm

Returns current value

1: Enable month comparison

Table 103: RTC.RMONAR

Type

211

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212 Register descriptions

7.2.15 RTC control register 1 (RTC.RCR1)

RTC.RCR1

is an 8-bit read/write register containing a carry flag and alarm flag, plus flags to enable or disable interrupts for these flags.

The CIE and AIE bits are initialized to 0 by a power-on or manual reset; the value of bits other than CIE and AIE is undefined. In standby mode RTC.RCR1

is not initialized, and retains its current value.

Field

RTC.RCR1

0x38

Bits

Operation

Read

Write

Hard reset

[1:2]

Operation

Read

Write

Hard reset

Size Volatile

Yes

Synopsis Type

0: Alarm registers and counter values do not match

1: Alarm registers in which the ENB bit is set to 1 and counter values match

0: Clear the alarm condition

1: Ignored

Reserved

Reserved RO

Ignored

Alarm flag RW

Sets to 1 when the alarm time set in those registers among

RTC.RSECAR, RTC.RMINAR, RTC.RHRAR, RTC.RWKAR,

RTC.RDAYAR, and RTC.RMONAR in which the ENB bit is set to 1 matches the respective counter values

Table 104: RTC.RCR1

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Field cie

RTC.RCR1

0x38

Bits Size Volatile

Operation

Read

Write

Hard reset

Operation

Read

Write

Hard reset

[5:6]

Operation

Read

Write

Hard reset

Yes

Synopsis

Alarm interrupt enable flag

Type

Enables or disables interrupt generation when the alarm flag

(AF) is set to 1

Returns current value

0: Alarm interrupt is not generated when AF flag is set to 1

(initial value)

1: Alarm interrupt is generated when AF flag is set to 1

Yes Carry interrupt enable flag RW

Enables or disables interrupt generation when the carry flag

(CF) is set to 1

Returns current value

0: Alarm interrupt is not generated when AF flag is set to 1

(initial value)

1: Carry interrupt is generated when CF flag is set to 1

Reserved RO

Reserved

Undefined

Ignored

Undefined

Table 104: RTC.RCR1

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Field

RTC.RCR1

0x38

Bits Size Volatile

Operation

Read

Write

Hard reset

Yes Carry flag

Synopsis Type

Sets flag to 1 on generation of a second counter carry, or a

64 Hz counter carry when the 64 Hz counter is read

The count register value read at this time is not guaranteed, and so the count register must be read again.

0: No second counter carry, or 64 Hz counter carry when 64

Hz counter is read

1: Second counter carry, or 64 Hz counter carry when 64 Hz counter is read

0: Clear the carry flag

1= Generate a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read

Undefined

Table 104: RTC.RCR1

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Register descriptions 215

7.2.16 RTC control register 2 (RTC.RCR2)

RTC.RCR2

is an 8-bit read/write register used for periodic interrupt control,

30-second adjustment, and frequency divider RESET and RTC count control.

RTC.RCR2

is basically initialized to 0x09 by a power-on reset, except that the value of the PEF bit is undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value of the PEF bit is undefined. In standby mode

RTC.RCR2

is not initialized, and retains its current value.

Field start reset

RTC.RCR2

0x3C

Bits

Operation

Read

Write

Hard reset

Operation

Read

Write

Hard reset

Size Volatile

Yes Start bit

Returns current value

Synopsis

Stops and restarts counter (clock) operation

Type

Yes Reset bit RW

Initializes frequency divider circuits by writing 1 to this bit

When 1 is written to the RESET bit, the frequency divider circuits (RTC prescaler and RTC.R64CNT) are reset and the

RESET bit is automatically cleared to 0 (that is it does not need to be written with 0).

Returns current value

0: Normal clock operation (initial value)

1: Frequency divider circuits are reset

0: Second, minute, hour, day, day-of-week, month, and year counters are stopped

1: Second, minute, hour, day, day-of-week, month, and year counters operate normally (initial value)

Table 105: RTC.RCR2

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Field rtcen

RTC.RCR2

0x3C

Bits

Operation

Read

Write

Hard reset

Operation

Read

Write

Hard reset

Size Volatile

Yes

Synopsis

Second adjustment

Type

Used for 30-second adjustment

When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. The frequency divider circuits (RTC prescaler and RTC.R64CNT) are also reset at this time. This bit always returns 0 if read.

Returns current value

0: Normal clock operation (initial value)

1: 30-second adjustment performed

Yes Oscillator enable

Controls the operation of the RTC’s crystal oscillator

Returns current value

0: NRTC crystal oscillator is halted

1: RTC crystal oscillator is operated (initial value)

Table 105: RTC.RCR2

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Register descriptions 217

Field pes0,

PES1, pes2

RTC.RCR2

0x3C

Bits Size Volatile

[4:6]

Operation

Read

Write

Yes

Specifies the period for periodic interrupts

Returns current value

Bit 6:

PES2

Bit 5:

PES1

Periodic interrupt enable

Bit 4:

PES0

Synopsis

Description

Type

No periodic interrupt generation (initial value)

Periodic interrupt generated at 1/256-second intervals

Periodic interrupt generated at 1/64-second intervals

Periodic interrupt generated at 1/16-second intervals

Periodic interrupt generated at 1/4-second intervals

Periodic interrupt generated at 1/2-second intervals

Periodic interrupt generated at 1-second intervals

Periodic interrupt generated at 2-second intervals

Hard reset 0

Table 105: RTC.RCR2

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Register descriptions

RTC.RCR2

0x3C pef

Field Bits

Read

Write

Size Volatile

Operation

Hard reset

Yes

Synopsis

Periodic interrupt flag

Type

Allows interrupt generation at the interval specified by bits

PES2 to PES0

Returns current value

0: Interrupt is not generated

1: Interrupt is generated

Undefined

Table 105: RTC.RCR2

A. The 64 Hz counter continues to operate unless stopped by means of the

RTCEN bit.

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Operation

7.3 Operation

Examples of the use of the RTC are shown below.

7.3.1 Time setting procedures

Figure 22 shows examples of the time setting procedures.

Stop clock

Reset frequency divider

Set RCR2.RESET to 1

Clear RCR2.START to 0

Set second/minute/hour/day/ day-of-week/month/year

In any order

Start clock operation

Set RCR2.START to 1

(a) Setting time after stopping clock

Yes

Clear carry flag

Write to counter register

Clear RCR1.CF to 0

(Write 1 to RCR1.AF so that alarm flag is not cleared)

Set RYRCNT first and RSECCNT last

Carry flag = 1?

Read RCR1 register and check CF bit

(b) Setting time while clock is running

Figure 22: Examples of time-setting procedures

219

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Operation

The procedure for setting the time after stopping the clock is shown in the first flow diagram in

Figure 22

. The programming for this method is simple, and it is useful for setting all the counters, from second to year.

The procedure for setting the time while the clock is running is shown in the second flow diagram in

Figure 22 . This method is useful for modifying only certain counter

values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data. The carry flag should therefore be used to check the write status. If the carry flag ( RTC.RCR1.CF

) is set to 1, the write must be repeated.

The interrupt function can also be used to determine the carry flag status.

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Operation

7.3.2 Time reading procedures

Figure 23 shows examples of the time-reading procedures.

Yes

Disable carry interrupts

Clear carry flag

Read counter register

Clear RCR1.CIE to 0

Clear RCR1.CF to 0

(Write 1 to RCR1.AF so that alarm flag is not cleared)

Carry flag = 1?

Read RCR1 register and check CF bit

(a) Reading time without using interrupts

221

Clear carry flag

Enable carry interrupts

Clear carry flag

Read counter register

Set RCR1.CIE to 1

Clear RCR1.CF to 0

(Write 1 to RCR1.AF so that alarm flag is not cleared)

Yes

Interrupt generated?

Disable carry interrupts Clear RCR1.CIE to 0

(b) Reading time using interrupts

Figure 23: Examples of time-reading procedures

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222 Operation

If a carry occurs while the time is being read, the correct time will not be obtained and the read must be repeated. The procedure for reading the time without using interrupts is shown in the first flow diagram, and the procedure using carry interrupts in the second flow diagram in

Figure 23

. The method without using interrupts is normally used to keep the program simple.

7.3.3 Alarm function

The use of the alarm function is illustrated in

Figure 24

Clock running

Disable alarm interrupts

Set alarm time

Clear RCR1.AIE to prevent erroneous interrupts

Clear alarm flag

Be sure to reset the flag as it may have been set during alarm time setting

Set RCR1.AIE to 1 Enable alarm interrupts

Monitor alarm time

(Wait for interrupt or check alarm flag)

Figure 24: Example of use of alarm function

An alarm can be generated by the second, minute, hour, day of the week, day or month value, or a combination of these. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set the alarm time in the lower bits.

Write 0 to the ENB bit in registers not involved in the alarm setting.

When the counter and the alarm time match, RTC.RCR1.AF is set to 1. Alarm detection can be confirmed by reading this bit, but normally an interrupt is used. If

1 has been written to RTC.RCR1.AIE, an alarm interrupt is generated in the event of alarm, enabling the alarm to be detected.

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Interrupts 223

The alarm flag remains set while the counter and alarm time match. If the alarm flag is cleared by writing 0 during this period, it will therefore be set again immediately afterward. This needs to be taken into consideration when writing the program.

7.4 Interrupts

There are 3 kinds of RTC interrupt:

• alarm interrupts,

• periodic interrupts,

• carry interrupts.

An alarm interrupt request (ATI) is generated when the alarm flag (AF) in

RTC.RCR1

is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1.

A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2 to PES0) in RTC.RCR2

are set to a value other than 000 and the periodic interrupt flag (PEF) is set to 1.

A carry interrupt request (CUI) is generated when the carry flag (CF) in RTC.RCR1

is set to 1 while the carry interrupt enable bit (CIE) is also set to 1.

7.5.1 Register initialization

After powering on and making the RTC.RCR1

to 1) and make initial settings for all the other registers.

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224 Usage notes

7.5.2 Crystal oscillator circuit

Crystal oscillator circuit constants (recommended values) are shown in

Table 106 , and the RTC crystal oscillator circuit in Figure 25

f osc

C in

C out

32.768 kHz 10-22 pF 10-22 pF

Table 106: Crystal oscillator circuit constants (recommended values)

VDD-RTC

RTC

ST40RA

EXTAL2

XTAL2

IN C

OUT

1.8 V

Figure 25: Example of crystal oscillator circuit connection

Note: 1 Select either the C

or C

OUT

side for the frequency adjustment variable capacitor according to requirements such as the adjustment range and degree of stability. The typical value of both C

and C

OUT

is 15 pF.

2 Built-in resistance value R

(typical value) = 10 M Ω, R

(typical value) = 400 k Ω

3 C

and C

OUT

values include floating capacitance due to the wiring. Take care when using a solid-earth board.

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Usage notes 225

4 The crystal oscillation stabilization time depends on the mounted circuit constants and floating capacitance and should be decided after consultation with the crystal resonator manufacturer.

5 Place the crystal resonator and load capacitors C

and C

OUT

as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins).

6 Ensure that the crystal resonator connection pin (EXTAL2 and XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines.

7 The typical value of C

RTC

is 100 nF.

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Usage notes

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Timer unit

(TMU)

8.1 Overview

This chapter describes the on-chip 32-bit timer unit (TMU) module comprising three

32-bit timer channels (channels 0 to 2).

8.1.1 Features

The TMU has the following features:

• auto-reload type 32-bit down-counter provided for each channel,

• input capture function provided in channel 2,

• selection of rising edge or falling edge as external clock input edge when external clock is selected or input capture function is used,

• 32-bit timer constant register for auto-reload use, read/write at any time, and

32-bit down-counter provided for each channel,

• selection of 7 counter input clocks for each channel,

external clock (TCLK),

on-chip RTC output clock,

5 internal clocks (P/4, P/16, P/64, P/256, P/1024) (P is the peripheral module clock),

• each channel can also operate in module standby mode when the on-chip RTC output clock is selected as the counter input clock, that is, timer operation continues even when the clock has been stopped for the TMU,

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Overview

timer count operations using an external or internal clock are only possible when a clock is supplied to the timer unit,

• synchronous read operation,

• 2 interrupt sources,

1 underflow source (channels 0 to 2),

1 input capture source (channel 2),

• DMAC data transfer request capability,

on channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is generated.

1. As the timer counters (TCNT) are serially modified 32-bit registers and the internal peripheral module bus is 16 bits wide, there is a time difference when reading the upper 16 bits and lower 16 bits of TCNT. To prevent counter read value drift due to this time difference, a synchronization circuit is provided that allows simultaneous reading of all 32 bits of the TCNT data.

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Overview

8.1.2 Block diagram

Figure 26 shows a block diagram of the TMU.

RESET, STBY, etc.

TUNI0 PCLK/4, 16, 64* TUNI1 TCLK RTCCLK TUNI2 TICPI2

TMU control unit

Prescaler

To each channel

TCLK control unit

TOCR

TSTR

Ch 0

Counter unit

Interrupt control unit

Ch 1

Counter unit

Interrupt control unit

Ch 2

Counter unit

Interrupt control unit

229

TCR0 TCOR0 TCNT0 TCR1 TCOR1 TCNT1 TCR2 TCOR2 TCNT2 TCPR2

Bus interface

Internal peripheral module bus

Note: * Signals with 1/4, 1/16, and 1/64 the P φ frequency, supplied to the on-chip peripheral functions.

Figure 26: Block diagram of TMU

8.1.3 Pin configuration

Table 107 shows the TMU pins.

Pin Name

Clock input/clock output

Abbreviation

TCLK

I/O

I/O

Function

External clock input pin/input capture control input pin

RTC output pin (shared with RTC)

Table 107: TMU pins

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8.1.4 Register configuration

Table 108 summarizes the TMU registers. All addresses are given as offsets to the

TMU base address. Refer to the system address map for the value of TMUBASE.

Channel

Register name

Description

Common

TMU.TOCR

TMU.TSTR

Timer output control register,

see Table 110 on page 232

Timer start register,

see Table 111 on page 233

TMU.TCOR0

Timer constant register 0,

see Table 112 on page 235

TMU.TCNT0

Timer counter 0,

see Table 113 on page 236

TMU.TCR0

Timer control register 0,

see Table 114 on page 237

TMU.TCOR1

Timer constant register 1,

see Table 112 on page 235

TMU.TCNT1

Timer counter 1,

see Table 113 on page 236

TMU.TCR1

Timer control register 1,

see Table 114 on page 237

TMU.TCOR2

Timer constant register 2,

see Table 112 on page 235

TMU.TCNT2

Timer counter 2,

see Table 113 on page 236

TMU.TCR2

Timer control register 2,

see Table 115 on page 239

TMU.TCPR2

Input capture register,

see Table 116 on page 243

Table 108: TMU registers

Type

Address offset

Access size

0x00 8

RW 0x04

RW 0x08

RW 0x0C

RW 0x10

RW 0x14

RW 0x18

RW 0x1C

RW 0x20

RW 0x24

RW 0x28

RO 0x2C

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Overview

Register name

TMU.TOCR

TMU.TSTR

TMU.TCOR0

TMU.TCNT0

TMU.TCR0

TMU.TCOR1

TMU.TCNT1

TMU.TCR1

TMU.TCOR2

TMU.TCNT2

TMU.TCR2

TMU.TCPR2

Power-on reset

Initialized

Held

Manual reset Standby mode Initial value

Initialized

Held

Initialized

Held

0x00

0xFFFFFFFF

0x0000

0xFFFFFFFF

0x0000

0xFFFFFFFF

0x0000

Undefined

Table 109: Initialization of TMU registers

A. Not initialized in standby mode when the input clock is the on-chip RTC output clock

B. Counts in module standby mode when the input clock is the on-chip RTC output clock.

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Register descriptions

8.2.1 Timer output control register (TMU.TOCR)

TMU.TOCR

is an 8-bit read/write register that specifies whether external pin TCLK is used as the external clock or input capture control input pin, or as the on-chip

RTC output clock output pin.

TMU.TOCR

is initialized to 0x00 by a power-on or manual reset, but is not initialized in standby mode.

Field

TCOE

TMU.TOCR

0x00

Bits

[0]

Operation

Read

Write

Hard reset

[1:7]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis

Timer output control

Type

Specifies whether timer clock pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin

Returns current value

0: Timer clock pin (TCLK) is used as external clock input or input capture control input pin

1: Timer clock pin (TCLK) is used as on-chip RTC output clock output pin

Yes

Reserved

Invalid

Table 110: TMU.TOCR

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Register descriptions 233

8.2.2 Timer start register (TMU.TSTR)

TMU.TSTR

is an 8-bit read/write register that specifies whether the channel 0 to 2 timer counters (TCNT) are operated or stopped.

TMU.TSTR

is initialized to 0x00 by a power-on or manual reset. In module standby mode, TMU.TSTR

is not initialized when the input clock selected by each channel is the on-chip RTC output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK) or internal clock (Pø)

Field

STR0

STR1

TMU.TSTR

0x04

Bits

[0]

Operation

Read

Write

Hard reset

[1]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis

Counter 0 start

Type

Specifies whether timer counter 0 (TMU.TCNT0) is operated or stopped

Returns current value

0: TMU.TCNT0 count operation is stopped

1: TMU.TCNT0 performs count operation

No Counter 1 start RW

Specifies whether timer counter 1 (TMU.TCNT1) is operated or stopped

Returns current value

0: TMU.TCNT1 count operation is stopped

1: TMU.TCNT1 performs count operation

Table 111: TMU.TSTR

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234 Register descriptions

Field

STR2

TMU.TSTR

0x04

Bits

[2]

Operation

Read

Write

Hard reset

[3:7]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis

Counter 2 start

Type

Specifies whether timer counter 2 (TMU.TCNT2) is operated or stopped

Returns current value

0: TMU.TCNT2 count operation is stopped

1: TMU.TCNT2 performs count operation

Yes

Reserved

Invalid

Table 111: TMU.TSTR

8.2.3 Timer constant registers (TMU.TCOR)

The TCOR registers are 32-bit read/write registers. There are 3 TCOR registers, 1 for each channel.

When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value.

The TCOR registers are initialized to 0xFFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode.

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Register descriptions 235

Field

TMU.TCOR[n]

(n = 0 to 2)

0x08 + (n * 0x0C)

Bits Size Volatile

[0:31]

Operation

Read

Write

Hard reset

32 No

Synopsis

Timer constant

Reloads TCNT [n] when it underflows

Returns current value

Updates current value

0xFFFF FFFF

Table 112: TMU.TCOR[n]

Type

8.2.4 Timer counters (TMU.TCNT)

The TCNT registers are 32-bit read/write registers. There are 3 TCNT registers, 1 for each channel.

Each TCNT counts down on the input clock selected by TPSC2 to TPSC0 in the timer control register ( TCR ).

When a TCNT counter underflows while counting down, the underflow flag (UNF) is set in the corresponding timer control register ( TCR ). At the same time, the timer constant register ( TCOR ) value is set in TCNT , and the count-down operation continues from the set value.

As the TCNT registers are serially modified 32-bit registers and the internal peripheral module bus is 16 bits wide, there is a time difference when reading the upper 16 bits and lower 16 bits of TCNT . To prevent counter read value drift due to this time difference, a synchronization circuit is provided. When the upper 16 bits are read, the lower 16 bits are simultaneously stored in a buffer register. After the upper 16 bits are read, the lower 16 bits are read from the buffer register.

The TCNT registers are initialized to 0xFFFF FFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode.

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236 Register descriptions

Field

TMU.TCNT[n]

(n = 0 to 2)

0x0C + (n * 0x0C)

Bits

Read

Write

Hard reset

Size Volatile

[0:31]

Operation

32 Yes Timer counter

Synopsis

Counts on the clock selected by TMU.TCR

32-bit down counter

Returns current value

Updates current value

0xFFFFFFFF

Table 113: TMU.TCNT[n]

Type

When the input clock is the on-chip RTC output clock (RTCCLK), TCNT counts even in module standby mode (that is, when the clock for the TMU is stopped). When the input clock is the external clock (TCLK) or internal clock (P), TCNT contents are retained in standby mode.

8.2.5 Timer control registers (TMU.TCR)

The TCR registers are 16-bit read/write registers. There are 3 TCR registers, 1 for each channel.

Each TCR selects the count clock, specifies the edge when an external clock is selected, and controls interrupt generation when the flag indicating timer counter

(TCNT) underflow is set to 1. TMU.TCR2

is also used for channel 2 input capture control, and control of interrupt generation in the event of input capture.

The TCR registers are initialized to 0x0000 by a power-on or manual reset, but are not initialized in standby mode.

Note: there are 2 register formats 1 used by TCR[0] and TCR[1] and another by TCR[2] .

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Register descriptions 237

Field

TPSC

CKEG

TMU.TCR[n]

(n = 0 to 1)

0x10 + (n * 0x0C)

Bits

[0:2]

Operation

Read

Write

Hard reset

[3:4]

Operation

Read

Write

Hard reset

Size Volatile

Specifies the TCNT count clock for channel [n]

Returns current value

000: Counts on P φ /4

001: Counts on P φ /16

010: Counts on P φ /64

011: Counts on P φ /64

100: Counts on P φ /1024

101: Reserved (do not set)

110: Counts on-chip RTC output clock

111: Counts on external clock

000

Synopsis

Timer prescaler

Type

No Clock edge RW

Selects the external clock input edge when an external clock is selected or the input capture function is used

Returns current value

00: Count or input capture register set on rising edge

01: Count or input capture register set on falling edge

1x = Count or input capture register set on both rising and falling edges

Table 114: TMU.TCR[0:1]

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Register descriptions

Field

UNIE

UNF

TMU.TCR[n]

(n = 0 to 1)

0x10 + (n * 0x0C)

Hard reset

[6:7] 2

Operation

Read

Write

Hard reset

[8] 1

Operation

Read

Bits

[5]

Operation

Read

Write

Hard reset

[9:15]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis

Underflow interrupt control

Type

Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1, indicating TCNT underflow

Returns current value

0: Interrupt due to underflow (TUNI) is not enabled

1: Interrupt due to underflow (TUNI) is enabled

Reserved RO

Reserved

Ignored

Yes Underflow flag

Status flag that indicates the occurrence of underflow

0= TCNT has not underflowed

1= TCNT has underflowed

0= Clears flag to 0

1= Write ignored

Reserved

Invalid

Table 114: TMU.TCR[0:1]

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Register descriptions 239

When the input capture function is used, a data transfer request is sent to the

DMAC in the event of input capture.

When using the input capture function, the TCLK pin must be designated as an input pin with the TCOE bit in the TMU.TOCR

TMU.TCNT2

value in the input capture register ( TMU.TCPR2

The TMU.TCNT2

value is set in TMU.TCPR2

only when the TMU.TCR2

.ICPF bit is 0.

When the TMU.TCR2

.ICPF bit is 1, TMU.TCPR2

is not set in the event of input capture. When input capture occurs, a DMAC transfer request is generated regardless of the value of the TMU.TCR2

.ICPF bit. However, a new DMAC transfer request is not generated until processing of the previous request is finished.

Field

TPSC

TMU.TCR[2] 0x28

Bits

Hard reset

Size Volatile

[0:2]

Operation

Read

Write

3 No

Synopsis

Timer prescaler

Specifies the TCNT count clock for channel 2

Returns current value

000: Counts on P φ /4

001: Counts on P φ /16

010: Counts on P φ /64

011: Counts on P φ /64

100: Counts on P φ /1024

101: Reserved (Do not set

110: Counts on-chip RTC output clock

111: Counts on external clock

000

Table 115: TMU.TCR[2]

Type

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Register descriptions

Field

CKEG

UNIE

TMU.TCR[2] 0x28

Bits

[3:4]

Operation

Read

Write

Hard reset

[5]

Operation

Read

Write

Hard reset

Size Volatile

No Clock edge

Synopsis Type

Selects the external clock input edge when an external clock is selected or the input capture function is used

Returns current value

00: Count or input capture register set on rising edge

01: Count or input capture register set on falling edge

1x = Count or input capture register set on both rising and falling edges

No Underflow interrupt control RW

Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1, indicating TCNT underflow

Returns current value

0: Interrupt due to underflow (TUNI) is not enabled

1: Interrupt due to underflow (TUNI) is enable

Table 115: TMU.TCR[2]

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Register descriptions 241

Field

ICPE

UNF

TMU.TCR[2] 0x28

Bits

[6:7]

Operation

Read

Write

Hard reset

[8]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis

Input capture control

Type

00: Input capture function not used

01: Reserved (do not set)

10: Input capture function used, but interrupt due to input capture (TICPI2) not enabled

Data transfer request is sent to DMAC in the event of input capture

11: Input capture function used, and interrupt due to input capture (TICPI2) enabled

Data transfer request is sent to DMAC in the event of input capture

RW Yes Underflow flag

Indicates the occurrence of underflow

0: TCNT has not underflowed

1: TCNT has underflowed

0: Clear flag to 0

1= Ignored

Specifies whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used

Returns current value

Table 115: TMU.TCR[2]

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Register descriptions

Field

ICPF

TMU.TCR[2] 0x28

Bits Size Volatile

[9]

Operation

Read

Write

Hard reset

[10:15]

Operation

Read

Write

Hard reset

Yes

Synopsis

Input capture interrupt flag

Indicates the occurrence of input capture

This status flag is provided in channel 2 only.

0: Input capture has not occurred

1: Input capture has occurred

0: Clear flag to 0

1: Ignored

Reserved

Invalid

Table 115: TMU.TCR[2]

Type

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Register descriptions 243

8.2.6 Input capture register (TMU.TCPR2)

TMU.TCPR2

is a 32-bit read-only register for use with the input capture function, provided only in channel 2.

The input capture function is controlled by means of the input capture control bits

(ICPE1, ICPE0) and clock edge bits (CKEG1, CKEG0) in TMU.TCR2

. When input capture occurs, the TMU.TCNT2

value is copied into TMU.TCPR2

. The value is set in

TMU.TCPR2

only when the ICPF bit in TMU.TCR2

is 0.

TMU.TCPR2

is not initialized by a power-on or manual reset, or in standby mode.

Field Bits Size Volatile

[0:31]

Operation

Read

Write

Hard reset

Gives the value of TMU.TCNT2 when capture occurs

Returns current value

Ignored

0xFFFFFFFF

Table 116: TMU.TCPR2

Synopsis

Input capture value

Type

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244 Operation

8.3 Operation

Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32-bit timer constant register (TCOR). The channels have an auto- reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function.

8.3.1 Counter operation

When 1 of bits STR0 to STR2 is set to 1 in the timer start register ( TMU.TSTR

), the timer counter (TCNT) for the corresponding channel starts counting. When TCNT underflows, the UNF flag is set in the corresponding timer control register ( TCR ). If the UNIE bit in TCR is set to 1 at this time, an interrupt request is sent to the CPU.

At the same time, the value is copied from TCOR into TCNT, and the count-down continues (auto-reload function).

Example of count operation setting procedure

Figure 27 shows an example of the count operation setting procedure.

1 Select the count clock with bits TPSC2 to TPSC0 in the timer control register

( TCR ). When an external clock is selected, set the TCLK pin to input mode with the TCOE bit in TMU.TOCR

, and select the external clock edge with bits CKEG1 and CKEG0 in TCR .

2 Specify whether an interrupt is to be generated on TCNT underflow with the

UNIE bit in TCR .

3 When the input capture function is used, set the ICPE bits in TCR , including specification of whether the interrupt function is to be used.

4 Set a value in the timer constant register ( TCOR ).

5 Set the initial value in the timer counter ( TCNT ).

6 Set the STR bit to 1 in the timer start register ( TMU.TSTR

) to start the count

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Operation

PRELIMINARY DATA

Operation selection

Select count clock 1

Underflow interrupt generation setting

When input capture function is used

Input capture interrupt generation setting

Timer constant register setting

Set initial timer counter value

Start count 6

Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated.

Figure 27: Example of count operation setting procedure

245

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Operation

Auto-reload count operation

Figure 28 shows the

TCNT auto-reload operation.

TCNT value

TCOR

TCOR value set in TCNT on underflow

H'00000000

STR0–STR2

UNF

Time

Figure 28: TCNT auto-reload operation

TCNT count timing

Operating on internal clock

Any of 5 count clocks (Pø/4, Pø/16, Pø/64, Pø/256, or Pø/1024) scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2 to

TPSC0 bits in TCR .

Figure 29 shows the timing in this case.

Internal clock

TCNT N + 1 N

Figure 29: Count timing when operating on internal clock

N – 1

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Operation 247

Operating on external clock

External clock pin ( TCLK ) input can be selected as the timer clock by means of the

TPSC2 to TPSC0 bits in TCR . The detected edge (rising, falling, or both edges) can be selected with the CKEG1 and CKEG0 bits in TCR.

Figure 30 shows the timing

for both-edge detection.

P φ

External clock input pin

TCNT N + 1 N N – 1

Figure 30: Count timing when operating on external clock

Operating on-chip RTC output clock

The on-chip RTC output clock can be selected as the timer clock by means of the

TPSC2 to TPSC0 bits in TCR .

Figure 31 shows the timing in this case.

RTC output clock

TCNT N + 1 N N – 1

Figure 31: Count timing when operating on on-chip RTC output clock

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248 Operation

8.3.2 Input capture function

Channel 2 has an input capture function.

The procedure for using the input capture function follows.

1 Use the TCOE bit in the timer output control register ( TMU.TOCR

) to set the

TCLK pin to input mode.

2 Use bits TPSC2 to TPSC0 in the timer control register ( TCR ) to set an internal clock or the on-chip RTC output clock as the timer operating clock.

3 Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function, and whether interrupts are to generated when this function is used.

4 Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK signal is to be used to set the timer counter (TCNT) value in the input capture register ( TMU.TCPR2

This function cannot be used in standby mode.

When input capture occurs, the TMU.TCNT2

value is set in TMU.TCPR2

only when the ICPF bit in TMU.TCR2

is 0. Also, a new DMAC transfer request is not generated until processing of the previous request is finished.

Figure 32 shows the operation timing when the input capture function is used (with

TCLK rising edge detection).

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Interrupts

TCNT value

TCOR

PRELIMINARY DATA

TCOR value set in TCNT on underflow

249

H'00000000

TCLK

Time

TCPR2 TCNT value set

TICPI2

Figure 32: Operation timing when using input capture function

8.4 Interrupts

There are 4 TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used). Underflow interrupts are generated on channels 0 to 2, and input capture interrupts on channel 2 only.

An underflow interrupt request is generated (for each channel) according to the

AND of UNF and the interrupt enable bit (UNIE) in TCR .

When the input capture function is used and an input capture request is generated, an interrupt is requested if the input capture input flag (ICPF) in TMU.TCR2

is 1 and the input capture control bits (ICPE1, ICPE0) in TMU.TCR2

are 11.

The TMU interrupt sources are summarized in Table 117

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Channel Interrupt Source

TUNI0

TUNI1

TUNI2

TICPI2

Description

Underflow interrupt 0

Underflow interrupt 1

Underflow interrupt 2

Input capture interrupt 2

Table 117: TMU interrupt sources

Usage notes

Priority

High

↑

↓

Low

8.5.1 Register writes

When performing a register write, timer count operation must be stopped by clearing the start bit (STR0 to STR2) for the relevant channel in the timer start register ( TMU.TSTR

8.5.2 TCNT register reads

When performing a TCNT register read, processing for synchronization with the timer count operation is performed. If a timer count operation and register read processing are performed simultaneously, the TCNT counter value prior to the count-down operation is read by means of the synchronization processing.

8.5.3 Resetting the RTC frequency divider

When the on-chip RTC output clock is selected as the count clock, the RTC frequency divider should be reset.

8.5.4 External clock frequency

Ensure that the external clock frequency for any channel does not exceed P/4.

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Serial communication interface with FIFO

(SCIF)

9.1 Overview

This chapter describes a single-channel serial communication interface module with built-in FIFO registers (SCIF). The SCIF can perform asynchronous serial communication.

16 stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication.

9.1.1 Features

SCIF features are listed below.

• Asynchronous serial communication in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as UART or ACIA.

There is a choice of eight serial data transfer formats:

data length: 7 or 8 bits,

stop bit length: 1 or 2 bits

parity: even, odd or none.

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Overview

• Receive error detection:

parity,

framing,

overrun errors.

• Break detection: if the receive data following that in which a framing error occurred is also at the space 0 level, and there is a frame error, a break is detected. When a framing error occurs, a break can also be detected by reading the RXD pin level directly from the serial port register ( SCIF.SCSPTR

• Full duplex communication capability: the transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously.

The transmitter and receiver both have a 16 stage FIFO buffer structure, enabling fast and continuous serial data transmission and reception.

• On-chip baud rate generator allows any bit rate to be selected.

• Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin.

• 4 interrupt sources: there are 4 interrupt sources that can issue requests independently:

TRANSMIT-FIFO-DATA-EMPTY ,

BREAK ,

RECEIVE-FIFO-DATA-FULL ,

RECEIVE-ERROR .

• The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a TRANSMIT-FIFO-DATA-EMPTY or RECEIVE-FIFO-DATA-FULL interrupt.

• When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption.

• Modem control functions (RTS and CTS) are provided.

• The amount of data in the transmit and receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained.

• A TIME-OUT ERROR ( DR ) can be detected during reception.

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Overview

9.1.2 Block diagram

Figure 33 shows a block diagram of the SCIF.

Module data bus

RxD2

TxD2

SCFRDR2

(16-stage)

SCRSR2

SCFTDR2

(16-stage)

SCTSR2

Parity generation

Parity check

SCSMR2

SCLSR2

SCFDR2

SCFCR2

SCFSR2

SCSCR2

SCSPTR2

Transmission/ reception control

Clock

SCBRR2

Baud rate generator

External clock

SCK2

CTS2

RTS2

SCIF

SCRSR2: Receive shift register

SCFRDR2: Receive FIFO data register

SCTSR2: Transmit shift register

SCFTDR2: Transmit FIFO data register

SCSMR2: Serial mode register

SCSCR2: Serial control register

SCFSR2: Serial status register

SCBRR2: Bit rate register

SCSPTR2: Serial port register

SCFCR2: FIFO control register

SCFDR2: FIFO data count register

SCLSR2: Line status register

Figure 33: Block diagram of SCIF

Internal data bus

P φ

P φ /4

/16

/64

TXI

RXI

ERI

BRI

253

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9.1.3 Pin configuration

Table 118

shows the SCIF pin configuration.

Pin name Abbreviation I/O Function

Serial clock pin

Receive data pin

MRESET/SCK

MD2/RXD

Transmit data pin MD1/TXD

Modem control pin CTS

Modem control pin MD8/RTS

Input

Output

I/O

Clock input

Receive data input

Transmit data output

Transmission enabled (clear to send)

Transmission request (request to send)

Table 118: SCIF pins

Note: The MRESET/SCK pin functions as the MRESET manual reset pin when a manual reset is executed. The MD1/TXD, MD/RXD , and MD8/RTS pins function as the MD1,

MD2 , and MD8 mode input pins after a power-on reset. These pins are made to function as serial pins by performing SCIF operation settings with the TE and RE bits in SCIF.SCSCR

and the MCE bit in SCIF.SCFCR

. Break state transmission and detection can be set in the SCIF’s SCIF.SCSPTR

register.

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Overview 255

9.1.4 Register configuration

The SCIF has the internal registers shown in

Table 119 . These registers are used to

specify the data format and bit rate, and to perform transmitter and receiver control. All addresses are given as offsets from the base address for this module. See the system address map for details.

Register name Description Type

Initial value

Address offset

Access size

SCIF.SCRSR

SCIF.SCFRDR

SCIF.SCTSR

SCIF.SCFTDR

SCIF.SCSMR

SCIF.SCSCR

SCIF.SCFSR

SCIF.SCBRR

SCIF.SCFCR

SCIF.SCFDR

SCIF.SCSPTR

SCIF.SCLSR

Receive shift register

Receive FIFO data register, see

Table 120 on page 257

Transmit shift register

Transmit FIFO data register, see

Table 121 on page 258

Serial mode register, see

Table 122 on page 259

Serial control register, see

Table 123 on page 264

Serial status register, see

Table 124 on page 271

Bit rate register, see

Table 125 on page 283

FIFO control register, see

Table 127 on page 285

FIFO data count register, see

Table 128 on page 291

Serial port register, see

Table 129 on page 293

Line status register, see

Table 130 on page 301

R(W)

Undefined 0x14

Undefined 0x0C

0x0000

0x0060

0xFF

0x0000

0x00

0x08

0x10

0x04

0x18

0x1C

0x20

0x24

Table 119: SCIF registers

A. Only 0 can be written, to clear flags. Bits 15 to 8, 3, and 2 are read-only, and cannot be modified.

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256 Register descriptions

B. The value of bits 6, 4 and 0 is undefined.

C. Only 0 can be written, to clear flags. Bits 15 to 1 are read-only, and cannot be modified.

This section describes all register states for the SCIF module.

Note: all addresses are given as offsets from the base address for this module. See the system address map for details.

9.2.1 Receive shift register (SCIF.SCRSR)

Bit 7 6 5 4 3 2 1 0

RW -

SCIF.SCRSR

is the register used to receive serial data.

The SCIF sets serial data input from the RXD pin in SCIF.SCRSR

in the order received, starting with the LSB (bit 0), and converts it to parallel data. When 1one byte of data has been received, it is transferred to the receive FIFO register,

SCIF.SCFRDR

, automatically.

SCIF.SCRSR

cannot be directly read or written to by the CPU.

9.2.2 Receive FIFO data register (SCIF.SCFRDR)

SCIF.SCFRDR

is a 16 stage FIFO register that stores received serial data.

When the SCIF has received 1 byte of serial data, it transfers the received data from

SCIF.SCRSR

to SCIF.SCFRDR

where it is stored, and completes the receive operation. SCIF.SCRSR

is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO register is full (16 data bytes).

SCIF.SCFRDR

is a read-only register, and cannot be written to by the CPU.

If a read is performed when there is no receive data in the receive FIFO register, an undefined value will be returned. When the receive FIFO register is full of receive

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are undefined after a power-on reset or manual reset.

Field

SCIF.SCF

RDR

SCIF.SCFRDR

0x14

Bits

Write

Hard reset

Size Volatile

[0:7]

Operation

Read

Yes

Synopsis

16-byte receive FIFO data register

Type

Holds data transferred from the SCIF.SCRSR

Returns and removes the next data item in the FIFO

If the FIFO is empty an undefined value is returned.

Invalid

Undefined

Table 120: SCIF.SCFRDR

9.2.3 Transmit shift register (SCIF.SCTSR)

Bit 7 6 5 4 3 2 1 0

RW — — — — — — — —

SCIF.SCTSR

is the register used to transmit serial data.

To perform serial data transmission, the SCIF first transfers transmit data from

SCIF.SCFTDR

to SCIF.SCTSR

, then sends the data to the TXD pin starting with the

LSB (bit 0).

When transmission of 1 byte is completed, the next transmit data is transferred from SCIF.SCFTDR

to SCIF.SCTSR

, and transmission started, automatically.

SCIF.SCTSR

cannot be directly read or written to by the CPU.

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9.2.4 Transmit FIFO data register (SCIF.SCFTDR)

SCIF.SCFTDR

is a 16 stage FIFO register that stores data for serial transmission.

If SCIF.SCTSR

is empty when transmit data has been written to SCIF.SCFTDR

, the

SCIF transfers the transmit data written in SCIF.SCFTDR

to SCIF.SCTSR

and starts serial transmission.

SCIF.SCFTDR

is a write-only register, and cannot be read by the CPU.

The next data cannot be written when SCIF.SCFTDR

is filled with 16 bytes of transmit data. Data written in this case is ignored. The contents of SCIF.SCFTDR

are undefined after a power-on reset or manual reset.

Field

SCFTDR

SCIF.SCFTDR

0x0C

Bits

Hard reset

Size Volatile

[0:7]

Operation

Read

Write

8 Yes

Stores data for serial transmission

Invalid

Synopsis

16-byte transmit FIFO data register

Appends data to the FIFO register to be copied to

SCIF.SCTSR

If the FIFO is full the write is ignored.

Undefined

Type

Table 121: SCIF.SCFTDR

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Register descriptions 259

9.2.5 Serial mode register (SCIF.SCSMR)

SCIF.SCSMR

is a 16-bit register used to set the SCIF’s serial transfer format and select the baud rate generator clock source.

SCIF.SCSMR

can be read or written to by the CPU at all times.

SCIF.SCSMR

is initialized to 0x0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state.

Field

CKS1,

CKS0

STOP

SCIF.SCSMR

0x00

Read

Write

Hard reset

[2]

Operation

Read

Write

Hard reset

[3]

Operation

Read

Write

Hard reset

Bits Size Volatile

[0:1]

Operation

2 No

Synopsis

Clock select 1 and 0

Type

Selects the clock source for the on-chip baud rate generator.

See Section : Bits 1 and 0: clock select 1 and 0 (CKS1,

CKS0) on page 263

Returns current value

Updates current value

Reserved

No Stop bit length

Sets the stop bit length

Returns current value

See Section : Bit 3: stop bit length (STOP) on page 262

Table 122: SCIF.SCSMR

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Register descriptions

Field

O/E

CHR

SCIF.SCSMR

0x00

Read

Write

Hard reset

[6] 1

Operation

Read

Write

Hard reset

[7:15]

Operation

Read

Write

Hard reset

Bits

[4]

Operation

Read

Write

Hard reset

[5]

Operation

Size Volatile

No Parity mode

Synopsis Type

Selects either even or odd parity for use in parity addition and checking

This field is only used when the PE bit is set to 1.

Returns the current value.

See Section : Bit 4: parity mode (O/E) on page 261

No Parity Enable RW

Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception

Returns current value

See Section : Bit 5: parity enable (PE) on page 261

No Character Length RW

Selects 7 or 8 bits as the asynchronous mode data length.

Returns current value

See Section : Bit 6: character length (CHR) on page 261

RO -

Reserved

Table 122: SCIF.SCSMR

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Register descriptions

Bits 15 to 7: reserved

These bits are always read as 0, and should only be written with 0.

Bit 6: character length (CHR)

Selects 7 or 8 bits as the asynchronous mode data length.

Bit 6: CHR Description

8-bit data (initial value)

7-bit data

A. When 7-bit data is selected, the MSB (bit 7) of

SCIF.SCFTDR

is not transmitted.

261

Bit 5: parity enable (PE)

Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception.

Bit 5: PE Description

Parity bit addition and checking disabled

(Initial value)

Parity bit addition and checking enabled

A. When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit.

Bit 4: parity mode (O/E)

Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and

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Bit 4: O/E Description

Even parity

(initial value)

Odd parity

A. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even.

B. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd.

Bit 3: stop bit length (STOP)

Selects 1 or 2 bits as the stop bit length.

Bit 3: STOP Description

1 stop bit

(initial value)

2 stop bits

A. In transmission, 1 bit (stop bit) is added to the end of a transmit character before it is sent.

B. In transmission, 2 bits (stop bits) are added to the end of a transmit character before it is sent.

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Register descriptions 263

In reception, only the first stop bit is checked, regardless of the stop bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character.

Bit 2: reserved

This bit is always read as 0, and should only be written with 0.

Bits 1 and 0: clock select 1 and 0 (CKS1, CKS0)

These bits select the clock source for the on-chip baud rate generator. The clock source can be selected from Pø, Pø/4, Pø/16, and Pø/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see

Section 9.2.8: Bit rate register (SCIF.SCBRR) on page 282

Bit 1: CKS1

Bit 0: CKS0

1 0

A. Pø: Peripheral clock

Description

φ A

clock (initial value)

P φ /4 clock

/16 clock

P φ /64 clock

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9.2.6 Serial control register (SCIF.SCSCR)

The SCIF.SCSCR

register performs enabling or disabling of SCIF transfer operations, and interrupt requests, and selection of the serial clock source.

SCIF.SCSCR

can be read or written at any time.

SCIF.SCSCR

is initialized to 0x0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state.

Field

CKE0

CKE1

SCIF.SCSCR

0x08

Bits Size Volatile

[0]

Operation

Read

Write

Hard reset

[1]

Operation

Read

Write

Hard reset

[2]

Operation

Read

Write

Hard reset

Synopsis

No Clock enable 0

Selects the SCIF clock source

Returns the current value

See

Clock enable (CKE0 and CKE1) on page 269

No Clock enable 1

Selects the SCIF clock source

Returns the current value

See

Clock enable (CKE0 and CKE1) on page 269

Reserved

Invalid

Table 123: SCIF.SCSCR

Type

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Register descriptions 265

Field

REIE

RIE

SCIF.SCSCR

0x08

Bits Size Volatile

[3]

Operation

Read

Write

Hard reset

[4] 1

Operation

Read

Write

Hard reset

[5]

Operation

Read

Write

Hard reset

[6]

Operation

Read

Write

Hard reset

Synopsis

Receive error interrupt enable

Type

Enables or disables generation of receive-error interrupt

(ERI) and BREAK interrupt (BRI) requests

Returns the current value

See

Bit 3: receive error interrupt enable (REIE) on page 269 .

Enables or disables the start of serial reception by the SCIF

Returns the current value

See

Bit 4: receive enable (RE) on page 268

No Transmit enable RW

Enables or disables the start of serial transmission by the

SCIF

Returns the current value

See

Bit 5: transmit enable (TE) on page 268 .

No Receive interrupt enable

Enables or disables generation of a receive interrupts

Returns the current value

See

Bit 6: receive interrupt enable (RIE) on page 267

Table 123: SCIF.SCSCR

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Register descriptions

TIE

Field

SCIF.SCSCR

0x08

Bits Size Volatile

[7]

Operation

Read

Write

Hard reset

[8:15]

Operation

Read

Write

Hard reset

Synopsis Type

No Transmit interrupt enable

Enables or disables transmit interrupts

Returns the current value

See

Bit 7: transmit interrupt enable (TIE) on page 267

No Reserved RO

Reserved

Invalid

Table 123: SCIF.SCSCR

Bits 15 to 8 and 2: reserved

These bits are always read as 0, and should only be written with 0.

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Register descriptions

Bit 7: transmit interrupt enable (TIE)

Bit 7 enables or disables TRANSMIT-FIFO-DATA-EMPTY interrupt ( TXI ) request generation when serial transmit data is transferred from SCIF.SCFTDR

SCIF.SCTSR

. The number of data bytes in the transmit FIFO register falls to or below the transmit trigger set number, and the TDFE flag in the serial status register ( SCIF.SCFSR

) is set to 1.

Bit 7: TIE Description

0 TRANSMIT-FIFO-DATA-EMPTY interrupt (TXI) request disabled

(initial value)

1 Transmit-FIFO-data-empty interrupt (TXI) request enabled

A. TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to SCIF.SCFTDR, reading 1 from the TDFE flag, then clearing it to 0, or by clearing the TIE bit to 0.

267

Bit 6: receive interrupt enable (RIE)

Bit 6 enables or disables generation of the following requests:

• a receive data full interrupt ( RXI ) request when the RDF flag or DR flag in

SCIF.SCFSR

is set to 1,

• a receive error interrupt ( ERI ) request when the ER flag in SCIF.SCFSR

is set to

• a BREAK interrupt ( BRI ) request when the BRK flag in SCIF.SCFSR

or the

ORER flag in SCIF.SCLSR

is set to 1.

Bit 6: RIE

Description

Disables the RXI, ERI and BRI requests (initial value)

Enables the RXI, ERI and BRI requests

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Register descriptions

A. An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0.

Bit 5: transmit enable (TE)

Bit 5 enables or disables the start of serial transmission by the SCIF.

Bit 5: TE Description

Transmission disabled (initial value)

Transmission enabled

A. Serial transmission is started when transmit data is written to SCIF.SCFTDR

in this state.

Serial mode register ( SCIF.SCSMR

) and FIFO control register ( SCIF.SCFCR

) settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1.

Bit 4: receive enable (RE)

Bit 4 enables or disables the start of serial reception by the SCIF.

Bit 4: RE Description

Reception disabled

(initial value)

Reception enabled

A. Clearing the RE bit to 0 does not affect the DR, ER, BRK,

RDF, FER, PER, and ORER flags, which retain their states.

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Register descriptions

B. Serial transmission is started when a start bit is detected in this state. Serial mode register

( SCIF.SCSMR

) and FIFO control register ( SCIF.SCFCR

) settings must be made, the reception format decided, and the receive FIFO reset, before the RE bit is set to 1.

269

Bit 3: receive error interrupt enable (REIE)

Bit 3 enables or disables generation of receive error interrupt ( ERI ) and BREAK interrupt ( BRI ) requests. The REIE bit setting is valid only when the RIE bit is 0.

Bit 3: REIE Description

ERI and BRI requests disabled

(initial value)

1 ERI and BRI requests enabled

A. ERI and BRI requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI requests are generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is to be notified of ERI and BRI requests.

Bit 2: reserved

This bit is always read as 0, and cannot be modified.

Clock enable (CKE0 and CKE1)

These bits select the SCIF clock source and enable or disable clock output from the

SCK pin. The combination of CKE1 and CKE0 determine whether the SCK pin functions as serial clock output pin or the serial clock input pin.

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270 Register descriptions

Note: however, the setting of the CKE0 bit is valid only when CKE1: 0 (internal clock operation). When CKE1: 1 (external clock) CKE0 is ignored. These bits must be set before determining the SCIF’s operating mode with SCIF.SCSMR

Bit 1: CKE1 Bit 0: CKE0 Description

Use internal clock

SCK pin functions as input pin, input signal ignored

(initial value)

Use internal clock

SCK pin functions as clock output

A. Outputs a clock with a frequency 16 times the bit rate.

9.2.7 Serial status register (SCIF.SCFSR)

SCIF.SCFSR

is a 16-bit register. The lower 8 bits consist of status flags that indicate the operating status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the receive FIFO register.

SCIF.SCFSR

can be read or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR.

Note: in order to clear these flags they must be read as 1 beforehand. The FER flag and

PER flag are read-only flags and cannot be modified.

SCIF.SCFSR

is initialized to 0x0060 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state.

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Register descriptions 271

Field

RDF

PER

SCIF.SCFSR

0X10

Bits

[0]

Operation

Read

Write

Hard reset

[1] 1

Operation

Read

Write

Hard reset

[2]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis Type

Yes Receive data ready

Indicates that there are fewer than the receive trigger set number of data bytes in SCIF.SCFRDR

, and no further data has arrived for at least 15 etu after the stop bit of the last data received

See

Bit 0: receive data ready (DR) on page 282

Returns current value

0: Clear the flag

Yes RECEIVE-FIFO-DATA-FULL

Indicates that the received data has been transferred from

SCIF.SCRSR

to SCIF.SCFRDR

, and the number of receive data bytes in SCIF.SCFRDR

is equal to or greater than the receive trigger number set by bits RTRG1 and

RTRG0 in the FIFO control register (SCIF.SCFCR)

See

Bit 1: receive-FIFO-data-full (RDF) on page 281

Returns current value

0: Clear the flag

Yes Parity error RO

Indicates a parity error in the data read from SCIF.SCFRDR

See

Bit 2: parity error (PER) on page 280

Returns current value

Invalid

Table 124: SCIF.SCFSR

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Register descriptions

Field

FER

BRK

TDFE

SCIF.SCFSR

0X10

Bits

Read

Write

Hard reset

[5] 1

Read

Write

Hard reset

Size Volatile

[3]

Operation

Read

Write

Hard reset

[4] 1

Operation

Yes Framing error

Synopsis

Indicates a framing error in the data read from

SCIF.SCFRDR

See

Bit 3: framing error (FER) on page 280

Returns current value

Type

Invalid

Break detect

Indicates that a receive data break signal has been detected

See

Bit 4: break detect (BRK) on page 279

Returns current value

0: Clear the flag

Yes TRANSMIT-FIFO-DATA-EMPTY

Indicates that data has been transferred from SCIF.SCFTDR to SCIF.SCTSR, the number of data bytes in SCIF.SCFTDR has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register

(SCIF.SCFCR), and new transmit data can be written to

SCIF.SCFTDR

See

Bit 5: transmit-FIFO-data-empty (TDFE) on page 278

Returns current value

0: Clear the flag

Table 124: SCIF.SCFSR

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Register descriptions 273

Field

TEND

FER3 to

FER0

SCIF.SCFSR

0X10

Bits

[6]

Operation

Read

Write

Hard reset

[7] 1

Operation

Read

Write

Hard reset

[8:11]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis Type

Yes Transmit end

Indicates that there is no valid data in SCIF.SCFTDR when the last bit of the transmit character is sent, and transmission has been ended

See

Bit 6: transmit end (TEND) on page 277 .

Returns current value

0: Clear the flag

Receive error

Indicates that a framing error or parity error occurred during

reception.See Bit 7: receive error (ER) on page 274

Returns current value

Only 0 can be written. This clears the flag

Yes Number of framing errors RO

These bits indicate the number of data bytes in which a framing error occurred in the receive data stored in

SCIF.SCFRDR

See

Bits 11 to 8: number of framing errors (FER3 to FER0) on page 274

Returns current value

Invalid

Table 124: SCIF.SCFSR

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Register descriptions

Field

PER3 to

PER0

SCIF.SCFSR

0X10

Bits

Read

Write

Hard reset

Size Volatile

[12:15] 4

Operation

Yes

Synopsis

Number of parity errors

Type

These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCIF.SCFRDR

See

Bits 15 to 12: number of parity errors (PER3 to PER0) on page 274 .

Returns current value

Invalid

Table 124: SCIF.SCFSR

Bits 15 to 12: number of parity errors (PER3 to PER0)

Bits 15 to 12 indicate the number of data bytes in which a parity error occurred in the receive data stored in SCIF.SCFRDR

. After the ER bit in SCIF.SCFSR

is set, the value indicated by bits 15 to 12 is the number of data bytes in which a parity error occurred. If all 16 bytes of receive data in SCIF.SCFRDR

have parity errors, the value indicated by bits PER3 to PER0 will be 0.

Bits 11 to 8: number of framing errors (FER3 to FER0)

Bits 11 to 8 indicate the number of data bytes in which a framing error occurred in the receive data stored in SCIF.SCFRDR

. After the ER bit in SCIF.SCFSR

is set, the value indicated by bits 11 to 8 is the number of data bytes in which a framing error occurred. If all 16 bytes of receive data in SCIF.SCFRDR

have framing errors, the value indicated by bits FER3 to FER0 will be 0.

Bit 7: receive error (ER)

Bit 7 indicates that a framing error or parity error occurred during reception. The

ER flag is not affected and retains its previous state when the RE bit in

SCIF.SCSCR

is cleared to 0. When a receive error occurs, the receive data is still transferred to SCIF.SCFRDR

, and reception continues. The FER and PER bits in

SCIF.SCFSR

can be used to determine whether there is a receive error in the data read from SCIF.SCFRDR.

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275

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Register descriptions

Bit 7: ER Description

No framing error or parity error occurred during reception (initial value)

Clearing conditions are:

Power-on reset

Manual reset

When 0 is written to ER after reading ER = 1

A framing error or parity error occurred during reception

Setting conditions are:

When the SCIF checks whether the stop bit at the end of the receive data is 1

When reception ends, and the stop bit is 0

When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in

SCIF.SCSMR

A. In 2 stop bit mode, only the first stop bit is checked for a value of 1. The second stop bit is not checked.

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Register descriptions 277

Bit 6: transmit end (TEND)

Bit 6 indicates that there is no valid data in SCIF.SCFTDR

when the last bit of the transmit character is sent, and transmission has been ended.

Bit 6: TEND

Description

Transmission in progress

Clearing conditions are:

When transmit data is written to SCIF.SCFTDR, and 0 is written to TEND after reading TEND = 1.

When data is written to SCIF.SCFTDR by the DMAC

Transmission ended (initial value)

Setting conditions are:

When there is a power-on reset or manual reset.

When the TE bit in SCIF.SCSCR is 0.

When there is no transmit data in SCIF.SCFTDR on transmission of the last bit of a 1-byte serial transmit character.

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Register descriptions

Bit 5: transmit-FIFO-data-empty (TDFE)

Bit 5 indicates that data has been transferred from SCIF.SCFTDR

to SCIF.SCTSR

, the number of data bytes in SCIF.SCFTDR

has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register

( SCIF.SCFCR

), and new transmit data can be written to SCIF.SCFTDR.

Bit 5: TDFE Description

A number of transmit data bytes exceeding the transmit trigger set number written to SCIF.SCFTDR

Clearing conditions are:

When transmit data exceeding the transmit trigger set number is written to SCIF.SCFTDR, and 0 is written to

TDFE after reading TDFE = 1.

When transmit data exceeding the transmit trigger set number is written to SCIF.SCFTDR by the DMAC.

The number of transmit data bytes in SCIF.SCFTDR does not exceed the transmit trigger set number

(initial value)

Setting conditions are:

When there is a power-on reset or manual reset.

When the number of SCIF.SCFTDR transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation

A. As SCIF.SCFTDR

is a 16-byte FIFO register, the maximum number of bytes that can be written when

TDFE = 1 is 16 (transmit trigger set number). Data written in excess of this will be ignored. The number of data bytes in SCIF.SCFTDR

is indicated by the upper bits of SCIF.SCFDR

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Register descriptions

Bit 4: break detect (BRK)

Bit 4 indicates that a receive data BREAK signal has been detected.

Bit 4: BRK Description

0 A BREAK signal has not been received (initial value)

Clearing conditions are:

Power-on reset or manual reset

When 0 is written to BRK after reading BRK = 1

A break signal has been received

Setting condition is:

When data with a framing error is received, followed by the space 0 level (low level) for at least 1 frame length

A. When a BREAK is detected, the receive data (0x00) following detection is not transferred to SCIF.SCFRDR

When the break ends and the RECEIVE signal returns to mark 1, receive data transfer is resumed.

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Register descriptions

Bit 3: framing error (FER)

Bit 3 indicates a framing error in the data read from SCIF.SCFRDR

Bit 3: FER

Description

No framing error in the receive data read from

SCIF.SCFRDR

(initial value)

Clearing conditions are:

When there is a power-on reset or manual reset.

When there is no framing error in SCIF.SCFRDR

read data.

Framing error in the receive data read from

SCIF.SCFRDR

Setting condition is:

When there is a framing error in SCIF.SCFRDR

read data.

Bit 2: parity error (PER)

Bit 2 indicates a parity error in the data read from SCIF.SCFRDR

Bit 2: PER

Description

No parity error in the receive data read from

SCIF.SCFRDR

(initial value)

Clearing conditions are:

When there is a power-on reset or manual reset.

When there is no parity error in SCIF.SCFRDR

read data.

Parity error in the receive data read from

SCIF.SCFRDR

Setting condition is:

When there is a parity error in SCIF.SCFRDR

read data.

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Register descriptions 281

Bit 1: receive-FIFO-data-full (RDF)

Bit 1 indicates that the received data has been transferred from SCIF.SCRSR

SCIF.SCFRDR

, and the number of receive data bytes in SCIF.SCFRDR

is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register ( SCIF.SCFCR

Bit 1: RDF Description

The number of receive data bytes in SCIF.SCFRDR

is less than the receive trigger set number (initial value)

Clearing conditions are:

Power-on reset or manual reset

When SCIF.SCFRDR

is read until the number of receive data bytes in

SCIF.SCFRDR

falls below the receive trigger set number, and 0 is written to RDF after reading RDF = 1

When SCIF.SCFRDR

is read by the DMAC until the number of receive data bytes in SCIF.SCFRDR

falls below the receive trigger set number

The number of receive data bytes in SCIF.SCFRDR

is equal to or greater than the receive trigger set number

Setting condition is:

When SCIF.SCFRDR

contains at least the receive trigger set number of receive data bytes

SCIF.SCFRDR

is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in

SCIF.SCFRDR

is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCIF.SCFRDR

is indicated by the lower bits of SCIF.SCFDR

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Register descriptions

Bit 0: receive data ready (DR)

Bit 0 indicates that there are fewer than the receive trigger set number of data bytes in SCIF.SCFRDR

, and no further data has arrived for at least 15 etu after the stop bit of the last data received.

Bit 0: DR Description

0 Reception is in progress or has ended normally and there is no receive data left in SCIF.SCFRDR

(initial value)

Clearing conditions are:

Power-on reset or manual reset

When all the receive data in SCIF.SCFRDR

has been read, and 0 is written to DR after reading DR = 1

When all the receive data in SCIF.SCFRDR

has been read by the DMAC

1 No further receive data has arrived

Setting condition is:

When SCIF.SCFRDR

contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu

after the stop bit of the last data received

A. Etu: elementary time unit (time for transfer of 1 bit)

B. Equivalent to 1.5 frames with an 8-bit, 1 stop bit format

9.2.8 Bit rate register (SCIF.SCBRR)

SCIF.SCBRR

is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in

SCIF.SCSMR

SCIF.SCBRR

can be read or written to by the CPU at all times.

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Register descriptions 283

SCIF.SCBRR

is initialized to H’FF by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state.

Field

SCBRR

SCIF.SCBRR

0x04

Bits Size Volatile

[0:7]

Operation

Read

Write

Hard reset

Synopsis

Bit rate register

Type

Specifies the serial transfer bit rate in accordance with the baud rate generator operating clock

Returns current value

Updates current Value

0xFF

Table 125: SCIF.SCBRR

The SCIF.SCBRR

setting is found from the following equation. Asynchronous mode

×

-------------------------------------

2n – 1

×

– 1 = N

Where:

B = Bit rate (bits/s)

N = SCIF.SCBRR

setting for baud rate generator (0

≤

255)

= Peripheral module operating frequency (MHz) n = Baud rate generator input clock (n = 0 to 3)

(See

Table 126 for the relation between n and the clock.)

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Register descriptions

3 n

SCIF.SCSMR setting

CKS0 Clock CKS1

P φ

P φ /4

P φ /16

P φ /64

Table 126: Relation between n and the clock

The bit rate error in asynchronous mode is found from the following equation:

(

N + 1

) ×

×

P 10

-------------------------------------------------------------1

× ×

2n – 1

–

×

100

9.2.9 FIFO control register (SCIF.SCFCR)

SCIF.SCFCR

performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit.

SCIF.SCFCR

can be read or written at any time.

SCIF.SCFCR

is initialized to 0x0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state.

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Register descriptions 285

Field

LOOP

RFRS

TFRST

MCE

SCIF.SCFCR

0x18

Bits

[0]

Operation

Read

Write

Hard reset

[1]

Operation

Read

Write

Hard reset

[2]

Operation

Read

Write

Hard reset

[3]

Operation

Read

Write

Hard reset

Size Volatile

No Loopback test

Synopsis

Enables loopback testing

See Bit 0: loopback test (LOOP) on page 290

Returns current value

Type

Updates current value

No Received FIFO data register reset RW

Enables FIFO reset on a power-on or manual reset

See Bit 1: receive FIFO data register reset (RFRST) on page 290

Returns current value

Updates current value

No Transmit FIFO data register reset RW

Enables FIFO reset on a power-on or manual reset. See

Bit

2: transmit FIFO data register reset (TFRST) on page 290 .

Returns current value

Updates current value

No Modem control enable RW

Enables modem control signals. See

Bit 3: modem control enable (MCE) on page 289

Returns current value

Updates current value

Table 127: SCIF.SCFCR

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Register descriptions

Field

TTRG0

TTRG1

RTRG0

RTRG1

RSTRG0

RSTRG1

RSTRG2

SCIF.SCFCR

0x18

Bits Size Volatile

[4:5]

Operation

Read

Write

Hard reset

[6:7]

Operation

Read

Write

Hard reset

[8:10]

Operation

Read

Write

Hard reset

Synopsis

Transmit FIFO data number triggers

Type

Sets the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag

See Bits 5 and 4: transmit FIFO data number trigger

(TTRG1, TTRG0) on page 289 .

Returns current value

Updates current value

No Receive FIFO data number triggers RW

Sets the number of receive data bytes that sets the receive data full (RDF) flag

See Bits 7 and 6: receive FIFO data number trigger

(RTRG1, RTRG0) on page 288

Returns current value

Updates current value

No RTS output active trigger

Sets the number of receive data bytes that sets the

NOT_RTS signal active

See Bits 10, 9 and 8: RTS output active trigger

(RSTRG2, RSTRG1 and RSTRG0) on page 288

Returns current value

Updates current value

Table 127: SCIF.SCFCR

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Register descriptions 287

Field

SCIF.SCFCR

0x18

Bits Size Volatile

[11:15] 5

Operation

Read

Write

Hard reset

Yes

Reserved.

Reserved

Synopsis

0 (should only be written with 0)

Table 127: SCIF.SCFCR

Bits 15 to 11: reserved

Bits 15 to 11 are always read as 0, and should only be written with 0.

Type

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Register descriptions

Bits 10, 9 and 8: RTS output active trigger (RSTRG2, RSTRG1 and RSTRG0)

Bits 10, 9 and 8 set the NOT_RTS signal active when the number of received data stored in the receive FIFO data register ( SCFRDR ) exceeds the trigger number, as shown in the table.

Bit 10: RSTRG2 Bit 9: RSTRG1

Bit 8: RSTRG0

RTS output active trigger

15 (initial value)

Bits 7 and 6: receive FIFO data number trigger (RTRG1, RTRG0)

Bits 7 and 6 are used to set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status register ( SCIF.SCFSR

The RDF flag is set when the number of receive data bytes in SCIF.SCFRDR

is equal to or greater than the trigger set number shown in the following table.

Bit 7: RTRG1

Bit 6: RTRG0

Receive trigger number

1 (initial value)

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Register descriptions 289

Bits 5 and 4: transmit FIFO data number trigger (TTRG1, TTRG0)

Bits 5 and 4 are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status register

( SCIF.SCFSR

). The TDFE flag is set when the number of transmit data bytes in

SCIF.SCFTDR

is equal to or less than the trigger set number shown in the following table.

Bit 5: TTRG1

Bit 4: TTRG0

Transmit trigger number

Empty bytes in

SCIF.SCFTDR when TDFE flag is set

Bit 3: modem control enable (MCE)

Bit 3 enables the CTS and RTS modem control signals.

Bit 3: MCE Description

Modem signals disabled

(initial value)

1 Modem signals enabled

A. CTS is fixed at active 0 regardless of the input value, and RTS output is also fixed at 0.

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Register descriptions

Bit 2: transmit FIFO data register reset (TFRST)

Bit 2 invalidates the transmit data in the transmit FIFO data register and resets it to the empty state.

Bit 2:

TFRST

Description

Reset operation disabled

(initial value)

Reset operation enabled

A. A reset operation is performed in the event of a power-on reset or manual reset.

Bit 1: receive FIFO data register reset (RFRST)

Bit 1 invalidates the receive data in the receive FIFO data register and resets it to the empty state. A reset operation is performed in the event of a power-on reset or manual reset.

Bit 1: RFRST

Description

Reset operation disabled

(initial value)

Reset operation enabled

Bit 0: loopback test (LOOP)

Bit 0 internally connects the transmit output pin ( TXD ) and receive input pin ( RXD ), and the RTS pin and CTS pin, enabling loopback testing.

Bit 0: LOOP

Description

Loopback test disabled

(initial value)

Loopback test enabled

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Register descriptions 291

9.2.10 FIFO data count register (SCIF.SCFDR)

SCIF.SCFDR

is a 16-bit register that indicates the number of data bytes stored in

SCIF.SCFTDR

and SCIF.SCFRDR

The upper bits show the number of transmit data bytes in SCIF.SCFTDR

, and the lower bits show the number of receive data bytes in SCIF.SCFRDR

SCIF.SCFDR

can be read by the CPU at all times.

Field

SCIF.SCFDR

0x1C

Bits

[0:4]

Operation

Read

Write

Hard reset

[5:7]

Operation

Read

Write

Hard reset

Size Volatile

Yes

Invalid

0x00

Synopsis

Received data count

Type

These bits show the number of receive data bytes in

SCIF.SCFRDR

Returns the current count

A value of 0x00 indicates that there is no receive data, and a value of 0x10 indicates that SCIF.SCFRDR is full of receive data.

Yes

Reserved.

Reserved

0 (should only be written with 0)

Table 128: SCIF.SCFDR

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Register descriptions

Field

T0 to T4

SCIF.SCFDR

0x1C

Bits

Write

Hard reset

[13:15] 3

Operation

Read

Write

Hard reset

Size Volatile

[8:12]

Operation

Read

Yes

Synopsis

Transmitted data count

Type

Shows the number of untransmitted data bytes in

SCIF.SCFTDR

Returns the current count

A value of 0x00 indicates that there is no transmit data, and a value of 0x10 indicates that SCIF.SCFTDR is full of transmit data

Invalid

0x00

Yes

Reserved

0 (should only be written with 0)

Table 128: SCIF.SCFDR

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Register descriptions 293

9.2.11 Serial port register (SCIF.SCSPTR)

SCIF.SCSPTR

is a 16-bit read/write register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins.

Input data can be read from the RXD pin, output data written to the TXD pin, and breaks in serial transmission and reception controlled by means of bits 1 and 0.

Data can be read from, and output data written to, the CTS pin by means of bits 5 and 4. Data can be read from, and output data written to, the RTS pin by means of bits 6 and 7.

SCIF.SCSPTR

can be read or written to at any time.

All SCIF.SCSPTR

bits except bits 6, 4, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, and 0 is undefined. SCIF.SCSPTR

is not initialized in standby mode or in the module standby state.

Field

SPB2DT

SPB2IO

SCIF.SCSPTR

0x20

Bits

[0]

Operation

Read

Write

Hard reset

[1]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis

Serial port break data

Type

Specifies the serial port RxD pin input data and TxD pin output data

See Bit 0: serial port break data (SPB2DT) on page 298

Returns current value

Updates current value

Undefined

No Serial port break I/O RW

Specifies the serial port TxD pin output condition

See Bit 1: serial port break I/O (SPB2IO) on page 298 .

Returns current value

Updates current value

Table 129: SCIF.SCSPTR

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Register descriptions

Field

SCKDT

SCKIO

CTSDT

CTSIO

SCIF.SCSPTR

0x20

Bits Size Volatile

[2]

Operation

Read

Write

Hard reset

[3]

Operation

Read

Write

Hard reset

[4]

Operation

Read

Write

Hard reset

[5]

Operation

Read

Write

Hard reset

Synopsis

Serial port clock port data (SCKDT)

Type

Specifies the I/O data for the SCK pin serial port

See Bit 2: serial port clock port data (SCKDT) on page 297

Returns current value

Updates current value

Yes Serial port clock port I/O

Sets the I/O for the SCK pin serial port

See Bit 3: serial port clock port data (SCKIO) on page 297

Returns current value

Updates current value

No Serial port CTS port data RW

Specifies the serial port CTS pin input/output data

See Bit 4: serial port CTS port data (CTSDT) on page 297 .

Returns current value

Updates current value

Undefined

No Serial port CTS port I/O RW

Specifies the serial port CTS pin input/output condition

See Bit 5: serial port CTS port I/O (CTSIO) on page 296

Returns current value

Updates current value

Table 129: SCIF.SCSPTR

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Register descriptions

Field

RTSDT

RTSIO

SCIF.SCSPTR

0x20

Bits

[6]

Operation

Read

Write

Hard reset

[7]

Operation

Read

Write

Hard reset

[8:15]

Operation

Read

Write

Hard reset

Size Volatile

Synopsis

Serial port RTS port data

Type

Specifies the serial port RTS pin input/output data

See Bit 6: serial port RTS port data (RTSDT) on page 296

Returns current value

Updates current value

Undefined

No Serial port RTS port I/O RW

Specifies the serial port RTS pin input/output condition

See Bit 7: serial port RTS port I/O (RTSIO) on page 296 .

Returns current value

Updates current value

Yes

Reserved

0x00

Reserved

0 (should only be written with 0)

Table 129: SCIF.SCSPTR

Bits 15 to 8: reserved

Bits 15 to 8 are always read as 0, and should only be written with 0.

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Register descriptions

Bit 7: serial port RTS port I/O (RTSIO)

Bit 7 specifies the serial port RTS pin input/output condition. When the RTS pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the

MCE bit in SCIF.SCFCR

should be cleared to 0.

Bit 7: RTSIO Description

RTSDT bit value is not output to RTS pin (initial value)

RTSDT bit value is output to RTS pin

Bit 6: serial port RTS port data (RTSDT)

Bit 6 specifies the serial port RTS pin input/output data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for details). In output mode, the RTSDT bit value is output to the RTS pin. The RTS pin value is read from the

RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined.

Bit 6: RTSDT

Description

Input/output data is low level

Input/output data is high level

Bit 5: serial port CTS port I/O (CTSIO)

Bit 5 specifies the serial port CTS pin input/output condition. When the CTS pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the

MCE bit in SCIF.SCFCR

should be cleared to 0.

Bit 5: CTSIO

Description

CTSDT bit value is not output to CTS pin

(initial value)

CTSDT bit value is output to CTS pin

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Register descriptions 297

Bit 4: serial port CTS port data (CTSDT)

Bit 4 specifies the serial port CTS pin input/output data. Input or output is specified by the CTSIO bit (see the description of bit 5, CTSIO, for details). In output mode, the CTSDT bit value is output to the CTS pin. The CTS pin value is read from the

CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined.

Bit 4: CTSDT

Description

Input/output data is low level

Input/output data is high level

Bit 3: serial port clock port data (SCKIO)

Bit 3 sets the I/O for the SCK pin serial port. To actually set the SCK pin as the port output pin and output the value set in the SCKDT bit, set the CKE1 and CKE0 bits of the SCSCR register to 0.

Bit 3: SCKIO

Description

Shows that the value of the SCKDT bit is not output to the SCK pin (initial value)

Shows that the value of the SCKDT bit is output to the

SCK pin.

Bit 2: serial port clock port data (SCKDT)

Bit 2 specifies the I/O data for the SCK pin serial port. The SCKIO bit specifies input or output (see bit 3: SCKIO for details). When set for output, the value of the

SCKDT bit is output to the SCK pin. Regardless of the value of the SCKIO bit, the value of the SCK pin is fetched from the SCKDT bit. The initial value after a power-on reset or manual reset is undefined.

Bit 2: SCKDT

Description

Shows input/output data is low level

Shows input/output data is high level

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Register descriptions

Bit 1: serial port break I/O (SPB2IO)

Bit 1 specifies the serial port TXD pin output condition. When the TXD pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the

TE bit in SCIF.SCSCR

should be cleared to 0.

Bit 1: SPB2IO

Description

SPB2DT bit value is not output to the TxD pin (initial value)

SPB2DT bit value is output to the TxD pin

Bit 0: serial port break data (SPB2DT)

Bit 0 specifies the serial port RXD pin input data and TXD pin output data. The TXD pin output condition is specified by the SPB2IO bit (see the description of bit 1,

SPB2IO, for details). When the TXD pin is designated as an output, the value of the

SPB2DT bit is output to the TXD pin. The RXD pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined.

Bit 0:

SPB2DT

Description

Input/output data is low level

Input/output data is high level

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Register descriptions

SCIF I/O port block diagrams are shown in Figure 34

Figure 37 .

MD8/RTS2

Mode setting register

Reset

RTSIO

SPTRW

Reset

RTSDT

SPTRW

Internal data bus

SCIF

Modem control enable signal*

RTS2 signal

SPTRR

SPTRW: Write to SPTR

SPTRR: Read SPTR

Note: * The RTS2 pin function is designated as modem control by the MCE bit in SCFCR2.

Figure 34: MD8/RTS pin

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Register descriptions

CTS2

Reset

CTSIO

SPTRW

Reset

CTSDT

SPTRW

Internal data bus

SCIF

CTS2 signal

Modem control enable signal*

SPTRR

SPTRW: Write to SPTR

SPTRR: Read SPTR

Note: * The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2.

Figure 35: CTS pin

MD1/TxD2

Reset

SPB2IO

SPTRW

Reset

SPB2DT

SPTRW

Mode setting register

SPTRW: Write to SPTR

Figure 36: MD1/TxD pin

Internal data bus

SCIF

Transmit enable signal

Serial transmit data

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Register descriptions

PRELIMINARY DATA

301

MD2/RxD2

SCIF

Serial receive data Mode setting register

Internal data bus

SPTRR

SPTRR: Read SPTR

Figure 37: MD2/RxD pin

9.2.12 Line status register (SCIF.SCLSR)

SCIF.SCLSR

is a 16-bit register which contains the overrun error flag.

Field

ORER

SCIF.SCLSR

Bits

[0]

Operation

Siz e

Read

Write

Hard reset

Volatile

0X24

Synopsis

Yes Overrun error

Indicates that an overrun error occurred

See Bit 0: overrun error (ORER) on page 302 .

Returns the current value

0: clear the flag

Only 0 can be written

Table 130: SCIF.SCLSR

Type

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Register descriptions

Field

SCIF.SCLSR

0X24

Bits

Siz e

[1:15]

Operation

Read

Write

Hard reset

Volatile Synopsis

Yes

Reserved

Table 130: SCIF.SCLSR

Type

Bits 15 to 1: reserved

Bits 15 to 1 are always read as 0, and should only be written with 0.

Bit 0: overrun error (ORER)

Bit 0 indicates that an overrun error occurred during reception, causing abnormal termination.

Bit 0: ORER Description

0 Reception in progress, or reception has ended normally

(initial value)

Clearing conditions are:

Power-on reset or manual reset

When 0 is written to ORER after reading ORER = 1

An overrun error occurred during reception

Setting condition is:

When the next serial reception is completed while the receive FIFO is full

A. The ORER flag is not affected and retains its previous state when the RE bit in SCIF.SCSCR is cleared to 0.

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Operation 303

B. The receive data prior to the overrun error is retained in SCIF.SCFRDR

, and the data received subsequently is lost. Serial reception cannot be continued while the

ORER flag is set to 1.

9.3 Operation

9.3.1 Overview

The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character.

16 stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed.

RTS and CTS signals are also provided as modem control signals. The transmission format is selected using the serial mode register ( SCIF.SCSMR

), as shown in

Table 122 . The SCIF clock source is determined by the CKE1 bit in the serial control

), as shown in Table 131 . SCIF communication provides the

following features:

• choice of 7 or 8 bits for data length,

• choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length),

• detection of framing errors, parity errors, RECEIVE-FIFO-DATA-FULL state, overrun errors, receive data ready state, and breaks, during reception,

• indication of the number of data bytes stored in the transmit and receive FIFO registers,

• choice of internal or external clock as SCIF clock source,

when internal clock is selected the SCIF operates on the baud rate generator clock,

when external clock is selected a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used)

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Operation

SCIF.SCSMR settings

Bit

CHR

Bit 5:

Bit 3:

STO

0 0

Mode

Asynchronous mode

1 -

SCIF transfer format

Data length

Multiprocessor bit

Parity bit

Stop bit length

No No 1 bit

8-bit data

7-bit data

Yes

2 bits

1 bit

2 bits

1 bit

2 bits

1 bit

2 bits

Bit 1:

CKE1

SCIF.SCSCR setting

Bit 0:

CKE0

Mode

Asynchronous mode

SCIF transmit/receive clock

Clock source

SCK pin function

Internal SCIF does not use SCK pin

Internal Output clock with frequency of

16 times the bit rate.

Asynchronous mode

External

Inputs clock with frequency of

16 times the bit rate

Inputs clock with frequency of

16 times the bit rate

Table 131: SCIF.SCSCR settings for SCIF clock source selection

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0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

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Operation 305

9.3.2 Serial operation

Data transfer format

Table 132 shows the data transfer formats that can be used. Any of the 8 transfer

formats can be selected according to the SCIF.SCSMR

settings. In

Table 132

S = start bit, STOP = stop bit and P = parity bit.

SCIF.SCSMR settings

CHR PE STOP

Serial transfer format and frame length

1 2 3 4 5 6 7 8 9 10 11

0 0 0 S 8-bit data STOP

S 8-bit data

STOP STOP

P STOP

S 8-bit data

S 7-bit data

P STOP

STOP

STOP STOP S 7-bit data

S 7-bit data P STOP

S 7-bit data

Table 132: Serial transfer formats

P STOP STOP

STOP

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306 Operation

Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCIF’s serial clock, according to the setting of the CKE1 bit in SCIF.SCSCR

. For details of SCIF clock source selection, see

Table 131 .

When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.

Data transfer operations

SCIF initialization

Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCIF.SCSCR

to 0, then initialize the SCIF as described below.

When the transfer format is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0,

SCIF.SCTSR

is initialized.

Note: clearing the TE and RE bits to 0 does not change the contents of SCIF.SCFSR

SCIF.SCFTDR

, or SCIF.SCFRDR

The TE bit should be cleared to 0 after all transmit data has been sent and the

TEND flag in SCIF.SCFSR

has been set. TEND can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. Before setting TE again to start transmission, the TFRST bit in

SCIF.SCFCR

should first be set to 1 to reset SCIF.SCFTDR

When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case.

Figure 38 shows a sample SCIF initialization flowchart.

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Operation

Initialization

Clear TE and RE bits in SCSCR2 to 0

Set TFRST and RFRST bits in SCFCR2 to 1

Set CKE1 bit in SCSCR2

(leaving TE and RE bits cleared to 0)

Set data transfer format in SCSMR2

Set value in SCBRR2

Wait

1-bit interval elapsed?

Yes

Set RTRG1–0, TTRG1–0, and MCE bits in SCFCR2

Clear TFRST and RFRST bits to 0

Set TE and RE bits in SCSCR2 to 1, and set RIE, TIE, and REIE bits

End

1. Set the clock selection in SCSCR2.

Be sure to clear bits RIE and TIE, and bits TE and RE, to 0.

2. Set the data transfer format in

SCSMR2.

3. Write a value corresponding to the bit rate into SCBRR2. (Not necessary if an external clock is used.)

4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR2 to 1. Also set the RIE, REIE, and

TIE bits.

Setting the TE and RE bits enables the TxD2 and RxD2 pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit.

Figure 38: Sample SCIF initialization flowchart

307

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Operation

Serial data transmission

Figure 39 shows a sample flowchart for serial transmission.

Use the following procedure for serial data transmission after enabling the SCIF for transmission.

Start of transmission

Read TDFE flag in SCFSR2

TDFE = 1?

Yes

Write transmit data (16 - transmit trigger set number) to SCFTDR2, read 1 from TDFE flag and TEND flag in SCFSR2, then clear to 0

All data transmitted?

Yes

Read TEND flag in SCFSR2

TEND = 1?

Yes

Break output?

Yes

Clear SPB2DT to 0 and set SPB2IO to 1

Clear TE bit in SCSCR2 to 0

End of transmission

Figure 39: Sample serial transmission flowchart

1. SCIF status check and transmit data write:

Read SCFSR2 and check that the

TDFE flag is set to 1, then write transmit data to SCFTDR2, read 1 from the TDFE and TEND flags, then clear these flags to 0.

The number of transmit data bytes that can be written is 16 - (transmit trigger set number).

2. Serial transmission continuation procedure:

To continue serial transmission, read

1 from the TDFE flag to confirm that writing is possible, then write data to

SCFTDR2, and then clear the TDFE flag to 0.

3. Break output at the end of serial transmission:

To output a break in serial transmission, clear the SPB2DT bit to

0 and set the SPB2IO bit to 1 in

SCSPTR2, then clear the TE bit in

SCSCR2 to 0.

In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR2 indicated by the upper 8 bits of

SCFDR2.

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Operation 309

In serial transmission, the SCIF operates as described below.

1 When data is written into SCIF.SCFTDR

, the SCIF transfers the data from

SCIF.SCFTDR

to SCIF.SCTSR

and starts transmitting. Confirm that the TDFE flag in the serial status register ( SCIF.SCFSR

) is set to 1 before writing transmit data to SCIF.SCFTDR

. The number of data bytes that can be written is at least

16 (transmit trigger setting).

2 When data is transferred from SCIF.SCFTDR

to SCIF.SCTSR

and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCIF.SCFTDR

. When the number of transmit data bytes in

SCIF.SCFTDR

falls to or below the transmit trigger number set in the FIFO control register ( SCIF.SCFCR

), the TDFE flag is set. If the TIE bit in

SCIF.SCSCR

is set to 1 at this time, a TRANSMIT-FIFO-DATA-EMPTY interrupt

(TXI) request is generated. The serial transmit data is sent from the TXD pin in the following order:

2.1 start bit: one 0-bit is output,

2.2 transmit data: 8-bit or 7-bit data is output in LSB first order,

2.3 parity bit: 1 parity bit (even or odd parity) is output (a format in which a parity bit is not output can also be selected),

2.4 stop bit(s): 1 or two 1-bits (stop bits) are output,

2.5 mark state: 1 is output continuously until the start bit that starts the next transmission is sent.

3 The SCIF checks the SCIF.SCFTDR

transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCIF.SCFTDR

SCIF.SCTSR

, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCIF.SCFSR

is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output.

Figure 40 shows an example of the operation for transmission in asynchronous

mode.

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Operation

Serial data

Start bit

0 D0 D1

Data Parity bit

Stop bit

D7 0/1 1

Start bit

0 D0 D1

Data Parity bit

D7 0/1

Stop bit

Idle state

(mark state)

TDFE

TEND

TXI interrupt request

Data written to SCFTDR2 and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler

TXI interrupt request

One frame

Figure 40: Example of transmit operation (example with 8-bit data, parity, 1 stop bit)

When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark state after transmission of 1 frame. When CTS is set to 0, the next transmit data is output starting from the start bit.

Figure 41 shows

an example of the operation when modem control is used.

Serial data

TxD2

Start bit

0 D0 D1

Parity bit

Stop bit

D7 0/1 1

Start bit

0 D0 D1 D7 0/1

CTS2

Drive high before stop bit

Figure 41: Example of operation using modem control (CTS)

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Operation 311

Serial data reception

Figure 42 and

Figure 43 show a sample flowchart for serial reception. Use the

following procedure for serial data reception after enabling the SCIF for reception.

Start of reception

Read ER, DR, BRK flags in

SCFSR2 and ORER flag in SCLSR2

ER or DR or BRK or ORER

= 1?

Read RDF flag in SCFSR2

RDF = 1?

Yes

Read receive data in

SCFRDR2, and clear RDF flag in SCFSR2 to 0

All data received?

Yes

Clear RE bit in SCSCR2 to 0

End of reception

Yes

Error handling

1. Receive error handling and break detection: Read the DR,

ER, and BRK flags in

SCFSR2, and the ORER flag in SCLSR2, to identify any error, perform the appropriate error handling, then clear the

DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD2 pin.

2. SCIF status check and receive data read : Read SCFSR2 and check that RDF = 1, then read the receive data in SCFRDR2, read 1 from the RDF flag, and then clear the RDF flag to 0.

The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt.

3. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from

SCFRDR2, read 1 from the

RDF flag, then clear the RDF flag to 0. The number of receive data bytes in

SCFRDR2 can be ascertained by reading the lower bits of

SCFDR2.

Figure 42: Sample serial reception flowchart (1)

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Operation

Error handling

ORER = 1?

Yes

Overrun error handling

ER = 1?

Yes

Receive error handling

BRK = 1?

Yes

Break handling

1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in

SCFSR2.

2. When a break signal is received, receive data is not transferred to

SCFRDR2 while the BRK flag is set.

However, note that the last data in

SCFRDR2 is H'00 (the break data in which a framing error occurred is stored).

DR = 1?

Yes

Read receive data in SCFRDR2

Clear DR, ER, BRK flags in SCFSR2, and ORER flag in SCLSR2, to 0

End

Figure 43: Sample serial reception flowchart (2)

In serial reception, the SCIF operates as described below.

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Operation 313

1 The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception.

2 The received data is stored in SCIF.SCRSR

in LSB to MSB order.

3 The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks:

3.1 stop bit check: the SCIF checks whether the stop bit is 1 (if there are 2 stop bits, only the first is checked),

3.2 the SCIF checks whether receive data can be transferred from the receive shift register ( SCIF.SCRSR

) to SCIF.SCFRDR

3.3 overrun error check: the SCIF checks that the ORER flag is 0, indicating that no overrun error has occurred,

3.4 break check: the SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCIF.SCFRDR

Note: Reception continues when a receive error occurs.

4 If the RIE bit in SCIF.SCSCR

is set to 1 when the RDF or DR flag changes to 1, a

RECEIVE-FIFO-DATA-FULL interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCIF.SCSCR

is set to 1 when the ER flag changes to 1, a receive error interrupt (ERI) request is generated. If the RIE bit or REIE bit in

SCIF.SCSCR

is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated.

Figure 44 shows an example of the operation for reception.

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Operation

Serial data

Start bit

0 D0 D1

Data Parity bit

Stop bit

D7 0/1 1

Start bit

0 D0 D1

Data Parity bit

D7 0/1

Stop bit

0 0/1

RDF

FER

One frame

RXI interrupt request

Data read and RDF flag read as 1 then cleared to

0 by RXI interrupt handler

ERI interrupt request generated by receive error

Figure 44: Example of SCIF receive operation (example with 8-bit data, parity, 1 stop bit)

5 When modem control is enabled, the RTS signal is output when SCIF.SCFRDR

is empty. When RTS is 0, reception is possible. When RTS is 1, this indicates that

SCIF.SCFRDR

contains 15 or more bytes of data, and there is no free space, reception is not possible.

Figure 45 shows an example of the operation when

modem control is used.

Serial data

RxD2

Start bit

0 D0 D1 D2

Parity bit

Stop bit

D7 0/1 1

Start bit

RTS2

Figure 45: Example of operation using modem control (RTS)

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SCIF interrupt sources and the DMAC 315

9.4 SCIF interrupt sources and the DMAC

The SCIF has 4 interrupt sources:

• TRANSMIT-FIFO-DATA-EMPTY interrupt ( TXI ) request,

• receive error interrupt ( ERI ) request,

• RECEIVE-FIFO-DATA-FULL interrupt ( RXI ) request,

• BREAK interrupt ( BRI ) request.

Table 133 shows the interrupt sources and their order of priority. The interrupt

sources are enabled or disabled by means of the TIE, RIE, and REIE bits in

SCIF.SCSCR

. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources.

When transmission and reception is carried out using the DMAC, output of interrupt requests to the interrupt controller can be inhibited by clearing the RIE bit in SCIF.SCSCR

to 0. By setting the REIE bit to 1 while the RIE bit is cleared to

0, it is possible to output ERI and BRI interrupt requests, but not RXI interrupt requests.

When the TDFE flag in the serial status register ( SCIF.SCFSR

) is set to 1, a TXI request is generated separately from the interrupt request. A TXI request can activate the DMAC to perform data transfer.

When the RDF flag or DR flag in SCIF.SCFSR

is set to 1, a RXI request is generated separately from the interrupt request. A RXI request can activate the DMAC to perform data transfer.

When using the DMAC for transmission and reception, set and enable the DMAC before making the SCIF settings. See the specification of the DMA controller module for details of the DMAC setting procedure.

When the BRK flag in SCIF.SCFSR

or the ORER flag in the line status register

( SCIF.SCLSR

) is set to 1, a BRI request is generated. The TXI indicates that transmit data can be written, and the RXI indicates that there is receive data in

SCIF.SCFRDR

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Usage notes

Interrupt source

ERI

RXI

BRI

TXI

Description

DMAC activation

Priority on reset release

Interrupt initiated by receive-error flag (ER)

Interrupt initiated by receive-FIFO-data-full flag

(RDF) or receive data ready flag (DR)

Interrupt initiated by break flag (BRK) or overrun error flag (ORER)

Interrupt initiated by

TRANSMIT-FIFO-DATA-EMPTY flag (TDFE)

Not possible High

Possible

Not possible

Possible Low

Table 133: SCIF interrupt sources

See the Exceptions chapter of the CPU Architecture manual , for priorities and the relationship with non-SCIF interrupts.

Note the following when using the SCIF.

9.5.1 SCIF.SCFTDR writing and the TDFE flag

The TDFE flag in the serial status register ( SCIF.SCFSR

) is set when the number of transmit data bytes written in the transmit FIFO data register ( SCIF.SCFTDR

) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the

FIFO control register ( SCIF.SCFCR

). After TDFE is set, transmit data up to the number of empty bytes in SCIF.SCFTDR

can be written, allowing efficient continuous transmission.

However, if the number of data bytes written in SCIF.SCFTDR

is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when

SCIF.SCFTDR

contains more than the transmit trigger number of transmit data bytes.

The number of transmit data bytes in SCIF.SCFTDR

can be found from the upper 8 bits of the FIFO data count register ( SCIF.SCFDR

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9.5.2 SCIF.SCFRDR reading and the RDF flag

The RDF flag in the serial status register ( SCIF.SCFSR

) is set when the number of receive data bytes in the receive FIFO data register ( SCIF.SCFRDR

) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register ( SCIF.SCFCR

). After RDF is set, receive data equivalent to the trigger number can be read from SCIF.SCFRDR

, allowing efficient continuous reception.

However, if the number of data bytes in SCIF.SCFRDR

is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read.

The number of receive data bytes in SCIF.SCFRDR

can be found from the lower 8 bits of the FIFO data count register ( SCIF.SCFDR

9.5.3 Break detection and processing

BREAK signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the BREAK state the input from the RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set.

Although the SCIF stops transferring receive data to SCIF.SCFRDR

after receiving a BREAK , the receive operation continues.

9.5.4 Sending a break signal

The input/output condition and level of the TXD pin are determined by bits SPB2IO and SPB2DT in the serial port register ( SCIF.SCSPTR

). This feature can be used to send a BREAK signal.

After the serial transmitter is initialized, the TXD pin function is not selected and the value of the SPB2DT bit substitutes for the mark state until the TE bit is set to

1 (that is transmission is enabled). The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) beforehand.

To send a BREAK signal during serial transmission, clear the SPB2DT bit to 0

(designating low level), then clear the TE bit to 0 (halting transmission). When the

TE bit is cleared to 0, the transmitter is initialized, regardless of its current state, and 0 is output from the TXD pin.

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318 Usage notes

9.5.5 Receive data sampling timing and receive margin

The SCIF operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the 8th base

clock pulse. The timing is shown in Figure 46 .

Figure 46: Receive data sampling timing in asynchronous mode

The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).

............................................................................................................(1)

M = Receive margin (%)

N = Ratio of clock frequency to bit rate (N = 16)

D = Clock duty cycle (D = 0 to 1.0)

L = Frame length (L = 9 to 12)

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F = Absolute deviation of clock frequency

From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).

When D = 0.5 and F = 0:

M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ....................................................(2)

This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

9.5.6 SCK/MRESET

As the manual reset pin is multiplexed with the SCK pin, a manual reset must not be executed while the SCIF is operating in external clock mode.

9.5.7 When using the DMAC

When using the DMAC for transmission and reception, inhibit output of RXI and TXI requests to the interrupt controller. If interrupt request output is enabled, interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the interrupt handler.

9.5.8 Serial ports

Note: when the SCIF pin value is read using a serial port, the value read will be the value

2 peripheral clock cycles earlier.

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User break controller

(UBC)

PRELIMINARY DATA

10.1 Overview

The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU. This function makes it easy to design an effective self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator.

10.1.1 Features

The UBC has the features described below.

• Two break channels (A and B): user break interrupts can be generated on independent conditions for channels A and B, or on sequential conditions

(sequential break setting: channel A then channel B).

• Five break compare conditions:

address (selection of 32-bit virtual address and ASID for comparison),

data: channel B only, 32-bit mask capability,

bus cycle: instruction access or operand access,

read/write,

operand size: byte, word, longword, quadword.

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Overview

• Address comparison has the following options:

all bits compared,

lower 10 bits masked,

lower 12 bits masked,

lower 16 bits masked,

lower 20 bits masked,

all bits masked.

• ASID comparison has the following options:

all bits compared,

all bits masked.

• An instruction access cycle break can be effected before or after the instruction is executed.

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Overview

10.1.2 Block diagram

Figure 47 shows a block diagram of the UBC.

Access control

Address bus

Channel A

Access comparator

Address comparator

BBRA

BARA

BASRA

BAMRA

Channel B

Access comparator

Address comparator

BBRB

BARB

BASRB

BAMRB

Data comparator

BDRB

BDMRB

BBRA: Break bus cycle register A

BARA: Break address register A

BASRA: Break ASID register A

BAMRA: Break address mask register A

BBRB: Break bus cycle register B

BARB: Break address register B

BASRB: Break ASID register B

BAMRB: Break address mask register B

BDRB: Break data register B

BDMRB: Break data mask register B

BRCR: Break control register

Control BRCR

User break trap request

Figure 47: Block diagram of user break controller

Data bus

323

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324 Register overview

10.2 Register overview

Table 134 shows a summary of the UBC registers.

Address offset

Register name

Description Type

Access size

P4 Area

UBC.BARA

Break address register A,

see Section 10.3.2:

Break address register A

(UBC.BARA) on page 328

UBC.BAMRA

Break address mask register A,

see Section 10.3.4:

Break address mask register A

(UBC.BAMRA) on page 329

UBC.BBRA

RW Break bus cycle register A,

see Section 10.3.5:

Break bus cycle register A

(UBC.BBRA) on page 331

UBC.BASRA

Break ASID register A,

see Section 10.3.3:

Break ASID register A

(UBC.BASRA) on page 329

0xFF200000

0xFF200004

0xFF200008

0xFF000014

0x1F200000

0x1F200004

0x1F200008

0x1F000014

Table 134: UBC registers

Initial value

Undefined

0x0000

Undefined

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Register overview 325

Address offset

Register name

Description Type

Access size

0xFF20000

Area

1F20000C UBC.BARB

UBC.BAMRB

Break address mask register B,

see Section 10.3.8:

Break address mask register B

(UBC.BAMRB) on page 333

UBC.BBRB

Break address register B,

see Section 10.3.6:

Break address register B

(UBC.BARB) on page 333

UBC.BASRB

Break bus cycle register B, see

Section 10.3.11:

Break bus cycle register B

(UBC.BBRB) on page 336

Break ASID register B,

see Section 10.3.7:

Break ASID register B

(UBC.BASRB) on page 333

UBC.BDRB

Break data register

see Section 10.3.9:

Break data register

B (UBC.BDRB) on page 334

0xFF200010

0xFF200014

0xFF000018

0xFF200018

0x1F200010

0x1F200014

0x1F000018

0x1F200018

Table 134: UBC registers

Initial value

Undefined

0x0000

Undefined

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326 Register overview

Register name

Description

UBC.BDMRB

Break data mask register B, see

Section 10.3.10:

Break data mask register B

(UBC.BDMRB) on page 335

UBC.BRCR

Break control register, see

Section 10.3.12:

Break control register

(UBC.BRCR) on page 337

Type

0xFF20001

Address offset

Access size

Area

0x1F20001C 32

Initial value

Undefined

0xFF200020 0x1F200020 16

0x0000

Table 134: UBC registers

A. Some bits are not initialized. See

Section 10.3.12: Break control register (UBC.BRCR) on page 337

, for details.

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Register descriptions 327

10.3 Register descriptions

10.3.1 Access to UBC control registers

The access size must be the same as the control register size. If the sizes are different, a write will not be effected in a UBC register write operation, and a read operation will return an undefined value. UBC control register contents cannot be transferred to a floating-point register using a floating-point memory load instruction.

When a UBC control register is updated, use either of the following methods to make the updated value valid.

• Execute an RTE instruction after the memory store instruction that updated the register. The updated value will be valid from the RTE instruction jump destination onward.

• Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the ST40 executes 2 instructions in parallel and a minimum of 0.5 state is required for execution of 1 instruction, 11 instructions must be inserted. The updated value will be valid from the 6th state onward.

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10.3.2 Break address register A (UBC.BARA)

Bit 31 30 29 28 27 26 25 24

Initial value -

Type

BAA31 BAA30 BAA29 BAA28

BAA2

BAA26

BAA2

Bit 23 22 21 20 19

Initial value -

Type

BAA23 BAA22 BAA21 BAA20

BAA1

18 17 16

BAA18

BAA1

Bit 15 14 13 12 11 10 9 8

BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8

Initial value -

Type RW

Bit 7 6 5 4 3 2 1 0

BAA7

Initial value -

Type RW

BAA6

BAA5

BAA4

BAA3

BAA2 BAA1 BAA0

Break address register A ( UBC.BARA

) is a 32-bit read/write register that specifies the virtual address used in the channel A break conditions. UBC.BARA

is not initialized by a power-on reset or manual reset.

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Register descriptions

Bits 31 to 0: break address A31 to A0 (BAA31 to BAA0)

These bits hold the virtual address (bits 31 to 0) used in the channel A break conditions.

10.3.3 Break ASID register A (UBC.BASRA)

329

Bit 7 6 5 4 3 2 1 0

BASA7 BASA6 BASA5 BASA4 BASA3 BASA2 BASA1 BASA0

Initial value -

Type RW

Break ASID register A ( UBC.BASRA

) is an 8-bit read/write register that specifies the ASID used in the channel A break conditions. UBC.BASRA

is not initialized by a power-on reset or manual reset.

Bits 7 to 0: break ASID A7 to A0 (BASA7 to BASA0)

These bits hold the ASID (bits 7 to 0) used in the channel A break conditions.

10.3.4 Break address mask register A (UBC.BAMRA)

Bit 7

Initial value 0

Type RO

3 2 1 0

BAMA2 BASMA BAMA1 BAMA0

Break address mask register A ( UBC.BAMRA

) is an 8-bit read/write register that specifies which bits are to be masked in the break ASID set in UBC.BASRA

and the break address set in UBC.BARA

. UBC.BAMRA

is not initialized by a power-on reset or manual reset.

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Register descriptions

Bits 7 to 4: reserved

These bits are always read as 0, and should only be written with 0.

Bit 2: break ASID mask A (BASMA):

Specifies whether all bits of the channel A break ASID (BASA7 to BASA0) are to be masked.

Bit 2: BASMA Description

All UBC.BASRA bits are included in break conditions

No UBC.BASRA bits are included in break conditions

Bits 3, 1, and 0: break address mask A2 to A0 (BAMA2 to BAMA0):

These bits specify which bits of the channel A break address (BAA31 to BAA0) set in

UBC.BARA

are to be masked.

Bit 3: BAMA2 Bit 1: BAMA1 Bit 0: BAMA0

0 0 0

Don’t care

Description

All UBC.BARA bits are included in break conditions

Lower 10 bits of UBC.BARA are masked, and not included in break conditions

Lower 12 bits of UBC.BARA are masked, and not included in break conditions

All UBC.BARA bits are masked, and not included in break conditions

Lower 16 bits of UBC.BARA are masked, and not included in break conditions

Lower 20 bits of UBC.BARA are masked, and not included in break conditions

Reserved (cannot be set)

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10.3.5 Break bus cycle register A (UBC.BBRA)

Bit

Initial value

Type

RO RO

331

Bit

Initial value

Type

SZA2

IDA1

IDA0

3 2

RWA1

RWA0

SZA1

SZA0

RW RW RW RW RW RW RW

Break bus cycle register A ( UBC.BBRA

) is a 16-bit read/write register that sets 3 conditions:

• instruction access/operand access,

• read/write,

• operand size from among the channel A break conditions.

UBC.BBRA

is initialized to 0x0000 by a power-on reset or manual reset. It retains its value in standby mode.

Bits 15 to 7: reserved

These bits are always read as 0, and should only be written with 0.

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Register descriptions

Bits 5 and 4: instruction access/operand access select A (IDA1, IDA0):

These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions.

Bit 5: IDA1

1 0

Bit 4: IDA0 Description

Condition comparison is not performed (Initial value)

Instruction access cycle is used as break condition

Operand access cycle is used as break condition

Instruction access cycle or operand access cycle is used as break condition

Bits 3 and 2: read/write select A (RWA1, RWA0)

These bits specify whether a read cycle or write cycle is used as the bus cycle in the channel A break conditions.

Bit 3: RWA1

1 0

Bit 2: RWA0 Description

Condition comparison is not performed (Initial value)

Read cycle is used as break condition

Write cycle is used as break condition

Read cycle or write cycle is used as break condition

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Register descriptions 333

Bits 6, 1, and 0: operand size select A (SZA2 to SZA0)

These bits select the operand size of the bus cycle used as a channel A break condition.

Bit 6:

SZA2

Bit 1:

SZA1

Bit 0:

SZA0

Description

Operand size is not included in break conditions

(initial value)

Byte access is used as break condition

Word access is used as break condition

Longword access is used as break condition

Quadword access is used as break condition

Reserved (cannot be set)

10.3.6 Break address register B (UBC.BARB)

UBC.BARB

is the channel B break address register. The bit configuration is the same as for UBC.BARA.

10.3.7 Break ASID register B (UBC.BASRB)

UBC.BASRB

is the channel B break ASID register. The bit configuration is the same as for UBC.BASRA.

10.3.8 Break address mask register B (UBC.BAMRB)

UBC.BAMRB

is the channel B break address mask register. The bit configuration is the same as for UBC.BAMRA

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10.3.9 Break data register B (UBC.BDRB)

Bit 31 30 29 28 27 26 25 24

BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24

Initial value

Type RW RW RW RW RW RW RW RW

Bit

Initial value

23 22 21 20 19 18 17 16

BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16

RW RW RW RW RW RW RW RW

Initial value

Bit 15 14 13 12 11 10 9 8

BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9

BDB8

RW RW RW RW RW RW RW RW

Bit 7

BDB7

BDB6

BDB5

4 3

BDB4

BDB3

BDB2

BDB1

BDB0

Initial value

RW RW RW RW RW RW RW RW RW

Break data register B ( UBC.BDRB

) is a 32-bit read/write register that specifies the data (bits 31 to 0) to be used in the channel B break conditions. UBC.BDRB

is not initialized by a power-on reset or manual reset.

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Register descriptions 335

Bits 31 to 0: break data B31 to B0 (BDB31 to BDB0):

These bits hold the data (bits 31 to 0) to be used in the channel B break conditions.

10.3.10 Break data mask register B (UBC.BDMRB)

Bit 31 30 29 28 27 26 25 24

BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24

Initial value

Type RW RW RW RW RW RW RW RW

Bit 23 22 21 20 19 18 17 16

BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16

Initial value

Type RW RW RW RW RW RW RW RW

Bit 15 14 13 12 11 10 9 8

BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8

Initial value

Type RW RW RW RW RW RW RW RW

Bit 7 6 5 4 3 2 1 0

BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0

Initial value

Type RW RW RW RW RW RW RW RW

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Register descriptions

Break data mask register B ( UBC.BDMRB

) is a 32-bit read/write register that specifies which bits of the break data set in UBC.BDRB

are to be masked.

UBC.BDMRB

is not initialized by a power-on reset or manual reset.

Bits 31 to 0: break data mask B31 to B0 (BDMB31 to BDMB0)

These bits specify whether the corresponding bit of the channel B break data

(BDB31 to BDB0) set in UBC.BDRB

is to be masked.

Bit 31 to 0: BDMBA

Description (where n = 31 to 0)

Channel B break data bit BDB[n] is included in break conditions

Channel B break data bit BDB[n] is masked, and not included in break conditions

Note: when the data bus value is included in the break conditions, the operand size should be specified. When byte size is specified, set the same data in bits 15 to 8 and 7 to 0 of

UBC.BDRB and UBC.BDMRB.

10.3.11 Break bus cycle register B (UBC.BBRB)

UBC.BBRB

is the channel B bus break register. The bit configuration is the same as for UBC.BBRA

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10.3.12 Break control register (UBC.BRCR)

Bit

Initial value

Type

15 14 13

CMFA CMFB

10 9

PCBA

337

Bit

Initial value

Type

7 6 5

DBEB PCBB

SEQ

UBDE

The break control register ( UBC.BRCR

) is a 16-bit read/write register that specifies

1 whether channels A and B are to be used as 2 independent channels or in a sequential condition,

2 whether the break is to be effected before or after instruction execution, the register is to be included in the channel B break conditions, and

4 whether the user break debug function is to be used. UBC.BRCR

also contains condition match flags. The CMFA, CMFB, and UBDE bits in UBC.BRCR

are initialized to 0 by a power-on reset, but retain their value in standby mode. The value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual reset, so these bits should be initialized by software as necessary.

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Register descriptions

Bit 15: condition match flag A (CMFA)

Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.)

Bit 15: CMFA

Description

Channel A break condition is not matched (initial value)

Channel A break condition match has occurred

Bit 14: condition match flag B (CMFB)

Set to 1 when a break condition set for channel B is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.)

Bit 14: CMFB

Description

Channel B break condition is not matched (initial value)

Channel B break condition match has occurred

Bits 13 to 11: reserved

These bits are always read as 0, and should only be written with 0.

Bit 10: instruction access break select A (PCBA)

Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset.

Bit 10: PCBA Description

Channel A PC break is effected before instruction execution

Channel A PC break is effected after instruction execution

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Register descriptions 339

Bits 9 and 8: reserved

These bits are always read as 0, and should only be written with 0.

Bit 7: data break enable B (DBEB)

Specifies whether the data bus condition is to be included in the channel B break conditions. This bit is not initialized by a power-on reset or manual reset.

Bit 7: DBEB Description

Data bus condition is not included in channel B conditions

Data bus condition is included in channel B conditions

Note: when the data bus is included in the break conditions, bits IDB1 to 0 in break bus

cycle register B (UBC.BBRB) should be set to 10 or 11.

Bit 6: PC break select B (PCBB)

Specifies whether a channel B instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset.

Bit 6: PCBB Description

Channel B PC break is effected before instruction execution

Channel B PC break is effected after instruction execution

Bits 5 and 4: reserved

These bits are always read as 0, and should only be written with 0.

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Register descriptions

Bit 3: sequence condition select (SEQ)

Specifies whether the conditions for channels A and B are to be independent or sequential. This bit is not initialized by a power-on reset or manual reset.

Bit 3: SEQ

Description

Channel A and B comparisons are performed as independent conditions

Channel A and B comparisons are performed as sequential conditions (channel A then channel B)

Bits 2 and 1: reserved

These bits are always read as 0, and should only be written with 0.

Bit 0: user break debug enable (UBDE)

Specifies whether the user break debug function (see

Section 10.6: User break debug support function on page 352 ) is to be used.

Bit 0: UBDE Description

User break debug function is not used (initial value)

User break debug function is used

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10.4 Operation

10.4.1 Explanation of terms relating to accesses

An instruction access is an access that obtains an instruction. An operand access is any memory access for the purpose of instruction execution. For example, the access to address PC + dispx2 + 4 in the instruction MOV.W @ (disp, PC), Rn (an access very close to the program counter) is an operand access. The fetching of an instruction from the branch destination when a branch instruction is executed is also an instruction access. As the term “data” is used to distinguish data from an address, the term “operand access” is used in this section.

In the ST40, all operand accesses are treated as either read accesses or write accesses. The following instructions require special attention:

• PREF, OCBP, and OCBWB instructions: treated as read accesses,

• MOVCA and OCBI instructions: treated as write accesses,

• TAS instruction: treated as 1 read access and 1 write access.

The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no access data.

The ST40 handles all operand accesses as having a data size. The data size can be byte, word, longword, or quadword. The operand data size for the PREF, OCBP,

OCBWB, MOVCA, and OCBI instructions is treated as longword.

10.4.2 Explanation of terms relating to instruction intervals

In this section, “1 (2, 3,...) instruction(s) after...”, as a measure of the distance between 2 instructions, is defined as follows. A branch is counted as an interval of 2 instructions.

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Example of sequence of instructions with no branch

100 Instruction A (0 instructions after instruction A)

102 Instruction B (1 instruction after instruction A)

104 Instruction [c](2 instructions after instruction A)

106 Instruction [d](3 instructions after instruction A)

Example of sequence of instructions with a branch

100 Instruction A:BT/S L200 (0 instructions after instruction

102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B)

L200 200 Instruction [c](3 instructions after instruction A, 2 instructions after instruction B)

202 Instruction [d](4 instructions after instruction A, 3 instructions after instruction B)

The example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4.

10.4.3 User break operation sequence

The sequence of operations from setting of break conditions to user break exception handling is described below.

1 Specify pre- or post-execution breaking in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel A and channel

B break conditions, in the break control register ( UBC.BRCR

2 Set the break addresses in the break address registers for each channel

( UBC.BARA

, UBC.BARB

), the ASIDs corresponding to the break space in the break ASID registers ( UBC.BASRA

, UBC.BASRB

), and the address and ASID masking methods in the break address mask registers ( UBC.BAMRA

UBC.BAMRB

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3 If the data bus value is to be included in the break conditions, also set the break data in the break data register ( UBC.BDRB

) and the data mask in the break data mask register ( UBC.BDMRB

4 Set the break bus conditions in the break bus cycle registers ( UBC.BBRA

UBC.BBRB

5 If either of the instruction access/operand access select group (IDA[n] and

IDB[n] bits) or read/write select group (RWA[n] and RWB[n] bits) of the

UBC.BBRA OR UBC.BBRB registers are set to 00, a user break interrupt is not generated on the corresponding channel. the and UBC.BBRB

settings after all other break-related register settings have been completed. If breaks are enabled with UBC.BBRA/

UBC.BBRB

while the break address, data, or mask register, or the break control register is in the initial state after a reset, a break may be generated inadvertently.

7 The operation when a break condition is satisfied depends on the BL bit (in the

CPU’s SR register). When the BL bit is 0, exception handling is started and the condition match flag (CMFA, CMFB) for the respective channel is set for the matched condition. When the BL bit is 1, the condition match flag (CMFA,

CMFB) for the respective channel is set for the matched condition but exception handling is not started.

The condition match flags (CMFA, CMFB) are set by a branch condition match, but are not reset. Therefore, a memory store instruction should be used on the

UBC.BRCR

Section 10.4.6: Condition match flag setting on page 346

, for the exact setting conditions for the condition match flags.

8 When sequential condition mode has been selected, and the channel B condition is matched after the channel A condition has been matched, a break is effected at the instruction at which the channel B condition was matched. See

Section 10.4.8: Contiguous A and B settings for sequential conditions on page 348 , for the operation when the channel A condition match and channel B

condition match occur close together. With sequential conditions, only the channel B condition match flag is set. When sequential condition mode has been selected, if it is wished to clear the channel A match when the channel A condition has been matched but the channel B condition has not yet been matched, this can be done by writing 0 to the SEQ bit in the UBC.BRCR

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344 Operation

10.4.4 Instruction access cycle break

1 When an instruction access, read or word setting is made in the break bus cycle register ( UBC.BBRA, UBC.BBRB

), an instruction access cycle can be used as a break condition. In this case, breaking before or after execution of the relevant instruction can be selected with the PCBA/PCBB bit in the break control register

( UBC.BRCR

). When an instruction access cycle is used as a break condition, clear the LSB of the break address registers ( UBC.BARA

, UBC.BARB

) to 0. A break will not be generated if this bit is set to 1.

2 When a pre-execution break is specified, the break is effected when it is confirmed that the instruction is to be fetched and executed. Therefore, an overrun-fetched instruction (an instruction that is fetched but not executed when a branch or exception occurs) cannot be used in a break. However, if a TLB miss or TLB protection violation exception occurs at the time of the fetch of an instruction subject to a break, the break exception handling is carried out first.

The instruction TLB exception handling is performed when the instruction is re- executed (see Exception Types and Priorities in the ST40 CPU Architecture

Manual ). Also, since a delayed branch instruction and the delay slot instruction are executed as a single instruction, if a pre-execution break is specified for a delay slot instruction, the break will be effected before execution of the delayed branch instruction. However, a pre-execution break cannot be specified for the delay slot instruction for an RTE instruction.

3 With a pre-execution break, the instruction set as a break condition is executed, then a break interrupt is generated before the next instruction is executed.

When a post-execution break is set for a delayed branch instruction, the delay slot is executed and the break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction 2 instructions ahead of the branch instruction (when the branch is not made).

4 When an instruction access cycle is set for channel B, break data register B

( UBC.BDRB

) is ignored in judging whether there is an instruction access match.

Therefore, a break condition specified by the DBEB bit in UBC.BRCR

is not executed.

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10.4.5 Operand access cycle break

1 In the case of an operand access cycle break, the bits included in address bus comparison vary as shown in

Table 135

according to the data size specification in the break bus cycle register ( UBC.BBRA, UBC.BBRB

Data size Address bits compared

Quadword (100)

Longword (011)

Word (010)

Byte (001)

Not included in condition (000)

Address bits A31 to A3

Address bits A31 to A2

Address bits A31 to A1

Address bits A31 to A0

In quadword access, address bits A31 to A3

In longword access, address bits A31 to A2

In word access, address bits A31 to A1

In byte access, address bits A31 to A0

Table 135: Bits included in address bus comparison

2 When data value is included in the break conditions in channel B, set the DBEB bit in the break control register ( UBC.BRCR

) to 1. In this case, break data register B ( UBC.BDRB

) and break data mask register B ( UBC.BDMRB

) settings are necessary in addition to the address condition. A user break interrupt is generated when all 3 conditions (address, ASID, and data) are matched. When a quadword access occurs, the 64-bit access data is divided into an upper 32 bits and lower 32 bits, and interpreted as two 32-bit data units. A break is generated if either of the 32-bit data units satisfies the data match condition.

Set the IDB1 and IDB0 bits in break bus cycle register B ( UBC.BBRB

) to 10 or

11. When byte data is specified, the same data should be set in the 2 bytes comprising bits 15 to 8 and bits 7 to 0 in break data register B ( UBC.BDRB

) and break data mask register B ( UBC.BDMRB

). When word or byte is set, bits 31 to

16 of UBC.BDRB

and UBC.BDMRB

are ignored.

3 When the DBEB bit in the break control register ( UBC.BRCR

) is set to 1, a break is not generated by an operand access with no access data (an operand access in a PREF, OCBP, OCBWB, or OCBI instruction).

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10.4.6 Condition match flag setting

Instruction access with post-execution condition, or operand access

The flag is set when execution of the instruction that causes the break is completed. As an exception to this, however, in the case of an instruction with more than 1 operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed.

Example 1

100

102

BT L200 (branch performed)

Instruction (operand access break on channel A): flag not set

Example 2

110

112

FADD (FPU exception)

Instruction (operand access break on channel A): flag not set

Instruction access with pre-execution condition

The flag is set when the break match condition is detected.

Example 1

110

112

Instruction (pre-execution break on channel A): flag set

Instruction (pre-execution break on channel B): flag not set

Example 2

110 Instruction (pre-execution break on channel B, instruction access TLB miss): flag set

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10.4.7 Program counter (PC) value saved

1 When instruction access (pre-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred. In this case, a user break interrupt is generated and the fetched instruction is not executed.

2 When instruction access (post-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction to be executed after the instruction at which the break condition match occurred. In this case, the fetched instruction is executed, and a user break interrupt is generated before execution of the next instruction.

3 When an instruction access (post-execution) break condition is set for a delayed branch instruction, the delay slot instruction is executed and a user break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction 2 instructions ahead of the branch instruction

(when the branch is not made). In this case, the PC value saved to SPC is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made).

4 When operand access (address only) is set as a break condition, the address of the instruction to be executed after the instruction at which the condition match occurred is saved to SPC.

5 When operand access (address + data) is set as a break condition, execution of the instruction at which the condition match occurred is completed. A user break interrupt is generated before execution of instructions from 1 instruction later to

4 instructions later. It is not possible to specify at which instruction, from 1 later to 4 later, the interrupt will be generated. The start address of the instruction after the instruction for which execution is completed at the point at which user break interrupt handling is started is saved to SPC.

6 If an instruction between 1 instruction later and 4 instructions later causes another exception, control is performed as follows. Designating the exception caused by the break as exception 1, and the exception caused by an instruction between 1 instruction later and 4 instructions later as exception 2, the fact that memory updating and register updating that essentially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the existence of exception 1. The program counter value saved is the address of the first instruction for which execution is suppressed. Whether exception 1 or exception

2 is used for the exception jump destination and the value written to the exception register ( EXPEVT, INTEVT ) is not guaranteed. However, if exception 2 is from a source not synchronized with an instruction (external interrupt or

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348 Operation peripheral module interrupt), exception 1 is used for the exception jump destination and the value written to the exception register ( EXPEVT, INTEVT ).

10.4.8 Contiguous A and B settings for sequential conditions

When channel A match and channel B match timings are close together, a sequential break may not be guaranteed. Rules relating to the guaranteed range are given below.

Instruction access matches on both channel A and channel B

Instruction B is 0 instructions after instruction A

Instruction B is 1 instruction after instruction A

Instruction B is 2 or more instructions after instruction A

Equivalent to setting the same address. Do not use this setting.

Sequential operation is not guaranteed.

Sequential operation is guaranteed.

Instruction access match on channel A, operand access match on channel B

Instruction B is 0 or 1 instruction after instruction A

Instruction B is 2 or more instructions after instruction A

Sequential operation is not guaranteed.

Sequential operation is guaranteed.

Operand access match on channel A, instruction access match on channel B

Instruction B is 0 to 3 instructions after instruction A

Instruction B is 4 or more instructions after instruction A

Sequential operation is not guaranteed.

Sequential operation is guaranteed.

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Operation 349

Operand access matches on both channel A and channel B

Do not make a setting such that a single operand access will match the break conditions of both channel A and channel B. There are no other restrictions. For example, sequential operation is guaranteed even if 2 accesses within a single instruction match channel A and channel B conditions in turn.

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350 Usage notes

10.5 Usage notes

1 Do not execute a post-execution instruction access break for the SLEEP instruction.

2 Do not make an operand access break setting between 1 and 3 instructions before a SLEEP instruction.

3 The value of the BL bit referenced in a user break exception depends on the break setting, as follows.

3.1 Pre-execution instruction access break: the BL bit value before the executed instruction is referenced.

3.2 Post-execution instruction access break: the OR of the BL bit values before and after the executed instruction is referenced.

3.3 Operand access break (address or data): the BL bit value after the executed instruction is referenced.

3.4

Instruction that modifies the BL bit: see Table 136

SL.BL

0 to 0

1 to 0

0 to 1

1 to 1

Pre-executio n instruction access

Post-executi on instruction access

Pre-executio n instruction access

Post-executi on instruction access

Operand access

(address/ data)

Accepted

Masked

Accepted

Masked

Accepted

Masked

Accepted

Masked

Accepted

Masked

Accepted

Masked

Table 136: Break setting for an instruction that modifies the BL bit

Accepted

Masked

3.5 RTE delay slot: the BL bit value before execution of a delay slot instruction is the same as the BL bit value before execution of an RTE instruction. The BL bit value after execution of a delay slot instruction is the same as the first BL bit value for the first instruction executed on returning by means of an RTE

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Usage notes 351 instruction (the same as the value of the BL bit in SSR before execution of the

RTE instruction).

3.6 If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit before execution of the first instruction of the exception handling routine is 1.

4 If channels A and B both match independently at virtually the same time, and, as a result, the SPC value is the same for both user break interrupts, only 1 user break interrupt is generated, but both the CMFA bit and the CMFB bit are set.

For example:

110

112

Instruction (post-execution instruction break on channel

→

SPC = 112, CMFA = 1

Instruction (pre-execution instruction break on channel

→

SPC = 112, CMFB = 1

5 The PCBA or PCBB bit in UBC.BRCR

is invalid for an instruction access break setting.

6 When the SEQ bit in UBC.BRCR

is 1, the internal sequential break state is initialized by a channel B condition match.

For example:

A → A → B (user break generated) B → (no break generated)

7 In the event of contention between a re-execution type exception and a post-execution break in a multistep instruction, the re-execution type exception is generated. In this case, the CMF bit may or may not be set to 1 when the break condition occurs.

8 A post-execution break is classified as a completion type exception.

Consequently, in the event of contention between a completion type exception and a post-execution break, the post-execution break is suppressed in accordance with the priorities of the 2 events. For example, in the case of contention between a TRAPA instruction and a post-execution break, the user break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition.

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User break debug support function

10.6 User break debug support function

The user break debug support function enables the processing used in the event of a user break exception to be changed. When a user break exception occurs, if the

UBDE bit is set to 1 in the UBC.BRCR

register, the DBR register value will be used as the branch destination address instead of [VBR + offset]. The value of R15 is saved in the SGR register regardless of the value of the UBDE bit in the UBC.BRCR

Figure 48 .

Exception/interrupt generation

Hardware operation

SPC

←

SSR

←

SR.BL

←

B'1

SR.MD

←

B'1

SR.RB

←

B'1

Exception

EXPEVT

←

exception code

Exception/ interrupt/trap?

Interrupt

INTEVT

←

interrupt code

Yes

SGR

←

R15

(BRCR.UBDE == 1) &&

(user break exception)?

Reset exception?

PC ← DBR PC ← VBR + vector offset

Trap

TRA

Yes

←

TRAPA (imm)

H'A0000000

Exception handler Debug program

R15

←

SGR

(STC instruction)

Execute RTE instruction

←

SPC

←

SSR

End of exception operations

Figure 48: User break debug support function flowchart

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10.7 Examples of use

10.7.1 Instruction access cycle break condition settings

Independent channel A channel B mode: user break interrupt generated

Under these conditions a user break is generated after execution of the instruction at address 0x00000404 with ASID = 0x80, or before execution of an instruction at addresses 0x00008000 to 0x000083FE with ASID = 0x70.

Register settings

UBC.BASRA

= 0x80,

UBC.BARA

= 0x00000404,

UBC.BAMRA

= 0x00,

UBC.BBRA

= 0x0014,

UBC.BASRB

= 0x70,

UBC.BARB

= 0x00008010,

UBC.BAMRB

= 0x01,

UBC.BBRB

= 0x0014,

UBC.BDRB

= 0x00000000,

UBC.BDMRB

= 0x00000000,

UBC.BRCR

= 0x0400.

Conditions set

Independent channel A channel B mode

Channel A

ASID: 0x80

Address: 0x00000404

Address mask: 0x00

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Examples of use

Bus cycle: instruction access (post-instruction- execution), read (operand size not included in conditions)

Channel B

ASID: 0x70

Address: 0x00008010

Address mask: 0x01

Data: 0x00000000

Data mask: 0x00000000

Bus cycle: instruction access (pre-instruction- execution), read (operand size not included in conditions)

Channel A channel B sequential mode: user break interrupt generated

Under these conditions the instruction at address 0x00037266 with ASID = 0x80 is executed, then a user break is generated before execution of the instruction at address 0x0003722E with ASID = 0x70.

Register settings

UBC.BASRA

= 0x80,

UBC.BARA

= 0x00037226,

UBC.BAMRA

= 0x00,

UBC.BBRA

= 0x0016,

UBC.BASRB

= 0x70,

UBC.BARB

= 0x0003722E,

UBC.BAMRB

= 0x00,

UBC.BBRB

= 0x0016,

UBC.BDRB

= 0x00000000,

UBC.BDMRB

= 0x00000000,

UBC.BRCR

= 0x0008.

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Conditions set

Channel A channel B sequential mode

Channel A

ASID: 0x80

Address: 0x00037226

Address mask: 0x00

Bus cycle: instruction access (pre-instruction- execution), read, word

Channel B

ASID: 0x70

Address: 0x0003722E

Address mask: 0x00

Data: 0x00000000

Data mask: 0x00000000

Bus cycle: instruction access (pre-instruction- execution), read, word

Independent channel A channel B mode: user break interrupts not generated

Under these conditions a user break interrupt is not generated on channel A since the instruction access is not a write cycle.

A user break interrupt is not generated on channel B since instruction access is performed on an even address.

Register settings

UBC.BASRA

= 0x80

UBC.BARA

= 0x00027128

UBC.BAMRA

= 0x00

UBC.BBRA

= 0x001A

UBC.BASRB

= 0x70

UBC.BARB

= 0x00031415

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UBC.BAMRB

= 0x00

UBC.BBRB

= 0x0014

UBC.BDRB

= 0x00000000

UBC.BDMRB

= 0x00000000

UBC.BRCR

= 0x0000

Conditions set

Independent channel A and channel B mode

Channel A

ASID: 0x80

Address: 0x00027128

Address mask: 0x00

Bus cycle: CPU, instruction access (pre-instruction- execution), write, word

Channel B

ASID: 0x70

Address: 0x00031415

Address mask: 0x00

Data: 0x00000000

Data mask: 0x00000000

Bus cycle: CPU, instruction access (pre-instruction- execution), read (operand size not included in conditions)

10.7.2 Operand access cycle break condition settings

Under these conditions on channel A, a user break interrupt is generated in the event of a longword read at address 0x00123454, a word read at address

0x00123456, or a byte read at address 0x00123456, with ASID = 0x80.

On channel B, a user break interrupt is generated when 0xA512 is written by word access to any address from 0x000AB000 to 0x000ABFFE with ASID = 0x70.

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Register settings

UBC.BASRA

= 0x80

UBC.BARA

= 0x00123456

UBC.BAMRA

= 0x00

UBC.BBRA

= 0x0024

UBC.BASRB

= 0x70

UBC.BARB

= 0x000ABCDE

UBC.BAMRB

= 0x02

UBC.BBRB

= 0x002A

UBC.BDRB

= 0x0000A512

UBC.BDMRB

= 0x00000000

UBC.BRCR

= 0x0080

Conditions set

Independent channel A channel B mode

Channel A

ASID: 0x80

Address: 0x00123456

Address mask: 0x00

Bus cycle: operand access, read (operand size not included in conditions)

Channel B

ASID: 0x70

Address: 0x000ABCDE

Address mask: 0x02

Data: 0x0000A512

Data mask: 0x00000000

Bus cycle: operand access, write, word data break enabled

357

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358 Examples of use

10.7.3 User break controller stop function

This function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating.

Note: If you use this function, you cannot use the user break controller.

10.7.4 Transition to user break controller stopped state

Setting the MSTP5 bit of the CPG.STBGR2

(inside the CPG) to 1 stops the clock supply and causes the user break controller to enter the stopped state. Follow steps

1 to 5 below to set the MSTP5 bit to 1 and enter the stopped state.

1 Initialize UBC.BBRA

and UBC.BBRB

to 0.

2 Initialize to 0.

3 Make a dummy read of UBC.BBCR

4 Read , then set the MSTP5 bit in the read data to 1 and write back.

5 Make 2 dummy reads of CPG.STBCR2

Make sure that, if an exception or interrupt occurs while performing steps 1 to 5, you do not change the values of these registers in the exception handling routine.

Do not read or write the following registers while the user break controller clock is stopped:

• UBC.BARA

• UBC.BAMRA

• UBC.BBRA

• UBC.BARB

• UBC.BAMRB

• UBC.BBRB

• UBC.BDRB

• UBC.BDMRB

• UBC.BRCR

If these registers are read or written, the value cannot be guaranteed.

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10.7.5 Cancelling the user break controller stopped state

The clock supply can be restarted by setting the CPG.MSTP5 bit of STBCR2 (inside the CPG) to 0. The user break controller can then be operated again. Follow steps 6 and 7 below to clear the MSTP5 bit to 0 to cancel the stopped state. This is similar to the transition to the stopped state.

6 Read , then clear the MSTP5 bit in the read data to 0 and write the modified data back.

7 Make 2 dummy reads of CPG.STBGR2

As with the transition to the stopped state, if an exception or interrupt occurs while processing steps 6 and 7, make sure that the values in these registers are not changed in the exception handling routine.

10.7.6 Examples of stopping and restarting the user break controller

The following are example programs:

; Transition to user break controller stopped state

; (1)Initialize BBRA and BBRB to 0.

mov #0, R0 mov.l#BBRA, R1 mov.w R0, @R1 mov.l#BBRB, R1 mov.w R0, @R1

; (2)Initialize BBCR to 0.

mov.l #BBCR, R1 mov.w R0, @R1

; (3)Dummy read BRCR.

mov.w R1, R0

; (4)Read STBCR2, then set MSTP5 bit in the read data to 1 and write it back mov.l #STBCR2, R1 mov.b @R0, R1 or #H’1, R0 mov.bR0, @R1

; (5)Twice dummy read STBCR2.

mov.b @R1, R0 mov.b @R1, R0

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Examples of use

; Canceling user break controller stopped state

; (6)Read STBCR2, then clear MSTP5 bit in the read data to 0 and write it back mov.l #STBCR2, R1 mov.b @R1, R0

and #H’FE, R0 mov.b R0, @R1

; (7)Twice dummy read STBGR2.

mov.b@R1, R0 mov.b@R1, R0

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User debug interface

(UDI)

11.1 Overview

11.1.1 Features

The user debug interface (UDI) is a serial input/output interface conforming to

JTAG, IEEE 1149.1, and IEEE Standard Test Access Port and Boundary- Scan

Architecture. The ST40’s UDI supports boundary-scan, and is used for emulator connection. The functions of this interface should not be used when using an emulator. Refer to the emulator manual for the method of connecting the emulator.

The UDI uses 6 pins ( DCK , TMS , TDI , TDO , NOT_TRST , and NOT_ASEBRK /

BRKACK ). The pin functions and serial transfer protocol conform to the JTAG specifications.

11.1.2 Block diagram

Figure 49 shows a block diagram of the UDI. The TAP (test access port) controller

and control registers are reset independently of the chip reset pin by driving the

NOT_TRST pin low or setting TMS to 1 and applying DCK for at least 5 clock cycles.

The other circuits are reset and initialized in an ordinary reset. The UDI circuit has

6 internal registers: SDBPR , SDBSR , SDIR , SDDRH , and SDDRL (these last 2 together designated SDDR ) and SDINT . The SDBPR register supports the JTAG bypass mode, SDBSR is a shift register forming a JTAG boundary scan, SDIR is the command register, SDDR is the data register and SDINT is the UDI interrupt register. SDIR can be accessed directly from the TDI and TDO pins.

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/BRKACK

TMS

Break control

Interrupt/reset etc.

TAP controller

Decoder

Overview

TDI

SDBPR

TDO MUX

Figure 49: Block diagram of UDI circuit

SDIR

SDINT

SDDRH

SDDRL

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11.1.3 Pin configuration

Table 137 shows the UDI pin configuration.

Pin name Description I/O Function

When not used

DCK

TMS

NOT_TRST

TDI

TDO

Clock pin

Mode pin

Input

Same as the JTAG serial clock input pin

(TCK). Data is transferred from data input pin TDI to the UDI circuit, and data is read from data output pin TDO, in synchronization with this signal.

The mode select input pin. Changing this signal in synchronization with DCK determines the meaning of the data input from TDI. The protocol conforms to the JTAG (IEEE Std 1149.1) specification.

Reset pin

Data input pin

Data output pin

Input The input pin that resets the UDI. This signal is received asynchronously with respect to DCK, and effects a reset of the JTAG interface circuit when low.

NOT_TRST must be driven low for a certain period when powering on, regardless of whether or not JTAG is used. This differs from the IEEE specification.

Input The data input pin. Data is sent to the

UDI circuit by changing this signal in synchronization with DCK.

Output The data output pin. Data is sent to the

UDI circuit by reading this signal in synchronization with DCK.

Emulator pin Input/ output

Dedicated emulator pin

Open

Fix at ground

Open

NOT_ASEBRK/

BRKACK

Table 137: UDI pins

A. Pulled up inside the chip. When designing a board that allows use of an emulator, or when using interrupts and resets via the UDI, there is no problem in connecting a pull-up resistance externally.

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B. When designing a board that enables the use of an emulator, or when using interrupts and resets via the UDI, drive NOT_TRST low for a period overlapping NOT_RESET at power-on, and also provide for control by NOT_TRST alone.

The maximum frequency of DCK ( TMS , TDI , TDO ) is 20 MHz. Make the DCK or ST40

CPG setting so that the DCK frequency is lower than that of the ST40’s on-chip peripheral module clock.

11.1.4 Register configuration

Table 138 shows the UDI registers. Except for

SDBPR and SDBSR , these registers are mapped in the control register space and can be referenced by the CPU.

Register name

Description

CPU side

Initial value

0xFFFFFFFD

Fixed values

Type

P4 address

Area 7 address

Access

0xFFF00000 0x1FF00000 16 size

UDI.SDIR

UDI.SDDR/

SDDRH

Instruction register, see

Section 11.2.1:

Instruction register (SDIR) on page 367

Data register H, see

Section 11.2.2:

Data register

UDI.SDDRL

Data register L, see

Section 11.2.2:

Data register

Interrupt factor register (SDINT) on page 371

Undefined

0xFFF00008

0xFFF0000A

Table 138: UDI registers on CPU side

0x1FF00008

0x1FF0000A

32/16

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CPU side

Register name

Description Initial value

Type

P4 address

Area 7 address

Access size

UDI.SDBPR

Bypass register, see

Section 11.2.3:

Bypass register

(SDBPR) on page 371

UDI.SDINT

Interrupt factor register, see

Section 11.2.4:

UDI.SDBSR

Boundary scan register see

Section 11.2.5:

Boundary scan register (SDBSR) on page 372

Undefined

0x00000000

Undefined -

0xFFF00014 0x1FF00014 18

Table 138: UDI registers on CPU side

A. Initialized when the NOT_TRST pin goes low or when the TAP is in the test-logic-reset state.

B. The value read from UDI is fixed (0xFFFF FFFD)

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Initial value

UDI side

Register name

Description

Type Access size

UDI.SDIR

Instruction register, see

Section 11.2.1: Instruction register (SDIR) on page 367

UDI.SDDR/

SDDRH

Data register H, see

UDI.SDDRL

Data register L, see

Section 11.2.3: Bypass register

UDI.SDBPR

Bypass register, see

(SDBPR) on page 371

UDI.SDINT

Interrupt factor register, see

Section 11.2.4: Interrupt factor register (SDINT) on page 371

UDI.SDBSR

Boundary scan register see

Section 11.2.5: Boundary scan register (SDBSR) on page 372

0xFFFFFFFD

Fixed values

Undefined

0x00000000

Undefined -

Table 139: UDI registers on UDI side

A. Initialized when the NOT_TRST pin goes low or when the TAP is in the test-logic-reset state.

B. The value read from UDI is fixed (0xFFFF FFFD)

C. 1 can be written to the LSB using the UDI interrupt command.

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Register descriptions 367

11.2 Register descriptions

11.2.1 Instruction register (SDIR)

The instruction register ( SDIR ) is a 16-bit register that can only be read by the CPU.

In the initial state, bypass mode is set. The value (command) is set from the serial input pin ( TDI ). SDIR is initialized by the NOT_TRST pin or in the TAP test-logic-reset state. When this register is written to from the UDI, writing is possible regardless of the CPU mode. Operation is undefined if a reserved command is set in this register.

Bit

Initial value

TI7

TI6

TI5

TI4

T13

T12

T11

T10

Bit

Initial value

Bits 15 to 8:

Bit 15:

T17

Bit 14:

T16

Bit 13:

T15

Bit 12:

T14

Bit 11:

TI3

Bit 10:

TI2

Bit 9:

TI1

Bit 8:

TI0

1 -

Description

EXTEST

SAMPLE/

PRELOAD

UDI reset negate

UDI reset assert

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Register descriptions

Bit 15:

T17

Bit 14:

T16

Bit 13:

T15

Bit 12:

T14

Other than above

Bit 11:

TI3

Bit 10:

TI2

Bit 9:

TI1

Bit 8:

TI0

Description

UDI interrupt

Bypass mode (initial value)

Reserved

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Register descriptions

Test instruction bits (TI7 to TI0)

Bit 15:

T17

Bit 14:

T16

Other than above

Bit 13:

T15

Bit 12:

T14

Bit 11:

TI3

Bit 10:

TI2

Bit 9:

TI1

Bit 8:

TI0

Description

EXTEST

SAMPLE/

PRELOAD

UDI reset negate

UDI reset assert

UDI interrupt

Bypass mode (initial value)

Reserved

369

Bits 7 to 0: reserved

These bits are always read as 1, and should only be written with 1.

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11.2.2 Data register (SDDR)

The data register ( SDDR ) is a 32-bit register, comprising the 2 16-bit registers

SDDRH and SDDRL , that can be read and written to by the CPU. The value in this register is not initialized by a NOT_TRST or CPU reset.

Bit 31 30 29 28 27 26 25 24

Initial value

Bit 23 22 21 20 19 18 17 16

Initial value

Bit

Initial value

Bit 7 6 5 4 3 2 1 0

Initial value

Bits 31 to 0: DR Data

These bits store the SDDR value.

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11.2.3 Bypass register (SDBPR)

The bypass register ( SDBPR ) is a 1-bit register that cannot be accessed by the CPU.

When bypass mode is set in SDIR , SDBPR is connected between the TDI pin and

TDO pin of the UDI.

11.2.4 Interrupt factor register (SDINT)

The interrupt factor register ( SDINT ) is a 16-bit register that can be read and written from the CPU. When a UDI interrupt command is set in the SDIR

(Update-IR) using the UDI pin, the INTREQ bit is set to 1. While SDIR has the UDI interrupt command, the SDINT register is connected between UDI pins TDI and

TDO , and can be read as a 32-bit register. The high 16 bits are 0 and the low 16 bits are SDINT .

Only 0 can be written to the INTREQ bit from the CPU. While this bit is 1, the interrupt request continues to be generated, and must therefore be cleared to 0 by the interrupt handler. This register is initialized by NOT_TRST or when in the test-logic-reset state.

Bit

Initial value

Bit

Initial value

Bits 15 to 1: reserved

These bits always read as 1, and should only be written with 0.

INTREQ

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Bit 0: interrupt request bit (INTREQ)

Shows the existence of an interrupt request from the UDI interrupt command. The interrupt request can be cleared by writing 0 to this bit from the CPU. When 1 is written to this bit, the existing value is retained.

11.2.5 Boundary scan register (SDBSR)

The boundary scan register ( SDBSR ) is a shift register on the pad for controlling the chip’s I/O pins. Using the EXTEST and SAMPLE/PRELOAD commands, it can perform a JTAG (IEEE Std 1149.1)-compatible boundary scan test.

11.3 Operation

11.3.1 TAP control

Figure 50 shows the internal states of the TAP control circuit. These conform to the

state transitions specified by JTAG.

• The transition condition is the TMS value at the rising edge of DCK .

• The TDI value is sampled at the rising edge of DCK , and shifted at the falling edge.

• The TDO value changes at the falling edge of DCK . When not in the Shift-DR or

Shift-IR state, TDO is in the high-impedance state.

• In a transition to NOT_TRST = 0, a transition is made to the Test-Logic-Reset state asynchronously with respect to DCK .

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Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Figure 50: TAP control state transition diagram

11.3.2 UDI reset

A power-on reset is effected by an SDIR command. A reset is effected by sending a

UDI reset assert command, and then sending a UDI reset negate command, from the UDI pin (see

Figure 51 ). The interval required between the UDI reset assert

command and the UDI reset negate command is the same as the length of time the reset pin is held low in order to effect a power-on reset.

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Hitachi-UDI pin

Hitachi-UDI reset assert

Chip internal reset

CPU state Normal

Hitachi-UDI reset negate

Reset Reset processing

Figure 51: UDI reset

11.3.3 UDI interrupt

The UDI interrupt function generates an interrupt by setting a command value in

SDIR from the UDI. The UDI interrupt is of general exception/interrupt operation type, with a branch to an address based on VBR and return effected by means of an

RTE instruction. The exception code stored in control register INTEVT in this case is

0x600. The priority of the UDI interrupt can be controlled with bits 3 to 1 of control register IPRC.

The UDI interrupt request signal is asserted when, after the command is set

(UPDATE-IR), the INTREQ bit of the SDINT register is set to 1. The interrupt request signal is not negated until 0 is written to the INTREQ bit by software, and there is therefore no risk of the interrupt request being unexpectedly missed. While the UDI interrupt command is set in SDIR , the SDINT register is connected between

TDI and TDO .

11.3.4 Bypass

The UDI pins can be set to the bypass mode specified by JTAG by setting a command in SDIR from the UDI.

11.3.5 Boundary scan (EXTEST, SAMPLE/RELOAD)

The UDI pin can be set in the JTAG boundary scan mode by setting a command in

SDIR from the UDI. Limitations to this are detailed in the relevant product datasheet.

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11.4 Usage notes

11.4.1 SDIR command

Once an SDIR command has been set, it remains unchanged until initialization by asserting NOT_TRST or placing the TAP in the test-logic-reset state, or until another command (other than a UDI interrupt command) is written from the UDI.

11.4.2 SDIR commands in sleep mode

Sleep mode is cleared by a UDI interrupt or UDI reset, and these exception requests are accepted in this mode. In standby mode, neither a UDI interrupt nor a UDI reset is accepted.]

11.4.3 Emulator

The UDI is used for emulator connection. Therefore, UDI functions cannot be used when an emulator is used.

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Advanced user

debugger

(AUD)

12.1 Overview

The advanced user debugger (AUD) provides the function to support debugging of user programs. This function traces such events as branch and memory access that occur when a program is executed and outputs them.

12.1.1 Features

Features of the AUD are as follows:

• 6 input/output pins,

• memory mapped control and status register,

• branch tracing function: tracing of branch destination and branch source addresses,

• window data tracing function: support of A and B 2-channel windows,

for tracing addresses for CPU memory accesses made in the range and their data,

support of 8-, 16-, 32- and 64-bit data lengths,

• for outputting address differential information by small bit count,

• incorporation of 8-level FIFO,

• full trade mode: for outputting all traced data

• real-time trace mode: for obtaining traced data in real-time,

• AUD output clock ratio select function: support of 1, 1/2, 1/4 and 1/8 CPU clock ratios.

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12.1.2 Block diagram

Figure 52 shows a block diagram of the AUD.

CPU FPU

CPU Branch Trace

CPU Address BUS

CPU Store BUS

FPU Store BUS

Load1 BUS

Load2 BUS

AUDCK

AUDSYNC

AUDATA3-0

AUD

Comparator

FIFO

Sync logic &

State machine

AUCSR

AUWASR

AUWAER

AUWBSR

AUWBER

Figure 52: Block diagram of AUD

Overview

32bit

64bit

32bit

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AUD interface pins 379

12.2 AUD interface pins

The AUD has 6 pins for outputting various traced data. The details are shown in

Table 140 .

Pin name Description I/O Description

AUDCK AUD clock Output AUD clock output

The clock ratios are selected from 1, 1/2, 1/4 and 1/8 times of the CPU clock.

AUDATA[3:0]

AUDSYNC

AUD data bus Output The following information is time-shared for output:

• AUD bus command,

• branch destination address/branch source address,

• address/data contents.

AUD sync signal Output AUD bus command valid signals

0: Valid data output to AUDATA

1: AUD bus command output to AUDATA

Table 140: AUD pins

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12.3 Register summary

The AUD has such registers such as AUCSR for controlling the AUD functions, and

AUWASR , AUWBSR , AUWAER and AUWBER for setting windows. These 4 registers

are detailed in Table 141 .

Register name Description Type

Address

Access

7 size

P4 Area

0xFF2000CC 0x1F2000CC 16

Initial value

0x0000 AUD.AUCSR

AUD control register

AUD.AUWASR

AUD window A start address register

AUD.AUWAER

AUD window A end address register

AUD.AUWBSR

AUD window B start address register

AUD.AUWBER

AUD window B end address register

RW 0xFF2000D0 0x1F2000D0 32

RW 0xFF2000D4 0x1F2000D4 32

RW 0xFF2000D8 0x1F2000D8 32

RW 0xFF2000DC 0x1F2000DC 32

Undefined

Table 141: AUD registers

Note: The AUCSR , AUWASR , AUWAER , AUWBSR and AUWBER registers are readable and writable only in the ASE mode.

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ASE hardware break controller

13.1 Overview

The ASE hardware break controller is partly responsible for emulation functions.

When break conditions are set, the controller generates an ASE hardware break interrupt in response to the content of the CPU bus cycle. This function facilitates the creation of a self-monitoring debugger.

13.1.1 Features

The ASE hardware break controller has the following features:

• 4 channels (S, T, U, and V),

• conditions set independently for the individual channels, or ASE hardware break interrupts can be requested with sequential conditions (sequential settings: channel U → channel V, channel T → channel U → channel V, channel

→

channel T

→

channel U

→

channel V),

• 32-bit logical address and ASID compare:

address compare: compare all bits, mask lower 10 bits, mask lower 12 bits, mask lower 16 bits, mask lower 20 bits, mask all bits,

ASID compare: compare all bits, mask all bits,

• data: channel V only, 32-bit maskable,

• bus cycle: instruction access, operand access

• read/write

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• data size: byte, word, longword, quadword

• break on instruction access cycle can be set for either before or after instruction execution.

13.1.2 Differences between the user break controller and ASE hardware break controller

1 The user break controller has 2 channels (A and B); the ASE hardware break controller has 4 channels (S, T, U, and V) which are completely independent from

A and B.

2 The branch is to address VBR + 0x00000100 or DBR on a user break, and address 0xFC000000 on an ASE hardware break.

3 There is a change to privileged mode on a user break; the change is to ASE mode on an ASE hardware break.

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13.1.3 Block diagram

Figure 53 illustrates the block diagram of the User break controller and the ASE

hardware break controller.

Access control

Local address bus

Channel A

Access comparator

Address comparator

Channel V

Access comparator

Address comparator

Data comparator

BBRA

BARA

BASRA*

BAMRA

Channel B

Access comparator

Address comparator

Data comparator

Channels S,T,U

Access comparator

Address comparator

BBRB

BARB

BASRB*

BAMRB

BDRB

BDMRB

BBRS

BARS

BASRS*

BAMRS

BBRV

BARV

BASRV*

BAMRV

BDRV

BDMRV

Control

Break interrupt request

BRCR

BRCRA

BRCRS

IOBAR

IOBDR

ASEEVT

Data bus

Figure 53: Block diagram of user break controller and ASE hardware break controller

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13.2 Register summary

Table 142 shows the control register configuration of the ASE hardware break

controller. The BRCR is the same as that listed for the user break controller.

Register name

ASE.BARS

ASE.BAMRS

ASE.BBRS

ASE.BASRS

ASE.BART

ASE.BAMRT

ASE.BBRT

ASE.BASRT

ASE.BARU

ASE.BAMRU

ASE.BBRU

ASE.BASRU

ASE.BARV

ASE.BAMRV

ASE.BBRV

ASE.BASRV

ASE.BDRV

ASE.BDMRV

ASE.BRCRA

Description

Break address register S

Break address mask register S

Break bus cycle register S

Break ASID register S

Break address register T

Break address mask register T

Break bus cycle register T

Break ASID register T

Break address register U

Break address mask register U

Break bus cycle register U

Break ASID register U

Break address register V

Break address mask register V

Break bus cycle register V

Break ASID register V

Break data register V

Break data mask register V

ASE Break control register

Table 142: ASE hardware break controller registers

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Register name

ASE.BRCRS

ASE.IOBAR

ASE.IOBDR

ASE.ASEEVT

Description

Break control register S

I/O break address register

I/O break data register

ASE interrupt source register

Table 142: ASE hardware break controller registers

A. BASRS, BASRT, BASRU, BASRV registers are located in CCN.

385

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Register summary

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Appendices

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ST40 system architectural conventions

A.1 Introduction

The ST40 follows architectural conventions which present a consistent interface to

ST40 modules.

Note: since systems are typically a mixture of legacy blocks and new IP, in places it is not practical to follow these convention strictly. Nonetheless this appendix documents some of those conventions and describes the semantics of the formats used in this document.

A.1.1 Memory blocks

There are three types of memory blocks:

• control blocks (CB),

• data blocks (DB),

• undefined blocks (UB).

A control block contains a collection of memory-mapped registers holding a variety of status and control information for an ST40 module. There is a 1-to-1 association between ST40 modules and control blocks. Most control blocks contain a Version

Control Register ( VCR ). A VCR identifies the module associated with that control block, the version number of that module, the memory blocks associated with that module (if any) and the module’s error status.

A data block is a contiguous range of data memory blocks associated with a module.

These blocks are not control blocks and do not contain a VCR . Data blocks are typically used to provide access to memory. A module may be associated with 0, 1 or more data blocks. The set of data blocks associated with a module must be

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390 contiguous in physical address space. Each data block is associated with exactly 1 module.

All blocks which are neither control blocks nor data blocks are undefined blocks.

Undefined blocks do not provide useful functionality and all accesses to undefined blocks are errors. Packets destined for an undefined block are routed to the Debug module where an error is recorded. Control blocks are typically 64 Kbytes to

16 Mbytes for the ST40 implementation.

A.1.2 Control registers

A control register is a memory-mapped register held in a control block. Control registers are 32 or 64-bit wide and allocated on addresses that are 4- or 8-byte aligned.

Each control register has a unique name. Control register names are composed hierarchically by concatenating sub-names together separated by a period (‘.’). The left-most sub-name indicates the module that implements that control register.

Succeeding sub-names repeatedly refine the classification of the control register. A control register can be refined to a field by concatenating the control register name with the field name separated by a period (‘.’). A field can be refined to a single bit by concatenating the field with the bit name separated by a period (‘.’).

An example control register is DMA.VCR

. This name refers to the VCR register within the DMA module. An example field is DMA.VCR.STATUS.PERR_FLAGS

This name refers to the PERR_FLAGS field within the DMA .VCR

control register.

An example bit is DMA.VCR.STSUS.

PERR _ FLAGS .

ERR _ RCV . This name refers to the

ERR_RCV bit within the DMA.VCR.

PERR _ FLAGS field.

Control registers are accessed using the SuperHyway. The set of transactions that are supported by a control register depends on the implementation of that control register. Control registers are typically read using a whole-word LoadWord transaction and written using a whole-word StoreWord transaction. It is possible to have control registers that support other transactions, though these are much less common.

Each control block is fully populated by an array of control registers. For ST40 there are 16 Mbytes of control registers space in each control block. Typically, however, each module will only implement a very small proportion of the available control registers.

The semantics of a control register are, in general, specific to that control register and defined by the architecture of the module that implements that control register.

However, there are conventions which all control registers adhere to. Additionally,

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391 there is a standard table format for describing the layout of control registers. These are described in the following sections.

Register conventions

Each control register is either reserved, undefined or defined.

Reserved control registers

Reserved control registers are used to reserve parts of the control block address space. A read from a reserved control register always returns 0. Writes to a reserved control register are always ignored.

In some ST40 implementations reserved registers have specific functionality.

Software must therefore not make assumptions about these registers. A read should be considered to contain undefined data, and writes should only be of zero.

If a control register is reserved, it is possible that this control register will have a different implementation in future components in the ST40 family.

Undefined control registers

Undefined control registers are used to identify parts of the control block address space where the behavior of accesses is not well defined by the architecture. The specification of a particular undefined control register may elaborate on the actual behavior.

Typically, an access causing a request to an undefined control register will result in an error flag being set in the VCR of the module that deals with the request.

Additionally, a response from an access to an undefined control register might result in an error flag being set in the VCR of the module that deals with the response.

A read from an undefined control register will typically return an undefined value or an implementation defined value. A write to an undefined control register will typically be ignored or lead to behavior that is architecturally undefined.

If a control register is undefined, it is possible that this control register will have a different implementation in future components in the ST40 family.

Defined control registers

Defined control registers are implemented and the behavior of accesses is well defined. A defined control register is composed of 1 or more fields. Each field is a collection of bits in the control register. All bits in a defined control register belong to a field. Further categorization of a defined control register is performed at the field level.

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Field conventions

Each field in a defined control register is either reserved or defined.

Reserved fields

Reserved fields are used to reserve parts of a control register. A read from a reserved field always returns 0. Writes to a reserved field are always ignored.

If a field is reserved, it is possible that this control field will have a different implementation in future components in the ST40 family.

Defined fields

A defined field is either read-only, read/write or other.

A read-only field indicates that the value of the field cannot be changed by software.

A read from a read-only field returns the value associated with that field. A write to a read-only field is ignored.

A read/write field indicates that the value of the field has conventional read and write behavior. A read from a read-write field returns the value of that field. A write to a read/write field sets the value of the field.

An other field indicates that the field has atypical semantics. The specification of an other field describes the actual semantics.

In addition to the above defined field types, a field is also either volatile or non-volatile. A non-volatile field is never changed autonomously by hardware, while a volatile field may be changed autonomously by hardware. When a field is volatile, its specification describes the actual semantics. A non-volatile read-only field has an immutable value.

When the value of a field is not architecturally defined, the field is said to have an undefined value. For example, a writable field might have an undefined value between hard reset and the first time that it is written.

A field may have some values which are reserved. These values must not be written into that field, otherwise the behavior of the access is not well defined by the architecture. The specification of a particular writable field which has reserved values will enumerate the reserved values and may elaborate on the actual behavior. It is possible that all values apart from 1 specific value may be reserved.

In this case, the field must be programmed with that specific value.

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Control register layout

The standard table format for describing the layout of a control register is

illustrated in Table 143 .

[register name] [address offset]

Field

[field]

Bits Size Volatile

[bits] [size] [volatile]

Operation [operation]

[synopsis]

Read

Write

Hard reset

[read]

[write]

[hard reset]

Synopsis

Table 143: Standard table format for describing a control register layout

Type

[type]

The fields in square brackets in this table are place-holders for the following information:

• [register name]: the name of the register,

• [address offset]: the byte-offset of the register in the control block of the module containing the register,

• [field]: the name of the field,

• [bits]: the bit numbers occupied by this field. The least significant bit in a control register is bit 0; the most significant bit in a control register is bit 63. A single number indicates a single bit. The notation [x:y] represents the inclusive contiguous range of bits starting at bit x and ending at bit y,

• [size]: the number of bits occupied by this field,

• [volatile]: yes indicates that the field is volatile, while no indicates that the field is not volatile,

• [synopsis]: a summary of the purpose of this field,

• [type]: the type of this field. This can be Res to indicate a reserved field, RO to indicate a read-only field, RW to indicate a read-write field or Other to indicate an other field,

• [operation]: defines the operation of this field,

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• [read]: defines the behavior of this field for a valid read access,

• [write]: defines the behavior of this field for a valid write access,

• [hard reset]: defines the value of this field after a hard reset.

The set of rows used to describe a field are repeated for each field in the control register.

A.1.3 Version control registers

The control register at offset 0 of every control block is the version control register of the module that implements that control block. Thus, the physical address of a control block is the same as the physical address of the VCR in that control block.

Every VCR uses the same layout. This allows software to parse a VCR value without knowledge of the implementation of the module that provided the VCR . It is architecturally guaranteed that no VCR will ever have a value of 0.

The VCR of each module contains the fields listed below.

• PERR_FLAGS: this field contains the packet error flags ( P-ERROR flags) which report the error status of the interface between this module and the packet-router. The set of supported flags and their standard semantics are described in

Appendix A: P-ERROR flags on page 397 . Further information on

the supported P-ERROR flags of the module is given in the VCR description for that module.

• MERR_FLAGS: this field contains module specific error flags ( M-ERROR flags).

The set of supported flags (if any) and their semantics are given in the VCR description for that module.

• MOD_VERS: this field is provided to allow software to distinguish different versions of a module. This allows software to take appropriate action if there are differences between module versions.

• MOD_ID: this field is provided to allow software to identify and distinguish different modules.

• BOT_MB: if this module is associated with 1 or more data blocks then this value indicates the destination value for the data block with the lowest address. If this module is associated with 0 data blocks then this value will be the destination value for the control block of this module.

• TOP_MB: if this module is associated with 1 or more data blocks then this value indicates the destination value for the data block with the highest address. If

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395 this module is associated with 0 data blocks then this value will be the destination value for the control block of this module.

Note: If a module is associated with data blocks, then these data blocks will be contiguous in the address space. This allows ranges of data blocks to be described as the inclusive range from the value of bot_mb to the value of top_mb.

The VCR format is illustrated in

Table 144 .

Field

PERR_FLAGS

MERR_FLAGS

MOD_VERS

[MODULE].VCR

0x000000

Bits Size Volatile Synopsis

[0:7]

Operation

Read

Write

Hard reset

[8:15] 8

Operation

Read

Write

Hard reset

[16:31] 16

Operation

Read

Write

Hard reset

Yes P-port error flags

See Appendix A: P-ERROR flags on page 397

Yes P-MODULE error flags (module specific)

See Appendix A: M-ERROR flags on page 401

No Module version

Indicates module version number

Returns [MOD_VERS]

Ignored

[ MOD_VERS]

Table 144: Standard VCR format

Type

Varies

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Field

MOD_ID

BOT_MB

TOP_MB

[MODULE].VCR

0x000000

Bits Size Volatile

[32:47] 16

Operation

Read

Write

Hard reset

[48:55] 8

Operation

Read

Write

Hard reset

[56:63] 8

Operation

Read

Write

Hard reset

Synopsis

No Module identity

Identifies module

Returns [MOD_ID]

Ignored

[MOD_ID]

No Bottom memory block

Identifies bottom memory block

Returns [BOT_MB]

Ignored

[BOT_MB]

No Top memory block

Identifies top memory block

Returns [TOP_MB]

Ignored

[TOP_MB]

Table 144: Standard VCR format

Type

The fields in square brackets in this table are place-holders for the following information:

• [MODULE] : the name of the module that contains this VCR . The module name will be 1 of the modules provided by the ST40,

• [ MOD_VERS ] : the version number of this module,

• [ MOD_ID ] : the identity of this module,

• [ BOT_MB ] : the destination value for the bottom memory block of this module,

• [ TOP_MB ] : the destination value for the top memory block of this module.

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A.1.4 P-ERROR flags

The P-ERROR flags are a set of 8 flags in a ST40 module’s VCR which indicate errors in the interface between that module and the packet-router. 2 of these error flags are reserved and always read 0. The remaining 6 error flags are used in a standard way by all ST40 modules, though not all modules implement all of these flags. If a module does not implement a particular P-ERROR flag, then that flag has reserved behavior.

All P-ERROR flags are 0 after hard reset. Implemented P-ERROR flags are volatile and are set to 1 by hardware whenever the associated error condition arises. The

P-ERROR flags will be cleared autonomously by hardware only at hard reset.

Software can read and write these flags at any time using appropriate accesses.

It is possible for multiple error conditions to be triggered by a single request. The actual behavior in such cases is specified by the module receiving that request.

The complete set of supported P-ERROR flags is given in

Table 145

Bit Name

ERR_RCV 0

Bit

Read

Write

Size Volatile

Operation

Hard reset

Synopsis Type

Yes An error response has been received RW or

Res

Indicates that an earlier request from that module was invalid

This bit is set by the module hardware if an error response is received by that module from the packet-router. It is cleared autonomously by hardware only at hard reset.

Returns current value

Updates the current value if this bit is implemented by this module

Ignored if this bit is not implemented by this module

Software may write to this bit at any time.

Table 145: P-ERROR flags

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Bit Name

ERR_SNT

BAD_ADDR

Bit

Operation

Read

Write

Size Volatile

Hard reset

Read

Write

Operation

Hard reset

Synopsis Type

Yes An error response has been sent RW or

RES

Indicates that an earlier request to that module was invalid

This bit is set by the module hardware if an error response is sent by that module to the packet-router. It is cleared autonomously by hardware only at hard reset.

Returns current value

Updates the current value if this bit is implemented by this module

Ignored if this bit is not implemented by this module

Software may write to this bit at any time.

Yes A request for an undefined control register has been received

RW or

Res

This bit is set by the module hardware if the module receives a request for an undefined control register. It is cleared autonomously by hardware only at hard reset.

Returns current value

Updates the current value if this bit is implemented by this module

Ignored if this bit is not implemented by this module

Software may write to this bit at any time.

Table 145: P-ERROR flags

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Bit Name

UNSOL_RESP 3

Bit

Read

Write

Size Volatile

Operation

Hard reset

Synopsis Type

Yes An unsolicited response has been received

RW or

Res

This bit is set by the module hardware if the module detects that it has received an unsolicited response. It is cleared autonomously by hardware only at hard reset.

A response is unsolicited if it does not match an outstanding request sent by that module. If a module is incapable of generating requests then all responses to that module are unsolicited. All responses with illegal destinations are routed to the DEBUG where they are signalled as unsolicited responses.

It is possible that a module may receive an unsolicited response which is not detected as unsolicited. This will cause that module to exhibit architecturally undefined behavior.

Software can attempt to clear this flag by writing a 0 to it.

However, this does not necessarily remove the cause of this error condition. If the error condition persists then this flag will continue to be set until a subsequent hard reset.

Returns current value

Updates the current value if this bit is implemented by this module

Ignored if this bit is not implemented by this module

Software may write to this bit at any time.

Table 145: P-ERROR flags

399

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Bit Name

BAD_DEST

BAD_OPC

Bit Size Volatile

Operation

Read

Write

Hard reset

Operation

Read

Write

Hard reset

[6:7] 2

Operation

Read

Write

Hard reset

Synopsis Type

Yes A request with an illegal destination has been received

RW or

Res

This bit is set by the module hardware if a request with an illegal destination is received by that module from the packet-router. This bit will be cleared autonomously by hardware only at hard reset.

Returns current value

If this bit is implemented by this module, writes update the current value. If this bit is not implemented by this module, writes are ignored. Software may write to this bit at any time.

Yes A request with an unsupported opcode has been received

RW or

Res

This bit is set by the module hardware if a request with an unsupported opcode is received by that module from the packet-router. This error can arise because not all modules support all packet-router opcodes. This bit will be cleared autonomously by hardware only at hard reset.

Returns current value

Updates the current value if this bit is implemented by this module

Ignored if this bit is not implemented by this module

Software may write to this bit at any time.

Reserved

Returns 0

Ignored

Reserved

Res

Table 145: P-ERROR flags

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A.1.5 M-ERROR flags

The M-ERROR flags are a set of 8 flags in a module’s VCR which indicate errors specific to that module. If a module does not implement a particular M-ERROR flag, then that flag has reserved behavior.

All M-ERROR flags are 0 after hard reset. Implemented M-ERROR flags are volatile and are set to 1 by hardware whenever the associated error condition arises. The

M-ERROR flags will be cleared autonomously by hardware only after hard reset.

Software can read and write these flags at any time using appropriate accesses.

A.1.6 Memory map conventions

The ST40 physical memory map is organized so that each control block contains a

VCR at offset 0. Additionally, the address range of each data block is described by the VCR of its associated control block. In general, each control block is allocated at a higher address than its data block.

This organization allows software to scan the ST40 memory map to locate control blocks and data blocks. The software can run on a ST40 CPU, or it can run on the host and access ST40 memory using the debug link protocol. The scanning can be achieved in a safe manner with accesses that do not cause major changes to the architectural state of the system. The scanning algorithm scans downwards through the memory map reading 8-byte words from addresses aligned to 2

bytes.

This scan should start at the highest address aligned to 2

24 i.e. 0xFF000000. The

BOT_MB and TOP_MB information in the VCR of each control block should be used to ensure that data blocks are skipped over in the scanning sequence. It is important to ensure that data blocks are not read from, since data blocks may correspond to areas of data that have to be configured carefully and to address space that is implemented using off-chip state. It is possible that reads from off-chip state could modify the state of external memory-mapped peripherals.

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Each 8-byte quadword that is read is to the first 8-byte quad word in a memory block. If the access is to an undefined block then the access will be to an illegal destination address. This will cause the following behavior:

• DEBUG.VCR.

PERR _ FLAGS .

BAD _ ADDR

will be set since the access will cause a request to an illegal destination to be sent to the DEBUG module.

• DEBUG.VCR.

PERR

FLAGS

ERR

SNT will be set since the access will cause an error response to be returned by the DEBUG.

• If the access is to a control block then the access will return the value of the VCR for that control block without setting any error bit nor generating an error response.

These different behaviors can be used to distinguish accesses to an undefined block from accesses to a control block. The scanning algorithm detects data blocks through the VCR values of control blocks. The scanning algorithm itself makes no accesses to locations within data blocks.

This algorithm can be used to classify each ST40 memory block between

0x00000000 and 0xFF000000 (inclusive) as a control block, a data block or an undefined block. Since each VCR value contains a module identity and module version, it is possible for software to check for the presence of particular modules and to handle different module versions appropriately.

A.1.7 P-MODULE specification standards

The specification of each module defines the functionality provided by that module.

Each module defines the following:

• The memory map of each memory block associated with that module. In particular, the memory map of each control block associated with that module indicates whether each control register in that block has defined, reserved or undefined behavior.

• The interactions of that module with the SuperHyway packet-router. This includes the set of transactions that can be initiated by that module, and the transactions that can be serviced by that module. The behavior and signalling of error cases is also fully described.

• The format of all control registers defined by that module and the behavior of all fields in each control register for different types of access.

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PRELIMINARY DATA

Register address list

Block

AUD

DMA

Register name

AUCSR

AUWAER

AUWASR

AUWBER

AUWBSR

CHAN[0]

Address offset

Description

P4 Area 7

AUD control register

AUD window A end address register

AUD window A start address register

AUD window B end address register

AUD window B start address register

State associated with channel 0

Table 20 on page 47

0xFF2000CC

0xFF2000D4

0xFF2000D0

0xFF2000DC

0xFF2000D8

0x100 to 0x1F8

0x1F2000CC

0x1F2000D4

0x1F2000D0

0x1F2000DC

0x1F2000D8

Table 146: Register address list

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Block Register name

DMA

CHAN[0].

ACTION

CHAN[0].

CONTROL

CHAN[0].

COUNT

CHAN[0].

DAR

CHAN[0].

DISABLE

CHAN[0].

ENABLE

CHAN[0].

IDENTITY

CHAN[0].

POINTER

CHAN[0].

SAR

CHAN[0].

STATUS

Description

Cause action on a control bit associated with this channel

Channel control

Channel count

Channel destination address

Disable a control bit associated with this channel

Enable a control bit associated with this channel

Table 32 on page 75

Channel identity

Table 31 on page 71

Pointer to the current or last register memory image

Table 36 on page 85

Channel source address

Status of a control bit associated with this channel

0x20

0x80

0x88

0x98

0x10

0x08

0x00

0x28

0x90

0x18

Table 146: Register address list

Address offset

P4 Area 7

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PRELIMINARY DATA

Block

DMA

Register name Description

CHAN[0].

SUBBASE

CHAN[0].

SUBDISABLE

CHAN[0].

SUBENABLE

CHAN[0].

SUBINT_ACT

CHAN[0].

SUBINT_DIS

CHAN[0].

SUBINT_ENB

CHAN[0].

SUBINT_STAT

CHAN[1:4].

CONTROL

CHAN[1:4].

COUNT

CHAN[1:4].

DAR

CHAN[1:4].

DISABLE

Base pointer to the table of register images in main memory

Table 38 on page 88

Subheading disable

Table 40 on page 90

Subchannel enable

Table 39 on page 89

Subchannel interrupt action

Table 44 on page 92

Subchannel interrupt disable

Table 42 on page 91

Subchannel interrupt enable

Table 41 on page 90

Subchannel interrupt status

Table 44 on page 92

Channel control

Channel count

Channel destination address

Disable or reset a control bit associated with this channel

0x30

0x40

0x38

0x60

0x50

0x48

0x58

0x80

0x88

0x98

0x10

Table 146: Register address list

Address offset

P4 Area 7

405

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Block

DMA

Register name Description

CHAN[1:4].

DST_LENGTH

CHAN[1:4].

ENABLE

CHAN[1:4].

IDENTITY

CHAN[1:4].

NEXT_PTR

CHAN[1:4].

POINTER

CHAN[1:4].

REQUEST

CHAN[1:4].

SAR

CHAN[1:4].

SRC_LENGTH

CHAN[1:4].

SRC_STRIDE

CHAN[1:4].

STATUS

2D destination line length

Table 52 on page 105

Enable or set a control bit associated with this channel

Table 32 on page 75

Channel identity

Table 31 on page 71

Pointer to the next register set

Table 49 on page 102

Pointer to the current or last register set

Table 36 on page 85

The number of the request associated with this channel

Table 37 on page 86

Channel source address

2D source line length

Table 50 on page 103

2D source line stride

Table 51 on page 104

Status of a control bit associated with this channel

0xB8

0x08

0x00

0xA0

0x28

0x30

0x90

0xA8

0xB0

0x18

Table 146: Register address list

Address offset

P4 Area 7

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PRELIMINARY DATA

Block

DMA

Register name

CHAN[1]

CHAN[2]

CHAN[3]

CHAN[4]

CHANNEL[1:4].

ACTION

DEFINED

DISABLE

ENABLE

ERROR

HANDSHAKE

Address offset

Description

State associated with channel 1

State associated with channel 2

State associated with channel 3

State associated with channel 4

Cause action on a control bit associated with this channel

Section 3.3.2: Interrupt control register (ICR) on page 27

Global DMA channel defined

Table 29 on page 70

Global disable

Table 25 on page 66

Global enable

Table 24 on page 65

Global error status

Table 28 on page 69

Global request handshake protocol

Table 30 on page 70

0x200 to 0x2F8

0x300 to 0x3F8

0x400 to 0x4F8

0x500 to 0x4F8

0x20

0x38

0x18

0x10

0x30

0x40

Area 7

Table 146: Register address list

407

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Block

DMA

INTC

Register name Description

INTERRUPT

STATUS

VCR.STATUS

Global DMA status

Table 26 on page 67

Version control register: module status

Table 22 on page 62

VCR.VERSION

Version control register: module version

Table 23 on page 64

ICR Interrupt control

IPRA

IPRB

Global interrupt status

Table 27 on page 68

Interrupt priority level A

Section 3.3.1: Interrupt priority registers A to D

Section 3.3.1: Interrupt priority registers A to D

Interrupt priority level B

Section 3.3.1: Interrupt priority registers A to D

IPRC

IPRD

Interrupt priority level C

Section 3.3.1: Interrupt priority registers A to D

Interrupt priority level D

Section 9.2.1: Receive shift register (SCIF.SCRSR) on page 256

0x28

0x20

0x00

0x08

0x00

0x04

0x08

0x0C

0x10

Table 146: Register address list

Address offset

P4 Area 7

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PRELIMINARY DATA

Block

INTC2

Register name Description

INTC2MODE INTC2 mode

Table 18 on page 39

INTMSK00

INTMSK04

Interrupt mask 00

Table 12 on page 34

Interrupt mask 04

Table 13 on page 35

INTMSK08 Interrupt mask 08

Table 14 on page 35

INTMSKCLR00 Interrupt mask clear 00

Table 15 on page 36

INTMSKCLR04 Interrupt mask clear 04

Table 16 on page 37

INTMSKCLR08 Interrupt mask clear 08

Table 17 on page 37

INTPRI00

INTPRI04

Interrupt priority level 00

Table 6 on page 30

Interrupt priority level 04

Table 7 on page 31

INTPRI08

INTREQ00

INTREQ04

Interrupt priority level 08

Table 8 on page 31

Interrupt request level 00

Table 9 on page 32

Interrupt request level 04

Table 10 on page 33

0x80

0x40

0x44

0x48

0x60

0x64

0x68

0x00

0x04

0x08

0x20

0x24

Table 146: Register address list

Address offset

P4 Area 7

409

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Block

INTC2

PIO

RTC

Register name

INTREQ08

PC0[0:2]

PC1[0:2]

PC2[0:2]

PCOMP[0:2]

PIN[0:2]

PMASK[0:2]

POUT[0:2]

R64CNT

RCR1

RCR2

RDAYAR

Address offset

Description

P4 Area 7

Interrupt request level 08

Table 11 on page 33

Configuration

Table 59 on page 113

Configuration

Table 60 on page 114

Configuration

Table 61 on page 115

Compare data

Table 63 on page 117

Input data

Table 58 on page 112

Compare mask

Table 64 on page 117

Output data

Table 55 on page 109

64 Hz counter

Table 90 on page 185

RTC control register 1

Table 104 on page 212

RTC control register 2

Table 105 on page 215

Day alarm register

Table 102 on page 208

0x28

0x1B010020 + (0x10000 * n)

0x1B010030 + (0x10000 * n)

0x1B010040 + (0x10000 * n)

0x1B010050 + (0x10000 * n)

0x1B010010 + (0x10000 * n)

0x1B010060 + (0x10000 * n)

0x1B010000 + (0x10000 * n)

0x00

0x38

0x3C

0x30

Table 146: Register address list

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PRELIMINARY DATA

Block

RTC

Register name

RDAYCNT

RHRAR

RHRCNT

RMINAR

RMINCNT

RMONAR

RMONCNT

RSECAR

RSECCNT

RWKAR

RWKCNT

RYRCNT

Description

Day counter

Table 95 on page 194

Hour alarm register

Table 100 on page 204

Hour counter

Table 93 on page 190

Minute alarm register

Table 99 on page 202

Minute counter

Table 92 on page 188

Month alarm register

Table 103 on page 210

Month counter

Table 96 on page 196

Second alarm register

Table 98 on page 200

Second counter

Table 91 on page 186

Day of week alarm register

Table 101 on page 206

Day of week counter

Table 94 on page 192

Year counter

Table 97 on page 198

0x14

0x28

0x0C

0x24

0x08

0x34

0x18

0x20

0x04

0x2C

0x10

0x1C

Table 146: Register address list

Address offset

P4 Area 7

411

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Block

SCIF

Register name

SCBRR2

SCFCR2

SCFDR2

SCFRDR2

SCFSR2

SCFTDR2

SCLSR2

SCRSR2

SCSCR2

SCSMR2

SCSPTR2

Description

Bit rate register

Table 125 on page 283

FIFO control register

Table 127 on page 285

FIFO data count register

Table 128 on page 291

Receive FIFO data register

Table 120 on page 257

Serial status register

Table 124 on page 271

Transmit FIFO data register

Table 121 on page 258

Line status register

Table 130 on page 301

Receive shift register

Serial control register

Table 123 on page 264

Serial mode register

Table 122 on page 259

Serial port register

Table 129 on page 293

0x04

0x18

0x1C

0x14

0x10

0x0C

0x24

0x08

0x00

0x20

Table 146: Register address list

Address offset

P4 Area 7

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413

Block

SCIF

TMU

Register name

SCTSR2

TCNT0

TCNT1

TCNT2

TCOR0

TCOR1

TCOR2

TCPR2

TCR0

TCR1

TCR2

TOCR

Description

Transmit shift register

Section 9.2.3: Transmit shift register (SCIF.SCTSR) on page 257

Timer counter 0

Table 113 on page 236

Timer counter 1

Table 113 on page 236

Timer counter 2

Table 113 on page 236

Timer constant register 0

Table 112 on page 235

Timer constant register 1

Table 112 on page 235

Timer constant register 2

Table 112 on page 235

Input capture register

Table 116 on page 243

Timer control register 0

Table 114 on page 237

Timer control register 1

Table 114 on page 237

Timer control register 2

Table 115 on page 239

Timer output control register

Table 110 on page 232

0x0C

0x18

0x24

0x08

0x14

0x20

0x2C

0x10

0x1C

0x28

0x00

Table 146: Register address list

Address offset

P4 Area 7

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Block

TMU

UBC

Register name

TSTR

BAMRA

BAMRB

BARA

BARB

BASRA

BASRB

Address offset

Description

Timer start register

Table 111 on page 233

Break address mask register A

Section 10.3.4: Break address mask register A

(UBC.BAMRA) on page 329

Break address mask register B

Section 10.3.8: Break address mask register B

(UBC.BAMRB) on page 333

Break address register A

Section 10.3.2: Break address register A

(UBC.BARA) on page 328

Break address register B

Section 10.3.6: Break address register B

(UBC.BARB) on page 333

Break ASID register A

Section 10.3.3: Break ASID register A (UBC.BASRA) on page 329

Break ASID register B

Section 10.3.7: Break ASID register B (UBC.BASRB) on page 333

0x04

0xFF200004

0xFF200010

0xFF200000

0xFF20000C

0xFF000014

0xFF000018

Area 7

0x1F200004

0x1F200010

0x1F200000

1F20000C

0x1F000014

0x1F000018

Table 146: Register address list

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415

Block

UBC

UDI

Register name

BBRA

BBRB

BDMRB

BDRB

BRCR

SDBPR

SDBSR

SDDRH

Address offset

Description

Break bus cycle register A

Section 10.3.5: Break bus cycle register A

(UBC.BBRA) on page 331

Break bus cycle register B

Section 10.3.11: Break bus cycle register B

(UBC.BBRB) on page 336

Break data mask register B

Section 10.3.10: Break data mask register B

(UBC.BDMRB) on page 335

Break data register B

Section 10.3.9: Break data register B (UBC.BDRB) on page 334

Break control register

Section 10.3.12: Break control register

(UBC.BRCR) on page 337

Bypass register

Section 11.2.3: Bypass register (SDBPR) on page 371

Boundary scan register

Section 11.2.5: Boundary scan register (SDBSR) on page 372

Data register H

0xFF200008

0xFF200014

0xFF20001C

0xFF200018

0xFF200020

0xFFF00008

Area 7

0x1F200008

0x1F200014

0x1F20001C

0x1F200018

0x1F200020

0x1FF00008

Table 146: Register address list

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Block

UDI

Register name

SDDRL

SDINT

SDIR

Address offset

Description

Data register L