STMicroelectronics L9780 Datasheet
Advertisement
Advertisement
L9780
Wide range air fuel sensor control interface
LQFP48
*$3*36
Datasheet
-
production data
2 channels available to connect compensation networks
Short to battery diagnostic on functional ground
(pin SR)
Short to battery/ground diagnostic on voltage from reference cell (pin INRC)
-5 V internal supply
4 MHz internal oscillator
Package: 48 pin LQFP
Technology: BCD5s_70 V
Features
Voltage controlled current source (VCCS) pump cell driver with selectable voltage clamp, offset compensation, diagnostic (short to battery) and 2 output channels
Impedance measurement of reference cell
10-bit multiplexed A/D converter
Scaling amplifier with sample & hold and offset compensation
Control voltage amplifier with sample & hold and offset compensation
Synchronous or asynchronous functionality selectable via SPI
Heater FET driver with diagnostic (short to battery, short to ground, open circuit)
4 possible levels for clean current
SPI with fault detection
Digital input and outputs compatible with 5 V or
3.3 V voltage supply
Order code
L9780
L9780TR
Description
L9780 is an IC designed to interface a variety of wide range air fuel sensors.
The device manages the oxygen pump of the wide range air fuel sensor by means of a voltage controlled current source (VCCS). The reference for the VCCS is generated by a PI controller with external compensation network in order to adapt the device to different sensors. The user can choose between two different networks using the
SPI interface. L9780 is fully compatible with most sensors on the market.
The internal timing state machine automatically manages all the operations needed for a right sequencing of the measurement process. All the main time values can be configured by SPI.
L9780 drives also an external FET used to control the sensor heater. The device protects the sensor and all the I/O against shorts and provides the diagnosis by SPI.
Table 1. Device summary
Package
LQFP48
LQFP48
Packing
Tray
Tape and reel
November 2014
This is information on a product in full production.
DocID026356 Rev 3 1/56 www.st.com
Contents
Contents
L9780
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin INRC functionalities: INRC amplifier, clean currents, pull-down current 13
Pin FV, FVOUT functionalities: FVOUT amplifier . . . . . . . . . . . . . . . . . . . 15
Pin TG1, TG2, OUT1, OUT2, SNS functionalities: the VCCS . . . . . . . . . 15
Pin PG1, PG2, SR functionalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin HD, HG functionalities: heater FET driver and diagnostic . . . . . . . . . 25
2/56 DocID026356 Rev 3
L9780
Contents
SPI not valid command fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Digital interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DocID026356 Rev 3 3/56
4
Contents
L9780
SPI output register (status configuration) . . . . . . . . . . . . . . . . . . . . . . . 39
SPI output register (input echo configuration) . . . . . . . . . . . . . . . . . . . . 42
4/56 DocID026356 Rev 3
L9780
List of tables
List of tables
vs. possible R tot
to guarantee phase margin and bandwidth . . . . . . . . . . . . . . . . . . . . 18
INRC, RCT2 and integrator amplifiers, RCT1, INRC and band-gap switches, clean currents 44
DocID026356 Rev 3 5/56
5
List of figures
List of figures
L9780
6/56 DocID026356 Rev 3
L9780 Pin description
Figure 1. Pin connection diagram (top view)
4'
3.3
434
).2#
2#4
2#4
32
0'
0'
($
434
('
.#
.#
#,
#,
"'
&6/54
6&
#!
#!
#
#"
#"
Pin number
13
14
15
16
17
9
10
11
12
7
8
5
6
3
4
1
2
Pin name
PG2
HD
TST2
HG
SY
PW
SO
CLK
SI
TG1
SNS
TST1
INRC
RCT1
RCT2
SR
PG1
Table 2. Pin function
Pin description
Switching TAG resistor pin channel 1
VCCS sense pin
Test mode pin 1
Reference cell input
Impedance test pin 1
Impedance test amplifier input
Sensor return
Protection fet gate channel 1
Protection fet gate channel 2
Heater fet drain
Test mode pin 2
Heater fet gate
Synchronous mode pin
Heater PWM input pin
Serial data output
SPI clock
Serial data input
DocID026356 Rev 3
*$3*36
7/56
55
Pin description
Pin number
46
47
48
42
43
44
45
38
39
40
41
34
35
36
37
30
31
32
33
26
27
28
29
22
23
24
25
18
19
20
21
VESD
GNDA
VCCA n.c.
TG2
OUT2
OUT1
CL1 n.c.
n.c.
VCCCP
FLCP1
FLCP2
GNDCP
CP
C2B
C3
C2A
C1A
FV
FVOUT
BG
CL2
CSN
VCCI
GNDD
VCCD n.c.
n.c.
n.c.
C1B
Table 2. Pin function (continued)
Pin name Pin description
SPI chip select
Digital transfer level supply
Digital ground
Digital supply
Not connected pin
Not connected pin
Not connected pin
Compensation network pin1, side B
Compensation network pin2, side B
Compensation network common pin
Compensation network pin2, side A
Compensation network pin1, side A
VCCS filtered control voltage pin
Analog output
Bandgap voltage
VCCS voltage clamp channel 2
VCCS voltage clamp channel 1
Not connected pin
Not connected pin
Charge pump supply
Charge pump floating pin 1
Charge pump floating pin 2
Charge pump analog ground
-5V charge pump output
ESD reference voltage
Analog ground
Analog supply
Not connected pin
Switching TAG resistor pin channel 2
Pump cell output pin channel 2
Pump cell output pin channel 1
L9780
8/56 DocID026356 Rev 3
L9780 Operating conditions
2.2
L9780 may not operate out of the maximum rating ranges. Once the correct situation is restored after one of the following conditions is not respected (but not exceeding the absolute maximum rating range) the part is still able to work with no damage.
Symbol
V s
V
ESD
V in
I in
T j
Table 3. Maximum ratings
Parameter
Supply voltage:
VCCA, VCCD, VCCCP
VCCI
ESD reference
Input voltage
HD, RCT1, RCT2, INRC
SR, SNS
CSN, SI, CLK, PW, SY
Input current
VESD
SR, RCT1, RCT2, SNS
INRC
HD
OUT1, OUT2, TG1, TG2
(leakage for maximum short to battery voltage)
SR, RCT1, RCT2, SNS, INRC, HD, OUT1, OUT2,
TG1, TG2
(when the voltage is driven below the normal operating range)
CSN, SI, CLK, PW, SY
Junction temperature
Value
4.9 to 5.1
3.14 to 5.1
40
0 to 40
-VCCA to VCCA
0 to VCCA
-20
10
50
150
350
-275
±275
-40 to 150
Unit
V
V
V mA
μ A
μ A
μ A
μ A
μ A
μ A
°C
Absolute maximum ratings
The part can be irreparably damaged if the voltages out of the absolute maximum ratings ranges are applied to the pins. The part at these ratings could not work properly.
Symbol
V s
V
ESD
Table 4. Absolute maximum ratings
Parameter
Supply voltage:
VCCA, VCCD, VCCCP, VCCI
ESD reference
Value
-0.3 to +6.5
+53
Unit
V
V
DocID026356 Rev 3 9/56
55
Operating conditions
Symbol
Table 4. Absolute maximum ratings (continued)
Parameter
V in
Input voltage:
HD
RCT1, RCT2, INRC
SR, SNS, TGx, OUTx
CSN, SI, CLK, PW, SY, SO
C1B, C2B, C3, C2A, C1A, BG, CL2, CL1, FV,
FVOUT, PG1, PG2, HG
CP
FLCP1
FLCP2
TST1, TST2
|TGx – OUTx|
I in
Input current:
VESD
SR, RCT1, RCT2, SNS
INRC
HD
OUT1, OUT2, TG1, TG2
(leakage for maximum short to battery voltage)
SR, RCT1, RCT2, SNS, INRC, HD, OUT1, OUT2,
TG1, TG2
(when the voltage is driven below the normal operating range)
CSN, SI, CLK, PW, SY
T stg
T j
Storage temperature range
Maximum junction temperature
1. Voltage at the pin cannot exceed V
ESD
+0.3 V.
Value
-VCCA to +40
-0.3 to VCCI+0.3
-0.3 to VCCA+0.3
-6.5 to +0.3
-0.3 to VCCCP+0.3
CP-0.3 to +0.3
-0.3 to 40
(1)
+16
-20
10
50
150
500
-500
±500
-65 to +150
+150
L9780
Unit
V mA
μ A
μ A
μ A
μ A
μ A
μ A
°C
°C
2.3 Operating temperature range
Symbol
T amb
Table 5. Operating temperature range
Parameter
Operating temperature range
Value
-40 to 125
Unit
°C
10/56 DocID026356 Rev 3
L9780 Block diagram
The following is L9780 block diagram; the description of each block and the definition of external components can be found in the next sections.
Figure 2. Block diagram
#OMP
NETWORK!
#OMP
NETWORK"
3%.3/2
2EF
CELL
0UMP
CELL
4AG
RESISTOR
(42
3.3
0ROTECTION
&%4
6)'.
(EATER&%4
).2#
#!
SWITCH!
).2#
SWITCH"
#" #!
#
37!
#"
#
37"
2%&
)NTEGRATOR
AMPLIFIER
# 6##!
6##$ 6###0
6%3$
6SUPPLY
6##!
).2# ).2#
AMPLIFIER
#LEAR
CURRENT
0ULLDOWN
CURRENT
2&6
6
GENERATOR
&,#0
&,#0
#0
2#4 2#4
AMPLIFIER
2#4
2#4
SWITCH
32
0'
0'DRIVER
0'
0'DRIVER
"ANDGAP
SWITCH
"UFFER
"ANGAP
VOLTAGE
2%&
GENERATOR
3.3
/54
/54
4'
4'
6##3
($
('
(EATERDIAGNOSTIC
(EATERDRIVER
6##!
#,
6##!
#,
0ARKING
AMPLIFIER
0/2
3ENSOR
FAULT
DETECTION
-58
4IMING
STATE
MACHINE
-(Z
OSCILLATOR
2EFERENCE
GENERATOR
"'
2%&
3(
2%&
3(
2%&
&6/54
AMPLIFIER
&6/54
BIT!$
CONVERTER
30)
3CALING
AMPLIFIER
&6
6##)
3)
3/
#,+
#3.
07
0
*$3*36
DocID026356 Rev 3 11/56
55
Main functionalities L9780
12/56
4 different power supplies are present in the device: VCCA, VCCD, VCCCP, VCCI, respectively for analog part, digital part, charge pump, digital interfaces. Digital inputs are compatible with 2 different logic levels (5 V or 3.3 V, the possible levels for VCCI), and are converted to the range 0V-VCCD using internal level shifters connected to VCCD and VCCI.
In the device a negative charge pump is also present and it is used to generate -5 V voltage level (on CP pin), to bias the substrate and to allow the excursion to the negative range to the output pins of VCCS. Charge pump clock frequency is 2 MHz.
3 different ground pins are also present in the device: GNDA, GNDD, GNDCP, respectively for analog, digital and charge pump circuitry.
Possible ranges for power supplies, currents consumption and input/output logic levels are specified in
Table 13 . External component values are specified in
.
On the device a high ESD reference voltage pin (VESD) is available and is used as a protection for the pins externally connected to the sensor and for HD pin; this voltage must be the highest in the application and has to be always connected to the device, through the
RC low pass filter shown in Figure 12
(external component values are specified in
For pins compatible to negative voltages, the negative ESD reference voltage is the substrate (internally connected to CP pin, -5 V). All the other pins have a 5V positive ESD protection voltage level and GND as negative ESD protection voltage level.
Into the device the following voltage references are present:
– a band-gap voltage (typical value 1.215 V) with 3 trimming bits dedicated;
– REF voltage; obtained as the band-gap multiplied by a factor of 1.555; typical value for this voltage is 1.89 V (possible range for this parameter is specified in
– REF2 voltage; typical value is about VCCA/2 (possible range for this parameter is
All internal currents are generated from a reference current obtained by the band-gap
(buffered on BG pin) applied on an external resistance; the possible BG pin voltage range is specified in
Table 9 , the value of external resistance is defined in
.
All timing references are calculated as multiples of the period of the internal oscillator
(TOSC); the typical oscillation frequency is 4 MHz, the possible range is specified in
. Internal oscillator has 4 trimming bits dedicated.
DocID026356 Rev 3
L9780
4.4
4.5
Main functionalities
Power on reset
A power on reset (POR) circuit is present into the device; this circuit monitors VCCA,
VCCCP, VCCD, GNDA, GNDCP, GNDD voltage levels. If one of the supplies falls below (or
one of the grounds exceeds) the defined POR threshold (defined in Table 10
) all the outputs are driven in inactive state, all the registers are set at their default state and the time state machine and all the timers are fixed in the reset state. All these actions are applied after a typical filter time of 15 μ
s (possible range is defined in Table 15
). When the supply that has caused POR condition reaches POR value plus hysteresis (or the ground decreases under
POR threshold) all the outputs are re-enabled.
During reset condition an internal switch connects the charge pump output voltage (CP pin) to GNDA.
Pin INRC functionalities: INRC amplifier, clean currents, pulldown current
Pin INRC in the application is connected to the sensor reference cell; the voltage generated by this cell and applied on L9780 INRC pin is a function of the parameter of the sensor and gives information about how much the λ parameter is far from the target value. The final purpose is to obtain λ =1, that in terms of electrical parameters means to have 450 mV as output of the reference cell (and applied on INRC pin). In the device this pin is the input of an amplifier (INRC amplifier) with gain selectable via SPI (using bit INRCGAIN). The output of this amplifier is one of the multiplexed inputs of the A/D converter (in order to give the μ P the estimation of the λ parameter of the sensor via SPI) and is also internally connected by a switch (INRC switch) to C1A or C1B pin and the external compensation network. The selection of channel A or B is possible using bit COMPSEL. Electrical parameters of INRC
amplifier and INRC switches are specified in Table 10
.
On INRC pin is present a diagnostic circuitry able to detect short to battery/ground conditions and communicate it via SPI (bits STBS2 and STGRC of SPI output register); short to battery detection is always enabled, while the short to ground detection is disabled by default; it can be enabled using bit STGINRC. INRC short to battery/ground thresholds
typical values are 3.2 V and 200 mV (possible ranges are defined in Table 13
). The consequences of the detection of each one of these faults are described in
The INRC pin is connected to the clean current generator: it is a pull-up current source used to clean the air reference of the sensor; the generated current value is selectable via SPI
(using bits CCS[3..0]). Possible clean current values are specified in Table 10
.
On the same pin a 500 μ A pull-down current source is also available, used in order to prevent the presence of false short to battery detection due to capacitive commutations. The activation of this current is selectable via SPI (bit INRCPD); pull-down current range is specified in
A detailed bit description is present in
.
DocID026356 Rev 3 13/56
55
Main functionalities
4.6 Pin RCT1 – RCT2 functionalities: RCT2 amplifier, RCT1 switch, RCT1 band-gap switch
L9780
RCT2 pin is the input of an amplifier with typical gain 4.2 (electrical characteristics of RCT2 amplifier are specified in
Table 10 ). The output of this amplifier is evaluated during the
impedance test and converted in order to communicate its value via SPI to the μ P: the value of RCT2 amplifier output, measured in 2 different conditions (with RCT1 switch open and closed), can in fact give a feedback about the impedance of the reference cell, and consequently about the temperature of the sensor.
RCT1 pin is connected through a switch (RCT1 switch) to ground and through another switch (RCT1 band-gap switch) to the band-gap voltage; both these functions are used during the reference cell impedance test, in particular the second one is used to restore the correct charge of the reference cell after the impedance test (charge balance mechanism).
RCT1 switches resistance range and RCT1 voltage during charge balance are specified in
. For the time diagram of the sequence and the related description see
. Values of external components connected to pins RCT1 and RCT2 are
specified in
4.7 Pin C1A, C2A, C1B, C2B, C3 functionalities: compensation network connection
These pins are used to connect externally the compensation network to the device; via SPI
(using COMPSEL bit) it is possible to select the desired channel (A or B) and connect the external network to the pins C1(A or B), C2(A or B) and C3. The pins of the non selected channel are in high impedance state. C1 is internally connected to the output of INRC amplifier through the INRC switch (driven by the logic during the impedance test, for details see
), while C2 and C3 are internally connected to the inverting input and the
output of an integrator amplifier (C3 is also the VCCS control voltage pin). The non inverting input of the amplifier is connected to REF voltage (typ 1.89 V). The integrator amplifier and the VCCS create a loop (with the external compensation network) of a PI controller. When the loop reaches a stable condition (
= 1), on INRC pin there are 450 mV (if 4.2 gain for
INRC amplifier is selected), while the inputs of integrator amplifier are both to 1.89 V
(450 pin).
mV * 4.2). In this condition there is no output current from the VCCS cell (2.5 V on C3
The values of the external components that must be used in compensation network depend on the sensor that will be driven by the device.
Two examples of possible compensation networks (with defined external components values) are shown below.
Figure 3. Typical sensor D compensation network
K 7 P&
/04 /04 K 7 &
# # #
*$3*36
14/56 DocID026356 Rev 3
L9780 Main functionalities
Figure 4. Typical sensor N compensation network
K 7 P&
K 7 N& K 7 &
# # #
Figure 5. Typical sensor B compensation network
K 7 P&
/04 /04 K 7 &
*$3*36
4.8
4.9
# # #
GAPGPS01860
Typical ranges for integrator amplifier electrical parameters are specified in
Pin FV, FVOUT functionalities: FVOUT amplifier
C3 pin voltage is the VCCS direct input control voltage. Thanks to the presence of the
external capacitor on FV pin (CFV, specified in Table 19
) and the internal resistance RFV
(typical value 5 k Ω and possible range specified in
), on FV pin the low pass filtered
C3 voltage can be measured. FV voltage is the input of the FVOUT amplifier used to provide on FVOUT pin a signal range compatible with an external A/D converter, as follows:
FVOUT = REF2 + G * (FV – REF2)
Where G is the gain of VOUT amplifier selectable via SPI (using bits SAMP[2..0]) among the following values: 1 - 1.5 - 2 - 3 - 4 - 6 - 8 – 12. A sample and hold circuitry and the offset compensation technique are used in the architecture of FVOUT amplifier; for this cell all the electrical parameters are specified in
Pin TG1, TG2, OUT1, OUT2, SNS functionalities: the VCCS
TG1, TG2, OUT1, OUT2, SNS are the interface pins between VCCS structure and the external pump cell. The pump cell allows to control the oxygen concentration by forcing an electric current through the cell itself; in other words it is possible to control the direction and the intensity of oxygen transport, because it is directly related to the direction and the intensity of the current. By controlling the amount of current through the pump cell, it is possible to control the amount of oxygen and consequently the λ parameter of the sensor; closing this mechanism into a loop, like in L9780, it is possible to regulate the pump cell current in order to obtain the target λ = 1. The best working condition for the sensor is the high temperature; in this condition the AC impedance of the pump cell can be assumed to be a large capacitance in series to with a resistor of about 20-30 Ω . When cold, the pump cell can be assumed to be an open circuit.
DocID026356 Rev 3 15/56
55
Main functionalities L9780
VCCS is a voltage controlled current source and is able to sink or source current from the pump cell, depending on its control voltage, that is the voltage present on C3 pin. Through
TG and OUT pins there is the VCCS output current flow, while SNS is a sense pin. VCCS present in L9780 has 2 output channels (1 and 2), selectable via SPI (using bit VCCSOUT);
TG and OUT pins of the non selected channel are in high impedance condition. In VCCS architecture there are 2 internal switches (TG switches) able to short OUT and TG pins of
(using bit TGEN).
); the actuation of these switches can be selected via SPI
Figure 6. VCCS external resistance configuration
,
4' 2TG
3ENSOR
4'
4'
SWITCH
4'%.
/54
3.3
4'
SWITCH
/54
2TG
2OUT
4!'
RESISTOR
2OUT 4OTHE
PUMCELL
*$3*36
If the switch is in off condition the TG pin of the selected channel is in high impedance state.
If the TG switch is in on state the output current of VCCS structure can flow both through TG and OUT pins and can be described with the following expression:
I out
= - (C3 – REF2)/R tot where R tot
is the external total resistance, that can be obtained as a combination of all the external resistances connected to the VCCS pins. Referring to
tot
can be calculated as follows:
R tot
= R out
// (R tg
+ TAG resistor) where R tg channel.
and R out
are the series resistances of the VCCS pins related to the selected
Otherwise, if TG switch is in off state, R tot
= R out can be described with the following expression:
and consequently the VCCS output current
I out
= - (C3 – REF2)/R out
The VCCS characteristic is shown in Figure 7 . In this figure the relationship between SNS
voltage and the voltage on R tot
resistance (that is equal to the difference between OUT voltage and SNS voltage) is defined; these two quantities are in agreement in sign as both
16/56 DocID026356 Rev 3
L9780 Main functionalities depend on the VCCS output current multiplied by a resistance value (the resistance of the pump cell in SNS voltage case and the R tot
resistance in the voltage drop case); from the same figure it is evident that the maximum SNS voltage dynamic range compatible with
L9780 VCCS architecture is -2 V < SNS < 2.4 V and the maximum drop allowed on R
Rout if TG switch is off) is 1.8 V.
tot
(or
Figure 7. VCCS characteristic
/546 3.36 )
OUT
X2
TOT
6
SLOPE^
2
TOT
2
PUMP
6
6
6
*$3*36
At the startup of the device, VCCS structure is disabled by default, that means that all its pins are in high impedance condition and the “parking functionality” is active; in other words, the parking amplifier is switched on and a voltage similar to REF2 is present on C3 pin (see block diagram in
). Besides, a pull-down resistor is internally connected by default from OUT1 pin to GNDA; this is done to avoid that a leakage current can increase the voltage value of VCCS pins until the short to battery condition. When VCCS is enabled or a sensor short to battery condition is detected, the pull-down resistor is automatically disconnected from OUT1 pin; when VCCS is disabled and no fault conditions are present,
VCCS pull-down resistor can be re enabled via SPI (using bit VCCSPD).
If no sensor short to battery condition is present, VCCS structure can be enabled and the output channel selected with an SPI frame (using bits VCCSEN and VCCSOUT); in this case the “parking functionality” is disabled. When VCCS is enabled, it is also possible to activate/deactivate clamp functionality via SPI (using bit CLAMPEN), in order to protect the sensor; when the clamp functionality is activated, a voltage control is enabled on SNS pin and, if its value is going to exceed the voltage range defined by the user, the clamp circuit intervenes in order to modify the VCCS output current and make SNS pin reenter the clamp limits. The clamp limit range can be symmetric or asymmetric; the desired kind of range can be defined via SPI (bit CLAMPSIM). In case of symmetric range, if VCL is the clamp voltage defined by the user, the consequent range allowed for SNS voltage is:
-VCL < SNS < +VCL, with 0.75V<VCL<2V
In case of asymmetric range, if VCL is the clamp voltage defined by the user, the consequent range for SNS voltage is:
-0.8333*VCL < SNS < +VCL, with 0.75 V < VCL < 2.4 V
If the clamp circuit is activated and intervenes while VCCS is working, it is visible also via
SPI because CLAMP bit in SO register is kept = 1 until the clamp circuit is acting during
VCCS activation. The clamp voltage VCL is defined by the user and is equal to the voltage applied on CL1 or CL2 pin; the input channel chosen to read the clamp voltage can be selected via SPI (bit CLAMPCL); the non selected pin can be left open.
DocID026356 Rev 3 17/56
55
Main functionalities L9780
On all VCCS pins a short to battery diagnostic is always active: a short to battery condition is detected if OUT or TG pins exceed VCCA voltage + 30 mV or if SNS pin exceed STBS3 threshold voltage (2.7 V typical value, possible range defined in short to battery fault detection are specified in
). The consequences of a
On SNS pin is also present a short to ground diagnostic circuitry, that is able to detect if SNS pin is into the range SNS_NTH < SNS < SNS_PTH (SNS_NTH and SNS_PTH are voltage thresholds specified in
Table 13 , their typical values are -200 mV and 200 mV). The
consequences of a sensor short to ground detection are specified in
VCCS is designed to respect specification of minimum bandwidth (100 kHz) for different R tot values and is able to guarantee in all conditions a minimum phase margin of 60°. This is possible thanks to the programmability of the VCCS internal compensation capacitances
(C int
). In SPI input frame, 6bit for capacitance configuration are present (VCCSCAP[5..0]); these bits allow to drive the connection of internal compensation capacitances, that in this way are selectable by the user. The higher is the value of capacitance selected and the higher is the phase margin of the structure, but the lower is the consequent bandwidth; with some simplifications the bandwidth of VCCS can be described with the following formula:
Ft = (Gm_in * Gm_outDC * R tot
)/ (2 π * C int
) where Gm_in * Gm_outDC is a constant parameter depending by on the structure used in the design; R tot
is the external total resistance and C int
the internal selectable capacitance.
In the following table it is shown that a wide range of possible R tot the correct compromise between bandwidth and phase margin.
can be driven obtaining
Table 6. C int
vs. possible R tot
to guarantee phase margin and bandwidth
C int
(pF)
Maximum R tot
[ Ω ] value to guarantee a phase margin > 60°
Minimum R tot
[ Ω ] value to guarantee a bandwidth > 100 kHz
1 6 4
2 13 9
3 19 13
4 26 17
5 33 22
6 40 27
7 46 31
8 53 35
9 60 40
10 66
11 72
44
48
12 79
13 85
14 91
15 98
16 104
17 111
53
57
61
65
69
74
18/56 DocID026356 Rev 3
L9780 Main functionalities
Table 6. C int
vs. possible R tot
to guarantee phase margin and bandwidth (continued)
C int
(pF)
Maximum R tot
[ Ω ] value to guarantee a phase margin > 60°
Minimum R tot
[ Ω ] value to guarantee a bandwidth > 100 kHz
18 117
19 123
20 129
78
82
86
21 135
22 141
90
94
23 148 99
24 154 103
25 160 107
26 166 111
27 172 115
28 178 119
29 184 123
30 190 127
31 196 131
32 202 135
33 208 139
34 214 143
35 220 147
36 226 151
37 231 154
38 237 158
39 243 162
40 249 166
41 255 170
42 261 174
43 267 178
44 272 181
45 278 185
46 284 189
47 290 193
48 295 197
49 301 201
50 306 204
51 312 208
DocID026356 Rev 3 19/56
55
Main functionalities L9780
Table 6. C int
vs. possible R tot
to guarantee phase margin and bandwidth (continued)
C int
(pF)
Maximum R tot
[ Ω ] value to guarantee a phase margin > 60°
Minimum R tot
[ Ω ] value to guarantee a bandwidth > 100 kHz
52 318 212
53 324 216
54 329 219
55 335 223
56 341 227
57 347 231
58 352 235
59 357 238
60 363 242
61 369 246
62 374 249
63 380 253
64 386 257
In the table above the list of selectable C int and minimum R
> 100 kHz.
tot
is shown and for each C int
is specified maximum
value that guarantee respectively a phase margin > 60° and a bandwidth
In order to avoid that during the activation of VCCS for a short time the output current can be out of control, the selection or the change of different functionalities of VCCS (like the change of output channel, of input clamp or of C int
capacitances) are possible only when
VCCS is disabled. Well defined rules have to be respected in order to be able to drive correctly VCCS; these rules are specified in
.
All VCCS electrical parameters ranges are specified in sections Table 12
and
the logic signals used to select VCCS functionalities are defined in detail in section 7.3.
4.10 Pin PG1, PG2, SR functionalities
The device is able to drive via SPI (through bits PG1EN, PG2EN) the gate of the external protection FET, that can be connected to PG1 or PG2 pin. This external FET acts as a switch that connects to ground the second terminal of the pump cell and completes the path for VCCS output current (see block diagram in
Figure 2 ). In this condition SR pin voltage is
expected to be low; if the voltage value exceeds STBS1 threshold (typical value of 200mV
and possible range specified in Table 13
), a sensor short to battery condition is detected.
For the consequences of this detection see Section 5.1
.
In order to avoid the possibility that the external FET switch on when the device is un-powered the FET driver has 100 k (typ) pull down resistor permanently connected to
PG1 and PG2 pins. Electrical parameters of PG driver are specified in
.
20/56 DocID026356 Rev 3
L9780 Main functionalities
4.11 Analog to digital conversion
In the device a 10bit A/D converter is present. The analog voltages to be converted are multiplexed by the logic while the state machine is running and are: the output of RCT2 amplifier, the output of INRC amplifier and FV pin voltage (see block diagram in
Between the analog inputs and the A/D converter a scaling amplifier is present; this cell is able to amplify the input signal according to the gain selected via SPI (using bit SAMP[2..0]) with the following relation:
OUTsa = REF2 + G * (Input_voltage – REF2) where G is the gain selectable via SPI among the following values: 1 - 1.5 - 2 - 3 - 4 - 6 - 8 –
12, and OUTsa is the output of the scaling amplifier (and the input of A/D converter). When the selected input of the scaling amplifier is the output of the INRC or RCT2 amplifier, G is fixed (=1), while when the input is FV voltage the gain G can be modified by the user. The multiplexing sequence at the input of the scaling amplifier when the state machine is running
The absolute conversion accuracy compared to an ideal transfer curve is ±2 counts. All the electrical parameters regarding the scaling amplifier and the A/D conversion are specified in
The nominal conversion of the scaling amplifier output is defined in the following formula: count_SA =
--------------------
1024
where: count_SA is the result of the A/D conversion;
OUTsa is the output voltage of the scaling amplifier; floor: a function that returns the greatest integer less than or equal to the argument.
DocID026356 Rev 3 21/56
55
Main functionalities L9780
4.12 Timing state machine
The internal temporization of A/D conversion and of the impedance test are defined by an internal state machine that acts as shown in
.
Figure 8. State machine diagram
4SMC
3TATE
MACHINE
CLOCK
-58 2#4AMP
).2#AMP
&6
-583(
!$
CONVERSION
2#4
SWITCH
3AMPLE
(OLD
#ONVERTER
)DLE
/N
/FF
/N
"ANDGAP
SWITCH
/FF
).2#
SWITCH
/PEN
#LOSED
-EASUREMENT
ACTIVE
TD
TD
T!$
TSPL
T!$
TSPL
TD
TSPL
TD
T!$ T!$
TD
TD
TD
T-!
T2
T)3/
TD
T"
TD
T).2#
&6/543(
3AMPLE
(OLD
*$3*36
The A/D conversion results give an indication about the
parameter of the sensor (that is in relation with INRC pin voltage), about the VCCS output current (from FV voltage evaluation) and about the sensor temperature (from the double conversion of the output of RCT2 amplifier the external μ P is able to evaluate the impedance of the reference cell and consequently the temperature).
All times are defined in Table 16
; some of them (the state machine clock period (T duration of RCT1 switch and band-gap switch pulses (t
R
INRC switch pulse ( tINRC
and t
B smc
), the
) and the second portion of
)) can be defined by SPI (using bits MCP[1..0], ITPT[6..0],
CBT[6..0], ISPT[2..0]), while the first portion of INRC switch pulse is determined by the summation of different events. The SPI selectable variables can not change during the measurement; if any change occurs while a measurement is on going, the new values will be applied in the next measurement cycle.
In SO output frame, 3 bits are dedicated to the measurement cycle counter (COUNT[2..0]); the value measured by the counter is cleared after every power on reset, is automatically incremented by one at every falling edge of measurement clock and latched in SO output
22/56 DocID026356 Rev 3
L9780 Main functionalities register. When the counter reaches its maximum value, the count restarts from zero. The measurement is able to operate in free running or synchronized mode, according to SPI selection (bit SNC); if free running mode is selected, the timing state machine is continuously running, otherwise if synchronized mode is selected the measurement cycle starts for each rising edge on SY pin; if multiple rising edges are detected on SY pin during one measurement cycle, they will be ignored. For a more detailed description of the bits
.
When the INRC amplifier is selected by the MUX, the scaling amplifier gain is automatically set to 1, and the nominal transfer function from INRC pin to A/D output is: count_INRC =
and the nominal transfer function is:
-----------------
1024
INRC =
1024
1
Ginrc
VCCA where:
Ginrc is the gain of the INRC amplifier; count_INRC is the result of the A/D conversion of INRC pin voltage;
INRC is the INRC pin voltage level.
INRC voltage resolution depends on different contributions:
A/D error conversion (±2 counts); scaling amplifier gain accuracy (±0.5%); scaling amplifier offset (±300 μ V);
INRC amplifier gain accuracy (±1%);
INRC amplifier output offset (±21 mV);
VCCA voltage precision.
When the RCT2 amplifier is selected by the MUX, the scaling amplifier gain is automatically set to 1, and the nominal transfer function from RCT2 pin to A/D output is: count_RCT2 =
-----------------
1024
and the nominal transfer function is:
RCT2 =
1024
1
Grtc2
VCCA where:
Grct2 is the gain of the RCT2 amplifier; count_RCT2 is the result of the A/D conversion of RCT2 pin voltage;
RCT2 is the RCT2 pin voltage level.
DocID026356 Rev 3 23/56
55
Main functionalities
RCT2 voltage resolution depends on different contributions:
A/D error conversion (±2 counts); scaling amplifier gain accuracy (±.5%); scaling amplifier offset (±300 μ V);
RCT2 amplifier gain accuracy (±1%);
RCT2 amplifier output offset (±21 mV);
VCCA voltage precision.
L9780
When the VCCS filtered control voltage FV is selected by the MUX, the nominal transfer function from VCCS current (I_VCCS) to A/D output is: count_VCCS =
+
Gsa -I_VCCS
VCCA
Rtot
1024
and the nominal transfer function is:
I_VCCS = –
1024 where:
Gsa is the scaling amplifier gain;
I_VCCS is the VCCS output current;
–
1
2
1
Gsa Rtot
VCCA count_VCCS is the result of the A/D conversion of FV pin voltage;
Rtot is the VCCS external resistance as defined in
I_VCCS current resolution depends on different contributions:
A/D error conversion (±2 counts); scaling amplifier gain accuracy (±0.5% if Gsa=1, ±1% if Gsa = 1.5-2-3-4, ±2% if
Gsa=6-8-12); scaling amplifier offset (±300 μ V);
VCCS gain accuracy (±1.2%);
VCCS offset (±700 μ V);
VCCA voltage precision;
Rtot precision.
24/56 DocID026356 Rev 3
L9780 Main functionalities
4.13 Pin HD, HG functionalities: heater FET driver and diagnostic
As shown in the block diagram of Figure 2
, HG pin is externally connected to the gate of the external heater FET (an NMOS in low-side configuration, with the drain directly connected to the heater element), while HD is connected to the drain through the external resistance
RHD (possible range for this resistor is specified in
The heater is necessary in order to make the sensor work at a correct temperature. The sensor can only operate in high temperature conditions, but as it is not able to reach the desired range of temperature passively, an active heater is usually incorporated into the sensor structure. This heater is normally composed by an ohmic resistor through which the heater FET current is forced. The μ P is able to obtain information regarding the sensor temperature from the results of the impedance test performed into the device and communicated to the μ P via SPI (the higher is the sensor temperature, the lower is its impedance); consequently, the μ P can intervene on sensor temperature acting on PW pin.
PW is a digital input pin of the device and can be driven with a PWM signal by the μ P. PW pin signal is then internally inverted by the logic and the consequent signal is then applied on HG pin, conditioning the activation/deactivation of the external heater FET (and so the power consumption necessary to heat the sensor).
Capacitive coupling due to heater commutations can cause undesired signals on the reference cell; in order to avoid it, the logic freezes the current state of HG signal during the measurement cycle. HG status will be driven again by PW signal once the measurement cycle is completed.
In order to avoid that the external FET switches on when VIGN voltage is present but the device is un-powered, a 100 k Ω pull-down resistor is permanently connected to HG pin.
A diagnostic circuitry is also present into the heater driver, in order to detect open circuit, short to ground or short to battery fault conditions; the logic into the device can communicate via SPI to the μ P the fault detection through OCH, STGH, STBH bit status.
The actions related to the diagnostic fault detection are described in Section 5.4
, while all the heater diagnostic thresholds are specified in
Table 13 . More details about the heater
diagnostic bits can be found in
.
The ranges of the electrical parameters of the heater FET driver are specified in
.
DocID026356 Rev 3 25/56
55
Diagnostic
5 Diagnostic
5.1
L9780
Sensor short to battery
L9780 is able to detect and take actions when a short to battery condition happens on its sensor pins. In particular voltage levels on pins INRC, SNS, SR, OUT1/2 and TG1/2 are controlled. If INRC, SNS or SR pin exceeds the corresponding voltage threshold reported in
(or one of TG/OUT pins exceeds VCCA + 30 mV), a possible sensor short to battery condition is detected. Sensor short to battery diagnostic on SR pin is not active when both PG1 and PG2 are OFF.
Possible sensor short to battery condition is confirmed by the logic (and reported in the SPI output register) and the failure countermeasures are applied in the device only if the duration of the fault is greater than a filter time defined as a multiple of the clock period
(possible filter times ranges are defined in
Table 17 ); in other words, when the possible
sensor short to battery condition is detected, a logic counter starts and when the count reaches the value defined in
Table 17 the fault condition is considered validated. This
counter is reset when the possible short to battery fault is cleared and after every power on reset.
As soon as a possible sensor short to battery condition is detected the VCCS pull-down resistor is disabled immediately, without waiting any filter time; the pull-down will be user.
Actions
Once the sensor short to battery fault is validated (the duration of possible fault is greater than the filter time) the following actions are taken:
1.
Latch off PG1 and PG2;
2. Disable VCCS output current (all VCCS pins are in high impedance condition), impedance test and charge balance switches;
3. Set the STBS1/ STBS2/ STBS3 bit in the SPI output register, according to the pin where the fault has been detected (STBS3 in case of TG/OUT pins).
These actions remain valid until cleared by the user.
During short to battery condition, all pins compatible with this fault have to respect the leakage current consumption specified in
When the short to battery condition is cleared, VCCS, impedance test and charge balance switches may be re enabled asynchronously from VCCS clock if their enable bits are =1. In order to avoid this situation these functions should be disabled via SPI when a short to battery fault is reported. When the fault is de asserted, these functions can be re enabled via
SPI.
For more details about SPI bits see
5.2 INRC pin short to ground
The device is able to detect and take actions when a short to ground condition happens on
INRC pin. This detection is active only if STGINRC bit in SPI input register is set =1 and only if the impedance test switch is disabled.
26/56 DocID026356 Rev 3
L9780
5.3
Diagnostic
If INRC pin is below the corresponding voltage threshold reported in
short to ground condition is detected. Possible short to ground condition is confirmed by the logic (and reported in the SPI output register) only if the duration of the fault is greater than a filter time, defined as a multiple of the clock period; in other words, when the possible sensor short to ground condition is detected, a logic counter starts and when the count reaches the value defined in
Table 17 , the fault condition is considered validated. This
counter is reset when the possible short to ground fault is cleared and after every power on reset.
Actions
Once the INRC short to ground fault is validated (the duration of possible fault is greater than the filter time) the following action is taken:
1.
Set the STGRC bit in the SPI output register.
This action remains valid until cleared by the user.
SNS pin short to ground
The device is able to detect and take actions when a short to ground condition happens on
SNS pin.
If SNS pin is in the range SNS_NTH < SNS < SNS_PTH (SNS_NTH, SNS_PTH thresholds values reported in
Table 13 ), a possible short to ground condition is detected. Possible short
to ground condition is confirmed by the logic (and reported in the SPI output register) only if the duration of the fault is greater than a filter time, defined as a multiple of the clock period; in other words, when the possible sensor short to ground condition is detected a logic counter starts and when the count reaches the value defined in
Table 17 , the fault condition
is considered validated. This counter is reset when the possible short to ground fault is cleared and after every power on reset.
Actions
Once the SNS short to ground fault is validated (the duration of possible fault is greater than the filter time) the following action is taken:
1.
Set the STGSNS bit in the SPI output register.
This action remains valid until cleared by the user.
Application note
When the regulation loop is approaching the condition =1, that in terms of electrical parameters means to have 450 mV as output of the reference cell (applied on INRC pin), the output current of the VCCS is very small so the voltage of SNS is near to GND. This does not flag a fault condition but the STGSNS bit in the SPI output register is expected to be set.
The device is able to detect and take actions when a fault condition happens on external heater FET, connected to the device through HG and HD pins. Detected fault conditions are: heater short to battery, heater short to ground, heater open circuit.
DocID026356 Rev 3 27/56
55
Diagnostic
5.4.1
5.4.2
L9780
From a design point of view, to HD pin are connected an 80 μ A sink current generator
(normally on, except for particular diagnostic conditions) and a 190 μ A source current generator (normally off, except for particular diagnostic conditions); possible ranges for generated currents are specified in
Heater short to battery
When the external heater is in “on” condition, the heater drain is expected to be low (the external heater is considered “on” when the HG voltage value is higher than a specific threshold, defined in
Table 13 , typical value 4V). If the heater drain voltage value is higher
than the heater short to battery threshold (selectable via SPI using bit STBHTH, as defined
), a possible heater short to battery condition is detected. Possible heater short to battery condition is confirmed by the logic (and reported in the SPI output register) only if the duration of the fault is greater than a filter time, defined as a multiple of the clock period; in other words, when the possible heater short to battery condition is detected, a logic counter starts and when the count reaches the value defined in
Table 17 (and selectable via SPI
using bit STBHFT[1..0]) the fault condition is considered validated. This counter is reset when the possible short to battery fault is cleared and after every power on reset.
Actions
Once the heater short to battery fault is validated (the duration of possible fault is greater than the filter time) the following actions are taken:
1.
Latch HG off;
2. Set STBH bit in SPI output register.
These actions remain valid until cleared by the user.
Heater short to ground
When the external heater is in “off” condition, the heater drain is expected to be high. If the heater drain voltage value is lower than the heater short to ground threshold HSG (3.69
V typical value, possible range specified in
Table 13 ), a possible heater short to ground
condition is detected. Possible heater short to ground condition is confirmed only if the duration of the fault is greater than a filter time, defined as a multiple of the clock period; in other words, when the possible heater short to ground condition is detected a logic counter starts and when the count reaches the value defined in
Table 17 the fault condition is
considered validated. This counter is reset when the possible short to ground fault is cleared and after every power on reset.
Actions
Once the heater short to ground fault is validated (the duration of possible fault is greater than the filter time) the following actions are taken:
1.
Set the STGH bit in SPI output register;
2. Latch HG off;
3. Invoke a test of heater open circuit.
These actions remain valid until cleared by the user or modified after the open circuit test.
28/56 DocID026356 Rev 3
L9780
5.4.3
Diagnostic
Heater open circuit
The device is able to distinguish between heater FET short to ground and open circuit conditions. Once the heater open circuit test is invoked, the following actions are taken:
1.
Turn off HD sink current generator;
2. Turn on HD source current generator;
3. If HD voltage value > open circuit threshold (specified in
open circuit is detected and immediately validated.
Actions
Once the heater open circuit fault is validated the following actions are taken:
1.
Set the OCH bit in SPI output register;
2. Clear the STGH bit in SPI output register.
These actions remain valid until cleared by the user.
5.5.1
Once a fault condition is reported in the SPI output register but the fault condition is removed from the device, the user is able to clear the register and restore the normal operative condition. This is possible using the CLEARFLT bit in the SPI input register. The effect of this bit is to clear all the latched fault conditions and re enable every previously disabled output; on HD pin sink and source currents are restored to their default condition.
The bit is then internally cleared when the clear operation is completed.
SPI data fault
The device continuously monitors the data input on SPI register. Bits 14 and 15 (CB0, CB1) are the data confirmation bits and if one of their values is different from the expected
(CB0=0, CB1=1) an SPI data fault is detected and immediately validated.
Actions
Once an SPI data fault is validated the following actions are taken:
1.
Ignore the corrupted message;
2. Assert SPIF1 and de assert SPIF2 bits in the output register; these bits are latched until cleared by CLEARFLT;
3. Set REG bit to ‘0’.
DocID026356 Rev 3 29/56
55
Diagnostic
5.5.2
5.5.3
L9780
SPI length fault
Receiving an SPI frame with a length different from [64 + (n*8)] bits is considered an SPI length fault, immediately detected and validated.
Actions
Once an SPI length fault is validated the following actions are taken:
1.
Ignore the corrupted message;
2. Assert SPIF1 and de assert SPIF2 bits in the output register; these bits are latched until cleared by CLEARFLT;
3. Set REG bit to ‘0’.
SPI not valid command fault
Any of the following conditions is considered an SPI not valid command fault:
1.
SPI frame with INRCPD = VCCSEN = 1;
2. SPI frame with VCCSPD = VCCSEN = 1;
3. When VCCS is enabled, the SPI frame modifies VCCSOUT, COMPSEL or
VCCSCAP[5..0] bit status;
4. When VCCS and clamp are enabled, the SPI frame modifies CLAMPCL or CLAMPSIM bit status.
The fault is validated immediately.
Actions
Once an SPI not valid command fault is validated the following actions are taken:
1.
Ignore the corrupted message;
2. Assert and latch SPIF1 and de assert SPIF2 bits in the output register; these bits are latched until cleared by CLEARFLT;
3. Set REG bit to ‘0’.
5.6 Loss of ground
L9780 has no loss of ground detection. If one of the grounds exceeds the power on reset voltage threshold, the device enters the reset condition. For detailed description see
.
30/56 DocID026356 Rev 3
L9780
6
Digital interface description
Digital interface description
L9780 contains a serial peripheral interface (SPI) composed by the serial clock (CLK), serial data out (SO), serial data in (SI), chip select (CSN) and is configured as an SPI slave. If
CSN is asserted and the SPI master continues to issue CLK pulses after the SPI shift register is filled, the device shall shift the master’s SI data out on SO output.
SPI can support a daisy chain configuration, so the external processor can send SPI commands to multiple devices without using additional chip select pins, as shown in
.
Figure 9. Daisy chain configuration
,?
#3.
,?
#3.
,?
#3.
#3.
-/3) 3) 3) 3)
3/ 3/ 3/
0
#,+ #,+ #,+
#,+
-)3/
*$3*36
Figure 10. SPI transmission in Daisy chain configuration
0#3.
,#3.
0-/3)
,?-)3/
,?-/3)
,?-)3/
#OMMAND
,?
OUTPUT
#OMMAND
#OMMAND
#OMMAND
#OMMAND
,?-/3)
,?-)3/
,?
OUTPUT
,?
OUTPUT
#OMMAND
,?-/3)
0-)3/
,?
OUTPUT
,?
OUTPUT
,?
OUTPUT
-3" ,3"
*$3*36
The first 64 bit data coming out of SO are the output register bits; the subsequent bits are the SPI commands received through SI pin.
DocID026356 Rev 3 31/56
55
Digital interface description L9780
6.1 CSN
CSN pin is used to select the device for serial transfer. If CSN is asserted, SO pin exits its tri state condition and all status information is latched into SPI shift register; register data are shifted into SI pin and out from SO pin on each subsequent CLK. If CSN is negated, SO pin is in tri state condition and the fault register is reloaded (latched) with current filtered status bits. CSN is immune to spurious pulses of 50 ns or shorter (SO pin can exit tri state condition but no fault clear is applied and no status bit changes). An internal 30 μ A pull-up current is present on CSN pin in order to force the negated condition if a pin open circuit is present.
6.2 CLK
CLK pin provides to the device the clock signal necessary for serial data transfer. When
CSN is asserted the device latches input data and shall shift output data on CLK rising edge.
6.3 SI
SI pin is able to receive data from the master microprocessor while CSN is asserted. The
MSB is the first bit and LSB is the last bit of the word received on SI. The input word consists of 64 bit; follows the description of the SPI input register.
6.3.1 SPI input register
62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
32/56
Bit 63 – 60:
These bits are not used and their status is ignored.
Bit 59: REG
The meaning of this bit is to select a specific content for SO register. If REG=‘0’, SO contains the status register, if REG=‘1’ SO contains the input register. The device sends the requested information in the next SPI frame.
Default state for this bit after power on reset: 0.
DocID026356 Rev 3
L9780 Digital interface description
Bit 58: INRCPD
This bit enables (INRCPD=’1’) or disables (INRCPD=’0’) INRC pull-down current.
If the device receives an SPI command in order to modify the status of this bit in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. The information reported in the output register is the configuration used in the last measurement cycle.
If the device receives an SPI command in order to modify INRCPD and VCCSEN bits at the same time, it will perform these two actions in sequence, with a delay between the two events. In particular if in the input frame INRCPD=’0’ and VCCSEN =’1’, the device disables
INRC pull-down before enabling VCCS, viceversa if in the input frame INRCPD=’1’ and
VCCSEN =’0’, the device disables VCCS before enabling INRC pull-down current.
For correct use of this bit, refer also to
Default state for this bit after power on reset: 0.
Bit 57: STGINRC
This bit enables (STGINRC=’1’) or disables (STGINRC=’0’) short to ground diagnostic on
INRC pin.
Default state for this bit after power on reset: 0.
Bit 56: INRCGAIN
This bit selects the gain of INRC amplifier as follows:
INRCGAIN =’0’ => selected 4.2 gain;
INRCGAIN =’1’ => selected 2.1 gain.
Possible ranges for these gains are specified in section 8.1.2.1.
If the device receives an SPI command in order to modify the gain of INRC amplifier in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. The value of the gain reported in the output register is the gain used in the last measurement cycle.
Default state for this bit after power on reset: 0.
Bit 55: TGEN
This bit enables (TGEN=’1’) or disables (TGEN=’0’) VCCS TG switches between TG and
OUT pins.
If the device receives an SPI command in order to modify TGEN bit in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. TGEN bit value reported in the output register is the value used in the last measurement cycle.
Default state for this bit after power on reset: 0.
Bit 54: VCCSEN
This bit enables (VCCSEN=’1’) or disables (VCCSEN=’0’) VCCS cell. When VCCSEN=’0’,
VCCS is disabled and the “parking functionality” is active, that means that on C3 pin a voltage similar to REF2 is present (the range of this voltage is specified in
DocID026356 Rev 3 33/56
55
Digital interface description L9780
If the device receives an SPI command in order to modify VCCSEN bit in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. VCCSEN bit value reported in the output register is the value used in the last measurement cycle.
Refer to INRCPD bit description to define VCCS and INRC pull-down current switch on sequence.
Refer to VCCSPD bit description to define VCCS and VCCS pull-down resistor switch on sequence.
For correct use of this bit, refer also to
Default state for this bit after power on reset: 0.
Bit 53: VCCSOUT
This bit selects VCCS output channel (and corresponding TG pin) as follows:
VCCSOUT=’0’ => selected channel 1;
VCCSOUT=’1’ => selected channel 2.
If the device receives an SPI command in order to modify VCCSOUT bit in the middle of a measurement cycle while VCCS is disabled, it stores the new information and applies it at the beginning of the new measurement cycle. VCCSOUT bit value reported in the output register is the value used in the last measurement cycle.
For correct use of this bit, refer also to
Default state for this bit after power on reset: 0.
Bit 52: VCCSPD
This bit enables (VCCSPD=’1’) or disables (VCCSPD=’0’) VCCS pull-down resistor on
OUT1 pin.
If the device receives an SPI command in order to modify VCCSPD bit in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. VCCSPD bit value reported in the output register is the value used in the last measurement cycle.
If the device receives an SPI command in order to modify VCCSPD and VCCSEN bits at the same time, it will perform these two actions in sequence, with a delay between the two events. In particular if in the input frame VCCSPD=’0’ and VCCSEN =’1’, the device disables
VCCS pull-down before enabling VCCS, viceversa if in the input frame VCCSPD=’1’ and
VCCSEN =’0’, the device disables VCCS before enabling VCCS pull-down resistor.
For correct use of this bit, refer also to
Default state for this bit after power on reset: 1.
Bit 51: COMPSEL
This bit selects the output compensation network as follows:
COMPSEL=’0’ => selected channel A;
COMPSEL=’1’ => selected channel B.
If the device receives an SPI command in order to modify COMPSEL bit in the middle of a measurement cycle while VCCS is disabled, it stores the new information and applies it at
34/56 DocID026356 Rev 3
L9780 Digital interface description the beginning of the new measurement cycle. COMPSEL bit value reported in the output register is the value used in the last measurement cycle.
For correct use of this bit, refer also to
Default state for this bit after power on reset: 0.
Bit 50: CLAMPEN
This bit enables (CLAMPEN=’1’) or disables (CLAMPEN=’0’) VCCS voltage clamp.
If the device receives an SPI command in order to modify CLAMPEN bit in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. CLAMPEN bit value reported in the output register is the value used in the last measurement cycle.
Default state for this bit after power on reset: 0.
Bit 49: CLAMPCL
This bit selects the clamp voltage input pin as follows:
CLAMPCL=’0’ => selected pin CL1;
CLAMPCL=’1’ => selected pin CL2.
If the device receives an SPI command in order to modify CLAMPCL bit in the middle of a measurement cycle while VCCS is disabled, it stores the new information and applies it at the beginning of the new measurement cycle. CLAMPCL bit value reported in the output register is the value used in the last measurement cycle.
For correct use of this bit, refer also to
Default state for this bit after power on reset: 0
Bit 48: CLAMPSIM
This bit selects symmetric or asymmetric voltage clamp limit range as follows:
CLAMPSIM=’0’ => symmetric clamp limit range;
CLAMPSIM=’1’ => asymmetric clamp limit range.
For the meaning of symmetric/asymmetric range refer to VCCS analog description in section 5.9.
If the device receives an SPI command in order to modify CLAMPSIM bit in the middle of a measurement cycle while VCCS is disabled, it stores the new information and applies it at the beginning of the new measurement cycle. CLAMPSIM bit value reported in the output register is the value used in the last measurement cycle.
For correct use of this bit, refer also to
Default state for this bit after power on reset: 0
Bit 47: CLEARFLT
This bit is used to clear latched faults when the origin of the fault is removed, as follows:
CLEARFLT=’0’ => no action;
CLEARFLT=’1’ => clears faults after CSN bit returns to ‘1’.
DocID026356 Rev 3 35/56
55
Digital interface description L9780
Default state for this bit after power on reset: 0.
Bit 46 - 43: CCS[3..0]
These bits are used to select the clean current source on INRC pin, as specified in
If the device receives an SPI command in order to modify CCS[3..0] bits in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. CCS[3..0] bits reported in the output register are the values used in the last measurement cycle.
Default state for these bits after power on reset: 0000.
Bit 42 - 40: SAMP[2..0]
These bits are used to select the gain of the scaling and FVOUT amplifiers, as specified in
If the device receives an SPI command in order to modify SAMP[2..0] bits in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. SAMP[2..0] bits reported in the output register are the values used in the last measurement cycle.
Default state for these bits after power on reset: 000.
Bit 39 - 34: VCCSCAP[5..0]
These bits are used to set the compensation capacitance C int
into VCCS cell. 1pF is permanently connected as compensation capacitance; to this value the decimal conversion of VCCSCAP[5..0] sequence has to be added in order to obtain the total capacitance used as compensation, as follows:
VCCSCAP[5..0] = 000000 => 1 pF
VCCSCAP[5..0] = 111111 => 64 pF
The device is able to change compensation capacitance only when the VCCS is disabled.
The correct selection of C int
depends on the kind of the external resistive network that the
VCCS has to drive; some rules for a correct selection of C int
.
capacitance are described in
For correct use of these bits, refer also to
.
Default state for these bits after power on reset: 111111.
Bit 33 - 32: MCP[1..0]
These bits are used to set the measurement clock period (Tsmc), as specified in Table 16
.
If the device receives an SPI command in order to modify MCP[1..0] bits in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. MCP[1..0] bits reported in the output register are the values used in the last measurement cycle.
When the device is configured in synchronous mode, MCP bit configuration is ignored and the status bits reported in SPI output register is 00.
For the description of the timing sequence refer to Section 4.12
Default state for these bits after power on reset: 00.
36/56 DocID026356 Rev 3
L9780 Digital interface description
Bit 31: STBHTH
This bit selects the heater short to battery threshold as follows:
STBHTH=’0’ => 250 mV;
STBHTH=’1’ => 425 mV;
The possible ranges of these thresholds are specified in
If the device receives an SPI command in order to modify STBHTH bit in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. STBHTH bit value reported in the output register is the value used in the last measurement cycle.
Default state for this bit after power on reset: 0.
Bit 30 - 24: ITPT[6..0]
These bits are used to set the RCT1 switch time pulse duration (t
R
), as specified in section
.
If the device receives a configuration ITPT[6..0]=’0011000’ or less (except 0000000), the device considers this configuration as ‘0011001’, and shall provide SO response with the configuration received from SI, even if is ‘0011000’ or less.
If the device receives an SPI command in order to modify ITPT[6..0] bits in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. ITPT[6..0] bits reported in the output register are the values used in the last measurement cycle.
For the description of the timing sequence refer to Section 4.12
Default state for these bits after power on reset: 0000000 (corresponding to disable state).
Bit 23: SNC
This bit selects the synchronized mode for the device (when SNC=’1’) or the free running mode (when SNC=’0’).
If the device receives an SPI command in order to set SNC=’1’ bit in the middle of a measurement cycle, it terminates the measurement cycle and discards all the temporary conversions; then operates in idle configuration until a rising edge on SY pin is detected; this is the signal necessary to start a new measurement cycle and to clear the measurement counter.
Default state for this bit after power on reset: 0.
Bit 22 - 16: CBT[6..0]
These bits are used to set the RCT1 band-gap switch time pulse duration (t
B
), as specified in
If the device receives an SPI command in order to modify CBT[6..0] bits in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. CBT[6..0] bits reported in the output register are the values used in the last measurement cycle.
For the description of the timing sequence refer to Section 4.12
Default state for these bits after power on reset: 0000000.
DocID026356 Rev 3 37/56
55
Digital interface description L9780
Bit 15 - 14: CB[1..0]
These are confirmation bits.
CB1 => expected always = ‘1’; if it is not verified, a problem (short to ground or open) in SPI interface is present;
CB0 => expected always = ‘0’; if it is not verified, a problem (short to supply) in SPI interface is present.
Bit 13:
This bit is not used and its status is ignored.
Bit 12 - 11: STBHFT[1..0]
These bits are used to define the heater short to battery fault time duration, as specified in
.
Default state for these bits after power on reset: 00.
Bit 10 - 8: ISPT[2..0]
These bits are used to define the INRC switch time pulse duration ( tINRC
), as specified in
.
If the device receives an SPI command in order to modify ISPT[2..0] bits in the middle of a measurement cycle, it stores the new information and applies it at the beginning of the new measurement cycle. ISPT[2..0] bits reported in the output register are the values used in the last measurement cycle.
For the description of the timing sequence refer to Section 4.12
Default state for these bits after power on reset: 000.
Bit 7: PG2EN
This bit enables (PG2EN=’1’) or disables (PG2EN=’0’) protection FET on channel 2. If a sensor short to battery condition is detected, the PG driver remains off even if a frame with
PG2EN=’1’ is sent; if
detailed description of the diagnostic fault detection refer to Section 5.1
.
Default state for this bit after power on reset: 0.
Bit 6: PG1EN
This bit enables (PG1EN=’1’) or disables (PG1EN=’0’) protection FET on channel 1. If a sensor short to battery condition is detected, the PG driver remains off even if a frame with
PG1EN=’1’ is sent; if the driver is in on state and a sensor short to battery condition is detected, it will be switched off. For a detailed description of the diagnostic fault detection
Default state for this bit after power on reset: 0.
Bit 5 – 0:
These bits are not used and their status is ignored.
38/56 DocID026356 Rev 3
L9780 Digital interface description
6.4 SO
SO pin is in tri state condition when CSN is negated. When CSN is asserted the MSB is the first bit and LSB is the last bit of the word transmitted on SO.
SPI output register can be configured to report the configuration status of the device (with conversion and fault detection results) or can be configured to report an echo of the previous SPI input sequence. The first solution can be selected setting REG bit to ‘0’; the second solution can be selected setting REG bit to ‘1’. The output word consists of 64 bit.
Here following the description of the SPI output register in both configurations.
6.4.1 SPI output register (status configuration)
62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bit 63:
Bit not used.
Bit 62 - 60: VER[2..0]
Silicon version bits. These bits are updated after every silicon revision as follows:
Table 7. Silicon version bits
0 0 1 silicon
Bit 59: REG
This bit represents the SO content, as follows:
REG=’0’ => SO status register;
REG=’1’ => SO input register.
Bit 58:
Bit not used.
DocID026356 Rev 3 39/56
55
Digital interface description L9780
Bit 57 - 48: RCAMP[9..0]
10 bit A/D conversion of the output of INRC amplifier. For detailed description of the timing sequence refer to
.
Bit 47 - 45: COUNT[2..0]
3 bit measurement counter. For detailed description of the timing sequence refer to
Bit 44 - 42: STBS[3..1]
These bits represent the sensor short to battery condition as follows:
STBS=’0’ => no fault;
STBS=’1’ => short to battery detected.
with the following association:
STBS1 => short to battery detected on SR pin;
STBS2 => short to battery detected on INRC pin;
STBS3 => short to battery detected on SNS, OUT or TG pins.
For detailed description of the fault detection refer to section Section 5.1
Bit 41 - 32: FV[9..0]
10 bit A/D conversion of FV pin voltage. For detailed description of the timing sequence
.
Bit 31 - 30: CB[1..0]
These are confirmation bits and their values is fixed, CB1=’1’, CB0=’0’; these bits can be used by the μ P to detect SPI data faults.
Bit 29 - 28: SPIF[1..2]
These bits indicate the presence of an SPI data fault, as described in the following table:
Table 8. SPI data fault
SPIF1 SPIF2 Description
1 0
1
SPI fault: SPI length error / data fault (CB error)
SPI fault: illegal SPI command
Bit 27 - 26:
Bits not used.
Bit 25 - 16: RCIMP1_[9..0]
10 bit A/D conversion of the output of RCT2 amplifier before the activation of RCT1 switch.
For detailed description of the timing sequence refer to
.
Bit 15: STGSNS
This bit represents the sensor short to ground condition on SNS pin as follows:
STGSNS=’0’ => no fault;
40/56 DocID026356 Rev 3
L9780 Digital interface description
STGSNS=’1’ => short to ground detected.
For detailed description of the fault detection refer to Section 5.2
.
Bit 14: CLAMP
This bit indicates the activation of VCCS clamp as follows:
CLAMP=’0’ => no activation;
CLAMP=’1’ => clamp activated.
For detailed description of the analog circuitry refer to
Bit 13: OCH
This bit represents the heater open circuit condition as follows:
OCH=’0’ => no fault;
OCH=’1’ => heater open circuit.
If the device detects a heater open circuit and then a short to ground condition without any fault clear frame between these 2 events, both OCH and STGH bits can be =’1’ in SPI output frame.
For detailed description of the fault detection refer to Section 5.4.3
.
Bit 12: STBH
This bit represents the heater short to battery condition as follows:
STBH=’0’ => no fault;
STBH=’1’ => heater short to battery.
For detailed description of the fault detection refer to s
.
Bit 11: STGH
This bit represents the heater short to ground condition as follows:
STGH=’0’ => no fault;
STGH=’1’ => heater short to ground.
For detailed description of the fault detection refer to Section 5.4.2
.
Bit 10: STGRC
This bit represents the sensor short to ground condition on INRC pin as follows:
STGRC=’0’ => no fault;
STGRC=’1’ => short to ground detected.
For detailed description of the fault detection refer to Section 5.2
Bit 9 - 0: RCIMP2_[9..0]
10 bit A/D conversion of the output of RCT2 amplifier while RCT1 switch is active. For detailed description of the timing sequence refer to
.
DocID026356 Rev 3 41/56
55
Digital interface description L9780
6.4.2 SPI output register (input echo configuration)
62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bit 63 – 0:
for the description of these bits.
42/56 DocID026356 Rev 3
L9780 Electrical characteristics
VCCD = VCCA = VCCCP = 4.9 V to 5.1 V, VCCI = 3.14 V to VCCD, R bg
T amb
=-40°C to 125/150°C; unless otherwise specified.
= 12.1 k ±1%,
Parameter
Table 9. Supplies and control inputs
Conditions Min.
Power supplies
VCCA + VCCD + VCCCP current
VCCS disabled
VCCS enabled, full load
VESD pin leakage current
Negative supply voltage (CP pin)
VESD voltage = 14.7V; T j
= 85 °C
VESD voltage = 40 V
CP current = 18 mA;
OUT, TG current = 0 mA
-
-
-
-
-VCCCP
Interface logic level supply current consumption (VCCI pin)
SO pin current = -800 μ A 0
POR (power on reset)
VCCA POR threshold
VCCA POR hysteresis
Release reset above this voltage
Issue reset below this voltage
-
VCCD, VCCCP POR threshold
Release reset above this voltage
Issue reset below this voltage
VCCD + VCCCP POR hysteresis -
GNDD, GNDCP loss detection Referred to GNDA
VCCA loss detection
GNDA loss detection
VCCD - VCCA
GNDA - GNDD
-
4.1
100
3.82
3.58
140
175
165
165
Current reference
Reference pin voltage (BG pin) 1.178
Logic levels (SI, CLK, CSN, PW, SY pins)
Input high voltage
Input low voltage
Input hysteresis
SI, CLK input leakage current
-
-
-
Vin = VCCI
0.1
-
-
0.3
Vin = from 0V to input low voltage max -1
Input pull-up current (CSN, PW pins)
Vin = from GNDA to input high voltage min
Input pull-down current (SY pin) Vin = from input low voltage min to VCCI
-50
10
Max.
4.6
4.45
300
4.22
3.98
440
225
215
215
0.7
-
-
1
-
30
40
5
20
-4.3
1
1.252
-10
50
Unit mA mA
μ A
μ A
V mA
V
VCCI
μ A
V
V mV
V
V mV mV mV mV
DocID026356 Rev 3 43/56
55
Electrical characteristics L9780
Parameter
Logic levels (SO pin)
Output low voltage
Table 9. Supplies and control inputs (continued)
Conditions Min.
Max.
Unit
Output high voltage
SO pin leakage current
SO current = 1.6 mA
VCCI = 4.9 V, SO current = -800 μ A
VCCI = 3.13 V, SO current = -100 μ A
Vin = VCCI or GNDA, tri state condition
-
VCCI – 0.8V -
-5
0.4
5
V
μ A
Table 10. INRC, RCT2 and integrator amplifiers, RCT1, INRC and band-gap switches, clean currents
Parameter Conditions Min.
Max.
Unit
INRC amplifier
Bias point (voltage measured on
C1A/B pin)
INRC pin voltage = 450 mV
GAIN
Output offset voltage
Output voltage swing
INRCGAIN bit = 0
-
INRCGAIN bit = 1
Maximum output voltage,
C1 pin current = -500 μ A
Minimum output voltage,
C1 pin current = 500 μ A
INRCPD bit = 1 INRC pull down current
RCT2 amplifier
GAIN
Output offset voltage
Output voltage swing
-
INRCGAIN = 0
Maximum output voltage, output current = -500 μ A
Minimum output voltage, output current = 500 μ A
Impedance test disabled RCT2 leakage current
Integrator amplifier
Input offset voltage
Open loop gain
Reference voltage (REF)
Input bias current (C2 pin)
Output voltage swing
-
-
-
C3 current = -500 μ A, C2 voltage < 0.9 *
REF voltage
C3 current = 500 μ A,
C2 voltage > 1.1 * REF voltage
1.842
4.137
2.079
-26
4.3
0
400
4.137
-26
4.3
0
-1
-8
100
1.848
-0.2
VCCA–0.3
0
1.937
4.242
2.121
26
VCCA
200
600
4.242
26
VCCA
200
1
8
-
1.932
0.2
VCCA
300
V
V/V
V/V mV
V mV
μ A
V/V mV
V mV
μ A mV dB
V
μ A
V mV
44/56 DocID026356 Rev 3
L9780 Electrical characteristics
Table 10. INRC, RCT2 and integrator amplifiers, RCT1, INRC and band-gap switches, clean currents (continued)
Parameter Conditions Min.
Max.
Unit
Parking voltage C3 voltage with VCCSEN bit = 0
REF2–
0.02
REF2+
0.02
V
RCT1 switch
On resistance
RCT1 bandgap switch
On resistance
Output voltage (RCT1 pin)
INRC switch
-
-
Charge balance mechanism activated
On resistance -
Output leakage current in off state
(C1 pin)
Charge balance mechanism activated
Clean currents
Clean current
Bits CCS[3..0] = 0000,
0 < INRC < VCCA
Bits CCS[3..0] = 0001,
0 < INRC < 2 V
Bits CCS[3..0] = 0010,
0 < INRC < 2 V
Bits CCS[3..0] = 0100,
0 < INRC < 2 V
Bits CCS[3..0] = 1000,
0 < INRC < 2 V
4
2
1.154
2.5
-1
-1
-15.4
-22
-44
-88
16
16
1.275
20
1
1
-12.6
-18
-36
-72
Ω
Ω
V
Ω
μ A
μ A
Table 11. FVOUT, scaling amplifiers, A/D conversion, RFV resistor
Parameter Conditions Min.
Max.
RFV resistor
RFV resistor value
FVOUT amplifier
3.75 6.25
GAIN
Bit SAMP[2..0] = 000; nominal gain = 1 0.995 1.005
Bit SAMP[2..0] = 001; nominal gain = 1.5 1.485 1.515
Bit SAMP[2..0] = 010; nominal gain = 2 1.98 2.02
Bit SAMP[2..0] = 011; nominal gain = 3
Bit SAMP[2..0] = 100; nominal gain = 4
Bit SAMP[2..0] = 101; nominal gain = 6
2.955
3.93
5.88
3.015
4.03
6.12
Unit k Ω
V/V
DocID026356 Rev 3 45/56
55
Electrical characteristics L9780
Table 11. FVOUT, scaling amplifiers, A/D conversion, RFV resistor (continued)
Parameter Conditions
GAIN
Bit SAMP[2..0] = 110; nominal gain = 8
Bit SAMP[2..0] = 111; nominal gain = 12
Input offset voltage -
Bias reference voltage ( REF2 )
Output voltage swing
Maximum output voltage, output current = -500 μ A
Minimum output voltage, output current = 500 μ A
Min.
Max.
Unit
7.84
11.7
VCCA –
0.2
8.16
12.18
V/V
-0.3 0.3 mV
0.498 0.502 VCCA
VCCA V
0 200 mV
Scaling amplifier
GAIN
Input offset voltage
A/D conversion
Bit SAMP[2..0] = 000; nominal gain = 1 0.995 1.005
Bit SAMP[2..0] = 001; nominal gain = 1.5 1.485 1.515
Bit SAMP[2..0] = 010; nominal gain = 2 1.98 2.02
Bit SAMP[2..0] = 011; nominal gain = 3
Bit SAMP[2..0] = 100; nominal gain = 4
Bit SAMP[2..0] = 101; nominal gain = 6
Bit SAMP[2..0] = 110; nominal gain = 8
Bit SAMP[2..0] = 111; nominal gain = 12
-
2.97
3.94
5.88
7.84
11.76
-0.3
3.03
4.04
6.12
8.16
12.24
0.3
V/V mV
INRC amplifier
VCCS current conversion
ADC error conversion
INRC pin voltage = 225 mV
INRC pin voltage = 400 mV
INRC pin voltage = 500 mV
FV pin voltage = 4.3 V
FV pin voltage = 3.85 V
FV pin voltage = 2.5 V
FV pin voltage = 1.15 V
FV pin voltage = 700 mV
Mean error after 8 A/D conversions
Maximum error for each conversion
180
324
407
863
775
508
221
125
-4
-2
207
364
453
898
802
515
248
160
4
2 cnts
Parameter
VCCS
SNS common mode range
Table 12. VCCS, PG1 (PG2) driver, Heater Fet driver
Conditions Min.
Design information -2
Max.
2.4
Unit
V
46/56 DocID026356 Rev 3
L9780 Electrical characteristics
RTOT maximum drop
|OUT voltage – SNS voltage|; design information
-
RTOT range
Gain
Max VCCS current
Design information
Δ I (OUT pin) / ( Δ V (C3 pin) * RTOT)
50
0.988
C3 voltage = 0V, RTOT = 0 12
C3 voltage = 5V, RTOT = 0 -20
VCCS leakage current (evaluated on OUT1, OUT2, SNS pins)
Bit VCCSEN = 0, OUT1 = OUT2 = SNS
= 0V, T = 150 °C
Bit VCCSEN = 0, OUT1 = OUT2 = SNS
= 5V, T = 150 °C
-5
-
Offset voltage
C3 voltage = REF2, VCCS offset voltage
= OUT voltage – SNS voltage
Voltage clamp error, positive limit CL1 (CL2) voltage – SNS voltage
Voltage clamp error, negative limit CL1 (CL2) voltage – SNS voltage
Output impedance -
Common mode gain
C3 voltage fixed, SNS pin moved,
Δ (OUT voltage – SNS voltage) / SNS voltage
TG switch on resistance
VCCS pull-down resistance
OUT differential current
Internal switch between TG and OUT pin
-
OUT current = 0mA; OUT current variation if SNS pin is moved from 0V to
-2 V or to 2.4 V
OUT current = ±12 mA; RTOT = 120 Ω ;
OUT current variation if SNS pin is moved from 0 V to -2 V (I=12 mA) or to
2.4 V (I=-12 mA)
OUT current = ±11 mA; RTOT = 97 Ω ;
OUT current variation if SNS pin is moved from 0 V to -2 V (I=11 mA) or to
2.4 V (I=-11 mA)
-0.7
-25
-50
100
-2
-
-
-
-
10
PG driver
Parameter
Table 12. VCCS, PG1 (PG2) driver, Heater Fet driver
Conditions Min.
PG pin output voltage
Pull-down resistor
Heater FET driver
PG current = -10 μ A
-
PG current = 10 μ A
VCCA -0.1
0
70
HG pin output voltage
Pull-down resistor
PG current = -10 μ A
-
PG current = 10 μ A
VCCA -0.2
0
70
5
2
4
21
7
40
20
VCCA
100
130
VCCA
100
130
0.7
25
50
-
Max.
1.8
300
1.012
20
-12
5 mV mV mV k Ω mV/V
Unit
V
Ω
V/V mA
μ A
Ω k Ω
μ A
V mV k Ω
V mV k Ω
DocID026356 Rev 3 47/56
55
Electrical characteristics L9780
Parameter
Table 13. Diagnostic
Conditions
Heater diagnostic
HD diagnostic current
HD diagnostic current
HG pin voltage threshold for on state of Heater FET
Heater short to ground threshold
(HSG)
-
Source current, HD = 3 V
Sink current, HD = 3 V
If HG voltage > specified value, Heater
FET is considered on
Heater short to battery threshold
Heater open circuit threshold
Bit STBHTH = 0
-
Bit STBHTH = 1
INRC, SR, SNS diagnostic
INRC short to ground threshold -
SNS short to ground threshold
SNS_PTH: positive threshold
SNS_NTH: negative threshold
Sensor short to battery threshold
STBS1: SR pin
STBS2: INRC pin
STBS3: SNS pin
Min.
160
68
3.88
0.715
0.76
225 275
400 450
HSG-0.45
HSG-0.01
175
175
-250
175
0.62
2.6
Max.
220
92
4.12
225
225
-150
225
0.66
2.8
Parameter
Table 14. Leakage currents
Conditions
Short to battery compatible pins
HD leakage current
SR + INRC sum of leakage currents
INRC + SR + SNS + TG1 + TG2
+ OUT1 + OUT2 sum of leakage currents
RCT1 + RCT2 sum of leakage currents
HD voltage = 53 V
Applied voltage on pins under test = 0 V,
19 V, T = 150 °
Applied voltage on pins under test = 0 V,
19 V, 40 V, T = 150 °C
Applied voltage on pins under test = 0 V,
19 V, T = 150 °C
Min.
0 150
- 3
-
Max.
- 20
3
Unit mV mV mV mV
VCCA
V
Unit
μ A
μ A
μ A
V
VCCA mV mV
V
48/56 DocID026356 Rev 3
L9780 Electrical characteristics
VCCD = VCCA = VCCCP = 4.9 V to 5.1 V, VCCI = 3.14 V to VCCD, R bg
T amb unless otherwise specified.
= 12.1 k Ω ±1%,
=-40 °C to 125/150 °C. Timing is considered with respect to 20 % and 70 % of VCCA
Table 15. AC parameters
Conditions Min.
Max.
Unit Parameter
Internal oscillator
Clock frequency ( FOSC )
POR (power on reset)
POR filter time
INRC amplifier
TOSC = 1/FOSC
-
3.8
10
4.2
20
MHz
μ s
1.5 - V/ μ s Slew rate
RCT2 amplifier
Slew rate
Integrator amplifier
Slew rate
FVOUT amplifier: S&H
Time constant
Voltage sag
Synchronization delay
Scaling amplifier: S&H
Time constant
Voltage sag
VCCS
En/disable sequence delay
Gate drivers
HG transition time
PG transition time
-
-
Sample mode
Hold mode
-
Sample mode
Hold mode
Hold mode
Rise time, 5nF load
Fall time
Fall time, diagnostic shutoff
Rise time, 5nF load
Fall time
1.5
1.5
-
0
30
30
0
0
0
-
0
0
4
-
-
1
0.5
16
1
0.5
50
50
200
1.5
200
V/ μ s
V/ μ s
μ s mV/ μ s
μ s
μ s mV/ μ s
TOSC
μ s
μ s ns
μ s ns
DocID026356 Rev 3 49/56
55
Electrical characteristics L9780
Parameter
Table 16. Timing
Conditions Min.
Max.
Heater PWM frequency
State machine clock (T smc
)
Design information
Bit MCP[1..0] = 00
Bit MCP[1..0] = 01
Bit MCP[1..0] = 10
0 600
RCT1 switch time (t
R
)
Bit MCP[1..0] = 11 nitp: decimal conversion of ITPT[6..0]; lower value limited by hardware to nitp = 25. No pulse if set to 0.
0 2*nitp
RCT1 band-gap switch time (t
B
) ncbt: decimal conversion of CBT[6..0]
INRC switch extension time
(t
INRC
) ninrc: decimal conversion of ISPT[2..0]
S&H settling time (t spl
) -
2*ncbt
960*ninrc
20
1024*ninrc
A/D conversion time (t
AD
) - 40 td1 14
Settling delay td2 16 td3 18
SY assertion time
SY de-assertion time
3
3 -
-
Integrator settling time
-
-
Time from VCCSEN de assertion to parking functionality activation
-
40000
80000
200000
400000
1
Parameter
Table 17. Diagnostic filter times
Conditions
Heater short to ground filter time
STBHFT[1..0] = 00
Heater short to battery filter time
STBHFT[1..0] = 01
STBHFT[1..0] = 10
STBHFT[1..0] = 11
Sensor short to battery filter time On SR, INRC, SNS pins
Sensor short to ground filter time On INRC, SNS pins
Min.
20
20
20
960
80
60
40
Max.
1024
81
61
41
21
21
24
Unit
Hz
T
OSC ms
Unit
T
OSC
50/56 DocID026356 Rev 3
L9780 Electrical characteristics
SPI data shift happens on rising edges. Logic timing parameters are defined in
Parameter
Table 18. Logic communications timing
Conditions Min.
Max.
Unit
Transfer frequency (f t
) -
CLK period (t
CLK
) -
Enable lead time (t enLEAD
) -
Enable lag time (t enLAG
) -
CLK high time (t
CLKH
) -
CLK low time (t
CLKL
) -
SI input setup time (t
SIS
) -
SI input hold time (t
SIH
) -
VCCI = 3.13 V; Cload = 50 pF
VCCI = 3.13 V; Cload = 100 pF
SO access time (t
SOA
)
VCCI = 4.75 V; Cload = 50 pF
VCCI = 4.75 V; Cload = 100 pF
SO disable time (t
SOD
) -
VCCI = 3.13 V; Cload = 50 pF
SO output valid time (t
SOV
)
VCCI = 3.13 V; Cload = 100 pF
VCCI = 4.75 V; Cload = 50 pF
VCCI = 4.75 V; Cload = 100 pF
SO output hold time (t
SOH
) -
CLK hold time (t
CLKHOLD
) -
CSN negated time (t
CSN
) -
375 -
50 -
50 -
15 -
20
- 340 ns
-
-
- 100
- 60
160
40
80
20 -
300 -
2 - μ s
Figure 11. SPI timing diagram
TEN,!' T#3.
#3.
TEN,%!$ T#,+( FT T#,+(/,$
#,+
3/
T3/!
-3"/54
T#,+,
T3/6
$!4!
T3/(
,3"/54
T3/$
$/.g4#!2%
3)
T3)3 T3)(
-3").
$!4!
,3").
DocID026356 Rev 3
*$3*36
51/56
55
Application circuit L9780
52/56
6##
Figure 12. Application circuit
,
6##!
6##$
6##
6###0
#!
#!
#
#"
#"
"ATTERY
6##
26%3$
#6## #6## #6## #6##
#6%3$
2"'
22#4
22#4
2EFERENCE
CELL
23.3
#3.3
#'.$
3.3
#2#4
#).2#
22#4
6%3$
"'
2#4
2#4
).2#
4'
4'
/54
3.3
/54
4!'
RESISTOR
0UMP
CELL 232
32
0'
(EATER
2($
0'
($
('
#,
#,
&,#0
&,#0
#0
&6/54
&6
#3.
#,+
3)
3/
07
39
434
434
'.$!
'.$$
'.$#0
#&,
##0
2&6/54
#&6/54
#&6
6##
0
6##
*$3*36
Table 19. External components value
Parameter
(1)
Min.
Typ.
Max.
Unit
CVCC* -
RVESD -
CVESD -
100 -
1 -
10 nF k Ω nF
RBG 11.979 12.1 12.221 k Ω
RRCT1 442 Ω
CRCT1 -
CINRC -
1
2.2
-
-
μ F nF
RSNS -
CSNS -
RRCT21 -
10 -
1 -
45.3 k Ω
μ F k Ω
DocID026356 Rev 3
L9780 Application circuit
Table 19. External components value (continued)
Parameter
(1)
Min.
Typ.
Max.
Unit
RRCT22 -
CGND -
RSR -
RHD -
CFL
(2)
CCP
-
CFV -
-
11 -
1 -
10 -
470 -
1 -
4.7 k Ω nF k
2 7.5 k
Ω
Ω nF
μ F
CFVOUT 0.1 10 100 nF
RFVOUT 5 7.5 k Ω
μ F
1. Not defined external components have values depending on the kind of sensor that has to be managed (as for compensation network components or VCCS external resistors) or depending on the value defined by the user (like for CL voltage dividers). TST pins have to be left open.
2. It is recommended to use ceramic capacitances and place them as close as possible to the part.
Figure 13. Sensor circuit
7* 5WJ
7* 5WJ
7$*
UHVLVWRU
287
616
5RX W
287 5RX W
Sensors value:
Sensor D: Rout = 301 Ω typ, Rtg = 0 Ω , TAG resistor 596 Ω ;
Sensor B: Rout = 61.9 Ω typ, Rtg = 0 Ω , TAG resistor 113 Ω ;
Sensor N: Rout = 137 Ω typ, Rtg = 221 Ω typ, TAG resistor 408 Ω .
*$3*36
DocID026356 Rev 3 53/56
55
Package information L9780
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
Figure 14. LQFP48 mechanical data and package dimensions
$)-
MM INCH
-).
490 -!8
-).
490 -!8
$
$
%
%
%
E
,
C
$
!
!
!
B
,
K
CCC
MIN TYP MAX
/54,).%!.$
-%#(!.)#!,$!4!
"ODY XXMM
,1&0
54/56 DocID026356 Rev 3
$
*$3*36
L9780 Revision history
Date
15-May-2014
01-Oct-2014
27-Nov-2014
Revision
Table 20. Document revision history
Changes
1
2
3
Initial release.
Updated
Table 4: Absolute maximum ratings on page 9 .
In the
Table 4: Absolute maximum ratings added ’TGx, OUTx’ at the
Parameter ‘SR, SNS’ of V in
,.
Updated for the parameter |TGx - OUTx| the value from +20 V to
DocID026356 Rev 3 55/56
55
L9780
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
56/56 DocID026356 Rev 3
Download
Public link updated
The public link to your chat has been updated. You may view and manage your chat links after registration here.
Document public link
Advertisement
