STMicroelectronics STWBC-MC Datasheet

STWBC-MC

Digital controller for wireless battery chargers transmitters for

Qi multicoil applications

Datasheet

-

production data

Features

 Digital controller for wireless battery charger transmitter

 Multi-coil inductive transmitters optimized for:

– Cell phones and smartphones

– Tablets and phablets

– Charging accessories

 Support for Wireless Power Consortium (WPC)

1.2 EPP applications

– Backward compatible with WPC BPP and

1.1 5W applications

 Support for half-bridge topology with DC/DC

 V

IN

range: 3 V to 5.5 V

– Supports USB V

IN

 Active presence detector

 Foreign object detection

 Q-factor measurement

 Parametric customization via GUI

 Turnkey firmware solution

 Peripherals

– 10-bit ADC

– UART interface

– I 2 C master fast/slow speed rate

– GPIOs

 Memory

– Flash and EEPROM with read-while-write

(RWW) and Error Correction Code (ECC)

– Program memory: 32 Kbytes Flash; data retention: 20 years at 55 °C after 1000 cycles at 55 °C

– Data memory: 1 Kbyte true data EEPROM; data retention: 20 years at 55 °C after 1000 cycles at 85 °C

– RAM: 6 Kbytes

 Transmitter reference design:

– Multi-coil EPP topology

– 2-layer PCBs

– Active object detection

– Graphical user interface for application monitoring

 Operating temperature: -40 °C up to 105 °C

 Package: VFQFPN32 5 x 5 mm

Table 1. Ordering information

Type Package

STWBC-MC

STWBC-MCTR

VFQFPN32, tube

VFQFPN32 tape and reel

July 2019

This is information on a product in full production.

DS12373 Rev 3 1/32 www.st.com

3

4

1

2

Contents

Contents

5

STWBC-MC

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

STWBC-MC system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STWBC-MC pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pins functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1

Power supplies: VDD, VDDA, VSS, VSSA, VOUT . . . . . . . . . . . . . . . . . . 10

4.2

DC/DC converter: DCDC_DRV, DCDC_DAC, CMP_OUT_V, CS_CMP,

DCDC_DAC_REF, DEMAGNET, VTARGET 10

4.3

Half-bridge driver: UPBL, DNBL, PWM_QFOD, WAVE_SNS . . . . . . . . . 10

4.4

Wireless power functions: TANK_VOLTAGE, ISENSE, COIL_TEMP,

SYMBOL_DETECT, CURRENT_DEMOD, QFOD_ADC 11

4.5

Input power supply management: VMAIN, STROBE_SR . . . . . . . . . . . . .11

4.6

External digital interface: UART_TX, UART_RX . . . . . . . . . . . . . . . . . . . 12

4.7

General purpose output: GPO_7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.8

Coil selection, LEDs and Quick Charge IO: I2C_SDA, I2C_SCL,

STROBE_SR 12

4.9

Debug: SWIM, NRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5

Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.6

Loading capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.7

Pin output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.8

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.9

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.9.1

5.9.2

VOUT external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/32 DS12373 Rev 3

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7

STWBC-MC

8

Contents

5.9.3

5.9.4

5.9.5

5.9.6

5.9.7

5.9.8

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Fast pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

I

2 C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10-bit SAR ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1

VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DS12373 Rev 3 3/32

32

List of tables

List of tables

STWBC-MC

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Flash program memory/data E

2

PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9.

Voltage DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10.

Current DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11.

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12.

I

2

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13.

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14.

ADC accuracy characteristic at V

DD

/V

DDA

= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 16.

VFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 17.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4/32 DS12373 Rev 3

STWBC-MC

List of figures

List of figures

Figure 1.

Wireless charging system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

STWBC-MC device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

STWBC-MC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4.

Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7.

External capacitor C

VOUT

Figure 8.

V

OH

Figure 9.

V

OL

Figure 10.

V

OH

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

standard pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

standard pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

standard pad at 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

standard pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11.

V

OL

Figure 12.

V

OH

Figure 13.

V

OL

Figure 14.

V

OH

Figure 15.

V

OL

fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

fast pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

fast pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 16.

ADC equivalent input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17.

ADC accuracy parameter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18.

VFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DS12373 Rev 3 5/32

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Description

1 Description

STWBC-MC

The STWBC-MC is the digital controller for the wireless battery charger (WBC) transmitters

(TX) from STMicroelectronics optimized for the extended power profile (EPP) Wireless

Power Consortium (WPC) multi-coil applications up to 15 W.

It offers the most flexible and efficient solution for controlling the power transfer to a receiver

(RX) in WBC-enabled applications such as smartphones, tablets and other battery-powered devices that use the electromagnetic induction for recharging.

The TX is responsible for controlling the transmitting coil and generating the correct amount of power requested by the RX. The RX continuously provides the transmitter with the correct power level requested, by modulating the transmitter carrier through the controlled resistive or capacitive load. Generating the correct amount of power ensures the highest level of endto-end efficiency due to reduced energy losses. It also helps maintaining a lower operational temperature.

The TX can adapt to the amount of energy transferred by the coil by modulating the frequency, duty cycle or amplitude of the PWM voltage on the transmitting coil.

The STWBC-MC is capable of bidirectional communication with the RX as specified by the

WPC 1.2 protocol.

Figure 1. Wireless charging system description

6/32

The STWBC-MC firmware is specifically designed to take advantage of the hardware to monitor and control the correct wireless charging operations.

DS12373 Rev 3

STWBC-MC

2 STWBC-MC system architecture

STWBC-MC system architecture

The STWBC-MC is a flexible controller that supports a half-bridge coil driver together with a

DC/DC controller, which regulates the input voltage of the bridge in order to control the amount of power transmitter to the receiver. It also controls the selection of the active coil for multi-coil topologies.

The digital controller also regulates the half-bridge operating frequency and duty cycle to further adjusting the amount of power increasing the overall efficiency at the light-load.

It implements the WPC 1.2 protocol, including foreign object detection (FOD) extensions. An accurate Q-factor measurement provides enhanced FOD.

The STWBC-MC is able to manage both the WPC baseline power profile (up to 5 W) and extended power profile (EPP).

Figure 2 illustrates the overall system blocks implemented in the STWBC-MC architecture.

Figure 2. STWBC-MC device architecture

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Firmware

The STWBC-MC firmware is available in a turnkey software package distributed as a binary file.

The STWBC-MC provides the UART communication interface, for external programming of parameters and STWBC-MC control.

DS12373 Rev 3 7/32

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STWBC-MC pinout and pin description

3 STWBC-MC pinout and pin description

This section shows the pinout used by the STWBC-MC.

Figure 3. STWBC-MC configuration

STWBC-MC

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Pin number

6

7

4

5

8

1

2

3

Pin name

UART_RX

PWM_QFOD

I2C_SDA

I2C_SCL

DNBL

STROBE_SR

GPO_7

CMP_OUT_V

Table 2. Pinout description

Pin type Description

DI

DO

DO

DO

DO

DO

DO

AI

UART RX link on USB debug connector

PWM dedicated to QFOD circuit

I2C_SDA used for coil selection

I2C_SCL used for coil selection

Output signal for HB low side driver

Strobe ouput for shift latch register

Digital ouput

Boost output voltage sensing

DS12373 Rev 3

".

STWBC-MC STWBC-MC pinout and pin description

15

16

17

18

19

24

25

26

27

28

29

30

31

32

Pin number

9

10

11

12

13

14

20

21

22

23

Table 2. Pinout description (continued)

Pin name

CS_CMP

DCDC_DAC_REF

WAVE_SNS

CURRENT_DEMOD

VDDA

VSSA

TANK_VOLTAGE

VTARGET

QFOD_ADC

COIL_TEMP

ISENSE

VMAIN

DCDC_DRV

DEMAGNET

SYMBOL_DETECT

DCDC_DAC

UPBL

DNBL_FB

SWIM

NRST

VDD

VSS

VOUT

UART_TX

Pin type Description

AI

AI

AI

AI

PS

PS

AI

AI

AI

AI

AI

Boost current sensing

DAC reference value for boost output voltage

Symbol detector based on delta frequency

Current demodulation

Analog power supply

Analog ground

Analog input to measure the LC voltage (power calculation)

Boost voltage measurement

High sensitivity peak voltage detector used for quality factor measurement

Analog input for temperature measurement. The input is connected to external NTC biased to the

VDD_STWBC

Analog input to measure the current flowing into the power bridge

Analog input to measure the main power supply

DCDC boost PWM drive

Transformer demagnetization sensing

Voltage demodulation

AI

DO

DI

DI

DO

DO

DI

DIO

DI

PS

Boost PWM output DAC (setting the CPP3 comparator voltage reference)

Output signal for HB high side driver

Hardware PWM feedback

Digital I/O for debug interface

Reset input monitoring

Digital and I/O power supply

PS Digital and I/O ground

Supply Internal LDO output

DO UART TX link on USB debug connector

Note: The operative voltage of analog inputs (AI) ranges from 0 V to 1.2 V.

DS12373 Rev 3 9/32

32

Pins functional description

4 Pins functional description

This section describes the functions related to the pins of the device.

4.1

4.2

4.3

STWBC-MC

Power supplies: VDD, VDDA, VSS, VSSA, VOUT

The digital portion of the STWBC-MC is powered using VDD and VSS (typically 4.5 V).

The analog portion of the STWBC-MC is powered using VDDA and VSSA (typically 4.5 V).

VDD and VDDA should be correctly filtered to allow the correct operation of the device.

The STWBC-MC generates its own internal power supply which needs a filter capacitor of

1 µF on the VOUT pin.

DC/DC converter: DCDC_DRV, DCDC_DAC, CMP_OUT_V,

CS_CMP, DCDC_DAC_REF, DEMAGNET, VTARGET

The STWBC-MC is designed to drive a DC/DC boost converter placed in front of the halfbridge coil driver. The DC/DC power switch (external NMOS) is driven by the DCDC_DRV pin through an output buffer.

The DC/DC inductor charging current is monitored using a sense resistor. The sense resistor has to be connected to the CS_CMP pin so that the STWBC-MC can detect current flowing into the inductor.

The DC/DC converter loop compares a reference target voltage applied on the

DCDC_DAC_REF pin with the feedback voltage connected to the CMP_OUT_V pin. The

CMP_OUT_V signal is a partition of the DC/DC output voltage.

The DCDC_DAC_REF reference voltage is variable in order to adjust the DC/DC output voltage depending on wireless power solution requirements. The DCDC_DAC_REF is generated by filtering the PWM signal present on the DCDC_DAC pin. A second order passive filter is required.

The DC/DC output voltage is monitored by the STWBC-MC using the VTARGET pin. The

VTARGET should be generated as a partition of the DCDC output voltage.

In order to enhance the efficiency at the medium and low load, the DC/DC converter can operate in the quasi-resonant mode. To do so, the STWBC-MC monitors the demagnetization of the inductor using the DEMAGNET pin.

Half-bridge driver: UPBL, DNBL, PWM_QFOD, WAVE_SNS

The power half-bridge is driven using UPBL and DNBL pins. The UPBL pin has to be connected to a high-side gate driver, while the DNBL pin has to be connected to a low-side gate driver for the power switches.

UPBL and DNBL pins are active high: when 1, the corresponding power switch has to be

ON.

10/32 DS12373 Rev 3

STWBC-MC Pins functional description

The STWBC-MC integrates a programmable deadtime between the active states of UPBL and DNBL avoiding simultaneous conduction of power switches. The external gate driver doesn't need to manage deadtime.

The STWBC-MC requires the following capability to be supported by the gate driver:

 UPBL = 0, DNBL = 0: in such case, the power half-bridge must be in the high impedance state.

 UPBL = 1, DNBL = 0: high side power switch must be ON.

 UPBL = 0, DNBL = 1: low side power switch must be ON.

 UPBL = 1, DNBL = 1: optional mode where both high and low side power switches must be ON (simultaneous conduction).

While the power half-bridge is driven with the UPBL and DNBL signals, a low energy drive is needed to run the coil quality factor estimation. For this function, the bridge is driven by using the PWM_QFOD pin instead of UPBL (UPBL is 0 during this operation). PWM_QFOD has to be connected to the low energy high side switch while DNBL is still used for the low side low impedance switch drive.

In many situation the STWBC-MC requires a ¼ wave synchronization with the LC tank connected to the half-bridge. A simple passive detector must be connected to the LC tank and the WAVE_SNS pin. The WAVE_SNS pin should be limited to a  0.6 V swing.

4.4

4.5

Wireless power functions: TANK_VOLTAGE, ISENSE,

COIL_TEMP, SYMBOL_DETECT, CURRENT_DEMOD,

QFOD_ADC

The STWBC-MC requires monitoring the peak voltage on the LC tank as well as the rectified current circulating in the tank. To do so, a peak voltage detector of the LC tank must be connected to the TANK_VOLTAGE pin and a filtered current sensor must be connected to the ISENSE pin .

For quality factor measurement, a high sensitivity peak voltage detector of the LC tank must be connected to the QFOD_ADC pin.

The STWBC-MC requires external signal conditioning blocks to pre-demodulate the WPC

Qi messages. One of this block detects the effect of modulation on the LC tank voltage and it must be connected to the SYMBOL_DETECT pin. Another block is required to detect the effect of modulation on the LC tank current and it must be connected to the

CURRENT_DEMOD pin.

For safety reason the STWBC-MC is capable to monitor the temperature of the transmitting coil. In order to do so, a NTC thermistor must be connected to the COIL_TEMP pin.

Input power supply management: VMAIN, STROBE_SR

The STWBC-MC monitors the input power supply voltage using the VMAIN pin. This voltage is used for optimum programming of the DCDC converter but also for the wireless power mode of the operation.

DS12373 Rev 3 11/32

32

Pins functional description

4.6 External digital interface: UART_TX, UART_RX

STWBC-MC

The STWBC-MC can be programmed and/or controlled using a 57600 bps, 8 bits, 1 start,

1 stop no-parity UART interface. The STWBC-MC UART TX output is present on the

UART_TX pin and the UART RX input is present on the UART_RX pin.

4.7 General purpose output: GPO_7

Not used.

4.8

4.9

Coil selection, LEDs and Quick Charge IO: I2C_SDA,

I2C_SCL, STROBE_SR

The STWBC-MC embeds an I²C master interface on I2C_SDA and I2C_SCL pins. This interface is used to select the active coil in a multi-coil TX system, with the aid of a GPIO expander, which is also used to drive two LEDs (typically red and green), and the USB

Quick Charge input voltage selection.

Specifically, the STWBC-MC is capable of requesting 12 V output voltage available from some USB wall adapters. While the USB wall adapter provides 5 V by default, using a specific signaling on the D+ and D- signals of the USB interface, 12 V can be obtained if supported. When 12 V is available, the STWBC-MC can provide up to 15W in the RX. The

GPIO expander output QC_IO interfaces with the USB connector through a simple circuitry.

The STROBE_SR output needs to be connected to the STROBE input of the GPIO expander.

Debug: SWIM, NRST

The SWIM pin may be used to interface with the STLINK/V2 debugger. The STWBC-MC can be reset using the active low NRST pin.

12/32 DS12373 Rev 3

STWBC-MC

5 Electrical characteristics

5.1

Electrical characteristics

Parameter conditions

Unless otherwise specified, all voltages are referred to V connected to the same voltage value. V

SS shortest wire loop.

and V

SS

. V

DDA

and V

DD

must be

SSA

must be connected together with a

5.2 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

A

= T

A

max. (given by

5.3

5.4

5.5

Typical values

Unless otherwise specified, typical data are based on T

A

= 25 °C, V

DD

and V

DDA

= 5 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range.

Typical curves

Unless otherwise specified, all typical curves are given as design guidelines only and are not tested.

Typical current consumption

For typical current consumption measurements, V

DD

shown in Figure 4

.

and V

DDA are connected together as

DS12373 Rev 3 13/32

32

Electrical characteristics

Figure 4. Supply current measurement conditions

STWBC-MC

5.6 Loading capacitors

The loading conditions used for the pin parameter measurement are shown in

Figure 5 .

Figure 5. Pin loading conditions

14/32 DS12373 Rev 3

STWBC-MC

5.7 Pin output voltage

The input voltage measurement on a pin is described in Figure 6

.

Figure 6. Pin input voltage

Electrical characteristics

5.8 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device reliability.

Table 3. Voltage characteristics

Symbol

V

DDX

- V

SSX

V

IN

V

DD

- V

DDA

Ratings

Supply voltage

(1)

Input voltage on any other pin

(2)

Variation between different power pins

V

SS

- V

SSA

Variation between all the different ground pins

(3)

Min.

-0.3

V

SS

-0.3

-

-

Max.

6.5

V

DD

+0.3

50

50

Unit mV mV

1. All power V power supply.

(V

DD

, V

DDA

) and ground V

SSX

(V

SS

, V

SSA

) pins must always be connected to the external

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V

IN

maximum is respected. If V

IN cannot be respected, the injection current must be limited externally to the I

INJ(PIN) injection is induced by V

IN

> V

DD

while a negative injection is induced by V

IN

< V

SS

maximum

value. A positive

.

3. V

SS

and V

SSA

signals must be interconnected together with a short wire loop.

V

DS12373 Rev 3 15/32

32

Electrical characteristics STWBC-MC

Symbol

Table 4. Current characteristics (1)

Ratings Max.

Unit

I

VDDX

I

VSSX

Total current into V

DDX

power lines

(2)

Total current out of V

SSX power lines

(2)

100

100

I

IO

Output current sunk by any I/Os and control pin

Ref. to Table 10 on page 21

mA

Output current source by any I/Os and control pin -

I

INJ(PIN)

(3)

,

(4)

I

INJ(TOT)

(3)

,

(4)

,

(5)

Injected current on any pin

Sum of injected currents

± 4

± 20

1. Data based on characterization results, not tested in production.

2. All power V power supply.

(V

DD

, V

DDA

) and ground V

SSX

(V

SS

, V

SSA

) pins must always be connected to the external

3. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V injection is induced by V

IN

> V

DD

IN

maximum is respected. If V

IN

while a negative injection is induced by V

IN

< V

SS

maximum

value. A positive

.

4. Negative injection disturbs the analog performance of the device.

5. When several inputs are submitted to a current injection, the maximum characterization with the 

IINJ(PIN)



IINJ(PIN

) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on

maximum current injection on four I/O port pins of the device.

Symbol

T

STG

T

J

Table 5. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Max.

-65 to 150

150

Unit

ºC

16/32 DS12373 Rev 3

STWBC-MC

5.9

Electrical characteristics

Operating conditions

The device must be used in operating conditions that comply with the parameters in Table 6

.

In addition, a full account must be taken for all physical capacitor characteristics and tolerances.

Symbol

Table 6. General operating conditions

Parameter Conditions Min.

Typ. Max. Unit f

CPU

V

DD1

, V

DDA1

V

DD

, V

DDA

Internal CPU clock frequency

Operating voltages

Nominal operating voltages

Core digital power supply

-

-

-

-

-

3

(1)

3.3

(1)

16

-

-

5 5.5

5

1.8

(2)

(1)

5

(1)

MHz

V

V

OUT

C

VOUT

: capacitance of external capacitor

(3)

ESR of external capacitor

(2)

ESL of external capacitor

(2)

at 1 MHz

-

-

470

0.05

-

-

-

-

3300 nF

0.2

15

 nH



JA

(4)

T

A

FR4 multilayer PCB

Ambient temperature

VFQFPN32

Pd = 100 mW

-

-40

26

-

°C/W

105 °C

1. The external power supply can range from 3 V to 5.5 V although IC performances are optimized for the power supply equal to 5 V.

2. Internal core power supply voltage.

3. Care should be taken when the capacitor is selected due to its tolerance, its dependency on temperature,

DC bias and frequency.

4. To calculate P

Dmax

(T

A

), use the formula P

Dmax

= (T

Jmax

- T

A

)/ 

JA

.

Symbol

Table 7. Operating conditions at power-up/power-down

Parameter Conditions Min Typ.

Max.

Unit

V

IT

+

V

IT

-

Power-on reset threshold

Brownout reset threshold -

2.65

2.58 2.73 2.88

V

HYS(BOR)

Brownout reset hysteresis -

1. VDD rise must be monotone. The slew rate should be between 1  V/  s and 0.5 V/  s.

2.8

70

2.98

-

(1)

(1)

V mV

DS12373 Rev 3 17/32

32

Electrical characteristics

5.9.1 VOUT external capacitor

STWBC-MC

The stabilization of the main regulator is achieved by connecting an external capacitor

C

VOUT

(a)

to the VOUT pin. The C

VOUT

is specified in Section 5.9: Operating conditions

.

Care should be taken to limit the series inductance to less than 15 nH.

Figure 7. External capacitor C

VOUT

18/32 a. ESR is the equivalent series resistance and ESL is the equivalent inductance.

DS12373 Rev 3

STWBC-MC

5.9.2

Electrical characteristics

Memory characteristics

Flash program and memory/data E

2

PROM.

General conditions: T

A

= -40 °C to 105 °C.

Symbol

Table 8. Flash program memory/data E

2

PROM

Parameter Conditions Min.

(1)

Typ.

(1)

Max.

(1)

t t

PROG

ERASE

Standard programming time

(Including erase) for byte/word/block

(1 byte/4 bytes/128 bytes)

Fast programming time for

1 block (128 bytes)

Erase time for 1 block

(128 bytes)

Erase/write cycles (2) program memory)

T

A

-

-

-

= 25 °C

-

-

-

10 K

6

3

3

-

6.6

3.3

3.3

-

N

WE

Erase/write cycles memory)

(2)

(data

T

A

= 85 °C

T

A

= 105 °C

100 K

35 K

-

-

-

t

RET

I

DDPRG

Data retention (program memory) after 10 K erase/write cycles at T

A

= 25 °C

Data retention (program memory) after 10 K erase/write cycles at T

A

= 25 °C

Data retention (data memory) after 100 K erase/write cycles at

T

A

= 85 °C

Data retention (data memory) after 35 K erase/write cycles at

T

A

= 105 °C

Supply current during program and erase cycles

T

T

T

T

RET

RET

RET

RET

-40 ºC 

= 85 °C

= 105 °C

= 85 °C

= 105 °C

T

A

 105 ºC

15

11

15

6

-

-

-

-

-

2 -

-

-

-

-

1. Data based on characterization results, not tested in production.

2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.

Unit ms ms

Cycles

Years mA

DS12373 Rev 3 19/32

32

Electrical characteristics

5.9.3 I/O port pin characteristics

STWBC-MC

The I/O port pin parameters are specified under general operating conditions for V

DD unless otherwise specified. Unused input pins should not be left floating.

and T

A

Symbol

Table 9. Voltage DC characteristics

Description Min.

(1)

Typ.

Max.

(1)

Unit

V

IL

V

IH

V

OL1

V

OL2

V

OL3

V

OH1

V

OH2

V

OH3

H

VS

R

PU

Input low voltage

Input high voltage

(2)

Output low voltage at 3.3 V

(3)

Output low voltage at 5 V

Hysteresis input voltage

Pull-up resistor

(3)

Output low voltage high sink at 3.3 V / 5 V

(2)

Output high voltage at 3.3 V

Output high voltage at 5 V

(6)

(3)

(3)

Output high voltage high sink at 3.3 V / 5 V

(2)

,

(5)

,

(5)

-0.3

0.7 * V

V

DD

-0.4

(4)

V

DD

-0.5

V

DD

-0.6

(4)

-

-

-

-

30

DD

-

-

-

-

0.6

-

-

-

(4)

0.1 * V

45

DD

0.3 * V

V

DD

0.4

(4)

0.5

-

-

-

-

-

60

DD

1. Data based on characterization result, not tested in production.

2. Input signals cannot exceed V

DDX

(V

DDX

= V

DD

, V

DDA

).

3. Parameter applicable to signals: PWM_QFOD, DNBL, LED, QC_IO, DCDC_DRV, DCDC_DAC, UPBL,

UART_TX.

4. Electrical threshold voltage not characterized at -40 ºC.

5. Parameter applicable to the signals: SWIM, DEMAGNET.

6. Applicable to any digital inputs.

V k 

20/32 DS12373 Rev 3

STWBC-MC Electrical characteristics

Symbol

Table 10. Current DC characteristics

Description Min.

Typ. Max.

(1)

Unit

I

OL1

I

OL2

I

OLhs1

I

OLhs2

I

OH1

I

OH2

I

OHhs1

I

OHhs2

I

LKg

I

_Inj



I_Inj

Standard output low level current at 3.3 V and V

OL1

(2)

Standard output low level current at 5 V and V

OL2

(2)

High sink output low level current at 3.3 V and V

OL3

(3)

High sink output low level current at 5 V and V

OL3

(3)

Standard output high level current at 3.3 V and V

OH1

(2)

Standard output high level current at 5 V and V

OLH2

(2)

High sink output high level current at 3.3 V and V

OH3

(3)

High sink output high level current at 5 V and V

OH3

(3)

Input leakage current digital - analog V

SS

 V

IN

 V

DD

(4)

Injection current (5) , (6)

Total injection current (sum of all I/O and control pins)

(5)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1.5

3

5

7.75

1.5

3

5

7.75

± 1

± 4

± 20

1. Data based on characterization result, not tested in production.

2. Parameter applicable to signals: PWM_QFOD, DNBL, LED, QC_IO, DCDC_DRV, DCDC_DAC, UPBL,

UART_TX.

3. Parameter applicable to the signals: SWIM, DEMAGNET.

4. Applicable to any digital inputs.

5. The maximum value must never be exceeded.

6. The negative injection current on TANK_VOLTAGE, VTARGET, QFOD_ADC, COIL_TEMP, ISENSE,

VMAIN pins have to be avoided since it affects ADC conversion accuracy.

mA

µA mA

DS12373 Rev 3 21/32

32

Electrical characteristics STWBC-MC

5.9.4 Typical output level curves

This section shows the typical output level curves measured on a single output pin for the three pad family present in the STWBC-MC device.

Standard pad

This pad class is associated to the following pins: I2C_SDA, I2C_SCL, LED, QC_IO,

SYMBOL_DETECT, SWIM, UART_TX.

.

Figure 8. V

OH

standard pad at 3.3 V Figure 9. V

OL

standard pad at 3.3 V

7EE7

7EE7

5Ÿ$

7EE7

5 Ÿ$

*PI <N">

Figure 10. V

OH

standard pad at 5 V

".

7EE7

5 Ÿ$

7EE7

5Ÿ$

7EE7

5 Ÿ$

*PM <N">

Figure 11. V

OL

standard pad at 5 V

".

*PI <N">

7EE7

5 Ÿ$

7EE7

5Ÿ$

7EE7

5Ÿ$

".

*PM <N">

7EE7

5 Ÿ$

7EE7

5Ÿ$

7EE7

5Ÿ$

".

22/32 DS12373 Rev 3

STWBC-MC Electrical characteristics

5.9.5 Fast pad

This pad class is associated to the PWM_QFOD, DNBL, DCDC_DRV, DCDC_DAC, UPBL pins.

Figure 12. V

OH

fast pad at 3.3 V Figure 13. V

OL

fast pad at 3.3 V

*PI <N">

Figure 14. V

OH

fast pad at 5 V

7EE7

5 Ÿ$

7EE7

5Ÿ$

7EE7

5 Ÿ$

M

".

7EE7

5 Ÿ$

7EE7

5Ÿ$

7EE7

5 Ÿ$

*PM <N">

Figure 15. V

OL

fast pad at 5 V

".

*PI <N">

7EE7

5 Ÿ$

7EE7

5Ÿ$

7EE7

5Ÿ$

".

*PM<N">

7EE7

5Ÿ$

7EE7

5Ÿ$

7EE7

5Ÿ$

".

DS12373 Rev 3 23/32

32

Electrical characteristics

5.9.6 Reset pin characteristics

STWBC-MC

Subject to general operating conditions for V

DD

and T

A

unless otherwise specified.

Symbol

Table 11. NRST pin characteristics

Parameter Conditions Min.

(1)

V

IL(NRST)

V

IH(NRST)

V

OL(NRST)

R

PU(NRST) t

IFP(NRST) t

INFP(NRST) t

OP(NRST)

NRST input low level voltage

NRST input high level voltage

(1)

NRST output low level voltage

(1)

NRST pull-up resistor

(2)

NRST input filtered pulse (3)

NRST not input filtered pulse

(3)

NRST output filtered pulse

(3)

(1)

I

OL

= 2 mA

-

-

-

-

-

-0.3

0.7 x V

1. Data based on characterization results, not tested in production.

2. The RPU pull-up equivalent resistor is based on a resistive transistor.

3. Data guaranteed by design, not tested in production.

-

30

-

500

15

DD

Typ.

-

-

40

-

-

-

-

Max.

(1)

0.3 x V

DD

V

DD

+ 0.3

0.5

60

75

-

-

Unit

V k  ns

µs

5.9.7 I

2

C interface characteristics

Symbol

Table 12. I 2 C interface characteristics

Standard mode

Parameter

Min.

(1)

Max.

(1)

Fast mode

Min.

(1)

Max.

(1)

Unit t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA)

t r(SCL) t f(SDA)

t f(SCL) t h(STA) t su(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time (V

DD

= 3.3 to 5 V)

(3)

SDA and SCL fall time (V

DD

= 3.3 to 5 V)

(3)

START condition hold time

Repeated START condition setup time

4.7

4.0

250

0

(2)

-

-

4.0

4.7

-

-

-

-

1000

300

-

-

1.3

0.6

100

0

(2)

-

-

0.6

0.6

-

900

(2)

300

300

-

-

-

-

µs ns

µs t su(STO)

STOP condition setup time 4.0

t w(STO:STA)

STOP to START condition time (bus free) 4.7

C b

Capacitive load for each bus line

(4)

-

1. Data based on standard I

2

C protocol requirement, not tested in production.

-

-

50

0.6

1.3

-

-

-

50

2. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time.

3. I

2

C multifunction signals require the high sink pad configuration and the interconnection of 1 k  pull-up resistances.

4. 50 pF is the maximum load capacitance value to meet the I 2 C std. timing specifications.

µs

µs pF

24/32 DS12373 Rev 3

STWBC-MC

5.9.8

Electrical characteristics

10-bit SAR ADC characteristics

The 10-bit SAR ADC parameters are specified under general operating conditions for V

DDA and T

A

unless otherwise specified.

Symbol

Table 13. ADC characteristics

Parameter Min.

Typ.

Max.

Unit

N

R

ADCIN

V

IN

V ref

Resolution

ADC input impedance

(1)

Input conversion voltage range

ADC main reference voltage

(3)

-

1

0

-

10

-

-

1.250

-

-

1.25

(1)

,

-

(2)

1. Maximum input analog voltage cannot exceed V

DD

/V

DDA

.

2. Exceeding the maximum voltage on TANK_VOLTAGE, VTARGET, COIL_TEMP, ISENSE, QFOD_ADC

signals has to be avoided since it may impact the ADC conversion accuracy defined in Table 14 .

3. ADC reference voltage at T

A

= 25 °C.

bit

M 

V

ADC accuracy characteristics

See

Figure 17

for more details about ADC accuracy parameter definition.

Symbol

Table 14. ADC accuracy characteristic at V

DD

/V

DDA

= 5 V

Parameter

Min.

(2)

Typ.

(1)

Max.

(2)

Unit

|E

O

|

|E

G

|

E

OG

E

OG

E

OG

|E

D

|

|E

L

|

Offset error

(3)

,

(4)

Gain error

(3)

,

(4)

,

(5)

Offset + gain error

(3)

,

(4)

,

(5)

,

(6)

Offset + gain error

(3)

Offset + gain error

(3)

,

(4)

,

(5)

,

(7)

,

(4)

,

(5)

Differential linearity error

(1)

Integral linearity error

(3)

,

(4)

,

(8)

,

(2) , (3)

-

-

-8.3

-10.9

-13.8

-

-

0.5

0.4

-

-

-

0.8

2.0

-

-

-

-

8.9

10.9

10.9

LSB

1. Operating temperature: T

A

= 25 °C .

2. Data based on characterization results, not tested in production.

3. ADC accuracy vs. negative injection current. The injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of #the conversion being performed on another analog input. It is recommended that a Schottky diode (pin to ground) should be added to standard analog pins which may potentially inject a negative current. Any positive injection current within the limits specified for

I

INJ(PIN) and  I

INJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy. The ADC accuracy parameters may be also impacted exceeding the ADC maximum input voltage V

IN

.

4. Results in manufacturing test mode.

5. Gain error evaluated with the two-point method.

6. Temperature operating range: 0 ºC  T

A

 85 ºC.

7. Temperature operating range: -25 ºC  T

A

 105 ºC.

8. Temperature operating range: -40 ºC  T

A

 105 ºC.

DS12373 Rev 3 25/32

32

Electrical characteristics

ADC equivalent input circuit

Figure 16

shows the ADC equivalent input circuit.

Figure 16. ADC equivalent input circuit

STWBC-MC

Figure 17. ADC accuracy parameter definitions

26/32 DS12373 Rev 3

STWBC-MC Electrical characteristics

E

T

= total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

E

O

= offset error: deviation between the first actual transition and the first ideal one.

E

OG

= offset + gain error (1-point gain): deviation between the last ideal transition and the last actual one.

E

G

= gain error (2-point gain): defined so that E

OG

= E

O deviation of the characteristic slope).

+ E

G

(parameter correlated to the

E

D

= differential linearity error: maximum deviation between actual steps and the ideal one.

E

L

= integral linearity error: maximum deviation between any actual transition and the end point correlation line.

DS12373 Rev 3 27/32

32

Thermal characteristics

6 Thermal characteristics

STWBC-MC

The STWBC-MC functionality cannot be guaranteed when the device is operating under the maximum chip junction temperature (T

Jmax

).

T

Jmax

, in degrees Celsius, may be calculated using the following equation:

T

Jmax

= T

Amax

+ (PD max

x 

JA

) where:

T

Amax is the maximum ambient temperature in °C



JA

is the package junction to ambient thermal resistance in °C/W

PD max is the sum of PINT max

and PI/O max

(PD max

= PINT max

+ PI/O max

)

PINT max is the product of I

DD

and V internal power.

DD

, expressed in Watts. This is the maximum chip

PI/O max

PI/O max

V

OH

/I

OH

represents the maximum power dissipation on output pins where:

=  (V

OL

* I

OL

) +  [(V

DD

- V

OH

) * I

OH

], taking into account the actual V

OL

/I

OL

and

of the I/Os at the low and high level.

Table 15. Thermal characteristics

Symbol Parameter Value



JA

Thermal resistance junction to ambient

(1)

26

1. Thermal resistance are based on JEDEC JESD51-2 with a 4-layer PCB in a natural convection environment.

Unit

°C/W

28/32 DS12373 Rev 3

STWBC-MC

7 Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

7.1 VFQFPN32 package information

Figure 18. VFQFPN32 package outline

DS12373 Rev 3 29/32

32

Package information

Note:

STWBC-MC

Symbol b

D

D2

E

A

A1

A3

E2 e

L ddd

Table 16. VFQFPN32 package mechanical data

Databook dimension (mm)

Min.

0.80

0

-

0.18

4.85

3.40

4.85

3.40

-

0.30

-

Typ.

0.90

0.02

0.20

0.25

5.00

3.45

5.00

3.45

0.50

0.40

-

Max.

1.00

0.05

-

0.30

5.15

3.50

5.15

3.50

0.55

0.50

0.08

VFQFPN stands for “Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead”.

Very thin profile: 0.80 < A  00 mm.

Details of the terminal 1 are optional, but must be located on the top surface of the package by using either a mold or marked features.

Package outline exclusive of any mold flashes dimensions and metal burrs.

30/32 DS12373 Rev 3

STWBC-MC

8 Revision history

Date

03-Jan-2018

07-Aug-2018

13-Jul-2019

Revision history

Table 17. Document revision history

Revision Changes

1

2

3

Initial release.

Document has been changed from internal to public.

Updated Table 2

,

Figure 3 and made changes to

Section 4

DS12373 Rev 3 31/32

32

STWBC-MC

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