STMicroelectronics STWBC Datasheet

STWBC

Digital controller for wireless battery charger (WBC) transmitters Qi

1.1.2 A11 certified, PMA compatible

Datasheet

-

production data

VFQFPN32



Memory

– Flash and E

2

PROM with read-while-write

(RWW) and error correction code (ECC)

– Program memory: 32 KBytes Flash; data retention 15 years at 85

°

C after 10 kcycles at 25

°

C

– Data memory: 1 KByte true data E

2

PROM; data retention:15 years at 85

°

C after 100 kcycles at 85

°

C

– RAM: 6 KBytes



Reference design features

– 2 layers PCBs

– Active object detection

– Graphical user interface for application monitoring

– Evaluation boards



Operating temperature: -40

°

C up to 105

°

C



Package: VFQFPN32

Features



Digital controller for wireless battery charger transmitter



Multiple Qi certified and PMA standard compatible



Support for up to 5 W applications

– Mobile

– Wearable, sports gear, medical

– Remote controllers



Native support to half-bridge and full bridge topologies



5 V supply voltage



2 firmware options

– Turnkey solution for quick design

– APIs available for application customization

(a)



Peripherals available via APIs

(a)

– ADC with 10 bit precision and 1 M



input impedance

– UART

– I

2

C master fast/slow speed rate

– GPIOs

Applications



Certified Qi A11

– Evaluation board: STEVAL-ISB027V1

– Power rate: 5W

– Input: 5V



Qi A13

(a)

– Power rate: 5 W

– Input: 5 - 16 V, 12 V



Wearable

(a)

– Power rate: 2 W

– Input: 5 V



PMA

(a)

– power rate: 5 W

– input: 5 V a. Contact local sale representative for further details: see www.st.com.

February 2015

This is information on a product in full production.

DocID027322 Rev 3 1/36

www.st.com

1

2

3

Contents

Contents

4

5

STWBC

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Introduction to wireless battery charging systems . . . . . . . . . . . . . . . . 8

Certified Qi A11 solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1

Pinout for STWBC in Qi A11 configuration . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Loading capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Pin output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

VOUT external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 18

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Typical output level curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Fast pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

I

2

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10-bit SAR ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.4

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.1

5.4.2

Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Static latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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9

STWBC

6

7

Contents

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1

Package design overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

DocID027322 Rev 3 3/36

36

List of tables

List of tables

STWBC

Table 1.

Table 2.

Table 3.

Table 4.

Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.

Table 6.

Table 7.

Table 8.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

HSI RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

LSI RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9.

PLL internal source clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10.

Flash program memory/data E

2

PROM memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11.

Voltage DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12.

Current DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13.

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14.

I

2

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 15.

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 16.

ADC accuracy characteristics at V

DD

Table 17.

ADC accuracy characteristics at V

DD

/V

DDA

/V

DDA

3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 18.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 19.

Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 20.

Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 21.

VFQFPN32 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 22.

Silicon product order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 23.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4/36 DocID027322 Rev 3

STWBC

List of figures

List of figures

Figure 1.

STWBC device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2.

System view of a wireless charging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3.

STWBC pinout view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4.

Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7.

External capacitor C

VOUT

Figure 8.

V

OH

Figure 9.

V

OL

Figure 10.

V

OH

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

standard pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

standard pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

standard pad at 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

standard pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 11.

V

OL

Figure 12.

V

OH

Figure 13.

V

OL

Figure 14.

V

OH

Figure 15.

V

OL

fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

fast pad at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

fast pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

fast pad at 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 16.

ADC conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17.

VFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DocID027322 Rev 3 5/36

36

Description

1 Description

STWBC

The STWBC is the digital controller for wireless battery charger (WBC) transmitters (TX) from STMicroelectronics, offering the most flexible and efficient solution for controlling power transfer to a receiver (RX) in WBC-enabled applications such as phones, wearables, and other battery powered devices that use electromagnetic induction for recharging.

As a member of the Qi Wireless Power Consortium and the PMA (Power Matters Alliance),

ST ensures full compatibility with these leading wireless charging protocols and holds certification for the Qi 1.1.2 A11 standard.

The STWBC performs all the functions for transmitter control: thanks to the internal 96 MHz clock and supporting both half-bridge and full bridge topologies, it is able to precisely control the amount of transmitted power to match the requirements of the receiving unit in terms of maximizing the efficiency of the power transfer.

The STWBC comes with firmware options to offer customers the ability to personalize their end product without the need of external microcontrollers:



A turnkey Qi 1.1.2 A11 certified solution, fully interoperable with Qi enabled mobile phones.



API (application programming interface) access to customize the underlying firmware, for example modifying the behavior of the LEDs or GPIOs in response to the receiver behavior and supporting I²C and UART communication within a network.

The STWBC Qi 1.1.2 A11 certified solution is available in the STMicroelectronics STEVAL-

ISB027V1 reference design, intended for all Qi compatible receivers such as in Qi enabled mobile phones.

In the reference design the STWBC integrates the foreign object detection (FOD): the digital feedback between TX and RX units allows the detection of metal objects close to the receiver that could result in potential hazards, enabling the STWBC to stop power transmission when such objects are detected.

The reference design is offered together with a complete ecosystem to support customers in building their applications, including the Qi 1.1.2 A11 certified board (STEVAL-ISB027V1),

API libraries and documentation to develop software customizations, as well as a comprehensive graphical user interface to monitor real-time performance and diagnostics.

6/36 DocID027322 Rev 3

STWBC

Figure 1. STWBC device architecture

Vbus Monitor

5V or 3.3V

V input

2x LED

ADC

GPIOs

UART

I2C

Customizable

Digital controller

Digital Bridge

Controller

Temperature

Protection

Topology specific

Firmware

(including Qi certification)

Overcurrent

Protection

Signal & Protocol

Demodulator

FOD

STWBC

Active Object detector

Description

DocID027322 Rev 3 7/36

36

Introduction to wireless battery charging systems

2

STWBC

Introduction to wireless battery charging systems

Wireless battery charging systems replace the traditional power supply cable by means of electromagnetic induction between a transmitting pad (TX) and a battery powered unit (RX), such as a mobile phone or a battery pack.

The power transmitter unit is responsible for controlling the transmitting coil and generating the correct amount of power requested by the receiver unit. The receiver unit continuously feedbacks to the transmitter the correct power level requested by modulating the transmitter carrier by means of a controlled resistive of capacitive insertion. Generating the correct amount of power guarantees the highest level of end-to-end efficiency due to reduced energy waste. Also, it helps maintaining a lower operational temperature.

The digital feedback is also used to detect foreign objects, i.e.: metal incorrectly exposed to the coils. By stopping the application as soon as a foreign object is detected the risk of damage is reduced.

Digital wireless battery transmitters can adapt the amount of energy transferred by the coil by modulating the frequency, duty cycles or coil input voltage.

Figure 2. System view of a wireless charging system

8/36

Thanks to the internal STWBC 96 MHz clock, support for half-bridge and full bridge topologies and protocol detection units, the STWBC can drive the power emitted by a transmitting coil. The STWBC firmware sits on the top of the hardware to monitor and control the correct wireless charging operations.

DocID027322 Rev 3

STWBC

3 Certified Qi A11 solution

Certified Qi A11 solution

The STWBC has been certified for Qi A11, thanks to the STEVAL-ISB027V1 reference design. The certification is based on the Qi standard version 1.1.2 and supports FOD

(“Foreign Object Detection”).

The STEVAL-ISB027V1 reference design provides a complete kit which includes the

STWBC IC, firmware, layout, graphical interfaces and tools. The layout is based on a costeffective 2-layer PCB.

Firmware

The STWBC firmware is available in two separate software packages:



Turn-key: the firmware is distributed as a binary file.



API customizable: the firmware is designed as a library and external functions as well as peripherals can be added by means of APIs.

The software APIs allow a great freedom of application customization. The STWBC and the

API library can be accessed by programming the internal controller via standard programming tools such as the IAR™ Workbench

®

Studio.

Every STWBC wireless charging architecture is a reference design supported by firmware, evaluation boards, application notes and PCB layouts notes.

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Pinout and pin description

4 Pinout and pin description

STWBC

The STWBC is a multifunction device that can support several wireless charging

architectures. The pinout is therefore application specific.

Section 4.1

shows the pinout used by the STWBC when the Qi A11 configuration is used.

4.1 Pinout for STWBC in Qi A11 configuration

Figure 3. STWBC pinout view

10/36 DocID027322 Rev 3

STWBC Pinout and pin description

11

12

13

14

15

16

Pin no.

1

2

18

19

20

8

9

3

4

5

6

7

10

17

21

22

23

24

25

26

27

Pin name

UART_RX

(1)

PWM_AUX/GPIO_2

(1)

I2C_SDA/DIGIN [4]

(1)

I2C_SCL/DIGIN [5]

(1)

DRIVEOUT [3]

GPIO_0

(1)

GPIO_1

(1)

CPP_INT_3

CPP_INT_2

CPP_REF

CPP_INT_1

CPP_INT_0

VDDA

VSSA

TANK_VOLTAGE

VBRIDGE

SPARE_ADC

(1)

NTC_TEMP

ISENSE

VMAIN

DRIVEOUT [0]

DIGIN [0]

(1)

DIGIN [1]

(1)

DRIVEOUT [1]

DRIVEOUT [2]

DIGIN [2]

(1)

SWIM

AI

AI

PS

PS

AI

DI

DO

DO

DO

DO

AI

AI

AI

AI

AI

AI

DO

DO

DO

DIO

Table 1. Pinout description

Pin type API firmware description Bin firmware description

UART RX link

PWM output or GPO

I2C_SDA / digital input 4

I2C_SCL / digital input 5

Output driver for low-side branch right

Digital output for the green light indicator / general purpose I/O

Digital output for the red light indicator / general purpose I/O

Symbol detector

UART RX link

Not used, must not be connected to any potential inactive (internal pull-up) inactive (internal pull-up)

Output driver for low-side branch right

Digital output for the green light indicator

Digital output for the red light indicator

Symbol detector

Vmain monitor Vmain monitor

External reference for CPP_INT_3

(if not used, must be tied to GND)

Symbol detector

External reference for CPP_INT_3

(if not used, must be tied to GND)

Symbol detector

Symbol detector

Analog power supply

Analog ground

Symbol detector

Analog power supply

Analog ground

LC tank voltage probe

Inactive (to be tied to GND)

LC tank voltage probe

Inactive (to be tied to GND)

Spare analog input (to be tied to

GND if not used)

Spare analog input (to be tied to

GND)

NTC temperature measurement.

NTC temperature measurement.

LC tank current measurement

Vmain monitor

Output driver for low-side branch left

Digital input 0

Digital input 1

Output driver for high-side branch left

Output driver for high-side branch right

Digital input 2

Debug interface

LC tank current measurement

Vmain monitor

Output driver for low-side branch left

Inactive (internal pull-up)

Inactive (internal pull-up)

Output driver for high-side branch left

Output driver for high-side branch right

Inactive (internal pull-up)

Debug interface

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Pinout and pin description

Pin no.

Pin name

28

29

30

31

32

1. API configurable.

NRST

VDD

VSS

VOUT

UART_TX

(1)

STWBC

Table 1. Pinout description (continued)

Pin type API firmware description

DI

PS

PS

Supply

DO

Reset

Digital and I/O power supply

Digital and I/O ground

Internal LDO output

UART TX link

Bin firmware description

Reset

Digital and I/O power supply

Digital and I/O ground

Internal LDO output

UART TX link

12/36 DocID027322 Rev 3

STWBC Electrical characteristics

5.1.1

Unless otherwise specified, all voltages are referred to V connected to the same voltage value. V

SS shortest wire loop.

and V

SS

. V

DDA

and V

DD

must be

SSA must be connected together with the

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

A

= T

A

max. (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in

Table 2

,

Table 3

and from

Table 5 on page 17

to

Table 17 on page 29

footnotes and are not tested in production.

Unless otherwise specified, typical data are based on T

A

= 25 °C, V

DD

and V

DDA

= 3.3 V.

They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range.

Unless otherwise specified, all typical curves are given as design guidelines only and are not tested.

For typical current consumption measurements, V

DD

shown in

Figure 4

.

and V

DDA are connected together as

DocID027322 Rev 3 13/36

36

Electrical characteristics

Figure 4. Supply current measurement conditions

STWBC

The loading conditions used for the pin parameter measurement are shown in

Figure 5

:

Figure 5. Pin loading conditions

14/36 DocID027322 Rev 3

STWBC

The input voltage measurement on a pin is described in

Figure 6

.

Figure 6. Pin input voltage

Electrical characteristics

5.2 Absolute maximum ratings

Stresses above those listed as 'absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device reliability.

Symbol

Table 2. Voltage characteristics

Ratings

V

DDX

- V

SSX

V

IN

V

DD

- V

DDA

V

SS

- V

SSA

Supply voltage

(1)

Input voltage on any other pin

(2)

Variation between different power pins

Variation between all the different ground pins

(3)

Min.

-0.3

VSS -0.3

V

ESD

Electrostatic discharge voltage

Max.

6.5

VDD +0.3

50

50

Unit

V mV

Refer to absolute maximum ratings

(electrical sensitivity) in

Section 5.4.1 on page 31

.

1. All power V power supply.

(V

DD

, V

DDA

) and ground V

SSX

(V

SS

, V

SSA

) pins must always be connected to the external

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V

IN

maximum is respected. If V cannot be respected, the injection current must be limited externally to the I injection is induced by V

IN

> V

DD

while a negative injection is induced by V

INJ(PIN)

IN

< V

IN

maximum

value. A positive

SS

.

3. V

SS

and V

SSA

signals must be interconnected together with a short wire loop.

DocID027322 Rev 3 15/36

36

Electrical characteristics STWBC

Symbol

Table 3. Current characteristics

Ratings Max.

(1)

Unit

I

VDDX

I

VSSX

Total current into VDDX power lines

(2)

Total current out of VSSX power lines

(2)

100

100

I

IO

Output current sunk by any I/Os and control pin

Ref. to

Table 11 on page 21

mA

Output current source by any I/Os and control pin

I

INJ(PIN)

(3)

,

(4)

I

INJ(TOT)

(3)

,

(4)

,

(5)

Injected current on any pin

Sum of injected currents

±4

±20

1. Data based on characterization results, not tested in production

2. All power V power supply.

(V

DD

, V

DDA

) and ground V

SSX

(V

SS

, V

SSA

) pins must always be connected to the external

3. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V injection is induced by V

IN

> V

DD

IN

maximum is respected. If V

IN

while a negative injection is induced by V

IN

< V

SS

maximum

value. A positive

.

4. Negative injection disturbs the analog performance of the device.

5. When several inputs are submitted to a current injection, the maximum positive and negative injected currents (instantaneous values). These results are based on characterization with



IINJ(PIN)



IINJ(PIN)

is the absolute sum of the

maximum current injection on four I/O port pins of the device.

Symbol

T

STG

T

J

Table 4. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Max.

-65 to 150

150

Unit

ºC

16/36 DocID027322 Rev 3

STWBC Electrical characteristics

The device must be used in operating conditions that respect the parameters in

Table 5

. In

addition, a full account must be taken for all physical capacitor characteristics and tolerances.

Symbol

Table 5. General operating conditions

Parameter Conditions Min.

Typ.

Max. Unit

V

DD1

, V

DDA1

V

DD

, V

DDA

Operating voltages

Nominal operating voltages

Core digital power supply

3

(1)

3.3

(1)

5.5

5

(1)

(1)

V

1.8

(2)

V

OUT

C

VOUT

: capacitance of external capacitor

(3)

ESR of external capacitor

(2)

ESL of external capacitor

(2) at 1 MHz

470

0.05

3300

0.2

nF





JA

(4)

T

A

FR4 multilayer PCB

Ambient temperature

VFQFPN32

Pd = 100 mW -40

26

105

°C/W

1. The external power supply can be within range from 3 V up to 5.5 V.

2. Internal core power supply voltage.

3. Care should be taken when the capacitor is selected due to its tolerance, its dependency on temperature,

DC bias and frequency.

4. To calculate P

Dmax

(T

A

), use the formula P

Dmax

= (T

Jmax

- T

A

)/



JA

.

°C

Symbol

Table 6. Operating conditions at power-up/power-down

Parameter

t

TEMP

V

IT

+

V

IT

-

Reset release delay

Power-on reset threshold

Brownout reset threshold

1. Guaranteed by design, not tested in production.

2. Power supply ramp must be monotone.

Conditions

V

DD rising

Min.

(1)

Typ. Max.

(2)

3

2.65

2.8

2.98

2.58

2.73

2.88

Unit

ms

V

DocID027322 Rev 3 17/36

36

Electrical characteristics

5.3.1 VOUT external capacitor

STWBC

The stabilization of the main regulator is achieved by connecting an external capacitor

C

VOUT

(b) to the VOUT pin. The C

VOUT

is specified in

Section 5.3: Operating conditions

.

Care should be taken to limit the series inductance to less than 15 nH.

Figure 7. External capacitor C

VOUT

5.3.2 Internal clock sources and timing characteristics

HSI RC oscillator

The HSI RC oscillator parameters are specified under general operating conditions for V

DD and T

A

.

Symbol Parameter

Table 7. HSI RC oscillator

Conditions

f

HSI

Frequency

ACC

HSI

Accuracy of HSI oscillator

(factory calibrated)

(1)

,

(2)

V

DD

T

A

= 3.3 V

= 25 ºC

V

DD

= 3.3 V

-40 ºC



T

A



105 ºC

V

DD

= 5 V

-40 ºC



T

A



105 ºC t

SU(HSI)

HSI oscillator wakeup time including calibration

1. Data based on characterization results, not tested in production.

2. Variation referred to f

HSI

nominal value.

Min.

(1)

-1%

-4%

-4%

Typ.

Max.

(1)

16

Unit

MHz

1

+1%

+4%

+4%

%

µs

18/36 b. ESR is the equivalent series resistance and ESL is the equivalent inductance.

DocID027322 Rev 3

STWBC Electrical characteristics

LSI RC oscillator

The LSI RC oscillator parameters are specified under general operating conditions for V

DD and T

A

.

Symbol Parameter

Table 8. LSI RC oscillator

Conditions

f

LSI

Frequency

ACC

LSI

Accuracy of LSI oscillator t

SU(LSI)

LSI oscillator wakeup time

1. Guaranteed by design, not tested in production.

3.3 V



V

DD



5 V

-40 ºC



T

A



105 ºC

Min.

(1)

Typ.

Max.

(1)

Unit

153.6

kHz

-10%

7

10% %

µs

PLL internal source clock

Symbol

Table 9. PLL internal source clock

Parameter Conditions

f

IN f

OUT t lock

Input frequency

PLL lock time

(2)

Output frequency

3.3 V



V

-40 ºC



T

A

DD



5 V



105 ºC

1. Data based on characterization results, not tested in production.

2. PLL maximum input frequency 16 MHz.

Min Typ.

Max.

(1)

Unit

16

96

MHz

200 µs

DocID027322 Rev 3 19/36

36

Electrical characteristics STWBC

Flash program and memory/data E

2

PROM memory

General conditions: T

A

= -40 °C to 105 °C.

Table 10. Flash program memory/data E

2

PROM memory

Parameter Conditions Min.

(1)

Typ.

(1)

Max.

(1)

Symbol Unit

t t

PROG

ERASE

Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes)

Fast programming time for 1 block (128 bytes)

Erase time for 1 block (128 bytes)

Erase/write cycles(

(2)

(program memory)

6

3

3

6.6

3.3

3.3

ms ms

N

WE

Erase/write cycles

(2)

(data memory)

T

A

= 25 °C

T

A

= 85 °C

T

A

= 105 °C

10 K

100 K

35 K

Cycles t

RET

I

DDPRG

Data retention (program memory) after 10 K erase/write cycles at T

A

= 25 °C

Data retention (program memory) after 10 K erase/write cycles at T

A

= 25 °C

Data retention (data memory) after 100 K erase/write cycles at T

A

= 85 °C

Data retention (data memory) after 35 K erase/write cycles at T

A

= 105 °C

Supply current during program and erase cycles

T

T

T

T

RET

RET

RET

RET

-40 ºC



= 85 °C

= 105 °C

= 85 °C

= 105 °C

T

A



105 ºC

15

11

15

6

2

Years mA

1. Data based on characterization results, not tested in production.

2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.

20/36 DocID027322 Rev 3

STWBC Electrical characteristics

5.3.4 I/O port pin characteristics

The I/O port pin parameters are specified under general operating conditions for V

DD unless otherwise specified. Unused input pins should not be left floating.

and T

A

Symbol

Table 11. Voltage DC characteristics

Description Min.

(1)

Typ.

V

IL

V

IH

V

OL1

V

OL2

V

OL3

V

OH1

V

OH2

V

OH3

H

VS

R

PU

Input low voltage

Input high voltage

(2)

Output low voltage at 3.3 V

(3)

Output low voltage at 5 V

Hysteresis input voltage

Pull-up resistor

(3)

Output low voltage high sink at 3.3 V / 5 V

(2)

,

(5)

Output high voltage at 3.3 V

Output high voltage at 5 V

(7)

(3)

(3)

Output high voltage high sink at 3.3 V / 5 V

(2)

,

(6)

,

(5)

,

(6)

0.7 * V

V

DD

-0.3

DD

- 0.4

(4)

V

DD

- 0.5

V

DD

- 0.6

(4)

0.1 * V

30

DD

1. Data based on characterization result, not tested in production.

2. All signals are not 5 V tolerant (input signals can't be exceeded V

DDX

(V

DDX

= V

DD

, V

DDA

).

3. Parameter applicable to signals: GPIO_[0:2], DRIVEOUT[0:3], PWM_AUX.

4. Electrical threshold voltage not yet characterized at -40 ºC.

5. Parameter applicable to signal: SWIM.

6. Parameter applicable to signal: DIGIN [0].

7. Applicable to any digital inputs.

0.6

(4)

45

Max.

(1)

0.3 * V

DD

V

DD

0.4

(4)

0.5

60

Unit

V k



DocID027322 Rev 3 21/36

36

Electrical characteristics STWBC

Symbol

Table 12. Current DC characteristics

Description Min.

Typ.

Max.

(1)

Unit

I

OL1

I

OL2

I

OLhs1

I

OLhs2

I

OH1

I

OH2

I

OHhs1

I

OHhs2

I

LKg

I_ lnj



I_ lnj

Standard output low level current at 3.3 V and V

OL1

(2)

Standard output low level current at 5 V and V

OL 2

(2)

High sink output low level current at 3.3 V and V

OL3

(3)

,

(4)

High sink output low level current at 5 V and V

OL

(3)

,

(4)

Standard output high level current at 3.3 V and V

OH1

(2)

Standard output high level current at 5 V and V

OLH2

(2)

High sink output low level current at 3.3 V and V

OH3

(3)

,

(4)

High sink output low level current at 5 V and V

OH3

(3)

,

(4)

Input leakage current digital - analog V

SS



V

IN



V

DD

(5)

Injection current

(6)

,

(7)

Total injection current (sum of all I/O and control pins)

(6)

1.5

3

5

7.75

1.5

3

5

7.75

± 1

±4

± 20

1. Data based on characterization result, not tested in production.

2. Parameter applicable to signals: GPIO_[0:2], DRIVEOUT[0:3], PWM_AUX.

3. Parameter applicable to signal: SWIM.

4. Parameter applicable to signal: DIGIN [0].

5. Applicable to any digital inputs.

6. Maximum value must never be exceeded.

7. Negative injection current on the ADCIN [7:0] signals (product depending) => SPARE_ADC signals have to avoid since impact the ADC conversion accuracy.

mA



A mA

22/36 DocID027322 Rev 3

STWBC

5.3.5

Electrical characteristics

Typical output level curves

This section shows the typical output voltage level curves measured on a single output pin for the two-pad family present in the STWBC device.

Standard pad

This pad is associated to the following signals: DIGIN [0:1], SWIM and GPIO_[0:2] when available.

Figure 8. V

OH

standard pad at 3.3 V

Figure 9. V

OL

standard pad at 3.3 V

DocID027322 Rev 3 23/36

36

Electrical characteristics

Figure 10. V

OH

standard pad at 5 V

STWBC

Figure 11. V

OL

standard pad at 5 V

24/36 DocID027322 Rev 3

STWBC Electrical characteristics

This pad is associated to the DRIVEOUT[0:3], PWM_AUX signals if the external pin is available.

Figure 12. V

OH

fast pad at 3.3 V

Figure 13. V

OL

fast pad at 3.3 V

DocID027322 Rev 3 25/36

36

Electrical characteristics

Figure 14. V

OH

fast pad at 5 V

STWBC

Figure 15. V

OL

fast pad at 5 V

26/36 DocID027322 Rev 3

STWBC Electrical characteristics

The reset pin parameters are specified under general operating conditions for V

DD unless otherwise specified.

and T

A

Symbol

Table 13. NRST pin characteristics

Parameter Conditions

V

IL(NRST)

V

IH(NRST)

V

OL(NRST)

R

PU(NRST) t

IFP(NRST) t

INFP(NRST) t

OP(NRST)

NRST input low level voltage

NRST input high level voltage

(1)

NRST output low level voltage

(1)

NRST pull-up resistor

(2)

NRST input filtered pulse

(3)

NRST not input filtered pulse

(3)

NRST output filtered pulse

(3)

(1)

I

OL

= 2 mA

1. Data based on characterization results, not tested in production.

2. The RPU pull-up equivalent resistor is based on a resistive transistor.

3. Data guaranteed by design, not tested in production.

Min.

(1)

-0.3

0.7 x V

DD

30

500

15

Typ.

40

Max.

(1)

0.3 x V

DD

V

DD

+ 0.3

0.5

60

75

Unit

k

V

 ns

µs

5.3.8 I

2

C interface characteristics

Symbol

Table 14. I

2

C interface characteristics

Parameter

Standard mode

Min.

(1)

Max.

(1)

Fast mode

Min.

(1)

Max.

(1)

t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA)

t r(SCL) t f(SDA)

t f(SCL) t h(STA) t su(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time (VDD = 3.3 to 5 V)

(3)

SDA and SCL fall time (VDD = 3.3 to 5 V)

(3)

START condition hold time

Repeated START condition setup time

4.7

4.0

250

0

(2)

4.0

4.7

1000

300

1.3

0.6

100

0

(2)

0.6

0.6

900

(2)

300

300 t su(STO)

STOP condition setup time 4.0

t w(STO:STA)

STOP to START condition time (bus free)

C b

Capacitive load for each bus line

(4)

1. Data based on standard I

2

C protocol requirement, not tested in production.

4.7

50

0.6

1.3

50

2. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time

3. I

2

C multifunction signals require the high sink pad configuration and the interconnection of 1 K pull-up resistances.

4. 50 pF is the maximum load capacitance value to meet the I

2

C std timing specifications.

Unit

µs ns

µs

µs

µs pF

DocID027322 Rev 3 27/36

36

Electrical characteristics

5.3.9 10-bit SAR ADC characteristics

STWBC

The 10-bit SAR ADC oscillator parameters are specified under general operating conditions for V

DDA

and T

A

unless otherwise specified.

Symbol Parameter

Table 15. ADC characteristics

Conditions Min.

Typ.

Max.

Unit

R

N

ADCIN

V

V

IN1 ref

Resolution

ADC input impedance

Conversion voltage range for gain x1

ADC main reference voltage

(3)

1

0

10

1.250

1.25

(1)

,

(2)

1. Maximum input analog voltage cannot exceed V

DDA

.

2. Exceeding the maximum voltage on the SPARE_ADC signals for the related conversion scale must be avoided since the ADC conversion accuracy can be impacted.

3. ADC reference voltage at T

A

= 25 °C.

bit

M



V

ADC accuracy characteristics at V

DD

/V

DDA

3.3 V

Symbol

Table 16. ADC accuracy characteristics at V

DD

/V

DDA

3.3 V

Parameter Typ.

(1)

Min.

(2)

Max.

(2)

Unit

|E

T

|

|E

O

|

|E

G

|

E

O+G

E

O+G

E

O+G

|E

D

|

|E

L

|

Total unadjusted error

(3)

Offset error

(3)

,

(4)

,

(5)

Gain error

(3)

,

(4)

,

(5)

,

(6)

Offset + gain error

(6)

,

(7)

Offset + gain error

(6)

,

(8)

Offset + gain error

(6)

,

(9)

Integral linearity error

(3)

,

,

(4)

,

(5)

Differential linearity error

(1)

,

(2)

(4)

,

(5)

,

(3)

2.8

0.3

0.4

0.5

1.4

-8.5

-11

-14.3

9.3

11

11.3

LSB

1. Temperature operating: T

A

= 25 °C.

2. Data based on characterization results, not tested in production.

3. ADC accuracy vs. negative injection current. Injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of the conversion being performed on another analog input. It is recommended a Schottky diode (pin to ground) to be added to standard analog pins which may potentially inject the negative current. Any positive injection current within the limits specified for

I

INJ(PIN) and



INJ(PIN)

in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC accuracy parameters may be also impacted exceeding the ADC maximum input voltage V

IN1

or V

IN2

.

4. Results in manufacturing test mode.

5. Data aligned with trimming voltage parameters.

6. Gain error evaluation with the two point method.

7. Temperature operating range: 0 ºC



T

A



85 ºC.

8. Temperature operating range: -25 ºC



T

A



105 ºC.

9. Temperature operating range: -40 ºC



TA



105 ºC.

28/36 DocID027322 Rev 3

STWBC Electrical characteristics

ADC accuracy characteristics at V

DD

/V

DDA

5 V

Symbol

Table 17. ADC accuracy characteristics at V

DD

/V

DDA

5 V

Parameter Typ.

(1)

Min.

(2)

Max.

(2)

Unit

|E

T

| Total unadjusted error

(3)

|E

O

|

Offset error

(3)

,

(4)

,

(5)

|E

G

| Gain error

(3)

,

(4)

,

(5)

,

(6)

E

O+G

Offset + gain error

(6)

,

(7)

E

O+G

Offset + gain error

(6)

,

(8)

EO+G

Offset + gain error

(6)

,

(9)

(4)

,

(5)

|E

D

| Differential linearity error

(1)

,

(2)

,

(3)

|E

L

| Integral linearity error

(3)

,

(4)

,

(5)

TBD

0.5

0.4

0.8

2.0

-8.3

-10.9

-13.8

8.9

10.9

10.9

LSB

1. Temperature operating: TA= 25 °C.

2. Data based on characterization results, not tested in production.

3. ADC accuracy vs. negative injection current. Injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of the conversion being performed on another analog input. It is recommended a Schottky diode (pin to ground) to be to added to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I and

 parameters may be also impacted exceeding the ADC maximum input voltage V

IN1 or V

IN2

.

INJ(PIN)

IINJ(PIN) in the I/O port pin characteristic section does not affect the ADC accuracy. The ADC accuracy

4. Results in manufacturing test mode.

5. Data aligned with trimming voltage parameters.

6. Gain error evaluation with two point method.

7. Temperature operating range: 0 ºC



T

A



85 ºC.

8. Temperature operating range: -25 ºC



T

A



105 ºC.

9. Temperature operating range: -40 ºC



TA



105 ºC. 11.

DocID027322 Rev 3 29/36

36

Electrical characteristics

ADC conversion accuracy

Figure 16. ADC conversion accuracy

STWBC

30/36

ADC accuracy parameter definitions:



E

T

= total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.



E

O

= offset error: deviation between the first actual transition and the first ideal one.



E

OG

= offset + gain error (1-point gain): deviation between the last ideal transition and the last actual one.



E

G

= gain error (2-point gain): defined so that EOG = EO + EG (parameter correlated to the deviation of the characteristic slope).



E

D

= differential linearity error: maximum deviation between actual steps and the ideal one.



E

L

= integral linearity error: maximum deviation between any actual transition and the end point correlation line.

DocID027322 Rev 3

STWBC Electrical characteristics

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts * (n + 1) supply pin).

Symbol

Table 18. ESD absolute maximum ratings

Ratings Conditions

Maximum value

Unit

V

ESD(HBM)

V

ESD(CDM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

V

ESD(MM)

Electrostatic discharge voltage

(machine model)

T

A

= 25 °C, conforming to

JEDEC/JESD22-A114E

T

A

= 25 °C, conforming to

ANSI/ESD STM 5.3.1 ESDA

T

A

= 25 °C, conforming to

JEDEC/JESD-A115-A

2000

500

200

V

Data based on characterization results, not tested in production.

Two complementary static tests are required on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power supply pin) and a current injection (applied to

THE each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard.

Symbol

LU

Table 19. Electrical sensitivity

Parameter Conditions

Static latch-up class T

A

= 105 °C

Level

A

DocID027322 Rev 3 31/36

36

Thermal characteristics STWBC

The STWBC functionality cannot be guaranteed when the device operating exceeds the maximum chip junction temperature (T

Jmax

).

T

Jmax

, in °C, may be calculated using equation:

T

Jmax

= T

Amax

+ (P

Dmax x



J

A

) where:

T

Amax

is the maximum ambient temperature in °C



J

A

is the package junction to ambient thermal resistance in °C/W

P

Dmax is the sum of P

INTmax and P

I/Omax

(P

Dmax

= P

INTmax

+ PI/O max

)

P

INTmax

power.

is the product of I

DD

and V

DD

, expressed in watts. This is the maximum chip internal

P

I/Omax

represents the maximum power dissipation on output pins where:

P

I/Omax

=



(V

OL

* I

OL

) +



[(V

DD

- V

OH

) * I

OH

], taking into account the actual V

OL

/I

OL

and V

OH

/I

OH

of the I/Os at the low and high level.

Symbol

Table 20. Package thermal characteristics

Parameter Value Unit



JA

VFQFPN32 - thermal resistance junction to ambient

(1)

26 °C/W

1. Thermal resistance is based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

32/36 DocID027322 Rev 3

STWBC Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at:

www.st.com

.

ECOPACK is an ST trademark.

Figure 17. VFQFPN32 package outline

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36

Package information

7.2

Note:

Package mechanical data

Symbol

b

D

D2

E

A

A1

A3

E2 e

L ddd

Table 21. VFQFPN32 package mechanical data

Dimensions (mm)

Min.

0.80

0

0.18

4.85

3.40

4.85

3.40

0.30

Typ.

0.90

0.02

0.20

0.25

5.00

3.45

5.00

3.45

0.50

0.40

Max.

1.00

0.05

3.50

0.55

0.50

0.08

0.30

5.15

3.50

5.15

STWBC

1. VFQFPN stands for “Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead”.

2. Very thin profile: 0.80 < A ≤ 1.00 mm.

3. Details of the terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features.

4. Package outline exclusive of any mold flashes dimensions and metal burrs.

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STWBC Order codes

Order code

STWBC

STWBCTR

Table 22. Silicon product order code

Package

VFQFPN32

Packaging

Tube

Tape and reel

Date

18-Dec-2014

23-Feb-2015

26-Feb-2015

Table 23. Document revision history

Revision Changes

1

2

3

Initial release.

Updated main title

on page 1

.

Updated

Section : Applications on page 1

(added

“certified” to Qi A11).

Added

Section 3: Certified Qi A11 solution on page 9

.

Updated

Figure 3: STWBC pinout view on page 10

(updated title, replaced by new figure).

Updated

Table 1: Pinout description on page 11

(replaced by new table).

Added

Section 5: Electrical characteristics on page 13

and

Section 6: Thermal characteristics on page 32

.

Minor modifications throughout document.

Updated main title

on page 1

.

Updated

Section : Features on page 1

(minor modifications).

Updated

Section 1: Description on page 6

(replaced by

new Description).

Added

Section 2: Introduction to wireless battery charging systems on page 8

(added title and Description from rev. 2, updated title of

Figure 2

).

Removed Section “2 STWBC system architecture” from page 7 (

Figure 2 on page 8

moved to

Section 1:

Description

).

Updated

Section 3: Certified Qi A11 solution on page 9

(renumbered headings).

Minor modifications throughout document.

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36

STWBC

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2015 STMicroelectronics – All rights reserved

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