STMicroelectronics M24256-DR Datasheet
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M24256-BW M24256-BR M24256-BF
M24256-DR M24256-DF
Datasheet
256-Kbit serial I²C bus EEPROM
TSSOP8 (DW)
169 mil width
WLSCP (CU)
SO8N (MN)
150 mil width
UFDFPN8 (MC)
DFN8 - 2x3 mm
WLSCP (CS)
Unsawn wafer
Product status link
M24256-BF
M24256-DF
M24256-BR
M24256-DR
M24256-BW
Features
• Compatible with following I 2 C bus modes:
– 1 MHz
– 400 kHz
– 100 kHz
• Memory array:
– 256 Kbit (32 Kbyte) of EEPROM
– Page size: 64 byte
– Additional write lockable page (M24256-D order codes)
• Single supply voltage and high speed:
– 1 MHz clock from 1.7 V to 5.5 V
• Write:
– Byte write within 5 ms
– Page write within 5 ms
• Operating temperature range:
– from -40 °C up to +85 °C
• Random and sequential read modes
• Write protect of the whole memory array
• Enhanced ESD/latch-Up protection
• More than 4 million write cycles
• More than 200-years data retention
Packages
• RoHS-compliant and Halogen-free (ECOPACK2)
• SO8 ECOPACK2
• TSSOP8 ECOPACK2
• UFDFPN8 ECOPACK2
• WLCSP ECOPACK2
• Unsawn wafer (each die is tested)
DS1766 - Rev 35 - November 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
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Description
Description
The M24256 is a 256-Kbit I 2 C-compatible EEPROM (electrically erasable programmable memory) organized as
32 K × 8 bits.
The M24256-BW can operate with a supply voltage from 2.5 V to 5.5 V, the M24256-BR AND M24256-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M24256-BF and M24256-DF can operate with a supply voltage from 1.7 V to 5.5 V. All these devices operate with a clock frequency of 1 MHz (or less), over an ambient temperature range of –40 °C / +85 °C. The M24256-D offers an additional page, named the identification page
(64 byte). The identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode.
Figure 1. Logic diagram
VCC
E0-E2
SCL
WC
3
M24xxx
SDA
VSS
E2, E1, E0
SDA
SCL
WC
V
CC
V
SS
Signal name
Table 1. Signal names
Chip enable
Serial data
Serial clock
Write control
Supply voltage
Ground
Function
Figure 2. 8-pin package connections, top view
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
1.
See Section 9 Package information
for package dimensions, and how to identify pin 1
-
-
Input
I/O
Input
Input
Direction
DS1766 - Rev 35 page 2/47
DS1766 - Rev 35
Position
1
2
3
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Description
Figure 3. WLCSP connections
A
B
C
D
E
1 2 3
WC
E0
V
CC
SCL
SDA
E1
V
SS
E2
Marking side
(top view)
3 2 1
E1
V
SS
E2
WC
E0
SDA
V
CC
SCL
Bump side
(bottom view)
C
D
E
A
B
A
WC
-
E1
Table 2. Signal vs. bump position
B
-
E0
-
C
V
CC
-
V
SS
D
-
SDA
-
E
SCL
-
E2 page 3/47
2
2.1
2.2
2.3
2.4
2.5
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Signal description
Signal description
Serial clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on
SDA(out).
Serial data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from serial data (SDA) to V
CC
indicates how to calculate the value of the pull-up resistor).
Chip enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2,
b1) of the 7-bit device select code (see Table 3 ). These inputs must be tied to V
CC
or V
SS
When not connected (left floating), these inputs are read as low (0).
Figure 4. Chip enable inputs connection
VCC VCC
Ei
M24xxx
VSS
Ei
M24xxx
VSS
Write control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when write control (WC) is driven high. Write operations are enabled when write control (WC) is either driven low or left floating.
When write control (WC) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged.
V
SS
(ground)
V
SS
is the reference for the V
CC
supply voltage.
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Supply voltage (VCC)
2.6
2.6.1
2.6.2
2.6.3
2.6.4
Supply voltage (V
CC
)
Operating supply voltage (V
CC
)
Prior to selecting the memory and issuing instructions to it, a valid and stable V
CC
voltage within the specified
[V
CC
(min), V
CC
(max)] range must be applied (see Operating conditions in Section 8 DC and AC parameters
). In order to secure a stable DC supply voltage, it is recommended to decouple the V
CC
line with a suitable capacitor
(usually of the order of 10 nF to 100 nF) close to the V
CC
/V
SS
package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t
W
).
Power-up conditions
The V
CC
voltage has to rise continuously from 0 V up to the minimum V conditions in
Section 8 DC and AC parameters
).
CC
operating voltage (see Operating
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.
At power-up, the device does not respond to any instruction until V
CC
has reached the internal reset threshold voltage. This threshold is lower than the minimum V
CC
operating voltage (see Operating conditions
in Section 8 DC and AC parameters ). When V
CC
passes over the POR threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until V
CC
reaches a valid and stable DC voltage within the specified [V
CC
(min), V
CC
(max)] range (see Operating conditions in Section 8 DC and AC parameters
).
In a similar way, during power-down (continuous decrease in V
CC
), the device must not be accessed when V
CC drops below V
CC
(min). When V
CC
drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it.
Power-down conditions
During power-down (continuous decrease in V
CC
), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress).
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Memory organization
Memory organization
The memory is organized as shown below.
Figure 5. Block diagram
DATA REGISTER
+
ECC
SENSE AMPLIFIERS
PAGE LATCHES X DECODER
SCL
SDA
WC
Ei
I/O
START & STOP
DETECT
CONTROL
LOGIC
ARRAY
IDENTIFICATION PAGE
HV GENERATOR
+
SEQUENCER
ADDRESS
REGISTER
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Device operation
Device operation
The device supports the I 2 C protocol. This is summarized in
. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications.
Figure 6. I 2 C bus protocol
SCL
SDA
START
Condition
SDA
Input
SDA
Change
STOP
Condition
3 7 SCL
SDA
1
MSB
2 8 9
ACK
START
Condition
SCL
SDA
1
MSB
2 3 7 8 9
ACK
STOP
Condition
DS1766 - Rev 35 page 7/47
4.1
4.2
4.3
4.4
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Start condition
Start condition
Start is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A start condition must precede any data transfer instruction. The device continuously monitors (except during a write cycle) serial data (SDA) and serial clock (SCL) for a start condition.
Stop condition
Stop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable and driven high. A stop condition terminates communication between the device and the bus master. A read instruction that is followed by
NoAck can be followed by a stop condition to force the device into the standby mode.
A stop condition at the end of a write instruction triggers the internal write cycle.
Data input
During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct device operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data
(SDA) signal must change only when serial clock (SCL) is driven low.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases serial data (SDA) after sending eight bits of data. During the 9 th clock pulse period, the receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits.
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Device addressing
Device addressing
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in
(most significant bit first).
Table 3. Device select code
Device select code when addressing the memory array
Device select code when accessing the Identification page
b7
1
1 b6
0
0
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared with the value read on input pins E0, E1 and E2.
b5
1
1 b4
0
1
Chip Enable address
b3
E2
E2 b2
E1
E1 b1
E0
E0
RW b0
RW
RW
When the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (E2, E1, E0) inputs.
The 8 th bit is the Read/Write bit (RW). This bit is set to 1 for read and 0 for write operations.
If a match occurs on the device select code, the corresponding device gives an acknowledgement on serial data
(SDA) during the 9 th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into standby mode.
DS1766 - Rev 35 page 9/47
5
5.1
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Instructions
Instructions
Write operations
Following a start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The
address byte with an acknowledge bit, and then waits for the data byte.
A15 A14
Table 4. Most significant address byte
A13 A12 A11 A10 A9 A8
A7 A6 A5
Table 5. Least significant address byte
A4 A3 A2 A1 A0
When the bus master generates a stop condition immediately after a data byte Ack bit (in the “10 th bit” time slot), either at the end of a byte write or a page write, the internal write cycle t
W other time slot does not trigger the internal write cycle.
is triggered. A stop condition at any
After the stop condition and the successful completion of an internal write cycle (t
W
), the device internal address counter is automatically incremented to point to the next byte after the last modified byte.
During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests.
If the write control input (WC) is driven high, the write instruction is not executed and the accompanying data bytes are not
acknowledged, as shown in Figure 8 .
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Write operations
5.1.1
Byte write
After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected, by write control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a stop condition, as shown in Figure 7 .
Figure 7. Write mode sequences with WC = 0 (data write enabled)
WC
Byte Write Dev sel
ACK
Byte addr
ACK
Byte addr
ACK
Data in
ACK
RW
WC
Page Write
Dev sel
ACK
Byte addr
ACK
Byte addr
ACK
Data in 1
ACK
Data in 2
RW
WC (cont’d)
Page Write (cont’d)
ACK
Data in N
ACK
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Write operations
5.1.2
Page write
The page write mode allows up to 64 byte to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A6, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0.
The bus master sends from 1 to 64 byte of data, each of which is acknowledged by the device if write control
(WC) is low. If write control (WC) is high, the contents of the addressed memory location are not modified, and
each data byte is followed by a NoAck, as shown in Figure 8
. After each transferred byte, the internal page address counter is incremented.
The transfer is terminated by the bus master generating a stop condition.
Figure 8. Write mode sequences with WC = 1 (data write inhibited)
WC
Byte write
WC
Page write
WC (cont’d)
Page write (cont’d)
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Write operations
5.1.3
5.1.4
5.1.5
•
•
Write identification page (M24256-D only)
The identification page (64 byte) is an additional page which can be written and (later) permanently locked in read-only mode. It is written by issuing the write identification page instruction. This instruction uses the same protocol and format as page write (into memory array), except for the following differences:
Device type identifier = 1011b
MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’. LSB address bits
A5/A0 define the byte address inside the Identification page.
If the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (NoAck).
Lock identification page (M24256-D only)
•
•
The lock identification page instruction (Lock ID) permanently locks the identification page in read-only mode. The lock ID instruction is similar to byte write (into memory array) with the following specific conditions:
•
Device type identifier = 1011b
Address bit A10 must be ‘1’; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
ECC (error correction code) and write cycling
The error correction code (ECC) is an internal logic function which is transparent for the I 2 C communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ECC detects this bit and replaces it with the correct value.
The read reliability is therefore much improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently.
In this case, the ECC function also writes/cycles the three other bytes located in the same group (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined
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Write operations
5.1.6
•
•
Minimizing write delays by polling on ACK
The maximum write time (t w
) is shown in AC characteristics tables in
Section 8 , but the typical time is shorter. To
make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in
, is:
• Initial condition: a write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back to step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 9. Write cycle polling flowchart using ACK
Write cycle in progress
Start condition
Device select with RW = 0
NO ACK returned
YES
First byte of instruction with RW = 0 already decoded by the device
Re-start
NO
Next operation is addressing the memory
YES
Send address and receive ACK
Stop NO
StartCondition
YES
Data for the write operation
Continue the write operation
Device select with RW = 1
Continue the random read operation
1.
The seven most significant bits of the device select code of a random read (bottom right box in the figure) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the figure).
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5.2
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Read operations
Read operations
Read operations are performed independently of the state of the write control (WC) signal.
After the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address.
For the read instructions, after each byte read (data out), the device waits for an acknowledgement (data in) during the 9 th
bit time. If the bus master does not acknowledge during this 9 th
time, the device terminates the data transfer and switches to its standby mode.
Figure 10. Read mode sequences
Current
Address
Read
Dev sel
ACK
Data out
NO ACK
RW
Random
Address
Read
Dev sel *
ACK
Byte addr
ACK
Byte addr
ACK
Dev sel *
ACK
Data out
NO ACK
RW RW
Sequential
Current
Read
Sequential
Random
Read
Dev sel
ACK
Data out 1
ACK
RW
ACK NO ACK
Data out N
Dev sel *
ACK
Byte addr
ACK
Byte addr
ACK
Dev sel *
ACK
Data out1
ACK
RW RW
ACK NO ACK
Data out N
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Read identification page (M24256-D only)
5.2.1
5.2.2
5.2.3
5.3
Random address read
) but without sending a stop condition. Then, the bus master sends another start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a stop condition.
Current address read
For the current address read operation, following a start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition, as shown in
Figure 10 , without acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory or the identification page. When accessing the Identification page, the address counter value is loaded with the byte location in the identification page, therefore the next current address read in the memory uses this new address counter value.
When accessing the memory, it is safer to always use the random address read instruction (this instruction loads
instead of the current address Read instruction.
Sequential read
This operation can be used after a current address read or a random address read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and
must generate a Stop condition, as shown in Figure 10
.
The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h.
Read identification page (M24256-D only)
The identification page (64 bytes) is an additional page which can be written and (later) permanently locked in
Read-only mode.
The identification page can be read by issuing an read identification page instruction. This instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as
1011b. The MSB address bits A15/A6 are don't care, the LSB address bits A5/A0 define the byte address inside the identification page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the identification page from location 10d, the number of bytes should be less than or equal to 54, as the ID page boundary is 64 bytes).
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5.4
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Read the lock status (M24256-D only)
Read the lock status (M24256-D only)
The locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. The device returns an acknowledge bit if the identification page is unlocked, otherwise a NoAck bit if the identification page is locked.
Right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that:
• Start: the truncated command is not executed because the start condition resets the device internal logic,
• Stop: the device is then set back into standby mode by the stop condition.
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Initial delivery state
Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1 (each byte contains
FFh).
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Maximum rating
Maximum rating
Stressing the device outside the ratings listed in
may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Absolute maximum ratings
Symbol
-
T
STG
T
LEAD
I
OL
V
IO
V
CC
V
ESD
Parameter
Ambient operating temperature
Storage temperature
Lead temperature during soldering
DC output current (SDA = 0)
Input or output range
Supply voltage
Electrostatic pulse (Human Body model) (2)
Min.
-40
–65
–
–0.50
-0.50
–
Max.
130
150
5
6.5
6.5
4000
Unit
°C
°C
°C mA
V
V
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July
2011).
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012 standard, C1=100 pF, R1=1500 Ω).
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DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device.
Symbol
V
CC
T
A f
C
Table 7. Operating conditions (voltage range W)
Parameter
Supply voltage
Ambient operating temperature
Operating clock frequency
Min.
2.5
–40
-
Max.
5.5
85
1
Unit
V
°C
MHz
Symbol
V
CC
T
A f
C
Table 8. Operating conditions (voltage range R)
Parameter
Supply voltage
Ambient operating temperature
Operating clock frequency
Min.
1.8
–40
-
Max.
5.5
85
1
Unit
V
°C
MHz
Symbol
V
CC
T
A f
C
Table 9. Operating conditions (voltage range F)
Parameter
Supply voltage
Ambient operating temperature
Operating clock frequency
Min.
1.7
-40
-
Max.
5.5
85
1
Unit
V
°C
MHz
Symbol
C bus
-
-
-
Table 10. AC measurement conditions
Parameter
Load capacitance
SCL input rise/fall time, SDA input fall time
Input levels
Input and output timing reference levels
Min.
-
Max.
100
50
0.2 V
CC
to 0.8 V
CC
0.3 V
CC
to 0.7 V
CC
Unit pF ns
V
V
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DC and AC parameters
0.2V
CC
Figure 11. AC measurement I/O waveform
Input voltage levels
0.8V
CC
Input and output
Timing reference levels
0.7V
CC
0.3V
CC
Table 11. Input parameters
Symbol
C
IN
C
IN
Z
Z
L
H
Input capacitance (SDA)
Input capacitance (other pins)
Input impedance (E2, E1, E0, WC) (2)
Test condition
-
-
V
IN
< 0.3 V
CC
V
IN
> 0.7 V
CC
1. Characterized only, not tested in production.
2. E2, E1, E0 input impedance when the memory is selected (after a Start condition).
Min.
-
-
30
500
Max.
8
6
-
-
Unit pF pF kΩ kΩ
Table 12. Cycling performance by groups of four bytes
Symbol
Ncycle
Parameter
Test condition
T
A
≤ 25 °C, V
CC
(min) < V
CC
< V
CC
(max)
T
A
= 85 °C, V
CC
(min) < V
CC
< V
CC
(max)
Max.
4,000,000
1,200,000
Unit
Write cycle
1. The write cycle endurance is defined by characterization and qualification. For devices embedding the ECC functionality
(see ECC (error correction code) and write cycling), the write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer.
2. A Write cycle is executed when either a page write, a byte write, a write identification page or a lock identification page instruction is decoded. When using the byte write, the page write or the write identification page, refer also to
Section 5.1.5 ECC (error correction code) and write cycling
Table 13. Memory cell data retention
Parameter Test condition Min.
Unit
Data retention
T
A
= 55 °C 200 Year
1. The data retention behaviour is checked in production, while the data retention limit defined in this table is extracted from characterization and qualification results.
page 21/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
DC and AC parameters
Table 14. DC characteristics (M24256-BW, device grade 6)
Symbol
I
LI
Parameter
Input leakage current
(SCL, SDA, E2, E1, E0)
I
LO
Output leakage current
V
IN
Test conditions (in addition to those in
= V
SS
or V
CC
, device in Standby mode
) Min.
-
Max.
± 2
Unit
µA
I
I
I
CC
CC0
CC1
Supply current (Read)
Supply current (Write)
Standby supply current
SDA in Hi-Z, external voltage applied on SDA: V
SS
or V
CC
V
CC
= 2.5 V, f
C
= 400 kHz
(rise/fall time < 50 ns)
V
CC
= 5.5 V, f
C
= 400 kHz
(rise/fall time < 50 ns)
2.5 V ≤V
CC
≤ 5.5 V, f
C
= 1 MHz
(rise/fall time < 50 ns)
During t
W
,
2.5 V ≤ V
CC
≤ 5.5 V
V
IN
= V
SS
or V
CC
, V
CC
= 2.5 V
V
IN
= V
SS
or V
CC
, V
CC
= 5.5 V
-
-
-
-
-
-
± 2
2.5
1
2
2
3
µA mA mA
μA
μA
V
V
IL
IH
Input low voltage
(SCL, SDA, WC, E2, E1, E0)
Input high voltage
(SCL, SDA)
Input high voltage
(WC, E2, E1, E0)
-
-
–0.45
0.7 V
0.7 V
CC
CC
0.3 V
6.5
V
CC
CC
V
V
+0.6
V
V
OL
Output low voltage
I
OL
= 2.1 mA, V
CC
= 2.5 V or
I
OL
= 3 mA, V
CC
= 5.5 V
0.4
1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle t
W
(t
W
is triggered by the correct decoding of a write instruction).
3. E i
inputs should be tied to V ss
(see
Section 2.3 Chip enable (E2, E1, E0) ).
4. Ei inputs should be tied to Vcc (see
Section 2.3 Chip enable (E2, E1, E0) ).
V page 22/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
DC and AC parameters
Table 15. DC characteristics (M24256-BR, M24256-DR device grade 6)
Symbol Parameter
Test conditions (1) (in addition to those in
Min.
Max.
Unit
I
LI
Input leakage current
( E0, E1, E2, SCL, SDA)
V
IN
= V
SS
or V
CC
, device in Standby mode ± 2 µA
I
I
I
I
LO
CC
CC0
CC1
Output leakage current
Supply current (Read)
Supply current (Write)
Standby supply current
SDA in Hi-Z, external voltage applied on SDA: V
SS
or
V
CC
V
CC
= 1.8 V, f c
= 400 kHz f c
= 1 MHz
During t
W
1.8 V ≤ V
CC
≤ 2.5 V
V
IN
= V
SS
or V
CC
, V
CC
= 1.8 V
-
-
-
-
± 2
0.8
2.5
2
1
µA mA mA mA
µA
V
V
IL
IH
Input low voltage (SCL, SDA,
WC,E2, E1, E0)
Input high voltage
(SCL, SDA)
Input high voltage
1.8 V ≤ V
1.8 V ≤ V
1.8 V ≤ V
CC
CC
CC
< 2.5 V
< 2.5 V
< 2.5 V
-0.45
0.75 V
0.75 V
CC
CC
0.25 V
6.5
V
CC
CC
V
V
+0.6
V
V
OL
Output low voltage I
OL
= 1 mA, V
CC
= 1.8 V 0.2
1. If the application uses the voltage range R device with 2.5 V < V cc
< 5.5 V and -40 °C < T
A
< +85 °C, please refer to
Table 14 instead of this table.
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle t
W
(t
W
is triggered by the correct decoding of a write instruction).
4. Ei inputs should be tied to V
SS
(see
Section 2.3 Chip enable (E2, E1, E0)
).
5. Ei inputs should be tied to V
CC
(see
Section 2.3 Chip enable (E2, E1, E0) ).
V page 23/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
DC and AC parameters
Table 16. DC characteristics (M24256-BF, M24256-DF, device grade 6)
Symbol Parameter
Test conditions (1) (in addition to those in
Min.
Max.
Unit
I
I
I
I
I
LI
LO
CC
CC0
CC1
Input leakage current
(E0, E1, E2, SCL, SDA)
Output leakage current
Supply current (Read)
Supply current (Write)
Standby supply current
V
IN
= V
SS
or V
CC device in Standby mode
SDA in Hi-Z, external voltage applied on SDA: V
SS
or
V
CC
V
CC
= 1.7 V, f c
= 400 kHz f c
= 1 MHz
During t
W
1.7 V < V
CC
< 2.5 V
Device not selected,
V
IN
= V
SS
or V
CC
, V
CC
= 1.7 V
-
-
-
-
-
± 2
± 2
0.8
2.5
2
1
µA
µA mA mA
µA
V
V
IL
IH
Input low voltage (SCL, SDA,
WC,E2, E1, E0)
Input high voltage
(SCL, SDA)
Input high voltage
1.7 V ≤ V
1.7 V ≤ V
1.7 V ≤ V
CC
CC
CC
< 2.5 V
< 2.5 V
< 2.5 V
-0.45
0.75 V
0.75 V
CC
CC
0.25 V
6.5
V
CC
CC
V
V
+0.6
V
V
OL
Output low voltage I
OL
= 1 mA, V
CC
= 1.7 V 0.2
1. If the application uses the voltage range F device with 2.5 V < V
CC
Table 14 instead of this table.
< 5.5 V and -40 °C < T
A
< +85 °C, please refer to
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle t
W
(t
W
is triggered by the correct decoding of a write instruction).
4. Ei inputs should be tied to V
SS
(see
Section 2.3 Chip enable (E2, E1, E0)
).
5. Ei inputs should be tied to V
CC
(see
Section 2.3 Chip enable (E2, E1, E0) ).
V page 24/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
DC and AC parameters
Table 17. 400 kHz AC characteristics t
CLQV
t
CHDL t
DLCL t
CHDH t
DHDL t
WLDL
t
DHWH
t
W t
NS
Symbol f
C t
CHCL t
CLCH t
QL1QL2
t
XH1XH2 t
XL1XL2 t
DXCH t
CLDX t
CLQX
t
Alt.
f
SCL t
HIGH t
LOW t t
HD:WC t
WR
-
F
R t
F t
SU:DAT t
HD:DAT t
DH t
AA t
SU:STA t
HD:STA t
SU:STO t t
BUF
SU:WC
Clock frequency
Clock pulse width high
Clock pulse width low
SDA (out) fall time
Input signal rise time
Input signal fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition setup time
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start condition
WC set up time (before the Start condition)
WC hold time (after the Stop condition)
Internal Write cycle duration
Parameter
Pulse width ignored (input filter on SCL and SDA) - single glitch
Min.
600
1300
20
-
0
1
-
-
100
0
100
-
600
600
600
1300
Max.
400
300
900
-
-
-
-
-
-
-
-
-
-
-
5
80
Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns
µs
µs ms ns
1. Characterized only, not tested in production.
2. With C
L
= 10 pF.
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when f
C
< 400 kHz.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of
SDA.
5. t
CLQV that R
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3V
CC bus
× C bus
time constant is within the values specified in Figure 12 .
or 0.7V
CC
, assuming
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
page 25/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
DC and AC parameters
Table 18. 1 MHz AC characteristics t
CLQV
t
CHDL t
DLCL t
CHDH t
DHDL t
WLDL
t
DHWH
t
W t
NS
Symbol f
C t
CHCL t
CLCH t
XH1XH2 t
XL1XL2 t
QL1QL2
t
DXCH t
CLDX t
CLQX
Alt.
f
SCL t
HIGH t
LOW t
R t
F t
F t
SU:DAT t
HD:DAT t
DH t
AA t
SU:STA t
HD:STA t
SU:STO t t t
BUF
SU:WC
HD:WC t
WR
-
Clock frequency
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
Data in setup time
Data in hold time
Data out hold time
Start condition setup time
Start condition hold time
Stop condition setup time
Write time
Parameter
Clock low to next data valid (access time)
Time between Stop condition and next Start condition
WC set up time (before the Start condition)
WC hold time (after the Stop condition)
Pulse width ignored (input filter on SCL and SDA)
Min.
260
500
0
50
0
100
-
250
250
250
500
0
1
-
-
Max.
1
120
450
-
-
-
-
-
-
-
-
-
-
-
5
50
Unit
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
µs
µs ms ns
1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be less than 120 ns when f
C
< 1 MHz.
2. Characterized only, not tested in production.
3. With C
L
= 10 pF.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of
SDA.
5. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V
CC
or 0.7 V
CC
, assuming that the Rbus × Cbus time constant is within the values specified in
.
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
page 26/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
DC and AC parameters
Figure 12. Maximum R bus
value versus bus parasitic capacitance (C bus
) for an I 2 C bus at maximum frequency f
C
= 400 kHz
100
10
4 k
R bu s ×
Here R bus
x C bus
= 120 ns
C bu s = 400 ns
1
10 1000
The R bus
x C bus
time constant must be below the 400 ns time constant line represented on the left.
V
CC
R bus
I²C bus master
SCL
SDA
C bus
M24xxx
30 100
Bus line capacitor (pF)
Figure 13. Maximum R bus
value versus bus parasitic capacitance (C bus
) for an I 2 C bus at maximum frequency f
C
= 1MHz
10 0
10
4
1
10
R bus x C bus = 150
ns
Here,
R bus
x C bus
= 120 ns
30
Bus line capacitor (pF)
100
V
CC
The R bus
x C bus
time constant
Must be below the 150 ns
Time constant line represented on the left
I²C bus master
SCL
SDA
R bus
C bus
M24xxx page 27/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
DC and AC parameters
Figure 14. AC waveforms
SCL tXH1XH2
Start condition tXL1XL2 tDLCL tCHCL
SDA In
WC tCLCH tCHDL tWLDL
Stop condition tXH1XH2
SDA
Input tCLDX SDA
Change tDXCH tXL1XL2
SCL
SDA In tCHDH tW
Write cycle tCHDL
Stop condition
Start condition tCHDH tDHDL tDHWH
Start condition tCHCL
SCL
SDA Out tCLQV
Data valid tCLQX
Data valid tQL1QL2 page 28/47
9
9.1
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK ® is an ST trademark.
For die information concerning the M24256-BF delivered in unsawn wafer, please contact your nearest ST Sales
Office.
UFDFPN8 (DFN8) package information
UFDFPN8 is an 8-lead, 2 × 3 mm, 0.55 mm thickness ultra thin profile fine pitch dual flat package.
Figure 15. UFDFPN8 - Outline
N
D A B
Pin #1
ID marking
E ccc C
A
A1 eee C
Seating plane
Side view
A3
C
2x aaa C
1 2
Top view
L3
Pin #1
ID marking
1 2
D2 e b
2x aaa C
L1
E2
K
L
ND-1 x e
Bottom view
See Detail “A”
L L3
Datum A e/2 e
Detail “A”
Even terminal
L1
Terminal tip
1.
Maximum package warpage is 0.05 mm.
2.
Exposed copper is not systematic and can appear partially or totally according to the cross section.
3.
Drawing is not to scale.
4.
The central pad (the area E2 by D2 in the above illustration) must be either connected to V
SS
or left floating
(not connected) in the end application.
DS1766 - Rev 35 page 29/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
UFDFPN8 (DFN8) package information
Table 19. UFDFPN8 - Mechanical data
Symbol
K
L
L1
L3 aaa bbb ccc ddd
A
A1 b
D
D2
E
E2 e
Min
0.450
0.000
0.200
0.300
0.300
-
0.300
-
-
-
-
1.900
1.200
2.900
1.200
-
millimeters
Typ
0.550
0.020
0.250
-
-
-
-
-
-
-
-
2.000
-
3.000
-
0.500
-
Max
0.600
0.050
0.300
2.100
1.600
3.100
1.600
-
-
0.500
0.150
-
0.150
0.100
0.100
0.050
0.080
Min
0.0177
0.0000
0.0079
0.0748
0.0472
0.1142
0.0472
0.0197
0.0118
0.0118
-
0.0118
-
-
-
-
-
Typ
0.0217
0.0008
0.0098
0.0787
-
-
-
-
-
-
-
-
-
-
0.1181
-
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.
3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.
Max
0.0236
0.0020
0.0118
0.0827
0.0630
0.1220
0.0630
-
0.0197
0.0059
-
0.0059
0.0039
0.0039
0.0020
0.0031
Figure 16. UFDFPN8 - Recommended footprint
1.400
0.500
0.300
0.600
1.200
1.300
1.
Dimensions are expressed in millimeters.
page 30/47
9.2
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
TSSOP8 package information
TSSOP8 package information
TSSOP8 is an 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package.
Figure 17. TSSOP8 – Outline
D
8 5
E1 E
1 4
α
A1
CP
A
A2 b e
1.
Drawing is not to scale.
Table 20. TSSOP8 – Mechanical data
Symbol c
CP
D e
E
A
A1
A2 b
E1
L
L1
α
Min.
-
0.050
0.800
0.190
0.090
-
2.900
-
6.200
4.300
0.450
-
0° millimeters
Typ.
-
-
1.000
-
-
-
3.000
0.650
6.400
4.400
0.600
1.000
-
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
-
6.600
4.500
0.750
-
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
0.1142
-
0.2441
0.1693
0.0177
-
0°
Min.
-
0.0020
0.0315
0.0075
0.0035
-
L1
L inches
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
-
Typ.
-
-
0.0394
-
-
c
0.1220
-
0.2598
0.1772
0.0295
-
8°
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
DS1766 - Rev 35 page 31/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
TSSOP8 package information
Figure 18. TSSOP8 – Recommended footprint
2.3
1.0
7.0
0.65
1.
Dimensions are expressed in millimeters.
0.35
page 32/47
9.3
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
SO8N package information
SO8N package information
SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package.
Figure 19. SO8N – Outline
A2 A ccc h x 45˚ c b e
D
0.25 mm
GAUGE PLANE k
8
1
E1 E
A1
L1
L
1.
Drawing is not to scale.
Table 21. SO8N – Mechanical data
Symbol c
D
E
E1 e
A
A1
A2 b h k
L
L1 ccc
Min.
-
0.100
1.250
0.280
0.170
4.800
5.800
3.800
-
0.250
0°
0.400
-
millimeters
Typ.
-
4.900
6.000
3.900
1.270
-
-
-
-
-
-
-
1.040
-
Max.
1.750
0.250
-
0.480
0.230
5.000
6.200
4.000
-
0.500
8°
1.270
-
0.100
Min.
-
0.0039
0.0492
0.0110
0.0067
0.1890
0.2283
0.1496
-
0.0098
0°
0.0157
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
inches
Typ.
-
0.1929
0.2362
0.1535
0.0500
-
-
-
-
-
-
-
0.0409
-
Max.
0.0689
0.0098
-
0.0189
0.0091
0.1969
0.2441
0.1575
-
0.0197
8°
0.0500
-
0.0039
DS1766 - Rev 35 page 33/47
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
SO8N package information
Figure 20. SO8N - Recommended footprint
0.6 (x8)
1.
Dimensions are expressed in millimeters.
1.27
DS1766 - Rev 35 page 34/47
9.4
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
WLCSP8 (CS) package information
WLCSP8 (CS) package information
WLCSP8 is a 8 bumps, 1.289 x 1.379 mm, 0.4 mm pitch wafer level chip scale package
Figure 21. WLCSP8 - Outline bbb Z
D
X Y
E
Reference
Wafer back side
(4X) aaa
A2
A
Side view
Detail A e2 e
F e3
H
G
Orientation
Bump side e1
Bump eee Z
A1
Ø
Ø ccc M ddd M
Z
Z b
X Y
Detail A
Rotated 90 °
Z
Seating plane
1.
Drawing is not to scale
2.
Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3.
Bump position designation per JESD 95-1, SPP-010.
DS1766 - Rev 35 page 35/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
WLCSP8 (CS) package information
Table 22. WLCSP8 - Mechanical data
Symbol aaa bbb ccc ddd eee e2 e3
F
G
H
A
A1
A2
D
E e e1
Min
0.500
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
millimeters
Typ
0.540
0.190
0.350
0.270
1.289
1.379
0.800
0.693
0.400
0.400
0.342
0.245
0.245
0.110
0.110
0.110
0.060
0.060
Max
0.580
-
-
-
1.309
1.399
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
0.0197
-
-
-
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 22. WLCSP8 - Recommended footprint
0.800
0.400
inches
Typ
0.0213
0.0075
0.0138
0.0106
0.0507
0.0542
0.0315
0.0273
0.0157
0.0157
0.0135
0.0096
0.0096
0.0043
0.0043
0.0043
0.0024
0.0024
Max
0.0228
-
-
-
-
-
-
-
-
0.0515
0.0550
-
-
-
-
-
-
-
0.400
0.693
8 bumps x Ø 0.270
1.
Dimensions are expressed in millimeters.
page 36/47
9.5
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
WLCSP8 (CU) package information
WLCSP8 (CU) package information
This WLCSP is a 8 balls, 1.289 x 1.376 mm, 0.4 mm pitch, with BSC, wafer level chip scale package
Figure 23. WLCSP8 - Outline e1
D aaa
(2X)
X
Y
Detail A
G e
Orientation reference
TOP VIEW
E aaa
(2X)
A3
SIDE VIEW
A1
A
A2 b
3
2
1 e2 e3
F
E D C B A
BOTTOM VIEW
Orientation reference bbb Z
A1 ccc M ddd M b
Z X Y
Z
Detail A
Rotated 90
Z
Seating plane
1.
Drawing is not to scale.
2.
Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3.
Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4.
Bump position designation per JESD 95-1, SPP-010.
DS1766 - Rev 35 page 37/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
WLCSP8 (CU) package information
Table 23. WLCSP8 - Mechanical data
Millimeters
-
-
-
-
-
-
-
Min
0.255
-
-
-
-
-
-
-
-
-
e e1 e2 e3
F
A
A1
A2
A3 b
D
E
G aaa bbb ccc ddd eee
Typ
0.295
0.095
0.175
0.025
0.185
1.289
1.376
0.400
0.800
0.346
0.693
0.342
0.245
0.110
0.110
0.110
0.060
0.060
Max
0.335
1.309
1.396
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to the 4rd decimal place
-
-
-
-
-
-
-
Min
0.0100
-
-
-
-
-
-
-
-
-
-
Figure 24. WLCSP8 - Recommended footprint inches
0.0507
0.0542
0.0157
0.0315
0.0136
0.0273
0.0135
Typ
0.0116
0.0037
0.0069
0.0010
0.0073
0.0096
0.0043
0.0043
0.0043
0.0024
0.0024
0.800
0.400
0.346
0.693
0.0515
0.0550
-
-
-
-
-
Max
0.0132
-
-
-
-
-
-
-
-
-
-
8 bumps x 0.185
1.
Dimensions are expressed in millimeters.
page 38/47
10
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Ordering information
Ordering information
Table 24. Ordering information scheme
Example:
Device type
M24 = I 2 C serial access EEPROM
Device function
256 = 256 Kbit (32 K x 8 bit)
Device family
B = Without identification page
D = With identification page
Operating voltage
W = V
CC
= 2.5 V to 5.5 V
R = V
CC
= 1.8 V to 5.5 V
F = V
CC
= 1.7 V to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (DFN8)
CS = WLCSP (chip scale package)
CU = WLCSP Ultra-thin
Device grade
M24
6 = Industrial: device tested with standard test flow over -40 to 85 °C
Option
T = Tape and reel packing blank = tube packing
Plating technology
P or G = ECOPACK2
Process
/K = Manufacturing technology code
256 - D W MN 6 T P
1. ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants).
2. These process letters appear on the device package (marking) and on the shipment box. Contact your nearest ST Sales
Office for further information
/K
DS1766 - Rev 35 page 39/47
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Ordering information
Note:
Table 25. Ordering information scheme (unsawn wafer)
Example:
Device type
M24 = I 2 C serial access EEPROM
Device function
256 = 256 Kbit (32 K x 8 bit)
Device family
B = Without identification page
Operating voltage
F = V
CC
= 1.7 V to 5.5 V
Process
K = F8H
Delivery form
W =Unsawn wafer
Wafer thickness
20 = Non-backlapped wafer
Wafer testing
I = Inkless test
Device grade
90 = -40°C to 85°C
M24 256 B F K W 20 I
1. For all information concerning the M24256 delivered in unsawn wafer, please contact your nearest ST Sales Office.
/90
Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production.
ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.
DS1766 - Rev 35 page 40/47
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Revision history
Date
22-Jun-2012
01-Aug-2012
18-Sep-2012
20-Nov-2012
17-Dec-2012
21-Feb-2014
17-Jun-2014
01-Jun-2015
26
27
28
29
30
31
32
33
Table 26. Document revision history
Revision Changes
Datasheet revision 25 split into:
– M24256-125 datasheet for automotive products (range 3),
– M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF (this datasheet) for standard products (range 6).
Added:
– Reference M24256-DF
– Table 1: Signal names, Table 12: Memory cell data retention
Updated:
– Table 17: 400 kHz AC characteristics and Table 18: 1 MHz AC characteristics: added set up and hold timing conditions on WC (t
WLDL
and t
DHWH
)
– Figure 18: M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline and Table 21: M24256-DFCS6TP/K, WLCSP 8- bump waferlevel chip scale package mechanical data
– Cycling and data retention limits
Deleted:
– UFDFPN8, package revision MB
Updated Figure 3: WLCSP connections and Figure 18: M24256-DFCS6TP/K,
WLCSP 8-bump wafer-level chip scale package outline.
Changed title of Figure 3: WLCSP connections.
Updated Section 5.2.2: Current Address Read.
Corrected “Device family” data in Table 24: Ordering information scheme.
Deleted note (3) under Table 3: Device select code.
Modified ICCO condition in Table 15: DC characteristics (M24256-BR,
M24256-DR device grade 6).
Deleted incorrect table (Table 15. DC characteristics (M24256-R, device grade
6)).
Updated package list in Table 24: Ordering information scheme.
Updated Figure 3: WLCSP connections.
Added notes 4. and 5. in Table 14 and notes 5. and 6. in Table 15 and Table
16
Updated
– Figure 3,
– note 1 on Table 12
– In Table 24 note 1 on Package and blank reference on Option.
Added:
– Unsawn wafer reference on cover page and Table 25: Ordering information scheme (unsawn wafer)
– Figure 20: WLCSP (CS) - 8-bump, 1.289 x 1.376 mm, 0.4 mm pitch wafer level chip scale package recommended footprint
– reference to Engineering samples
Updated:
– Section 2.6.2, Section 4.5
DS1766 - Rev 35 page 41/47
DS1766 - Rev 35
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Date
14-Mar-2018
19-Nov-2020
Revision
34
35
Changes
– Note 2 on Table 6
– Table 18
– Note 2 on Figure 15
– Table 21
– Note 2 on Table 24
Removed:
– Note on t
NS
max value on Table 18
Added WLCSP (CU) package in cover page and in Section 9: Package information, Table 2: Signals vs. bump position.
Updated Table 10: AC measurement conditions, Table 22: WLCSP (CS)-
8-bump, 1.289 x 1.376 mm, 0.4 mm pitch wafer level chip scale package mechanical data, Table 24: Ordering information scheme
•
•
•
•
Updated:
,
Table 6. Absolute maximum ratings
,
Table 12. Cycling performance by groups of four bytes ,
Table 14. DC characteristics (M24256-BW, device grade 6)
,
Table 15. DC characteristics (M24256-BR, M24256-DR device grade 6)
,
Table 16. DC characteristics (M24256-BF, M24256-DF, device grade 6)
,
Table 18. 1 MHz AC characteristics ,
note 1 in
Table 13. Memory cell data retention
title of
Figure 17. TSSOP8 – Outline and Table 20. TSSOP8 –
Figure 19. SO8N – Outline , Table 21. SO8N
Figure 20. SO8N - Recommended footprint ;
,
Mechanical data and Figure 22. WLCSP8 - Recommended footprint
;
Table 23. WLCSP8 - Mechanical data
and
Figure 24. WLCSP8 - Recommended footprint
•
Added:
, Figure 18. TSSOP8 – Recommended footprint
page 42/47
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Contents
Contents
DS1766 - Rev 35 page 43/47
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Contents
DS1766 - Rev 35 page 44/47
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
List of tables
List of tables
DS1766 - Rev 35 page 45/47
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
List of figures
List of figures
value versus bus parasitic capacitance (C bus
) for an I 2 C bus at maximum frequency f
value versus bus parasitic capacitance (C bus
) for an I 2 C bus at maximum frequency f
DS1766 - Rev 35 page 46/47
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
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DS1766 - Rev 35 page 47/47
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