The memory array is based on advanced true EEPROM technology (electrically erasable programmable memory). The M24256-DRE is a byte-alterable memory (32 K × 8 bits) organized as 512 pages of 64 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic.

The M24256-DRE offers an additional Identification Page (64 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.

Figure 1. Logic diagram

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6/42 DocID027418 Rev 2

M24256-DRE

E2, E1, E0

SDA

SCL

Signal name

Figure 2. 8-pin package connection

Description

Table 1. Signal names

Function

Chip enable

Serial Data

Serial Clock

Write Control

Supply voltage

Ground -

Input

I/O

Input

Direction

(

966

9&&

6&/

6'$

$,I

1. See

Section 9: Package mechanical data for package dimensions, and how to identify pin 1.

DocID027418 Rev 2 7/42

Signal description M24256-DRE

2.1

2.2

2.3

2.4 Serial Clock (SCL)

The signal applied on this input is used to strobe the data available on SDA(in) and to output the data on SDA(out).

Serial Data (SDA)

SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected between SDA and V

CC indicates how to calculate the value of the pull-up resistor).

(

Figure 10 and Figure 11

Chip Enable (E2, E1, E0)

(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see

Table 2

). These inputs must be tied to V

or V

, as shown in

Figure 3 . When not connected (left floating), these inputs

are read as low (0).

Figure 3. Device select code

6## 6##

-XXX

633

-XXX

633

Write Control (WC)

This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write

Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating.

When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged.

8/42 DocID027418 Rev 2

M24256-DRE

2.5 V

SS

(ground)

is the reference for the V

supply voltage.

2.6 Supply voltage (V

CC

)

is the supply voltage pin.

Signal description

DocID027418 Rev 2 9/42

Device operation M24256-DRE

The device supports the I 2 C protocol (see

Figure 4 ).

The I 2 C bus is controlled by the bus master and the device is always a slave in all communications.

The device (bus master or a slave) that sends data on to the bus is defined as a transmitter; the device (bus master or a slave) is defined as a receiver when reading the data.

Figure 4. I 2 C bus protocol

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10/42 DocID027418 Rev 2

M24256-DRE Device operation

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock

(SCL) for a Start condition.

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master.

A Stop condition at the end of a Write instruction triggers the internal Write cycle.

3.4

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock

(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock

(SCL) is driven low.

Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9 th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.

DocID027418 Rev 2 11/42

Device operation M24256-DRE

To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, as

shown in Table 2 .

The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable address (E2, E1, E0). A device select code handling any value other than 1010b (to select the memory) or 1011b (to select the Identification page) is not acknowledged by the memory device.

Up to eight memory devices can be connected on a single I

C bus. Each one is given a unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is received, the memory device only responds if the Chip Enable Address is the same as the value decoded on the E2, E1, E0 inputs.

The 8 th

bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

Table 2. Device select code

Device type identifier

(1)

Chip Enable address

(2) b1 b7 b6 b5 b4 b3 b2

When accessing the memory

When accessing the

Identification page

1. The most significant bit, b7, is sent first.

2. E0, E1 and E2 bits are compared with the value read on input pins E0,E1,E2.

RW b0

If a match occurs on the device select code, the corresponding memory device gives an acknowledgment on Serial Data (SDA) during the 9 th bit time. If the memory device does not match the device select code, it deselects itself from the bus, and goes into Standby mode.

Once the memory device has acknowledged the device select code (Table 2), the memory device waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (Table 3). The memory device responds to each address byte with an acknowledge bit.

12/42 DocID027418 Rev 2

M24256-DRE Device operation

Table 3. Significant address bits

Memory

(Device type identifier = 1010b)

Identification page

(Device type identifier = 1011b)

Random

Address Read b4 b3 b2 b1 b0 b7 b6 b5 b15 b14 b13

A14

A13 b12 b11

A12

A11 b10 A1 0 b9 A9 b8 A8

A 0

Write

A 0

A14

A13

A12

A11

A1 0

Read

Identification page

Write

Identification page

Lock

Identification page

A 0

Read lock status

Note: A: significant address bit.

X: bit is Don’t Care.

DocID027418 Rev 2 13/42

Device operation M24256-DRE

Note:

The M24256-DRE offers an Identification Page (64 bytes) in addition to the 256-Kbit memory.

The Identification page contains two fields:

• Device identification code: the first three bytes are programmed by STMicroelectronics

with the Device identification code, as shown in Table 4 .

• Application parameters: the bytes after the Device identification code are available for application specific data.

If the end application does not need to read the Device identification code, this field can be overwritten and used to store application-specific data. Once the application-specific data are written in the Identification page, the whole Identification page should be permanently locked in Read-only mode.

The instructions Read, Write and Lock Identification Page are detailed in

Section 4:

Instructions .

Table 4. Device identification code

Content Value

Address in

Identification page

00h

01h

02h

ST manufacturer code

C family code

Memory density code

20h

E0h

0Fh (256-Kbit)

14/42 DocID027418 Rev 2

M24256-DRE

4 Instructions

Instructions

For a Write operation, the bus master sends a Start condition followed by a device select

code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5

, and waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (

Table 3

). The device responds to each address byte with an acknowledge bit, and then waits for the data byte.

When the bus master generates a Stop condition immediately after a data byte Ack bit (in the “10 th

bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle t

is then triggered. A Stop condition at any other time slot does not trigger the internal

Write cycle.

During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.

After the successful completion of an internal Write cycle (t

), the device internal address counter is automatically incremented to point to the next byte after the last modified byte.

If the Write Control input (WC) is driven High, the Write instruction is not executed and the accompanying data bytes are not

acknowledged, as shown in Figure 6

DocID027418 Rev 2 15/42

Instructions M24256-DRE

After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the

device replies with NoAck, and the location is not modified (see Figure 6

). If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in

Figure 5 .

Figure 5. Write mode sequences with WC = 0 (data write enabled)

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16/42 DocID027418 Rev 2

M24256-DRE Instructions

Note:

The Page Write mode allows up to N

(1)

bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A6, are the same. If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the page are overwritten.

The bus master sends from 1 to N

(1)

bytes of data, each of which is acknowledged by the device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte received by the device is

not acknowledged, as shown in Figure 6

. After each byte is transferred, the internal byte address counter is incremented. The transfer is terminated by the bus master generating a

Stop condition.

Figure 6. Write mode sequences with WC = 1 (data write inhibited)

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1. N is the number of bytes in a page.

DocID027418 Rev 2 17/42

Instructions M24256-DRE

The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences:

• Device type identifier = 1011b

• Most significant address bits A15/A6 are don't care, except for address bit A10 which must be “0”. Least significant address bits A5/A0 define the byte location inside the

Identification page.

If the Identification page is locked, the data bytes transferred during the Write Identification

Page instruction are not acknowledged (NoAck).

The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions:

• Device type identifier = 1011b

• Address bit A10 must be ‘1’; all other address bits are don't care

• The data byte must be equal to the binary value xxxx xx1x, where x is don't care

18/42 DocID027418 Rev 2

M24256-DRE Instructions

The maximum Write time (t w

) is shown in AC characteristics tables in Section 8: DC and AC parameters , but the typical time is shorter. To make use of this, a polling sequence can be

used by the bus master.

The sequence, as shown in

Figure 7 , is:

• Initial condition: a Write cycle is in progress.

• Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).

• Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 7. Write cycle polling flowchart using ACK

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DocID027418 Rev 2 19/42

Instructions M24256-DRE

Read operations are performed independently of the state of the Write Control (WC) signal.

After the successful completion of a Read operation, the device internal address counter is incremented by one, to point to the next byte address.

Figure 8. Read mode sequences

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The Random Address Read is a sequence composed of a truncated Write sequence (to

define a new address pointer value, see Table 3 ) followed by a current Read.

The Random Address Read sequence is therefore the sum of [Start + Device Select code with R/W=0 + two address bytes] (without Stop condition, as shown in

Figure 8 ) and [Start

condition + Device Select code with R/W=1]. The memory device acknowledges the sequence and then outputs the contents of the addressed byte. To terminate the data transfer, the bus master does not acknowledge the last data byte and then issues a Stop condition.

DocID027418 Rev 2

M24256-DRE Instructions

For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte pointed by the internal address counter. The counter is then incremented.

The bus master terminates the transfer with a Stop condition, as shown in

Figure 8 ,

without acknowledging the byte.

Note that the address counter value is defined by instructions accessing either the memory or the Identification page. When accessing the Identification page, the address counter value is loaded with the Identification page byte location, when accessing the memory, it is safer to always use the Random Address Read instruction (this instruction loads the address counter with the byte location to read in the memory) instead of the Current

Address Read instruction.

A sequential Read can be used after a Current Address Read or a Random Address Read.

After a Read instruction, the device can continue to output the next byte(s) in sequence if the bus master sends additional clock pulses and if the bus master does acknowledge each transmitted data byte. To terminate the stream of bytes, the bus master must not

acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8

The sequential read is controlled with the device internal address counter which is automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address

00h.

4.2.5

The Identification Page can be read by issuing a Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The most significant address bits A15/A6 are don't care and the least significant address bits A5/A0 define the byte location inside the

Identification page. The number of bytes to read in the ID page must not exceed the page boundary.

Read the lock status

The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit after the data byte if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked.

Right after this, it is recommended to transmit to the device a Start condition followed by a

Stop condition, so that:

• Start: the truncated command is not executed because the Start condition resets the device internal logic,

• Stop: the device is then set back into Standby mode by the Stop condition.

DocID027418 Rev 2 21/42

Instructions

4.2.6

M24256-DRE

Acknowledge in Read mode

For all Read instructions, the device waits, after each byte sent out, for an acknowledgment during the “9 th

bit” time. If the bus master does not send the Acknowledge (the master drives

SDA high during the 9 th

bit time), the device terminates the data transfer and enters its

Standby mode.

22/42 DocID027418 Rev 2

M24256-DRE

5

Application design recommendations

Application design recommendations

5.1.1 Operating supply voltage (V

)

Prior to selecting the memory and issuing instructions to it, a valid and stable V

CC within the specified [V

(min), V

(max)] range must be applied (see

Table 7

voltage

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal Write cycle (t

W secure a stable DC supply voltage, it is recommended to decouple the V

CC suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V

CC pins.

line with a

). In order to

package

When the power supply is turned on, the V

CC the minimum V

voltage has to rise continuously from 0 V up to

operating voltage defined in

Table 7

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.

At power-up, the device does not respond to any instruction until V

reaches the internal threshold voltage (this threshold is defined in the DC characteristic

Table 10 as V

RES

When V

passes over the POR threshold, the device is reset and in the following state:

• in the Standby power mode

• deselected

As soon as the V

voltage has reached a stable value within the [V

(min), V range (defined in

Table 7

), the device is ready for operation.

(max)]

5.1.3 Power-down

During power-down (continuous decrease in the V

supply voltage below the minimum

operating voltage defined in Table 7

), the device must be in Standby power mode (that is after a STOP condition or after the completion of the Write cycle t

W cycle is in progress).

if an internal Write

DocID027418 Rev 2 23/42

Application design recommendations M24256-DRE

5.2 Cycling Correction Code (ECC)

The error correction code (ECC) is an internal logic function which is transparent for the I

C communication protocol.

The ECC logic is implemented on each group of four EEPROM bytes

(1)

. Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved.

Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group

(1)

. As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in

Table 6

Example 1: maximum cycling limit reached with 1 million cycles per byte

Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group cycling budget is 4 million cycles.

Example 2: maximum cycling limit reached with unequal byte cycling

Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times, byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million cycles.

24/42

1. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer

DocID027418 Rev 2

M24256-DRE Delivery state

The device is delivered as follows:

• The memory array is set to all 1s (each byte = FFh).

• Identification page: the first three bytes define the Device identification code (value

defined in Table 4 ). The content of the following bytes is Don’t Care.

DocID027418 Rev 2 25/42

Maximum rating M24256-DRE

Stressing the device outside the ratings listed in

Table 5

may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 5. Absolute maximum ratings

Parameter Min.

Max.

Unit

Ambient operating temperature –40 130 °C

STG

LEAD

ESD

Storage temperature

Lead temperature during soldering

Input or output range

DC output current (SDA = 0)

Supply voltage

Electrostatic pulse (Human Body model)

(2)

–65

see note

–0.50

150

(1)

6.5

4000

°C

V mA

1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST

ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous

Substances (RoHS directive 2011/65/EU of July 2011).

2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with

ANSI/ESDA/JEDEC JS-001-2012, C1=100 pF, R1=1500 Ω , R2=500 Ω ).

26/42 DocID027418 Rev 2

M24256-DRE

8 DC and AC parameters

DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device.

Symbol

Table 6. Cycling performance by groups of four bytes

Parameter Test condition Min.

Max.

Unit

Ncycle

Write cycle endurance

(1)

TA ≤

< 5.5 V

TA = 85 °C, 1.7 V < V

< 5.5 V

4,000,000

1,200,000

Write cycle

(2)

TA = 105 °C, 1.7 V < V

< 5.5 V 900,000

1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N,

4*N+1, 4*N+2, 4*N+3] where N is an integer, or for the status register byte (refer also to

Section 5.2: Cycling with Error Correction Code (ECC) ). The Write cycle endurance is defined

by characterization and qualification.

2. A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or a Lock Identification Page instruction is decoded. When using those Write instructions, refer

also to Section 5.2: Cycling with Error Correction Code (ECC)

Symbol

Table 7. Operating conditions (voltage range R)

Parameter Min.

Max.

Supply voltage

Ambient operating temperature

1.7

–40

5.5

105

Unit

°C

Symbol

C bus

Table 8. AC measurement conditions

Parameter

Load capacitance

SCL input rise/fall time, SDA input fall time

Input levels

Input and output timing reference levels

Min.

Max.

100

0.2 V

to 0.8 V

0.3 V

to 0.7 V

Figure 9. AC measurement I/O waveform

)NPUTVOLTAGELEVELS

6##

)NPUTANDOUTPUT

4IMINGREFERENCELEVELS

6##

Unit pF ns

-36

DocID027418 Rev 2 27/42

DC and AC parameters M24256-DRE

Symbol

Table 9. Input parameters

Parameter

(1)

Input capacitance (SDA)

Input capacitance (other pins)

Input impedance (E2, E1, E0, WC)

(2)

Test condition

< 0.3 V

> 0.7 V

Min.

Max.

Unit

500

1. Characterized only, not tested in production.

2. E2, E1, E0 input impedance when the memory is selected (after a Start condition).

pF pF k Ω k Ω

28/42 DocID027418 Rev 2

M24256-DRE DC and AC parameters

Symbol Parameter

Table 10. DC characteristics

Test conditions (in addition to those in

Table 7 and Table 8

)

Min.

Max.

Unit

Input leakage current

(SCL, SDA, E i

)

= V

or V

CC, device in Standby mode

± 2 µA

Output leakage current

Supply current (Read)

SDA in Hi-Z, external voltage applied on SDA: V

or V

CC f

= 400 kHz, V

= 5.5 V f

= 400 kHz, V

= 2.5 V f

= 400 kHz, V

= 1.7 V f

= 1 MHz, V

= 5.5 V f

= 1 MHz, V

= 2.5 V -

± 2

µA mA mA mA mA mA

CC0

CC1

Supply current (Write)

Standby supply current

= 1 MHz, V

= 1.7 V

During t

Device not selected

(1)(2)

, t° = 85

°C, V

= V

or V

, V

= 1.7 V

Device not selected

(1)(2)

, t° = 85

°C, V

= V

or V

, V

= 2.5 V

Device not selected

(1)(2)

, t° = 85

°C, V

= V

or V

, V

= 5.5 V

Device not selected

(1)

, t° = 105 °C,

= V

or V

, V

= 1.7 V

Device not selected

(1)

, t° = 105 °C

= V

or V

, V

= 2.5 V

Device not selected

(1)

, t° = 105 °C,

= V

or V

, V

= 5.5 V

2.5

5 mA mA

µA

Input low voltage (SCL, SDA, WC, E i

)

(3)

Input high voltage (SCL, SDA)

Input high voltage (WC, E i

)

(4)

–0.45

0.3 V

0.7 V

6.5

0.7 V

+0.6

Output low voltage

= 2.1 mA, V

= 2.5 V or

= 3 mA, V

= 5.5 V

= 1 mA, V

= 1.7 V -

0.4

0.3

RES

(2)

Internal reset threshold voltage 0.5

1.5

1. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle t

is triggered by the correct decoding of a Write instruction).

2. Characterized only, not 100% tested.

3. Ei inputs should be tied to Vss (see

Section 2.3

4. Ei inputs should be tied to V

(see

Section 2.3

DocID027418 Rev 2 29/42

DC and AC parameters M24256-DRE

Symbol Alt.

Table 11. 400 kHz AC characteristics

Parameter

(1)

Min.

Max. Unit t f

C t

CHCL t

CLCH t

QL1QL2

(2) t

XH1XH2 t

XL1XL2 t

DXCH t

CLDX t

CLQX

(5) t

CLQV

(6) t

CHDL t

DLCL t

CHDH t t

WLDL

(2)(7)

DHWH

(2)(8) t

DHDL t

(2) t t t t t t f

SCL t

HIGH t

LOW t t t t

F t

R t

F t

SU:DAT t

HD:DAT

SU:STA

HD:STA

SU:STO

BUF

SU:WC

HD:WC

Clock frequency

Clock pulse width high

Clock pulse width low

SDA (out) fall time (3)

Input signal rise time

Input signal fall time

Data in set up time

Data in hold time

Data out hold time

Clock low to next data valid (access time)

Start condition setup time

Start condition hold time

Stop condition set up time

Time between Stop condition and next Start condition

WC set up time (before the Start condition)

WC hold time (after the Stop condition)

Write time

Pulse width ignored (input filter on SCL and

SDA) - single glitch

600

1300

(4)

100

600

1300

400

900

120

(4)

80 ns

µs

µs ms ns

1. Test conditions (in addition to those in

Table 7 and Table 8

2. Characterized value, not tested in production.

3. With C

= 10 pF.

4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when f

< 400 kHz.

5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

6. t

CLQV

0.3V

is the time (from the falling edge of SCL) required by the SDA bus line to reach either

or 0.7V

Figure 10.

, assuming that R bus

× C bus time constant is within the values specified in

7. WC=0 set up time condition to enable the execution of a WRITE command.

8. WC=0 hold time condition to enable the execution of a WRITE command.

ns ns ns ns ns ns ns ns ns kHz ns ns ns

30/42 DocID027418 Rev 2

M24256-DRE DC and AC parameters

Symbol Alt.

Table 12. 1 MHz AC characteristics

Parameter

(1)

Min.

Max. Unit t t f

C t

CHCL t

CLCH t

XH1XH2 t

XL1XL2 t

QL1QL2

(3) t

DXCH t

CLDX t

CLQX

(4) t

CLQV

(5) t

CHDL t

DLCL t

CHDH

WLDL

(6)(3)

DHWH

(7)(3) t t

DHDL t

(3) t t t t t t f

SCL t

HIGH t

LOW t t t t

R t

F t

SU:DAT t

HD:DAT

SU:STA

HD:STA

SU:STO

BUF

SU:WC

HD:WC

Clock frequency

Clock pulse width high

Clock pulse width low

Input signal rise time

Input signal fall time

SDA (out) fall time

Data in setup time

Data in hold time

Data out hold time

Clock low to next data valid (access time)

Start condition setup time

Start condition hold time

Stop condition setup time

Time between Stop condition and next Start condition

WC set up time (before the Start condition)

WC hold time (after the Stop condition)

Write time

Pulse width ignored (input filter on SCL and

SDA)

260

400

(2)

100

250

500

120

450

(2)

80 ns

µs

µs ms ns

1. Test conditions (in addition to those in Table 7 and Table 8 ).

2. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the I²C specification that the input signal rise and fall times be more than

20 ns and less than 120 ns when f

< 1 MHz.

3. Characterized only, not tested in production.

4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

5. t

CLQV

0.3 V

is the time (from the falling edge of SCL) required by the SDA bus line to reach either

or 0.7 V in

Figure 11 .

, assuming that the Rbus × Cbus time constant is within the values specified

6. WC=0 set up time condition to enable the execution of a WRITE command.

7. WC=0 hold time condition to enable the execution of a WRITE command.

ns ns ns ns ns ns ns ns ns

MHz ns ns ns

DocID027418 Rev 2 31/42

DC and AC parameters M24256-DRE

Figure 10. Maximum R bus

value versus bus parasitic capacitance (C bus

bus at maximum frequency f

= 400 kHz

) for an I 2 C

K ½

BUS

(ERE2BUS§#BUSNS

§#

BUS

"USLINECAPACITORP&

MUSTBEBELOWTHENS

TIMECONSTANTLINEREPRESENTED

ONTHELEFT

BUS

)£#BUS

MASTER

3#,

3$!

BUS

-XXX

AIB

Figure 11. Maximum R bus

value versus bus parasitic capacitance C

bus at maximum frequency f

= 1MHz bus

) for an I 2 C

BUS §#

BUS NS

BUS

(ERE

§ #

BUS

4HE2

BUS

§#

BUS

TIMECONSTANT

MUSTBEBELOWTHENS

TIMECONSTANTLINEREPRESENTED

ONTHELEFT

)£#BUS

MASTER

3#,

3$!

BUS

-XXX

"USLINECAPACITORP&

-36

32/42 DocID027418 Rev 2

M24256-DRE DC and AC parameters

Figure 12. AC waveforms

^> ƚy,ϭy,Ϯ

^ƚĂƌƚ

ĐŽŶĚŝƚŝŽŶ ƚy>ϭy>Ϯ ƚ>> ƚ,> ƚ>,

^ƚŽƉ

ĐŽŶĚŝƚŝŽŶ

^ƚĂƌƚ

ĐŽŶĚŝƚŝŽŶ

^/Ŷ t ƚ,> ƚy,ϭy,Ϯ

/ŶƉƵƚ ƚ>y ^

ŚĂŶŐĞ ƚy, ƚt>>

^ƚŽƉ

ĐŽŶĚŝƚŝŽŶ

^/Ŷ ƚ,, ƚt tƌŝƚĞĐǇĐůĞ

^KƵƚ ƚ>Ys ƚ,>

ĂƚĂǀĂůŝĚ ƚ>Yy

ĂƚĂǀĂůŝĚ ƚy>ϭy>Ϯ ƚ,> ƚY>ϭY>Ϯ ƚ,, ƚ,> ƚ,t,

^ƚĂƌƚ

ĐŽŶĚŝƚŝŽŶ

/ϬϬϳϵϱŝ

DocID027418 Rev 2 33/42

Package mechanical data

9 Package mechanical data

M24256-DRE

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

Figure 13.TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package outline

34/42

ϴ ϱ

Đ ϭ ϭ ϰ ɲ

Ϯ ϭ

>ϭ

W ď Ğ

76623$0B9

1. Drawing is not to scale.

Table 13. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

b c

A2 e

0.050

0.800

0.190

0.090

2.900

6.200

4.300

1.000

3.000

0.650

6.400

4.400

1.200

0.150

1.050

0.300

0.200

0.100

3.100

6.600

4.500

0.0020

0.0315

0.0075

0.0035

0.1142

0.2441

0.1693

0.0394

0.1181

0.0256

0.2520

0.1732

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.1220

0.2598

0.1772

DocID027418 Rev 2

M24256-DRE Package mechanical data

Table 13. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

L 0.450

0.600

0.750

0.0177

0.0236

L1 1.000

0.0394

α 0° 8° 0°

1. Values in inches are converted from mm and rounded to four decimal digits.

0.0295

8°

9.2 SO8N package information

Figure 14. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline

CCC

*$8*(3/$1(

% %

62$B9

1. Drawing is not to scale.

Table 14. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

E b c

E1 e

0.100

1.250

0.280

0.170

4.800

5.800

3.800

4.900

6.000

3.900

1.270

1.750

0.250

0.480

0.230

5.000

6.200

4.000

0.0039

0.0492

0.0110

0.0067

0.1890

0.2283

0.1496

0.1929

0.2362

0.1535

0.0500

0.0689

0.0098

0.0189

0.0091

0.1969

0.2441

0.1575

DocID027418 Rev 2 35/42

Package mechanical data M24256-DRE

Table 14. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

h k

L1 ccc

0.250

0°

0.400

1.040

0.500

8°

1.270

0.100

0.0098

0°

0.0157

1. Values in inches are converted from mm and rounded to four decimal digits.

0.0409

0.0197

8°

0.0500

0.0039

Figure 15. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint

[

2B)3B9

1. Dimensions are expressed in millimeters.

36/42 DocID027418 Rev 2

M24256-DRE Package mechanical data

Figure 16.WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package outline

3LQ,'PDUNLQJ

$ %

'DWXP<

3LQ

(

6HH=

'HWDLO

[

DDD #

7RSYLHZ

1'[H

%RWWRPYLHZ

1;E EEE

GGG

$ %

'DWXP<

FFF #

HHH #

6HDWLQJSODQH

/ /

7HUPLQDOWLS

6LGHYLHZ

'HWDLO³=´

1. Drawing is not to scale.

$<B0(B9

Table 15. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

E e

A1 b

0.700

0.025

0.200

1.900

2.900

0.300

1.050

0.400

0.750

0.045

0.250

2.000

3.000

0.500

0.800

0.065

0.300

2.100

3.100

0.150

1.650

1.450

0.0276

0.0010

0.0079

0.0748

0.1142

0.0118

0.0413

0.0157

0.0295

0.0018

0.0098

0.0787

0.1181

0.0197

0.0315

0.0026

0.0118

0.0827

0.1220

0.0059

0.0650

0.0571

DocID027418 Rev 2 37/42

Package mechanical data M24256-DRE

Table 15. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

(2)

(3) aaa bbb

0.300

0.500

0.150

0.100

0.0118

0.0197

0.0059

0.0039

ccc ddd eee

(4)

0.100

0.050

0.0039

0.0020

0.080

0.0031

1. Values in inches are converted from mm and rounded to four decimal digits.

2. NX is the number of terminals.

3. ND is the number of terminals on “D” sides.

4. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.

38/42 DocID027418 Rev 2

M24256-DRE Part numbering

Note:

Table 16. Ordering information scheme

Example: M24 256-D R MN 8 T P /K

Device type

M24 = I

C serial access EEPROM

Device function

256-D = 256 Kbit (32 K x 8 bits) plus identification page

Operating voltage

R = V

= 1.7 V to 5.5 V

Package

(1)

MN = SO8 (150 mil width)

DW = TSSOP8 (169 mil width)

MF = WFDFPN8 (2 x 3 mm)

Device grade

8 = -40 to 105 °C.

Option

T = Tape and reel packing blank = tube packing

Plating technology

P or G = ECOPACK2

Process

/K = Manufacturing technology code

1. All package are ECOPACK2 ® (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants)

For a list of available options (speed, package, etc.) or for further information on any aspect of the devices, please contact your nearest ST sales office.

DocID027418 Rev 2 39/42

Part numbering M24256-DRE

Engineering samples

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

40/42 DocID027418 Rev 2

M24256-DRE Revision history

Date

27-Jan-2015

30-Jan-2017

Revision

Table 17. Document revision history

Changes

Initial release.

Updated

Features

Table 7: Operating conditions (voltage range R)

Table 6: Cycling performance by groups of four bytes ,

Table 10: DC characteristics

Table 16: Ordering information scheme

Updated format of

Section 9: Package mechanical data

DocID027418 Rev 2 41/42

M24256-DRE

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

42/42 DocID027418 Rev 2

Reklam

256-Kbit serial I²C bus EEPROM - 105°C operation

Features

Contents

List of tables

List of figures

1 Description

2.1

2.2

2.3

2.4

Serial Clock (SCL)

Serial Data (SDA)

Chip Enable (E2, E1, E0)

Write Control (WC)

2.5 V

SS

(ground)

2.6 Supply voltage (V

CC

)

3.4

Acknowledge bit (ACK)

4 Instructions

5

Application design recommendations

5.2 Cycling Correction Code (ECC)

8 DC and AC parameters

9 Package mechanical data

9.2 SO8N package information

7RSYLHZ

%RWWRPYLHZ

6LGHYLHZ

'HWDLO³=´

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