STMicroelectronics IIS2ICLX Datasheet
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IIS2ICLX
Datasheet
High-accuracy, high-resolution, low-power, 2-axis digital inclinometer with embedded Machine Learning Core
Ceramic cavity LGA-16
(5 x 5 x 1.7 mm)
Product status link
IIS2ICLX
Product summary
Order code IIS2ICLXTR
Temp. range [°C]
Package
Packing
-40 to +105
CC LGA-16
(5 x 5 x 1.7 mm)
Tape and reel
Product resources
AN5509 (IIS2ICLX)
AN5536 (Machine Learning Core)
AN5542 (Finite State Machine)
AN5551 (Tilt sensing)
TN0018 (Design and soldering)
Product labels
Features
• 2-axis linear accelerometer
• Selectable full scale: ±0.5/±1/±2/±3 g
• Ultra-low noise performance: 15 µ g /√Hz
• Superior stability over temperature (<0.075 m g /°C) and repeatability
• Embedded compensation for high stability over temperature
• I²C/SPI digital output interface
• Low power: 0.42 mA with 2 axes delivering full performance
• Sensor hub feature to efficiently collect data from additional external sensors
• Smart embedded FIFO up to 3 kbytes
• Programmable high-pass and low-pass digital filters
• Programmable Machine Learning Core to integrate AI algorithms and reduce power consumption at system level
• Programmable Finite State Machine to process data from accelerometer and one external sensor
• Extended operating temperature range (-40 °C to +105 °C)
• Embedded temperature sensor
• Analog supply voltage: 1.71 V to 3.6 V
• High shock survivability
• ECOPACK , RoHS and "Green" compliant
Applications
• Precision inclinometers
• Antenna pointing and platform leveling
• Structural health monitoring
• Precise leveling instruments
• Installation and monitoring of equipment
• Robotics and industrial automation
Description
The IIS2ICLX is a high-accuracy (ultra-low noise, high stability and repeatability) and low-power two-axis linear accelerometer with digital output.
The IIS2ICLX has a selectable full scale of ±0.5/±1/±2/±3 g and is capable of providing the measured accelerations to the application over an I²C or SPI digital interface.
Its high accuracy, stability over temperature and repeatability make IIS2ICLX particularly suitable for inclination measurement applications (inclinometers).
The sensing element is manufactured using a dedicated micromachining process developed by STMicroelectronics to produce inertial sensors and actuators on silicon wafers.
The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
DS13005 - Rev 6 - August 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
IIS2ICLX
The IIS2ICLX has an unmatched set of embedded features (programmable FSM,
Machine Learning Core, sensor hub, FIFO, event decoding and interrupts) which are enablers for implementing smart and complex sensor nodes which deliver high accuracy and performance at very low power.
The IIS2ICLX is available in a high-performance (low-stress) ceramic cavity land grid array (CC LGA) package and can operate within a temperature range of -40 °C to
+105 °C.
DS13005 - Rev 6 page 2/122
1
Note:
IIS2ICLX
Overview
Overview
The IIS2ICLX is a high-accuracy (ultra-low noise, high stability and repeatability) and ultra-low-power two-axis digital accelerometer specifically recommended for inclination measurements (inclinometers) in Industry 4.0
applications.
All design aspects and the testing and calibration of the IIS2ICLX have been optimized to reach superior accuracy, stability, repeatability and extremely low noise.
The IIS2ICLX has a selectable full scale of ±0.5/±1/±2/±3 g and is capable of providing the measured accelerations to the application over an I²C or SPI digital interface.
Its unique set of embedded features (programmable FSM, Machine Learning Core, sensor hub, FIFO, event decoding and interrupts) facilitate the implementation of smart and complex sensor nodes which deliver high accuracy at very low power.
Like the entire portfolio of ST MEMS sensors, the IIS2ICLX leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
The IIS2ICLX is available in a high-performance (low-stress) ceramic cavity land grid array (CC LGA) package and can operate within a temperature range of -40 °C to +105 °C.
Due to the use of epoxy glue for lid sealing, hermeticity of the package is not guaranteed. Processing or use of this package in a harsh environment should be assessed by the customer.
DS13005 - Rev 6 page 3/122
2
Embedded low-power features
The IIS2ICLX features the following on-chip functions:
• 3 kbytes data buffering
– 100% efficiency with flexible configurations and partitioning
– Possibility to store timestamp and external sensors
•
•
•
Event-detection interrupts (fully configurable)
– Wakeup
– Click and double-click sensing
– Stationary/Motion detection
Specific IP blocks with negligible power consumption and high-performance
– Finite State Machine for accelerometer and external sensors
– Machine Learning Core
Sensor hub
– Up to 5 total sensors: internal accelerometer and 4 external sensors
IIS2ICLX
Embedded low-power features
DS13005 - Rev 6 page 4/122
2.1
IIS2ICLX
Finite State Machine
Finite State Machine
The IIS2ICLX can be configured to generate interrupt signals activated by user-defined motion patterns. To do this, up to 16 embedded finite state machines can be programmed independently for motion detection and decoding.
Definition of Finite State Machine
A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model composed of a finite number of states and transitions between states, similar to a flow chart in which one can inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to different states through transitions dependent on the inputs, and can finally end in a specific state (called stop state). The current state is determined by the past states of the system. The following figure shows a generic state machine.
Figure 1. Generic state machine
DS13005 - Rev 6
Finite State Machine in the IIS2ICLX
The IIS2ICLX works as an accelerometer sensor, generating acceleration output data. It is also possible to connect an external sensor (an accelerometer, a gyroscope, a pressure sensor etc.) by using the Sensor Hub feature (Mode 2). These data can be used as input of up to 16 programs in the embedded Finite State Machine
( Figure 2. State machine in the IIS2ICLX
).
All 16 finite state machines are independent: each one has its dedicated memory area and it is independently executed. An interrupt is generated when the end state is reached or when some specific command is performed.
Figure 2. State machine in the IIS2ICLX
IIS2ICLX
ACC [LSB]
SIGNAL
CONDITIONING
FSM
FSM Output
EXT. SENSOR (GYRO) [LSB]
(optional) page 5/122
2.2
IIS2ICLX
Machine Learning Core
Machine Learning Core
The IIS2ICLX embeds a dedicated core for machine learning processing that provides system flexibility, allowing some algorithms run in the application processor to be moved to the MEMS sensor with the advantage of consistent reduction in power consumption.
Machine Learning Core logic allows identifying if a data pattern (for example motion, pressure, temperature, magnetic data, etc.) matches a user-defined set of classes. Typical examples of applications could be anomalous vibration recognition, complex movement or condition identification, activity detection, etc.
The IIS2ICLX Machine Learning Core works on data patterns coming from the accelerometer, but it is also possible to connect and process external sensor data (from a gyroscope or additional external inclinometer/ accelerometer, temperature or pressure sensors) by using the Sensor Hub feature (Mode 2).
The input data can be filtered using a dedicated configurable computation block containing filters and features computed in a fixed time window defined by the user.
Machine learning processing is based on logical processing composed of a series of configurable nodes characterized by "if-then-else" conditions where the "feature" values are evaluated against defined thresholds.
Figure 3. Machine Learning Core in the IIS2ICLX
INPUT
Sensor Data & Hub
Machine
Learning Core
OUTPUT
Machine
Learning Core
Logical processing
Accelerometer
External Sensor
Filters
Features
Results
Interrupts
The IIS2ICLX can be configured to run up to 8 flows simultaneously and independently and every flow can generate up to 256 results. The total number of nodes can be up to 512.
The results of the machine learning processing are available in dedicated output registers readable from the application processor at any time.
The IIS2ICLX Machine Learning Core can be configured to generate an interrupt when a change in the result occurs.
DS13005 - Rev 6 page 6/122
3
3.1
IIS2ICLX
Pin description
Pin description
Y
1
(TOP VIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
X
Figure 4. Pin connections
15
14
16
1
2
3
13 12
4
TOP
VIEW
5
11
10
9
8
6
7
Pin connections
•
•
The IIS2ICLX offers flexibility to connect the pins in order to have two different mode connections and functionalities. In detail:
Mode 1 : I²C slave interface or SPI (3- and 4-wire) serial interface is available;
Mode 2 : I²C slave interface or SPI (3- and 4-wire) serial interface and I²C interface master for external sensor connections are available.
Figure 5. IIS2ICLX connection modes
Mode 1
HOST
I 2 C /
SPI (3/4-w)
IIS2ICLX
Mode 2
HOST
I 2 C /
SPI (3/4-w)
IIS2ICLX
Master I 2 C
LSM6DSM sensors
In the following table each mode is described for the pin connections and function.
DS13005 - Rev 6 page 7/122
IIS2ICLX
Pin connections
Pin number
1
Name
VDD_IO
2
3
4
5
12
13
14
15
16
6
7
8
9
10
11
CS
GND
INT2
SDO/SA0
INT1
SDx
VDD
VDD
SCL
SDA/SDI
SCx
GND
NC
NC
NC
Table 1. Pin description
Mode 1 function Mode 2 function
Power supply for I/O pins (recommended 100 nF filter capacitor)
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled and reset)
Programmable interrupt 2 (INT2) /
Data enable (DEN)
0 V supply
Programmable interrupt 2 (INT2) /
Data enable (DEN)/I²C master external synchronization signal (MDRDY)
SPI 4-wire serial data output (SDO)
I²C least significant bit of the device address (SA0)
Connect to GND or VDD_IO
Programmable Interrupt 1 (INT1)
I²C serial data master (MSDA)
Power supply (recommended 100 nF filter capacitor)
Power supply (recommended 100 nF filter capacitor)
I²C serial clock (SCL)
SPI serial port clock (SPC)
Connect to GND or VDD_IO
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
I²C serial clock master (MSCL)
GND
Connect to GND or leave unconnected
Connect to GND or leave unconnected
Connect to GND or leave unconnected
DS13005 - Rev 6 page 8/122
IIS2ICLX
Module specifications
4
Module specifications
4.1
Mechanical characteristics
@ Vdd = 3.0 V, T = 25 °C, unless otherwise noted.
Table 2. Mechanical characteristics
Symbol
FS
So
So_acc
Sensitivity change over life (4)
TCSo Sensitivity change vs. temperature
Off
ODR
Zero-
Zerog g level offset accuracy
noise density
Off_acc Zerog level change over life
TCOff Zerog level change vs. temperature
NL
An
Non-linearity
Parameter
Measurement range
Digital output data rate
FS = ±0.5
FS = ±1.0
FS = ±2.0
FS = ±3.0
Test conditions
From -40° to +105°C,delta from 25 °C
From -40° to +105°C, delta from 25 °C
Best-fit straight line
Bw
VRE
Bandwidth
Vibration rectification error
@ODR 833 Hz
FS = ±2 g ; ODR = 50 Hz;
2.5 grms vibration in 50 - 2000 Hz band
F0
ST
Top
Sensor resonant frequency
Self-test
Operating temperature range
@FS = ±2 g 1
-40
1. Min/Max values are based on characterization results at 3σ on a limited number of samples, not tested in production and not guaranteed.
2. Typical specifications are not guaranteed.
3. Sensitivity range after MSL3 preconditioning.
4. Drift over life assessed based on behavior after 1000h of THS (Temperature Humidity Storage) at T=+85°C /
RH = 85%.
5. Typical zero-g level offset value after MSL3 preconditioning.
Min.
-2%
Typ.
±0.5
±1.0
±2.0
±3.0
0.015
0.031
0.061
0.122
+2%
-0.25
±0.07
+0.25
-0.012
±0.01
+0.012
-8 +8 m
Unit g g
/LSB
%
%/°C m g
-2.5
±1 +2.5
m g
-0.075
±0.020
+0.075
m g /°C
0.1
15 30 µ
% FS g /√Hz
12.5
26
52
104
208
416
833
260
Hz
Hz
1
900
15
+105 m
Hz m g
°C g
DS13005 - Rev 6 page 9/122
4.2
4.3
IIS2ICLX
Electrical characteristics
Electrical characteristics
@ Vdd = 3.0 V, T = 25 °C, unless otherwise noted.
Table 3. Electrical characteristics
Symbol
Vdd Supply voltage
Vdd_IO I/O pins supply voltage
Idd Current consumption
IddPD Current consumption during power-down
Ton Turn-on time
V
IH
V
IL
V
OH
Digital high-level input voltage
Digital low-level input voltage
High-level output voltage
V
OL
Top
Parameter
Low-level output voltage
Operating temperature range
I
Test conditions
I
OH
= 4 mA
OL
Min.
1.71
1.62
-40
0.7 *Vdd_IO
VDD_IO - 0.2
1.8
420
3
15
Max.
3.6
3.6
0.3 *Vdd_IO
0.2
+105
V
V
°C
1. Min/Max values are based on characterization results at 3σ on a limited number of samples, not tested in production and not guaranteed.
2. Typical specifications are not guaranteed.
3. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels V
OH
and V
OL
.
Unit
V
V
µA
µA ms
V
V
Temperature sensor characteristics
@ Vdd = 3.0 V, T = 25 °C unless otherwise noted.
Table 4. Temperature sensor characteristics
Symbol
TODR
Parameter
Temperature refresh rate
Test conditions Min.
52
Max.
Unit
Hz
Toff
Tsens
Temperature sensitivity
TST Temperature stabilization time
T_ADC_res Temperature ADC resolution
Top Operating temperature range
-15
256
16
+15
500
°C
LSB/°C
µs bit
°C -40 +105
1. Typical specifications are not guaranteed.
2. The output of the temperature sensor is 0 LSB (typ.) at 25 °C. Absolute temperature accuracy can be improved (reducing the effect of temperature offset) by performing OPC (one-point calibration) at room temperature (25 °C).
3. Time from power ON to valid data based on characterization data.
DS13005 - Rev 6 page 10/122
4.4
4.4.1
IIS2ICLX
Communication interface characteristics
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values (in mode 3)
Value
Symbol
CS setup time
CS hold time
SDI input hold time
SDO valid output time
Parameter
5
20
Max
Unit t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
SPI clock frequency
SDI input setup time
SDO output hold time
SDO output disable time
Min
100
5
15
5
10
50
50 ns
MHz ns
1. Values are evaluated at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.
Figure 6. SPI slave timing diagram (in mode 3)
Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both input and output ports.
DS13005 - Rev 6 page 11/122
IIS2ICLX
Communication interface characteristics
4.4.2
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Symbol Parameter
Table 6. I²C slave timing values f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST) t su(SR) t su(SP) t w(SP:SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
START condition hold time
Repeated START condition setup time
STOP condition setup time
Bus free time between STOP and START condition
1. Data based on standard I²C protocol requirement, not tested in production.
4
4.7
4
4.7
I²C standard mode
Min Max
0 100
4.7
4.0
250
0 3.45
Figure 7. I²C slave timing diagram
0.6
0.6
0.6
1.3
Min Max
0 400
1.3
0.6
100
0 0.9
Unit kHz
µs ns
µs
SDA
START t su(SR) t w(SP:SR)
REPEATED
START
START t su(SDA) t h(SDA) t su(SP)
STOP
Note:
SCL t h(ST) t w(SCLL) t w(SCLH)
Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
DS13005 - Rev 6 page 12/122
4.5
Note:
IIS2ICLX
Absolute maximum ratings
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Vdd and Vdd_IO
T
STG
Sg
ESD
Vin
Table 7. Absolute maximum ratings
Ratings
Supply voltage
Storage temperature range
Acceleration g for 0.1 ms
Electrostatic discharge protection (HBM)
Input voltage on any control pin
(including CS, SPC, SDI, SDO)
Note: Supply voltage on any pin should never exceed 4.8 V.
Maximum value
-0.3 to 4.8
-40 to +125
10000
2
0.3 to Vdd_IO +0.3
Unit
V
°C g kV
V
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS13005 - Rev 6 page 13/122
IIS2ICLX
Digital interfaces
5
Digital interfaces
5.1
5.2
I²C/SPI interface
The registers embedded inside the IIS2ICLX may be accessed through both the I²C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with
SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied high (i.e connected to Vdd_IO).
Pin name
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
Table 8. Serial interface pin description
Pin description
SPI enable
I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
I²C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
I²C less significant bit of the device address
I²C serial interface
The IIS2ICLX I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also be read back.
The relevant I²C terminology is provided in the table below.
Table 9. I²C terminology
Term
Transmitter The device which sends data to the bus
Receiver
Master
Slave
The device which receives data from the bus
Description
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.
The I²C interface is implemeted with fast mode (400 kHz) I²C standards as well as with the standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h) .
DS13005 - Rev 6 page 14/122
IIS2ICLX
I²C serial interface
5.2.1
Command
Read
Write
Read
Write
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to
LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The Slave ADdress (SAD) associated to the IIS2ICLX is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is ‘1’
(address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b).
This solution permits to connect and address two different inertial modules to the same I²C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the IIS2ICLX behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an
8-bit sub-address (SUB) is transmitted. The increment of the address is configured by
(IF_INC).
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.
Table 10 explains how the SAD+Read/Write bit pattern is composed, listing all the possible
configurations.
SAD[6:1]
110101
110101
110101
110101
Table 10. SAD+Read/Write patterns
SAD[0] = SA0
0
0
1
1
R/W
1
0
1
0
SAD+R/W
11010101 (D5h)
11010100 (D4h)
11010111 (D7h)
11010110 (D6h)
Master
Slave
Master
Slave
ST
ST
Table 11. Transfer when master is writing one byte to slave
SAD + W SUB DATA
SAK SAK
Table 12. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA
SAK SAK SAK
DATA
SAK
SAK
SP
SP
Master
Slave
ST
Table 13. Transfer when master is receiving (reading) one byte of data from slave
SAD + W SUB SR SAD + R
SAK SAK SAK DATA
NMAK SP
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W
Slave SAK
SUB
SAK
SR SAD+R
SAK DATA
MAK
DATA
MAK
DATA
NMAK SP
DS13005 - Rev 6 page 15/122
IIS2ICLX
I²C serial interface
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the
SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge.
DS13005 - Rev 6 page 16/122
5.3
IIS2ICLX
SPI bus interface
SPI bus interface
The IIS2ICLX SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.
The serial interface communicates to the application using 4 wires: CS , SPC , SDI and SDO .
Figure 8. Read and write protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
(IF_INC) bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
DS13005 - Rev 6 page 17/122
5.3.1
IIS2ICLX
SPI bus interface
SPI read
Figure 9. SPI read protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reads.
Figure 10. Multiple byte SPI read protocol (2-byte example) (in mode 3)
CS
SPC
SDI
SDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8
DS13005 - Rev 6 page 18/122
IIS2ICLX
SPI bus interface
5.3.2
SPI write
Figure 11. SPI write protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
5.3.3
The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-...
: data DI(...-8). Further data in multiple byte writes.
Figure 12. Multiple byte SPI write protocol (2-byte example) (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
SPI read in 3-wire mode
A 3-wire mode is entered by setting the
CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial interface mode
selection).
Figure 13. SPI read protocol in 3-wire mode (in mode 3)
CS
SPC
SDI/O
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
DS13005 - Rev 6 page 19/122
5.4
IIS2ICLX
Master I²C interface
Master I²C interface
If the IIS2ICLX is configured in Mode 2, a master I²C line is available. The master serial interface is mapped to the following dedicated pins.
Pin name
MSCL
MSDA
MDRDY
Table 15. Master I²C pin details
Pin description
I²C serial clock master
I²C serial data master
I²C master external synchronization signal
DS13005 - Rev 6 page 20/122
IIS2ICLX
Functionality
6
Functionality
6.1
6.1.1
Block diagram of filters
Figure 14. Block diagram of filters
M
E
M
S O
R
N
S
S
E
XL front-end
Temperature sensor
ADC
Low Pass
Filter
(LPF1)
Voltage and current reference
Trimming Circuit
& Test Interface
Clock & Phase
Generator
Composite
Filter
Digital
Processing and functions
Power
Management
I 2 C/SPI
Interface
CS
SCL/SPC
SDA/SDIO
SDO
Interrupt
Mng
INT1
INT2
FTP
Block diagrams of the accelerometer filters
In the IIS2ICLX, the filtering chain for the accelerometer part is composed of the following:
• Digital filter (LPF1)
• Composite filter
Details of the block diagram appear in the following figure.
Figure 15. Accelerometer UI chain
Digital
LP Filter
LPF1
ADC
Composite
Filter
ODR_XL[3:0]
DS13005 - Rev 6 page 21/122
DS13005 - Rev 6
LPF1 output
IIS2ICLX
Block diagram of filters
Figure 16. Accelerometer composite filter
Digital
LP Filter
LPF2
LPF2_XL_EN
0
USER
OFFSET
USR_OFF_ON_OUT
0
HP_SLOPE_XL_EN
0
1
1 USR_OFF_W
OFS_USR[7:0]
HPCF_XL[2:0]
Digital
HP Filter
HPCF_XL[2:0]
1
0
1
0
USR_OFF_ON_WU SLOPE_FDS
Wake-up
001
010
…
111
1
I
FIFO
2
C / SPI
SLOPE
FILTER
000
HPCF_XL[2:0]
S/D Tap page 22/122
6.2
6.2.1
6.2.2
IIS2ICLX
FIFO
FIFO
The presence of a FIFO buffer allows consistent power saving for the system since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO.
•
•
The IIS2ICLX embeds 3 kbytes of data in FIFO to store the following data:
• Accelerometer
•
External sensors (up to 4)
Timestamp
Temperature
•
•
•
•
•
•
The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFOdedicated configurations: accelerometer and temperature sensor batch rates can be selected by the user. Writing external sensor data in FIFO can be triggered by the accelerometer data-ready signal or by an external sensor interrupt. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32.
The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows recognizing the meaning of a word in FIFO.
FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the ODR or BDR (Batch Data Rate) configuration is performed, the application can correctly reconstruct the timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores information of the new configuration and timestamp in which the change was applied in the device.
The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)
using the
) can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of these status events, the configuration can be set in
INT1_CTRL (0Dh) and INT2_CTRL (0Eh) .
The FIFO buffer can be configured according to six different modes:
Bypass mode
FIFO mode
Continuous mode
Continuous-to-FIFO mode
Bypass-to-continuous mode
Bypass-to-FIFO mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the
Bypass mode
In Bypass mode (
FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains
empty. Bypass mode is also used to reset the FIFO when in FIFO mode.
FIFO mode
In FIFO mode ( FIFO_CTRL4 (0Ah)
(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the
FIFO until it is full.
To reset FIFO content, Bypass mode should be selected by writing
(FIFO_MODE_[2:0]) to '000'. After this reset command, it is possible to restart FIFO mode by writing
(FIFO_MODE_[2:0]) to '001'.
The FIFO buffer memorizes up to 3 kbytes of data but the depth of the FIFO can be resized by setting the WTM
[8:0] bits in
FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)
. If the STOP_ON_WTM bit in
is set to
'1', FIFO depth is limited up to the WTM [8:0] bits in
FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)
.
DS13005 - Rev 6 page 23/122
6.2.3
6.2.4
6.2.5
6.2.6
IIS2ICLX
FIFO
Continuous mode
Continuous mode (
FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new
data arrives, the older data is discarded.
A FIFO threshold flag
FIFO_STATUS2 (3Bh) (FIFO_WTM_IA) is asserted when the number of unread samples in
FIFO is greater than or equal to
FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)
(WTM [8:0]).
It is possible to route the FIFO_WTM_IA flag to the INT1 pin by writing in register INT1_CTRL (0Dh)
(INT1_FIFO_TH) = '1' or to the INT2 pin by writing in register INT2_CTRL (0Eh)
(INT2_FIFO_TH) = '1'.
A full-flag interrupt can be enabled,
INT1_CTRL (0Dh) (INT1_FIFO_FULL) = '1' or INT2_CTRL (0Eh)
(INT2_FIFO_FULL) = '1', in order to indicate FIFO saturation and eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag
in FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples
available in FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) (DIFF_FIFO_[9:0]).
•
•
Continuous-to-FIFO mode
In Continuous-to-FIFO mode (
FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 011), FIFO behavior changes according
to the trigger event detected in one of the following interrupt events:
• Single tap
Double tap
Wake-up
When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.
When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
•
•
Bypass-to-Continuous mode
In Bypass-to-Continuous mode ( FIFO_CTRL4 (0Ah)
(FIFO_MODE_[2:0] = '100'), data measurement storage inside FIFO operates in Continuous mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
• Single tap
Double tap
Wake-up
Bypass-to-FIFO mode
•
•
operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
• Single tap
Double tap
Wake-up
DS13005 - Rev 6 page 24/122
6.2.7
IIS2ICLX
FIFO
FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7
(FIFO_DATA_OUT registers from (79h) to (7Eh)).
The DIFF_FIFO_[9:0] field in the
FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)
registers contains the number of words (1 byte TAG + 6 bytes DATA) collected in FIFO.
In addition, it is possible to configure a counter of the batch events of the accelerometer sensor. The
flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh)
alerts that the counter reaches a selectable threshold
(CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch) ). This allows
triggering the reading of FIFO with the desired latency of one single sensor. As for the other FIFO status events, the flag COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by asserting the corresponding bits
(INT1_CNT_BDR of
INT1_CTRL (0Dh) and INT2_CNT_BDR of INT2_CTRL (0Eh)
).
Meta information about the accelerometer sensor configuration changes can be managed by enabling the
ODR_CHG_EN bit in
DS13005 - Rev 6 page 25/122
7
IIS2ICLX
Frequency response
Frequency response
The IIS2ICLX filtering chain and frequency response are detailed in the following figures.
Figure 17. Filtering chain f0=900Hz
Analog
Front-end+
ADC
ADC
Low-Pass
Filter
Composite
Filter
MEMS LPF1 Composite Filter
The output of the ADC converter is filtered with a digital low-pass filter to ensure the intended sensor’s frequency response.
The frequency response at the output of the LPF1 filter is indicated in the following figure.
Figure 18. Frequency response at the output of LPF1 filter at different ODR configurations
DS13005 - Rev 6
The frequency response is determined by CAD simulation.
page 26/122
IIS2ICLX
Typical performance characteristics
8
Typical performance characteristics
8.1
Frequency response measurements
The frequency response of the IIS2ICLX, measured on a mechanical shaker, is indicated in the following figures.
Measurements have been performed with the IIS2ICLX configured with the digital composite filter bypassed.
Figure 19. Frequency response- X-axis ODR = 833 Hz, BW = ODR/2
Figure 20. Frequency response - Y-axis ODR = 833 Hz, BW = ODR/2
Figure 21. Frequency response - X-axis ODR = 104 Hz, BW = ODR/2
DS13005 - Rev 6 page 27/122
IIS2ICLX
Frequency response measurements
Figure 22. Frequency response - Y-axis ODR = 104 Hz, BW = ODR/2
Figure 23. Frequency response - X-axis ODR = 12.5 Hz, BW = ODR/2
Figure 24. Frequency response - Y-axis ODR = 12.5 Hz, BW = ODR/2
Note: Characterization data on a few parts. Not measured in production and not guaranteed.
DS13005 - Rev 6 page 28/122
IIS2ICLX
Application hints
9
Application hints
9.1
IIS2ICLX electrical connections in Mode 1
Figure 25. IIS2ICLX electrical connections in Mode 1
GND or Vdd IO
SCL
Mode 1
HOST
I 2 C/SPI (3/4-w)
IIS2ICLX
C2
100nF
GND
NC (1)
NC (1)
VDDIO
CS
(1) Leave pin electrically unconnected and soldered to PCB.
SDx
VDD
C1
100nF
GND
GND or Vdd IO
Vdd
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration data are selectable and accessible through the
I²C/SPI interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the I²C/SPI interface.
DS13005 - Rev 6 page 29/122
9.2
IIS2ICLX
IIS2ICLX electrical connections in Mode 2
IIS2ICLX electrical connections in Mode 2
Figure 26. IIS2ICLX electrical connections in Mode 2
C2
100nF
GND
NC (1)
NC (1)
VDDIO
CS
(1) Leave pin electrically unconnected and soldered to PCB.
SCL
MSDA
Mode 2
HOST
I 2 C/SPI (3/4-w)
IIS2ICLX
Master I 2 C
VDD
C1
100nF
GND
Vdd
External sensors
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration data are selectable and accessible through the
I²C/SPI primary interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the I²C/SPI primary interface.
DS13005 - Rev 6 page 30/122
IIS2ICLX
IIS2ICLX electrical connections in Mode 2
The procedure to correctly initialize the device is as follows:
1.
INT1: Leave unconnected or connect with external pull-down during power-on. Pull-up must be avoided on this pin.
2.
INT2: Recommend to not connect with external pull-up.
3.
Properly configure the device: a.
SPI interface: I2C_disable = 1 in
CTRL4_C (13h) and DEVICE_CONF = 1 in
b.
I²C interface: I2C_disable = 0 (default) in CTRL4_C (13h)
and DEVICE_CONF = 1 in CTRL9_XL (18h)
.
Pin # Name
1
2
3
4
5
6
7
8
9
10
SDO
SA0
INT1
VDD
VDD
SCL
11 SDA/SDI
12
VDD_IO
CS
GND
INT2
SDx
SCx
Table 16. Internal pin status
Pin status Mode 1 Mode 1 function Mode 2 function
Power supply for I/O pins
(recommended 100 nF filter capacitor)
I²C/SPI mode selection
(1:SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
Programmable interrupt 2
0 V supply
(INT2) / Data enable (DEN)
Programmable interrupt 2 (INT2)/
Data enable (DEN)/ I²C master external synchronization signal
(MDRDY)
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
Programmable Interrupt 1 (INT1)
Connect to GND or VDD_IO I²C serial data master (MSDA)
Default: input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
DEVICE_CONF = 1 in reg 18h.
Default: output forced to ground Default: output forced to ground
Default: input without pull-up.
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Default: input with pull-down (1)
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers.
Pin status Mode 2
Default: input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
DEVICE_CONF = 1 in reg 18h.
Default: input without pull-up.
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Default: input with pull-down (1)
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers.
Power supply (recommended 100 nF filter capacitor )
Power supply (recommended 100 nF filter capacitor )
I²C serial clock (SCL) / SPI serial port clock (SPC)
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
Default: input without pull-up
Default: input without pull-up
Default: input without pull-up
Default: input without pull-up
Connect to GND or VDD_IO I²C serial clock master (MSCL)
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers.
Default: input without pull-up.
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers.
13
14
15
16
GND
NC
NC
NC
GND
Connect to GND or leave unconnected
Connect to GND or leave unconnected
Connect to GND or leave unconnected
1. INT1 must be set to '0' or left unconnected during power-on.
DS13005 - Rev 6 page 31/122
IIS2ICLX
Register map
10
Register map
Name
FUNC_CFG_ACCESS
PIN_CTRL
RESERVED
FIFO_CTRL1
FIFO_CTRL2
FIFO_CTRL3
FIFO_CTRL4
COUNTER_BDR_REG1
COUNTER_BDR_REG2
INT1_CTRL
INT2_CTRL
WHO_AM_I
CTRL1_XL
RESERVED
CTRL3_C
CTRL4_C
CTRL5_C
CTRL6_C
CTRL7_XL
CTRL8_XL
CTRL9_XL
CTRL10_C
ALL_INT_SRC
WAKE_UP_SRC
TAP_SRC
DEN_SRC
STATUS_REG
RESERVED
OUT_TEMP_L
OUT_TEMP_H
RESERVED
OUTX_L_A
OUTX_H_A
The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses.
Table 17. Registers address map
Type
Register address
Hex Binary
00000001
00000010
1E
1F
20
21
22-27
28
29
19
1A
1B
1C
1D
14
15
16
17
18
0D
0E
0F
10
11
12
13
01
02
03-06
07
08
09
0A
0B
0C
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00011110
00011111
00100000
00100001
00100010
00101000
00101001
RW
RW
RW
RW
RW
RW
RW
R
RW
-
RW
RW
RW
RW
-
RW
RW
RW
RW
RW
RW
R
R
R
-
R
-
R
RW
R
R
R
R
Default
00000000
00111111
00000100
00000000
00000000
00000000
00000000
00000000
11100000
00000000 output output output output output
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
01101011
00000000 output output output output
Comment
Reserved
Reserved
Reserved
Reserved
DS13005 - Rev 6 page 32/122
Name
OUTY_L_A
OUTY_H_A
RESERVED
EMB_FUNC_STATUS_MAINPAGE
FSM_STATUS_A_MAINPAGE
FSM_STATUS_B_MAINPAGE
MLC_STATUS_MAINPAGE
STATUS_MASTER_MAINPAGE
FIFO_STATUS1
FIFO_STATUS2
RESERVED
TIMESTAMP0
TIMESTAMP1
TIMESTAMP2
TIMESTAMP3
RESERVED
TAP_CFG0
TAP_CFG1
TAP_CFG2
RESERVED
INT_DUR2
WAKE_UP_THS
WAKE_UP_DUR
RESERVED
MD1_CFG
MD2_CFG
RESERVED
INTERNAL_FREQ_FINE
RESERVED
X_OFS_USR
Y_OFS_USR
RESERVED
FIFO_DATA_OUT_TAG
FIFO_DATA_OUT_X_L
FIFO_DATA_OUT_X_H
FIFO_DATA_OUT_Y_L
FIFO_DATA_OUT_Y_H
FIFO_DATA_OUT_Z_L
FIFO_DATA_OUT_Z_H
DS13005 - Rev 6
IIS2ICLX
Register map
Type
RW
RW
RW
-
RW
R
R
R
R
-
RW
RW
-
RW
RW
-
R
-
RW
R
R
R
R
R
R
-
R
R
-
R
RW
-
R
R
R
R
R
R
R
56
57
58
59
5A
40
41
42
43
44-55
5B
5C
5D
5E
5F
60-62
63
64-72
73
38
39
3A
3B
3C-3F
Hex
2A
2B
2C-34
35
36
37
74
75-77
78
79
7A
7B
7C
7D
7E
Register address
Binary
00101010
00101011
00110101
00110110
00110111
00111000
00111001
00111010
00111011
01000000
01000001
01000010
01000011
01100011
01110011
01110100
01111000
01111001
01111010
01111011
01111100
01111101
01111110
01010110
01010111
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111 output output output output
00000000
00000000
Default output output output output output output output output output
00000000
00000000
00000000
00000000
00000000 output
00000000
00000000 output output output output output output output
Comment
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved page 33/122
11
11.1
11.2
IIS2ICLX
Register description
Register description
The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration and temperature data. The register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface.
FUNC_CFG_ACCESS (01h)
Enable embedded functions register (r/w)
Table 18. FUNC_CFG_ACCESS register
FUNC_CFG_
ACCESS
SHUB_REG_
ACCESS
0
0
1. This bit must be set to '0' for the correct operation of the device.
0
0
0
0
Table 19. FUNC_CFG_ACCESS register description
FUNC_CFG_ACCESS
SHUB_REG_ACCESS
Enable access to the embedded functions configuration registers.
Default value: 0
Enable access to the sensor hub (I²C master) registers.
Default value: 0
1. Details concerning the embedded functions configuration registers are available in
Section 12 Embedded functions register map
and Section 13 Embedded functions register description .
2. Details concerning the sensor hub registers are available in Section 16 Sensor hub register map
and Section 17 Sensor hub register description .
PIN_CTRL (02h)
SDO pin pull-up enable/disable register (r/w)
Table 20. PIN_CTRL register
0
SDO_
PU_EN
1
1
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
1
1
SDO_PU_EN
Table 21. PIN_CTRL register description
Enable pull-up on SDO pin. Default value: 0
(0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up)
1
1
DS13005 - Rev 6 page 34/122
11.3
11.4
IIS2ICLX
FIFO_CTRL1 (07h)
FIFO_CTRL1 (07h)
FIFO control register 1 (r/w)
WTM7 WTM6 WTM5
Table 22. FIFO_CTRL1 register
WTM4 WTM3 WTM2 WTM1 WTM0
Table 23. FIFO_CTRL1 register description
WTM[7:0]
FIFO watermark threshold, in conjunction with WTM8 in
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.
FIFO_CTRL2 (08h)
FIFO control register 2 (r/w)
Table 24. FIFO_CTRL2 register
STOP_ON
_WTM
0
0
ODRCHG
_EN
1. This bit must be set to '0' for the correct operation of the device.
0
0
0
WTM8
Table 25. FIFO_CTRL2 register
STOP_ON_WTM
Sensing chain FIFO stop values memorization at threshold level
(0: FIFO depth is not limited (default);
1: FIFO depth is limited to the threshold level, defined in
FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)
ODRCHG_EN
WTM8
Enables ODR CHANGE virtual sensor to be batched in FIFO
FIFO watermark threshold, in conjunction with WTM[7:0] in
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in FIFO is greater than or equal to the threshold level.
DS13005 - Rev 6 page 35/122
11.5
IIS2ICLX
FIFO_CTRL3 (09h)
FIFO_CTRL3 (09h)
FIFO control register 3 (r/w)
Table 26. FIFO_CTRL3 register
0
0
0
0
BDR_XL_3
1. This bit must be set to '0' for the correct operation of the device.
BDR_XL_2 BDR_XL_1 BDR_XL_0
BDR_XL_[3:0]
Table 27. FIFO_CTRL3 register description
Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.
(0000: Accelerometer not batched in FIFO (default);
0001: 12.5 Hz;
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
0101: 208 Hz;
0110: 417 Hz;
0111: 833 Hz;
1000: not allowed;
1001: not allowed;
1010: not allowed;
1011: 1.6 Hz;
1100-1111: not allowed)
DS13005 - Rev 6 page 36/122
11.6
IIS2ICLX
FIFO_CTRL4 (0Ah)
FIFO_CTRL4 (0Ah)
FIFO control register 4 (r/w)
Table 28. FIFO_CTRL4 register
DEC_TS_
BATCH_1
DEC_TS_
BATCH_0
ODR_T_
BATCH_1
ODR_T_
BATCH_0
1. This bit must be set to '0' for the correct operation of the device.
0
FIFO_
MODE2
FIFO_
MODE1
FIFO_
MODE0
Table 29. FIFO_CTRL4 register description
Selects decimation for timestamp batching in FIFO. Writing rate will be the rate of the accelerometer divided by the decimation decoder
DEC_TS_BATCH_[1:0]
(00: Timestamp not batched in FIFO (default);
01: Decimation 1;
10: Decimation 8;
11: Decimation 32)
ODR_T_BATCH_[1:0]
Selects Batch Data Rate (write frequency in FIFO) for temperature data
(00: Temperature not batched in FIFO (default);
01: 1.6 Hz;
10: 12.5 Hz;
11: 52 Hz)
FIFO_MODE[2:0]
FIFO mode selection
(000: Bypass mode: FIFO disabled;
001: FIFO mode: stops collecting data when FIFO is full;
010: Reserved;
011: Continuous-to-FIFO mode: Continuous mode until trigger is deasserted, then FIFO mode;
100: Bypass-to-Continuous mode: Bypass mode until trigger is deasserted, then Continuous mode;
101: Reserved;
110: Continuous mode: if the FIFO is full, the new sample overwrites the older one;
111: Bypass-to-FIFO mode: Bypass mode until trigger is deasserted, then FIFO mode.)
DS13005 - Rev 6 page 37/122
11.7
11.8
IIS2ICLX
COUNTER_BDR_REG1 (0Bh)
COUNTER_BDR_REG1 (0Bh)
Counter batch data rate register 1 (r/w)
Table 30. COUNTER_BDR_REG1 register dataready_ pulsed
RST_COUNTER
_BDR
0
1. This bit must be set to '0' for the correct operation of the device.
CNT_BDR_
TH_8
Table 31. COUNTER_BDR_REG1 register description dataready_pulsed
Enables pulsed data-ready mode
(0: Data-ready latched mode (returns to 0 only after an interface reading) (default);
1: Data-ready pulsed mode (the data ready pulses are 75 µs long)
RST_COUNTER_BDR
Resets the internal counter of batch events for a single sensor.
This bit is automatically reset to zero if it was set to ‘1’.
CNT_BDR_TH_8
In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch)
, sets the threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in
FIFO_STATUS2 (3Bh) is set to ‘1’.
COUNTER_BDR_REG2 (0Ch)
Counter batch data rate register 2 (r/w)
CNT_BDR_
TH_7
CNT_BDR_
TH_6
CNT_BDR_
TH_5
CNT_BDR_
TH_4
CNT_BDR_
TH_3
CNT_BDR_
TH_2
CNT_BDR_
TH_1
CNT_BDR_
TH_0
Table 32. COUNTER_BDR_REG2 register description
CNT_BDR_TH_[7:0]
In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh) , sets the threshold for the
internal counter of batch events. When this counter reaches the threshold, the counter is reset and the
COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh)
is set to ‘1’.
DS13005 - Rev 6 page 38/122
11.9
IIS2ICLX
INT1_CTRL (0Dh)
INT1_CTRL (0Dh)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried over INT1. The output of the pin will be the OR combination
of the signals selected here and in MD1_CFG (5Eh) .
11.10
11.11
DEN_DRDY
_flag
INT1_
CNT_BDR
INT1_
FIFO_FULL
INT1_
FIFO_OVR
1. This bit must be set to '0' for the correct operation of the device.
INT1_
FIFO_TH
DEN_DRDY_flag
INT1_CNT_BDR
INT1_FIFO_FULL
INT1_FIFO_OVR
INT1_FIFO_TH
INT1_BOOT
INT1_DRDY_XL
INT1_
BOOT
Table 33. INT1_CTRL register description
Sends DEN_DRDY (DEN stamped on Sensor Data flag) to INT1 pin.
Enables COUNTER_BDR_IA interrupt on INT1.
Enables FIFO full flag interrupt on INT1 pin.
Enables FIFO overrun interrupt on INT1 pin.
Enables FIFO threshold interrupt on INT1 pin.
Enables boot status on INT1 pin.
Enables accelerometer data-ready interrupt on INT1 pin.
0
INT1_
DRDY_XL
INT2_CTRL (0Eh)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried over INT2. The output of the pin will be the OR combination
of the signals selected here and in MD2_CFG (5Fh) .
Table 34. INT2_CTRL register
0
INT2_
CNT_BDR
INT2_
FIFO_FULL
INT2_
FIFO_OVR
1. This bit must be set to '0' for the correct operation of the device.
INT2_
FIFO_TH
INT2_
DRDY_TEMP
INT2_CNT_BDR
INT2_FIFO_FULL
INT2_FIFO_OVR
INT2_FIFO_TH
INT2_DRDY_TEMP
INT2_DRDY_XL
Table 35. INT2_CTRL register description
Enables COUNTER_BDR_IA interrupt on INT2 pin.
Enables FIFO full flag interrupt on INT2 pin.
Enables FIFO overrun interrupt on INT2 pin.
Enables FIFO threshold interrupt on INT2 pin.
Enables temperature sensor data-ready interrupt on INT2 pin.
Enables accelerometer data-ready interrupt on INT2 pin.
0
INT2_
DRDY_XL
WHO_AM_I (0Fh)
WHO_AM_I register (r). This is a read-only register. Its value is fixed at 6Bh.
0 1 1
Table 36. Who_Am_I register
0 1 0 1 1
DS13005 - Rev 6 page 39/122
IIS2ICLX
CTRL1_XL (10h)
11.12
CTRL1_XL (10h)
Accelerometer control register 1 (r/w)
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0
1. This bit must be set to '0' for the correct operation of the device.
FS1_XL
ODR_XL[3:0]
FS[1:0]_XL
LPF2_XL_EN
FS0_XL LPF2_XL_EN
Table 37. CTRL1_XL register description
Accelerometer ODR selection (see Table 38
)
Accelerometer full-scale selection (see
)
Accelerometer high-resolution selection
(0: output from first stage digital filtering selected (default);
1: output from LPF2 second filtering stage selected)
ODR_XL3
0
0
0
0
0
0
0
0
1
ODR_XL2
0
0
0
0
1
1
1
1 x
Table 38. Accelerometer ODR selection
ODR_XL1
0
0
1
1
0
0
1
1 x
ODR_XL0
0
1
0
1
0
1
0
1 x
Table 39. Accelerometer full-scale selection
FS[1:0]_XL
00
01
10
11
ODR selection [Hz]
Power-down
12.5 Hz
26 Hz
52 Hz
104 Hz
208 Hz
416 Hz
833 Hz
RESERVED
XL_FS
±0.5 g
±3 g
±1 g
±2 g
0
DS13005 - Rev 6 page 40/122
IIS2ICLX
CTRL3_C (12h)
11.13
CTRL3_C (12h)
Control register 3 (r/w)
Table 40. CTRL3_C register
BOOT BDU H_LACTIVE PP_OD
1. This bit must be set to '0' for the correct operation of the device.
SIM IF_INC 0
SW_RESET
Table 41. CTRL3_C register description
BOOT
Reboots memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
This bit is automatically cleared.
BDU
Block Data Update. Default value: 0
(0: continuous update;
1: output registers are not updated until MSB and LSB have been read)
H_LACTIVE
Interrupt activation level. Default value: 0
(0: interrupt output pins active high; 1: interrupt output pins active low
PP_OD
SIM
Push-pull/open-drain selection on INT1 and INT2 pins. This bit must be set to '0' when H_LACTIVE is set to '1'.
Default value: 0
(0: push-pull mode; 1: open-drain mode)
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
IF_INC
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).
Default value: 1
(0: disabled; 1: enabled)
SW_RESET
Software reset. Default value: 0
(0: normal mode; 1: reset device)
This bit is automatically cleared.
DS13005 - Rev 6 page 41/122
IIS2ICLX
CTRL4_C (13h)
11.14
11.15
CTRL4_C (13h)
Control register 4 (r/w)
Table 42. CTRL4_C register
0
0
INT2_on
_INT1
0
DRDY_MASK
1. This bit must be set to '0' for the correct operation of the device.
I2C_disable
INT2_on_INT1
DRDY_MASK
I2C_disable
Table 43. CTRL4_C register description
All interrupt signals available on INT1 pin enable. Default value: 0
(0: interrupt signals divided between INT1 and INT2 pins;
1: all interrupt signals in logic or on INT1 pin)
Enables data available
(0: disabled;
1: mask DRDY on pin until filter settling ends )
Disables I²C interface. Default value: 0
(0: SPI and I²C interfaces enabled (default); 1: I²C interface disabled)
CTRL5_C (14h)
Control register 5 (r/w)
Table 44. CTRL5_C register
0
0
0
0
1. This bit must be set to '0' for the correct operation of the device.
0
0
ST[1:0]_XL
Table 45. CTRL5_C register description
Linear acceleration sensor self-test enable. Default value: 00
(00: Self-test disabled; Other: refer to Table 46
)
ST1_XL
0
0
1
1
0
ST1_XL
Table 46. Linear acceleration sensor self-test mode selection
ST0_XL
0
1
0
1
Normal mode
Positive sign self-test
Negative sign self-test
Not allowed
Self-test mode
0
ST0_XL
DS13005 - Rev 6 page 42/122
IIS2ICLX
CTRL6_C (15h)
11.16
11.17
CTRL6_C (15h)
Control register 6 (r/w)
TRIG_EN LVL1_EN LVL2_EN
Table 47. CTRL6_C register
0
USR_
OFF_W
1. This bit must be set to '0' for the correct operation of the device.
0
TRIG_EN
LVL1_EN
LVL2_EN
USR_OFF_W
Table 48. CTRL6_C register description
Enables DEN data edge-sensitive trigger mode. Refer to
.
Enables DEN data level-sensitive trigger mode. Refer to
.
Enables DEN level-sensitive latched mode. Refer to Table 49 .
Weight of XL user offset bits of registers X_OFS_USR (73h)
,
(0: 2 -10 g /LSB;
1: 2 -6 g /LSB)
0
0
TRIG_EN, LVL1_EN, LVL2_EN
100
010
011
110
Table 49. Trigger mode selection
Trigger mode
Edge-sensitive trigger mode is selected
Level-sensitive trigger mode is selected
Level-sensitive latched mode is selected
Level-sensitive FIFO enable mode is selected
CTRL7_XL (16h)
Control register 7 (r/w)
Table 50. CTRL7_XL register
0
0
0
0
1. This bit must be set to '0' for the correct operation of the device.
0
USR_OFF_
ON_OUT
0
Table 51. CTRL7_XL register description
USR_OFF_ON_OUT
Enables accelerometer user offset correction block; it's valid for the low-pass path - see
Figure 16. Accelerometer composite filter . Default value: 0
(0: accelerometer user offset correction block bypassed;
1: accelerometer user offset correction block enabled)
DS13005 - Rev 6 page 43/122
IIS2ICLX
CTRL8_XL (17h)
11.18
CTRL8_XL (17h)
Control register 8 (r/w)
Table 52. CTRL8_XL register
HPCF_XL_2 HPCF_XL_1 HPCF_XL_0
HP_REF_
MODE_XL
FASTSETTL_
MODE_XL
1. This bit must be set to '0' for the correct operation of the device.
HP_SLOPE_
XL_EN
0
0
HPCF_XL_[2:0]
HP_SLOPE_XL_EN
Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to Table 53 .
HP_REF_MODE_XL
Enables accelerometer high-pass filter reference mode (valid for high-pass path -
HP_SLOPE_XL_EN bit must be ‘1’). Default value: 0
(0: disabled, 1: enabled)
FASTSETTL_MODE_XL
Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after writing this bit. Active only during device exit from power- down mode. Default value: 0
(0: disabled, 1: enabled)
1. HPCF_XL_[2:0] must be set to "111" before enabling this bit.
2. When enabled, the first output data have to be discarded.
Filter type
Low pass
High pass
Table 53. Accelerometer bandwidth configurations
HP_SLOPE_XL_EN
0
1
LPF2_XL_EN
0
1
-
HPCF_XL_[2:0]
000
001
010
011
100
101
110
111
011
100
101
110
111
-
000
001
010
Bandwidth
ODR/2
ODR/4
ODR/10
ODR/20
ODR/45
ODR/100
ODR/200
ODR/400
ODR/800
SLOPE (ODR/4)
ODR/10
ODR/20
ODR/45
ODR/100
ODR/200
ODR/400
ODR/800
DS13005 - Rev 6 page 44/122
IIS2ICLX
CTRL9_XL (18h)
11.19
11.20
CTRL9_XL (18h)
Control register 9 (r/w)
Table 54. CTRL9_XL register
DEN_X DEN_Y 1
1
1. This bit must be set to ‘1’ to properly use the DEN feature.
2. This bit must be set to '0' for the correct operation of the device.
DEN_EN DEN_LH
DEVICE
_CONF
0
Table 55. CTRL9_XL register description
DEN_X
DEN_Y
DEN_EN
DEN value stored in LSB of X-axis. Default value: 1
(0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB)
DEN value stored in LSB of Y-axis. Default value: 1
(0: DEN not stored in Y-axis LSB; 1: DEN stored in Y-axis LSB)
Enable DEN functionality. Default value: 0
(0: disabled; 1: enabled)
DEN_LH
DEN active level configuration. Default value: 0
(0: active low; 1: active high)
DEVICE_CONF
Enables the proper device configuration. Default value: 0
(0: default; 1: enabled)
It is recommended to set this bit to 1 at initialization phase (and after any software reset) and always keep it to 1 afterwards.
CTRL10_C (19h)
Control register 10 (r/w)
Table 56. CTRL10_C register
0
0
TIMESTAMP
_EN
0
1. This bit must be set to '0' for the correct operation of the device.
0
0
0
Table 57. CTRL10_C register description
TIMESTAMP_EN
Enables timestamp counter. Default value: 0
(0: disabled; 1: enabled)
The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and
0
DS13005 - Rev 6 page 45/122
11.21
11.22
ALL_INT_SRC (1Ah)
Source register for all interrupts (r)
TIMESTAMP
_ENDCOUNT
0
SLEEP_
CHANGE
Table 58. ALL_INT_SRC register
0
DOUBLE_
TAP
SINGLE_
TAP
TIMESTAMP_ENDCOUNT
SLEEP_CHANGE
DOUBLE_TAP
SINGLE_TAP
WU_IA
WU_IA
Table 59. ALL_INT_SRC register description
Alerts timestamp overflow within 6.4 ms
Detects change event in stationary/motion status. Default value: 0
(0: change status not detected; 1: change status detected)
Double-tap event status. Default value: 0
(0:event not detected, 1: event detected)
Single-tap event status. Default value: 0
(0:event not detected, 1: event detected)
Wake-up event status. Default value: 0
(0: event not detected, 1: event detected)
WAKE_UP_SRC (1Bh)
Wake-up interrupt source register (r)
0
SLEEP_
CHANGE_IA
0
Table 60. WAKE_UP_SRC register
SLEEP_
STATE
WU_IA X_WU Y_WU
SLEEP_CHANGE_IA
SLEEP_STATE
WU_IA
X_WU
Y_WU
Table 61. WAKE_UP_SRC register description
Detects change event in stationary/motion status. Default value: 0
(0: change status not detected; 1: change status detected)
Sleep status bit. Default value: 0
(0: sleep event not detected; 1: sleep event detected)
Wakeup event detection status. Default value: 0
(0: wakeup event not detected; 1: wakeup event detected.)
Wakeup event detection status on X-axis. Default value: 0
(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)
Wakeup event detection status on Y-axis. Default value: 0
(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)
IIS2ICLX
ALL_INT_SRC (1Ah)
0
0
DS13005 - Rev 6 page 46/122
IIS2ICLX
TAP_SRC (1Ch)
11.23
11.24
TAP_SRC (1Ch)
Tap source register (r)
X_TAP
Y_TAP
0
TAP_IA
SINGLE_TAP
DOUBLE_TAP
TAP_SIGN
TAP_IA
SINGLE_
TAP
Table 62. TAP_SRC register
DOUBLE
TAP
TAP_SIGN X_TAP
Table 63. TAP_SRC register description
Tap event detection status. Default: 0
(0: tap event not detected; 1: tap event detected)
Single-tap event status. Default value: 0
(0: single tap event not detected; 1: single tap event detected)
Double-tap event detection status. Default value: 0
(0: double-tap event not detected; 1: double-tap event detected)
Sign of acceleration detected by tap event. Default: 0
(0: positive sign of acceleration detected by tap event;
1: negative sign of acceleration detected by tap event)
Tap event detection status on X-axis. Default value: 0
(0: tap event on X-axis not detected; 1: tap event on X-axis detected)
Tap event detection status on Y-axis. Default value: 0
(0: tap event on Y-axis not detected; 1: tap event on Y-axis detected)
Y_TAP 0
DEN_SRC (1Dh)
DEN data-ready register (r)
DEN_DRDY 0 0
Table 64. DEN_SRC register
0 0 0 0
Table 65. DEN_SRC register description
DEN_DRDY
DEN data-ready signal. It is set high when data output is related to the data coming from a DEN active condition.
1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready pulsed bit of the
register.
0
DS13005 - Rev 6 page 47/122
IIS2ICLX
STATUS_REG (1Eh)
11.25
11.26
STATUS_REG (1Eh)
Status register (r)
TDA
XLDA
0 0 0
Table 66. STATUS_REG register
0 0 TDA
Table 67. STATUS_REG register description
Temperature new data available. Default: 0
(0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
Accelerometer new data available. Default value: 0
(0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)
0 XLDA
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.
Temp7 Temp6 Temp5
Table 68. OUT_TEMP_L register
Temp4 Temp3 Temp2 Temp1 Temp0
Temp15 Temp14 Temp13
Table 69. OUT_TEMP_H register
Temp12 Temp11 Temp10
Temp[15:0]
Table 70. OUT_TEMP register description
Temperature sensor output data. The value is expressed as two’s complement.
Temp9 Temp8
DS13005 - Rev 6 page 48/122
IIS2ICLX
OUTX_L_A (28h) and OUTX_H_A (29h)
11.27
11.28
11.29
OUTX_L_A (28h) and OUTX_H_A (29h)
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
D7 D6 D5
Table 71. OUTX_L_A register
D4 D3 D2 D1 D0
D15 D14 D13
Table 72. OUTX_H_A register
D12 D11 D10
D[15:0]
Table 73. OUTX_H_A register description
X-axis linear acceleration value. D[15:0] expressed in two’s complement.
D9 D8
OUTY_L_A (2Ah) and OUTY_H_A (2Bh)
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
D7 D6 D5
Table 74. OUTY_L_A register
D4 D3 D2 D1 D0
D15 D14 D13
Table 75. OUTY_H_A register
D12 D11 D10
D[15:0]
Table 76. OUTY_H_A register description
Y-axis linear acceleration value. D[15:0] expressed in two’s complement.
D9
EMB_FUNC_STATUS_MAINPAGE (35h)
Embedded function status register (r)
IS_FSM_LC 0
Table 77. EMB_FUNC_STATUS_MAINPAGE register
0 0 0 0
IS_FSM_LC
Table 78. EMB_FUNC_STATUS_MAINPAGE register description
Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
0
D8
0
DS13005 - Rev 6 page 49/122
IIS2ICLX
FSM_STATUS_A_MAINPAGE (36h)
11.30
11.31
FSM_STATUS_A_MAINPAGE (36h)
Finite State Machine status register (r)
IS_FSM8 IS_FSM7
Table 79. FSM_STATUS_A_MAINPAGE register
IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
Table 80. FSM_STATUS_A_MAINPAGE register description
Interrupt status bit for FSM8 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM7 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM6 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM5 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM4 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM3 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM2 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM1 interrupt event. (1: interrupt detected; 0: no interrupt)
FSM_STATUS_B_MAINPAGE (37h)
Finite State Machine status register (r)
IS_FSM16 IS_FSM15
Table 81. FSM_STATUS_B_MAINPAGE register
IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
Table 82. FSM_STATUS_B_MAINPAGE register description
Interrupt status bit for FSM16 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM15 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM14 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM13 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM12 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM11 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM10 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM9 interrupt event. (1: interrupt detected; 0: no interrupt)
DS13005 - Rev 6 page 50/122
IIS2ICLX
MLC_STATUS_MAINPAGE (38h)
11.32
11.33
MLC_STATUS_MAINPAGE (38h)
Machine Learning Core status register (r)
IS_MLC8 IS_MLC7
Table 83. MLC_STATUS_MAINPAGE register
IS_MLC6 IS_MLC5 IS_MLC4 IS_MLC3 IS_MLC2 IS_MLC1
IS_MLC8
IS_MLC7
IS_MLC6
IS_MLC5
IS_MLC4
IS_MLC3
IS_MLC2
IS_MLC1
Table 84. MLC_STATUS_MAINPAGE register description
Interrupt status bit for MLC8 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC7 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC6 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC5 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC4 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC3 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC2 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC1 interrupt event. (1: interrupt detected; 0: no interrupt)
STATUS_MASTER_MAINPAGE (39h)
Sensor hub source register (r)
WR_ONCE_
DONE
SLAVE3_
NACK
Table 85. STATUS_MASTER_MAINPAGE register
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK
0 0
SENS_HUB_
ENDOP
Table 86. STATUS_MASTER_MAINPAGE register description
WR_ONCE_DONE
SLAVE3_NACK
SLAVE2_NACK
SLAVE1_NACK
SLAVE0_NACK
When the bit WRITE_ONCE in
is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
SENS_HUB_ENDOP
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded;
1: sensor hub communication concluded)
DS13005 - Rev 6 page 51/122
IIS2ICLX
FIFO_STATUS1 (3Ah)
11.34
11.35
FIFO_STATUS1 (3Ah)
FIFO status register 1 (r)
Table 87. FIFO_STATUS1 register
DIFF_FIFO_7 DIFF_FIFO_6 DIFF_FIFO_5 DIFF_FIFO_4 DIFF_FIFO_3 DIFF_FIFO_2 DIFF_FIFO_1 DIFF_FIFO_0
DIFF_FIFO_[7:0]
Table 88. FIFO_STATUS1 register description
Number of unread sensor data (TAG + 6 bytes) stored in FIFO
In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh)
.
FIFO_STATUS2 (3Bh)
FIFO status register 2 (r)
FIFO_
WTM_IA
FIFO_
OVR_IA
FIFO_
FULL_IA
Table 89. FIFO_STATUS2 register
COUNTER_
BDR_IA
FIFO_OVR_
LATCHED
0 DIFF_FIFO_9 DIFF_FIFO_8
Table 90. FIFO_STATUS2 register description
FIFO_WTM_IA
FIFO_OVR_IA
FIFO_FULL_IA
COUNTER_BDR_IA
FIFO watermark status. Default value: 0
(0: FIFO filling is lower than WTM;
1: FIFO filling is equal to or greater than WTM)
Watermark is set through bits WTM[8:0] in
and
.
FIFO overrun status. Default value: 0
(0: FIFO is not completely filled; 1: FIFO is completely filled)
Smart FIFO full status. Default value: 0
(0: FIFO is not full; 1: FIFO will be full at the next ODR)
Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in
COUNTER_BDR_REG2 (0Ch) . Default value: 0
This bit is reset when these registers are read.
FIFO_OVR_LATCHED
Latched FIFO overrun status. Default value: 0
This bit is reset when this register is read.
DIFF_FIFO_[9:8]
Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00
In conjunction with DIFF_FIFO[7:0] in
DS13005 - Rev 6 page 52/122
IIS2ICLX
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h)
11.36
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3
(43h)
Timestamp first data output register (r). The value is expressed as a 32-bit word and the bit resolution is 25 µs.
D31 D30
Table 91. TIMESTAMP output registers
D29 D28 D27 D26 D25 D24
D23 D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1
D[31:0]
Table 92. TIMESTAMP output register description
Timestamp output registers: 1LSB = 25 µs
The formula below can be used to calculate a better estimation of the actual timestamp resolution:
TS_Res = 1 / (40000 + (0.0015 * INTERNAL_FREQ_FINE * 40000))
where INTERNAL_FREQ_FINE is the content of INTERNAL_FREQ_FINE (63h)
.
D0
DS13005 - Rev 6 page 53/122
IIS2ICLX
TAP_CFG0 (56h)
11.37
11.38
TAP_CFG0 (56h)
Configuration of filtering and tap recognition functions (r/w)
0
INT_CLR_
ON_READ
SLEEP_STATUS
_ON_INT
Table 93. TAP_CFG0 register
SLOPE_FDS TAP_X_EN TAP_Y_EN 0 LIR
Table 94. TAP_CFG0 register description
INT_CLR_ON_READ
This bit allows immediately clearing the latched interrupts of an event detection upon the read of the corresponding status register. It must be set to 1 together with LIR. Default value: 0
(0: latched interrupt signal cleared at the end of the ODR period;
1: latched interrupt signal immediately cleared)
SLEEP_STATUS_ON_INT
Motion/stationary interrupt mode configuration.
If INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or sleep change on the INT pins. Default value: 0
(0: sleep change notification on INT pins; 1: sleep status reported on INT pins)
SLOPE_FDS
TAP_X_EN
TAP_Y_EN
LIR
HPF or SLOPE filter selection on wake-up function. Default value: 0 (
0: SLOPE filter applied; 1: HPF applied)
Enable X direction in tap recognition. Default value: 0
(0: X direction disabled; 1: X direction enabled)
Enable Y direction in tap recognition. Default value: 0
(0: Y direction disabled; 1: Y direction enabled)
Latched Interrupt. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
TAP_CFG1 (57h)
Tap configuration register (r/w)
0 0
TAP_
PRIORITY
Table 95. TAP_CFG1 register
TAP_THS
_X_4
TAP_THS
_X_3
TAP_THS
_X_2
TAP_THS
_X_1
TAP_THS
_X_0
TAP_PRIORITY
TAP_THS_X_[4:0]
Table 96. TAP_CFG1 register description
(0: X max, Y min;
1: Y max, X min)
X-axis tap recognition threshold. Default value: 0
1 LSB = FS_XL / (2 5 )
Note: If selecting FS_XL = ±3 g, 1 LSB = 4 / 2 5 g.
DS13005 - Rev 6 page 54/122
IIS2ICLX
TAP_CFG2 (58h)
11.39
11.40
TAP_CFG2 (58h)
Enables interrupt and tap recognition functions (r/w)
INTERRUPTS
_ENABLE
0 0
Table 97. TAP_CFG2 register
TAP_THS_
_Y_4
TAP_THS_
_Y_3
TAP_THS_
_Y_2
TAP_THS_
_Y_1
TAP_THS_
_Y_0
INTERRUPTS_ENABLE
TAP_THS_Y_[4:0]
Table 98. TAP_CFG2 register description
Enable basic interrupts (wake-up, tap). Default value: 0
(0: interrupt disabled; 1: interrupt enabled)
Y-axis tap recognition threshold. Default value: 0
1 LSB = FS_XL / (2 5 )
Note: If selecting FS_XL = ±3 g, 1 LSB = 4 / 2 5 g.
INT_DUR2 (5Ah)
Tap recognition function setting register (r/w)
DUR3 DUR2 DUR1
Table 99. INT_DUR2 register
DUR0 QUIET1 QUIET0 SHOCK1 SHOCK0
Table 100. INT_DUR2 register description
DUR[3:0]
QUIET[1:0]
Duration of maximum time gap for double tap recognition. Default: 0000
When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to
16/ODR_XL time. If the DUR[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
Expected quiet time after a tap detection. Default value: 00
Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET[1:0] bits are set to a different value, 1LSB corresponds to 4/ODR_XL time.
SHOCK[1:0]
Maximum duration of overthreshold event. Default value: 00
Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event.
The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK[1:0] bits are set to a different value, 1LSB corresponds to 8/ODR_XL time.
DS13005 - Rev 6 page 55/122
IIS2ICLX
WAKE_UP_THS (5Bh)
11.41
11.42
WAKE_UP_THS (5Bh)
Single/double-tap selection and wake-up configuration (r/w)
SINGLE_
DOUBLE_TAP
USR_OFF_
ON_WU
Table 101. WAKE_UP_THS register
WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0
Table 102. WAKE_UP_THS register description
SINGLE_DOUBLE_TAP
Single/double-tap event enable. Default: 0
(0: only single-tap event enabled;
1: both single and double-tap events enabled)
USR_OFF_ON_WU
WK_THS[5:0]
Drives the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the wakeup function.
Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
.
Default value: 000000
WAKE_UP_DUR (5Ch)
Wakeup and sleep mode functions duration setting register (r/w)
0
WAKE_
DUR1
Table 103. WAKE_UP_DUR register
WAKE_
DUR0
WAKE_
THS_W
SLEEP_
DUR3
SLEEP_
DUR2
SLEEP_
DUR1
WAKE_DUR[1:0]
WAKE_THS_W
SLEEP_DUR[3:0]
Table 104. WAKE_UP_DUR register description
Wake up duration event. Default: 00
1LSB = 1 ODR_time
Weight of 1 LSB of wakeup threshold. Default: 0
(0: 1 LSB = FS_XL / (2 6 );
1: 1 LSB = FS_XL / (2 8 ))
Note: If selecting FS_XL = ±3 g then: if WAKE_THS_W = 0, 1 LSB = 4 / 2 6 g; if WAKE_THS_W = 1, 1 LSB = 4 / 2 8 g .
Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)
1 LSB = 512 ODR
SLEEP_
DUR0
DS13005 - Rev 6 page 56/122
IIS2ICLX
MD1_CFG (5Eh)
11.43
MD1_CFG (5Eh)
Functions routing on INT1 register (r/w)
Table 105. MD1_CFG register
INT1_SLEEP
_CHANGE
INT1_
SINGLE_TAP
INT1_WU 0
INT1_
DOUBLE_TAP
1. This bit must be set to '0' for the correct operation of the device.
0
INT1_
EMB_FUNC
INT1_SHUB
Table 106. MD1_CFG register description
INT1_SLEEP_CHANGE
Routing of stationary/motion recognition event on INT1. Default: 0
(0: routing of stationary/motion event on INT1 disabled;
1: routing of stationary/motion event on INT1 enabled)
INT1_SINGLE_TAP
Routing of single-tap recognition event on INT1. Default: 0
(0: routing of single-tap event on INT1 disabled;
1: routing of single-tap event on INT1 enabled)
INT1_WU
INT1_DOUBLE_TAP
INT1_EMB_FUNC
INT1_SHUB
Routing of wakeup event on INT1. Default value: 0
(0: routing of wakeup event on INT1 disabled;
1: routing of wakeup event on INT1 enabled)
Routing of double-tap event on INT1. Default value: 0
(0: routing of double-tap event on INT1 disabled;
1: routing of double-tap event on INT1 enabled)
Routing of embedded functions event on INT1. Default value: 0
(0: routing of embedded functions event on INT1 disabled;
1: routing embedded functions event on INT1 enabled)
Routing of sensor hub communication concluded event on INT1.
Default value: 0
(0: routing of sensor hub communication concluded event on INT1 disabled; 1: routing of sensor hub communication concluded event on INT1 enabled)
1. Stationary/motion interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in the
DS13005 - Rev 6 page 57/122
IIS2ICLX
MD2_CFG (5Fh)
11.44
MD2_CFG (5Fh)
Functions routing on INT2 register (r/w)
Table 107. MD2_CFG register
INT2_SLEEP
_CHANGE
INT2_
SINGLE_TAP
INT2_WU 0
INT2_
DOUBLE_TAP
1. This bit must be set to '0' for the correct operation of the device.
0
INT2_
EMB_FUNC
INT2_
TIMESTAMP
Table 108. MD2_CFG register description
INT2_SLEEP_CHANGE
INT2_SINGLE_TAP
INT2_WU
INT2_DOUBLE_TAP
INT2_EMB_FUNC
Routing of stationary/motion recognition event on INT2. Default: 0
(0: routing of stationary/motion event on INT2 disabled;
1: routing of stationary/motion event on INT2 enabled)
Single-tap recognition routing on INT2. Default: 0
(0: routing of single-tap event on INT2 disabled;
1: routing of single-tap event on INT2 enabled)
Routing of wakeup event on INT2. Default value: 0
(0: routing of wakeup event on INT2 disabled;
1: routing of wake-up event on INT2 enabled)
Routing of double-tap event on INT2. Default value: 0
(0: routing of double-tap event on INT2 disabled;
1: routing of double-tap event on INT2 enabled)
Routing of embedded functions event on INT2. Default value: 0
(0: routing of embedded functions event on INT2 disabled;
1: routing embedded functions event on INT2 enabled)
Enables routing on INT2 pin of the alert for timestamp overflow within 6.4 ms.
INT2_TIMESTAMP
1. Stationary/motion interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in the
DS13005 - Rev 6 page 58/122
IIS2ICLX
INTERNAL_FREQ_FINE (63h)
11.45
INTERNAL_FREQ_FINE (63h)
Internal frequency register (r)
Table 109. INTERNAL_FREQ_FINE register
FREQ_FINE7 FREQ_FINE6 FREQ_FINE5 FREQ_FINE4 FREQ_FINE3 FREQ_FINE2 FREQ_FINE1 FREQ_FINE0
Table 110. INTERNAL_FREQ_FINE register description
FREQ_FINE[7:0]
Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.15%.
8-bit format, 2's complement.
The formula below can be used to calculate a better estimation of the actual ODR:
ODR_Actual = (6667 + ((0.0015 * INTERNAL_FREQ_FINE) * 6667)) / ODR_Coeff
Selected_ODR
12.5
26
52
104
208
416
833
ODR_Coeff
512
256
128
64
32
16
8
The Selected_ODR parameter has to be derived from the ODR_XL selection (
Table 38. Accelerometer ODR selection
) in order to estimate the accelerometer ODR.
DS13005 - Rev 6 page 59/122
IIS2ICLX
X_OFS_USR (73h)
11.46
11.47
X_OFS_USR (73h)
Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally subtracted from the acceleration value measured on the X-axis.
X_OFS_
USR_7
X_OFS_
USR_6
X_OFS_
USR_5
Table 111. X_OFS_USR register
X_OFS_
USR_4
X_OFS_
USR_3
X_OFS_
USR_2
X_OFS_
USR_1
X_OFS_
USR_0
Table 112. X_OFS_USR register description
X_OFS_USR_[7:0]
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on
. The value must be in the range [-127 127].
Y_OFS_USR (74h)
Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is internally subtracted from the acceleration value measured on the Y-axis.
Y_OFS_
USR_7
Y_OFS_
USR_6
Y_OFS_
USR_5
Table 113. Y_OFS_USR register
Y_OFS_
USR_4
Y_OFS_
USR_3
Y_OFS_
USR_2
Y_OFS_
USR_1
Y_OFS_
USR_0
Table 114. Y_OFS_USR register description
Y_OFS_USR_[7:0]
Accelerometer Y-axis user offset calibration expressed in 2’s complement, weight depends on
. The value must be in the range [-127, +127].
DS13005 - Rev 6 page 60/122
IIS2ICLX
FIFO_DATA_OUT_TAG (78h)
11.48
FIFO_DATA_OUT_TAG (78h)
FIFO tag register (r)
TAG_
SENSOR_4
TAG_
SENSOR_3
Table 115. FIFO_DATA_OUT_TAG register
TAG_
SENSOR_2
TAG_
SENSOR_1
TAG_
SENSOR_0
TAG_CNT_1 TAG_CNT_0
TAG_
PARITY
Table 116. FIFO_DATA_OUT_TAG register description
TAG_SENSOR_[4:0]
Identifies the sensor in:
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
,
FIFO_DATA_OUT_Y_H (7Ch) , and FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
For details, refer to Table 117
.
TAG_CNT_[1:0]
TAG_PARITY
2-bit counter which identifies sensor time slot
Parity check of TAG content
Table 117. FIFO tag
TAG_SENSOR_[4:0]
0x02
0x03
0x04
0x05
0x06
0x07
0x0E
0x0F
0x10
0x11
0x19
0x08
0x09
0x0A
0x0B
0x0C
0x0D
Sensor name
Accelerometer
Temperature
Timestamp
CFG_Change
Reserved
Sensor Hub Slave 0
Sensor Hub Slave 1
Sensor Hub Slave 2
Sensor Hub Slave 3
Sensor Hub Nack
DS13005 - Rev 6 page 61/122
IIS2ICLX
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
11.49
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
FIFO data output X (r)
D15
Table 118. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers
D14 D13 D12 D11 D10 D9 D8
11.50
D7
D[15:0]
D6 D5 D4 D3 D2 D1
Table 119. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description
FIFO X-axis output
D0
FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch)
FIFO data output Y (r)
D15
Table 120. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers
D14 D13 D12 D11 D10 D9 D8
11.51
D7
D[15:0]
D6 D5 D4 D3 D2 D1
Table 121. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description
FIFO Y-axis output
D0
FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
FIFO data output Z (r)
D15
Table 122. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers
D14 D13 D12 D11 D10 D9 D8
Note:
D7 D6 D5 D4 D3 D2 D1
D[15:0]
Table 123. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description
FIFO Z-axis output
Fields related to the Z-axis are intended for usage in conjunction with an external sensor.
D0
DS13005 - Rev 6 page 62/122
IIS2ICLX
Embedded functions register map
12
Embedded functions register map
The table given below provides a list of the registers for the embedded functions available in the device and the corresponding addresses. Embedded functions registers are accessible when FUNC_CFG_EN is set to '1' in
Name
PAGE_SEL
EMB_FUNC_EN_B
PAGE_ADDRESS
PAGE_VALUE
EMB_FUNC_INT1
FSM_INT1_A
FSM_INT1_B
MLC_INT1
EMB_FUNC_INT2
FSM_INT2_A
FSM_INT2_B
MLC_INT2
EMB_FUNC_STATUS
FSM_STATUS_A
FSM_STATUS_B
MLC_STATUS
PAGE_RW
RESERVED
FSM_ENABLE_A
FSM_ENABLE_B
FSM_LONG_COUNTER_L
FSM_LONG_COUNTER_H
FSM_LONG_COUNTER_CLEAR
FSM_OUTS1
FSM_OUTS2
FSM_OUTS3
FSM_OUTS4
FSM_OUTS5
FSM_OUTS6
FSM_OUTS7
FSM_OUTS8
FSM_OUTS9
FSM_OUTS10
Table 124. Register address map - embedded functions
Type
Register address
Binary
00000010
00000101
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010111
18-45
46
47
48
49
10
11
12
13
14
15
17
Hex
02
05
08
09
0A
0B
0C
0D
0E
0F
53
54
55
50
51
52
4A
4C
4D
4E
4F
01000110
01000111
01001000
01001001
01001010
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
-
RW
RW
RW
RW
RW
RW
R
R
R
R
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
R
R
R
R
R
R
RW
R
R
R
R
Default
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
01101011
00000000
00000000 output output output output
00000000
00000000
00000000
00000000
00000000
00000000 output output output output output output output output output output
Comment
Reserved
DS13005 - Rev 6 page 63/122
IIS2ICLX
Embedded functions register map
Name
FSM_OUTS11
FSM_OUTS12
FSM_OUTS13
FSM_OUTS14
FSM_OUTS15
FSM_OUTS16
RESERVED
EMB_FUNC_ODR_CFG_B
EMB_FUNC_ODR_CFG_C
RESERVED
EMB_FUNC_INIT_B
MLC0_SRC
MLC1_SRC
MLC2_SRC
MLC3_SRC
MLC4_SRC
MLC5_SRC
MLC6_SRC
MLC7_SRC
Type
R
R
R
R
R
R
R
R
R
R
-
RW
RW
-
RW
R
R
R
R
70
71
72
73
74
75
76
77
5C-5E
5F
60
61-66
67
Hex
56
57
58
59
5A
5B
Register address
Binary
01010110
01010111
01011000
01011001
01011010
01011011
01011111
01100000
01100111
01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111
Default output output output output output output
01001011
00010101
00000000 output output output output output output output output
Comment
Reserved
Reserved
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS13005 - Rev 6 page 64/122
IIS2ICLX
Embedded functions register description
13
Embedded functions register description
13.1
13.2
13.3
PAGE_SEL (02h)
Enable advanced features dedicated page (r/w)
Table 125. PAGE_SEL register
PAGE_SEL3 PAGE_SEL2 PAGE_SEL1 PAGE_SEL0
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
0
0
PAGE_SEL[3:0]
Table 126. PAGE_SEL register description
Select the advanced features dedicated page. Default value: 0000
EMB_FUNC_EN_B (05h)
Embedded functions enable register (r/w)
Table 127. EMB_FUNC_EN_B register
0
0
0
MLC_EN
1. This bit must be set to '0' for the correct operation of the device.
0
0
MLC_EN
FSM_EN
Table 128. EMB_FUNC_EN_B register description
Enable Machine Learning Core feature. Default value: 0
(0: Machine Learning Core feature disabled;
1: Machine Learning Core feature enabled)
Enable Finite State Machine (FSM) feature. Default value: 0
(0: FSM feature disabled; 1: FSM feature enabled)
0
0
1
FSM_EN
PAGE_ADDRESS (08h)
Page address register (r/w)
PAGE_
ADDR7
PAGE_
ADDR6
Table 129. PAGE_ADDRESS register
PAGE_
ADDR5
PAGE_
ADDR4
PAGE_
ADDR3
PAGE_
ADDR2
PAGE_
ADDR1
PAGE_
ADDR0
Table 130. PAGE_ADDRESS register description
PAGE_ADDR[7:0]
the address of the register to be written/read in the advanced features page selected through the bits
PAGE_SEL[3:0] in register
.
DS13005 - Rev 6 page 65/122
13.4
13.5
IIS2ICLX
PAGE_VALUE (09h)
PAGE_VALUE (09h)
Page value register (r/w)
PAGE_
VALUE7
PAGE_
VALUE6
PAGE_
VALUE5
Table 131. PAGE_VALUE register
PAGE_
VALUE4
PAGE_
VALUE3
PAGE_
VALUE2
PAGE_
VALUE1
PAGE_
VALUE0
Table 132. PAGE_VALUE register description
PAGE_VALUE[7:0]
PAGE_READ = 1 in register PAGE_RW (17h)
) the data at the address PAGE_ADDR[7:0] of the selected advanced features page.
EMB_FUNC_INT1 (0Ah)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried over INT1. The pin's output will supply the OR combination of the selected signals.
Table 133. EMB_FUNC_INT1 register
INT1_
FSM_LC
0
0
0
1. This bit must be set to '0' for the correct operation of the device.
0
0
Table 134. EMB_FUNC_INT1 register description
INT1_FSM_LC
Routing of FSM long counter timeout interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of
0
0
DS13005 - Rev 6 page 66/122
13.6
IIS2ICLX
FSM_INT1_A (0Bh)
FSM_INT1_A (0Bh)
INT1 pin control register (r/w).
Each bit in this register enables a signal to be carried over INT1. The pin's output will supply the OR combination of the selected signals.
Table 135. FSM_INT1_A register
INT1_FSM8 INT1_FSM7 INT1_FSM6 INT1_FSM5 INT1_FSM4 INT1_FSM3 INT1_FSM2 INT1_FSM1
Table 136. FSM_INT1_A register description
Routing of FSM8 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM7 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM6 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM5 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM4 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM3 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM2 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM1 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of
DS13005 - Rev 6 page 67/122
13.7
IIS2ICLX
FSM_INT1_B (0Ch)
FSM_INT1_B (0Ch)
INT1 pin control register (r/w).
Each bit in this register enables a signal to be carried over INT1. The pin's output will supply the OR combination of the selected signals.
Table 137. FSM_INT1_B register
INT1_FSM16 INT1_FSM15 INT1_FSM14 INT1_FSM13 INT1_FSM12 INT1_FSM11 INT1_FSM10 INT1_FSM9
Table 138. FSM_INT1_B register description
INT1_FSM16
INT1_FSM15
INT1_FSM14
INT1_FSM13
INT1_FSM12
INT1_FSM11
INT1_FSM10
Routing of FSM16 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM15 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM14 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM13 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM12 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM11 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM10 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM9 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of
DS13005 - Rev 6 page 68/122
13.8
13.9
IIS2ICLX
MLC_INT1 (0Dh)
INT1_MLC8
INT1_MLC7
INT1_MLC6
INT1_MLC5
INT1_MLC4
INT1_MLC3
INT1_MLC2
INT1_MLC1
MLC_INT1 (0Dh)
INT1 pin control register (r/w).
Each bit in this register enables a signal to be carried over INT1. The pin's output will supply the OR combination of the selected signals.
Table 139. MLC_INT1 register
INT1_MLC8 INT1_MLC7 INT1_MLC6 INT1_MLC5 INT1_MLC4 INT1_MLC3 INT1_MLC2 INT1_MLC1
Table 140. MLC_INT1 register description
Routing of MLC8 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of MLC7 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of MLC6 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of MLC5 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of MLC4 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of MLC3 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of MLC2 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of MLC1 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
EMB_FUNC_INT2 (0Eh)
INT2 pin control register (r/w).
Each bit in this register enables a signal to be carried over INT2. The pin's output will supply the OR combination of the selected signals.
Table 141. EMB_FUNC_INT2 register
INT2_
FSM_LC
0
0
0
1. This bit must be set to '0' for the correct operation of the device.
0
0
Table 142. EMB_FUNC_INT2 register description
INT2_FSM_LC
Routing of FSM long counter timeout interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of
is set to 1.
0
0
DS13005 - Rev 6 page 69/122
IIS2ICLX
FSM_INT2_A (0Fh)
13.10
FSM_INT2_A (0Fh)
INT2 pin control register (r/w).
Each bit in this register enables a signal to be carried over INT2. The pin's output will supply the OR combination of the selected signals.
Table 143. FSM_INT2_A register
INT2_FSM8 INT2_FSM7 INT2_FSM6 INT2_FSM5 INT2_FSM4 INT2_FSM3 INT2_FSM2 INT2_FSM1
Table 144. FSM_INT2_A register description
Routing of FSM8 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM7 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM6 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM5 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM4 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM3 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM2 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM1 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of
is set to 1.
DS13005 - Rev 6 page 70/122
IIS2ICLX
FSM_INT2_B (10h)
13.11
FSM_INT2_B (10h)
INT2 pin control register (r/w).
Each bit in this register enables a signal to be carried over INT2. The pin's output will supply the OR combination of the selected signals.
Table 145. FSM_INT2_B register
INT2_FSM16 INT2_FSM15 INT2_FSM14 INT2_FSM13 INT2_FSM12 INT2_FSM11 INT2_FSM10 INT2_FSM9
Table 146. FSM_INT2_B register description
INT2_FSM16
INT2_FSM15
INT2_FSM14
INT2_FSM13
INT2_FSM12
INT2_FSM11
INT2_FSM10
Routing of FSM16 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM15 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM14 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM13 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM12 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM11 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM10 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM9 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of
is set to 1.
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IIS2ICLX
MLC_INT2 (11h)
13.12
13.13
INT2_MLC8
INT2_MLC7
INT2_MLC6
INT2_MLC5
INT2_MLC4
INT2_MLC3
INT2_MLC2
INT2_MLC1
MLC_INT2 (11h)
INT2 pin control register (r/w).
Each bit in this register enables a signal to be carried over INT2. The pin's output will supply the OR combination of the selected signals.
Table 147. MLC_INT2 register
INT2_MLC8 INT2_MLC7 INT2_MLC6 INT2_MLC5 INT2_MLC4 INT2_MLC3 INT2_MLC2 INT2_MLC1
Table 148. MLC_INT2 register description
Routing of MLC8 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of MLC7 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of MLC6 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of MLC5 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of MLC4 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of MLC3 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of MLC2 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of MLC1 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
EMB_FUNC_STATUS (12h)
Embedded function status register (r)
IS_FSM_LC 0 0
Table 149. EMB_FUNC_STATUS register
0 0 0
IS_FSM_LC
Table 150. EMB_FUNC_STATUS register description
Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
0 0
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IIS2ICLX
FSM_STATUS_A (13h)
13.14
13.15
FSM_STATUS_A (13h)
Finite State Machine status register (r)
IS_FSM8 IS_FSM7
Table 151. FSM_STATUS_A register
IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
Table 152. FSM_STATUS_A register description
Interrupt status bit for FSM8 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM7 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM6 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM5 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM4 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM3 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM2 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM1 interrupt event. (1: interrupt detected; 0: no interrupt)
FSM_STATUS_B (14h)
Finite State Machine status register (r)
IS_FSM16 IS_FSM15
Table 153. FSM_STATUS_B register
IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
Table 154. FSM_STATUS_B register description
Interrupt status bit for FSM16 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM15 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM14 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM13 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM12 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM11 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM10 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM9 interrupt event. (1: interrupt detected; 0: no interrupt)
DS13005 - Rev 6 page 73/122
IIS2ICLX
MLC_STATUS (15h)
13.16
13.17
MLC_STATUS (15h)
Machine Learning Core status register (r)
IS_MLC8 IS_MLC7 IS_MLC6
Table 155. MLC_STATUS register
IS_MLC5 IS_MLC4 IS_MLC3 IS_MLC2 IS_MLC1
IS_MLC8
IS_MLC7
IS_MLC6
IS_MLC5
IS_MLC4
IS_MLC3
IS_MLC2
IS_MLC1
Table 156. MLC_STATUS register description
Interrupt status bit for MLC8 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC7 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC6 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC5 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC4 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC3 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC2 interrupt event. (1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC1 interrupt event. (1: interrupt detected; 0: no interrupt)
PAGE_RW (17h)
Enable read and write mode of advanced features dedicated page (r/w)
Table 157. PAGE_RW register
EMB_
FUNC_LIR
PAGE_
WRITE
PAGE_
READ
0
1. This bit must be set to '0' for the correct operation of the device.
0
0
0
Table 158. PAGE_RW register description
EMB_FUNC_LIR
PAGE_WRITE
PAGE_READ
Latched Interrupt mode for Embedded Functions. Default value: 0
(0: Embedded Functions interrupt request not latched;
1: Embedded Functions interrupt request latched)
Enable writes to the selected advanced features dedicated page.
(1: enable; 0: disable)
Enable reads from the selected advanced features dedicated page.
Default value: 0
(1: enable; 0: disable)
1. Page selected by PAGE_SEL[3:0] in
0
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IIS2ICLX
FSM_ENABLE_A (46h)
13.18
13.19
FSM_ENABLE_A (46h)
FSM enable register (r/w)
FSM8_EN FSM7_EN
Table 159. FSM_ENABLE_A register
FSM6_EN FSM5_EN FSM4_EN FSM3_EN FSM2_EN FSM1_EN
FSM8_EN
FSM7_EN
FSM6_EN
FSM5_EN
FSM4_EN
FSM3_EN
FSM2_EN
FSM1_EN
FSM16_EN
FSM15_EN
FSM14_EN
FSM13_EN
FSM12_EN
FSM11_EN
FSM10_EN
FSM9_EN
Table 160. FSM_ENABLE_A register description
FSM8 enable. Default value: 0 (0: FSM8 disabled; 1: FSM8 enabled)
FSM7 enable. Default value: 0 (0: FSM7 disabled; 1: FSM7 enabled)
FSM6 enable. Default value: 0 (0: FSM6 disabled; 1: FSM6 enabled)
FSM5 enable. Default value: 0 (0: FSM5 disabled; 1: FSM5 enabled)
FSM4 enable. Default value: 0 (0: FSM4 disabled; 1: FSM4 enabled)
FSM3 enable. Default value: 0 (0: FSM3 disabled; 1: FSM3 enabled)
FSM2 enable. Default value: 0 (0: FSM2 disabled; 1: FSM2 enabled)
FSM1 enable. Default value: 0 (0: FSM1 disabled; 1: FSM1 enabled)
FSM_ENABLE_B (47h)
FSM enable register (r/w)
FSM16_EN FSM15_EN
Table 161. FSM_ENABLE_B register
FSM14_EN FSM13_EN FSM12_EN FSM11_EN FSM10_EN FSM9_EN
Table 162. FSM_ENABLE_B register description
FSM16 enable. Default value: 0 (0: FSM16 disabled; 1: FSM16 enabled)
FSM15 enable. Default value: 0 (0: FSM15 disabled; 1: FSM15 enabled)
FSM14 enable. Default value: 0 (0: FSM14 disabled; 1: FSM14 enabled)
FSM13 enable. Default value: 0 (0: FSM13 disabled; 1: FSM13 enabled)
FSM12 enable. Default value: 0 (0: FSM12 disabled; 1: FSM12 enabled)
FSM11 enable. Default value: 0 (0: FSM11 disabled; 1: FSM11 enabled)
FSM10 enable. Default value: 0 (0: FSM10 disabled; 1: FSM10 enabled)
FSM9 enable. Default value: 0 (0: FSM9 disabled; 1: FSM9 enabled)
DS13005 - Rev 6 page 75/122
IIS2ICLX
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
13.20
13.21
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
FSM long counter status register (r/w).
Long counter value is an unsigned integer value (16-bit format); this value can be reset using the LC_CLEAR bit in the
register.
FSM_LC_7 FSM_LC_6
Table 163. FSM_LONG_COUNTER_L register
FSM_LC_5 FSM_LC_4 FSM_LC_3 FSM_LC_2 FSM_LC_1 FSM_LC_0
FSM_LC_[7:0]
FSM_LC_[15:8]
Table 164. FSM_LONG_COUNTER_L register description
Long counter current value (LSbyte). Default value: 00000000
Table 165. FSM_LONG_COUNTER_H register
FSM_LC_15 FSM_LC_14 FSM_LC_13 FSM_LC_12 FSM_LC_11 FSM_LC_10 FSM_LC_9 FSM_LC_8
Table 166. FSM_LONG_COUNTER_H register description
Long counter current value (MSbyte). Default value: 00000000
FSM_LONG_COUNTER_CLEAR (4Ah)
FSM long counter reset register (r/w)
Table 167. FSM_LONG_COUNTER_CLEAR register
0
0
0
0
0
1. This bit must be set to '0' for the correct operation of the device.
0
FSM_LC_
CLEARED
FSM_LC_
CLEAR
Table 168. FSM_LONG_COUNTER_CLEAR register description
FSM_LC_CLEARED This read-only bit is automatically set to 1 when the long counter reset is done. Default value: 0
FSM_LC_CLEAR Clear FSM long counter value. Default value: 0
DS13005 - Rev 6 page 76/122
13.22
Note:
13.23
Note:
FSM_OUTS1 (4Ch)
FSM1 output register (r)
P_X N_X P_Y
Table 169. FSM_OUTS1 register
N_Y P_Z N_Z 0
Table 170. FSM_OUTS1 register description
P_X FSM1 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM1 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM1 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM1 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM1 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM1 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
FSM_OUTS2 (4Dh)
FSM2 output register (r)
P_X N_X P_Y
Table 171. FSM_OUTS2 register
N_Y P_Z N_Z 0
Table 172. FSM_OUTS2 register description
P_X FSM2 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM2 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM2 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM2 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM2 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM2 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
IIS2ICLX
FSM_OUTS1 (4Ch)
0
0
DS13005 - Rev 6 page 77/122
13.24
Note:
13.25
Note:
FSM_OUTS3 (4Eh)
FSM3 output register (r)
P_X N_X P_Y
Table 173. FSM_OUTS3 register
N_Y P_Z N_Z 0
Table 174. FSM_OUTS3 register description
P_X FSM3 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM3 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM3 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM3 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM3 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM3 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
FSM_OUTS4 (4Fh)
FSM4 output register (r)
P_X N_X P_Y
Table 175. FSM_OUTS4 register
N_Y P_Z N_Z 0
Table 176. FSM_OUTS4 register description
P_X FSM4 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM4 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM4 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM4 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM4 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM4 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
IIS2ICLX
FSM_OUTS3 (4Eh)
0
0
DS13005 - Rev 6 page 78/122
13.26
Note:
13.27
Note:
FSM_OUTS5 (50h)
FSM5 output register (r)
P_X N_X P_Y
Table 177. FSM_OUTS5 register
N_Y P_Z N_Z 0
Table 178. FSM_OUTS5 register description
P_X FSM5 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM5 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM5 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM5 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM5 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM5 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
FSM_OUTS6 (51h)
FSM6 output register (r)
P_X N_X P_Y
Table 179. FSM_OUTS6 register
N_Y P_Z N_Z 0
Table 180. FSM_OUTS6 register description
P_X FSM6 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM6 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM6 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM6 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM6 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM6 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
IIS2ICLX
FSM_OUTS5 (50h)
0
0
DS13005 - Rev 6 page 79/122
13.28
Note:
13.29
Note:
FSM_OUTS7 (52h)
FSM7 output register (r)
P_X N_X P_Y
Table 181. FSM_OUTS7 register
N_Y P_Z N_Z 0
Table 182. FSM_OUTS7 register description
P_X FSM7 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM7 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM7 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM7 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM7 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM7 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
FSM_OUTS8 (53h)
FSM8 output register (r)
P_X N_X P_Y
Table 183. FSM_OUTS8 register
N_Y P_Z N_Z 0
Table 184. FSM_OUTS8 register description
P_X FSM8 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM8 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM8 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM8 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM8 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM8 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
IIS2ICLX
FSM_OUTS7 (52h)
0
0
DS13005 - Rev 6 page 80/122
13.30
Note:
13.31
Note:
FSM_OUTS9 (54h)
FSM9 output register (r)
P_X N_X P_Y
Table 185. FSM_OUTS9 register
N_Y P_Z N_Z 0
Table 186. FSM_OUTS9 register description
P_X FSM9 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM9 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM9 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM9 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM9 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM9 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
FSM_OUTS10 (55h)
FSM10 output register (r)
P_X N_X P_Y
Table 187. FSM_OUTS10 register
N_Y P_Z N_Z 0
Table 188. FSM_OUTS10 register description
P_X FSM10 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM10 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM10 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM10 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM10 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM10 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
IIS2ICLX
FSM_OUTS9 (54h)
0
0
DS13005 - Rev 6 page 81/122
13.32
Note:
13.33
Note:
FSM_OUTS11 (56h)
FSM11 output register (r)
P_X N_X P_Y
Table 189. FSM_OUTS11 register
N_Y P_Z N_Z 0
Table 190. FSM_OUTS11 register description
P_X FSM11 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM11 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM11 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM11 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM11 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM11 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
FSM_OUTS12 (57h)
FSM12 output register (r)
P_X N_X P_Y
Table 191. FSM_OUTS12 register
N_Y P_Z N_Z 0
Table 192. FSM_OUTS12 register description
P_X FSM12 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM12 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM12 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM12 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM12 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM12 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
IIS2ICLX
FSM_OUTS11 (56h)
0
0
DS13005 - Rev 6 page 82/122
13.34
Note:
13.35
Note:
FSM_OUTS13 (58h)
FSM13 output register (r)
P_X N_X P_Y
Table 193. FSM_OUTS13 register
N_Y P_Z N_Z 0
Table 194. FSM_OUTS13 register description
P_X FSM13 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM13 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM13 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM13 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM13 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM13 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
FSM_OUTS14 (59h)
FSM14 output register (r)
P_X N_X P_Y
Table 195. FSM_OUTS14 register
N_Y P_Z N_Z 0
Table 196. FSM_OUTS14 register description
P_X FSM14 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM14 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM14 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM14 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM14 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM14 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
IIS2ICLX
FSM_OUTS13 (58h)
0
0
DS13005 - Rev 6 page 83/122
13.36
Note:
13.37
Note:
FSM_OUTS15 (5Ah)
FSM15 output register (r)
P_X N_X P_Y
Table 197. FSM_OUTS15 register
N_Y P_Z N_Z 0
Table 198. FSM_OUTS15 register description
P_X FSM15 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM15 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM15 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM15 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM15 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM15 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
FSM_OUTS16 (5Bh)
FSM16 output register (r)
P_X N_X P_Y
Table 199. FSM_OUTS16 register
N_Y P_Z N_Z 0
Table 200. FSM_OUTS16 register description
P_X FSM16 output: positive event detected on the X-axis. (0: event not detected; 1: event detected)
N_X FSM16 output: negative event detected on the X-axis. (0: event not detected; 1: event detected)
P_Y FSM16 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected)
N_Y FSM16 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected)
P_Z FSM16 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected)
N_Z FSM16 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected)
Fields related to the Z-axis are intended for use in conjunction with an external sensor.
IIS2ICLX
FSM_OUTS15 (5Ah)
0
0
DS13005 - Rev 6 page 84/122
IIS2ICLX
EMB_FUNC_ODR_CFG_B (5Fh)
13.38
13.39
13.40
EMB_FUNC_ODR_CFG_B (5Fh)
Finite State Machine output data rate configuration register (r/w)
Table 201. EMB_FUNC_ODR_CFG_B register
0
1
0
FSM_ODR1 FSM_ODR0
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device
0
FSM_ODR[1:0]
Table 202. EMB_FUNC_ODR_CFG_B register description
Finite State Machine ODR configuration:
(00: 12.5 Hz;
01: 26 Hz (default);
10: 52 Hz;
11: 104 Hz)
1
EMB_FUNC_ODR_CFG_C (60h)
Machine Learning Core output data rate configuration register (r/w)
Table 203. EMB_FUNC_ODR_CFG_C register
0
0
MLC_ODR1 MLC_ODR0
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
0
1
MLC_ODR[1:0]
Table 204. EMB_FUNC_ODR_CFG_C register description
Machine Learning Core ODR configuration:
(00: 12.5 Hz;
01: 26 Hz (default);
10: 52 Hz;
11: 104 Hz)
0
EMB_FUNC_INIT_B (67h)
Embedded functions initialization register (r/w)
Table 205. EMB_FUNC_INIT_B register
0
0
0
MLC_INIT
1. This bit must be set to '0' for the correct operation of the device.
0
0
MLC_INIT
FSM_INIT
Table 206. EMB_FUNC_INIT_B register description
Machine Learning Core initialization request. Default value: 0
FSM initialization request. Default value: 0
0
1
1
FSM_INIT
DS13005 - Rev 6 page 85/122
IIS2ICLX
MLC0_SRC (70h)
13.41
13.42
13.43
13.44
MLC0_SRC (70h)
Machine Learning Core source register (r)
MLC0_
SRC_7
MLC0_
SRC_6
MLC0_
SRC_5
Table 207. MLC0_SRC register
MLC0_
SRC_4
MLC0_
SRC_3
MLC0_
SRC_2
MLC0_SRC_[7:0]
Table 208. MLC0_SRC register description
Output value of MLC0 decision tree
MLC1_SRC (71h)
Machine Learning Core source register (r)
MLC1_
SRC_7
MLC1_
SRC_6
MLC1_
SRC_5
Table 209. MLC1_SRC register
MLC1_
SRC_4
MLC1_
SRC_3
MLC1_
SRC_2
MLC1_SRC_[7:0]
Table 210. MLC1_SRC register description
Output value of MLC1 decision tree
MLC2_SRC (72h)
Machine Learning Core source register (r)
MLC2_
SRC_7
MLC2_
SRC_6
MLC2_
SRC_5
Table 211. MLC2_SRC register
MLC2_
SRC_4
MLC2_
SRC_3
MLC2_
SRC_2
MLC2_SRC_[7:0]
Table 212. MLC2_SRC register description
Output value of MLC2 decision tree
MLC3_SRC (73h)
Machine Learning Core source register (r)
MLC3_
SRC_7
MLC3_
SRC_6
MLC3_
SRC_5
Table 213. MLC3_SRC register
MLC3_
SRC_4
MLC3_
SRC_3
MLC3_
SRC_2
MLC3_SRC_[7:0]
Table 214. MLC3_SRC register description
Output value of MLC3 decision tree
MLC0_
SRC_1
MLC0_
SRC_0
MLC1_
SRC_1
MLC1_
SRC_0
MLC2_
SRC_1
MLC2_
SRC_0
MLC3_
SRC_1
MLC3_
SRC_0
DS13005 - Rev 6 page 86/122
IIS2ICLX
MLC4_SRC (74h)
13.45
13.46
13.47
13.48
MLC4_SRC (74h)
Machine Learning Core source register (r)
MLC4_
SRC_7
MLC4_
SRC_6
MLC4_
SRC_5
Table 215. MLC4_SRC register
MLC4_
SRC_4
MLC4_
SRC_3
MLC4_
SRC_2
MLC4_SRC_[7:0]
Table 216. MLC4_SRC register description
Output value of MLC4 decision tree
MLC5_SRC (75h)
Machine Learning Core source register (r)
MLC5_
SRC_7
MLC5_
SRC_6
MLC5_
SRC_5
Table 217. MLC5_SRC register
MLC5_
SRC_4
MLC5_
SRC_3
MLC5_
SRC_2
MLC5_SRC_[7:0]
Table 218. MLC5_SRC register description
Output value of MLC5 decision tree
MLC6_SRC (76h)
Machine Learning Core source register (r)
MLC6_
SRC_7
MLC6_
SRC_6
MLC6_
SRC_5
Table 219. MLC6_SRC register
MLC6_
SRC_4
MLC6_
SRC_3
MLC6_
SRC_2
MLC6_SRC_[7:0]
Table 220. MLC6_SRC register description
Output value of MLC6 decision tree
MLC7_SRC (77h)
Machine Learning Core source register (r)
MLC7_
SRC_7
MLC7_
SRC_6
MLC7_
SRC_5
Table 221. MLC7_SRC register
MLC7_
SRC_4
MLC7_
SRC_3
MLC7_
SRC_2
MLC7_SRC_[7:0]
Table 222. MLC7_SRC register description
Output value of MLC7 decision tree
MLC4_
SRC_1
MLC4_
SRC_0
MLC5_
SRC_1
MLC5_
SRC_0
MLC6_
SRC_1
MLC6_
SRC_0
MLC7_
SRC_1
MLC7_
SRC_0
DS13005 - Rev 6 page 87/122
14
IIS2ICLX
Embedded advanced features
Embedded advanced features
The following table provides a list of the registers for the embedded advanced features page 1. These registers are accessible when PAGE_SEL[3:0] are set to 0001 in
.
Table 223. Register address map - embedded advanced features page 1
Name
FSM_LC_TIMEOUT_L
FSM_LC_TIMEOUT_H
FSM_PROGRAMS
FSM_START_ADD_L
FSM_START_ADD_H
Type
RW
RW
RW
RW
RW
Hex
Register address
Binary
7A
7B
7C
7E
7F
01111010
01111011
01111100
01111110
01111111
Default
00000000
00000000
00000000
00000000
00000000
Comment
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
Write procedure example:
Example: write value 01h of register at address 7Ch (FSM_PROGRAMS) in Page 1
1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h)
2. Write bit PAGE_WRITE = 1 in PAGE_RW (17h) register
3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h)
4. Write 7Ch in PAGE_ADDR register (08h)
5. Write 06h in PAGE_DATA register (09h)
6. Write bit PAGE_WRITE = 0 in PAGE_RW (17h) register
7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h)
// Enable access to embedded functions registers
// Select write operation mode
// Select page 1
// Set address
// Set value to be written
// Write operation disabled
// Disable access to embedded functions registers
Read procedure example:
Example: read value of register at address 7Ch (FSM_PROGRAMS) in Page 1
1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h)
2. Write bit PAGE_READ = 1 in PAGE_RW (17h) register
3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h)
4. Write 7Ch in PAGE_ADDR register (08h)
5. Read value of PAGE_DATA register (09h)
6. Write bit PAGE_READ = 0 in PAGE_RW (17h) register
7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h)
// Enable access to embedded functions registers
// Select read operation mode
// Select page 1
// Set address
// Get register value
// Read operation disabled
// Disable access to embedded functions registers
Note: Steps 1 and 2 of both procedures are intended to be performed at the beginning of the procedure. Steps
6 and 7 of both procedures are intended to be performed at the end of the procedure. If the procedure involves multiple operations, only steps 3, 4 and 5 must be repeated for each operation. If, in particular, the multiple operations involve consecutive registers, only step 5 can be performed.
DS13005 - Rev 6 page 88/122
15
IIS2ICLX
Embedded advanced features register description
Embedded advanced features register description
15.1
15.1.1
15.1.2
Page 1 - Embedded advanced features registers
FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh)
FSM long counter timeout register (r/w).
The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reaches this value, the FSM generates an interrupt.
FSM_LC_
TIMEOUT7
FSM_LC_
TIMEOUT6
Table 224. FSM_LC_TIMEOUT_L register
FSM_LC_
TIMEOUT5
FSM_LC_
TIMEOUT4
FSM_LC_
TIMEOUT3
FSM_LC_
TIMEOUT2
FSM_LC_
TIMEOUT1
FSM_LC_
TIMEOUT0
FSM_LC_TIMEOUT[7:0]
Table 225. FSM_LC_TIMEOUT_L register description
FSM long counter timeout value (LSbyte). Default value: 00000000
FSM_LC_
TIMEOUT15
FSM_LC_
TIMEOUT14
Table 226. FSM_LC_TIMEOUT_H register
FSM_LC_
TIMEOUT13
FSM_LC_
TIMEOUT12
FSM_LC_
TIMEOUT11
FSM_LC_
TIMEOUT10
FSM_LC_
TIMEOUT9
FSM_LC_
TIMEOUT8
FSM_LC_TIMEOUT[15:8]
Table 227. FSM_LC_TIMEOUT_H register description
FSM long counter timeout value (MSbyte). Default value: 00000000
FSM_PROGRAMS (7Ch)
FSM number of programs register (r/w)
FSM_N_
PROG7
FSM_N_
PROG6
Table 228. FSM_PROGRAMS register
FSM_N_
PROG5
FSM_N_
PROG4
FSM_N_
PROG3
FSM_N_
PROG2
FSM_N_
PROG1
FSM_N_PROG[7:0]
Table 229. FSM_PROGRAMS register description
Number of FSM programs; must be less than or equal to 16. Default value: 00000000
FSM_N_
PROG0
DS13005 - Rev 6 page 89/122
IIS2ICLX
Page 1 - Embedded advanced features registers
15.1.3
FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh)
FSM start address register (r/w). First available address is 0x033C.
FSM_
START7
FSM_
START6
Table 230. FSM_START_ADD_L register
FSM_
START5
FSM_
START4
FSM_
START3
FSM_
START2
FSM_
START1
FSM_START[7:0]
FSM_START[15:8]
Table 231. FSM_START_ADD_L register description
FSM start address value (LSbyte). Default value: 00000000
FSM_
START15
FSM_
START14
Table 232. FSM_START_ADD_H register
FSM_
START13
FSM_
START12
FSM_
START11
FSM_
START10
FSM_
START9
Table 233. FSM_START_ADD_H register description
FSM start address value (MSbyte). Default value: 00000000
FSM_
START0
FSM_
START8
DS13005 - Rev 6 page 90/122
IIS2ICLX
Sensor hub register map
16
Sensor hub register map
Name
SENSOR_HUB_1
SENSOR_HUB_2
SENSOR_HUB_3
SENSOR_HUB_4
SENSOR_HUB_5
SENSOR_HUB_6
SENSOR_HUB_7
SENSOR_HUB_8
SENSOR_HUB_9
SENSOR_HUB_10
SENSOR_HUB_11
SENSOR_HUB_12
SENSOR_HUB_13
SENSOR_HUB_14
SENSOR_HUB_15
SENSOR_HUB_16
SENSOR_HUB_17
SENSOR_HUB_18
MASTER_CONFIG
SLV0_ADD
SLV0_SUBADD
SLV0_CONFIG
SLV1_ADD
SLV1_SUBADD
SLV1_CONFIG
SLV2_ADD
SLV2_SUBADD
SLV2_CONFIG
SLV3_ADD
SLV3_SUBADD
SLV3_CONFIG
DATAWRITE_SLV0
STATUS_MASTER
The table given below provides a list of the registers for the sensor hub functions available in the device and the corresponding addresses. The sensor hub registers are accessible when bit SHUB_REG_ACCESS is set to '1' in
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
R
R
R
R
Type
Table 234. Registers address map
Register address
Binary
00000010
00000011
00000100
00000101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
11
12
13
0E
0F
10
14
15
09
0A
0B
0C
0D
Hex
02
06
07
08
03
04
05
1F
20
21
22
1C
1D
1E
19
1A
1B
16
17
18
Comment Default output output output output output output
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000 output output output output output output output output output output output output output
DS13005 - Rev 6 page 91/122
IIS2ICLX
Sensor hub register map
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS13005 - Rev 6 page 92/122
IIS2ICLX
Sensor hub register description
17
Sensor hub register description
17.1
17.2
17.3
SENSOR_HUB_1 (02h)
Sensor hub output register (r)
First byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub1_7
Sensor
Hub1_6
Table 235. SENSOR_HUB_1 register
Sensor
Hub1_5
Sensor
Hub1_4
Sensor
Hub1_3
Sensor
Hub1_2
Sensor
Hub1_1
Sensor
Hub1_0
SensorHub1[7:0]
Table 236. SENSOR_HUB_1 register description
First byte associated to external sensors
SENSOR_HUB_2 (03h)
Sensor hub output register (r)
Second byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub2_7
Sensor
Hub2_6
Table 237. SENSOR_HUB_2 register
Sensor
Hub2_5
Sensor
Hub2_4
Sensor
Hub2_3
Sensor
Hub2_2
Sensor
Hub2_1
Sensor
Hub2_0
SensorHub2[7:0]
SensorHub3[7:0]
Table 238. SENSOR_HUB_2 register description
Second byte associated to external sensors
SENSOR_HUB_3 (04h)
Sensor hub output register (r)
Third byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub3_7
Sensor
Hub3_6
Table 239. SENSOR_HUB_3 register
Sensor
Hub3_5
Sensor
Hub3_4
Sensor
Hub3_3
Sensor
Hub3_2
Sensor
Hub3_1
Sensor
Hub3_0
Table 240. SENSOR_HUB_3 register description
Third byte associated to external sensors
DS13005 - Rev 6 page 93/122
17.4
17.5
17.6
IIS2ICLX
SENSOR_HUB_4 (05h)
SENSOR_HUB_4 (05h)
Sensor hub output register (r)
Fourth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub4_7
Sensor
Hub4_6
Table 241. SENSOR_HUB_4 register
Sensor
Hub4_5
Sensor
Hub4_4
Sensor
Hub4_3
Sensor
Hub4_2
Sensor
Hub4_1
Sensor
Hub4_0
SensorHub4[7:0]
SensorHub5[7:0]
Table 242. SENSOR_HUB_4 register description
Fourth byte associated to external sensors
SENSOR_HUB_5 (06h)
Sensor hub output register (r)
Fifth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub5_7
Sensor
Hub5_6
Table 243. SENSOR_HUB_5 register
Sensor
Hub5_5
Sensor
Hub5_4
Sensor
Hub5_3
Sensor
Hub5_2
Sensor
Hub5_1
Sensor
Hub5_0
Table 244. SENSOR_HUB_5 register description
Fifth byte associated to external sensors
SENSOR_HUB_6 (07h)
Sensor hub output register (r)
Sixth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub6_7
Sensor
Hub6_6
Table 245. SENSOR_HUB_6 register
Sensor
Hub6_5
Sensor
Hub6_4
Sensor
Hub6_3
Sensor
Hub6_2
Sensor
Hub6_1
Sensor
Hub6_0
SensorHub6[7:0]
Table 246. SENSOR_HUB_6 register description
Sixth byte associated to external sensors
DS13005 - Rev 6 page 94/122
17.7
17.8
17.9
IIS2ICLX
SENSOR_HUB_7 (08h)
SENSOR_HUB_7 (08h)
Sensor hub output register (r)
Seventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub7_7
Sensor
Hub7_6
Table 247. SENSOR_HUB_7 register
Sensor
Hub7_5
Sensor
Hub7_4
Sensor
Hub7_3
Sensor
Hub7_2
Sensor
Hub7_1
Sensor
Hub7_0
SensorHub7[7:0]
SensorHub8[7:0]
Table 248. SENSOR_HUB_7 register description
Seventh byte associated to external sensors
SENSOR_HUB_8 (09h)
Sensor hub output register (r)
Eighth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub8_7
Sensor
Hub8_6
Table 249. SENSOR_HUB_8 register
Sensor
Hub8_5
Sensor
Hub8_4
Sensor
Hub8_3
Sensor
Hub8_2
Sensor
Hub8_1
Sensor
Hub8_0
Table 250. SENSOR_HUB_8 register description
Eighth byte associated to external sensors
SENSOR_HUB_9 (0Ah)
Sensor hub output register (r)
Ninth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub9_7
Sensor
Hub9_6
Table 251. SENSOR_HUB_9 register
Sensor
Hub9_5
Sensor
Hub9_4
Sensor
Hub9_3
Sensor
Hub9_2
Sensor
Hub9_1
Sensor
Hub9_0
SensorHub9[7:0]
Table 252. SENSOR_HUB_9 register description
Ninth byte associated to external sensors
DS13005 - Rev 6 page 95/122
IIS2ICLX
SENSOR_HUB_10 (0Bh)
17.10
17.11
17.12
SENSOR_HUB_10 (0Bh)
Sensor hub output register (r)
Tenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub10_7
Sensor
Hub10_6
Table 253. SENSOR_HUB_10 register
Sensor
Hub10_5
Sensor
Hub10_4
Sensor
Hub10_3
Sensor
Hub10_2
Sensor
Hub10_1
Sensor
Hub10_0
SensorHub10[7:0]
SensorHub11[7:0]
Table 254. SENSOR_HUB_10 register description
Tenth byte associated to external sensors
SENSOR_HUB_11 (0Ch)
Sensor hub output register (r)
Eleventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub11_7
Sensor
Hub11_6
Table 255. SENSOR_HUB_11 register
Sensor
Hub11_5
Sensor
Hub11_4
Sensor
Hub11_3
Sensor
Hub11_2
Sensor
Hub11_1
Sensor
Hub11_0
Table 256. SENSOR_HUB_11 register description
Eleventh byte associated to external sensors
SENSOR_HUB_12 (0Dh)
Sensor hub output register (r)
Twelfth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub12_7
Sensor
Hub12_6
Table 257. SENSOR_HUB_12 register
Sensor
Hub12_5
Sensor
Hub12_4
Sensor
Hub12_3
Sensor
Hub12_2
Sensor
Hub12_1
Sensor
Hub12_0
SensorHub12[7:0]
Table 258. SENSOR_HUB_12 register description
Twelfth byte associated to external sensors
DS13005 - Rev 6 page 96/122
IIS2ICLX
SENSOR_HUB_13 (0Eh)
17.13
17.14
17.15
SENSOR_HUB_13 (0Eh)
Sensor hub output register (r)
Thirteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub13_7
Sensor
Hub13_6
Table 259. SENSOR_HUB_13 register
Sensor
Hub13_5
Sensor
Hub13_4
Sensor
Hub13_3
Sensor
Hub13_2
Sensor
Hub13_1
Sensor
Hub13_0
SensorHub13[7:0]
SensorHub14[7:0]
Table 260. SENSOR_HUB_13 register description
Thirteenth byte associated to external sensors
SENSOR_HUB_14 (0Fh)
Sensor hub output register (r)
Fourteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub14_7
Sensor
Hub14_6
Table 261. SENSOR_HUB_14 register
Sensor
Hub14_5
Sensor
Hub14_4
Sensor
Hub14_3
Sensor
Hub14_2
Sensor
Hub14_1
Sensor
Hub14_0
Table 262. SENSOR_HUB_14 register description
Fourteenth byte associated to external sensors
SENSOR_HUB_15 (10h)
Sensor hub output register (r)
Fifteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub15_7
Sensor
Hub15_6
Table 263. SENSOR_HUB_15 register
Sensor
Hub15_5
Sensor
Hub15_4
Sensor
Hub15_3
Sensor
Hub15_2
Sensor
Hub15_1
Sensor
Hub15_0
SensorHub15[7:0]
Table 264. SENSOR_HUB_15 register description
Fifteenth byte associated to external sensors
DS13005 - Rev 6 page 97/122
IIS2ICLX
SENSOR_HUB_16 (11h)
17.16
17.17
17.18
SENSOR_HUB_16 (11h)
Sensor hub output register (r)
Sixteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub16_7
Sensor
Hub16_6
Table 265. SENSOR_HUB_16 register
Sensor
Hub16_5
Sensor
Hub16_4
Sensor
Hub16_3
Sensor
Hub16_2
Sensor
Hub16_1
Sensor
Hub16_0
SensorHub16[7:0]
SensorHub17[7:0]
Table 266. SENSOR_HUB_16 register description
Sixteenth byte associated to external sensors
SENSOR_HUB_17 (12h)
Sensor hub output register (r)
Seventeenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub17_7
Sensor
Hub17_6
Table 267. SENSOR_HUB_17 register
Sensor
Hub17_5
Sensor
Hub17_4
Sensor
Hub17_3
Sensor
Hub17_2
Sensor
Hub17_1
Sensor
Hub17_0
Table 268. SENSOR_HUB_17 register description
Seventeenth byte associated to external sensors
SENSOR_HUB_18 (13h)
Sensor hub output register (r)
Eighteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub18_7
Sensor
Hub18_6
Table 269. SENSOR_HUB_18 register
Sensor
Hub18_5
Sensor
Hub18_4
Sensor
Hub18_3
Sensor
Hub18_2
Sensor
Hub18_1
Sensor
Hub18_0
SensorHub18[7:0]
Table 270. SENSOR_HUB_18 register description
Eighteenth byte associated to external sensors
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IIS2ICLX
MASTER_CONFIG (14h)
17.19
17.20
MASTER_CONFIG (14h)
Master configuration register (r/w)
RST_MASTER
_REGS
WRITE_
ONCE
Table 271. MASTER_CONFIG register
START_
CONFIG
PASS_THROUGH
_MODE
SHUB_
PU_EN
MASTER
_ON
AUX_SENS
_ON1
AUX_SENS
_ON0
Table 272. MASTER_CONFIG register description
RST_MASTER_REGS
WRITE_ONCE
START_CONFIG
PASS_THROUGH_MODE
SHUB_PU_EN
MASTER_ON
AUX_SENS_ON[1:0]
Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. Default value: 0
Slave 0 write operation is performed only at the first sensor hub cycle.
Default value: 0
(0: write operation for each sensor hub cycle;
1: write operation only for the first sensor hub cycle)
Sensor hub trigger signal selection. Default value: 0
(0: sensor hub trigger signal is the accelerometer data-ready;
1: sensor hub trigger signal external from INT2 pin)
I²C interface pass-through. Default value: 0
(0: pass-through disabled;
1: pass-through enabled, main I²C line is short-circuited with the auxiliary line)
Master I²C pull-up enable. Default value: 0
(0: internal pull-up on auxiliary I²C line disabled;
1: internal pull-up on auxiliary I²C line enabled)
Sensor hub I²C master enable. Default: 0
(0: master I²C of sensor hub disabled; 1: master I²C of sensor hub enabled)
Number of external sensors to be read by the sensor hub.
(00: one sensor (default);
01: two sensors;
10: three sensors;
11: four sensors)
SLV0_ADD (15h)
I²C slave address of the first external sensor (Sensor 1) register (r/w) slave0_ add6 slave0_ add5 slave0_ add4
Table 273. SLV0_ADD register slave0_ add3 slave0_ add2 slave0_ add1 slave0_ add0 slave0_add[6:0] rw_0
Table 274. SLV0_ADD register description
I²C slave address of Sensor1 that can be read by the sensor hub. Default value: 0000000
Read/write operation on Sensor 1. Default value: 0
(0: write operation; 1: read operation) rw_0
DS13005 - Rev 6 page 99/122
IIS2ICLX
SLV0_SUBADD (16h)
17.21
17.22
17.23
SLV0_SUBADD (16h)
Address of register on the first external sensor (Sensor 1) register (r/w) slave0_ reg7 slave0_ reg6 slave0_ reg5
Table 275. SLV0_SUBADD register slave0_ reg4 slave0_ reg3 slave0_ reg2 slave0_ reg1 slave0_ reg0
Table 276. SLV0_SUBADD register description slave0_reg[7:0]
Address of register on Sensor1 that has to be read/written according to the rw_0 bit value in
(15h) . Default value: 00000000
SLAVE0_CONFIG (17h)
First external sensor (Sensor1) configuration and sensor hub settings register (r/w)
Table 277. SLAVE0_CONFIG register
SHUB_
ODR_1
SHUB_
ODR_0
0
0
BATCH_EXT_
SENS_0_EN
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave0_ numop2
SHUB_ODR_[1:0]
BATCH_EXT_SENS_0_EN
Slave0_numop[2:0]
Table 278. SLAVE0_CONFIG register description
Rate at which the master communicates. Default value: 00
(00: 104 Hz (or the accelerometer ODR if it is less than 104 Hz);
01: 52 Hz (or the accelerometer ODR if it is less than 52 Hz);
10: 26 Hz (or the accelerometer ODR if it is less than 26 Hz);
11: 12.5 Hz (or the accelerometer ODR if it is less than 12.5 Hz)
Enable FIFO data batching of first slave. Default value: 0
Number of read operations on Sensor 1. Default value: 000
Slave0_ numop1
Slave0_ numop0
SLV1_ADD (18h)
I²C slave address of the second external sensor (Sensor 2) register (r/w)
Slave1_ add6
Slave1_ add5
Slave1_ add4
Table 279. SLV1_ADD register
Slave1_ add3
Slave1_ add2
Slave1_ add1
Slave1_add[6:0] r_1
Table 280. SLV1_ADD register description
I²C slave address of Sensor 2 that can be read by the sensor hub.
Default value: 0000000
Read operation on Sensor 2 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
Slave1_ add0 r_1
DS13005 - Rev 6 page 100/122
IIS2ICLX
SLV1_SUBADD (19h)
17.24
17.25
17.26
SLV1_SUBADD (19h)
Address of register on the second external sensor (Sensor 2) register (r/w)
Slave1_ reg7
Slave1_ reg6
Slave1_ reg5
Table 281. SLV1_SUBADD register
Slave1_ reg4
Slave1_ reg3
Slave1_ reg2
Slave1_ reg1
Slave1_ reg0
Table 282. SLV1_SUBADD register description
Slave1_reg[7:0]
SLAVE1_CONFIG (1Ah)
Second external sensor (Sensor 2) configuration register (r/w)
Table 283. SLAVE1_CONFIG register
0
0
0
0
BATCH_EXT_
SENS_1_EN
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave1_ numop2
Slave1_ numop1
BATCH_EXT_SENS_1_EN
Slave1_numop[2:0]
Table 284. SLAVE1_CONFIG register description
Enable FIFO data batching of second slave. Default value: 0
Number of read operations on Sensor 2. Default value: 000
Slave1_ numop0
SLV2_ADD (1Bh)
I²C slave address of the third external sensor (Sensor 3) register (r/w)
Slave2_ add6
Slave2_ add5
Slave2_ add4
Table 285. SLV2_ADD register
Slave2_ add3
Slave2_ add2
Slave2_ add1
Slave2_add[6:0] r_2
Table 286. SLV2_ADD register description
I²C slave address of Sensor 3 that can be read by the sensor hub.
Read operation on Sensor 3 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
Slave2_ add0 r_2
DS13005 - Rev 6 page 101/122
IIS2ICLX
SLV2_SUBADD (1Ch)
17.27
17.28
17.29
SLV2_SUBADD (1Ch)
Address of register on the third external sensor (Sensor 3) register (r/w)
Slave2_ reg7
Slave2_ reg6
Slave2_ reg5
Table 287. SLV2_SUBADD register
Slave2_ reg4
Slave2_ reg3
Slave2_ reg2
Slave2_ reg1
Slave2_ reg0
Table 288. SLV2_SUBADD register description
Slave2_reg[7:0]
.
SLAVE2_CONFIG (1Dh)
Third external sensor (Sensor 3) configuration register (r/w)
Table 289. SLAVE2_CONFIG register
0
0
0
0
BATCH_EXT_
SENS_2_EN
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave2_ numop2
BATCH_EXT_SENS_2_EN
Slave2_numop[2:0]
Table 290. SLAVE2_CONFIG register description
Enable FIFO data batching of third slave. Default value: 0
Number of read operations on Sensor 3. Default value: 000
Slave2_ numop1
Slave2_ numop0
SLV3_ADD (1Eh)
I²C slave address of the fourth external sensor (Sensor 4) register (r/w)
Slave3_ add6
Slave3_ add5
Slave3_ add4
Table 291. SLV3_ADD register
Slave3_ add3
Slave3_ add2
Slave3_ add1
Slave3_add[6:0] r_3
Table 292. SLV3_ADD register description
I²C slave address of Sensor 4 that can be read by the sensor hub.
Read operation on Sensor 4 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
Slave3_ add0 r_3
DS13005 - Rev 6 page 102/122
IIS2ICLX
SLV3_SUBADD (1Fh)
17.30
17.31
17.32
SLV3_SUBADD (1Fh)
Address of register on the fourth external sensor (Sensor 4) register (r/w)
Slave3_ reg7
Slave3_ reg6
Slave3_ reg5
Table 293. SLV3_SUBADD register
Slave3_ reg4
Slave3_ reg3
Slave3_ reg2
Slave3_ reg1
Slave3_ reg0
Table 294. SLV3_SUBADD register description
Slave3_reg[7:0] Address of register on Sensor 4 that has to be read according to the r_3 bit value in
SLAVE3_CONFIG (20h)
Fourth external sensor (Sensor 4) configuration register (r/w)
Table 295. SLAVE3_CONFIG register
0
0
0
0
BATCH_EXT_
SENS_3_EN
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave3_ numop2
BATCH_EXT_SENS_3_EN
Slave3_numop[2:0]
Table 296. SLAVE3_CONFIG register description
Enable FIFO data batching of fourth slave. Default value: 0
Number of read operations on Sensor 4. Default value: 000
Slave3_ numop1
Slave3_ numop0
DATAWRITE_SLV0 (21h)
Data to be written into the slave device register (r/w)
Slave0_ dataw7
Slave0_ dataw6
Table 297. DATAWRITE_SLV0 register
Slave0_ dataw5
Slave0_ dataw4
Slave0_ dataw3
Slave0_ dataw2
Slave0_ dataw1
Slave0_ dataw0
Slave0_dataw[7:0]
Table 298. DATAWRITE_SLV0 register description
Data to be written into the slave 0 device according to the rw_0 bit in register SLV0_ADD (15h)
.
Default value: 00000000
DS13005 - Rev 6 page 103/122
IIS2ICLX
STATUS_MASTER (22h)
17.33
STATUS_MASTER (22h)
Sensor hub source register (r)
WR_ONCE
_DONE
SLAVE3_
NACK
Table 299. STATUS_MASTER register
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK
0 0
SENS_HUB
_ENDOP
Table 300. STATUS_MASTER register description
WR_ONCE_DONE
SLAVE3_NACK
SLAVE2_NACK
SLAVE1_NACK
SLAVE0_NACK
When the bit WRITE_ONCE in
is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
SENS_HUB_ENDOP
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded;
1: sensor hub communication concluded)
DS13005 - Rev 6 page 104/122
18
IIS2ICLX
Soldering information
Soldering information
The LGA package is compliant with the ECOPACK , RoHS and "Green" standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
For the land pattern and soldering recommendations, please consult technical note TN0018 available on www.st.com
.
DS13005 - Rev 6 page 105/122
19
19.1
IIS2ICLX
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
LGA-16L package information
The IIS2ICLX is available in a high-performance (low-stress) ceramic cavity land grid array (CC LGA) package.
Due to the use of epoxy glue for lid sealing, hermeticity is not guaranteed. Processing or use of this package in a harsh environment should be assessed by the customer.
Figure 27. Ceramic cavity LGA-16: package outline and mechanical data
H
L
Note:
Note:
Pin 1 indicator
Top and bottom view: dimensions are expressed in mm.
Item
Length [L]
Width [W]
Height [H]
Pad size
Table 301. Outer dimensions
Dimension [mm]
5
5
1.7 typ
0.7 x 0.5
General tolerance is ±0.1 mm unless otherwise specified.
Tolerance [mm]
±0.15
±0.15
±0.15
±0.15
8535893_A
DS13005 - Rev 6 page 106/122
IIS2ICLX
Revision history
Date
27-May-2020
09-Jun-2020
18-Jun-2020
20-Aug-2020
18-Sep-2020
24-Aug-2021
3
4
5
6
Table 302. Document revision history
Version
1
2
Changes
Initial release
Updated title of datasheet
Updated CS pin in Table 16. Internal pin status and added procedure to initialize the device
Added DEVICE_CONF bit to CTRL9_XL
Updated description of X-axis tap recognition threshold in TAP_CFG1 (57h)
Updated description of Y-axis tap recognition threshold in TAP_CFG2 (58h)
Updated description of weight of 1 LSB of wakeup threshold in
WAKE_UP_DUR (5Ch)
Updated description of BDR_XL_[3:0] in FIFO_CTRL3 (09h)
Updated description of ODR_T_BATCH_[1:0] in FIFO_CTRL4 (0Ah)
Updated Table 48. CTRL6_C register description
Updated Table 38. Accelerometer ODR selection
Updated description of BDR_XL_[3:0] in FIFO_CTRL3 (09h), adding 1.6 Hz
Updated description of ODR_T_BATCH_[1:0] in FIFO_CTRL4 (0Ah), adding
1.6 Hz
Added
Updated sensitivity change over life in Table 2. Mechanical characteristics
Updated Note below
Updated bits 0 and 1 of registers FSM_OUTS1 (4Ch) through
DS13005 - Rev 6 page 107/122
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Contents
Contents
DS13005 - Rev 6 page 108/122
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Contents
DS13005 - Rev 6 page 109/122
IIS2ICLX
Contents
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 53
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) . . . . . . . . . . . . . . . . . . . . . 62
FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) . . . . . . . . . . . . . . . . . . . . . 62
DS13005 - Rev 6 page 110/122
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Contents
FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) . . . . . . . . . . . . . . . . . . . . . 62
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) . . . . . . . . . . . . . . . 76
DS13005 - Rev 6 page 111/122
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Contents
FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh). . . . . . . . . . . . . . . . . . . . 89
FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) . . . . . . . . . . . . . . . . . . . . . 90
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Contents
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Contents
DS13005 - Rev 6 page 114/122
IIS2ICLX
List of tables
List of tables
DS13005 - Rev 6 page 115/122
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List of tables
DS13005 - Rev 6 page 116/122
IIS2ICLX
List of tables
DS13005 - Rev 6 page 117/122
IIS2ICLX
List of tables
DS13005 - Rev 6 page 118/122
IIS2ICLX
List of tables
DS13005 - Rev 6 page 119/122
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List of tables
DS13005 - Rev 6 page 120/122
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List of figures
List of figures
DS13005 - Rev 6 page 121/122
IIS2ICLX
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DS13005 - Rev 6 page 122/122
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