STMicroelectronics LSM6DSO Datasheet
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LSM6DSO
Datasheet iNEMO inertial module: always-on 3D accelerometer and 3D gyroscope
LGA-14L
(2.5 x 3.0 x 0.83 mm) typ.
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LSM6DSO
Order code
Product summary
LSM6DSO LSM6DSOTR
Temperature range [°C]
-40 to +85
Package
Packing
LGA-14L
(2.5 x 3 x 0.83 mm)
Tray Tape & Reel
Product label
Features
• Power consumption: 0.55 mA in combo high-performance mode
• “Always-on" experience with low power consumption for both accelerometer and gyroscope
• Smart FIFO up to 9 kbyte
• Android compliant
• ±2/±4/±8/±16 g full scale
• ±125/±250/±500/±1000/±2000 dps full scale
• Analog supply voltage: 1.71 V to 3.6 V
• Independent IO supply (1.62 V)
• Compact footprint: 2.5 mm x 3 mm x 0.83 mm
• SPI / I²C & MIPI I3C SM serial interface with main processor data synchronization
• Auxiliary SPI for OIS data output for gyroscope and accelerometer
• Advanced pedometer, step detector and step counter
• Significant Motion Detection, Tilt detection
• Standard interrupts: free-fall, wakeup, 6D/4D orientation, click and double-click
• Programmable Finite State Machine: accelerometer, gyroscope and external sensors
• Embedded temperature sensor
• ECOPACK ® , RoHS and “Green” compliant
Applications
• Motion tracking and gesture detection
• Sensor hub
• Indoor navigation
• IoT and connected devices
• Smart power saving for handheld devices
• EIS and OIS for camera applications
• Vibration monitoring and compensation
Description
The LSM6DSO is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope boosting performance at 0.55 mA in high-performance mode and enabling always-on low-power features for an optimal motion experience for the consumer.
The LSM6DSO supports main OS requirements, offering real, virtual and batch sensors with 9 kbytes for dynamic data batching. ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
DS12140 - Rev 2 - January 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
LSM6DSO
The LSM6DSO has a full-scale acceleration range of ±2/±4/±8/±16 g and an angular rate range of ±125/±250/±500/±1000/±2000 dps.
The LSM6DSO fully supports EIS and OIS applications as the module includes a dedicated configurable signal processing path for OIS and auxiliary SPI, configurable for both the gyroscope and accelerometer.
High robustness to mechanical shock makes the LSM6DSO the preferred choice of system designers for the creation and manufacturing of reliable products.The
LSM6DSO is available in a plastic land grid array (LGA) package.
DS12140 - Rev 2 page 2/172
1
LSM6DSO
Overview
Overview
The LSM6DSO is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope.
The LSM6DSO delivers best-in-class motion sensing that can detect orientation and gestures in order to empower application developers and consumers with features and capabilities that are more sophisticated than simply orienting their devices to portrait and landscape mode.
The event-detection interrupts enable efficient and reliable motion tracking and contextual awareness, implementing hardware recognition of free-fall events, 6D orientation, click and double-click sensing, activity or inactivity, stationary/motion detection and wakeup events.
The LSM6DSO supports main OS requirements, offering real, virtual and batch mode sensors. In addition, the
LSM6DSO can efficiently run the sensor-related features specified in Android, saving power and enabling faster reaction time. In particular, the LSM6DSO has been designed to implement hardware features such as significant motion detection, stationary/motion detection, tilt, pedometer functions, timestamping and to support the data acquisition of an external magnetometer.
The LSM6DSO offers hardware flexibility to connect the pins with different mode connections to external sensors to expand functionalities such as adding a sensor hub, auxiliary SPI, etc.
Up to 9 kbytes of FIFO with compression and dynamic allocation of significant data (i.e. external sensors, timestamp, etc.) allows overall power saving of the system.
Like the entire portfolio of MEMS sensor modules, the LSM6DSO leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
The LSM6DSO is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm to address ultra-compact solutions.
DS12140 - Rev 2 page 3/172
2
2.1
2.2
2.3
LSM6DSO
Embedded low-power features
Embedded low-power features
The LSM6DSO has been designed to be fully compliant with Android, featuring the following on-chip functions:
• 9 kybtes data buffering, data can be compressed two or three times
– 100% efficiency with flexible configurations and partitioning
– Possibility to store timestamp
•
•
•
Event-detection interrupts (fully configurable)
– Free-fall
– Wakeup
– 6D orientation
– Click and double-click sensing
– Activity/Inactivity recognition
– Stationary/Motion detection
Specific IP blocks with negligible power consumption and high-performance
– Pedometer functions: step detector and step counters
– Tilt
– Significant Motion Detection
– Finite State Machine (FSM) for accelerometer, gyroscope, and external sensors
Sensor hub
– Up to 6 total sensors: 2 internal (accelerometer and gyroscope) and 4 external sensors
Tilt detection
The tilt function helps to detect activity change and has been implemented in hardware using only the accelerometer to achieve targets of both ultra-low power consumption and robustness during the short duration of dynamic accelerations.
The tilt function is based on a trigger of an event each time the device's tilt changes and can be used with different scenarios, for example:
1.
Triggers when phone is in a front pants pocket and the user goes from sitting to standing or standing to sitting;
2.
Doesn’t trigger when phone is in a front pants pocket and the user is walking, running or going upstairs.
Significant Motion Detection
The Significant Motion Detection (SMD) function generates an interrupt when a ‘significant motion’, that could be due to a change in user location, is detected. In the LSM6DSO device this function has been implemented in hardware using only the accelerometer.
SMD functionality can be used in location-based applications in order to receive a notification indicating when the user is changing location.
Finite State Machine
The LSM6DSO can be configured to generate interrupt signals activated by user-defined motion patterns. To do this, up to 16 embedded finite state machines can be programmed independently for motion detection such as glance gestures, absolute wrist tilt, shake and double-shake detection.
Definition of Finite State Machine
A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model composed of a finite number of states and transitions between states, similar to a flow chart in which one can inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to different states through transitions dependent on the inputs, and can finally end in a specific state (called stop
shows a generic state machine.
DS12140 - Rev 2 page 4/172
DS12140 - Rev 2
Figure 1. Generic state machine
LSM6DSO
Finite State Machine
Finite State Machine in the LSM6DSO
The LSM6DSO works as a combo accelerometer-gyroscope sensor, generating acceleration and angular rate output data. It is also possible to connect an external sensor (magnetometer) by using the Sensor Hub feature
(Mode 2). These data can be used as input of up to 16 programs in the embedded Finite State Machine
( Figure 2. State machine in the LSM6DSO ).
All 16 finite state machines are independent: each one has its dedicated memory area and it is independently executed. An interrupt is generated when the end state is reached or when some specific command is performed.
Figure 2. State machine in the LSM6DSO page 5/172
3
Pin description
Figure 3. Pin connections
LSM6DSO
Pin description
3.1
Pin connections
The LSM6DSO offers flexibility to connect the pins in order to have four different mode connections and functionalities. In detail:
•
•
Mode 1 : I²C / MIPI I3C SM slave interface or SPI (3- and 4-wire) serial interface is available;
Mode 2 : I²C / MIPI I3C SM slave interface or SPI (3- and 4-wire) serial interface and I²C interface master for external sensor connections are available;
•
•
Mode 3: I²C / MIPI I3C
SM slave interface or SPI (3- and 4-wire) serial interface is available for the application processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is available for the gyroscope ONLY;
Mode 4: I²C / MIPI I3C SM slave interface or SPI (3- and 4-wire) serial interface is available for the application processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is available for the accelerometer and gyroscope.
DS12140 - Rev 2 page 6/172
DS12140 - Rev 2
LSM6DSO
Pin connections
Mode 1
HOST
I 2 C /
MIPI I3C
SM
/
SPI (3/4-w)
LSM6DSO
Mode 2
HOST
I 2
MIPI I3C
C /
SM
/
SPI (3/4-w)
LSM6DSO
Master I 2 C
LSM6DSM sensors
Figure 4. LSM6DSO connection modes
Mode 3
HOST
I 2 C /
MIPI I3C
SM
/
SPI (3/4-w)
LSM6DSO
Mode 4
HOST
I 2
MIPI I3C
C /
SM
/
SPI (3/4-w)
LSM6DSO
Aux SPI (3/4-w) For gyro data only
Camera module
Aux SPI (3/4-w) For XL and gyro data
Camera module
In the following table each mode is described for the pin connections and function.
Pin# Name Mode 1 function
1 SDO/SA0
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
2
3
6
7
4 INT1
5 VDDIO
8
GND
GND
9
SDx
SCx
INT2
Connect to VDDIO or GND
Connect to VDDIO or GND
Programmable interrupt 2
(INT2) / Data enable (DEN)
10 OCS_Aux Leave unconnected
11 SDO_Aux
Connect to VDD_IO or leave unconnected
Table 1. Pin description
Mode 2 function
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
I²C serial data master (MSDA)
I²C serial clock master (MSCL)
Mode 3 / Mode 4 function
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
Auxiliary SPI 3/4-wire interface serial data input (SDI) and SPI 3-wire serial data output (SDO)
Auxiliary SPI 3/4-wire interface serial port clock (SPC_Aux)
Programmable interrupt in I²C and SPI
Power supply for I/O pins
0 V supply
0 V supply
Power supply
Programmable interrupt 2 (INT2)/
Data enable (DEN)/I²C master external synchronization signal
(MDRDY)
Programmable interrupt 2 (INT2)/
Data enable (DEN)
Connect to VDD_IO or leave
Auxiliary SPI 3/4-wire interface enable
Auxiliary SPI 3-wire interface: leave
Auxiliary SPI 4-wire interface: serial data output (SDO_Aux) page 7/172
LSM6DSO
Pin connections
Pin# Name Mode 1 function
12
13
CS
SCL
I²C/MIPI I3C SM /SPI mode selection
(1: SPI idle mode / I²C/MIPI
I3C SM communication enabled;
0: SPI communication mode /
I²C/MIPI I3C SM disabled)
I²C/MIPI I3C SM serial clock
(SCL)
SPI serial port clock (SPC)
14 SDA
I²C/MIPI I3C SM serial data
(SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
1. Recommended 100 nF filter capacitor.
2. Leave pin electrically unconnected and soldered to PCB.
Mode 2 function
I²C/MIPI I3C SM /SPI mode selection
(1: SPI idle mode / I²C/MIPI
I3C SM communication enabled;
0: SPI communication mode / I²C/
MIPI I3C SM disabled)
Mode 3 / Mode 4 function
I²C/MIPI I3C SM /SPI mode selection
(1: SPI idle mode / I²C/MIPI I3C SM communication enabled;
0: SPI communication mode / I²C/
MIPI I3C SM disabled)
I²C/MIPI I3C SM serial clock (SCL)
SPI serial port clock (SPC)
I²C/MIPI I3C SM serial clock (SCL)
SPI serial port clock (SPC)
I²C/MIPI I3C SM serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output
(SDO)
I²C/MIPI I3C SM serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
DS12140 - Rev 2 page 8/172
LSM6DSO
Module specifications
4
Module specifications
4.1
Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Symbol Parameter
LA_FS Linear acceleration measurement range
G_FS Angular rate measurement range
LA_So Linear acceleration sensitivity
G_So Angular rate sensitivity
G_So% Sensitivity tolerance
LA_SoDr
Linear acceleration sensitivity change vs. temperature (4)
G_SoDr
Angular rate sensitivity change vs. temperature (4)
LA_TyOff Linear acceleration zero-g level offset accuracy
G_TyOff Angular rate zero-rate level
LA_OffDr Linear acceleration zero-g level change vs. temperature (4)
G_OffDr Angular rate typical zero-rate level change vs. temperature
Rn
Rate noise density in high-performance mode (6)
RnRMS
Gyroscope RMS noise in normal/low-power mode (7)
An
Table 2. Mechanical characteristics
Acceleration noise density in high-performance mode
Test conditions
FS = ±2 g
FS = ±4 g
FS = ±8 g
FS = ±16 g
FS = ±125 dps
FS = ±250 dps
FS = ±500 dps
FS = ±1000 dps
FS = ±2000 dps at component level from -40° to +85° from -40° to +85°
FS = ±2
FS = ±4
FS = ±8 g g g
FS = ±16 g
Min.
Typ.
±2
±4
±8
±16
±125
±250
±500
±1000
±2000
0.061
0.122
0.244
0.488
4.375
8.75
17.50
35
70
±1
±0.01
±0.007
±20
±1
±0.1
±0.010
3.8
75
70
75
80
110
Max.
m mdps/LSB
µ
Unit g dps g g
/LSB
/√Hz
%
%/°C
%/°C m g dps m g / °C dps/°C mdps/√Hz mdps
DS12140 - Rev 2 page 9/172
LSM6DSO
Mechanical characteristics
Symbol
RMS
LA_ODR
G_ODR
Parameter
Acceleration RMS noise in normal/low-power mode (9)
Acceleration RMS noise in ultra-low-power mode
Linear acceleration output data rate
Angular rate output data rate
Test conditions
FS = ±2 g
FS = ±4 g
FS = ±8 g
FS = ±16 g
FS = ±2 g
Vst
Linear acceleration self-test output change
Angular rate self-test output change (15) (16)
FS = 250 dps
FS = 2000 dps
Top Operating temperature range
1. Typical specifications are not guaranteed.
2. Sensitivity values after factory calibration test and trimming.
3. Subject to change.
4. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured during final test for production.
5. Values after factory calibration test and trimming.
6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting.
7. Gyroscope RMS noise in normal/low-power mode is independent of the ODR and FS setting.
8. Accelerometer noise density in high-performance mode is independent of the ODR.
9. Accelerometer RMS noise in normal/low-power/ultra-low-power mode is independent of the ODR.
10. Noise RMS related to BW = ODR/2.
11. This ODR is available when the accelerometer is in low-power mode.
12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes.
50
20
150
-40
Min.
Typ.
1.8
2.0
2.4
3.0
5.5
12.5
26
52
104
208
416
833
1666
3332
6664
12.5
26
52
104
208
416
833
1666
3332
6664
Max.
1700
80
700
+85
Unit m g (RMS)
Hz m g dps dps
°C
DS12140 - Rev 2 page 10/172
13. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 mg at ±2 g full scale.
14. Accelerometer self-test limits are full-scale independent.
15. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes.
16. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale.
LSM6DSO
Mechanical characteristics
DS12140 - Rev 2 page 11/172
LSM6DSO
Electrical characteristics
4.2
Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Table 3. Electrical characteristics
Symbol
Vdd Supply voltage
Vdd_IO Power supply for I/O
Parameter
IddHP
Gyroscope and accelerometer current consumption in high-performance mode
LA_IddHP Accelerometer current consumption in high-performance mode
Test conditions
LA_IddLP Accelerometer current consumption in low-power mode
LA_IddULP Accelerometer current consumption in ultra-low-power mode
ODR = 52 Hz
ODR = 1.6 Hz
ODR = 52 Hz
ODR = 1.6 Hz
IddPD
Ton
Gyroscope and accelerometer current consumption during power-down
Turn-on time
V
IH
Digital high-level input voltage
Min.
1.71
1.62
0.7 *
VDD_IO
1.8
0.55
170
26
4.5
9.5
4.4
3
35
Max.
Unit
3.6
V
3.6
V mA
µA
µA
µA
0.3 *
VDD_IO
V
V
µA ms
V
V
IL
Digital low-level input voltage
V
OH
High-level output voltage I
OH
= 4 mA
VDD_IO -
0.2
V
OL
Top
Low-level output voltage
Operating temperature range
I
OL
1. Typical specifications are not guaranteed.
2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pin in order to guarantee the correct digital output voltage levels V
OH
and V
OL
.
-40
4.3
Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
0.2
+85
V
°C
Table 4. Temperature sensor characteristics
Symbol Parameter
Toff
TSen
Temperature refresh rate
Temperature offset
Temperature sensitivity
TST
Temperature stabilization time
T_ADC_res Temperature ADC resolution
Top Operating temperature range
Test condition Min.
-15
Typ.
52
256
16
Max.
+15
500
Unit
Hz
°C
LSB/°C
-40 +85
1. Typical specifications are not guaranteed.
2. When the accelerometer is in low-power mode or ultra-low-power mode and the gyroscope part is turned off, the TODR value is equal to the accelerometer ODR.
3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
4. Time from power ON to valid data based on characterization data.
µs bit
°C
DS12140 - Rev 2 page 12/172
LSM6DSO
Communication interface characteristics
4.4
4.4.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values (in mode 3)
Value
Symbol Parameter Unit
Min Max t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
5
20
5
15
5
10
50
50 ns
MHz ns
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production
Figure 5. SPI slave timing diagram (in mode 3)
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both input and output ports.
DS12140 - Rev 2 page 13/172
LSM6DSO
Communication interface characteristics
4.4.2
Note:
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 6. I²C slave timing values
Symbol f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST) t su(SR) t su(SP) t w(SP:SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
Parameter
SDA data hold time
START condition hold time
Repeated START condition setup time
STOP condition setup time
Bus free time between STOP and START condition
Min
1. Data based on standard I²C protocol requirement, not tested in production.
0
4.7
4.0
250
0
4
4.7
4
4.7
Max
100
3.45
Figure 6. I²C slave timing diagram
0
0.6
0.6
0.6
1.3
I²C fast mode
Min Max
0 400
1.3
0.6
100
0.9
Unit kHz
µs ns
µs
µs
SDA
START t su(SR) t w(SP:SR)
REPEATED
START
START t su(SDA) t h(SDA) t su(SP)
STOP
SCL t h(ST) t w(SCLL) t w(SCLH)
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both ports.
DS12140 - Rev 2 page 14/172
4.5
Note:
LSM6DSO
Absolute maximum ratings
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Vdd
T
STG
Sg
ESD
Vin
Table 7. Absolute maximum ratings
Ratings
Supply voltage
Storage temperature range
Acceleration g for 0.2 ms
Electrostatic discharge protection (HBM)
Input voltage on any control pin
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Maximum value
-0.3 to 4.8
-40 to +125
20,000
2
-0.3 to Vdd_IO +0.3
Unit
V
°C g kV
V
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS12140 - Rev 2 page 15/172
LSM6DSO
Terminology
4.6
4.6.1
4.6.2
Terminology
Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device.
Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large
number of sensors (see Table 2 ).
An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time (see
).
Zero-g and zero-rate level
Linear acceleration zerog level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g . Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zerog offset.
Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zerog level change vs. temperature” in
Table 2. Mechanical characteristics
. The zerog level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors.
Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise
MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress.
This value changes very little over temperature and time (see
Table 2. Mechanical characteristics
).
DS12140 - Rev 2 page 16/172
LSM6DSO
Digital interfaces
5
Digital interfaces
5.1
5.1.1
I²C/SPI interface
The registers embedded inside the LSM6DSO may be accessed through both the I²C and SPI serial interfaces.
The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied high (i.e connected to Vdd_IO).
Pin name
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
Table 8. Serial interface pin description
Pin description
SPI enable
I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
I²C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
I²C less significant bit of the device address
I²C serial interface
The LSM6DSO I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also be read back.
The relevant I²C terminology is provided in the table below.
Table 9. I²C terminology
Term
Transmitter The device which sends data to the bus
Receiver
Master
Slave
The device which receives data from the bus
Description
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.
The I²C interface is implemented with fast mode (400 kHz) I²C standards as well as with the standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h) .
DS12140 - Rev 2 page 17/172
LSM6DSO
I²C/SPI interface
Command
Read
Write
Read
Write
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to
LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The Slave ADdress (SAD) associated to the LSM6DSO is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is ‘1’
(address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b).
This solution permits to connect and address two different inertial modules to the same I²C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the LSM6DSO behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an
(IF_INC).
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.
Table 10 explains how the SAD+Read/Write bit pattern is composed, listing all the possible
configurations.
SAD[6:1]
110101
110101
110101
110101
Table 10. SAD+Read/Write patterns
SAD[0] = SA0
0
0
1
1
R/W
1
0
1
0
SAD+R/W
11010101 (D5h)
11010100 (D4h)
11010111 (D7h)
11010110 (D6h)
Master
Slave
Master
Slave
ST
ST
Table 11. Transfer when master is writing one byte to slave
SAD + W SUB DATA
SAK SAK
Table 12. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA
SAK SAK SAK
DATA
SAK
SAK
SP
SP
Master
Slave
ST
Table 13. Transfer when master is receiving (reading) one byte of data from slave
SAD + W SUB SR SAD + R
SAK SAK SAK DATA
NMAK SP
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
DS12140 - Rev 2 page 18/172
LSM6DSO
I²C/SPI interface
Slave SAK SAK SAK DATA DATA DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a
STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge.
DS12140 - Rev 2 page 19/172
LSM6DSO
I²C/SPI interface
5.1.2
SPI bus interface
The LSM6DSO SPI is a bus slave. The SPI allows writing and reading the registers of the device.
The serial interface communicates to the application using 4 wires: CS , SPC , SDI and SDO .
Figure 7. Read and write protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
(IF_INC) bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
SPI read
Figure 8. SPI read protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reads.
DS12140 - Rev 2 page 20/172
DS12140 - Rev 2
LSM6DSO
I²C/SPI interface
SPI write
Figure 9. Multiple byte SPI read protocol (2-byte example) (in mode 3)
CS
SPC
SDI
SDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8
Figure 10. SPI write protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1 -7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 11. Multiple byte SPI write protocol (2-byte example) (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
SPI read in 3-wire mode
A 3-wire mode is entered by setting the
CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial interface mode
selection).
page 21/172
Figure 12. SPI read protocol in 3-wire mode (in mode 3)
CS
SPC
SDI/O
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
LSM6DSO
I²C/SPI interface
DS12140 - Rev 2 page 22/172
LSM6DSO
MIPI I3CSM interface
5.2
5.2.1
Note:
5.2.2
MIPI I3C SM interface
MIPI I3C
SM
slave interface
•
•
•
•
•
•
•
The LSM6DSO interface includes a MIPI I3C SM SDR only slave interface (compliant with release 1.0 of the specification) with MIPI I3C SM SDR embedded features:
CCC command
Direct CCC communication (SET and GET)
Broadcast CCC communication
Private communications
Private read and write for single byte
Multiple read and write
In-Band Interrupt request
Error Detection and Recovery Methods (S0-S6)
Refer to
Section 5.3 I²C/I3C coexistence in LSM6DSO
for details concerning the choice of the interface when powering up the device.
MIPI I3C
SM
CCC supported commands
The list of MIPI I3C SM CCC commands supported by the device is detailed in the following table.
Command
ENTDAA
SETDASA
ENEC
DISEC
ENTAS0
ENTAS1
ENTAS2
ENTAS3
SETXTIME
Command code
0x07
0x87
0x80 / 0x00
0x81/ 0x01
0x82 / 0x02
0x83 / 0x03
0x84 / 0x04
0x85 / 0x05
0x98 / 0x28
GETXTIME
RSTDAA
SETMWL
SETMRL
SETNEWDA
GETMWL
0x99
0x86 / 0x06
0x89 / 0x08
0x8A / 0x09
0x88
0x8B
Default
Table 15. MIPI I3C SM CCC commands
Description
DAA procedure
Assign Dynamic Address using Static Address 0x6B/0x6A depending on SDO pin
Slave activity control (direct and broadcast)
Slave activity control (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Enter activity state (direct and broadcast)
Timing information exchange
0x07
0x00
0x05
0x92
Timing information exchange
Reset the assigned dynamic address (direct and broadcast)
Define maximum write length during private write (direct and broadcast)
Define maximum read length during private read (direct and broadcast)
Change dynamic address
0x00
0x08
(2 byte)
Get maximum write length during private write
DS12140 - Rev 2 page 23/172
Command
GETMRL
GETPID
GETBCR
GETDCR
GETSTATUS
GETMXDS
Command code
0x8C
0x8D
0x8E
0x8F
0x90
0x94
Default
0x00
0x10
0x09
(3 byte)
0x02
0x08
0x00
0x6C
0x10
0x0B
0x07
(1 byte)
Device ID register
Bus characteristics register
Description
Get maximum read length during private read
0x44 default MIPI I3C SM Device Characteristic Register
0x00
0x00
(2 byte)
Status register
0x00
0x20
(2 byte)
Return max data speed
LSM6DSO
MIPI I3CSM interface
DS12140 - Rev 2 page 24/172
5.3
LSM6DSO
I²C/I3C coexistence in LSM6DSO
I²C/I3C coexistence in LSM6DSO
In the LSM6DSO, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike filters on the SDA and SCL pins that are not compatible with I3C timing.
The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1 pin when the device is powered up:
• INT1 pin floating (internal pull-down): I²C/I3C both active, see
• INT1 pin connected to VDD_IO: only I3C active, see
Figure 13. I²C and I3C both active (INT1 pin not connected)
1.
Address assignment (DAA or ENTDA) must be performed with I²C Fast Mode Plus Timing. When the slave is addressed, the I²C slave is disabled and the timing is compatible with I3C specifications.
Figure 14. Only I3C active (INT1 pin connected to VDD_IO)
DS12140 - Rev 2
1.
When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using I3C SDR timing.
page 25/172
5.4
5.5
LSM6DSO
Master I²C interface
Master I²C interface
If the LSM6DSO is configured in Mode 2, a master I²C line is available. The master serial interface is mapped in the following dedicated pins.
Pin name
MSCL
MSDA
MDRDY
Table 16. Master I²C pin details
I²C serial clock master
I²C serial data master
I²C master external synchronization signal
Pin description
Auxiliary SPI interface
If the LSM6DSO is configured in Mode 3 or Mode 4, the auxiliary SPI is available. The auxiliary SPI interface is mapped to the following dedicated pins.
Table 17. Auxiliary SPI pin details
Pin name
OCS_Aux Auxiliary SPI 3/4-wire enable
SDx
SCx
Pin description
Auxiliary SPI 3/4-wire data input (SDI_Aux) and SPI 3-wire data output (SDO_Aux)
Auxiliary SPI 3/4-wire interface serial port clock
SDO_Aux Auxiliary SPI 4-wire data output (SDO_Aux)
When the LSM6DSO is configured in Mode 3 or Mode 4, the auxiliary SPI can be connected to a camera module for OIS/EIS support. In this configuration, the auxiliary SPI can write only to the dedicated registers
,
,
CTRL3_OIS (72h) . All the registers are accessible in Read mode
from both the primary interface and auxiliary SPI.
Mode 3 is enabled when the OIS_EN_SPI2 bit in
CTRL1_OIS (70h) register is set to 1.
Mode 4 is enabled when both the OIS_EN_SPI2 bit and the Mode4_EN bit in
CTRL1_OIS (70h) register are set
to 1.
DS12140 - Rev 2 page 26/172
LSM6DSO
Functionality
6
Functionality
6.1
6.2
6.2.1
6.3
Operating modes
•
•
In the LSM6DSO, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes.
The LSM6DSO has three operating modes available:
• only accelerometer active and gyroscope in power-down only gyroscope active and accelerometer in power-down both accelerometer and gyroscope sensors active with independent ODR
The accelerometer is activated from power-down by writing ODR_XL[3:0] in
CTRL1_XL (10h) while the gyroscope
is activated from power-down by writing ODR_G[3:0] in CTRL2_G (11h)
. For combo mode the ODRs are totally independent.
Accelerometer power modes
In the LSM6DSO, the accelerometer can be configured in five different operating modes: power-down, ultra-lowpower, low-power, normal mode and high-performance mode. The operating mode selected depends on the value
ODRs (from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to '1'. Low-power mode is available for lower ODRs (1.6, 12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and
208 Hz.
Accelerometer ultra-low-power mode
The LSM6DSO can be configured in ultra-low-power (ULP) mode by setting the XL_ULP_EN bit to 1 in
register. This mode can be used in accelerometer-only mode (gyroscope sensor must be configured in power-down mode) and for ODR_XL values between 1.6 Hz and 208 Hz.
When ULP mode is intended to be used, the bit XL_HM_MODE must be set to 0.
When ULP mode is switched ON/OFF, the accelerometer must be configured in power-down condition.
ULP mode cannot be used in Mode 3 or Mode 4 connection modes.
The embedded functions based on accelerometer data (free-fall, 6D/4D, tap, double tap, wake-up, activity/ inactivity, stationary/motion, step counter, step detection, significant motion, tilt) and the FIFO batching functionality are still supported when ULP mode is enabled.
Gyroscope power modes
In the LSM6DSO, the gyroscope can be configured in four different operating modes: power-down, low-power, normal mode and high-performance mode. The operating mode selected depends on the value of the
G_HM_MODE bit in
CTRL7_G (16h) . If G_HM_MODE is set to '0', high-performance mode is valid for all ODRs
(from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the G_HM_MODE bit has to be set to '1'. Low-power mode is available for lower ODRs (12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.
DS12140 - Rev 2 page 27/172
LSM6DSO
Block diagram of filters
6.4
6.4.1
Block diagram of filters
Figure 15. Block diagram of filters
M
E
M
S
N
S
S
E
O
R
Gyro UI/OIS front-end
XL UI/OIS front-end
Temperature sensor
ADC1
ADC2
Voltage and current references
Trimming circuit and Test interface
Low Pass
UI Gyro
Low Pass
UI XL
Low Pass
OIS Gyro
Low Pass
OIS XL
Clock and phase generator
Regs array,
FIFO
Regs array
I 2 C/ MIPI I3C
/SPI interface
SM
Interrupt mng
Interrupt mng
Auxiliary
SPI
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
INT1
INT2
CS
SPC_Aux
SDI_Aux
SDO_Aux
Power management
FTP
Block diagrams of the accelerometer filters
•
•
In the LSM6DSO, the filtering chain for the accelerometer part is composed of the following:
• Analog filter (anti-aliasing)
Digital filter (LPF1)
Composite filter
Details of the block diagram appear in the following figure.
Figure 16. Accelerometer UI chain
Analog
Anti-aliasing
LP Filter
Digital
LP Filter
LPF1
ADC
Composite
Filter
ODR_XL[3:0]
DS12140 - Rev 2 page 28/172
LSM6DSO
Block diagram of filters
Note:
LPF1 output
(1)
Figure 17. Accelerometer composite filter
Free-fall
LOW_PASS_ON_6D
Advanced functions
Digital
LP Filter
LPF2
LPF2_XL_EN
0
USER
OFFSET
0
1
6D / 4D
USR_OFF_ON_OUT
0
HP_SLOPE_XL_EN
0
1
1 USR_OFF_W
OFS_USR[7:0]
HPCF_XL[2:0]
Digital
HP Filter
1
0
1
0
USR_OFF_ON_WU SLOPE_FDS
Wake-up
Activity /
Inactivity
001
010
…
111
HPCF_XL[2:0]
1
FIFO
SPI /
I 2 C /
MIPI I3C
SM
SLOPE
FILTER
000
HPCF_XL[2:0]
S/D Tap
1.
The cutoff value of the LPF1 output is ODR/2 when the accelerometer is in high-performance mode. This value is equal to 700 Hz when the accelerometer is in low-power or normal mode.
Advanced functions include pedometer, step detector and step counter, significant motion detection, and tilt functions.
The accelerometer filtering chain when Mode 4 is enabled is illustrated in the following figure.
Figure 18. Accelerometer chain with Mode 4 enabled
Analog
Anti-aliasing
LP Filter
Digital
LP Filter
LPF_OIS
ODR XL
@6.6 kHz
ADC SPI_Aux
FILTER_XL_CONF_OIS[2:0]
UI chain
DS12140 - Rev 2 page 29/172
LSM6DSO
Block diagram of filters
Note:
6.4.2
Note:
Mode 4 is enabled when Mode4_EN = 1 and OIS_EN_SPI2 = 1 in
.
The configuration of the accelerometer UI chain is not affected by enabling Mode 4.
Accelerometer output values are in registers
OUTX_L_A (28h) and OUTX_H_A (29h) through not found and ODR
at 6.66 kHz.
Accelerometer full-scale management between the UI chain and OIS chain depends on the setting of the
XL_FS_MODE bit in register
Block diagrams of the gyroscope filters
In the LSM6DSO, the gyroscope filtering chain depends on the mode configuration:
• Mode 1 (for User Interface (UI) and Electronic Image Stabilization (EIS) functionality through primary interface) and Mode 2
Figure 19. Gyroscope digital chain - Mode 1 (UI/EIS) and Mode 2
ADC
SPI/
I
2
C/
MIPI I3C
SM
HPF
0
1
HP_EN_G
LPF1
FTYPE [2:0]
0
LPF2
1
LPF1_SEL_G
ODR_G[3:0]
FIFO
In this configuration, the gyroscope ODR is selectable from 12.5 Hz up to 6.66 kHz. A low-pass filter (LPF1) is available if the auxiliary SPI is disabled, for more details about the filter characteristics see
.
The digital LPF2 filter cannot be configured by the user and its cutoff frequency depends on the selected gyroscope ODR, as indicated in the following table.
Table 18. Gyroscope LPF2 bandwidth selection
Gyroscope ODR [Hz]
12.5
26
52
104
208
417
833
1667
3333
6667
LPF2 cutoff [Hz]
4.2
8.3
16.6
33.0
66.8
135.9
295.5
1108.1
1320.7
1441.8
Data can be acquired from the output registers and FIFO over the primary I²C/I³C/SPI interface.
DS12140 - Rev 2 page 30/172
DS12140 - Rev 2
• Mode 3 / Mode 4 (for OIS and EIS functionality)
Figure 20. Gyroscope digital chain - Mode 3 / Mode 4 (OIS/EIS)
LSM6DSO
Block diagram of filters
ADC
Digital
HP Filter
HP_EN_G
(3)
0
1
Digital
LP Filter
LPF2
FIFO
ODR_G[3:0]
SPI / I 2 C /
MIPI I3C SM
HP_EN_OIS
(3)
1
0
Digital (1) (2)
LP Filter
LPF1
FTYPE[1:0]_OIS
SPI_Aux
ODR Gyro
@6.6 kHz
1.
When Mode3/4 is enabled, the LPF1 filter is not available in the gyroscope UI chain.
2.
It is recommended to avoid using the LPF1 filter in Mode1/2 when Mode3/4 is intended to be used.
3.
HP_EN_OIS can be used to select the HPF on the OIS path only if the HPF is not used in the UI chain. If both the HP_EN_G bit and HP_EN_OIS bit are set to 1, the HP filter is applied to the UI chain only.
•
•
The auxiliary interface needs to be enabled in
In Mode 3/4 configuration, there are two paths: the chain for User Interface (UI) where the ODR is selectable from 12.5 Hz up to 6.66 kHz the chain for OIS/EIS where the ODR is at 6.66 kHz and the LPF1 is available. The LPF1 configuration
filter characteristics see
Table 151. Gyroscope OIS chain digital LPF1 filter bandwidth selection
. Gyroscope output values are in registers 22h to 27h with the selected full scale (FS[1:0]_G_OIS bit in
).
page 31/172
LSM6DSO
FIFO
6.5
6.5.1
FIFO
•
•
•
•
•
•
The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out from the FIFO.
The LSM6DSO embeds 3 kbytes of data in FIFO (up to 9 kbytes with the compression feature enabled) to store the following data:
Gyroscope
Accelerometer
External sensors (up to 4)
Step counter
Timestamp
Temperature
•
•
Writing data in the FIFO can be configured to be triggered by the:
• Accelerometer / gyroscope data-ready signal
Sensor hub data-ready signal
Step detection signal
•
•
•
•
The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFOdedicated configurations: accelerometer, gyroscope and temperature sensor batching rates can be selected by the user. External sensor writing in FIFO can be triggered by the accelerometer data-ready signal or by an external sensor interrupt. The step counter can be stored in FIFO with associated timestamp each time a step is detected. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32.
The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows recognizing the meaning of a word in FIFO.
FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the
ODR or BDR (Batching Data Rate) configuration is performed, the application can correctly reconstruct the timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores information of the new configuration and timestamp in which the change was applied in the device.
Finally, FIFO embeds a compression algorithm that the user can enable in order to have up to 9 kbytes of data stored in FIFO and take advantage of interface communication length for FIFO flushing and communication power consumption.
The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)
using the
WTM[8:0] bits. To monitor the FIFO status, dedicated registers ( FIFO_STATUS1 (3Ah) ,
) can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of these status events, the configuration can be set in
The FIFO buffer can be configured according to six different modes:
• Bypass mode
• FIFO mode
Continuous mode
Continuous-to-FIFO mode
Bypass-to-continuous mode
Bypass-to-FIFO mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the
Bypass mode
In Bypass mode (
FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains
empty. Bypass mode is also used to reset the FIFO when in FIFO mode.
DS12140 - Rev 2 page 32/172
LSM6DSO
FIFO
6.5.2
6.5.3
6.5.4
6.5.5
FIFO mode
In FIFO mode ( FIFO_CTRL4 (0Ah)
(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the
FIFO until it is full.
To reset FIFO content, Bypass mode should be selected by writing
(FIFO_MODE_[2:0]) to
'000'. After this reset command, it is possible to restart FIFO mode by writing
(FIFO_MODE_[2:0]) to '001'.
The FIFO buffer memorizes up to 9 kBytes of data (with compression enabled) but the depth of the FIFO can be
is set to '1', FIFO depth is limited up to the WTM [8:0] bits in
and
.
Continuous mode
Continuous mode (
FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new
data arrives, the older data is discarded.
A FIFO threshold flag
FIFO_STATUS2 (3Bh) (FIFO_WTM_IA) is asserted when the number of unread samples in
FIFO is greater than or equal to
FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)
(WTM [8:0]).
It is possible to route the FIFO_WTM_IA flag to
to the INT1 pin by writing in register
(INT1_FIFO_TH) = '1' or to the INT2 pin by writing in register
(INT2_FIFO_TH) = '1'.
A full-flag interrupt can be enabled,
(INT1_FIFO_FULL) = '1' or INT2_CTRL (0Eh)
(INT2_FIFO_FULL) = '1', in order to indicate FIFO saturation and eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag
in FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples
available in FIFO_STATUS1 (3Ah)
and FIFO_STATUS2 (3Bh) (DIFF_FIFO_[9:0]).
•
•
•
•
•
Continuous-to-FIFO mode
In Continuous-to-FIFO mode (
FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 011), FIFO behavior changes according
to the trigger event detected in one of the following interrupt events:
Single tap
Double tap
Wake-up
Free-fall
D6D
When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.
When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
•
•
•
•
•
Bypass-to-Continuous mode
In Bypass-to-Continuous mode ( FIFO_CTRL4 (0Ah)
(FIFO_MODE_[2:0] = '100'), data measurement storage inside FIFO operates in Continuous mode when selected triggers are equal to '1', otherwise FIFO content is reset
(Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
Single tap
Double tap
Wake-up
Free-fall
D6D
DS12140 - Rev 2 page 33/172
LSM6DSO
FIFO
6.5.6
6.5.7
•
•
•
•
•
Bypass-to-FIFO mode
In Bypass-to-FIFO mode (
FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = '111'), data measurement storage inside FIFO
operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
Single tap
Double tap
Wake-up
Free-fall
D6D
FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes:
one tag byte ( FIFO_DATA_OUT_TAG (78h)
, in order to identify the sensor, and 6 bytes of fixed data
(FIFO_DATA_OUT registers from (79h) to (7Eh)).
The DIFF_FIFO_[9:0] field in the
registers contains the number of words (1 byte TAG + 6 bytes DATA) collected in FIFO.
In addition, it is possible to configure a counter of the batch events of accelerometer or gyroscope sensors. The
flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh)
alerts that the counter reaches a selectable threshold
(CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh)
and COUNTER_BDR_REG2 (0Ch) ). This allows
triggering the reading of FIFO with the desired latency of one single sensor. The sensor is selectable using the
TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh)
. As for the other FIFO status events, the flag
COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by asserting the corresponding bits
(INT1_CNT_BDR of
and INT2_CNT_BDR of INT2_CTRL (0Eh)
).
In order to maximize the amount of accelerometer and gyroscope data in FIFO, the user can enable the compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in
functions registers bank) and the FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h) . When compression is
enabled, it is also possible to force writing non-compressed data at a selectable rate using the
UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h) .
Meta information about accelerometer and gyroscope sensor configuration changes can be managed by enabling
the ODR_CHG_EN bit in FIFO_CTRL2 (08h)
.
DS12140 - Rev 2 page 34/172
LSM6DSO
Application hints
7
Application hints
7.1
LSM6DSO electrical connections in Mode 1
Figure 21. LSM6DSO electrical connections in Mode 1
GND or VDDIO
SDO/SA0
SDx
SCx
INT1
1
4
14 12
5
TOP
VIEW
7
11
8
NC
(1)
NC
(1)
INT2
VDD
C1
Vdd
GND
100 nF
C2
GND
100 nF
Vdd_IO
Mode 1
HOST
I 2 C /
MIPI I3C
SM
/
SPI (3/4-w)
LSM6DSO
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
1.
Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C/MIPI I3C SM interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C/MIPI I3C SM interface.
DS12140 - Rev 2 page 35/172
7.2
LSM6DSO
LSM6DSO electrical connections in Mode 2
LSM6DSO electrical connections in Mode 2
Figure 22. LSM6DSO electrical connections in Mode 2
SDO/SA0
MSDA
MSCL
INT1
1
4
14 12
5
TOP
VIEW
7
11
8
NC
(1)
NC
(1)
Vdd
MDRDY/INT2
VDD
C1
GND
100 nF
C2
GND
100 nF
Vdd_IO
Mode 2
HOST
I 2 C /
MIPI I3C
SM
/
SPI (3/4-w)
LSM6DSO
Master I 2 C
LSM6DSM sensors
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
1.
Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C/MIPI I3C SM primary interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C/MIPI I3C SM primary interface.
DS12140 - Rev 2 page 36/172
7.3
Note:
LSM6DSO
LSM6DSO electrical connections in Mode 3 and Mode 4
LSM6DSO electrical connections in Mode 3 and Mode 4
Figure 23. LSM6DSO electrical connections in Mode 3 and Mode 4 (auxiliary 3/4-wire SPI)
SDO
SDI_Aux
SPC_Aux
INT1
C2
100 nF
GND
1
4
14 12
5
TOP
VIEW
7
11
8
NC
(1)
OCS_Aux
INT2
VDD
Vdd
C1
100 nF
GND
Vdd_IO
Mode 3
HOST
I 2
MIPI I3C
C
SM
/
/
SPI (3/4-w)
LSM6DSO
Mode 4
HOST
I 2
MIPI I3C
C
SM
/
/
SPI (3/4-w)
LSM6DSO
Aux SPI (3-w) For gyro data only
Camera module
Aux SPI (3-w) For XL and gyro data
Camera module
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
1.
Leave pin electrically unconnected and soldered to PCB.
system is off).
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device is selectable and accessible through the SPI/I²C/MIPI I3C SM primary interface.
Measured acceleration/angular rate data is selectable and accessible through the SPI/I²C/MIPI I3C SM primary interface and auxiliary SPI.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C/MIPI I3C SM interface.
DS12140 - Rev 2 page 37/172
7
8
5
6 pin#
1
2
3
4
9
10
11
12
Name
SDO
SA0
SDx
SCx
INT1
VDDIO
GND
GND
VDD
INT2
OCS_Aux
Table 19. Internal pin status
Pin status Mode 1 Mode 1 function
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
MIPI I3C SM least significant bit of the static address
(SA0)
Mode 2 function Mode 3 / Mode 4 function
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
MIPI I3C SM least significant bit of the static address
(SA0)
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
MIPI I3C SM least significant bit of the static address
(SA0)
Default: input without pull-up
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Connect to VDDIO or GND
Connect to VDDIO or GND
I²C serial data master
(MSDA)
I²C serial clock master
(MSCL)
Auxiliary SPI 3/4-wire interface serial data input
(SDI) and SPI 3-wire serial data output (SDO)
Auxiliary SPI 3/4-wire interface serial port clock
(SPC_Aux)
Default: input without pull-up
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up).
Default: input without pull-up
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up).
Programmable interrupt 1 /
If device is used as MIPI
I3C SM pure slave, this pin must be set to ‘1’.
Power supply for I/O pins
0 V supply
0 V supply
Power supply
Programmable interrupt 2
(INT2) / Data enabled
(DEN)
Programmable interrupt 1 /
If device is used as MIPI
I3C SM pure slave, this pin must be set to ‘1’.
Power supply for I/O pins
0 V supply
0 V supply
Power supply
Programmable interrupt 2
(INT2) / Data enabled
(DEN) / I²C master external synchronization signal
(MDRDY)
Programmable interrupt 1 /
If device is used as MIPI
I3C SM pure slave, this pin must be set to ‘1’.
Power supply for I/O pins
0 V supply
0 V supply
Power supply
Programmable interrupt 2
(INT2) / Data enabled
(DEN)
Default: input with pull-down (2)
Default: output forced to ground
Leave unconnected Leave unconnected
Auxiliary SPI 3/4-wire interface enabled
Default: input with pull-up
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
SDO_Aux
CS
Connect to VDDIO or leave unconnected
I²C/SPI mode selection
(1:SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
Connect to VDDIO or leave unconnected
I²C/SPI mode selection
(1:SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
Auxiliary SPI 3-wire interface: leave unconnected / Auxiliary SPI
4-wire interface: serial data output (SDO_Aux)
I²C/SPI mode selection
(1:SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
Default: input with pull-up
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Default: input with pull-up
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
I3C_disable = 1 in reg 18h.
Pin status Mode 2
Default: input without pull-up
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Default: output forced to ground
Pin status Mode 3/4
Default: input without pull-up
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Default: input without pull-up
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up).
Default: input without pull-up
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up).
Default: input with pull-down
Default: input without pull-up
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up).
Default: input without pull-up
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up)
Default: input with pull-down
Default: output forced to ground
Default: input with pull-up
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Default: input with pull-up
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Default: input with pull-up
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
I3C_disable = 1 in reg 18h.
Default: input without pull-up
(regardless of the value of bit
OIS_PU_DIS in reg 02h.)
Default: input with pull-up
Pull-up is enabled if bit SIM_OIS = 1
(Aux_SPI 3-wire) in reg 70h and bit
OIS_PU_DIS = 0 in reg 02h.
Default: input with pull-up
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
I3C_disable = 1 in reg 18h.
pin#
13
14
Name
SCL
SDA
Mode 1 function Mode 2 function Mode 3 / Mode 4 function
I²C/MIPI I3C SM serial clock
(SCL) / SPI serial port clock
(SPC)
I²C/MIPI I3C SM serial clock
(SCL) / SPI serial port clock
(SPC)
I²C/MIPI I3C SM serial data
(SDA) / SPI serial data input (SDI) / 3-wire interface serial data output
(SDO)
I²C/MIPI I3C SM serial data
(SDA) / SPI serial data input (SDI) / 3-wire interface serial data output
(SDO)
I²C/MIPI I3C SM serial clock
(SCL) / SPI serial port clock
(SPC)
I²C/MIPI I3C SM serial data
(SDA) / SPI serial data input (SDI) / 3-wire interface serial data output
(SDO)
Pin status Mode 1
Default: input without pull-up
Default: input without pull-up
Pin status Mode 2
Default: input without pull-up
Default: input without pull-up
1. Mode 3 is enabled when the OIS_EN_SPI2 bit in the
CTRL1_OIS (70h) register is set to 1. Mode 4 is enabled when both the OIS_EN_SPI2 bit and
the Mode4_EN bit in the
CTRL1_OIS (70h) register are set to 1.
2. INT1 must be set to '0' or left unconnected during power-on if the I²C/SPI interfaces are used.
Note:
Internal pull-up value is from 30 kΩ to 50 kΩ, depending on VDDIO.
The procedure to enable the pull-up on pins 2 and 3 is as follows:
1. From the primary I²C/I³C/SPI interface: write 40h in register at address 01h (enable access to the sensor hub registers)
2. From the primary I²C/I³C/SPI interface: write 08h in register at address 14h (enable the pull-up on pins 2 and 3)
3. From the primary I²C/I³C/SPI interface: write 00h in register at address 01h (disable access to the sensor hub registers)
Pin status Mode 3/4
Default: input without pull-up
Default: input without pull-up
LSM6DSO
Register mapping
8
Register mapping
Name
FUNC_CFG_ACCESS
PIN_CTRL
RESERVED
FIFO_CTRL1
FIFO_CTRL2
FIFO_CTRL3
FIFO_CTRL4
COUNTER_BDR_REG1
COUNTER_BDR_REG2
INT1_CTRL
INT2_CTRL
WHO_AM_I
CTRL1_XL
CTRL2_G
CTRL3_C
CTRL4_C
CTRL5_C
CTRL6_C
CTRL7_G
CTRL8_XL
CTRL9_XL
CTRL10_C
ALL_INT_SRC
WAKE_UP_SRC
TAP_SRC
D6D_SRC
STATUS_REG
RESERVED
OUT_TEMP_L
OUT_TEMP_H
OUTX_L_G
OUTX_H_G
OUTY_L_G
The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses.
Table 20. Registers address map
Type
01
02
1A
1B
1C
1D
17
18
19
1E
1F
20
21
22
23
24
12
13
14
15
16
0D
0E
0F
10
11
08
09
0A
0B
0C
Register address
Hex Binary
00000001
00000010
03-06
07
00010010
00010011
00010100
00010101
00010110
0001 0111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
00100011
00100100
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
-
RW
R
R
R
R
RW
RW
RW
R
R
R
R
-
R
R
Default
00000000
00111111
00000100
00000000
00000000
00000000
00000000
00000000
11100000
00000000 output output output output output
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
01101100
00000000
00000000 output output output output output
Comment
R (SPI2)
R (SPI2)
R (SPI2)
R (SPI2)
R (SPI2)
R (SPI2)
R (SPI2)
R (SPI2)
R (SPI2)
R (SPI2)
R (SPI2)
DS12140 - Rev 2 page 40/172
Name
OUTY_H_G
OUTZ_L_G
OUTZ_H_G
OUTX_L_A
OUTX_H_A
OUTY_L_A
OUTY_H_A
OUTZ_L_A
OUTZ_H_A
RESERVED
EMB_FUNC_STATUS_MAINPAGE
FSM_STATUS_A_MAINPAGE
FSM_STATUS_B_MAINPAGE
RESERVED
STATUS_MASTER_MAINPAGE
FIFO_STATUS1
FIFO_STATUS2
RESERVED
TIMESTAMP0
TIMESTAMP1
TIMESTAMP2
TIMESTAMP3
RESERVED
TAP_CFG0
TAP_CFG1
TAP_CFG2
TAP_THS_6D
INT_DUR2
WAKE_UP_THS
WAKE_UP_DUR
FREE_FALL
MD1_CFG
MD2_CFG
RESERVED
I3C_BUS_AVB
INTERNAL_FREQ_FINE
RESERVED
INT_OIS
CTRL1_OIS
DS12140 - Rev 2
LSM6DSO
Register mapping
Type
RW
RW
RW
-
RW
R
-
R
R
RW
RW
RW
RW
RW
R
R
-
R
R
RW
RW
R
R
R
R
R
R
R
R
R
R
R
R
-
R
-
-
R
R
5D
5E
5F
60-61
62
63
64-6E
6F
70
58
59
5A
5B
5C
40
41
42
43
44-55
56
57
29
2A
2B
2C
2D
25
26
27
28
2E-34
35
36
37
38
39
3A
3B
3C-3F
Register address
Hex Binary
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00110101
00110110
00110111
00111001
00111010
00111011
01000000
01000001
01000010
01000011
01100010
01100011
01101111
01110000
01010110
01010111
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111
Default output output output output output output output output output output output output
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000 output
00000000
00000000 output output output output output output output
Comment
R (SPI2)
R (SPI2)
R (SPI2)
R (SPI2)
RW (SPI2)
RW (SPI2) page 41/172
LSM6DSO
Register mapping
Name Type
CTRL2_OIS
CTRL3_OIS
X_OFS_USR
Y_OFS_USR
Z_OFS_USR
RESERVED
FIFO_DATA_OUT_TAG
FIFO_DATA_OUT_X_L
FIFO_DATA_OUT_X_H
FIFO_DATA_OUT_Y_L
FIFO_DATA_OUT_Y_H
FIFO_DATA_OUT_Z_L
FIFO_DATA_OUT_X_H
1. This register status is read using the primary interface for user interface data.
2. This register status is read using the auxiliary SPI for OIS data.
RW
-
R
R
R
R
R
R
R
R
R
RW
RW
75
76-77
78
79
7A
7B
7C
7D
7E
71
72
73
74
Register address
Hex Binary
01110001
01110010
01110011
01110100
01110101
01111000
01111001
01111010
01111011
01111100
01111101
01111110
Default
00000000
00000000
00000000
00000000
00000000 output output output output output output output
Comment
RW (SPI2)
RW (SPI2)
DS12140 - Rev 2 page 42/172
9
9.1
9.2
LSM6DSO
Register description
Register description
The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface.
FUNC_CFG_ACCESS (01h)
Enable embedded functions register (r/w)
Table 21. FUNC_CFG_ACCESS register
FUNC_CFG_
ACCESS
SHUB_REG
ACCESS
0
0
1. This bit must be set to '0' for the correct operation of the device.
0
0
0
0
Table 22. FUNC_CFG_ACCESS register description
FUNC_CFG_ACCESS
SHUB_REG_ACCESS
Enable access to the embedded functions configuration registers.
Default value: 0
Enable access to the sensor hub (I²C master) registers.
Default value: 0
1. Details concerning the embedded functions configuration registers are available in
Section 10 Embedded functions register mapping
and
Section 11 Embedded functions register description
.
and Section 15 Sensor hub register description .
PIN_CTRL (02h)
SDO, OCS_AUX, SDO_AUX pins pull-up enable/disable register (r/w)
OIS_
PU_DIS
SDO_
PU_EN
1
Table 23. PIN_CTRL register
1 1 1 1 1
OIS_PU_DIS
SDO_PU_EN
Table 24. PIN_CTRL register description
Disable pull-up on both OCS_Aux and SDO_Aux pins. Default value: 0
(0: OCS_Aux and SDO_Aux pins with pull-up;
1: OCS_Aux and SDO_Aux pins pull-up disconnected)
Enable pull-up on SDO pin
(0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up)
DS12140 - Rev 2 page 43/172
9.3
9.4
LSM6DSO
FIFO_CTRL1 (07h)
FIFO_CTRL1 (07h)
FIFO control register 1 (r/w)
WTM7 WTM6 WTM5
Table 25. FIFO_CTRL1 register
WTM4 WTM3 WTM2 WTM1 WTM0
Table 26. FIFO_CTRL1 register description
WTM[7:0]
FIFO watermark threshold, in conjunction with WTM8 in
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.
FIFO_CTRL2 (08h)
FIFO control register 2 (r/w)
STOP_ON
_WTM
FIFO_
COMPR_
RT_EN
0
Table 27. FIFO_CTRL2 register
ODRCHG
_EN
0
UNCOPTR_
RATE_1
UNCOPTR_
RATE_0
WTM8
Table 28. FIFO_CTRL2 register description
STOP_ON_WTM
FIFO_COMPR_RT_EN
Enables/Disables compression algorithm runtime
ODRCHG_EN
Sensing chain FIFO stop values memorization at threshold level
(0: FIFO depth is not limited (default);
1: FIFO depth is limited to threshold level, defined in
and
)
UNCOPTR_RATE_[1:0]
Enables ODR CHANGE virtual sensor to be batched in FIFO
This field configures the compression algorithm to write non-compressed data at each rate.
(0: Non-compressed data writing is not forced;
1: Non-compressed data every 8 batch data rate;
2: Non-compressed data every 16 batch data rate;
3: Non-compressed data every 32 batch data rate)
WTM8
FIFO watermark threshold, in conjunction with WTM_FIFO[7:0] in FIFO_CTRL1 (07h)
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.
1. This bit is effective if the FIFO_COMPR_EN bit of EMB_FUNC_EN_B (05h) is set to 1.
DS12140 - Rev 2 page 44/172
9.5
LSM6DSO
FIFO_CTRL3 (09h)
FIFO_CTRL3 (09h)
FIFO control register 3 (r/w)
BDR_GY_3 BDR_GY_2
Table 29. FIFO_CTRL3 register
BDR_GY_1 BDR_GY_0 BDR_XL_3 BDR_XL_2 BDR_XL_1 BDR_XL_0
BDR_GY_[3:0]
BDR_XL_[3:0]
Table 30. FIFO_CTRL3 register description
Selects Batching Data Rate (writing frequency in FIFO) for gyroscope data.
(0000: Gyro not batched in FIFO (default);
0001: 12.5 Hz;
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
0101: 208 Hz;
0110: 417 Hz;
0111: 833 Hz;
1000: 1667 Hz;
1001: 3333 Hz;
1010: 6667 Hz;
1011: 6.5 Hz;
1100-1111: not allowed)
Selects Batching Data Rate (writing frequency in FIFO) for accelerometer data.
(0000: Accelerometer not batched in FIFO (default);
0001: 12.5 Hz;
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
0101: 208 Hz;
0110: 417 Hz;
0111: 833 Hz;
1000: 1667 Hz;
1001: 3333 Hz;
1010: 6667 Hz;
1011: 1.6 Hz;
1100-1111: not allowed)
DS12140 - Rev 2 page 45/172
9.6
LSM6DSO
FIFO_CTRL4 (0Ah)
FIFO_CTRL4 (0Ah)
FIFO control register 4 (r/w)
DEC_TS_
BATCH_1
DEC_TS_
BATCH_0
ODR_T_
BATCH_1
Table 31. FIFO_CTRL4 register
ODR_T_
BATCH_0
0
FIFO_
MODE2
FIFO_
MODE1
FIFO_
MODE0
Table 32. FIFO_CTRL4 register description
Selects decimation for timestamp batching in FIFO. Writing rate will be the maximum rate between
XL and GYRO BDR divided by decimation decoder.
DEC_TS_BATCH_[1:0]
(00: Timestamp not batched in FIFO (default);
01: Decimation 1: max(BDR_XL[Hz],BDR_GY[Hz]) [Hz];
10: Decimation 8: max(BDR_XL[Hz],BDR_GY[Hz])/8 [Hz];
11: Decimation 32: max(BDR_XL[Hz],BDR_GY[Hz])/32 [Hz])
ODR_T_BATCH_[1:0]
Selects batching data rate (writing frequency in FIFO) for temperature data
(00: Temperature not batched in FIFO (default);
01: 1.6 Hz;
10: 12.5 Hz;
11: 52 Hz)
FIFO_MODE[2:0]
FIFO mode selection
(000: Bypass mode: FIFO disabled;
001: FIFO mode: stops collecting data when FIFO is full;
010: Reserved;
011: Continuous-to-FIFO mode: Continuous mode until trigger is deasserted, then FIFO mode;
100: Bypass-to-Continuous mode: Bypass mode until trigger is deasserted, then Continuous mode;
101: Reserved;
110: Continuous mode: if the FIFO is full, the new sample overwrites the older one;
111: Bypass-to-FIFO mode: Bypass mode until trigger is deasserted, then FIFO mode.)
DS12140 - Rev 2 page 46/172
9.7
LSM6DSO
COUNTER_BDR_REG1 (0Bh)
COUNTER_BDR_REG1 (0Bh)
Counter batch data rate register 1 (r/w) dataready_ pulsed
RST_
COUNTER
_BDR
Table 33. COUNTER_BDR_REG1 register
TRIG_
COUNTER
_BDR
0 0
CNT_BDR_
TH_10
CNT_BDR_
TH_9
CNT_BDR_
TH_8
Table 34. COUNTER_BDR_REG1 register description dataready_pulsed
RST_COUNTER_BDR
Enables pulsed data-ready mode
(0: Data-ready latched mode (returns to 0 only after an interface reading) (default);
1: Data-ready pulsed mode (the data ready pulses are 75 µs long)
Resets the internal counter of batching events for a single sensor.
This bit is automatically reset to zero if it was set to ‘1’.
TRIG_COUNTER_BDR
Selects the trigger for the internal counter of batching events between XL and gyro.
(0: XL batching event;
1: GYRO batching event)
CNT_BDR_TH_[10:8]
In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch)
, sets the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset
and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.
DS12140 - Rev 2 page 47/172
9.8
9.9
LSM6DSO
COUNTER_BDR_REG2 (0Ch)
COUNTER_BDR_REG2 (0Ch)
Counter batch data rate register 2 (r/w)
CNT_BDR_
TH_7
CNT_BDR_
TH_6
Table 35. COUNTER_BDR_REG2 register
CNT_BDR_
TH_5
CNT_BDR_
TH_4
CNT_BDR_
TH_3
CNT_BDR_
TH_2
CNT_BDR_
TH_1
CNT_BDR_
TH_0
Table 36. COUNTER_BDR_REG2 register description
CNT_BDR_TH_[7:0]
In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh) , sets the threshold for the
internal counter of batching events. When this counter reaches the threshold, the counter is reset and
the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh)
is set to ‘1’.
INT1_CTRL (0Dh)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried out on INT1 when the MIPI I3C SM dynamic address is not assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI (In-Band Interrupt) when the MIPI
I3C SM interface is used. The output of the pin will be the OR combination of the signals selected here and in
.
DEN_DRDY
_flag
INT1_
CNT_BDR
INT1_
FIFO_FULL
Table 37. INT1_CTRL register
INT1_
FIFO_OVR
INT1_
FIFO_TH
INT1_
BOOT
INT1_
DRDY_G
INT1_
DRDY_XL
Table 38. INT1_CTRL register description
DEN_DRDY_flag Sends DEN_DRDY (DEN stamped on Sensor Data flag) to INT1 pin
INT1_CNT_BDR Enables COUNTER_BDR_IA interrupt on INT1 interface is used.
SM interface is used.
SM
INT1_FIFO_TH
INT1_BOOT
INT1_DRDY_G
INT1_DRDY_XL
Enables FIFO threshold interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3C SM interface is used.
Enables boot status on INT1 pin
Enables gyroscope data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI
I3C SM interface is used.
Enables accelerometer data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the
MIPI I3C SM interface is used.
DS12140 - Rev 2 page 48/172
LSM6DSO
INT2_CTRL (0Eh)
9.10
9.11
INT2_CTRL (0Eh)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried out on INT2 when the MIPI I3C SM dynamic address in not assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI when the MIPI I3C SM interface is used.
The output of the pin will be the OR combination of the signals selected here and in MD2_CFG (5Fh) .
0
INT2_
CNT_BDR
INT2_
FIFO_FULL
Table 39. INT2_CTRL register
INT2_
FIFO_OVR
INT2_
FIFO_TH
INT2_
DRDY_TEMP
INT2_
DRDY_G
INT2_
DRDY_XL
Table 40. INT2_CTRL register description
INT2_CNT_BDR Enables COUNTER_BDR_IA interrupt on INT2
INT2_FIFO_FULL Enables FIFO full flag interrupt on INT2 pin
INT2_FIFO_OVR
INT_FIFO_TH
Enables FIFO overrun interrupt on INT2 pin
Enables FIFO threshold interrupt on INT2 pin
INT2_DRDY_TEMP
Enables temperature sensor data-ready interrupt on INT2 pin. It can be also used to trigger an IBI when the MIPI I3C SM interface is used and INT2_ON_INT1 = ‘1’ in
.
INT2_DRDY_G
INT2_DRDY_XL
Gyroscope data-ready interrupt on INT2 pin
Accelerometer data-ready interrupt on INT2 pin
WHO_AM_I (0Fh)
WHO_AM_I register (r). This is a read-only register. Its value is fixed at 6Ch.
0 1 1
Table 41. WhoAmI register
0 1 1 0 0
DS12140 - Rev 2 page 49/172
LSM6DSO
CTRL1_XL (10h)
9.12
CTRL1_XL (10h)
Accelerometer control register 1 (r/w)
ODR_XL3 ODR_XL2 ODR_XL1
Table 42. CTRL1_XL register
ODR_XL0 FS1_XL FS0_XL LPF2_XL_EN 0
ODR_XL[3:0]
FS[1:0]_XL
LPF2_XL_EN
FS[1:0]_XL
00 (default)
01
10
11
Table 43. CTRL1_XL register description
Accelerometer ODR selection (see Table 44
)
Accelerometer full-scale selection (see
)
Accelerometer high-resolution selection
(0: output from first stage digital filtering selected (default);
1: output from LPF2 second filtering stage selected)
Table 44. Accelerometer ODR register setting
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0
ODR selection [Hz] when
XL_HM_MODE = 1 in
1
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
0
1
1
0
0
1 x
0
1
1
0
1
0
1
0
1
0
1
0 x
Power-down
1.6 Hz (low power only)
12.5 Hz (low power)
26 Hz (low power)
52 Hz (low power)
104 Hz (normal mode)
208 Hz (normal mode)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance)
6.66 kHz (high performance)
Not allowed
ODR selection [Hz] when
Power-down
12.5 Hz (high performance)
12.5 Hz (high performance)
26 Hz (high performance)
52 Hz (high performance)
104 Hz (high performance)
208 Hz (high performance)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance)
6.66 kHz (high performance)
Not allowed
Table 45. Accelerometer full-scale selection
XL_FS_MODE = ‘0’ in
2 g
16 g
4 g
8 g
XL_FS_MODE = ‘1’ in CTRL8_XL (17h)
2 g
2 g
4 g
8 g
DS12140 - Rev 2 page 50/172
LSM6DSO
CTRL2_G (11h)
9.13
CTRL2_G (11h)
Gyroscope control register 2 (r/w)
ODR_G3 ODR_G2 ODR_G1
Table 46. CTRL2_G register
ODR_G0 FS1_G FS0_G FS_125 0
ODR_G[3:0]
FS[1:0]_G
FS_125
Table 47. CTRL2_G register description
Gyroscope output data rate selection. Default value: 0000
(Refer to
)
Gyroscope UI chain full-scale selection
(00: 250 dps;
01: 500 dps;
10: 1000 dps;
11: 2000 dps)
Selects gyro UI chain full-scale 125 dps
(0: FS selected through bits FS[1:0]_G;
1: FS set to 125 dps)
ODR_G3 ODR_G2
0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
ODR_G1 ODR_G0
1
1
0
0
0
0
0
1
1
0
1
1
Table 48. Gyroscope ODR configuration setting
0
1
0
0
1
0
1
0
1
1
0
1
ODR [Hz] when G_HM_MODE = 1
Power down
12.5 Hz (low power)
26 Hz (low power)
52 Hz (low power)
104 Hz (normal mode)
208 Hz (normal mode)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance
6.66 kHz (high performance
Not available
ODR [Hz] when G_HM_MODE = 0 in
Power down
12.5 Hz (high performance)
26 Hz (high performance)
52 Hz (high performance)
104 Hz (high performance)
208 Hz (high performance)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance)
6.66 kHz (high performance)
Not available
DS12140 - Rev 2 page 51/172
LSM6DSO
CTRL3_C (12h)
9.14
CTRL3_C (12h)
Control register 3 (r/w)
BOOT BDU H_LACTIVE
Table 49. CTRL3_C register
PP_OD SIM IF_INC 0 SW_RESET
Table 50. CTRL3_C register description
BOOT
Reboots memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
This bit is automatically cleared.
BDU
Block Data Update. Default value: 0
(0: continuous update;
1: output registers are not updated until MSB and LSB have been read)
H_LACTIVE
Interrupt activation level. Default value: 0
(0: interrupt output pins active high; 1: interrupt output pins active low)
PP_OD
SIM
Push-pull/open-drain selection on INT1 and INT2 pins. Default value: 0
(0: push-pull mode; 1: open-drain mode)
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
IF_INC
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).
Default value: 1
(0: disabled; 1: enabled)
SW_RESET
Software reset. Default value: 0
(0: normal mode; 1: reset device)
This bit is automatically cleared.
DS12140 - Rev 2 page 52/172
LSM6DSO
CTRL4_C (13h)
9.15
CTRL4_C (13h)
Control register 4 (r/w)
0 SLEEP_G
INT2_on
_INT1
Table 51. CTRL4_C register
0 DRDY_MASK I2C_disable
LPF1_
SEL_G
Table 52. CTRL4_C register description
SLEEP_G
Enables gyroscope Sleep mode. Default value:0
(0: disabled; 1: enabled)
INT2_on_INT1
All interrupt signals available on INT1 pin enable. Default value: 0
(0: interrupt signals divided between INT1 and INT2 pins;
1: all interrupt signals in logic or on INT1 pin)
DRDY_MASK
Enables data available
(0: disabled;
1: mask DRDY on pin (both XL & Gyro) until filter settling ends (XL and Gyro independently masked).
I2C_disable
LPF1_SEL_G
Disables I²C interface. Default value: 0
(0: SPI, I²C and MIPI I3C SM interfaces enabled (default); 1: I²C interface disabled)
Enables gyroscope digital LPF1 if auxiliary SPI is disabled; the bandwidth can be selected through
FTYPE[2:0] in
.
(0: disabled; 1: enabled)
0
DS12140 - Rev 2 page 53/172
LSM6DSO
CTRL5_C (14h)
9.16
CTRL5_C (14h)
Control register 5 (r/w)
XL_ULP_EN ROUNDING1 ROUNDING0
Table 53. CTRL5_C register
0 ST1_G ST0_G ST1_XL ST0_XL
Table 54. CTRL5_C register description
XL_ULP_EN
ROUNDING[1:0]
ST[1:0]_G
ST[1:0]_XL
Accelerometer ultra-low-power mode enable. Default value: 0 (1)
(0: Ultra-low-power mode disabled; 1: Ultra-low-power mode enabled)
Circular burst-mode (rounding) read from the output registers. Default value: 00
(00: no rounding;
01: accelerometer only;
10: gyroscope only;
11: gyroscope + accelerometer)
Angular rate sensor self-test enable. Default value: 00
(00: Self-test disabled; Other: refer to
Linear acceleration sensor self-test enable. Default value: 00
(00: Self-test disabled; Other: refer to
.
ST1_G
0
0
1
1
Table 55. Angular rate sensor self-test mode selection
ST0_G
0
1
0
1
Self-test mode
Normal mode
Positive sign self-test
Not allowed
Negative sign self-test
ST1_XL
0
0
1
1
Table 56. Linear acceleration sensor self-test mode selection
ST0_XL
0
1
0
1
Self-test mode
Normal mode
Positive sign self-test
Negative sign self-test
Not allowed
DS12140 - Rev 2 page 54/172
LSM6DSO
CTRL6_C (15h)
9.17
CTRL6_C (15h)
Control register 6 (r/w)
TRIG_EN LVL1_EN LVL2_EN
Table 57. CTRL6_C register
XL_HM
_MODE
USR_
OFF_W
FTYPE_2 FTYPE_1 FTYPE_0
Table 58. CTRL6_C register description
TRIG_EN
LVL1_EN
LVL2_EN
XL_HM_MODE
USR_OFF_W
FTYPE[2:0]
DEN data edge-sensitive trigger enable. Refer to
.
DEN data level-sensitive trigger enable. Refer to
.
DEN level-sensitive latched enable. Refer to
High-performance operating mode disable for accelerometer. Default value: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
Weight of XL user offset bits of registers X_OFS_USR (73h)
,
(0: 2 -10 g /LSB;
1: 2 -6 g /LSB)
Gyroscope's low-pass filter (LPF1) bandwidth selection
shows the selectable bandwidth values (available if auxiliary SPI is disabled).
TRIG_EN, LVL1_EN, LVL2_EN
100
010
011
110
Table 59. Trigger mode selection
Trigger mode
Edge-sensitive trigger mode is selected
Level-sensitive trigger mode is selected
Level-sensitive latched mode is selected
Level-sensitive FIFO enable mode is selected
FTYPE
[2:0]
000
001
010
011
100
101
110
111
12.5 Hz
4.2
4.2
4.2
4.2
4.2
4.2
4.1
3.9
26 Hz
8.3
8.3
8.3
8.3
8.3
8.3
7.8
6.7
Table 60. Gyroscope LPF1 bandwidth selection
52 Hz
16.6
16.6
16.6
16.6
16.7
16.8
13.4
9.7
104 Hz
33.0
33.0
33.0
33.0
33.0
31.0
19.0
11.5
208 Hz
67.0
67.0
67.0
67.0
62.4
43.2
23.1
12.2
416 Hz
136.6
130.5
120.3
137.1
86.7
48.0
24.6
12.4
833 Hz
239.2
192.4
154.2
281.8
96.6
49.4
25.0
12.5
1.67 kHz
304.2
220.7
166.6
453.2
99.6
49.8
25.1
12.5
3.33 kHz
328.5
229.6
170.1
559.2
NA
NA
NA
NA
6.67 kHz
335.5
232.0
171.1
609.0
NA
NA
NA
NA
DS12140 - Rev 2 page 55/172
LSM6DSO
CTRL7_G (16h)
9.18
CTRL7_G (16h)
Control register 7 (r/w)
Table 61. CTRL7_G register
G_HM_
MODE
HP_EN_G HPM1_G HPM0_G
1. This bit must be set to '0' for the correct operation of the device.
0
OIS_ON_EN
USR_OFF
_ON_OUT
OIS_ON
Table 62. CTRL7_G register description
G_HM_MODE
HP_EN_G
HPM_G[1:0]
USR_OFF_ON_
OUT
OIS_ON
Disables high-performance operating mode for gyroscope. Default value: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
Enables gyroscope digital high-pass filter. The filter is enabled only if the gyro is in HP mode. Default value: 0
(0: HPF disabled; 1: HPF enabled)
Gyroscope digital HP filter cutoff selection. Default: 00
(00: 16 mHz;
01: 65 mHz;
10: 260 mHz;
11: 1.04 Hz)
Selects how to enable and disable the OIS chain, after first configuration and enabling through SPI2.
(0: OIS chain is enabled/disabled with SPI2 interface;
1: OIS chain is enabled/disabled with primary interface)
Enables accelerometer user offset correction block; it's valid for the low-pass path - see
Figure 17. Accelerometer composite filter
. Default value: 0
(0: accelerometer user offset correction block bypassed;
1: accelerometer user offset correction block enabled)
Enables/disables the OIS chain from primary interface when the OIS_ON_EN bit is '1'.
(0: OIS disabled; 1: OIS enabled)
1. First, enabling OIS and OIS configurations must be done through SPI2, with OIS_ON_EN and OIS_ON set to '0'.
DS12140 - Rev 2 page 56/172
LSM6DSO
CTRL8_XL (17h)
9.19
CTRL8_XL (17h)
Control register 8 (r/w)
HPCF_XL_2 HPCF_XL_1 HPCF_XL_0
Table 63. CTRL8_XL register
HP_REF_
MODE_XL
FASTSETTL_
MODE_XL
HP_SLOPE_
XL_EN
XL_FS_
MODE
LOW_PASS_
ON_6D
Filter type
Low pass
Table 64. CTRL8_XL register description
HPCF_XL_[2:0] Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to
.
HP_REF_
MODE_XL
FASTSETTL
_MODE_XL
Enables accelerometer high-pass filter reference mode (valid for high-pass path - HP_SLOPE_XL_EN bit
must be ‘1’). Default value: 0 (1)
(0: disabled, 1: enabled)
Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after writing this bit. Active only during device exit from power- down mode. Default value: 0
(0: disabled, 1: enabled)
HP_SLOPE_
XL_EN
Accelerometer slope filter / high-pass filter selection. Refer to
Figure 24. Accelerometer block diagram .
XL_FS_MODE
LOW_PASS
_ON_6D
Accelerometer full-scale management between UI chain and OIS chain
(0: Old full-scale mode. When XL UI is on, the full scale is the same between UI/OIS and is chosen by the UI
CTRL registers; when XL UI is in PD, the OIS can choose the FS.
1: New full-scale mode. Full scales are independent between the UI/OIS chain but both bound to 8 g.)
LPF2 on 6D function selection. Refer to
. Default value: 0
(0: ODR/2 low-pass filtered data sent to 6D interrupt function;
1: LPF2 output data sent to 6D interrupt function)
1. When enabled, the first output data have to be discarded.
Table 65. Accelerometer bandwidth configurations
HP_SLOPE_
XL_EN
LPF2_XL_EN HPCF_XL_[2:0]
0
0
1
-
000
001
010
011
100
101
110
111
Bandwidth
ODR/2
ODR/4
ODR/10
ODR/20
ODR/45
ODR/100
ODR/200
ODR/400
ODR/800
DS12140 - Rev 2 page 57/172
LSM6DSO
CTRL8_XL (17h)
Filter type
High pass
LPF1 output
(1)
HP_SLOPE_
XL_EN
1
LPF2_XL_EN
-
HPCF_XL_[2:0]
000
001
010
011
100
101
110
111
Figure 24. Accelerometer block diagram
Bandwidth
SLOPE (ODR/4)
ODR/10
ODR/20
ODR/45
ODR/100
ODR/200
ODR/400
ODR/800
Free-fall
LOW_PASS_ON_6D
Advanced functions
Digital
LP Filter
LPF2
LPF2_XL_EN
0
USER
OFFSET
0
1
6D / 4D
USR_OFF_ON_OUT
0
HP_SLOPE_XL_EN
0
1
1 USR_OFF_W
OFS_USR[7:0]
HPCF_XL[2:0]
Digital
HP Filter
1
0
1
0
USR_OFF_ON_WU SLOPE_FDS
Wake-up
Activity /
Inactivity
001
010
…
111
HPCF_XL[2:0]
1
FIFO
SPI /
I 2 C /
MIPI I3C
SM
SLOPE
FILTER
000
HPCF_XL[2:0]
S/D Tap
DS12140 - Rev 2 page 58/172
LSM6DSO
CTRL9_XL (18h)
9.20
CTRL9_XL (18h)
Control register 9 (r/w)
Table 66. CTRL9_XL register
DEN_X DEN_Y DEN_Z DEN_XL_G DEN_XL_EN
1. This bit must be set to '0' for the correct operation of the device.
DEN_LH I3C_disable 0
Table 67. CTRL9_XL register description
DEN_X
DEN_Y
DEN_Z
DEN_XL_G
DEN_XL_EN
DEN_LH
I3C_disable
DEN value stored in LSB of X-axis. Default value: 1
(0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB)
DEN value stored in LSB of Y-axis. Default value: 1
(0: DEN not stored in Y-axis LSB; 1: DEN stored in Y-axis LSB)
DEN value stored in LSB of Z-axis. Default value: 1
(0: DEN not stored in Z-axis LSB; 1: DEN stored in Z-axis LSB)
DEN stamping sensor selection. Default value: 0
(0: DEN pin info stamped in the gyroscope axis selected by bits [7:5];
1: DEN pin info stamped in the accelerometer axis selected by bits [7:5])
Extends DEN functionality to accelerometer sensor. Default value: 0
(0: disabled; 1: enabled)
DEN active level configuration. Default value: 0
(0: active low; 1: active high)
Disables MIPI I3C SM communication protocol
(0: SPI, I²C, MIPI I3C SM interfaces enabled (default);
1: MIPI I3C SM interface disabled)
1. It is recommended to set this bit to '1' during the initial device configuration phase, when the I3C interface is not used.
DS12140 - Rev 2 page 59/172
LSM6DSO
CTRL10_C (19h)
9.21
9.22
CTRL10_C (19h)
Control register 10 (r/w)
0 0
TIMESTAMP
_EN
Table 68. CTRL10_C register
0 0 0 0 0
Table 69. CTRL10_C register description
TIMESTAMP_EN
Enables timestamp counter. default value: 0
(0: disabled; 1: enabled)
The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and
ALL_INT_SRC (1Ah)
Source register for all interrupts (r)
TIMESTAMP
_ENDCOUNT
0
Table 70. ALL_INT_SRC register
SLEEP_
CHANGE_IA
D6D_IA
DOUBLE_
TAP
SINGLE_
TAP
WU_IA FF_IA
Table 71. ALL_INT_SRC register description
TIMESTAMP_ENDCOUNT Alerts timestamp overflow within 6.4 ms
SLEEP_CHANGE_IA
Detects change event in activity/inactivity status. Default value: 0
(0: change status not detected; 1: change status detected)
D6D_IA
DOUBLE_TAP
SINGLE_TAP
WU_IA
FF_IA
Interrupt active for change in position of portrait, landscape, face-up, face-down. Default value: 0
(0: change in position not detected; 1: change in position detected)
Double-tap event status. Default value: 0
(0:event not detected, 1: event detected)
Single-tap event status. Default value:0
(0: event not detected, 1: event detected)
Wake-up event status. Default value: 0
(0: event not detected, 1: event detected)
Free-fall event status. Default value: 0
(0: event not detected, 1: event detected)
DS12140 - Rev 2 page 60/172
LSM6DSO
WAKE_UP_SRC (1Bh)
9.23
WAKE_UP_SRC (1Bh)
Wake-up interrupt source register (r)
0
SLEEP_
CHANGE_IA
FF_IA
Table 72. WAKE_UP_SRC register
SLEEP_
STATE
WU_IA X_WU Y_WU
SLEEP_ CHANGE_IA
FF_IA
SLEEP_STATE
WU_IA
X_WU
Y_WU
Z_WU
Table 73. WAKE_UP_SRC register description
Detects change event in activity/inactivity status. Default value: 0
(0: change status not detected; 1: change status detected)
Free-fall event detection status. Default value: 0
(0: free-fall event not detected; 1: free-fall event detected)
Sleep status bit. Default value: 0
(0: Activity status; 1: Inactivity status)
Wakeup event detection status. Default value: 0
(0: wakeup event not detected; 1: wakeup event detected.)
Wakeup event detection status on X-axis. Default value: 0
(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)
Wakeup event detection status on Y-axis. Default value: 0
(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)
Wakeup event detection status on Z-axis. Default value: 0
(0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected)
Z_WU
DS12140 - Rev 2 page 61/172
LSM6DSO
TAP_SRC (1Ch)
9.24
TAP_IA
SINGLE_TAP
DOUBLE_TAP
TAP_SIGN
X_TAP
Y_TAP
Z_TAP
TAP_SRC (1Ch)
Tap source register (r)
0 TAP_IA
SINGLE_
TAP
Table 74. TAP_SRC register
DOUBLE_
TAP
TAP_SIGN X_TAP
Table 75. TAP_SRC register description
Tap event detection status. Default: 0
(0: tap event not detected; 1: tap event detected)
Single-tap event status. Default value: 0
(0: single tap event not detected; 1: single tap event detected)
Double-tap event detection status. Default value: 0
(0: double-tap event not detected; 1: double-tap event detected.)
Sign of acceleration detected by tap event. Default: 0
(0: positive sign of acceleration detected by tap event;
1: negative sign of acceleration detected by tap event)
Tap event detection status on X-axis. Default value: 0
(0: tap event on X-axis not detected; 1: tap event on X-axis detected)
Tap event detection status on Y-axis. Default value: 0
(0: tap event on Y-axis not detected; 1: tap event on Y-axis detected)
Tap event detection status on Z-axis. Default value: 0
(0: tap event on Z-axis not detected; 1: tap event on Z-axis detected)
Y_TAP Z_TAP
DS12140 - Rev 2 page 62/172
LSM6DSO
D6D_SRC (1Dh)
9.25
D6D_SRC (1Dh)
Portrait, landscape, face-up and face-down source register (r)
DEN_DRDY D6D_IA ZH
Table 76. D6D_SRC register
ZL YH YL XH
Table 77. D6D_SRC register description
DEN_DRDY
DEN data-ready signal. It is set high when data output is related to the data coming from a DEN active
D6D_IA
ZH
Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0
(0: change position not detected; 1: change position detected)
Z-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
ZL
YH
YL
XH
XL
Z-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
Y-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over-threshold) detected)
Y-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
X-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
X-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready_pulsed bit of the
register.
XL
DS12140 - Rev 2 page 63/172
LSM6DSO
STATUS_REG (1Eh) / STATUS_SPIAux (1Eh)
9.26
STATUS_REG (1Eh) / STATUS_SPIAux (1Eh)
The STATUS_REG register is read by the primary interface SPI/I²C & MIPI I3C SM (r).
0 0 0
Table 78. STATUS_REG register
0 0 TDA GDA
TDA
GDA
XLDA
Table 79. STATUS_REG register description
Temperature new data available. Default: 0
(0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
Gyroscope new data available. Default value: 0
(0: no set of data available at gyroscope output;
1: a new set of data is available at gyroscope output)
Accelerometer new data available. Default value: 0
(0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)
The STATUS_SPIAux register is read by the auxiliary SPI.
0 0 0
Table 80. STATUS_SPIAux register
0 0
GYRO_
SETTLING
GDA
GYRO_
SETTLING
GDA
XLDA
Table 81. STATUS_SPIAux description
High when the gyroscope output is in the settling phase
Gyroscope data available (reset when one of the high parts of the output data is read)
Accelerometer data available (reset when one of the high parts of the output data is read)
XLDA
XLDA
DS12140 - Rev 2 page 64/172
LSM6DSO
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
9.27
9.28
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.
Temp7 Temp6 Temp5
Table 82. OUT_TEMP_L register
Temp4 Temp3 Temp2 Temp1 Temp0
Temp15 Temp14 Temp13
Table 83. OUT_TEMP_H register
Temp12 Temp11 Temp10 Temp9 Temp8
Temp[15:0]
Table 84. OUT_TEMP register description
Temperature sensor output data
The value is expressed as two’s complement sign extended on the MSB.
OUTX_L_G (22h) and OUTX_H_G (23h)
Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (
) of gyro user interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro.
D7 D6 D5
Table 85. OUTX_L_G register
D4 D3 D2 D1 D0
D15 D14 D13
Table 86. OUTX_H_G register
D12 D11 D10
D[15:0]
Table 87. OUTX_H_G register description
Pitch axis (X) angular rate value
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3C SM : Gyro UI chain pitch axis output
SPI2: Gyro OIS chain pitch axis output
D9 D8
DS12140 - Rev 2 page 65/172
LSM6DSO
OUTY_L_G (24h) and OUTY_H_G (25h)
9.29
9.30
OUTY_L_G (24h) and OUTY_H_G (25h)
Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (
) of the gyro user interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro.
D7 D6 D5
Table 88. OUTY_L_G register
D4 D3 D2 D1 D0
D15 D14 D13
Table 89. OUTY_H_G register
D12 D11 D10 D9 D8
D[15:0]
Table 90. OUTY_H_G register description
Roll axis (Y) angular rate value
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3C SM : Gyro UI chain roll axis output
SPI2: Gyro OIS chain roll axis output
OUTZ_L_G (26h) and OUTZ_H_G (27h)
Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (
) of the gyro user interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro.
D7 D6 D5
Table 91. OUTZ_L_G register
D4 D3 D2 D1 D0
D15 D14 D13
Table 92. OUTZ_H_G register
D12 D11 D10
D[15:0]
Table 93. OUTZ_H_G register description
Yaw axis (Z) angular rate value
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3C SM : Gyro UI chain yaw axis output
SPI2: Gyro OIS chain yaw axis output
D9 D8
DS12140 - Rev 2 page 66/172
LSM6DSO
OUTX_L_A (28h) and OUTX_H_A (29h)
9.31
9.32
OUTX_L_A (28h) and OUTX_H_A (29h)
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
) of the accelerometer user interface.
If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of the OIS (
D7 D6 D5
Table 94. OUTX_L_A register
D4 D3 D2 D1 D0
D15 D14 D13
Table 95. OUTX_H_A register
D12 D11 D10 D9 D8
D[15:0]
Table 96. OUTX_H_A register description
X-axis linear acceleration value.
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3C SM : Accelerometer UI chain X-axis output
SPI2: Accelerometer OIS chain X-axis output
OUTY_L_A (2Ah) and OUTY_H_A (2Bh)
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
) of the accelerometer user interface.
If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of the OIS (
D7 D6 D5
Table 97. OUTY_L_A register
D4 D3 D2 D1 D0
D15 D14 D13
Table 98. OUTY_H_A register
D12 D11 D10
D[15:0]
Table 99. OUTY_H_A register description
Y-axis linear acceleration value
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3C SM : Accelerometer UI chain Y-axis output
SPI2: Accelerometer OIS chain Y-axis output
D9 D8
DS12140 - Rev 2 page 67/172
LSM6DSO
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
9.33
9.34
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
) of the accelerometer user interface.
If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of the OIS (
D7 D6 D5
Table 100. OUTZ_L_A register
D4 D3 D2 D1 D0
D15 D14 D13
Table 101. OUTZ_H_A register
D12 D11 D10 D9 D8
D[15:0]
Table 102. OUTZ_H_A register description
Z-axis linear acceleration value
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3C SM : Accelerometer UI chain Z-axis output
SPI2: Accelerometer OIS chain Z-axis output
EMB_FUNC_STATUS_MAINPAGE (35h)
Embedded function status register (r)
IS_FSM_LC 0
Table 103. EMB_FUNC_STATUS_MAINPAGE register
IS_SIGMOT IS_TILT IS_STEP_DET 0 0
IS_FSM_LC
IS_SIGMOT
IS_TILT
IS_STEP_DET
Table 104. EMB_FUNC_STATUS_MAINPAGE register description
Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for significant motion detection
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for tilt detection
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for step detection
(1: interrupt detected; 0: no interrupt)
0
DS12140 - Rev 2 page 68/172
LSM6DSO
FSM_STATUS_A_MAINPAGE (36h)
9.35
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
FSM_STATUS_A_MAINPAGE (36h)
Finite State Machine status register (r)
IS_FSM8 IS_FSM7
Table 105. FSM_STATUS_A_MAINPAGE register
IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1
Table 106. FSM_STATUS_A_MAINPAGE register description
Interrupt status bit for FSM8 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM7 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM6 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM5 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM4 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM3 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM2 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM1 interrupt event.
(1: interrupt detected; 0: no interrupt)
DS12140 - Rev 2 page 69/172
LSM6DSO
FSM_STATUS_B_MAINPAGE (37h)
9.36
9.37
FSM_STATUS_B_MAINPAGE (37h)
Finite State Machine status register (r)
IS_FSM16 IS_FSM15
Table 107. FSM_STATUS_B_MAINPAGE register
IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
Table 108. FSM_STATUS_B_MAINPAGE register description
Interrupt status bit for FSM16 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM15 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM14 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM13 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM12 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM11 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM10 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM9 interrupt event.
(1: interrupt detected; 0: no interrupt)
STATUS_MASTER_MAINPAGE (39h)
Sensor hub source register (r)
WR_ONCE_
DONE
SLAVE3_
NACK
Table 109. STATUS_MASTER_MAINPAGE register
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK
0 0
SENS_HUB_
ENDOP
Table 110. STATUS_MASTER_MAINPAGE register description
WR_ONCE_DONE
SLAVE3_NACK
SLAVE2_NACK
SLAVE1_NACK
When the bit WRITE_ONCE in
is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
SENS_HUB_ENDOP
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded;
1: sensor hub communication concluded)
DS12140 - Rev 2 page 70/172
LSM6DSO
FIFO_STATUS1 (3Ah)
9.38
9.39
FIFO_STATUS1 (3Ah)
FIFO status register 1 (r)
DIFF_
FIFO_7
DIFF_
FIFO_6
DIFF_
FIFO_5
Table 111. FIFO_STATUS1 register
DIFF_
FIFO_4
DIFF_
FIFO_3
DIFF_
FIFO_2
DIFF_
FIFO_1
DIFF_
FIFO_0
DIFF_FIFO_[7:0]
Table 112. FIFO_STATUS1 register description
Number of unread sensor data (TAG + 6 bytes) stored in FIFO
In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh)
.
FIFO_STATUS2 (3Bh)
FIFO status register 2 (r)
Table 113. FIFO_STATUS2 register
FIFO_
WTM_IA
FIFO_
OVR_IA
FIFO_
FULL_IA
COUNTER
_BDR_IA
FIFO_OVR_
1. This bit must be set to '0' for the correct operation of the device.
LATCHED
0
DIFF_
FIFO_9
DIFF_
FIFO_8
Table 114. FIFO_STATUS2 register description
FIFO_
WTM_IA
FIFO_
OVR_IA
FIFO_
FULL_IA
FIFO watermark status. Default value: 0
(0: FIFO filling is lower than WTM;
1: FIFO filling is equal to or greater than WTM)
Watermark is set through bits WTM[8:0] in
FIFO_CTRL2 (08h) and FIFO_CTRL1 (07h) .
FIFO overrun status. Default value: 0
(0: FIFO is not completely filled; 1: FIFO is completely filled)
Smart FIFO full status. Default value: 0
(0: FIFO is not full; 1: FIFO will be full at the next ODR)
COUNTER_
BDR_IA
Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in COUNTER_BDR_REG1 (0Bh) and
COUNTER_BDR_REG2 (0Ch) . Default value: 0
This bit is reset when these registers are read.
FIFO_OVR_
LATCHED
Latched FIFO overrun status. Default value: 0
This bit is reset when this register is read.
DIFF_
FIFO_[9:8]
Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00
In conjunction with DIFF_FIFO[7:0] in
DS12140 - Rev 2 page 71/172
9.40
LSM6DSO
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h)
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3
(43h)
Timestamp first data output register (r). The value is expressed as a 32-bit word and the bit resolution is 25 µs.
D31 D30
Table 115. TIMESTAMP output registers
D29 D28 D27 D26 D25 D24
D23
D15
D22
D14
D21
D13
D20
D12
D19
D11
D18
D10
D17
D9
D16
D8
D7
D[31:0]
D6 D5 D4 D3 D2
Table 116. TIMESTAMP output register description
Timestamp output registers: 1LSB = 25 µs
D1 D0
DS12140 - Rev 2 page 72/172
LSM6DSO
TAP_CFG0 (56h)
9.41
TAP_CFG0 (56h)
Activity/inactivity functions, configuration of filtering, and tap recognition functions (r/w)
0
INT_CLR_
ON_READ
SLEEP_
STATUS_
ON_INT
Table 117. TAP_CFG0 register
SLOPE_FDS TAP_X_EN TAP_Y_EN TAP_Z_EN LIR
Table 118. TAP_CFG0 register description
INT_CLR_ON_READ
This bit allows immediately clearing the latched interrupts of an event detection upon the read of the corresponding status register. It must be set to 1 together with LIR. Default value: 0
(0: latched interrupt signal cleared at the end of the ODR period;
1: latched interrupt signal immediately cleared)
SLEEP_STATUS_ON_INT
Activity/inactivity interrupt mode configuration.
If INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or sleep change on the INT pins. Default value: 0
(0: sleep change notification on INT pins; 1: sleep status reported on INT pins)
SLOPE_FDS
TAP_X_EN
HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions. Default value: 0 (
0: SLOPE filter applied; 1: HPF applied)
Enable X direction in tap recognition. Default value: 0
(0: X direction disabled; 1: X direction enabled)
TAP_Y_EN
TAP_Z_EN
LIR
Enable Y direction in tap recognition. Default value: 0
(0: Y direction disabled; 1: Y direction enabled)
Enable Z direction in tap recognition. Default value: 0
(0: Z direction disabled; 1: Z direction enabled)
Latched Interrupt. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
DS12140 - Rev 2 page 73/172
LSM6DSO
TAP_CFG1 (57h)
9.42
9.43
TAP_CFG1 (57h)
Tap configuration register (r/w)
TAP_
PRIORITY_2
TAP_
PRIORITY_1
TAP_
PRIORITY_0
Table 119. TAP_CFG1 register
TAP_THS_X_4 TAP_THS_X_3 TAP_THS_X_2 TAP_THS_X_1 TAP_THS_X_0
TAP_PRIORITY_[2:0]
TAP_THS_X_[4:0]
Table 120. TAP_CFG1 register description
Selection of axis priority for TAP detection (see
X-axis tap recognition threshold. Default value: 0
1 LSB = FS_XL / (2 5 )
TAP_PRIORITY_[2:0]
000
001
010
011
100
101
110
111
Table 121. TAP priority decoding
Max. priority
X
Y
X
Z
X
Y
Z
Z
Mid. priority
Y
X
Z
Y
Y
Z
X
Y
TAP_CFG2 (58h)
Enables interrupt and inactivity functions, and tap recognition functions (r/w).
Min. priority
Z
Z
Y
X
Z
X
Y
X
INTERRUPTS_
ENABLE
INACT_EN1
Table 122. TAP_CFG2 register
INACT_EN0 TAP_THS_Y_4 TAP_THS_Y_3 TAP_THS_Y_2 TAP_THS_Y_1 TAP_THS_Y_0
INTERRUPTS_
ENABLE
INACT_EN[1:0]
TAP_THS_Y_[4:0]
Table 123. TAP_CFG2 register description
Enable basic interrupts (6D/4D, free-fall, wake-up, tap, inactivity). Default value: 0
(0: interrupt disabled; 1: interrupt enabled)
Enable activity/inactivity (sleep) function. Default value: 00
(00: stationary/motion-only interrupts generated, XL and gyro do not change;
01: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro does not change;
10: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to sleep mode;
11: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to power-down mode)
Y-axis tap recognition threshold. Default value: 0
1 LSB = FS_XL / (2 5 )
DS12140 - Rev 2 page 74/172
LSM6DSO
TAP_THS_6D (59h)
9.44
TAP_THS_6D (59h)
Portrait/landscape position and tap function threshold register (r/w).
D4D_EN
Table 124. TAP_THS_6D register
SIXD_THS1 SIXD_THS0
TAP_
THS_Z_4
TAP_
THS_Z_3
TAP_
THS_Z_2
TAP_
THS_Z_1
TAP_
THS_Z_0
D4D_EN
SIXD_THS[1:0]
TAP_THS_Z_[4:0]
Table 125. TAP_THS_6D register description
4D orientation detection enable. Z-axis position detection is disabled.
Default value: 0
(0: enabled; 1: disabled)
Threshold for 4D/6D function. Default value: 00
For details, refer to Table 126
.
Z-axis recognition threshold. Default value: 0
1 LSB = FS_XL / (2 5 )
SIXD_THS[1:0]
00
01
10
11
Table 126. Threshold for D4D/D6D function
Threshold value
80 degrees
70 degrees
60 degrees
50 degrees
DS12140 - Rev 2 page 75/172
LSM6DSO
INT_DUR2 (5Ah)
9.45
9.46
INT_DUR2 (5Ah)
Tap recognition function setting register (r/w).
DUR3 DUR2 DUR1
Table 127. INT_DUR2 register
DUR0 QUIET1 QUIET0 SHOCK1 SHOCK0
Table 128. INT_DUR2 register description
DUR[3:0]
QUIET[1:0]
Duration of maximum time gap for double tap recognition. Default: 0000
When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to
16*ODR_XL time. If the DUR[3:0] bits are set to a different value, 1LSB corresponds to 32*ODR_XL time.
Expected quiet time after a tap detection. Default value: 00
Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different value, 1LSB corresponds to 4*ODR_XL time.
SHOCK[1:0]
Maximum duration of overthreshold event. Default value: 00
Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event.
The default value of these bits is 00b which corresponds to 4*ODR_XL time. If the SHOCK[1:0] bits are set to a different value, 1LSB corresponds to 8*ODR_XL time.
WAKE_UP_THS (5Bh)
Single/double-tap selection and wake-up configuration (r/w)
SINGLE_
DOUBLE_
TAP
Table 129. WAKE_UP_THS register
USR_OFF_
ON_WU
WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0
Table 130. WAKE_UP_THS register description
SINGLE_
DOUBLE_TAP
Single/double-tap event enable. Default: 0
(0: only single-tap event enabled;
1: both single and double-tap events enabled)
USR_OFF_
ON_WU
WK_THS[5:0]
Drives the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the wakeup function.
Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in WAKE_UP_DUR (5Ch)
. Default value:
000000
DS12140 - Rev 2 page 76/172
LSM6DSO
WAKE_UP_DUR (5Ch)
9.47
WAKE_UP_DUR (5Ch)
Free-fall, wakeup and sleep mode functions duration setting register (r/w)
Table 131. WAKE_UP_DUR register
FF_DUR5 WAKE_DUR1 WAKE_DUR0
WAKE_THS_
W
SLEEP_DUR
3
SLEEP_DUR
2
SLEEP_DUR
1
SLEEP_DUR
0
Table 132. WAKE_UP_DUR register description
FF_DUR5
WAKE_DUR[1:0]
WAKE_THS_W
Free fall duration event. Default: 0
For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in
configuration.
1 LSB = 1 ODR_time
Wake up duration event. Default: 00
1LSB = 1 ODR_time
Weight of 1 LSB of wakeup threshold. Default: 0
(0: 1 LSB = FS_XL / (2 6 );
1: 1 LSB = FS_XL / (2 8 ) )
SLEEP_DUR[3:0]
Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)
1 LSB = 512 ODR
DS12140 - Rev 2 page 77/172
LSM6DSO
FREE_FALL (5Dh)
9.48
FREE_FALL (5Dh)
Free-fall function duration setting register (r/w)
FF_DUR4 FF_DUR3 FF_DUR2
Table 133. FREE_FALL register
FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0
Table 134. FREE_FALL register description
FF_DUR[4:0]
Free-fall duration event. Default: 0
For the complete configuration of the free fall duration, refer to FF_DUR5 in WAKE_UP_DUR (5Ch)
configuration
FF_THS[2:0]
Free fall threshold setting. Default: 000
For details refer to Table 135
.
FF_THS[2:0]
000
001
010
011
100
101
110
111
Table 135. Threshold for free-fall function
Threshold value
156 m g
219 m g
250 m g
312 m g
344 m g
406 m g
469 m g
500 m g
DS12140 - Rev 2 page 78/172
LSM6DSO
MD1_CFG (5Eh)
9.49
MD1_CFG (5Eh)
Functions routing on INT1 register (r/w)
INT1_
SLEEP_
CHANGE
INT1_
SINGLE_
TAP
INT1_WU
Table 136. MD1_CFG register
INT1_FF
INT1_
DOUBLE_
TAP
INT1_6D
INT1_
EMB_FUNC
INT1_
SHUB
Table 137. MD1_CFG register description
INT1_SLEEP_CHANGE
INT1_SINGLE_TAP
INT1_WU
INT1_FF
INT1_DOUBLE_TAP
INT1_6D
INT1_EMB_FUNC
INT1_SHUB
Routing of activity/inactivity recognition event on INT1. Default: 0
(0: routing of activity/inactivity event on INT1 disabled;
1: routing of activity/inactivity event on INT1 enabled)
Routing of single-tap recognition event on INT1. Default: 0
(0: routing of single-tap event on INT1 disabled;
1: routing of single-tap event on INT1 enabled)
Routing of wakeup event on INT1. Default value: 0
(0: routing of wakeup event on INT1 disabled;
1: routing of wakeup event on INT1 enabled)
Routing of free-fall event on INT1. Default value: 0
(0: routing of free-fall event on INT1 disabled;
1: routing of free-fall event on INT1 enabled)
Routing of tap event on INT1. Default value: 0
(0: routing of double-tap event on INT1 disabled;
1: routing of double-tap event on INT1 enabled)
Routing of 6D event on INT1. Default value: 0
(0: routing of 6D event on INT1 disabled;
1: routing of 6D event on INT1 enabled)
Routing of embedded functions event on INT1. Default value: 0
(0: routing of embedded functions event on INT1 disabled;
1: routing embedded functions event on INT1 enabled)
Routing of sensor hub communication concluded event on INT1.
Default value: 0
(0: routing of sensor hub communication concluded event on INT1 disabled;
1: routing of sensor hub communication concluded event on INT1 enabled)
1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in
register.
DS12140 - Rev 2 page 79/172
LSM6DSO
MD2_CFG (5Fh)
9.50
MD2_CFG (5Fh)
Functions routing on INT2 register (r/w)
INT2_
SLEEP_
CHANGE
INT2_
SINGLE_
TAP
INT2_WU
Table 138. MD2_CFG register
INT2_FF
INT2_
DOUBLE_
TAP
INT2_6D
INT2_
EMB_
FUNC
INT2_
TIMESTAMP
Table 139. MD2_CFG register description
INT2_SLEEP_CHANGE
INT2_SINGLE_TAP
INT2_WU
INT2_FF
INT2_DOUBLE_TAP
INT2_6D
INT2_EMB_FUNC
INT2_TIMESTAMP
Routing of activity/inactivity recognition event on INT2. Default: 0
(0: routing of activity/inactivity event on INT2 disabled;
1: routing of activity/inactivity event on INT2 enabled)
Single-tap recognition routing on INT2. Default: 0
(0: routing of single-tap event on INT2 disabled;
1: routing of single-tap event on INT2 enabled)
Routing of wakeup event on INT2. Default value: 0
(0: routing of wakeup event on INT2 disabled;
1: routing of wake-up event on INT2 enabled)
Routing of free-fall event on INT2. Default value: 0
(0: routing of free-fall event on INT2 disabled;
1: routing of free-fall event on INT2 enabled)
Routing of tap event on INT2. Default value: 0
(0: routing of double-tap event on INT2 disabled;
1: routing of double-tap event on INT2 enabled)
Routing of 6D event on INT2. Default value: 0
(0: routing of 6D event on INT2 disabled;
1: routing of 6D event on INT2 enabled)
Routing of embedded functions event on INT2. Default value: 0
(0: routing of embedded functions event on INT2 disabled;
1: routing embedded functions event on INT2 enabled)
Enables routing on INT2 pin of the alert for timestamp overflow within
6.4 ms
1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in
register.
DS12140 - Rev 2 page 80/172
LSM6DSO
I3C_BUS_AVB (62h)
9.51
9.52
I3C_BUS_AVB (62h)
I3C_BUS_AVB register (r/w)
Table 140. I3C_BUS_AVB register
0
0
0
I3C_Bus_Avb
_Sel1
I3C_Bus_Avb
1. This bit must be set to '0' for the correct operation of the device.
_Sel0
0
0
PD_DIS_
INT1
Table 141. I3C_BUS_AVB register description
PD_DIS_INT1
This bit allows disabling the INT1 pull-down.
(0: Pull-down on INT1 enabled (pull-down is effectively connected only when no interrupts are routed to the INT1 pin or when I3C dynamic address is assigned);
1: Pull-down on INT1 disabled (pull-down not connected)
These bits are used to select the bus available time when I3C IBI is used.
Default value: 00
I3C_Bus_Avb_Sel[1:0]
(00: bus available time equal to 50 µsec (default);
01: bus available time equal to 2 µsec;
10: bus available time equal to 1 msec;
11: bus available time equal to 25 msec)
INTERNAL_FREQ_FINE (63h)
Internal frequency register (r)
FREQ_
FINE7
FREQ_
FINE6
Table 142. INTERNAL_FREQ_FINE register
FREQ_
FINE5
FREQ_
FINE4
FREQ_
FINE3
FREQ_
FINE2
FREQ_
FINE1
FREQ_
FINE0
Table 143. INTERNAL_FREQ_FINE register description
FREQ_FINE[7:0]
Difference in percentage of the effective ODR (and Timestamp Rate) with respect to the typical. Step:
0.15%. 8-bit format, 2's complement.
DS12140 - Rev 2 page 81/172
LSM6DSO
INT_OIS (6Fh)
9.53
INT_OIS (6Fh)
OIS interrupt configuration register and accelerometer self-test enable setting. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
INT2_
DRDY_OIS
LVL2_OIS DEN_LH_OIS
Table 144. INT_OIS register
0 ST1_XL_OIS ST0_XL_OIS
INT2_DRDY_OIS
LVL2_OIS
DEN_LH_OIS
ST[1:0]_XL_OIS
Table 145. INT_OIS register description
Enables OIS chain DRDY on INT2 pin. This setting has priority over all other INT2 settings.
Enables level-sensitive latched mode on the OIS chain. Default value: 0
Indicates polarity of DEN signal on OIS chain
(0: DEN pin is active-low;
1: DEN pin is active-high)
Selects accelerometer self-test – effective only if XL OIS chain is enabled. Default value: 00
(00: Normal mode;
01: Positive sign self-test;
10: Negative sign self-test;
11: not allowed)
DS12140 - Rev 2 page 82/172
LSM6DSO
CTRL1_OIS (70h)
9.54
CTRL1_OIS (70h)
OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
0 LVL1_OIS SIM_OIS
Table 146. CTRL1_OIS register
Mode4_EN
FS1_G_
OIS
FS0_G_
OIS
FS_125_
OIS
OIS_EN_
SPI2
Table 147. CTRL1_OIS register description
LVL1_OIS
SIM_OIS
FS_125_OIS
OIS_EN_SPI2
Enables OIS data level-sensitive trigger
SPI2 3- or 4-wire interface. Default value: 0
(0: 4-wire SPI2;
1: 3-wire SPI2)
Mode4_EN
Enables accelerometer OIS chain. OIS outputs are available through SPI2 in registers 28h-2Dh.
Note: OIS_EN_SPI2 must be enabled (i.e. set to ‘1’) to enable also XL OIS chain.
Selects gyroscope OIS chain full-scale
(00: 250 dps;
FS[1:0]_G_OIS 01: 500 dps;
10: 1000 dps;
11: 2000 dps)
Selects gyroscope OIS chain full-scale 125 dps
(0: FS selected through bits FS[1:0]_OIS_G;
1: 125 dps)
Enables OIS chain data processing for gyro in Mode 3 and Mode 4 (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
When the OIS chain is enabled, the OIS outputs are available through the SPI2 in registers
(22h) and OUTX_H_G (23h) through not found and
STATUS_REG (1Eh) / STATUS_SPIAux (1Eh) , and LPF1
is dedicated to this chain.
register
.
DEN mode on the OIS path is active in the gyroscope only.
LVL1_OIS, LVL2_OIS
10
11
Table 148. DEN mode selection
DEN mode
Level-sensitive trigger mode is selected
Level-sensitive latched mode is selected
DS12140 - Rev 2 page 83/172
LSM6DSO
CTRL2_OIS (71h)
9.55
CTRL2_OIS (71h)
OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
HPM1_OIS
Table 149. CTRL2_OIS register
HPM0_OIS 0
FTYPE_1
_OIS
FTYPE_0
_OIS
HP_EN_OIS
Table 150. CTRL2_OIS register description
HPM[1:0]_OIS
Selects gyroscope OIS chain digital high-pass filter cutoff. Default value: 00
(00: 16 mHz;
01: 65 mHz;
10: 260 mHz;
11: 1.04 Hz)
FTYPE_[1:0]_OIS
Selects gyroscope digital LPF1 filter bandwidth. Table 151
shows cutoff and phase values obtained with all configurations.
HP_EN_OIS Enables gyroscope OIS chain digital high-pass filter
Table 151. Gyroscope OIS chain digital LPF1 filter bandwidth selection
FTYPE_[1:0]_OIS
00
01
10
11
Cutoff [Hz]
335.5
232.0
171.1
609.0
Phase @ 20 Hz [°]
-6.69
-8.78
-11.18
-4.91
DS12140 - Rev 2 page 84/172
LSM6DSO
CTRL3_OIS (72h)
9.56
Note:
Note:
CTRL3_OIS (72h)
OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
FS1_XL_
OIS
FS0_XL_
OIS
Table 152. CTRL3_OIS register
FILTER_XL_
CONF_OIS_2
FILTER_XL_
CONF_OIS_1
FILTER_XL_
CONF_OIS_0
ST1_OIS ST0_OIS
ST_OIS_
CLAMPDIS
FS[1:0]_XL_OIS
FILTER_XL_
CONF_OIS_[2:0]
ST[1:0]_OIS
ST_OIS_
CLAMPDIS
Table 153. CTRL3_OIS register description
Selects accelerometer OIS channel full-scale. See
Selects accelerometer OIS channel bandwidth. See
Selects gyroscope OIS chain self-test. Default value: 00
lists the output variation when the self-test is enabled and ST_OIS_CLAMPDIS = '1'.
(00: Normal mode;
01: Positive sign self-test;
10: Normal mode;
11: Negative sign self-test)
Disables OIS chain clamp
(0: All OIS chain outputs = 8000h during self-test;
1: OIS chain self-test outputs as shown in
FS[1:0]_XL_OIS
00 (default)
01
10
11
Table 154. Accelerometer OIS channel full-scale selection
XL_FS_MODE = ‘0’
XL UI ON
Full-scale selected from user interface
XL UI PD
2 g
16 g
4 g
8 g
XL_FS_MODE = ‘1’
-
2 g
2 g
4 g
8 g
XL_FS_MODE bit is in
When the accelerometer full-scale value is selected only from the UI side it is readable also from the OIS side.
Table 155. Accelerometer OIS channel bandwidth and phase
FILTER_XL_CONF_OIS[2:0]
000
001
010
011
100
101
Typ. overall bandwidth [Hz]
289
258
120
65.1
33.2
16.6
Typ. overall phase [°]
-5.72 @ 20 Hz
-6.80 @ 20 Hz
-13.2 @ 20 Hz
-21.5 @ 20 Hz
-19.1 @ 10 Hz
-33.5 @ 10 Hz
DS12140 - Rev 2 page 85/172
LSM6DSO
X_OFS_USR (73h)
9.57
9.58
FILTER_XL_CONF_OIS[2:0]
110
111
Typ. overall bandwidth [Hz]
8.30
4.14
Typ. overall phase [°]
-26.7 @ 4 Hz
-26.2 @ 2 Hz
Full scale
2000
1000
500
250
125
Table 156. Self-test nominal output variation
Ouput variation [dps]
400
200
100
50
25
X_OFS_USR (73h)
Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally subtracted from the acceleration value measured on the X-axis.
X_OFS_
USR_7
X_OFS_
USR_6
X_OFS_
USR_5
Table 157. X_OFS_USR register
X_OFS_
USR_4
X_OFS_
USR_3
X_OFS_
USR_2
X_OFS_
USR_1
X_OFS_
USR_0
Table 158. X_OFS_USR register description
X_OFS_USR_[7:0]
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on
. The value must be in the range [-127 127].
Y_OFS_USR (74h)
Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is internally subtracted from the acceleration value measured on the Y-axis.
Y_OFS_
USR_7
Y_OFS_
USR_6
Y_OFS_
USR_5
Table 159. Y_OFS_USR register
Y_OFS_
USR_4
Y_OFS_
USR_3
Y_OFS_
USR_2
Y_OFS_
USR_1
Y_OFS_
USR_0
Table 160. Y_OFS_USR register description
Y_OFS_USR_[7:0]
Accelerometer Y-axis user offset calibration expressed in 2’s complement, weight depends on
. The value must be in the range [-127, +127].
DS12140 - Rev 2 page 86/172
LSM6DSO
Z_OFS_USR (75h)
9.59
9.60
Z_OFS_USR (75h)
Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is internally subtracted from the acceleration value measured on the Z-axis.
Z_OFS_
USR_7
Z_OFS_
USR_6
Z_OFS_
USR_5
Table 161. Z_OFS_USR register
Z_OFS_
USR_4
Z_OFS_
USR_3
Z_OFS_
USR_2
Z_OFS_
USR_1
Z_OFS_
USR_0
Table 162. Z_OFS_USR register description
Z_OFS_USR_[7:0]
Accelerometer Z-axis user offset calibration expressed in 2’s complement, weight depends on
USR_OFF_W in
. The value must be in the range [-127, +127].
FIFO_DATA_OUT_TAG (78h)
FIFO tag register (r)
TAG_
SENSOR_4
TAG_
SENSOR_3
Table 163. FIFO_DATA_OUT_TAG register
TAG_
SENSOR_2
TAG_
SENSOR_1
TAG_
SENSOR_0
TAG_CNT_1 TAG_CNT_0
TAG_
PARITY
Table 164. FIFO_DATA_OUT_TAG register description
TAG_SENSOR_[4:0]
FIFO tag: identifies the sensor in:
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
,
FIFO_DATA_OUT_Y_H (7Ch) , and FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
For details, refer to Table 165
TAG_CNT_[1:0]
TAG_PARITY
2-bit counter which identifies sensor time slot
Parity check of TAG content
Table 165. FIFO tag
TAG_SENSOR_[4:0]
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Sensor name
Gyroscope NC
Accelerometer NC
Temperature
Timestamp
CFG_Change
Accelerometer NC_T_2
Accelerometer NC_T_1
Accelerometer 2xC
Accelerometer 3xC
Gyroscope NC_T_2
Gyroscope NC_T_1
Gyroscope 2xC
Gyroscope 3xC
Sensor Hub Slave 0
DS12140 - Rev 2 page 87/172
LSM6DSO
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
9.61
TAG_SENSOR_[4:0]
0x0F
0x10
0x11
0x12
0x19
Sensor name
Sensor Hub Slave 1
Sensor Hub Slave 2
Sensor Hub Slave 3
Step Counter
Sensor Hub Nack
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
FIFO data output X (r)
D15
Table 166. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers
D14 D13 D12 D11 D10 D9 D8
9.62
D7 D6 D5 D4 D3 D2 D1 D0
Table 167. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description
FIFO X-axis output D[15:0]
FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch)
FIFO data output Y (r)
D15
Table 168. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers
D14 D13 D12 D11 D10 D9 D8
9.63
D7 D6 D5 D4 D3 D2 D1 D0
Table 169. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description
FIFO Y-axis output D[15:0]
FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
FIFO data output Z (r)
D15
Table 170. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers
D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1
D[15:0]
Table 171. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description
FIFO Z-axis output
D0
DS12140 - Rev 2 page 88/172
LSM6DSO
Embedded functions register mapping
10
Embedded functions register mapping
The table given below provides a list of the registers for the embedded functions available in the device and the corresponding addresses. Embedded functions registers are accessible when FUNC_CFG_EN is set to '1' in
Name
PAGE_SEL
EMB_FUNC_EN_A
EMB_FUNC_EN_B
PAGE_ADDRESS
PAGE_VALUE
EMB_FUNC_INT1
FSM_INT1_A
FSM_INT1_B
EMB_FUNC_INT2
FSM_INT2_A
FSM_INT2_B
EMB_FUNC_STATUS
FSM_STATUS_A
FSM_STATUS_B
PAGE_RW
RESERVED
EMB_FUNC_FIFO_CFG
FSM_ENABLE_A
FSM_ENABLE_B
FSM_LONG_COUNTER_L
FSM_LONG_COUNTER_H
FSM_LONG_COUNTER_CLEAR
FSM_OUTS1
FSM_OUTS2
FSM_OUTS3
FSM_OUTS4
FSM_OUTS5
FSM_OUTS6
FSM_OUTS7
FSM_OUTS8
FSM_OUTS9
FSM_OUTS10
Table 172. Register address map - embedded functions
Type r/w r/w r r r r/w r/w r/w r/w r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r/w
18-43
44
46
47
48
10
12
13
14
17
0A
0B
0C
0E
0F
02
04
05
08
09
52
53
54
55
4F
50
51
49
4A
4C
4D
4E
Register address
Hex Binary
00000010
00000100
00000101
00001000
00001001
00001010
00001011
00001100
00001110
00001111
00010000
00010010
00010011
00010100
00010111
01000100
01000110
01000111
01001000
01001001
01001010
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
Default
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000 output output output
00000000
00000000
00000000
00000000
00000000
00000000
00000000 output output output output output output output output output output
Comment
DS12140 - Rev 2 page 89/172
LSM6DSO
Embedded functions register mapping
Name
FSM_OUTS11
FSM_OUTS12
FSM_OUTS13
FSM_OUTS14
FSM_OUTS15
FSM_OUTS16
RESERVED
EMB_FUNC_ODR_CFG_B
STEP_COUNTER_L
STEP_COUNTER_H
EMB_FUNC_SRC
EMB_FUNC_INIT_A
EMB_FUNC_INIT_B
Type r r r r r r r/w r r r/w r/w r/w
Register address
Hex Binary
5A
5B
5E
5F
62
63
64
66
67
56
57
58
59
01010110
01010111
01011000
01011001
01011010
01011011
01011110
01011111
01100010
01100011
01100100
01100110
01100111
Default output output output output output output
01001011 output output output
00000000
00000000
Comment
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS12140 - Rev 2 page 90/172
LSM6DSO
Embedded functions register description
11
Embedded functions register description
11.1
11.2
PAGE_SEL (02h)
Enable advanced features dedicated page (r/w)
Table 173. PAGE_SEL register
PAGE_SEL3 PAGE_SEL2 PAGE_SEL1 PAGE_SEL0
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
0
0
PAGE_SEL[3:0]
Table 174. PAGE_SEL register description
Select the advanced features dedicated page
Default value: 0000
EMB_FUNC_EN_A (04h)
Embedded functions enable register (r/w)
Table 175. EMB_FUNC_EN_A register
0
0
SIGN_
MOTION_EN
TILT_EN PEDO_EN
1. This bit must be set to '0' for the correct operation of the device.
0
SIGN_MOTION_EN
TILT_EN
PEDO_EN
Table 176. EMB_FUNC_EN_A register description
Enable significant motion detection function. Default value: 0
(0: significant motion detection function disabled;
1: significant motion detection function enabled)
Enable tilt calculation. Default value: 0
(0: tilt algorithm disabled;
1: tilt algorithm enabled)
Enable pedometer algorithm. Default value: 0
(0: pedometer algorithm disabled;
1: pedometer algorithm enabled)
0
0
1
0
DS12140 - Rev 2 page 91/172
LSM6DSO
EMB_FUNC_EN_B (05h)
11.3
11.4
EMB_FUNC_EN_B (05h)
Embedded functions enable register (r/w)
Table 177. EMB_FUNC_EN_B register
0
0
0
PEDO_
ADV_EN
1. This bit must be set to '0' for the correct operation of the device.
FIFO_
COMPR_EN
0
0
FSM_EN
Table 178. EMB_FUNC_EN_B register description
PEDO_ADV_EN
Enable pedometer false-positive rejection block and advanced detection feature block. Default value: 0
(0: Pedometer advanced features block disabled;
1: Pedometer advanced features block enabled)
FIFO_COMPR_EN
FSM_EN
Enable FIFO compression feature. Default value: 0
(0: FIFO compression feature disabled;
1: FIFO compression feature enabled)
Enable Finite State Machine (FSM) feature. Default value: 0
(0: FSM feature disabled; 1: FSM feature enabled)
1. This bit is effective if the FIFO_COMPR_RT_EN bit of
PAGE_ADDRESS (08h)
Page address register (r/w)
PAGE_
ADDR7
PAGE_
ADDR6
Table 179. PAGE_ADDRESS register
PAGE_
ADDR5
PAGE_
ADDR4
PAGE_
ADDR3
PAGE_
ADDR2
PAGE_
ADDR1
PAGE_
ADDR0
Table 180. PAGE_ADDRESS register description
PAGE_ADDR[7:0]
the address of the register to be written/read in the advanced features page selected through the bits
PAGE_SEL[3:0] in register
.
DS12140 - Rev 2 page 92/172
LSM6DSO
PAGE_VALUE (09h)
11.5
11.6
PAGE_VALUE (09h)
Page value register (r/w)
PAGE_
VALUE7
PAGE_
VALUE6
PAGE_
VALUE5
Table 181. PAGE_VALUE register
PAGE_
VALUE4
PAGE_
VALUE3
PAGE_
VALUE2
PAGE_
VALUE1
PAGE_
VALUE0
Table 182. PAGE_VALUE register description
PAGE_VALUE[7:0]
PAGE_READ = 1 in register PAGE_RW (17h)
) the data at the address PAGE_ADDR[7:0] of the selected advanced features page.
EMB_FUNC_INT1 (0Ah)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR combination of the selected signals.
Table 183. EMB_FUNC_INT1 register
INT1_
FSM_LC
0
INT1_
SIG_MOT
INT1_TILT
INT1_STEP_
DETECTOR
1. This bit must be set to '0' for the correct operation of the device.
0
0
Table 184. EMB_FUNC_INT1 register description
INT1_FSM_LC
Routing of FSM long counter timeout interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of significant motion event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
INT1_TILT
INT1_STEP_
Routing of tilt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of pedometer step recognition event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of
0
DS12140 - Rev 2 page 93/172
LSM6DSO
FSM_INT1_A (0Bh)
11.7
FSM_INT1_A (0Bh)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR combination of the selected signals.
INT1_
FSM8
INT1_
FSM7
INT1_
FSM6
Table 185. FSM_INT1_A register
INT1_
FSM5
INT1_
FSM4
INT1_
FSM3
INT1_
FSM2
INT1_
FSM1
Table 186. FSM_INT1_A register description
Routing of FSM8 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM7 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM6 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM5 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM4 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM3 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM2 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM1 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of
DS12140 - Rev 2 page 94/172
LSM6DSO
FSM_INT1_B (0Ch)
11.8
FSM_INT1_B (0Ch)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR combination of the selected signals.
INT1_
FSM16
INT1_
FSM15
INT1_
FSM14
Table 187. FSM_INT1_B register
INT1_
FSM13
INT1_
FSM12
INT1_
FSM11
INT1_
FSM10
INT1_
FSM9
Table 188. FSM_INT1_B register description
INT1_FSM16
INT1_FSM15
INT1_FSM14
INT1_FSM13
INT1_FSM12
INT1_FSM11
INT1_FSM10
Routing of FSM16 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM15 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM14 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM13 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM12 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM11 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM10 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM9 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of
DS12140 - Rev 2 page 95/172
LSM6DSO
EMB_FUNC_INT2 (0Eh)
11.9
EMB_FUNC_INT2 (0Eh)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR combination of the selected signals.
Table 189. EMB_FUNC_INT2 register
INT2_
FSM_LC
0
INT2_
SIG_MOT
INT2_TILT
INT2_STEP_
DETECTOR
1. This bit must be set to '0' for the correct operation of the device.
0
0
Table 190. EMB_FUNC_INT2 register description
INT2_FSM_LC
INT2_STEP_
Routing of FSM long counter timeout interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of significant motion event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
INT2_TILT
Routing of tilt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of pedometer step recognition event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of
is set to 1.
0
DS12140 - Rev 2 page 96/172
LSM6DSO
FSM_INT2_A (0Fh)
11.10
FSM_INT2_A (0Fh)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR combination of the selected signals.
INT2_
FSM8
INT2_
FSM7
INT2_
FSM6
Table 191. FSM_INT2_A register
INT2_
FSM5
INT2_
FSM4
INT2_
FSM3
INT2_
FSM2
INT2_
FSM1
Table 192. FSM_INT2_A register description
Routing of FSM8 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM7 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM6 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM5 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM4 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM3 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM2 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM1 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of
is set to 1.
DS12140 - Rev 2 page 97/172
LSM6DSO
FSM_INT2_B (10h)
11.11
FSM_INT2_B (10h)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR combination of the selected signals.
INT2_
FSM16
INT2_
FSM15
INT2_
FSM14
Table 193. FSM_INT2_B register
INT2_
FSM13
INT2_
FSM12
INT2_
FSM11
INT2_
FSM10
INT2_
FSM9
Table 194. FSM_INT2_B register description
INT2_FSM16
INT2_FSM15
INT2_FSM14
INT2_FSM13
INT2_FSM12
INT2_FSM11
INT2_FSM10
Routing of FSM16 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM15 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM14 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM13 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM12 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM11 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM10 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM9 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of
is set to 1.
DS12140 - Rev 2 page 98/172
LSM6DSO
EMB_FUNC_STATUS (12h)
11.12
EMB_FUNC_STATUS (12h)
Embedded function status register (r)
IS_
FSM_LC
0
Table 195. EMB_FUNC_STATUS register
IS_
SIGMOT
IS_
TILT
IS_
STEP_DET
0
IS_FSM_LC
IS_SIGMOT
IS_TILT
IS_STEP_DET
Table 196. EMB_FUNC_STATUS register description
Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for significant motion detection
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for tilt detection
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for step detection
(1: interrupt detected; 0: no interrupt)
0 0
DS12140 - Rev 2 page 99/172
LSM6DSO
FSM_STATUS_A (13h)
11.13
FSM_STATUS_A (13h)
Finite State Machine status register (r)
IS_FSM8 IS_FSM7
Table 197. FSM_STATUS_A register
IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
Table 198. FSM_STATUS_A register description
Interrupt status bit for FSM8 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM7 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM6 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM5 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM4 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM3 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM2 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM1 interrupt event.
(1: interrupt detected; 0: no interrupt)
DS12140 - Rev 2 page 100/172
LSM6DSO
FSM_STATUS_B (14h)
11.14
FSM_STATUS_B (14h)
Finite State Machine status register (r)
IS_FSM16 IS_FSM15
Table 199. FSM_STATUS_B register
IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
Table 200. FSM_STATUS_B register description
Interrupt status bit for FSM16 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM15 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM14 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM13 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM12 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM11 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM10 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM9 interrupt event.
(1: interrupt detected; 0: no interrupt)
DS12140 - Rev 2 page 101/172
LSM6DSO
PAGE_RW (17h)
11.15
PAGE_RW (17h)
Enable read and write mode of advanced features dedicated page (r/w)
Table 201. PAGE_RW register
EMB_
FUNC_LIR
PAGE_
WRITE
PAGE_
READ
0
1. This bit must be set to '0' for the correct operation of the device.
0
0
0
11.16
Table 202. PAGE_RW register description
EMB_FUNC_LIR
PAGE_WRITE
PAGE_READ
Latched Interrupt mode for embedded functions. Default value: 0
(0: Embedded Functions interrupt request not latched;
1: Embedded Functions interrupt request latched)
Enable writes to the selected advanced features dedicated page.
Default value: 0
(1: enable; 0: disable)
Enable reads from the selected advanced features dedicated page.
Default value: 0
(1: enable; 0: disable)
1. Page selected by PAGE_SEL[3:0] in
EMB_FUNC_FIFO_CFG (44h)
Embedded functions batching configuration register (r/w)
Table 203. EMB_FUNC_FIFO_CFG register
0
PEDO_
FIFO_EN
0
0
1. This bit must be set to '0' for the correct operation of the device.
0
0
0
PEDO_FIFO_EN
Table 204. EMB_FUNC_FIFO_CFG register description
Enable FIFO batching of step counter values. Default value: 0
0
0
DS12140 - Rev 2 page 102/172
LSM6DSO
FSM_ENABLE_A (46h)
11.17
FSM_ENABLE_A (46h)
FSM enable register (r/w)
FSM8_EN FSM7_EN
Table 205. FSM_ENABLE_A register
FSM6_EN FSM5_EN FSM4_EN FSM3_EN FSM2_EN FSM1_EN
11.18
FSM8_EN
FSM7_EN
FSM6_EN
FSM5_EN
FSM4_EN
FSM3_EN
FSM2_EN
FSM1_EN
Table 206. FSM_ENABLE_A register description
FSM8 enable. Default value: 0 (0: FSM8 disabled; 1: FSM8 enabled)
FSM7 enable. Default value: 0 (0: FSM7 disabled; 1: FSM7 enabled)
FSM6 enable. Default value: 0 (0: FSM6 disabled; 1: FSM6 enabled)
FSM5 enable. Default value: 0 (0: FSM5 disabled; 1: FSM5 enabled)
FSM4 enable. Default value: 0 (0: FSM4 disabled; 1: FSM4 enabled)
FSM3 enable. Default value: 0 (0: FSM3 disabled; 1: FSM3 enabled)
FSM2 enable. Default value: 0 (0: FSM2 disabled; 1: FSM2 enabled)
FSM1 enable. Default value: 0 (0: FSM1 disabled; 1: FSM1 enabled)
FSM_ENABLE_B (47h)
FSM enable register (r/w)
FSM16_EN FSM15_EN
Table 207. FSM_ENABLE_B register
FSM14_EN FSM13_EN FSM12_EN FSM11_EN FSM10_EN FSM9_EN
FSM16_EN
FSM15_EN
FSM14_EN
FSM13_EN
FSM12_EN
FSM11_EN
FSM10_EN
FSM9_EN
Table 208. FSM_ENABLE_B register description
FSM16 enable. Default value: 0 (0: FSM16 disabled; 1: FSM16 enabled)
FSM15 enable. Default value: 0 (0: FSM15 disabled; 1: FSM15 enabled)
FSM14 enable. Default value: 0 (0: FSM14 disabled; 1: FSM14 enabled)
FSM13 enable. Default value: 0 (0: FSM13 disabled; 1: FSM13 enabled)
FSM12 enable. Default value: 0 (0: FSM12 disabled; 1: FSM12 enabled)
FSM11 enable. Default value: 0 (0: FSM11 disabled; 1: FSM11 enabled)
FSM10 enable. Default value: 0 (0: FSM10 disabled; 1: FSM10 enabled)
FSM9 enable. Default value: 0 (0: FSM9 disabled; 1: FSM9 enabled)
DS12140 - Rev 2 page 103/172
LSM6DSO
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
11.19
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
FSM long counter status register (r/w)
Long counter value is an unsigned integer value (16-bit format); this value can be reset using the LC_CLEAR bit
in FSM_LONG_COUNTER_CLEAR (4Ah) register.
FSM_LC_7 FSM_LC_6
Table 209. FSM_LONG_COUNTER_L register
FSM_LC_5 FSM_LC_4 FSM_LC_3 FSM_LC_2 FSM_LC_1 FSM_LC_0
FSM_LC_[7:0]
Table 210. FSM_LONG_COUNTER_L register description
Long counter current value (LSbyte). Default value: 00000000
Table 211. FSM_LONG_COUNTER_H register
FSM_LC_15 FSM_LC_14 FSM_LC_13 FSM_LC_12 FSM_LC_11 FSM_LC_10 FSM_LC_9 FSM_LC_8
11.20
FSM_LC_[15:8]
Table 212. FSM_LONG_COUNTER_H register description
Long counter current value (MSbyte). Default value: 00000000
FSM_LONG_COUNTER_CLEAR (4Ah)
FSM long counter reset register (r/w)
Table 213. FSM_LONG_COUNTER_CLEAR register
0
0
0
0
0
1. This bit must be set to '0' for the correct operation of the device.
0
FSM_LC_
CLEARED
FSM_LC_
CLEAR
Table 214. FSM_LONG_COUNTER_CLEAR register description
FSM_LC_CLEARED This read-only bit is automatically set to 1 when the long counter reset is done. Default value: 0
FSM_LC_CLEAR Clear FSM long counter value. Default value: 0
DS12140 - Rev 2 page 104/172
11.21
FSM_OUTS1 (4Ch)
FSM1 output register (r)
P_X N_X P_Y
Table 215. FSM_OUTS1 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 216. FSM_OUTS1 register description
FSM1 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM1 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM1 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM1 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM1 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS1 (4Ch)
N_V
DS12140 - Rev 2 page 105/172
11.22
FSM_OUTS2 (4Dh)
FSM2 output register (r)
P_X N_X P_Y
Table 217. FSM_OUTS2 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 218. FSM_OUTS2 register description
FSM2 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM2 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM2 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM2 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM2 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS2 (4Dh)
N_V
DS12140 - Rev 2 page 106/172
11.23
FSM_OUTS3 (4Eh)
FSM3 output register (r)
P_X N_X P_Y
Table 219. FSM_OUTS3 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 220. FSM_OUTS3 register description
FSM3 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM3 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM3 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM3 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM3 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS3 (4Eh)
N_V
DS12140 - Rev 2 page 107/172
11.24
FSM_OUTS4 (4Fh)
FSM4 output register (r)
P_X N_X P_Y
Table 221. FSM_OUTS4 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 222. FSM_OUTS4 register description
FSM4 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM4 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM4 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM4 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM4 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS4 (4Fh)
N_V
DS12140 - Rev 2 page 108/172
11.25
FSM_OUTS5 (50h)
FSM5 output register (r)
P_X N_X P_Y
Table 223. FSM_OUTS5 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 224. FSM_OUTS5 register description
FSM5 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM5 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM5 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM5 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM5 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS5 (50h)
N_V
DS12140 - Rev 2 page 109/172
11.26
FSM_OUTS6 (51h)
FSM6 output register (r)
P_X N_X P_Y
Table 225. FSM_OUTS6 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 226. FSM_OUTS6 register description
FSM6 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM6 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM6 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM6 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM6 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS6 (51h)
N_V
DS12140 - Rev 2 page 110/172
11.27
FSM_OUTS7 (52h)
FSM7 output register (r)
P_X N_X P_Y
Table 227. FSM_OUTS7 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 228. FSM_OUTS7 register description
FSM7 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM7 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM7 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM7 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM7 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS7 (52h)
N_V
DS12140 - Rev 2 page 111/172
11.28
FSM_OUTS8 (53h)
FSM8 output register (r)
P_X N_X P_Y
Table 229. FSM_OUTS8 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 230. FSM_OUTS8 register description
FSM8 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM8 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM8 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM8 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM8 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS8 (53h)
N_V
DS12140 - Rev 2 page 112/172
11.29
FSM_OUTS9 (54h)
FSM9 output register (r)
P_X N_X P_Y
Table 231. FSM_OUTS9 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 232. FSM_OUTS9 register description
FSM9 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM9 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM9 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM9 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM9 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS9 (54h)
N_V
DS12140 - Rev 2 page 113/172
11.30
FSM_OUTS10 (55h)
FSM10 output register (r)
P_X N_X P_Y
Table 233. FSM_OUTS10 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 234. FSM_OUTS10 register description
FSM10 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM10 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM10 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM10 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM10 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS10 (55h)
N_V
DS12140 - Rev 2 page 114/172
11.31
FSM_OUTS11 (56h)
FSM11 output register (r)
P_X N_X P_Y
Table 235. FSM_OUTS11 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 236. FSM_OUTS11 register description
FSM11 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM11 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM11 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM11 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM11 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS11 (56h)
N_V
DS12140 - Rev 2 page 115/172
11.32
FSM_OUTS12 (57h)
FSM12 output register (r)
P_X N_X P_Y
Table 237. FSM_OUTS12 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 238. FSM_OUTS12 register description
FSM12 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM12 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM12 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM12 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM12 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS12 (57h)
N_V
DS12140 - Rev 2 page 116/172
11.33
FSM_OUTS13 (58h)
FSM13 output register (r)
P_X N_X P_Y
Table 239. FSM_OUTS13 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 240. FSM_OUTS13 register description
FSM13 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM13 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM13 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM13 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM13 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS13 (58h)
N_V
DS12140 - Rev 2 page 117/172
11.34
FSM_OUTS14 (59h)
FSM14 output register (r)
P_X N_X P_Y
Table 241. FSM_OUTS14 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 242. FSM_OUTS14 register description
FSM14 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM14 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM14 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM14 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM14 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS14 (59h)
N_V
DS12140 - Rev 2 page 118/172
11.35
FSM_OUTS15 (5Ah)
FSM15 output register (r)
P_X N_X P_Y
Table 243. FSM_OUTS15 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 244. FSM_OUTS15 register description
FSM15 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM15 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM15 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM15 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM15 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS15 (5Ah)
N_V
DS12140 - Rev 2 page 119/172
11.36
FSM_OUTS16 (5Bh)
FSM16 output register (r)
P_X N_X P_Y
Table 245. FSM_OUTS16 register
N_Y P_Z N_Z
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 246. FSM_OUTS16 register description
FSM16 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM16 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM16 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM16 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM16 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
P_V
LSM6DSO
FSM_OUTS16 (5Bh)
N_V
DS12140 - Rev 2 page 120/172
LSM6DSO
EMB_FUNC_ODR_CFG_B (5Fh)
11.37
11.38
EMB_FUNC_ODR_CFG_B (5Fh)
Finite State Machine output data rate configuration register (r/w)
Table 247. EMB_FUNC_ODR_CFG_B register
0
1
0
FSM_ODR1 FSM_ODR0
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
0
1
FSM_ODR[1:0]
Table 248. EMB_FUNC_ODR_CFG_B register description
Finite State Machine ODR configuration:
(00: 12.5 Hz;
01: 26 Hz (default);
10: 52 Hz;
11: 104 Hz)
STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h)
Step counter output register (r)
STEP_7 STEP_6
Table 249. STEP_COUNTER_L register
STEP_5 STEP_4 STEP_3 STEP_2 STEP_1
1
STEP_0
STEP_[7:0]
STEP_[15:8]
Table 250. STEP_COUNTER_L register description
Step counter output (LSbyte)
STEP_15 STEP_14
Table 251. STEP_COUNTER_H register
STEP_13 STEP_12 STEP_11 STEP_10 STEP_9 STEP_8
Table 252. STEP_COUNTER_H register description
Step counter output (MSbyte)
DS12140 - Rev 2 page 121/172
LSM6DSO
EMB_FUNC_SRC (64h)
11.39
EMB_FUNC_SRC (64h)
Embedded function source register (r/w)
PEDO_RST
_STEP
0
Table 253. EMB_FUNC_SRC register
STEP_
DETECTED
STEP_
COUNT_
DELTA_IA
STEP_
OVERFLOW
STEPCOUNT
ER_BIT_SET
0 0
11.40
Table 254. EMB_FUNC_SRC register description
PEDO_RST_STEP
STEP_DETECTED
STEP_COUNT_DELTA_IA
Reset pedometer step counter. Read/write bit.
(0: disabled; 1: enabled)
Step detector event detection status. Read-only bit.
(0: step detection event not detected; 1: step detection event detected)
Pedometer step recognition on delta time status. Read-only bit.
(0: no step recognized during delta time;
1: at least one step recognized during delta time)
STEP_OVERFLOW
Step counter overflow status. Read-only bit.
(0: step counter value < 2 16 ; 1: step counter value reached 2 16 )
STEPCOUNTER_BIT_SET
This bit is equal to 1 when the step count is increased. If a timer period is programmed in
PEDO_SC_DELTAT_L (D0h) & PEDO_SC_DELTAT_H (D1h) embedded advanced features
(page 1) registers, this bit is kept to 0.
Read-only bit.
EMB_FUNC_INIT_A (66h)
Embedded functions initialization register (r/w)
Table 255. EMB_FUNC_INIT_A register
0
0
SIG_MOT
_INIT
TILT
_INIT
1. This bit must be set to '0' for the correct operation of the device.
STEP_DET
_INIT
0
SIG_MOT_INIT
TILT_INIT
STEP_DET_INIT
Table 256. EMB_FUNC_INIT_A register description
Significant motion detection algorithm initialization request. Default value: 0
Tilt algorithm initialization request. Default value: 0
Pedometer step counter/detector algorithm initialization request.
Default value: 0
0
0
DS12140 - Rev 2 page 122/172
LSM6DSO
EMB_FUNC_INIT_B (67h)
11.41
EMB_FUNC_INIT_B (67h)
Embedded functions initialization register (r/w)
Table 257. EMB_FUNC_INIT_B register
0
0
0
0
FIFO_
COMPR_INIT
1. This bit must be set to '0' for the correct operation of the device.
0
FIFO_COMPR_INIT
FSM_INIT
Table 258. EMB_FUNC_INIT_B register description
FIFO compression feature initialization request. Default value: 0
FSM initialization request. Default value: 0
0
FSM_INIT
DS12140 - Rev 2 page 123/172
12
LSM6DSO
Embedded advanced features pages
Embedded advanced features pages
The table given below provides a list of the registers for the embedded advanced features page 0. These
registers are accessible when PAGE_SEL[3:0] are set to 0000 in PAGE_SEL (02h) .
Name
MAG_SENSITIVITY_L
MAG_SENSITIVITY_H
MAG_OFFX_L
MAG_OFFX_H
MAG_OFFY_L
MAG_OFFY_H
MAG_OFFZ_L
MAG_OFFZ_H
MAG_SI_XX_L
MAG_SI_XX_H
MAG_SI_XY_L
MAG_SI_XY_H
MAG_SI_XZ_L
MAG_SI_XZ_H
MAG_SI_YY_L
MAG_SI_YY_H
MAG_SI_YZ_L
MAG_SI_YZ_H
MAG_SI_ZZ_L
MAG_SI_ZZ_H
MAG_CFG_A
MAG_CFG_B r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
Table 259. Register address map - embedded advanced features page 0
Type
Hex
Register address
Binary
CC
CD
CE
CF
D0
D1
D4
D5
C7
C8
C9
CA
CB
C2
C3
C4
C5
C6
BA
BB
C0
C1
11000111
11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111
11010000
11010001
11010100
11010101
10111010
10111011
11000000
11000001
11000010
11000011
11000100
11000101
11000110
Default
00111100
00000000
00000000
00000000
00000000
00000000
00111100
00000000
00000000
00000000
00111100
00000101
00000010
00100100
00010110
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Comment
The table given below provides a list of the registers for the embedded advanced features page 1. These
registers are accessible when PAGE_SEL[3:0] are set to 0001 in PAGE_SEL (02h) .
Name
Table 260. Register address map - embedded advanced features page 1
FSM_LC_TIMEOUT_L
FSM_LC_TIMEOUT_H
FSM_PROGRAMS
Type r/w r/w r/w
Register address
Hex Binary
7A
7B
7C
01111010
01111011
01111100
Default
00000000
00000000
00000000
Comment
DS12140 - Rev 2 page 124/172
LSM6DSO
Embedded advanced features pages
Note:
Name
FSM_START_ADD_L
FSM_START_ADD_H
PEDO_CMD_REG
PEDO_DEB_STEPS_CONF
PEDO_SC_DELTAT_L
PEDO_SC_DELTAT_H
Type r/w r/w r/w r/w r/w r/w
Register address
Hex Binary
7E
7F
83
84
D0
D1
01111110
01111111
10000011
10000100
11010000
11010001
Default
00000000
00000000
00000000
00001010
00000000
00000000
Comment
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
Write procedure example:
Example: write value 06h register at address 84h (PEDO_DEB_STEPS_CONF) in Page 1
1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h)
2. Write bit PAGE_WRITE = 1 in PAGE_RW (17h) register
3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h)
4. Write 84h in PAGE_ADDR register (08h)
5. Write 06h in PAGE_DATA register (09h)
6. Write bit PAGE_WRITE = 0 in PAGE_RW (17h) register
7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h)
// Enable access to embedded functions registers
// Select write operation mode
// Select page 1
// Set address
// Set value to be written
// Write operation disabled
// Disable access to embedded functions registers
Read procedure example:
Example: read value of register at address 84h (PEDO_DEB_STEPS_CONF) in Page 1
1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h)
2. Write bit PAGE_READ = 1 in PAGE_RW (17h) register
3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h)
4. Write 84h in PAGE_ADDR register (08h)
5. Read value of PAGE_DATA register (09h)
6. Write bit PAGE_READ = 0 in PAGE_RW (17h) register
7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h)
// Enable access to embedded functions registers
// Select read operation mode
// Select page 1
// Set address
// Get register value
// Read operation disabled
// Disable access to embedded functions registers
Steps 1 and 2 of both procedures are intended to be performed at the beginning of the procedure. Steps 6 and 7 of both procedures are intended to be performed at the end of the procedure. If the procedure involves multiple operations, only steps 3, 4 and 5 must be repeated for each operation. If, in particular, the multiple operations involve consecutive registers, only step 5 can be performed.
DS12140 - Rev 2 page 125/172
13
LSM6DSO
Embedded advanced features register description
Embedded advanced features register description
13.1
13.1.1
Page 0 - Embedded advanced features registers
MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh)
External magnetometer sensitivity value register (r/w) for the Finite State Machine
This register corresponds to the LSB-to-gauss conversion value of the external magnetometer sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Default value of MAG_SENS[15:0] is 0x1624, corresponding to 0.0015 gauss/LSB.
MAG_
SENS_7
MAG_
SENS_6
Table 261. MAG_SENSITIVITY_L register
MAG_
SENS_5
MAG_
SENS_4
MAG_
SENS_3
MAG_
SENS_2
MAG_
SENS_1
MAG_
SENS_0
MAG_SENS_[7:0]
Table 262. MAG_SENSITIVITY_L register description
External magnetometer sensitivity (LSbyte). Default value: 00100100
MAG_
SENS_15
MAG_
SENS_14
Table 263. MAG_SENSITIVITY_H register
MAG_
SENS_13
MAG_
SENS_12
MAG_
SENS_11
MAG_
SENS_10
MAG_
SENS_9
MAG_
SENS_8
MAG_SENS_[15:8]
Table 264. MAG_SENSITIVITY_H register description
External magnetometer sensitivity (MSbyte). Default value: 00010110
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13.1.2
MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h)
Offset for X-axis hard-iron compensation register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 265. MAG_OFFX_L register
MAG_OFFX_7 MAG_OFFX_6 MAG_OFFX_5 MAG_OFFX_4 MAG_OFFX_3 MAG_OFFX_2 MAG_OFFX_1 MAG_OFFX_0
MAG_OFFX_[7:0]
Table 266. MAG_OFFX_L register description
Offset for X-axis hard-iron compensation (LSbyte). Default value: 00000000
MAG_OFFX_15 MAG_OFFX_14
Table 267. MAG_OFFX_H register
MAG_OFFX_13 MAG_OFFX_12 MAG_OFFX_11 MAG_OFFX_10 MAG_OFFX_9 MAG_OFFX_8
13.1.3
MAG_OFFX_[15:8]
Table 268. MAG_OFFX_H register description
Offset for X-axis hard-iron compensation (MSbyte). Default value: 00000000
MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h)
Offset for Y-axis hard-iron compensation register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 269. MAG_OFFY_L register
MAG_OFFY_7 MAG_OFFY_6 MAG_OFFY_5 MAG_OFFY_4 MAG_OFFY_3 MAG_OFFY_2 MAG_OFFY_1 MAG_OFFY_0
MAG_OFFY_[7:0]
Table 270. MAG_OFFY_L register description
Offset for Y-axis hard-iron compensation (LSbyte). Default value: 00000000
MAG_OFFY_15 MAG_OFFY_14
Table 271. MAG_OFFY_H register
MAG_OFFY_13 MAG_OFFY_12 MAG_OFFY_11 MAG_OFFY_10 MAG_OFFY_9 MAG_OFFY_8
MAG_OFFY_[15:8]
Table 272. MAG_OFFY_H register description
Offset for Y-axis hard-iron compensation (MSbyte). Default value: 00000000
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13.1.4
MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h)
Offset for Z-axis hard-iron compensation register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 273. MAG_OFFZ_L register
MAG_OFFZ_7 MAG_OFFZ_6 MAG_OFFZ_5 MAG_OFFZ_4 MAG_OFFZ_3 MAG_OFFZ_2 MAG_OFFZ_1 MAG_OFFZ_0
MAG_OFFZ_[7:0]
Table 274. MAG_OFFZ_L register description
Offset for Z-axis hard-iron compensation (LSbyte). Default value: 00000000
MAG_OFFZ_15 MAG_OFFZ_14
Table 275. MAG_OFFZ_H register
MAG_OFFZ_13 MAG_OFFZ_12 MAG_OFFZ_11 MAG_OFFZ_10 MAG_OFFZ_9 MAG_OFFZ_8
13.1.5
MAG_OFFZ_[15:8]
Table 276. MAG_OFFZ_H register description
Offset for Z-axis hard-iron compensation (MSbyte). Default value: 00000000
MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 277. MAG_SI_XX_L register
MAG_SI_XX_7 MAG_SI_XX_6 MAG_SI_XX_5 MAG_SI_XX_4 MAG_SI_XX_3 MAG_SI_XX_2 MAG_SI_XX_1 MAG_SI_XX_0
MAG_SI_XX_[7:0]
Table 278. MAG_SI_XX_L register description
Soft-iron correction row1 col1 coefficient (LSbyte). Default value: 00000000
Table 279. MAG_SI_XX_H register
MAG_SI_XX_15 MAG_SI_XX_14 MAG_SI_XX_13 MAG_SI_XX_12 MAG_SI_XX_11 MAG_SI_XX_10 MAG_SI_XX_9 MAG_SI_XX_8
MAG_SI_XX_[15:8]
Table 280. MAG_SI_XX_H register description
Soft-iron correction row1 col1 coefficient (MSbyte). Default value: 00111100
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13.1.6
MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 281. MAG_SI_XY_L register
MAG_SI_XY_7 MAG_SI_XY_6 MAG_SI_XY_5 MAG_SI_XY_4 MAG_SI_XY_3 MAG_SI_XY_2 MAG_SI_XY_1 MAG_SI_XY_0
MAG_SI_XY_[7:0]
Table 282. MAG_SI_XY_L register description
Soft-iron correction row1 col2 (and row2 col1) coefficient (LSbyte). Default value: 00000000
Table 283. MAG_SI_XY_H register
MAG_SI_XY_15 MAG_SI_XY_14 MAG_SI_XY_13 MAG_SI_XY_12 MAG_SI_XY_11 MAG_SI_XY_10 MAG_SI_XY_9 MAG_SI_XY_8
13.1.7
Table 284. MAG_SI_XY_H register description
MAG_SI_XY_[15:8] Soft-iron correction row1 col2 (and row2 col1) coefficient (MSbyte). Default value: 00000000
MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 285. MAG_SI_XZ_L register
MAG_SI_XZ_7 MAG_SI_XZ_6 MAG_SI_XZ_5 MAG_SI_XZ_4 MAG_SI_XZ_3 MAG_SI_XZ_2 MAG_SI_XZ_1 MAG_SI_XZ_0
MAG_SI_XZ_[7:0]
Table 286. MAG_SI_XZ_L register description
Soft-iron correction row1 col3 (and row3 col1) coefficient (LSbyte). Default value: 00000000
Table 287. MAG_SI_XZ_H register
MAG_SI_XZ_15 MAG_SI_XZ_14 MAG_SI_XZ_13 MAG_SI_XZ_12 MAG_SI_XZ_11 MAG_SI_XZ_10 MAG_SI_XZ_9 MAG_SI_XZ_8
Table 288. MAG_SI_XZ_H register description
MAG_SI_XZ_[15:8] Soft-iron correction row1 col3 (and row3 col1) coefficient (MSbyte). Default value: 00000000
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13.1.8
MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 289. MAG_SI_YY_L register
MAG_SI_YY_7 MAG_SI_YY_6 MAG_SI_YY_5 MAG_SI_YY_4 MAG_SI_YY_3 MAG_SI_YY_2 MAG_SI_YY_1 MAG_SI_YY_0
MAG_SI_YY_[7:0]
Table 290. MAG_SI_YY_L register description
Soft-iron correction row2 col2 coefficient (LSbyte). Default value: 00000000
Table 291. MAG_SI_YY_H register
MAG_SI_YY_15 MAG_SI_YY_14 MAG_SI_YY_13 MAG_SI_YY_12 MAG_SI_YY_11 MAG_SI_YY_10 MAG_SI_YY_9 MAG_SI_YY_8
13.1.9
MAG_SI_YY_[15:8]
Table 292. MAG_SI_YY_H register description
Soft-iron correction row2 col2 coefficient (MSbyte). Default value: 00111100
MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 293. MAG_SI_YZ_L register
MAG_SI_YZ_7 MAG_SI_YZ_6 MAG_SI_YZ_5 MAG_SI_YZ_4 MAG_SI_YZ_3 MAG_SI_YZ_2 MAG_SI_YZ_1 MAG_SI_YZ_0
MAG_SI_YZ_[7:0]
Table 294. MAG_SI_YZ_L register description
Soft-iron correction row2 col3 (and row3 col2) coefficient (LSbyte).
Default value: 00000000
Table 295. MAG_SI_YZ_H register
MAG_SI_YZ_15 MAG_SI_YZ_14 MAG_SI_YZ_13 MAG_SI_YZ_12 MAG_SI_YZ_11 MAG_SI_YZ_10 MAG_SI_YZ_9 MAG_SI_YZ_8
MAG_SI_YZ_[15:8]
Table 296. MAG_SI_YZ_H register description
Soft-iron correction row2 col3 (and row3 col2) coefficient (MSbyte).
Default value: 00000000
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13.1.10
MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
Table 297. MAG_SI_ZZ_L register
MAG_SI_ZZ_7 MAG_SI_ZZ_6 MAG_SI_ZZ_5 MAG_SI_ZZ_4 MAG_SI_ZZ_3 MAG_SI_ZZ_2 MAG_SI_ZZ_1 MAG_SI_ZZ_0
MAG_SI_ZZ_[7:0]
Table 298. MAG_SI_ZZ_L register description
Soft-iron correction row3 col3 coefficient (LSbyte). Default value: 00000000
MAG_SI_ZZ_15 MAG_SI_ZZ_14
Table 299. MAG_SI_ZZ_H register
MAG_SI_ZZ_13 MAG_SI_ZZ_12 MAG_SI_ZZ_11 MAG_SI_ZZ_10 MAG_SI_ZZ_9 MAG_SI_ZZ_8
MAG_SI_ZZ_[15:8]
Table 300. MAG_SI_ZZ_H register description
Soft-iron correction row3 col3 coefficient (MSbyte). Default value: 00111100
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13.1.11
13.1.12
MAG_CFG_A (D4h)
External magnetometer coordinates (Y and Z axes) rotation register (r/w)
Table 301. MAG_CFG_A register
0
MAG_Y_
AXIS2
MAG_Y_
AXIS1
MAG_Y_
AXIS0
1. This bit must be set to ‘0’ for the correct operation of the device.
0
MAG_Z_
AXIS2
MAG_Z_
AXIS1
MAG_Z_
AXIS0
Table 302. MAG_CFG_A description
MAG_Y_AXIS[2:0]
MAG_Z_AXIS[2:0]
Magnetometer Y-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation)
(000: Y = Y; (default)
001: Y = -Y;
010: Y = X;
011: Y = -X;
100: Y = -Z;
101: Y = Z;
Others: Y = Y)
Magnetometer Z-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation)
(000: Z = Y;
001: Z = -Y;
010: Z = X;
011: Z = -X;
100: Z = -Z;
101: Z = Z; (default)
Others: Z = Y)
MAG_CFG_B (D5h)
External magnetometer coordinates (X-axis) rotation register (r/w).
0
0
0
Table 303. MAG_CFG_B register
0
0
MAG_X_
AXIS2
1. This bit must be set to ‘0’ for the correct operation of the device.
MAG_X_
AXIS1
MAG_X_
AXIS0
Table 304. MAG_CFG_B description
MAG_X_AXIS[2:0]
Magnetometer X-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation)
(000: X = Y;
001: X = -Y;
010: X = X; (default)
011: X = -X;
100: X = -Z;
101: X = Z;
Others: X = Y)
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13.2
13.2.1
Page 1 - Embedded advanced features registers
FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh)
FSM long counter timeout register (r/w)
The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reaches this value, the FSM generates an interrupt.
FSM_LC_
TIMEOUT7
FSM_LC_
TIMEOUT6
Table 305. FSM_LC_TIMEOUT_L register
FSM_LC_
TIMEOUT5
FSM_LC_
TIMEOUT4
FSM_LC_
TIMEOUT3
FSM_LC_
TIMEOUT2
FSM_LC_
TIMEOUT1
FSM_LC_
TIMEOUT0
FSM_LC_TIMEOUT[7:0]
Table 306. FSM_LC_TIMEOUT_L register description
FSM long counter timeout value (LSbyte). Default value: 00000000
FSM_LC_
TIMEOUT15
FSM_LC_
TIMEOUT14
Table 307. FSM_LC_TIMEOUT_H register
FSM_LC_
TIMEOUT13
FSM_LC_
TIMEOUT12
FSM_LC_
TIMEOUT11
FSM_LC_
TIMEOUT10
FSM_LC_
TIMEOUT9
FSM_LC_
TIMEOUT8
13.2.2
FSM_LC_TIMEOUT[15:8]
Table 308. FSM_LC_TIMEOUT_H register description
FSM long counter timeout value (MSbyte). Default value: 00000000
FSM_PROGRAMS (7Ch)
FSM number of programs register (r/w)
FSM_N_
PROG7
FSM_N_
PROG6
Table 309. FSM_PROGRAMS register
FSM_N_
PROG5
FSM_N_
PROG4
FSM_N_
PROG3
FSM_N_
PROG2
FSM_N_
PROG1
FSM_N_
PROG0
FSM_N_PROG[7:0]
Table 310. FSM_PROGRAMS register description
Number of FSM programs; must be less than or equal to 16.
Default value: 00000000
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13.2.3
FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh)
FSM start address register (r/w). First available address is 0x033C.
FSM_
START7
FSM_
START6
Table 311. FSM_START_ADD_L register
FSM_
START5
FSM_
START4
FSM_
START3
FSM_
START2
FSM_
START1
FSM_
START0
FSM_START[7:0]
Table 312. FSM_START_ADD_L register description
FSM start address value (LSbyte). Default value: 00000000
FSM_
START15
FSM_
START14
Table 313. FSM_START_ADD_H register
FSM_
START13
FSM_
START12
FSM_
START11
FSM_
START10
FSM_
START9
FSM_
START8
13.2.4
FSM_START[15:8]
Table 314. FSM_START_ADD_H register description
FSM start address value (MSbyte). Default value: 00000000
PEDO_CMD_REG (83h)
Pedometer configuration register (r/w)
0
0
0
Table 315. PEDO_CMD_REG register
0
CARRY_
COUNT_EN
FP_
REJECTION_
EN
1. This bit must be set to '0' for the correct operation of the device.
0
AD_
DET_EN
Table 316. PEDO_CMD_REG register description
CARRY_COUNT_EN
FP_REJECTION_EN
Set when user wants to generate interrupt only on count overflow event.
Enables the false-positive rejection feature.
Enables the advanced detection feature.
1. This bit is effective if the PEDO_ADV_EN bit of
is set to 1.
2. This bit is effective if both the FP_REJECTION_EN bit in
PEDO_CMD_REG (83h) register and the PEDO_ADV_EN bit of
are set to 1.
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13.2.5
PEDO_DEB_STEPS_CONF (84h)
Pedometer debounce configuration register (r/w)
DEB_
STEP7
DEB_
STEP6
Table 317. PEDO_DEB_STEPS_CONF register
DEB_
STEP5
DEB_
STEP4
DEB_
STEP3
DEB_
STEP2
DEB_
STEP1
DEB_
STEP0
13.2.6
DEB_STEP[7:0]
Table 318. PEDO_DEB_STEPS_CONF register description
Debounce threshold. Minimum number of steps to increment the step counter (debounce).
Default value: 00001010
PEDO_SC_DELTAT_L (D0h) & PEDO_SC_DELTAT_H (D1h)
Time period register for step detection on delta time (r/w)
PD_SC_7 PD_SC_6
Table 319. PEDO_SC_DELTAT_L register
PD_SC_5 PD_SC_4 PD_SC_3 PD_SC_2 PD_SC_1 PD_SC_0
PD_SC_15 PD_SC_14
Table 320. PEDO_SC_DELTAT_H register
PD_SC_13 PD_SC_12 PD_SC_11 PD_SC_10 PD_SC_9 PD_SC_8
PD_SC_[15:0]
Table 321. PEDO_SC_DELTAT_H/L register description
Time period value (1LSB = 6.4 ms)
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14
LSM6DSO
Sensor hub register mapping
Sensor hub register mapping
Name
SENSOR_HUB_1
SENSOR_HUB_2
SENSOR_HUB_3
SENSOR_HUB_4
SENSOR_HUB_5
SENSOR_HUB_6
SENSOR_HUB_7
SENSOR_HUB_8
SENSOR_HUB_9
SENSOR_HUB_10
SENSOR_HUB_11
SENSOR_HUB_12
SENSOR_HUB_13
SENSOR_HUB_14
SENSOR_HUB_15
SENSOR_HUB_16
SENSOR_HUB_17
SENSOR_HUB_18
MASTER_CONFIG
SLV0_ADD
SLV0_SUBADD
SLV0_CONFIG
SLV1_ADD
SLV1_SUBADD
SLV1_CONFIG
SLV2_ADD
SLV2_SUBADD
SLV2_CONFIG
SLV3_ADD
SLV3_SUBADD
SLV3_CONFIG
DATAWRITE_SLV0
STATUS_MASTER
The table given below provides a list of the registers for the sensor hub functions available in the device and the corresponding addresses. The sensor hub registers are accessible when bit SHUB_REG_ACCESS is set to '1' in
rw rw rw rw rw r r rw r r r r r r r r r r r r r r r r rw rw rw rw rw rw rw rw r
Table 322. Register address map - sensor hub registers
Type
1D
1E
1F
1A
1B
1C
20
21
22
15
16
17
18
19
12
13
14
0F
10
11
0A
0B
0C
07
08
09
0D
0E
Hex
Register address
Binary
02
03
04
05
06
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
0001 0111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
Default output output output output output
00000000
00000000
00000000
00000000
00000000
00000000 output output output output output output output output output output output output output
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000 output
Comment
DS12140 - Rev 2 page 136/172
LSM6DSO
Sensor hub register mapping
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS12140 - Rev 2 page 137/172
LSM6DSO
Sensor hub register description
15
Sensor hub register description
15.1
15.2
15.3
SENSOR_HUB_1 (02h)
Sensor hub output register (r)
First byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub1_7
Sensor
Hub1_6
Table 323. SENSOR_HUB_1 register
Sensor
Hub1_5
Sensor
Hub1_4
Sensor
Hub1_3
Sensor
Hub1_2
Sensor
Hub1_1
Sensor
Hub1_0
SensorHub1[7:0]
Table 324. SENSOR_HUB_1 register description
First byte associated to external sensors
SENSOR_HUB_2 (03h)
Sensor hub output register (r)
Second byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub2_7
Sensor
Hub2_6
Table 325. SENSOR_HUB_2 register
Sensor
Hub2_5
Sensor
Hub2_4
Sensor
Hub2_3
Sensor
Hub2_2
Sensor
Hub2_1
Sensor
Hub2_0
SensorHub2[7:0]
Table 326. SENSOR_HUB_2 register description
Second byte associated to external sensors
SENSOR_HUB_3 (04h)
Sensor hub output register (r)
Third byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub3_7
Sensor
Hub3_6
Table 327. SENSOR_HUB_3 register
Sensor
Hub3_5
Sensor
Hub3_4
Sensor
Hub3_3
Sensor
Hub3_2
Sensor
Hub3_1
Sensor
Hub3_0
SensorHub3[7:0]
Table 328. SENSOR_HUB_3 register description
Third byte associated to external sensors
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SENSOR_HUB_4 (05h)
15.4
15.5
15.6
SENSOR_HUB_4 (05h)
Sensor hub output register (r)
Fourth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub4_7
Sensor
Hub4_6
Table 329. SENSOR_HUB_4 register
Sensor
Hub4_5
Sensor
Hub4_4
Sensor
Hub4_3
Sensor
Hub4_2
Sensor
Hub4_1
Sensor
Hub4_0
SensorHub4[7:0]
Table 330. SENSOR_HUB_4 register description
Fourth byte associated to external sensors
SENSOR_HUB_5 (06h)
Sensor hub output register (r)
Fifth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub5_7
Sensor
Hub5_6
Table 331. SENSOR_HUB_5 register
Sensor
Hub5_5
Sensor
Hub5_4
Sensor
Hub5_3
Sensor
Hub5_2
Sensor
Hub5_1
Sensor
Hub5_0
SensorHub5[7:0]
Table 332. SENSOR_HUB_5 register description
Fifth byte associated to external sensors
SENSOR_HUB_6 (07h)
Sensor hub output register (r)
Sixth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub6_7
Sensor
Hub6_6
Table 333. SENSOR_HUB_6 register
Sensor
Hub6_5
Sensor
Hub6_4
Sensor
Hub6_3
Sensor
Hub6_2
Sensor
Hub6_1
Sensor
Hub6_0
SensorHub6[7:0]
Table 334. SENSOR_HUB_6 register description
Sixth byte associated to external sensors
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LSM6DSO
SENSOR_HUB_7 (08h)
15.7
15.8
15.9
SENSOR_HUB_7 (08h)
Sensor hub output register (r)
Seventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub7_7
Sensor
Hub7_6
Table 335. SENSOR_HUB_7 register
Sensor
Hub7_5
Sensor
Hub7_4
Sensor
Hub7_3
Sensor
Hub7_2
Sensor
Hub7_1
Sensor
Hub7_0
SensorHub7[7:0]
Table 336. SENSOR_HUB_7 register description
Seventh byte associated to external sensors
SENSOR_HUB_8 (09h)
Sensor hub output register (r)
Eighth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub8_7
Sensor
Hub8_6
Table 337. SENSOR_HUB_8 register
Sensor
Hub8_5
Sensor
Hub8_4
Sensor
Hub8_3
Sensor
Hub8_2
Sensor
Hub8_1
Sensor
Hub8_0
SensorHub8[7:0]
Table 338. SENSOR_HUB_8 register description
Eighth byte associated to external sensors
SENSOR_HUB_9 (0Ah)
Sensor hub output register (r)
Ninth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub9_7
Sensor
Hub9_6
Table 339. SENSOR_HUB_9 register
Sensor
Hub9_5
Sensor
Hub9_4
Sensor
Hub9_3
Sensor
Hub9_2
Sensor
Hub9_1
Sensor
Hub9_0
SensorHub9[7:0]
Table 340. SENSOR_HUB_9 register description
Ninth byte associated to external sensors
DS12140 - Rev 2 page 140/172
LSM6DSO
SENSOR_HUB_10 (0Bh)
15.10
SENSOR_HUB_10 (0Bh)
Sensor hub output register (r)
Tenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub10_7
Sensor
Hub10_6
Table 341. SENSOR_HUB_10 register
Sensor
Hub10_5
Sensor
Hub10_4
Sensor
Hub10_3
Sensor
Hub10_2
Sensor
Hub10_1
Sensor
Hub10_0
15.11
SensorHub10[7:0]
Table 342. SENSOR_HUB_10 register description
Tenth byte associated to external sensors
SENSOR_HUB_11 (0Ch)
Sensor hub output register (r)
Eleventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub11_7
Sensor
Hub11_6
Table 343. SENSOR_HUB_11 register
Sensor
Hub11_5
Sensor
Hub11_4
Sensor
Hub11_3
Sensor
Hub11_2
Sensor
Hub11_1
Sensor
Hub11_0
15.12
SensorHub11[7:0]
Table 344. SENSOR_HUB_11 register description
Eleventh byte associated to external sensors
SENSOR_HUB_12 (0Dh)
Sensor hub output register (r)
Twelfth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub12_7
Sensor
Hub12_6
Table 345. SENSOR_HUB_12 register
Sensor
Hub12_5
Sensor
Hub12_4
Sensor
Hub12_3
Sensor
Hub12_2
Sensor
Hub12_1
Sensor
Hub12_0
SensorHub12[7:0]
Table 346. SENSOR_HUB_12 register description
Twelfth byte associated to external sensors
DS12140 - Rev 2 page 141/172
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SENSOR_HUB_13 (0Eh)
15.13
SENSOR_HUB_13 (0Eh)
Sensor hub output register (r)
Thirteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub13_7
Sensor
Hub13_6
Table 347. SENSOR_HUB_13 register
Sensor
Hub13_5
Sensor
Hub13_4
Sensor
Hub13_3
Sensor
Hub13_2
Sensor
Hub13_1
Sensor
Hub13_0
15.14
SensorHub13[7:0]
Table 348. SENSOR_HUB_13 register description
Thirteenth byte associated to external sensors
SENSOR_HUB_14 (0Fh)
Sensor hub output register (r)
Fourteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub14_7
Sensor
Hub14_6
Table 349. SENSOR_HUB_14 register
Sensor
Hub14_5
Sensor
Hub14_4
Sensor
Hub14_3
Sensor
Hub14_2
Sensor
Hub14_1
Sensor
Hub14_0
15.15
SensorHub14[7:0]
Table 350. SENSOR_HUB_14 register description
Fourteenth byte associated to external sensors
SENSOR_HUB_15 (10h)
Sensor hub output register (r)
Fifteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub15_7
Sensor
Hub15_6
Table 351. SENSOR_HUB_15 register
Sensor
Hub15_5
Sensor
Hub15_4
Sensor
Hub15_3
Sensor
Hub15_2
Sensor
Hub15_1
Sensor
Hub15_0
SensorHub15[7:0]
Table 352. SENSOR_HUB_15 register description
Fifteenth byte associated to external sensors
DS12140 - Rev 2 page 142/172
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SENSOR_HUB_16 (11h)
15.16
SENSOR_HUB_16 (11h)
Sensor hub output register (r)
Sixteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub16_7
Sensor
Hub16_6
Table 353. SENSOR_HUB_16 register
Sensor
Hub16_5
Sensor
Hub16_4
Sensor
Hub16_3
Sensor
Hub16_2
Sensor
Hub16_1
Sensor
Hub16_0
15.17
SensorHub16[7:0]
Table 354. SENSOR_HUB_16 register description
Sixteenth byte associated to external sensors
SENSOR_HUB_17 (12h)
Sensor hub output register (r)
Seventeenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub17_7
Sensor
Hub17_6
Table 355. SENSOR_HUB_17 register
Sensor
Hub17_5
Sensor
Hub17_4
Sensor
Hub17_3
Sensor
Hub17_2
Sensor
Hub17_1
Sensor
Hub17_7
15.18
SensorHub17[7:0]
Table 356. SENSOR_HUB_17 register description
Seventeenth byte associated to external sensors
SENSOR_HUB_18 (13h)
Sensor hub output register (r)
Eighteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub18_7
Sensor
Hub18_6
Table 357. SENSOR_HUB_17 register
Sensor
Hub18_5
Sensor
Hub18_4
Sensor
Hub18_3
Sensor
Hub18_2
Sensor
Hub18_1
Sensor
Hub18_0
SensorHub18[7:0]
Table 358. SENSOR_HUB_17 register description
Eighteenth byte associated to external sensors
DS12140 - Rev 2 page 143/172
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MASTER_CONFIG (14h)
15.19
MASTER_CONFIG (14h)
Master configuration register (r/w)
RST_MASTER
_REGS
WRITE_
ONCE
Table 359. MASTER_CONFIG register
START_
CONFIG
PASS_
THROUGH
_MODE
SHUB_
PU_EN
MASTER_ON
AUX_
SENS_ON1
AUX_
SENS_ON0
15.20
RST_MASTER_REGS
WRITE_ONCE
START_CONFIG
PASS_THROUGH_MODE
SHUB_PU_EN
MASTER_ON
AUX_SENS_ON[1:0]
Table 360. MASTER_CONFIG register description
Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. Default value: 0
Slave 0 write operation is performed only at the first sensor hub cycle. Default value: 0
(0: write operation for each sensor hub cycle;
1: write operation only for the first sensor hub cycle)
Sensor hub trigger signal selection. Default value: 0
(0: sensor hub trigger signal is the accelerometer/gyro data-ready;
1: sensor hub trigger signal external from INT2 pin)
I²C interface pass-through. Default value: 0
(0: pass-through disabled;
1: pass-through enabled, main I²C line is short-circuited with the auxiliary line)
Master I²C pull-up enable. Default value: 0
(0: internal pull-up on auxiliary I²C line disabled;
1: internal pull-up on auxiliary I²C line enabled)
Sensor hub I²C master enable. Default: 0
(0: master I²C of sensor hub disabled; 1: master I²C of sensor hub enabled)
Number of external sensors to be read by the sensor hub.
(00: one sensor (default);
01: two sensors;
10: three sensors;
11: four sensors)
SLV0_ADD (15h)
I²C slave address of the first external sensor (Sensor 1) register (r/w).
slave0_ add6 slave0_ add5 slave0_ add4
Table 361. SLV0_ADD register slave0_ add3 slave0_ add2 slave0_ add1 slave0_ add0 rw_0 slave0_add[6:0] rw_0
Table 362. SLV_ADD register description
I²C slave address of Sensor1 that can be read by the sensor hub.
Default value: 0000000
Read/write operation on Sensor 1. Default value: 0
(0: write operation; 1: read operation)
DS12140 - Rev 2 page 144/172
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SLV0_SUBADD (16h)
15.21
SLV0_SUBADD (16h)
Address of register on the first external sensor (Sensor 1) register (r/w) slave0_ reg7 slave0_ reg6 slave0_ reg5
Table 363. SLV0_SUBADD register slave0_ reg4 slave0_ reg3 slave0_ reg2 slave0_ reg1 slave0_ reg0
15.22
15.23
Table 364. SLV0_SUBADD register description slave0_reg[7:0]
Address of register on Sensor1 that has to be read/written according to the rw_0 bit value in
(15h) . Default value: 00000000
SLAVE0_CONFIG (17h)
First external sensor (Sensor1) configuration and sensor hub settings register (r/w)
Table 365. SLAVE0_CONFIG register
SHUB_
ODR_1
SHUB_
ODR_0
0
0
BATCH_EXT
_SENS_0_EN
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave0_ numop2
Slave0_ numop1
Slave0_ numop0
Table 366. SLAVE0_CONFIG register description
SHUB_ODR_[1:0]
Rate at which the master communicates. Default value: 00
(00: 104 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 104 Hz);
01: 52 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 52 Hz);
10: 26 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 26 Hz);
11: 12.5 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 12.5 Hz)
BATCH_EXT_
SENS_0_EN
Enable FIFO batching data of first slave. Default value: 0
Slave0_numop[2:0] Number of read operations on Sensor 1. Default value: 000
SLV1_ADD (18h)
I²C slave address of the second external sensor (Sensor 2) register (r/w)
Slave1_ add6
Slave1_ add5
Slave1_ add4
Table 367. SLV1_ADD register
Slave1_ add3
Slave1_ add2
Slave1_ add1
Slave1_ add0 r_1
Slave1_add[6:0] r_1
Table 368. SLV1_ADD register description
I²C slave address of Sensor 2 that can be read by the sensor hub.
Default value: 0000000
Read operation on Sensor 2 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
DS12140 - Rev 2 page 145/172
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SLV1_SUBADD (19h)
15.24
SLV1_SUBADD (19h)
Address of register on the second external sensor (Sensor 2) register (r/w)
Slave1_ reg7
Slave1_ reg6
Slave1_ reg5
Table 369. SLV1_SUBADD register
Slave1_ reg4
Slave1_ reg3
Slave1_ reg2
Slave1_ reg1
Slave1_ reg0
15.25
15.26
Table 370. SLV1_SUBADD register description
Slave1_reg[7:0]
SLAVE1_CONFIG (1Ah)
Second external sensor (Sensor 2) configuration register (r/w)
Table 371. SLAVE1_CONFIG register
0
0
0
0
BATCH_EXT_
SENS_1_EN
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave1_ numop2
Slave1_ numop1
Slave1_ numop0
BATCH_EXT_SENS_1_EN
Slave1_numop[2:0]
Table 372. SLAVE1_CONFIG register description
Enable FIFO batching data of second slave. Default value: 0
Number of read operations on Sensor 2. Default value: 000
SLV2_ADD (1Bh)
I²C slave address of the third external sensor (Sensor 3) register (r/w)
Slave2_ add6
Slave2_ add5
Slave2_ add4
Table 373. SLV2_ADD register
Slave2_ add3
Slave2_ add2
Slave2_ add1
Slave2_ add0 r_2
Slave2_add[6:0] r_2
Table 374. SLV2_ADD register description
I²C slave address of Sensor 3 that can be read by the sensor hub.
Read operation on Sensor 3 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
DS12140 - Rev 2 page 146/172
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SLV2_SUBADD (1Ch)
15.27
SLV2_SUBADD (1Ch)
Address of register on the third external sensor (Sensor 3) register (r/w)
Slave2_ reg7
Slave2_ reg6
Slave2_ reg5
Table 375. SLV2_SUBADD register
Slave2_ reg4
Slave2_ reg3
Slave2_ reg2
Slave2_ reg1
Slave2_ reg0
15.28
15.29
Table 376. SLV2_SUBADD register description
Slave2_reg[7:0]
.
SLAVE2_CONFIG (1Dh)
Third external sensor (Sensor 3) configuration register (r/w)
0
0
0
Table 377. SLAVE2_CONFIG register
0
BATCH_EXT
_SENS_2_EN
Slave2_ numop2
1. This bit must be set to ‘0’ for the correct operation of the device.
BATCH_EXT_SENS_2_EN
Slave2_numop[2:0]
Table 378. SLAVE2_CONFIG register description
Enable FIFO batching data of third slave. Default value: 0
Number of read operations on Sensor 3. Default value: 000
SLV3_ADD (1Eh)
I²C slave address of the fourth external sensor (Sensor 4) register (r/w)
Slave3_ add6
Slave3_ add5
Slave3_ add4
Table 379. SLV3_ADD register
Slave3_ add3
Slave3_ add2
Slave3_ add1
Slave2_ numop1
Slave3_ add0
Slave2_ numop0 r_3
Slave3_add[6:0] r_3
Table 380. SLV3_ADD register description
I²C slave address of Sensor 4 that can be read by the sensor hub.
Read operation on Sensor 4 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
DS12140 - Rev 2 page 147/172
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SLV3_SUBADD (1Fh)
15.30
SLV3_SUBADD (1Fh)
Address of register on the fourth external sensor (Sensor 4) register (r/w)
Slave3_ reg7
Slave3_ reg6
Slave3_ reg5
Table 381. SLV3_SUBADD register
Slave3_ reg4
Slave3_ reg3
Slave3_ reg2
Slave3_ reg1
Slave3_ reg0
15.31
15.32
Table 382. SLV3_SUBADD register description
Slave3_reg[7:0] Address of register on Sensor 4 that has to be read according to the r_3 bit value in
SLAVE3_CONFIG (20h)
Fourth external sensor (Sensor 4) configuration register (r/w)
Table 383. SLAVE3_CONFIG register
0
0
0
0
BATCH_EXT
_SENS_3_EN
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave3_ numop2
BATCH_EXT_SENS_3_EN
Slave3_numop[2:0]
Table 384. SLAVE3_CONFIG register description
Enable FIFO batching data of fourth slave. Default value: 0
Number of read operations on Sensor 4. Default value: 000
DATAWRITE_SLV0 (21h)
Data to be written into the slave device register (r/w)
Slave0_ dataw7
Slave0_ dataw6
Table 385. DATAWRITE_SLV0 register
Slave0_ dataw5
Slave0_ dataw4
Slave0_ dataw3
Slave0_ dataw2
Slave3_ numop1
Slave0_ dataw1
Slave3_ numop0
Slave0_ dataw0
Slave0_dataw[7:0]
Table 386. DATAWRITE_SLV0 register description
Data to be written into the slave 0 device according to the rw_0 bit in register SLV0_ADD (15h)
.
Default value: 00000000
DS12140 - Rev 2 page 148/172
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STATUS_MASTER (22h)
15.33
STATUS_MASTER (22h)
Sensor hub source register (r)
WR_ONCE_
DONE
SLAVE3_
NACK
Table 387. STATUS_MASTER register
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK
0 0
SENS_HUB
_ENDOP
Table 388. STATUS_MASTER register description
WR_ONCE_DONE
SLAVE3_NACK
SLAVE2_NACK
SLAVE1_NACK
When the bit WRITE_ONCE in
is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
SENS_HUB_ENDOP
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded;
1: sensor hub communication concluded)
DS12140 - Rev 2 page 149/172
16
Soldering information
The LGA package is compliant with the ECOPACK ® , RoHS and "Green" standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Land pattern and soldering recommendations are available at www.st.com/mems.
LSM6DSO
Soldering information
DS12140 - Rev 2 page 150/172
LSM6DSO
Package information
17
17.1
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
LGA-14L package information
Figure 25. LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data
Pin1 indicator
W H 0.5
Pin1 indicator
4x (0.1)
TOP VIEW
14x 0.25±0.05
1
BOTTOM VIEW
14x 0.475±0.05
ITEM
L e n g t
W i d t h h [
[ L ]
W ]
H e i g h t [ H ]
Dimensions are in millimeter unless otherwise specified
General tolerance is +/-0.1mm unless otherwise specified
OUTER DIMENSIONS
DIMENSION [mm]
2 .
3 .
0 .
5
0
8
0
0
6
TOLERANCE [mm]
±
±
M
0
0
A
.
.
1
1
X
DM00249496_1
DS12140 - Rev 2 page 151/172
17.2
LGA-14 packing information
Figure 26. Carrier tape information for LGA-14 package
LSM6DSO
LGA-14 packing information
Figure 27. LGA-14 package orientation in carrier tape
DS12140 - Rev 2 page 152/172
DS12140 - Rev 2
LSM6DSO
LGA-14 packing information
A
Figure 28. Reel information for carrier tape of LGA-14 package
T
40mm min.
Access hole at slot location
B
C
D N
Full radius
G measured at hub
Tape slot in core for tape start
2.5mm min. width
Table 389. Reel dimensions for carrier tape of LGA-14 package
Reel dimensions (mm)
A (max)
B (min)
C
D (min)
N (min)
G
T (max)
330
1.5
13 ±0.25
20.2
60
12.4 +2/-0
18.4
page 153/172
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Revision history
Date
22-Aug-2018
25-Jan-2019
Revision
1
2
Table 390. Document revision history
Changes
Initial release
Added product label indicating ST's commitment to sustainable technology
Updated LA_TyOff in
Table 2. Mechanical characteristics
Updated footnotes in Table 4. Temperature sensor characteristics
Updated
Table 60. Gyroscope LPF1 bandwidth selection
Updated
Textual update in MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh)
DS12140 - Rev 2 page 154/172
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Contents
Contents
DS12140 - Rev 2 page 155/172
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Contents
DS12140 - Rev 2 page 156/172
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Contents
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 72
DS12140 - Rev 2 page 157/172
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Contents
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) . . . . . . . . . . . . . . . . . . . . . 88
FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) . . . . . . . . . . . . . . . . . . . . . 88
FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) . . . . . . . . . . . . . . . . . . . . . 88
DS12140 - Rev 2 page 158/172
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Contents
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) . . . . . . . . . . . . . . 104
DS12140 - Rev 2 page 159/172
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Contents
STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) . . . . . . . . . . . . . . . . . . . . . . . . .121
MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh) . . . . . . . . . . . . . . . . . . 126
FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh). . . . . . . . . . . . . . . . . . . 133
FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) . . . . . . . . . . . . . . . . . . . . 134
PEDO_SC_DELTAT_L (D0h) & PEDO_SC_DELTAT_H (D1h) . . . . . . . . . . . . . . . . . . . . 135
DS12140 - Rev 2 page 160/172
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Contents
DS12140 - Rev 2 page 161/172
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Contents
DS12140 - Rev 2 page 162/172
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List of tables
List of tables
DS12140 - Rev 2 page 163/172
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List of tables
DS12140 - Rev 2 page 164/172
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List of tables
DS12140 - Rev 2 page 165/172
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List of tables
DS12140 - Rev 2 page 166/172
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List of tables
DS12140 - Rev 2 page 167/172
LSM6DSO
List of tables
DS12140 - Rev 2 page 168/172
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List of tables
DS12140 - Rev 2 page 169/172
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List of tables
DS12140 - Rev 2 page 170/172
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List of figures
List of figures
DS12140 - Rev 2 page 171/172
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS12140 - Rev 2 page 172/172
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