STMicroelectronics STM32MP153A Datasheet

Table 13: General operating conditions .

0.30

<1.2

361

Dual-core Cortex-A7 FPU Neon TrustZone

2 × 32-Kbyte L1 data cache

2 × 32-Kbyte L1 instruction cache

18x18

0.8

0.40

<1.4

448

256-Kbyte level 2 unified coherent cache

STM32MP153A: 2 × 650 MHz

STM32MP153D: 2 × 800 MHz

Cortex-M4 FPU

209 MHz

128 Kbytes (secure)

256 Kbytes (securable)

384 Kbytes

64 Kbytes

4 Kbytes (securable, tamper protected)

Up to 1 Gbyte, single rank

128 bytes (32x32-bit, securable, tamper protected)

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STM32MP153A/D

Table 1. STM32MP153A/D features and peripheral counts (continued)

Description

Features

TFBGA257 LFBGA354 TFBGA361 LFBGA448

Advanced 16 bits

General purpose

16 bits

32 bits

Basic 16 bits

Low power 16 bits

A7 timers 64 bits

SysTick

24 bits

RTC/AWU

Watchdog

SPI

Having I2S

I2C (with SMB/PMB support)

USART (smartcard, SPI, IrDA, LIN)

+ UART (IrDA, LIN)

SAI

EHCI/OHCI Host

2 × 4 (secure, non-secure, virtual, hypervisor)

1 (securable)

3 (independent, independent secure, window)

6 (1 securable)

6 (2 securable)

4 + 4 (including 1 securable USART) some can be a boot source

4 (up to 8 audio channels), with I2S master/slave, PCM input,

SPDIF-TX

2 ports

Embedded HS PHY with BCD

Boot

USB

OTG HS/FS

(dual role port)

Embedded PHYs

Yes, embedded FS or HS PHY with BCD, can be a boot source Boot

SPDIF-RX

FDCAN

HDMI-CEC

Including the following securable

SDMMC (SD, SDIO,

QuadSPI e •MMC)

3 (2 × high-speed + 1 × full-speed)

4 inputs

2 (1 × TTCAN), clock calibration, 10 Kbyte shared buffer

1 × USART, 1 × SPI, 2 × I2C

1 × USART, 1 × SPI, 2 × I2C on securable GPIOs

3 (8 + 8 + 4 bits), e •MMC or SD can be a boot source

Yes (dual-quad), can be a boot source

Boot

DS12502 Rev 6 17/256

Description STM32MP153A/D

Table 1. STM32MP153A/D features and peripheral counts (continued)

Features

TFBGA257 LFBGA354 TFBGA361 LFBGA448

FMC

Parallel address/data 8/16-bit

Parallel AD-Mux 8/16-bit

NAND 8/16-bit

Gigabit Ethernet

10/100M Ethernet

LCD-TFT

DMA

Hash

Parallel interface

True random number generator

Fuses (one-time programmable)

Camera interface Bus width

GPIOs with interrupt (total count)

Securable GPIOs

Wakeup pins

Tamper pins (active tamper)

DFSDM

Up to 16-bit synchronized ADC

Low noise 16 bit (differential)

16 bit (differential)

ADC channels in total (2)

12-bit DAC

Internal ADC/DAC VREF

VREF+ input pin

4 × CS, up to 4 × 64 Mbyte

4 × CS, up to 4 × 64 Mbytes

Yes, 1 × CS, SLC, BCH4/8, can be a boot source

MII, RMII with PTP and EEE

MII, RMII, GMII, RGMII with

PTP and EEE

Up to 24-bit data, up to 90 MHz pixel clock

(up to 1366 × 768 60 fps or up to 1920 × 1080 30 fps)

3 instances (1 securable), 48 physical channels in total

SHA-256, MD5, HMAC dual instances (secure and non-secure)

True-RNG, dual instances (secure and non-secure)

3072 effective bits (secure, >1500 bits available for user)

14-bit

98 148 176

2 (1)

17 (7)

Yes

3 (1)

8 input channels with 6 filters

2 (up to 3.6/4/4.5/5/6 Msps on 16/14/12/10/8-bit each)

2 (1)

20 (9)

1.5 V, 1.8 V, 2.048 V, 2.5 V or VREF+ input

No boot

Boot

1. With inner matrix balls having 0.65 mm pitch to allow optimized PCB routing for supplies.

2. In addition, there is also 6 internal channels for temperature, internal voltage reference, V acquisitions.

DDCORE

, V

BAT

/4, DAC1 or DAC2

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STM32MP153A/D Description

Figure 1. STM32MP153A/D block diagram

ETM

CNT (Timer)

Cortex-A7 CPU

650/800

(1)

MHz + MMU +

FPU + NEON

32K D$

32K I$

GIC T

Cortex-A7 CPU

650/800

(1)

MHz + MMU +

FPU + NEON

32K D$

32K I$

CNT (Timer)

ETM

(R)(G)MII

10/100/1000

DDRCTRL

LPDDR2/3

DDR3/3L

QUADSPI (dual)

16b

FMC

SDMMC1

SDMMC2

24b

16b

USBH

(2 x HS Host)

PLLUSB

LTDC

(LCD)

GPIOZ

Trace port

Smartcard

IrDA

I2C4 / SMBUS

I2C6 / SMBUS

SPI6

USART1

ETZPC

IWDG1

BSEC

OTP Fuses

RTC / AWU

TAMP / Backup Regs

LSE (32kHz XTAL)

Sys. Timing

GENeration

STGENC

STGENR

IC Supplies

128 bits async

AHB2APB

32 bits

@VDD_ANA

CSI debug TimeStamp

GENerator TSGEN

DAP

(JTAG / SWD)

SYSRAM 256KB

ROM 128KB

BKPSRAM 4KB

RNG1

HASH1

DLYBQS

(QUADSPI DLY control)

CRC1

DLYBSD1

(SDMMC1 DLY control)

DLYBSD2

(SDMMC2 DLY control)

MDMA

32 Channels

STM

Cortex-M4 CPU 209 MHz

+ MPU + FPU

NVIC

SYSTICK

SRAM1 128KB

SRAM2 128KB

SRAM3/SRAM4 64K/64K

RETSRAM 64KB

HSEM

IPCC

CRC2

RNG2

HASH2

D-Bus

I-Bus

S-Bus

HSI

LSI

16b

BOOT pins

16b

USBPHYC

(USB 2 x PHY control)

IWDG2

DDRPHYC

DDRPERFM

VREFBUF

LPTIM2

LPTIM3

LPTIM4

LPTIM5

SAI4

SYSCFG

HDP

TIM1 / PWM

TIM8 / PWM

TIM15

TIM16

TIM17

SAI1

SAI2

SAI3

64 bits

1. STM32MP153A: 650 MHz, STM32MP153D: 800 MHz

DTS

(Digital temperature sensor)

Voltage Regulators

Supply Supervision

AXI

AHB

APB

AHB2APB

DMA1

8 Streams

DMAMUX1

DMA2

8 Streams

64bits

@VDD

@VDD_ANA

AXI master

2x2

Matrix

AHB2APB

32 bits

AHB master

TrustZone

security protection

APB2 (104.5 MHz)

@VDD

HSE (XTAL) 2

@VDD_PLL

@VDDA

PLL1/2/3/4

RCC

PWR

16b

EXTI

DCMI

(Camera I/F)

DLYBSD3

(SDMMC3 DLY control)

SDMMC3

OTG

(HS/FS)

ADC1

ADC2

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

GPIOH

GPIOI

16ext

14b

16b

GPIOJ

GPIOK

TIM2

TIM3

TIM4

TIM5

TIM6

16b

32b

16b

32b

16b

TIM7

TIM12

TIM13

TIM14

16b

LPTIM1

MDIOS

16b

USART2 Smartcard

IrDA

USART3 Smartcard

IrDA

UART4

UART5

UART7

UART8

12b

DAC1

DAC2

I2C1 / SMBUS

I2C2 / SMBUS

I2C3 / SMBUS

I2C5 / SMBUS

CEC (HDMI-CEC)

SPDIFRX

SPI2 / I2S2

SPI1 / I2S1

DFSDM1

4ch

SPI3 / I2S3

WWDG1

USART6 Smartcard

IrDA

SPI4

SPI5

8ch

FDCAN1 (TT)

Buffer 10KB

FDCAN2

CCU

MSv47450V4

176

DS12502 Rev 6 19/256

Functional overview

3 Functional overview

3.1

3.1.1

3.1.2

STM32MP153A/D

Dual-core Arm

®

Cortex

®

-A7 subsystem

Features

• ARMv7-A architecture

• 32-Kbyte L1 instruction cache for each CPU

• 32-Kbyte L1 data cache for each CPU

• 256-Kbyte level2 cache

• Arm

+ Thumb

-2 instruction set

• Arm ® TrustZone ® security technology

• Arm

NEON™ Advanced SIMD

• DSP and SIMD extensions

• VFPv4 floating-point

• Hardware virtualization support

• Embedded trace module (ETM)

• Integrated generic interrupt controller (GIC) with 256 shared peripheral interrupts

• Integrated generic timer (CNT)

Overview

The Cortex-A7 processor is a very energy-efficient applications processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20 % more single thread performance than the

Cortex-A5 and provides similar performance than the Cortex-A9.

The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex-

A17 processors, including virtualization support in hardware, NEON ™ , and 128-bit AMBA ® 4

AXI bus interface.

The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5 processor. It also benefits from an integrated L2 cache designed for low-power, with lower transaction latencies and improved OS support for cache maintenance. On top of this, there is improved branch prediction and improved memory system performance, with 64-bit loadstore path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web browsing.

Thumb-2 technology

Delivers the peak performance of traditional Arm ® code while also providing up to a 30 % reduction in memory requirement for instructions storage.

TrustZone technology

Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry partners.

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STM32MP153A/D Functional overview

NEON

NEON technology can accelerate multimedia and signal processing algorithms such as video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis. The Cortex-A7 provides an engine that offers both the performance and functionality of the Cortex-A7 floating-point unit (FPU) and an implementation of the NEON advanced SIMD instruction set for further acceleration of media and signal processing functions. The NEON extends the Cortex-A7 processor FPU to provide a quad-MAC and additional 64-bit and 128-bit register set supporting a rich set of

SIMD operations over 8-, 16- and 32-bit integer and 32-bit floating-point data quantities.

Hardware virtualization

Highly efficient hardware support for data management and arbitration, whereby multiple software environments and their applications are able to simultaneously access the system capabilities. This enables the realization of devices that are robust, with virtual environments that are well isolated from each other.

Optimized L1 caches

Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. There is also the option of cache coherence for enhanced inter-processor communication, or support of a rich SMP capable OS for simplified multicore software development.

Integrated L2 cache controller

Provides low-latency and high-bandwidth access to cached memory in high-frequency, or to reduce the power consumption associated with off-chip memory access.

Cortex-A7 floating-point unit (FPU)

The FPU provides high-performance single and double precision floating-point instructions compatible with the Arm VFPv4 architecture that is software compatible with previous generations of Arm floating-point coprocessor.

Snoop control unit (SCU)

The SCU is responsible for managing the interconnect, arbitration, communication, cache to cache and system memory transfers, cache coherence and other capabilities for the processor.

This system coherence also reduces software complexity involved in maintaining software coherence within each OS driver.

Generic interrupt controller (GIC)

Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritization of system interrupts.

Supporting up to 288 independent interrupts, under software control, each interrupt can be distributed across A7 cores, hardware prioritized, and routed between the operating system and TrustZone software management layer.

DS12502 Rev 6 21/256

Functional overview STM32MP153A/D

This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a hypervisor.

3.2

Note:

Arm

®

Cortex

®

-M4 with FPU

The Arm

Cortex

-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.

Memory protection unit (MPU)

The memory protection unit (MPU) manages the Cortex

-M4 access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions.

The MPU defines access rules for privileged accesses and user program accesses. It allows the definition of up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory.

When an unauthorized access is performed, a memory management exception is generated.

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STM32MP153A/D

3.3

3.3.1

3.3.2

Memories

Functional overview

External SDRAM

The STM32MP153A/D devices embed a controller for external SDRAM which support the following devices

• LPDDR2 or LPDDR3, 16- or 32-bit data, up to 1 Gbyte, up to 533 MHz clock.

• DDR3 or DDR3L, 16- or 32-bit data, up to 1 Gbyte, up to 533 MHz clock.

Embedded SRAM

All devices feature:

• SYSRAM in MPU domain: 256 Kbytes

• SRAM1 in MCU domain: 128 Kbytes

• SRAM2 in MCU domain: 128 Kbytes

• SRAM3 in MCU domain: 64 Kbytes

• SRAM4 in MCU domain: 64 Kbytes

• RETRAM (retention RAM): 64 Kbytes

The content of this area can be retained in Standby or V

BAT mode.

• BKPSRAM (backup SRAM): 4 Kbytes

The content of this area is protected against possible unwanted write accesses, and can be retained in Standby or V

BAT mode.

BKPSRAM can be defined (in ETZPC) as accessible by secure software only.

DS12502 Rev 6 23/256

Functional overview

3.4

STM32MP153A/D

DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL)

DDRCTRL combined with DDRPHYC provides a complete memory interface solution for

DDR memory subsystem.

• Two 64-bit AMBA 4 AXI4 ports interface (XPI)

• AXI clock asynchronous to the controller

• Supported standards:

– JEDEC DDR3 SDRAM specification, JESD79-3E for DDR3/3L with 32-bit interface

– JEDEC LPDDR2 SDRAM specification, JESD209-2E for LPDDR2 with 32-bit interface

– JEDEC LPDDR3 SDRAM specification, JESD209-3B for LPDDR3 with 32-bit interface

• Advanced scheduler and SDRAM command generator

• Programmable full data width (32-bit) or half data width (16-bit)

• Advanced QoS support with 3 traffic class on read and 2 traffic classes on write

• Options to avoid starvation of lower priority traffic

• Guaranteed coherency for write-after-read (WAR) and read-after-write (RAW) on AXI ports

• Programmable support for burst length options (4, 8,16)

• Write combine to allow multiple writes to the same address to be combined into a single write

• Single rank configuration

• Supports automatic SDRAM power-down entry and exit caused by lack of transaction arrival for programmable time

• Supports automatic clock stop (LPDDR2/3) entry and exit caused by lack of transaction arrival

• Supports automatic low power mode operation caused by lack of transaction arrival for programmable time via hardware low power interface

• Programmable paging policy

• Supports automatic or under software control self-refresh entry and exit

• Support for deep power-down entry and exit under software control (LPDDR2)

• Support for explicit SDRAM mode register updates under software control

• Flexible address mapper logic to allow application specific mapping of row, column, bank bits

• User-selectable refresh control options

• DDRPERFM associated block to help for performance monitoring and tuning

DDRCTRL and DDRPHYC can be defined (in ETZPC) as accessible by secure software only.

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STM32MP153A/D

3.5

Functional overview

TrustZone address space controller for DDR (TZC)

TZC is used to filter read/write accesses to DDR controller according to TrustZone rights and according to non-secure master (NSAID) on up to 9 programmable regions.

• Configuration is supported by trusted software only

• 2 filter units working concurrently

• 9 regions:

– region 0 is always enabled and covers the whole address range.

– regions 1 to 8 have programmable base/end address and can be assigned to any one or both filters.

• Secure and non-secure access permissions programmed per region

• Non-secure accesses are filtered according to NSAID

• Regions controlled by same filter must not overlap

• Fail modes with error and/or interrupt

• Acceptance capability = 256

• Gate keeper logic to enable and disable of each filter

• Speculative accesses

DS12502 Rev 6 25/256

Functional overview STM32MP153A/D

3.6 Boot modes

At startup, the boot source used by the internal BootROM is selected by the BOOT pin and

OTP bytes.

BOOT2 BOOT1 BOOT0

Table 2. Boot modes

Initial boot mode Comments

UART and USB

(1)

Serial NOR Flash e •MMC (3)

NAND Flash

(3)

Reserved (NoBoot)

SD card

(3)

UART and USB

(3)

(1)(3)

Wait incoming connection on:

– USART2/3/6 and UART4/5/7/8 on default pins

– USB high-speed device

(2)

Serial NOR Flash on QUADSPI

(4) e •MMC on SDMMC2 (default)

(4)(5)

SLC NAND Flash on FMC

Used to get debug access without boot from Flash memory

SD card on SDMMC1 (default)

(4)(5)

Wait incoming connection on:

– USART2/3/6 and UART4/5/7/8 on default pins

– USB high-speed device on OTG_HS_DP/DM pins

(2)

Serial NAND Flash on QUADSPI

(4)

1 1 1 Serial NAND Flash

(3)

1. can be disabled by OTP settings.

2. USB requires 24 MHz HSE clock/crystal if OTP is not programmed for different frequency.

3. Boot source can be changed by OTP settings (e.g. initial boot on SD card, then e •MMC with OTP settings).

4. Default pins can be altered by OTP.

5. Alternatively, another SDMMC1 or SDMMC2 interface than this default can be selected by OTP.

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STM32MP153A/D Functional overview

3.7 Power supply management

3.7.1 Power supply scheme

• The V

DD is the main supply for I/Os and internal part kept powered during Standby mode. Useful voltage range is 1.71 V to 3.6 V (e.g. 1.8 V, 2.5 V, 3.0 V or 3.3 V typ.)

– V

DD_PLL

and V

DD_ANA

must be star-connected to V

• The V

DDCORE

is the main digital voltage and is usually shutdown during Standby mode.

Voltage range during Run mode is 1.18 V to 1.25/1.38 V (1.2/1.34 V typ.), see

• The VBAT pin can be connected to the external battery (1.2 V < V

BAT external battery is used, it is mandatory to connect this pin to V

< 3.6 V). If no

• The VDDA pin is the analog (ADC/DAC/VREF), supply voltage range is 1.71 V to 3.6 V.

DAC can only be used when V requires V

DDA

DDA is above or equal 1.8 V. Using Internal V

equal to or higher than V

REF+

+ 0.3 V.

REF+

• The VDDA1V8_REG pin is the output of internal regulator and connected internally to

USB PHY and USB PLL. Internal V

DDA1V8_REG regulator is enabled by default and can be controlled by software. It is always shut down during Standby mode.

There is specific BYPASS_REG1V8 pin that must be connected either to V

or V

to activate or deactivate the voltage regulator. It is mandatory to bypass the 1.8 V regulator when V

is below 2.25 V (BYPASS_REG1V8 = V

VDDA1V8_REG pin must be connected to V

1.65 V - 1.98 V supply (1.8 V typ.).

DD)

. In that case,

(if below 1.98 V) or to a dedicated

•

• VDDA1V1_REG pin is the output of internal regulator connected internally to USB PHY.

Internal V

DDA1V1_REG

regulator is enabled by default and can be controlled by software. It is always shut down during Standby mode.

• V

DD3V3_USBHS

and V

DD3V3_USBFS

are respectively the USB high-speed and full-speed

PHY supply. Voltage range is 3.07 V to 3.6 V. V

DD3V3_USBFS

OTG_VBUS and ID pins. So, V

DD3V3_USBFS

is used to supply

must be supplied as well when USB highspeed OTG device is used. If not used, must be connected to V

DD.

Caution: V

DD3V3_USBHS

must not be present unless V

DDA1V8_REG

is present, otherwise permanent

STM32MP153A/D damage could occur. Must be ensured by PMIC ranking order or with external component in case of discrete component power supply implementation.

• V

DDQ_DDR

is the DDR IO supply.

– Voltage range is 1.425 V to 1.575 V for interfacing DDR3 memories (1.5 V typ.).

– Voltage range is 1.283 V to 1.45 V for interfacing DDR3L memories (1.35 V typ.).

– Voltage range is 1.14 V to 1.3 V for interfacing LPDDR2 or LPDDR3 memories

(1.2 V typ.).

During power-up and power-down phases, the following power sequence requirements must be respected:

• When V

is below 1 V, other power supplies (V

DDCORE

DDA1V1_REG

, V

DD3V3_USBHS/FS

, V

DDQ_DDR

, V

DDA

, V

) must remain below V

DDA1V8_REG

+ 300 mV.

• When V

is above 1 V, all power supplies are independent.

During the power-down phase, V

can temporarily become lower than other supplies only if the energy provided to the STM32MP153A/D device remains below 1 mJ; this allows

DS12502 Rev 6 27/256

Functional overview STM32MP153A/D external decoupling capacitors to be discharged with different time constants during the power- down transient phase.

Figure 2. Power-up/down sequence

3.6

DDX

(1)

BOR0

3.7.2

0.3

Power-on Operating mode Power-down time

Invalid supply area V

DDX

< V

+ 300 mV V

DDX

independent from V

MSv47490V1

1. V

DDX

refers to any power supply among V

DDQ_DDR

DDCORE

, V

DDA

, V

DDA1V8_REG

, , V

DDA1V1_REG

, V

DD3V3_USBHS/FS

Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry:

• Power-on reset (POR)

The POR supervisor monitors V

power supply and compares it to a fixed threshold.

The devices remain in reset mode when V

is below this threshold,

• Power-down reset (PDR)

The PDR supervisor monitors V

DD below a fixed threshold.

power supply. A reset is generated when V

DD drops

The PDR supervisor can be enabled/disabled through PDR_ON pin.

• Brownout reset (BOR)

The BOR supervisor monitors V

DD below this threshold.

power supply. Three BOR thresholds (from 2.1 to

2.7 V) can be configured through option bytes. A reset is generated when V

drops

• Power-on reset V

DDCORE

(POR_VDDCORE)

The POR_VDDCORE supervisor monitors V

DDCORE

power supply and compares it to a fixed threshold. The V

DDCORE this threshold,

domain remain in reset mode when V

DDCORE

is below

• Power-down reset V

DDCORE

(PDR_VDDCORE)

The PDR_VDDCORE supervisor monitors V

DDCORE reset is generated when V

DDCORE

power supply. A V drops below a fixed threshold.

DDCORE

domain

The PDR_VDDCORE supervisor can be enabled/disabled through PDR_ON_CORE pin.

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STM32MP153A/D

3.8 Low-power strategy

Functional overview

There are several ways to reduce power consumption on STM32MP153A/D:

• Decrease dynamic power consumption by slowing down the CPU clocks and/or the bus matrix clocks and/or controlling individual peripheral clocks.

• Save power consumption when the CPU is IDLE, by selecting among the available lowpower mode according to the user application needs. This allows the best compromise between short startup time, low-power consumption, as well as available wakeup sources, to be achieved.

The CPUs feature several low-power modes:

• CSleep (CPU clock stopped)

• CStop (CPU sub-system clock stopped)

• Stop (bus matrix clocks stalled, the oscillators can be stopped)

• CStandby (MPU sub-system clock stopped and wakeup via reset)

• Standby (system powered down)

• LP-Stop and LPLV-Stop (bus matrix clocks stalled, the oscillators can be stopped, lowpower mode signaled to external regulator)

CSleep and CStop low-power modes are entered by the CPU when executing the WFI (wait for interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the

Cortex-M4 core is set after returning from an interrupt service routine.

If part of the domain is not in low-power mode, the domain remains in the current mode.

Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the CPUs are in CStop or CStandby mode.

System power mode

Table 3. System versus domain power mode

MPU

Run mode

CRun or CSleep

CStop or CStandby

CRun or CSleep

MCU

CRun or CSleep

CStop

Stop mode

LP-Stop mode

LPLV-Stop mode

CStop or CStandby CStop

Standby mode

CStandby or (CStop and

MPU PDDS = 1 and MPU CSTBYDIS = 1)

CStop and

MCU PDDS = 1

DS12502 Rev 6 29/256

Functional overview

3.9

3.9.1

Reset and clock controller (RCC)

STM32MP153A/D

The clock and reset controller manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows application of clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can be changed without modifying the baudrate.

Clock management

The devices embed four internal oscillators, two oscillators with external crystal or resonator, three internal oscillators with fast startup time and four PLLs.

The RCC receives the following clock source inputs:

• Internal oscillators:

– 64 MHz HSI clock (1% accuracy)

– 4 MHz CSI clock

– 32 kHz LSI clock

• External oscillators:

– 8-48 MHz HSE clock

– 32.768 kHz LSE clock

The RCC provides four PLLs:

• The PLL1 is dedicated to the MPU clocking

• The PLL2 provides:

– The clocks for the AXI-SS (including APB4, APB5, AHB5 and AHB6 bridges)

– The clocks for the DDR interface

• The PLL3 provides:

– The clocks for the MCU, and its bus matrix (including the APB1, APB2, APB3,

AHB1, AHB2, AHB3 and AHB4)

– The kernel clocks for peripherals

• The PLL4 is dedicated to the generation of the kernel clocks for various peripherals

The system starts on the HSI clock. The user application can then select the clock configuration.

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3.9.2 System reset sources

Functional overview

The power-on reset initializes all registers while the system reset reinitializes the system except for the debug, part of the RCC and power controller status registers, as well as the backup power domain.

An application reset is generated from one of the following sources:

– a reset from NRST pad

– a reset from POR and PDR signal (generally called power-on reset)

– a reset from BOR (generally called brownout)

– a reset from the independent watchdogs 1

– a reset from the independent watchdogs 2

– a software reset from the Cortex-M4 (MCU)

– a software reset from the Cortex-A7 (MPU)

– a failure on HSE, when the clock security system feature is activated

A system reset is generated from one of the following sources:

– An application reset,

– A reset from POR_VDDCORE signal,

– Every time the system exits from Standby.

3.10 Hardware semaphore (HSEM)

The HW semaphore block provides 64 (32-bit) register-based semaphores.

The semaphores can be used to ensure synchronization between different processes running on a core and between different cores. The HSEM provides a non blocking mechanism to lock semaphores in an atomic way. The following functions are provided:

• Locking a semaphore can be done in 2 ways:

– 2-step lock: by writing CoreID and ProcessID to the semaphore, followed by a read check.

– 1-step lock: by reading the CoreID from the semaphore.

• Interrupt generation when a semaphore is freed.

– Each semaphore may generated an interrupt on one of the interrupt lines.

• Semaphore clear protection.

– A semaphore is only cleared when CoreID and ProcessID matches.

• Global semaphore clear per CoreID.

3.11 Inter-processor communication controller (IPCC)

The inter-processor communication controller (IPCC) is used for communicating data between two processors.

The IPCC block provides a non blocking signaling mechanism to post and retrieve communication data in an atomic way. It provides the signaling for four channels:

• two channels in the direction from processor 1 to processor 2

• two channels in the opposite direction.

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Functional overview STM32MP153A/D

It is then possible to have two different communication types in each direction.

The IPCC communication data must be located in a common memory, which is not part of the IPCC block.

3.11.1 IPCC main features

• Status signaling for the four channels

– Channel occupied/free flag, also used as lock

• Two interrupt lines per processor

– One for RX channel occupied (communication data posted by sending processor)

– One for TX channel free (communication data retrieved by receiving processor)

• Interrupt masking per channel

– Channel occupied mask

– Channel free mask

• Two channel operation modes

– Simplex (each channel has its own communication data memory location)

– Half duplex (a single channel in associated to a bidirectional communication data information memory location)

3.12 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.

After reset, all GPIOs are in analog mode to reduce power consumption.

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.

Additionally, GPIO pins on port Z can be individually set as secure, which would mean that software accesses to these GPIOs and associated peripherals defined as secure are restricted to secure software running on Cortex-A7.

3.13 TrustZone protection controller (ETZPC)

ETZPC is used to configure TrustZone security of bus masters and slaves with programmable-security attributes (securable resources) such as:

• On-chip SYSRAM with programmable secure region size

• AHB and APB peripherals to be made secure

Notice that by default, SYSRAM and peripheral are set to secure access only, so, not accessible by non-secure masters such as Cortex-M4 or DMA1/DMA2.

ETZPC can also allocate peripherals and SRAM to be accessible only by the Cortex-M4 and/or DMA1/DMA2. This ensures the safe execution of the Cortex-M4 firmware, protected from other masters (e.g. Cortex-A7) unwanted accesses.

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3.14 Bus-interconnect matrix

The devices feature an AXI bus matrix, one main AHB bus matrix and bus bridges that allow

bus masters to be interconnected with bus slaves (see Figure 3 , the dots represent the

enabled master/slave connections).

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Functional overview

Figure 3. STM32MP153A/D bus matrix

STM32MP153A/D

M10 M0 M1 M2 M3 M4 M5 M6 M7 M9

S0 MPU_AXI_DDR1

MPU_AXI_DDR2

S2 MPU_AHB6

MPU_AHB_MCU

S4 MPU_AXI_FMC

MPU_AXI_QUADSPI

S6 MPU_AXI_SYSRAM

MPU_AXI_ROM

S8 MPU_AXI_STM

MPU_AHB5

S10 MPU_APB5

S11

MPU_DBG_APB

DDRCTRL 533 MHz

AHB bridge to AHB6

To MCU interconnect

FMC/NAND

QUADSPI

SYSRAM 256 KB

ROM 128 KB

STM

AHB bridge to AHB5

APB bridge to APB5

APB bridge to DBG APB

Default slave

AXIMC

M0 M1 M2 M3 M4

NIC-400 AXI 64 bits 266 MHz - 10 masters / 12 slaves

M5 M6 M7 M8 M9

S0 MCU_AHB_MEM0

MCU_AHB_MEM1

S2 MCU_AHB_MEM2

S8 MCU_AHB_MEM3

S3 MCU_AHB3

MCU_AHB2

S5 MCU_AHB_MPU

MCU_AHB_RET

S7 MCU_AHB4

Interconnect AHB 32 bits 209 MHz - 10 masters / 9 slaves

Masters access S0 XOR S1 layer

AXI 64 synchronous master port

AXI 64 synchronous slave port

AXI 64 asynchronous master port

AXI 64 asynchronous slave port

AHB 32 synchronous master port

AHB 32 synchronous slave port

AHB 32 asynchronous master port

AHB 32 asynchronous slave port

SRAM1

SRAM2

SRAM3

SRAM4

Bridge to AHB3

Bridge to AHB2

To MPU interconnect

RetentionRAM

Bridge to AHB4

MSv47455V2

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3.15 DMA controllers

The devices features three DMA modules to unload CPU activity:

• A master direct memory access (MDMA)

The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface.

The MDMA is located in MPU domain. It is able to interface with the other DMA controllers located in MCU domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly.

Each of the 32 channels can perform block transfers, repeated block transfers and linked list transfers.

The MDMA can be set to make secure transfers to secured memories.

• Two DMA controllers (DMA1, DMA2), located in MCU domain. Each controller is a dual-port AHB, for a total of 16 DMA channels to perform FIFO-based block transfers.

The DMAMUX is an extension of the DMA1 and DMA2 controllers. It multiplexes and routes the DMA peripheral requests to the DMA1 or DMA2 controllers, with a high flexibility, maximizing the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output trigger or DMA event.

3.16 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex ® -

M4 with FPU core.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving, higher-priority interrupts

• Support tail chaining

• Processor context automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

3.17 Extended interrupt and event controller (EXTI)

The extended interrupt and event controller (EXTI) manages individual CPU and system wakeup through configurable and direct event inputs. It provides wake-up requests to the power control, and generates an interrupt request to the CPUs NVIC or GIC and events to the CPUs event inputs. For each CPU an additional event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wake-up requests allow the system to be woken up from Stop mode, and the

CPUs to be woken up from CStop and CStandby modes.

The interrupt request and event request generation can also be used in Run mode.

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Functional overview STM32MP153A/D

The block also includes the EXTI IOport selection.

Each interrupt or event can be set as secure in order to restrict access to secure software only.

3.18 Cyclic redundancy check calculation unit (CRC1, CRC2)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps computing a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.19 Flexible memory controller (FMC)

The FMC controller main features are the following:

• Interface with static-memory mapped devices including:

– NOR Flash memory

– Static or pseudo-static random access memory (SRAM, PSRAM)

– NAND Flash memory with 4-bit/8-bit BCH hardware ECC

• 8-,16-bit data bus width

• Independent chip select control for each memory bank

• Independent configuration for each memory bank

• Write FIFO

3.20 Dual Quad-SPI memory interface (QUADSPI)

The QUADSPI is a specialized communication interface targeting single, dual or quad SPI

Flash memories. It can operate in any of the three following modes:

• indirect mode: all the operations are performed using the QUADSPI registers

• status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting

• memory-mapped mode: the external Flash memory is mapped to the address space and is seen by the system as if it was an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad-SPI Flash memories are accessed simultaneously.

QUADSPI is coupled with a delay block (DLYBQS) allowing the support of external data frequency above 100 MHz.

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3.21 Analog-to-digital converters (ADCs)

The STM32MP153A/D devices embed two analog-to-digital converters, which resolution can be configured to 16, 14, 12, 10 or 8 bits. Each ADC shares up to 20 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

• simultaneous ADC1/ADC2 conversion

• interleaved ADC1/ADC2 conversion.

The ADC can be served by the DMA controller, thus allowing the automatic transfer of ADC converted values to a destination location without any software action.

In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

In order to synchronize A/D conversion and timers, the ADCs can be triggered by any of

TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, LPTIM1, LPTIM2 and LPTIM3 timers.

3.22 Temperature sensor

The STM32MP153A/D devices embed a temperature sensor that generates a voltage (V

) that varies linearly with the temperature. This temperature sensor is internally connected to

ADC2_INP12. It can measure the device ambient temperature ranging from –40 to +125 °C with a precision of ±2%.

The temperature sensor has a good linearity, but it has to be calibrated to obtain a good overall accuracy of the temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST.

The temperature sensor factory calibration data are stored by ST in the OTP area, which is accessible in read-only mode.

3.23 Digital temperature sensor (DTS)

The device embeds a frequency output temperature sensor. This block counts the frequency based on the LSE or PCLK to provide the temperature information.

Following functions can be supported:

• Interrupt generation by temperature threshold.

• Wakeup signal generation by temperature threshold.

3.24 V

BAT

operation

The V

BAT

power domain contains the RTC, the backup registers, the retention RAM and the backup SRAM.

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Functional overview

Note:

STM32MP153A/D

In order to optimize battery duration, this power domain is supplied by V

when available or by the voltage applied on VBAT pin (when V switched when the PDR detects that V

supply is not present). V

BAT

power is

has dropped below the PDR level.

The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or directly by V

. In the later case, VBAT mode is not functional.

BAT

operation is activated when V

is not present.

The V

BAT

SRAM.

pin supplies the RTC, the backup registers, the retention RAM and the backup

None of these events: external interrupts, TAMP event, or RTC alarm/events are able to directly restore the V

supply and force the STM32MP153A/D device out of the V

BAT operation. Nevertheless, TAMP events and RTC alarm/events can be used to generate a signal to an external circuitry (typically a PMIC) that can restore the STM32MP153A/D V

DD supply.

When PDR_ON pin is connected to V

SS more available and VBAT

(internal reset OFF), the V

BAT pin must be connected to V

functionality is no

3.25 Digital-to-analog converters (DAC1, DAC2)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.

This dual digital interface supports the following features:

• Two DAC converters: one for each output channel

• 8-bit or 12-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Sample and hold mode to reduce the power consumption

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel including DMA underrun error detection

• External triggers for conversion

• input voltage reference V

REF+ or internal VREFBUF reference.

The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.

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3.26 Voltage reference buffer (VREFBUF)

The STM32MP153A/D devices embed a voltage reference buffer which can be used as voltage reference for ADC, DACs and also as voltage reference for external components through the VREF+ pin.

The internal voltage reference buffer supports four voltages:

• 1.5 V

• 1.8 V

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off.

Figure 4. Voltage reference buffer

VREFBUF

Bandgap +

DDA

DAC, ADC

VREF+

Low frequency cut-off capacitor

100 nF

MSv40197V1

3.27 Digital filter for sigma delta modulators (DFSDM1)

The device embeds one DFSDM with support for 6 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs.

The DFSDM peripheral is dedicated to interface external Σ∆ modulators to

STM32MP153A/D and perform digital filtering of the received data streams. Σ∆ modulators are used to convert analog signals into digital serial streams that constitute the inputs of the

DFSDM. The DFSDM can also interface PDM (pulse density modulation) microphones and perform the PDM to PCM conversion and filtering (hardware accelerated). The DFSDM features optional parallel data stream inputs from internal ADC peripherals or

STM32MP153A/D memory (through DMA/CPU transfers into DFSDM).

The DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user-defined filter parameters with up to 24-bit final ADC resolution.

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Functional overview STM32MP153A/D

The DFSDM peripheral supports:

• 8 multiplexed input digital serial channels:

– configurable SPI interface to connect various SD modulator(s)

– configurable Manchester coded 1-wire interface support

– PDM (pulse density modulation) microphone input support

– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

– clock output for SD modulator(s): 0…20 MHz

• Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution):

– internal sources: ADC data or memory data streams (DMA)

• 6 digital filter modules with adjustable digital signal processing:

– Sinc x filter: filter order/type (1…5), oversampling ratio (1…1024)

– integrator: oversampling ratio (1…256)

• Up to 24-bit output data resolution, signed output data format

• Automatic data offset correction (offset stored in register by user)

• Continuous or single conversion

• Start-of-conversion triggered by:

– software trigger

– internal timers

– external events

– start-of-conversion synchronously with first digital filter module (DFSDM0)

• Analog watchdog feature:

– low value and high value data threshold registers

– dedicated configurable Sinc x digital filter (order = 1…3, oversampling ratio =

1…32)

– input from final output data or from selected input digital serial channels

– continuous monitoring independently from standard conversion

• Short circuit detector to detect saturated analog input values (bottom and top range):

– up to 8-bit counter to detect 1…256 consecutive 0’s or 1’s on serial data stream

– monitoring continuously each input serial channel

• Break signal generation on analog watchdog event or on short circuit detector event

• Extremes detector:

– storage of minimum and maximum values of final conversion data

– refreshed by software

• DMA capability to read the final conversion data

• Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence

• “Regular” or “injected” conversions:

– “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions

– “injected” conversions for precise timing and with high conversion priority

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3.28 Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock and

14-bit of data. It features:

• Programmable polarity for the input pixel clock and synchronization signals

• Parallel data communication can be 8-, 10-, 12- or 14-bit

• Supports 8-bit progressive video monochrome or raw Bayer format, YC b

C r

4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)

• Supports continuous mode or snapshot (a single frame) mode

• Capability to automatically crop the image

3.29 LCD-TFT display controller (LTDC)

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to

WXGA (1366 × 768) @60 fps or up to Full HD (1920 × 1080) @30 fps resolution with the following features:

• Up to 90 MHz pixel clock

• 2 display layers with dedicated FIFO

• Color look-up table (CLUT) up to 256 colors (256×24-bit) per layer

• Up to 8 input color formats selectable per layer

• Flexible blending between two layers using alpha value (per pixel or constant)

• Flexible programmable parameters for each layer

• Color keying (transparency color)

• Up to 4 programmable interrupt events

• AXI master interface

3.30 True random number generator (RNG1, RNG2)

The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.

RNG1 can be defined (in ETZPC) as accessible by secure software only.

3.31 Hash processors (HASH1, HASH2)

The devices embed two processors that support the advanced algorithms usually required to ensure authentication, data integrity and non-repudiation when exchanging messages with a peer:

• Universal HASH

– SHA-1, SHA224 and SHA256 (secure HASH algorithms)

– MD5

– HMAC

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Functional overview STM32MP153A/D

The accelerator supports DMA request generation.

HASH1 can be defined (in ETZPC) as accessible by secure software only.

3.32 Boot and security and OTP control (BSEC)

The BSEC (boot and security and OTP control) is intended to control an OTP (one time programmable) fuse box, used for embedded non-volatile storage for device configuration and security parameters. Some part of BSEC should be configured as accessible by secure software only.

3.33 Timers and watchdogs

The devices include two advanced-control timers, ten general-purpose timers, two basic timers, five low-power timers, three watchdogs, a SysTick timer in Cortex-M4 and 4 system timers in each Cortex-A7.

All timer counters can be frozen in debug mode.

Table 4 compares the features of the advanced-control, general-purpose, basic and low-

power timers.

Timer type

Advanced

-control

General purpose

Timer

TIM1,

TIM8

TIM2,

TIM5

TIM3,

TIM4

TIM12

TIM13,

TIM14

TIM15

TIM16,

TIM17

Counter resolution

Table 4. Timer feature comparison

Counter type

Prescaler factor

DMA request generation

Capture/ compare channels

Complementary output

Max interface clock

(MHz)

Max timer clock

(MHz)

(1)

16-bit

32-bit

16-bit

Up, down, up/down

Any integer between 1 and 65536

Yes

104.5

209

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Timer type

Timer

Table 4. Timer feature comparison (continued)

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/ compare channels

Complementary output

Max interface clock

(MHz)

Max timer clock

(MHz)

(1)

Basic

TIM6,

TIM7

16-bit Up

Any integer between 1 and 65536

Yes 0

Lowpower

LPTIM1,

LPTIM2,

LPTIM3,

LPTIM4,

LPTIM5

16-bit Up

1, 2, 4, 8,

16, 32, 64,

128

No 1

(2)

1. The maximum timer clock is up to 209 MHz depending on TIMGxPRE bit in the RCC.

2. No capture channel on LPTIM.

104.5

209

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Functional overview STM32MP153A/D

3.33.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.

Their 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge- or center-aligned modes)

• One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose timers. If configured as 16-bit PWM generators, they have full modulation capability (0-

100%).

The advanced-control timer can work together with the general-purpose timers via the timer link feature for synchronization or event chaining.

TIM1 and TIM8 support independent DMA request generation.

3.33.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13,

TIM14, TIM15, TIM16, TIM17)

There are ten synchronizable general-purpose timers embedded in the STM32MP153A/D

devices (see Table 4 for differences).

• TIM2, TIM3, TIM4, TIM5

The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and

TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.

TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the timer link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.

• TIM12, TIM13, TIM14, TIM15, TIM16, TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers or used as simple timebases.

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3.33.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base.

TIM6 and TIM7 support independent DMA request generation.

3.33.4 Low-power timer (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)

The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the device from Stop mode.

These low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous / one-shot mode

• Selectable software / hardware input trigger

• Selectable clock source:

• Internal clock source: LSE, LSI, HSI or APB clock

• External clock source over LPTIM input (working even with no internal clock source running, used by the pulse counter application)

• Programmable digital glitch filter

• Encoder mode

3.33.5 Independent watchdog (IWDG1, IWDG2)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC(LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

IWDG1 can be defined (in ETZPC) as accessible by secure software only.

3.33.6 System window watchdog (WWDG1)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.33.7 SysTick timer (Cortex-M4)

This timer is embedded inside Cortex-M4 core and dedicated to real-time operating systems, but can also be used as a standard downcounter. It features:

• A 24-bit downcounter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source.

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Functional overview STM32MP153A/D

3.33.8 Generic timers (Cortex-A7 CNT)

Cortex-A7 generic timers embedded inside Cortex-A7 are fed by value from system timing generation (STGEN).

The Cortex-A7 processor provides a set of four timers for each processor:

• Physical timer for use in secure and non-secure modes. The registers for the physical timer are banked to provide secure and non-secure copies.

• Virtual timer for use in non-secure modes.

• Physical timer for use in hypervisor mode.

Generic timers are not memory mapped peripherals, they are accessible only by specific

Cortex-A7 coprocessor instructions (cp15).

3.34 System timer generation (STGEN)

The system timing generation (STGEN) generates a time count value that provides a consistent view of time for all Cortex-A7 generic timers.

The system timing generation has the following key features:

• 64-bit wide to avoid roll-over issues.

• Starts from zero or a programmable value.

• A control APB interface (STGENC) enables the timer to be saved and restored across powerdown events.

• Read-only APB interface (STGENR) enables the timer value to be read by non-secure software and debug tools.

• The timer value incrementing can be stopped during system debug.

STGENC can be defined (in ETZPC) as accessible by secure software only.

3.35 Real-time clock (RTC)

The RTC provides an automatic wakeup to manage all low-power modes.

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar with programmable alarm interrupts.

The RTC includes also a periodic programmable wakeup flag with interrupt capability.

Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format

(BCD). The sub-seconds value is also available in binary format.

Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed.

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy.

After backup domain reset, all RTC registers are protected against possible parasitic write accesses.

46/256 DS12502 Rev 6

STM32MP153A/D Functional overview

As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, Low-power mode or under reset).

The RTC unit main features are the following:

• Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year.

• Daylight saving compensation programmable by software.

• Programmable alarm with interrupt function. The alarm can be triggered by any combination of the calendar fields.

• Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

• Accurate synchronization with an external clock using the subsecond shift feature.

• Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration window of several seconds

• Timestamp function for event saving

• Maskable interrupts/events:

– Alarm A

– Alarm B

– Wakeup interrupt

– Timestamp

• TrustZone support:

– RTC fully securable

– Alarm A, alarm B, wakeup timer and timestamp individual secure or non-secure configuration

3.36 Tamper and backup registers (TAMP)

32 x 32-bit backup registers are retained in all low-power modes and also in VBAT mode.

They can be used to store sensitive data as their content is protected by an tamper detection circuit. 3 tamper pins and 5 internal tampers are available for anti-tamper detection. The external tamper pins can be configured for edge detection, edge and level, level detection with filtering, or active tamper which increases the security level by auto checking that the tamper pins are not externally opened or shorted.

DS12502 Rev 6 47/256

Functional overview STM32MP153A/D

TAMP main features

• 32 backup registers:

– the backup registers (TAMP_BKPxR) are implemented in the RTC domain that remains powered-on by VBAT when the V

power is switched off.

• 3 external tamper detection events.

– Each external event can be configured to be active or passive.

– External passive tampers with configurable filter and internal pull-up.

• 5 internal tamper events.

• Any tamper detection can generate a RTC timestamp event.

• Any tamper detection erases the backup registers.

• TrustZone support:

– Tamper secure or non-secure configuration.

– Backup registers configuration in 3 configurable-size areas:

1 read/write secure area.

1 write secure/read non-secure area.

1 read/write non-secure area.

• Monotonic counter.

48/256 DS12502 Rev 6

STM32MP153A/D Functional overview

3.37 Inter-integrated circuit interface (I2C1, I2C2, I2C3, I2C4, I2C5,

I2C6)

The STM32MP153A/D embeds six I

C interfaces.

The I

2 serial I

C bus interface handles communications between the STM32MP153A/D and the

C bus. It controls all I

C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

• System management bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK control

– Address resolution protocol (ARP) support

– SMBus alert

• Power system management protocol (PMBus™) specification rev 1.1 compatibility

• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming.

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

I2C4 and I2C6 can be defined (in ETZPC) as accessible by secure software only.

3.38 Universal synchronous asynchronous receiver transmitter

(USART1, USART2, USART3, USART6 and UART4, UART5,

UART7, UART8)

The STM32MP153A/D devices have four embedded universal synchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous

receiver transmitters (UART4, UART5, UART7 and UART8). Refer to Table 5

for a summary of USARTx and UARTx features.

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN master/slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to

10 Mbit/s.

USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability.

DS12502 Rev 6 49/256

Functional overview STM32MP153A/D

All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the STM32MP153A/D from Stop mode using baudrates up to 200 Kbaud.The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 5. USART features

USART modes/features

(1)

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode (master/slave)

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from low power mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

USART data length

1. X = supported.

USART1/2/3/6

UART4/5/7/8

7, 8 and 9 bits

USART1 can be defined (in ETZPC) as accessible by secure software only.

3.39 Serial peripheral interface (SPI1, SPI2, SPI3, SPI4, SPI5,

SPI6)– inter- integrated sound interfaces (I2S1, I2S2, I2S3)

The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that allow communication at up to 50 Mbit/s in master and slave modes, in half-duplex, fullduplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode, hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.

Three standard I 2 S interfaces (I2S1, I2S2, I2S3, multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in full-duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I 2 S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling

50/256 DS12502 Rev 6

STM32MP153A/D Functional overview frequency. All I 2 S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA capability.

SPI6 can be defined (in ETZPC) as accessible by secure software only.

3.40 Serial audio interfaces (SAI1, SAI2, SAI3, SAI4)

The devices embed 4 SAIs that allow the design of many stereo or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller.

Audio sampling frequencies up to 192 kHz are supported.

In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.

The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other SAIs to work synchronously.

3.41 SPDIF receiver interface (SPDIFRX)

The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1).

The main SPDIFRX features are the following:

• Up to 4 inputs available

• Automatic symbol rate detection

• Maximum symbol rate: 12.288 MHz

• Stereo stream from 32 to 192 kHz supported

• Supports audio IEC-60958 and IEC-61937, consumer applications

• Parity bit management

• Communication using DMA for audio samples

• Communication using DMA for control and user channel information

• Interrupt capabilities

The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal is available, the SPDIFRX re-samples the incoming signal, decode the

Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the

CPU decoded data, and associated status flags.

The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that is used to compute the exact sample rate for clock drift algorithms.

DS12502 Rev 6 51/256

Functional overview STM32MP153A/D

3.42 Management data input/output (MDIOS)

The devices embed a MDIO slave interface. It includes the following features:

• 32 MDIO register addresses, each of which is managed using separate input and output data registers:

– 32 x 16-bit firmware read/write, MDIO read-only output data registers

– 32 x 16-bit firmware read-only, MDIO write-only input data registers

• Configurable slave (port) address

• Independently maskable interrupts/events:

– MDIO register write

– MDIO register read

– MDIO protocol error

• Able to operate in and wake up from Stop mode

3.43 Secure digital input/output MultiMediaCard interface

(SDMMC1, SDMMC2, SDMMC3)

Three secure digital input/output MultiMediaCard interfaces (SDMMC) provide an interface between the AHB bus and SD memory cards, SDIO cards and MMC devices.

The SDMMC features include the following:

• Full compliance with MultiMediaCard System Specification Version 4.51

Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit.

• Full compatibility with previous versions of MultiMediaCards (backward compatibility).

• Full compliance with SD memory card specifications version 4.1

(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and

UHS-II mode not supported).

• Full compliance with SDIO card specification version 4.0.

Card support for two different databus modes: 1-bit (default) and 4-bit.

(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and

UHS-II mode not supported).

• Data transfer up to 208 Mbyte/s for the 8-bit mode.

(depending maximum allowed I/O speed).

• Data and command output enable signals to control external bidirectional drivers.

• The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the interface and the SRAM.

• IDMA linked list support

Each SDMMC is coupled with a delay block (DLYBSD) allowing support of an external data frequency above 100 MHz.

3.44 Controller area network (FDCAN1, FDCAN2)

The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory and a clock calibration unit.

52/256 DS12502 Rev 6

STM32MP153A/D Functional overview

Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.

FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event synchronized time-triggered communication, global system time, and clock drift compensation. The FDCAN1 contains additional registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and time-triggered

CAN communication.

A 10 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers (and triggers for TTCAN). This message RAM is shared between the two FDCAN1 and FDCAN2 modules.

The common clock calibration unit is optional. It can be used to generate a calibrated clock for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1.

3.45 Universal serial bus high-speed host (USBH)

The devices embed one USB high-speed host (up to 480 Mbit/s) with two physical ports.

USBH supports both low, full-speed (OHCI) as well as high-speed (EHCI) operations independently on each port. It integrates two transceivers which can be used for either lowspeed (1.2 Mbit/s), full-speed (12 Mbit/s) or high-speed operation (480 Mbit/s), the second high-speed transceiver is shared with OTG high-speed.

The USB HS is compliant with the USB 2.0 specification. The USB HS controllers require dedicated clocks that are generated by a PLL inside the USB high-speed PHY.

3.46 USB on-the-go high-speed (OTG)

The devices embed one USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and high-speed operation (480 Mbit/s) shared with USB Host second port.

The USB OTG HS is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume.

The USB OTG controllers require a dedicated 48 MHz clock that is generated by a PLL inside RCC or inside the USB high-speed PHY.

DS12502 Rev 6 53/256

Functional overview STM32MP153A/D

The main features are:

• Combined Rx and Tx FIFO size of 4 Kbyte with dynamic FIFO sizing

• Supports the session request protocol (SRP) and host negotiation protocol (HNP)

• 8 bidirectional endpoints

• 16 host channels with periodic OUT support

• Software configurable to OTG1.3 and OTG2.0 modes of operation

• USB 2.0 LPM (link power management) support

• Battery charging specification revision 1.2 support

• Internal FS or HS OTG PHY support

• Internal USB DMA

• HNP/SNP/IP inside (no need for any external resistor)

• For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

3.47 Gigabit Ethernet MAC interface (ETH1)

The devices provide an IEEE-802.3-2002-compliant gigabit media access controller

(GMAC) for Ethernet LAN communications through an industry-standard mediumindependent interface (MII), a reduced medium-independent interface (RMII), a gigabit medium-independent interface (GMII) or a reduced gigabit medium-independent interface

(RGMII).

The STM32MP153A/D requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device port using 17 signals for MII, 7 signals for RMII, 26 signals for GMII or 13 signals for RGMII, and can be clocked using the 25 MHz (MII, RMII, GMII, RGMII) or 125 MHz (GMII, RGMII) from the STM32MP153A/D or from the PHY.

The devices include the following features:

• Operation modes and PHY interfaces

– 10, 100, and 1000 Mbps data transfer rates

– Support of both full-duplex and half-duplex operations

– MII, RMII, GMII and RGMII PHY interfaces

• Multiple queues support and audio video bridging (AVB) management

– Separate channels or queues for AV data transfer in 100 and 1000 Mbps modes

– Two queues on the Rx paths and two queues on the Tx path for AV traffic

– One DMA for Rx path and two DMA for Tx path (one per transmit channels)

– Several arbitration algorithms between queues: weighted round robin (WRR), strict priority (SP), weighted strict priority (WSP), IEEE 802.1-Qav specified creditbased shaper (CBS) algorithm for Transmit channels

• Processing control

– Multi-layer Packet filtering: MAC filtering on source (SA) and destination (DA) address with perfect and hash filter, VLAN tag-based filtering with perfect and

54/256 DS12502 Rev 6

STM32MP153A/D Functional overview hash filter, Layer 3 filtering on IP source (SA) or destination (DA) address, Layer 4 filtering on source (SP) or destination (DP) port

– Double VLAN processing: insertion of up to two VLAN tags in transmit path, tag filtering in receive path

– IEEE 1588-2008/PTPv2 support

– Supports network statistics with RMON/MIB counters (RFC2819/RFC2665)

• Hardware offload processing

– Preamble and start-of-frame data (SFD) insertion or deletion

– Integrity Checksum offload engine for IP header and TCP/UDP/ICMP payload: transmit checksum calculation and insertion, receive checksum calculation and comparison

– Automatic ARP request response with the device's MAC address

– TCP Segmentation: Automatic split of large transmit TCP packet into multiple small packets

• Low-power mode

– Energy efficient Ethernet (Standard IEEE 802.3az-2010)

– Remote wakeup packet and AMD Magic Packet™ detection

3.48 High-definition multimedia interface (HDMI) – Consumer electronics control (CEC)

The device embeds a HDMI-CEC controller that provides hardware support for the consumer electronics control (CEC) protocol (supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wake up the STM32MP153A/D from Stop mode on data reception.

3.49 Debug infrastructure

The devices offer a comprehensive set of debug and trace features to support software development and system integration.

• Breakpoint debugging

• Code execution tracing

• Software instrumentation

• JTAG debug port

• Serial-wire debug port

• Trigger input and output

• Serial-wire trace port

• Trace port

• Arm ® CoreSight™ debug and trace components

The debug can be controlled via a JTAG/serial-wire debug access port, using industry standard debugging tools.

A trace port allows data to be captured for logging and analysis.

DS12502 Rev 6 55/256

Pinouts, pin description and alternate functions

4

STM32MP153A/D

Pinouts, pin description and alternate functions

VSS

PD1

PG15 PE6

PB7

PD7

PC6

Figure 5. STM32MP153A/DADxx TFBGA257 pinout

5 6 7 8 9 10 11 12 13 14

VSS PD3 PC8 PE4 DNU DNU

15 16

JTDO-

TRACES

JTCK-

SWCLK

DDR_

DQ0

PA15 PG6 PB4 PE5 PA8 PC9 PC10 DNU DNU DNU NJTRST JTDI

DDR_

DQ1

VSS

DDR_

DQ3

DDR_

DQ7

DDR_

DQS0N

DDR_

DQS0P

PE12

PG12

PD8

PE0

PE11

NRST

PD4

PE15

PE13

VSS

PC15-

OSC32_

OUT

PC14-

OSC32_

VSS

PC13

BOOT2

PH0-

OSC_IN

BOOT0

PH1-

OSC_

OUT

NRST_

CORE

PWR_LP

PDR_ON

_CORE

BOOT1

PD5

PE1

PD6

PD0

PD9

VBAT

PD14

PA9

PD10

PE14

PD15

VSS

VDD

PB3 PB15 PB9

PE3

VDD

CORE

VSS

VDD

CORE

VSS

PB14

PC12

VDD

CORE

VSS

VDD

CORE

PC7

PD2

VDD

CORE

VSS

VDD

CORE

VSS

PC11 DNU

VDD_

Unused

VSS

JTMS-

SWDIO

DDR_

RESETN

DDR_

DQM0

DDR_

DQ2

DDR_

DQ6

VSS

VDD

CORE

VSS

VDD

CORE

VDD1V2_

Unused

DDR_ZQ

VDDA

1V8_

Unused

VDD1V2_

Unused

VSS

VDD

CORE

VSS

DDR_

DTO1

DDR_

DTO0

VDD

CORE

DDR_A7

VDDQ_

DDR

DDR_A5

VDDQ_

DDR

DDR_

RASN

VSS

DDR_

DQ4

DDR_

DQ5

DDR_A13 DDR_A9

DDR_A2 VSS DDR_A3

VSS DDR_A0

DDR_

BA0

DDR_

BA2

DDR_

ODT

DDR_

CSN

DDR_

WEN

DDR_

CASN

VSS

DDR_

CLKN

VSS

DDR_

CLKP

DDR_A15

PA14

VSS

PA13 PDR_ON

VDDA

PWR_ON VREF+

VSSA

PA3 PA0

PE2 PC2 PC3

PA5

PA1

PG14 PG13

PC1 PA2

PA4

VDDA

VSS

PB13

VDD

VSS

VDD

VSS

VDD

VSS

PE9

VDD

CORE

VSS

VDDA

1V8_

REG

VSS

VDD

CORE

VSS

VDDA

1V1_

REG

VDD

CORE

VSS

VDD

3V3_

USB

PF10

DDR_

ATO

VDD

CORE

VSS

USB_

RREF

VDDQ_

DDR

DDR_A6

VDDQ_

DDR

VSS

DDR_A10 DDR_A12 DDR_A1

VSS DDR_A14 DDR_A11

DDR_

CKE

DDR_

BA1

DDR_A4

DDR_

DQ8

VSS

DDR_A8

DDR_

DQ13

DDR_

DQ10

PB1

PC5

VSS

PB0

PC4

PA7

PB11

PB12

PA6

PC0 PB10 PG11 PG10 PD11

PB8

PF11

PB5

VSS

PG8 PE7

PF7

PF8

PG9

VSS

PF9

PF6

BYPASS

_REG1V8

PE8

USB_

DP2

PG7 PE10

PD13

PB2

PD12

USB_

DP1

PA11

PA12

PA10

DDR_

DQ14

DDR_

DQS1N

DDR_

DQ9

OTG_

VBUS

DDR_

DQ15

DDR_

DQM1

DDR_

DQS1P

USB_

DM2

PB6 VSS

USB_

DM1

DDR_

VREF

DDR_

DQ12

DDR_

DQ11

VSS

MSv47441V2

The above figure shows the package top view.

56/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

VSS

PG15

PD0

PE1 VSS

PE15 VSS

PE6

C PE11 PE13 VSS

VSS PE12 PE14

PD6

PD1

PD7

PE0

VSS

Figure 6. STM32MP153A/DABxx LFBGA354 pinout

PE3

PB7

PD10

VSS

PG6

VSS

PD3

PD4

VSS

PB3

PE5

PA15

PD5

VDD

CORE

PB15

PA8

PA9

VSS

PC7

PC9

PC11

VDD_

Unused

DNU

15 16 17

DNU

VDD1V2_

Unused

DDR_

DQ0

DDR_

DQ1

VSS

PB4

PB14

PB9

VDD

CORE

PD2

PC12

PC6

VSS

PE4

VDDA

1V8_

Unused

DNU DNU DNU

VDD1V2_

Unused

DDR_

DQ3

DDR_

DQ7

DDR_

DQS0N

PC8 VSS VSS VSS VSS VSS VSS

DDR_

DQM0

DDR_

DQS0P

PC10 NJTRST

VDD

CORE

VSS

JTDI

VDD

CORE

JTDO-

TRACE

SWO

JTMS-

SWDIO

JTCK-

SWCLK

DDR_

DQ5

VSS

VDDQ_

DDR

VSS

DDR_

DQ2

DDR_A7

DDR_

DQ4

DDR_

DQ6

F PG12 PD8 PD14

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS_

PLL2

VDDQ_

DDR

VSS DDR_A13 DDR_ZQ DDR_A3

G PD15 VSS PD9 VSS

VDD

CORE

VSS

PC14-

OSC32_

PC15-

OSC32_

OUT

VBAT

NRST

NRST_

CORE

VDD

CORE

VSS

VDD

CORE

VSS VSS_PLL VDD_PLL VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD_

PLL2

VSS

VDDQ_

DDR

DDR_

RESETN

DDR_A9 DDR_A2

DDR_

BA0

VSS

VDDQ_

DDR

VSS

VDD

CORE

DDR_A5 DDR_A0

DDR_

ODT

VSS

VDDQ_

DDR

DDR_

BA2

DDR_

WEN

DDR_

CSN

DDR_

DTO1

K BOOT0 VSS PC13 BOOT1 VSS

PWR_ON BOOT2

VDD_

ANA

VSS_

ANA

PH0-

OSC_IN

PH1-

OSC_

OUT

VREFVDDA

N PDR_ON

_CORE

PDR_ON VREF+ VSSA

VDD

VSS

VDD

PWR_LP PA13

PA14

PE2

VSS

PC2

PA3

PA0

PC3

VDD

VSS

VDD

VSS

VDD

CORE

VSS

VDD

CORE

VDD

VSS

VDD

CORE

VSS

VDDQ_

DDR

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDDQ_

DDR

DDR_A15 DDR_A12

DDR_

RASN

DDR_

CLKP

VDD VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDDQ_

DDR

VSS

DDR_

CASN

DDR_

DTO0

DDR_

CLKN

DDR_A1 DDR_A11 DDR_A10

PA5

PA4

VSS

VSSA VDD

VSSA

PA6

VSS

PA7

VDD

VSS

VDD

PC0

VSS

VDD

VSS

VDD

VSS

VDD

PB5 PB13

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDDQ_

DDR

DDR_A6

DDR_

BA1

DDR_A14

DDR_

ATO

VDD VSS

VDD

CORE

VSS

VDDQ_

DDR

VSS DDR_A4

DDR_

DQ8

DDR_

CKE

VSS

PE7

VDD

PE8

VSS

VDD

CORE

VSS

VDDQ_

DDR

VSS DDR_A8

DDR_

DQ10

PB6 PB2 PG9

BYPASS

_REG1V8

PA10

DDR_

DQ9

DDR_

DQ13

DDR_

DQS1N

PG14 PG13

PB11

VSS

PC1

PA2

VSS

PB1

PB0

PA1 PF11

PC4 PB10

VSS PG8 VSS

PC5 PB12 PG11 PG10 PD11

PB8 PE9 PF7

PF10

PF6

PF9

PF8 PD12 PD13

VSS_

USBHS

VSS_

USBHS

OTG_

VBUS

PE10

PG7

VDDA

1V8_

REG

VSS_

USBHS

USB_

DM2

VDDA

1V1_

REG

VDD3V3_

USBHS

USB_

DP2

PA12

USB_

DP1

VSS_

USBHS

USB_

RREF

VSS

PA11

USB_

DM1

VDD3V3_

USBFS

DDR_

VREF

DDR_

DQ15

DDR_

DQM1

DDR_

DQS1P

DDR_

DQ14

DDR_

DQ12

DDR_

DQ11

VSS

MSv47442V2

The above figure shows the package top view.

DS12502 Rev 6 57/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

VSS

PI3

PZ1

PZ6

PH5

PH15 PH12

PI0

3 4

PE13 PE11

PH10 PH14 PH11

PH13 PD6

PI2

PI7

PZ4

PZ5

PD15

PD9 PC13

PI1

PI5

PZ0

VSS

PZ7

PI4

PI6

PZ3

PI9

PZ2

PD8 PG12

PC15-

OSC32

_OUT

PC14-

OSC32

_IN

PD14 PI8

BOOT2 NRST

NRST_

CORE

PF1

PH4 PE12 PD10

PE15 VSS

PH9

PH8

Figure 7. STM32MP153A/DACxx TFBGA361 pinout

6 7

PD4 PG15

PE14 VSS

PE0

PD5

PF5

1B VDD

CORE

VSS

VDD

CORE

VSS

PA9

PD0

PE1

PF0

VDD

CORE

VSS

VDD

CORE

VSS

PD1

PE3

PF4

VSS

VDD

CORE

VSS

VDD

CORE

PG6

PB9

PE6

PD7

VDD

CORE

VSS

VDD

CORE

VSS

PB3

PC7

PE5

PB7

PB15

VSS

PD2

PA8

PB4

PC12

PF2

PC6

PD3

DNU

PB14

VDDA

1V8_

Unused

DNU

PC10

16 17 18 19 20 21 22 23

DNU

VSS

PC11

DNU

JTDO-

TRACE

SWO

JTDI

DDR_

DQ20

VDD_

Unused

TRST

JTCK-

SWCLK

DDR_

DQ19

VDD

1V2_

Unused

VDD

1V2_

Unused

PA15

PC9 PC8 PE4

DDR_

DQ23

DDR_

DQ16

VSS

DDR_

DQS2N

JTMS-

SWDIO

VSS

DDR_

RESET

DDR_

DQ22

DDR_

DQ3

DDR_

DQS2P

DDR_

DQM2

DDR_

DQ17

DDR_

DQ0

DDR_

DQ18

DDR_

DQ21

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDDQ_

DDR

VSS

VDDQ_

DDR

VSS

VDDQ_

DDR

VDDQ_

DDR

VSS

DDR_

A13

VSS

DDR_

DQ1

DDR_

DQ7

DDR_

DQS0P

DDR_

DQS0N

DDR_

DQ2

DDR_

DQ6

DDR_

DQM0

DDR_

DQ4

DDR_

DQ5

DDR_

DTO0

VSS

DDR_

VDD

CORE

VSS

VDD

CORE

VSS

VDDQ_

DDR

DDR_

DTO1

DDR_

ODT

DDR_

BA0

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDDQ_

DDR

VSS

DDR_

WEN

DDR_

BA2

DDR_

CSN

BOOT0

PH0-

OSC_IN

PH1-

OSC_

OUT

PI10

VSS PI11

PWR_

PA14

PDR_

VREF+

PDR_

ON_

CORE

PG3

PF3

PA13

PA3

PG2

PWR_

BOOT1

ANA0

PA5

ANA1

PA4

VBAT

VSS_

ANA

VDDA

VSS

VDD_

ANA

VSSA

VDD

VSS

VDD

VSS

VDD

VSS

VDD

CORE

VSS

VDD

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDDQ_

DDR

VSS

VDDQ_

DDR

VDDQ_

DDR

VSS

VDDQ_

DDR

DDR_

CASN

DDR_

RASN

DDR_

CLKP

DDR_

CLKN

DDR_

A15

VSS

DDR_

A12

DDR_

A11

DDR_

A14

DDR_

A10

DDR_

CKE

DDR_

DQ8

DDR_

DQ10

DDR_

DQ13

DDR_

BA1

DDR_

DQ9

DDR_

DQS1P

DDR_

DQS1N

DDR_

VSS

DDR_

DQM1

PG1

PE2

PG14

PB11

VSS

PC3

PC2

PG13

PG4

PG0

VSS

PB10

PH3

PA0

PA2

PH7

PF15

PA1

PH2

PF13

VSS

PC0

PF14 PB12

PG5 PG11

PC1

PB0

PB1

PC5

PC4

PB5

VSS

PA7

PA6

DDR_

DQ11

DDR_

DQ14

DDR_

DQ12

PF12

PE9

PG8

PF11

PB13

PB8

PD11

PH6

PE7

PG10

PF8

PF10 PG9 PB6 PE10 PB2 PA10 PD12

DDR_

ATO

DDR_

DQ15

DDR_

DQ25

DDR_

DQ24

VSS

PF7

PF6

BYPAS

S_REG

1V8

PF9

VDDA

1V8_

REG

VDD

3V3_

USBHS

VSS_

USBHS

VDD

3V3_

USBFS

VDDA

1V1_

REG

USB_

DM2

USB_

DM1

PA11

USB_

RREF

PE8 PG7

USB_

DP2

USB_

DP1

PD13

DDR_

DQM3

PA12

OTG_

VBUS

DDR_

DQ27

DDR_

VREF

VSS

DDR_

DQ29

DDR_

DQ31

DDR_

DQ28

DDR_

DQ30

DDR_

DQ26

DDR_

DQS3P

DDR_

DQS3N

VSS

MSv47443V2

The above figure shows the package top view.

58/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

VSS

PH5

3 4

PH4 PE13

PH10 VSS PH11 PE14

PH15 PH14 VSS PE15

PK6

PK7

Figure 8. STM32MP153A/DAAxx LFBGA448 pinout

6 7 8 9 10 11 12 13 14 15 16

PK4

PK3

PJ13

PJ14

PD10

PJ12

PD5

PF1

PE3

PD1

PA9

PD3

PB3

PB15

PB14

VDD_

Unused

DNU

PA8

VDDA

1V8_

Unused

DNU

17 18

DNU

VDD

1V2_

Unused

VDD

1V2_

Unused

VSS

20 21 22

DDR_

DQ20

DDR_

DQ23

VSS

DDR_

DQ19

DDR_

DQ16

DDR_

DQS2N

PE0 PK5 PJ15 VSS PD4 PD0 VSS PE5 PB4 VSS VSS VSS VSS VSS VSS VSS

DDR_

DQS2P

DDR_

DQM2

PI0

PI2

PI7

PZ4

PI13

PJ3

PJ5

PD15

PD8

PI14

PI1

PI5

PZ0

PI12

PJ0

PJ4

PH13

PI3

PI15

PZ6

PZ7

PJ10

VSS

PE12

PZ3

VSS

PZ5

PG12

PJ2

PE11

VSS

PH12

PI6

PZ1

PI9

PZ2

PH8

PH9

VSS

PJ8

PI4

PJ11

PE1

PK1

VSS

PK0

PK2

VSS

PF5 PG15

PE6

PF4

VDD

CORE

PF0

PD7

VSS

PG6

VDD

CORE

PD2

PA15 PC12

PB7 PB9

VSS

PC7

PC6

PF2

VDD

CORE

PC9

PC8

PC10

VSS

PC11 JTDI

JTCK-

SWCLK

VDD_

PLL2

VSS_

PLL2

DDR_

DQ22

DDR_

DQ17

DDR_

DQ18

TRST

JTDO-

TRACE

SWO

JTMS-

SWDIO

VDDQ_

DDR

PE4 VSS

VDDQ_

DDR

DDR_

VDDQ_

DDR

VSS

DDR_

A13

VSS

DDR_

DQ3

DDR_

DQ0

DDR_

DQ21

DDR_

RESET

DDR_

DQ7

VSS

DDR_

DQ1

DDR_

DQM0

DDR_

DQS0N

DDR_

DQS0P

VDD

CORE

VDDQ_

DDR

DDR_

DQ5

DDR_

DQ2

DDR_

DQ6

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VDDQ_

DDR

VSS

DDR_

VSS

DDR_

DQ4

VDDQ_

DDR

DDR_

BA2

DDR_

BA0

DDR_

DTO1

DDR_

PJ9

PD9

PD6 PJ7 PJ6 PJ1

PD14 VBAT

VSS_

PLL

VDD_

PLL

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VSS

VDD

CORE

VDDQ_

DDR

VSS

DDR_

CSN

VSS VSS

DDR_

ODT

DDR_

DTO0

VDDQ_

DDR

DDR_

A15

DDR_

RASN

DDR_

WEN

DDR_

CASN

PI8 PC13 BOOT0 BOOT1

VDD_

ANA

PC14-

OSC32

_IN

PC15-

OSC32

_OUT

NRST_

CORE

NRST

VSS

PA14

BOOT2

ANA0

VSS_

ANA

VDDA

VREF-

VREF+

VSSA

PH0-

OSC_IN

PWR_

PH1-

OSC_

OUT

PDR_

ON_

CORE

PWR_

PDR_

PI11

PC3

PF3

PA3

PG3

PA1

ANA1

PA5

VSS

VSSA

PA4

VSS

PF14

VDD

VSS

PG5

VSS

VDD

VSS

VDD

PF12 PB10

VDD

VSS

VDD

PC0

VSS

VDD

VSS

PG11

PB13 PH6

VDD

CORE

VSS

VDD

PF10

VSS

VDD

CORE

VDD

VSS

PB2

VDD

CORE

VSS

VDD

CORE

VDD

CORE

VDD

PD13

VDD

CORE

VSS

OTG_

VBUS

VDDQ_

DDR

VDDQ_

DDR

VSS

VDDQ_

DDR

VSS

VDDQ_

DDR

VDDQ_

DDR

VSS

VDDQ_

DDR

DDR_

A10

DDR_

A14

DDR_

BA1

DDR_

VSS

DDR_

A12

DDR_

CLKP

DDR_

A11

DDR_

CKE

VSS

DDR_

VSS

DDR_

DQ13

DDR_

DQ11

VSS

DDR_

DQ12

DDR_

CLKN

DDR_

DQ10

DDR_

DQ9

DDR_

DQ14

DDR_

DQ8

DDR_

DQS1N

DDR_

DQM1

DDR_

DQS1P

DDR_

DQ15

DDR_

DQ24

PI10 PH7 PA13 PG2 PG0 PF15 PF13 PF11 PA6 PE7 PE9 PD12 PB6 PE10 PG9 PA12 VSS

VDDQ_

DDR

VSS

DDR_

DQ25

DDR_

DQ31

DDR_

DQ30

PC2

PG13 PG14

VSS

PE2

PA2

VSS

PA0

PC1

PG1 PB11

VSS

PG4

PB1

PB0

PH3

PC5 PB12 PB5 PG10 PF7

PC4

VSS

PH2

PG8 PA7 VSS

PB8 PD11 PF8

PG7 PE8

VSS_

USBHS

VSS_

USBHS

VSS_

USBHS

PA11

PF6

PF9

BYPAS

S_REG

1V8

VSS_

USBHS

VDDA1

V8_

REG

VDD

3V3_

USBHS

USB_

DM2

USB_

DP2

USB_

DP1

USB_

DM1

VSS_

USBHS

VDD

3V3_

USBFS

PA10

USB_

RREF

VDDA

1V1_

REG

VSS

VDDQ_

DDR

VSS

DDR_

DQS3P

DDR_

DQS3N

VSS

DDR_

ATO

DDR_

VREF

DDR_

DQ29

DDR_

DQ27

DDR_

DQ28

DDR_

DQ26

DDR_

DQM3

VSS

MSv47444V2

The above figure shows the package top view.

DS12502 Rev 6 59/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Name

Table 6. Legend/abbreviations used in the pinout table

Abbreviation Definition

Pin name

Pin type

I/O structure

Unless otherwise specified, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

DNU

Output only pin

Input / output pin

Analog or special level pin

Do not use. Used for test purpose during production. Ball should be individually left open and not connected to any other ball, not even to another

DNU ball.

FT(U/D/PD)

DDR

RST

5 V tolerant I/O (with fixed pull-up / pull-down / programmable pull-down)

3.6 V tolerant I/O directly connected to DAC

1.5 V, 1.35 V or 1.2 V I/O for DDR3, DDR3L, LPDDR2/LPDDR3 interface

Analog signal

Reset pin with weak pull-up resistor

Option for TT or FT I/Os

I2C FM+ option _f

(1)

(2)

(3)

(4)

Analog option (supplied by VDDA for the analog part of the I/O)

USB option (supplied by VDD3V3_USBxx for the USB part of the I/O)

High-speed output for 1.8V typ. VDD (for SPI, SDMMC, QUADSPI, TRACE)

_vh

(5)

Very-high-speed option for 1.8V typ. VDD (for ETH, SPI, SDMMC, QUADSPI,

TRACE)

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Notes

Alternate functions

Additional functions

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

are: FT_f, FT_favh, FT_fh, FT_fha, FT_uf

are: FT_a, TT_a, FT_avh, FT_favh, FT_fha, FT_ha, TT_ha

are: FT_u, FT_uf

are: FT_h, FT_fh, FT_fha, FT_ha, TT_ha

are: FT_vh, FT_avh, FT_favh

60/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

1E2 K6 1F3

A1 A1 A1

1B3

1A2

PH5

PH10

PH12

PH13

VDD

VSS

PH14

PH15

PJ8

PI14

PI15

PI0

PI1

PI2

VDDCORE

PI3

PI4

PI5

PI6

I/O FT_f -

I/O FT

I/O FT_f -

I/O

I2C2_SDA, SPI5_NSS,

SAI4_SD_B, EVENTOUT

TIM5_CH1, I2C4_SMBA,

I2C1_SMBA, DCMI_D1, LCD_R4,

EVENTOUT

HDP2, TIM5_CH3, I2C4_SDA,

I2C1_SDA, DCMI_D3, LCD_R6,

EVENTOUT

TIM8_CH1N, UART4_TX,

FDCAN1_TX, LCD_G2,

EVENTOUT

I/O

FT_h

FT_h -

TIM8_CH2N, UART4_RX,

FDCAN1_RX, DCMI_D4,

LCD_G3, EVENTOUT

TIM8_CH3N, DCMI_D11,

LCD_G4, EVENTOUT

TRACED14, TIM1_CH3N,

TIM8_CH1, UART8_TX,

LCD_G1, EVENTOUT

TRACECLK, LCD_CLK,

EVENTOUT

I/O

I/O FT_h -

LCD_G2, LCD_R0, EVENTOUT

TIM5_CH4, SPI2_NSS/I2S2_WS,

DCMI_D13, LCD_G5,

EVENTOUT

TIM8_BKIN2,

SPI2_SCK/I2S2_CK, DCMI_D8,

LCD_G6, EVENTOUT

TIM8_CH4,

SPI2_MISO/I2S2_SDI, DCMI_D9,

LCD_G7, EVENTOUT

I/O

FT_h

FT -

TIM8_ETR,

SPI2_MOSI/I2S2_SDO,

DCMI_D10, EVENTOUT

TIM8_BKIN, SAI2_MCLK_A,

DCMI_D5, LCD_B4, EVENTOUT

TIM8_CH1, SAI2_SCK_A,

DCMI_VSYNC, LCD_B5,

EVENTOUT

TIM8_CH2, SAI2_SD_A,

DCMI_D6, LCD_B6, EVENTOUT

DS12502 Rev 6 61/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

F2 F1

A19 A23 A19

G1 B2

A22

PI7

VSS

PZ1

PZ3

PI9

PZ0

PZ2

PZ4

VSS

PG12

PZ5

VDDCORE

PZ6

PZ7

I/O

I/O FT_fh -

I/O FT_f -

I/O

I/O FT_fh -

I/O FT_f -

I/O FT_h -

I/O FT_f -

TIM8_CH3, SAI2_FS_A,

DCMI_D7, LCD_B7, EVENTOUT

I2C6_SDA, I2C2_SDA,

I2C5_SDA,

SPI1_MISO/I2S1_SDI,

I2C4_SDA, USART1_RX,

SPI6_MISO, EVENTOUT

I2C6_SDA, I2C2_SDA,

I2C5_SDA, SPI1_NSS/I2S1_WS,

I2C4_SDA,

USART1_CTS/USART1_NSS,

SPI6_NSS, EVENTOUT

HDP1, UART4_RX,

FDCAN1_RX, LCD_VSYNC,

EVENTOUT

I2C6_SCL, I2C2_SCL,

SPI1_SCK/I2S1_CK,

USART1_CK, SPI6_SCK,

EVENTOUT

I2C6_SCL, I2C2_SCL,

I2C5_SMBA,

SPI1_MOSI/I2S1_SDO,

I2C4_SMBA, USART1_TX,

SPI6_MOSI, EVENTOUT

I2C6_SCL, I2C2_SCL,

I2C5_SCL, I2C4_SCL,

EVENTOUT

LPTIM1_IN1, SPI6_MISO,

SAI4_CK2,

USART6_RTS/USART6_DE,

SPDIFRX_IN2, LCD_B4,

SAI4_SCK_A, ETH1_PHY_INTN,

FMC_NE4, LCD_B1, EVENTOUT

I2C6_SDA, I2C2_SDA,

I2C5_SDA, I2C4_SDA,

USART1_RTS/USART1_DE,

EVENTOUT

I2C6_SCL, I2C2_SCL,

USART1_CK, I2S1_MCK,

I2C4_SMBA, USART1_RX,

EVENTOUT

I2C6_SDA, I2C2_SDA,

USART1_TX, EVENTOUT

62/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

N1 C3

1D3 E11

C17 C12 C3

B19

1B1

B6 C7

E13

1A4 H11

PI12

VSS

PI13

VDDCORE

PJ10

PJ11

PJ0

PJ1

PJ2

VDD

PJ3

VSS

PJ4

VDDCORE

PJ5

PJ6

PJ7

VSS

PD6

H13 VDDCORE

L2 PJ9

I/O

FT_h

FT_h -

I/O FT_h - TRACED9, LCD_R2, EVENTOUT

I/O FT_h -

TRACED10, LCD_R3,

EVENTOUT

I/O

FT_h -

TRACED11, LCD_R4,

EVENTOUT

S -

TRACED0, HDP0, LCD_HSYNC,

EVENTOUT

TRACED1, HDP1, LCD_VSYNC,

EVENTOUT

TIM1_CH2N, TIM8_CH2,

SPI5_MOSI, LCD_G3,

EVENTOUT

TIM1_CH2, TIM8_CH2N,

SPI5_MISO, LCD_G4,

EVENTOUT

TRACED8, LCD_R7, LCD_R1,

EVENTOUT

I/O

FT_h

TRACED12, LCD_R5,

EVENTOUT

TRACED2, HDP2, LCD_R6,

EVENTOUT

TRACED3, HDP3, TIM8_CH2,

LCD_R7, EVENTOUT

TRACED13, TIM8_CH2N,

LCD_G0, EVENTOUT

I/O

FT_ha

FT_h -

TIM16_CH1N, SAI1_D1,

DFSDM1_CKIN4,

DFSDM1_DATIN1,

SPI3_MOSI/I2S3_SDO,

SAI1_SD_A, USART2_RX,

FMC_NWAIT, DCMI_D10,

LCD_B2, EVENTOUT

TRACED15, TIM1_CH3,

TIM8_CH1N, UART8_RX,

LCD_G2, EVENTOUT

DS12502 Rev 6 63/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

1E1

1C2

1C1

F4 -

1C4 F6 1B1

G2 H1 L2

W1 D1 C21 C8

1A6 -

1D1 H3 1F1 M4

D4 C11

VDD_PLL

VSS_PLL

PD14

PD15

PD8

PD9

VDD

VSS

VDDCORE

VBAT

VSS

PI8

PC13

C19

VSS

PC15-

OSC32_OUT

H15 VDDCORE

VDDCORE

PC14-

OSC32_IN

I/O

S -

I/O FT_a -

TIM4_CH3, SAI3_MCLK_B,

UART8_CTS,

FMC_AD0/FMC_D0, EVENTOUT

TIM4_CH4, SAI3_MCLK_A,

UART8_CTS,

FMC_AD1/FMC_D1, LCD_R1,

EVENTOUT

DFSDM1_CKIN3, SAI3_SCK_B,

USART3_TX, SPDIFRX_IN2,

FMC_AD13/FMC_D13, LCD_B7,

EVENTOUT

DFSDM1_DATIN3, SAI3_SD_B,

USART3_RX,

FMC_AD14/FMC_D14,

DCMI_HSYNC, LCD_B0,

EVENTOUT

I/O

(1)

EVENTOUT

RTC_OUT2/

RTC_LSCO,

TAMP_IN2/

TAMP_OUT3,

WKUP4

RTC_OUT1/

RTC_TS/

RTC_LSCO,

TAMP_IN1/

TAMP_OUT2/

TAMP_OUT3,

WKUP3

OSC32_OUT

The loading conditions used for pin parameter measurement are shown in Figure 9

EVENTOUT

OSC32_IN

64/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

E2 J1

J3 J2

H3 K1

K3 K4

H1 L2 M2

R2 NRST

R1 NRST_CORE

BOOT0

BOOT1

BOOT2

M2 L1

K1 P1

T1 PH0-OSC_IN I/O

C20

VDDCORE

PH1-

OSC_OUT

VSS

I/O

PWR_ON

PWR_LP

PDR_ON_

CORE

PDR_ON

L3 N2 R3

1G2

1G1

VDD_ANA

VSS_ANA

I/O RST -

I RST -

FTPD

L2 P2 N2 W3 PA13 I/O FT_a -

1G4

W5 E2 F21

1F1 M4 1H1 R5

1F2 -

M3 N3 R4

1G1 N4 1H2 R6

PA14

PI11

PI10

VDD

VSS

VDDCORE

VDDA

VREF+

VSSA

I/O

FT_a

EVENTOUT

DBTRGO, DBTRGI, MCO1,

UART4_TX, EVENTOUT

DBTRGO, DBTRGI, MCO2,

EVENTOUT

MCO1, I2S_CKIN, LCD_G6,

EVENTOUT

HDP0,

USART3_CTS/USART3_NSS,

ETH1_GMII_RX_ER/

ETH1_MII_RX_ER,

LCD_HSYNC, EVENTOUT

OSC_IN

OSC_OUT

PWR_ONLP

BOOTFAILN

WKUP5

DS12502 Rev 6 65/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

P3 T3 W2 U3

M3 -

W4 W2

U1 V3

T4 U4

P1 T1 Y1 Y2

E4 H3

N10

N2 P3 U2 T4

P2 T2 Y2 Y1

V2 W4

VSSA

VREF-

PH7

PF3

PC3

PG3

PE2

VDD

VSS

PA3

PC2

PG2

I/O

FT_fh

FT_vh

FT_ha

FT_vh

FT_a

FT_vh

I/O FT_favh -

I/O FT_avh -

I2C3_SCL, SPI5_MISO,

ETH1_GMII_RXD3/

ETH1_MII_RXD3/

ETH1_RGMII_RXD3,

MDIOS_MDC, DCMI_D9,

EVENTOUT

ETH1_GMII_TX_ER, FMC_A3,

EVENTOUT

TRACECLK, DFSDM1_DATIN1,

SPI2_MOSI/I2S2_SDO,

ETH1_GMII_TX_CLK/

ETH1_MII_TX_CLK, EVENTOUT

TRACED3, TIM8_BKIN2,

DFSDM1_CKIN1,

ETH1_GMII_TXD7, FMC_A13,

EVENTOUT

TRACECLK, SAI1_CK1,

I2C4_SCL, SPI4_SCK,

SAI1_MCLK_A,

QUADSPI_BK1_IO2,

ETH1_GMII_TXD3/

ETH1_MII_TXD3/

ETH1_RGMII_TXD3, FMC_A23,

EVENTOUT

TIM2_CH4, TIM5_CH4,

LPTIM5_OUT, TIM15_CH2,

USART2_RX, LCD_B2,

ETH1_GMII_COL/

ETH1_MII_COL, LCD_B5,

EVENTOUT

DFSDM1_CKIN1,

SPI2_MISO/I2S2_SDI,

DFSDM1_CKOUT,

ETH1_GMII_TXD2/

ETH1_MII_TXD2/

ETH1_RGMII_TXD2,

DCMI_PIXCLK, EVENTOUT

TRACED2, MCO2, TIM8_BKIN,

ETH1_GMII_TXD6, FMC_A12,

EVENTOUT

ADC1_INP13,

ADC1_INN12

ADC1_INP15,

PVD_IN

ADC1_INP12,

ADC1_INN11

66/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

R2 U1 AA1 AA2

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

W1 Y4

R3 U2 AA2 AA1

U3 R4

N3 R3 AB3 AA3

T1 U4 AA4 V4

PG14

PG1

PG13

ANA0

PA0

VSS

ANA1

PA1

I/O FT_vh -

A A

I/O FT_ha -

TRACED1, LPTIM1_ETR,

SPI6_MOSI, SAI4_D1,

USART6_TX,

QUADSPI_BK2_IO3,

SAI4_SD_A, ETH1_GMII_TXD1/

ETH1_MII_TXD1/

ETH1_RGMII_TXD1/

ETH1_RMII_TXD1, FMC_A25,

LCD_B0, EVENTOUT

TRACED1, ETH1_GMII_TXD5,

FMC_A11, EVENTOUT

TRACED0, LPTIM1_OUT,

SAI1_CK2, SAI4_CK1,

SPI6_SCK, SAI1_SCK_A,

USART6_CTS/USART6_NSS,

SAI4_MCLK_A,

ETH1_GMII_TXD0/

ETH1_MII_TXD0/

ETH1_RGMII_TXD0/

ETH1_RMII_TXD0, FMC_A24,

LCD_R0, EVENTOUT

ADC1_INP0,

ADC1_INN1,

ADC2_INP0,

ADC2_INN1

TIM2_CH1/TIM2_ETR,

TIM5_CH1, TIM8_ETR,

TIM15_BKIN,

USART2_CTS/USART2_NSS,

UART4_TX, SDMMC2_CMD,

SAI2_SD_B, ETH1_GMII_CRS/

ETH1_MII_CRS, EVENTOUT

ADC1_INP16,

WKUP1

ADC1_INP1,

ADC2_INP1

ETH_CLK, TIM2_CH2,

TIM5_CH2, LPTIM3_OUT,

TIM15_CH1N,

USART2_RTS/USART2_DE,

UART4_RX,

QUADSPI_BK1_IO3,

SAI2_MCLK_B,

ETH1_GMII_RX_CLK/

ETH1_MII_RX_CLK/

ETH1_RGMII_RX_CLK/

ETH1_RMII_REF_CLK, LCD_R2,

EVENTOUT

ADC1_INP17,

ADC1_INN16

DS12502 Rev 6 67/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

1H1

1J1

1F3

AC2

AB1

AB2

AC3

AA6

K21

AB4

AB2

AB3

E19

PA5

PA4

PG0

PB11

PG4

PA2

VDD

PC1

VSS

PG5

F10 1B3 J10 VDDCORE

I/O

TT_ha

TT_a

FT_vh

FT_ha

I/O FT_favh -

TIM2_CH1/TIM2_ETR,

TIM8_CH1N, SAI4_CK1,

SPI1_SCK/I2S1_CK, SPI6_SCK,

SAI4_MCLK_A, LCD_R4,

EVENTOUT

HDP0, TIM5_ETR, SAI4_D2,

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS,

USART2_CK, SPI6_NSS,

SAI4_FS_A, DCMI_HSYNC,

LCD_VSYNC, EVENTOUT

TRACED0, DFSDM1_DATIN0,

ETH1_GMII_TXD4, FMC_A10,

EVENTOUT

TIM2_CH4, LPTIM2_ETR,

I2C2_SDA, DFSDM1_CKIN7,

USART3_RX,

ETH1_GMII_TX_EN/

ETH1_MII_TX_EN/

ETH1_RGMII_TX_CTL/

ETH1_RMII_TX_EN, LCD_G5,

EVENTOUT

TIM1_BKIN2,

ETH1_GMII_GTX_CLK/

ETH1_RGMII_GTX_CLK,

FMC_A14, EVENTOUT

TIM2_CH3, TIM5_CH3,

LPTIM4_OUT, TIM15_CH1,

USART2_TX, SAI2_SCK_B,

SDMMC2_D0DIR, ETH1_MDIO,

MDIOS_MDIO, LCD_R1,

EVENTOUT

TRACED0, SAI1_D1,

DFSDM1_DATIN0,

DFSDM1_CKIN4,

SPI2_MOSI/I2S2_SDO,

SAI1_SD_A, SDMMC2_CK,

ETH1_MDC, MDIOS_MDC,

EVENTOUT

TIM1_ETR,

ETH1_GMII_CLK125/

ETH1_RGMII_CLK125,

FMC_A15, EVENTOUT

ADC1_INP19,

ADC1_INN18,

ADC2_INP19,

ADC2_INN18,

DAC_OUT2

ADC1_INP18,

ADC2_INP18,

DAC_OUT1

ADC1_INP14,

WKUP2

ADC1_INP11,

ADC1_INN10,

ADC2_INP11,

ADC2_INN10,

TAMP_IN3,

WKUP6

68/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

U2 W3 AB6 AB5

Y4 W6

U1 V3 AA7 AA5

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

AA3 Y6

AC4 V7

Y5 W7

AB4 AB7

V1 V4 AB7 AA6

PH3

PB0

PF15

PB1

VSS

PF14

PF13

PH2

PC5

I/O FT_h -

I/O FT_a -

I/O FT_fh -

I/O FT_a -

S -

I/O FT_fha -

I/O FT_ha -

I/O FT_h -

I/O FT_a -

DFSDM1_CKIN4,

QUADSPI_BK2_IO1,

SAI2_MCLK_B,

ETH1_GMII_COL/

ETH1_MII_COL, LCD_R1,

EVENTOUT

TIM1_CH2N, TIM3_CH3,

TIM8_CH2N, DFSDM1_CKOUT,

UART4_CTS, LCD_R3,

ETH1_GMII_RXD2/

ETH1_MII_RXD2/

ETH1_RGMII_RXD2,

MDIOS_MDIO, LCD_G1,

EVENTOUT

TRACED7, I2C4_SDA,

I2C1_SDA, ETH1_GMII_RXD7,

FMC_A9, EVENTOUT

TIM1_CH3N, TIM3_CH4,

TIM8_CH3N, DFSDM1_DATIN1,

LCD_R6, ETH1_GMII_RXD3/

ETH1_MII_RXD3/

ETH1_RGMII_RXD3,

MDIOS_MDC, LCD_G0,

EVENTOUT

TRACED6, DFSDM1_CKIN6,

I2C4_SCL, I2C1_SCL,

ETH1_GMII_RXD6, FMC_A8,

EVENTOUT

TRACED5, DFSDM1_DATIN6,

I2C4_SMBA, I2C1_SMBA,

DFSDM1_DATIN3,

ETH1_GMII_RXD5, FMC_A7,

EVENTOUT

LPTIM1_IN2,

QUADSPI_BK2_IO0,

SAI2_SCK_B, ETH1_GMII_CRS/

ETH1_MII_CRS, LCD_R0,

EVENTOUT

SAI1_D3, DFSDM1_DATIN2,

SAI4_D4, SAI1_D4,

SPDIFRX_IN4,

ETH1_GMII_RXD1/

ETH1_MII_RXD1/

ETH1_RGMII_RXD1/

ETH1_RMII_RXD1, SAI4_D3,

EVENTOUT

ADC1_INP9,

ADC1_INN5,

ADC2_INP9,

ADC2_INN5

ADC1_INP5,

ADC2_INP5

ADC2_INP6,

ADC2_INN2

ADC2_INP2

ADC1_INP8,

ADC1_INN4,

ADC2_INP8,

ADC2_INN4

DS12502 Rev 6 69/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

V2 W4 AC7

M8 -

1D2 E8 P3

1J3 R7 1J2

1E4 -

E10

F12

1G2 E12

Y10

AB8

AC8

1H3

AB5

P21

AB6

J12

U10

F16

PC4

VDD

VSS

VDD

PF12

VDDCORE

PF11

VSS

PA7

VDDCORE

PA6

VDD

PC0

VSS

I/O FT_a -

I/O

I/O FT_ha -

FT_ha

DFSDM1_CKIN2, I2S1_MCK,

SPDIFRX_IN3,

ETH1_GMII_RXD0/

ETH1_MII_RXD0/

ETH1_RGMII_RXD0/

ETH1_RMII_RXD0, EVENTOUT

TRACED4, ETH1_GMII_RXD4,

FMC_A6, EVENTOUT

SPI5_MOSI, SAI2_SD_B,

DCMI_D12, LCD_G5,

EVENTOUT

TIM1_CH1N, TIM3_CH2,

TIM8_CH1N, SAI4_D1,

SPI1_MOSI/I2S1_SDO,

SPI6_MOSI, TIM14_CH1,

QUADSPI_CLK,

ETH1_GMII_RX_DV/

ETH1_MII_RX_DV/

ETH1_RGMII_RX_CTL/

ETH1_RMII_CRS_DV,

SAI4_SD_A, EVENTOUT

TIM1_BKIN, TIM3_CH1,

TIM8_BKIN, SAI4_CK2,

SPI1_MISO/I2S1_SDI,

SPI6_MISO, TIM13_CH1,

MDIOS_MDC, SAI4_SCK_A,

DCMI_PIXCLK, LCD_G2,

EVENTOUT

DFSDM1_CKIN0, LPTIM2_IN2,

DFSDM1_DATIN4, SAI2_FS_B,

QUADSPI_BK2_NCS, LCD_R5,

EVENTOUT

ADC1_INP4,

ADC2_INP4

ADC1_INP6,

ADC1_INN2

ADC1_INP2

ADC1_INP7,

ADC1_INN3,

ADC2_INP7,

ADC2_INN3

ADC1_INP3,

ADC2_INP3

ADC1_INP10,

ADC2_INP10

70/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

1J2

E14

1B5

AC5

AA10

V21

AA7

J14

V10

F20

AA8

U11

PB10

VDDCORE

PB12

VDDCORE

PB13

VSS

PB5

PG11

I/O

FT_fha -

FT_vh

FT_vh -

I/O FT_avh -

TIM2_CH3, LPTIM2_IN1,

I2C2_SCL, SPI2_SCK/I2S2_CK,

DFSDM1_DATIN7, USART3_TX,

QUADSPI_BK1_NCS,

ETH1_GMII_RX_ER/

ETH1_MII_RX_ER, LCD_G4,

EVENTOUT

TIM1_BKIN, I2C6_SMBA,

I2C2_SMBA,

SPI2_NSS/I2S2_WS,

DFSDM1_DATIN1, USART3_CK,

USART3_RX, FDCAN2_RX,

ETH1_GMII_TXD0/

ETH1_MII_TXD0/

ETH1_RGMII_TXD0/

ETH1_RMII_TXD0, UART5_RX,

EVENTOUT

TIM1_CH1N, DFSDM1_CKOUT,

LPTIM2_OUT,

SPI2_SCK/I2S2_CK,

DFSDM1_CKIN1,

USART3_CTS/USART3_NSS,

FDCAN2_TX, ETH1_GMII_TXD1/

ETH1_MII_TXD1/

ETH1_RGMII_TXD1/

ETH1_RMII_TXD1, UART5_TX,

EVENTOUT

ETH_CLK, TIM17_BKIN,

TIM3_CH2, SAI4_D1,

I2C1_SMBA,

SPI1_MOSI/I2S1_SDO,

I2C4_SMBA,

SPI3_MOSI/I2S3_SDO,

SPI6_MOSI, FDCAN2_RX,

SAI4_SD_A, ETH1_PPS_OUT,

UART5_RX, DCMI_D10,

LCD_G7, EVENTOUT

TRACED11, USART1_TX,

UART4_TX, SPDIFRX_IN1,

ETH1_GMII_TX_EN/

ETH1_MII_TX_EN/

ETH1_RGMII_TX_CTL/

ETH1_RMII_TX_EN, DCMI_D3,

LCD_B3, EVENTOUT

DS12502 Rev 6 71/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

1B5

1J4 W7 AA9 W11

V7 T10 AA11 W10

1C3

1H2 E16

1C2

Y11

W6 AB10

AB9

AB11

V11

AB8

P11

AA9

VDDCORE

PH6

VSS

PB8

VDDCORE

PG8

VDD

PG10

VSS

PE9

VDDCORE

PE7

VSS

I/O

FT_h

FT_vh

FT_h

FT_ha

FT_h

I/O FT_favh -

TIM12_CH1, I2C2_SMBA,

SPI5_SCK, ETH1_GMII_RXD2/

ETH1_MII_RXD2/

ETH1_RGMII_RXD2,

MDIOS_MDIO, DCMI_D8,

EVENTOUT

HDP6, TIM16_CH1, TIM4_CH3,

DFSDM1_CKIN7, I2C1_SCL,

SDMMC1_CKIN, I2C4_SCL,

SDMMC2_CKIN, UART4_RX,

FDCAN1_RX, SDMMC2_D4,

ETH1_GMII_TXD3/

ETH1_MII_TXD3/

ETH1_RGMII_TXD3,

SDMMC1_D4, DCMI_D6,

LCD_B6, EVENTOUT

TRACED15,

TIM2_CH1/TIM2_ETR,

ETH_CLK, TIM8_ETR,

SPI6_NSS, SAI4_D2,

USART6_RTS/USART6_DE,

USART3_RTS/USART3_DE,

SPDIFRX_IN3, SAI4_FS_A,

ETH1_PPS_OUT, LCD_G7,

EVENTOUT

TRACED10, UART8_CTS,

LCD_G3, SAI2_SD_B,

QUADSPI_BK2_IO2, FMC_NE3,

DCMI_D2, LCD_B2, EVENTOUT

TIM1_CH1, DFSDM1_CKOUT,

UART7_RTS/UART7_DE,

QUADSPI_BK2_IO2,

FMC_AD6/FMC_D6, EVENTOUT

TIM1_ETR, TIM3_ETR,

DFSDM1_DATIN2, UART7_RX,

QUADSPI_BK2_IO0,

FMC_AD4/FMC_D4, EVENTOUT

72/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

1J7

U10

V8 AB9

U10 AC11 AB10

U14 U11

F11

AC10

1D5 G11 1C4 -

W7 W8 AB12 AA10

Y12

AA5

Y18

AA8

1C6

K11

V12

AA13 AA11

W12

G10

W9 AA14 AB11

K13

PD11

VDDCORE

PF7

PF8

VDDCORE

PF10

VSS

PF6

VDDCORE

PD12

VSS

PF9

VDDCORE

I/O FT_h -

S -

I/O FT_ha -

I/O FT_h -

I/O FT_ha -

I/O FT_fha -

I/O FT_ha -

LPTIM2_IN2, I2C4_SMBA,

I2C1_SMBA,

USART3_CTS/USART3_NSS,

QUADSPI_BK1_IO0,

SAI2_SD_A,

FMC_A16/FMC_CLE,

EVENTOUT

TIM17_CH1, SPI5_SCK,

SAI1_MCLK_B, UART7_TX,

QUADSPI_BK1_IO2, EVENTOUT

TRACED12, TIM16_CH1N,

SPI5_MISO, SAI1_SCK_B,

UART7_RTS/UART7_DE,

TIM13_CH1,

QUADSPI_BK1_IO0, EVENTOUT

TIM16_BKIN, SAI1_D3, SAI4_D4,

SAI1_D4, QUADSPI_CLK,

SAI4_D3, DCMI_D11, LCD_DE,

EVENTOUT

TIM16_CH1, SPI5_NSS,

SAI1_SD_B, UART7_RX,

QUADSPI_BK1_IO3,

SAI4_SCK_B, EVENTOUT

LPTIM1_IN1, TIM4_CH1,

LPTIM2_IN1, I2C4_SCL,

I2C1_SCL,

USART3_RTS/USART3_DE,

QUADSPI_BK1_IO1,

SAI2_FS_A,

FMC_A17/FMC_ALE,

EVENTOUT

TRACED13, TIM17_CH1N,

SPI5_MOSI, SAI1_FS_B,

UART7_CTS, TIM14_CH1,

QUADSPI_BK1_IO1, EVENTOUT

DS12502 Rev 6 73/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

V11 W10 AC14

1E3 F15

1F5

W11 T12

U12 T11 AC13

V12 V10

V13 T13

H10

Y14

Y15

1D1

Y16

U13 U12 AA19

Y11

G12

W13

Y12

W14

K15

V13

V14

PG7

VSS

VDDCORE

PB6

PE8

PE10

VDDCORE

PB2

VDDCORE

PD13

AA12

G14

VDD

VSS

1J8 V16 AB18 AA17 USB_RREF

1H7

W12 AA15 AB13

VDD3V3_

USBHS

VDD3V3_

USB

V10 W13 AC16 AB14 USB_DP2

I/O

FT_h

I/O FT_fha -

I/O FT_h -

I/O FT_ha -

S -

I/O FT_ha -

I/O FT_fha -

TRACED5, SAI1_MCLK_A,

USART6_CK,

UART8_RTS/UART8_DE,

QUADSPI_CLK,

QUADSPI_BK2_IO3, DCMI_D13,

LCD_CLK, EVENTOUT

TIM16_CH1N, TIM4_CH1,

I2C1_SCL, CEC, I2C4_SCL,

USART1_TX, FDCAN2_TX,

QUADSPI_BK1_NCS,

DFSDM1_DATIN5, UART5_TX,

DCMI_D5, EVENTOUT

TIM1_CH1N, DFSDM1_CKIN2,

UART7_TX, QUADSPI_BK2_IO1,

FMC_AD5/FMC_D5, EVENTOUT

TIM1_CH2N, DFSDM1_DATIN4,

UART7_CTS,

QUADSPI_BK2_IO3,

FMC_AD7/FMC_D7, EVENTOUT

TRACED4, RTC_OUT2,

SAI1_D1, DFSDM1_CKIN1,

USART1_RX, I2S_CKIN,

SAI1_SD_A,

SPI3_MOSI/I2S3_SDO,

UART4_RX, QUADSPI_CLK,

EVENTOUT

LPTIM1_OUT, TIM4_CH2,

I2C4_SDA, I2C1_SDA,

I2S3_MCK, QUADSPI_BK1_IO3,

SAI2_SCK_A, FMC_A18,

EVENTOUT

S -

FT_u -

USBH_HS_DP2,

OTG_HS_DP

74/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

W10 V13 AB16 AA14 USB_DM2 A

U13 AA16 Y13 VSS_USBHS S

Y14 VSS_USBHS S

U11 T15 AB13 AA12

BYPASS_

REG1V8

FT_u -

FT -

W8 PG9

1G3

1H5

R10

1H5 V11 AB14 AB12

1H3 G17

1J6 W11 AB15 AB17

VDD

VDDA1V8_

REG

VSS

VDDA1V1_

REG

VSS

G4 AA21 H7

U14

V12 -

1D4 G6 AC1

R12

VDD

Y15 VSS_USBHS S

AA13 VSS_USBHS S

J9 VSS S

V15 AA16 VSS_USBHS S

W14 W14 AB17 AB15 USB_DM1

V14 V14 AC17 AA15 USB_DP1

V15 U16 AB19 W16

T14

Y13

W15

J11

PA12

VSS

VDDCORE

I/O FT_h -

I/O FT_uf -

FT_u -

DBTRGO, USART6_RX,

SPDIFRX_IN4,

QUADSPI_BK2_IO2,

SAI2_FS_B,

FMC_NE2/FMC_NCE,

DCMI_VSYNC, LCD_R1,

EVENTOUT

USBH_HS_DM2,

OTG_HS_DM

TIM1_ETR, I2C6_SDA,

I2C5_SDA, UART4_TX,

USART1_RTS/USART1_DE,

SAI2_FS_B, FDCAN1_TX,

LCD_R5, EVENTOUT

USBH_HS_DM1

USBH_HS_DP1

OTG_FS_DP

DS12502 Rev 6 75/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

U15 V17 AA18 Y16 PA11 I/O FT_uf -

TIM1_CH4, I2C6_SCL,

I2C5_SCL, SPI2_NSS/I2S2_WS,

UART4_RX,

USART1_CTS/USART1_NSS,

FDCAN1_RX, LCD_R4,

EVENTOUT

OTG_FS_DM

1C6 H12

1F4 G10 AC23

1D3 -

W15 AA17 AB16

VDDCORE

VSS

VDD3V3_

USBFS

V16 U15 AC19

U16 T16 Y17

V15

Y17

OTG_VBUS

PA10

A FT_u -

I/O FT_u -

AB20 AB20 DDR_DQ27 I/O DDR -

1B9 E15 1A8 E18 VDDQ_DDR S -

AB21 AB21 DDR_DQ26 I/O DDR -

G12

J13

AC22 AA21

VSS

DDR_DQ28

I/O

DDR -

1H4 G14 1A3 J17 VSS S -

AC21 AA20 DDR_DQ29 I/O DDR -

Y22 W20 DDR_DQ25 I/O DDR -

AB22 Y21 DDR_DQS3P I/O DDR -

H5 J20 VSS S -

AB23 Y22 DDR_DQS3N I/O DDR -

F14 1B7

F17 VDDQ_DDR

AA20 AA22 DDR_DQM3 O

VDDQ_DDR

DDR

AA22 W21

H7 1A5 K3

DDR_DQ31

VSS

I/O

DDR

AA23 W22 DDR_DQ30 I/O DDR -

U9 H9 1A7

Y23

V22

VSS

DDR_DQ24

I/O

DDR -

G16 VDDQ_DDR S -

TIM1_CH3, SPI3_NSS/I2S3_WS,

USART1_RX, MDIOS_MDIO,

SAI4_FS_B, DCMI_D1, LCD_B1,

EVENTOUT

OTG_FS_VBUS,

OTG_HS_VBUS

OTG_FS_ID,

OTG_HS_ID

76/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

L10 VDDCORE

W16 W16 AC20 AB19 DDR_VREF

H11 K10 VSS S -

W17 W18 W23 V20 DDR_DQ12 I/O DDR -

1C5 H13 1B2 K12 VSS S -

V17 W17 Y21 V21 DDR_DQ15 I/O DDR -

H15 K14 VSS S -

U17 V18 W22 U21 DDR_DQ14 I/O DDR -

W18 V19 W21 T20 DDR_DQ11 I/O DDR -

G15 1B9 H17 VDDQ_DDR S -

V19 U19 U22 T22 DDR_DQS1P I/O DDR -

1E5 1B4 L9 VSS S -

U18 T19 U23 R22 DDR_DQS1N I/O DDR -

V18 U18 V22 T21 DDR_DQM1 O DDR -

1D9 J16 VDDQ_DDR S -

T18 T18 T23 R20 DDR_DQ13 I/O DDR -

J3 1B6 VSS S -

U19 T17 U21 R21

1G5 J6 L11

DDR_DQ9

VSS

I/O DDR -

S -

T19 R18 T22 P21 DDR_DQ10 I/O DDR -

H14 VDDQ_DDR S -

R18 P18 T21 N22 DDR_DQ8 I/O DDR -

J8 1B8 L13 VSS

1J5 J10 L17 VSS

1F8 N19 Y19 AA19 DDR_ATO

1C8

1G9 N16 W20 U19

VDDCORE

VDDQ_DDR

DDR_A6

K17 VDDQ_DDR

T17 R17 Y20 U18

J12 1C1 L19

R17 P17 V20 T18

DDR_A8

VSS

DDR_A4

DDR -

DS12502 Rev 6 77/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

1A6 J14 1C3 L20

P17 P19 T20 R19

VSS

DDR_CKE

P18 N17 U20 R18

J15 L16

DDR_BA1

VDDQ_DDR

N18 N18 R21 P18 DDR_A14

K2 M7

N19 M18 R20 P19

K5 1C5 M10

VSS

DDR_A11

VSS

1D6 K7 M12

M17 M19 R22 N18

J9 1D5 L12

1D9 -

M18 L17 P23 N19

M19 M17 P22 M18

VSS

DDR_A10

VDDCORE

VDDQ_DDR

DDR_A12

DDR_A1

K9 1C7 M14 VSS

J19 K17 N20 M22 DDR_CASN

1F6 K11 N9 VSS

J18 J17 M20 M21 DDR_WEN

K14 M17 VDDQ_DDR

1E9 L18 N21 M20 DDR_RASN

L17 L19 N22 N20 DDR_CLKP

K13 1C9 VSS

K18 K19 N23 N21 DDR_CLKN

1F9 1E8 N16 VDDQ_DDR

1D8 K18 K20 L22 DDR_DTO0

1C8 J19 L21 K21 DDR_DTO1

L18 L16 P20 M19 DDR_A15

1H6 1D2 N11 VSS

1E6 -

K15 N13

J17 J18 M22 L18

H18 H19 L22 L21

VDDCORE

VSS

DDR_CSN

DDR_ODT

DDR -

78/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

H17 J16 M21 K18

1C7 L6 1D4 N17

DDR_BA2

VSS

G18 H18 L20 K19

L15 P17

DDR_A0

VDDQ_DDR

G19 G19 L23 K20 DDR_BA0

E17 F17 F20 G18

L8 P3

F17 G18 J20 J18

1E7 L10 1D6 P7

F19 F19 K22 J19

DDR_A13

VSS

DDR_A2

VSS

DDR_A3

C16 G16

M14

1F9

D20

F19

VDDQ_DDR

DDR_

RESETN

R16 VDDQ_DDR

1C9 H17 H20 H19

L12 1D8 P10

DDR_A5

VSS

1A9 E17 E20 F18

L14 P12

1A8 F18 K23 K22

DDR_A7

VSS

DDR_ZQ

DDR

DDR -

A -

E18 G17 G20 H18

1G7 M5 1E1 P14

J11 1D7 L14

D18 E18 J21 J21

M7 P20

D19 D17 J22 H20

W13 M9 1E3 -

C18 D18 H21 H21

DDR_A9

VSS

VDDCORE

DDR_DQ4

VSS

DDR_DQ5

VSS

DDR_DQ2

I/O DDR -

I/O

DDR -

DDR

I/O DDR -

T17 VDDQ_DDR

C19 D19 H22 H22 DDR_DQ6

1G8 VDDQ_DDR

S -

I/O DDR -

S -

B19 C19 G22 G22 DDR_DQS0P I/O DDR -

M11 R8 VSS S -

DDR -

DS12502 Rev 6 79/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

B18 B19 G23 G21 DDR_DQS0N I/O DDR -

N15 VDDQ_DDR S -

C17 C18 H23 G20 DDR_DQM0 O

1H9 U16 VDDQ_DDR S

B17 B18 G21 G19 DDR_DQ7

DDR

I/O DDR -

1B8 M13 1E5 R17

A18 A18 F22 F21

M15 1E7 T7

VSS

DDR_DQ1

VSS

S -

I/O DDR -

S -

A17 A17 E22 E21

B16 B17 E21 E20

DDR_DQ0

DDR_DQ3

P14 1H9 V17 VDDQ_DDR

1H8 -

J13

I/O

DDR

VSS

VDDCORE

E23 E22 DDR_DQ21 I/O DDR -

C14 N8

1E9

D21

T11

D20

T19

VSS

DDR_DQ22

VSS

I/O

S -

DDR

D22 D21 DDR_DQ17 I/O DDR -

D23 D22 DDR_DQ18 I/O DDR -

N10 1F2

W18 VDDQ_DDR

U7 VSS

S -

C22 C21 DDR_DQS2P I/O DDR -

B23 B22 DDR_DQS2N I/O DDR -

R15 1J8

C23

C22

VDDQ_DDR

DDR_DQM2

DDR

Y19

N12 1F4 U13

VDDQ_DDR

VSS

S -

B22 B21 DDR_DQ16 I/O DDR -

1J9 N14

A22 A21 DDR_DQ23 I/O DDR -

U15 VSS S -

B21 B20 DDR_DQ19 I/O DDR -

A21 A20 DDR_DQ20 I/O DDR -

80/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

1J4

P7 1F6 -

VDD

VSS

S -

M11 VDDCORE S -

C15 D15 C20 E17 JTMS-SWDIO I/O FTU -

FTD -

A16 D16 B20 D17 JTCK-SWCLK I

A15 D14 A19 E16

JTDO-

TRACESWO

B15 D13 A20 D16 JTDI I

1G6 K8 1E2 -

B14 D12 B19 E15

VDDCORE

NJTRST

FTU

FTU -

FTU

G13

F13

1B6 B12

C12

C14

C16

D18 VDD_PLL2

D19

B14

C14

VSS_PLL2

VDDA1V8_Un used

VSS

C13 C15

A13 B15 B17 B17

B13 A15 A17 A17

1B7 A16

B12 A14

A12 B14

C14

C17

A16

B16

A18

A16

B16

C16

VSS

DNU

VDD1V2_Unus ed

DNU

DNU DNU

C15

C16

C17

C18

VSS

B11 B13 C15 B15

C12 A13 B15 A15

P8 T13

DNU

VDD

DNU

C13 A12 B18 A14 VDD_Unused S

1A7 B16

D17 P9

C18

B18

U17

VDD1V2_Unus ed

VSS

S -

DS12502 Rev 6 81/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

C11 A11

A10 B11

B10 D11

1D7 K12

K10

C11

P11

A10

G17 P13

D16

D19

D18

1F8

D15

1E4

B13

D17

1G3

D15

F15

PC11

VDDCORE

PE4

M13 VDDCORE

E14

U20

F14

C13

D14

PC8

VSS

PC10

VDDCORE

PB4

PC9

VSS

I/O FT_ha -

S -

I/O FT_h -

I/O FT_ha -

I/O FT_fh -

TRACED3, DFSDM1_DATIN5,

SPI3_MISO/I2S3_SDI,

USART3_RX, UART4_RX,

QUADSPI_BK2_NCS,

SAI4_SCK_B, SDMMC1_D3,

DCMI_D4, EVENTOUT

TRACED1, SAI1_D2,

DFSDM1_DATIN3, TIM15_CH1N,

SPI4_NSS, SAI1_FS_A,

SDMMC2_CKIN,

SDMMC1_CKIN, SDMMC2_D4,

SDMMC1_D4, FMC_A20,

DCMI_D4, LCD_B0, EVENTOUT

TRACED0, TIM3_CH3,

TIM8_CH3, UART4_TX,

USART6_CK,

UART5_RTS/UART5_DE,

SDMMC1_D0, DCMI_D2,

EVENTOUT

TRACED2, DFSDM1_CKIN5,

SPI3_SCK/I2S3_CK,

USART3_TX, UART4_TX,

QUADSPI_BK1_IO1,

SAI4_MCLK_B, SDMMC1_D2,

DCMI_D8, LCD_R2, EVENTOUT

TRACED8, TIM16_BKIN,

TIM3_CH1, SAI4_CK2,

SPI1_MISO/I2S1_SDI,

SPI3_MISO/I2S3_SDI,

SPI2_NSS/I2S2_WS,

SPI6_MISO, SDMMC2_D3,

SAI4_SCK_A, UART7_TX,

EVENTOUT

TRACED1, TIM3_CH4,

TIM8_CH4, I2C3_SDA,

I2S_CKIN, UART5_CTS,

QUADSPI_BK1_IO0,

SDMMC1_D1, DCMI_D3,

LCD_B2, EVENTOUT

82/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

C10

D10

1A5 B10

1G4 P10

P15

1A4

1B4 C10

K17

B11

B14

A14

D12

1E6

A13

C13

D13

1G5

D13 PC7

M15 VDDCORE

E13

F13

D12

V16

B13

A13

E12

V18

PC6

PF2

PD2

VDD

VSS

VDDCORE

PA8

PB14

PC12

VSS

I/O FT_ha -

I/O FT_h -

I/O FT_ha -

I/O FT_fh -

I/O FT_h -

HDP4, TIM3_CH2, TIM8_CH2,

DFSDM1_DATIN3, I2S3_MCK,

USART6_RX,

SDMMC1_D123DIR,

SDMMC2_D123DIR,

SDMMC2_D7, SDMMC1_D7,

DCMI_D1, LCD_G6, EVENTOUT

HDP1, TIM3_CH1, TIM8_CH1,

DFSDM1_CKIN3, I2S2_MCK,

USART6_TX, SDMMC1_D0DIR,

SDMMC2_D0DIR, SDMMC2_D6,

SDMMC1_D6, DCMI_D0,

LCD_HSYNC, EVENTOUT

I2C2_SMBA, SDMMC2_D0DIR,

SDMMC3_D0DIR,

SDMMC1_D0DIR, FMC_A2,

EVENTOUT

TIM3_ETR, I2C5_SMBA,

UART4_RX, UART5_RX,

SDMMC1_CMD, DCMI_D11,

EVENTOUT

MCO1, TIM1_CH1, TIM8_BKIN2,

I2C3_SCL,

SPI3_MOSI/I2S3_SDO,

USART1_CK, SDMMC2_CKIN,

SDMMC2_D4,

OTG_FS_SOF/OTG_HS_SOF,

SAI4_SD_B, UART7_RX,

LCD_R6, EVENTOUT

TIM1_CH2N, TIM12_CH1,

TIM8_CH2N, USART1_TX,

SPI2_MISO/I2S2_SDI,

DFSDM1_DATIN2,

USART3_RTS/USART3_DE,

SDMMC2_D0, EVENTOUT

TRACECLK, MCO2, SAI4_D3,

SPI3_MOSI/I2S3_SDO,

USART3_CK, UART5_TX,

SAI4_SD_B, SDMMC1_CK,

DCMI_D9, EVENTOUT

DS12502 Rev 6 83/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

1F7

L11

B12

C11

A11

A10

D14

B10

B12 PB15

N12 VDDCORE

C12

U12

A12

V19

D11

B11

F12

PE5

VDD

PB3

VSS

PG6

VDDCORE

PD3

PB9

I/O FT_h -

S -

I/O FT_h -

I/O FT_fh -

RTC_REFIN, TIM1_CH3N,

TIM12_CH2, TIM8_CH3N,

USART1_RX,

SPI2_MOSI/I2S2_SDO,

DFSDM1_CKIN2, SDMMC2_D1,

EVENTOUT

TRACED3, SAI1_CK2,

DFSDM1_CKIN3, TIM15_CH1,

SPI4_MISO, SAI1_SCK_A,

SDMMC2_D0DIR,

SDMMC1_D0DIR, SDMMC2_D6,

SDMMC1_D6, FMC_A21,

DCMI_D6, LCD_G0, EVENTOUT

TRACED9, TIM2_CH2,

SAI4_CK1, SPI1_SCK/I2S1_CK,

SPI3_SCK/I2S3_CK, SPI6_SCK,

SDMMC2_D2, SAI4_MCLK_A,

UART7_RX, EVENTOUT

TRACED14, TIM17_BKIN,

SDMMC2_CMD, DCMI_D12,

LCD_R7, EVENTOUT

HDP5, DFSDM1_CKOUT,

SPI2_SCK/I2S2_CK,

DFSDM1_DATIN0,

USART2_CTS/USART2_NSS,

SDMMC1_D123DIR,

SDMMC2_D7,

SDMMC2_D123DIR,

SDMMC1_D7, FMC_CLK,

DCMI_D5, LCD_G7, EVENTOUT

HDP7, TIM17_CH1, TIM4_CH4,

DFSDM1_DATIN7, I2C1_SDA,

SPI2_NSS/I2S2_WS, I2C4_SDA,

SDMMC2_CDIR, UART4_TX,

FDCAN1_TX, SDMMC2_D5,

SDMMC1_CDIR, SDMMC1_D5,

DCMI_D7, LCD_B7, EVENTOUT

84/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

N17

M10

C19

1G7

D11

E11

W17

A11

F11

L13 1F5 N14 VDDCORE

1A3

1J6

D10

B10

C10

W19

A10

F10

PA15

VSS

PA9

PB7

PD1

VDD

PD0

VSS

PE3

PD5

PD7

VDDCORE

I/O FT_h -

S -

I/O FT_h -

I/O FT_fh -

I/O FT_h -

I/O FT_fh -

DBTRGI, TIM2_CH1/TIM2_ETR,

SAI4_D2, SDMMC1_CDIR, CEC,

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS, SPI6_NSS,

UART4_RTS/UART4_DE,

SDMMC2_D5, SDMMC2_CDIR,

SDMMC1_D5, SAI4_FS_A,

UART7_TX, LCD_R1,

EVENTOUT

TIM1_CH2, I2C3_SMBA,

SPI2_SCK/I2S2_CK,

USART1_TX, SDMMC2_CDIR,

SDMMC2_D5, DCMI_D0,

LCD_R5, EVENTOUT

TIM17_CH1N, TIM4_CH2,

I2C1_SDA, I2C4_SDA,

USART1_RX, SDMMC2_D1,

DFSDM1_CKIN5, FMC_NL,

DCMI_VSYNC, EVENTOUT

I2C6_SCL, DFSDM1_DATIN6,

I2C5_SCL, SAI3_SD_A,

UART4_TX, FDCAN1_TX,

SDMMC3_D0, DFSDM1_CKIN7,

FMC_AD3/FMC_D3, EVENTOUT

I2C6_SDA, DFSDM1_CKIN6,

I2C5_SDA, SAI3_SCK_A,

UART4_RX, FDCAN1_RX,

SDMMC3_CMD,

DFSDM1_DATIN7,

FMC_AD2/FMC_D2, EVENTOUT

TRACED0, TIM15_BKIN,

SAI1_SD_B, SDMMC2_CK,

FMC_A19, EVENTOUT

USART2_TX, SDMMC3_D2,

FMC_NWE, EVENTOUT

TRACED6, DFSDM1_DATIN4,

I2C2_SCL, DFSDM1_CKIN1,

USART2_CK, SPDIFRX_IN1,

SDMMC3_D3, FMC_NE1,

EVENTOUT

DS12502 Rev 6 85/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

B1 A2 B7

F18 R12 1H4

1E8 M12 1F7

1A2

R10

R14

N11

C10

1G9

D10

E10

P13

U14

PG15

PE6

VSS

PF0

VDDCORE

PF1

VSS

PF4

VDDCORE

PD4

VDD

PF5

VSS

PD10

P15

VDDCORE

PJ12

PJ13

PJ14

I/O FT_fh -

I/O FT_h -

I/O FT_fh -

I/O FT_h -

I/O

TRACED7, SAI1_D2, I2C2_SDA,

SAI1_FS_A,

USART6_CTS/USART6_NSS,

SDMMC3_CK, DCMI_D13,

EVENTOUT

TRACED2, TIM1_BKIN2,

SAI1_D1, TIM15_CH2,

SPI4_MOSI, SAI1_SD_A,

SDMMC2_D0, SDMMC1_D2,

SAI2_MCLK_B, FMC_A22,

DCMI_D7, LCD_G1, EVENTOUT

I2C2_SDA, SDMMC3_D0,

SDMMC3_CKIN, FMC_A0,

EVENTOUT

I2C2_SCL, SDMMC3_CMD,

SDMMC3_CDIR, FMC_A1,

EVENTOUT

USART2_RX, SDMMC3_D1,

SDMMC3_D123DIR, FMC_A4,

EVENTOUT

SAI3_FS_A,

USART2_RTS/USART2_DE,

SDMMC3_D1, DFSDM1_CKIN0,

FMC_NOE, EVENTOUT

USART2_TX, SDMMC3_D2,

FMC_A5, EVENTOUT

RTC_REFIN, TIM16_BKIN,

DFSDM1_CKOUT, I2C5_SMBA,

SPI3_MISO/I2S3_SDI,

SAI3_FS_B, USART3_CK,

FMC_AD15/FMC_D15, LCD_B3,

EVENTOUT

LCD_G3, LCD_B0, EVENTOUT

LCD_G4, LCD_B1, EVENTOUT

LCD_B2, EVENTOUT

86/256 DS12502 Rev 6

STM32MP153A/D Pinouts, pin description and alternate functions

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

A19 R16 1H6 Y10

1A1

1G6

VSS

PJ15

VDDCORE

PK0

E8 PK2

R11

N13

K19 U3 1H8 Y20

1G8 P12

Y18

VDD

VSS

R14 VDDCORE

B6 PK3

A6 PK4

C6 PK5

VSS

PK6

VDDCORE

PK7

1J3

AA4

1H7 T15

C5 E6

PK1

PE0

PE1

VSS

PH8

VDDCORE

PH9

I/O FT_h -

I/O

I/O FT_h -

I/O

I/O FT_h -

I/O

I/O FT_f -

I/O

LCD_B3, EVENTOUT

TIM1_CH1N, TIM8_CH3,

SPI5_SCK, LCD_G5,

EVENTOUT

TRACED4, TIM1_CH1, HDP4,

TIM8_CH3N, SPI5_NSS,

LCD_G6, EVENTOUT

TRACED5, TIM1_BKIN, HDP5,

TIM8_BKIN, LCD_G7,

EVENTOUT

LCD_B4, EVENTOUT

LCD_B5, EVENTOUT

TRACED6, HDP6, LCD_B6,

EVENTOUT

TRACED7, HDP7, LCD_B7,

EVENTOUT

LCD_DE, EVENTOUT

LPTIM1_ETR, TIM4_ETR,

LPTIM2_ETR,

SPI3_SCK/I2S3_CK,

SAI4_MCLK_B, UART8_RX,

SAI2_MCLK_A, FMC_NBL0,

DCMI_D2, EVENTOUT

LPTIM1_IN2, I2S2_MCK,

SAI3_SD_B, UART8_TX,

FMC_NBL1, DCMI_D3,

EVENTOUT

TIM5_ETR, I2C3_SDA,

DCMI_HSYNC, LCD_R2,

EVENTOUT

TIM12_CH2, I2C3_SMBA,

DCMI_D0, LCD_R3, EVENTOUT

DS12502 Rev 6 87/256

118

Pinouts, pin description and alternate functions STM32MP153A/D

Pin Number

Table 7. STM32MP153A/D pin and ball definitions (continued)

Pin functions

Pin name

(function after reset)

Alternate functions

Additional functions

R13

R19 U8 AA18

U17 1J5 AB1

W19 W1 AB18

W19 1J7 AB22

VDDCORE

PH11

VSS

1B2

1. IO supplied by VSW domain.

PE11

PE12

PE13

PE14

PE15

PH4

I/O

I/O FT_h -

I/O FT_f -

I/O FT_h -

I/O

I/O FT_f -

TIM1_CH2, DFSDM1_CKIN4,

SPI4_NSS, USART6_CK,

SAI2_SD_B,

FMC_AD8/FMC_D8, DCMI_D4,

LCD_G3, EVENTOUT

TIM1_CH3N, DFSDM1_DATIN5,

SPI4_SCK, SDMMC1_D0DIR,

SAI2_SCK_B,

FMC_AD9/FMC_D9, LCD_B4,

EVENTOUT

HDP2, TIM1_CH3,

DFSDM1_CKIN5, SPI4_MISO,

SAI2_FS_B,

FMC_AD10/FMC_D10,

DCMI_D6, LCD_DE, EVENTOUT

TIM5_CH2, I2C4_SCL,

I2C1_SCL, DCMI_D2, LCD_R5,

EVENTOUT

TIM1_CH4, SPI4_MOSI,

UART8_RTS/UART8_DE,

SAI2_MCLK_B,

SDMMC1_D123DIR,

FMC_AD11/FMC_D11, LCD_G0,

LCD_CLK, EVENTOUT

HDP3, TIM1_BKIN, TIM15_BKIN,

USART2_CTS/USART2_NSS,

UART8_CTS, FMC_NCE2,

FMC_AD12/FMC_D12, LCD_R7,

EVENTOUT

I2C2_SCL, LCD_G5, LCD_G4,

EVENTOUT

88/256 DS12502 Rev 6

Port

PA0

PA1

PA2

PA3

PA4

PA5

Port A

PA6

PA7

PA8

PA9

PA10

PA11

PA12

AF0 AF1

HDP/SYS/RTC

TIM1/2/16/17/

LPTIM1/SYS/

RTC

ETH_CLK

HDP0

MCO1

TIM2_CH1/

TIM2_ETR

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM2_CH1/

TIM2_ETR

TIM1_BKIN

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR

Table 8. Alternate function AF0 to AF7 (1)

AF2

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM5_CH4

TIM5_ETR

TIM3_CH1

TIM3_CH2

I2C6_SCL

I2C6_SDA

AF3

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

TIM8_ETR

AF4 AF5

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

TIM15_BKIN -

LPTIM3_OUT TIM15_CH1N

LPTIM4_OUT

LPTIM5_OUT

TIM15_CH1

TIM15_CH2

SAI4_D2

TIM8_CH1N

TIM8_BKIN

TIM8_CH1N

TIM8_BKIN2

SAI4_CK1

SAI4_CK2

SAI4_D1

I2C3_SCL

I2C3_SMBA

I2C5_SCL

I2C5_SDA

SPI1_NSS/

I2S1_WS

SPI1_SCK/I2S1

_CK

SPI1_MISO/

I2S1_SDI

SPI1_MOSI/

I2S1_SDO

SPI3_MOSI/

I2S3_SDO

SPI2_SCK/

I2S2_CK

SPI3_NSS/

I2S3_WS

SPI2_NSS/

I2S2_WS

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

SPI3_NSS/

I2S3_WS

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

USART2_CTS/

USART2_NSS

USART2_RTS/

USART2_DE

USART2_TX

USART2_RX

USART2_CK

UART4_RX

UART4_TX

USART1_CK

USART1_TX

USART1_RX

USART1_CTS/

USART1_NSS

USART1_RTS/

USART1_DE

Port

Port A

PA13

PA14

PA15

PB0

AF0

HDP/SYS/RTC

DBTRGO

DBTRGI

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

DBTRGI

TIM2_CH1/

TIM2_ETR

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

MCO1

MCO2

SAI4_D2

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

SDMMC1_

CDIR

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

CEC

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

SPI1_NSS/

I2S1_WS

TIM1_CH2N TIM3_CH3 TIM8_CH2N -

PB1

PB2

PB3

PB4

Port B

PB5

PB6

PB7

PB8

PB9

PB10

TRACED4

TRACED9

TRACED8

ETH_CLK

HDP6

HDP7

TIM1_CH3N

RTC_OUT2

TIM2_CH2

TIM16_BKIN

TIM17_BKIN

TIM16_CH1N

TIM17_CH1N

TIM16_CH1

TIM17_CH1

TIM2_CH3

TIM3_CH4

SAI1_D1

TIM3_CH1

TIM3_CH2

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

TIM8_CH3N

DFSDM1_

CKIN1

SAI4_D1

DFSDM1_

CKIN7

DFSDM1_

DATIN7

LPTIM2_IN1

USART1_RX

SAI4_CK1

SAI4_CK2

I2C1_SMBA

I2C1_SCL

I2C1_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2S_CKIN

SPI1_SCK/

I2S1_CK

SPI1_MISO/

I2S1_SDI

SPI1_MOSI/

I2S1_SDO

CEC

SDMMC1_

CKIN

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

SPI3_NSS/

I2S3_WS

DFSDM1_

CKOUT

DFSDM1_

DATIN1

SAI1_SD_A

SPI3_SCK/

I2S3_CK

SPI3_MISO/

I2S3_SDI

I2C4_SMBA

I2C4_SCL

I2C4_SDA

I2C4_SCL

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

SPI6_NSS

I2C4_SDA

DFSDM1_

DATIN7

SPI3_MOSI/

I2S3_SDO

SPI2_NSS/

I2S2_WS

SPI3_MOSI/

I2S3_SDO

USART1_TX

USART1_RX

SDMMC2_

CKIN

SDMMC2_

CDIR

USART3_TX

Port

PB11

PB12

Port B PB13

PB14

AF0

HDP/SYS/RTC

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

PB15 RTC_REFIN

PC0

PC1

PC2

Port C PC3

PC4

PC5

PC6

TRACED0

TRACECLK

HDP1

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

I2C6_SMBA

TIM12_CH1

TIM12_CH2

SAI1_D1

SAI1_D3

TIM3_CH1

LPTIM2_ETR

DFSDM1_

CKOUT

TIM8_CH2N

TIM8_CH3N

DFSDM1_

CKIN0

DFSDM1_

DATIN0

DFSDM1_

CKIN1

DFSDM1_

DATIN1

DFSDM1_

CKIN2

DFSDM1_

DATIN2

TIM8_CH1

I2C2_SDA

I2C2_SMBA

LPTIM2_OUT

USART1_TX

USART1_RX

LPTIM2_IN2

DFSDM1_

CKIN4

SAI4_D4

DFSDM1_

CKIN3

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

SPI2_MISO/

I2S2_SDI

SPI2_MOSI/

I2S2_SDO

SPI2_MOSI/

I2S2_SDO

SPI2_MISO/

I2S2_SDI

SPI2_MOSI/

I2S2_SDO

I2S1_MCK

I2S2_MCK

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

DFSDM1_

CKIN7

DFSDM1_

DATIN1

DFSDM1_

CKIN1

DFSDM1_

DATIN2

DFSDM1_

CKIN2

DFSDM1_

DATIN4

SAI1_SD_A

DFSDM1_

CKOUT

USART3_RX

USART3_CK

USART3_CTS/

USART3_NSS

USART3_RTS/

USART3_DE

SAI1_D4

USART6_TX

Port

PC7

PC8

PC9

PC10

Port C

PC11

PD1

Port D

PD2

PD3

PD4

PD5

AF0

HDP/SYS/RTC

HDP4

TRACED0

TRACED1

TRACED2

TRACED3

PC12 TRACECLK

PC13

PC14

PC15

PD0

HDP5

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

TIM3_CH2

TIM3_CH3

TIM3_CH4

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

TIM8_CH2

TIM8_CH3

TIM8_CH4

DFSDM1_

CKIN5

DFSDM1_

DATIN5

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

DFSDM1_

DATIN3

I2C3_SDA

I2S_CKIN

MCO2 SAI4_D3 -

I2C6_SDA

I2C6_SCL

TIM3_ETR

DFSDM1_

CKIN6

DFSDM1_

DATIN6

DFSDM1_

CKOUT

I2C5_SDA

I2C5_SCL

I2C5_SMBA

SPI2_SCK/

I2S2_CK

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

I2S3_MCK

UART4_TX

SPI3_SCK/

I2S3_CK

SPI3_MISO/

I2S3_SDI

SPI3_MOSI/

I2S3_SDO

SAI3_SCK_A

USART6_RX

USART6_CK

USART3_TX

USART3_RX

USART3_CK

SAI3_SD_A

UART4_RX

DFSDM1_

DATIN0

SAI3_FS_A

USART2_CTS/

USART2_NSS

USART2_RTS/

USART2_DE

USART2_TX

Port

PD6

PD7

PD8

PD9

TRACED6

Port D PD10 RTC_REFIN

PD11

PD12

PD13

PD14

PD15

PE0

Port E

PE1

PE2

PE3

AF0

HDP/SYS/RTC

TRACECLK

TRACED0

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

TIM16_CH1N

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

SAI1_D1

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

DFSDM1_

DATIN1

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

SPI3_MOSI/

I2S3_SDO

TIM16_BKIN -

DFSDM1_

CKIN4

DFSDM1_

DATIN4

DFSDM1_

CKIN3

DFSDM1_

DATIN3

DFSDM1_

CKOUT

I2C2_SCL

I2C5_SMBA

SPI3_MISO/

I2S3_SDI

LPTIM2_IN2 I2C4_SMBA I2C1_SMBA

LPTIM1_IN1

LPTIM1_OUT

LPTIM1_ETR

LPTIM1_IN2

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

TIM4_ETR

SAI1_CK1

LPTIM2_IN1

I2C4_SCL

I2C4_SDA

LPTIM2_ETR

I2C4_SCL

TIM15_BKIN

I2C1_SCL

I2C1_SDA

SPI3_SCK/

I2S3_CK

I2S2_MCK

SPI4_SCK

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

SAI1_SD_A

DFSDM1_

CKIN1

SAI3_SCK_B

SAI3_SD_B

SAI3_FS_B

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

USART2_RX

USART2_CK

USART3_TX

USART3_RX

USART3_CK

I2S3_MCK

SAI3_MCLK_B

SAI3_MCLK_A

USART3_CTS/

USART3_NSS

USART3_RTS/

USART3_DE

SAI4_MCLK_B

SAI3_SD_B

SAI1_MCLK_A

SAI1_SD_B

Port

PE4

PE5

PE6

PE7

PE8

PE9

Port E

PE10

PE11

PE12

PE13

PE14

PE15

Port F

PF0

PF1

AF0

HDP/SYS/RTC

TRACED1

TRACED3

TRACED2

HDP2

HDP3

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

TIM1_BKIN2

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

SAI1_D2

SAI1_CK2

SAI1_D1

TIM3_ETR

DFSDM1_

DATIN3

DFSDM1_

CKIN3

DFSDM1_

DATIN2

DFSDM1_

CKIN2

DFSDM1_

CKOUT

DFSDM1_

DATIN4

DFSDM1_

CKIN4

DFSDM1_

DATIN5

DFSDM1_

CKIN5

TIM15_CH1N

TIM15_CH1

TIM15_CH2

SPI4_NSS

SPI4_MISO

SPI4_MOSI

SPI4_NSS

SPI4_SCK

SPI4_MISO

SPI4_MOSI

TIM1_BKIN TIM15_BKIN -

I2C2_SDA

I2C2_SCL -

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

SAI1_FS_A

SAI1_SCK_A

SAI1_SD_A

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

SDMMC2_

CKIN

SDMMC2_

D0DIR

SDMMC2_D0

UART7_RX

UART7_TX

UART7_RTS/

UART7_DE

UART7_CTS

USART6_CK

USART2_CTS/

USART2_NSS

Port

PF8

Port F

PF9

PF10

PF11

PF12

PF2

PF3

PF4

PF5

PF6

PF7

PF13

PF14

PF15

PG0

Port G

PG1

PG2

AF0

HDP/SYS/RTC

TRACED12

TRACED13

TRACED4

TRACED5

TRACED6

TRACED7

TRACED0

TRACED1

TRACED2

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

TIM16_CH1

TIM17_CH1

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

I2C2_SMBA

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

SPI5_NSS

SPI5_SCK

TIM16_CH1N

TIM17_CH1N

TIM16_BKIN

MCO2

SAI1_D3

SAI4_D4

DFSDM1_

DATIN6

DFSDM1_

CKIN6

DFSDM1_

DATIN0

TIM8_BKIN

I2C4_SMBA

I2C4_SCL

I2C4_SDA

SPI5_MISO

SPI5_MOSI

I2C1_SMBA

I2C1_SCL

I2C1_SDA

AF6 AF7

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

SAI1_SD_B

SAI1_MCLK_B

SAI1_SCK_B

SAI1_FS_B

SAI1_D4

DFSDM1_

DATIN3

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

USART2_RX

USART2_TX

UART7_RX

UART7_TX

UART7_RTS/

UART7_DE

UART7_CTS

Port

PG3

PG4

PG5

PG6

PG7

PG8

TRACED3

TRACED14

TRACED5

TRACED15

Port G

PG9 DBTRGO

PG10 TRACED10

PG11 TRACED11

PG12 -

PG13

PG14

PG15

Port H

PH0

PH1

PH2

AF0

HDP/SYS/RTC

TRACED0

TRACED1

TRACED7

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

TIM1_BKIN2

TIM1_ETR

TIM17_BKIN

TIM2_CH1/

TIM2_ETR

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

ETH_CLK

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

TIM8_BKIN2

TIM8_ETR

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

DFSDM1_

CKIN1

USART1_TX

SPI6_NSS

LPTIM1_IN1

LPTIM1_OUT

LPTIM1_ETR

LPTIM1_IN2

SAI1_CK2

SAI1_D2

SAI4_CK1

I2C2_SDA

SPI6_MISO

SPI6_SCK

SPI6_MOSI

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

SAI4_CK2

SAI1_SCK_A

SAI1_MCLK_A USART6_CK

SAI4_D2

USART6_RTS/

USART6_DE

USART6_RX

UART4_TX -

USART6_RTS/

USART6_DE

USART6_CTS/

USART6_NSS

SAI4_D1

SAI1_FS_A

USART6_TX

USART6_CTS/

USART6_NSS

Port

PH3

Port H

PH4

PH5

PH6

PH7

PH8

PH9

PH10

PH11

PH12

PH13

PH14

PH15

PI0

Port I

PI1

PI2

PI3

HDP2

AF0

HDP/SYS/RTC

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

TIM12_CH1

TIM5_ETR

TIM12_CH2

TIM5_CH1

TIM5_CH2

TIM5_CH3

DFSDM1_

CKIN4

TIM8_CH1N

TIM8_CH2N

TIM8_CH3N

I2C2_SCL

I2C2_SDA

I2C2_SMBA

I2C3_SCL

I2C3_SDA

I2C3_SMBA

I2C4_SMBA

I2C4_SCL

I2C4_SDA

TIM5_CH4

TIM8_BKIN2

TIM8_CH4

TIM8_ETR -

SPI5_NSS

SPI5_SCK

SPI5_MISO

I2C1_SMBA

I2C1_SCL

I2C1_SDA

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

SPI2_MISO/

I2S2_SDI

SPI2_MOSI/

I2S2_SDO

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

Port

Port I

Port J

PI11

PI12

PI13

PI14

PI15

PJ0

PJ1

PJ2

PJ3

PJ4

PJ5

PJ6

PJ7

PI4

PI5

PI6

PI7

PI8

PI9

PI10

HDP1

HDP0

MCO1

TRACED0

TRACED1

TRACECLK

TRACED8

TRACED9

TRACED10

TRACED11

TRACED12

TRACED2

TRACED3

TRACED13

AF0

HDP/SYS/RTC

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

HDP0

HDP1

HDP2

HDP3

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

TIM8_BKIN

TIM8_CH1

TIM8_CH2

TIM8_CH3

TIM8_CH2

TIM8_CH2N

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

I2S_CKIN

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

Port

Port J

Port K

PJ15

PK0

PK1

PK2

PK3

PK4

PK5

PK6

PK7

PJ8

PJ9

PJ10

PJ11

PJ12

PJ13

PJ14

PZ0

Port Z

PZ1

TRACED14

TRACED15

TRACED4

TRACED5

TRACED6

TRACED7

AF0

HDP/SYS/RTC

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

TIM1_CH3N

TIM1_CH3

TIM1_CH2N

TIM1_CH2

TIM1_CH1N

TIM1_CH1

TIM1_BKIN

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

HDP4

HDP5

HDP6

HDP7

I2C6_SCL

I2C6_SDA

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

TIM8_CH1

TIM8_CH1N

TIM8_CH2

TIM8_CH2N

TIM8_CH3

TIM8_CH3N

TIM8_BKIN

I2C2_SCL

I2C2_SDA

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

I2C5_SDA

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

SPI5_MOSI

SPI5_MISO

SPI5_SCK

SPI5_NSS

SPI1_SCK/

I2S1_CK

SPI1_MISO/

I2S1_SDI

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

USART1_CK

I2C4_SDA USART1_RX

Port

PZ2

AF0

HDP/SYS/RTC

PZ3

Port Z

PZ4

PZ5

PZ6

PZ7

1. Refer to

Table 9 for AF8 to AF15.

AF1

TIM1/2/16/17/

LPTIM1/SYS/

RTC

Table 8. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

SAI1/4/I2C6/

TIM3/4/5/12/

HDP/SYS

I2C6_SCL

I2C6_SDA

I2C6_SCL

SAI4/I2C2/

TIM8/

LPTIM2/3/4/5/

DFSDM1

/SDMMC1

I2C2_SCL

I2C2_SDA

I2C2_SCL

SAI4/

I2C1/2/3/4/5/

USART1/

TIM15/LPTIM2/

DFSDM1/CEC

I2C5_SMBA

I2C5_SDA

I2C5_SCL

SPI1/I2S1/

SPI2/I2S2/

SPI3/I2S3/

SPI4/5/6/I2C1/

SDMMC1/3/

CEC

SPI1_MOSI/

I2S1_SDO

SPI1_NSS/

I2S1_WS

I2C6_SDA

I2C6_SCL

I2C6_SDA

I2C2_SDA

I2C2_SCL

I2C2_SDA

I2C5_SDA

USART1_CK

I2S1_MCK

AF6

SPI3/I2S3/

SAI1/3/4/

I2C4/UART4/

DFSDM1

AF7

SPI2/I2S2/

SPI3/I2S3/

SPI6/

USART1/2/3/6/

UART7/

SDMMC2

I2C4_SMBA

I2C4_SDA

I2C4_SCL

I2C4_SDA

I2C4_SMBA

USART1_TX

USART1_CTS/

USART1_NSS

USART1_RTS/

USART1_DE

USART1_RX

USART1_TX

AF8 AF9

Table 9. Alternate function AF8 to AF15 (1)

AF10 AF11 AF12 AF13 AF14

Port

Port A

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

UART5/LCD

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

UART4_TX

UART4_RX

SAI2_SCK_B

SPI6_NSS

SPI6_SCK

SPI6_MISO

SPI6_MOSI

SDMMC2_CMD

QUADSPI_

BK1_IO3

SAI2_SD_B

SAI2_MCLK_B

ETH1_GMII_

CRS/

ETH1_MII_CRS

ETH1_GMII_RX

_CLK/

ETH1_MII_RX_

CLK/

ETH1_RGMII_

RX_CLK/

ETH1_RMII_

REF_CLK

LCD_R2

SDMMC2_

D0DIR

ETH1_MDIO

LCD_B2

TIM13_CH1

ETH1_GMII_

COL/

ETH1_MII_COL

MDIOS_MDC

TIM14_CH1 QUADSPI_CLK

ETH1_GMII_RX

_DV/

ETH1_MII_RX_

DV/

ETH1_RGMII_

RX_CTL/

ETH1_RMII_

CRS_DV

MDIOS_MDIO

SAI4_FS_A

SAI4_MCLK_A -

SAI4_SCK_A DCMI_PIXCLK

SAI4_SD_A

DCMI_HSYNC LCD_VSYNC

LCD_R1

LCD_B5

LCD_R4

LCD_G2

AF15

SYS

EVENTOUT

Port

Port A

PA8

PA9

SDMMC2_

CKIN

SDMMC2_

CDIR

PA10

PA11 -

PA12 SAI2_FS_B

PA13

PA14

PA15

UART4_TX

UART4_RTS/

UART4_DE

Port B

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

PB0 UART4_CTS

PB1

PB2

PB3

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SDMMC2_D4

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

OTG_FS_SOF/

OTG_HS_SOF

AF11

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

AF12

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

SAI4_SD_B

AF13

UART7_RX

SDMMC2_D5 DCMI_D0

FDCAN1_RX

FDCAN1_TX

SDMMC2_D5

LCD_R3

LCD_R6

UART4_RX QUADSPI_CLK

SPI6_SCK SDMMC2_D2

SDMMC2_

CDIR

MDIOS_MDIO

SDMMC1_D5

SAI4_FS_B

SAI4_FS_A

ETH1_GMII_

RXD2/

ETH1_MII_

RXD2/

ETH1_RGMII_

RXD2

ETH1_GMII_

RXD3/

ETH1_MII_

RXD3/

ETH1_RGMII_

RXD3

MDIOS_MDIO

MDIOS_MDC

SAI4_MCLK_A

DCMI_D1

UART7_TX

UART7_RX

AF14

UART5/LCD

LCD_R6

LCD_R5

LCD_B1

LCD_R4

LCD_R5

LCD_R1

LCD_G1

LCD_G0

AF15

SYS

EVENTOUT

Port

PB4

PB5

PB6

PB7

PB8

Port B

PB9

PB10

PB11

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

SPI6_MISO

SPI6_MOSI

UART4_RX

UART4_TX

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SDMMC2_D3

FDCAN2_RX

FDCAN2_TX

FDCAN1_RX

FDCAN1_TX

QUADSPI_

BK1_NCS

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI4_SD_A

QUADSPI_BK1

_NCS

SDMMC2_D1

SDMMC2_D4

SDMMC2_D5

ETH1_PPS_

OUT

DFSDM1_

DATIN5

DFSDM1_

CKIN5

ETH1_GMII_

TXD3/

ETH1_MII_

TXD3/

ETH1_RGMII_

TXD3

SDMMC1_CDI

ETH1_GMII_

RX_ER/

ETH1_MII_

RX_ER

ETH1_GMII_

TX_EN/

ETH1_MII_

TX_EN/

ETH1_RGMII_

TX_CTL/

ETH1_RMII_

TX_EN

SAI4/UART5/

FMC/SDMMC1/

MDIOS

SAI4_SCK_A

UART5_RX

UART5_TX

FMC_NL

SDMMC1_D4

SDMMC1_D5

UART7/DCMI/

LCD/RNG

UART7_TX

DCMI_D10

DCMI_D5

DCMI_VSYNC

DCMI_D6

DCMI_D7

AF14

UART5/LCD

LCD_G7

LCD_B6

LCD_B7

LCD_G4

LCD_G5

AF15

SYS

EVENTOUT

Port

Port B

Port C

PB12 USART3_RX

PB13

PB14

PB15

PC0

PC1

PC2

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

SAI2_FS_B

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

FDCAN2_RX

FDCAN2_TX

SDMMC2_D0

SDMMC2_D1

SDMMC2_CK

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

ETH1_GMII_

TXD0/

ETH1_MII_

TXD0/

ETH1_RGMII_

TXD0/

ETH1_RMII_

TXD0

ETH1_GMII_

TXD1/

ETH1_MII_

TXD1/

ETH1_RGMII_

TXD1/

ETH1_RMII_

TXD1

QUADSPI_BK2

_NCS

ETH1_MDC

ETH1_GMII_

TXD2/

ETH1_MII_

TXD2/

ETH1_RGMII_

TXD2

SAI4/UART5/

FMC/SDMMC1/

MDIOS

MDIOS_MDC

UART7/DCMI/

LCD/RNG

DCMI_PIXCLK

AF14

UART5/LCD

UART5_RX

UART5_TX

LCD_R5

AF15

SYS

EVENTOUT

Port

Port C

PC3

PC4

PC5

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

PC6

PC7

PC8

SDMMC1_

D0DIR

SDMMC1_

D123DIR

UART5_RTS/

UART5_DE

PC9 UART5_CTS

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

SPDIFRX_IN3

SPDIFRX_IN4 -

ETH1_GMII_

TX_CLK/

ETH1_MII_

TX_CLK

ETH1_GMII_

RXD0/

ETH1_MII_

RXD0/

ETH1_RGMII_

RXD0/

ETH1_RMII_

RXD0

ETH1_GMII_

RXD1/

ETH1_MII_

RXD1/

ETH1_RGMII_

RXD1/

ETH1_RMII_

RXD1

SAI4_D3 -

SDMMC2_

D0DIR

SDMMC2_

D123DIR

QUADSPI_BK1

_IO0

SDMMC2_D6

SDMMC2_D7

SDMMC1_D6

SDMMC1_D7

SDMMC1_D0

SDMMC1_D1

DCMI_D0

DCMI_D1

DCMI_D2

DCMI_D3

AF14

UART5/LCD

LCD_HSYNC

LCD_G6

LCD_B2

AF15

SYS

EVENTOUT

Port

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

PC10 UART4_TX

PC11 UART4_RX

Port C

PC12 UART5_TX

PC13

PC14

PC15

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

QUADSPI_

BK1_IO1

QUADSPI_

BK2_NCS

SAI4_MCLK_B

SAI4_SCK_B

SAI4_SD_B

SDMMC1_D2

SDMMC1_D3

SDMMC1_CK

DCMI_D8

DCMI_D4

DCMI_D9

AF14

UART5/LCD

LCD_R2

AF15

SYS

EVENTOUT

Port

PD0

PD1

PD2

PD3

Port D

PD4

PD5

PD6

PD7

PD8

PD9

UART4_TX

UART5_RX

SDMMC1_

D123DIR

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

UART4_RX

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

FDCAN1_RX SDMMC3_CMD

FDCAN1_TX

SDMMC3_D0

DFSDM1_

DATIN7

DFSDM1_

CKIN7

FMC_AD2/

FMC_D2

FMC_AD3/

FMC_D3

SDMMC1_CMD DCMI_D11

SDMMC2_D7

SDMMC2_

D123DIR

SDMMC1_D7 FMC_CLK DCMI_D5

SPDIFRX_IN2

SDMMC3_D1

SDMMC3_D2

SPDIFRX_IN1 SDMMC3_D3

DFSDM1_

CKIN0

FMC_NOE

FMC_NWE

FMC_NWAIT

FMC_NE1

FMC_AD13/

FMC_D13

FMC_AD14/

FMC_D14

DCMI_D10

DCMI_HSYNC

AF14

UART5/LCD

LCD_G7

LCD_B2

LCD_B7

LCD_B0

AF15

SYS

EVENTOUT

Port

PD10

PD11

Port D

PD12

PD13

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

PD14 UART8_CTS

PD15 UART8_CTS

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

QUADSPI_

BK1_IO3

SAI2_SD_A

SAI2_FS_A

SAI2_SCK_A -

FMC_AD15/

FMC_D15

FMC_A16/

FMC_CLE

FMC_A17/FMC

_ALE

FMC_A18 -

FMC_AD0/

FMC_D0

FMC_AD1/

FMC_D1

AF14

UART5/LCD

LCD_B3

LCD_R1

AF15

SYS

EVENTOUT

Port

Port E

PE0

PE1

PE2

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

UART8_RX

UART8_TX

PE3

PE4

SDMMC1_

CKIN

PE5

SDMMC1_

D0DIR

PE6 SDMMC1_D2

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

QUADSPI_

BK1_IO2

SDMMC2_CK

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

SAI2_MCLK_A

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

ETH1_GMII_

TXD3/

ETH1_MII_

TXD3/

ETH1_RGMII_

TXD3

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

FMC_NBL0

FMC_NBL1

FMC_A23

FMC_A19

DCMI_D2

DCMI_D3

SDMMC2_D4 SDMMC1_D4 FMC_A20 DCMI_D4

SDMMC2_D6

SAI2_MCLK_B

SDMMC1_D6

FMC_A21

FMC_A22

DCMI_D6

DCMI_D7

AF14

UART5/LCD

LCD_B0

LCD_G0

LCD_G1

AF15

SYS

EVENTOUT

Port

PE7

PE8

PE9

PE10

Port E PE11

PE12

PE13

PE14

PF0

Port F PF1

PF2

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

SDMMC1_

D0DIR

UART8_RTS/

UART8_DE

PE15 UART8_CTS

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

QUADSPI_

BK2_IO0

QUADSPI_

BK2_IO1

QUADSPI_

BK2_IO2

QUADSPI_

BK2_IO3

SAI2_SD_B

SAI2_SCK_B

SAI2_FS_B

SAI2_MCLK_B

FMC_NCE2

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SDMMC1_

D123DIR

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

FMC_AD4/

FMC_D4

FMC_AD5/

FMC_D5

FMC_AD6/

FMC_D6

FMC_AD7/

FMC_D7

FMC_AD8/

FMC_D8

FMC_AD9/

FMC_D9

FMC_AD10/

FMC_D10

FMC_AD11/

FMC_D11

FMC_AD12/

FMC_D12

DCMI_D4

DCMI_D6

LCD_G0

SDMMC3_D0

SDMMC3_CMD

SDMMC2_

D0DIR

SDMMC3_

CKIN

SDMMC3_

CDIR

SDMMC3_

D0DIR

SDMMC1_

D0DIR

FMC_A0

FMC_A1

FMC_A2 -

AF14

UART5/LCD

LCD_G3

LCD_B4

LCD_DE

LCD_CLK

LCD_R7

AF15

SYS

EVENTOUT

Port

PF3

PF4

PF5

PF6

PF7

Port F

PF8

PF9

PF10

PF11

PF12

PF13

PF14

Port F PF15

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

ETH1_GMII_

TX_ER

FMC_A3 -

SDMMC3_D1

SDMMC3_

D123DIR

FMC_A4

FMC_A5 -

SDMMC3_D2

QUADSPI_

BK1_IO3

QUADSPI_

BK1_IO2

SAI4_SCK_B

TIM13_CH1

TIM14_CH1

QUADSPI_CLK

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

SAI2_SD_B

SAI4_D3

DCMI_D11

DCMI_D12

ETH1_GMII_

RXD4

ETH1_GMII_

RXD5

ETH1_GMII_

RXD6

ETH1_GMII_

RXD7

FMC_A6

FMC_A7

FMC_A8

FMC_A9 -

AF14

UART5/LCD

LCD_DE

LCD_G5

AF15

SYS

EVENTOUT

AF8 AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

Port

Port G

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

PG0

PG1

PG2

PG3

PG4

PG5 -

PG6

PG7

PG8

PG9

UART8_RTS/

UART8_DE

USART3_RTS/

USART3_DE

QUADSPI_CLK

SPDIFRX_IN3

SPDIFRX_IN4

QUADSPI_

BK2_IO2

SDMMC2_CMD

SAI4_FS_A

SAI2_FS_B

ETH1_GMII_

TXD4

ETH1_GMII_

TXD5

ETH1_GMII_

TXD6

ETH1_GMII_

TXD7

ETH1_GMII_

GTX_CLK/

ETH1_RGMII_

GTX_CLK

ETH1_GMII_

CLK125/

ETH1_RGMII_

CLK125

QUADSPI_

BK2_IO3

ETH1_PPS_

OUT

SAI4/UART5/

FMC/SDMMC1/

MDIOS

FMC_A10

FMC_A11

FMC_A12

FMC_A13

FMC_A14

FMC_A15

FMC_NE2/FMC

_NCE

UART7/DCMI/

LCD/RNG

DCMI_D12

DCMI_D13

DCMI_VSYNC

AF14

UART5/LCD

LCD_R7

LCD_CLK

LCD_G7

LCD_R1

AF15

SYS

EVENTOUT

Port

Port G

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

PG10 UART8_CTS

PG11 SPDIFRX_IN1

PG12 SPDIFRX_IN2

PG13

PG14 -

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

LCD_G3

LCD_B4

QUADSPI_

BK2_IO3

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI2_SD_B

SAI4_SCK_A

SAI4_MCLK_A

SAI4_SD_A

QUADSPI_

BK2_IO2

ETH1_GMII_

TX_EN/

ETH1_MII_

TX_EN/

ETH1_RGMII_

TX_CTL/

ETH1_RMII_

TX_EN

ETH1_PHY_

INTN

ETH1_GMII_

TXD0/

ETH1_MII_

TXD0/

ETH1_RGMII_

TXD0/

ETH1_RMII_

TXD0

ETH1_GMII_

TXD1/

ETH1_MII_

TXD1/

ETH1_RGMII_

TXD1/

ETH1_RMII_

TXD1

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

FMC_NE3

FMC_NE4

FMC_A24

FMC_A25

DCMI_D2

DCMI_D3

AF14

UART5/LCD

LCD_B2

LCD_B3

LCD_B1

LCD_R0

LCD_B0

AF15

SYS

EVENTOUT

AF8

Port

Port G PG15

PH0

PH1

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

PH2

PH3

Port H

PH4

PH5

PH6

PH7

PH8

AF9

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

QUADSPI_

BK2_IO0

QUADSPI_

BK2_IO1

LCD_G5

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SDMMC3_CK

SAI2_SCK_B

SAI2_MCLK_B

ETH1_GMII_

CRS/

ETH1_MII_CRS

ETH1_GMII_

COL/

ETH1_MII_COL

ETH1_GMII_

RXD2/

ETH1_MII_

RXD2/

ETH1_RGMII_

RXD2

ETH1_GMII_

RXD3/

ETH1_MII_

RXD3/

ETH1_RGMII_

RXD3

SAI4/UART5/

FMC/SDMMC1/

MDIOS

SAI4_SD_B

MDIOS_MDIO

MDIOS_MDC

UART7/DCMI/

LCD/RNG

DCMI_D13

DCMI_D8

DCMI_D9

DCMI_HSYNC

AF14

UART5/LCD

LCD_R0

LCD_R1

LCD_G4

LCD_R2

AF15

SYS

EVENTOUT

Port

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

Port H

Port I

PI4

PI5

PI6

PI7

PI0

PI1

PI2

PI3

PI8

PI9

PH9

PH10

PH11 -

PH12 -

PH13 UART4_TX

PH14 UART4_RX

PH15 -

UART4_RX

PI10

USART3_CTS/

USART3_NSS

AF9

FDCAN1_TX

FDCAN1_RX

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

SAI2_MCLK_A

SAI2_SCK_A

SAI2_SD_A

SAI2_FS_A

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10

AF11

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

ETH1_GMII_

RX_ER/

ETH1_MII_

RX_ER

AF12 AF13

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

DCMI_D0

DCMI_D1

DCMI_D2

DCMI_D3

DCMI_D4

DCMI_D11

DCMI_D13

DCMI_D8

DCMI_D9

DCMI_D10

DCMI_D5

DCMI_VSYNC

DCMI_D6

DCMI_D7

AF14

UART5/LCD

LCD_R3

LCD_R4

LCD_R5

LCD_R6

LCD_G2

LCD_G3

LCD_G4

LCD_G5

LCD_G6

LCD_G7

LCD_B4

LCD_B5

LCD_B6

LCD_B7

LCD_VSYNC

LCD_HSYNC

AF15

SYS

EVENTOUT

Port

Port I

Port J

PJ6

PJ7

PJ8

PJ9

PJ2

PJ3

PJ4

PJ5

PJ10

PJ11

PJ12

PJ13

PJ14

PI11

PI12

PI13

PI14

PI15

PJ0

PJ1

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

UART8_TX

UART8_RX

AF9

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

LCD_G6

LCD_G2

LCD_R7

LCD_G3

LCD_G4

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

AF14

UART5/LCD

LCD_HSYNC

LCD_VSYNC

LCD_CLK

LCD_R0

LCD_R1

LCD_R2

LCD_R3

LCD_R4

LCD_R5

LCD_R6

LCD_R7

LCD_G0

LCD_G1

LCD_G2

LCD_G3

LCD_G4

LCD_B0

LCD_B1

LCD_B2

AF15

SYS

EVENTOUT

Port

AF8

SPI6/SAI2/

USART3/

UART4/5/8/

SDMMC1/2/

SPDIFRX

Port J PJ15

PK0

PK1

Port K

PK2

PK3

PK4

PK5

Port Z

PZ2

PZ3

PZ4

PZ5

PK6

PK7

PZ0

PZ1

PZ6

PZ7

1. Refer to

Table 8 for AF0 to AF7.

SPI6_SCK

SPI6_MISO

SPI6_MOSI

SPI6_NSS

AF9

FDCAN1/2/

TIM13/14/

QUADSPI/

SDMMC2/3/

LCD/SPDIFRX

Table 9. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

SAI2/4/

QUADSPI/

FMC/

SDMMC2/3/

OTG_FS/

OTG_HS

DFSDM1/

QUADSPI/

SDMMC1/

MDIOS/ETH1

SAI4/UART5/

FMC/SDMMC1/

MDIOS

UART7/DCMI/

LCD/RNG

AF14

UART5/LCD

LCD_B3

LCD_G5

LCD_G6

LCD_G7

LCD_B4

LCD_B5

LCD_B6

LCD_B7

LCD_DE

AF15

SYS

EVENTOUT

Memory mapping

5 Memory mapping

STM32MP153A/D

Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals.

118/256 DS12502 Rev 6

STM32MP153A/D

6 Electrical characteristics

Electrical characteristics

6.1

6.1.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on

100% of the devices with an junction temperature at T

J selected temperature range).

= 25 °C and T

= T

Jmax

(given by the

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ).

6.1.2

6.1.3

6.1.4

Typical values

Unless otherwise specified, typical data are based on T

= 25 °C, V

1.2 V. They are given only as design guidelines and are not tested.

= 3.3 V, V

DDCORE

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

Loading capacitor

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 10 .

Figure 9. Pin loading conditions Figure 10. Pin input voltage

Device pin Device pin

C = 50 pF

MSv47493V1

DS12502 Rev 6

MSv47494V1

119/256

234

Electrical characteristics

6.1.6 Power supply scheme

Figure 11. Power supply scheme

STM32MP153A/D

DDR

PHY

1V1 regulator

USB HS

PHY

Core domain

1V8 regulator

USB FS

IOs

DDCORE

IOports

IOs

BKUP

IOs

IO logic

(MPU, peripherals,

RAM)

(MCU, peripherals,

RAM)

(System logic, Peripherals)

DD_ANA

)

IOports

BAT

DD_PLL

SS_PLL

VDD

IOs

IO logic

PLLs

HSI, CSI, HSE,

LSI, WKUP,

IWDG

Power switch

VDD domain

VSW domain

Retention regulator

IO logic

RET

Backup regulator

BKP

Power switch

Retention

RAM

Backup domain

LSE, RTC, AWU,

Tamper, backup registers, Reset

Retention domain

Backup RAM

DDA

REF+

REF-

SSA

REF_BUF

Analog domain

ADC, DAC

REF+

REF-

MSv46560V3

Caution: Each power supply pair (V

, V

DDCORE

, V

DDA

SSA

...) must be decoupled with filtering ceramic capacitors. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.

This might cause incorrect operation of the device.

120/256 DS12502 Rev 6

STM32MP153A/D

6.1.7

Electrical characteristics

The number of needed capacitances and their values are provided in AN5031 “Getting started with STM32MP1 Series hardware development” available from the ST website www.st.com

Current consumption measurement

Figure 12. Current consumption measurement scheme

DD_CORE

DDCORE

DD_VBAT

BAT

6.2

DDA

DD_ANA

DD_PLL

MSv50921V2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 10: Voltage characteristics

Table 11: Current characteristics

, and

Table 12: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Symbols

DDX

- V

SSX

Table 10. Voltage characteristics (1)

Ratings Min

External main supply voltage (including V

DD_ANA

REF+

)

, V

DD_PLL

, V

DDA

, V

DD3V3_USB

, V

BAT

, -0.3

External core supply voltage -0.3

Max

3.9

1.5

Unit

DDCORE

DDA_DDR

DDA1V8

DDR IO supply voltage

1.8 V supply (V

DDA1V8_REG

)

-0.3

1.98

3.9

DS12502 Rev 6 121/256

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Electrical characteristics STM32MP153A/D

Symbols

Table 10. Voltage characteristics (continued) (1)

Ratings Min Max Unit

(2)

Input voltage on FT_xxx pins

Input voltage on TT_xx pins

Input voltage on OTG_VBUS pin

Input voltage on USB/OTG_HS_DP/DM pins

Input voltage on OTG_FS_DP/DM pins

Input voltage on any other pins

- 0.3

Min(V

, V

DDA

BAT

) +3.9

3.9

6.0

(5)

5.25

5.5

3.9

| ∆ V

DDX

Variations between different V

DDX the same domain

power pins of

50 mV

SSx

-V

REF+

- V

DDA

Variations between all the different ground pins

Allowed voltage difference for V

REF+

> V

DDA

0.4

1. All power (V , V , V

DD3V3_USB

, V

DDCORE

, V

BAT

) and ground (V

, V connected to the external/internal power supply, in the permitted range.

SSA

, V

SSX

) pins must always be

2. V

maximum must always be respected. Refer to

Table 49

for the maximum allowed injected current values.

3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.

4. To sustain a voltage higher than 3.9 V the internal pull-up/pull-down resistors must be disabled.

5. Voltage should be also below Min(V

, V

DD3V3_USBFS

) + 3.9 V

Symbols

Table 11. Current characteristics

Ratings Max Unit

ΣIV

ΣI

ΣIV

(PIN)

Total current into sum of all V

power lines (source)

(1)

Total current out of sum of all V

ground lines (sink)

Maximum current into each V

power pin (source)

Maximum current out of each V

ground pin (sink)

Table 10: Voltage characteristics

Output current sunk by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins

(2)

Total output current sourced by sum of all I/Os and control pins

(2)

440

100

140

140 mA

INJ(PIN)

(3)(4)

Injected current on FT_xxx, TT_xx, NRST pins except PA4, PA5 -5/+0

ΣI

INJ(PIN)

Injected current on PA4, PA5

Total injected current (sum of all I/Os and control pins)

(5)

-0/0

±25

1. All power (V

, V

DDA

, V

DD3V3_USB

, V

DDCORE

) and ground (V

, V

SSA

, V

SSX

) pins must always be

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins.

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. A positive injection is induced by V

while a negative injection is induced by V

SS values.

. I

INJ(PIN)

must never be exceeded. Refer also to

for the maximum allowed input voltage

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STM32MP153A/D Electrical characteristics

5. When several inputs are submitted to a current injection, the maximum ∑I positive and negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the

STG

Symbol

Table 12. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature (suffix 1)

Maximum junction temperature (suffix 3)

Value

-65 to +150

105

125

Unit

°C

6.3 Operating conditions

6.3.1

Symbol

F mpuss_ck

F mcu_ck

F pclk1

F pclk2

F pclk3

F pclk4

F pclk5

DD_ANA

(3)

DD_PLL

DD_PLL2

(4)

General operating conditions

F axiss_ck

, F hclk5

F hclk6

Table 13. General operating conditions

Parameter Operating conditions Min.

Cortex-A7 subsystem

STM32MP153A

STM32MP153D

Internal AXI, AHB5,

AHB6 clock frequency

Internal MCU AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Internal APB3 clock frequency

Internal APB4 clock frequency

Internal APB5 clock frequency

I/Os and embedded regulators (REG1V1,

REG1V8) supply voltage

SYSCFG_IOCTRLSETR = 0

SYSCFG_IOCTRLSETR ≠ 0

System analog supply voltage

1.71

(1)(2)

1.71

PLL supply voltage 1.71

Typ

Max.

650

800

266

Unit

209

104.5

MHz

104.5

133

3.6

2.7

3.6

DS12502 Rev 6 123/256

234

Electrical characteristics STM32MP153A/D

Symbol

Table 13. General operating conditions (continued)

Parameter Operating conditions

DDCORE

DDA

Digital core domain supply voltage

Analog operating voltage

Run mode

(F mpuss_ck

above 650 MHz) (5)

Run mode

(F mpuss_ck

up to 650 MHz)

Stop, LP-Stop mode

LPLV-Stop mode

Standby mode

ADC used with V

REF

< 2 V

ADC used with V

REF

> 2 V

DAC used

VREFBUF with V

REF

= 1.5 V

(7)

VREFBUF with V

REF and ADC used

= 1.5 V

VREFBUF with V

REF

= 1.8 V (8)

VREFBUF with V

REF

= 2.048 V

VREFBUF with V

REF

= 2.5 V

ADC, DAC, V

REF

not used

64 KB retention SRAM not used

DD3V3_USBFS

(9)

BAT

DDQ_DDR

(11)

DDA1V8_REG

Backup operating voltage

USB FS I/O supply voltage

USB HS I/O supply voltage

USB I/O supply voltage

64 KB retention SRAM used

USB OTG FS used

USB OTG FS not used

USBH or USB OTG HS used

USBH and USB OTG HS not used

USB used

USB not used

DDR3 memory

DDR PHY supply voltage

DDR3L memory

LPDDR2 or LPDDR3

USB HS PHY voltage supply with 1.8 V regulator in bypass mode

BYPASS_REG1V8 = V

Min.

1.30

1.18

1.8

1.65

1.10

0.85

1.62

1.8

3.07

1.425

1.283

1.14

2.1

2.35

2.8

1.2

1.4

3.07

Typ

1.34

1.20

0.90

3.3

1.5

1.35

1.2

1.8

3.3

Max.

1.38

Unit

3.6

1.575

1.45

1.3

1.25

(6)

0.75

3.6

1.95

124/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Symbol

Table 13. General operating conditions (continued)

Parameter Operating conditions Min.

Typ Max.

Unit

VIN

I/O Input voltage

TTxa I/O

OTG_VBUS I/O

DDR I/O

USB HS I/O

All I/O except TTxa

Junction temperature range

Suffix 1 version

Suffix 3 version

-0.3

-1

-0.3

-20

-40

+0.3

6 (12)

DDQ_DDR

5.25

See

(13)

105

125

V o

1. Once nRST is released functionality is guaranteed down to V

BOR

falling edge max.

2. Min V

is 2.25 V when REG1V8 is used BYPASS_REG1V8 = 0.

3. Should be connected to same power supply voltage as V

4. It is recommended to connect V

DD_PLL

and V

DD_PLL2

to same power supply as V

5. Only for STM32MP153Dxx1 devices

6. 1.25 V is the max allowed voltage, however LPLV-Stop mode is only relevant for V

DDCORE

up to 0.95 V. In LPLV-Stop mode, if VDDQ_DDR is not shutdown, to avoid overconsumption on VDDQ_DDR, the DDR memory must be put in

SelfRefresh and DDR PHY must be set in retention mode (setting bit DDRRETEN: DDR retention enable of PWR control register 3 (PWR_CR3)).

7. DAC cannot be used with V

REF

below 1.8 V.

8. ADC cannot be used with V

REF

below 2 V and V

DDA

above 2 V.

9. Depending on package selected, either V

DD3V3_USBFS

and V

DD3V3_USBHS

or only V

DD3V3_USB

are available.

10. For operation with voltage higher than Min (V must be disabled.

, V

DDA

, V

DD3V3_USBFS

) + 0.3 V, the internal Pull-up and Pull-Down resistors

11. Independent from any other supply, see details in

Section 3.7.1: Power supply scheme .

12. Min(V

, V

DD3V3_USBFS

) + 3.6 V < 6 V.

13. Min(V

, V

DDA

, V

DD3V3_USBFS

) + 3.6 V < 5.5 V. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.

6.3.2 Operating conditions at power-up / power-down

Subject to general operating conditions.

DS12502 Rev 6 125/256

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Electrical characteristics STM32MP153A/D

Symbol

Table 14. Operating conditions at power-up / power-down

Parameter Min Max Unit t t

VDD

(1)

VDDA

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

DD3V3_USBxx

rise time rate

∞

∞ t

VDD3V3_USB

(2) t

VDD3V3_USBHS t

VDD3V3_USBFS

DD3V3_USBxx

fall time rate

∞

µs/V t

VDDCORE

DDCORE

rise time rate (from reset to RUN mode)

DDCORE

rise time rate (from

LPLV-Stop to RUN mode)

2000

1000

(3)

(4)

DDCORE

fall time rate 7.33

∞

1. V

must be present before V

DDCORE

2. V

DDA1V8_REG

must be present before V

DD3V3_USBHS

3. In case V

DDCORE

rise time is larger than 2 ms/V, user should control the NRST_CORE signal with a Power

Good (PG) control signal from the external regulator to avoid dysfunction of the device due to V potentially not yet established when internal reset signal is de-activated after t and

Figure 13

VDDCORETEMPO

DDCORE

(cf.

Table 14

4. In case V to V

DDCORE case, the V

rise time at exit of LPLV-Stop is larger than 1 ms/V, there is a risk of unwanted reset due

potentially not yet established after t

DDCORE

SEL_VDDCORETEMPO

(cf.

Table 14 and

Figure 14

). In such a supply should not be decreased during LPLV-Stop mode.

Figure 13. V

DDCORE

rise time from reset average rise time rate should be less than t

VDDCORE

Max (from reset to Run mode)

DDCORE

DDCORE should be above

DDCORE

Min when vddcore_ok is enabled

DDCORE

Min

PVDCORE_0

(rising edge) t t

VDDCORETEMPO pvdcore_out vddcore_ok

Run mode

DDCORE

Min = V

PVDCORE_0

Min (rising edge) + t

VDDCORETEMPO

Min / t

VDDCORE

Max

MSv47497V2

126/256 DS12502 Rev 6

STM32MP153A/D

DDCORE

Min

PVDCORE_1

(falling edge)

Electrical characteristics

Figure 14. V

DDCORE

rise time from LPLV-Stop average rise time rate should be less than t

VDDCORE

Max (from LPLV-Stop to Run mode)

DDCORE

DDCORE should be above

DDCORE

Min at the end of t

SEL_VDDCORETEMPO t t

SEL_VDDCORETEMPO

PWR_LP

LPLV-

Stop mode

Wait Run mode

DDCORE

Min = V

PVDCORE_1

Min (falling edge) + t

VSEL_VDDCORETEMPO

Min / t

VDDCORE

Max

MSv47499V2

6.3.3 Embedded reset and power control block characteristics

The parameters given in

Table 15 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in Table 13: General operating

Symbol t

RSTTEMPO

(1)

BOR0

BOR1

BOR2

BOR3

PVD0

Table 15. Embedded reset and power control block characteristics

Parameter Conditions Min Typ

Reset temporization. after

BOR0 released

377

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Programmable Voltage

Detector threshold 0

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

1.62

1.58

2.055

1.955

2.355

2.255

2.655

2.555

1.905

1.805

2.4

2.3

2.7

2.6

1.67

1.63

2.1

1.95

1.85

Max

550

1.71

1.67

2.145

2.045

2.445

2.345

2.745

2.645

1.995

1.895

Unit

µs

DS12502 Rev 6 127/256

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Electrical characteristics STM32MP153A/D

Table 15. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6 hyst_BOR0

Programmable Voltage

Detector threshold 1

Programmable Voltage

Detector threshold 2

Programmable Voltage

Detector threshold 3

Programmable Voltage

Detector threshold 4

Programmable Voltage

Detector threshold 5

Programmable Voltage

Detector threshold 6

Hysteresis voltage of BOR0

DD_BOR_PVD

(1)(3)

V hyst_BOR hyst_BOR_PVD

AVM_0

AVM_1

AVM_2

Hysteresis voltage of BOR Unless BOR0

Hysteresis voltage of BOR

(unless BOR0) and PVD

(2)

BOR (unless BOR0) and PVD consumption from V

Hysteresis in

RUN mode

Analog voltage (V

DDA threshold 0

) detector

Rising edge

Falling edge

Analog voltage (V

DDA threshold 1

) detector

Rising edge

Falling edge

Analog voltage (V

DDA threshold 2

) detector

Rising edge

Falling edge

VDD_AVM

VDDA_AVM

The parameters given in Table 16

AVM_3 hyst_VDDA

PVDCORE_0

(4)

Analog voltage (V

DDA threshold 3

) detector

Rising edge

Falling edge

Hysteresis of analog voltage

DDA

) detector

Analog Voltage Monitoring

DDA

) consumption on V

Analog Voltage Monitoring

DDA

) consumption on V

DDA

Digital core domain supply voltage (V

DDCORE threshold 0 (Run)

) detector

Resistor bridge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge in

RUN mode

Hysteresis in

RUN mode

2.055

1.955

2.205

2.105

2.355

2.255

2.505

2.405

2.655

2.555

2.805

2.705

0.246

1.655

1.555

2.055

1.955

2.455

2.355

2.755

2.655

0.95

0.91

2.4

2.3

2.55

2.45

2.1

2.25

2.15

2.7

2.6

2.85

2.75

100

1.7

1.6

2.1

2.5

2.4

2.8

2.7

100

2.12

0.995

0.955

2.795

0.626

1.745

1.645

2.145

2.045

2.545

2.445

2.845

2.745

2.145

2.045

2.295

2.195

2.445

2.345

2.595

2.495

2.745

2.645

2.895

0.248

1.04

Unit

V mV mV mV

µA mV

µA

128/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Table 15. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit t t

PVDCORE_1

SEL_VDDCORETE

MPO

(5) hyst_VDDCORE

VDDCORETEMPO

Digital core domain supply voltage (V

DDCORE

) detector threshold 1 (LPLV_Stop)

Hysteresis of Digital core domain supply voltage

DDCORE

) detector

Tempo on VPVDCORE_0 at rising edge of V

DDCORE ensure that V

DDCORE established

is fully

Tempo on V

PVDCORE_1 edge of V

DDCORE

at rising

to ensure that

is fully established on exit of LPLV-Stop mode

DDCORE

Voltage Monitoring consumption on V

USB Threshold voltage

Falling edge

0.71

200

234

1.7

0.755

340

380

2.6

0.8

550

606

4.2

V mV

µs

µA

USB_VTH 1.21

1. Guaranteed by design.

2. No hysteresis when using PVD_IN pin.

3. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables.

4. During the first rising edge of V the end of the t

VDDCORETEMPO

DDCORE

, the slope should be less than 2 ms/V to ensure V

DDCORE

is fully established before

5. When exiting from LPLV-Stop mode to RUN mode the rising slope for V

DDCORE

is fully established before the end of the t

VDDCORETEMPO

DDCORE

should be less than 1 ms/V to ensure

6.3.4 Embedded reference voltage

, Table 17 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in Table 13: General operating

Symbol

REFINT t

S_vrefint

(1)(2) t

S_vbat

The parameters given in Table 18

t start_vrefint

I refbuf

(2)

Table 16. Embedded reference voltage

Parameter Conditions Min

Internal reference voltages

ADC sampling time when reading the internal reference voltage

-40 °C < TJ < 125 °C

BAT

sampling time when reading the internal V

BAT reference voltage

Start time of reference voltage buffer when ADC is enable

Reference Buffer consumption for ADC

DDA

= 3.3 V

1.175

4.3

9.8

0.8

9.1

Typ

1.210

13.6

Max

1.241

4.6

27.7

Unit

µs

µA

DS12502 Rev 6 129/256

234

Electrical characteristics

Symbol

Table 16. Embedded reference voltage (continued)

Parameter Conditions Min

ΔV

REFINT

(2) coeff_VREFINT

Internal reference voltage spread over the temperature range

Average temperature coefficient

-40 °C < T

< 125 °C

Average temperature coefficient

DDcoeff

Average Voltage coefficient 3.0 V < V

< 3.6 V -

1. The shortest sampling time for the application can be determined by multiple iterations.

2. Guaranteed by design.

Typ

4.3

STM32MP153A/D

Max

Unit mV

1370 ppm/°C ppm/V

Symbol

Table 17. Embedded reference voltage calibration value

Parameter Memory address

REFIN_CAL

Raw data acquired at temperature of 30 °C, V

DDA

= V

REF+

= 3.3 V 0x5C00 5250[31:16]

(1)(2)

1. Mandatory to read in 32-bits word and do relevant mask and shift to isolate required bits.

2. These address is inside BSEC which should be enabled in RCC to allow access.

6.3.5 Embedded regulators characteristics

, Table 19 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in Table 13: General operating

REG1V1 embedded regulator (USB_PHY)

Symbol

Table 18. REG1V1 embedded regulator (USB_PHY) characteristics

(1)

Parameter Condition Min Typ Max

I t

DDA1V1_

REG

L esr load

START

INRUSH

VDD

Regulated output voltage -

Load Capacitor

Equivalent Serial Resistor of Cload

Static load current

(3)

Start-up time. from

PWR_CR3.REG11EN = 1 to

PWR_CR3.REG11RDY = 1

Inrush Current to load external capacitor at start

=2.2uF

=3.3uF

Regulator Current consumption on

Regulator Enabled and I load

0 mA

Regulator Enabled and I load

30 mA

1.045

1.1

0.1

1.1

2.2

(2)

150

176

1.155

3.3

600

180

205

242

1. Guaranteed by design.

2. For better dynamic performances a 2.2 μF typical value external capacitor is recommended.

3. Load is for internal STM32MP153A/D analog blocks, no additional external load is accepted unless mentioned.

Unit

µF mΩ mA

µs mA

µA

130/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

REG1V8 embedded regulator (USB)

Symbol

Table 19. REG1V8 embedded regulator (USB) characteristics

(1)

Parameter Condition Min Typ Max

I t

DDA1V8_

REG

L esr load

START

INRUSH

VDD

Regulator input voltage

Regulated output voltage after trimming

Load Capacitor

Equivalent Serial Resistor of Cload

Static load current

(3)

Start-up time. from

PWR_CR3.REG11EN = 1 to

PWR_CR3.REG11RDY = 1

=2.2uF

=3.3uF

Inrush Current to load external capacitor at start

Regulator Current consumption on

Regulator Enabled and I load

0 mA

Regulator Enabled and I load

70 mA

2.25

1.7

0.5

0.1

3.3

1.8

2.2

(2)

130

170

3.6

1.9

3.3

600

150

100

181

231

1. Guaranteed by design.

2. For better dynamic performances a 2.2 μF typical value external capacitor is recommended.

3. Load is for internal STM32MP153A/D analog blocks, no additional external load is accepted unless mentioned.

Unit

µF mΩ mA

µs mA

µA

6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 12: Current consumption measurement scheme

All the Run mode current consumption measurements given in this section are performed with a CoreMark code unless otherwise specified.

Typical and maximum current consumption

The device is placed under the following conditions:

• All I/O pins are in analog input mode except when explicitly mentioned.

• All peripherals are disabled except when explicitly mentioned.

• The maximum values are obtained for V

BAT the typical values for V specified.

BAT

= 3.6 V and V

= 3.3 V and V

DDCORE

= 1.25 V, and

= 1.2 V unless otherwise

The parameters given in

Table 21 to

Table 25 are derived from tests performed under

supply voltage conditions summarized in Table 13: General operating conditions

DS12502 Rev 6 131/256

234

Symbol Parameter

DDCORE

Supply current in

Run mode

DDCORE

Supply current in

Run mode

DDCORE

Supply current in

Run mode

Table 20. Current consumption (I

DDCORE

) in Run mode (1)

Conditions Typ

MPU SS mode

All peripherals enabled

(2)

CRun

(P0Run,

P1Run)

All peripherals enabled

CRun

(P0Run,

P1Run)

All peripherals disabled

CRun

(P0Run,

P1Run)

MCU

SS mode

Oscillator

CRun HSE+HSI+LSI+PLL

CStop HSE+HSI+LSI+PLL

MPU clk

(MHz)

800

744

648

600

400

800

744

648

600

400

800

744

648

600

400

MCU clk

(MHz)

209

Tj =

25 °C

375

325

415

400

275

270

235

340

560

545

385

575

560

400

385

Tj =

25 °C

460

405

460

445

345

335

295

420

610

590

475

620

605

485

475

Tj =

85 °C

Max

Tj =

105 °C

Tj =

125 °C

Unit

795

740

895

880

680

665

615

1050

1035

815

805

750

1040

1025

805

650

595

710

695

535

525

470

610

850

835

660

865

850

675

660

1000

945

1000

990

935

880

865

810 mA mA mA

Symbol Parameter

DDCORE

Supply current in

Run mode

Table 20. Current consumption (I

DDCORE

) in Run mode (1) (continued)

Conditions Typ

MPU SS mode

All peripherals disabled

CRun

(P0Run,

P1Stop)

MCU

SS mode

CStop

Oscillator

HSE+HSI+PLL

HSE+HSI

HSI+PLL

HSI

MPU clk

(MHz)

800

(3)

744

648

600

300

150

Tj =

25 °C

135

275

265

180

175

35.5

MCU clk

(MHz)

Tj =

25 °C

190

135

105

320

310

240

230

Tj =

85 °C

Max

Tj =

105 °C

Tj =

125 °C

Unit

520

470

440

425

760

750

570

565

410

420

415

410

380

330

295

280

575

565

425

420

265

275

270

270 mA

725

675

645

630

770

765

615

625

620

615

Symbol Parameter

DDCORE

Supply current in

Run mode

MPU in

CSleep with

WFI (CLK

OFF). All peripherals disabled

Table 20. Current consumption (I

DDCORE

) in Run mode (1) (continued)

Conditions Typ

MPU SS mode

CSleep

(P0Stop,

P1Stop)

MCU

SS mode

CStop

Oscillator

HSE+HSI+PLL

HSE+HSI

HSI+PLL

HSI

MPU clk

(MHz)

800

744

Table 50: I/O static characteristics

648

600

300

150

Tj =

25 °C

100

48.5

165

160

110

32.5

MCU clk

(MHz)

Tj =

25 °C

150

115

210

205

160

155

Tj =

85 °C

Max

Tj =

105 °C

Tj =

125 °C

Unit

485

450

430

420

650

495

490

405

415

410

405

340

310

290

280

465

350

265

275

270

265 mA

685

655

635

625

695

610

620

615

610

Symbol Parameter

DDCORE

Supply current in

Run mode

Table 20. Current consumption (I

DDCORE

) in Run mode (1) (continued)

Conditions Typ

MPU SS mode

All peripherals disabled

CStop

(P0Stop,

P1Stop)

MCU

SS mode

CRun

Oscillator

HSE+HSI+PLL

HSE+HSI

HSI+PLL

HSI

CSI+HSI+PLL

CSI+HSI

MPU clk

(MHz)

Tj =

25 °C

33.5

59.5

38.5

37.5

27.5

59.5

MCU clk

(MHz)

209

100

Tj =

25 °C

115

100

Tj =

85 °C

Max

Tj =

105 °C

Tj =

125 °C

Unit

415

400

420

415

405

395

410

400

420

450

430

435

430

275

260

280

275

265

255

270

260

280

305

285

295

285 mA

620

605

625

620

610

600

615

605

625

650

635

640

635

Table 20. Current consumption (I

DDCORE

) in Run mode (1) (continued)

Conditions Typ Max

Symbol Parameter

MPU SS mode

MCU

SS mode

Oscillator

MPU clk

(MHz)

MCU clk

(MHz)

Tj =

25 °C

Tj =

25 °C

Tj =

85 °C

Tj =

105 °C

Tj =

125 °C

DDCORE

Supply current in

Run mode

MCU in

CSleep with

WFI (CLK

OFF). All peripherals disabled

CStop

(P0Stop,

P1Stop)

CSleep

HSE+HSI+PLL

HSE+HSI

HSI+PLL

HSI

CSI+HSI+PLL

CSI+HSI

209

100

59.5

47.5

55.5

51.5

23.5

100

295

280

290

285

270

260

275

260

275

265

255

1. HSE = 24 MHz, AXI clk (F axiss_ck

) = Max(F mpuss_ck

, 264).

2. Activity on peripherals and bus masters other than processors, could lead to additional power consumption above these values, largely dependent on the amount of initialized peripherals and their activity.

3. Typical value given with V

DDCORE

= 1.34 V, maximum values given with V

DDCORE

= 1.38 V.

410

400

420

415

405

395

410

400

415

435

420

430

425

620

605

625

620

610

600

615

605

620

640

625

635

630

Unit mA

Symbol

Parameter

Supply current in Run mode

Table 21. Current consumption (I

) in Run mode (1)

Conditions Typ

MPU SS mode

MCU

SS mode

Oscillator

Tj =

25 °C

CRun

(P0Run, P1Run)

CRun HSE+HSI+LSI+PLL1,2,3,4 3.95

CRun

(P0Run, P1Stop)

CStop

HSI+PLL1,2

HSE+HSI

HSI

3.00

1.75

1.25

1. HSE = 24 MHz.

Tj =

25 °C

Tj =

85 °C

Max

Tj =

105 °C

Tj =

125 °C

Unit

6.14

4.67

3.45

2.46

6.40

4.90

3.48

2.48

6.50

5.00

3.49

2.49

6.60

5.10

3.50

2.50

mA mA

Symbol Parameter

DDCORE

Supply current in

Stop mode

All peripherals disabled

Table 22. Current consumption in Stop mode (1)

Conditions Typ Max

MPU SS mode

MCU SS mode

CStop

(P0Stop,

P1Stop)

CStandby

(P0Stop,

P1Stop)

CStop

(P0Stop,

P1Stop)

CStandby

(P0Stop,

P1Stop)

CStop

Tj =

25 °C

980

19000

Tj =

85 °C

985

90500

90000

Tj =

105 °C

985

150000

Tj =

125 °C

995

230000

225000

Tj =

25 °C

1500

55000

54500

Tj =

85 °C

1560

Tj =

105 °C

1580

Tj =

125 °C

1600

261000 425000 585000

Unit

µA

1. HSE = 24 MHz.

Symbol Parameter

DDCORE

Supply current in

LPLV-Stop mode

All Peripheral disabled

Table 23. Current consumption in LPLV-Stop mode (1)

Conditions Typ

(2)

MPU SS mode

CStop

(P0Stop,

P1Stop)

CStandby

(P0Stop,

P1Stop)

CStop

(P0Stop,

P1Stop)

CStandby

(P0Stop,

P1Stop)

MCU SS mode

CStop

Tj =

25 °C

980

7150

Tj =

85 °C

985

Tj =

105 °C

985

Tj =

125 °C

995

Tj =

25 °C

1500

Max

(3)

Tj =

85 °C

Tj =

105 °C

1560

1580

Tj =

125 °C

1600

39000 67500 105000 25000 122000 190000 290000

1. HSE = 24 MHz.

2. V

DDCORE

= 0.9 V.

3. V

DDCORE

= 0.95 V.

Unit

µA

Table 24. Current consumption in Standby mode (1)

Conditions Typ

Symbol Parameter

MPU SS mode

MCU

SS mode

Supply current in

Standby mode

Backup

SRAM

OFF,

RTC

OFF,

LSE

OFF

Retention

RAM OFF

CStandby

(P0Stop,

P1Stop)

Backup

SRAM

ON,

RTC

ON, LSE

ON, medium

_high drive

Retention

RAM ON

CStandby

(P0Stop,

P1Stop)

CStandby

(P0Stop,

P1Stop)

1. IWDG OFF, LSI OFF, V

DDCORE

= 0 V.

CStop

Tj =

25 °C

1.95

9.6

Tj =

85 °C

4.00

38.5

460

Tj =

105 °C

7.60

64.5

800

Tj =

125 °C

13.5

105

1300

Tj =

25 °C

17.5

130

Tj =

85 °C

Max

Tj =

105 °C

Tj=

125 °C

Unit

850

110

1500

180

2300

µA

Symbol Parameter

DDVBAT

Supply current in

BAT

mode

Table 25. Current consumption in V

BAT

mode

Conditions Typ

Backup SRAM OFF,

RTC OFF, LSE OFF

Backup SRAM OFF,

RTC ON, LSE ON, medium_high drive

Backup SRAM ON,

RTC ON,. LSE ON, medium_high drive

Backup SRAM ON,

RTC ON,. LSE ON, high drive

Retention

RAM OFF

BAT

(V)

2.4

3.3

3.6

3.3

3.6

1.6

2.4

3.3

3.6

3.3

3.6

1.6

2.4

1.6

2.4

Tj =

25 °C

8.25

8.45

9.5

9.55

1.25

1.4

1.55

7.75

7.9

8.4

8.6

9.2

9.85

0.007

0.008

0.012

0.041

0.073

0.84

1.05

Tj =

85 °C

31.5

1.5

2.25

31.5

32.5

33.5

0.13

0.14

0.175

0.52

0.62

1.05

1.3

Tj =

105 °C

60.5

1.9

3.05

3.35

60.5

62.5

0.39

0.415

0.495

1.45

1.65

1.35

1.6

Tj =

125 °C

88.5

91.5

95.5

2.8

5.7

6.25

87.5

97.5

100

1.1

1.15

1.35

3.9

4.25

2.1

2.45

Tj =

25 °C

0.11

Tj =

85 °C

3.5

Max

Tj =

105 °C

5.5

2.2

Tj =

125 °C

151

Unit

µA

Symbol Parameter

DDVBAT

Supply current in

BAT

mode

Table 25. Current consumption in V

BAT

mode (continued)

Conditions Typ

Backup SRAM ON,

RTC ON,. LSE ON, medium_high drive

Backup SRAM ON,

RTC ON, LSE ON, high drive

Retention

RAM ON

BAT

(V)

3.3

3.6

1.6

2.4

1.6

2.4

3.3

3.6

Tj =

25 °C

84.5

75.5

84.5

Tj =

85 °C

405

410

420

430

435

405

410

425

435

440

Tj =

105 °C

760

765

785

795

815

770

790

805

820

Tj =

125 °C

1250

1300

1350

1250

1300

1350

Tj =

25 °C

180

Tj =

85 °C

850

870

Max

Tj =

105 °C

1350

Tj =

125 °C

2000

Unit

µA

Electrical characteristics STM32MP153A/D

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

The I/Os used by an application contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin.

The theoretical formula is provided below:

= V

DDx

×

6.3.7 where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDx

is the MCU supply voltage f

is the I/O switching frequency

is the total capacitance seen by the I/O pin: C = CINT+ CEXT

Wakeup time from low-power modes

The wakeup times given in Table 26

are measured starting from the wakeup event trigger up to the first instruction executed by the MPU or MCU:

• For CSleep modes:

– the MPU or MCU goes in low-power mode after WFE (Wait For Event) instruction.

• For CStop modes:

– MCU goes in low-power mode after WFE (Wait For Event) instruction.

– MPU goes in low-power mode after WFI (Wait For Interrupt) instruction.

• WKUPx pin is used to wakeup from low-power modes.

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Symbol

MPU wakeup

All timings are derived from tests performed under ambient temperature and V

= 3.3 V.

Table 26. Low-power mode wakeup timings

Parameter

System mode

Conditions (after wakeup) Typ

(1)

Max (

Unit t

WUCSLEEP_M

MPU wakeup from

CSleep, MCU in CSleep

Run HSE 24 MHz, SYSRAM 31 32 mpuss_ ck clock cycles t t

WUCSTOP_MP

MPU wakeup from

CStop, MCU in CStop

MPU wakeup from

CStop, MCU in CRun

WULPLV-

Stop_MPU

MPU wakeup from

CStop with system in

LPLV-Stop (LVDS=1),

MCU in CStop

MCU wakeup

Stop

Run

LPLV-

Stop

HSI 64 MHz, SYSRAM

HSE + PLL 648 MHz, SYSRAM

HSI 64 MHz, SYSRAM

HSE + PLL 648 MHz, SYSRAM

HSI 64 MHz, SYSRAM

5.7

112

0.54

220

0.083

0.17

410 640

µs

6 7 mcu_ck clock cycles t

WUCSLEEP_M

MCU wakeup from

CSleep, MPU in CSleep

Run HSE 24 MHz, SRAM t

WULPLV-

Stop_MCU

MCU wakeup from

CStop with system in

LPLV-Stop (LVDS=1),

MPU in CStop

LPLV-

Stop

HSI 64 MHz, SRAM,

MCTMPSKP = 1

HSI 64 MHz, SRAM,

MCTMPSKP = 0, PWR_LP delay = 1 ms t

WUCSTOP_

MCU

MCU wakeup from

CStop, MPU in CStop

Stop HSI 64 MHz, SRAM t

WUCSTOP_

MCU2

MCU wakeup from

CStop, HSI active

(HSIKERON=1), MPU in

CStop

Stop

(HSI active)

HSI 64 MHz, SRAM t

WUCSTOP_

MCU3 t

WUSTANDBY_

MCU

MCU wakeup from

CStop, MPU in CRun

MCU wakeup from

STANDBY

Run HSI 64 MHz, SRAM

Standby HSI 64 MHz, RETRAM

1. Guaranteed by characterization results unless otherwise specified.

5.3

1.4

5.3

0.33

0.12

2.2

0.5

0.18

2550 3000

µs ms

µs

Symbol

Table 27. Wakeup time using USART

(1)

Parameter t

WUUSART

Wakeup time needed to calculate the maximum USART baud rate allowing the wakeup from Stop mode when USART clock source is HSI.

1. Guaranteed by design.

Conditions

Stop

Typ

Max

6.7

Unit

µs

DS12502 Rev 6 143/256

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Electrical characteristics

6.3.8 External clock source characteristics

STM32MP153A/D

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.

Digital and analog bypass modes are available.

The external clock signal has to respect the Table 50: I/O static characteristics . However,

Figure 16

for analog bypass mode. In analog bypass mode the clock can be a sinusoidal waveform.

Symbol

Table 28. High-speed external user clock characteristics

(digital bypass) (1)

Parameter Min Typ Max f

HSE_ext

HSEH -

HSEL)

DC t

W(HSE)

User external clock source frequency

OSC_IN amplitude

OSC_IN input voltage

OSC_IN high or low time

1. Guaranteed by design.

0.7×V

7 -

0.3×V

Unit

MHz

V ns

Figure 15. High-speed external clock source AC timing diagram (digital bypass)

144/256

VHSEH

90 %

VHSEL

10 % tr(HSE)

THSE tf(HSE) tW(HSE) tW(HSE) t

External clock source fHSE_ext

OSC_IN

STM32

Symbol f

HSE_ext

HSE

Table 29. High-speed external user clock characteristics

(analog bypass) (1)

Parameter Min Typ Max

User external clock source frequency duty cycle (Square wave) duty cycle deterioration

Absolute input range

±10

(2)

±20

(3)

DD ai17528b

Unit

MHz

DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Table 29. High-speed external user clock characteristics

(analog bypass) (1) (continued)

Parameter Min Typ Max Symbol Unit

PP t

(5)

OSC_IN peak-to-peak amplitude

Time to start

0.2

(4)

0.67×V

10 (6)

µs tr/tf

(HSE)

Rise and Fall time

(10% to 90% threshold levels of the input peak-to-peak amplitude)

0.05 ×T

HSE

0.3 ×T

HSE ns

(HSE)

Power consumption 150

(7)

500

(8)

µA

1. Guaranteed by design.

2. Guaranteed by design with a square wave signal (@25 °C, V

DC is the DC component of the input signal.

=3.3 V /V

= 400 mV / V

=1 V) where

3. Guaranteed by design with a square wave signal (@25 °C, V

DC is the DC component of the input signal.

=1.71 V /V

= 200 mV / V

=0.8 V) where

4. minimum peak-to-peak amplitude (@25 °C, 0.1<V input signal.

-0.1 V) where V

DC is the DC component of the

5. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized analog bypass clock interface is reached. This value is measured with 200 mV peak-to-peak amplitude.

6. Maximum start-up time is obtained with 200 mV peak-to-peak amplitude.

7. with a sine wave signal (V

= 400 mV / V

=0.4 V) where V

is the DC component of the input signal.

8. with a sine wave signal (V input signal.

= 3.6 V / V

= 800 mV / V

= 1.8 V) where V

DC is the DC component of the

Figure 16. High-speed external clock source AC timing diagram (analog bypass)

HSE

HSE t r(HSE)

90% t

10%

External clock source f

HSE_ext

OSC_IN

STM32

Table 30. Low-speed external user clock characteristics

(analog bypass) (1)

Parameter Min Typ Max Symbol f

LSE_ext

LSE

User external clock source frequency

Absolute input range

32.768

(2)

MSv47498V1

Unit kHz

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234

Electrical characteristics STM32MP153A/D

Table 30. Low-speed external user clock characteristics

(analog bypass) (1) (continued)

Parameter Min Typ Max Symbol Unit

(LSE)

OSC32_IN peak-to-peak amplitude

Power consumption

0.2

(3)

120 -

1. Guaranteed by design.

2. V

is equal to V

when present or V

BAT

otherwise

3. Minimum peak-to-peak amplitude (@25 °C, 0.1 < V the input signal.

< V

- 0.1 V) where V

DC is the DC component of

V nA

Figure 17. Low-speed external clock source AC timing diagram (analog bypass)

LSE

LSE t

Note:

External clock source f

LSE_ext

OSC32_IN

STM32

MSv63037V1

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The

external clock signal has to respect the Table 50: I/O static characteristics . However, the

Figure 17

for analog bypass.

Table 31. Low-speed external user clock characteristics (digital bypass)

(1)

Symbol Parameter Min Typ Max Unit f

LSE_ext

LSEH

LSEL t w(LSEH) t w(LSEL)

User external clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

1. Guaranteed by design.

0.7 × V

250

32.768

1000

0.3 V

kHz

V ns

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

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STM32MP153A/D Electrical characteristics

Figure 18. Low-speed external clock source AC timing diagram

VLSEH

VLSEL

90%

10 % tr(LSE)

TLSE tf(LSE) tW(LSE) tW(LSE) t

External clock source fLSE_ext

OSC32_IN

STM32 ai17529b

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 8 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in

Table 32 . In

the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 32. 8-48 MHz HSE oscillator characteristics (1)

Parameter Operating conditions

(2)

Oscillator frequency

Feedback resistor

During startup

(3)

DD(HSE)

HSE current consumption

= 3 V, Rm = 150 Ω

= 12 pF at 4 MHz

= 3 V, Rm = 120 Ω

= 12 pF at 16 MHz

= 3 V, Rm = 100 Ω

= 10 pF at 24 MHz

= 3 V, Rm = 80 Ω

= 8 pF at 32 MHz

= 3 V, Rm = 80 Ω

= 8 pF at 48 MHz

Startup Gm critmax t

(4)

Maximum critical crystal gm

Start-up time V

is stabilized

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

Min

Typ

200

0.35

0.40

0.45

0.65

0.95

Max

1.5

Unit

MHz kΩ mA mA/V ms

DS12502 Rev 6 147/256

234

Electrical characteristics STM32MP153A/D

3. This consumption level occurs during the first 2/3 of the t

SU(HSE)

startup time.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note:

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 19

). C

and C

are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. The PCB and MCU pin capacitance must be included

(10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing C

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 19. Typical application with a 24 MHz crystal

OSC_IN f

HSE

24 MHz crystal

Bias controlled gain

OSC_OUT

STM32

MSv63062V1

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in

Table 33 . In

148/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Symbol

Table 33. Low-speed external user clock characteristics (1)

Parameter Operating conditions

(2)

Min Typ Max Unit

Oscillator frequency

LSE current consumption

LSEDRV[1:0] = 00,

Low drive capability

LSEDRV[1:0] = 01,

Medium Low drive capability

LSEDRV[1:0] = 10,

Medium high drive capability

32.768

290

390

550 -

kHz nA

Gm critmax

Maximum critical crystal gm

LSEDRV[1:0] = 11,

High drive capability

LSEDRV[1:0] = 00,

Low drive capability

LSEDRV[1:0] = 01,

Medium Low drive capability

LSEDRV[1:0] = 10,

Medium high drive capability

900

0.5

0.75

1.7

µA/V

LSEDRV[1:0] = 11,

High drive capability

2.7

(3)

Startup time V

is stabilized 2 s

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers.

3. t

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 20. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

HSE

32.768 kHz resonator

Bias controlled gain

OSC32_OUT

STM32 ai17531c

1. Adding an external resistor between OSC32_IN and OSC32_OUT is forbidden.

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Electrical characteristics STM32MP153A/D

6.3.9 External clock source security characteristics

Table 34. High-speed external user clock security system (HSE CSS) (1)

Symbol Parameter Min Typ Max Unit

I t

DCM(HSE_CSS) t

DCP(HSE_CSS)

VDD(HSE_CSS)

Time to detect clock missing

Time to detect clock presence

Power consumption (f

HSE

= 48 MHz)

1. Guaranteed by design.

250

μ s ns

μ A

6.3.10 Internal clock source characteristics

The parameters given in

Table 35 ,

Table 36 and Table 37

are derived from tests performed under ambient temperature and V

General operating conditions .

supply voltage conditions summarized in

Table 13:

64 MHz high-speed internal RC oscillator (HSI)

Symbol

HSI

(2)

TRIM

DuCy(HSI)

VDD (HSI)

Table 35. HSI oscillator characteristics (1)

Parameter Conditions

HSI frequency

HSI user trimming step

= 3.3 V, T

= 30 °C

Trimming is not a multiple of 32

Trimming is 128, 256 and

384

Trimming is 64, 192, 320 and 448

Other trimming are a multiple of 32 (not including multiple of 64 and 128)

Duty Cycle

HSI oscillator frequency drift over V

(reference is 3.3 V)

= 1.71 to 3.6 V

TEMP (HSI)

(3)

HSI oscillator frequency drift over temperature after factory calibration

= -20 to 110 °C

= -40 to 125 °C t su

(HSI)

HSI oscillator start-up time (Time between Enable rising and First output clock edge.) t stab

(HSI)

HSI oscillator stabilization time

HSI oscillator power consumption

1. Guaranteed by design unless otherwise specified.

2. Guaranteed by test in production.

3. Guaranteed by characterization results.

at 1% of target frequency

Min Typ Max Unit

63.7

64 64.3

MHz

-0.12

-1.25

-1.75

0.24

0.33

-2.43

-0.70

-0.30

1.47

0.03

0.75

0.95

3 -

300 400

µs

µA

150/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

4 MHz low-power internal RC oscillator (CSI)

Symbol f

CSI

(2)

TRIM Trimming step

Table 36. CSI oscillator characteristics

(1)

Parameter

CSI frequency

Conditions

= 3.3 V, T

= 30 °C

Trimming code is not a multiple of 16

Trimming code is a multiple of

DuCy(CSI) Duty Cycle -

∆

VDD

(CSI) +

(3)

TEMP

(CSI) t su(CSI)

CSI oscillator frequency drift over

& drift over temperature

CSI oscillator startup time

= 1.71 to 3.6 V

= 0 to 85 °C

t stab(CSI)

CSI oscillator stabilization time

(to reach ±5% of f

CSI

)

CSI oscillator power consumption

= 0 to 85 °C

DD(CSI)

1. Guaranteed by design.

2. Guaranteed by test in production.

3. Guaranteed by characterization results.

Min Typ Max Unit

3.98

4 4.02

MHz

0.85

-1.65

±1.43

1.5

2.4

µs cycle

µA

32 kHz low-speed internal (LSI) RC oscillator

Symbol f

LSI t su(LSI)

Table 37. LSI oscillator characteristics

(1)

Parameter

LSI frequency

Conditions

= 30 °C,

(2)

= 3.3 V

= -40 to 125 °C,

= 1.71 to 3.6 V

Min

31.4

LSI oscillator startup time (Time between Enable rising and First output clock edge.)

I t stab(LSI)

DD(LSI)

LSI oscillator stabilization time

(5% of final value)

LSI oscillator power consumption

1. Guaranteed by design.

2. Guaranteed by test in production.

Typ

110

120

Max

32.6

33.6

125

170

230

Unit kHz

µs nA

6.3.11 PLL characteristics

The parameters given in

Table 38 ,

Table 39

, Table 40

are derived from tests performed under temperature and V

operating conditions

supply voltage conditions summarized in Table 13: General

DS12502 Rev 6 151/256

234

Electrical characteristics STM32MP153A/D

PLL1_1600, PLL2_1600 characteristics

Symbol f

PLL_IN

Table 38. PLL1_1600, PLL2_1600 characteristics

(1)

Parameter Conditions Min

Normal mode and Sigma delta mode 8 PLL input clock

PLL input clock duty cycle

PLL P,Q,R multiplier output clock

3.125

PLL_P_Q_R_

OUT

PLL P,Q,R clock duty cycle

Division by 1

Even divisions

(N multiple of 2)

45 f

VCO_OUT t

LOCK

PLL VCO output

PLL lock time

Odd divisions

(N not multiple of 2)

Normal mode

Sigma-delta mode (CKIN ≥ 8 MHz)

Typ

Max Unit

16 MHz

800

(2)

MHz

[100,

(N+1)/

2N] - 5

[100,

(N+1)/

2N]

800

[100,

(N+1)/

2N] +

1600 MHz

150

µs

170

LOCK

Lock Accuracy

(Ratio VCO frequency versus target frequency at lock)

±2 %

152/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Symbol

Table 38. PLL1_1600, PLL2_1600 characteristics (1) (continued)

Parameter Conditions Min Typ

Jitter

RMS cycle-tocycle jitter

RMS period jitter f

PLL_P_Q_R_OUT to 16

division = 1

Without Fractional mode

VCO = 800 MHz

VCO = 1066 MHz

VCO = 1600 MHz f

PLL_P_Q_R_OUT to 16

division = 1

With Fractional mode

VCO = 1066 MHz

VCO = 1600 MHz f

PLL_P_Q_R_OUT to 16

division = 1

Without Fractional mode

VCO = 800 MHz

VCO = 1066 MHz

VCO = 1600 MHz f

PLL_P_Q_R_OUT to 16

division = 1

With Fractional mode

VCO = 1066 MHz

VCO = 1600 MHz

Long term jitter f

PLL_P_Q_R_OUT to 16

division = 1 f

PLL_IN

= 8 MHz

Without Fractional mode

VCO = 800 MHz

VCO = 1066 MHz

VCO = 1600 MHz f

PLL_P_Q_R_OUT to 16

division = 1 f

PLL_IN

= 8 MHz

With Fractional mode

VCO = 800 MHz

VCO = 1066 MHz

VCO = 1600 MHz

VDD_PLL

(2)

VDDCORE

(2)

PLL power consumption on

DD_PLL (Analog)

PLL power consumption on

DDCORE (Digital)

VCO freq = 1600 MHz

VCO freq = 800 MHz

VCO freq = 1600 MHz

VCO freq = 800 MHz

1. Guaranteed by design unless otherwise specified.

2. Guaranteed by characterization results.

3. Measured on DDR high speed IO.

4. Measured on DDR high speed IO for 10000 output clock cycles.

225

(4)

930

560

4200

2100

Max Unit

±ps

±ps ps

µA

μA

Symbol f

PLL_IN

PLL3_800, PLL4_800 characteristics

Parameter

Table 39. PLL3_800, PLL4_800 characteristics

(1)

Conditions Min

PLL input clock

PLL input clock duty cycle

Normal mode

Sigma delta mode

Typ

Max Unit

MHz

90 %

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Electrical characteristics STM32MP153A/D

Symbol f

PLL_P_Q_R_

OUT

PLL P,Q,R clock duty cycle f

VCO_OUT t

LOCK

Table 39. PLL3_800, PLL4_800 characteristics (1) (continued)

Parameter Conditions Min Typ

PLL P,Q,R multiplier output clock

3.125

PLL VCO output

PLL lock time

Even divisions

(N multiple of 2)

Odd divisions

(N not multiple of 2)

Normal mode

Sigma-delta mode (CKIN ≥ 8 MHz)

45 50

Max Unit

800 (2)

MHz

[100,

(N+1)/

2N] - 5

[100,

(N+1)/

2N]

400

[100,

(N+1)/

2N] +

800 MHz

150

170

µs

LOCK

Lock accuracy

(Ratio VCO frequency versus target frequency at lock)

±2 %

Jitter

VDD_PLL

RMS cycle-tocycle jitter

RMS period jitter

Long term jitter

PLL power consumption on

DD_PLL (Analog) f

PLL_P_Q_R_OUT

25 to 100

division =

Without Fractional mode f

PLL_P_Q_R_OUT

25 to 100

division =

With Fractional mode f

PLL_P_Q_R_OUT

25 to 100

division =

Without Fractional mode f

PLL_P_Q_R_OUT

25 to 100

division =

With Fractional mode f

PLL_P_Q_R_OUT

25 to 100

division = f

PLL_IN

= 8 MHz

Without Fractional mode f

PLL_P_Q_R_OUT

25 to 100

division = f

PLL_IN

= 8 MHz

With Fractional mode

VCO freq = 800 MHz

VCO freq = 400 MHz

VCO = 400 MHz

VCO = 600 MHz

VCO = 800 MHz

VCO = 600 MHz

VCO = 800 MHz

VCO = 400 MHz

VCO = 600 MHz

VCO = 800 MHz

VCO = 600 MHz

VCO = 800 MHz

VCO = 400 MHz

VCO = 600 MHz

VCO = 800 MHz

VCO = 400 MHz

VCO = 600 MHz

VCO = 800 MHz

80 (3)

Table 46: EMI characteristics

225

(4)

600

320

610

350

±ps

±ps ps

µA

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Symbol

Table 39. PLL3_800, PLL4_800 characteristics (1) (continued)

Parameter Conditions

VDDCORE

PLL power consumption on

DDCORE (Digital)

VCO freq = 800 MHz

VCO freq = 400 MHz

1. Guaranteed by design unless otherwise specified.

2. Guaranteed by characterization results.

3. Measured on GPIO.

4. Measured on GPIO for 10000 output clock cycles.

Min

Typ Max Unit

2200 5250

1130 4550

µA

PLL_USB (2880 MHz) characteristics

Table 40. USB_PLL characteristics (1) f

PLL_IN f

PLL_INFIN f

PLL_OUT f

VCO_OUT t

LOCK t

PDN

DDA1V1_R

EG(PLL)

Symbol Parameter

PLL input clock

PFD input clock

PLL multiplier output clock

PLL VCO output

PLL lock time

PLL power down time

PLL power consumption on

DDA1V1_REG

(internal connection)

DDA1V8_R

EG(PLL)

PLL power consumption on

DDA1V8_REG

(internal connection)

1. Guaranteed by design unless otherwise specified.

Condition

PLL in power down f

VCO_OUT

= 2880 MHz

PLL in power down f

VCO_OUT

= 2880 MHz

Min

19.2

Typ Max Unit

480

2880

4.4

38.4

MHz

38.4

MHz

100

425

5.6

2.5

MHz

µs

µA mA

6.3.12 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows the reduction of electromagnetic interferences (see

). It is available only on the

PLL1_1600 and PLL2_1600.

Symbol f

Mod md

MODEPER * INCSTEP

1. Guaranteed by design.

Table 41. SSCG parameters constraint

Parameter Min

Modulation frequency

Peak modulation depth

0.25

Typ

Max

(1)

-1

Unit kHz

Equation 1

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Electrical characteristics STM32MP153A/D

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER = round f

PLL_IN

⁄ (

Mod

) ] f

PLL_IN

and fMod must be expressed in Hz.

As an example:

If f

PLL_IN

= 1 MHz, and f

MOD

= 1 kHz, the modulation depth (MODEPER) is given by equation 1:

MODEPER = [

⁄ ( ×

) ] = 250

Equation 2

Equation 2 allows the increment step (INCSTEP) calculation:

INCSTEP = round [ ( ( 2

– 1 ) × md PLLN ) ⁄ ( 100 5 × MODEPER ) ] f

VCO_OUT

must be expressed in MHz.

With a modulation depth (md) = ±2% (4% peak-to-peak), and PLLN = 240 (in MHz):

INCSTEP = round [ ( ( 2

– 1 ) × 2 240 ) ⁄ ( 100 5 × 250 ) ] = 126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized

% = ( × 100 × 5 ) ⁄ ( ( 2

– 1 ) × PLLN )

As a result: md quantized

% = ( × 100 × 5 ) ⁄ ( ( 2

– 1 ) × 240 ) = 2.002%(peak)

Figure 21

and

Figure 22 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is f

PLL_OUT

nominal.

T mode

is the modulation period.

md is the modulation depth.

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Figure 21. PLL output clock waveforms in center spread mode

Frequency (PLL_OUT) md

F0 md

Time tmode 2xtmode

Figure 22. PLL output clock waveforms in down spread mode

Frequency (PLL_OUT) ai17291

2xmd

Time tmode 2xtmode ai17292b

6.3.13 Memory characteristics

OTP characteristics

The characteristics are given at T

= -40 to 125 °C unless otherwise specified.

VDD

Symbol

VDDCORE

Table 42. OTP characteristics

Parameter Conditions

OTP consumption on V

DDCORE

OTP consumption on V

OTP

(1)

NB_CYCLE

(2)

OTP operating Frequency

Maximum number of reading cycles

1. Guaranteed by design.

2. Guaranteed by characterization results.

Programming

Reading

PowerDown

Programming

Reading

PowerDown

Min

Max

450

490

4.2

10000

2200

500

Unit

µA

MHz

Million

µA

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Electrical characteristics STM32MP153A/D

DDR characteristics

DDR3, DDR3L I/O DC specifications

The following table provides input and output DC threshold values and on-die-termination

(ODT) recommended values. The conditions for the output threshold values are unterminated outputs loaded with 1 pF capacitor load. The ODT values are measured after impedance calibration.

Symbol

IH(DC)

IL(DC)

Table 43. DC specifications – DDR3 or DDR3L mode (1)

Parameter Min Typ

DC input voltage high

DC input voltage low

DC output logic high

DC output logic low

Input termination resistance (ODT) to V

DDQ

Input leakage current, SSTL mode, unterminated

1. Guaranteed by design.

REF

+ 0.09

SSQ

- 0.3

0.8 × V

DDQ

100

120

0.01

Max Unit

DDQ

REF

- 0.09

V 0.2 × V

DDQ

140

4.8

Ω

μA

LPDDR2, LPDDR3 I/O DC specifications

The following table provides input and output DC threshold values. The conditions for the output threshold values are un-terminated outputs loaded with 1 pF capacitor load.

Symbol

Table 44. DC specifications – LPDDR2 or LPDDR3 mode

(1)

Parameter

IH(DC)

IL(DC)

ILEAK

DC input voltage high

DC input voltage low

DC output logic high

DC output logic low

Input leakage current

1. Guaranteed by design.

Min

REF

+ 0.13

SSQ

0.9 × V

DDQ

Typ

0.01

Max Unit

DDQ

REF

- 0.13

0.1 × V

DDQ

4.51

μA

6.3.14 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

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Symbol

FESD

FTB

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : a burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 45

. They are based on the EMS levels and classes defined in application note AN1709 available from the ST website www.st.com

Table 45. EMS characteristics

Parameter Conditions

Level/

Class

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

DD functional disturbance

and V

SS pins to induce a

= 3.3 V, T

F mpuss_ck

= +25 °C, LFBGA448,

= 650 or 800 MHz, mcu_ck

= 209 MHz,

M4 core not running, conforms to IEC 61000-4-2

As a consequence, it is recommended to add a serial resistor (1 kΩ) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened

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Electrical characteristics STM32MP153A/D

EMI to prevent unrecoverable errors occurring (see application note AN1015 available from the

ST website www.st.com

.).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

Symbol Parameter

Peak level

Table 46. EMI characteristics

Conditions

= 3.6 V, T

= 25 °C,

LFBGA448 package,

F mcu_ck

= 209 MHz,

M4 core not running, conforming to IEC61967-2

Monitored frequency band

Max vs. [f

HSE

/F mpuss_ck

]

Unit

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI Level

24/650 MHz 24/800 MHz

-2

3.5

-1

3.5

dBµV

6.3.15 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC

JS-001 and ANSI/ESDA/JEDEC JS-002 standards.

Symbol Ratings

Table 47. ESD absolute maximum ratings

Conditions Packages Class

Maximum value

(1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

1. Guaranteed by characterization results.

= +25 °C conforming to ANSI/ESDA/JEDEC

JS-001

= +25 °C conforming to ANSI/ESDA/JEDEC

JS-002

All

2000

250

Static latchup

Two complementary static tests are required on three parts to assess the latchup performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with JESD78 IC latchup standard.

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STM32MP153A/D Electrical characteristics

Symbol Parameter

Static latchup class

Table 48. Electrical sensitivities

Conditions

= +25 °C conforming to JESD78

Class

II level A

6.3.16 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below V

(for standard, 3.3 V-capable I/O pins) should be avoided during the normal

or above V

DD product operation. However, in order to give an indication of the robustness of the device in cases when an abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation).

The following tables are the compilation of the SIC1/SIC2 and functional ESD results.

Negative induced A negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

Symbol

Table 49. I/O current injection susceptibility (1)

Description

Negative injection

ANA0, ANA1, PA4, PA5

INJ

PG2, PG3, PG4, PH2

All other FTxx I/Os

1. Guaranteed by characterization .

Positive injection

N/A

Unit mA

6.3.17 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 50: I/O static characteristics are

derived from tests performed under the conditions summarized in

Table 13: General operating conditions

. All I/Os are CMOS and TTL compliant.

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Electrical characteristics STM32MP153A/D

Symbol Parameter

Table 50. I/O static characteristics

Condition Min Typ Max Unit

(1)

HYS

I/O input low level voltage

I/O input high level voltage

TT_xx, FT_xxx and NRST I/O input hysteresis

FT_xx input leakage current

1.71 V < V

2.7 V < V

1.71 V < V

< 2.7 V

< 3.6 V

1.71 V < V

< 3.6 V

0 < V

≤ Max(V

)

(6)

Max(V

(6)(2)(3)

) < V

≤ 5.5 V

0.7 × V

0.1 ×

0.35 × V

0.3 × V

0.45 × V

+ 0.35

250

3500

V mV

I leak

FT_u, IO

0 < V

≤ Max(V

)

(6)

Max(V

(6)(3)

) < V

≤ 5.5 V

500

5000

(4) nA

TT_xx input leakage current 0 < V

≤ Max(V

)

(6)

100

Weak pull-up equivalent resistor (5)

25 40 55

(6)

25 40 55 kΩ

Weak pull-down equivalent resistor

Table 51 are derived from tests

I/O pin capacitance 5 -

1. Guaranteed by design.

2. All FT_xx IO except FT_uf, FT_u.

3. V

must be less than Max(V

) + 3.6 V.

4. To sustain a voltage higher than MIN(V be disabled.

, V

DDA

, V

DD3V3_USBxxx

) +0.3 V, the internal pull-up and pull-down resistors must

5. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

6. Max(V

) is the maximum value of all the I/O supplies.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in

Figure 23

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Figure 23. VIL/VIH for FT I/Os

Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed V

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

. In particular:

• The sum of the currents sourced by all the I/Os on V

DD consumption of the MCU sourced on V

∑I

VDD

(see

Table 11

, plus the maximum Run mode

, cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

∑I

VSS

(see Table 11

plus the maximum Run mode

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in

performed under ambient temperature and V

supply voltage conditions summarized in

Table 13: General operating conditions . All I/Os are CMOS and TTL compliant.

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Electrical characteristics STM32MP153A/D

Table 51. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 (1)

Symbol Parameter Conditions

(3)

Min Max Unit

(3)

OLFM+

(3)

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage for an FT_f

IO pin in FM+ mode

CMOS port

(2)

= 8 mA

2.0 V ≤ V

≤ 3.6 V

CMOS port

(2)

= -8 mA

2.0 V ≤ V

≤ 3.6 V

TTL port

(2)

= 8 mA

2.0 V ≤ V

≤ 3.6 V

TTL port (2)

= -8 mA

2.0 V ≤ V

≤ 3.6 V

= 20 mA

2.7 V ≤ V

≤ 3.6 V

= -20 mA

2.7 V ≤ V

≤ 3.6 V

= 4 mA

1.71 V ≤ V

≤ 3.6 V

= -4 mA

1.71 V ≤ V

≤ 3.6 V

= 20 mA

2.7 V ≤ V

≤ 3.6 V

= 10 mA

1.71 V ≤ V

≤ 3.6 V

2.4

-0.45

-0.4

-1.3

0.4

1.3

0.45

0.4

1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 10:

Voltage characteristics

, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ∑IIO.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

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Symbol

Table 52. Output voltage characteristics for PC13, PC14, PC15 and PI8 (1)

Parameter Conditions

(3)

Min Max Unit

(3)

(2)

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

CMOS port

(2)

= 3 mA

2.7 V ≤ V

≤ 3.6 V

CMOS port

(2)

= -3 mA

2.7 V ≤ V

≤ 3.6 V

TTL port

(2)

= 3 mA

2.7 V ≤ V

≤ 3.6 V

TTL port (2)

= -3 mA

2.7 V ≤ V

≤ 3.6 V

= 1.5 mA

1.62 V ≤ V

≤ 3.6 V

= -1.5 mA

1.62 V ≤ V

≤ 3.6 V

2.4

− 0.4

0.4

1. The I

current sourced or sunk by the device must always respect the absolute maximum rating specified in

Table 10:

Voltage characteristics

, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

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Electrical characteristics

Output buffer timing characteristics (HSLV option disabled)

Speed Symbol

F max

(3) t r

/t f

(4)

max

t r

/t f

(4)

Table 53. Output timing characteristics (HSLV OFF)

(1)(2)

Parameter conditions Min

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time

C = 50 pF, 2.7 V ≤ V

≤ 3.6 V

C = 30 pF, 2.7 V ≤ V

≤ 3.6 V

C = 20 pF, 2.7 V ≤ V

≤ 3.6 V

C = 10 pF, 2.7 V ≤ V

≤ 3.6 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 2.7 V ≤ V

≤ 3.6 V

C = 30 pF, 2.7 V ≤ V

≤ 3.6 V

C = 20 pF, 2.7 V ≤ V

≤ 3.6 V

C = 10 pF, 2.7 V ≤ V

≤ 3.6 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 2.7 V ≤ V

≤ 3.6 V

C = 30 pF, 2.7 V ≤ V

≤ 3.6 V

C = 20 pF, 2.7 V ≤ V

≤ 3.6 V

C = 10 pF, 2.7 V ≤ V

≤ 3.6 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 2.7 V ≤ V

≤ 3.6 V

C = 30 pF, 2.7 V ≤ V

≤ 3.6 V

C = 20 pF, 2.7 V ≤ V

≤ 3.6 V

C = 10 pF, 2.7 V ≤ V

≤ 3.6 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

STM32MP153A/D

Unit

MHz ns

Max

103

4.9

18.3

8.1

6.5

5.7

4.6

3.9

3.3

2.7

13.3

11.4

10.2

8.8

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Table 53. Output timing characteristics (HSLV OFF) (1)(2) (continued)

Speed Symbol Parameter conditions Min Max Unit

F t t

max

r r

/t f

(4)

max

Table 50: I/O static characteristics ).

(4)

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time

C = 50 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 30 pF, 2.7 V ≤ V

≤ 3.6 V (5)

C = 20 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 10 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V (5)

C = 50 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 30 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 20 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 10 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V (5)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 50 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 30 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 20 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 10 pF, 2.7 V ≤ V

≤ 3.6 V (5)

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 50 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 30 pF, 2.7 V ≤ V

≤ 3.6 V (5)

C = 20 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 10 pF, 2.7 V ≤ V

≤ 3.6 V

(5)

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(5)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V (5) -

124

144

166

3.5

2.7

2.2

1.7

6.3

4.8

3.2

110

150

185

210

2.2

1.8

1.3

5.3

3.3

2.5

MHz ns

1. Guaranteed by design.

2. GPIO under VSW domain (PC13, PC14, PC15, PI8) are frequency limited. The maximum frequency is 2 MHz with a maximum load of 30 pF. Only one I/O at a time can be used as GPIO output and these I/Os must not be used as a current source (e.g to drive a LED). For theses IOs, the speed value must be kept to (default) 00.

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Electrical characteristics STM32MP153A/D

3. The maximum frequency is defined with the following conditions: (t r

+t f

) ≤ 2/3, skew ≤ 1/20 T and 45% < duty cycle < 55%.

4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.

5. Compensation system enabled.

Output buffer timing characteristics (IO structure with _h, HSLV option enabled)

The HSLVEN_xx bits of SYSCFG_IOCTRLSETR register (together with OTP bit

PRODUCT_BELOW_2V5) can be used to optimize the I/O speed when the product voltage is below 2.5 V typ. (2.7 V max.).

Table 54. Output timing characteristics (HSLV ON, _h IO structure) (1)

Speed Symbol Parameter conditions Min Max

F max

(2) t r

/t f

(3)

F max

(2) t r

/t f

(3)

F max

(2) t r

/t f

(3)

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V (4)

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

126

162

4.7

3.3

2.7

1.9

5.7

4.2

3.5

2.7

101

7.1

5.8

100

9.9

8.1

Unit

MHz ns

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Table 54. Output timing characteristics (HSLV ON, _h IO structure) (1) (continued)

Speed Symbol Parameter conditions Min Max Unit

F t max

(2) r

/t f

(3)

Maximum frequency

Output high to low level fall time and output low to high level rise time

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V (4)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V (4) -

111

145

172

4.3

2.3

1.6

MHz

1. Guaranteed by design.

2. The maximum frequency is defined with the following conditions: (t r

+t f

) ≤ 2/3, skew ≤ 1/20 T and 45% < duty cycle < 55%.

3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.

4. Compensation system enabled.

Output buffer timing characteristics (IO structure with _vh, HSLV option enabled)

The HSLVEN_xx bits of SYSCFG_IOCTRLSETR register (together with OTP bit

PRODUCT_BELOW_2V5) can be used to optimize the I/O speed when the product voltage is below 2.5 V typ. (2.7 V max.).

Table 55. Output timing characteristics (HSLV ON, _vh IO structure)

(1)

Speed Symbol Parameter conditions Min Max

F max

(2) t r

/t f

(3)

Maximum frequency

Output high to low level fall time and output low to high level rise time

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

9.2

7.4

6.5

5.2

Unit

MHz ns

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Electrical characteristics STM32MP153A/D

Table 55. Output timing characteristics (HSLV ON, _vh IO structure) (1) (continued)

Speed Symbol Parameter conditions Min Max Unit

F t t t max

(2) r

/t f

(3) max

(2) r

/t f

(3) max

(2) r

/t f

(3)

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V (4)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V (4)

C = 50 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 30 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 20 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

C = 10 pF, 1.71 V ≤ V

≤ 2.7 V

(4)

100

6.1

4.7

3.9

118

162

4.9

3.5

2.8

2.1

121

162

245

4.2

2.8

2.1

1.4

MHz ns

1. Guaranteed by design.

2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3, skew ≤ 1/20 T and 45% < Duty cycle < 55%.

3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.

4. Compensation system enabled.

6.3.18 NRST and NRST_CORE pin characteristics

The NRST and NRST_CORE pins input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Unless otherwise specified, the parameters given in

Table 56 are derived from tests

performed under the ambient temperature and V

DD in

Table 13: General operating conditions .

supply voltage conditions summarized

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Symbol

Table 56. NRST and NRST_CORE pin characteristics

Parameter Conditions Min Typ Max Unit

(2)

F(NRST)

(2)

Weak pull-up equivalent resistor

(1)

NRST/NRST_CORE Input filtered pulse

NF(NRST)

(2)

NRST/NRST_CORE Input not filtered pulse

= V

1.71 V < V

< 3.6 V

350

kΩ ns

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order).

2. Guaranteed by design.

Figure 24. Recommended NRST and NRST_CORE pin protection

External reset circuit (1)

NRST(2)

VDD

RPU

0.1 μF

Filter

Internal Reset

STM32 ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST/NRST_CORE pin can go below the V specified in

Table 56

. Otherwise the reset is not taken into account by the device.

IL(NRST)

max level

6.3.19 FMC characteristics

Unless otherwise specified, the parameters given in

Table 57

to Table 70

for the FMC interface are derived from tests performed under the ambient temperature, F mc_hclk frequency and V

supply voltage conditions summarized in Table 13: General operating

, with the following configuration:

(F hclk6

)

• Output speed is set to OSPEEDRy[1:0] = 11

• Measurement points are done at CMOS levels: 0.5×V

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output

characteristics.

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Electrical characteristics STM32MP153A/D

Asynchronous waveforms and timings

Figure 25

through Figure 28 represent asynchronous waveforms and

Table 57 through

Table 64 provide the corresponding timings. The results shown in these tables are obtained

with the following FMC configuration:

• AddressSetupTime = 0x1

• AddressHoldTime = 0x1

• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)

• DataHoldTime = 0x1 (1×T fmc_ker_ck operations)

for read operations and 2×T fmc_ker_ck

for write

• ByteLaneSetup = 0x1

• BusTurnAroundDuration = 0x0

• Capacitive load C

= 30 pF

In all the timing tables, the T fmc_ker_ck

is the fmc_ker_ck clock period.

Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms t w(NE)

FMC_NE t v(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

FMC_A[25:0] t v(A_NE) t v(BL_NE)

Address t h(A_NOE) t h(BL_NOE)

FMC_NBL[1:0] t h(Data_NE) t h(Data_NOE)

FMC_D[15:0] t su(Data_NOE) t su(Data_NE)

Data t v(NADV_NE) t w(NADV)

FMC_NADV

(1)

FMC_NWAIT

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

th(NE_NWAIT) tsu(NWAIT_NE)

MS32753V1

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Table 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)

Symbol Parameter Min Max t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOEx high setup time

Data hold time after FMC_NOE high

Data hold time after FMC_NEx high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. Guaranteed by characterization results.

3T fmc_ker_ck

-1

2T fmc_ker_ck

-1

T fmc_ker_ck

-1

2T fmc_ker_ck

-1

T fmc_ker_ck

+15

3T fmc_ker_ck

+0.5

2T fmc_ker_ck

T fmc_ker_ck

Unit ns

Table 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings

(1)(2)

Symbol Parameter Min Max Unit t w(NE) t w(NOE) t w(NWAIT) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NE low time

FMC_NWE low time

FMC_NWAIT low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results.

2. N

WAIT

pulse width is equal to 1 AHB cycle.

7T fmc_ker_ck

-0.5

7T fmc_ker_ck

6T fmc_ker_ck

-0.5

6T fmc_ker_ck

T fmc_ker_ck

7T fmc_ker_ck

5T fmc_ker_ck

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Electrical characteristics STM32MP153A/D

Figure 26. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE)

FMC_NEx

FMC_NOE

FMC_NWE

FMC_A[25:0]

FMC_NBL[1:0]

FMC_D[15:0] tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) th(A_NWE)

Address th(BL_NWE)

NBL th(Data_NWE)

Data t v(NADV_NE) tw(NADV) t h(NE_NWE)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

(1)

Symbol Parameter Min Max t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NWE high

Data to FMC_NEx low to Data valid

Data hold time after FMC_NWE high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. Guaranteed by characterization results.

4T fmc_ker_ck

-0.5

4T fmc_ker_ck

T fmc_ker_ck

-0.5

T fmc_ker_ck

-0.5

T fmc_ker_ck

+0.5

2T fmc_ker_ck

-0.5

3T fmc_ker_ck

-1

3T fmc_ker_ck

-0.5

0.5

2.5

3T fmc_ker_ck

-1

0.5

fmc_ker_ck

+0.5

MS32754V1

Unit ns

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Table 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t w(NWE) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NE low time

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results.

2. N

WAIT

pulse width is equal to 1 AHB cycle.

8T fmc_ker_ck

-0.5

5T fmc_ker_ck

-0.5

8T fmc_ker_ck

6T fmc_ker_ck

8T fmc_ker_ck

+0.5

5T fmc_ker_ck

Figure 27. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE)

FMC_ NE tv(NOE_NE) t h(NE_NOE)

FMC_NOE tw(NOE)

FMC_NWE tv(A_NE) th(A_NOE)

FMC_ A[25:16]

Address tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL th(Data_NE)

FMC_ AD[15:0] t v(NADV_NE) t v(A_NE)

Address th(AD_NADV) tw(NADV) tsu(Data_NE) tsu(Data_NOE)

Data th(Data_NOE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32755V1

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Electrical characteristics STM32MP153A/D

Symbol t w(NE) t v(NOE_NE) t tw(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV) t h(AD_NADV) t h(A_NOE)

Table 61. Asynchronous multiplexed PSRAM/NOR read timings (1)

Parameter Min Max

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time

FMC_AD(address) valid hold time after

FMC_NADV high

4T fmc_ker_ck

-0.5

4T fmc_ker_ck

2T fmc_ker_ck

-0.5

2T fmc_ker_ck

T fmc_ker_ck

-0.5

fmc_ker_ck

-1

T fmc_ker_ck

+0.5

0.5

1.5

T fmc_ker_ck

-3 -

Address hold time after FMC_NOE high t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Data to FMC_NEx high setup time

Data to FMC_NOE high setup time

Data hold time after FMC_NEx high

Data hold time after FMC_NOE high

1. Guaranteed by characterization results.

Address held until next read operation

T fmc_ker_ck

+15

Unit ns

Symbol

Table 62. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings

(1)

Parameter Min Max t t w(NE) t w(NOE) t su(NWAIT_NE) h(NE_NWAIT)

FMC_NE low time

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results.

7T fmc_ker_ck

-0.5

5T fmc_ker_ck

-0.5

7T fmc_ker_ck

5T fmc_ker_ck

8T fmc_ker_ck

6T fmc_ker_ck

Unit ns

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STM32MP153A/D Electrical characteristics

Figure 28. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE)

FMC_ NEx

FMC_NOE

FMC_NWE

FMC_ A[25:16]

FMC_ NBL[1:0]

FMC_ AD[15:0] t v(NADV_NE) tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) t v(A_NE)

Address th(A_NWE)

Address th(BL_NWE)

NBL tv(Data_NADV)

Data th(AD_NADV) tw(NADV) t h(NE_NWE) th(Data_NWE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32756V1

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Electrical characteristics STM32MP153A/D

Symbol

Table 63. Asynchronous multiplexed PSRAM/NOR write timings (1)

Parameter Min Max t t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV) t h(AD_NADV) h(A_NWE)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time T fmc_ker_ck

+0.5

FMC_AD(address) valid hold time after FMC_NADV high T fmc_ker_ck

+0.5

Address hold time after FMC_NWE high

Address held until next write operation t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)

FMC_BL hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_NADV high to Data valid

Data hold time after FMC_NWE high

1. Guaranteed by characterization results.

5T fmc_ker_ck

-0.5

5T fmc_ker_ck

3T fmc_ker_ck

3T fmc_ker_ck fmc_ker_ck

-0.5

+0.5

T fmc_ker_ck

2T fmc_ker_ck

-1 2T fmc_ker_ck

+0.5

2T fmc_ker_ck

-0.5

0.5

1 fmc_ker_ck

0.5

fmc_ker_ck

Unit ns

Symbol

Table 64. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings (1)

Parameter Min Max Unit t w(NE)

FMC_NE low time t w(NWE) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results.

9T fmc_ker_ck

-0.5

9T fmc_ker_ck

+0.5

6T fmc_ker_ck

-0.5

8T fmc_ker_ck

6T fmc_ker_ck

+1 ns

Synchronous waveforms and timings

Figure 29

through Figure 32

represent synchronous waveforms and Table 65

through

Table 68 provide the corresponding timings. The results shown in these tables are obtained

with the following FMC configuration:

• BurstAccessMode = FMC_BurstAccessMode_Enable

• MemoryType = FMC_MemoryType_CRAM

• WriteBurst = FMC_WriteBurst_Enable

• CLKDivision = 1

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

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In all the timing tables, the T fmc_ker_ck

FMC_CLK maximum values:

is the fmc_ker_ck clock period, with the following

• For 2.7 V < V

< 3.6 V, FMC_CLK = 130 MHz at 20 pF

• For 1.71 V < V

< 1.9 V, FMC_CLK = 95 MHz at 20 pF

Figure 29. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx t d(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH)

AD[15:0] tsu(NWAITV-CLKH)

D1 th(CLKH-ADV) tsu(ADV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-ADV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-NWAITV) th(CLKH-NWAITV)

MS32757V1

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Electrical characteristics STM32MP153A/D

Symbol

Table 65. Synchronous multiplexed NOR/PSRAM read timings (1)

Parameter Min t w(CLK) t d(CLKL-NExL) t d(CLKH_NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV) t su(ADV-CLKH) t h(CLKH-ADV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data before FMC_CLK high

FMC_A/D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).

R×T fmc_ker_ck

-1

(2)

R×T fmc_ker_ck

/2+0.5

R×T fmc_ker_ck

/2+1.5

R×T fmc_ker_ck

/2+0.5

1.5

Max

1.5

Unit ns

180/256 DS12502 Rev 6

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Figure 30. Synchronous multiplexed PSRAM write timings tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx td(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) td(CLKL-Data)

AD[15:0] td(CLKL-Data)

D1 D2

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKH-NBLH)

FMC_NBL

MS32758V1

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Electrical characteristics STM32MP153A/D

Symbol

Table 66. Synchronous multiplexed PSRAM write timings (1)

Parameter Min t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t

(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period, V

range = 2.7 to 3.6 V

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).

R×T fmc_ker_ck

-1

(2)

R×T fmc_ker_ck

/2+0.5

R×T fmc_ker_ck

/2+1.5

R×T fmc_ker_ck

/2+0.5

R×T fmc_ker_ck

/2+0.5

1.5

Max

1.5

Unit ns

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Figure 31. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

FMC_CLK td(CLKL-NExL)

Data latency = 0 td(CLKH-NExH)

FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE

FMC_D[15:0] tsu(DV-CLKH) tsu(NWAITV-CLKH)

D1 th(CLKH-DV) tsu(DV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-DV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

Symbol

Table 67. Synchronous non-multiplexed NOR/PSRAM read timings (1)

Parameter t w(CLK) t

(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t su(DV-CLKH) t h(CLKH-DV) t

(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_D[15:0] valid data before FMC_CLK high

FMC_D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

Min

R×T fmc_ker_ck

-1

(2)

R×T fmc_ker_ck

/2+0.5

R×T fmc_ker_ck

/2+1.5

R×T fmc_ker_ck

/2+1.5

through Figure 36 represent synchronous waveforms, and Table 69

1.5

Max

1.5

Unit ns

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Electrical characteristics STM32MP153A/D

2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).

Figure 32. Synchronous non-multiplexed PSRAM write timings tw(CLK) tw(CLK)

FMC_CLK td(CLKL-NExL)

FMC_NEx td(CLKL-NADVL)

FMC_NADV

Data latency = 0 td(CLKL-NADVH) td(CLKH-NExH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE

FMC_D[15:0] td(CLKL-Data)

D1 td(CLKL-Data)

FMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH)

FMC_NBL td(CLKH-NBLH) th(CLKH-NWAITV)

MS32760V1

184/256 DS12502 Rev 6

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Symbol

Table 68. Synchronous non-multiplexed PSRAM write timings (1)

Parameter Min t

(CLK) t d(CLKL-NExL) t

(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-Data) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).

R×T fmc_ker_ck

-1

(2)

R×T fmc_ker_ck

R×T fmc_ker_ck

R×T fmc_ker_ck

R×T fmc_ker_ck

1.5

Max

1.5

Unit ns

NAND controller waveforms and timings

Figure 33

and Table 70

provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration:

• FMC_SetupTime = 0x01

• FMC_WaitSetupTime = 0x03

• FMC_HoldSetupTime = 0x02

• FMC_HiZSetupTime = 0x01

• Bank = FMC_Bank_NAND

• MemoryDataWidth = FMC_MemoryDataWidth_16b

• ECC = FMC_ECC_Enable

• ECCPageSize = FMC_ECCPageSize_512Bytes

• TCLRSetupTime = 0

• TARSetupTime = 0

• C

= 30 pF

In all timing tables, the T fmc_ker_ck

is the fmc_ker_ck clock period.

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Electrical characteristics STM32MP153A/D

Figure 33. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE td(ALE-NOE) th(NOE-ALE)

FMC_NOE (NRE) tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32767V1

Figure 34. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE td(ALE-NWE) th(NWE-ALE)

FMC_NOE (NRE)

FMC_D[15:0] tv(NWE-D) th(NWE-D)

MS32768V1

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Figure 35. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) td(ALE-NOE) th(NOE-ALE)

FMC_NWE tw(NOE)

FMC_NOE tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32769V1

Figure 36. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) td(ALE-NOE)

FMC_NWE tw(NWE) th(NOE-ALE)

FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32770V1

Symbol

Table 69. Switching characteristics for NAND Flash read cycles (1)

Parameter t w(N0E) t su(D-NOE) t h(NOE-D) t d(ALE-NOE) t h(NOE-ALE)

FMC_NOE low width

FMC_D[15-0] valid data before FMC_NOE high

FMC_D[15-0] valid data after FMC_NOE high

FMC_ALE valid before FMC_NOE low

FMC_NWE high to FMC_ALE invalid

1. Guaranteed by characterization results.

Min

4T fmc_ker_ck

-1

3T fmc_ker_ck

+0.5

Max

4T fmc_ker_ck

2T fmc_ker_ck

Unit ns

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Electrical characteristics STM32MP153A/D

Symbol

Table 70. Switching characteristics for NAND Flash write cycles (1)

Parameter t w(NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t d(ALE-NWE) t h(NWE-ALE)

FMC_NWE low width

FMC_NWE low to FMC_D[15-0] valid

FMC_NWE high to FMC_D[15-0] invalid

FMC_D[15-0] valid before FMC_NWE high

FMC_ALE valid before FMC_NWE low

FMC_NWE high to FMC_ALE invalid

1. Guaranteed by characterization results.

Min

4T fmc_ker_ck

-1

3T fmc_ker_ck

4T fmc_ker_ck

-3

3T fmc_ker_ck

+0.5

Max

4T fmc_ker_ck

2T fmc_ker_ck

Unit ns

6.3.20 QUADSPI interface characteristics

Unless otherwise specified, the parameters given in

Table 71 and

Table 72 for QUADSPI

are derived from tests performed under the ambient temperature, F axiss_ck

DD the following configuration:

frequency and

supply voltage conditions summarized in

Table 13: General operating conditions , with

• Output speed is set to OSPEEDRy[1:0] = 11

• Measurement points are done at CMOS levels: 0.5×V

• I/O compensation cell enabled

• HSLV activated when V

≤ 2.7 V

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics.

Symbol

F ck1/t(CLK) t w(CLKH) t w(CLKL) t s(IN) t h(IN) t v(OUT) t h(OUT)

Table 71. QUADSPI characteristics in SDR mode

Parameter Conditions Min Typ

QUADSPI clock frequency

2.7 V ≤ V

< 3.6 V

= 20 pF

1.71 V < V

<3.6 V

= 15 pF

QUADSPI clock high and low time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

(CLK)

/2 - 0.5

(CLK)

/2 - 0.5

1.25

2.75

Max

166

90 t

(CLK)

/2 + 0.5

(CLK)

/2 + 0.5

1.5

Unit

MHz ns

188/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Symbol

Table 72. QUADSPI characteristics in DDR mode

Parameter Conditions t t t t

F ck1/t(CLK)

QUADSPI clock frequency t w(CLKH) t w(CLKL)

QUADSPI clock high and low time t sr(IN)

, t sf(IN)

Data input setup time t hr(IN)

, t hf(IN)

Data input hold time vr(OUT) vf(OUT) hr(OUT) hf(OUT)

Data output valid time

Data output hold time

2.7 V < V

< 3.6 V

CL=20 pF

1.71 V < V

< 3.6 V

CL=15 pF

DHHC = 0

DHHC = 1

Pres = 1, 2...

DHHC = 0

DHHC = 1

Pres = 1, 2...

Min

(CLK)

/2 - 0.5

(CLK)

/2 - 0.5

0.5

2.75

0 t

(CLK)

Typ

1 t

(CLK)

/2 + 0.5

(CLK)

/2 + 0.5

1.5

(CLK)

/4+1 t

(CLK)

/4+1.5

Max

Unit

MHz ns t r(CLK)

Figure 37. QUADSPI timing diagram - SDR mode t

(CLK) t w(CLKH) t w(CLKL) t f(CLK)

Clock

Data output

Data input t v(OUT) t h(OUT)

IO0

IO0 t s(IN)

IO1 t h(IN)

IO1

IO2

IO2 t r(CLK)

Figure 38. QUADSPI timing diagram - DDR mode t

(CLK) t w(CLKH) t w(CLKL) t f(CLK)

MSv36878V2

Clock

Data output

Data input t vf(OUT) t hr(OUT)

IO0

IO1 t sf(IN) t hf(IN)

IO1

IO2

IO2 t vr(OUT) t hf(OUT)

IO3

IO4 t sr(IN) t hr(IN)

IO5

IO4 IO5

MSv36879V3

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Electrical characteristics STM32MP153A/D

6.3.21 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 73

for the delay block are derived from tests performed under the ambient temperature, f rcc_c_ck

frequency and V

voltage summarized in Table 13: General operating conditions

supply t init t

∆

Symbol

Table 73. Dynamics characteristics: Delay block characteristics

Parameter Conditions Min Typ Max

Initial delay

Unit Delay -

900

1200

1500

Unit ps

6.3.22 16-bit ADC characteristics

Unless otherwise specified, the parameters given in

Table 74 are derived from tests

performed under the ambient temperature, f pclk2

frequency and V

DDA

supply voltage

conditions summarized in Table 13: General operating conditions

Symbol

DDA

REF+

REF-

ADC

Parameter

Table 74. ADC characteristics (1)(2)

Conditions Min

Analog power supply

Positive reference voltage

Negative reference voltage

ADC clock frequency

DDA

≥ 2 V

DDA

< 2 V

1.62

2 V ≤ V

DDA

≤3.3 V

BOOST = 1 0.12

BOOST = 0 0.12

Typ

DDA

SSA

Max

3.6

DDA

Unit

MHz

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STM32MP153A/D Electrical characteristics

Symbol f

S f

TRIG

Parameter

Table 74. ADC characteristics (1)(2) (continued)

Sampling rate for Fast channels, BOOST = 1, f

ADC

= 36 MHz, sampling time = 1.5 cycles

Sampling rate for Fast channels, BOOST = 0, f

ADC

= 20 MHz, sampling time = 1.5 cycles

Sampling rate for Slow channels, BOOST = 1, f

ADC

= 28 MHz, sampling time = 2.5 cycles

Sampling rate for Slow channels, BOOST = 0, f

ADC

= 20 MHz, sampling time = 2.5 cycles

External trigger frequency

AIN

(3)

CMIV

ADC

Conversion voltage range

Common mode input voltage

Internal sample and hold capacitor t

ADCREG_

STUP t

STAB

ADC LDO startup time

ADC power-up time

Conditions

16-bit resolution

14-bit resolution

12-bit resolution

10-bit resolution

8-bit resolution

16-bit resolution

14-bit resolution

12-bit resolution

10-bit resolution

8-bit resolution

16-bit resolution

14-bit resolution

12-bit resolution

10-bit resolution

8-bit resolution

16-bit resolution

14-bit resolution

12-bit resolution

10-bit resolution

8-bit resolution f

ADC

= 36 MHz

16-bit resolution

LDO already started

Min

Typ

Max

2.50

2.86

3.6

REF

REF+

REF

/2+

10%

2.80

3.30

2.55

2.80

3.11

3.50

4.00

1.82

2.00

2.22

6.00

2.00

2.20

2.50

3.60

4.00

4.50

5.00

REF

/2-

10%

Unit

MSPS

MHz

1/f

ADC

V pF

µs

1/f

ADC

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Electrical characteristics STM32MP153A/D

Symbol Parameter

Table 74. ADC characteristics (1)(2) (continued)

Conditions Min Typ Max t

CAL

Offset and linearity calibration time

Offset calibration time

OFF_CAL

t t

LATR

LATRINJ

Trigger conversion latency for regular and injected channels without aborting the conversion

Trigger conversion latency for regular and injected channels when a regular conversion is aborted

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11 t t

CONV

Sampling time

Total conversion time

(including sampling time)

N-bit resolution

DDA(ADC)

DDA(REF)

DDA(ADC)

ADC consumption from

DDA

supply (single-ended)

DDA(REF)

ADC consumption from

DDA

supply (differential)

ADC consumption from

REF+

(differential)

ADC consumption from

REF+

supply (singleended)

= 3.6 Msps, BOOST = 1

= 1 Msps, BOOST = 0

= 3.6 Msps, BOOST = 1

= 1 Msps, BOOST = 0

= 3.6 Msps, BOOST = 1

= 1 Msps, BOOST = 0

= 3.6 Msps, BOOST = 1

= 1 Msps, BOOST = 0 -

1. Guaranteed by design.

2. Voltage BOOSTER on ADC switches must be used for V

DDA

< 2.4 V (switches inside IO).

3. Depending on the package, V

REF-

can be internally connected to V

SSA

4. 9 to 818 cycles @ 14-bit mode.

2.5

1.5

16384 t s

+ N/2

(4)

1280

1900

460

260

140

1700

445

160

2.5

2.25

3.5

3.25

810.5

Unit

1/f

ADC

μA

192/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Table 75. Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 °C and V

DDA

= 1.6 V (1)

Resolution

(2)

RAIN (Ω)

Fast channels

(3)

(ns)

Slow channels

(4)

(ns)

16 bits 47

(5)

107 166

14 bits

12 bits

10 bits

100

150

220

100

150

220

330

470

680

1000 (5)

100

150

220

330

470

680

1000

1500

2200

3300

4700

137

168

209

279

381

552

786

1140

1600

345

488

103

106

112

121

192

125

127

134

146

144

151

157

171

169

205

264

106

140

187

258

367

537

776

1130

1600

329

462

62.5

66.2

72.7

85.4

161

76.7

81.5

89.8

107

90.8

967

108

128

132

177

2.36

DS12502 Rev 6 193/256

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Electrical characteristics STM32MP153A/D

Table 75. Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 °C and V

DDA

= 1.6 V (1) (continued)

Resolution

(2)

RAIN (Ω)

Fast channels

(3)

(ns)

Slow channels

(4)

(ns)

8 bits

680

1000

1500

2200

3300

4700

6800

10000

15000

2200

1. Refer to Table 74 for the values of RAIN, RADC and CADC.

100

150

220

330

470

48.7

51.4

56.4

65.8

80.4

106

139

189

269

390

562

827

1170

1670

2440

3660

5360

1. Guaranteed by design.

2. The tolerance is 8 LSB for 16-bit, 4 LSB for 14-bit, 2 LSB for 12-bit, 10-bit and 8-bit conversions.

3. On ADC1, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF11, PF12.

On ADC2, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF13, PF14.

4. Slow channels are all ADC inputs except the fast channels.

5. Maximum external input impedance value authorized for the given resolution.

208

284

405

572

840

1170

1670

2430

3630

5310

82.4

84.6

88.7

95.7

108

130

160

194/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Symbol Parameter

Table 76. ADC accuracy (1)(2)(3)(4)(5)(6)(7)

Conditions

(8)

Min Typ

(9)

Max Unit

(10)

ENOB

SINAD

SNR

THD

(11)

Total unadjusted error

Differential linearity error

Integral linearity error

Effective number of bits

(2 MSPS)

Signal-tonoise and distortion ratio

(2 MSPS)

Signal-tonoise ratio

(2 MSPS)

Total harmonic distortion

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

BOOST = 1

BOOST = 0

±LSB bits dB

1. Guaranteed by characterization.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy versus negative injection current: injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The above table gives the ADC performance in 16-bit mode.

5. Dual Simultaneous mode is limited to 12-bit.

6. Dual mode consisting in an injected conversion (reset) occurring during another (regular) conversion is forbidden.

7. Dual Interleaved 16-bit/14-bit/12-bit modes can work if the delay between the 2 ADCs is as specified in

Table 77

77.6

82.4

84.3

-85

-88

-90

-93

13.3

13.7

77.5

78.75

84.2

±6

±4

±6

±4

12.5

12.75

±5

±7

±6

±5

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Electrical characteristics STM32MP153A/D

8. ADC clock frequency ≤36 MHz, 2 V ≤ V

DDA

≤ 3.3 V, 1.6 V ≤ V

REF+

≤ V

DDA

, BOOSTEN (for I/O) = 1.

9. V

DDA

= V

REF+

= 3.3 V, 25 °C.

10. ET, ED, EL are specified for [2 V ≤ V

DDA

≤ 3.3 V with 2 V ≤ V

REF+

≤ V

DDA

] and [1.6V ≤ V

DDA

≤ 2 V with 1.6V ≤ V

REF+

≤

11. ENOB, SINAD, SNR and THD are specified for V

DDA

= V

REF+

= 3.3 V.

Table 77. Minimum delay for interleaved conversion versus resolution

16-bit Mode 14-bit mode 12-bit Mode

Boost Fclk (MHz)

Delay

ADC1/ADC2

(clock cycles)

4.5

5.5

4.5

2.5

3.5

4.5

5.5

1.5

2.5

1.5

Data rate

(MSPS)

Delay

ADC1/ADC2

(clock cycles)

3.5

4.5

3.5

2.5

3.5

4.5

1.5

3.7

3.8

4.0

4.2

4.3

3.9

2.3

2.4

2.6

2.7

2.9

3.5

2.0

1.8

2.0

1.8

2.0

2.2

2.3

2.1

2.0

1.7

2.0

1.8

1.0

2.0

1.5

Data rate

(MSPS)

Delay

ADC1/ADC2

(clock cycles)

3.5

1.5

2.5

3.5

1.5

4.4

4.6

4.0

4.2

4.3

4.5

2.7

2.8

3.0

3.2

3.3

4.2

2.0

2.3

2.0

2.2

2.0

2.2

2.3

2.5

2.0

1.7

2.0

2.3

1.0

2.0

1.5

Data rate

(MSPS)

4.4

4.6

4.8

5.0

5.2

5.4

3.2

3.4

3.6

3.8

4.0

4.2

2.7

2.3

2.5

2.8

2.4

2.6

2.8

3.0

2.0

2.5

2.0

2.3

1.0

2.0

1.5

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Table 77. Minimum delay for interleaved conversion versus resolution (continued)

16-bit Mode 14-bit mode 12-bit Mode

Boost Fclk (MHz)

Delay

ADC1/ADC2

(clock cycles)

5.5

4.4

4.6

4.7

4.9

4.0

4.1

4.3

5.0

5.1

Data rate

(MSPS)

Delay

ADC1/ADC2

(clock cycles)

4.5

5.2

5.3

5.5

5.7

4.7

4.8

5.0

5.8

6.0

Data rate

(MSPS)

Delay

ADC1/ADC2

(clock cycles)

3.5

Data rate

(MSPS)

6.2

6.4

6.6

6.8

5.6

5.8

6.0

7.0

7.2

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN)

Section 6.2

does not affect the ADC accuracy.

and ∑I

INJ(PIN)

DS12502 Rev 6 197/256

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Electrical characteristics STM32MP153A/D

Figure 39. ADC accuracy characteristics

V REF+

[1LSB IDEAL =

4096

V DDA

(or depending on package)]

4096

4095

4094

4093

(2)

EO EL

1L SBIDEAL

(3)

(1)

VSSA

1 2 3 456 7 4093 4094 4095 4096

VDDA

1. Example of an actual transfer curve.

2. Ideal transfer curve.

3. End point correlation line.

4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

Figure 40. Typical connection diagram using the ADC ai14395c

VAIN

RAIN(1)

AINx

Cparasitic

VDD

0.6 V

IL±1 μA

STM32

Sample and hold ADC converter

RADC(1)

12-bit converter

CADC(1) ai17534b

2. C f pad capacitance (roughly 5 pF). A high C

ADC

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

should be reduced.

parasitic

value downgrades conversion accuracy. To remedy this,

198/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

General PCB design guidelines

PCB design guidelines are provided in AN5031 “Getting started with STM32MP1 Series hardware development.” available from the ST website www.st.com

6.3.23 DAC electrical characteristics

Symbol

DDA

REF+

REF-

BON

BOFF

Parameter

Table 78. DAC characteristics (1)(2)

Conditions

Analog supply voltage

Positive reference voltage

Negative reference voltage

Resistive Load

Output Impedance

Output impedance sample and hold mode, output buffer ON

Output impedance sample and hold mode, output buffer OFF

DAC output buffer ON, Not valid in Sample

& Hold mode connected to

SSA connected to

DDA

DAC output buffer OFF

= 2.7 V

DAC output buffer ON

DAC output buffer OFF

= 2.7 V

= 2.0 V

Capacitive Load

DAC output buffer OFF

Sample and Hold mode

Min

1.8

1.80

10.3

25 -

0.1

Typ

3.3

SSA

Max Unit

3.6

DDA

0.2

0 -

1.6

2.6

17.8

18.7

DDA

0.2

(3)

REF

+ kΩ kΩ kΩ pF

µF

DAC output buffer ON

DAC_OUT

Voltage on DAC_OUT output

DAC output buffer OFF t

SETTLING t

WAKEUP

(4)

PSRR

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DAC_OUT reaches the final value of ±1LSB)

Normal mode,

DAC output buffer ON

±1 LSB

Normal mode,

DAC output buffer OFF,

+/-1LSB, Cload ≤ 10 pF

Wakeup time from off state (setting the Enx bit in the DAC Control register) until the ±1LSB final value

Normal mode,

DAC output buffer ON

Normal mode,

DAC output buffer OFF

DDA

supply rejection ratio

Normal mode

DAC output buffer ON

-80

7.5

-28

µs

µs dB

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Electrical characteristics STM32MP153A/D

Symbol t

SAMP

CI int

V offset

DDA(DAC)

DDV(DAC)

Table 78. DAC characteristics (1)(2) (continued)

Parameter Conditions Min

Sampling time in Sample and Hold mode

=100nF

(Code transition between the lowest input code and the highest input code when DAC_OUT reaches final value ± 1LSB)

DACMCR.MODEx

[2:0] =

100/101

(BUFFER ON)

DACMCR.MODEx[2:0] = 110

(BUFFER OFF)

DACMCR.MODEx[2:0] = 111

(INTERNAL BUFFER OFF)

Internal sample and hold capacitor

Middle code offset for 1 trim code step

REF+

= 3.6 V

REF+

= 1.8 V -

DAC output buffer ON

No load, middle code (0x800)

No load, worst code (0xF1C)

DAC quiescent consumption from V

DDA

DAC output buffer OFF

No load, middle/worst code (0x800)

Sample and Hold mode,

= 100 nF

Typ

0.7

11.5

0.3

2.2

450

213

360

490

360×TON/

(TON+TOFF)

(5)

DAC consumption from

REF+

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code (0xF1C)

No load, middle/worst code (0x800)

170

160

Sample and Hold mode, Buffer

ON, C

= 100 nF (worst code)

Sample and Hold mode, Buffer

OFF, C

= 100 nF (worst code)

170×TON/

(TON+TOFF)

170×TON/

(TON+TOFF)

Max Unit

ms pF

µV

µA

1. Guaranteed by design.

2. Unless otherwise noted, C output buffer is OFF.

≤ 50 pF with R

≥ 5 kΩ when DAC output buffer is ON, or C

≤ 10 pF with no R

when DAC

3. Since V

REF+

must always be ≤ VDDA, maximum V

DAC_OUT

= minimum value between Max(V

REF+

) and Max(V

DDA

-0.2)

4. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).

5. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more details.

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STM32MP153A/D Electrical characteristics

Symbol Parameter

Table 79. DAC accuracy (1)

Conditions Min Typ

(2)

Max Unit

DNL

INL

Offset

Offset1

Gain

TUECal

SNR

THD

SINAD

ENOB

Differential non linearity

(3)

Integral non linearity

(4)

Offset error at code

0x800

(4)

DAC output buffer ON

REF+

3.6 V

REF+

1.8 V

DAC output buffer OFF

Offset error at code

0x001

(5)

Gain error

(6)

Total unadjusted error

DAC output buffer OFF

DAC output buffer ON

1 kHz

REF+

=3.6 V

=1.8 V

Signal-tonoise ratio

(7)

Total harmonic

distorsion (7)

1 kHz, BW = 500 kHz

1kHz

Signal-tonoise and distortion

ratio

(7)

Effective number of bits

±2

±4

±5

±7

±8

±5

±1

±10

±8

67.8

-78.6

67.5

10.9

LSB

LSB dB dB dB bits

1. Unless otherwise noted, C output buffer is OFF.

≤ 50 pF with R

≥ 5 kΩ when DAC output buffer is ON, or C

≤ 10 pF with no R

when DAC

2. Guaranteed by characterization.

3. Difference between two consecutive codes minus 1 LSB.

4. Difference between measured the value at Code i and the value measured at Code i on a line drawn between Code 0 and last Code 4095.

5. Difference between the value measured at Code (0x001) and the ideal value.

6. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF when the buffer is OFF, and from code giving 0.2 V and (V

REF+

- 0.2 V) when the buffer is ON.

7. Signal is -0.5dBFS with F sampling

=1 MHz.

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Electrical characteristics

Figure 41. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

R L

DAC_OUTx 12-bit digital to analog converter

C L

STM32MP153A/D ai17157V3

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

6.3.24 Voltage reference buffer characteristics

Symbol

DDA

TRIM

Parameter

Analog supply voltage

REFBUF

_OUT

Voltage Reference

Buffer Output

Trim step resolution

Load capacitor

Table 80. VREFBUF characteristics (1)

Conditions

Normal mode

Degraded mode

(2)

Normal mode

@30 °C

V load

= 10 uA

DDA

= 3.3 V

Degraded mode

VSCALE = 000

VSCALE = 001

VSCALE = 010

VSCALE = 011

VSCALE = 000

VSCALE = 001

VSCALE = 010

VSCALE = 011

VSCALE = 000

VSCALE = 001

VSCALE = 010

VSCALE = 011

VSCALE = 000

VSCALE = 001

VSCALE = 010

VSCALE = 011

Min Typ Max

2.8

2.4

2.1

1.8

1.62

3.3

1.62

1.80

2.498

2.500

2.502

2.047

2.049

2.051

1.800

1.804

1.807

1.500

1.504

1.507

DDA

220 mV

DDA

220 mV

DDA

220 mV

DDA

220 mV

±0.05

DDA

0.5

1 1.50

3.6

2.80

2.40

2.10

Unit

% uF

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STM32MP153A/D Electrical characteristics

Symbol Parameter

Table 80. VREFBUF characteristics (1) (continued)

Conditions Min Typ Max Unit

I esr load line_reg

Equivalent Serial

Resistor of C

Static load current

Line regulation 2.8 V ≤ V

DDA

≤ 3.6 V

I load

= 500 µA

I load

= 4 mA

200

100

Ω mA ppm/V

I load_reg

Load regulation

500 µA ≤ I

LOAD

4 mA

≤

Normal Mode 50 ppm/ mA

T coeff

PSRR t

START

Temperature coefficient

Power supply rejection

Start-up time

(3)

-40 °C < T

100 kHz

= 0.5 µF

= 1 µF

= 1.5 µF

< +125 °C -

T coeff_

VREF

INT

+75

300

500

650

350

650

800 ppm/

°C dB

µs

INRUSH

Control of maximum

DC current drive on

REFBUF_OUT startup phase

during

(4)

8 13.5

DDA(VRE

FBUF)

VREFBUF consumption from

DDA

LOAD

= 0 µA

LOAD

= 500 µA

LOAD

= 4 mA -

µA

VREF

BUF_PullD own

Pull-down resistor when ENVR = HIZ = 0

100 Ω

1. Guaranteed by design.

2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (V

DDA

-drop voltage).

3. if VREF+ pin has residual voltage when VREFBUF is enabled (VREFBUF_CSR.ENVR=1), this might create an overshoot on VREFBUF output longer than t

START

To avoid this, it is necessary that VREF+ pin is correctly discharged before being enabled (below VREFBUF_OUT minus

1 V, for example below 1.5 V for VSCALE = 000)

This could be achieved by ensuring VREFBUF is in OFF mode (VREFBUF_CSR.ENVR=0 and VREFBUF_CSR.HIZ=0) for sufficient time to discharge C

through VREFBUF pull-down.

4. To properly control VREFBUF I

INRUSH

current during the startup phase and the change of scaling, V

DDA voltage should be in the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.

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Electrical characteristics STM32MP153A/D

6.3.25 Temperature sensor characteristics

Symbol

Table 81. Temperature sensor characteristics

Parameter Min Typ Max Unit

(1)

VSENSE linearity with temperature (from Vsensor voltage)

VSENSE linearity with temperature (from ADC counter) 3

Avg_Slope

(2)

Average slope (from Vsensor voltage) 2 -

Average slope (from ADC counter) 2 -

(3) t start_run

Voltage at 30 °C ± 5 °C

Startup time in Run mode (buffer startup)

ADC sampling time when reading the temperature

Sensor consumption

Sensor buffer consumption

5.3

9.8

0.11 0.18 0.31

2.3

0.62

3.8

40.5

6.1

1. Guaranteed by design.

2. Guaranteed by characterization.

3. Measured at V

DDA

= 3.3 V ± 10 mV. The V

ADC conversion result is stored in the TS_CAL1 byte.

°C mV/°C

µs

µA

Symbol

Table 82. Temperature sensor calibration values

Parameter Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at temperature of

30 °C ±5 °C

DDA

= V

REF+

= 3.3 V ±10 mV

TS ADC raw data acquired at temperature of

130 °C ±2 °C

DDA

= V

REF+

= 3.3 V ±10 mV

0x5C00 525C[15:0]

(1)(2)

0x5C00 525C[31:16]

(1)(2)

1. It is mandatory to read a 32-bit word and to do relevant masking and shifting to isolate the required bits.

2. This address is located inside the BSEC and the access is allowed after being enabled in the RCC.

6.3.26 DTS characteristics

Symbol f

DTS

SLOPE

TOTAL_

ERROR

Table 83. DTS characteristics

(1)

Parameter

Output Clock frequency (PTAT clock)

Average slope

Linearity with temperature (from

Output clock frequency).

Conditions

DDCORE

= 1.2 V

Temperature measurement error

DDCORE

= 1.2 V

Temperature:

-40 to 125 °C

Min Typ Max Unit

500 -

1600 -

3.8

kHz

Hz/°C

°C

-5 +5 °C

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STM32MP153A/D Electrical characteristics

Symbol

Table 83. DTS characteristics (1) (continued)

Parameter

VDD

CORE t

TRIM

Additional error due to V variation

DDCORE t

WAKE_UP

Calibration time

Wake-up time from off state until

DTS ready signal = 1

DDCORE_DTS

DTS consumption on V

1. Guaranteed by design.

DDCORE

Conditions

Min Typ Max Unit

20 -

°C/V ms

μs

µA

6.3.27 V

BAT

ADC monitoring characteristics and charging characteristics

Symbol

Table 84. V

BAT

ADC monitoring characteristics

Parameter t

(1)

S_vbat

Resistor bridge for V

BAT

Ratio on V

BAT

Error on Q

measurement

ADC sampling time when reading V

BAT input

1. Guaranteed by design.

Min

–10

9.8

Typ

Max

+10

Unit kΩ

µs

Symbol

Table 85. V

BAT

charging characteristics

Parameter Condition Min

Battery charging resistor

VBRS in PWR_CR3= 0

VBRS in PWR_CR3= 1 -

Typ

1.5

Max Unit

kΩ

6.3.28 Temperature and V

BAT

monitoring characteristics for tamper detection

Table 86. Temperature and V

BAT

monitoring characteristics for temper detection

Symbol Parameter Min Typ Max Unit

TEMP high

TEMP low

BAThigh

(1)

BATlow

Table 90 for DFSDM are derived from

High temperature monitoring

Low temperature monitoring

High supply monitoring

Low supply monitoring

1. Monitored supply is V

(i.e. V

if V

is present, V

BAT

otherwise)

105

-42

3.47

1.3

116

-31

3.59

1.34

126

-20

3.73

1.43

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Electrical characteristics STM32MP153A/D

6.3.29 V

DDCORE

monitoring characteristics

Symbol

Table 87. V

DDCORE

monitoring characteristics

Parameter t

S_vddcore

(1)

ADC sampling time when reading V

DDCORE input

1. Guaranteed by design.

Min

100

Typ

Max

Unit ns

6.3.30 Voltage booster for analog switch

Symbol

Table 88. Voltage booster for analog switch characteristics

Parameter

DD t

SU(BOOST)

Supply voltage

Booster startup time

DD(BOOST)

Booster consumption

Condition

1.71 V ≤ V

≤ 2.7 V

2.7 V < V

< 3.6 V

Min Typ Max Unit

1.71

3.6

125

250

µs

µA

6.3.31 Compensation cell

Symbol

Table 89. Compensation cell characteristics

Parameter Condition Min Typ Max Unit

COMPCELL

current consumption during code calculation

READY

Time needed for code calculation

1.71 V ≤ V

≤ 2.7 V

2.7 V < V

< 3.6 V

1.71 V ≤ V

≤ 2.7 V

2.7 V < V

< 3.6 V -

3.5

300

250 mA

µs

6.3.32 Digital filter for sigma-delta modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in

tests performed under the ambient temperature, f pclkx

frequency and V

supply voltage summarized in

Table 13: General operating conditions , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5×V

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for

DFSDMx).

206/256 DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Symbol Parameter

Table 90. DFSDM measured timing

Conditions Min Typ Max Unit f

DFSDMCLK f

CKIN

(1/T

CKIN

) f

CKOUT

DFSDM clock 1.71 V < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 V < V

< 3.6 V

Input clock frequency

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

2.7 < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0] ≠ 0),

1.71 < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0] ≠ 0),

2.7 < V

< 3.6 V

Output clock frequency

1.71 < V

< 3.6 V -

DuCy

CKOUT

Output clock frequency duty cycle

1.71 < V

< 3.6 V

Even division

CKOUTDIV[7:0] = n

1,3,5,..

Odd division

CKOUTDIV[7:0] = n

2,4,6,..

(((n/2+1)/

(n+1))*100)-5

((n/2+1)/

(n+1))*100 t t t t

T wh(CKIN) wl(CKIN) su h

Manchester

Input clock high and low time

Data input setup time

Data input hold time

Manchester data period

(recovered clock period)

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < V

< 3.6 V

Manchester mode (SITP[1:0]=2,3),

Internal clock mode

(SPICKSEL[1:0]≠0),

1.71 < V

< 3.6 V

CKIN

/2 - 0.5

CKIN

0.5

(CKOUTDIV+

×T

1. See DFSDM section in RM0442 reference manual for definition of CKOUTDIV.

/2 f

SYSCLK

DFSDMCLK

/4)

DFSDMCLK

/4)

DFSDMCLK

/4)

MHz

DFSDMCLK

/4)

(((n/2+1)/

(n+1))*100)

(2×CKOUT

DIV) ×

% ns

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234

Electrical characteristics

Figure 42. Channel transceiver timing diagrams

STM32MP153A/D

(SPICKSEL=0) t su t h t wl t wh t r t f

SITP = 00 t su t h

SITP = 01

SPICKSEL=3

SPICKSEL=2

SPICKSEL=1

SITP = 0

SITP = 1 t su t h t wl t wh t r t f t su t h

SITP = 2

SITP = 3 recovered clock recovered data

0 0 1 1 0

MS30766V2

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6.3.33 Camera interface (DCMI) characteristics

Unless otherwise specified, the parameters given in

Table 91 for DCMI are derived from

tests performed under the ambient temperature, F mcu_ck

frequency and V

supply voltage summarized in

Table 13: General operating conditions , with the following configuration:

• DCMI_PIXCLK polarity: falling

• DCMI_VSYNC and DCMI_HSYNC polarity: high

• Data formats: 14 bits

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5×V

Symbol

Table 91. DCMI characteristics (1)

Parameter Min Max Unit

Frequency ratio DCMI_PIXCLK/F mcu_ck

DCMI_PIXCLK Pixel clock input

Pixel t su(DATA) t h(DATA) t su(HSYNC) t su(VSYNC) t h(HSYNC) t h(VSYNC)

Pixel clock input duty cycle

Data input setup time

Data input hold time

DCMI_HSYNC/DCMI_VSYNC input setup time

DCMI_HSYNC/DCMI_VSYNC input hold time

1. Guaranteed by characterization results.

0.5

0.4

MHz

% ns

Figure 43. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK t su(HSYNC) t h(HSYNC)

DCMI_HSYNC t su(VSYNC) t h(HSYNC)

DCMI_VSYNC t su(DATA) t h(DATA)

DATA[0:13]

MS32414V2

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Electrical characteristics STM32MP153A/D

6.3.34 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 92 for LCD-TFT are derived from

tests performed under the ambient temperature, F pclk4

frequency and V

supply voltage summarized in

Table 13: General operating conditions , with the following configuration:

• LCD_CLK polarity: high

• LCD_DE polarity: low

• LCD_VSYNC and LCD_HSYNC polarity: high

• Pixel formats: 24 bits

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5×V

• I/O compensation cell enabled

Symbol f

CLK

Parameter

Table 92. LTDC characteristics

(1)

Conditions

LTDC clock output frequency

LTDC clock output duty cycle

2.7 V < V

< 3.6 V

OSPEEDR[1:0] = 11, 10

1.71 V < V

< 3.6 V

OSPEEDR[1:0] = 11

1.71 V < V

< 3.6 V

OSPEEDR[1:0] = 10

CLK t w(CLKH), t w(CLKL)

Clock High time, low time -

Min

Max

55 t w(CLK)

/2 - 0.5 t w(CLK)

/2 + 0.5

t v(DATA)

Data output valid time t h(DATA) t v(HSYNC), t v(VSYNC), t v(DE) t h(HSYNC), t h(VSYNC) t h(DE)

Data output hold time

HSYNC/VSYNC/DE output valid time

HSYNC/VSYNC/DE output hold time

1. Guaranteed by characterization results.

OSPEEDR[1:0] = 11

OSPEEDR[1:0] = 10

OSPEEDR[1:0] = 11

OSPEEDR[1:0] = 10

2.5

3.5

Unit

MHz

% ns

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Figure 44. LCD-TFT horizontal timing diagram tCLK

LCD_CLK

LCD_VSYNC tv(HSYNC)

LCD_HSYNC tv(HSYNC) tv(DE) th(DE)

LCD_DE

LCD_R[0:7]

LCD_G[0:7]

LCD_B[0:7]

HSYNC width tv(DATA)

Pixel

Horizontal back porch th(DATA)

Active width

Pixel

Horizontal back porch

One line

MS32749V1 tCLK

Figure 45. LCD-TFT vertical timing diagram

LCD_CLK tv(VSYNC) tv(VSYNC)

LCD_VSYNC

LCD_R[0:7]

LCD_G[0:7]

LCD_B[0:7]

M lines data

VSYNC width

Vertical back porch

Active width

One frame

Vertical back porch

MS32750V1

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6.3.35 Timer characteristics

The parameters given in

Table 93 are guaranteed by design.

Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 93. TIMx characteristics

(1)(2)

Parameter t t res(TIM) f

TIMxCLK f

EXT

Res

TIM

MAX_COUNT

Timer resolution time

Timer kernel clock

Timer external clock frequency on CH1 to CH4

Timer resolution

Maximum possible count with 16-bit counters

Maximum possible count with 32-bit counter

(TIM2, TIM5)

1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.

2. Guaranteed by design.

Min

Max

209 f

TIMxCLK

16/32

65536

65536 ×

65536

Unit t

TIMxCLK

MHz bit t

TIMxCLK

Symbol

Table 94. LPTIMx characteristics (1)(2)

Parameter Min f t f res(TIM)

LPTIMxCLK

EXT

Timer resolution time

Timer kernel clock

Timer external clock frequency on Input1 and

Input2

Res

TIM t

MAX_COUNT

Timer resolution

Maximum possible count

1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers.

2. Guaranteed by design.

Max

104.5

LPTIMxCLK

65536

Unit t

TIMxCLK

MHz bit t

TIMxCLK

6.3.36 Communications interfaces

I2C interface characteristics

The I2C interface meets the timings requirements of the I 2 C-bus specification for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s.

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I

C timings requirements are guaranteed by design when the I2C peripheral is properly configured and when the i2c_ker_ck frequency is greater than the minimum shown in the table below:

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STM32MP153A/D Electrical characteristics

Symbol f(I2CCLK)

Table 95. Minimum i2c_ker_ck frequency in all I2C modes

Parameter Condition Min

I2CCLK frequency

Standard-mode

Fast-mode

Fast-mode Plus

Analog filter ON

DNF=0

Analog filter OFF

DNF=1

Analog filter ON

DNF=0

Analog filter OFF

DNF=1

Unit

MHz

The SDA and SCL I/O requirements are met with the following restrictions:

• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

is disabled, but is still present.

• The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load C load

supported in Fm+, which is given by these formulas: t r(SDA/SCL)

= 0.8473 × R p

× C load

R p(min)

= (V

-V

OL(max)

)/I

OL(max)

Where R p

is the I2C lines pull-up. Refer to Section 6.3.17: I/O port characteristics

for the I2C

I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 96

for the analog filter characteristics:

Symbol

Table 96. I2C analog filter characteristics

(1)

Parameter t

Maximum pulse width of spikes that are suppressed by the analog filter

1. Guaranteed by design.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered.

Min

(2)

Max

260

(3)

Unit ns

The I2C pins can be set in FM+ mode in SYSCFG_PMCR register.

Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the ambient temperature and V

DD in

Table 13: General operating conditions .

supply voltage conditions summarized

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Electrical characteristics STM32MP153A/D

Symbol

Table 97. I2C FM+ pin characteristics

Parameter Conditions Min Max Unit

F max

(1)

T f

(2)

Maximum frequency

Output high to low level fall time

C = 50 pF

1.71 ≤ V

≤ 3.6 V

MHz ns

1. The maximum frequency is defined with the following conditions:

- (Tr + Tf) ≤ ⅔T

- 45% < duty cycle < 55%.

2. The fall time is defined between 70% and 30% of the output waveform accordingl to I

UM10204 rev- Oct 2012.

C specification NXP

SPI interface characteristics

Unless otherwise specified, the parameters given in

Table 98 for the SPI interface are

derived from tests performed under the ambient temperature, f pclkx

frequency and V

supply voltage conditions summarized in Table 13: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5×V

• I/O compensation cell enabled

• HSLV activated when V

≤ 2.7 V

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

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Symbol Parameter

Table 98. SPI dynamic characteristics (1)

Conditions

Master mode

1.71 V ≤ V

≤ 3.6 V

SPI1

Master mode

2.7 V ≤ V

≤ 3.6 V

SPI1

Master mode

1.71 V ≤ V

≤ 3.6 V

SPI2, SPI3

Master mode

2.7 V ≤ V

≤ 3.6 V

SPI2, SPI3 f

SCK

SPI clock frequency Master mode

1.71 V ≤ V

≤ 3.6 V

SPI4, SPI5, SPI6

Slave receiver mode

1.71 V ≤ V

≤ 3.6 V

SPI1, SPI2, SPI3

Slave receiver mode

1.71 V ≤ V

≤ 3.6 V

SPI4, SPI5, SPI6

Slave mode transmitter/full duplex

2.7 V ≤ V

≤ 3.6 V

Slave mode transmitter/full duplex

1.71 V ≤ V

≤ 3.6 V t su(NSS)

NSS setup time

NSS hold time

Slave mode t h(NSS) t w(SCKH)

, t w(SCKL)

SCK high and low time Master mode

Min

T pclk

- 1

Electrical characteristics

Typ

Max

100

Unit

MHz

T pclk

(2)

T pclk

+ 1 ns

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Electrical characteristics

First bit OUT t h(SI)

Next bits OUT

STM32MP153A/D

Symbol

Table 98. SPI dynamic characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit t su(MI) t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO)

Data input setup time

Data input hold time

Master mode

Slave mode

Master mode

Slave mode

Data output access time Slave mode

Data output disable time Slave mode

7.5

t v(SO)

Data output valid time

Slave mode

2.7 V ≤ V

≤ 3.6 V

Slave mode

1.71 V ≤ V

≤ 3.6 V

Master mode

14 ns t v(MO)

1.5

2.5

t h(SO)

Data output hold time

Slave mode

1.71 V ≤ V

≤ 3.6 V

Master mode

8 t h(MO)

1 -

1. Guaranteed by characterization results.

2. Maximum frequency in slave transmitter mode is determined by the sum of t having t su(MI)

= 0 while Duty(SCK) = 50%.

v(SO)

and t su(MI)

which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

Figure 46. SPI timing diagram - slave mode and CPHA = 0

NSS input t su(NSS) t w(SCKH) t c(SCK) t r(SCK) t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO) t w(SCKL) t v(SO) t h(SO) t f(SCK) t dis(SO)

MISO output Last bit OUT t su(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

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Figure 47. SPI timing diagram - slave mode and CPHA = 1 (1)

NSS input t su(NSS) t w(SCKH) t c(SCK) t f(SCK) t h(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO output

MOSI input t a(SO) t w(SCKL) t v(SO) t su(SI)

First bit OUT t h(SI)

First bit IN t h(SO)

Next bits OUT

Next bits IN t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

1. Measurement points are done at 0.5×V

and with external C

= 30 pF.

Figure 48. SPI timing diagram - master mode (1)

High

NSS input tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN BIT6 IN tr(SCK) tf(SCK)

LSB IN th(MI)

MOSI

OUTPUT

MSB OUT tv(MO)

B I T1 OUT th(MO)

LSB OUT ai14136c

1. Measurement points are done at 0.5×V

and with external C

= 30 pF.

I2S interface characteristics

Unless otherwise specified, the parameters given in

Table 99 for the I2S interface are

derived from tests performed under the ambient temperature, f pclkx

frequency and V

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Electrical characteristics STM32MP153A/D

supply voltage conditions summarized in Table 13: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5×V

• I/O compensation cell enabled

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics (CK, SD, WS).

Symbol f

MCK f

Parameter

I2S main clock output

I2S clock frequency

Table 99. I2S dynamic characteristics (1) t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

1. Guaranteed by characterization results.

Conditions Min

Master data

Slave data

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1.5

0.5

256×8K

0.5

8.5

Unit

MHz

MHz ns

Max

256×Fs

64×Fs

6.5

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STM32MP153A/D Electrical characteristics

Figure 49. I2S slave timing diagram (Philips protocol)

(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 50. I2S master timing diagram (Philips protocol)

(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

SAI characteristics

Unless otherwise specified, the parameters given in Table 100

for SAI are derived from tests performed under the ambient temperature, F pclk2

frequency and V

supply voltage

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Electrical characteristics STM32MP153A/D

conditions summarized in Table 13: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are performed at CMOS levels: 0.5×V

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics (SCK,SD,WS).

Symbol f

MCK

CK t v(FS) t su(FS) t h(FS) t su(SD_A_MR) t su(SD_B_SR) t h(SD_A_MR) t h(SD_B_SR)

Parameter

SAI Main clock output

Table 100. SAI characteristics

(1)

Conditions

SAI bit clock frequency (2)

FS valid time

FS setup time

FS hold time

Data input setup time

Data input hold time

Master transmitter

2.7 V ≤ V

≤ 3.6 V

Master transmitter

1.71 V ≤ V

≤ 3.6 V

Master receiver

1.71 V ≤ V

≤ 3.6 V

Slave transmitter

2.7 V ≤ V

≤ 3.6 V

Slave transmitter

1.71 V ≤ V

≤ 3.6 V

Slave receiver

1.71 ≤ V

≤ 3.6 V

Master mode

2.7 V ≤ V

≤ 3.6 V

Master mode

1.71 V ≤ V

≤ 3.6 V

Slave mode

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Min

2.5

1.5

0.5

Max

Unit

MHz

MHz ns

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Symbol

Table 100. SAI characteristics (1) (continued)

Parameter Conditions t v(SD_B_ST)

Slave transmitter (after enable edge)

2.7 V ≤ V

≤ 3.6 V

Data output valid time

Slave transmitter (after enable edge)

1.71 V ≤ V

≤ 3.6 V

Data output hold time Slave transmitter (after enable edge) t h(SD_B_ST) t v(SD_A_MT)

Master transmitter (after enable edge)

2.7 V ≤ V

≤ 3.6 V

Data output valid time

Master transmitter (after enable edge)

1.71 V ≤ V

≤ 3.6 V

Data output hold time Master transmitter (after enable edge) t h(SD_A_MT)

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

Min

8.5

Max

Unit ns

Figure 51. SAI master timing waveforms

1/fSCK

SAI_SCK_X th(FS)

SAI_FS_X

(output)

SAI_SD_X

(transmit) tv(FS)

SAI_SD_X

(receive) tsu(SD_MR) tv(SD_MT)

Slot n th(SD_MR)

Slot n+2

Slot n th(SD_MT)

MS32771V1

Figure 52. SAI slave timing waveforms

SAI_SCK_X tw(CKH_X)

SAI_FS_X

(input)

SAI_SD_X

(transmit) tsu(FS)

SAI_SD_X

(receive) tw(CKL_X) th(FS) tsu(SD_SR) tv(SD_ST)

Slot n th(SD_SR)

Slot n+2

Slot n th(SD_ST)

MS32772V1

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Electrical characteristics STM32MP153A/D

MDIOS characteristics

Symbol

MDC t d(MDIOS) t su(MDIOS) t h(MDIOS)

Table 101. MDIOS timing parameters

Parameter Min

Management data clock

Management data input/output output valid time

Management data input/output setup time

Management data input/output hold time

6.5

0.5

Typ

Max Unit

MHz ns

The MDIOS controller is mapped on APB1 domain. The frequency of the APB bus should at least 1.5 times the MDC frequency: F pclk1

≥ 1.5 * F

MDC

Figure 53. MDIOS timing diagram

MDC

MDIOS_MDC t d(MDIOS)

MDIOS_MDIO(O) t su(MDIOS) t h(MDIOS)

MDIOS_MDIO(I)

MSv50900V1

SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in

Table 102 for the SDIO/MMC interface

are derived from tests performed under the ambient temperature, F hclk6

frequency and V

supply voltage conditions summarized in Table 13: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5×V

• I/O compensation cell enabled

• HSLV activated when V

≤ 2.7 V

• Delay block disabled

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output

characteristics.

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Table 102. Dynamic characteristics: SD / MMC / e •MMC characteristics,

= 2.7 V to 3.6 V (1)(2)

Parameter Conditions Min Typ Max Symbol f

Clock frequency in data transfer mode 0

SDIO_CK/f pclk2

frequency ratio t

W(CKL)

Clock low time 8.5

= 52 MHz t

W(CKH)

Clock high time 8.5

CMD, D inputs (referenced to CK) in MMC and SD HS/SDR

(3)

/DDR

Refer to Section 6.3.17: I/O port characteristics

mode

ISU

Input setup time HS 1.5

IH t

IDW

(4)

Input hold time HS

Input valid window (variable window)

1.5

2.5

CMD, D outputs (referenced to CK) in MMC and SD HS/SDR

OV t

Output valid time HS

Output hold time HS

CMD, D inputs (referenced to CK) in SD default mode

2.5

9.5

5 t

ISUD t

IHD

Input setup time SD

Input hold time SD

CMD, D outputs (referenced to CK) in SD default mode

1.5

OVD t

OHD

Output valid default time SD

Output hold default time SD

0.5

1. Guaranteed by characterization results.

2. Above 100 MHz, C

= 20 pF.

3. For SD 1.8 V support, an external voltage converter is required.

4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

6.5

1.5

130

8/3

Table 103. Dynamic characteristics: SD / MMC / e •MMC characteristics

= 1.71 V to 1.9 V

(1)(2)

Parameter Conditions Min Typ Max Symbol f

Clock frequency in data transfer mode

W(CKL)

SDIO_CK/f pclk2

frequency ratio

Clock low time t

W(CKH)

Clock high time

CMD, D inputs (referenced to CK) in e •MMC mode

= 52 MHz t

ISU t

IH t

IDW

(3)

Input setup time HS

Input hold time HS

Input valid window (variable window)

CMD, D outputs (referenced to CK) in e •MMC mode

8.5

1.5

2.5

9.5

105

8/3

Unit

MHz

ns ns ns ns ns

Unit

MHz

ns ns

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Electrical characteristics STM32MP153A/D

Table 103. Dynamic characteristics: SD / MMC / e •MMC characteristics

= 1.71 V to 1.9 V (1)(2) (continued)

Parameter Conditions Min Typ Max Symbol t

OV t

Output valid time HS

Output hold time HS

1. Guaranteed by characterization results.

2. C

= 20 pF.

3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Figure 54. SDIO high-speed mode

Unit ns

224/256

CK

D, CMD

(output)

Figure 55. SD default mode

tOVD tOHD

ai14

DS12502 Rev 6

STM32MP153A/D Electrical characteristics

Figure 56. DDR mode t

(CK) t w(CKH) t w(CKL) t f(CK) t r(CK)

Clock t vf(OUT) t hr(OUT) t vr(OUT) t hf(OUT)

Data output D0 D1 t sf(IN) t hf(IN)

D2 D3 D4 t sr(IN) t hr(IN)

Data input D0 D1 D2 D3 D4 D5

MSv63044V1

FDCAN (controller area network) interface

for more details on the input/output alternate function characteristics (FDCANx_TX and FDCANx_RX).

USB OTG_FS characteristics

The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation).

Symbol

Table 104. USB OTG_FS electrical characteristics

Parameter Condition Min Typ Max Unit

DD33USB

PUI

USB transceiver operating voltage

Embedded USB_DP pull-up value during idle

3.0

(1)

900

1250

3.6

1600

PUR

Embedded USB_DP pull-up value during reception

Output driver impedance

(2)

1400 2300 3200

Ω

DRV

Driver high and low 28 36 44

1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7 to 3.0 V voltage range.

2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver.

Note: When VBUS sensing feature is enabled, a typical 200 μ A input current (required to determine the different sessions validity according to USB standard) can be observed.

Ethernet (ETH) characteristics

Unless otherwise specified, the parameters given in

Table 105 , Table 106

Table 107

Table 108

and

Table 109 for MDIO/SMA, RMII, GMII, RGMII and MII are derived from tests

performed under the ambient temperature, F axiss_ck

frequency summarized in

Table 13:

General operating conditions , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 20 pF

• Measurement points are done at CMOS levels: 0.5×V

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Electrical characteristics STM32MP153A/D

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output

characteristics.

Table 105

gives the list of Ethernet MAC timings for the MDIO/SMA and

Figure 57

shows the corresponding timing diagram.

Table 105. Dynamics characteristics: Ethernet MAC timings for MDIO/SMA (1)

Symbol Parameter Min Typ Max Unit t

MDC

T d(MDIO) t su(MDIO) t h(MDIO)

MDC cycle time(2.5 MHz)

Write data valid time

Read data setup time

Read data hold time

1. Guaranteed by characterization results.

399

0.5

13.5

400

401

Figure 57. Ethernet MDIO/SMA timing diagram tMDC

ETH_MDC td(MDIO)

ETH_MDIO(O) tsu(MDIO) th(MDIO)

ETH_MDIO(I)

MS31384V1

Table 106

gives the list of Ethernet MAC timings for the RMII and Figure 58 shows the

corresponding timing diagram.

Table 106. Dynamics characteristics: Ethernet MAC timings for RMII (1)

Symbol Parameter Min Typ Max t su(RXD) t ih(RXD) t su(CRS) t ih(CRS) t d(TXEN) t d(TXD)

Receive data setup time

Receive data hold time

Carrier sense setup time

Carrier sense hold time

Transmit enable valid delay time

Transmit data valid delay time

1. Guaranteed by characterization results.

1.5

5.5

6.5

9.5

Unit ns

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Figure 58. Ethernet RMII timing diagram

RMII_REF_CLK td(TXEN) td(TXD)

RMII_TX_EN

RMII_TXD[1:0] tsu(RXD) tsu(CRS)

RMII_RXD[1:0]

RMII_CRS_DV tih(RXD) tih(CRS) ai15667b

Table 107

gives the list of Ethernet MAC timings for MII and

Figure 59 shows the

corresponding timing diagram.

Symbol

Table 107. Dynamics characteristics: Ethernet MAC timings for MII (1)

Parameter Min Typ Max t su(RXD) t ih(RXD) t su(DV) t ih(DV) t su(ER) t ih(ER) t d(TXEN) t d(TXD)

Receive data setup time

Receive data hold time

Data valid setup time

Data valid hold time

Error setup time

Error hold time

Transmit enable valid delay time

Transmit data valid delay time

1. Guaranteed by characterization results.

0.5

7.5

10.5

Unit ns

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Electrical characteristics

MII_RX_CLK

MII_RXD[3:0]

MII_RX_DV

MII_RX_ER tsu(RXD) tsu(ER) tsu(DV)

Figure 59. Ethernet MII timing diagram tih(RXD) tih(ER) tih(DV)

STM32MP153A/D

MII_TX_CLK td(TXEN) td(TXD)

MII_TX_EN

MII_TXD[3:0] ai15668b

Table 108. Dynamics characteristics: Ethernet MAC signals for GMII (1)

Symbol Parameter Min Typ Max t su(RXD) t ih(RXD) t su(DV) t ih(DV) t su(ER) t ih(ER) t d(TXEN) t d(TXD)

Receive data setup time

Receive data hold time

Data valid setup time

Data valid hold time

Error setup time

Error hold time

Transmit enable valid delay time

Transmit data valid delay time

1. Guaranteed by characterization results.

0.5

1.5

Unit ns

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Figure 60. Ethernet GMII timing diagram

GMII_RX_CLK

GMII_RXD[7:0]

GMII_RX_DV

GMII_RX_ER t su(RXD) t su(ER) t su(DV) t ih(RXD) t ih(ER) t ih(DV)

GTX_CLK t d(TXEN) t d(TXD)

GMII_TX_EN

GMII_TXD[7:0]

MSv50970V1

Table 109. Dynamics characteristics: Ethernet MAC signals for RGMII (1)

Symbol Rating t su(RXD) t ih(RXD) t su(RX_CTL) t ih(RX_CTL)

T skewT(TX_CTL)

T skewT(TXD)

Receive data setup time

Receive data hold time

Receive control valid setup time

Receive control valid hold time

Transmit control valid delay time

Transmit data valid delay time

1. Guaranteed by characterization results.

2. Guaranteed by design.

Min

1.12

(2)

-0.25

Typ

0.25

Max

0.5

Unit ns

Figure 61. Ethernet RGMII timing diagram t skewT

RGMII_GTX_CLK

RGMII_TXD[3:0]

RGMII_TX_CTL

RGMII_RX_CLK

RGMII_RXD[3:0]

RGMII_RX_CTL t su t ih

MSv50971V2

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Electrical characteristics STM32MP153A/D

6.3.37 USART interface characteristics

Unless otherwise specified, the parameters given in

Table 110 for USART are derived from

tests performed under the ambient temperature, f

HCLK

frequency and V

supply voltage

conditions summarized in Table 110

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5×V

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART).

Symbol Parameter

Table 110. USART characteristics (1)

Conditions Min f

CK t su(NSS) t h(NSS) t w(CKH), t w(CKL)

USART clock frequency

NSS setup time

NSS hold time

CK high and low time

Master mode

USART2,3,6

Master mode

USART1

Slave mode

Master mode t

1/f

ker

(2)

/2 - 1 t t t t su(RX) h(RX) v(TX) h(TX)

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master mode

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Master mode

1. Guaranteed by characterization results.

2. T ker

is the usart_ker_ck_pres clock period defined in the product reference manual.

t ker

Unless otherwise specified, the parameters given in Table 112 and Table 113 for JTAG/SWD

Typ

1/f

0.5

Max

12.5

16.5

1/f

/2 + 1

Unit

MHz ns ns ns ns ns ns ns

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CPHA=0

CPOL=0

CPHA=0

CPOL=1

Figure 62. USART timing diagram in master mode

1/f

CPHA=1

CPOL=0

CPHA=1

CPOL=1

INPUT

OUTPUT t su(RX) t w(CKH) t w(CKL)

MSB IN t h(RX)

MSB OUT t v(TX)

BIT6 IN LSB IN

BIT1 OUT t h(TX)

LSB OUT

MSv65386V4

Figure 63. USART timing diagram in slave mode

NSS input t su(NSS) t w(CKH)

1/f

CK t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

TX output t w(CKL)

First bit OUT t h(RX) t v(TX) t h(TX)

Next bits OUT Last bit OUT t su(RX)

RX input First bit IN Next bits IN Last bit IN

MSv65387V4

6.3.38 USB High-Speed PHY characteristics

REF

Symbol

DDA1V1_REG(PHY)

Table 111. USB High-Speed PHY characteristics (1)

Parameter Conditions

Reference resistor on USB_RREF pin

High-Speed TX

(2)

One USB port

Two USB ports

High-Speed RX

(3)

/ Idle

One USB port

Two USB ports

Ful-Speed and Low-Speed mode (Suspend, TX or RX)

Min Typ Max Unit

2.97 3.00 3.03

kΩ

1.4

2.4

mA 5.4

10.4

0 -

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Electrical characteristics STM32MP153A/D

Symbol

Table 111. USB High-Speed PHY characteristics (1) (continued)

Parameter Conditions

DDA1V8_REG(PHY)

DDA3V3_USBHS(PHY)

High-Speed TX

High-Speed RX

(2)

(3)

/ Idle

One USB port

Two USB ports

One USB port

Two USB ports

Ful-Speed and Low-Speed mode (Suspend, TX or RX)

One USB port

High-Speed TX

(2)

Two USB ports

One USB port

High-Speed RX

(3)

/ Idle

Two USB ports

One USB port

Full-Speed Suspend (host mode)

Two USB ports

One USB port

Full-Speed Suspend (peripheral mode)

Two USB ports

One USB port

Full-Speed TX

(2)

Two USB ports

Full-Speed RX

(3)

One USB port

Two USB ports

One USB port

Low-Speed TX

(2)

Low-Speed RX

(3)

Two USB ports

One USB port

Two USB ports

1. Guaranteed by design unless otherwise specified.

2. USB link 100% of the time in transmission

3. USB link 100% of the time in reception

Min Typ Max Unit mA mA

0.2

0.4

6.5

10.5

6.5

11.5

25.5

50.5

2.5

5.5

11.5

4.3

6.1

6.3.39 JTAG/SWD interface characteristics

are derived from tests performed under the ambient temperature, f rcc_c_ck

DD following configuration:

frequency and

supply voltage summarized in Table 13: General operating conditions , with the

• Output speed is set to OSPEEDRy[1:0] = 0x10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5×V

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output

characteristics.

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Symbol

F pp

1/t c(TCK) ti su(TMS) ti h(TMS) ti su(TDI) ti h(TDI) t ov (TDO) t oh(TDO)

Table 112. Dynamics characteristics: JTAG characteristics

Parameter Conditions Min Typ Max

clock frequency

2.7 V < V

< 3.6 V

1.71 V < V

< 3.6 V -

TMS input setup time

TMS input hold time

TDI input setup time

TDI input hold time

2.5

1 -

TDO output valid time

2.7 V < V

< 3.6 V

1.71 V < V

< 3.6 V -

TDO output hold time

7 -

Symbol

F pp

1/t c(SWCLK) ti su(SWDIO) ti h(SWDIO) t ov (SWDIO) t oh(SWDIO)

Table 113. Dynamics characteristics: SWD characteristics

Parameter Conditions Min Typ Max

SWCLK clock frequency

SWDIO input setup time

SWDIO input hold time

2.7 V < V

< 3.6 V

1.71 V < V

< 3.6 V

2.7 V < V

< 3.6 V SWDIO output valid time

SWDIO output hold time

1.71 V < V

< 3.6 V

2.5

8.5

Unit

MHz ns

Unit

MHz ns

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Electrical characteristics

TCK

TDI/TMS

Figure 64. JTAG timing diagram t c(TCK) t su(TMS/TDI) t h(TMS/TDI) t w(TCKL) t w(TCKH) t ov(TDO)

TDO

Figure 65. SWD timing t c(SWCLK)

SWCLK

SWDIO

(receive)

SWDIO

(transmit) t su(SWDIO) t h(SWDIO) t ov(SWDIO) t wSWCLKL) t w(SWCLKH) t oh(SWDIO)

STM32MP153A/D t oh(TDO)

MSv40458V1

MSv40459V1

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7 Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

ECOPACK is an ST trademark.

7.1 TFBGA257 package information

This TFBGA is a 257 balls, 10x10 mm, 0.5/0.65 mm pitch, low profile fine pitch ball grid array package

Figure 66. TFBGA257 - Outline

E1 E2 b (257 balls) eee M C A B fff M C

F2 e1 e2

A1 ball pad corner

Peripheral ball matrix pitch 0.5 mm

16 14

15 13

W e1

Central ball matrix pitch 0.65 mm

F2 e2

SEATING

PLANE

BOTTOM VIEW TOP VIEW

D ddd C

A1 A

SIDE VIEW

B02Y_ME_V1

1. Drawing is not to scale.

2. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.

For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone

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Package information STM32MP153A/D

Table 114. TFBGA257 - Mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

E2 e1 e2

F2 ddd eee

(4) fff

(5)

(2)

A2 b

(3)

0.170

0.250

9.850

0.810

0.300

10.000

9.000

10.000

9.000

5.200

0.500

0.650

0.500

2.400

1.200

0.350

10.150

0.100

0.150

0.050

0.007

0.010

0.3878

0.0319

0.012

0.3937

0.3543

0.3937

0.3543

0.2047

0.0197

0.0256

0.0197

0.0945

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. - The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug.

- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

3. Initial ball equal 0.300 mm.

4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.

5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.

For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones.

0.0039

0.0059

0.0020

0.0472

0.0157

0.3996

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Figure 67. TFBGA257 - Recommended footprint

Dpad

Dsm

B02Y_FP_V1

1. Dimensions are expressed in millimeters.

Table 115. TFBGA257 - Recommended PCB design rules (0.5/0.65 mm pitch, BGA)

Dimension Recommended values

Pitch

Dpad

Dsm

Stencil opening

Stencil thickness

0.5/0.65 mm

0.230 mm

0.390 mm typ.

0.230 mm

0.125 mm to 0.100 mm

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Package information STM32MP153A/D

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 68. TFBGA257 marking (package top view)

Product

identification

STM32MP15x xADxx

Revision

MSv60330V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

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7.2 LFBGA354 package information

Package information

This LFBGA is a 354 balls, 16x16 mm, 0.8 mm pitch, low profile fine pitch ball grid array package

Figure 69. LFBGA354 - Outline b (354 balls) eee M C A B fff M C e

16 14

15 13

A1 ball pad corner

F e

SEATING

PLANE

BOTTOM VIEW ddd C

TOP VIEW

A2 A1 A

SIDE VIEW

B02Z_ME_V1

1. Drawing is not to scale.

2. The tolerance of position that controls the location of the balls within the matrix with respect to each other.

Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones.

Table 116. LFBGA354 - Mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

(2)

(3)

A2 b

(4)

0.250

0.350

15.850

0.900

0.400

16.000

1.290

0.450

16.150

0.0098

0.0138

0.6240

0.0354

0.0157

0.6299

0.0508

0.0177

0.6358

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Table 116. LFBGA354 - Mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max

E1 e

F ddd eee

(5) fff

(6)

15.850

14.400

16.000

14.400

0.800

16.150

0.120

0.150

0.080

0.6240

0.5669

0.6299

0.5669

0.0315

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. LFBGA stands for Low profile Fine pitch Ball Grid Array package.

Low profile: 1.20mm < A ≤ 1.70mm / Fine pitch: e < 1.00mm pitch. The total profile height (Dim A) is measured from the seating plane to the top of the component The maximum total package height is calculated by the RSS method (Root Sum Square).

A Max = A1 Typ + A2 Typ + A4 Typ + √(A1² + A2² + A4² tolerance values).

3. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug.

A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

4. Initial ball equal 0.400 mm.

5. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.

6. The tolerance of position that controls the location of the balls within the matrix with respect to each other.

Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones.

0.6358

0.0050

0.0059

0.0031

Figure 70. LFBGA354 - Recommended footprint

240/256

1. Dimensions are expressed in millimeters.

Dpad

Dsm

DS12502 Rev 6

B02Z_FP_V1

STM32MP153A/D Package information

Table 117. LFBGA354 - Recommended PCB design rules (0.8 mm pitch, BGA)

Dimension Recommended values

Pitch

Dpad

Dsm

Stencil opening

Stencil thickness

0.8 mm

0.320 mm

0.520 mm typ.

0.320 mm

0.125 mm to 0.100 mm

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 71. LFBGA354 marking (package top view)

Product

identification

STM32MP15xxABx

Y WW

Revision

MSv60332V1

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Package information

7.3 TFBA361 package information

STM32MP153A/D

This TFBGA is a 361 ball, 12x12 mm, 0.5/0.65 mm pitch, thin profile fine pitch ball grid array package.

Figure 72. TFBGA361 - Outline eee M fff M

C A B

C b (361 balls)

E1 E2 e2

F1 e1

Peripheral ball matrix pitch 0.5 mm

A1 ball pad corner

8 6 4 2

9 7 5 3 1

Central ball matrix pitch 0.65 mm e1 e2

BOTTOM VIEW

TOP VIEW

SEATING

PLANE

C ddd C

A2 A1 A

SIDE VIEW

B031_ME_V1

1. Drawing is not to scale.

2. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug.

A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

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Table 118. TFBGA361 - Mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

E2 e1 e2

F2 ddd eee

(4) fff

(5)

A (2)

A2 b

(3)

0.150

0.250

11.850

0.810

0.300

12.000

11.000

12.000

11.000

5.200

0.500

0.650

0.500

3.400

1.200

0.350

12.150

0.080

0.150

0.080

0.0059

0.010

0.4665

0.0319

0.012

0.4724

0.4331

0.4724

0.4331

0.2047

0.0197

0.0256

0.0197

0.1339

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. TFBGA stands for Thin Profile Fine Pitch Ball Grid Array. The total profile height (dim A) is measured from the seating plane to the top of the component.

3. Initial ball equal to 0.300 mm.

4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.

5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.

0.0031

0.0059

0.0031

0.0472

0.0157

0.4783

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Package information

Figure 73. TFBGA361 - Recommended footprint

STM32MP153A/D

Dpad

Dsm

B031_FP_V2

Table 119. TFBGA361 - Recommended PCB design rules (0.5/0.65 mm pitch BGA)

Dimension Recommended values

Pitch

Dpad

Dsm

Stencil opening

Stencil thickness

0.5/0.65 mm

0.230 mm

0.390 mm typ.

0.230 mm

0.125 mm to 0.100 mm

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Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 74. TFBGA361 marking (package top view)

Product

identification

STM32MP15x xACxx

Revision

MSv60331V1

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Package information

7.4 LFBGA448 package information

STM32MP153A/D

This LFBGA is a 448 balls, 18x18 mm, 0.8 mm pitch, low profile fine pitch ball grid array package.

Figure 75. LFBGA448 - Outline

246/256

F e eee fff

C A B

C b (448 Balls)

A1 corner index area

16 14

15 13

E1 e

BOTTOM VIEW

SEATING

PLANE

TOP VIEW

A4 A3

SIDE VIEW

B032_LFBGA448_ME_V1

1. Drawing is not to scale.

2. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug.

A distinguishing feature is allowed on the surface of the package to identify the terminal A1 corner.The exact shape and size of this feature are optional.

Table 120. LFBGA448 - Mechanical data millimeters inches

(1)

Symbol

(2)

A4 b

(3)

Min

0.210

0.350

17.850

Typ

0.290

0.400

18.000

Max

1.320

0.650

0.450

18.150

Min

0.0083

0.0138

0.7028

Typ

0.0114

0.0157

0.7087

Max

0.0520

0.0256

0.0177

0.7146

DS12502 Rev 6

STM32MP153A/D Package information

Table 120. LFBGA448 - Mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max

E1 e

F ddd eee

(4) fff

(5)

17.850

16.800

18.000

16.800

0.800

0.600

0.120

0.150

0.080

18.150

0.7028

0.6614

0.7087

0.6614

0.0315

0.0236

0.0047

0.0059

0.0031

0.7146

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Low profile: 1.20 mm < A ≤ 1.70 mm / Fine pitch: e < 1.00 mm pitch.

The total profile height (Dim.A) is measured from the seating plane “C” to the top of the component. The maximum total package height is calculated by the RSS method (Root Sum Square).

A Max = A1 Typ + A3 Typ + A4 Typ + √(A1² + A3² + A4² tolerance values).

3. The typical ball diameter before mounting is 0.40 mm

4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.

5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.

The axis of each ball must lie simultaneously in both tolerance zones.

Figure 76. LFBGA448 - Recommended footprint

Dpad

Pitch

Dpad

Dsm

BGA_WLCSP_FT_V1

Table 121. LFBGA448 - Recommended PCB design rules (0.8 mm pitch, BGA)

Dimension Recommended values

0.8 mm

0.320 mm

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Package information STM32MP153A/D

Table 121. LFBGA448 - Recommended PCB design rules (0.8 mm pitch, BGA)

Dimension Recommended values

Dsm

Stencil opening

Stencil thickness

0.520 mm typ.

0.320 mm

0.125 mm to 0.100 mm

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 77. LFBGA448 marking (package top view)

Product

identification

STM32MP15xxAAx

Y WW

Revision

MSv60333V1

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7.5 Thermal characteristics

Package thermal characteristics in Table 122 are specified with conditions as per JEDEC

JESD51-6, JESD51-8, JESD51-9, and JESD51-12. These typical values will vary in function of board thermal characteristics and other components on the board.

Θjb:

Thermal resistance junction-ambient.

Thermal resistance junction-board.

Thermal resistance junction-top-case.

Thermal parameter junction-board.

Ψjt: Thermal parameter junction-top-case.

Motherboard type: four layers, JEDEC 2S2P

Table 122. Thermal characteristics

Value

Symbol Parameter

(1)

(2)

(3) jb jt

(4)

(5)

TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch

TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch

LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch

LFBGA448 - 448-ball 18x18 mm 0.80 mm pitch

TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch

TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch

LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch

LFBGA448 - 448-ball 18x18 mm 0.80 mm pitch

TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch

TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch

LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch

TLFBGA448 - 448-ball 18x18 mm 0.80 mm pitch

TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch

TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch

LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch

LFBGA448 - 448-ball 18x18 mm 0.80 mm pitch

TFBGA257 - 257-ball 10x10 mm 0.50/0.65 mm pitch

TFBGA361 - 361-ball 12x12 mm 0.50/0.65 mm pitch

LFBGA354 - 354-ball 16x16 mm 0.80 mm pitch

LFBGA448 - 448-ball 18x18 mm 0.80 mm pitch

1. Per JEDEC JESD51-9

2. Per JEDEC JESD51-8

3. Per JEDEC JESD51-12 best practice guidelines

4. Per JEDEC JESD51-12.

5. Per JEDEC JESD51-12.

Natural convection 1m/s (200 ft/mn)

36.079

35.151

34.145

28.545

31.79

30.953

30.121

24.797

19.487

20.555

22.038

17.409

10.768

10.049

9.675

8.439

18.949

20.002

21.456

16.946

0.383

0.354

0.339

0.297

18.332

19.398

20.894

16.574

0.812

0.735

0.658

0.542

Unit

°C/W

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Package information

7.5.1 Reference documents

STM32MP153A/D

JESD51-6 Integrated Circuit Thermal Test Method Environmental Conditions - Forced

Convection (Moving Air). Available from www.jedec.org.

JESD51-8 Integrated Circuit Thermal Test Method Environmental Conditions —Junction-to-

Board. Available from www.jedec.org.

JESD51-9 Test Boards for Area Array Surface. Mount Package Thermal. Measurements.

Available from www.jedec.org.

JESD51-12 Guidelines for Reporting and Using Electronic Package Thermal Information.

Available from www.jedec.org.

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8 Ordering information

Ordering information

Table 123. STM32MP153A/D ordering information scheme

Example:

Device family

STM32 = Arm-based 32-bit processor

STM32 MP 153 D AA 1

Product type

MP = MPU product

Device subfamily

153 = STM32MP153 Line

Security option

A = Basic security, 650 MHz

D = Basic security, 800 MHz

Package and pin count

AD = TFBGA257 10x10, 257 balls pitch 0.5 mm

AB = LFBGA354 16x16, 354 balls pitch 0.8 mm

AC = TFBGA361 12x12, 361 balls pitch 0.5 mm

AA = LFBGA448 18x18, 448 balls pitch 0.8 mm

Junction temperature range

1 = -20 °C < T

< +105 °C, up to 800 MHz Cortex ® -A7 (1)

3 = -40 °C < T

< +125 °C, up to 650 MHz Cortex

-A7