STMicroelectronics STM32F413RH Reference Manual

Below you will find brief information for STM32F413 Microcontroller, STM32F423 Microcontroller. These advanced Arm-based 32-bit microcontrollers feature embedded Flash, various peripherals (ADC, DAC, DMA), and low-power modes, suitable for diverse embedded applications.
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RM0430
Reference manual
STM32F413/423 advanced Arm&reg;-based 32-bit MCUs
Introduction
This reference manual targets application developers. It provides complete information on
how to use the memory and the peripherals of the STM32F413/423 microcontrollers.
The STM32F413/423 is a line of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics refer to the
datasheet.
For information on the Arm&reg; Cortex&reg;-M4 with FPU core, refer to the Cortex&reg;-M4 Technical
Reference Manual.
The STM32F413/423 microcontrollers include ST state-of-the-art patented technology.
Related documents
Available from STMicroelectronics web site www.st.com:
• STM32F413xG STM32F413xH datasheet (DS11581)
• STM32F423xH datasheet (DS11580)
• STM32 Cortex&reg;-M4 MCUs and MPUs programming manual (PM0214)
• STM32F413xG/xH and STM32F423xH device errata (ES0372)
October 2024
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Contents
RM0430
Contents
1
2
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.1
General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.2
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.3
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.4
Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.1
2.2
3
2.1.1
I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.1.2
D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.1.3
S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.1.4
DMA memory bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.1.5
DMA peripheral bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.1.6
BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.1.7
AHB/APB bridges (APB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2.2
Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 58
2.3
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.4
Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.5
Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.6
Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Embedded Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.4
Read interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.5
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System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4.1
Relation between CPU clock frequency and Flash memory read time . 68
3.4.2
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 69
Erase and program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.5.1
Unlocking the Flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.5.2
Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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3.6
4
5
3.5.3
Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.5.4
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.5.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.6.1
Description of user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.6.2
Programming user option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.6.3
Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.6.4
Write protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.6.5
Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . . 79
3.7
One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.8
Flash interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.8.1
Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . 82
3.8.2
Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.8.3
Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 83
3.8.4
Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.8.5
Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.8.6
Flash option control register (FLASH_OPTCR) . . . . . . . . . . . . . . . . . . . 86
3.8.7
Flash interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.1
CRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2
CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.3
CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4
CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.4.1
Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.4.2
Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.4.3
Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.4.4
CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Power controller (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.1
5.2
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.1.1
Independent A/D converter supply and reference voltage . . . . . . . . . . . 95
5.1.2
Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.1.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2.1
Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . . 98
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5.3
5.4
5.5
6
Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2.3
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 99
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.3.1
Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.3.2
Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.3.3
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.4
Batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.3.5
Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.6
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.7
Programming the RTC alternate functions to wake up the device from
the Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
5.4.1
PWR power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . 112
5.4.2
PWR power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . 114
PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Reset and clock control (RCC) for STM32F413/423 . . . . . . . . . . . . . . 117
6.1
6.2
6.3
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5.2.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
6.1.1
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.1.2
Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1.3
Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
6.2.1
HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2.2
HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.2.3
PLL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.2.4
LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.2.5
LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.2.6
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.2.7
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.2.8
RTC/AWU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2.9
Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2.10
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.2.11
Internal/external clock measurement using TIM5/TIM11 . . . . . . . . . . . 126
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.1
RCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.2
RCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 131
6.3.3
RCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 133
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6.3.4
RCC clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.5
RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 138
6.3.6
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
for STM32F413xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.7
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
for STM32F423xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.8
RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 142
6.3.9
RCC APB1 peripheral reset register for (RCC_APB1RSTR) . . . . . . . . 142
6.3.10
RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 146
6.3.11
RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 149
6.3.12
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
for STM32F413xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.13
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
for STM32F423xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.14
RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 153
6.3.15
RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . 153
6.3.16
RCC APB2 peripheral clock enable register
(RCC_APB2ENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.17
RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.3.18
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F413xx . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.19
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F423xx . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.20
RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.21
RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.22
RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.23
RCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 171
6.3.24
RCC clock control &amp; status register (RCC_CSR) . . . . . . . . . . . . . . . . 172
6.3.25
RCC spread spectrum clock generation register (RCC_SSCGR) . . . . 175
6.3.26
RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . . . . . . 176
6.3.27
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) . . 178
6.3.28
RCC clocks gated enable register (CKGATENR) . . . . . . . . . . . . . . . . 180
6.3.29
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2) . 181
6.3.30
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
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7.1
GPIO introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.2
GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.3
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.4
8
6/1321
7.3.1
General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.3.2
I/O pin multiplexer and mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.3.3
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.3.4
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.3.5
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.3.6
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.3.7
I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.3.8
External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.3.9
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.3.10
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.3.11
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.3.12
Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.3.13
Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15
port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.3.14
Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . 195
7.3.15
Selection of RTC additional functions . . . . . . . . . . . . . . . . . . . . . . . . . 196
GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.4.1
GPIO port mode register (GPIOx_MODER) (x = A...H) . . . . . . . . . . . . 197
7.4.2
GPIO port output type register (GPIOx_OTYPER)
(x = A...H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.4.3
GPIO port output speed register (GPIOx_OSPEEDR)
(x = A...H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.4.4
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A...H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.4.5
GPIO port input data register (GPIOx_IDR) (x = A...H) . . . . . . . . . . . . 199
7.4.6
GPIO port output data register (GPIOx_ODR) (x = A...H) . . . . . . . . . . 199
7.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A...H) . . . . . . . . . 199
7.4.8
GPIO port configuration lock register (GPIOx_LCKR)
(x = A...H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.4.9
GPIO alternate function low register (GPIOx_AFRL) (x = A...H) . . . . . 201
7.4.10
GPIO alternate function high register (GPIOx_AFRH)
(x = A...H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.4.11
GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 205
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8.1
I/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
8.2
SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
8.2.1
SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 205
8.2.2
SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . 206
8.2.3
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
8.2.4
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
8.2.5
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
8.2.6
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
8.2.7
SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 209
8.2.8
Compensation cell control register (SYSCFG_CMPCR) . . . . . . . . . . . 210
8.2.9
SYSCFG configuration register (SYSCFG_CFGR) . . . . . . . . . . . . . . . 211
8.2.10
DFSDM Multi-channel delay control register (SYSCFG_MCHDLYCR) 211
8.2.11
SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 215
9.1
DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.2
DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.3
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.3.1
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.3.2
DMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.3.3
DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
9.3.4
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
9.3.5
Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
9.3.6
DMA streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
9.3.7
Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 220
9.3.8
Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
9.3.9
Circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.3.10
Double-buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.3.11
Programmable data width, packing/unpacking, endianness . . . . . . . . 226
9.3.12
Single and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
9.3.13
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
9.3.14
DMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
9.3.15
DMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
9.3.16
Flow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
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10
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Summary of the possible DMA configurations . . . . . . . . . . . . . . . . . . . 234
9.3.18
Stream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
9.3.19
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
9.4
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
9.5
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
9.5.1
DMA low interrupt status register (DMA_LISR) . . . . . . . . . . . . . . . . . . 237
9.5.2
DMA high interrupt status register (DMA_HISR) . . . . . . . . . . . . . . . . . 238
9.5.3
DMA low interrupt flag clear register (DMA_LIFCR) . . . . . . . . . . . . . . 239
9.5.4
DMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . . 239
9.5.5
DMA stream x configuration register (DMA_SxCR) . . . . . . . . . . . . . . . 240
9.5.6
DMA stream x number of data register (DMA_SxNDTR) . . . . . . . . . . 243
9.5.7
DMA stream x peripheral address register (DMA_SxPAR) . . . . . . . . . 244
9.5.8
DMA stream x memory 0 address register
(DMA_SxM0AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
9.5.9
DMA stream x memory 1 address register
(DMA_SxM1AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
9.5.10
DMA stream x FIFO control register (DMA_SxFCR) . . . . . . . . . . . . . . 245
9.5.11
DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
10.1
10.2
10.3
8/1321
9.3.17
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 251
10.1.1
NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
10.1.2
SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
10.1.3
Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 251
10.2.1
EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
10.2.2
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
10.2.3
Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
10.2.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
10.2.5
External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 259
EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
10.3.1
Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
10.3.2
Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
10.3.3
Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 261
10.3.4
Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 262
10.3.5
Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . 263
10.3.6
Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
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10.3.7
11
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
11.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
11.2
FSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
11.3
FMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
11.4
AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
11.4.1
11.5
11.6
Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 268
External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
11.5.1
12
EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
NOR flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
11.6.1
External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
11.6.2
Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 273
11.6.3
General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
11.6.4
NOR flash/PSRAM controller asynchronous transactions . . . . . . . . . . 274
11.6.5
Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
11.6.6
NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
11.6.7
FSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Quad-SPI interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
12.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
12.2
QUADSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
12.3
QUADSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
12.3.1
QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
12.3.2
QUADSPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
12.3.3
QUADSPI command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
12.3.4
QUADSPI signal interface protocol modes . . . . . . . . . . . . . . . . . . . . . 312
12.3.5
QUADSPI indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
12.3.6
QUADSPI automatic status-polling mode . . . . . . . . . . . . . . . . . . . . . . 316
12.3.7
QUADSPI memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
12.3.8
QUADSPI flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . . 317
12.3.9
QUADSPI delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
12.3.10 QUADSPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
12.3.11 QUADSPI use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
12.3.12 Sending the instruction only once . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
12.3.13 QUADSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
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12.3.14 QUADSPI busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . . 320
12.3.15 NCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
12.4
QUADSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
12.5
QUADSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
12.5.1
QUADSPI control register (QUADSPI_CR) . . . . . . . . . . . . . . . . . . . . . 323
12.5.2
QUADSPI device configuration register (QUADSPI_DCR) . . . . . . . . . 326
12.5.3
QUADSPI status register (QUADSPI_SR) . . . . . . . . . . . . . . . . . . . . . 327
12.5.4
QUADSPI flag clear register (QUADSPI_FCR) . . . . . . . . . . . . . . . . . . 328
12.5.5
QUADSPI data length register (QUADSPI_DLR) . . . . . . . . . . . . . . . . 328
12.5.6
QUADSPI communication configuration register (QUADSPI_CCR) . . 329
12.5.7
QUADSPI address register (QUADSPI_AR) . . . . . . . . . . . . . . . . . . . . 331
12.5.8
QUADSPI alternate-byte register (QUADSPI_ABR) . . . . . . . . . . . . . . 331
12.5.9
QUADSPI data register (QUADSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . 332
12.5.10 QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . . . . 332
12.5.11 QUADSPI polling status match register (QUADSPI_PSMAR) . . . . . . 333
12.5.12 QUADSPI polling interval register (QUADSPI_PIR) . . . . . . . . . . . . . . 333
12.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . . . . . . . 334
12.5.14 QUADSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
13
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
13.1
ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
13.2
ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
13.3
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
13.3.1
ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
13.3.2
ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
13.3.3
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
13.3.4
Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
13.3.5
Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
13.3.6
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
13.3.7
Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
13.3.8
Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
13.3.9
Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
13.3.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
10/1321
13.4
Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
13.5
Channel-wise programmable sampling time . . . . . . . . . . . . . . . . . . . . . 344
13.6
Conversion on external trigger and trigger polarity . . . . . . . . . . . . . . . . 345
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Contents
13.7
Fast conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
13.8
Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
13.9
13.8.1
Using the DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
13.8.2
Managing a sequence of conversions without using the DMA . . . . . . 347
13.8.3
Conversions without DMA and without overrun detection . . . . . . . . . . 348
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
13.10 Battery charge monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
13.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
13.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
13.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
13.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
13.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
13.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 356
13.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 357
13.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . 357
13.12.7 ADC watchdog higher threshold register (ADC_HTR) . . . . . . . . . . . . . 357
13.12.8 ADC watchdog lower threshold register (ADC_LTR) . . . . . . . . . . . . . . 358
13.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 358
13.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 359
13.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 360
13.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 361
13.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 361
13.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 362
13.12.15 ADC Common status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . . 362
13.12.16 ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . . 363
13.12.17 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
14
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
14.1
DAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
14.2
DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
14.3
DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
14.3.1
DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
14.3.2
DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
14.3.3
DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
14.3.4
DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
14.3.5
DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
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14.4
14.3.6
DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
14.3.7
DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
14.3.8
Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
14.3.9
Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
14.4.1
Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 374
14.4.2
Independent trigger with single LFSR generation . . . . . . . . . . . . . . . . 374
14.4.3
Independent trigger with different LFSR generation . . . . . . . . . . . . . . 374
14.4.4
Independent trigger with single triangle generation . . . . . . . . . . . . . . . 375
14.4.5
Independent trigger with different triangle generation . . . . . . . . . . . . . 375
14.4.6
Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
14.4.7
Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 376
14.4.8
Simultaneous trigger with single LFSR generation . . . . . . . . . . . . . . . 376
14.4.9
Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 376
14.4.10 Simultaneous trigger with single triangle generation . . . . . . . . . . . . . . 377
14.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 377
14.5
DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
14.5.1
DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
14.5.2
DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . 381
14.5.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
14.5.4
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
14.5.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
14.5.6
DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
14.5.7
DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
14.5.8
DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
14.5.9
Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
14.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
14.5.11 DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
14.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 385
14.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 385
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14.5.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
14.5.15 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
15
Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . . 388
15.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
15.2
DFSDM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
15.3
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
15.4
DFSDM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
15.4.1
DFSDM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
15.4.2
DFSDM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
15.4.3
DFSDM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
15.4.4
Serial channel transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
15.4.5
Configuring the input serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . 407
15.4.6
Parallel data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
15.4.7
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
15.4.8
Digital filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.4.9
Integrator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
15.4.10 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
15.4.11 Short-circuit detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
15.4.12 Extreme detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
15.4.13 Data unit block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
15.4.14 Signed data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
15.4.15 Launching conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
15.4.16 Continuous and fast continuous modes . . . . . . . . . . . . . . . . . . . . . . . . 417
15.4.17 Request precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
15.4.18 Power optimization in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
15.5
DFSDM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
15.6
DFSDM DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
15.7
DFSDM channel y registers (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
15.8
15.7.1
DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . . 420
15.7.2
DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . . 423
15.7.3
DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
15.7.4
DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
15.7.5
DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . . . 425
DFSDM filter x module registers (x=0..3) . . . . . . . . . . . . . . . . . . . . . . . . 426
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15.8.1
DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . . . . . . . . . 426
15.8.2
DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . . . . . . . . . 429
15.8.3
DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . . 430
15.8.4
DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . . 432
15.8.5
DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
15.8.6
DFSDM filter x control register (DFSDM_FLTxFCR) . . . . . . . . . . . . . . 433
15.8.7
DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
15.8.8
DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
15.8.9
DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
15.8.10 DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
15.8.11 DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
15.8.12 DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
15.8.13 DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
15.8.14 DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
15.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . 439
15.8.16 DFSDM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
16
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . 450
16.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
16.2
RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
16.3
RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
16.4
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16.3.1
RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
16.3.2
RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
16.3.3
Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
16.3.4
RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
16.3.5
RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
16.3.6
RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
16.3.7
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
16.3.8
RNG low-power use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
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16.5
RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.6
RNG entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.7
17
16.6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.6.2
Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
16.6.3
Data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
16.7.1
RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
16.7.2
RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
16.7.3
RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
16.7.4
RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Advanced-control timers (TIM1&amp;TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 461
17.1
TIM1&amp;TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
17.2
TIM1&amp;TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
17.3
TIM1&amp;TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
17.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
17.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
17.3.3
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
17.3.4
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
17.3.5
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
17.3.6
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
17.3.7
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
17.3.8
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
17.3.9
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
17.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
17.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 489
17.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 494
17.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
17.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
17.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
17.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
17.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
17.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 502
17.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
17.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
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17.4
TIM1&amp;TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
17.4.1
TIM1&amp;TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 506
17.4.2
TIM1&amp;TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 507
17.4.3
TIM1&amp;TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 509
17.4.4
TIM1&amp;TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . 511
17.4.5
TIM1&amp;TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 513
17.4.6
TIM1&amp;TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 514
17.4.7
TIM1&amp;TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . 515
17.4.8
TIM1&amp;TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . 518
17.4.9
TIM1&amp;TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . 520
17.4.10 TIM1&amp;TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
17.4.11 TIM1&amp;TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
17.4.12 TIM1 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 524
17.4.13 TIM1&amp;TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . 524
17.4.14 TIM1&amp;TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . 525
17.4.15 TIM1 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 525
17.4.16 TIM1&amp;TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . 526
17.4.17 TIM1&amp;TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . 526
17.4.18 TIM1&amp;TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . 526
17.4.19 TIM1&amp;TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . 528
17.4.20 TIM1&amp;TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . 529
17.4.21 TIM1&amp;TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
18
General-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 532
18.1
TIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
18.2
TIM2 to TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
18.3
TIM2 to TIM5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
18.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
18.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
18.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
18.3.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
18.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
18.3.6
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
18.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
18.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
18.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
18.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
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18.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 557
18.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
18.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
18.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 560
18.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
18.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
18.4
TIM2 to TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
18.4.1
TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 570
18.4.2
TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 572
18.4.3
TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 573
18.4.4
TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 575
18.4.5
TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
18.4.6
TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 578
18.4.7
TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 579
18.4.8
TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 582
18.4.9
TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . 583
18.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
18.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
18.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 585
18.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 586
18.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 586
18.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 587
18.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 587
18.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 588
18.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 588
18.4.19 TIM2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
18.4.20 TIM5 option register (TIM5_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
18.4.21 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
19
General-purpose timers (TIM9 to TIM14) . . . . . . . . . . . . . . . . . . . . . . . 593
19.1
TIM9 to TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
19.2
TIM9 to TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
19.3
19.2.1
TIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
19.2.2
TIM10/TIM11 and TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . 594
TIM9 to TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
19.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
19.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
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19.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
19.3.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
19.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
19.3.6
PWM input mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 605
19.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
19.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
19.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
19.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
19.3.11 TIM9/12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 611
19.3.12 Timer synchronization (TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
19.3.13 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
19.4
TIM9 and TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
19.4.1
TIM9/12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 614
19.4.2
TIM9/12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . 616
19.4.3
TIM9/12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . 617
19.4.4
TIM9/12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
19.4.5
TIM9/12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . 620
19.4.6
TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . 620
19.4.7
TIM9/12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . 624
19.4.8
TIM9/12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
19.4.9
TIM9/12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
19.4.10 TIM9/12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 625
19.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 626
19.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 626
19.4.13 TIM9/12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
19.5
18/1321
TIM10/11/13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
19.5.1
TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 629
19.5.2
TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . 630
19.5.3
TIM10/11/13/14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . 630
19.5.4
TIM10/11/13/14 event generation register (TIMx_EGR) . . . . . . . . . . . 631
19.5.5
TIM10/11/13/14 capture/compare mode register 1
(TIMx_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
19.5.6
TIM10/11/13/14 capture/compare enable register
(TIMx_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
19.5.7
TIM10/11/13/14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 636
19.5.8
TIM10/11/13/14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 636
19.5.9
TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 636
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19.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 637
19.5.11 TIM11 option register 1 (TIM11_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . 637
19.5.12 TIM10/11/13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
20
Basic timers (TIM6/7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
20.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
20.2
TIM6/7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
20.3
TIM6/7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
20.4
21
20.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
20.3.2
Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
20.3.3
Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
20.3.4
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
TIM6/7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
20.4.1
TIM6/7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 648
20.4.2
TIM6/7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 649
20.4.3
TIM6/7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . 649
20.4.4
TIM6/7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
20.4.5
TIM6/7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . 650
20.4.6
TIM6/7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
20.4.7
TIM6/7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
20.4.8
TIM6/7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . 651
20.4.9
TIM6/7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
21.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
21.2
LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
21.3
LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
21.4
LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
21.4.1
LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
21.4.2
LPTIM trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
21.4.3
LPTIM input1 multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
21.4.4
LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
21.4.5
Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
21.4.6
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
21.4.7
Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
21.4.8
Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
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21.4.9
Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
21.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
21.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
21.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
21.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
21.4.14 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
21.4.15 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
21.5
LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
21.6
LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
21.7
LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
21.7.1
LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . . 665
21.7.2
LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . . 666
21.7.3
LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . . 667
21.7.4
LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . . 668
21.7.5
LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 670
21.7.6
LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . . 671
21.7.7
LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . . 672
21.7.8
LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 672
21.7.9
LPTIM1 option register (LPTIM1_OPTR) . . . . . . . . . . . . . . . . . . . . . . 673
21.7.10 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
22
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
22.1
IWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
22.2
IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
22.3
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
22.4
23
20/1321
22.3.1
Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
22.3.2
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
22.3.3
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
22.4.1
Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
22.4.2
Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
22.4.3
Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
22.4.4
Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
22.4.5
IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
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Contents
23.1
WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
23.2
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
23.3
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
23.4
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 683
23.5
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
23.6
WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
23.6.1
Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
23.6.2
Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 686
23.6.3
Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
23.6.4
WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
AES hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
24.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
24.2
AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
24.3
AES implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
24.4
AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
24.4.1
AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
24.4.2
AES internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
24.4.3
AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
24.4.4
AES procedure to perform a cipher operation . . . . . . . . . . . . . . . . . . . 695
24.4.5
AES decryption key preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
24.4.6
AES ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . . . . 700
24.4.7
AES task suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
24.4.8
AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . . . 702
24.4.9
AES counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
24.4.10 AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
24.4.11 AES Galois message authentication code (GMAC) . . . . . . . . . . . . . . 714
24.4.12 AES counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . 716
24.4.13 .AES data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . . . 721
24.4.14 AES key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
24.4.15 AES initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
24.4.16 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
24.4.17 AES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
24.5
AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
24.6
AES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
24.7
AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
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24.7.1
AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
24.7.2
AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
24.7.3
AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 732
24.7.4
AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 733
24.7.5
AES key register 0 (AES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
24.7.6
AES key register 1 (AES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
24.7.7
AES key register 2 (AES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
24.7.8
AES key register 3 (AES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
24.7.9
AES initialization vector register 0 (AES_IVR0) . . . . . . . . . . . . . . . . . . 735
24.7.10 AES initialization vector register 1 (AES_IVR1) . . . . . . . . . . . . . . . . . . 735
24.7.11 AES initialization vector register 2 (AES_IVR2) . . . . . . . . . . . . . . . . . . 736
24.7.12 AES initialization vector register 3 (AES_IVR3) . . . . . . . . . . . . . . . . . . 736
24.7.13 AES key register 4 (AES_KEYR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
24.7.14 AES key register 5 (AES_KEYR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
24.7.15 AES key register 6 (AES_KEYR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
24.7.16 AES key register 7 (AES_KEYR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
24.7.17 AES suspend registers (AES_SUSPxR) . . . . . . . . . . . . . . . . . . . . . . . 738
24.7.18 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
25
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
25.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
25.2
RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
25.3
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
25.3.1
Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
25.3.2
Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
25.3.3
Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
25.3.4
Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
25.3.5
RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
25.3.6
Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
25.3.7
Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
25.3.8
RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
25.3.9
RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
25.3.10 RTC coarse digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
25.3.11 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
25.3.12 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
25.3.13 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
25.3.14 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
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25.3.15 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
25.4
RTC and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
25.5
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
25.6
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
25.6.1
RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
25.6.2
RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
25.6.3
RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
25.6.4
RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 761
25.6.5
RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 763
25.6.6
RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . . 764
25.6.7
RTC calibration register (RTC_CALIBR) . . . . . . . . . . . . . . . . . . . . . . . 765
25.6.8
RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 766
25.6.9
RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 767
25.6.10 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 768
25.6.11 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 768
25.6.12 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 769
25.6.13 RTC time stamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 770
25.6.14 RTC time stamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 770
25.6.15 RTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . . 771
25.6.16 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 771
25.6.17 RTC tamper and alternate function configuration register
(RTC_TAFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
25.6.18 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 774
25.6.19 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 775
25.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 776
25.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
26
Fast-mode Plus Inter-integrated circuit interface (FMPI2C) . . . . . . . 779
26.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
26.2
FMPI2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
26.3
FMPI2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
26.4
FMPI2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
26.4.1
FMPI2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
26.4.2
FMPI2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
26.4.3
FMPI2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
26.4.4
FMPI2C mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
26.4.5
FMPI2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
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26.4.6
FMPI2C reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
26.4.7
FMPI2C data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
26.4.8
FMPI2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
26.4.9
FMPI2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
26.4.10 FMPI2C_TIMINGR register configuration examples . . . . . . . . . . . . . . 810
26.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
26.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
26.4.13 SMBus FMPI2C_TIMEOUTR register configuration examples . . . . . . 816
26.4.14 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
26.4.15 SMBus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
26.4.16 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
26.5
FMPI2C in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
26.6
FMPI2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
26.7
FMPI2C DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
26.7.1
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
26.7.2
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
26.8
FMPI2C debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
26.9
FMPI2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
26.9.1
FMPI2C control register 1 (FMPI2C_CR1) . . . . . . . . . . . . . . . . . . . . . 827
26.9.2
FMPI2C control register 2 (FMPI2C_CR2) . . . . . . . . . . . . . . . . . . . . . 830
26.9.3
FMPI2C own address 1 register (FMPI2C_OAR1) . . . . . . . . . . . . . . . 832
26.9.4
FMPI2C own address 2 register (FMPI2C_OAR2) . . . . . . . . . . . . . . . 832
26.9.5
FMPI2C timing register (FMPI2C_TIMINGR) . . . . . . . . . . . . . . . . . . . 833
26.9.6
FMPI2C timeout register (FMPI2C_TIMEOUTR) . . . . . . . . . . . . . . . . 834
26.9.7
FMPI2C interrupt and status register (FMPI2C_ISR) . . . . . . . . . . . . . 835
26.9.8
FMPI2C interrupt clear register (FMPI2C_ICR) . . . . . . . . . . . . . . . . . . 838
26.9.9
FMPI2C PEC register (FMPI2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . 839
26.9.10 FMPI2C receive data register (FMPI2C_RXDR) . . . . . . . . . . . . . . . . . 839
26.9.11 FMPI2C transmit data register (FMPI2C_TXDR) . . . . . . . . . . . . . . . . 840
26.9.12 FMPI2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
27
Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 842
27.1
I2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
27.2
I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
27.3
I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
27.3.1
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27.3.2
I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
27.3.3
I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
27.3.4
Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
27.3.5
Programmable noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
27.3.6
SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
27.3.7
SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
27.3.8
DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
27.3.9
Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
27.4
I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
27.5
I2C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
27.6
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
27.6.1
I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
27.6.2
I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
27.6.3
I2C own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 865
27.6.4
I2C own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 866
27.6.5
I2C data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
27.6.6
I2C status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
27.6.7
I2C status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
27.6.8
I2C clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 870
27.6.9
I2C TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
27.6.10 I2C FLTR register (I2C_FLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
27.6.11 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
28
Universal synchronous receiver transmitter (USART)
/universal asynchronous receiver transmitter (UART) . . . . . . . . . . . 874
28.1
USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
28.2
USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
28.3
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
28.4
USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
28.4.1
USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
28.4.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
28.4.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
28.4.4
Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
28.4.5
USART receiver tolerance to clock deviation . . . . . . . . . . . . . . . . . . . . 897
28.4.6
Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
28.4.7
Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
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28.4.8
LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 901
28.4.9
USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
28.4.10 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 905
28.4.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
28.4.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
28.4.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 910
28.4.14 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
29
28.5
USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
28.6
USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
28.6.1
Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
28.6.2
Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
28.6.3
Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
28.6.4
Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
28.6.5
Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
28.6.6
Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
28.6.7
Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 924
28.6.8
USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . . . . . . . . . . 926
29.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
29.1.1
SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
29.1.2
SPI extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
29.1.3
I2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
29.2
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
29.3
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
29.3.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
29.3.2
Communications between one master and one slave . . . . . . . . . . . . . 930
29.3.3
Standard multislave communication . . . . . . . . . . . . . . . . . . . . . . . . . . 933
29.3.4
Multimaster communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
29.3.5
Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 934
29.3.6
Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
29.3.7
SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
29.3.8
Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
29.3.9
Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 939
29.3.10 Procedure for disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
29.3.11 Communication using DMA (direct memory addressing) . . . . . . . . . . . 942
29.3.12 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
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29.3.13 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
29.4
SPI special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
29.4.1
TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
29.4.2
CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
29.5
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
29.6
I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
29.6.1
I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
29.6.2
I2S full-duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
29.6.3
Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
29.6.4
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
29.6.5
I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
29.6.6
I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
29.6.7
I2S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
29.6.8
I2S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
29.6.9
I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
29.6.10 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
29.7
SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
29.7.1
SPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 967
29.7.2
SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
29.7.3
SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
29.7.4
SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
29.7.5
SPI CRC polynomial register (SPI_CRCPR) (not used in I2S
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
29.7.6
SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode) . . . . . . 973
29.7.7
SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode) . . . . . . . 973
29.7.8
SPI_I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 974
29.7.9
SPI_I2S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 975
29.7.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
30
Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
30.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
30.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
30.3
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
30.4
Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
30.5
SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
30.6
Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
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30.7
Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
30.7.1
Frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
30.7.2
Frame synchronization polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
30.7.3
Frame synchronization active level length . . . . . . . . . . . . . . . . . . . . . . 984
30.7.4
Frame synchronization offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
30.7.5
FS signal role . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
30.8
Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
30.9
SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
30.10 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
30.11 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
30.12 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
30.12.1 Mute mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
30.12.2 MONO/STEREO function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
30.12.3 Companding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
30.12.4 Output data line management on an inactive slot . . . . . . . . . . . . . . . . 994
30.13 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
30.13.1 FIFO overrun/underrun (OVRUDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
30.13.2 Anticipated frame synchronisation detection (AFSDET) . . . . . . . . . . . 998
30.13.3 Late frame synchronization detection . . . . . . . . . . . . . . . . . . . . . . . . . 998
30.13.4 Codec not ready (CNRDY AC’97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
30.13.5 Wrong clock configuration in master mode (with NODIV = 0) . . . . . . . 999
30.14 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
30.15 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
30.16 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
30.17 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
30.17.1 SAI xConfiguration register 1 (SAI_xCR1) where x is A or B . . . . . . . 1002
30.17.2 SAI xConfiguration register 2 (SAI_xCR2) where x is A or B . . . . . . . 1005
30.17.3 SAI xFrame configuration register (SAI_XFRCR) where x is A or B . 1007
30.17.4 SAI xSlot register (SAI_xSLOTR) where x is A or B . . . . . . . . . . . . . 1009
30.17.5 SAI xInterrupt mask register2(SAI_xIM) where x is A or B . . . . . . . . 1010
30.17.6 SAI xStatus register (SAI_xSR) where x is A or B . . . . . . . . . . . . . . . 1012
30.17.7 SAI xClear flag register (SAI_xCLRFR) where X is A or B . . . . . . . . 1014
30.17.8 SAI xData register (SAI_xDR) where x is A or B . . . . . . . . . . . . . . . . 1015
30.17.9 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
31
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Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . 1017
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31.1
SDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
31.2
SDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
31.3
SDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
31.4
31.3.1
SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
31.3.2
SDIO APB2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
31.4.1
Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
31.4.2
Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
31.4.3
Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
31.4.4
Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
31.4.5
Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
31.4.6
Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
31.4.7
Stream access, stream write and stream read
(MultiMediaCard only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
31.4.8
Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . 1038
31.4.9
Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038
31.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038
31.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
31.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
31.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
31.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
31.5
31.6
31.7
Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
31.5.1
R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
31.5.2
R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
31.5.3
R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
31.5.4
R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
31.5.5
R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
31.5.6
R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
31.5.7
R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
31.5.8
R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
31.6.1
SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . 1057
31.6.2
SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . 1058
31.6.3
SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
31.6.4
SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
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31.8
SDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
31.8.1
SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . 1059
31.8.2
SDIO clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . 1059
31.8.3
SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . 1061
31.8.4
SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . 1061
31.8.5
SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . 1062
31.8.6
SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . 1062
31.8.7
SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . 1063
31.8.8
SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . 1064
31.8.9
SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . 1064
31.8.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . 1067
31.8.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
31.8.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . 1068
31.8.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
31.8.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . 1072
31.8.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . 1073
31.8.16 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
32
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
32.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
32.2
bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
32.3
bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
32.4
32.5
30/1321
32.3.1
CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
32.3.2
Control, status, and configuration registers . . . . . . . . . . . . . . . . . . . . 1078
32.3.3
Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
32.3.4
Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
32.4.1
Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
32.4.2
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
32.4.3
Sleep mode (low-power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
32.5.1
Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
32.5.2
Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
32.5.3
Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . 1083
32.6
Behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
32.7
bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
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32.7.1
Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
32.7.2
Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 1086
32.7.3
Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
32.7.4
Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
32.7.5
Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
32.7.6
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
32.7.7
Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
32.8
bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
32.9
CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
32.9.1
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
32.9.2
CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
32.9.3
CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
32.9.4
CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
32.9.5
bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . 1121
33.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1121
33.2
OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1122
33.2.1
General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
33.2.2
Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
33.2.3
Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
33.2.4
Split rail for USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
33.3
OTG_FS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1124
33.4
OTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1125
33.5
33.6
33.4.1
OTG_FS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
33.4.2
OTG_FS pin and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
33.4.3
OTG_FS core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
33.4.4
Embedded full-speed OTG PHY connected to OTG_FS . . . . . . . . . . 1126
33.4.5
OTG detections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
OTG_FS dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1127
33.5.1
ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
33.5.2
HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
33.5.3
SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
OTG_FS as a USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1128
33.6.1
SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
33.6.2
Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
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33.6.3
33.7
33.8
33.9
Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
OTG_FS as a USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1132
33.7.1
SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
33.7.2
USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
33.7.3
Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
33.7.4
Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
OTG_FS SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1137
33.8.1
Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
33.8.2
Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
OTG_FS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1138
33.10 OTG_FS Dynamic update of the OTG_HFIR register . . . . . . . . . . . . . .1139
33.11 OTG_FS data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1139
33.11.1 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
33.11.2 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
33.11.3 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
33.12 OTG_FS system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1144
33.13 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1144
33.14 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . .1146
33.14.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
33.15 OTG_FS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1150
33.15.1 OTG control and status register (OTG_GOTGCTL) . . . . . . . . . . . . . 1151
33.15.2 OTG interrupt register (OTG_GOTGINT) . . . . . . . . . . . . . . . . . . . . . 1154
33.15.3 OTG AHB configuration register (OTG_GAHBCFG) . . . . . . . . . . . . . 1155
33.15.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 1156
33.15.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 1158
33.15.6 OTG core interrupt register (OTG_GINTSTS) . . . . . . . . . . . . . . . . . . 1160
33.15.7 OTG interrupt mask register (OTG_GINTMSK) . . . . . . . . . . . . . . . . . 1164
33.15.8 OTG receive status debug read register (OTG_GRXSTSR) . . . . . . . 1167
33.15.9 OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . . 1168
33.15.10 OTG status read and pop registers (OTG_GRXSTSP) . . . . . . . . . . . 1169
33.15.11 OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . 1170
33.15.12 OTG receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 1171
33.15.13 OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
33.15.14 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
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33.15.15 OTG general core configuration register (OTG_GCCFG) . . . . . . . . . 1173
33.15.16 OTG core ID register (OTG_CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
33.15.17 OTG core LPM configuration register (OTG_GLPMCFG) . . . . . . . . . 1175
33.15.18 OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
33.15.19 OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
33.15.20 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
33.15.21 OTG host configuration register (OTG_HCFG) . . . . . . . . . . . . . . . . . 1180
33.15.22 OTG host frame interval register (OTG_HFIR) . . . . . . . . . . . . . . . . . 1181
33.15.23 OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
33.15.24 OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
33.15.25 OTG host all channels interrupt register (OTG_HAINT) . . . . . . . . . . 1183
33.15.26 OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
33.15.27 OTG host port control and status register (OTG_HPRT) . . . . . . . . . . 1185
33.15.28 OTG host channel x characteristics register (OTG_HCCHARx) . . . . 1187
33.15.29 OTG host channel x interrupt register (OTG_HCINTx) . . . . . . . . . . . 1188
33.15.30 OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . 1189
33.15.31 OTG host channel x transfer size register (OTG_HCTSIZx) . . . . . . . 1190
33.15.32 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
33.15.33 OTG device configuration register (OTG_DCFG) . . . . . . . . . . . . . . . 1191
33.15.34 OTG device control register (OTG_DCTL) . . . . . . . . . . . . . . . . . . . . 1192
33.15.35 OTG device status register (OTG_DSTS) . . . . . . . . . . . . . . . . . . . . . 1195
33.15.36 OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
33.15.37 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
33.15.38 OTG device all endpoints interrupt register (OTG_DAINT) . . . . . . . . 1198
33.15.39 OTG all endpoints interrupt mask register
(OTG_DAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
33.15.40 OTG device VBUS discharge time register
(OTG_DVBUSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
33.15.41 OTG device VBUS pulsing time register
(OTG_DVBUSPULSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
33.15.42 OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
33.15.43 OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
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33.15.44 OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . . 1202
33.15.45 OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . . 1205
33.15.46 OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
33.15.47 OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
33.15.48 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . 1208
33.15.49 OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
33.15.50 OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . 1210
33.15.51 OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
33.15.52 OTG device OUT endpoint x control register
(OTG_DOEPCTLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
33.15.53 OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
33.15.54 OTG power and clock gating control register (OTG_PCGCCTL) . . . 1216
33.15.55 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
33.16 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
33.16.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
33.16.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
33.16.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
33.16.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227
33.16.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248
33.16.6 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
33.16.7 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
34
Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
34.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
34.2
Reference Arm&reg; documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
34.3
SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1278
34.3.1
34.4
34.5
34/1321
Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1279
Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
34.4.1
SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
34.4.2
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
34.4.3
Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1280
34.4.4
Using serial wire and releasing the unused debug pins as GPIOs . . 1282
JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
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34.6
ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
34.6.1
MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
34.6.2
Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
34.6.3
Cortex&reg;-M4 with FPU TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
34.6.4
Cortex&reg;-M4 with FPU JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . 1285
34.7
JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285
34.8
SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
34.9
34.8.1
SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
34.8.2
SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
34.8.3
SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1288
34.8.4
DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
34.8.5
SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
34.8.6
SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
34.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
34.11 Capability of the debugger host to connect under system reset . . . . . 1292
34.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
34.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
34.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1293
34.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
34.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 1293
34.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
34.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
34.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
34.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
34.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
34.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
34.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1296
34.16.2 Debug support for timers, watchdog, bxCAN and I2C . . . . . . . . . . . . 1297
34.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 1297
34.16.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . . . . 1298
34.16.5 Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . . . . . 1300
34.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
34.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
34.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
RM0430 Rev 9
35/1321
36
Contents
RM0430
34.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
34.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1304
34.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 1304
34.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
34.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
34.17.8 TRACECLKIN connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
34.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
34.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
34.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
35
Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
35.1
Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
35.2
Flash size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309
35.3
Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309
36
Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311
37
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
36/1321
RM0430 Rev 9
RM0430
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Memory mapping vs. Boot mode/physical remap in STM32F413/423 . . . . . . . . . . . . . . . . 65
Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . 68
Maximum program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Access versus read protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
OTP area organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Flash register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CRC calculation unit register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Sleep-now entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Sleep-on-exit entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
BAM-now entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
BAM-on-exit entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Stop operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Stop mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Standby mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
RCC register map and reset values for STM32F413/423. . . . . . . . . . . . . . . . . . . . . . . . . 182
Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
RTC additional functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Source and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Source and destination address registers in double-buffer mode (DBM = 1) . . . . . . . . . . 226
Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . . . . . . . . . . . . . . . . 227
Restriction on NDT versus PSIZE and MSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
FIFO threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Possible DMA configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Vector table for STM32F413/423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 265
NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Non-multiplexed I/O NOR flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
16-bit multiplexed I/O NOR flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
RM0430 Rev 9
37/1321
42
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
38/1321
RM0430
NOR flash/PSRAM: example of supported memories
and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
FSMC_BCRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
FSMC_BTRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
FSMC_BCRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
FSMC_BTRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
FSMC_BWTRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
FSMC_BCRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
FSMC_BTRx bitfields (mode 2/B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
FSMC_BWTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
FSMC_BCRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
FSMC_BTRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
FSMC_BWTRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
FSMC_BCRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
FSMC_BTRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
FSMC_BWTRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
FSMC_BCRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
FSMC_BTRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
FSMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . 295
FSMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . 296
FSMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . 297
FSMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . 298
FSMC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
QUADSPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
QUADSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
QUADSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
External trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
ADC register map and reset values (common ADC registers) . . . . . . . . . . . . . . . . . . . . . 365
DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
DFSDMx implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
DFSDM external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
DFSDM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
DFSDM triggers connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
DFSDM break connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Demultiplexers (DM[6:1]) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Use-cases examples for beamforming applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Filter maximum output resolution (peak data values from filter output)
for some FOSR values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . 411
DFSDM interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
DFSDM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
RM0430 Rev 9
RM0430
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
List of tables
RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
RNG configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Output control bits for complementary OCx and OCxN channels
with break feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
TIM1&amp;TIM8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
TIMx internal trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
TIM2 to TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
TIMx internal trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
TIM9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
TIM10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
TIM6 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
STM32F413/423 LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Min/max IWDG timeout periods (ms) at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
AES internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
CTR mode initialization vector definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
GCM mode IVI bitfield initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Initialization of AES_IVRx registers in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . . . . . . . . . . . 723
DMA channel configuration for memory-to-AES data transfer . . . . . . . . . . . . . . . . . . . . . 724
DMA channel configuration for AES-to-memory data transfer . . . . . . . . . . . . . . . . . . . . . 725
AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Processing latency (in clock cycle) for ECB, CBC and CTR. . . . . . . . . . . . . . . . . . . . . . . 727
Processing latency for GCM and CCM (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . 727
AES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Effect of low power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
FMPI2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
FMPI2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
FMPI2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Comparison of analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
I&sup2;C-bus and SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . 786
FMPI2C configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
I&sup2;C-bus and SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Timing settings for fI2CCLK of 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
Timing settings for fI2CCLK of 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
RM0430 Rev 9
39/1321
42
List of tables
Table 149.
Table 150.
Table 151.
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
40/1321
RM0430
SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
TIMEOUTA[11:0] for maximum tTIMEOUT of 25 ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
TIMEOUTB[11:0] for maximum tLOW:SEXT and tLOW:MEXT of 8 ms . . . . . . . . . . . . . . . . . 816
TIMEOUTA[11:0] for maximum tIDLE of 50 &micro;s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Effect of low-power modes to FMPI2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
FMPI2C interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
FMPI2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . . . . . . . . . . . . . . . . . . 854
SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 12 MHz,
oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Error calculation for programmed baud rates at fPCLK = 16 MHz or fPCLK = 24 MHz,
oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz,
oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz,
oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz,
oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz,
oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
USART receiver tolerance when DIV fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
USART receiver tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . . 898
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
STM32F413/423 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 960
I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Example of possible audio frequency sampling range . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
Long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
RM0430 Rev 9
RM0430
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
Table 202.
Table 203.
Table 204.
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
List of tables
Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
DPSM flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Response type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
CAN implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
OTG_FS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
OTG_FS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
OTG_FS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
OTG_FS input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
Compatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 1138
Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150
Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150
TRDT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285
32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 1286
Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
RM0430 Rev 9
41/1321
42
List of tables
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
Table 251.
Table 252.
Table 253.
42/1321
RM0430
SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
Cortex&reg;-M4 with FPU AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
RM0430 Rev 9
RM0430
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
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Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
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Figure 26.
Figure 27.
Figure 28.
Figure 29.
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Figure 35.
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Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Flash memory interface connection inside system architecture . . . . . . . . . . . . . . . . . . . . . 66
Sequential 32-bit instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PCROP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Frequency measurement with TIM5 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . 127
Frequency measurement with TIM11 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . 128
Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Selecting an alternate function on STM32F413/423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
DMA block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Peripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Memory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
FIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
FSMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
FSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Mode 1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Mode 1 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Mode A read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Mode A write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Mode 2 and mode B read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Mode 2 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Mode B write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Mode C read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Mode C write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Mode D read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Mode D write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
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List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
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Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
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Figure 76.
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Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
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Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . . 295
Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . . 297
QUADSPI block diagram when dual-flash mode is disabled . . . . . . . . . . . . . . . . . . . . . . 308
QUADSPI block diagram when dual-flash mode is enabled . . . . . . . . . . . . . . . . . . . . . . 309
Example of read command in quad-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Example of a DDR command in quad-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
NCS when CKMODE = 0 (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 321
NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 322
NCS when CKMODE = 1 with an abort (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . 322
Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Analog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Right alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Left alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Left alignment of 6-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 348
DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 370
DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 372
DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 373
Single DFSDM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Input channel pins redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Clock absence timing diagram for SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Clock absence timing diagram for Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
First conversion for Manchester coding (Manchester synchronization) . . . . . . . . . . . . . . 401
Multi-channel delay block for pulse skipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Pulses skipper operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
DFSDM_CHyDATINR registers operation modes and assignment . . . . . . . . . . . . . . . . . 409
Example: Sinc3 filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Entropy source model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 464
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 464
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
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List of figures
Figure 99. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Figure 100. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 471
Figure 101. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 472
Figure 102. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Figure 103. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 473
Figure 104. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Figure 105. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 474
Figure 106. Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 474
Figure 107. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 476
Figure 108. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 477
Figure 109. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Figure 110. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Figure 111. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Figure 112. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Figure 113. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 481
Figure 114. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Figure 115. Output stage of capture/compare channel (channels 1 to 3) . . . . . . . . . . . . . . . . . . . . . . 482
Figure 116. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Figure 117. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Figure 118. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
Figure 119. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Figure 120. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Figure 121. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Figure 122. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 490
Figure 123. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 490
Figure 124. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Figure 125. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Figure 126. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Figure 127. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Figure 128. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 499
Figure 129. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 499
Figure 130. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Figure 131. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Figure 132. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Figure 133. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Figure 134. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Figure 135. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 136. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 534
Figure 137. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 535
Figure 138. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Figure 139. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Figure 140. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Figure 141. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Figure 142. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 537
Figure 143. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 538
Figure 144. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Figure 145. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Figure 146. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Figure 147. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Figure 148. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Figure 149. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 541
Figure 150. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
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Figure 151. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 542
Figure 152. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Figure 153. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 543
Figure 154. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 543
Figure 155. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 156. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 157. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Figure 158. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Figure 159. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Figure 160. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 548
Figure 161. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Figure 162. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 163. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Figure 164. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Figure 165. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Figure 166. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
Figure 167. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Figure 168. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Figure 169. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 559
Figure 170. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 560
Figure 171. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Figure 172. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Figure 173. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Figure 174. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Figure 175. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Figure 176. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Figure 177. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Figure 178. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Figure 179. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Figure 180. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure 181. General-purpose timer block diagram (TIM9 and TIM12) . . . . . . . . . . . . . . . . . . . . . . . . 594
Figure 182. General-purpose timer block diagram (TIM10/11/13/14) . . . . . . . . . . . . . . . . . . . . . . . . . 595
Figure 183. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 597
Figure 184. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 597
Figure 185. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Figure 186. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Figure 187. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Figure 188. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Figure 189. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Figure 190. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Figure 191. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 601
Figure 192. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
Figure 193. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
Figure 194. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 603
Figure 195. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Figure 196. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Figure 197. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Figure 198. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Figure 199. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Figure 200. Example of One-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
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Figure 201. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Figure 202. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Figure 203. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Figure 204. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 205. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 642
Figure 206. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 642
Figure 207. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Figure 208. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 209. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 210. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 211. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 212. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Figure 213. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 647
Figure 214. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Figure 215. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Figure 216. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . . 658
Figure 217. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Figure 218. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 659
Figure 219. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Figure 220. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Figure 221. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
Figure 222. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Figure 223. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
Figure 224. AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Figure 225. ECB encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Figure 226. CBC encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Figure 227. CTR encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Figure 228. GCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Figure 229. GMAC authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Figure 230. CCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Figure 231. STM32 cryptolib AES flowchart examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Figure 232. STM32 cryptolib AES flowchart examples (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Figure 233. Encryption key derivation for ECB/CBC decryption (Mode 2). . . . . . . . . . . . . . . . . . . . . . 700
Figure 234. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Figure 235. ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Figure 236. ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Figure 237. CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Figure 238. CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Figure 239. ECB/CBC encryption (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Figure 240. ECB/CBC decryption (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Figure 241. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Figure 242. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Figure 243. CTR decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Figure 244. Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Figure 245. GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Figure 246. Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Figure 247. GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Figure 248. Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Figure 249. CCM mode authenticated decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
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Figure 250. 128-bit block construction with respect to data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Figure 251. DMA transfer of a 128-bit data block during input phase . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 252. DMA transfer of a 128-bit data block during output phase . . . . . . . . . . . . . . . . . . . . . . . . 725
Figure 253. AES interrupt signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Figure 254. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Figure 255. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Figure 256. I&sup2;C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
Figure 257. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Figure 258. FMPI2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Figure 259. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Figure 260. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Figure 261. Slave initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Figure 262. Transfer sequence flow for FMPI2C slave transmitter, NOSTRETCH = 0 . . . . . . . . . . . . 794
Figure 263. Transfer sequence flow for FMPI2C slave transmitter, NOSTRETCH = 1 . . . . . . . . . . . . 795
Figure 264. Transfer bus diagrams for FMPI2C slave transmitter (mandatory events only) . . . . . . . . 796
Figure 265. Transfer sequence flow for FMPI2C slave receiver, NOSTRETCH = 0 . . . . . . . . . . . . . 797
Figure 266. Transfer sequence flow for FMPI2C slave receiver, NOSTRETCH = 1 . . . . . . . . . . . . . 798
Figure 267. Transfer bus diagrams for FMPI2C slave receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
Figure 268. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Figure 269. Master initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Figure 270. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Figure 271. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Figure 272. Transfer sequence flow for FMPI2C master transmitter, N ≤ 255 bytes . . . . . . . . . . . . . . 804
Figure 273. Transfer sequence flow for FMPI2C master transmitter, N &gt; 255 bytes. . . . . . . . . . . . . . 805
Figure 274. Transfer bus diagrams for FMPI2C master transmitter
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Figure 275. Transfer sequence flow for FMPI2C master receiver, N ≤ 255 bytes . . . . . . . . . . . . . . . 808
Figure 276. Transfer sequence flow for FMPI2C master receiver, N &gt; 255 bytes . . . . . . . . . . . . . . . . 809
Figure 277. Transfer bus diagrams for FMPI2C master receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Figure 278. Timeout intervals for tLOW:SEXT, tLOW:MEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
Figure 279. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . . . . . 817
Figure 280. Transfer bus diagram for SMBus slave transmitter (SBC = 1) . . . . . . . . . . . . . . . . . . . . . 818
Figure 281. Transfer sequence flow for SMBus slave receiver N bytes + PEC. . . . . . . . . . . . . . . . . . 819
Figure 282. Bus transfer diagrams for SMBus slave receiver (SBC = 1). . . . . . . . . . . . . . . . . . . . . . . 820
Figure 283. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
Figure 284. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Figure 285. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
Figure 286. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
Figure 287. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Figure 288. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Figure 289. Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Figure 290. Transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
Figure 291. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
Figure 292. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
Figure 293. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
Figure 294. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Figure 295. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Figure 296. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
Figure 297. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Figure 298. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
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Figure 299. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
Figure 300. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
Figure 301. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 902
Figure 302. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 903
Figure 303. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Figure 304. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Figure 305. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Figure 306. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Figure 307. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Figure 308. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
Figure 309. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
Figure 310. IrDA data modulation (3/16) -Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
Figure 311. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
Figure 312. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
Figure 313. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
Figure 314. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
Figure 315. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
Figure 316. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Figure 317. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
Figure 318. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
Figure 319. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
Figure 320. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
Figure 321. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Figure 322. Multimaster application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
Figure 323. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Figure 324. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Figure 325. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Figure 326. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Figure 327. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
Figure 328. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Figure 329. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
Figure 330. I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Figure 331. I2S full-duplex block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Figure 332. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 953
Figure 333. I2S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 953
Figure 334. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Figure 335. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 336. I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 954
Figure 337. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 954
Figure 338. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 955
Figure 339. MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Figure 340. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 955
Figure 341. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 342. LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 343. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 344. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 345. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 957
Figure 346. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 957
Figure 347. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
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Figure 348. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 958
Figure 349. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
Figure 350. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
Figure 351. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
Figure 352. Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
Figure 353. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . . 985
Figure 354. FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
Figure 355. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . . 986
Figure 356. First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
Figure 357. Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
Figure 358. AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
Figure 359. Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . . 993
Figure 360. Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Figure 361. Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
Figure 362. Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
Figure 363. FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
Figure 364. “No response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
Figure 365. (Multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
Figure 366. (Multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
Figure 367. Sequential read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Figure 368. Sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Figure 369. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Figure 370. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
Figure 371. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
Figure 372. SDIO_CK clock dephasing (BYPASS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
Figure 373. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Figure 374. Command path state machine (SDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
Figure 375. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
Figure 376. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Figure 377. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
Figure 378. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Figure 379. Dual-CAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Figure 380. Single-CAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Figure 381. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Figure 382. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Figure 383. bxCAN in Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Figure 384. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
Figure 385. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Figure 386. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Figure 387. Filter bank scale configuration - Register organization . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
Figure 388. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
Figure 389. Filtering mechanism example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
Figure 390. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
Figure 391. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
Figure 392. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
Figure 393. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
Figure 394. CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
Figure 395. OTG_FS full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Figure 396. OTG_FS A-B device connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Figure 397. OTG_FS peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
Figure 398. OTG_FS host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
Figure 399. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . . . . . . . . . . . . 1137
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Figure 400. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
Figure 401. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 1140
Figure 402. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . 1141
Figure 403. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
Figure 404. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228
Figure 405. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
Figure 406. Normal bulk/control OUT/SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
Figure 407. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
Figure 408. Normal interrupt OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
Figure 409. Normal interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
Figure 410. Isochronous OUT transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244
Figure 411. Isochronous IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247
Figure 412. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
Figure 413. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
Figure 414. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
Figure 415. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
Figure 416. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
Figure 417. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272
Figure 418. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
Figure 419. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
Figure 420. Block diagram of STM32 MCU and Cortex&reg;-M4 with FPU-level
debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
Figure 421. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
Figure 422. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283
Figure 423. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
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Documentation conventions
1.1
General information
The STM32F413/423 devices have an Arm&reg;(a) Cortex&reg;-M4 with FPU core.
1.2
List of abbreviations for registers
The following abbreviations(b) are used in register descriptions:
read/write (rw)
Software can read and write to this bit.
read-only (r)
Software can only read this bit.
write-only (w)
Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0)
Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1)
Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w)
Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r)
Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r)
Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs)
Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo)
Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t)
The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.)
Reserved bit, must be kept at reset value.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.
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Documentation conventions
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
•
1.4
Word: data of 32-bit length.
•
Half-word: data of 16-bit length.
•
Byte: data of 8-bit length.
•
IAP (in-application programming): IAP is the ability to re-program the flash memory
of a microcontroller while the user program is running.
•
ICP (in-circuit programming): ICP is the ability to program the flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
•
Option bytes: device configuration bits stored in the flash memory.
•
AHB: advanced high-performance bus.
Availability of peripherals
For availability of peripherals and their number across all devices, refer to the particular
device datasheet.
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2
System and memory overview
2.1
System architecture
In STM32F413/423, the main system consists of 32-bit multilayer AHB bus matrix that
interconnects:
•
•
Six masters:
–
Cortex&reg;-M4 with FPU core I-bus, D-bus and S-bus
–
DMA1 memory bus
–
DMA2 memory bus
–
DMA2 peripheral bus
Seven slaves:
–
Internal Flash memory ICode bus
–
Internal Flash memory DCode bus
–
Main internal SRAM1 (256 KB)
–
Auxiliary internal SRAM2 (64 KB)
–
AHB1 peripherals including AHB to APB bridges and APB peripherals
–
AHB2 peripherals
–
FSMC / QuadSPI
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1.
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System and memory overview
Figure 1. System architecture
S3
S4
S5
Access through remap
Access by aliasing
M0 ICODE
M1 DCODE
Flash
Up to 1.5 MB
M2
SRAM1
256 KB
M3
AHB
periph. 1
APB1
M4
AHB
periph. 2
APB2
M5
FSMC external
MemCtrl/
QuadSPI
M6
Bus matrix-S
ACCEL
DMA_P2
S2
DMA_MEM2
S-bus
S1
DMA_MEM1
D-bus
S0
GP
DMA2
GP
DMA1
DMA_PI
I-bus
ARM
Cortex-M4
SRAM2
64 KB
MSv40821V3
2.1.1
I-bus
This bus connects the Instruction bus of the Cortex&reg;-M4 with FPU core to the BusMatrix.
This bus is used by the core to fetch instructions. The target of this bus is a memory
containing code (internal Flash memory/SRAM1/SRAM2).
2.1.2
D-bus
This bus connects the databus of the Cortex&reg;-M4 with FPU to the BusMatrix. This bus is
used by the core for literal load and debug access. The target of this bus is a memory
containing code or data (internal Flash memory/SRAM1/SRAM2).
2.1.3
S-bus
This bus connects the system bus of the Cortex&reg;-M4 with FPU core to a BusMatrix. This
bus is used to access data located in a peripheral or in SRAM1 or in SRAM2. Instructions
may also be fetch on this bus (less efficient than ICode). The targets of this bus are the
internal SRAM1/SRAM2, the AHB1 peripherals including the APB peripherals, the AHB2
peripherals and the external memories through the FSMC and the QUADSPI.
2.1.4
DMA memory bus
This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
internal Flash memory, internal SRAM1/SRAM2 and additionally for S4 the AHB1/AHB2
peripherals including the APB peripherals.
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System and memory overview
2.1.5
RM0430
DMA peripheral bus
This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is
used by the DMA to access AHB peripherals or to perform memory-to-memory transfers.
The targets of this bus are the AHB and APB peripherals plus data memories: Flash
memory and internal SRAM1/SRAM2.
2.1.6
BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
round-robin algorithm.
2.1.7
AHB/APB bridges (APB)
The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between
the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.
Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies,
and to Table 1 for the address mapping of AHB and APB peripherals.
After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash
memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR or RCC_APBxENR register.
Note:
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When a 16- or an 8-bit access is performed on an APB register, the access is transformed
into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
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2.2
Memory organization
2.2.1
Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into eight main blocks, of 512 Mbytes each.
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2.2.2
Memory map and register boundary addresses
Figure 2. Memory map
Reserved
0xE010 0000 - 0xFFFF FFFF
Cortex&acirc;-M4 internal
peripherals
0xE000 0000 - 0xE00F FFFF
Reserved
0xA000 2000 – 0DFFF FFF
0A000 1FFF
AHB3
0x6000 0000
0x5FFF FFFF
AHB2
0xFFFF FFFF
512-Mbyte
block 7
0xE000 0000
0xDFFF FFFF
0xC000 0000
0xBFFF FFFF
Reserved
0x5000 0000
0x4002 6800 - 0x4FFF FFFF
0x4002 67FF
internal
peripherals
512-Mbyte
block 6
Not used
AHB1
Reserved
0xA000 2000
0xA000 1FFF
Reserved
0x4002 0000
0x4001 6800 - 0x4001 FFFF
0x4001 67FF
FMC
And
QuadSPI
0x6000 0000
0x5FFF FFFF
0x4000 0000
0x3FFF FFFF
APB2
512-Mbyte
block 2
peripherals
512-Mbyte
block 1 inc.
SRAM1/SRAM2
0x2000 0000
0x1FFF FFFF
512-Mbyte
block 0
Code
0x0000 0000
Reserved
SRAM2 (64 KB aliased
by bit-banding)
SRAM1 (256 KB aliased
by bit-banding)
Reserved
User option bytes
Reserved
OTP area + lock
0x2005 0000 - 0x3FFF FFFF
0x2004 0000 - 0x2004 FFFF
Reserved
0x2000 0000 - 0x2003 FFFF
0x4001 0000
0x4000 8000 - 0x4000 FFFF
0x4000 7FFF
0x1FFF C010 - 0x1FFF FFFF
0x1FFF C000 - 0x1FFF C00F
0x1FFF 7A10 - 0x1FFF BFFF
0x1FFF 7800 - 0x1FFF 7A0F
System memory
0x1FFF 0000- 0x1FFF 77FF
Reserved
0x1001 0000 - 0x1FFE FFFF
APB1
SRAM2 (64KB accessed by
0x1000 0000 - 0x1000 FFFF
CPU via Ibus and Dbus)
Reserved
0x0818 0000 - 0x0FFF FFFF
Flash memory
0x0800 0000 - 0x0817 FFFF
Aliased to Flash, system,
memory or SRAM1
depending, on the BOOT pins 0x0000 0000 - 0x07FF FFFF
0x4000 0000
MSv40822V2
All the memory map areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
refer to the following table.
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The following table gives the boundary addresses of the peripherals available in the
devices.
Table 1. Register boundary addresses
Bus
Boundary address
-
0xE010 0000 - 0xFFFF FFFF
Reserved
Cortex&reg;-M4
0xE000 0000 - 0xE00F FFFF
Cortex-M4 internal peripherals
0xA000 2000 - 0xDFFF FFFF
Reserved
0xA000 1000 - 0xA000 1FFF
QuadSPI control register
0xA000 0000 - 0xA000 0FFF
FSMC control register
0x9000 0000 - 0x9FFF FFFF
QUADSPI
0x7000 0000 - 0x08FFF FFFF
Reserved
0x6000 0000 - 0x6FFF FFFF
FSMC
0x5006 0C00 - 0x5FFF FFFF
Reserved
0x5006 0800 0x5006 0BFF
RNG
0x5006 0400 - 0x5006 07FF
Reserved
0x5006 0000 - 0x5006 03FF
AES(1)
0x5004 0000 - 0x5005 FFFF
Reserved
0x5000 0000 - 0x5003 FFFF
USB OTG FS
0x4002 6800 - 0x4FFF FFFF
Reserved
0x4002 6400 - 0x4002 67FF
DMA2
0x4002 6000 - 0x4002 63FF
DMA1
0x4002 4000 - 0X4002 5FFF
Reserved
0x4002 3C00 - 0x4002 3FFF
Flash interface register
0x4002 3800 - 0x4002 3BFF
RCC
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2000 - 0x4002 2FFF
Reserved
0x4002 1C00 - 0x4002 1FFF
GPIOH
0x4002 1800 - 0x4002 1BFF
GPIOG
0x4002 1400 - 0x4002 17FF
GPIOF
0x4002 1000 - 0x4002 13FF
GPIOE
0x4002 0C00 - 0x4002 0FFF
GPIOD
0x4002 0800 - 0x4002 0BFF
GPIOC
0x4002 0400 - 0x4002 07FF
GPIOB
0x4002 0000 - 0x4002 03FF
GPIOA
AHB3
AHB2
AHB1
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Table 1. Register boundary addresses (continued)
Bus
APB2
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Boundary address
Peripheral
0x4001 6800 - 0x4001 FFFF
Reserved
0x4001 6400 - 0x4001 67FF
DFSDM2
0x4001 6000 - 0x4001 63FF
DFSDM1
0x4001 5C00 - 0x4001 5FFF
Reserved
0x4001 5800 - 0x4001 5BFF
SAI1
0x4001 5400 - 0x4001 57FF
Reserved
0x4001 5000 - 0x4001 53FF
SPI5/I2S5
0x4001 4C00 - 0x4001 4FFF
Reserved
0x4001 4800 - 0x4001 4BFF
TIM11
0x4001 4400 - 0x4001 47FF
TIM10
0x4001 4000 - 0x4001 43FF
TIM9
0x4001 3C00 - 0x4001 3FFF
EXTI
0x4001 3800 - 0x4001 3BFF
SYSCFG
0x4001 3400 - 0x4001 37FF
SPI4/I2S4
0x4001 3000 - 0x4001 33FF
SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF
SDIO
0x4001 2400 - 0x4001 2BFF
Reserved
0x4001 2000 - 0x4001 23FF
ADC1
0x4001 1C00 - 0x4001 1FFF
UART10
0x4001 1800 - 0x4001 1BFF
UART9
0x4001 1400 - 0x4001 17FF
USART6
0x4001 1000 - 0x4001 13FF
USART1
0x4001 0800 - 0x4001 0FFF
Reserved
0x4001 0400 - 0x4001 07FF
TIM8
0x4001 0000 - 0x4001 03FF
TIM1
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Table 1. Register boundary addresses (continued)
Bus
APB1
Boundary address
Peripheral
0x4000 8000 - 0x4000 FFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
UART8
0x4000 7800 - 0x4000 7BFF
UART7
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PWR
0x4000 6C00 - 0x4000 6FFF
CAN3
0x4000 6800 - 0x4000 6BFF
CAN2
0x4000 6400 - 0x4000 67FF
CAN1
0x4000 6000 - 0x4000 63FF
I2CFMP1
0x4000 5C00 - 0x4000 5FFF
I2C3
0x4000 5800 - 0x4000 5BFF
I2C2
0x4000 5400 - 0x4000 57FF
I2C1
0x4000 5000 - 0x4000 53FF
UART5
0x4000 4C00 - 0x4000 4FFF
UART4
0x4000 4800 - 0x4000 4BFF
USART3
0x4000 4400 - 0x4000 47FF
USART2
0x4000 4000 - 0x4000 43FF
I2S3ext
0x4000 3C00 - 0x4000 3FFF
SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF
SPI2 / I2S2
0x4000 3400 - 0x4000 37FF
I2S2ext
0x4000 3000 - 0x4000 33FF
IWDG
0x4000 2C00 - 0x4000 2FFF
WWDG
0x4000 2800 - 0x4000 2BFF
RTC &amp; BKP Registers
0x4000 2400 - 0x4000 27FF
LPTIM1
0x4000 2000 - 0x4000 23FF
TIM14
0x4000 1C00 - 0x4000 1FFF
TIM13
0x4000 1800 - 0x4000 1BFF
TIM12
0x4000 1400 - 0x4000 17FF
TIM7
0x4000 1000 - 0x4000 13FF
TIM6
0x4000 0C00 - 0x4000 0FFF
TIM5
0x4000 0800 - 0x4000 0BFF
TIM4
0x4000 0400 - 0x4000 07FF
TIM3
0x4000 0000 - 0x4000 03FF
TIM2
1. AES is only available for STM32F423xx. This boundary address is reserved for STM32F413xx.
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2.3
Embedded SRAM
STM32F413/423 devices feature 320 Kbytes of system SRAM.
The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
Read and write operations are performed at CPU speed with 0 wait state.
The embedded SRAM is divided into two blocks:
•
SRAM1 mapped at address 0x2000 0000 and accessible by all AHB masters.
•
SRAM2 mapped at address 0x2004 0000 and accessible by all AHB masters.
The CPU can access the embedded SRAM1, through the System Bus or through the ICode/D-Code buses when boot from SRAM1 is selected or when physical remap is
selected (See Section 8.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP)).
To get the max performance on SRAM1 execution, physical remap should be selected (boot
or software selection).
The CPU can access the embedded SRAM2, through the System Bus or through the ICode/D-Code buses when SRAM2 is mapped at the address range: 0x1000 0000 to
0x1000 FFFF. To get the max performance on SRAM2 execution, mapping at the address
0x1000 0000 should be selected.
To get the max performance on embedded SRAM, use SRAM1/SRAM2 to execute code via
I-code and SRAM2/SRAM1 to store data
2.4
Flash memory overview
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms. It accelerates code execution with a system of instruction
prefetch and cache lines.
The Flash memory is organized as follows:
•
A main memory block divided into sectors.
•
System memory from which the device boots in System memory boot mode
•
512 OTP (one-time programmable) bytes for user data.
•
Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
Refer to Section 3: Embedded Flash memory interface for more details.
2.5
Bit banding
The Cortex&reg;-M4 with FPU memory map includes two bit-band regions. These regions map
each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a
word in the alias region has the same effect as a read-modify-write operation on the
targeted bit in the bit-band region.
In the STM32F4x3xx devices both the peripheral registers and the SRAM1 are mapped to a
bit-band region, so that single bit-band write and read operations are allowed. The
operations are only available for Cortex&reg;-M4 with FPU accesses, and not from other bus
masters (e.g. DMA).
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A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region. The mapping formula is:
bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number &times; 4)
where:
–
bit_word_addr is the address of the word in the alias memory region that maps to
the targeted bit
–
bit_band_base is the starting address of the alias region
–
byte_offset is the number of the byte in the bit-band region that contains the
targeted bit
–
bit_number is the bit position (0-7) of the targeted bit
Example
The following example shows how to map bit 2 of the byte located at SRAM1 address
0x20000300 to the alias region:
0x22006008 = 0x22000000 + (0x300*32) + (2*4)
Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit
2 of the byte at SRAM1 address 0x20000300.
Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM1
address 0x20000300 (0x01: bit set; 0x00: bit reset).
For more information on bit-banding, refer to the Cortex&reg;-M4 with FPU programming
manual (see Related documents on page 1).
2.6
Boot configuration
Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed
through the ICode/DCode buses) while the data area (SRAM) starts from address
0x2000 0000 (accessed through the system bus). The Cortex&reg;-M4 with FPU CPU always
fetches the reset vector on the ICode bus, which implies to have the boot space available
only in the code area (typically, Flash memory). STM32F4xx microcontrollers implement a
special mechanism to be able to boot from other memories (like the internal SRAM).
In the STM32F4x3xx, three different boot modes can be selected through the BOOT[1:0]
pins as shown in Table 2.
Table 2. Boot modes
Boot mode selection pins
Boot mode
Aliasing
BOOT1
BOOT0
x
0
Main Flash memory Main Flash memory is selected as the boot space
0
1
System memory
System memory is selected as the boot space
1
1
Embedded SRAM
Embedded SRAM is selected as the boot space
The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It
is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot
mode.
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BOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been
sampled, the corresponding GPIO pin is free and can be used for other purposes.
The BOOT pins are also resampled when the device exits the Standby mode. Consequently,
they must be kept in the required Boot mode configuration when the device is in the Standby
mode. After this startup delay is over, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.
Note:
When the device boots from SRAM, in the application initialization code, you have to
relocate the vector table in SRAM using the NVIC exception table and the offset register.
Embedded bootloader
The embedded bootloader mode is used to reprogram the Flash memory using one of the
interface described in the table below. The availability of the interface is package
dependent.
Table 3. Embedded bootloader interfaces
Package
USART1 USART2 USART3 I2C1
PA9/
PD6/
PB11/
PB6/
PA10
PD5
PB10
PB7
SPI3
I2C2
PF0/
PF1
I2C3
PA8/
PB4
I2C
FMP1
PB14/
PB15
SPI1
PA4/
PA5/
PA6/
PA7
PA15/
PC10/
PC11/
PC12
SPI4
PE11/ CAN2 USB
PE12/ PB5/ PA11
PE13/ PB13 /P12
PE14
UFQFPN48
Y
-
-
Y
-
Y
Y
Y
-
-
Y
Y
LQFP64
Y
-
-
Y
-
Y
Y
Y
Y
-
Y
Y
WLCSP81
Y
-
-
Y
-
Y
Y
Y
Y
Y
Y
Y
LQFP100
Y
Y
-
Y
-
Y
Y
Y
Y
Y
Y
Y
LQFP144
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
UFBGA100
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
UFBGA144
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
The USART peripherals operate at the internal 16 MHz oscillator (HSI) frequency, while the
CAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to
26 MHz).
The embedded bootloader code is located in system memory. It is programmed by ST
during production. For additional information, refer to application note AN2606.
Physical remap in STM32F413/423
Once the boot pins are selected, the application software can modify the memory
accessible in the code area (in this way the code can be executed through the ICode bus in
place of the System bus). This modification is performed by programming the Section 8.2.1:
SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.
The following memories can thus be remapped:
64/1321
•
Main Flash memory
•
System memory
•
Embedded SRAM
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Table 4. Memory mapping vs. Boot mode/physical remap in STM32F413/423
Addresses
Boot/Remap in main
Flash memory
Boot/Remap in
embedded SRAM
Boot/Remap in
System memory
0x2000 0000 - 0x2003 FFFF
SRAM (256 KB)
SRAM (256KB)
SRAM (256KB)
0x1FFF 0000 - 0x1FFF 77FF
System memory
System memory
System memory
0x0802 0000 - 0x1FFE FFFF
Reserved
Reserved
Reserved
0x0800 0000 - 0x080F FFFF
Flash memory
Flash memory
Flash memory
0x0400 000 - 0x07FF FFFF
Reserved
Reserved
Reserved
0x0000 0000 - 0x0003 FFFF(1)
Flash (1M) Aliased
SRAM1 (256 KB)
Aliased
System memory
(30 KB) Aliased
1. Even when aliased in the boot memory space, the related memory is still accessible at its original memory
space.
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Embedded Flash memory interface
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3
Embedded Flash memory interface
3.1
Introduction
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2
Main features
•
Flash memory read operations
•
Flash memory program/erase operations
•
Read / write protections
•
Prefetch on I-Code
•
64 cache lines of 128 bits on I-Code
•
8 cache lines of 128 bits on D-Code
Figure 3 shows the Flash memory interface connection inside the system architecture.
Figure 3. Flash memory interface connection inside system architecture
Cortex-M4 with FPU
I-Code bus
I-Code
AHB
32-bit
instruction Flash interface
bus
Flash
memory
D-Code
Cortex
core
S bus
D-code bus
AHB
32-bit
data bus
FLITF registers
AHB
32-bit
system bus
DMA1
Flash
memory
bus
128 bits
DMA2
AHB
periph1
SRAM and
External
memories
AHB
periph2
Access to instruction in Flash memory
Access to data and literal pool in Flash memory
FLITF register access
MS31423V1
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3.3
Embedded Flash memory interface
Embedded Flash memory
The Flash memory has the following main features:
•
Capacity up to 1.5 Mbyte
•
128 bits wide data read
•
Byte, half-word, word and double word write
•
Sector and mass erase
•
Memory organization
The Flash memory is organized as follows:
–
A main memory block divided into 4 sectors of 16 Kbyte, plus 1 sector of 64 Kbyte
and plus 11 sector of 128 Kbyte.
–
System memory from which the device boots in System memory boot mode
–
512 OTP (one-time programmable) bytes for user data
The OTP area contains 32 additional bits used to lock the corresponding OTP
data block.
–
•
Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
Low-power modes (for details refer to the Power control (PWR) section of the reference
manual)
Table 5. Flash module organization
Block
Main memory
Name
Block base addresses
Size
Sector 0
0x0800 0000 - 0x0800 3FFF
16 Kbyte
Sector 1
0x0800 4000 - 0x0800 7FFF
16 Kbyte
Sector 2
0x0800 8000 - 0x0800 BFFF
16 Kbyte
Sector 3
0x0800 C000 - 0x0800 FFFF
16 Kbyte
Sector 4
0x0801 0000 - 0x0801 FFFF
64 Kbyte
Sector 5
0x0802 0000 - 0x0803 FFFF
128 Kbyte
Sector 6
0x0804 0000 - 0x0805 FFFF
128 Kbyte
Sector 7
0x0806 0000 - 0x0807 FFFF
128 Kbyte
Sector 8
0x0808 0000 - 0x0809 FFFF
128 Kbyte
Sector 9
0x080A 0000 - 0x080B FFFF
128 Kbyte
Sector 10
0x080C 0000 - 0x080D FFFF
128 Kbyte
Sector 11
0x080E 0000 - 0x080F FFFF
128 Kbyte
Sector 12
0x08010 0000 - 0x0811 FFFF
128 Kbyte
Sector 13
0x0812 0000 - 0x0813 FFFF
128 Kbyte
Sector 14
0x0814 0000 - 0x0815 FFFF
128 Kbyte
Sector 15
0x0816 0000 - 0x0817 FFFF
128 Kbyte
0x1FFF 0000 - 0x1FFF 77FF
30 Kbyte
System memory
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Table 5. Flash module organization (continued)
Block
Name
Block base addresses
Size
OTP area
0x1FFF 7800 - 0x1FFF 7A0F
528 byte
Option bytes
0x1FFF C000 - 0x1FFF C00F
16 byte
3.4
Read interface
3.4.1
Relation between CPU clock frequency and Flash memory read time
To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the supply voltage of the device.
•
When VOS[1:0] = 0x01, the maximum value of fHCLK = 64 MHz.
•
When VOS[1:0] = 0x10, the maximum value of fHCLK = 84 MHz.
•
When VOS[1:0] = 0x11, the maximum value of fHCLK = 100 MHz.
Table 6. Number of wait states according to CPU clock (HCLK) frequency
HCLK (MHz)
Wait states (WS)
Voltage range
Voltage range
Voltage range
Voltage range
2.7 V - 3.6 V
2.4 V - 2.7 V
2.1 V - 2.4 V
1.7 V - 2.1 V
0 WS (1 CPU cycle)
0 &lt; HCLK ≤ 25
0 &lt; HCLK ≤ 20
0 &lt; HCLK ≤ 18
0 &lt; HCLK ≤ 16
1 WS (2 CPU cycles)
25 &lt; HCLK ≤ 50
20 &lt; HCLK ≤ 40
18 &lt; HCLK ≤ 36
16 &lt;HCLK ≤ 32
2 WS (3 CPU cycles)
50 &lt; HCLK ≤ 75
40 &lt; HCLK ≤ 60
36 &lt; HCLK ≤ 54
32 &lt; HCLK ≤ 48
3 WS (4 CPU cycles)
75 &lt; HCLK ≤ 100
60 &lt; HCLK ≤ 80
54 &lt; HCLK ≤ 72
48 &lt; HCLK ≤ 64
4 WS (5 CPU cycles)
-
80 &lt; HCLK ≤ 100
72 &lt; HCLK ≤ 90
64 &lt; HCLK ≤ 80
5 WS (6 CPU cycles)
-
-
90 &lt; HCLK ≤ 100
80 &lt; HCLK ≤ 96
6 WS (7 CPU cycles)
-
-
-
96 &lt; HCLK ≤ 100
(LATENCY)
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of
wait states needed to access the Flash memory with the CPU frequency.
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Embedded Flash memory interface
Increasing the CPU frequency
1.
Program the new number of wait states to the LATENCY bits in the FLASH_ACR
register
2.
Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register
3.
Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
4.
If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
5.
Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Decreasing the CPU frequency
1.
Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
2.
If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
3.
Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register
4.
Program the new number of wait states to the LATENCY bits in FLASH_ACR
5.
Check that the new number of wait states is used to access the Flash memory by
reading the FLASH_ACR register
Note:
A change in CPU clock configuration or wait state (WS) configuration may not be effective
straight away. To make sure that the current CPU clock frequency is the one you have
configured, you can check the AHB prescaler factor and clock source status values. To
make sure that the number of WS you have programmed is effective, you can read the
FLASH_ACR register.
3.4.2
Adaptive real-time memory accelerator (ART Accelerator™)
The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard Arm&reg; Cortex&reg;-M4 with FPU processors. It balances the inherent
performance advantage of the Arm&reg; Cortex&reg;-M4 with FPU over Flash memory
technologies, which normally requires the processor to wait for the Flash memory at higher
operating frequencies.
To release the processor full performance, the accelerator implements an instruction
prefetch queue and branch cache which increases program execution speed from the 128bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the
ART accelerator is equivalent to 0 wait state program execution from Flash memory at a
CPU frequency up to 100 MHz.
Instruction prefetch
Each Flash memory read operation provides 128 bits from either four instructions of 32 bits
or 8 instructions of 16 bits according to the program launched. So, in case of sequential
code, at least four CPU cycles are needed to execute the previous read instruction line.
Prefetch on the I-Code bus can be used to read the next sequential instruction line from the
Flash memory while the current instruction line is being requested by the CPU. Prefetch is
enabled by setting the PRFTEN bit in the FLASH_ACR register. This feature is useful if at
least one wait state is needed to access the Flash memory.
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Figure 4 shows the execution of sequential 32-bit instructions with and without prefetch
when 3 WSs are needed to access the Flash memory.
Figure 4. Sequential 32-bit instruction execution
@
1
WAIT
F
1
@
2
D
1
F
2
E
1
D
2
E
2
@
3
F
3
D
3
E
3
@
4
F
4
D
4
Without prefetch
E
4
@
5
F
5
WAIT
@
6
ins 1
fetch
ins 2
fetch
ins 3
fetch
Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4
@
1
Wait data
@
2
F
1
ins 4
fetch
D
5
F
6
@
7
ins 5
fetch
E
5
D
6
F
7
@
8
ins 6
fetch
E
6
D
7
F
8
ins 7
fetch
ins 8
fetch
Read ins 5, 6, 7, 8 Gives ins 5, 6, 7, 8
D
1
F
2
E
1
D
2
E
2
@
3
F
3
@
4
D
3
F
4
E
3
D
4
@
5
F
5
@
With prefetch
E
4
D
5
F
6
@
7
E
5
D
6
F
7
@
8
E
6
D
7
F
8
Cortex-M4 pipeline
@
F
D
E
AHB protocol
ins 1 ins 2 ins 3 ins 4 ins 5 ins 6 ins 7 ins 8
fetch fetch fetch fetch fetch fetch fetch fetch
Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4
Gives ins 5, 6, 7, 8
Read ins 5, 6, 7, 8
@ : address requested
F: Fetch stage
D: Decode stage
E: Execute stage
Read ins 9, 10, ...
MS31831V1
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Embedded Flash memory interface
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
Instruction cache memory
To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction
cache memory. This feature can be enabled by setting the instruction cache enable (ICEN)
bit in the FLASH_ACR register. Each time a miss occurs (requested data not present in the
currently used instruction line, in the prefetched instruction line or in the instruction cache
memory), the line read is copied into the instruction cache memory. If some data contained
in the instruction cache memory are requested by the CPU, they are provided without
inserting any delay. Once all the instruction cache memory lines have been filled, the LRU
(least recently used) policy is used to determine the line to replace in the instruction memory
cache. This feature is particularly useful in case of code containing loops.
Data management
Literal pools are fetched from Flash memory through the D-Code bus during the execution
stage of the CPU pipeline. The CPU pipeline is consequently stalled until the requested
literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB
databus D-Code have priority over accesses through the AHB instruction bus I-Code.
If some literal pools are frequently used, the data cache memory can be enabled by setting
the data cache enable (DCEN) bit in the FLASH_ACR register. This feature works like the
instruction cache memory, but the retained data size is limited to 8 rows of 128 bits.
Note:
Data in user configuration sector are not cacheable.
3.5
Erase and program operations
For any Flash memory program operation (erase or program), the CPU clock frequency
(HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a
device reset occurs during a Flash memory operation.
Any attempt to read the Flash memory on STM32F4xx while it is being written or erased,
causes the bus to stall. Read operations are processed correctly once the program
operation has completed. This means that code or data fetches cannot be performed while
a write/erase operation is ongoing.
3.5.1
Unlocking the Flash control register
After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the
Flash memory against possible unwanted operations due, for example, to electric
disturbances. The following sequence is used to unlock this register:
1.
Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
2.
Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)
Any wrong sequence will return a bus error and lock up the FLASH_CR register until the
next reset.
The FLASH_CR register can be locked again by software by setting the LOCK bit in the
FLASH_CR register.
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Note:
The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR
register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall
until the BSY bit is cleared.
3.5.2
Program/erase parallelism
The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It
represents the number of bytes to be programmed each time a write operation occurs to the
Flash memory. PSIZE is limited by the supply voltage and by whether the external VPP
supply is used or not. It must therefore be correctly configured in the FLASH_CR register
before any programming/erasing operation.
A Flash memory erase operation can only be performed by sector or for the whole Flash
memory (mass erase). The erase time depends on PSIZE programmed value. For more
details on the erase time, refer to the electrical characteristics section of the device
datasheet.
Table 7 provides the correct PSIZE values.
Table 7. Maximum program/erase parallelism
Voltage range 2.7 - 3.6 V
with External VPP
Voltage range
2.7 - 3.6 V
Maximum
parallelism size
x64
x32
x16
x8
PSIZE(1:0)
11
10
01
00
Note:
Voltage range
2.4 - 2.7 V
Voltage range
2.1 - 2.4 V
Voltage range
1.7 V - 2.1 V
Any program or erase operation started with inconsistent program parallelism/voltage range
settings may lead to unpredicted results. Even if a subsequent read operation indicates that
the logical value was effectively written to the memory, this value may not be retained.
To use VPP, an external high-voltage supply (between 8 and 9 V) must be applied to the VPP
pad. The external supply must be able to sustain this voltage range even if the DC
consumption exceeds 10 mA. It is advised to limit the use of VPP to initial programming on
the factory line. The VPP supply must not be applied for more than an hour, otherwise the
Flash memory might be damaged.
3.5.3
Erase
The Flash memory erase operation can be performed at sector level or on the whole Flash
memory (Mass Erase). Mass Erase does not affect the OTP sector or the configuration
sector.
Sector Erase
To erase a sector, follow the procedure below:
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1.
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2.
Set the SER bit and select the sector out of the 16 sectors in the main memory block
you wish to erase (SNB) in the FLASH_CR register
3.
Set the STRT bit in the FLASH_CR register
4.
Wait for the BSY bit to be cleared
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Embedded Flash memory interface
Mass Erase
To perform Mass Erase, the following sequence is recommended:
Note:
1.
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2.
Set the MER bit in the FLASH_CR register
3.
Set the STRT bit in the FLASH_CR register
4.
Wait for the BSY bit to be cleared
If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.
If both MERx and SER bits are reset and the STRT bit is set, an unpredictable behavior may
occur without generating any error flag. This condition should be forbidden.
3.5.4
Programming
Standard programming
The Flash memory programming sequence is as follows:
1.
Check that no main Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2.
Set the PG bit in the FLASH_CR register
3.
Perform the data write operation(s) to the desired memory address (inside main
memory block or OTP area):
4.
Note:
–
Byte access in case of x8 parallelism
–
Half-word access in case of x16 parallelism
–
Word access in case of x32 parallelism
–
Double word access in case of x64 parallelism
Wait for the BSY bit to be cleared.
Successive write operations are possible without the need of an erase operation when
changing bits from ‘1’ to ‘0’. Writing ‘1’ requires a Flash memory erase operation.
If an erase and a program operation are requested simultaneously, the erase operation is
performed first.
Programming errors
It is not allowed to program data to the Flash memory that would cross the 128-bit row
boundary. In such a case, the write operation is not performed and a program alignment
error flag (PGAERR) is set in the FLASH_SR register.
The write access type (byte, half-word, word or double word) must correspond to the type of
parallelism chosen (x8, x16, x32 or x64). If not, the write operation is not performed and a
program parallelism error flag (PGPERR) is set in the FLASH_SR register.
If the standard programming sequence is not respected (for example, if there is an attempt
to write to a Flash memory address when the PG bit is not set), the operation is aborted and
a program sequence error flag (PGSERR) is set in the FLASH_SR register.
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Programming and caches
If a Flash memory write access concerns some data in the data cache, the Flash write
access modifies the data in the Flash memory and the data in the cache.
If an erase operation in Flash memory also concerns data in the data or instruction cache,
you have to make sure that these data are rewritten before they are accessed during code
execution. If this cannot be done safely, it is recommended to flush the caches by setting the
DCRST and ICRST bits in the FLASH_CR register.
Note:
The I/D cache should be flushed only when it is disabled (I/DCEN = 0).
3.5.5
Interrupts
Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables
interrupt generation when an erase or program operation ends, that is when the busy bit
(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this
case, the end of operation (EOP) bit in the FLASH_SR register is set.
If an error occurs during a program, an erase, or a read operation request, one of the
following error flags is set in the FLASH_SR register:
•
PGAERR, PGPERR, PGSERR (Program error flags)
•
WRPERR (Protection error flag)
In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_CR register, an
interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.
Note:
If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.
Table 8. Flash interrupt request
Interrupt event
Event flag
Enable control bit
EOP
EOPIE
Write protection error
WRPERR
ERRIE
Programming error
PGAERR, PGPERR, PGSERR
ERRIE
End of operation
3.6
Option bytes
3.6.1
Description of user option bytes
The option bytes are configured by the end user depending on the application requirements.
Table 9 shows the organization of these bytes inside the user configuration sector.
Table 9. Option byte organization
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Address
[63:16]
[15:0]
0x1FFF C000
Reserved
ROP &amp; user option bytes (RDP &amp; USER)
0x1FFF C008
Reserved
Write protection nWRP bits for sectors 0 to 15
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Embedded Flash memory interface
Table 10. Description of the option bytes
Option bytes (word, address 0x1FFF C000)
RDP: Read protection option byte.
The read protection is used to protect the software code stored in Flash memory.
Bits 15:8
0xAA: Level 0, no protection
0xCC: Level 2, chip protection (debug and boot from RAM features disabled)
Others: Level 1, read protection of memories (debug features limited)
USER: User option byte
This byte is used to configure the following features:
– Select the watchdog event: Hardware or software
– Reset event when entering the Stop mode
– Reset event when entering the Standby mode
Bit 7
nRST_STDBY
0: Reset generated when entering the Standby mode
1: No reset generated
Bit 6
nRST_STOP
0: Reset generated when entering the Stop mode
1: No reset generated
Bit 5
WDG_SW
0: Hardware independent watchdog
1: Software independent watchdog
Bit 4
0x1: Not used
Bits 3:2
BOR_LEV: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset.
They can be written to program a new BOR level value into Flash memory.
00: BOR Level 3 (VBOR3), brownout threshold level 3
01: BOR Level 2 (VBOR2), brownout threshold level 2
10: BOR Level 1 (VBOR1), brownout threshold level 1
11: BOR off, POR/PDR reset threshold level is applied
Note: For full details on BOR characteristics, refer to the “Electrical characteristics”
section of the product datasheet.
Bits 1:0
0x1: Not used
Option bytes (word, address 0x1FFF C008)
Bit 15
SPRMOD: Selection of Protection Mode of nWPRi bits
0: nWPRi bits used for sector i write protection (Default)
1: nWPRi bits used for sector i PCROP protection (Sector)
nWRP: Flash memory write protection option bytes
sector 0 to 15 can be write protected
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Table 10. Description of the option bytes
3.6.2
Bit 14
nWRP15_14: Non Write Protection of sector 15 and 14
If SPRMOD is reset (default value):
0: Write protection active on sector 15 and 14.
1: Write protection not active on sector 15 and 14.
If SPRMOD is set (active):
0: PCROP protection not active on sector 15 and 14.
1: PCROP protection active on sector 15 and 14.
Bits 13:0
nWRPi
If SPRMOD is reset (default value):
0: Write protection active on sector i.
1: Write protection not active on sector i.
If SPRMOD is set (active):
0: PCROP protection not active on sector i.
1: PCROP protection active on sector i.
Programming user option bytes
To run any operation on this sector, the option lock bit (OPTLOCK) in the Flash option
control register (FLASH_OPTCR) must be cleared. To be allowed to clear this bit, you have
to perform the following sequence:
1.
Write OPTKEY1 = 0x0819 2A3B in the Flash option key register (FLASH_OPTKEYR)
2.
Write OPTKEY2 = 0x4C5D 6E7F in the Flash option key register (FLASH_OPTKEYR)
The user option bytes can be protected against unwanted erase/program operations by
setting the OPTLOCK bit by software.
Modifying user option bytes
To modify the user option value, follow the sequence below:
1.
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2.
Write the desired option value in the FLASH_OPTCR register.
3.
Set the option start bit (OPTSTRT) in the FLASH_OPTCR register
4.
Wait for the BSY bit to be cleared.
Note:
The value of an option is automatically modified by first erasing the user configuration sector
and then programming all the option bytes with the values contained in the FLASH_OPTCR
register.
3.6.3
Read protection (RDP)
The user area in the Flash memory can be protected against read operations by an
entrusted code. Three read protection levels are defined:
•
Level 0: no read protection
When the read protection level is set to Level 0 by writing 0xAA into the read protection
option byte (RDP), all read/write operations (if no write protection is set) from/to the
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Flash memory are possible in all boot configurations (Flash user boot, debug or boot
from RAM).
•
Level 1: read protection enabled
It is the default read protection level after option byte erase. The read protection Level
1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and
Level 2, respectively) into the RDP option byte. When the read protection Level 1 is set:
–
No access (read, erase, program) to Flash memory can be performed while the
debug feature is connected or while booting from RAM or system memory
bootloader. A bus error is generated in case of read request.
–
When booting from Flash memory, accesses (read, erase, program) to Flash
memory from user code are allowed.
When Level 1 is active, programming the protection option byte (RDP) to Level 0
causes the Flash memory to be mass-erased. As a result the user code area is cleared
before the read protection is removed. The mass erase only erases the user code area.
The other option bytes including write protections remain unchanged from before the
mass-erase operation. The OTP area is not affected by mass erase and remains
unchanged. Mass erase is performed only when Level 1 is active and Level 0
requested. When the protection level is increased (0-&gt;1, 1-&gt;2, 0-&gt;2) there is no mass
erase.
•
Level 2: debug/chip read protection disabled
The read protection Level 2 is activated by writing 0xCC to the RDP option byte. When
the read protection Level 2 is set:
–
All protections provided by Level 1 are active.
–
Booting from RAM or system memory bootloader is no more allowed.
–
JTAG, SWV (single-wire viewer), ETM, and boundary scan are disabled.
–
User option bytes can no longer be changed.
–
When booting from Flash memory, accesses (read, erase and program) to Flash
memory from user code are allowed.
Memory read protection Level 2 is an irreversible operation. When Level 2 is activated,
the level of protection cannot be decreased to Level 0 or Level 1.
Note:
The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a
consequence, boundary scan cannot be performed. STMicroelectronics is not able to
perform analysis on defective parts on which the Level 2 protection has been set.
Note:
If the read protection is set while the debugger is still connected (or had been connected
since the last power on) through JTAG/SWD, apply a POR (power-on reset) instead of a
system reset. If the read protection is programmed through software, do not set the
OBL_LAUNCH bit (FLASH_CR register) but perform a POR to reload the option byte. This
can be done with a transition Standby (or Shutdown) mode followed by a wakeup.
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--
Memory area
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Table 11. Access versus read protection level
Protection
Level
Debug features, Boot from RAM or
from System memory bootloader
Read
Main Flash Memory
Option Bytes
OTP
Level 1
Write
Erase
Booting from Flash memory
Read
Write
NO(1)
NO
Erase
YES
Level 2
NO
YES
Level 1
YES
YES
Level 2
NO
NO
Level 1
NO
NA
YES
NA
Level 2
NO
NA
YES
NA
1. The main Flash memory is only erased when the RDP changes from level 1 to 0. The OTP area remains unchanged.
Figure 5 shows how to go from one RDP level to another.
Figure 5. RDP levels
RDP /= AAh &amp; /= CCh
Others options modified
Level 1
RDP /= AAh
RDP /= CCh
default
Write options
including
RDP = CCh
Write optionsincluding
RDP /= CCh &amp; /= AAh
Write options
including
RDP = AAh
L ev e l 2
L ev e l 0
RDP = CCh
R D P = AA h
Write options
including
RDP = CCh
Options write (RDP level increase) includes
- Options erase
- New options program
Options write (RDP level decrease) includes
- Mass erase
- Options erase
- New options program
RDP = AAh
Others option(s) modified
Options write (RDP level identical) includes
- Options erase
- New options program
ai16045
3.6.4
Write protections
Up to 16 user sectors in Flash memory can be protected against unwanted write operations
due to loss of program counter contexts. When the non-write protection nWRPi bit
(0 ≤ i ≤ 14) in the FLASH_OPTCR registers is low, the corresponding sector cannot be
erased or programmed. Consequently, a mass erase cannot be performed if one of the
sectors is write-protected.
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If an erase/program operation to a write-protected part of the Flash memory is attempted
(sector protected by write protection bit, OTP part locked or part of the Flash memory that
can never be written like the ICP), the write protection error flag (WRPERR) is set in the
FLASH_SR register.
Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory sector i if the CPU debug features are connected (JTAG or
single wire) or boot code is being executed from RAM, even if nWRPi = 1.
Sector 14 and 15 are linked together and cannot be write-protected separately.
Write protection error flag
If an erase/program operation to a write protected area of the Flash memory is performed,
the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.
If an erase operation is requested, the WRPERR bit is set when:
•
Mass, sector erase are configured (MER or MER/MER1 and SER = 1)
•
A sector erase is requested and the Sector Number SNB field is not valid
•
A mass erase is requested while at least one of the user sector is write protected by
option bit (MER or MER/MER1 = 1 and nWRPi = 0 with 0 ≤ i ≤ 14 bits in the
FLASH_OPTCRx register
•
A sector erase is requested on a write protected sector. (SER = 1, SNB = i and
nWRPi = 0 with 0 ≤ i ≤ 14 bits in the FLASH_OPTCRx register)
•
The Flash memory is readout protected and an intrusion is detected.
If a program operation is requested, the WRPERR bit is set when:
3.6.5
•
A write operation is performed on system memory or on the reserved part of the user
specific sector.
•
A write operation is performed to the user configuration sector
•
A write operation is performed on a sector write protected by option bit.
•
A write operation is requested on an OTP area which is already locked
•
The Flash memory is read protected and an intrusion is detected.
Proprietary code readout protection (PCROP)
Flash memory user sectors (0 to 15) can be protected against D-bus read accesses by
using the proprietary readout protection (PCROP).
The PCROP protection is selected as follows, through the SPRMOD option bit in the
FLASH_CR register:
•
SPRMOD = 0: nWRPi control the write protection of respective user sectors
•
SPRMOD = 1: nWRPi control the read and write protection (PCROP) of respective
user sectors.
When a sector is readout protected (PCROP mode activated), it can only be accessed for
code fetch through ICODE Bus on Flash interface:
•
Any read access performed through the D-bus triggers a RDERR flag error.
•
Any program/erase operation on a PCROPed sector triggers a WRPERR flag error.
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Figure 6. PCROP levels
Write options
SPMOD = active
and valid nWRPi*
Level 1
RDP /= 0xAA
RDP /= 0xCC
default
Write options
SPMOD = active
and valid nWRPi*
Write options
SPMOD = active
and valid nWRPi*
No restriction on
Write options
Level 2
Level 0
RDP = 0xCC
RDP = 0xAA
Write options
SPMOD = active
and valid nWRPi*
User option sector erase
Program new options
Write options
SPMOD = active
and valid nWRPi*
Global mass erase
User option section erase
Program new options
* Valid nWRPi means that none of the nWRP bits set can be reset (transition from 1 to 0)
MS30467V1
The deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can
only occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not
respected, the user option byte modification is canceled and the write error WRPERR flag is
set. The modification of the users option bytes (BOR_LEV, RST_STDBY, ..) is allowed since
none of the active nWRPi bits is reset and SPRMOD is kept active.
Note:
80/1321
The active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
RM0430 Rev 9
RM0430
3.7
Embedded Flash memory interface
One-time programmable bytes
Table 12 shows the organization of the one-time programmable (OTP) part of the OTP area.
Table 12. OTP area organization
Block
0
1
[128:96]
[95:64]
[63:32]
[31:0]
Address byte 0
OTP0
OTP0
OTP0
OTP0
0x1FFF 7800
OTP0
OTP0
OTP0
OTP0
0x1FFF 7810
OTP1
OTP1
OTP1
OTP1
0x1FFF 7820
OTP1
OTP1
OTP1
OTP1
0x1FFF 7830
.
.
.
15
Lock block
.
.
.
.
.
.
OTP15
OTP15
OTP15
OTP15
0x1FFF 79E0
OTP15
OTP15
OTP15
OTP15
0x1FFF 79F0
LOCKB15 ...
LOCKB12
LOCKB11 ...
LOCKB8
LOCKB7 ...
LOCKB4
LOCKB3 ...
LOCKB0
0x1FFF 7A00
The OTP area is divided into 16 OTP data blocks of 32 bytes and one lock OTP block of 16
bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes
LOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP
data block can be programmed until the value 0x00 is programmed in the corresponding
OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP
bytes might not be taken into account correctly.
RM0430 Rev 9
81/1321
89
Embedded Flash memory interface
RM0430
3.8
Flash interface registers
3.8.1
Flash access control register (FLASH_ACR)
The Flash access control register is used to enable/disable the acceleration features and
control the Flash memory access time according to CPU frequency.
Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
12
11
3
2
1
0
15
14
13
Res.
Res.
Res.
DCRST ICRST
rw
w
10
9
8
7
6
5
4
DCEN
ICEN
PRFTEN
Res.
Res.
Res.
Res.
rw
rw
rw
LATENCY
rw
rw
rw
rw
Bits 31:13 Reserved, must be kept cleared.
Bit 12 DCRST: Data cache reset
0: Data cache is not reset
1: Data cache is reset
This bit can be written only when the D cache is disabled.
Bit 11 ICRST: Instruction cache reset
0: Instruction cache is not reset
1: Instruction cache is reset
This bit can be written only when the I cache is disabled.
Bit 10 DCEN: Data cache enable
0: Data cache is disabled
1: Data cache is enabled
Bit 9 ICEN: Instruction cache enable
0: Instruction cache is disabled
1: Instruction cache is enabled
Bit 8 PRFTEN: Prefetch enable
0: Prefetch is disabled
1: Prefetch is enabled
Bits 7:4 Reserved, must be kept cleared.
Bits 3:0 LATENCY: Latency
These bits represent the ratio of the CPU clock period to the Flash memory access time.
0000: Zero wait state
0001: One wait state
0010: Two wait states
1110: Fourteen wait states
1111: Fifteen wait states
82/1321
RM0430 Rev 9
RM0430
Embedded Flash memory interface
3.8.2
Flash key register (FLASH_KEYR)
The Flash key register is used to allow access to the Flash control register and so, to allow
program and erase operations.
Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait state, word access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEY[31:16]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
KEY[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 FKEYR: FPEC key
The following values must be programmed consecutively to unlock the FLASH_CR register
and allow programming/erasing it:
a) KEY1 = 0x45670123
b) KEY2 = 0xCDEF89AB
3.8.3
Flash option key register (FLASH_OPTKEYR)
The Flash option key register is used to allow program and erase operations in the user
configuration sector.
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OPTKEYR[31:16
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OPTKEYR[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 OPTKEYR: Option byte key
The following values must be programmed consecutively to unlock the FLASH_OPTCR
register and allow programming it:
a) OPTKEY1 = 0x08192A3B
b) OPTKEY2 = 0x4C5D6E7F
RM0430 Rev 9
83/1321
89
Embedded Flash memory interface
3.8.4
RM0430
Flash status register (FLASH_SR)
The Flash status register gives information on ongoing program and erase operations.
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSY
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OPERR
EOP
rc_w1
rc_w1
r
RDERR PGSERR PGPERR PGAERR WRPERR
rw
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:17 Reserved, must be kept cleared.
Bit 16 BSY: Busy
This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a
Flash memory operation and cleared when the operation finishes or an error occurs.
0: no Flash memory operation ongoing
1: Flash memory operation ongoing
Bits 15:9 Reserved, must be kept cleared.
Bit 8 RDERR: Read Protection Error (PCROP)
Set by hardware when an address to be read through the Dbus belongs to a read protected
part of the flash.
Reset by writing 1.
Bit 7 PGSERR: Programming sequence error
Set by hardware when a write access to the Flash memory is performed by the code while
the control register has not been correctly configured.
Cleared by writing 1.
Bit 6 PGPERR: Programming parallelism error
Set by hardware when the size of the access (byte, half-word, word, double word) during the
program sequence does not correspond to the parallelism configuration PSIZE (x8, x16,
x32, x64).
Cleared by writing 1.
Bit 5 PGAERR: Programming alignment error
Set by hardware when the data to program cannot be contained in the same 128-bit Flash
memory row.
Cleared by writing 1.
Bit 4 WRPERR: Write protection error
Set by hardware when an address to be erased/programmed belongs to a write-protected
part of the Flash memory.
Cleared by writing 1.
84/1321
RM0430 Rev 9
RM0430
Embedded Flash memory interface
Bits 3:2 Reserved, must be kept cleared.
Bit 1 OPERR: Operation error
Set by hardware when a flash operation (programming / erase /read) request is detected and
can not be run because of parallelism, alignment, or write protection error. This bit is set only
if error interrupts are enabled (ERRIE = 1).
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operations (program/erase) has/have
completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE =
1).
Cleared by writing a 1.
3.8.5
Flash control register (FLASH_CR)
The Flash control register is used to configure and start Flash memory operations.
Address offset: 0x10
Reset value: 0x8000 0000
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LOCK
Res.
Res.
Res.
Res.
Res.
ERRIE
EOPIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
STRT
rw
rw
8
rs
15
14
13
12
11
10
9
Res.
Res.
Res.
Res.
Res.
Res.
PSIZE[1:0]
rw
rs
7
6
Res.
rw
5
4
3
SNB[3:0]
rw
rw
rw
rw
2
1
0
MER
SER
PG
rw
rw
rw
Bit 31 LOCK: Lock
Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is
cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
Bits 30:26 Reserved, must be kept cleared.
Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is
set to 1.
0: Error interrupt generation disabled
1: Error interrupt generation enabled
Bit 24 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes
to 1.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bits 23:17 Reserved, must be kept cleared.
Bit 16 STRT: Start
This bit triggers an erase operation when set. It is set only by software and cleared when the
BSY bit is cleared.
Bits 15:10 Reserved, must be kept cleared.
RM0430 Rev 9
85/1321
89
Embedded Flash memory interface
RM0430
Bits 9:8 PSIZE: Program size
These bits select the program parallelism.
00 program x8
01 program x16
10 program x32
11 program x64
Bit 7 Reserved, must be kept cleared.
Bits 6:3 SNB: Sector number
These bits select the sector to erase.
0000 sector 0
0001 sector 1
...
1010 sector 10
1011 sector 11
1100 sector 12
1101 sector 13
1110 sector 14
1111 sector 15
Bit 2 MER: Mass Erase
Erase activated for all user sectors.
Bit 1 SER: Sector Erase
Sector Erase activated.
Bit 0 PG: Programming
Flash programming activated.
3.8.6
Flash option control register (FLASH_OPTCR)
The FLASH_OPTCR register is used to modify the user option bytes.
Address offset: 0x14
Reset value: 0x7FFF AAED
The option bits are loaded with values from Flash memory at reset release.
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31
30
29
28
27
26
25
24
SPR
MOD
nWRP
14_15
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
86/1321
rw
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
4
3
2
nWRP[13:0]
RDP[7:0]
rw
23
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
nRST_
STDBY
nRST_
STOP
WDG_
SW
rw
rw
rw
RM0430 Rev 9
Res.
1
0
BOR_LEV
OPT
STRT
OPT
LOCK
rw
rs
rs
rw
RM0430
Embedded Flash memory interface
Bit 31 SPRMOD: Selection of Protection Mode of nWPRi bits
0: PCROP disabled, nWPRi bits used for Write Protection on sector i
1: PCROP enabled, nWPRi bits used for PCROP Protection on sector i
Bit 30 nWRP14_15: Not write protect
This bit contains the value of the write-protection option byte of sectors 14 and 15. They can
be written to program a new write protect value into Flash memory. Sectors 14 and 15 are
linked together and cannot be programmed separately
0: Write protection active on sectors 14 and 15
1: Write protection not active on sectors 14 and 15
These bits contain the value of the write-protection and read-protection (PCROP) option
bytes for sectors 14 and 15 after reset. They can be written to program a new write-protect or
PCROP value into Flash memory.
If SPRMOD is reset:
0: Write protection active on sectors 14 and 15
1: Write protection not active on sectors 14 and 15
If SPRMOD is set:
0: PCROP protection not active on sectors 14 and 15
1: PCROP protection active on sectors 14 and 15
Bits 29:16 nWRP[13:0]: Not write protect
These bits contain the value of the write-protection option bytes of sectors after reset. They
can be written to program a new write protect value into Flash memory.
0: Write protection active on selected sector
1: Write protection not active on selected sector
These bits contain the value of the write-protection and read-protection (PCROP) option
bytes for sectors 0 to 13 after reset. They can be written to program a new write-protect or
PCROP value into Flash memory.
If SPRMOD is reset:
0: Write protection active on sector i
1: Write protection not active on sector i
If SPRMOD is set:
0: PCROP protection not active on sector i
1: PCROP protection active on sector i
Bits 15:8 RDP: Read protect
These bits contain the value of the read-protection option level after reset. They can be
written to program a new read protection value into Flash memory.
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, read protection of memories active
Bits 7:5 USER: User option bytes
These bits contain the value of the user option byte after reset. They can be written to
program a new user option byte value into Flash memory.
Bit 7: nRST_STDBY
Bit 6: nRST_STOP
Bit 5: WDG_SW
Note: When changing the WDG mode from hardware to software or from software to
hardware, a system reset is required to make the change effective.
Bit 4 Reserved, must be kept cleared. Always read as “0”.
RM0430 Rev 9
87/1321
89
Embedded Flash memory interface
RM0430
Bits 3:2 BOR_LEV: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset. They can be
written to program a new BOR level. By default, BOR is off. When the supply voltage (VDD)
drops below the selected BOR level, a device reset is generated.
00: BOR Level 3 (VBOR3), brownout threshold level 3
01: BOR Level 2 (VBOR2), brownout threshold level 2
10: BOR Level 1 (VBOR1), brownout threshold level 1
11: BOR off, POR/PDR reset threshold level is applied
Note: For full details about BOR characteristics, refer to the “Electrical characteristics” section
in the device datasheet.
Bit 1 OPTSTRT: Option start
This bit triggers a user option operation when set. It is set only by software and cleared when
the BSY bit is cleared.
Bit 0 OPTLOCK: Option lock
Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked.
This bit is cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
88/1321
RM0430 Rev 9
RM0430
3.8.7
Embedded Flash memory interface
Flash interface register map
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
ICEN
PRFTEN
Res.
Res.
DCEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLASH_SR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RDERR
PGSERR
PGPERR
PGAERR
WRPERR
Res.
OPTKEYR[15:0]
Res.
OPTKEYR[31:16]
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Res.
PSIZE[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EOPIE
Res.
Res.
ERRIE
Res.
Res.
nWRP[13:0]
0
0
1
0
RDP[7:0]
1
1
1
1
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
BOR_LEV
1
0
WDG_SW
Res.
0
0
nRST_STDB
Reset value
0
SNB[3:0]
nRST_STOP
FLASH_OPTCR
Res.
1
Res.
Reset value
SPRMOD
FLASH_CR
LOCK
Res.
0
EOP
FLASH_
OPTKEYR
0
KEY[15:0]
PG
0
0
OPTLOCK
0
0
Res.
0
0
OPERR
0
0
SER
0
nWRP14_15
0x14
0
KEY[31:16]
Reset value
0x10
0
Res.
0x0C
0
Res.
0x08
0
MER
Reset value
0
LATENCY
OPTSTRT
FLASH_KEYR
STRT
Res.
0x04
ICRST
Res.
Reset value
DCRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_ACR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
Register
Res.
Offset
Res.
Table 13. Flash register map and reset values
1
Refer to Section 2.2 on page 57 for the register boundary addresses.
RM0430 Rev 9
89/1321
89
CRC calculation unit
RM0430
4
CRC calculation unit
4.1
CRC introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a way of verifying
the flash memory integrity. The CRC calculation unit helps compute a signature of the
software during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
4.2
CRC main features
•
Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
–
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
•
Single input/output 32-bit data register
•
CRC computation done in four AHB clock cycles (HCLK)
•
General-purpose 8-bit register (can be used for temporary storage)
The block diagram is shown in Figure 7.
Figure 7. CRC calculation unit block diagram
AHB bus
32-bit (read access)
Data register (output)
CRC computation (polynomial: 0x4C11DB7)
32-bit (write access)
Data register (input)
ai14968
4.3
CRC functional description
The CRC calculation unit mainly consists of a single 32-bit data register, which:
90/1321
•
is used as an input register to enter new data in the CRC calculator (when writing into
the register)
•
holds the result of the previous CRC calculation (when reading the register)
RM0430 Rev 9
RM0430
CRC calculation unit
Each write operation into the data register creates a combination of the previous CRC value
and the new one (CRC computation is done on the whole 32-bit data word, and not byte per
byte).
The write operation is stalled until the end of the CRC computation, thus allowing back-toback write accesses or consecutive write and read accesses.
The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the
CRC_CR register. This operation does not affect the contents of the CRC_IDR register.
4.4
CRC registers
The CRC calculation unit contains two data registers and a control register.The peripheral
The CRC registers have to be accessed by words (32 bits).
4.4.1
Data register (CRC_DR)
Address offset: 0x00
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DR [31:16]
DR [15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 Data register bits
Used as an input register when writing new data into the CRC calculator.
Holds the previous CRC calculation result when it is read.
RM0430 Rev 9
91/1321
93
CRC calculation unit
4.4.2
RM0430
Independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
IDR[7:0]
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 General-purpose 8-bit data register bits
Can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register.
4.4.3
Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RESET
w
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 RESET bit
Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF.
This bit can only be set, it is automatically cleared by hardware.
92/1321
RM0430 Rev 9
RM0430
4.4.4
CRC calculation unit
CRC register map
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Independent data register
Reset value
Res.
RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRC_CR
Res.
0x08
0x0000
Res.
Reset value
Res.
CRC_IDR
Res.
0xFFFF FFFF
Res.
Reset value
Res.
Data register
Res.
0x04
CRC_DR
Res.
0x00
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 14. CRC calculation unit register map and reset values
0
Refer to Section 2.2 on page 57 for the register boundary addresses.
RM0430 Rev 9
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5
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5.1
Power supplies
There are two main power supply schemes:
•
VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal regulator disabled,
provided externally through VDD pins. Requires the use of an external power supply
supervisor connected to the VDD and PDR_ON pins.
•
VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
•
VDD_USB = 3.0 to 3.6 V
VDD_USB is a dedicated independent USB power supply for full speed transceivers.
Note:
VDD_USB value does not dependent on VDD and VDDA. However, VDD_USB must be the last
supply to be delivered to the device and the first to be switched off. When the three power
supplies are shut down, if VDD_USB remains active for a short period of time and VDDA/VDDIO
fall below the functional range, the device is not be damaged.
The device is still functional when VDD_USB is switched off.
The real-time clock (RTC), and the RTC backup registers can be powered from the VBAT
voltage when the main VDD supply is powered off.
Note:
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Depending on the operating power supply range, some peripheral may be used with limited
functionality and performance. For more details refer to section &quot;General operating
conditions&quot; in the datasheet.
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Power controller (PWR)
Figure 8. Power supply overview
VBAT
VBAT =
1.65 to 3.6V
GPIOs
IN
VCAP_1
VCAP_2
2 &times; 2.2 μF
VDD
1/2/...11/12
11 &times; 100 nF
+ 1 &times; 4.7 μF
VSS
1/2/...11/12
VDD_USB
BYPASS_REG
PDR_ON
VDD
Voltage
regulator
Flash memory
OTG
FS
PHY
Reset
controller
VDDA
VREF
100 nF
+ 1 μF
IO
Logic
Kernel logic
(CPU, digital
&amp; RAM)
VDD_USB
100 nF
+ 1 μF
Level shifter
OUT
VDD
Backup circuitry
(OSC32K,RTC,
Wakeup logic
Backup registers)
Power
switch
100 nF
+ 1 μF
VREF+
VREF-
ADC
Analog:
RCs,
PLL,..
VSSA
MSv39022V1
1. VDDA and VSSA must be connected to VDD and VSS, respectively.
5.1.1
Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC has an independent power supply which can be
separately filtered and shielded from noise on the PCB.
•
The ADC voltage supply input is available on a separate VDDA pin.
•
An isolated supply ground connection is provided on pin VSSA.
To ensure a better accuracy of low voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF. The voltage on VREF ranges from 1.7 V to VDDA.
5.1.2
Battery backup domain
Backup domain description
To retain the content of the RTC backup registers and supply the RTC when VDD is turned
off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by
another source.
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To allow the RTC to operate even when the main digital supply (VDD) is turned off, the VBAT
pin powers the following blocks:
•
The RTC
•
The LSE oscillator
•
PC13 to PC15 I/Os
The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset
block.
Warning:
During tRSTTEMPO (temporization at VDD startup) or after a PDR
is detected, the power switch between VBAT and VDD remains
connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO)
and VDD &gt; VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect VBAT to VDD
supply and add a 100 nF ceramic decoupling capacitor on VBAT pin.
When the backup domain is supplied by VDD (analog switch connected to VDD), the
following functions are available:
Note:
•
PC14 and PC15 can be used as either GPIO or LSE pins
•
PC13 can be used as a GPIO or additional functions can be configured (refer to
Table 27: RTC additional functions for more details about this pin configuration)
Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
PC13 to PC15 GPIOs in output mode is restricted: the speed has to be limited to 2 MHz with
a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive
an LED).
When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the following functions are available:
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•
PC14 and PC15 can be used as LSE pins only
•
PC13 can be used as the RTC additional function pin (refer to Table 27: RTC additional
functions for more details about this pin configuration)
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Power controller (PWR)
Backup domain access
After reset, the backup domain (RTC registers, and RTC backup register) is protected
against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
•
Access to the RTC and RTC backup registers
1.
Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see Section 6.3.14: RCC AHB3 peripheral clock enable register
(RCC_AHB3ENR))
2.
Set the DBP bit in the Section 5.4.1 to enable access to the backup domain
3.
Select the RTC clock source: see Section 6.2.8: RTC/AWU clock
4.
Enable the RTC clock by programming the RTCEN [15] bit in the Section 6.3.23: RCC
Backup domain control register (RCC_BDCR)
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes)
which are reset when a tamper detection event occurs. For more details refer to Section 25:
Real-time clock (RTC).
5.1.3
Voltage regulator
An embedded linear voltage regulator supplies all the digital circuitries except for the backup
domain and the Standby circuitry. The regulator output voltage is around 1.2 V.
This voltage regulator requires one or two external capacitors to be connected to one or two
dedicated pins, VCAP_1 and for some packages VCAP_2. Specific pins must be connected
either to VSS or VDD to activate or deactivate the voltage regulator. These pins depend on
the package.
When activated by software, the voltage regulator is always enabled after Reset. It works in
three different modes depending on the application modes.
•
In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories
and digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can
be scaled by software to different voltage values, Scale 1, scale 2, or scale 3, that can
be configured through the VOS[1:0] bits of the PWR_CR register. After reset the VOS
register is set to scale 2. When the PLL is OFF, the voltage regulator is set to scale 3
independently of the VOS register content. The VOS register content is only taken into
account once the PLL is activated and the HSI or HSE is selected as clock source.
The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency.
•
In Stop mode, the main regulator or the low-power regulator supplies low power to the
1.2 V domain, thus preserving the content of registers and internal SRAM. The voltage
regulator can be put either in main regulator mode (MR) or in low-power mode (LPR).
The programmed voltage scale remains the same during Stop mode:
Voltage scale 3 is automatically selected when the microcontroller enters Stop mode
(see Section 5.4.1: PWR power control register (PWR_CR)).
•
In Standby mode, the regulator is powered down. The content of the registers and
SRAM are lost except for the Standby circuitry and the backup domain.
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Note:
For more details, refer to the voltage regulator section in the STM32F413/423 datasheet.
5.2
Power supply supervisor
5.2.1
Power-on reset (POR)/power-down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting
from 1.8 V.
To use the device below 1.8 V, the internal power supervisor must be switched off using the
PDR_ON pin (please refer to section Power supply supervisor of the STM32F413/423
datasheet). The device remains in Reset mode when VDD/VDDA is below a specified
threshold, VPOR/PDR, without the need for an external reset circuit. For more details
concerning the power on/power-down reset threshold, refer to the electrical characteristics
of the datasheet.
Figure 9. Power-on reset/power-down reset waveform
VDD/VDDA
PDR
40 mV
hysteresis
PDR
Temporization
tRSTTEMPO
Reset
MS30431V1
5.2.2
Brownout reset (BOR)
During power on, the Brownout reset (BOR) keeps the device under reset until the supply
voltage reaches the specified VBOR threshold.
VBOR is configured through device option bytes. By default, BOR is off. 3 programmable
VBOR threshold levels can be selected:
Note:
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•
BOR Level 3 (VBOR3). Brownout threshold level 3.
•
BOR Level 2 (VBOR2). Brownout threshold level 2.
•
BOR Level 1 (VBOR1). Brownout threshold level 1.
For full details about BOR characteristics, refer to the &quot;Electrical characteristics&quot; section in
the device datasheet.
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Power controller (PWR)
When the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is
generated.
The BOR can be disabled by programming the device option bytes. In this case, the
power-on and power-down is then monitored by the POR/ PDR or by an external power
supervisor if the PDR is switched off through the PDR_ON pin (see Section 5.2.1: Power-on
reset (POR)/power-down reset (PDR)).
The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the
supply voltage).
Figure 10. BOR thresholds
VDD/VDDA
BOR threshold
100 mV
hysteresis
Reset
MS30433V1
5.2.3
Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the PWR power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the PWR power control/status register (PWR_CSR), to indicate
if VDD is higher or lower than the PVD threshold. This event is internally connected to the
EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The
rising/falling edge sensitivity of the EXTI line16 should be configured according to PVD
output behavior. For example, if the EXTI line 16 is configured to rising edge sensitivity, the
interrupt will be generated when VDD drops below the PVD threshold. As an example the
service routine could perform emergency shutdown tasks.
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Figure 11. PVD thresholds
VDD
PVD threshold
100 mV
hysteresis
PVD output
MS30432V2
5.3
Low-power modes
By default, the microcontroller is in Run mode after a system or a power-on reset. In Run
mode the CPU is clocked by HCLK and the program code is executed. Several low-power
modes are available to save power when the CPU does not need to be kept running, for
example when waiting for an external event. It is up to the user to select the mode that gives
the best compromise between low-power consumption, short startup time and available
wakeup sources.
The devices feature four low-power modes:
•
Sleep mode (Cortex&reg;-M4 with FPU core stopped, peripherals kept running)
•
Stop mode (all clocks are stopped)
•
Standby mode (1.2 V domain powered off)
•
Batch acquisition mode (BAM): the devices are in Sleep mode, the Flash memory is off,
needed peripheral are kept running, data transfer are still possible through DMA.
In addition, the power consumption in Run mode can be reduce by one of the following
means:
•
Slowing down the system clocks
•
Gating the clocks to the APBx and AHBx peripherals when they are unused.
Entering low-power mode
Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or
WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex&reg;-M4 with
FPU System Control register is set on Return from ISR.
Entering Low-power mode through WFI or WFE will be executed only if no interrupt is
pending or no event is pending.
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Exiting low-power mode
The MCU exits from Sleep and Stop modes low-power mode depending on the way the lowpower mode was entered:
•
If the WFI instruction or Return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
•
If the WFE instruction is used to enter the low-power mode, the MCU exits the lowpower mode as soon as an event occurs. The wakeup event can be generated either
by:
–
NVIC IRQ interrupt:
When SEVONPEND = 0 in the Cortex&reg;-M4 with FPU System Control register: by
enabling an interrupt in the peripheral control register and in the NVIC. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC
peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register)
have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and
interrupt the MCU.
When SEVONPEND = 1 in the Cortex&reg;-M4 with FPU System Control register: by
enabling an interrupt in the peripheral control register and optionally in the NVIC.
When the MCU resumes from WFE, the peripheral interrupt pending bit and when
enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear
pending register) have to be cleared. All NVIC interrupts will wakeup the MCU,
even the disabled ones.Only enabled NVIC interrupts with sufficient priority will
wakeup and interrupt the MCU.
–
Event
This is done by configuring a EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bits corresponding to the event
line is not set. It may be necessary to clear the interrupt flag in the peripheral.
The MCU exits from Standby low-power mode through an external reset (NRST pin), an
IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see
Figure 254: RTC block diagram).
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).
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Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
Table 15. Low-power mode summary
Mode name
Entry
Wakeup
Sleep and
BAM(1)
(Sleep now or
Sleep-onexit)
WFI or Return
from ISR
Any interrupt
WFE
Wakeup event
Stop
Standby
Effect on 1.2 V
domain clocks
Effect on
VDD
domain
clocks
Voltage regulator
CPU CLK OFF
no effect on other
clocks or analog
clock sources
None
ON
SLEEPDEEP bit Any EXTI line (configured
+ WFI, Return
in the EXTI registers,
from ISR or WFE internal and external lines)
PDDS bit +
SLEEPDEEP bit
+ WFI, Return
from ISR or WFE
WKUP pin rising edge,
RTC alarm (Alarm A or
Alarm B), RTC Wakeup
event, RTC tamper
events, RTC time stamp
event, external reset in
NRST pin, IWDG reset
All 1.2 V domain
clocks OFF
HSI and
HSE
oscillator
s OFF
Main regulator or
Low-Power
regulator (depends
on PWR power
control register
(PWR_CR)
OFF
1. Refer to Section 5.3.4: Batch acquisition mode for specific BAM entry and exit requirements.
5.3.1
Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 6.3.3: RCC clock configuration register (RCC_CFGR).
5.3.2
Peripheral clock gating
In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be
stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB1 peripheral clock enable register
(RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR) (see
Section 6.3.11: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR),
Section 6.3.12: RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) for
STM32F413xx and Section 6.3.14: RCC AHB3 peripheral clock enable register
(RCC_AHB3ENR)).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.
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5.3.3
Power controller (PWR)
Sleep mode
Entering Sleep mode
The Sleep mode is entered according to Entering low-power mode, when the SLEEPDEEP
bit in the Cortex&reg;-M4 with FPU System Control register is cleared.
Refer to Table 16 and Table 17 for details on how to enter Sleep mode.
Note:
All interrupt pending bits must be cleared before the sleep mode entry.
Exiting Sleep mode
The Sleep mode is exited according to Exiting low-power mode.
Refer to Table 16 and Table 17 for more details on how to exit Sleep mode.
Table 16. Sleep-now entry and exit
Sleep-now mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0, and
– No interrupt (for WFI) or event (for WFE) is pending.
Refer to the Cortex&reg;-M4 with FPU System Control register.
Mode entry
On Return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1,
– No interrupt is pending.
Refer to the Cortex&reg;-M4 with FPU System Control register.
Mode exit
If WFI or Return from ISR was used for entry:
Interrupt: Refer to Table 40: Vector table for STM32F413/423
If WFE was used for entry and SEVONPEND = 0
Wakeup event: Refer to Section 10.2.3: Wakeup event management
f WFE was used for entry and SEVONPEND = 1
Interrupt even when disabled in NVIC: refer to Table 40: Vector table for
STM32F413/423 or Wakeup event (see Section 10.2.3: Wakeup event
management).
Wakeup latency
None
Table 17. Sleep-on-exit entry and exit
Sleep-on-exit
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0, and
– No interrupt (for WFI) or event (for WFE) is pending.
Refer to the Cortex&reg;-M4 with FPU System Control register.
Mode entry
On Return from ISR while:
– SLEEPDEEP = 0, and
– SLEEPONEXIT = 1, and
– No interrupt is pending.
Refer to the Cortex&reg;-M4 with FPU System Control register.
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Table 17. Sleep-on-exit entry and exit (continued)
Sleep-on-exit
5.3.4
Description
Mode exit
Interrupt: refer to Table 40: Vector table for STM32F413/423
Wakeup latency
None
Batch acquisition mode
Entering BAM
The BAM is entered according to Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex&reg;-M4 with FPU System Control register is cleared.
Refer to Table 18 and Table 19 for details on how to enter Sleep mode.
Before entering Sleep mode, the Flash memory must be configured by software to operate
in the required low- power mode. If data need to be transferred from peripheral to RAM
during BAM, the DMA must be enabled before entering Sleep mode.
Exiting BAM
The BAM is exited according to Section : Exiting low-power mode.
Refer to Table 18 and Table 19 for more details on how to exit Sleep mode.
After waking up from BAM, the Flash memory must first to be waked up if code execution
restarts from Flash memory.
This wakeup time must be managed by software running from the internal SRAM.
Table 18. BAM-now entry and exit
Sleep-now mode
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Description
Mode entry
Set the Flash memory in low-power mode:
– FISSR/FMSSR and FPDS bits of the PWR_CR register
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex&reg;-M4 with FPU System Control register.
Mode exit
If WFI was used for entry:
Interrupt: Refer to Table 40: Vector table for STM32F413/423
If WFE was used for entry
Wakeup event: Refer to Section 10.2.3: Wakeup event management
If Flash memory wakeup time is needed, FISSR/FMSSR bits of PWR_CR
register must be set
Wakeup latency
None if code executed from RAM
Low-power mode Flash memory wakeup time, before restarting code
execution from Flash memory (refer to the Flash memory wakeup time in
the Electrical characteristics section of the datasheet).
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Table 19. BAM-on-exit entry and exit
Sleep-on-exit
Description
Mode entry
Set the Flash memory in low-power mode:
– FISSR/FMSSR and FPDS bits of the PWR_CR register
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex&reg;-M4 with FPU System Control register.
Mode exit
Interrupt: refer to Table 40: Vector table for STM32F413/423
If Flash memory wakeup time is needed, FISSR/FMSSR bits of PWR_CR
register must be set
Wakeup latency
None when code executed from internal SRAM
Low-power mode Flash memory wakeup time, before restarting code
execution from Flash memory (refer to the Flash memory wakeup time in
the Electrical characteristics section of the datasheet).
Note:
The BAM has been enhanced by adding SRAM2 that allows SRAM code to be executed
through the Ibus and Dbus, thus improving code execution performance.
5.3.5
Stop mode
The Stop mode is based on the Cortex&reg;-M4 with FPU deepsleep mode combined with
peripheral clock gating. The voltage regulator can be configured either in normal or lowpower mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI
and the HSE RC oscillators are disabled. Internal SRAM and register contents are
preserved.
Some settings in the PWR_CR register allow to further reduce the power consumption.
When the Flash memory is in power-down mode, an additional startup delay is incurred
when waking up from Stop mode (see Table 20: Stop operating modes and Section 5.4.1:
PWR power control register (PWR_CR)).
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Normal mode
Table 20. Stop operating modes
Stop mode
MRLV bit
LPLV bit
FPDS bit
LPDS bit
Wakeup latency
STOP MR
0
-
0
0
HSI RC startup time
STOP MRFPD
0
-
1
0
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode
STOP LP
0
0
0
1
HSI RC startup time +
regulator wakeup time from LP
mode
1
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode +
regulator wakeup time from LP
mode
0
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode +
Main regulator from low voltage
mode
1
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode +
regulator wakeup time from Low
Voltage LP mode
STOP LPFPD
STOP MRLV
STOP LPLV
-
1
-
0
-
1
1
-
-
Entering Stop mode
The Stop mode is entered according to Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex&reg;-M4 with FPU System Control register is set.
Refer to Table 21 for details on how to enter the Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPDS bit of the PWR power control register
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
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In Stop mode, the following features can be selected by programming individual control bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 23.3 in Section 23: Window watchdog (WWDG).
•
Real-time clock (RTC): this is configured by the RTCEN bit in the Section 6.3.23: RCC
Backup domain control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the
Section 6.3.24: RCC clock control &amp; status register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Section 6.3.23: RCC Backup domain control register (RCC_BDCR).
The ADC can also consume power during the Stop mode, unless it is disabled before
entering it. To disable it, the ADON bit in the ADC_CR2 register must be written to 0.
Note:
If the application needs to disable the external clock before entering Stop mode, the HSEON
bit must first be disabled and the system clock switched to HSI.
Otherwise, if the HSEON bit is kept enabled while the external clock (external oscillator) can
be removed before entering stop mode, the clock security system (CSS) feature must be
enabled to detect any external oscillator failure and avoid a malfunction behavior when
entering stop mode.
Exiting Stop mode
The Stop mode is exited according to Section : Exiting low-power mode.
Refer to Table 21 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.
Table 21. Stop mode entry and exit
Stop mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– No interrupt (for WFI) or event (for WFE) is pending,
– SLEEPDEEP bit is set in Cortex&reg;-M4 with FPU System Control register,
– PDDS bit is cleared in Power Control register (PWR_CR),
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR.
Mode entry
On Return from ISR:
– No interrupt is pending,
– SLEEPDEEP bit is set in Cortex&reg;-M4 with FPU System Control register,
– SLEEPONEXIT = 1,
– PDDS bit is cleared in Power Control register (PWR_CR).
Note: To enter Stop mode, all EXTI Line pending bits (in Section 10.3.6:
Pending register (EXTI_PR)), all peripheral interrupts pending bits,
the RTC Alarm (Alarm A and Alarm B), RTC wakeup, RTC tamper,
and RTC time stamp flags, must be reset. Otherwise, the Stop
mode entry procedure is ignored and program execution continues.
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Table 21. Stop mode entry and exit
Stop mode
5.3.6
Description
Mode exit
If WFI or Return from ISR was used for entry:
Any EXTI lines configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 40: Vector table for STM32F413/423.
If WFE was used for entry and SEVONPEND = 0
Any EXTI lines configured in event mode. Refer to Section 10.2.3:
Wakeup event management.
If WFE was used for entry and SEVONPEND = 1:
– Any EXTI lines configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be an external interrupt or a peripheral with wakeup capability. Refer to
Table 40: Vector table for STM32F413/423.
– Wakeup event: refer to Section 10.2.3: Wakeup event management.
Wakeup latency
See Table 20: Stop operating modes
Standby mode
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex&reg;-M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.2 V
domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are
also switched off. SRAM and register contents are lost except for registers in the backup
domain (RTC registers and RTC backup register), and Standby circuitry (see Figure 8).
Entering Standby mode
The Standby mode is entered according to Section : Entering low-power mode, when the
SLEEPDEEP bit in the Cortex&reg;-M4 with FPU System Control register is set.
Refer to Table 22 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 22.3 in Section 22: Independent watchdog (IWDG).
•
Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
backup domain control register (RCC_BDCR)
Exiting Standby mode
The Standby mode is exited according to Section : Exiting low-power mode. The SBF status
flag in PWR_CR (see Section 5.4.2: PWR power control/status register (PWR_CSR))
indicates that the MCU was in Standby mode. All registers are reset after wakeup from
Standby except for PWR_CR.
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Power controller (PWR)
Refer to Table 22 for more details on how to exit Standby mode.
Table 22. Standby mode entry and exit
Standby mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP is set in Cortex&reg;-M4 with FPU System Control register,
– PDDS bit is set in Power Control register (PWR_CR),
– No interrupt (for WFI) or event (for WFE) is pending,
– WUF bit is cleared in Power Control register (PWR_CR),
– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,
RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared
Mode entry
On return from ISR while:
– SLEEPDEEP bit is set in Cortex&reg;-M4 with FPU System Control register,
and
– SLEEPONEXIT = 1, and
– PDDS bit is set in Power Control register (PWR_CR), and
– No interrupt is pending,
– WUF bit is cleared in Power Control/Status register (PWR_SR),
– The RTC flag corresponding to the chosen wakeup source (RTC Alarm
A, RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared.
Mode exit
WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time stamp event, external reset in NRST pin, IWDG reset.
Wakeup latency
Reset phase.
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except for:
•
Reset pad (still available)
•
RTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC
clock calibration out
•
WKUP pin (PA0/PC0/PC1), if enabled
Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Cortex&reg;-M4 with
FPU core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 34.16.1: Debug support for low-power modes.
5.3.7
Programming the RTC alternate functions to wake up the device from
the Stop and Standby modes
The MCU can be woken up from a low-power mode by an RTC alternate function.
The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC
tamper event detection and RTC time stamp event detection.
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These RTC alternate functions can wake up the system from the Stop and Standby lowpower modes.
The system can also wake up from low-power modes without depending on an external
interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events.
The RTC provides a programmable time base for waking up from the Stop or Standby mode
at regular intervals.
For this purpose, two of the three alternate RTC clock sources can be selected by
programming the RTCSEL[1:0] bits in the Section 6.3.23: RCC Backup domain control
register (RCC_BDCR):
•
Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with a very low-power consumption
(additional consumption of less than 1 &micro;A under typical conditions)
•
Low-power internal RC oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC oscillator is designed to use minimum power.
RTC alternate functions to wake up the device from the Stop mode
•
•
•
To wake up the device from the Stop mode with an RTC alarm event, it is necessary to:
a)
Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC Alarm Interrupt in the RTC_CR register
c)
Configure the RTC to generate the RTC alarm
To wake up the device from the Stop mode with an RTC tamper or time stamp event, it
is necessary to:
a)
Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper
interrupt in the RTC_TAFCR register
c)
Configure the RTC to detect the tamper or time stamp event
To wake up the device from the Stop mode with an RTC wakeup event, it is necessary
to:
a)
Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC wakeup interrupt in the RTC_CR register
c)
Configure the RTC to generate the RTC Wakeup event
RTC alternate functions to wake up the device from the Standby mode
•
•
To wake up the device from the Standby mode with an RTC alarm event, it is necessary
to:
a)
Enable the RTC alarm interrupt in the RTC_CR register
b)
Configure the RTC to generate the RTC alarm
To wake up the device from the Standby mode with an RTC tamper or time stamp
event, it is necessary to:
a)
110/1321
Enable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper
interrupt in the RTC_TAFCR register
RM0430 Rev 9
RM0430
Power controller (PWR)
b)
•
Configure the RTC to detect the tamper or time stamp event
To wake up the device from the Standby mode with an RTC wakeup event, it is
necessary to:
a)
Enable the RTC wakeup interrupt in the RTC_CR register
b)
Configure the RTC to generate the RTC wakeup event
Safe RTC alternate function wakeup flag clearing sequence
If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared,
it will not be detected on the next event as detection is made once on the rising edge.
To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit
correctly from the Stop and Standby modes, it is recommended to follow the sequence
below before entering the Standby mode:
•
•
•
•
When using RTC alarm to wake up the device from the low-power modes:
a)
Disable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register)
b)
Clear the RTC alarm (ALRAF/ALRBF) flag
c)
Clear the PWR Wakeup (WUF) flag
d)
Enable the RTC alarm interrupt
e)
Re-enter the low-power mode
When using RTC wakeup to wake up the device from the low-power modes:
a)
Disable the RTC Wakeup interrupt (WUTIE bit in the RTC_CR register)
b)
Clear the RTC Wakeup (WUTF) flag
c)
Clear the PWR Wakeup (WUF) flag
d)
Enable the RTC Wakeup interrupt
e)
Re-enter the low-power mode
When using RTC tamper to wake up the device from the low-power modes:
a)
Disable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register)
b)
Clear the Tamper (TAMP1F/TSF) flag
c)
Clear the PWR Wakeup (WUF) flag
d)
Enable the RTC tamper interrupt
e)
Re-enter the low-power mode
When using RTC time stamp to wake up the device from the low-power modes:
a)
Disable the RTC time stamp interrupt (TSIE bit in RTC_CR)
b)
Clear the RTC time stamp (TSF) flag
c)
Clear the PWR Wakeup (WUF) flag
d)
Enable the RTC TimeStamp interrupt
e)
Re-enter the low-power mode
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5.4
Power control registers
5.4.1
PWR power control register (PWR_CR)
Address offset: 0x00
Reset value: 0x0000 8000 (reset by wakeup from Standby mode)
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
Res.
MRLV
DS
LPLV
DS
FPDS
DBP
rw
rw
rw
rw
VOS
rw
ADCDC1
rw
rw
21
rw
19
18
17
16
Res.
Res.
Res.
Res.
rw
rw
5
4
3
2
1
0
PVDE
CSBF
CWUF
PDDS
LPDS
rw
w
w
rw
rw
PLS[2:0]
rw
20
FISSR FMSSR
rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 FISSR: Flash Interface Stop while System Run
0: Flash Interface clock run (Default value).
1: Flash Interface clock off.
Note: This bit could not be set while executing with the Flash itself. It should be done with
specific routine executed from RAM.
Bit 20 FMSSR: Flash Memory Sleep System Run.
0: Flash standard mode (Default value)
1: Flash forced to be in STOP or DeepPower Down mode (depending of FPDS value bit) by
hardware.
Note: This bit could not be set while executing with the Flash itself. It should be done with
specific routine executed from RAM.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:14 VOS[1:0]: Regulator voltage scaling output selection
These bits control the main internal voltage regulator output voltage to achieve a trade-off
between performance and power consumption when the device does not operate at the
maximum frequency (refer to the corresponding datasheet for more details).
These bits can be modified only when the PLL is OFF. The new value programmed is active
only when the PLL is ON. When the PLL is OFF, the voltage regulator is set to scale 3
independently of the VOS register content.
00: Reserved (Scale 3 mode selected)
01: Scale 3 mode &lt;= 64 MHz
10: Scale 2 mode (reset value) &lt;= 84 MHz
11: Scale 1 mode &lt;= 100 MHz
Bit 13 ADCDC1:
0: No effect.
1: Refer to AN4073 for details on how to use this bit.
Note: This bit can only be set when operating at supply voltage range 2.7 to 3.6V and when
the Prefetch is OFF.
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Power controller (PWR)
Bit 12 Reserved, must be kept at reset value.
Bit 11 MRLVDS: Main regulator Low Voltage in Deep Sleep
0: Main regulator in Voltage scale 3 when the device is in Stop mode.
1: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is
in Stop mode.
Bit 10 LPLVDS: Low-power regulator Low Voltage in Deep Sleep
0: Low-power regulator on if LPDS bit is set when the device is in Stop mode.
1: Low-power regulator in Low Voltage and Flash memory in Deep Sleep mode if LPDS bit is
set when device is in Stop mode.
Bit 9 FPDS: Flash power-down in Stop mode
When set, the Flash memory enters power-down mode when the device enters Stop mode.
This allows to achieve a lower consumption in stop mode but a longer restart time.
0: Flash memory not in power-down when the device is in Stop mode
1: Flash memory in power-down when the device is in Stop mode
Bit 8 DBP: Disable backup domain write protection
In reset state, the RCC_BDCR register, the RTC registers (including the backup registers),
and the BRE bit of the PWR_CSR register, are protected against parasitic write access. This
bit must be set to enable write access to these registers.
0: Access to RTC and RTC Backup registers.
1: Access to RTC and RTC Backup registers.
Bits 7:5 PLS[2:0]: PVD level selection
These bits are written by software to select the voltage threshold detected by the
programmable voltage detector
000: 2.2 V
001: 2.3 V
010: 2.4 V
011: 2.5 V
100: 2.6 V
101: 2.7 V
110: 2.8 V
111: 2.9 V
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Programmable voltage detector enable
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
0: No effect.
1: Clear the SBF Standby Flag (write).
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
0: No effect.
1: Clear the WUF Wakeup Flag after 2 System clock cycles.
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Power controller (PWR)
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Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters deepsleep.
Bit 0 LPDS: Low-power deepsleep
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode.
1: Low-power Voltage regulator on during Stop mode.
5.4.2
PWR power control/status register (PWR_CSR)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
VOS
RDY
BRE
EWUP
1
EWUP
2
EWUP
3
Res.
Res.
BRR
PVDO
SBF
WUF
rw
rw
rw
rw
r
r
r
r
r
Res.
Res.
Res.
Res.
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
0: Not ready
1: Ready
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 BRE: Backup regulator enable
When set, the Backup regulator (used to maintain the backup domain content) is enabled. If
BRE is reset, the backup regulator is switched off. Once set, the application must wait that
the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the
backup registers will be maintained in the Standby and VBAT modes. The DBP bit of
PWR_CR register must be set to 1 before PWR_CSR.BRE can be written.
0: Backup regulator disabled
1: Backup regulator enabled
Note: This bit is not reset when the device wakes up from Standby mode, by a system reset,
or by a power reset. This bit is reset by a backup domain reset.
Bit 8 EWUP1: Enable WKUP1 pin (PA0)
This bit is set and cleared by software.
0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not
wakeup the device from Standby mode.
1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP1 pin wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
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Power controller (PWR)
Bit 7 EWUP2: Enable WKUP2 pin (PC0)
This bit is set and cleared by software.
0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not
wakeup the device from Standby mode.
1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP2 pin wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bit 6 EWUP3: Enable WKUP3 pin (PC1)
This bit is set and cleared by software.
0: WKUP3 pin is used for general purpose I/O. An event on the WKUP3 pin does not
wakeup the device from Standby mode.
1: WKUP3 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP3 pin wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 BRR: Backup regulator ready
Set by hardware to indicate that the Backup Regulator is ready.
0: Backup Regulator not ready
1: Backup Regulator ready
Note: This bit is not reset when the device wakes up from Standby mode or by a system reset
or power reset. This bit is reset by a backup domain reset.
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits.
1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Standby or reset until the PVDE bit is set.
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
reset) or by setting the CSBF bit in the PWR_CR register.
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in
the PWR_CR register.
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or
Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
EWUP bit) when the WKUP pin level is already high.
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Power controller (PWR)
5.5
RM0430
PWR register map
The following table summarizes the PWR registers.
EWUP3
Res.
0
Refer to Section 2.2 on page 57 for the register boundary addresses.
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LPDS
EWUP2
0
PDDS
EWUP1
0
0
0
0
0
SBF
BRE
0
0
WUF
0
CSBF
0
CWUF
0
PVDO
0
PVDE
DBP
0
Res.
FPDS
0
BRR
LPLVDS
0
Res.
Res.
MRLVDS
Res.
0
PLS[2:0]
Res.
ADCDC1
0
Res.
0
VOSRDY
Res.
VOS[1:0]
1
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
FMSSR
0
Res.
0
Res.
Res.
FISSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PWR_CSR
Res.
0x004
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PWR_CR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000
Register
Res.
Offset
Res.
Table 23. PWR - register map and reset values
0
0
0
0
RM0430
Reset and clock control (RCC) for STM32F413/423
6
Reset and clock control (RCC) for STM32F413/423
6.1
Reset
There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
6.1.1
System reset
A system reset sets all registers to their reset values unless specified otherwise in the
register description.
A system reset is generated when one of the following events occurs:
1.
A low level on the NRST pin (external reset)
2.
Window watchdog end of count condition (WWDG reset)
3.
Independent watchdog end of count condition (IWDG reset)
4.
A software reset (SW reset) (see Software reset)
5.
Low-power management reset (see Low-power management reset)
Software reset
The reset source can be identified by checking the reset flags in the RCC clock control &amp;
status register (RCC_CSR).
The SYSRESETREQ bit in Cortex&reg;-M4 with FPU Application Interrupt and Reset Control
Register must be set to force a software reset on the device. Refer to the Cortex&reg;-M4 with
FPU technical reference manual for more details.
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RM0430
Low-power management reset
There are two ways of generating a low-power management reset:
1.
Reset generated when entering the Standby mode:
This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes.
In this case, whenever a Standby mode entry sequence is successfully executed, the
device is reset instead of entering the Standby mode.
2.
Reset when entering the Stop mode:
This type of reset is enabled by resetting the nRST_STOP bit in the user option bytes.
In this case, whenever a Stop mode entry sequence is successfully executed, the
device is reset instead of entering the Stop mode.
For further information on the user option bytes, refer to the STM32F413/423 Flash
programming manual available from your ST sales office.
6.1.2
Power reset
A power reset is generated when one of the following events occurs:
1.
Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset
2.
When exiting the Standby mode
A power reset sets all registers to their reset values except the Backup domain.
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 &micro;s for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
Figure 12. Simplified diagram of the reset circuit
VDD/VDDA
RPU
External
reset
Filter
System reset
NRST
Pulse
generator
(min 20 μs)
WWDG reset
IWDG reset
Power reset
Software reset
Low-power management reset
ai16095c
6.1.3
Backup domain reset
The backup domain reset sets all RTC registers, the RCC_BDCR register and the bit BRE
of PWR_CSR register to their reset values.
Note:
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The bit DBP of the register PWR_CR must be set to 1 in order to generate the backup
domain reset.
RM0430 Rev 9
RM0430
Reset and clock control (RCC) for STM32F413/423
A backup domain reset is generated when one of the following events occurs:
6.2
1.
Software reset, triggered by setting the BDRST bit in the RCC Backup domain control
register (RCC_BDCR).
2.
VDD or VBAT power on, if both supplies have previously been powered off.
Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
•
HSI oscillator clock
•
HSE oscillator clock
•
Main PLL (PLL) clock
The devices have the two following secondary clock sources:
•
32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and,
optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.
•
32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC
clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
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RM0430
Figure 13. Clock tree
@V33
enable
Watchdog
ck_rcls
LSI RC
Watchdog
LS clock
LSI tempo
ck_lsi
LS
@Vsw
from USB FS Ip
ck_xtls
LSE tempo
LSE OSC
LS
@V33 @V12
L
/1 -&gt; 5
S
MCO2
PAD
ck_sys
ck_pll2r
not deepsleep
System
Clock
Level shifter
ck_sys
ck_hse
/8
ck_hsi
/R
Ip enable
if (APB1 presc = 1) x1
x2
else
PLLSRC
ck_rchs
/Q
Ip enable
APB1
PRESC
/ 1,2,4,8,16
ck_hsi
HSI tempo
ck_pllin
xN
AHB Peripheral
clocks
Ip enable
ck_pll
/P
Ip enable
AHB
PRESC
/ 1,2,..512
HSE tempo
HSI RC
VCO
Power ctrl
clock
cpu clock
/2 -&gt; 31
@V33
@V12
1
not(sleep or deepsleep)
@V33
level shifters
Lptimer
clock
O
Clock
Source
Control
ck_xths
Ip enable
ck_hse_1M
PAD
@V12
level shifters
Clock
Detector
RTC / AWU
ck_apb
clock
ck_lsi
ck_hsi
ck_lse
LS
ck_lse
@V33 @V12
L
/1 -&gt; 5
S
MCO1
HSE
OSC
adp_clk
adp_clk_req
RTC / AWU enable
ck_pll1p
CK48MSEL
ck_pll1q
APB1 peripheral
clocks
APB1 timer
clocks
Ip enable
APB2
PRESC
/ 1,2,4,8,16
/PLLM
Systick
clock
Ip enable
if (APB2 presc = 1) x1
else
x2
ck_pll1r
Ip enable
APB2 peripheral
clocks
APB2 timer
clocks
PLL1
PLLI2SSRC
ck_sys
Ip enable
DFSDM1
clock
Ip enable
DFSDM2
clock
Ip enable
SDIO
clock
Ip enable
USBFS
RNG
Ip enable
I2S2/3
clock
Ip enable
i2S1/4/5
clocks
CKDFSDMSEL
/PLLI2SM
VCO
/Q
xN
CKSDIOSEL
ck_plli2s_ext
/P
/R
ck_pl2q
ck_pll2r
I2S1SRC
PLL2
Ip enable
ck_i2s_apb1
Ip enable
ck_i2s_apb2
Ip enable
CKDFSDM1ASEL
Ip enable
CKDFSDM2ASEL
I2S2SRC
Ip enable
DFSDM1
ck_plli2s_ext
Ip enable
HS_ck
PLLDIVR
div 1 to 32
SAI1ASRC
R1
ck_hsi
ck_sys
ck_apb1
I2C4SEL
Ip enable
Ip enable
I2C4
clocks
Ip enable
SAI1_A
clocks
disable_debug
SAI1_B
clocks
I2S_CKIN
Ip enable
PLLI2SDIVR
div 1 to 32 R2
SAI1BSRC
@V33 @V12
L
S
ck_jtck
PAD
DFSDM2
clocks
JTAG
clocks
MSv42608V2
1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in
the device datasheet.
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The clock controller provides a high degree of flexibility to the application in the choice of the
external crystal or the oscillator to run the core and peripherals at the highest frequency
and, guarantee the appropriate frequency for peripherals that need a specific clock like USB
OTG FS, I2S and SDIO.
Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)
and the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is
100 MHz. The maximum allowed frequency of the high-speed APB2 domain is 100 MHz.
The maximum allowed frequency of the low-speed APB1 domain is 50 MHz
All peripheral clocks are derived from the system clock (SYSCLK) except for:
•
The USB OTG FS clock (48 MHz) and the SDIO clock (≤ 48 MHz) which are coming
from a specific output of PLL (PLL48CLK)
•
The I2S clock
To achieve high-quality audio performance, the I2S clock can be derived either from a
specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For
more information about I2S clock frequency and precision, refer to Section 29.6.4:
Clock generator.
•
I2CFMP1 clock which can also be generated from HSI, SYSCLK or APB1 clock.
The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick control and status register.
The timer clock frequencies are automatically set by hardware. There are two cases
depending on the value of TIMPRE bit in RCC_DCKCFGR register:
•
If TIMPRE bit is reset:
If the APB prescaler is configured to a division factor of 1, the timer clock frequencies
(TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies are twice the
frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.
•
If TIMPRE bit is set:
If the APB prescaler is configured to a division factor of 1 or 2, the timer clock
frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four
times the frequency of the APB domain to which the timers are connected: TIMxCLK =
4xPCLKx.
FCLK acts as Cortex&reg;-M4 with FPU free-running clock. For more details, refer to the
Cortex&reg;-M4 with FPU technical reference manual.
6.2.1
HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
•
HSE external crystal/ceramic resonator
•
HSE external user clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
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Figure 14. HSE/ LSE clock sources
Hardware configuration
OSC_OUT
External clock
(HI-Z)
External
source
OSC_IN OSC_OUT
Crystal/ceramic
resonators
CL1
Load
capacitors
CL2
External source (HSE bypass)
In this mode, an external clock source must be provided. You select this mode by setting the
HSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock
signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the
OSC_OUT pin should be left HI-Z. See Figure 14.
External crystal/ceramic resonator (HSE crystal)
The HSE has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in Figure 14. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the RCC clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control
register (RCC_CR).
6.2.2
HSI clock
The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used
directly as a system clock, or used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
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Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 &deg;C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC clock
control register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the RCC clock control register (RCC_CR).
The HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is
stable or not. At startup, the HSI RC output clock is not released until this bit is set by
hardware.
The HSI RC can be switched on and off using the HSION bit in the RCC clock control
register (RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 6.2.7: Clock security system (CSS) on page 124.
6.2.3
PLL configuration
The STM32F413/423 devices feature two PLLs:
•
•
A main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different
output clocks:
–
The first output is used to generate the high speed system clock (up to 100 MHz)
–
The second output is used to generate the clock for the USB OTG FS (48 MHz),
RNG and the SDIO (≤ 50 MHz).
A dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality
audio performance on the I2S interface.
Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is
recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as
PLL clock source, and configuration of division factors M, P, Q and multiplication factor N).
The PLLI2S uses the same input clock as the main PLL (HSI or HSE). However, the PLLI2S
has dedicated enable/disable and division factors configuration bits. Refer to Section 6.3.1:
RCC clock control register (RCC_CR), Section 6.3.2: RCC PLL configuration register
(RCC_PLLCFGR) and Section 6.3.26: RCC PLLI2S configuration register
(RCC_PLLI2SCFGR). Once the PLLI2S is enabled, the configuration parameters cannot be
changed.
The two PLLs are disabled by hardware when entering Stop and Standby modes, or when
an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC
PLL configuration register (RCC_PLLCFGR) and RCC clock configuration register
(RCC_CFGR) can be used to configure PLL and PLLI2S, respectively.
6.2.4
LSE clock
The LSE clock is generated using a 32.768kHz low speed external crystal or ceramic
resonator. It has the advantage providing a low-power but highly accurate clock source to
the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
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The LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain
control register (RCC_BDCR).
The LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock
interrupt register (RCC_CIR).
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RCC Backup
domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle)
with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left HI-Z. See Figure 14.
6.2.5
LSI clock
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 32 kHz. For more details, refer to the electrical characteristics
section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the RCC clock control &amp;
status register (RCC_CSR).
The LSIRDY flag in the RCC clock control &amp; status register (RCC_CSR) indicates if the lowspeed internal oscillator is stable or not. At startup, the clock is not released until this bit is
set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
6.2.6
System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as the system clock. When a clock source
is used directly or through PLL as the system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is
selected, the switch occurs when the clock source is ready. Status bits in the RCC clock
control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as the system clock.
6.2.7
Clock security system (CSS)
The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock
failure event is sent to the break inputs of advanced-control timer TIM1, and an interrupt is
generated to inform the software about the failure (clock security system interrupt CSSI),
allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex&reg;-M4 with
FPU NMI (non-maskable interrupt) exception vector.
Note:
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When the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt,
which causes the automatic generation of an NMI. The NMI is executed indefinitely unless
the CSS interrupt pending bit is cleared. As a consequence, the application has to clear the
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Reset and clock control (RCC) for STM32F413/423
CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register
(RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that
it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is
detected, then the system clock switches to the HSI oscillator and the HSE oscillator is
disabled.
If the HSE oscillator clock was the clock source of PLL used as the system clock when the
failure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also
disabled when the HSE fails.
6.2.8
RTC/AWU clock
Once the RTCCLK clock source has been selected, the only possible way of modifying the
selection is to reset the power domain.
The RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable
prescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits
in the RCC Backup domain control register (RCC_BDCR) and the RTCPRE[4:0] bits in RCC
clock configuration register (RCC_CFGR). This selection cannot be modified without
resetting the Backup domain.
If the LSE is selected as the RTC clock, the RTC will work normally if the backup or the
system supply disappears. If the LSI is selected as the AWU clock, the AWU state is not
guaranteed if the system supply disappears. If the HSE oscillator divided by a value
between 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup
or the system supply disappears.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a
consequence:
•
•
If LSE is selected as the RTC clock:
–
The RTC continues to work even if the VDD supply is switched off, provided the
VBAT supply is maintained.
–
The RTC remains clocked and functional under system reset.
If LSI is selected as the Auto-wakeup unit (AWU) clock:
–
•
The AWU state is not guaranteed if the VDD supply is powered off. Refer to
Section 6.2.5: LSI clock for more details on LSI calibration.
If the HSE clock is used as the RTC clock:
–
The RTC state is not guaranteed if the VDD supply is powered off or if the internal
voltage regulator is powered off (removing power from the 1.2 V domain).
Note:
To read the RTC calendar register when the APB1 clock frequency is less than seven times
the RTC clock frequency (fAPB1 &lt; 7xfRTCLCK), the software must read the calendar time and
date registers twice. The data are correct if the second read access to RTC_TR gives the
same result than the first one. Otherwise a third read access must be performed.
6.2.9
Watchdog clock
If the independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
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6.2.10
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Clock-out capability
Two microcontroller clock output (MCO) pins are available:
•
MCO1
You can output four different clock sources onto the MCO1 pin (PA8) using the
configurable prescaler (from 1 to 5):
–
HSI clock
–
LSE clock
–
HSE clock
–
PLL clock
The desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in
the RCC clock configuration register (RCC_CFGR).
•
MCO2
You can output four different clock sources onto the MCO2 pin (PC9) using the
configurable prescaler (from 1 to 5):
–
HSE clock
–
PLL clock
–
System clock (SYSCLK)
–
PLLI2S clock
The desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the
RCC clock configuration register (RCC_CFGR).
For the different MCO pins, the corresponding GPIO port has to be programmed in alternate
function mode.
The selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O
speed).
6.2.11
Internal/external clock measurement using TIM5/TIM11
It is possible to indirectly measure the frequencies of all on-board clock source generators
by means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in Figure 15
and Figure 16.
Internal/external clock measurement using TIM5 channel4
TIM5 has an input multiplexer which allows choosing whether the input capture is triggered
by the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits
in the TIM5_OR register.
The primary purpose of having the LSE connected to the channel4 input capture is to be
able to precisely measure the HSI (this requires to have the HSI used as the system clock
source). The number of HSI clock counts between consecutive edges of the LSE signal
provides a measurement of the internal clock period. Taking advantage of the high precision
of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency
with the same resolution, and trim the source to compensate for manufacturing-process
and/or temperature- and voltage-related frequency deviations.
The HSI oscillator has dedicated, user-accessible calibration bits for this purpose.
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The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the
precision is therefore tightly linked to the ratio between the two clock sources. The greater
the ratio, the better the measurement.
It is also possible to measure the LSI frequency: this is useful for applications that do not
have a crystal. The ultralow-power LSI oscillator has a large manufacturing process
deviation: by measuring it versus the HSI clock source, it is possible to determine its
frequency with the precision of the HSI. The measured value can be used to have more
accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an
IWDG timeout with an acceptable accuracy.
Use the following procedure to measure the LSI frequency:
1.
Enable the TIM5 timer and configure channel4 in Input capture mode.
2.
Set the TI4_RMP bits in the TIM5_OR register to 0x01 to connect the LSI clock
internally to TIM5 channel4 input capture for calibration purposes.
3.
Measure the LSI clock frequency using the TIM5 capture/compare 4 event or interrupt.
4.
Use the measured LSI frequency to update the prescaler of the RTC depending on the
desired time base and/or to compute the IWDG timeout.
Figure 15. Frequency measurement with TIM5 in Input capture mode
TIM5
TI4_RMP[1:0]
GPIO
RTC_WakeUp_IT
LSE
LSI
TI4
ai17741V2
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Internal/external clock measurement using TIM11 channel1
TIM11 has an input multiplexer which allows choosing whether the input capture is triggered
by the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in
the TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is
connected to channel 1 input capture to have a rough indication of the external crystal
frequency. This requires that the HSI is the system clock source. This can be useful for
instance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be
able to determine harmonic or subharmonic frequencies (–50/+100% deviations).
Figure 16. Frequency measurement with TIM11 in Input capture mode
TIM11
TI1_RMP[1:0]
GPIO
TI1
HSE_RTC(1 MHz)
ai18433
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6.3
RCC registers
Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in
register descriptions.
6.3.1
RCC clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 XX81
Note:
Where X is undefined.
Access: no wait state, word, half-word and byte access
31
Res.
15
30
Res.
14
29
Res.
13
28
Res.
12
27
26
25
24
PLLI2S PLLI2S
PLLRDY PLLON
RDY
ON
r
rw
r
rw
11
10
9
8
23
Res.
7
22
Res.
6
HSICAL[7:0]
r
r
r
r
r
21
Res.
5
20
Res.
4
19
18
17
16
CSSON
HSE
BYP
HSE
RDY
HSEON
rw
rw
r
rw
3
2
1
0
Res.
HSI
RDY
HSION
r
rw
HSITRIM[4:0]
r
r
r
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 PLLI2SRDY: PLLI2S clock ready flag
Set by hardware to indicate that the PLLI2S is locked.
0: PLLI2S unlocked
1: PLLI2S locked
Bit 26 PLLI2SON: PLLI2S enable
Set and cleared by software to enable PLLI2S.
Cleared by hardware when entering Stop or Standby mode.
0: PLLI2S OFF
1: PLLI2S ON
Bit 25 PLLRDY: Main PLL (PLL) clock ready flag
Set by hardware to indicate that PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: Main PLL (PLL) enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL
clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if an oscillator failure is detected.
0: Clock security system OFF (Clock detector OFF)
1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)
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Bit 18 HSEBYP: HSE clock bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit, to be used by the device.
The HSEBYP bit can be written only if the HSE oscillator is disabled.
0: HSE oscillator not bypassed
1: HSE oscillator bypassed with an external clock
Bit 17 HSERDY: HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared,
HSERDY goes low after 6 HSE oscillator clock cycles.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
These bits are initialized automatically at startup.
Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the internal HSI RC.
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: Internal high-speed clock ready flag
Set by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared,
HSIRDY goes low after 6 HSI clock cycles.
0: HSI oscillator not ready
1: HSI oscillator ready
Bit 0 HSION: Internal high-speed clock enable
Set and cleared by software.
Set by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in
case of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit
cannot be cleared if the HSI is used directly or indirectly as the system clock.
0: HSI oscillator OFF
1: HSI oscillator ON
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6.3.2
RCC PLL configuration register (RCC_PLLCFGR)
Address offset: 0x04
Reset value: 0x2400 3010
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLL clock outputs according to the formulas:
31
30
Res.
15
•
f(VCO clock) = f(PLL clock input) &times; (PLLN / PLLM)
•
f(PLL general clock output) = f(VCO clock) / PLLP
•
f(USB OTG FS, SDIO, RNG clock output) = f(VCO clock) / PLLQ
•
f(I2S, DFSDM clock output) = f(VCO clock)/ PLLR
29
28
27
PLLR[2:0]
26
25
24
PLLQ[3:0]
23
22
21
20
19
18
17
Res.
PLLSRC
Res.
Res.
Res.
Res.
PLLP[1:0]
2
rw
rw
rw
rw
rw
rw
rw
14
13
12
11
10
9
8
7
6
5
4
3
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Res.
rw
PLLN[8:0]
rw
16
rw
rw
1
0
rw
rw
PLLM[5:0]
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 PLLR[2:0]: Main PLL (PLL) division factor for I2S, DFSDM clocks
Set and cleared by software to control the frequency of the clock. These bits should be
written only if PLL is disabled.
Clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7
000: PLLR = 0, wrong configuration
001: PLLR = 1, wrong configuration
010: PLLR = 2
011: PLLR = 3
...
111: PLLR = 7
Bits 27:24 PLLQ[3:0]: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number
generator clocks.
Set and cleared by software to control the frequency of USB OTG FS clock, the random
number generator clock and the SDIO clock. These bits should be written only if PLL is
disabled.
Caution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIO and the
random number generator need a frequency lower than or equal to 48 MHz to work
correctly.
USB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15
0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 15
Bit 23 Reserved, must be kept at reset value.
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Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written
only when PLL and PLLI2S are disabled.
0: HSI clock selected as PLL and PLLI2S clock entry
1: HSE oscillator clock selected as PLL and PLLI2S clock entry
Bits 21:18 Reserved, must be kept at reset value.
Bits 17:16 PLLP[1:0]: Main PLL (PLL) division factor for main system clock
Set and cleared by software to control the frequency of the general PLL output clock. These
bits can be written only if PLL is disabled.
Caution: The software has to set these bits correctly not to exceed 100 MHz on this domain.
PLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8
00: PLLP = 2
01: PLLP = 4
10: PLLP = 6
11: PLLP = 8
Bit 15 Reserved, must be kept at reset value.
Bits 14:6 PLLN[8:0]: Main PLL (PLL) multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can
be written only when PLL is disabled. Only half-word and word accesses are allowed to
write these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output
frequency is between 100 and 432 MHz. (check also Section 6.3.26: RCC PLLI2S
configuration register (RCC_PLLI2SCFGR))
VCO output frequency = VCO input frequency &times; PLLN with 50 ≤ PLLN ≤ 432
000000000: PLLN = 0, wrong configuration
000000001: PLLN = 1, wrong configuration
...
000110010: PLLN = 50
...
001100011: PLLN = 99
001100100: PLLN = 100
...
110110000: PLLN = 432
110110001: PLLN = 433, wrong configuration
...
111111111: PLLN = 511, wrong configuration
Note: Multiplication factors possible for VCO input frequency higher than 1 MHz but care
must be taken to fulfill the VCO output frequency range as specified above.
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Reset and clock control (RCC) for STM32F413/423
Bits 5:0 PLLM[5:0]: Division factor for the main PLL (PLL) input clock
Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO.
These bits can be written only when the PLL and PLLI2S are disabled.
Caution: The software has to set these bits correctly to ensure that the VCO input frequency
ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit
PLL jitter.
VCO input frequency = PLL input clock frequency / PLLM with 2 ≤ PLLM ≤ 63
000000: PLLM = 0, wrong configuration
000001: PLLM = 1, wrong configuration
000010: PLLM = 2
000011: PLLM = 3
000100: PLLM = 4
...
111110: PLLM = 62
111111: PLLM = 63
6.3.3
RCC clock configuration register (RCC_CFGR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during a clock source switch.
31
30
MCO2[1:0]
rw
15
29
28
rw
rw
rw
14
13
12
rw
26
MCO2 PRE[2:0]
PPRE2[2:0]
rw
27
rw
rw
rw
11
10
rw
24
MCO1 PRE[2:0]
PPRE1[2:0]
rw
25
rw
rw
23
22
Res.
MCO1[1:0]
rw
9
8
Res.
Res.
21
rw
7
6
5
20
rw
rw
18
17
16
RTCPRE[4:0]
rw
rw
rw
rw
rw
4
3
2
1
0
HPRE[3:0]
rw
19
SWS[1:0]
rw
r
r
SW[1:0]
rw
rw
Bits 31:30 MCO2[1:0]: Microcontroller clock output 2
Set and cleared by software. Clock source selection may generate glitches on MCO2. It is
highly recommended to configure these bits only after reset before enabling the external
oscillators and the PLLs.
00: System clock (SYSCLK) selected
01: PLLI2S clock selected
10: HSE oscillator clock selected
11: PLL clock selected
Bits 29:27 MCO2PRE[1:0]: MCO2 prescaler
Set and cleared by software to configure the prescaler of the MCO2. Modification of this
prescaler may generate glitches on MCO2. It is highly recommended to change this
prescaler only after reset before enabling the external oscillators and the PLLs.
0xx: no division
100: division by 2
101: division by 3
110: division by 4
111: division by 5
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RM0430
Bits 26:24 MCO1PRE[1:0]: MCO1 prescaler
Set and cleared by software to configure the prescaler of the MCO1. Modification of this
prescaler may generate glitches on MCO1. It is highly recommended to change this
prescaler only after reset before enabling the external oscillators and the PLL.
0xx: no division
100: division by 2
101: division by 3
110: division by 4
111: division by 5
Bit 23 Reserved, always read as 0.
Bits 22:21 MCO1[1:0]: Microcontroller clock output 1
Set and cleared by software. Clock source selection may generate glitches on MCO1. It is
highly recommended to configure these bits only after reset before enabling the external
oscillators and PLL.
00: HSI clock selected
01: LSE oscillator selected
10: HSE oscillator clock selected
11: PLL clock selected
Bits 20:16 RTCPRE[4:0]: HSE division factor for RTC clock
Set and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock
for RTC.
Caution: The software has to set these bits correctly to ensure that the clock supplied to the
RTC is 1 MHz. These bits must be configured if needed before selecting the RTC
clock source.
00000: no clock
00001: no clock
00010: HSE/2
00011: HSE/3
00100: HSE/4
...
11110: HSE/30
11111: HSE/31
Bits 15:13 PPRE2[2:0]: APB high-speed prescaler (APB2)
Set and cleared by software to control APB high-speed clock division factor.
Caution: The software has to set these bits correctly not to exceed 100 MHz on this domain.
The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
PPRE2 write.
0xx: AHB clock not divided
100: AHB clock divided by 2
101: AHB clock divided by 4
110: AHB clock divided by 8
111: AHB clock divided by 16
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Reset and clock control (RCC) for STM32F413/423
Bits 12:10 PPRE1[2:0]: APB Low speed prescaler (APB1)
Set and cleared by software to control APB low-speed clock division factor.
Caution: The software has to set these bits correctly not to exceed 50 MHz on this domain.
The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
PPRE1 write.
0xx: AHB clock not divided
100: AHB clock divided by 2
101: AHB clock divided by 4
110: AHB clock divided by 8
111: AHB clock divided by 16
Bits 9:8 Reserved, must be kept at reset value.
Bits 7:4 HPRE[3:0]: AHB prescaler
Set and cleared by software to control AHB clock division factor.
Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
HPRE write.
Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
0xxx: system clock not divided
1000: system clock divided by 2
1001: system clock divided by 4
1010: system clock divided by 8
1011: system clock divided by 16
1100: system clock divided by 64
1101: system clock divided by 128
1110: system clock divided by 256
1111: system clock divided by 512
Bits 3:2 SWS[1:0]: System clock switch status
Set and cleared by hardware to indicate which clock source is used as the system clock.
00: HSI oscillator used as the system clock
01: HSE oscillator used as the system clock
10: PLL used as the system clock
11: not applicable
Bits 1:0 SW[1:0]: System clock switch
Set and cleared by software to select the system clock source.
Set by hardware to force the HSI selection when leaving the Stop or Standby mode or in
case of failure of the HSE oscillator used directly or indirectly as the system clock.
00: HSI oscillator selected as system clock
01: HSE oscillator selected as system clock
10: PLL selected as system clock
11: not allowed
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6.3.4
RM0430
RCC clock interrupt register (RCC_CIR)
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSSC
Res.
PLLI2S
RDYC
PLL
RDYC
HSE
RDYC
HSI
RDYC
LSE
RDYC
LSI
RDYC
w
w
w
w
w
w
w
15
Res.
14
Res.
13
12
11
10
PLLI2S
PLL
HSE
HSI
RDYIE RDYIE RDYIE RDYIE
rw
rw
rw
rw
9
8
LSE
RDYIE
LSI
RDYIE
7
CSSF
rw
rw
r
6
5
4
3
2
1
0
Res.
PLLI2S
RDYF
PLL
RDYF
HSE
RDYF
HSI
RDYF
LSE
RDYF
LSI
RDYF
r
r
r
r
r
r
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 22 Reserved, must be kept at reset value.
Bit 21 PLLI2SRDYC: PLLI2S ready interrupt clear
This bit is set by software to clear the PLLI2SRDYF flag.
0: No effect
1: PLLI2SRDYF cleared
Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
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Reset and clock control (RCC) for STM32F413/423
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLLI2S lock.
0: PLLI2S lock interrupt disabled
1: PLLI2S lock interrupt enabled
Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE: HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Bit 7 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 6 Reserved, must be kept at reset value.
Bit 5 PLLI2SRDYF: PLLI2S ready interrupt flag
Set by hardware when the PLLI2S locks and PLLI2SRDYIE is set.
Cleared by software setting the PLLRI2SDYC bit.
0: No clock ready interrupt caused by PLLI2S lock
1: Clock ready interrupt caused by PLLI2S lock
Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag
Set by hardware when PLL locks and PLLRDYIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
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RM0430
Bit 3 HSERDYF: HSE ready interrupt flag
Set by hardware when External High Speed clock becomes stable and HSERDYIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is set.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the External Low Speed clock becomes stable and LSERDYIE is
set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the internal low speed clock becomes stable and LSIRDYIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
6.3.5
RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2
RST
DMA1
RST
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
6
4
3
2
1
Res.
GPIOH
RST
GPIOG
RST
rw
rw
Res.
Res.
Res.
CRCRST
Res.
Res.
Res.
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DMA2RST: DMA2 reset
Set and cleared by software.
0: does not reset DMA2
1: resets DMA2
Bit 21 DMA1RST: DMA1 reset
Set and cleared by software.
0: does not reset DMA1
1: resets DMA1
Bits 20:13 Reserved, must be kept at reset value.
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5
GPIOF GPIOE GPIOD GPIOC GPIOB
RST
RST
RST
RST
RST
rw
rw
rw
rw
rw
0
GPIOA
RST
rw
RM0430
Reset and clock control (RCC) for STM32F413/423
Bit 12 CRCRST: CRC reset
Set and cleared by software.
0: does not reset CRC
1: resets CRC
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 GPIOHRST: IO port H reset
Set and cleared by software.
0: does not reset IO port H
1: resets IO port H
Bit 6 GPIOGRST: IO port G reset
Set and cleared by software.
0: does not reset IO port G
1: resets IO port G
Bit 5 GPIOFRST: IO port F reset
Set and cleared by software.
0: does not reset IO port F
1: resets IO port F
Bit 4 GPIOERST: IO port E reset
Set and cleared by software.
0: does not reset IO port E
1: resets IO port E
Bit 3 GPIODRST: IO port D reset
Set and cleared by software.
0: does not reset IO port D
1: resets IO port D
Bit 2 GPIOCRST: IO port C reset
Set and cleared by software.
0: does not reset IO port C
1: resets IO port C
Bit 1 GPIOBRST: IO port B reset
Set and cleared by software.
0: does not reset IO port B
1:resets IO port B
Bit 0 GPIOARST: IO port A reset
Set and cleared by software.
0: does not reset IO port A
1: resets IO port A
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6.3.6
RM0430
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
for STM32F413xx
Address offset: 0x14
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OTGFS
RST
RNG
RST
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSRST: USB OTG FS module reset
Set and cleared by software.
0: does not reset the USB OTG FS module
1: resets the USB OTG FS module
Bit 6 RNGRST: RNG module reset
Set and cleared by software.
0: does not reset RNG module
1: resets RNG module
Bits 5:0 Reserved, must be kept at reset value.
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Reset and clock control (RCC) for STM32F413/423
6.3.7
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
for STM32F423xx
Address offset: 0x14
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OTGFS
RST
RNG
RST
Res.
CRYP
RST
Res.
Res.
Res.
Res.
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSRST: USB OTG FS module reset
Set and cleared by software.
0: does not reset the USB OTG FS module
1: resets the USB OTG FS module
Bit 6 RNGRST: RNG module reset
Set and cleared by software.
0: does not reset RNG module
1: resets RNG module
Bit 5 Reserved, must be kept at reset value.
Bit 4 CRYPRST: CRYP module reset
Set and reset by software.
0: does not reset CRYP module
1: resets CRYP module
Bits 3:0 Reserved, must be kept at reset value.
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Reset and clock control (RCC) for STM32F413/423
6.3.8
RM0430
RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
QSPIRST
FSMC
RST
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPIRST: QUADSPI module reset
Set and cleared by software.
0: does not reset QUADSPI module
1: resets QUADSPI module
Bit 0 FSMCRST: Flexible memory controller module reset
Set and cleared by software.
0: does not reset the FSMC module
1: resets the FSMC module
6.3.9
RCC APB1 peripheral reset register for (RCC_APB1RSTR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
UART8 UART7
RST
RST
29
28
27
26
25
24
23
22
21
DAC
RST
PWR
RST
CAN3
RST
CAN2
RST
CAN1
RST
I2C4
RST
I2C3
RST
I2C2
RST
I2C1
RST
20
19
18
17
UART5 UART4 USART3 USART2
RST
RST
RST
RST
16
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI3
RST
SPI2
RST
Res.
Res.
WWDG
RST
Res.
LPTIMER1
RST
TIM14
RST
TIM7
RST
TIM6
RST
TIM5
RST
TIM4
RST
TIM3
RST
TIM2
RST
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
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rw
TIM13 TIM12
RST
RST
rw
RM0430 Rev 9
rw
RM0430
Reset and clock control (RCC) for STM32F413/423
Bit 31 UART8RST: UART 8 reset
Set and reset by software.
0: does not reset UART 8
1: resets the UART 8
Bit 30 UART7RST: UART 7 reset
Set and reset by software.
0: does not reset UART 7
1: resets the UART 7
Bit 29 DACRST: DAC reset
Set and reset by software.
0: does not reset DAC
1: resets DAC
Bit 28 PWRRST: Power interface reset
Set and reset by software.
0: does not reset the power interface
1: resets the power interface
Bit 27 CAN3RST: CAN 3 reset
Set and reset by software.
0: does not reset CAN 3
1: resets CAN 3
Bit 26 CAN2RST: CAN2 reset
Set and cleared by software.
0: does not reset CAN2
1: resets CAN2
Bit 25 CAN1RST: CAN1 reset
Set and cleared by software.
0: does not reset CAN1
1: resets CAN1
Bit 24 I2C4RST: I2C4 reset
Set and reset by software.
0: does not reset I2C4
1: resets I2C4
Bit 23 I2C3RST: I2C3 reset
Set and reset by software.
0: does not reset I2C3
1: resets I2C3
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: does not reset I2C2
1: resets I2C2
Bit 21 I2C1RST: I2C1 reset
Set and reset by software.
0: does not reset I2C1
1: resets I2C1
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Bit 20 UART5RST: UART5 reset
Set and reset by software.
0: does not reset UART5
1: resets UART5
Bit 19 UART4RST: UART4 reset
Set and reset by software.
0: does not reset UART4
1: resets UART4
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
0: does not reset USART3
1: resets USART3
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: does not reset USART2
1: resets USART2
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST: SPI3 reset
Set and cleared by software.
0: does not reset SPI3
1: resets SPI3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: does not reset SPI2
1: resets SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: does not reset the window watchdog
1: resets the window watchdog
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIMER1RST: LPTimer1 reset
Set and reset by software.
0: does not reset timer 1
1: resets timer 1
Bit 8 TIM14RST: TIM14 reset
Set and cleared by software.
0: does not reset TIM14
1: resets TIM14
Bit 7 TIM13RST: TIM13 reset
Set and cleared by software.
0: does not reset TIM13
1: resets TIM13
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RM0430
Reset and clock control (RCC) for STM32F413/423
Bit 6 TIM12RST: TIM12 reset
Set and cleared by software.
0: does not reset TIM12
1: resets TIM12
Bit 5 TIM7RST: TIM7 reset
Set and cleared by software.
0: does not reset TIM7
1: resets TIM7
Bit 4 TIM6RST: TIM6 reset
Set and cleared by software.
0: does not reset TIM6
1: resets TIM6
Bit 3 TIM5RST: TIM5 reset
Set and cleared by software.
0: does not reset TIM5
1: resets TIM5
Bit 2 TIM4RST: TIM4 reset
Set and cleared by software.
0: does not reset TIM4
1: resets TIM4
Bit 1 TIM3RST: TIM3 reset
Set and cleared by software.
0: does not reset TIM3
1: resets TIM3
Bit 0 TIM2RST: TIM2 reset
Set and cleared by software.
0: does not reset TIM2
1: resets TIM2
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Reset and clock control (RCC) for STM32F413/423
6.3.10
RM0430
RCC APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
DFSDM2 DFSDM1
Res.
RST
RST
15
14
13
12
11
10
SYSCFG SPI4
Res.
RST
RST
SPI1
RST
SDIO
RST
rw
rw
rw
rw
Res.
23
22
Res.
SAI1
RST
rw
rw
9
8
7
6
Res.
ADC
RST
UART10
RST
UART9
RST
rw
rw
rw
20
Res.
SPI5
RST
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 DFSDM2RST: DFSDM2 reset
Set and cleared by software.
0: does not reset DFSDM2
1: resets DFSDM2
Bit 24 DFSDM1RST: DFSDM1 reset
Set and cleared by software.
0: does not reset DFSDM1
1: resets DFSDM1
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI1RST: SAI1 reset
Set and reset by software.
0: does not reset SAI1
1: resets SAI1
Bit 21 Reserved, must be kept at reset value.
Bit 20 SPI5RST: SPI5RST
This bit is set and cleared by software.
0: does not reset SPI5
1: resets SPI5
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11RST: TIM11 reset
Set and cleared by software.
0: does not reset TIM11
1: resets TIM11
Bit 17 TIM10RST: TIM10 reset
Set and cleared by software.
0: does not reset TIM10
1: resets TIM10
Bit 16 TIM9RST: TIM9 reset
Set and cleared by software.
0: does not reset TIM9
1: resets TIM9
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19
18
17
16
Res.
TIM11
RST
TIM10
RST
TIM9
RST
rw
rw
rw
2
1
0
Res.
TIM8
RST
TIM1
RST
rw
rw
rw
5
4
USART6 USART1
RST
RST
rw
rw
3
Res.
RM0430
Reset and clock control (RCC) for STM32F413/423
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGRST: System configuration controller reset
Set and cleared by software.
0: does not reset the System configuration controller
1: resets the System configuration controller
Bit 13 SPI4RST: SPI4 reset
Set and reset by software.
0: does not reset SPI4
1: resets SPI4
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: does not reset SPI1
1: resets SPI1
Bit 11 SDIORST: SDIO reset
Set and cleared by software.
0: does not reset the SDIO module
1: resets the SDIO module
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 ADCRST: ADC interface reset
Set and cleared by software.
0: does not reset the ADC interface
1: resets the ADC interface
Bit 7 UART10RST: UART10 reset
Set and cleared by software.
0: does not reset UART10
1: resets UART10
Bit 6 UART9RST: UART9 reset
Set and cleared by software.
0: does not reset UART9
1: resets UART9
Bit 5 USART6RST: USART6 reset
Set and cleared by software.
0: does not reset USART6
1: resets USART6
Bit 4 USART1RST: USART1 reset
Set and cleared by software.
0: does not reset USART1
1: resets USART1
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Reset and clock control (RCC) for STM32F413/423
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8RST: TIM8 reset
Set and cleared by software.
0: does not reset TIM8
1: resets TIM8
Bit 0 TIM1RST: TIM1 reset
Set and cleared by software.
0: does not reset TIM1
1: resets TIM1
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RM0430
Reset and clock control (RCC) for STM32F413/423
6.3.11
RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
Address offset: 0x30
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
22
15
14
13
12
11
10
9
8
7
6
5
4
Res.
GPIOH
EN
GPIOG
EN
GPIOF
EN
GPIOE
EN
rw
rw
rw
rw
rw
Res.
Res.
Res.
CRCEN
Res.
Res.
Res.
rw
21
DMA2EN DMA1EN
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
3
2
1
0
rw
GPIOD GPIOC GPIOB GPIOA
EN
EN
EN
EN
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 21 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 GPIOHEN: IO port H clock enable
Set and reset by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bit 6 GPIOGEN: IO port G clock enable
Set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Bit 5 GPIOFEN: IO port F clock enable
Set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
Bit 4 GPIOEEN: IO port E clock enable
Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
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Reset and clock control (RCC) for STM32F413/423
Bit 3 GPIODEN: IO port D clock enable
Set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 2 GPIOCEN: IO port C clock enable
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
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RM0430
Reset and clock control (RCC) for STM32F413/423
6.3.12
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
for STM32F413xx
Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OTGFS
EN
RNG
EN
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSEN: USB OTG FS clock enable
Set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Bit 6 RNGEN: RNG clock enable
Set and cleared by software.
0: RNG clock disabled
1: RNG clock enabled
Bits 5:0 Reserved, must be kept at reset value.
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Reset and clock control (RCC) for STM32F413/423
6.3.13
RM0430
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
for STM32F423xx
Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OTGFS
EN
RNG
EN
Res.
CRYP
EN
Res.
Res.
Res.
Res.
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSEN: USB OTG FS clock enable
Set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Bit 6 RNGEN: RNG clock enable
Set and cleared by software.
0: RNG clock disabled
1: RNG clock enabled
Bit 5 Reserved, must be kept at reset value.
Bit 4 CRYPEN: CRYP clock enable
Set and reset by software.
0: CRYP clock disabled
1: CRYP clock enabled
Bits 3:0 Reserved, must be kept at reset value.
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RM0430
Reset and clock control (RCC) for STM32F413/423
6.3.14
RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
QSPI
EN
FSMC
EN
rw
rw
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPIEN: QUADSPI memory controller module clock enable
Set and cleared by software.
0: QUADSPI clock disabled
1: QUADSPI clock enabled
Bit 0 FSMCEN: Flexible memory controller module clock enable
Set and cleared by software.
0: FSMC module clock disabled
1: FSMC module clock enabled
6.3.15
RCC APB1 peripheral clock enable register (RCC_APB1ENR)
Address offset: 0x40
Reset value: 0x0000 0400
Access: no wait state, word, half-word and byte access.
31
30
UART8 UART7
EN
EN
29
28
27
26
25
24
23
22
21
DAC
EN
PWR
EN
CAN3
EN
CAN2
EN
CAN1
EN
I2CFMP1
EN
I2C3
EN
I2C2
EN
I2C1
EN
20
19
18
UART5 UART4 USART3 USART2
EN
EN
EN
EN
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI3
EN
SPI2
EN
TIM14
EN
TIM13
EN
TIM12
EN
TIM7
EN
TIM6
EN
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Res.
Res.
WWDG RTCAPB LPTIMER1
EN
EN
EN
rw
rw
rw
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Reset and clock control (RCC) for STM32F413/423
Bit 31 UART8EN: UART8 clock enable
Set and reset by software.
0: UART8 clock disabled
1: UART8 clock enable
Bit 30 UART7EN: UART7 clock enable
Set and reset by software.
0: UART7 clock disabled
1: UART7 clock enable
Bit 29 DACEN: DAC clock enable
Set and reset by software.
0: DAC clock disabled
1: DAC clock enable
Bit 28 PWREN: Power interface clock enable
Set and reset by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 CAN3EN: CAN 3 clock enable
This bit is set and cleared by software.
0: CAN 3 clock disabled
1: CAN 3 clock enabled
Bit 26 CAN2EN: CAN 2 clock enable
This bit is set and cleared by software.
0: CAN 2 clock disabled
1: CAN 2 clock enabled
Bit 25 CAN1EN: CAN 1 clock enable
This bit is set and cleared by software.
0: CAN 1 clock disabled
1: CAN 1 clock enabled
Bit 24 I2CFMP1EN: I2CFMP1 clock enable
This bit is set and cleared by software.
0: I2CFMP1 clock disabled
1: I2CFMP1 clock enabled
Bit 23 I2C3EN: I2C3 clock enable
Set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
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RM0430
Reset and clock control (RCC) for STM32F413/423
Bit 20 UART5EN: UART 5 clock enable
Set and RESET by software.
0: UART 5 clock disabled
1: UART 5 clock enabled
Bit 19 UART4EN: UART 4 clock enable
Set and cleared by software.
0: UART 4 clock disabled
1: UART 4 clock enabled
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI3 clock enable
Set and cleared by software.
0: SPI3 clock disabled
1: SPI3 clock enabled
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bit 10 RTCAPBEN: clock enable
Set and cleared by software.
0: The register clock interface of the RTC (APB) is disabled
1: The register clock interface of the RTC (APB) is enabled (default after reset)
Bit 9 LPTIMER1EN: LPTimer 1 clock enable
Set and reset by software.
0: LPTimer 1 clock disabled
1: LPTimer 1 clock enabled
Bit 8 TIM14EN: TIM14 reset
Set and cleared by software.
0: does not reset TIM14
1: resets TIM14
Bit 7 TIM13EN: TIM13 reset
Set and cleared by software.
0: does not reset TIM13
1: resets TIM13
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Reset and clock control (RCC) for STM32F413/423
Bit 6 TIM12EN: TIM12 reset
Set and cleared by software.
0: does not reset TIM12
1: resets TIM12
Bit 5 TIM7EN: TIM7 reset
Set and cleared by software.
0: does not reset TIM7
1: resets TIM7
Bit 4 TIM6EN: TIM6 reset
Set and cleared by software.
0: does not reset TIM6
1: resets TIM6
Bit 3 TIM5EN: TIM5 clock enable
Set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
Bit 2 TIM4EN: TIM4 clock enable
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 clock enable
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
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Reset and clock control (RCC) for STM32F413/423
6.3.16
RCC APB2 peripheral clock enable register
(RCC_APB2ENR)
Address offset: 0x44
Reset value: 0x0000 8000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
DFSDM2 DFSDM1
Res.
EN
EN
rw
rw
15
14
13
12
11
10
9
8
SPI1
EN
SDIO
EN
Res.
Res.
ADC1
EN
rw
rw
EXTIT
EN
rw
SYSCF
SPI4EN
GEN
rw
rw
23
22
Res.
SAI1
EN
21
20
Res.
SPI5
EN
rw
7
6
rw
rw
18
17
16
Res.
TIM11
EN
TIM10
EN
TIM9
EN
rw
5
4
UART10 UART9 USART6 USART1
EN
EN
EN
EN
rw
19
rw
rw
rw
rw
rw
3
2
1
0
Res.
Res.
TIM8
EN
TIM1
EN
rw
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 DFSDM2EN: DFSDM2 clock enable
Set and cleared by software
0: DFSDM2 clock disabled
1: DFSDM2 clock enabled
Bit 24 DFSDM1EN: DFSDM1 clock enable
Set and cleared by software
0: DFSDM1 clock disabled
1: DFSDM1 clock enabled
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI1EN:SAI 1 clock enable
Set and cleared by software
0: SAI 1 clock disabled
1: SAI 1 clock enabled
Bit 21 Reserved, must be kept at reset value.
Bit 20 SPI5EN:SPI5 clock enable
Set and cleared by software
0: SPI5 clock disabled
1: SPI5 clock enabled
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11EN: TIM11 clock enable
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Bit 17 TIM10EN: TIM10 clock enable
Set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
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Reset and clock control (RCC) for STM32F413/423
Bit 16 TIM9EN: TIM9 clock enable
Set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
Bit 15 EXTITEN: EXTIT APB SYSCTRL PFREE clock enable
Set and cleared by software.
0: Extit Apb sysctrl pfree clock disabled
1: Extit Apb sysctrl pfree clock enabled
Bit 14 SYSCFGEN: System configuration controller clock enable
Set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
Bit 13 SPI4EN: SPI4 clock enable
Set and reset by software.
0: SPI4 clock disabled
1: SPI4 clock enable
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 SDIOEN: SDIO clock enable
Set and cleared by software.
0: SDIO module clock disabled
1: SDIO module clock enabled
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 ADC1EN: ADC1 clock enable
Set and cleared by software.
0: ADC1 clock disabled
1: ADC1 clock enabled
Bit 7 UART10EN: UART10 clock enable
Set and cleared by software.
0: UART10 clock disabled
1: UART10 clock enabled
Bit 6 UART9EN: USART9 clock enable
Set and cleared by software.
0: USART9 clock disabled
1: USART9 clock enabled
Bit 5 USART6EN: USART6 clock enable
Set and cleared by software.
0: USART6 clock disabled
1: USART6 clock enabled
Bit 4 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
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Reset and clock control (RCC) for STM32F413/423
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8EN: TIM8 clock enable
Set and cleared by software.
0: TIM8 clock disabled
1: TIM8 clock enabled
Bit 0 TIM1EN: TIM1 clock enable
Set and cleared by software.
0: TIM1 clock disabled
1: TIM1 clock enabled
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Reset and clock control (RCC) for STM32F413/423
6.3.17
RM0430
RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x0063 90FF
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
DMA2
LPEN
DMA1
LPEN
rw
rw
6
5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
FLITF
LPEN
Res.
Res.
CRC
LPEN
Res.
Res.
Res.
Res.
rw
20
Res.
Res.
4
3
2
GPIOH GPIOG GPIOF GPIOE GPIOD
LPEN
LPEN LPEN LPEN
LPEN
rw
rw
rw
rw
rw
Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
Set and cleared by software.
0: DMA2 clock disabled during Sleep mode
1: DMA2 clock enabled during Sleep mode
Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode
Set and cleared by software.
0: DMA1 clock disabled during Sleep mode
1: DMA1 clock enabled during Sleep mode
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 SRAM2LPEN: SRAM2interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM2 interface clock disabled during Sleep mode
1: SRAM2 interface clock enabled during Sleep mode
Bit 16 SRAM1LPEN: SRAM1interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM1 interface clock disabled during Sleep mode
1: SRAM1 interface clock enabled during Sleep mode
Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode
Set and cleared by software.
0: Flash interface clock disabled during Sleep mode
1: Flash interface clock enabled during Sleep mode
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 CRCLPEN: CRC clock enable during Sleep mode
Set and cleared by software.
0: CRC clock disabled during Sleep mode
1: CRC clock enabled during Sleep mode
Bits 11:8 Reserved, must be kept at reset value.
RM0430 Rev 9
18
Res.
Bits 31:23 Reserved, must be kept at reset value.
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19
rw
GPIOC
LPEN
rw
17
16
SRAM2 SRAM1
LPEN LPEN
rw
rw
1
0
GPIOB GPIOA
LPEN LPEN
rw
rw
RM0430
Reset and clock control (RCC) for STM32F413/423
Bit 7 GPIOHLPEN: IO port H clock enable during sleep mode
Set and reset by software.
0: IO port H clock disabled during sleep mode
1: IO port H clock enabled during sleep mode
Bit 6 GPIOGLPEN: IO port G clock enable during Sleep mode
Set and cleared by software.
0: IO port G clock disabled during Sleep mode
1: IO port G clock enabled during Sleep mode
Bit 5 GPIOFLPEN: IO port F clock enable during Sleep mode
Set and cleared by software.
0: IO port F clock disabled during Sleep mode
1: IO port F clock enabled during Sleep mode
Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode
Set and cleared by software.
0: IO port E clock disabled during Sleep mode
1: IO port E clock enabled during Sleep mode
Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode
Set and cleared by software.
0: IO port D clock disabled during Sleep mode
1: IO port D clock enabled during Sleep mode
Bit 2 GPIOCLPEN: IO port C clock enable during Sleep mode
Set and cleared by software.
0: IO port C clock disabled during Sleep mode
1: IO port C clock enabled during Sleep mode
Bit 1 GPIOBLPEN: IO port B clock enable during Sleep mode
Set and cleared by software.
0: IO port B clock disabled during Sleep mode
1: IO port B clock enabled during Sleep mode
Bit 0 GPIOALPEN: IO port A clock enable during sleep mode
Set and cleared by software.
0: IO port A clock disabled during Sleep mode
1: IO port A clock enabled during Sleep mode
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Reset and clock control (RCC) for STM32F413/423
6.3.18
RM0430
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F413xx
Address offset: 0x54
Reset value: 0x0000 00C0
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OTGFS RNG
LPEN LPEN
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode
Set and cleared by software.
0: USB OTG FS clock disabled during Sleep mode
1: USB OTG FS clock enabled during Sleep mode
Bit 6 RNGLPEN: RNG clock enable during Sleep mode
Set and cleared by software.
0: RNG clock disabled during Sleep mode
1: RNG clock enabled during Sleep mode
Bits 5:0 Reserved, must be kept at reset value.
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RM0430
Reset and clock control (RCC) for STM32F413/423
6.3.19
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F423xx
Address offset: 0x54
Reset value: 0x0000 00D0
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRYP
LPEN
Res.
Res.
Res.
Res.
OTGFS RNG
LPEN LPEN
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSLPEN: USB OTG FS clock enable during sleep mode
Set and cleared by software.
0: USB OTG FS clock disabled during Sleep mode
1: USB OTG FS clock enabled during Sleep mode
Bit 6 RNGLPEN: RNG clock enable during sleep mode
Set and cleared by software.
0: RNG clock disabled during Sleep mode
1: RNG clock enabled during Sleep mode
Bit 5 Reserved, must be kept at reset value.
Bit 4 CRYPLPEN: CRYPG clock enable during sleep mode
Set and cleared by software.
0: CRYP clock disabled during Sleep mode
1: CRYP clock enabled during Sleep mode
Bits 3:0 Reserved, must be kept at reset value.
6.3.20
RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR)
Address offset: 0x58
Reset value: 0x0000 0003
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
QSPI
LPEN
FSMC
LPEN
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RM0430 Rev 9
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Res.
Res.
Res.
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Reset and clock control (RCC) for STM32F413/423
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPILPEN: QUADSPI memory controller module clock enable during Sleep mode
Set and cleared by software.
0: QUADSPI module clock disabled during Sleep mode
1: QUADSPI module clock enabled during Sleep mode
Bit 0 FSMCLPEN: Flexible memory controller module clock enable during Sleep mode
Set and cleared by software.
0: FSMC clock disabled during Sleep mode
1: FSMC clock enabled during Sleep mode
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6.3.21
Reset and clock control (RCC) for STM32F413/423
RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR)
Address offset: 0x60
Reset value: 0xFFFF CFFF
Access: no wait state, word, half-word and byte access.
31
30
29
UART8 UART7 DAC
LPEN LPEN LPEN
28
27
26
25
PWR
LPEN
CAN3
LPEN
CAN2
LPEN
CAN1
LPEN
24
23
I2CFMP1 I2C3
LPEN
LPEN
22
I2C2
LPEN
21
20
19
18
17
16
I2C1 UART5 UART4 USART3 USART2
LPEN LPEN LPEN
LPEN
LPEN
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI3
LPEN
SPI2
LPEN
Res.
Res.
TIM14
LPEN
TIM13
LPEN
TIM12
LPEN
TIM7
LPEN
TIM6
LPEN
TIM5
LPEN
TIM4
LPEN
TIM3
LPEN
TIM2
LPEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
WWDG RTCAPB LPTIMER1
LPEN
EN
EN
rw
rw
rw
Bit 31 UART8LPEN: UART8 clock enable during Sleep mode
Set and cleared by software.
0: UART8 clock disabled during Sleep mode
1: UART8 clock enabled during Sleep mode
Bit 30 UART7LPEN: UART7 clock enable during Sleep mode
Set and cleared by software.
0: UART7 clock disabled during Sleep mode
1: UART7 clock enabled during Sleep mode
Bit 29 DACLPEN: DAC clock enable during Sleep mode
Set and cleared by software.
0: DAC clock disabled during Sleep mode
1: DAC clock enabled during Sleep mode
Bit 28 PWRLPEN: Power interface clock enable during Sleep mode
Set and cleared by software.
0: Power interface clock disabled during Sleep mode
1: Power interface clock enabled during Sleep mode
Bit 27 CAN3LPEN: CAN3 clock enable during Sleep mode
Set and cleared by software.
0: CAN3 clock disabled during Sleep mode
1: CAN3 clock enabled during Sleep mode
Bit 26 CAN2LPEN: CAN2 clock enable during Sleep mode
Set and cleared by software.
0: CAN2 clock disabled during Sleep mode
1: CAN2 clock enabled during Sleep mode
Bit 25 CAN1LPEN: CAN1 clock enable during Sleep mode
Set and cleared by software.
0: CAN1 clock disabled during Sleep mode
1: CAN1 clock enabled during Sleep mode
Bit 24 I2CFMP1LPEN: I2CFMP1 clock enable during Sleep mode
Set and cleared by software.
0: I2CFMP1 clock disabled during Sleep mode
1: I2CFMP1 clock enabled during Sleep mode
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Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode
Set and cleared by software.
0: I2C3 clock disabled during Sleep mode
1: I2C3 clock enabled during Sleep mode
Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode
Set and cleared by software.
0: I2C2 clock disabled during Sleep mode
1: I2C2 clock enabled during Sleep mode
Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode
Set and cleared by software.
0: I2C1 clock disabled during Sleep mode
1: I2C1 clock enabled during Sleep mode
Bit 20 UART5LPEN: UART5 clock enable during Sleep mode
Set and cleared by software.
0: UART5 clock disabled during Sleep mode
1: UART5 clock enabled during Sleep mode
Bit 19 UART4LPEN: UART4 clock enable during Sleep mode
Set and cleared by software.
0: UART4 clock disabled during Sleep mode
1: UART4 clock enabled during Sleep mode
Bit 18 USART3LPEN: USART3 clock enable during Sleep mode
Set and cleared by software.
0: USART3 clock disabled during Sleep mode
1: USART3 clock enabled during Sleep mode
Bit 17 USART2LPEN: USART2 clock enable during Sleep mode
Set and cleared by software.
0: USART2 clock disabled during Sleep mode
1: USART2 clock enabled during Sleep mode
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3LPEN: SPI3 clock enable during Sleep mode
Set and cleared by software.
0: SPI3 clock disabled during Sleep mode
1: SPI3 clock enabled during Sleep mode
Bit 14 SPI2LPEN: SPI2 clock enable during Sleep mode
Set and cleared by software.
0: SPI2 clock disabled during Sleep mode
1: SPI2 clock enabled during Sleep mode
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode
Set and cleared by software.
0: Window watchdog clock disabled during sleep mode
1: Window watchdog clock enabled during sleep mode
Bit 10 RTCAPBEN: RTC APB clock enable during Sleep mode
Set and cleared by software.
0: RTC APB clock disabled during sleep mode
1: RTC APB watchdog clock enabled during sleep mode
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Reset and clock control (RCC) for STM32F413/423
Bit 9 LPTIMER1EN: TIM14 clock enable during Sleep mode
Set and cleared by software.
0: LPTimer 1 clock disabled during Sleep mode
1: LPTimer 1 clock enabled during Sleep mode
Bit 8 TIM14LPEN: TIM14 clock enable during Sleep mode
Set and cleared by software.
0: TIM14 clock disabled during Sleep mode
1: TIM14 clock enabled during Sleep mode
Bit 7 TIM13LPEN: TIM13 clock enable during Sleep mode
Set and cleared by software.
0: TIM13 clock disabled during Sleep mode
1: TIM13 clock enabled during Sleep mode
Bit 6 TIM12LPEN: TIM12 clock enable during Sleep mode
Set and cleared by software.
0: TIM12 clock disabled during Sleep mode
1: TIM12 clock enabled during Sleep mode
Bit 5 TIM7LPEN: TIM7 clock enable during Sleep mode
Set and cleared by software.
0: TIM7 clock disabled during Sleep mode
1: TIM7 clock enabled during Sleep mode
Bit 4 TIM6LPEN: TIM6 clock enable during Sleep mode
Set and cleared by software.
0: TIM6 clock disabled during Sleep mode
1: TIM6 clock enabled during Sleep mode
Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode
Set and cleared by software.
0: TIM5 clock disabled during Sleep mode
1: TIM5 clock enabled during Sleep mode
Bit 2 TIM4LPEN: TIM4 clock enable during Sleep mode
Set and cleared by software.
0: TIM4 clock disabled during Sleep mode
1: TIM4 clock enabled during Sleep mode
Bit 1 TIM3LPEN: TIM3 clock enable during Sleep mode
Set and cleared by software.
0: TIM3 clock disabled during Sleep mode
1: TIM3 clock enabled during Sleep mode
Bit 0 TIM2LPEN: TIM2 clock enable during Sleep mode
Set and cleared by software.
0: TIM2 clock disabled during Sleep mode
1: TIM2 clock enabled during Sleep mode
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6.3.22
RM0430
RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0317 F9F3
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
Res.
SAI1
LPEN
Res.
Res.
Res.
Res.
Res.
DFSDM2 DFSDM1
Res.
LPEN
LPEN
rw
rw
15
14
13
12
11
10
9
8
7
6
SPI1
LPEN
SDIO
LPEN
Res.
Res.
ADC1
LPEN
UART10
LPEN
UART9
LPEN
rw
rw
rw
rw
rw
EXTIT
LPEN
rw
SYSC
SPI4LP
FG
EN
LPEN
rw
rw
21
20
Res.
SPI5
LPEN
rw
3
USART6 USART1
Res.
LPEN
LPEN
rw
Bit 25 DFSDM2LPEN: DFSDM2 clock enable during Sleep mode
This bit is set and cleared by software
0: DFSDM2 clock disabled during Sleep mode
1: DFSDM2 clock enabled during Sleep mode
Bit 24 DFSDM1LPEN: DFSDM1 clock enable during Sleep mode
This bit is set and cleared by software
0: DFSDM1 clock disabled during Sleep mode
1: DFSDM1 clock enabled during Sleep mode
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI1LPEN: SAI1 clock enable during Sleep mode
This bit is set and cleared by software
0: SAI1 clock disabled during Sleep mode
1: SAI1 clock enabled during Sleep mode
Bit 21 Reserved, must be kept at reset value.
Bit 20 SPI5LPEN: SPI5 clock enable during Sleep mode
This bit is set and cleared by software
0: SPI5 clock disabled during Sleep mode
1: SPI5 clock enabled during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
Set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
RM0430 Rev 9
4
rw
18
17
16
TIM10
LPEN
TIM9
LPEN
rw
rw
rw
2
1
0
Res.
TIM8
LPEN
TIM1
LPEN
rw
rw
TIM11
Res.
LPEN
rw
5
Bits 31:26 Reserved, must be kept at reset value.
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Reset and clock control (RCC) for STM32F413/423
Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
Set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Bit 15 EXTITLPEN: EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode
Set and cleared by software.
0: EXTIT APB and SYSCTRL PFREE clock disabled during Sleep mode
1: EXTIT APB and SYSCTRL PFREE clock enabled during Sleep mode
Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
Set and cleared by software.
0: System configuration controller clock disabled during Sleep mode
1: System configuration controller clock enabled during Sleep mode
Bit 13 SPI4LPEN: SPI4 clock enable during sleep mode
Set and reset by software.
0: SPI4 clock disabled during sleep mode
1: SPI4 clock enabled during sleep mode
Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode
Set and cleared by software.
0: SPI1 clock disabled during Sleep mode
1: SPI1 clock enabled during Sleep mode
Bit 11 SDIOLPEN: SDIO clock enable during Sleep mode
Set and cleared by software.
0: SDIO module clock disabled during Sleep mode
1: SDIO module clock enabled during Sleep mode
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 ADC1LPEN: ADC1 clock enable during Sleep mode
Set and cleared by software.
0: ADC1 clock disabled during Sleep mode
1: ADC1 clock disabled during Sleep mode
Bit 7 UART10LPEN: UART10 clock enable during Sleep mode
Set and cleared by software.
0: UART10 clock disabled during Sleep mode
1: UART10 clock enabled during Sleep mode
Bit 6 UART9LPEN: UART9 clock enable during Sleep mode
Set and cleared by software.
0: UART9 clock disabled during Sleep mode
1: UART9 clock enabled during Sleep mode
Bit 5 USART6LPEN: USART6 clock enable during Sleep mode
Set and cleared by software.
0: USART6 clock disabled during Sleep mode
1: USART6 clock enabled during Sleep mode
Bit 4 USART1LPEN: USART1 clock enable during Sleep mode
Set and cleared by software.
0: USART1 clock disabled during Sleep mode
1: USART1 clock enabled during Sleep mode
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Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8LPEN: TIM8 clock enable during Sleep mode
Set and cleared by software.
0: TIM8 clock disabled during Sleep mode
1: TIM8 clock enabled during Sleep mode
Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode
Set and cleared by software.
0: TIM1 clock disabled during Sleep mode
1: TIM1 clock enabled during Sleep mode
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Reset and clock control (RCC) for STM32F413/423
6.3.23
RCC Backup domain control register (RCC_BDCR)
Address offset: 0x70
Reset value: 0x0000 0000
Note:
Reset by Backup domain reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control
register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are
write-protected and the DBP bit in the Section 5.4.1: PWR power control register
(PWR_CR) has to be set before these can be modified. Refer to Section 5.4.2: PWR power
control/status register (PWR_CSR) for further information. These bits are only reset after a
Backup domain Reset (see Section 6.1.3: Backup domain reset). Any internal or external
Reset will not have any effect on these bits.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BDRST
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RTCEN
Res.
Res.
Res.
Res.
Res.
RTCSEL[1:0]
Res.
Res.
Res.
Res.
rw
rw
rw
rw
0
LSEMOD LSEBYP LSERDY LSEON
rw
rw
r
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
can be used to reset them.
00: No clock
01: LSE oscillator clock used as the RTC clock
10: LSI oscillator clock used as the RTC clock
11: HSE oscillator clock divided by a programmable prescaler (selection through the
RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC
clock
Bits 7:4 Reserved, must be kept at reset value.
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RM0430
Bit 3 LSEMOD: External low-speed oscillator bypass
Set and reset by software to select crystal mode for low speed oscillator. Two power modes
are available.
0: LSE oscillator “low power” mode selection
1: LSE oscillator “high drive” mode selection
Bit 2 LSEBYP: External low-speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the LSE clock is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: External low-speed oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: LSE clock not ready
1: LSE clock ready
Bit 0 LSEON: External low-speed oscillator enable
Set and cleared by software.
0: LSE clock OFF
1: LSE clock ON
6.3.24
RCC clock control &amp; status register (RCC_CSR)
Address offset: 0x74
Reset value: 0x0E00 0000
Note:
Reset by system reset, except reset flags by power reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31
30
LPWR WWDG
RSTF RSTF
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IWDG
RSTF
SFT
RSTF
POR
RSTF
PIN
RSTF
BORRS
TF
RMVF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
0
r
r
r
r
r
r
r
rt_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LSIRDY LSION
r
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Reset and clock control (RCC) for STM32F413/423
Bit 31 LPWRRSTF: Low-power reset flag
Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Low-power management
reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
Set by hardware when an independent watchdog reset from VDD domain occurs.
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Bit 26 PINRSTF: PIN reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 BORRSTF: BOR reset flag
Cleared by software by writing the RMVF bit.
Set by hardware when a POR/PDR or BOR reset occurs.
0: No POR/PDR or BOR reset occurred
1: POR/PDR or BOR reset occurred
Bit 24 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
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RM0430
Bits 23:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low-speed oscillator ready
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.
0: LSI RC oscillator not ready
1: LSI RC oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable
Set and cleared by software.
0: LSI RC oscillator OFF
1: LSI RC oscillator ON
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Reset and clock control (RCC) for STM32F413/423
6.3.25
RCC spread spectrum clock generation register (RCC_SSCGR)
Address offset: 0x80
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
The spread spectrum clock generation is available only for the main PLL.
The RCC_SSCGR register must be written either before the main PLL is enabled or after
the main PLL disabled.
Note:
For full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to
the “Electrical characteristics” section in your device datasheet.
31
30
29
28
SSCG
EN
SPREAD
SEL
Res.
Res.
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
7
6
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
27
26
25
24
rw
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
INCSTEP[14:3]
INCSTEP[2:0]
rw
23
MODPER[12:0]
rw
Bit 31 SSCGEN: Spread spectrum modulation enable
Set and cleared by software.
0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)
1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)
Bit 30 SPREADSEL: Spread Select
Set and cleared by software.
To write before to set CR[24]=PLLON bit.
0: Center spread
1: Down spread
Bits 29:28 Reserved, must be kept at reset value.
Bits 27:13 INCSTEP[14:0]: Incrementation step
Set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile amplitude.
Bits 12:0 MODPER[12:0]: Modulation period
Set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile period.
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6.3.26
RM0430
RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
Address offset: 0x84
Reset value: 0x2400 3010
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLLI2S clock outputs according to the formulas:
•
31
30
Res.
15
f(VCO clock) = f(PLLI2S clock input) &times; (PLLI2SN / PLLI2SM)
•
f(USB OTG FS, SDIO, RNG clock output) = f(VCO clock) / PLLQ
•
f(DFSDM, I2S clock output) = f(VCO clock) / PLLR
29
28
27
PLLI2SR[2:0]
26
25
24
PLLI2SQ[3:0]
rw
rw
rw
rw
14
13
12
11
Res.
23
Res.
rw
rw
rw
10
9
8
22
21
20
rw
rw
rw
rw
18
17
16
rw
7
6
5
4
PLLI2SN[8:0]
rw
19
Res Res Res Res
Res. Res.
PLLI2SSRC
.
.
.
.
3
2
1
0
rw
rw
PLLI2SM[5:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 PLLI2SR[2:0]: PLLI2S division factor for I2S clocks
Set and cleared by software to control the I2S clock frequency. These bits should be written
only if the PLLI2S is disabled. The factor must be chosen in accordance with the prescaler
values inside the I2S peripherals, to reach 0.3% error when using standard crystals and 0%
error with audio crystals. For more information about I2S clock frequency and precision, refer
to Section 29.6.4: Clock generator in the I2S chapter.
Caution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.
I2S clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7
000: PLLR = 0, wrong configuration
001: PLLR = 1, wrong configuration
010: PLLR = 2
...
111: PLLR = 7
Bits 27:24 PLLI2SQ[3:0]: PLLI2S division factor for USB OTG FS/SDIO/RNG clock
Set and cleared by software to control the USB OTG FS/SDIO/RNG clock frequency. These
bits can be written only when the PLLI2S is disabled.
USB OTG FS/SDIO/RNG clock frequency = VCO frequency / PLLI2SQ with 2 ≤ PLLI2SQ ≤
15
0000: PLLI2SQ = 0, wrong configuration
0001: PLLI2SQ = 1, wrong configuration
0010: PLLI2SQ = 2
0011: PLLI2SQ = 3
0100: PLLI2SQ = 4
0101: PLLI2SQ = 5
...
1111: PLLI2SQ = 15
Bit 23 Reserved, must be kept at reset value.
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RM0430
Reset and clock control (RCC) for STM32F413/423
Bit 22 PLLI2SSRC: PLLI2S entry clock source
Set and cleared by software to select PLLI2S clock source. This bit can be written only when
PLLI2S is disabled.
0: HSE or HSI depending on PLLSRC of PLLCFGR
1: external AFI clock (CK_I2S_EXT) selected as PLL clock entry
Bits 21:15 Reserved, must be kept at reset value.
Bits 14:6 PLLI2SN[8:0]: PLLI2S multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLLI2S is disabled. Only half-word and word accesses are allowed to
write these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output frequency
is between 100 and 432 MHz. With VCO input frequency ranges from 1 to 2 MHz
(refer to Figure 14 and divider factor M of the RCC PLL configuration register
(RCC_PLLCFGR))
VCO output frequency = VCO input frequency &times; PLLI2SN with 50 ≤ PLLI2SN ≤ 432
000000000: PLLI2SN = 0, wrong configuration
000000001: PLLI2SN = 1, wrong configuration
...
001100010: PLLI2SN = 50
...
001100011: PLLI2SN = 99
001100100: PLLI2SN = 100
001100101: PLLI2SN = 101
001100110: PLLI2SN = 102
...
110110000: PLLI2SN = 432
110110000: PLLI2SN = 433, wrong configuration
...
111111111: PLLI2SN = 511, wrong configuration
Note: Between 50 and 99 multiplication factors are possible for VCO input frequency higher
than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency
as specified above.
Bits 5:0 PLLI2SM[5:0]: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO.
These bits can be written only when the PLL and PLLI2S are disabled.
Caution: The software has to set these bits correctly to ensure that the VCO input frequency
ranges from 1 to 2 MHz.It is recommended to select a frequency of 2 MHz to limit
PLL jitter.
VCO input frequency = PLL input clock frequency / PLLI2SM with 2 ≤ PLLI2SM ≤ 63
000000: PLLI2SM = 0, wrong configuration
000001: PLLI2SM = 1, wrong configuration...
000010: PLLI2SM = 2
000011: PLLI2SM = 3
000100: PLLI2SM = 4
.......
111110: PLLI2SM = 62
111111: PLLI2SM = 63
RM0430 Rev 9
177/1321
184
Reset and clock control (RCC) for STM32F413/423
6.3.27
RM0430
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
Address offset: 0x8C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
CKDFSD
M1SEL
30
29
26
25
24
21
20
rw
rw
rw
rw
rw
rw
rw
rw
rw
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
PLLDIVR[4:0]
rw
rw
rw
rw
TIMPRE
22
I2S2SRC[1:0]
rw
I2S1SRC[1:0]
23
SAI1BSRC
[1:0]
Res.
CKDFSD CKDFSD
M1ASEL M2ASEL
rw
27
Res.
rw
15
28
rw
SAI1ASRC[1:0]
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
PLLI2SDIVR[4:0]
rw
rw
rw
rw
rw
Bit 31 CKDFSDM1SEL: DFSDM1 &amp; DFSDM2 Kernel clock selection.
0: APB2 clock USED as Kernel clock
1: System clock used as Kernel clock
Bits 30:29 Reserved, must be kept at reset value.
Bits 28:27 I2S2SRC: I2S APB2 clocks source selection (I2S1/4/5)
Set and reset by software.
These bits should be written when the PLL and PLLI2S are disabled.
00: I2S APB2 clock frequency = f(PLLI2S_R)
01: I2S APB2 clock frequency = external I2S clock from pads - Alternate function input
frequency
10: I2S APB2 clock frequency = f(PLL_R)
11: I2S APB2 clock frequency = HSI/HSE depending on PLLSRC (PLLCFGR(22))
Bits 26:25 I2S1SRC: I2S APB1 clocks source selection (I2S2/3)
Set and reset by software to control the frequency of the APB1 I2S clock.
These bits should be written when the PLL and PLLI2S are disabled.
00: I2S APB1 clock frequency = f(PLLI2S_R)
01: I2S APB1 clock frequency = external I2S clock from pads - alternate function input
frequency
10: I2S APB1 clock frequency = f(PLL_R)
11: I2S APB1 clock frequency = HSI/HSE depending on PLLSRC (PLLCFGR(22))
Bit 24 TIMPRE: Timers clocks prescalers selection
Set and reset by software to control the clock frequency of all the timers kernels
(ck_tim &amp; ck_tgo) either on APB1 or APB2 domain.
0: The Timers kernels clock prescaler is equal to HPRE if PPREx is corresponding to division
by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4
or more. (Fck_tim = 2*Fck_pclk).
1: The Timers kernels clock prescaler is equal to HPRE if PPREx is corresponding to division
by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by
8 or more. (Fck_tim = 4 * Fck_pclk).
178/1321
RM0430 Rev 9
RM0430
Reset and clock control (RCC) for STM32F413/423
Bits 23:22 SAI1BSRC[1:0]: SAI1 B clock selection
Set and reset by software.
00: PLLI2S_R divided (R2) as SAI1 B clock
01: I2S_CLIN as SAI1 B clock
00: PLL_R divided (R1) as SAI1 B clock
11: HS_CK as SAI1 B clock
Bits 21:20 SAI1ASRC[1:0]: SAI1 A clock selection
Set and reset by software.
00: PLLI2S_R divided (R2) as SAI1 A clock
01: I2S_CLIN as SAI1 A clock
00: PLL_R divided (R1) as SAI1 A clock
11: HS_CK as SAI1 A clock
Bits 19:16 Reserved, must be kept at reset value.
Bit 15 CKDFSDM1ASEL: DFSDM1 audio clock selection.
0: CK_I2S_APB1 selected as audio clock
1: CK_I2S_APB2 selected as audio clock
Bit 14 CKDFSDM2ASEL: DFSDM2 audio clock selection.
0: CK_I2S_APB1 selected as audio clock
1: CK_I2S_APB2 selected as audio clock
Bits 13:9 PLLDIVR[4:0]: PLL division factor for SAI1 A/B clock
Set and reset by software to control the division factor of PLL_R1 clock.
These bits should be written when the PLL is disabled.
00000: PLL_R1 = wrong configuration
00001: PLL_R1 = div/1
....
10000: PLL_R1 = div/16
....
11111: PLL_R1 = div/31
Bits 8:5 Reserved, must be kept at reset value.
Bits 4:0 PLLI2SDIVR[4:0]: PLLI2S division factor for SAI1 A/B clock
Set and reset by software to control the division factor of PLLI2S_R2 clock.
These bits should be written when the PLLI2S is disabled.
00000: PLLI2S_R2 = wrong configuration
00001: PLLI2S_R2 = div/1
....
10000: PLLI2S_R2 = div/16
....
11111: PLLI2S_R2 = div/31
RM0430 Rev 9
179/1321
184
Reset and clock control (RCC) for STM32F413/423
6.3.28
RM0430
RCC clocks gated enable register (CKGATENR)
Address offset: 0x90
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
This register allows to enable or disable the clock gating for the specified IPs.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AHB2APB2
_CKEN
AHB2APB1
_CKEN
rw
rw
EVTCL RCC
FLITF SRAM SPARE CM4DBG
_CKEN _CKEN _CKEN _CKEN _CKEN _CKEN
rw
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 EVTCL_CKEN:
0: the clock gating is enabled
1: the cock gating is disabled, the clock is always enabled
Bit 6 RCC_CKEN: RCC clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 5 FLITF_CKEN: Flash Interface clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 4 SRAM_CKEN: SRAM (SRAM1 and SRAM2) controller clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 3 SPARE_CKEN: Spare clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 2 CM4DBG_CKEN: Cortex M4 ETM clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 1 AHB2APB2_CKEN: AHB to APB2 Bridge clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 0 AHB2APB1_CKEN: AHB to APB1 Bridge clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
180/1321
RM0430 Rev 9
RM0430
Reset and clock control (RCC) for STM32F413/423
6.3.29
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2)
Address offset: 0x94
Reset value: 0x0000 0000
This register allows to enable or disable the clock gating for the specified IPs.
31
30
LPTIMER1
SEL[1:0]
29
28
27
Res.
SDIO
SEL
CK48M
SEL
26
25
24
23
22
21
20
19
18
17
16
I2CFMP1
SEL[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
15
14
13
12
11
10
9
8
rw
7
rw
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:30 LPTIMER1SEL[1:0]: LPTIMER1 kernel clock source selection.
00: APB clock selected as LPTIMER1 clock
01: HSI clock selected as LPTIMER1 clock
10: LSI clock selected as LPTIMER1 clock
11: LSE clock selected as LPTIMER1 clock
Bit 29 Reserved, must be kept at reset value.
Bit 28 SDIOSEL: SDIO clock selection.
0: CK_48MHz (see CK48MSEL bit definition)
1: clock system
Bit 27 CK48MSEL: SDIO/USBFS clock selection.
0: f(PLL_Q)
1: f(PLLI2S_Q)
Bits 26:24 Reserved, must be kept at reset value.
Bits 23:22 I2CFMP1SEL[1:0]: I2CFMP1 kernel clock source selection
00: APB clock selected as I2CFMP1 clock
01: System clock selected as I2CFMP1 clock
10: HSI clock selected as I2CFMP1 clock
11: APB clock selected as I2CFMP1 (same as “00”)
Bits 21:0 Reserved, must be kept at reset value.
RM0430 Rev 9
181/1321
184
RCC_
AHB1ENR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2EN
DMA1EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRCEN
Res.
Res.
Res.
Res.
0x34
RCC_
AHB2ENR
Res.
Res.
Res.
182/1321
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CAN1RST
I2C1RST
UART5RST
UART4 RST
Res.
SPI5RST
Res.
RM0430 Rev 9
SPI1RST
GPIOCEN
GPIOBEN
GPIOAEN
Res.
Res.
Res.
TIM1RST
TIM8RST
TIM2RST
TIM3RST
TIM4RST
TIM5RST
TIM6RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FSMCRST
QSPIRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRCRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSSF
LSIRDYIE
LSERDYIE
HSIRDYIE
HSERDYIE
PLLRDYIE
PLLI2SRDYIE
Res.
Res.
LSIRDYC
LSERDYC
HSIRDYC
HSERDYC
PLLRDYC
GPIOARST
GPIOBRST
GPIOCRST
GPIODRST
LSIRDYF
LSERDYF
HSIRDYF
HSERDYF
PLLRDYF
GPIOFRST PLLI2SRDYF
GPIOGRST
CRYPRST GPIOERST
Res.
RNGRST
OTGFSRST GPIOHRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSSC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA1RST PLLI2SRDYC
DMA2RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PLLSRC
Res.
MCO1[1:0]
PLL ON
Res.
Res.
Res.
PPRE1[2:0]
PPRE2[2:0]
SW[1:0]
SWS[1:0]
Res.
Res.
PLLP[1:0]
HSEBYP
Res.
HSEON
HSERDY
Res.
CSSON
Res.
PLL RDY
PLL I2SON
Res.
PLL I2SRDY
MCO1PRE[2:0]
MCO2PRE[2:0]
HSION
HSIRDY
Res.
HSITRIM[4:0]
Res.
Res.
USART1RST
TIM7RST
TIM12RST
TIM13RST
TIM14RST
LPTIMER1RST
Res.
Res.
Res.
HPRE[3:0]
GPIODEN
Res.
WWDGRST
Res.
Res.
PLLN[8:0]
Res.
CRYPEN(1) GPIOEEN
UART9RST
USART6RST
GPIOFEN
UART10RST
ADCRST
Res.
Res.
SDIORST
GPIOGEN
Reserved
Res.
Reserved
HSICAL[7:0]
RNGEN
0x28
0x2C
Res.
0x1C
SPI2RST
Res.
RCC_
AHB3RSTR
SP45RST
Res.
0x18
RTCPRE[4:0]
SYSCFGRST
RCC_
AHB2RSTR
SPI3RST
0x14
Res.
RCC_
AHB1RSTR
Res.
0x10
TIM9RST
RCC_
CIR
Res.
0x0C
Res.
RCC_
CFGR
USART2RST
0x08
PLLQ[3:0]
TIM10RST
Res.
PLLR[2:0]
USART3RST
I2C2RST
SAI1RST
Res.
RCC_
PLLCFGR
Res.
Res.
0x04
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCC_
CR
MCO2[1:0]
0x00
Res.
Register
name
Res.
Addr.
offset
TIM11RST
I2C3RST
Res.
DFSDM1RST I2CFMP1RST
CAN2RST
Res.
DFSDM2RST
CAN3RST
Res.
Res.
DACRST
UART7RST
RCC_
APB2RSTR
PWRRST
UART8RST
0x24
Res.
RCC_
APB1RSTR
Res.
0x20
Res.
6.3.30
OTGFSEN GPIOHEN
0x30
Res.
Reset and clock control (RCC) for STM32F413/423
RM0430
RCC register map
Table 24 gives the register map and reset values
Table 24. RCC register map and reset values for STM32F413/423
PLLM[5:0]
Reserved
Res.
Res.
Res.
Res.
0x78
Reserved
0x7C
Reserved
RM0430 Rev 9
TIM8LPEN
TIM1LPEN
LSERDY
LSEON
LSIRDY
LSION
Res.
LSEMOD
Res.
Res.
USART1LPEN
Res.
Res.
LSEBYP
USART6LPEN
Res.
Res.
Res.
UART9LPEN
Res.
Res.
ADC1LPEN
Res.
Res.
SDIOLPEN
SPI1LPEN
SPI4LPEN
SYSCFGLPEN
UART10LPEN
Reserved
Res.
Reserved
Res.
0x68
0x6C
EXTITLPEN
TIM9LPEN
TIM10LPEN
TIM2LPEN
TIM3LPEN
TIM4LPEN
TIM5LPEN
TIM6LPEN
TIM7LPEN
TIM12LPEN
TIM13LPEN
TIM14LPEN
LPTIMER1EN
RTCAPBEN
WWDGLPEN
Res.
Res.
SPI2LPEN
SPI3LPEN
Res.
USART2LPEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FSMCLPEN
QSPILPEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRCLPEN
Res.
Res.
FLITFLPEN
SRAM1LPEN
SRAM2LPEN
Res.
Res.
Res.
DMA1LPEN
DMA2LPEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CAN3EN
CAN2EN
CAN1EN
Res.
Res.
DFSDM2EN
I2C1EN
UART5EN
UART4 EN
Res.
SPI5EN
Res.
GPIOCLPEN
GPIOBLPEN
GPIOALPEN
Res.
Res.
TIM1EN
TIM8EN
Res.
Res.
USART1EN
(1) GPIOELPEN
GPIODLPEN
USART6EN
UART9EN
UART10EN
ADC1EN
Res.
Res.
SDIOEN
SPI1EN
SPI4EN
SYSCFGEN
EXTITEN
TIM9EN
TIM10EN
TIM2EN
TIM3EN
TIM4EN
TIM5EN
TIM6EN
TIM7EN
TIM12EN
TIM13EN
TIM14EN
LPTIMER1EN
RTCAPBEN
WWDGEN
Res.
Res.
SPI2EN
SPI3EN
Res.
USART2EN
USART3EN
I2C2EN
SAI1EN
TIM11EN
I2C3EN
Res.
DFSDM1EN I2CFMP1EN
DACEN
PWREN
Res.
UART7EN
Res.
Res.
UART8EN
Res.
GPIOFLPEN
GPIOGLPEN
Res.
CRYPLPEN
Res.
Res.
RNGLPEN
OTGFSLPEN GPIOHLPEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
Res.
UART4 LPEN
Res.
Res.
Res.
Res.
Reserved
RTCSEL[1:0]
Res.
Res.
UART5LPEN
SPI5LPEN
USART3LPEN
I2C1LPEN
SAI1LPEN
TIM11LPEN
I2C2LPEN
Res.
Res.
Res.
0x48
0x4C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RTCEN
Res.
Res.
I2C3LPEN
Res.
0x5C
Res.
Res.
Res.
DFSDM1LPEN I2CFMP1LPEN
Res.
RCC_
AHB3LPENR
BDRST
Res.
RMVF
CAN1LPEN
DFSDM2LPEN
Res.
0x58
Res.
Res.
BORRSTF
CAN2LPEN
Res.
RCC_
AHB2LPENR
Res.
Res.
PADRSTF
CAN3LPEN
RCC_
APB2LPENR
Res.
0x54
Res.
Res.
PORRSTF
0x64
DACLPEN
RCC_
AHB1LPENR
Res.
0x50
Res.
RCC_
APB2ENR
PWRLPEN
UART7LPEN
0x44
Res.
UART8LPEN
RCC_
APB1ENR
Res.
RCC_
APB1LPENR
Res.
0x40
Res.
Res.
SFTRSTF
0x60
Res.
0x3C
Res.
Res.
WDGRSTF
RCC_
CSR
Res.
0x74
Res.
RCC_
BDCR
LPWRRSTF
0x70
WWDGRSTF
Register
name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x38
RCC_
AHB3ENR
FSMCEN
QSPIEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Addr.
offset
Res.
RM0430
Reset and clock control (RCC) for STM32F413/423
Table 24. RCC register map and reset values for STM32F413/423 (continued)
Reserved
Reserved
183/1321
184
CKGATENR
0x94
RCC_
DCKCFGR2
184/1321
Res.
Res.
Res.
CKDFSDM1ASEL
CKDFSDM2ASEL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RM0430 Rev 9
1. Only available for STM32F423xx.
Refer to Section 2.2 on page 57 for the register boundary addresses.
SPARE _CKEN
AHB2APB2_CKEN
AHB2APB1_CKEN
Res.
Res.
SRAM12_CKGA_BPEN
Res.
CM4DBG_CKEN
Res.
FLITF_CKEN
Res.
Res.
Res.
RCC_CKEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PLLI2SSRC
Res.
PLLI2SQ[3:0]
PLLI2SN[8:0]]
Res.
Res.
PLLI2SDIVR[4:0]]
EVTCL_CKEN
PLLDIVR[4:0]]
Res.
Res.
Res.
Res.
INCSTEP[14:0]
Res.
Res.
Res.
Res.
Res.
0x88
Res.
Res.
Res.
Res.
SAI1ASR[1:0]
SAI1BSR[1:0]
I2CFMP1SEL[1:0]
Res.
TIMPRE
I2S1SRC[1:0]
I2S2SRC[1:0]
Res.
Res.
Res.
CK48MSEL
RCC_
PLLI2SCFGR
PLLI2SR[2:0]
SSCGEN
0x84
Res.
RCC_
SSCGR
SDIOSEL
0x80
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
name
SPREADSEL
Addr.
offset
Res.
Res.
0x90
CKDFSDM1SEL
RCC_
DCKCFGR
LPTIMER1SEL0
0x8C
LPTIMER1SEL1
Reset and clock control (RCC) for STM32F413/423
RM0430
Table 24. RCC register map and reset values for STM32F413/423 (continued)
MODPER[11:0]
PLLI2SM[5:0]
Reserved
RM0430
General-purpose I/Os (GPIO)
7
General-purpose I/Os (GPIO)
7.1
GPIO introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking
register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH
and GPIOx_AFRL).
7.2
7.3
GPIO main features
•
Up to 16 I/Os under control
•
Output states: push-pull or open drain + pull-up/down
•
Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
•
Speed selection for each I/O
•
Input states: floating, pull-up/down, analog
•
Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
•
Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR
•
Locking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration
•
Analog function
•
Alternate function input/output selection registers (at most 16 AFs per I/O)
•
Fast toggle capable of changing every two clock cycles
•
Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions
GPIO functional description
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
•
Input floating
•
Input pull-up
•
Input-pull-down
•
Analog
•
Output open-drain with pull-up or pull-down capability
•
Output push-pull with pull-up or pull-down capability
•
Alternate function push-pull with pull-up or pull-down capability
•
Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is
to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no
risk of an IRQ occurring between the read and the modify access.
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Figure 17 show the basic structure of a 5 V tolerant I/O port bit. Table 25 gives the possible
port bit configurations.
Figure 17. Basic structure of a five-volt tolerant I/O port bit
Analog
To on-chip
peripheral
Alternate function input
Read/write
Input data register
on/off
VDD
TTL Schmitt
trigger
on/off
Protection
diode
Pull
up
I/O pin
Output driver
VDD
on/off
P-MOS
Protection
diode
Pull
down
VSS
Output
control
VSS
N-MOS
VSS
From on-chip
peripheral
VDD_FT (1)
Input driver
Output data register
Write
Bit set/reset registers
Read
Alternate function output
Push-pull,
open-drain or
disabled
Analog
ai15939b
1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.
Table 25. Port bit configuration table(1)
MODER(i)
[1:0]
01
186/1321
OTYPER(i)
OSPEEDR(i)
[B:A]
PUPDR(i)
[1:0]
I/O configuration
0
0
0
GP output
PP
0
0
1
GP output
PP + PU
0
1
0
GP output
PP + PD
1
1
Reserved
0
0
GP output
OD
1
0
1
GP output
OD + PU
1
1
0
GP output
OD + PD
1
1
1
Reserved (GP output OD)
0
1
SPEED
[B:A]
RM0430 Rev 9
RM0430
General-purpose I/Os (GPIO)
Table 25. Port bit configuration table(1) (continued)
MODER(i)
[1:0]
10
00
11
OTYPER(i)
OSPEEDR(i)
[B:A]
PUPDR(i)
[1:0]
I/O configuration
0
0
0
AF
PP
0
0
1
AF
PP + PU
0
1
0
AF
PP + PD
1
1
Reserved
0
0
AF
OD
1
0
1
AF
OD + PU
1
1
0
AF
OD + PD
1
1
1
Reserved
0
SPEED
[B:A]
1
x
x
x
0
0
Input
Floating
x
x
x
0
1
Input
PU
x
x
x
1
0
Input
PD
x
x
x
1
1
Reserved (input floating)
x
x
x
0
0
Input/output
x
x
x
0
1
x
x
x
1
0
x
x
x
1
1
Analog
Reserved
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.
7.3.1
General-purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and the I/O ports are
configured in input floating mode.
The debug pins are in AF pull-up/pull-down after reset:
•
PA15: JTDI in pull-up
•
PA14: JTCK/SWCLK in pull-down
•
PA13: JTMS/SWDAT in pull-up
•
PB4: NJTRST in pull-up
•
PB3: JTDO in floating state
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the N-MOS is activated when 0 is output).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB1
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.
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7.3.2
RM0430
I/O pin multiplexer and mapping
The microcontroller I/O pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin
at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin.
Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can
be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15)
registers:
•
After reset all I/Os are connected to the system’s alternate function 0 (AF0)
•
The peripherals’ alternate functions are mapped from AF1 to AF13
•
Cortex&reg;-M4 with FPU output EVENTOUT signal can be used by configuring the I/O pin
to output on AF15.
An event can be signaled through the configured pin after executing SEV assembly
instruction. It can be used as internal trigger for some peripheral or externally on
related GPIO.
This structure is shown in Figure 18: Selecting an alternate function on STM32F413/423
below.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, proceed as follows:
•
System function
Connect the I/O to AF0 and configure it depending on the function used:
Note:
–
JTAG/SWD, after each device reset these pins are assigned as dedicated pins
immediately usable by the debugger host (not controlled by the GPIO controller)
–
RTC_REFIN: this pin should be configured in Input floating mode
–
MCO1 and MCO2: these pins have to be configured in alternate function mode.
You can disable some or all of the JTAG/SWD pins and so release the associated pins for
GPIO usage.
For more details please refer to Section 6.2.10: Clock-out capability.
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General-purpose I/Os (GPIO)
Table 26. Flexible SWJ-DP pin assignment
SWJ I/O pin assigned
PA13 /
JTMS/
SWDIO
PA14 /
JTCK/
SWCLK
PA15 /
JTDI
PB3 /
JTDO
PB4/
NJTRST
Full SWJ (JTAG-DP + SW-DP) - Reset state
X
X
X
X
X
Full SWJ (JTAG-DP + SW-DP) but without
NJTRST
X
X
X
X
JTAG-DP Disabled and SW-DP Enabled
X
X
Available debug ports
JTAG-DP Disabled and SW-DP Disabled
•
Released
GPIO
Configure the desired I/O as output or input in the GPIOx_MODER register.
•
Peripheral alternate function
For the ADC, configure the desired I/O as analog in the GPIOx_MODER register.
For other peripherals:
•
–
Configure the desired I/O as an alternate function in the GPIOx_MODER register
–
Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDR registers, respectively
–
Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register
EVENTOUT
Configure the I/O pin used to output the Cortex&reg;-M4 with FPU EVENTOUT signal by
connecting it to AF15
Note:
Please refer to the “Alternate function mapping” table in the datasheets for the detailed
mapping of the system and peripherals’ alternate function I/O pins.
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RM0430
Figure 18. Selecting an alternate function on STM32F413/423
For pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function
AF0 (system)
AF1 (TIM1/TIM2)
AF2 (TIM3/5)
AF3 (TIM8/9)
AF4 (I2C1..3, I2CFMP1)
AF5 (SPI1/2/3/4)
AF6 (SPI2/3/4, DFSDM)
Pin x (x = 0..7)
AF7 (SPI2, USART1..3)
AF8 (DFSDM, USART3/6, CAN1)
1
AF9 (I2C1..3, I2CFMP1, CAN1/2, TIM12..14, QUADSPI)
AF10 (DFSDM, FSMC, QUADSPI, OTG_FS)
AF11
AF12 (FMC, SDIO)
AF13
AF14
AF15 (EVENTOUT)
AFRL[31:0]
For pins 8 to 15, the GPIOx_AFRH[31:0] register selects the dedicated alternate function
AF0 (system)
AF1 (TIM1/TIM2)
AF2 (TIM3/5)
AF3 (TIM8/9)
AF4 (I2C1..3, I2CFMP1)
AF5 (SPI1/2/3/4)
AF6 (SPI2/3/4, DFSDM)
Pin x (x = 8..15)
AF7 (SPI2, USART1..3)
AF8 (DFSDM, USART3/6, CAN1)
1
AF9 (I2C1..3, I2CFMP1, CAN1/2, TIM12..14, QUADSPI)
AF10 (DFSDM, FSMC, QUADSPI, OTG_FS)
AF11
AF12 (FMC, SDIO)
AF13
AF14
AF15 (EVENTOUT)
AFRH[31:0]
MSv39420V1
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7.3.3
General-purpose I/Os (GPIO)
I/O port control registers
Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os.
The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog).
The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type
(push-pull or open-drain) and speed (the I/O speed pins are directly connected to the
corresponding GPIOx_OSPEEDR register bits whatever the I/O direction). The
GPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.
7.3.4
I/O port data registers
Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 7.4.5: GPIO port input data register (GPIOx_IDR) (x = A...H) and Section 7.4.6:
GPIO port output data register (GPIOx_ODR) (x = A...H) for the register descriptions.
7.3.5
I/O data bitwise handling
The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BSRR(i) and
BSRR(i+SIZE). When written to 1, bit BSRR(i) sets the corresponding ODR(i) bit. When
written to 1, bit BSRR(i+SIZE) resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB1 write access.
7.3.6
GPIO locking mechanism
It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU or peripheral reset. Each GPIOx_LCKR bit
freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH).
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RM0430
The LOCK sequence (refer to Section 7.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A...H)) can only be performed using a word (32-bit long) access to the
GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same
time as the [15:0] bits.
For more details please refer to LCKR register description in Section 7.4.8: GPIO port
configuration lock register (GPIOx_LCKR) (x = A...H).
7.3.7
I/O alternate function input/output
Two registers are provided to select one out of the sixteen alternate function inputs/outputs
available for each I/O. With these registers, you can connect an alternate function to some
other pin as required by your application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of one I/O.
To know which functions are multiplexed on each GPIO pin, refer to the datasheets.
Note:
The application is allowed to select one of the possible peripheral functions for each I/O at a
time.
7.3.8
External interrupt/wakeup lines
All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode, refer to Section 10.2: External interrupt/event controller (EXTI)
and Section 10.2.3: Wakeup event management.
7.3.9
Input configuration
When the I/O port is programmed as Input:
•
the output buffer is disabled
•
the Schmitt trigger input is activated
•
the pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB1
clock cycle
•
A read access to the input data register provides the I/O State
Figure 19 shows the input configuration of the I/O port bit.
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General-purpose I/Os (GPIO)
Input data register
Figure 19. Input floating/pull up/pull down configurations
Read/write
Output data register
Write
Bit set/reset registers
Read
on
TTL Schmitt
trigger
VDD VDD
on/off
protection
diode
pull
up
input driver
I/O pin
on/off
output driver
pull
down
VSS
protection
diode
VSS
ai15940b
7.3.10
Output configuration
When the I/O port is programmed as output:
•
The output buffer is enabled:
–
Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
–
Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS
•
The Schmitt trigger input is activated
•
The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB1
clock cycle
•
A read access to the input data register gets the I/O state
•
A read access to the output data register gets the last written value
Figure 20 shows the output configuration of the I/O port bit.
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RM0430
Input data register
Figure 20. Output configuration
Write
Read/write
on
VDD
VDD
TTL Schmitt
trigger
on/off
Input driver
Output data register
Bit set/reset registers
Read
protection
diode
pull
up
Output driver
I/O pin
VDD
on/off
P-MOS
Output
control
protection
diode
pull
down
VSS
VSS
N-MOS
Push-pull or
VSS
Open-drain
ai15941b
7.3.11
Alternate function configuration
When the I/O port is programmed as alternate function:
•
The output buffer can be configured as open-drain or push-pull
•
The output buffer is driven by the signal coming from the peripheral (transmitter enable
and data)
•
The Schmitt trigger input is activated
•
The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB1
clock cycle
•
A read access to the input data register gets the I/O state
Figure 21 shows the Alternate function configuration of the I/O port bit.
Figure 21. Alternate function configuration
Input data register
Alternate function input
To on-chip
peripheral
Read/write
VDD VDD
TTL Schmitt
trigger
on/off
I/O pin
Output driver
on/off
VDD
P-MOS
Output
control
protection
diode
Pull
down
VSS
VSS
N-MOS
VSS
From on-chip
peripheral
protection
diode
Pull
up
Input driver
Output data register
Write
Bit set/reset registers
Read
on
push-pull or
open-drain
Alternate function output
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7.3.12
General-purpose I/Os (GPIO)
Analog configuration
When the I/O port is programmed as analog configuration:
Note:
•
The output buffer is disabled
•
The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
•
The weak pull-up and pull-down resistors are disabled
•
Read access to the input data register gets the value “0”
In the analog configuration, the I/O pins cannot be 5 Volt tolerant.
Figure 22 shows the high-impedance, analog-input configuration of the I/O port bit.
Figure 22. High impedance-analog configuration
Input data register
Analog
To on-chip
peripheral
Read/write
From on-chip
peripheral
7.3.13
Output data register
Write
Bit set/reset registers
Read
off
0
VDD
TTL Schmitt
trigger
protection
diode
Input driver
I/O pin
protection
diode
VSS
Analog
ai15943
Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15
port pins
The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose
PC14 and PC15 I/Os, respectively, when the LSE oscillator is off. The PC14 and PC15 I/Os
are only configured as LSE oscillator pins OSC32_IN and OSC32_OUT when the LSE
oscillator is ON. This is done by setting the LSEON bit in the RCC_BDCR register. The LSE
has priority over the GPIO function.
Note:
The PC14/PC15 GPIO functionality is lost when the 1.2 V domain is powered off (by the
device entering the standby mode) or when the backup domain is supplied by VBAT (VDD no
more supplied). In this case the I/Os are set in analog input mode.
7.3.14
Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1
I/Os, respectively, when the HSE oscillator is OFF. (after reset, the HSE oscillator is off). The
PH0/PH1 I/Os are only configured as OSC_IN/OSC_OUT HSE oscillator pins when the
HSE oscillator is ON. This is done by setting the HSEON bit in the RCC_CR register. The
HSE has priority over the GPIO function.
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7.3.15
RM0430
Selection of RTC additional functions
The STM32F4xx feature one GPIO pin RTC_AF1 that can be used for the detection of a
tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs.
•
The RTC_AF1 (PC13) can be used for the following purposes:
RTC_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wakeup
depending on the OSEL[1:0] bits in the RTC_CR register
•
RTC_CALIB output: this feature is enabled by setting the COE[23] in the RTC_CR
register
•
RTC_TAMP1: tamper event detection
•
RTC_TS: time stamp event detection
The selection of the corresponding pin is performed through the RTC_TAFCR register as
follows:
•
TAMP1INSEL is used to select which pin is used as the RTC_TAMP1 tamper input
•
TSINSEL is used to select which pin is used as the RTC_TS time stamp input
•
ALARMOUTTYPE is used to select whether the RTC_ALARM is output in push-pull or
open-drain mode
The output mechanism follows the priority order listed in Table 27.
Table 27. RTC additional functions(1)
TSINSEL
Pin
Time TAMP1INSEL
RTC_ALARM RTC_CALIB Tamper
TIMESTAMP
configuration
stamp
TAMPER1
enabled
enabled
enabled
pin
and function
enabled pin selection
selection
ALARMOUTTYP
configuration
Alarm out
output OD
1
Don’t care
Don’t
care
Don’t
care
Don’t care
Don’t care
0
Alarm out
output PP
1
Don’t care
Don’t
care
Don’t
care
Don’t care
Don’t care
1
Calibration
out output PP
0
1
Don’t
care
Don’t
care
Don’t care
Don’t care
Don’t care
TAMPER1
input floating
0
0
1
0
0
Don’t care
Don’t care
TIMESTAMP
and
TAMPER1
input floating
0
0
1
1
0
0
Don’t care
TIMESTAMP
input floating
0
0
0
1
Don’t care
0
Don’t care
Standard
GPIO
0
0
0
0
Don’t care
Don’t care
Don’t care
1. OD: open drain; PP: push-pull.
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7.4
GPIO registers
This section gives a detailed description of the GPIO registers.
For a summary of register bits, register address offsets and reset values, refer to Table 28.
The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits).
7.4.1
GPIO port mode register (GPIOx_MODER) (x = A...H)
Address offset: 0x00
Reset values:
31
30
MODER15[1:0]
•
0xA800 0000 for port A
•
0x0000 0280 for port B
•
0x0000 0000 for other ports
29
28
MODER14[1:0]
27
26
MODER13[1:0]
25
24
MODER12[1:0]
23
22
MODER11[1:0]
21
20
MODER10[1:0]
19
18
17
16
MODER9[1:0]
MODER8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODER7[1:0]
MODER6[1:0]
MODER5[1:0]
MODER4[1:0]
MODER3[1:0]
MODER2[1:0]
MODER1[1:0]
MODER0[1:0]
rw
rw
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rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 2y:2y+1 MODERy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O direction mode.
00: Input (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode
7.4.2
GPIO port output type register (GPIOx_OTYPER)
(x = A...H)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OT15
OT14
OT13
OT12
OT11
OT10
OT9
OT8
OT7
OT6
OT5
OT4
OT3
OT2
OT1
OT0
rw
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rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OTy: Port x configuration bits (y = 0..15)
These bits are written by software to configure the output type of the I/O port.
0: Output push-pull (reset state)
1: Output open-drain
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General-purpose I/Os (GPIO)
7.4.3
RM0430
GPIO port output speed register (GPIOx_OSPEEDR)
(x = A...H)
Address offset: 0x08
Reset values:
31
•
0x0C00 0000 for port A
•
0x0000 00C0 for port B
•
0x0000 0000 for other ports
30
29
OSPEEDR15
[1:0]
28
27
26
25
24
23
22
21
20
19
18
17
16
OSPEEDR14
[1:0]
OSPEEDR13
[1:0]
OSPEEDR12
[1:0]
OSPEEDR11
[1:0]
OSPEEDR10
[1:0]
OSPEEDR9
[1:0]
OSPEEDR8
[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSPEEDR7[1:0] OSPEEDR6[1:0] OSPEEDR5[1:0] OSPEEDR4[1:0]
rw
rw
rw
rw
rw
rw
rw
OSPEEDR3[1:0]
rw
rw
OSPEEDR2[1:0]
rw
rw
OSPEEDR1
[1:0]
OSPEEDR0
1:0]
rw
rw
rw
rw
rw
Bits 2y:2y+1 OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: Fast speed
11: High speed
Note: Refer to the product datasheets for the values of OSPEEDRy bits versus VDD
range and external load.
7.4.4
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A...H)
Address offset: 0x0C
Reset values:
31
30
PUPDR15[1:0]
•
0x6400 0000 for port A
•
0x0000 0100 for port B
•
0x0000 0000 for other ports
29
28
PUPDR14[1:0]
27
26
PUPDR13[1:0]
25
24
23
22
21
20
19
18
17
16
PUPDR12[1:0]
PUPDR11[1:0]
PUPDR10[1:0]
PUPDR9[1:0]
PUPDR8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PUPDR7[1:0]
PUPDR6[1:0]
PUPDR5[1:0]
PUPDR4[1:0]
PUPDR3[1:0]
PUPDR2[1:0]
PUPDR1[1:0]
PUPDR0[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 2y:2y+1 PUPDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
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RM0430 Rev 9
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RM0430
General-purpose I/Os (GPIO)
7.4.5
GPIO port input data register (GPIOx_IDR) (x = A...H)
Address offset: 0x10
Reset value: 0x0000 XXXX (where X means undefined)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IDR15
IDR14
IDR13
IDR12
IDR11
IDR10
IDR9
IDR8
IDR7
IDR6
IDR5
IDR4
IDR3
IDR2
IDR1
IDR0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDRy: Port input data (y = 0..15)
These bits are read-only and can be accessed in word mode only. They contain the input
value of the corresponding I/O port.
7.4.6
GPIO port output data register (GPIOx_ODR) (x = A...H)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10
rw
rw
rw
rw
rw
rw
9
8
7
6
5
4
3
2
1
0
ODR9
ODR8
ODR7
ODR6
ODR5
ODR4
ODR3
ODR2
ODR1
ODR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODRy: Port output data (y = 0..15)
These bits can be read and written by software.
Note: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the
GPIOx_BSRR register (x = A...H).
7.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A...H)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BS15
BS14
BS13
BS12
BS11
BS10
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
w
w
w
w
w
w
w
w
w
w
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RM0430 Rev 9
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General-purpose I/Os (GPIO)
RM0430
Bits 31:16 BRy: Port x reset bit y (y = 0..15)
These bits are write-only and can be accessed in word, half-word or byte mode. A read to
these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x set bit y (y= 0..15)
These bits are write-only and can be accessed in word, half-word or byte mode. A read to
these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit
7.4.8
GPIO port configuration lock register (GPIOx_LCKR)
(x = A...H)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU or peripheral reset.
Note:
A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this write sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000
Access: 32-bit word only, read/write register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCKK
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LCK15
LCK14
LCK13
LCK12
LCK11
LCK10
LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
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200/1321
RM0430 Rev 9
RM0430
General-purpose I/Os (GPIO)
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK[16]: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset
or a peripheral reset occurs.
LOCK key write sequence:
WR LCKR[16] = ‘1’ + LCKR[15:0]
WR LCKR[16] = ‘0’ + LCKR[15:0]
WR LCKR[16] = ‘1’ + LCKR[15:0]
RD LCKR
RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit will
return ‘1’ until the next CPU reset.
Bits 15:0 LCKy: Port x lock bit y (y= 0..15)
These bits are read/write but can only be written when the LCKK bit is ‘0.
0: Port configuration not locked
1: Port configuration locked
7.4.9
GPIO alternate function low register (GPIOx_AFRL) (x = A...H)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
AFRL7[3:0]
26
25
24
23
AFRL6[3:0]
22
21
20
19
AFRL5[3:0]
18
17
16
AFRL4[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
AFRL3[3:0]
rw
AFRL2[3:0]
rw
rw
AFRL1[3:0]
rw
AFRL0[3:0]
rw
rw
Bits 31:0 AFRLy: Alternate function selection for port x bit y (y = 0..7)
These bits are written by software to configure alternate function I/Os
AFRLy selection:
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
RM0430 Rev 9
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204
General-purpose I/Os (GPIO)
7.4.10
RM0430
GPIO alternate function high register (GPIOx_AFRH)
(x = A...H)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
28
27
26
AFRH15[3:0]
25
24
23
22
AFRH14[3:0]
21
20
19
18
AFRH13[3:0]
17
16
AFRH12[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AFRH11[3:0]
rw
rw
AFRH10[3:0]
rw
rw
rw
rw
AFRH9[3:0]
rw
rw
rw
rw
AFRH8[3:0]
rw
rw
rw
rw
rw
rw
Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15)
These bits are written by software to configure alternate function I/Os
AFRHy selection:
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
7.4.11
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
GPIO register map
The following table gives the GPIO register map and the reset values.
Register
0x00
GPIOA_
MODER
Reset value
1
202/1321
RM0430 Rev 9
0
0
0
0
MODER0[1:0]
MODER1[1:0]
MODER2[1:0]
0
0
0
0
0
0
0
0
0
MODER0[1:0]
0
0
0
0
MODER0[1:0]
0
0
0
MODER1[1:0]
1
0
MODER1[1:0]
0
MODER3[1:0]
MODER4[1:0]
0
0
0
MODER2[1:0]
0
1
0
MODER2[1:0]
0
0
0
MODER3[1:0]
0
0
MODER3[1:0]
0
MODER5[1:0]
MODER6[1:0]
0
0
0
MODER4[1:0]
0
0
0
MODER4[1:0]
0
0
0
MODER5[1:0]
0
0
MODER5[1:0]
0
MODER7[1:0]
MODER8[1:0]
0
0
0
MODER6[1:0]
0
0
0
MODER6[1:0]
0
0
0
MODER7[1:0]
0
0
MODER7[1:0]
0
MODER9[1:0]
MODER10[1:0]
0
0
0
MODER8[1:0]
0
0
0
MODER8[1:0]
0
0
0
MODER9[1:0]
0
0
MODER9[1:0]
0
0
MODER10[1:0]
0
MODER11[1:0]
MODER12[1:0]
0
0
MODER11[1:0]
0
0
0
MODER12[1:0]
0
0
MODER13[1:0]
0
MODER13[1:0]
MODER14[1:0]
0
0
0
MODER10[1:0]
0
0
0
MODER11[1:0]
Reset value
0
1
MODER12[1:0]
GPIOx_MODER
(where x =
C...H)
0
0
MODER13[1:0]
0
1
MODER14[1:0]
MODER15[1:0]
Reset value
0
MODER14[1:0]
0x00
GPIOB_
MODER
MODER15[1:0]
0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset
MODER15[1:0]
Table 28. GPIO register map and reset values
0
GPIOx_ODR
(where x = A...H)
0x18
GPIOx_BSRR
(where x = A...H)
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0430 Rev 9
ODR13
ODR12
ODR11
ODR10
ODR9
ODR8
ODR7
ODR6
ODR5
ODR4
ODR3
ODR2
ODR1
ODR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BS12
BS11
BS10
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
Reset value
BS13
0
0
0
0
0
0
0
GPIOx_IDR
(where x = A...H)
Reset value
IDR0
0
IDR1
0
IDR2
0
IDR3
0
IDR4
0
IDR5
0
IDR6
0
IDR7
0
IDR8
0
IDR9
0
IDR10
0
IDR11
0
IDR12
0
IDR13
0
0
OSPEEDR7[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
OT1
OT0
0
0
0
0
0
0
0
0
0
0
OSPEEDR0[1:0]
0
OSPEEDR0[1:0]
0
OSPEEDR0[1:0]
0
PUPDR0[1:0]
OT2
0
PUPDR0[1:0]
OT3
OSPEEDR1[1:0]
0
OSPEEDR1[1:0]
0
OSPEEDR1[1:0]
0
PUPDR1[1:0]
OT4
0
PUPDR1[1:0]
OT5
OSPEEDR2[1:0]
0
OSPEEDR2[1:0]
0
OSPEEDR2[1:0]
0
PUPDR2[1:0]
OT6
0
PUPDR2[1:0]
OT7
OSPEEDR3[1:0]
0
OSPEEDR3[1:0]
0
OSPEEDR3[1:0]
0
PUPDR3[1:0]
OT8
0
PUPDR3[1:0]
OT9
OSPEEDR4[1:0]
0
OSPEEDR4[1:0]
0
OSPEEDR4[1:0]
0
PUPDR4[1:0]
0
PUPDR4[1:0]
OT11
OT10
OSPEEDR5[1:0]
0
OSPEEDR5[1:0]
0
OSPEEDR5[1:0]
0
PUPDR5[1:0]
OT12
0
PUPDR5[1:0]
OT13
OSPEEDR6[1:0]
0
OSPEEDR6[1:0]
0
OSPEEDR6[1:0]
0
PUPDR6[1:0]
0
PUPDR6[1:0]
0
0
0
PUPDR0[1:0]
0
0
0
0
PUPDR1[1:0]
0
0
0
PUPDR2[1:0]
0
0
0
PUPDR3[1:0]
0
0
PUPDR4[1:0]
0
0
PUPDR5[1:0]
0
OT14
0
OT15
0
PUPDR6[1:0]
0
OSPEEDR7[1:0]
0
OSPEEDR7[1:0]
0
PUPDR7[1:0]
0
PUPDR7[1:0]
0
PUPDR7[1:0]
0
IDR14
0
ODR14
0
BS14
0
OSPEEDR8[1:0]
OSPEEDR9[1:0]
OSPEEDR10[1:0]
OSPEEDR11[1:0]
OSPEEDR12[1:0]
OSPEEDR13[1:0]
OSPEEDR14[1:0]
Reset value
IDR15
0
0
ODR15
0
OSPEEDR8[1:0]
0
OSPEEDR8[1:0]
0
PUPDR8[1:0]
0
PUPDR8[1:0]
0
PUPDR8[1:0]
0
0
0
BS15
0
Res.
0
0
Res.
0
OSPEEDR9[1:0]
0
OSPEEDR9[1:0]
0
PUPDR9[1:0]
0
PUPDR9[1:0]
0
0
BR0
0
Res.
0
0
PUPDR9[1:0]
0
0
Res.
0
Res.
0
OSPEEDR10[1:0]
0
OSPEEDR10[1:0]
0
PUPDR10[1:0]
0
PUPDR10[1:0]
0
0
Res.
0
Res.
0
0
PUPDR10[1:0]
0
0
Res.
0
Res.
0
OSPEEDR11[1:0]
1
OSPEEDR11[1:0]
0
PUPDR11[1:0]
0
PUPDR11[1:0]
0
0
Res.
0
Res.
0
1
PUPDR11[1:0]
0
0
Res.
0
Res.
0
OSPEEDR12[1:0]
0
OSPEEDR12[1:0]
0
PUPDR12[1:0]
0
PUPDR12[1:0]
OSPEEDR13[1:0]
0
OSPEEDR13[1:0]
0
PUPDR13[1:0]
1
PUPDR13[1:0]
OSPEEDR14[1:0]
1
1
0
Res.
0
Res.
0
0
0
PUPDR12[1:0]
Reset value
0
0
Res.
0
Res.
GPIOB_PUPDR
0
0
Res.
0
Res.
0
0
PUPDR13[1:0]
Reset value
0
Res.
0
Res.
0
0
Res.
0
Res.
Reset value
OSPEEDR14[1:0]
0
PUPDR14[1:0]
Reset value
PUPDR14[1:0]
OSPEEDR15[1:0]
0
Res.
Reset value
Res.
GPIOA_
OSPEEDER
OSPEEDR15[1:0]
Reset value
PUPDR14[1:0]
GPIOx_PUPDR
(where x =
C...H)
Res.
0x10
GPIOx_
OSPEEDR
(where x =
C...H)
Res.
0x0C
GPIOB_
OSPEEDR
OSPEEDR15[1:0]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x04
GPIOx_
OTYPER
(where x = A...H)
Res.
0x0C
GPIOA_PUPDR
PUPDR15[1:0]
0x0C
PUPDR15[1:0]
0x08
PUPDR15[1:0]
0x08
Res.
0x08
Res.
Register
Res.
Offset
Res.
0x14
BR15
RM0430
General-purpose I/Os (GPIO)
Table 28. GPIO register map and reset values (continued)
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
203/1321
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General-purpose I/Os (GPIO)
RM0430
Table 28. GPIO register map and reset values (continued)
Register
0x1C
GPIOx_LCKR
(where x = A...H)
0x20
GPIOx_AFRL
(where x = A...H)
0x24
GPIOx_AFRH
AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0]
(where x = A...H)
Reset value
Reset value
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
0
LCK7
0
LCK8
LCK12
0
LCK9
LCK13
0
LCK11
LCK14
0
LCK10
LCK15
Res.
Reset value
LCKK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset
0
0
0
0
0
0
0
0
0
0
0
0
AFRL7[3:0]
AFRL6[3:0]
AFRL5[3:0]
AFRL4[3:0]
AFRL3[3:0]
AFRL2[3:0]
AFRL1[3:0]
AFRL0[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2 on page 57 for the register boundary addresses.
204/1321
RM0430 Rev 9
0
0
0
0
0
0
0
0
AFRH9[3:0]
AFRH8[3:0]
0
0
0
0
0
0
0
0
RM0430
System configuration controller (SYSCFG)
8
System configuration controller (SYSCFG)
The system configuration controller is mainly used to remap the memory accessible in the
code area and manage the external interrupt line connection to the GPIOs.
8.1
I/O compensation cell
By default the I/O compensation cell is not used. However when the I/O output buffer speed
is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell
for slew rate control on I/O tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power
supply.
When the compensation cell is enabled, a READY flag is set to indicate that the
compensation cell is ready and can be used. The I/O compensation cell can be used only
when the supply voltage ranges from 2.4 to 3.6 V.
8.2
SYSCFG registers
8.2.1
SYSCFG memory remap register (SYSCFG_MEMRMP)
This register is used for specific configurations on memory remap:
•
Two bits are used to configure the type of memory accessible at address 0x0000 0000.
These bits are used to select the physical remap by software and so, bypass the BOOT
pins.
•
After reset these bits take the value selected by the BOOT pins. When booting from
main Flash memory with BOOT0 pin set to 0, this register takes the value 0x00.
In remap mode, the CPU can access the external memory via ICode bus instead of System
bus which boosts up the performance.
Address offset: 0x00
Reset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)
)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MEM_MODE
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RM0430 Rev 9
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System configuration controller (SYSCFG)
RM0430
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 MEM_MODE: Memory mapping selection
Set and cleared by software. This bit controls the memory internal mapping at
address 0x0000 0000. After reset these bits take the value selected by the Boot
pins.
00: Main Flash memory mapped at 0x0000 0000
01: System Flash memory mapped at 0x0000 0000
10: reserved
11: Embedded SRAM mapped at 0x0000 0000
Note: Refer to Figure 2: Memory map for details about the memory mapping at
address 0x0000 0000.
8.2.2
SYSCFG peripheral mode configuration register (SYSCFG_PMC)
Address offset: 0x04
Reset value: 0x0000 0000
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
Res.
18
Res.
17
16
Res.
ADC1D
C2
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 ADC1DC2:
0: No effect.
1: Refer to AN4073 on how to use this bit
Note: These bits can be set only if the following conditions are met:
- ADC clock higher or equal to 30 MHz.
- Only one ADC1DC2 bit must be selected if ADC conversions do not start
at the same time and the sampling times differ.
- These bits must not be set when the ADCDC1 bit is set in PWR_CR
register.
Bits 15:0 Reserved, must be kept at reset value.
206/1321
RM0430 Rev 9
RM0430
System configuration controller (SYSCFG)
8.2.3
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
EXTI3[3:0]
rw
EXTI2[3:0]
rw
EXTI1[3:0]
rw
EXTI0[3:0]
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
These bits are written by software to select the source input for the EXTIx
external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin (Reserved for EXTI3 and EXTI2 configurations)
Other configurations: reserved
8.2.4
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXTI7[3:0]
rw
rw
rw
EXTI6[3:0]
rw
rw
rw
rw
EXTI5[3:0]
rw
rw
RM0430 Rev 9
rw
rw
EXTI4[3:0]
rw
rw
rw
rw
rw
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System configuration controller (SYSCFG)
RM0430
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)
These bits are written by software to select the source input for the EXTIx
external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
Other configurations: reserved
8.2.5
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
EXTI11[3:0]
rw
rw
rw
EXTI10[3:0]
rw
rw
EXTI9[3:0]
rw
EXTI8[3:0]
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)
These bits are written by software to select the source input for the EXTIx external
interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
Other configurations: reserved
208/1321
RM0430 Rev 9
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RM0430
System configuration controller (SYSCFG)
8.2.6
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
EXTI15[3:0]
rw
rw
rw
EXTI14[3:0]
rw
rw
rw
rw
EXTI13[3:0]
rw
rw
rw
rw
EXTI12[3:0]
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)
These bits are written by software to select the source input for the EXTIx external
interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
8.2.7
SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PVDL
Res.
CLL
rw
rw
Bits 31:3 Reserved, must be kept at reset value.
RM0430 Rev 9
209/1321
214
System configuration controller (SYSCFG)
RM0430
Bit 2 PVDL: PVD lock
This bit is set by software. It can be cleared only by a system reset. It enables and
locks the PVD connection to TIM1/8 Break input. It also locks (write protection) the
PVDE and PVDS[2:0] bits of PWR_CR register.
0: PVD interrupt not connected to TIM1/8 Break input. PVDE and PVDS[2:0] can be
read and modified
1: PVD interrupt connected to TIM1/8 Break input. PVDE and PVDS[2:0] are readonly
Bit 1 Reserved, must be kept at reset value.
Bit 0 CLL: core lockup lock
This bit is set and cleared by software. It enables and locks the LOCKUP (Hardfault)
output of the Cortex&reg;-M4 with FPU core with TIM1/8 Break input.
0: Cortex&reg;-M4 with FPU LOCKUP output not connected to TIM1/8 Break input
1: Cortex&reg;-M4 with FPU LOCKUP output connected to TIM1/8 Break input
8.2.8
Compensation cell control register (SYSCFG_CMPCR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
READY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CMP_PD
r
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 READY: Compensation cell ready flag
0: I/O compensation cell not ready
1: O compensation cell ready
Bits 7:2 Reserved, must be kept at reset value.
Bit 0 CMP_PD: Compensation cell power-down
0: I/O compensation cell power-down mode
1: I/O compensation cell enabled
210/1321
RM0430 Rev 9
rw
RM0430
System configuration controller (SYSCFG)
8.2.9
SYSCFG configuration register (SYSCFG_CFGR)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2CFMP1_SDA I2CFMP1_SCL
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 I2CFMP1_SDA
Set and cleared by software. When this bit is set, it forces FM+ drive capability on
I2CFMP1_SDA pin selected through GPIO port mode register and GPIO alternate
function selection bits.
Bit 0 I2CFMP1_SCL
Set and cleared by software. When this bit is set, it forces FM+ drive capability on
I2CFMP1_SCL pin selected through GPIO port mode register and GPIO alternate
function selection bits.
8.2.10
DFSDM Multi-channel delay control register (SYSCFG_MCHDLYCR)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
DFSDM2 DFSDM2 DFSDM2 DFSDM2 DFSDM2 DFSDM
_CK26
_CK15
_CK04
_D6
_D4
2_D2
SEL
SEL
SEL
SEL
SEL
SEL
rw
rw
rw
rw
rw
rw
DFSDM
DFSDM1
DFSDM1 DFSDM DFSDM1 DFSDM1
MCHDL
DFSDM1
2_D0
_CKO
_CK13 1_CK02
_D2
_D0
YEN2
_CFG
SEL
SEL
SEL
SEL
SEL
SEL
rw
rw
rw
rw
rw
rw
rw
17
16
DFSDM2
DFSDM
DFSDM2
_CKO
2_CK37
_CFG
SEL
SEL
rw
rw
rw
1
0
MCHDL
YEN1
BSCK
SEL
rw
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18
DFSDM2_CKOSEL: Source selection for DFSDM2_CKOUT (M2 multiplexer on
Figure 81: Multi-channel delay block for pulse skipping
0: The source for DFSDM2_CKOUT is the CkOut generated by the DFSDM2
1: The source for DFSDM2_CKOUT is the output of M27
Bit 17
DFSDM2_CFG: CkIn source selection for DFSDM2 (M9, M10, M11, M12, M13, M14,
M15, M16 and M2 multiplexers on Figure 81: Multi-channel delay block for pulse
skipping
0: The source for CkIn[7:0] signals are the pins DFSDM2_CKINy (M[16:9] = 0)
1: The source for CkIn[7:0] signals are provided by the outputs of DM[6:3]
(M16:9] = 1)
RM0430 Rev 9
211/1321
214
System configuration controller (SYSCFG)
212/1321
RM0430
Bit 16
DFSDM2_CK37SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1
(DM3 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping)
0: The gated clock is distributed to CkIn3 (DM3 = 0)
1: The gated clock is distributed to CkIn7 (DM3 = 1)
Bit 15
DFSDM2_CK26SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC2
(DM4 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping)
0: The gated clock is distributed to CkIn2 (DM4 = 0)
1: The gated clock is distributed to CkIn6 (DM4 = 1)
Bit14
DFSDM2_CK15SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC3
(DM5 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping)
0: The gated clock is distributed to CkIn1 (DM5 = 0)
1: The gated clock is distributed to CkIn5 (DM5 = 1)
Bit 13
DFSDM2_CK04SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC4
(DM6 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping)
0: The gated clock is distributed to CkIn0 (DM6 = 0)
1: The gated clock is distributed to CkIn4 (DM6 = 1)
Bit 12
DFSDM2_D6SEL: Source selection for DatIn6 of DFSDM2 (M20 multiplexer on
Figure 81: Multi-channel delay block for pulse skipping)
0: The source for DatIn6 is from the DFSDM2_DATIN6 pin (M20 = 0)
1: DatIn6 is sharing the same data than DatIn7 (M20 = 1)
Bit 11
DFSDM2_D4SEL: Source selection for DatIn4 of DFSDM2 (M19 multiplexer on
Figure 81: Multi-channel delay block for pulse skipping)
0: The source for DatIn4 is from the DFSDM2_DATIN4 pin (M19 = 0)
1: DatIn4 is sharing the same data than DatIn5 (M19 = 1)
Bit 10
DFSDM2_D2SEL: Source selection for DatIn2 of DFSDM2 (M18 multiplexer on
Figure 81: Multi-channel delay block for pulse skipping)
0: The source for DatIn2 is from the DFSDM2_DATIN2 pin (M18 = 0)
1: DatIn2 is sharing the same data than DatIn3 (M18 = 1)
Bit 9
DFSDM2_D0SEL: Source selection for DatIn0 of DFSDM2 (M17 multiplexer on
Figure 81: Multi-channel delay block for pulse skipping)
0: The source for DatIn0 is from the DFSDM2_DATIN0 pin (M17 = 0)
1: DatIn0 is sharing the same data than DatIn1 (M17 = 1)
Bit 8
MCHDLYEN2: MCHDLY clock enable for DFSDM2 (G3,G4,G5,G6 gating signal on
Figure 81: Multi-channel delay block for pulse skipping)
0: Delay clock for DFSDM2 is disabled (G[6:3] = 0)
1: Delay clock for DFSDM2 is enabled (G[6:3] = 1)
Bit 7
DFSDM1_CKOSEL: Source selection for DFSDM1_CKOUT (M1 multiplexer on
Figure 81: Multi-channel delay block for pulse skipping)
0: The source for DFSDM1_CKOUT is the CkOut generated by the DFSDM1 (M1=0)
1: The source for DFSDM1_CKOUT is the output of M27 (M1=1)
Bit 6
DFSDM1_CFG: CkIn source selection for DFSDM1 (M3,M4,M5,M6 multiplexer on
Figure 1)
0: The source for CkIn[3:0] signals are the pins DFSDM1_CKINy (M[6:3] = 0)
1: The source for CkIn[3:0] signals are provided by the outputs of DM[2:1] (M[6:3] = 1)
Bit 5
DFSDM1_CK13SEL: Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1
(DM1 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping)
0: The gated clock is distributed to CkIn1 (DM1 = 0)
1: The gated clock is distributed to CkIn3 (DM1 = 1)
RM0430 Rev 9
RM0430
System configuration controller (SYSCFG)
Bit 4
DFSDM1_CK02SEL: Distribution of the DFSDM1 bitstream clock gated by TIM4 OC2
(DM2 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping)
0: The gated clock is distributed to CkIn0 (DM2 = 0)
1: The gated clock is distributed to CkIn2 (DM2 = 1)
Bit 3
DFSDM1_D2SEL: Source selection for DatIn2 of DFSDM1 (M8 multiplexer on
Figure 81: Multi-channel delay block for pulse skipping)
0: The source for DatIn2 is from the DFSDM1_DATIN2 pin (M8 = 0)
1: DatIn2 is sharing the same data than DatIn3 (M8 = 1)
Bit 2
DFSDM1_D0SEL: Source selection for DatIn0 of DFSDM1 (M7 multiplexer on
Figure 81: Multi-channel delay block for pulse skipping)
0: The source for DatIn0 is from the DFSDM1_DATIN0 pin (M7 = 0)
1: DatIn0 is sharing the same data than DatIn1 (M7 = 1)
Bit 1
MCHDLYEN1: MCHDLY clock enable for DFSDM1 (G1,G2 gating signal on
Figure 81: Multi-channel delay block for pulse skipping)
0: Delay clock for DFSDM1 is disabled (G[2:1] = 0)
1: Delay clock for DFSDM1 is enabled (G[2:1] = 1)
Bit 0
BSCKSEL: Bitstream clock source selection (M27, M28, M29 multiplexers on
Figure 81: Multi-channel delay block for pulse skipping)
0: The clock source is stopped for the bitstream clock (M[29:27] = 0)
1: The DFSDM2 is selected as clock source for the bitstream clock (M[29:27] = 1)
RM0430 Rev 9
213/1321
214
0x30
SYSCFG_MCHDLYCR
214/1321
DFSDM2_CFG
DFSDM2_CK37SEL
DFSDM2_CK26SEL
DFSDM2_CK15SEL
DFSDM2_CK04SEL
DFSDM2_D6SEL
DFSDM2_D4SEL
DFSDM2_D2SEL
DFSDM2_D0SEL
MCHDLYEN2
DFSDM1_CKOSEL
DFSDM1_CFG
DFSDM1_CK13SEL
DFSDM1_CK02SEL
DFSDM1_D2SEL
DFSDM1_D0SEL
MCHDLYEN1
BSCKSEL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFSDM2_CKOSEL
Reset value
Res.
SYSCFG_CFGR
Res.
0x24
RM0430 Rev 9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2 on page 57 for the register boundary addresses.
0
Reset value
I2CFMP1_SCL
Res.
CLL
Reset value
0
0
Res.
CMP_PD
0
Res.
0
Res.
PVDL
0
Res.
I2CFMP1_SDA
Reset value
0
Res.
0
0
0
Res.
0
Res.
0
0
0
Res.
0
0
Res.
0
Res.
0
0
0
Res.
0
0
Res.
0
Res.
0
0
Res.
EXTI8[3:0]
0
0
Res.
0
Res.
0
0
Res.
0
Res.
EXTI9[3:0]
0
0
Res.
READY
0
0
Res.
0
Res.
EXTI4[3:0]
0
0
Res.
EXTI0[3:0]
0
Res.
0
Res.
EXTI10[3:0]
0
Res.
EXTI11[3:0]
0
Res.
EXTI12[3:0]
0
Res.
EXTI5[3:0]
0
0
Res.
EXTI1[3:0]
0
Res.
EXTI13[3:0]
0
Res.
EXTI6[3:0]
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI2[3:0]
0
Res.
EXTI14[3:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI7[3:0]
0
0
Res.
EXTI15[3:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI3[3:0]
0
Res.
Res.
Reset value
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_CMPCR
Res.
0x20
Res.
SYSCFG_CFGR2
Res.
0x1C
Res.
SYSCFG_EXTICR4
Res.
0x14
SYSCFG_EXTICR3
Res.
0x10
SYSCFG_EXTICR2
Res.
0x0C
SYSCFG_EXTICR1
Res.
0x08
0
0
0
0
x
x
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC1DC2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_PMC
Res.
0x04
Res.
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
SYSCFG_
MEMRMP
MEM_MODE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
Res.
8.2.11
Res.
System configuration controller (SYSCFG)
RM0430
SYSCFG register map
The following table gives the SYSCFG register map and the reset values.
Table 29. SYSCFG register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0430
Direct memory access controller (DMA)
9
Direct memory access controller (DMA)
9.1
DMA introduction
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory and between memory and memory. Data can be quickly moved by
DMA without any CPU action. This keeps CPU resources free for other operations.
The DMA controller combines a powerful dual AHB master bus architecture with
independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix
architecture.
The two DMA controllers (DMA1, DMA2) have 8 streams each, dedicated to managing
memory access requests from one or more peripherals.
Each stream can have up to 16 channels (requests) in total.
Each DMA controller has an arbiter for handling the priority between DMA requests.
9.2
DMA main features
The main DMA features are:
•
Dual AHB master bus architecture, one dedicated to memory accesses and one
dedicated to peripheral accesses
•
AHB slave programming interface supporting only 32-bit accesses
•
8 streams for each DMA controller, up to 16 channels (requests) per stream
•
Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be
used in FIFO mode or direct mode:
•
–
FIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the
FIFO size
–
Direct mode: each DMA request immediately initiates a transfer from/to the
memory. When it is configured in direct mode (FIFO disabled), to transfer data in
memory-to-peripheral mode, the DMA preloads only one data from the memory to
the internal FIFO to ensure an immediate data transfer as soon as a DMA request
is triggered by a peripheral.
Each stream can be configured to be:
–
a regular channel that supports peripheral-to-memory, memory-to-peripheral and
memory-to-memory transfers
–
a double buffer channel that also supports double buffering on the memory side
•
Priorities between DMA stream requests are software-programmable (four levels
consisting of very high, high, medium, low) or hardware in case of equality (for
example, request 0 has priority over request 1)
•
Each stream also supports software trigger for memory-to-memory transfers (only
available for the DMA2 controller)
•
Each stream request can be selected among up to 16 possible channel requests. This
selection is software-configurable and allows several peripherals to initiate DMA
requests
•
The number of data items to be transferred can be managed either by the DMA
controller or by the peripheral:
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Direct memory access controller (DMA)
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RM0430
–
DMA flow controller: the number of data items to be transferred is softwareprogrammable from 1 to 65535
–
Peripheral flow controller: the number of data items to be transferred is unknown
and controlled by the source or the destination peripheral that signals the end of
the transfer by hardware
•
Independent source and destination transfer width (byte, half-word, word): when the
data widths of the source and destination are not equal, the DMA automatically
packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only
available in FIFO mode
•
Incrementing or non-incrementing addressing for source and destination
•
Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is
software-configurable, usually equal to half the FIFO size of the peripheral
•
Each stream supports circular buffer management
•
5 event flags (DMA half transfer, DMA transfer complete, DMA transfer error, DMA
FIFO error, direct mode error) logically ORed together in a single interrupt request for
each stream
RM0430 Rev 9
RM0430
Direct memory access controller (DMA)
9.3
DMA functional description
9.3.1
DMA block diagram
The figure below shows the block diagram of a DMA.
Figure 23. DMA block diagram
AHB master
DMA controller
REQ_STR0_CH0
REQ_STR0_CH1
STREAM 7
STREAM 6
FIFO
STREAM 5
FIFO
FIFO
AHB master
STREAM 7
STREAM 6
STREAM 5
STREAM 4
FIFO
STREAM 3
FIFO
STREAM 4
STREAM 1
STREAM 2
FIFO
REQ_STR7_CH0
REQ_STR7_CH1
STREAM 3
REQ_STREAM7
Arbiter
FIFO
REQ_STREAM5
REQ_STREAM6
STREAM 2
REQ_STREAM3
REQ_STREAM4
FIFO
REQ_STREAM1
REQ_STREAM2
STREAM 1
REQ_STR1_CH15
REQ_STREAM0
STREAM 0
REQ_STR1_CH0
REQ_STR1_CH1
STREAM 0
REQ_STR0_CH15
Memory port
REQ_STR7_CH15
Peripheral port
Channel
selection
AHB slave
programming
interface
Programming port
MSv42604V1
9.3.2
DMA overview
The DMA controller performs direct memory transfer: as an AHB master, the DMA controller
can take the control of the AHB bus matrix to initiate AHB transactions.
The DMA controller carries out the following transactions:
•
peripheral-to-memory
•
memory-to-peripheral
•
memory-to-memory
The DMA controller provides two AHB master ports: the AHB memory port, intended to be
connected to memories and the AHB peripheral port, intended to be connected to
peripherals. However, to allow memory-to-memory transfers, the AHB peripheral port must
also have access to the memories.
The AHB slave port is used to program the DMA controller (it supports only 32-bit
accesses).
RM0430 Rev 9
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Direct memory access controller (DMA)
9.3.3
RM0430
DMA transactions
A DMA transaction consists of a sequence of a given number of data transfers. The number
of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are softwareprogrammable.
Each DMA transfer consists of three operations:
•
a loading from the peripheral data register or a location in memory, addressed through
the DMA_SxPAR or DMA_SxM0AR register
•
a storage of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_SxPAR or DMA_SxM0AR register
•
a post-decrement of the DMA_SxNDTR register, containing the number of transactions
that still have to be performed
After an event, the peripheral sends a request signal to the DMA controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the
DMA controller. The peripheral releases its request as soon as it gets the Acknowledge
signal from the DMA controller. Once the request has been deasserted by the peripheral,
the DMA controller releases the Acknowledge signal. If there are more requests, the
peripheral can initiate the next transaction.
9.3.4
Channel selection
Each stream is associated with a DMA request that can be selected out of 16 possible
channel requests. The selection is controlled by the CHSEL[3:0] bits in the DMA_SxCR
register.
Caution:
A same peripheral request can be assigned to two different channels only if the application
ensures that these channels are not requested to be served at the same time. In other
words, if two different channels receive a same asserted peripheral request at the same
time, an unpredictable DMA hardware behavior occurs.
Figure 24. Channel selection
REQ_STRx_CH15
.
.
.
.
REQ_STREAMx
REQ_STRx_CH3
REQ_STRx_CH2
REQ_STRx_CH1
REQ_STRx_CH0
31
DMA_SxCR
28
25
0
CHSEL[3:0]
MSv39629V1
218/1321
RM0430 Rev 9
RM0430
Direct memory access controller (DMA)
The 16 requests from the peripherals (such as TIM, ADC, SPI, I2C) are independently
connected to each channel and their connection depends on the product implementation.
Table 30 and Table 31 give examples of DMA request mappings.
Table 30. DMA1 request mapping
Peripheral
requests
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Channel 0
SPI3_RX
I2C1_TX
SPI3_RX
SPI2_RX
SPI2_TX
SPI3_TX
-
SPI3_TX
Channel 1
I2C1_RX
I2C3_RX
TIM7_UP
I2CFMP1_RX
TIM7_UP
I2C1_RX
I2C1_TX
I2C1_TX
Channel 2
TIM4_CH1
TIM4_CH2
I2S2_EXT_TX
I2S3_EXT_TX
TIM4_UP
TIM4_CH3
Channel 3
I2S3_EXT_RX
TIM2_UP
TIM2_CH3
I2C3_RX
I2S2_EXT_RX
I2C3_TX
TIM2_CH1
TIM2_CH2
TIM2_CH4
TIM2_UP
TIM2_CH4
Channel 4
UART5_RX
USART3_RX
UART4_RX
USART3_TX
UART4_TX
USART2_RX
USART2_TX
I2CFMP1_TX
Channel 5
UART8_TX
UART7_TX
TIM3_UP
TIM3_CH4
UART7_RX
TIM3_CH1
TIM3_TRIG
TIM3_CH2
UART8_RX
TIM3_CH3
Channel 6
TIM5_CH3
TIM5_UP
TIM5_CH4
TIM5_TRIG
TIM5_CH1
TIM5_CH4
‘TIM5_TRIG
TIM5_CH2
I2C3_TX
TIM5_UP
USART2_RX
Channel 7
I2CFMP1_RX
TIM6_UP
I2C2_RX
I2C2_RX
USART3_TX
DAC1
DAC2
I2C2_TX
Channel 8
-
-
-
-
-
-
-
UART5_TX
I2CFMP1_TX I2S3_EXT_RX
Table 31. DMA2 request mapping
Peripheral
requests
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Channel 0
ADC1
SAI1_A
TIM8_CH1
TIM8_CH2
TIM8_CH3
SAI1_A
ADC1
SAI1_B
TIM1_CH1
TIM1_CH2
TIM1_CH3
UART9_RX
Channel 1
UART9_TX
-
-
-
SAI1B
-
-
-
Channel 2
-
-
SPI1_TX
SPI5_RX
SPI5_TX
AES_OUT(1)
AES_IN(1)
-
Channel 3
SPI1_RX
DFSDM1_
FLT1
SPI1_RX
SPI1_TX
DFSDM1_
FLT1
SPI1_TX
DFSDM1_
FLT0
QUADSPI
Channel 4
SPI4_RX
SPI4_TX
USART1_RX
SDIO
SPI4_RX
USART1_RX
SDIO
USART1_TX
Channel 5
UART10_RX
USART6_RX
USART6_RX
SPI4_RX
SPI4_TX
SPI5_TX
USART6_TX
USART6_TX
TIM1_UP
TIM1_CH3
UART10_TX
Channel 6
TIM1_TRIG
TIM1_CH1
TIM1_CH2
TIM1_CH1
TIM1_CH4
TIM1_TRIG
TIM1_COM
Channel 7
DFSDM1_
FLT0
TIM8_UP
TIM8_CH1
TIM8_CH2
TIM8_CH3
SPI5_RX
SPI5_TX
TIM8_CH4
TIM8_TRIG
TIM8_COM
Channel 8
DFSDM2_
FLT0
DFSDM2_
FLT1
DFSDM2_
FLT2
DFSDM2_
FLT3
DFSDM2_
FLT0
DFSDM2_
FLT1
DFSDM2_
FLT2
DFSDM2_
FLT3
Channel 9
-
-
-
UART10_RX
-
UART10_TX
-
-
1. Only available for STM32F423xx.
RM0430 Rev 9
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Direct memory access controller (DMA)
9.3.5
RM0430
Arbiter
An arbiter manages the 8 DMA stream requests based on their priority for each of the two
AHB master ports (memory and peripheral ports) and launches the peripheral/memory
access sequences.
Priorities are managed in two stages:
•
•
9.3.6
Software: each stream priority can be configured in the DMA_SxCR register. There are
four levels:
–
Very high priority
–
High priority
–
Medium priority
–
Low priority
Hardware: If two requests have the same software priority level, the stream with the
lower number takes priority over the stream with the higher number. For example,
stream 2 takes priority over stream 4.
DMA streams
Each of the eight DMA controller streams provides a unidirectional transfer link between a
source and a destination.
Each stream can be configured to perform:
•
Regular type transactions: memory-to-peripherals, peripherals-to-memory or memoryto-memory transfers
•
Double-buffer type transactions: double buffer transfers using two memory pointers for
the memory (while the DMA is reading/writing from/to a buffer, the application can
write/read to/from the other buffer).
The amount of data to be transferred (up to 65535) is programmable and related to the
source width of the peripheral that requests the DMA transfer connected to the peripheral
AHB port. The register that contains the amount of data items to be transferred is
decremented after each transaction.
9.3.7
Source, destination and transfer modes
Both source and destination transfers can address peripherals and memories in the entire
4-Gbyte area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.
The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers
three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory
transfers.
The table below describes the corresponding source and destination addresses.
Table 32. Source and destination address
220/1321
Bits DIR[1:0] of the
DMA_SxCR register
Direction
Source address
Destination address
00
Peripheral-to-memory
DMA_SxPAR
DMA_SxM0AR
01
Memory-to-peripheral
DMA_SxM0AR
DMA_SxPAR
RM0430 Rev 9
RM0430
Direct memory access controller (DMA)
Table 32. Source and destination address (continued)
Bits DIR[1:0] of the
DMA_SxCR register
Direction
Source address
Destination address
10
Memory-to-memory
DMA_SxPAR
DMA_SxM0AR
11
Reserved
-
-
When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register)
is a half-word or a word, respectively, the peripheral or memory address written into the
DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word
address boundary, respectively.
Peripheral-to-memory mode
Figure 25 describes this mode.
When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a
peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO.
When the threshold level of the FIFO is reached, the contents of the FIFO are drained and
stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is 0), the threshold level
of the FIFO is not used: after each single data transfer from the peripheral to the FIFO, the
corresponding data are immediately drained and stored into the destination.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
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Direct memory access controller (DMA)
RM0430
Figure 25. Peripheral-to-memory mode
DMA_SxM0AR
DMA controller
DMA_SxM1AR(1)
AHB memory
port
Memory bus
Memory
destination
REQ_STREAMx
FIFO
level
Arbiter
FIFO
AHB peripheral
port
Peripheral bus
peripheral
source
DMA_SxPAR
Peripheral DMA request
ai15948
1. For double-buffer mode.
Memory-to-peripheral mode
Figure 26 describes this mode.
When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream
immediately initiates transfers from the source to entirely fill the FIFO.
Each time a peripheral request occurs, the contents of the FIFO are drained and stored into
the destination. When the level of the FIFO is lower than or equal to the predefined
threshold level, the FIFO is fully reloaded with data from the memory.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is 0), the threshold level
of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to
transfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA
transfers the preloaded value into the configured destination. It then reloads again the
empty internal FIFO with the next data to be transfer. The preloaded data size corresponds
to the value of the PSIZE bitfield in the DMA_SxCR register.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
222/1321
RM0430 Rev 9
RM0430
Direct memory access controller (DMA)
Figure 26. Memory-to-peripheral mode
DMA_SxM0AR
DMA controller
DMA_SxM1AR(1)
AHB memory
port
Memory bus
Memory
source
REQ_STREAMx
Arbiter
FIFO
level
FIFO
AHB peripheral
port
DMA_SxPAR
Peripheral bus
Peripheral
destination
Peripheral DMA request
ai15949
1. For double-buffer mode.
Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral.
This is the memory-to-memory mode, described in Figure 27.
When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the
stream immediately starts to fill the FIFO up to the threshold level. When the threshold level
is reached, the FIFO contents are drained and stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the
DMA_SxCR register is cleared by software.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
Note:
When memory-to-memory mode is used, the circular and direct modes are not allowed.
RM0430 Rev 9
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Direct memory access controller (DMA)
RM0430
Figure 27. Memory-to-memory mode
DMA_SxM0AR
DMA controller
DMA_SxM1AR(1)
AHB memory
port
Memory bus
Memory 2
destination
Arbiter
Stream enable
FIFO
level
FIFO
AHB peripheral
port
DMA_SxPAR
Peripheral bus
Memory 1
source
ai15950
1. For double-buffer mode.
9.3.8
Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented or kept
constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR
register.
Disabling the increment mode is useful when the peripheral source or destination data is
accessed through a single register.
If the increment mode is enabled, the address of the next transfer is the address of the
previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on
the data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.
In order to optimize the packing operation, it is possible to fix the increment offset size for
the peripheral address whatever the size of the data transferred on the AHB peripheral port.
The PINCOS bit in the DMA_SxCR register is used to align the increment offset size with
the data size on the peripheral AHB port, or on a 32-bit address (the address is then
incremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.
If the PINCOS bit is set, the address of the following transfer is the address of the previous
one incremented by 4 (automatically aligned on a 32-bit address), whatever the PSIZE
value. The AHB memory port, however, is not impacted by this operation.
224/1321
RM0430 Rev 9
RM0430
9.3.9
Direct memory access controller (DMA)
Circular mode
The circular mode is available to handle circular buffers and continuous data flows (e.g.
ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR
register.
When the circular mode is activated, the number of data items to be transferred is
automatically reloaded with the initial value programmed during the stream configuration
phase, and the DMA requests continue to be served.
Note:
In the circular mode, it is mandatory to respect the following rule in case of a burst mode
configured for memory:
DMA_SxNDTR = Multiple of ((Mburst beat) &times; (Msize)/(Psize)), where:
–
(Mburst beat) = 4, 8 or 16 (depending on the MBURST bits in the DMA_SxCR
register)
–
((Msize)/(Psize)) = 1, 2, 4, 1/2 or 1/4 (Msize and Psize represent the MSIZE and
PSIZE bits in the DMA_SxCR register. They are byte dependent)
–
DMA_SxNDTR = Number of data items to transfer on the AHB peripheral port
For example: Mburst beat = 8 (INCR8), MSIZE = 00 (byte) and PSIZE = 01 (half-word), in
this case: DMA_SxNDTR must be a multiple of (8 &times; 1/2 = 4).
If this formula is not respected, the DMA behavior and data integrity are not guaranteed.
NDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data
size, otherwise this could result in a bad DMA behavior.
9.3.10
Double-buffer mode
This mode is available for all the DMA1 and DMA2 streams.
The double-buffer mode is enabled by setting the DBM bit in the DMA_SxCR register.
A double-buffer stream works as a regular (single buffer) stream with the difference that it
has two memory pointers. When the double-buffer mode is enabled, the circular mode is
automatically enabled (CIRC bit in DMA_SxCR is not relevant) and at each end of
transaction, the memory pointers are swapped.
In this mode, the DMA controller swaps from one memory target to another at each end of
transaction. This allows the software to process one memory area while the second memory
area is being filled/used by the DMA transfer. The double-buffer stream can work in both
directions (the memory can be either the source or the destination) as described in
Table 33.
Note:
In double-buffer mode, it is possible to update the base address for the AHB memory port
on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled, by respecting the
following conditions:
•
When the CT bit is 0 in the DMA_SxCR register, the DMA_SxM1AR register can be
written. Attempting to write to this register while CT = 1 sets an error flag (TEIF) and the
stream is automatically disabled.
•
When the CT bit is 1 in the DMA_SxCR register, the DMA_SxM0AR register can be
written. Attempting to write to this register while CT = 0, sets an error flag (TEIF) and
the stream is automatically disabled.
To avoid any error condition, it is advised to change the base address as soon as the TCIF
flag is asserted because, at this point, the targeted memory must have changed from
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memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in
accordance with one of the two above conditions.
For all the other modes (except the double-buffer mode), the memory address registers are
write-protected as soon as the stream is enabled.
Table 33. Source and destination address registers in double-buffer mode (DBM = 1)
Bits DIR[1:0] of the
DMA_SxCR register
Direction
Source address
Destination address
00
Peripheral-to-memory
DMA_SxPAR
DMA_SxM0AR / DMA_SxM1AR
01
Memory-to-peripheral DMA_SxM0AR / DMA_SxM1AR
DMA_SxPAR
Not allowed(1)
10
11
Reserved
-
-
1. When the double-buffer mode is enabled, the circular mode is automatically enabled. Since the memory-to-memory mode
is not compatible with the circular mode, when the double-buffer mode is enabled, it is not allowed to configure the
memory-to-memory mode.
9.3.11
Programmable data width, packing/unpacking, endianness
The number of data items to be transferred has to be programmed into DMA_SxNDTR
(number of data items to transfer bit, NDT) before enabling the stream (except when the
flow controller is the peripheral, PFCTRL bit in DMA_SxCR is set).
When using the internal FIFO, the data widths of the source and destination data are
programmable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-,
16- or 32-bit).
When PSIZE and MSIZE are not equal:
•
The data width of the number of data items to transfer, configured in the DMA_SxNDTR
register is equal to the width of the peripheral bus (configured by the PSIZE bits in the
DMA_SxCR register). For instance, in case of peripheral-to-memory, memory-toperipheral or memory-to-memory transfers and if the PSIZE[1:0] bits are configured for
half-word, the number of bytes to be transferred is equal to 2 &times; NDT.
•
The DMA controller only copes with little-endian addressing for both source and
destination. This is described in Table 34.
This packing/unpacking procedure may present a risk of data corruption when the operation
is interrupted before the data are completely packed/unpacked. So, to ensure data
coherence, the stream may be configured to generate burst transfers: in this case, each
group of transfers belonging to a burst are indivisible (refer to Section 9.3.12).
In direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is
not possible. In this case, it is not allowed to have different source and destination transfer
data widths: both are equal and defined by the PSIZE bits in the DMA_SxCR register.
MSIZE bits are not relevant.
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Direct memory access controller (DMA)
Table 34. Packing/unpacking and endian behavior (bit PINC = MINC = 1)
Number AHB
AHB
of data Memory
memory peripheral
items to transfer
port
port
transfer - number
width
width
(NDT)
Peripheral port address / byte lane
Memory port
address / byte
lane
Peripheral
transfer
number
PINCOS = 1
PINCOS = 0
8
8
4
-
1
2
3
4
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
1
2
3
4
0x0 / B0[7:0]
0x4 / B1[7:0]
0x8 / B2[7:0]
0xC / B3[7:0]
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
8
16
2
-
1
2
3
4
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
1
2
0x0 / B1|B0[15:0]
0x4 / B3|B2[15:0]
0x0 / B1|B0[15:0]
0x2 / B3|B2[15:0]
32
1
-
1
2
3
4
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
1
8
0x0 /
B3|B2|B1|B0[31:0]
0x0 /
B3|B2|B1|B0[31:0]
16
8
4
-
1
2
0x0 / B1|B0[15:0]
0x2 / B3|B2[15:0]
1
2
3
4
0x0 / B0[7:0]
0x4 / B1[7:0]
0x8 / B2[7:0]
0xC / B3[7:0]
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
16
16
2
-
1
2
0x0 / B1|B0[15:0]
0x2 / B1|B0[15:0]
1
2
0x0 / B1|B0[15:0]
0x4 / B3|B2[15:0]
0x0 / B1|B0[15:0]
0x2 / B3|B2[15:0]
16
32
1
-
1
2
0x0 / B1|B0[15:0]
0x2 / B3|B2[15:0]
1
0x0 /
B3|B2|B1|B0[31:0]
0x0 /
B3|B2|B1|B0[31:0]
1
0x0 / B3|B2|B1|B0[31:0]
32
8
4
-
1
2
3
4
0x0 / B0[7:0]
0x4 / B1[7:0]
0x8 / B2[7:0]
0xC / B3[7:0]
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
32
16
2
-
1
0x0 /B3|B2|B1|B0[31:0]
1
2
0x0 / B1|B0[15:0]
0x4 / B3|B2[15:0]
0x0 / B1|B0[15:0]
0x2 / B3|B2[15:0]
32
32
1
-
1
0x0 /B3|B2|B1|B0 [31:0]
1
0x0 /
B3|B2|B1|B0 [31:0]
0x0 /
B3|B2|B1|B0[31:0]
Note:
Peripheral port may be the source or the destination (it can also be the memory source in
the case of memory-to-memory transfer).
PSIZE, MSIZE and NDT[15:0] must be configured so as to ensure that the last transfer is
not incomplete. This can occur when the data width of the peripheral port (PSIZE bits) is
lower than the data width of the memory port (MSIZE bits). This constraint is summarized in
the table below.
Table 35. Restriction on NDT versus PSIZE and MSIZE
9.3.12
PSIZE[1:0] of DMA_SxCR
MSIZE[1:0] of DMA_SxCR
NDT[15:0] of DMA_SxNDTR
00 (8-bit)
01 (16-bit)
Must be a multiple of 2
00 (8-bit)
10 (32-bit)
Must be a multiple of 4
01 (16-bit)
10 (32-bit)
Must be a multiple of 2
Single and burst transfers
The DMA controller can generate single transfers or incremental burst transfers of 4, 8, or
16 beats.
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The size of the burst is configured by software independently for the two AHB ports by using
the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.
The burst size indicates the number of beats in the burst, not the number of bytes
transferred.
To ensure data coherence, each group of transfers that form a burst are indivisible: AHB
transfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master
during the sequence of the burst transfer.
Depending on the single or burst configuration, each DMA request initiates a different
number of transfers on the AHB peripheral port:
•
When the AHB peripheral port is configured for single transfers, each DMA request
generates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits
in the DMA_SxCR register
•
When the AHB peripheral port is configured for burst transfers, each DMA request
generates 4,8 or 16 beats of byte, half word or word transfers depending on the
PBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register.
The same as above has to be considered for the AHB memory port considering the
MBURST and MSIZE bits.
In direct mode, the stream can only generate single transfers and the MBURST[1:0] and
PBURST[1:0] bits are forced by hardware.
The address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to
ensure that all transfers within a burst block are aligned on the address boundary equal to
the size of the transfer.
The burst configuration has to be selected in order to respect the AHB protocol, where
bursts must not cross the 1 Kbyte address boundary because the minimum address space
that can be allocated to a single slave is 1 Kbyte. This means that the 1-Kbyte address
boundary must not be crossed by a burst block transfer, otherwise an AHB error is
generated, that is not reported by the DMA registers.
9.3.13
FIFO
FIFO structure
The FIFO is used to temporarily store data coming from the source before transmitting them
to the destination.
Each stream has an independent 4-word FIFO and the threshold level is softwareconfigurable between 1/4, 1/2, 3/4 or full.
To enable the use of the FIFO threshold level, the direct mode must be disabled by setting
the DMDIS bit in the DMA_SxFCR register.
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Direct memory access controller (DMA)
The structure of the FIFO differs depending on the source and destination data widths, and
is described in the figure below.
Figure 28. FIFO structure
4 words
Empty
Source: byte
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
1/4
1/2
3/4
Full
byte lane 3
B15
B 11
B7
B3
byte lane 2
B14
B10
B6
B2
byte lane 1
B13
B9
B5
B1
byte lane 0 W3 B12
W2 B8
W1 B4
W0 B0
Destination: word
W3, W2, W1, W0
4 words
Empty
Source: byte
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
byte lane 3
1/4
1/2
3/4
B15
B 11
B7
byte lane 2 H7 B14
H5 B10
H3 B6
B13
B9
B5
byte lane 0 H6 B12
H4 B8
H2 B4
byte lane 1
Full
B3
H1
Destination: half-word
B2
H7, H6, H5, H4, H3, H2, H1, H0
B1
H0
B0
4 words
Empty
Source: half-word
1/4
1/2
3/4
Full
byte lane 3
H7
H5
H3
H1
H6
H4
H2
H0
Destination: word
byte lane 2
H7 H6 H5 H4 H3 H2 H1 H0
W3, W2, W1, W0
byte lane 1
byte lane 0 W3
W2
W1
W0
4-words
Empty
Source: half-word
H7 H6 H5 H4 H3 H2 H1 H0
byte lane 3
1/4
1/2
3/4
B15
B 11
B7
byte lane 2 H7 B14
H5 B10
H3 B6
B13
B9
B5
byte lane 0 H6 B12
H4 B8
H2 B4
byte lane 1
Full
B3
H1
B1
H0
Destination: byte
B2
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
B0
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FIFO threshold and burst configuration
Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR
register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register). The
content pointed by the FIFO threshold must exactly match an integer number of memory
burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or
DMA_LISR register) is generated when the stream is enabled, then the stream is
automatically disabled. The allowed and forbidden configurations are described in the table
below. The forbidden configurations are highlighted in gray in the table.
Table 36. FIFO threshold configurations
MSIZE
Byte
Half-word
FIFO level
MBURST = INCR4
MBURST = INCR8
1/4
1 burst of 4 beats
Forbidden
1/2
2 bursts of 4 beats
1 burst of 8 beats
3/4
3 bursts of 4 beats
Forbidden
Full
4 bursts of 4 beats
2 bursts of 8 beats
1/4
Forbidden
1/2
1 burst of 4 beats
3/4
Forbidden
Full
2 bursts of 4 beats
1/2
Forbidden
3/4
Full
Forbidden
1 burst of 16 beats
Forbidden
1 burst of 8 beats
1/4
Word
MBURST = INCR16
Forbidden
Forbidden
1 burst of 4 beats
In all cases, the burst size multiplied by the data size must not exceed the FIFO size (data
size can be: 1 (byte), 2 (half-word) or 4 (word)).
Incomplete burst transfer at the end of a DMA transfer may happen if one of the following
conditions occurs:
•
For the AHB peripheral port configuration: the total number of data items (set in the
DMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size.
•
For the AHB memory port configuration: the number of remaining data items in the
FIFO to be transferred to the memory is not a multiple of the burst size multiplied by the
data size.
In such cases, the remaining data to be transferred is managed in single mode by the DMA,
even if a burst transaction is requested during the DMA stream configuration.
Note:
When burst transfers are requested on the peripheral AHB port and the FIFO is used
(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to
avoid permanent underrun or overrun conditions, depending on the DMA stream direction:
If (PBURST &times; PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with
PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.
This rule ensures that enough FIFO space at a time is free to serve the request from the
peripheral.
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Direct memory access controller (DMA)
FIFO flush
The FIFO can be flushed when the stream is disabled by resetting the EN bit in the
DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or
memory-to-memory transfers. If some data are still present in the FIFO when the stream is
disabled, the DMA controller continues transferring the remaining data to the destination
(even though stream is effectively disabled). When this flush is completed, the transfer
complete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set.
The remaining data counter DMA_SxNDTR keeps the value in this case to indicate how
many data items are currently available in the destination memory.
Note that during the FIFO flush operation, if the number of remaining data items in the FIFO
to be transferred to memory (in bytes) is less than the memory data width (for example 2
bytes in FIFO while MSIZE is configured to word), data is sent with the data width set in the
MSIZE bit in the DMA_SxCR register. This means that memory is written with an undesired
value. The software may read the DMA_SxNDTR register to determine the memory area
that contains the good data (start address and last address).
If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST
bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB
memory port), single transactions are generated to complete the FIFO flush.
Direct mode
By default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and
the FIFO threshold level is not used. This mode is useful when the system requires an
immediate and single transfer to or from the memory after each DMA request.
When the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads one data from the memory to the internal FIFO to
ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.
To avoid saturating the FIFO, it is recommended to configure the corresponding stream with
a high priority.
This mode is restricted to transfers where:
•
the source and destination transfer widths are equal and both defined by the
PSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are not relevant)
•
burst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR
are don’t care)
Direct mode must not be used when implementing memory-to-memory transfers.
9.3.14
DMA transfer completion
Different events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR
or DMA_HISR status register:
•
In DMA flow controller mode:
–
The DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode.
–
The stream is disabled before the end of transfer (by clearing the EN bit in the
DMA_SxCR register) and (when transfers are peripheral-to-memory or memory-
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to-memory) all the remaining data have been flushed from the FIFO into the
memory.
•
Note:
In Peripheral flow controller mode:
–
The last external burst or single request has been generated from the peripheral
and (when the DMA is operating in peripheral-to-memory mode) the remaining
data have been transferred from the FIFO into the memory
–
The stream is disabled by software, and (when the DMA is operating in peripheralto-memory mode) the remaining data have been transferred from the FIFO into
the memory
The transfer completion is dependent on the remaining data in FIFO to be transferred into
memory only in the case of peripheral-to-memory mode. This condition is not applicable in
memory-to-peripheral mode.
If the stream is configured in non-circular mode, after the end of the transfer (that is when
the number of data to be transferred reaches zero), the DMA is stopped (EN bit in
DMA_SxCR register is cleared by Hardware) and no DMA request is served unless the
software reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR
register).
9.3.15
DMA transfer suspension
At any time, a DMA transfer can be suspended to be restarted later on or to be definitively
disabled before the end of the DMA transfer.
There are two cases:
Note:
232/1321
•
The stream disables the transfer with no later-on restart from the point where it was
stopped. There is no particular action to do, except to clear the EN bit in the
DMA_SxCR register to disable the stream. The stream may take time to be disabled
(ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the
DMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The
value of the EN bit in DMA_SxCR is now 0 to confirm the stream interruption. The
DMA_SxNDTR register contains the number of remaining data items at the moment
when the stream was stopped so that the software can determine how many data items
have been transferred before the stream was interrupted.
•
The stream suspends the transfer before the number of remaining data items to be
transferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer
later by re-enabling the stream. In order to restart from the point where the transfer was
stopped, the software has to read the DMA_SxNDTR register after disabling the stream
by writing the EN bit in DMA_SxCR register (and then checking that it is at 0) to know
the number of data items already collected. Then:
–
The peripheral and/or memory addresses have to be updated in order to adjust
the address pointers
–
The SxNDTR register has to be updated with the remaining number of data items
to be transferred (the value read when the stream was disabled)
–
The stream may then be re-enabled to restart the transfer from the point it was
stopped
A transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to indicate the
end of transfer due to the stream interruption.
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9.3.16
Direct memory access controller (DMA)
Flow controller
The entity that controls the number of data to be transferred is known as the flow controller.
This flow controller is configured independently for each stream using the PFCTRL bit in the
DMA_SxCR register.
The flow controller can be:
•
The DMA controller: in this case, the number of data items to be transferred is
programmed by software into the DMA_SxNDTR register before the DMA stream is
enabled.
•
The peripheral source or destination: this is the case when the number of data items to
be transferred is unknown. The peripheral indicates by hardware to the DMA controller
when the last data are being transferred. This feature is only supported for peripherals
that are able to signal the end of the transfer.
When the peripheral flow controller is used for a given stream, the value written into the
DMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it is
forced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following
schemes:
•
Anticipated stream interruption: EN bit in DMA_SxCR register is reset to 0 by the
software to stop the stream before the last data hardware signal (single or burst) is sent
by the peripheral. In such a case, the stream is switched off and the FIFO flush is
triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the
corresponding stream is set in the status register to indicate the DMA completion. To
know the number of data items transferred during the DMA transfer, read the
DMA_SxNDTR register and apply the following formula:
–
Note:
Number_of_data_transferred = 0xFFFF – DMA_SxNDTR
•
Normal stream interruption due to the reception of a last data hardware signal: the
stream is automatically interrupted when the peripheral requests the last transfer
(single or burst) and when this transfer is complete. the TCIFx flag of the corresponding
stream is set in the status register to indicate the DMA transfer completion. To know the
number of data items transferred, read the DMA_SxNDTR register and apply the same
formula as above.
•
The DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is
set in the status register to indicate the forced DMA transfer completion. The stream is
automatically switched off even though the last data hardware signal (single or burst)
has not been yet asserted. The already transferred data is not lost. This means that a
maximum of 65535 data items can be managed by the DMA in a single transaction,
even in peripheral flow control mode.
When configured in memory-to-memory mode, the DMA is always the flow controller and
the PFCTRL bit is forced to 0 by hardware.
The circular mode is forbidden in the peripheral flow controller mode.
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9.3.17
RM0430
Summary of the possible DMA configurations
The table below summarizes the different possible DMA configurations. The forbidden
configurations are highlighted in gray in the table.
Table 37. Possible DMA configurations
DMA transfer
mode
Peripheral-tomemory
Source
Destination
Flow
controller
Circular
mode
DMA
Possible
AHB
AHB
peripheral port memory port
Peripheral Forbidden
DMA
Memory-toperipheral
AHB
memory port
Possible
AHB
peripheral port
Peripheral Forbidden
Memory-tomemory
9.3.18
AHB
AHB
peripheral port memory port
DMA only
Forbidden
Transfer
type
Direct
mode
single
Possible
burst
Forbidden
single
Possible
burst
Forbidden
single
Possible
burst
Forbidden
single
Possible
burst
Forbidden
single
burst
Forbidden
Doublebuffer mode
Possible
Forbidden
Possible
Forbidden
Forbidden
Stream configuration procedure
The following sequence must be followed to configure a DMA stream x (where x is the
stream number):
234/1321
1.
If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register,
then read this bit in order to confirm that there is no ongoing stream operation. Writing
this bit to 0 is not immediately effective since it is actually written to 0 once all the
current transfers are finished. When the EN bit is read as 0, this means that the stream
is ready to be configured. It is therefore necessary to wait for the EN bit to be cleared
before starting any stream configuration. All the stream dedicated bits set in the status
register (DMA_LISR and DMA_HISR) from the previous data block DMA transfer must
be cleared before the stream can be re-enabled.
2.
Set the peripheral port register address in the DMA_SxPAR register. The data is moved
from/ to this address to/ from the peripheral port after the peripheral event.
3.
Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R
register in the case of a double-buffer mode). The data is written to or read from this
memory after the peripheral event.
4.
Configure the total number of data items to be transferred in the DMA_SxNDTR
register. After each peripheral event or each beat of the burst, this value is
decremented.
5.
Select the DMA channel (request) using CHSEL[3:0] in the DMA_SxCR register.
6.
If the peripheral is intended to be the flow controller and if it supports this feature, set
the PFCTRL bit in the DMA_SxCR register.
7.
Configure the stream priority using the PL[1:0] bits in the DMA_SxCR register.
8.
Configure the FIFO usage (enable or disable, threshold in transmission and reception)
RM0430 Rev 9
RM0430
Direct memory access controller (DMA)
9.
Configure the data transfer direction, peripheral and memory incremented/fixed mode,
single or burst transactions, peripheral and memory data widths, circular mode,
double-buffer mode and interrupts after half and/or full transfer, and/or errors in the
DMA_SxCR register.
10. Activate the stream by setting the EN bit in the DMA_SxCR register.
As soon as the stream is enabled, it can serve any DMA request from the peripheral
connected to the stream.
Once half the data have been transferred on the AHB destination port, the half-transfer flag
(HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is
set. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is
generated if the transfer complete interrupt enable bit (TCIE) is set.
Warning:
9.3.19
To switch off a peripheral connected to a DMA stream
request, it is mandatory to, first, switch off the DMA stream to
which the peripheral is connected, then to wait for EN bit = 0.
Only then can the peripheral be safely disabled.
Error management
The DMA controller can detect the following errors:
•
•
•
Transfer error: the transfer error interrupt flag (TEIFx) is set when:
–
a bus error occurs during a DMA read or a write access
–
a write access is requested by software on a memory address register in
double-buffer mode whereas the stream is enabled and the current target memory
is the one impacted by the write into the memory address register (refer to
Section 9.3.10: Double-buffer mode)
FIFO error: the FIFO error interrupt flag (FEIFx) is set if:
–
a FIFO underrun condition is detected
–
a FIFO overrun condition is detected (no detection in memory-to-memory mode
because requests and transfers are internally managed by the DMA)
–
the stream is enabled while the FIFO threshold level is not compatible with the
size of the memory burst (refer to Table 36: FIFO threshold configurations)
Direct mode error: the direct mode error interrupt flag (DMEIFx) can only be set in the
peripheral-to-memory mode while operating in direct mode and when the MINC bit in
the DMA_SxCR register is cleared. This flag is set when a DMA request occurs while
the previous data have not yet been fully transferred into the memory (because the
memory bus was not granted). In this case, the flag indicates that two data items were
be transferred successively to the same destination address, which could be an issue if
the destination is not able to manage this situation
In direct mode, the FIFO error flag can also be set under the following conditions:
•
In the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory
bus is not granted for several peripheral requests.
•
In the memory-to-peripheral mode, an underrun condition may occur if the memory bus
has not been granted before a peripheral request occurs.
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Direct memory access controller (DMA)
RM0430
If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO
threshold level, the faulty stream is automatically disabled through a hardware clear of its
EN bit in the corresponding stream configuration register (DMA_SxCR).
If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty
stream is not automatically disabled and it is up to the software to disable or not the stream
by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss
when this kind of errors occur.
When the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR
register is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE,
FEIE, DMEIE) in the DMA_SxCR or DMA_SxFCR register is set.
Note:
When a FIFO overrun or underrun condition occurs, the data is not lost because the
peripheral request is not acknowledged by the stream until the overrun or underrun
condition is cleared. If this acknowledge takes too much time, the peripheral itself may
detect an overrun or underrun condition of its internal buffer and data might be lost.
9.4
DMA interrupts
For each DMA stream, an interrupt can be produced on the following events:
•
Half-transfer reached
•
Transfer complete
•
Transfer error
•
FIFO error (overrun, underrun or FIFO level error)
•
Direct mode error
Separate interrupt enable control bits are available for flexibility as shown in the table below.
Table 38. DMA interrupt requests
Interrupt event
Note:
236/1321
Event flag
Enable control bit
Half-transfer
HTIF
HTIE
Transfer complete
TCIF
TCIE
Transfer error
TEIF
TEIE
FIFO overrun/underrun
FEIF
FEIE
Direct mode error
DMEIF
DMEIE
Before setting an enable control bit EN = 1, the corresponding event flag must be cleared,
otherwise an interrupt is immediately generated.
RM0430 Rev 9
RM0430
Direct memory access controller (DMA)
9.5
DMA registers
The DMA registers have to be accessed by words (32 bits).
9.5.1
DMA low interrupt status register (DMA_LISR)
Address offset: 0x000
Reset value: 0x0000 0000
31
30
Res.
15
Res.
14
Res.
Res.
29
Res.
13
Res.
28
Res.
12
Res.
27
26
25
24
TCIF3
HTIF3
TEIF3
DMEIF
3
r
r
r
r
11
10
9
8
TCIF1
HTIF1
TEIF1
DMEIF
1
r
r
r
r
23
Res.
7
Res.
22
21
20
19
18
17
16
Res.
FEIF2
FEIF3
TCIF2
HTIF2
TEIF2
DMEIF
2
r
r
r
r
r
6
5
4
3
2
1
0
Res.
FEIF0
FEIF1
TCIF0
HTIF0
TEIF0
DMEIF
0
r
r
r
r
r
r
r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x.
Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No half transfer event on stream x
1: An half transfer event occurred on stream x.
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x.
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No direct mode error on stream x
1: A direct mode error occurred on stream x.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_LIFCR register.
0: No FIFO error event on stream x
1: A FIFO error event occurred on stream x.
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Direct memory access controller (DMA)
9.5.2
RM0430
DMA high interrupt status register (DMA_HISR)
Address offset: 0x004
Reset value: 0x0000 0000
31
30
29
28
27
26
HTIF7
25
24
TEIF7
DMEIF
7
23
22
21
18
17
16
TEIF6
DMEIF
6
Res.
FEIF6
FEIF7
r
r
r
r
r
8
7
6
5
4
3
2
1
0
TEIF5
DMEIF
5
Res.
FEIF5
TCIF4
HTIF4
TEIF4
DMEIF
4
Res.
FEIF4
r
r
r
r
r
r
r
Res.
Res.
Res.
TCIF7
r
r
r
r
15
14
13
12
11
10
9
Res.
Res.
Res.
Res.
TCIF5
HTIF5
r
r
HTIF6
19
Res.
Res.
TCIF6
20
r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x.
Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No half transfer event on stream x
1: An half transfer event occurred on stream x.
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x.
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No direct mode error on stream x
1: A direct mode error occurred on stream x.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x = 7 to 4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit
in DMA_HIFCR register.
0: No FIFO error event on stream x
1: A FIFO error event occurred on stream x.
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r
RM0430
Direct memory access controller (DMA)
9.5.3
DMA low interrupt flag clear register (DMA_LIFCR)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
CDMEI
CTCIF3 CHTIF3 CTEIF3
F3
23
Res.
w
w
w
w
11
10
9
8
7
CDMEI
F1
Res.
CTCIF1 CHTIF1 CTEIF1
w
w
w
w
22
21
20
19
18
CDMEI
CFEIF3 CTCIF2 CHTIF2 CTEIF2
F2
17
16
Res.
CFEIF2
w
w
w
w
w
6
5
4
3
2
1
0
CDMEI
F0
Res.
CFEIF0
CFEIF1 CTCIF0 CHTIF0 CTEIF0
w
w
w
w
w
w
w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register.
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register.
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register.
9.5.4
DMA high interrupt flag clear register (DMA_HIFCR)
Address offset: 0x00C
Reset value: 0x0000 0000
31
Res.
15
Res.
30
Res.
14
Res.
29
Res.
13
Res.
28
Res.
12
Res.
27
26
25
24
CDMEI
CTCIF7 CHTIF7 CTEIF7
F7
w
w
w
w
11
10
9
8
CDMEI
CTCIF5 CHTIF5 CTEIF5
F5
w
w
w
23
Res.
7
Res.
w
22
21
20
19
18
CDMEI
CFEIF7 CTCIF6 CHTIF6 CTEIF6
F6
w
w
w
w
w
6
5
4
3
2
CDMEI
CFEIF5 CTCIF4 CHTIF4 CTEIF4
F4
w
w
w
w
17
16
Res.
CFEIF6
w
1
0
Res.
CFEIF4
w
w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register.
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register.
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Direct memory access controller (DMA)
RM0430
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register.
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7 to 4)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register.
9.5.5
DMA stream x configuration register (DMA_SxCR)
This register is used to configure the concerned stream.
Address offset: 0x010 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
28
27
25
CHSEL[3:0]
24
23
22
21
20
19
18
16
Res.
CT
DBM
rw
rw
rw
rw
MBURST[1:0]
PBURST[1:0]
rw
rw
rw
rw
rw
rw
rw
12
11
10
9
8
7
6
5
4
3
2
1
0
PF
CTRL
TCIE
HTIE
TEIE
DMEIE
EN
rw
rw
rw
rw
rw
rw
MSIZE[1:0]
PSIZE[1:0]
rw
rw
rw
rw
MINC
PINC
CIRC
rw
rw
rw
DIR[1:0]
rw
rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:25 CHSEL[3:0]: Channel selection
These bits are set and cleared by software.
0000: channel 0 selected
0001: channel 1 selected
0010: channel 2 selected
0011: channel 3 selected
0100: channel 4 selected
0101: channel 5 selected
0110: channel 6 selected
0111: channel 7 selected
1000: channel 8 selected
1001: channel 9 selected
1010: channel 10 selected
1011: channel 11 selected
1100: channel 12 selected
1101: channel 13 selected
1110: channel 14 selected
1111: channel 15 selected
These bits are protected and can be written only if EN is 0.
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17
rw
PINC
OS
rw
26
RM0430 Rev 9
PL[1:0]
RM0430
Direct memory access controller (DMA)
Bits 24:23 MBURST[1:0]: Memory burst transfer configuration
These bits are set and cleared by software.
00: Single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN = 0.
In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN = 1.
Bits 22:21 PBURST[1:0]: Peripheral burst transfer configuration
These bits are set and cleared by software.
00: Single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN = 0.
In direct mode, these bits are forced to 0x0 by hardware.
Bit 20 Reserved, must be kept at reset value.
Bit 19 CT: Current target (only in double-buffer mode)
This bit is set and cleared by hardware. It can also be written by software.
0: Current target memory is memory 0 (addressed by the DMA_SxM0AR pointer).
1: Current target memory is memory 1 (addressed by the DMA_SxM1AR pointer).
This bit can be written only if EN = 0 to indicate the target memory area of the first transfer.
Once the stream is enabled, this bit operates as a status flag indicating which memory area
is the current target.
Bit 18 DBM: Double-buffer mode
This bit is set and cleared by software.
0: No buffer switching at the end of transfer
1: Memory target switched at the end of the DMA transfer
This bit is protected and can be written only if EN = 0.
Bits 17:16 PL[1:0]: priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
These bits are protected and can be written only if EN = 0.
Bit 15 PINCOS: Peripheral increment offset size
This bit is set and cleared by software
0: The offset size for the peripheral address calculation is linked to the PSIZE.
1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment).
This bit has no meaning if bit PINC = 0.
This bit is protected and can be written only if EN = 0.
This bit is forced low by hardware when the stream is enabled (EN = 1) if the direct mode is
selected or if PBURST are different from 00.
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Direct memory access controller (DMA)
RM0430
Bits 14:13 MSIZE[1:0]: Memory data size
These bits are set and cleared by software.
00: Byte (8-bit)
01: Half-word (16-bit)
10: Word (32-bit)
11: Reserved
These bits are protected and can be written only if EN = 0.
In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as
EN = 1.
Bits 12:11 PSIZE[1:0]: Peripheral data size
These bits are set and cleared by software.
00: Byte (8-bit)
01: Half-word (16-bit)
10: Word (32-bit)
11: Reserved
These bits are protected and can be written only if EN = 0.
Bit 10 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory address pointer fixed
1: Memory address pointer incremented after each data transfer (increment is done
according to MSIZE)
This bit is protected and can be written only if EN = 0.
Bit 9 PINC: Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral address pointer fixed
1: Peripheral address pointer incremented after each data transfer (increment done
according to PSIZE)
This bit is protected and can be written only if EN = 0.
Bit 8 CIRC: Circular mode
This bit is set and cleared by software and can be cleared by hardware.
0: Circular mode disabled
1: Circular mode enabled
When the peripheral is the flow controller (bit PFCTRL = 1), and the stream is enabled
(EN = 1), then this bit is automatically forced by hardware to 0.
It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is
enabled (EN = 1).
Bits 7:6 DIR[1:0]: Data transfer direction
These bits are set and cleared by software.
00: Peripheral-to-memory
01: Memory-to-peripheral
10: Memory-to-memory
11: Reserved
These bits are protected and can be written only if EN = 0.
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RM0430
Direct memory access controller (DMA)
Bit 5 PFCTRL: Peripheral flow controller
This bit is set and cleared by software.
0: DMA is the flow controller.
1: The peripheral is the flow controller.
This bit is protected and can be written only if EN = 0.
When the memory-to-memory mode is selected (bits DIR[1:0] = 10), then this bit is
automatically forced to 0 by hardware.
Bit 4 TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 3 HTIE: Half transfer interrupt enable
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
Bit 2 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 1 DMEIE: Direct mode error interrupt enable
This bit is set and cleared by software.
0: DME interrupt disabled
1: DME interrupt enabled
Bit 0 EN: Stream enable/flag stream ready when read low
This bit is set and cleared by software.
0: Stream disabled
1: Stream enabled
This bit is cleared by hardware:
–
on a DMA end of transfer (stream ready to be configured)
–
if a transfer error occurs on the AHB master buses
–
when the FIFO threshold on memory AHB port is not compatible with the burst size
When this bit is read as 0, the software is allowed to program the configuration and FIFO bits
registers. It is forbidden to write these registers when the EN bit is read as 1.
Note: Before setting EN bit to 1 to start a new transfer, the event flags corresponding to
the stream in DMA_LISR or DMA_HISR register must be cleared.
9.5.6
DMA stream x number of data register (DMA_SxNDTR)
Address offset: 0x014 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
NDT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
RM0430 Rev 9
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Direct memory access controller (DMA)
RM0430
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data items to transfer (0 up to 65535)
This bitfield can be written only when the stream is disabled. When the stream is enabled,
this bitfield is read-only, indicating the remaining data items to be transmitted. This bitfield
decrements after each DMA transfer.
Once the transfer is completed, this bitfield can either stay at zero (when the stream is in
normal mode), or be reloaded automatically with the previously programmed value
in the following cases:
–
when the stream is configured in circular mode
–
when the stream is enabled again by setting EN bit to 1
If the value of this bitfield is zero, no transaction can be served even if the stream is enabled.
9.5.7
DMA stream x peripheral address register (DMA_SxPAR)
Address offset: 0x018 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PAR[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
PAR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 PAR[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data is read/written.
These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR.
9.5.8
DMA stream x memory 0 address register
(DMA_SxM0AR)
Address offset: 0x01C + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
M0A[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
M0A[15:0]
rw
Bits 31:0 M0A[31:0]: Memory 0 address
Base address of memory area 0 from/to which the data is read/written.
These bits are write-protected. They can be written only if:
–
the stream is disabled (EN = 0 in DMA_SxCR) or
–
the stream is enabled (EN = 1 in DMA_SxCR) and CT = 1 in DMA_SxCR
(in double-buffer mode).
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RM0430
Direct memory access controller (DMA)
9.5.9
DMA stream x memory 1 address register
(DMA_SxM1AR)
Address offset: 0x020 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
M1A[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
M1A[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 M1A[31:0]: Memory 1 address (used in case of double-buffer mode)
Base address of memory area 1 from/to which the data is read/written.
This bitfield is used only for the double-buffer mode.
These bits are write-protected. They can be written only if:
–
the stream is disabled (EN = 0 in DMA_SxCR) or
–
the stream is enabled (EN = 1 in DMA_SxCR) and bit CT = 0 in DMA_SxCR .
9.5.10
DMA stream x FIFO control register (DMA_SxFCR)
Address offset: 0x024 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0021
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FEIE
Res.
rw
FS[2:0]
r
r
DMDIS
r
rw
FTH[1:0]
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 FEIE: FIFO error interrupt enable
This bit is set and cleared by software.
0: FE interrupt disabled
1: FE interrupt enabled
Bit 6 Reserved, must be kept at reset value.
Bits 5:3 FS[2:0]: FIFO status
These bits are read-only.
000: 0 &lt; fifo_level &lt; 1/4
001: 1/4 ≤ fifo_level &lt; 1/2
010: 1/2 ≤ fifo_level &lt; 3/4
011: 3/4 ≤ fifo_level &lt; full
100: FIFO is empty.
101: FIFO is full.
Others: Reserved (no meaning)
These bits are not relevant in the direct mode (DMDIS = 0).
RM0430 Rev 9
245/1321
250
Direct memory access controller (DMA)
RM0430
Bit 2 DMDIS: Direct mode disable
This bit is set and cleared by software. It can be set by hardware.
0: Direct mode enabled
1: Direct mode disabled
This bit is protected and can be written only if EN = 0.
This bit is set by hardware if the memory-to-memory mode is selected (DIR = 10
in DMA_SxCR), and EN = 1 in DMA_SxCR because the direct mode is not allowed
in the memory-to-memory configuration.
Bits 1:0 FTH[1:0]: FIFO threshold selection
These bits are set and cleared by software.
00: 1/4 full FIFO
01: 1/2 full FIFO
10: 3/4 full FIFO
11: Full FIFO
These bits are not used in the direct mode when the DMIS = 0.
These bits are protected and can be written only if EN = 0.
9.5.11
DMA register map
0x01C
246/1321
TCIF0
HTIF0
TEIF0
DMEIF0
FEIF4
HTIF4
TEIF4
DMEIF4
0
0
0
0
0
CFEIF0
CDMEIF0
0
0
0
0
CFEIF4
0
0
0
0
0
0
0
0
Res
0
0
0
0
EN
0
DMEIE
0
TEIE
0
Res
0
Res
CTEIF0
0
CDMEIF4
CHTIF0
0
CTEIF4
CTCIF0
0
CHTIF4
0
CTCIF4
CFEIF1
0
Res
CDMEIF1
0
CFEIF5
CTEIF1
0
HTIE
0
Res
TCIF4
0
TCIE
0
Res.
FEIF1
FEIF5
0
Res
DMEIF5
0
PFCTRL
0
FEIF0
TEIF1
DMEIF1
TEIF5
0
PSIZE[1:0]
0
Res.
HTIF1
HTIF5
0
CHTIF1
Res.
TCIF1
TCIF5
Res.
Res.
Res.
0
CTCIF1
Res
0
DIR[1:0]
Res
0
CDMEIF5
Res
0
CIRC
Res
0
CTEIF5
Res
0
0
0
0
0
0
0
NDT[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S0M0AR
Reset value
0
CHTIF5
Res
0
DMA_S0PAR
Reset value
0
PINC
Res
0
Reset value
0x018
0
MINC
0
MSIZE[1:0]
0
PINCOS
0
0
CTCIF5
CFEIF6
0
PL[1:0]
0
Res
0
Res
0
DBM
0
0
0
Res
0
CT
0
Res
0
PBURST[1:0]
CHSEL[3:0]
0
Res
0
Res
0
MBURST[1:0]
0
Res
CDMEIF2
CFEIF7
0
0
Res
CFEIF2
CTEIF2
0
CDMEIF6
CHTIF2
0
CTEIF6
CTCIF2
0
CHTIF6
0
CTCIF6
CFEIF3
0
Res
CDMEIF3
0
Res
TEIF3
0
CDMEIF7
CHTIF3
0
CTEIF7
0
CHTIF7
0
Res
0
Res
0
Res
DMEIF6
0
Res
TEIF6
0
Res
HTIF6
0
Res
TCIF6
0
Res
FEIF7
0
Res
DMEIF7
0
Res
FEIF6
TEIF7
0
Res
HTIF7
0
Res
TEIF2
DMEIF2
0
Res
HTIF2
0
Res
TCIF2
0
Res.
FEIF3
0
FEIF2
TEIF3
DMEIF3
0
Res.
HTIF3
0
Res
Res
Res
DMA_S0NDTR
Res
0x014
Res
Reset value
0
Res
Res
DMA_S0CR
0x010
Res
Reset value
0
TCIF7
Res.
Res
Res
Res
DMA_HIFCR
0x00C
Res
Reset value
0
CTCIF3
Res
Res
Res
DMA_LIFCR
0x008
Res
Reset value
0
CTCIF7
Res
Res
Res
DMA_HISR
0x004
Res
Reset value
TCIF3
DMA_LISR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000
Register
name
Res.
Offset
Res.
Table 39. DMA register map and reset values
0
0
0
M0A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0430 Rev 9
0
0
0
RM0430
Direct memory access controller (DMA)
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S0FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
0
0
0
0
0
0
0
FS[2:0]
FTH
[1:0]
0
1
0
0
0
0
1
Reset value
0x030
0x034
CIRC
DIR[1:0]
PSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S1FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
FEIE
Res
FS[2:0]
DMDIS
FTH[1:0]
M1A[31:0]
1
0
0
0
0
1
DIR
[1:0]
PFCTRL
TCIE
HTIE
TEIE
DMEIE
EN
0
CIRC
0
0
0
0
0
0
0
0
0
0
0
0
NDT[15:0]
0
DMA_S2PAR
0
PINC
0
PSIZE[1:0]
0
MINC
Res
0
MSIZE[1:0]
Res
0
PINCOS
Res
PL[1:0]
Res
0
Res
Res
0
Res
0
DBM
0
Res
0
CT
0
Res
0
Res
0
Res
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[3:0]
0
Res
Res
Res
Res
Res
DMA_S2NDTR
0
Res
Res
Res
DMA_S2CR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S2M0AR
0
0
0
M0A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S2FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
FEIE
Res
FS[2:0]
DMDIS
FTH[1:0]
M1A[31:0]
Res
DMA_S2M1AR
0
Res
0x054
0
0
Reset value
0x050
0
Reset value
Reset value
0x04C
0
Res
DMA_S1M1AR
0
Reset value
0x048
0
M0A[31:0]
Reset value
0x044
0
NDT[15:0]
Reset value
0x040
0
Res
0x03C
0
Res
0x038
0
0
PA[31:0]
DMA_S1M0AR
Reset value
0
0
DMA_S1PAR
Reset value
0
PINC
Res
0
MINC
Res
0
MSIZE[1:0]
Res
0
PINCOS
Res
PL[1:0]
Res
0
Res
0
Res
0
DBM
0
Res
0
CT
0
Res
0
Res
0
Res
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[3:0]
0
Res
Res
Res
DMA_S1NDTR
Res
0x02C
Res
Reset value
Res
DMA_S1CR
Res
0x028
0
Res
Reset value
0
EN
0
DMDIS
0
TEIE
0
DMEIE
0
HTIE
0
TCIE
0
Res
0
PFCTRL
0
Res
0
FEIE
Reset value
Res
M1A[31:0]
Res
0x024
DMA_S0M1AR
Res
0x020
Register
name
Res
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 39. DMA register map and reset values (continued)
1
0
0
Reset value
0
RM0430 Rev 9
0
0
1
247/1321
250
Direct memory access controller (DMA)
RM0430
Reset value
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S3FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
FEIE
Res
FS[2:0]
DMDIS
FTH[1:0]
1
0
0
0
0
1
PFCTRL
TCIE
HTIE
TEIE
DMEIE
EN
0
DIR
[1:0]
0
CIRC
0
PINC
0
PSIZE[1:0]
0
MINC
Res
0
MSIZE[1:0]
Res
0
PINCOS
Res
PL[1:0]
Res
0
Res
Res
0
Res
0
DBM
0
Res
0
CT
0
Res
Res
0
Res
0
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[3:0]
0
Res
Res
Res
Res
Res
0
Res
Res
Res
0
0
0
0
0
0
0
0
0
0
0
0
NDT[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S4M0AR
0
0
0
M0A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S4FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
FEIE
Res
FS[2:0]
DMDIS
FTH[1:0]
1
0
0
0
0
1
Reset value
0
DIR[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NDT[15:0]
0
RM0430 Rev 9
0
CIRC
0
PSIZE[1:0]
0
PINC
Res
0
MINC
Res
0
MSIZE[1:0]
Res
0
PINCOS
Res
PL[1:0]
Res
0
Res
0
Res
0
DBM
0
Res
0
CT
0
Res
Res
0
Res
0
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[3:0]
0
Res
Res
Res
Res
DMA_S5NDTR
Res
Reset value
Res
Res
DMA_S5CR
0
Res
Reset value
EN
0
DMEIE
0
TEIE
0
HTIE
0
TCIE
Reset value
Res
M1A[31:0]
Res
DMA_S4M1AR
248/1321
EN
0
0
Reset value
0x08C
TEIE
0
0
DMA_S4PAR
0x088
0
0
DMA_S4NDTR
0x084
0
0
Reset value
0x080
0
0
Reset value
0x07C
0
Reset value
DMA_S4CR
0x078
0
M1A[31:0]
Reset value
0x074
0
NDT[15:0]
Reset value
0x070
0
DMEIE
0
HTIE
0
TCIE
DIR[1:0]
0
PFCTRL
PINC
PSIZE[1:0]
0
M0A[31:0]
DMA_S3M1AR
0x06C
0
Res
0x068
0
PA[31:0]
DMA_S3M0AR
Reset value
0
PFCTRL
0x064
0
0
DMA_S3PAR
0x060
0
CIRC
Res
0
MINC
Res
0
MSIZE[1:0]
Res
0
PINCOS
Res
PL[1:0]
Res
0
Res
0
Res
0
CT
0
DBM
0
Res
0
Res
0
Res
Res
PBURST[1:0]
CHSEL[3:0]
0
Res
Res
0
Res
Res
DMA_S3NDTR
Res
0x05C
Res
Reset value
Res
DMA_S3CR
MBURST[1:0]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x058
Register
name
Res
Offset
Res
Table 39. DMA register map and reset values (continued)
0
0
0
0
0
0
0
0
0
RM0430
Direct memory access controller (DMA)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS[2:0]
FTH[1:0]
0
1
0
0
0
0
1
M0A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S5FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Reset value
CIRC
DIR[1:0]
PSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S6FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
FEIE
Res
FS[2:0]
DMDIS
FTH[1:0]
1
0
0
0
0
1
0
0
DIR[1:0]
PSIZE[1:0]
PINCOS
MSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
NDT[15:0]
0
DMA_S7PAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S7M0AR
Reset value
0
CIRC
Res
0
PINC
Res
0
MINC
Res
PL[1:0]
Res
0
Res
Res
0
Res
0
DBM
0
Res
0
CT
0
Res
0
Res
0
Res
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[3:0]
0
Res
Res
Res
Res
Res
DMA_S7NDTR
0
Res
Res
Res
DMA_S7CR
0
EN
0
DMEIE
0
TEIE
0
Res
M1A[31:0]
Reset value
Reset value
0x0C4
0
Res
DMA_S6M1AR
0
Reset value
0x0C0
0
M0A[31:0]
Reset value
0x0BC
0
0
Reset value
0x0B8
0
Res
0x0B4
0
Res
0x0B0
0
PA[31:0]
DMA_S6M0AR
Reset value
0
HTIE
0x0AC
0
NDT[15:0]
0
DMA_S6PAR
Reset value
0
TCIE
0x0A8
0
PINC
Res
0
MINC
Res
0
MSIZE[1:0]
Res
0
PINCOS
Res
PL[1:0]
Res
0
Res
0
Res
0
DBM
0
Res
0
CT
0
Res
0
Res
0
Res
Res.
PBURST[1:0]
MBURST[1:0]
CHSEL[3:0]
0
Res
Res.
Res
DMA_S6NDTR
Res
0x0A4
Res
Reset value
Res
DMA_S6CR
Res.
0x0A0
0
Res.
Reset value
EN
0
TEIE
0
DMEIE
0
HTIE
0
TCIE
Reset value
Res
M1A[31:0]
Res
DMA_S5M1AR
0
Res
0x09C
0
DMA_S5M0AR
Reset value
0x098
0
PFCTRL
0x094
0
PFCTRL
Reset value
DMDIS
PA[31:0]
Res
DMA_S5PAR
Res
0x090
Register
name
FEIE
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 39. DMA register map and reset values (continued)
0
0
0
M0A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0430 Rev 9
0
0
0
249/1321
250
Direct memory access controller (DMA)
RM0430
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S7FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Reset value
0
0
0
0
0
FS[2:0]
1
0
0
0
Refer to Section 2.2 for the register boundary addresses.
250/1321
0
FTH[1:0]
0
DMDIS
0
Res
0
Res
0
FEIE
0
Res
0x0CC
Reset value
Res
M1A[31:0]
Res
0x0C8
Res
DMA_S7M1AR
Offset
Res
Register
name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 39. DMA register map and reset values (continued)
RM0430 Rev 9
0
0
0
0
0
1
RM0430
Interrupts and events
10
Interrupts and events
10.1
Nested vectored interrupt controller (NVIC)
10.1.1
NVIC features
The nested vector interrupt controller NVIC includes the following features:
•
52 maskable interrupt channels (not including the 16 interrupt lines of Cortex&reg;-M4 with
FPU)
•
16 programmable priority levels (4 bits of interrupt priority are used)
•
low-latency exception and interrupt handling
•
power management control
•
implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to programming manual PM0214.
10.1.2
SysTick calibration value register
The SysTick calibration value is fixed to 10500, which gives a reference time base of 1 ms
with the SysTick clock set to 10.5 MHz (HCLK/8, with HCLK set to 84 MHz).
10.1.3
Interrupt and exception vectors
See Table 40, for the vector table for the STM32F413/423 devices.
10.2
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of up to 23 edge detectors for generating
event/interrupt requests. Each input line can be independently configured to select the type
(interrupt or event) and the corresponding trigger event (rising or falling or both). Each line
can also masked independently. A pending register maintains the status line of the interrupt
requests.
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265
Interrupts and events
RM0430
Position
Priority
Table 40. Vector table for STM32F413/423
Type of
priority
-
-
-
-
Reserved
0x0000 0000
-
-3
fixed
Reset
Reset
0x0000 0004
-
-2
fixed
NMI
Non maskable interrupt, Clock Security
System
0x0000 0008
-
-1
fixed
HardFault
All class of fault
0x0000 000C
-
0
settable
MemManage
Memory management
0x0000 0010
-
1
settable
BusFault
Pre-fetch fault, memory access fault
0x0000 0014
-
2
settable
UsageFault
Undefined instruction or illegal state
0x0000 0018
-
-
-
-
Reserved
0x0000 001C 0x0000 002B
-
3
settable
SVCall
System Service call via SWI instruction
0x0000 002C
-
4
settable
Debug Monitor
Debug Monitor
0x0000 0030
-
-
Reserved
0x0000 0034
-
Acronym
Description
Address
-
5
settable
PendSV
Pendable request for system service
0x0000 0038
-
6
settable
Systick
System tick timer
0x0000 003C
0
7
settable
WWDG
Window Watchdog interrupt
0x0000 0040
1
8
settable
PVD
PVD through EXTI line detection interrupt
0x0000 0044
2
9
settable
TAMP_STAMP
Tamper and TimeStamp interrupts
through the EXTI line
0x0000 0048
3
10
settable
RTC_WKUP
RTC Wakeup interrupt through the EXTI line
0x0000 004C
4
11
settable
FLASH
Flash global interrupt
0x0000 0050
5
12
settable
RCC
RCC global interrupt
0x0000 0054
6
13
settable
EXTI0
EXTI Line0 interrupt
0x0000 0058
7
14
settable
EXTI1
EXTI Line1 interrupt
0x0000 005C
8
15
settable
EXTI2
EXTI Line2 interrupt
0x0000 0060
9
16
settable
EXTI3
EXTI Line3 interrupt
0x0000 0064
10
17
settable
EXTI4
EXTI Line4 interrupt
0x0000 0068
11
18
settable
DMA1_Stream0
DMA1 Stream0 global interrupt
0x0000 006C
12
19
settable
DMA1_Stream1
DMA1 Stream1 global interrupt
0x0000 0070
13
20
settable
DMA1_Stream2
DMA1 Stream2 global interrupt
0x0000 0074
14
21
settable
DMA1_Stream3
DMA1 Stream3 global interrupt
0x0000 0078
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RM0430 Rev 9
RM0430
Interrupts and events
Position
Priority
Table 40. Vector table for STM32F413/423 (continued)
Type of
priority
15
22
settable
DMA1_Stream4
DMA1 Stream4 global interrupt
0x0000 007C
16
23
settable
DMA1_Stream5
DMA1 Stream5 global interrupt
0x0000 0080
17
24
settable
DMA1_Stream6
DMA1 Stream6 global interrupt
0x0000 0084
18
25
settable
ADC
ADC1 global interrupt
0x0000 0088
19
26
settable
CAN1_TX
CAN1 TX interrupt
0x0000 008C
20
27
settable
CAN1_RX0
CAN1 RX0 interrupt
0x0000 0090
21
28
settable
CAN1_RX1
CAN1 RX1 interrupt
0x0000 0094
22
29
settable
CAN1_SCE
CAN1 SCE interrupt
0x0000 0098
23
30
settable
EXTI9_5
EXTI Line[9:5] interrupts
0x0000 009C
24
31
settable
TIM1_BRK_TIM9
TIM1 Break interrupt
and TIM9 global interrupt
0x0000 00A0
25
32
settable
TIM1_UP_TIM10
TIM1 update interrupt
and TIM10 global interrupt
0x0000 00A4
26
33
settable
TIM_TRG_COM_TIM11
TIM1 Trigger &amp; Commutation interrupts
and TIM11 global interrupt
0x0000 00A8
27
34
settable
TIM1_CC
TIM1 Capture Compare interrupt
0x0000 00AC
28
35
settable
TIM2
TIM2 global interrupt
0x0000 00B0
29
36
settable
TIM3
TIM3 global interrupt
0x0000 00B4
30
37
settable
TIM4
TIM4 global interrupt
0x0000 00B8
31
38
settable
I2C1_EVT
I2C1 global event interrupt
0x0000 00BC
32
39
settable
I2C1_ERR
I2C1 global error interrupt
0x0000 00C0
33
40
settable
I2C2_EVT
I2C2 global event interrupt
0x0000 00C4
34
41
settable
I2C2_ERR
I2C2 global error interrupt
0x0000 00C8
35
42
settable
SPI1
SPI1 global interrupt
0x0000 00CC
36
43
settable
SPI2
SPI2 global interrupt
0x0000 00D0
37
44
settable
USART1
USART1 global interrupt
0x0000 00D4
38
45
settable
USART2
USART2 global interrupt
0x0000 00D8
39
46
settable
USART 3
USART3 global interrupt
0x0000 00DC
40
47
settable
EXTI15_10
EXTI Line[15:10] interrupts
0x0000 00E0
Acronym
Description
Address
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Interrupts and events
RM0430
Position
Priority
Table 40. Vector table for STM32F413/423 (continued)
Type of
priority
41
48
settable
EXTI17 /
RTC Alarm
EXTI Line 17 interrupt /
RTC Alarms (A and B) through EXTI line
interrupt
0x0000 00E4
42
49
settable
EXTI18 / OTG_FS_WKUP
EXTI Line 18 interrupt / USB On-The-Go FS
Wakeup through EXTI line interrupt
0x0000 00E8
43
50
settable
TIM8_BRK_TIM12
TIM8 Break interrupt
TIM12 global interrupt
0x0000 00EC
44
51
settable
TIM8_UP_TIM13
TIM8 Update interrupt
TIM13 global interrupt
0x0000 00F0
45
52
settable
TIM8_TRG_COM_TIM14
TIM8 Trigger &amp; Commutation interrupt
TIM14 global interrupt
0x0000 00F4
46
53
settable
TIM8_CC
TIM8 Cap/Com interrupt
0x0000 00F8
47
54
settable
DMA1_Stream7
DMA1 global interrupt Channel 7
0x0000 00FC
48
55
settable
FSMC
FSMC global interrupt
0x0000 0100
49
56
settable
SDIO
SDIO global interrupt
0x0000 0104
50
57
settable
TIM5
TIM5 global interrupt
0x0000 0108
51
58
settable
SPI3
SPI3 global interrupt
0x0000 010C
52
59
settable
UART4
UART4 global interrupt
0x0000 0110
53
60
settable
UART5
UART5 global interrupt
0x0000 0114
54
61
settable
TIM6_GLB_IT/DAC1/DAC2
TIMER6, DAC1 and DAC2 global interrupt
0x0000 0118
55
62
settable
TIM7
TIM7 global interrupt
0x0000 011C
56
63
settable
DMA2_Stream0
DMA2 Stream0 global interrupt
0x0000 0120
57
64
settable
DMA2_Stream1
DMA2 Stream1 global interrupt
0x0000 0124
58
65
settable
DMA2_Stream2
DMA2 Stream2 global interrupt
0x0000 0128
59
66
settable
DMA2_Stream3
DMA2 Stream3 global interrupt
0x0000 012C
60
67
settable
DMA2_Stream4
DMA2 Stream4 global interrupt
0x0000 0130
61
68
settable
DFSDM1_FLT0
SD filter0 global interrupt
0x0000 0134
62
69
settable
DFSDM1_FLT1
SD filter1 global interrupt
0x0000 0138
63
70
settable
CAN2_TX
CAN2 TX interrupt
0x0000 013C
64
71
settable
CAN2_RX0
BXCAN2 RX0 interrupt
0x0000 0140
65
72
settable
CAN2_RX1
BXCAN2 RX1 interrupt
0x0000 0144
66
73
settable
CAN2_SCE
CAN2 SCE interrupt
0x0000 0148
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Acronym
Description
Address
RM0430 Rev 9
RM0430
Interrupts and events
Position
Priority
Table 40. Vector table for STM32F413/423 (continued)
Type of
priority
67
74
settable
OTG_FS
USB On The Go FS global interrupt
0x0000 014C
68
75
settable
DMA2_Stream5
DMA2 Stream5 global interrupt
0x0000 0150
69
76
settable
DMA2_Stream6
DMA2 Stream6 global interrupt
0x0000 0154
70
77
settable
DMA2_Stream7
DMA2 Stream7 global interrupt
0x0000 0158
71
78
settable
USART6
USART6 global interrupt
0x0000 015C
I2C3_EV
I
2C3 event interrupt
0x0000 0160
0x0000 0164
72
79
settable
Acronym
Description
Address
73
80
settable
I2C3_ER
I2C3 error interrupt
74
81
settable
CAN3_TX
CAN 3 TX interrupt
0x0000 0168
75
82
settable
CAN3_RX0
BxCAN 3 RX0 interrupt
0x0000 016C
76
83
settable
CAN3_RX1
BxCAN 3 RX1 interrupt
0x0000 0170
77
84
settable
CAN3_SCE
CAN 3 SCE interrupt
0x0000 0174
79
86
settable
CRYPTO(1)
AES global interrupt
0x0000 017C
80
87
settable
RNG
RNG global interrupt
0x0000 0180
81
88
settable
FPU
FPU global interrupt
0x0000 0184
82
89
settable
UART7
UART7 global interrupt
0x0000 0188
83
90
settable
UART8
UART8 global interrupt
0x0000 018C
84
91
settable
SPI4
SPI4 global interrupt
0x0000 0190
85
92
settable
SPI5
SPI5 global interrupt
0x0000 0194
87
94
settable
SAI1
SAI1 global interrupt
0x0000 019C
88
95
settable
UART9
UART9 global interrupt
0x0000 01A0
89
96
settable
UART10
UART10 global interrupt
0x0000 01A4
92
99
settable
Quad-SPI
Quad-SPI global interrupt
0x0000 01B0
95
102
settable
I2CFMP1 event
I2CFMP1 event interrupt
0x0000 01BC
96
103
settable
I2CFMP1 error
I2CFMP1 error interrupt
0x0000 01C0
97
104
settable
EXTI23 / LPTIM1
LP Timer global interrupt or
EXTI interrupt line 23
0x0000 01C4
98
105
settable
DFSDM2_FLT0
DFSDM2 SD filter 0 global interrupt
0x0000 01C8
99
106
settable
DFSDM2_FLT1
DFSDM2 SD filter 1 global interrupt
0x0000 01CC
100
107
settable
DFSDM2_FLT2
DFSDM2 SD filter 2 global interrupt
0x0000 01D0
101
108
settable
DFSDM2_FLT3
DFSDM2 SD filter 3 global interrupt
0x0000 01D4
1. Only available for STM32F423xx.
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Interrupts and events
10.2.1
RM0430
EXTI main features
The main features of the EXTI controller are the following:
10.2.2
•
independent trigger and mask on each interrupt/event line
•
dedicated status bit for each interrupt line
•
generation of up to 23 software event/interrupt requests
•
detection of external signals with a pulse width lower than the APB2 clock period. Refer
to the electrical characteristics section of the STM32F4xx datasheets for details on this
parameter.
EXTI block diagram
Figure 29 shows the block diagram.
Figure 29. External interrupt/event controller block diagram
AMBA APB bus
PCLK2
Peripheral interface
23
23
23
Pending
request
register
Interrupt
mask
register
Software
interrupt
event
register
23
To NVIC interrupt
controller
23
23
23
Rising
trigger
selection
register
23
Falling
trigger
selection
register
23
23
23
Pulse
generator
23
23
Edge detect
circuit
Input
line
Event
mask
register
MS32662V1
10.2.3
Wakeup event management
The STM32F4xx are able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
•
256/1321
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex&reg;-M4 with FPU System Control register. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC
RM0430 Rev 9
RM0430
Interrupts and events
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
•
or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
To use an external line as a wakeup event, refer to Section 10.2.4: Functional description.
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Interrupts and events
10.2.4
RM0430
Functional description
To generate the interrupt, the interrupt line should be configured and enabled. This is done
by programming the two trigger registers with the desired edge detection and by enabling
the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register.
When the selected edge occurs on the external interrupt line, an interrupt request is
generated. The pending bit corresponding to the interrupt line is also set. This request is
reset by writing a ‘1’ in the pending register.
To generate the event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a ‘1’ to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set.
An interrupt/event request can also be generated by software by writing a ‘1’ in the software
interrupt/event register.
Hardware interrupt selection
To configure the 23 lines as interrupt sources, use the following procedure:
•
Configure the mask bits of the 23 interrupt lines (EXTI_IMR)
•
Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)
•
Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
external interrupt controller (EXTI) so that an interrupt coming from one of the 23 lines
can be correctly acknowledged.
Hardware event selection
To configure the 23 lines as event sources, use the following procedure:
•
Configure the mask bits of the 23 event lines (EXTI_EMR)
•
Configure the Trigger selection bits of the event lines (EXTI_RTSR and EXTI_FTSR)
Software interrupt/event selection
The 23 lines can be configured as software interrupt/event lines. The following is the
procedure to generate a software interrupt.
258/1321
•
Configure the mask bits of the 23 interrupt/event lines (EXTI_IMR, EXTI_EMR)
•
Set the required bit in the software interrupt register (EXTI_SWIER)
RM0430 Rev 9
RM0430
10.2.5
Interrupts and events
External interrupt/event line mapping
Up to STM32F413/423 are connected to the 16 external interrupt/event lines in the following
manner:
Figure 30. External interrupt/event GPIO mapping
EXTI0[3:0] bits in the SYSCFG_EXTICR1 register
PA0
PB0
PC0
PD0
PE0
PF0
EXTI0
PG0
PH0
EXTI1[3:0] bits in the SYSCFG_EXTICR1 register
PA1
PB1
PC1
PD1
PE1
PF1
PG1
PH1
EXTI1
...
EXTI15[3:0] bits in the SYSCFG_EXTICR4 register
PA15
PB15
PC15
PD15
PE15
PF15
PG15
EXTI15
MSv39617V1
The five other EXTI lines are connected as follows:
•
EXTI line 16 is connected to the PVD output
•
EXTI line 17 is connected to the RTC Alarm event
•
EXTI line 18 is connected to the USB OTG FS Wakeup event
•
EXTI line 21 is connected to the RTC Tamper and TimeStamp events
•
EXTI line 22 is connected to the RTC Wakeup event
•
EXTI line 23 is connected to the LPTIM1 asynchronous event
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Interrupts and events
10.3
RM0430
EXTI registers
Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in
register descriptions.
10.3.1
Interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MR23
MR22
MR21
Res.
Res.
MR18
MR17
MR16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MR15
MR14
MR13
MR12
MR11
MR10
MR9
MR8
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:21 MR[23:21]: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 MR[18:0]: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
10.3.2
Event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MR23
MR22
MR21
Res.
Res.
MR18
MR17
MR16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MR15
MR14
MR13
MR12
MR11
MR10
MR9
MR8
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:21 MR[23:21]: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 MR[18:0]: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
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RM0430 Rev 9
RM0430
Interrupts and events
10.3.3
Rising trigger selection register (EXTI_RTSR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TR23
TR22
TR21
Res.
Res.
TR18
TR17
TR16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TR15
TR14
TR13
TR12
TR11
TR10
TR9
TR8
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:21 TR[23:21]: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 TR[18:0]: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Note:
The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register,
the pending bit is be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
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10.3.4
RM0430
Falling trigger selection register (EXTI_FTSR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TR23
TR22
TR21
Res.
Res.
TR18
TR17
TR16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TR15
TR14
TR13
TR12
TR11
TR10
TR9
TR8
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:21 TR[23:21]: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 TR[18:0]: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Note:
The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register,
the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
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Interrupts and events
10.3.5
Software interrupt event register (EXTI_SWIER)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
SWIER SWIER SWIER SWIER SWIER SWIER SWIER
15
14
13
12
11
10
9
rw
rw
rw
rw
rw
rw
rw
23
22
21
SWIER SWIER SWIER
23
22
21
rw
rw
rw
7
6
5
20
19
Res.
Res.
4
3
18
17
16
SWIER SWIER SWIER
18
17
16
rw
rw
rw
2
1
0
SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:21 SWIER[23:21]: Software Interrupt on line x
If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is
set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 SWIER[18:0]: Software Interrupt on line x
If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is
set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).
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10.3.6
RM0430
Pending register (EXTI_PR)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PR23
PR22
PR21
Res.
Res.
PR18
PR17
PR16
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PR15
PR14
PR13
PR12
PR11
PR10
PR9
PR8
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:21 PR[22:21]: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by programming it to ‘1’.
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 PR[18:0]: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by programming it to ‘1’.
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10.3.7
Interrupts and events
EXTI register map
Table 41 gives the EXTI register map and the reset values.
Reset value
0
0
Res.
Res.
0
Res.
Res.
0
0
0
0
0
0
0
0
Res.
Res.
0
0
0
0
0
0
0
0
Res.
Res.
0
0
0
0
0
0
0
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SWIER[18:0]
0
0
0
0
0
0
0
0
Res.
0
0
0
TR[18:0]
0
Res.
0
PR
[23:21]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_PR
0
0
TR[18:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
SWIER
[23:21]
Res.
EXTI_SWIER
0
0
0
MR[18:0]
0
0
TR
[23:21]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
MR[18:0]
0
0
0
Reset value
0x14
0
Reset value
Res.
0x10
EXTI_FTSR
Res.
0x0C
0
Res.
Reset value
0
TR
[23:21]
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_RTSR
Res.
0x08
0
Res.
Reset value
0
MR
[23:21]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_EMR
0
Res.
Reset value
0x04
MR
[23:21]
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_IMR
Res.
0x00
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 41. External interrupt/event controller register map and reset values
0
0
0
PR[18:0]
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2 on page 57 for the register boundary addresses.
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RM0430
11
Flexible memory controller (FMC)
11.1
Introduction
The flexible memory controller (FMC) includes one memory controller:
•
11.2
The NOR/PSRAM memory controller
FSMC main features
The FSMC functional block makes the interface with: synchronous and asynchronous static
memories. Its main purposes are:
•
to translate AHB transactions into the appropriate external device protocol
•
to meet the access time requirements of the external memory devices
All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique chip select. The FSMC performs
only one access at a time to an external device.
The main features of the FSMC controller are the following:
•
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR flash memory
–
PSRAM (4 memory banks)
•
Interface with parallel LCD modules, supporting Intel 8080 and Motorola 6800 modes.
•
Burst mode support for faster access to synchronous devices such as NOR flash
memory, PSRAM)
•
Programmable continuous clock output for asynchronous and synchronous accesses
•
8-,16-bit wide data bus
•
Independent chip select control for each memory bank
•
Independent configuration for each memory bank
•
Write enable and byte lane select outputs for use with PSRAM, SRAM devices
•
External asynchronous wait control
•
Write FIFO with 16 x32-bit depth
The Write FIFO is common to all memory controllers and consists of:
•
a Write Data FIFO which stores the AHB data to be written to the memory (up to 32
bits) plus one bit for the AHB transfer (burst or not sequential mode)
•
a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data
size (up to 2 bits). When operating in burst mode, only the start address is stored
except when crossing a page boundary (for PSRAM). In this case, the AHB burst is
broken into two FIFO entries.
The Write FIFO can be disabled by setting the WFDIS bit in the FSMC_BCR1 register.
At startup the FSMC pins must be configured by the user application. The FSMC I/O pins
which are not used by the application can be used for other purposes.
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Flexible memory controller (FMC)
The FSMC registers that define the external device type and associated characteristics are
usually set at boot time and do not change until the next reset or power-up. However, the
settings can be changed at any time.
11.3
FMC block diagram
The FSMC consists of the following main blocks:
•
The AHB interface (including the FSMC configuration registers)
•
The NOR flash/PSRAM/SRAM controller
The block diagram is shown in the figure below.
Figure 31. FSMC block diagram
FSMC interrupts to NVIC
FSMC_NL (or NADV)
FSMC_CLK
From clock
controller
HCLK
Configuration
registers
NOR/PSRAM
memory
controller
NOR/PSRAM
signals
FSMC_NBL[1:0]
NOR / PSRAM / SRAM
shared signals
FSMC_A[25:0]
FSMC_D[15:0]
Shared signals
FSMC_NE[4:1]
FSMC_NOE
FSMC_NWE
FSMC_NWAIT
NOR / PSRAM / SRAM
shared signals
MSv39279V2
11.4
AHB interface
The AHB slave interface allows internal CPUs and other bus master peripherals to access
the external memories.
AHB transactions are translated into the external device protocol. In particular, if the
selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split
into consecutive 16- or 8-bit accesses. The FSMC chip select (FSMC_NEx) does not toggle
between the consecutive accesses except in case of Access mode D when the Extended
mode is enabled.
The FSMC generates an AHB error in the following conditions:
•
When reading or writing to a FSMC bank (Bank 1 to 4) which is not enabled.
•
When reading or writing to the NOR flash bank while the FACCEN bit is reset in the
FSMC_BCRx register.
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RM0430
The effect of an AHB error depends on the AHB master which has attempted the R/W
access:
•
If the access has been attempted by the Cortex&reg;-M4 with FPU CPU, a hard fault
interrupt is generated.
•
If the access has been performed by a DMA controller, a DMA transfer error is
generated and the corresponding DMA channel is automatically disabled.
The AHB clock (HCLK) is the reference clock for the FSMC.
11.4.1
Supported memories and transactions
General transaction rules
The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the
accessed external device has a fixed data width. This may lead to inconsistent transfers.
Therefore, some simple transaction rules must be followed:
•
AHB transaction size and memory data size are equal
There is no issue in this case.
•
AHB transaction size is greater than the memory size:
In this case, the FSMC splits the AHB transaction into smaller consecutive memory
accesses to meet the external data width. The FSMC chip select (FSMC_NEx) does
not toggle between the consecutive accesses.
•
AHB transaction size is smaller than the memory size:
The transfer may or not be consistent depending on the type of external device:
–
Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM)
In this case, the FSMC allows read/write transactions and accesses to the right
data through its byte lanes NBL[1:0].
Bytes to be written are addressed by NBL[1:0].
All memory bytes are read (NBL[1:0] are driven low during read transaction) and
the useless ones are discarded.
–
Accesses to devices that do not have the byte select feature (NOR)
This situation occurs when a byte access is requested to a 16-bit wide flash
memory. Since the device cannot be accessed in Byte mode (only 16-bit words
can be read/written from/to the flash memory), Write transactions and Read
transactions are allowed (the controller reads the entire 16-bit memory word and
uses only the required byte).
Wrap support for NOR flash/PSRAM
Wrap burst mode for synchronous memories is not supported. The memories must be
configured in Linear burst mode of undefined length.
Configuration registers
The FSMC can be configured through a set of registers. Refer to Section 11.6.6, for a
detailed description of the NOR flash/PSRAM controller registers.
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11.5
Flexible memory controller (FMC)
External device address mapping
From the FSMC point of view, the external memory is divided into fixed-size banks of
256 Mbytes each (see Figure 32):
•
Bank 1 used to address up to 4 NOR flash memory or PSRAM devices. This bank is
split into 4 NOR/PSRAM subbanks with 4 dedicated chip selects, as follows:
–
Bank 1 - NOR/PSRAM 1
–
Bank 1 - NOR/PSRAM 2
–
Bank 1 - NOR/PSRAM 3
–
Bank 1 - NOR/PSRAM 4
For each bank the type of memory to be used can be configured by the user application
through the Configuration register.
Figure 32. FSMC memory banks
Address
Bank
Supported memory type
Bank 1
4 x 64 MB
NOR/PSRAM/SRAM
0x6000 0000
0x6FFF FFFF
MS34476V1
11.5.1
NOR/PSRAM address mapping
HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 42.
Table 42. NOR/PSRAM bank selection
HADDR[27:26](1)
Selected bank
00
Bank 1 - NOR/PSRAM 1
01
Bank 1 - NOR/PSRAM 2
10
Bank 1 - NOR/PSRAM 3
11
Bank 1 - NOR/PSRAM 4
1. HADDR are internal AHB address lines that are translated to external memory.
The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.
Table 43. NOR/PSRAM External memory address
Memory width
(1)
Data address issued to the memory
Maximum memory capacity (bits)
8-bit
HADDR[25:0]
64 Mbytes x 8 = 512 Mbits
16-bit
HADDR[25:1] &gt;&gt; 1
64 Mbytes/2 x 16 = 512 Mbits
1. In case of a 16-bit external memory width, the FSMC internally uses HADDR[25:1] to generate the address
for external memory FSMC_A[24:0].
Whatever the external memory width, FSMC_A[0] must be connected to external memory address A[0].
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11.6
RM0430
NOR flash/PSRAM controller
The FSMC generates the appropriate signal timings to drive the following types of
memories:
•
•
•
Asynchronous SRAM and ROM
–
8 bits
–
16 bits
PSRAM (CellularRAM™)
–
Asynchronous mode
–
Burst mode for synchronous accesses
–
Multiplexed or non-multiplexed
NOR flash memory
–
Asynchronous mode
–
Burst mode for synchronous accesses
–
Multiplexed or non-multiplexed
The FSMC outputs a unique chip select signal, NE[4:1], per bank. All the other signals
(addresses, data and control) are shared.
The FSMC supports a wide range of devices through a programmable timings among
which:
•
Programmable wait states (up to 15)
•
Programmable bus turnaround cycles (up to 15)
•
Programmable output enable and write enable delays (up to 15)
•
Independent read and write timings and protocol to support the widest variety of
memories and timings
•
Programmable continuous clock (FSMC_CLK) output.
The FSMC Clock (FSMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the
selected external device either during synchronous accesses only or during asynchronous
and synchronous accesses depending on the CCKEN bit configuration in the FSMC_BCR1
register:
•
If the CCLKEN bit is reset, the FSMC generates the clock (CLK) only during
synchronous accesses (Read/write transactions).
•
If the CCLKEN bit is set, the FSMC generates a continuous clock during asynchronous
and synchronous accesses. To generate the FSMC_CLK continuous clock, Bank 1
must be configured in Synchronous mode (see Section 11.6.6: NOR/PSRAM controller
registers). Since the same clock is used for all synchronous memories, when a
continuous output clock is generated and synchronous accesses are performed, the
AHB data size has to be the same as the memory data width (MWID) otherwise the
FSMC_CLK frequency is changed depending on AHB data transaction (refer to
Section 11.6.5: Synchronous transactions for FSMC_CLK divider ratio formula).
The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through
dedicated registers (see Section 11.6.6: NOR/PSRAM controller registers).
The programmable memory parameters include access times (see Table 44) and support
for wait management (for PSRAM and NOR flash accessed in Burst mode).
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Table 44. Programmable NOR/PSRAM access parameters
11.6.1
Parameter
Function
Access mode
Unit
Min.
Max.
Address
setup
Duration of the address
setup phase
Asynchronous
AHB clock cycle
(HCLK)
0
15
Address hold
Duration of the address hold
phase
Asynchronous,
muxed I/Os
AHB clock cycle
(HCLK)
1
15
Data setup
Duration of the data setup
phase
Asynchronous
AHB clock cycle
(HCLK)
1
256
Bust turn
Duration of the bus
turnaround phase
Asynchronous and
AHB clock cycle
synchronous read
(HCLK)
/ write
0
15
Clock divide
ratio
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Synchronous
AHB clock cycle
(HCLK)
2
16
Data latency
Number of clock cycles to
issue to the memory before
the first data of the burst
Synchronous
Memory clock
cycle (CLK)
2
17
External memory interface signals
Table 45, Table 46 and Table 47 list the signals that are typically used to interface with NOR
flash memory, SRAM and PSRAM.
Note:
The prefix “N” identifies the signals that are active low.
NOR flash memory, non-multiplexed I/Os
Table 45. Non-multiplexed I/O NOR flash memory
FSMC signal name
I/O
Function
CLK
O
Clock (for synchronous access)
A[25:0]
O
Address bus
D[15:0]
I/O
Bidirectional data bus
NE[x]
O
Chip select, x = 1..4
NOE
O
Output enable
NWE
O
Write enable
NL(=NADV)
O
Latch enable (this signal is called address
valid, NADV, by some NOR flash devices)
NWAIT
I
NOR flash wait input signal to the FSMC
The maximum capacity is 512 Mbits (26 address lines).
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NOR flash memory, 16-bit multiplexed I/Os
Table 46. 16-bit multiplexed I/O NOR flash memory
FSMC signal name
I/O
Function
CLK
O
Clock (for synchronous access)
A[25:16]
O
Address bus
AD[15:0]
I/O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
A[15:0] and data D[15:0] are multiplexed on the databus)
NE[x]
O
Chip select, x = 1..4
NOE
O
Output enable
NWE
O
Write enable
NL(=NADV)
O
Latch enable (this signal is called address valid, NADV, by some NOR
flash devices)
NWAIT
I
NOR flash wait input signal to the FSMC
The maximum capacity is 512 Mbits.
PSRAM/SRAM, non-multiplexed I/Os
Table 47. Non-multiplexed I/Os PSRAM/SRAM
FSMC signal
name
I/O
Function
CLK
O
Clock (only for PSRAM synchronous access)
A[25:0]
O
Address bus
D[15:0]
I/O
Data bidirectional bus
NE[x]
O
Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
NOE
O
Output enable
NWE
O
Write enable
NL(= NADV)
O
Address valid only for PSRAM input (memory signal name: NADV)
NWAIT
I
PSRAM wait input signal to the FSMC
NBL[1:0]
O
Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)
The maximum capacity is 512 Mbits.
PSRAM, 16-bit multiplexed I/Os
Table 48. 16-Bit multiplexed I/O PSRAM
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FSMC signal
name
I/O
Function
CLK
O
Clock (for synchronous access)
A[25:16]
O
Address bus
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RM0430
Flexible memory controller (FMC)
Table 48. 16-Bit multiplexed I/O PSRAM (continued)
FSMC signal
name
I/O
Function
AD[15:0]
I/O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
A[15:0] and data D[15:0] are multiplexed on the databus)
NE[x]
O
Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
NOE
O
Output enable
NWE
O
Write enable
NL(= NADV)
O
Address valid PSRAM input (memory signal name: NADV)
NWAIT
I
PSRAM wait input signal to the FSMC
NBL[1:0]
O
Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)
The maximum capacity is 512 Mbits (26 address lines).
11.6.2
Supported memories and transactions
Table 49 below shows an example of the supported devices, access modes and
transactions when the memory data bus is 16-bit wide for NOR flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FSMC are shown in gray in
this example.
Table 49. NOR flash/PSRAM: example of supported memories
and transactions
Device
NOR flash
(muxed I/Os
and nonmuxed
I/Os)
Mode
R/W
AHB
data
size
Memory
data size
Allowed/
not
allowed
Comments
Asynchronous
R
8
16
Y
-
Asynchronous
W
8
16
N
-
Asynchronous
R
16
16
Y
-
Asynchronous
W
16
16
Y
-
Asynchronous
R
32
16
Y
Split into 2 FSMC accesses
Asynchronous
W
32
16
Y
Split into 2 FSMC accesses
Asynchronous
page
R
-
16
N
Mode is not supported
Synchronous
R
8
16
N
-
Synchronous
R
16
16
Y
-
Synchronous
R
32
16
Y
-
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Flexible memory controller (FMC)
RM0430
Table 49. NOR flash/PSRAM: example of supported memories
and transactions (continued)
Device
PSRAM
(multiplexed
I/Os and nonmultiplexed
I/Os)
SRAM and
ROM
11.6.3
Mode
R/W
AHB
data
size
Memory
data size
Allowed/
not
allowed
Comments
Asynchronous
R
8
16
Y
-
Asynchronous
W
8
16
Y
Use of byte lanes NBL[1:0]
Asynchronous
R
16
16
Y
-
Asynchronous
W
16
16
Y
-
Asynchronous
R
32
16
Y
Split into 2 FSMC accesses
Asynchronous
W
32
16
Y
Split into 2 FSMC accesses
Asynchronous
page
R
-
16
N
Mode is not supported
Synchronous
R
8
16
N
-
Synchronous
R
16
16
Y
-
Synchronous
R
32
16
Y
-
Synchronous
W
8
16
Y
Use of byte lanes NBL[1:0]
Synchronous
W
16/32
16
Y
-
Asynchronous
R
8 / 16
16
Y
-
Asynchronous
W
8 / 16
16
Y
Use of byte lanes NBL[1:0]
Asynchronous
R
32
16
Y
Split into 2 FSMC accesses
Asynchronous
W
32
16
Y
Split into 2 FSMC accesses
Use of byte lanes NBL[1:0]
General timing rules
Signals synchronization
11.6.4
•
All controller output signals change on the rising edge of the internal clock (HCLK)
•
In Synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
–
NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FSMC_CLK clock.
–
NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FSMC_CLK clock.
NOR flash/PSRAM controller asynchronous transactions
Asynchronous static memories (NOR flash, PSRAM, SRAM)
•
274/1321
Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
RM0430 Rev 9
RM0430
Flexible memory controller (FMC)
•
The FSMC always samples the data before de-asserting the NOE signal. This
guarantees that the memory data hold timing constraint is met (minimum Chip Enable
high to data transition is usually 0 ns)
•
If the Extended mode is enabled (EXTMOD bit is set in the FSMC_BCRx register), up
to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and
D modes for read and write operations. For example, read operation can be performed
in mode A and write in mode B.
•
If the Extended mode is disabled (EXTMOD bit is reset in the FSMC_BCRx register),
the FSMC can operate in mode 1 or mode 2 as follows:
–
Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP
= 0x0 or 0x01 in the FSMC_BCRx register)
–
Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in
the FSMC_BCRx register).
Mode 1 - SRAM/PSRAM (CRAM)
The next figures show the read and write transactions for the supported modes followed by
the required configuration of FSMC_BCRx, and FSMC_BTRx/FSMC_BWTRx registers.
Figure 33. Mode 1 read access waveforms
Memory transaction
A[25:0]
NBL[1:0]
NEx
NOE
NWE
High
data driven
by memory
D[15:0]
ADDSET
HCLK cycles
DATAST
HCLK cycles
MS34477V1
RM0430 Rev 9
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Flexible memory controller (FMC)
RM0430
Figure 34. Mode 1 write access waveforms
Memory transaction
A[25:0]
NBL[1:0]
NEx
NOE
1HCLK
NWE
D[15:0]
data driven by FSMC
ADDSET
(DATAST + 1)
HCLK cycles
HCLK cycles
MSv40113V1
The one HCLK cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the
DATAST value must be greater than zero (DATAST &gt; 0).
Table 50. FSMC_BCRx bitfields (mode 1)
276/1321
Bit number
Bit name
Value to set
31:22
Reserved
0x000
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in Asynchronous mode)
18:16
CPSIZE
0x0 (no effect in Asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x0
13
WAITEN
0x0 (no effect in Asynchronous mode)
12
WREN
As needed
11
Reserved
0x0
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
Don’t care
Set to 1 if the memory supports this feature. Otherwise keep at 0.
RM0430 Rev 9
RM0430
Flexible memory controller (FMC)
Table 50. FSMC_BCRx bitfields (mode 1) (continued)
Bit number
Bit name
Value to set
5:4
MWID
As needed
3:2
MTYP
As needed, exclude 0x2 (NOR flash memory)
1
MUXE
0x0
0
MBKEN
0x1
Table 51. FSMC_BTRx bitfields (mode 1)
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
Don’t care
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST HCLK cycles for read accesses).
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles).
Minimum value for ADDSET is 0.
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Flexible memory controller (FMC)
RM0430
Mode A - SRAM/PSRAM (CRAM) OE toggling
Figure 35. Mode A read access waveforms
Memory transaction
A[25:0]
NBL[1:0]
NEx
NOE
NWE
High
data driven
by memory
D[15:0]
ADDSET
HCLK cycles
DATAST
HCLK cycles
MS34479V1
1. NBL[1:0] are driven low during the read access
Figure 36. Mode A write access waveforms
Memory transaction
A[25:0]
NBL[1:0]
NEx
NOE
1HCLK
NWE
data driven by FSMC
D[15:0]
ADDSET
HCLK cycles
(DATAST + 1)
HCLK cycles
MS34480V1
278/1321
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Flexible memory controller (FMC)
The differences compared with Mode 1 are the toggling of NOE and the independent read
and write timings.
Table 52. FSMC_BCRx bitfields (mode A)
Bit number
Bit name
Value to set
31:22
Reserved
0x000
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in Asynchronous mode)
18:16
CPSIZE
0x0 (no effect in Asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x1
13
WAITEN
0x0 (no effect in Asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
Don’t care
5:4
MWID
As needed
3:2
MTYP
As needed, exclude 0x2 (NOR flash memory)
1
MUXEN
0x0
0
MBKEN
0x1
Set to 1 if the memory supports this feature. Otherwise keep at 0.
Table 53. FSMC_BTRx bitfields (mode A)
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x0
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for read
accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
Minimum value for ADDSET is 0.
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Flexible memory controller (FMC)
RM0430
Table 54. FSMC_BWTRx bitfields (mode A)
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x0
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for write
accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
Minimum value for ADDSET is 0.
Mode 2/B - NOR flash
Figure 37. Mode 2 and mode B read access waveforms
Memory transaction
A[25:0]
NADV
NEx
NOE
NWE
High
data driven
by memory
D[15:0]
ADDSET
HCLK cycles
DATAST
HCLK cycles
MS34481V2
280/1321
RM0430 Rev 9
RM0430
Flexible memory controller (FMC)
Figure 38. Mode 2 write access waveforms
Memory transaction
A[25:0]
NADV
NEx
NOE
1HCLK
NWE
D[15:0]
data driven by FMC
ADDSET
HCLK cycles
(DATAST + 1)
HCLK cycles
MS34482V2
Figure 39. Mode B write access waveforms
Memory transaction
A[25:0]
NADV
NEx
NOE
1HCLK
NWE
D[15:0]
data driven by FSMC
ADDSET
HCLK cycles
(DATAST + 1)
HCLK cycles
MSv40114V1
The differences with mode 1 are the toggling of NWE and the independent read and write
timings when extended mode is set (mode B).
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Flexible memory controller (FMC)
RM0430
Table 55. FSMC_BCRx bitfields (mode 2/B)
Bit number
Bit name
Value to set
31:22
Reserved
0x000
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in Asynchronous mode)
18:16
CPSIZE
0x0 (no effect in Asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x1 for mode B, 0x0 for mode 2
13
WAITEN
0x0 (no effect in Asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
0x1
5:4
MWID
As needed
3:2
MTYP
0x2 (NOR flash memory)
1
MUXEN
0x0
0
MBKEN
0x1
Set to 1 if the memory supports this feature. Otherwise keep at 0.
Table 56. FSMC_BTRx bitfields (mode 2/B)
282/1321
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x1 if Extended mode is set
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the access second phase (DATAST HCLK cycles) for
read accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 0.
RM0430 Rev 9
RM0430
Flexible memory controller (FMC)
Table 57. FSMC_BWTRx bitfields (mode 2/B)
Note:
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x1 if Extended mode is set
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the access second phase (DATAST HCLK cycles) for
write accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
The FSMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its
content is don’t care.
Mode C - NOR flash - OE toggling
Figure 40. Mode C read access waveforms
Memory transaction
A[25:0]
NADV
NEx
NOE
NWE
High
data driven
by memory
D[15:0]
ADDSET
HCLK cycles
DATAST
HCLK cycles
MS34484V1
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Flexible memory controller (FMC)
RM0430
Figure 41. Mode C write access waveforms
Memory transaction
A[25:0]
NADV
NEx
NOE
1HCLK
NWE
D[15:0]
data driven by FSMC
ADDSET
HCLK cycles
(DATAST + 1)
HCLK cycles
MS34485V1
The differences compared with mode 1 are the toggling of NOE and the independent read
and write timings.
Table 58. FSMC_BCRx bitfields (mode C)
284/1321
Bit number
Bit name
Value to set
31:22
Reserved
0x000
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in Asynchronous mode)
18:16
CPSIZE
0x0 (no effect in Asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x1
13
WAITEN
0x0 (no effect in Asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
0x1
5:4
MWID
As needed
Set to 1 if the memory supports this feature. Otherwise keep at 0.
RM0430 Rev 9
RM0430
Flexible memory controller (FMC)
Table 58. FSMC_BCRx bitfields (mode C) (continued)
Bit number
Bit name
Value to set
3:2
MTYP
0x02 (NOR flash memory)
1
MUXEN
0x0
0
MBKEN
0x1
Table 59. FSMC_BTRx bitfields (mode C)
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x2
27:24
DATLAT
0x0
23:20
CLKDIV
0x0
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for
read accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 0.
Table 60. FSMC_BWTRx bitfields (mode C)
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x2
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for
write accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
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Flexible memory controller (FMC)
RM0430
Mode D - asynchronous access with extended address
Figure 42. Mode D read access waveforms
Memory transaction
A[25:0]
NADV
NEx
NOE
NWE
High
data driven
by memory
D[15:0]
ADDSET
HCLK cycles
ADDHLD
HCLK cycles
DATAST
HCLK cycles
Figure 43. Mode D write access waveforms
286/1321
RM0430 Rev 9
MS34486V1
RM0430
Flexible memory controller (FMC)
The differences with mode 1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Table 61. FSMC_BCRx bitfields (mode D)
Bit number
Bit name
Value to set
31:22
Reserved
0x000
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in Asynchronous mode)
18:16
CPSIZE
0x0 (no effect in Asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x1
13
WAITEN
0x0 (no effect in Asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
Set according to memory support
5:4
MWID
As needed
3:2
MTYP
As needed
1
MUXEN
0x0
0
MBKEN
0x1
Set to 1 if the memory supports this feature. Otherwise keep at 0.
Table 62. FSMC_BTRx bitfields (mode D)
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x3
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for read
accesses.
7:4
ADDHLD
Duration of the middle phase of the read access (ADDHLD HCLK
cycles)
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 1.
RM0430 Rev 9
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Flexible memory controller (FMC)
RM0430
Table 63. FSMC_BWTRx bitfields (mode D)
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x3
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the second access phase (DATAST + 1 HCLK cycles) for
write accesses.
7:4
ADDHLD
Duration of the middle phase of the write access (ADDHLD HCLK
cycles)
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 1.
Muxed mode - multiplexed asynchronous access to NOR flash memory
Figure 44. Muxed read access waveforms
288/1321
RM0430 Rev 9
RM0430
Flexible memory controller (FMC)
Figure 45. Muxed write access waveforms
Memory transaction
A[25:16]
NADV
NEx
NOE
1HCLK
NWE
AD[15:0]
data driven by FSMC
Lower address
ADDSET
ADDHLD
(DATAST + 1)
HCLK cycles
HCLK cycles
HCLK cycles
MSv40112V2
The difference with mode D is the drive of the lower address byte(s) on the data bus.
Table 64. FSMC_BCRx bitfields (Muxed mode)
Bit number
Bit name
Value to set
31:22
Reserved
0x000
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in Asynchronous mode)
18:16
CPSIZE
0x0 (no effect in Asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x0
13
WAITEN
0x0 (no effect in Asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
0x1
5:4
MWID
As needed
Set to 1 if the memory supports this feature. Otherwise keep at 0.
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Flexible memory controller (FMC)
RM0430
Table 64. FSMC_BCRx bitfields (Muxed mode) (continued)
Bit number
Bit name
Value to set
3:2
MTYP
0x2 (NOR flash memory) or 0x1(PSRAM)
1
MUXEN
0x1
0
MBKEN
0x1
Table 65. FSMC_BTRx bitfields (Muxed mode)
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x0
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles for read
accesses and DATAST+1 HCLK cycles for write accesses).
7:4
ADDHLD
Duration of the middle phase of the access (ADDHLD HCLK cycles).
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles). Minimum
value for ADDSET is 1.
WAIT management in asynchronous accesses
If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
290/1321
RM0430 Rev 9
RM0430
Flexible memory controller (FMC)
The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles
before the end of the memory transaction. The following cases must be considered:
1.
The memory asserts the WAIT signal aligned to NOE/NWE which toggles:
DATAST ≥ ( 4 &times; HCLK ) + max_wait_assertion_time
2.
The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
max_wait_assertion_time &gt; address_phase + hold_phase
then:
DATAST ≥ ( 4 &times; HCLK ) + ( max_wait_assertion_time – address_phase – hold_phase )
otherwise
DATAST ≥ 4 &times; HCLK
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 46 and Figure 47 show the number of HCLK clock cycles that are added to the
memory access phase after WAIT is released by the asynchronous memory (independently
of the above cases).
Figure 46. Asynchronous wait during a read access waveforms
Memory transaction
A[25:0]
address phase
data setup phase
NEx
NWAIT
don’t care
don’t care
NOE
data driven by memory
D[15:0]
4HCLK
MS30463V2
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
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Flexible memory controller (FMC)
RM0430
Figure 47. Asynchronous wait during a write access waveforms
Memory transaction
A[25:0]
address phase
data setup phase
NEx
NWAIT
don’t care
don’t care
1HCLK
NWE
D[15:0]
data driven by FSMC
3HCLK
MS30464V2
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
11.6.5
Synchronous transactions
The memory clock, FSMC_CLK, is a submultiple of HCLK. It depends on the value of
CLKDIV and the MWID/ AHB data size, following the formula given below:
FSMC_CLK divider ratio = max (CLKDIV + 1,MWID ( AHB data size ))
Whatever MWID size: 16 or 8-bit, the FSMC_CLK divider ratio is always defined by the
programmed CLKDIV value.
Example:
•
If CLKDIV=1, MWID = 16 bits, AHB data size=8 bits, FSMC_CLK=HCLK/2.
NOR flash memories specify a minimum time from NADV assertion to CLK high. To meet
this constraint, the FSMC does not issue the clock to the memory during the first internal
clock cycle of the synchronous access (before NADV assertion). This guarantees that the
rising edge of the memory clock occurs in the middle of the NADV low pulse.
Data latency versus NOR memory latency
The data latency is the number of cycles to wait before sampling the data. The DATLAT
value must be consistent with the latency value specified in the NOR flash configuration
register. The FSMC does not include the clock cycle when NADV is low in the data latency
count.
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Flexible memory controller (FMC)
Caution:
Some NOR flash memories include the NADV Low cycle in the data latency count, so that
the exact relation between the NOR flash latency and the FSMC DATLAT parameter can be
either:
•
NOR flash latency = (DATLAT + 2) CLK clock cycles
•
or NOR flash latency = (DATLAT + 3) CLK clock cycles
Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can
be set to its minimum value. As a result, the FSMC samples the data and waits long enough
to evaluate if the data are valid. Thus the FSMC detects when the memory exits latency and
real data are processed.
Other memories do not assert NWAIT during latency. In this case the latency must be set
correctly for both the FSMC and the memory, otherwise invalid data are mistaken for good
data, or valid data are lost in the initial phase of the memory access.
Single-burst transfer
When the selected bank is configured in Burst mode for synchronous accesses, if for
example an AHB single-burst transaction is requested on 16-bit memories, the FSMC
performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the
AHB transfer is 32 bits) and de-assert the chip select signal when the last data is strobed.
Such transfers are not the most efficient in terms of cycles compared to asynchronous read
operations. Nevertheless, a random asynchronous access would first require to re-program
the memory access mode, which would altogether last longer.
Cross boundary page for CellularRAM™ 1.5
CellularRAM™ 1.5 does not allow burst access to cross the page boundary. The FSMC
controller is used to split automatically the burst access when the memory page size is
reached by configuring the CPSIZE bits in the FSMC_BCR1 register following the memory
page size.
Wait management
For synchronous NOR flash memories, NWAIT is evaluated after the programmed latency
period, which corresponds to (DATLAT+2) CLK clock cycles.
If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait
states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when
WAITPOL = 1).
When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1)
or on the next clock edge (bit WAITCFG = 0).
During wait-state insertion via the NWAIT signal, the controller continues to send clock
pulses to the memory, keeping the chip select and output enable signals valid. It does not
consider the data as valid.
In Burst mode, there are two timing configurations for the NOR flash NWAIT signal:
•
The flash memory asserts the NWAIT signal one data cycle before the wait state
(default after reset).
•
The flash memory asserts the NWAIT signal during the wait state
The FSMC supports both NOR flash wait state configurations, for each chip select, thanks
to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3).
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Figure 48. Wait configuration waveforms
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
addr[25:16]
NADV
NWAIT
(WAITCFG = 0)
NWAIT
(WAITCFG = 1)
inserted wait state
A/D[15:0]
addr[15:0]
data
data
data
ai15798c
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Flexible memory controller (FMC)
Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
addr[25:16]
NEx
NOE
NWE
High
NADV
NWAIT
(WAITCFG=0)
inserted wait state
(DATLAT + 2)
CLK cycles
A/D[15:0]
Addr[15:0]
data1
1 clock 1 clock
cycle cycle
data1
data2
Data strobes
data3
data4
Data strobes
ai17723g
1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM)
access, they are held low.
Table 66. FSMC_BCRx bitfields (Synchronous multiplexed read mode)
Bit number
Bit name
Value to set
31:22
Reserved
0x000
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
18:16
CPSIZE
15
ASYNCWAIT
0x0
14
EXTMOD
0x0
13
WAITEN
To be set to 1 if the memory supports this feature, to be kept at 0
otherwise
12
WREN
No effect on synchronous read
No effect on synchronous read
0x0 (no effect in Asynchronous mode)
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Table 66. FSMC_BCRx bitfields (Synchronous multiplexed read mode) (continued)
Bit number
Bit name
Value to set
11
WAITCFG
To be set according to memory
10
Reserved
0x0
9
WAITPOL
To be set according to memory
8
BURSTEN
0x1
7
Reserved
0x1
6
FACCEN
Set according to memory support (NOR flash memory)
5-4
MWID
As needed
3-2
MTYP
0x1 or 0x2
1
MUXEN
As needed
0
MBKEN
0x1
Table 67. FSMC_BTRx bitfields (Synchronous multiplexed read mode)
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Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x0
27-24
DATLAT
Data latency
27-24
DATLAT
Data latency
23-20
CLKDIV
0x0 to get CLK = HCLK
0x1 to get CLK = 2 &times; HCLK
..
19-16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15-8
DATAST
Don’t care
7-4
ADDHLD
Don’t care
3-0
ADDSET
Don’t care
RM0430 Rev 9
RM0430
Flexible memory controller (FMC)
Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)
Memory transaction = burst of 2 half words
HCLK
CLK
A[25:16]
addr[25:16]
NEx
Hi-Z
NOE
NWE
NADV
NWAIT
(WAITCFG = 0)
inserted wait state
(DATLAT + 2)
CLK cycles
A/D[15:0]
Addr[15:0]
data1
data1
data2
1 clock 1 clock
cycle cycle
ai14731g
1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Table 68. FSMC_BCRx bitfields (Synchronous multiplexed write mode)
Bit number
Bit name
31:22
Reserved
0x000
21
WFDIS
As needed
20
CCLKEN
As needed
19
18:16
15
Value to set
CBURSTRW 0x1
CPSIZE
As needed (0x1 for CRAM 1.5)
ASYNCWAIT 0x0
14
EXTMOD
0x0
13
WAITEN
To be set to 1 if the memory supports this feature, to be kept at 0
otherwise.
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Table 68. FSMC_BCRx bitfields (Synchronous multiplexed write mode) (continued)
Bit number
Bit name
Value to set
12
WREN
0x1
11
WAITCFG
0x0
10
Reserved
0x0
9
WAITPOL
to be set according to memory
8
BURSTEN
no effect on synchronous write
7
Reserved
0x1
6
FACCEN
Set according to memory support
5-4
MWID
As needed
3-2
MTYP
0x1
1
MUXEN
As needed
0
MBKEN
0x1
Table 69. FSMC_BTRx bitfields (Synchronous multiplexed write mode)
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Bit number
Bit name
Value to set
31-30
Reserved
0x0
29:28
ACCMOD
0x0
27-24
DATLAT
Data latency
23-20
CLKDIV
0x0 to get CLK = HCLK
0x1 to get CLK = 2 &times; HCLK
19-16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK).
15-8
DATAST
Don’t care
7-4
ADDHLD
Don’t care
3-0
ADDSET
Don’t care
RM0430 Rev 9
RM0430
Flexible memory controller (FMC)
11.6.6
NOR/PSRAM controller registers
SRAM/NOR-flash chip-select control register for bank x
(FSMC_BCRx)
Address offset: 0x00 + 0x8 * (x - 1), (x = 1 to 4)
Reset value: 0x0000 30DB, 0x0000 30D2, 0x0000 30D2, 0x0000 30D2
This register contains the control information of each memory bank, used for SRAMs,
PSRAM and NOR flash memories.
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
ASYNC
WAIT
EXT
MOD
WAIT
EN
WREN
WAIT
CFG
Res.
WAIT
POL
BURST
EN
Res.
FACC
EN
rw
rw
rw
rw
rw
rw
rw
rw
21
20
19
WFDIS
CCLK
EN
CBURST
RW
18
17
16
rw
rw
rw
rw
rw
rw
5
4
3
2
1
0
CPSIZE[2:0]
MWID[1:0]
MTYP[1:0]
MUX
EN
MBK
EN
rw
rw
rw
rw
rw
rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 WFDIS: Write FIFO disable
This bit disables the Write FIFO used by the FSMC controller.
0: Write FIFO enabled (Default after reset)
1: Write FIFO disabled
Note: The WFDIS bit of the FSMC_BCR2..4 registers is don’t care. It is only enabled through the
FSMC_BCR1 register.
Bit 20 CCLKEN: Continuous clock enable
This bit enables the FSMC_CLK clock output to external memory devices.
0: The FSMC_CLK is only generated during the synchronous memory access (read/write
transaction). The FSMC_CLK clock ratio is specified by the programmed CLKDIV value in the
FSMC_BCRx register (default after reset).
1: The FSMC_CLK is generated continuously during asynchronous and synchronous access. The
FSMC_CLK clock is activated when the CCLKEN is set.
Note: The CCLKEN bit of the FSMC_BCR2..4 registers is don’t care. It is only enabled through the
FSMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the
FSMC_CLK continuous clock.
Note: If CCLKEN bit is set, the FSMC_CLK clock ratio is specified by CLKDIV value in the
FSMC_BTR1 register. CLKDIV in FSMC_BWTR1 is don’t care.
Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories
connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the
FSMC_BTR2..4 and FSMC_BWTR2..4 registers for other banks has no effect.)
Bit 19 CBURSTRW: Write burst enable
For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write
operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FSMC_BCRx
register.
0: Write operations are always performed in Asynchronous mode.
1: Write operations are performed in Synchronous mode.
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Bits 18:16 CPSIZE[2:0]: CRAM page size
These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address
boundaries between pages. When these bits are configured, the FSMC controller splits
automatically the burst access when the memory page size is reached (refer to memory datasheet
for page size).
000: No burst split when crossing page boundary (default after reset)
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
Others: Reserved, must not be used
Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers
This bit enables/disables the FSMC to use the wait signal even during an asynchronous protocol.
0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after
reset).
1: NWAIT signal is taken in to account when running an asynchronous protocol.
Bit 14 EXTMOD: Extended mode enable
This bit enables the FSMC to program the write timings for non multiplexed asynchronous accesses
inside the FSMC_BWTR register, thus resulting in different timings for read and write operations.
0: values inside FSMC_BWTR register are not taken into account (default after reset)
1: values inside FSMC_BWTR register are taken into account
Note: When the Extended mode is disabled, the FSMC can operate in mode 1 or mode 2 as follows:
–
Mode 1 is the default mode when the SRAM/PSRAM memory type is selected
(MTYP = 0x0 or 0x01)
–
Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).
Bit 13 WAITEN: Wait enable bit
This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in
Synchronous mode.
0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the
programmed flash latency period).
1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to
insert wait states if asserted) (default after reset).
Bit 12 WREN: Write enable bit
This bit indicates whether write operations are enabled/disabled in the bank by the FSMC.
0: Write operations are disabled in the bank by the FSMC, an AHB error is reported.
1: Write operations are enabled for the bank by the FSMC (default after reset).
Bit 11 WAITCFG: Wait timing configuration
The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be
inserted when accessing the memory in Synchronous mode. This configuration bit determines if
NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:
0: NWAIT signal is active one data cycle before wait state (default after reset).
1: NWAIT signal is active during wait state (not used for PSRAM).
Bit 10 Reserved, must be kept at reset value.
Bit 9 WAITPOL: Wait signal polarity bit
Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous
mode.
0: NWAIT active low (default after reset)
1: NWAIT active high
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Flexible memory controller (FMC)
Bit 8 BURSTEN: Burst enable bit
This bit enables/disables synchronous accesses during read operations. It is valid only for
synchronous memories operating in Burst mode.
0: Burst mode disabled (default after reset). Read accesses are performed in Asynchronous mode.
1: Burst mode enable. Read accesses are performed in Synchronous mode.
Bit 7 Reserved, must be kept at reset value.
Bit 6 FACCEN: Flash access enable
Enables NOR flash memory access operations.
0: Corresponding NOR flash memory access is disabled.
1: Corresponding NOR flash memory access is enabled (default after reset).
Bits 5:4 MWID[1:0]: Memory data bus width
Defines the external memory device width, valid for all type of memories.
00: 8 bits
01: 16 bits (default after reset)
10: reserved
11: reserved
Bits 3:2 MTYP[1:0]: Memory type
Defines the type of external memory attached to the corresponding memory bank.
00: SRAM (default after reset for Bank 2...4)
01: PSRAM (CRAM)
10: NOR flash (default after reset for Bank 1)
11: reserved
Bit 1 MUXEN: Address/data multiplexing enable bit
When this bit is set, the address and data values are multiplexed on the data bus, valid only with
NOR and PSRAM memories:
0: Address/data non multiplexed
1: Address/data multiplexed on databus (default after reset)
Bit 0 MBKEN: Memory bank enable bit
Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
disabled bank causes an ERROR on AHB bus.
0: Corresponding memory bank is disabled.
1: Corresponding memory bank is enabled.
SRAM/NOR-flash chip-select timing register for bank x (FSMC_BTRx)
Address offset: 0x04 + 0x8 * (x - 1), (x = 1 to 4)
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank, used for SRAMs,
PSRAM and NOR flash memories.If the EXTMOD bit is set in the FSMC_BCRx register,
then this register is partitioned for write and read access, that is, 2 registers are available:
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RM0430
one to configure read accesses (this register) and one to configure write accesses
(FSMC_BWTRx registers).
31
30
29
Res.
Res.
ACCMOD[1:0]
28
27
26
25
24
23
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATLAT[3:0]
DATAST[7:0]
rw
rw
rw
rw
rw
22
21
20
19
CLKDIV[3:0]
ADDHLD[3:0]
rw
rw
rw
rw
rw
rw
18
17
16
BUSTURN[3:0]
ADDSET[3:0]
rw
rw
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:28 ACCMOD[1:0]: Access mode
Specifies the asynchronous access modes as shown in the timing diagrams. These bits are
taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
Bits 27:24 DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory
For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits
set), defines the number of memory clock cycles (+2) to issue to the memory before
reading/writing the first data:
This timing parameter is not expressed in HCLK periods, but in FSMC_CLK periods.
For asynchronous access, this value is don't care.
0000: Data latency of 2 CLK clock cycles for first burst access
1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FSMC_CLK signal)
Defines the period of FSMC_CLK clock output signal, expressed in number of HCLK cycles:
0000: FSMC_CLK period= 1x HCLK period
0001: FSMC_CLK period = 2 &times; HCLK periods
0010: FSMC_CLK period = 3 &times; HCLK periods
1111: FSMC_CLK period = 16 &times; HCLK periods (default value after reset)
In asynchronous NOR flash, SRAM or PSRAM accesses, this value is don’t care.
Note: Refer to Section 11.6.5: Synchronous transactions for FSMC_CLK divider ratio formula)
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Flexible memory controller (FMC)
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
These bits are written by software to add a delay at the end of a write-to-read (and read-towrite) transaction. This delay enables to match the minimum time between consecutive
transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the
memory to free the data bus after a read access (tEHQZ). The programmed bus turnaround
delay is inserted between an asynchronous read (muxed or mode D) or write transaction and
any other asynchronous /synchronous read or write to or from a static bank. The bank can be
the same or different in case of read, in case of write the bank can be different except for
muxed or mode D.
In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is
fixed
as follows:
• The bus turnaround delay is not inserted between two consecutive asynchronous write
transfers to the same static memory bank except for muxed mode and mode D.
• There is a bus turnaround delay of 1 HCLK clock cycle between:
–Two consecutive asynchronous read transfers to the same static memory bank except for
muxed mode and mode D.
–An asynchronous read to an asynchronous or synchronous write to any static bank or
dynamic bank except for muxed mode and mode D.
–An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank.
• There is a bus turnaround delay of 2 HCLK clock cycle between:
–Two consecutive synchronous writes (burst or single) to the same bank.
–A synchronous write (burst or single) access and an asynchronous write or read transfer
to or from static memory bank (the bank can be the same or different for the case of
read.
–Two consecutive synchronous reads (burst or single) followed by any
synchronous/asynchronous read or write from/to another static memory bank.
• There is a bus turnaround delay of 3 HCLK clock cycle between:
–Two consecutive synchronous writes (burst or single) to different static bank.
–A synchronous write (burst or single) access and a synchronous read from the same or a
different bank.
0000: BUSTURN phase duration = 0 HCLK clock cycle added
...
1111: BUSTURN phase duration = 15 x HCLK clock cycles added (default value after reset)
Bits 15:8 DATAST[7:0]: Data-phase duration
These bits are written by software to define the duration of the data phase (refer to Figure 33
to Figure 45), used in asynchronous accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 &times; HCLK clock cycles
0000 0010: DATAST phase duration = 2 &times; HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 &times; HCLK clock cycles (default value after reset)
For each memory type and access mode data-phase duration, refer to the respective figure
(Figure 33 to Figure 45).
Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK
clock cycles.
Note: In synchronous accesses, this value is don’t care.
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Bits 7:4 ADDHLD[3:0]: Address-hold phase duration
These bits are written by software to define the duration of the address hold phase (refer to
Figure 33 to Figure 45), used in mode D or multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration =1 &times; HCLK clock cycle
0010: ADDHLD phase duration = 2 &times; HCLK clock cycle
...
1111: ADDHLD phase duration = 15 &times; HCLK clock cycles (default value after reset)
For each access mode address-hold phase duration, refer to the respective figure (Figure 33
to Figure 45).
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
memory clock period duration.
Bits 3:0 ADDSET[3:0]: Address setup phase duration
These bits are written by software to define the duration of the address setup phase (refer to
Figure 33 to Figure 45), used in SRAMs, ROMs, asynchronous NOR flash and PSRAM:
0000: ADDSET phase duration = 0 &times; HCLK clock cycle
...
1111: ADDSET phase duration = 15 &times; HCLK clock cycles (default value after reset)
For each access mode address setup phase duration, refer to the respective figure
(Figure 33 to Figure 45).
Note: In synchronous accesses, this value is don’t care.
In Muxed mode or mode D, the minimum value for ADDSET is 1.
In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.
Note:
PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FSMC exits its
latency phase soon and starts sampling NWAIT from memory, then starts to read or write
when the memory is ready.
This method can be used also with the latest generation of synchronous flash memories that
issue the NWAIT signal, unlike older flash memories (check the datasheet of the specific
flash memory being used).
SRAM/NOR-flash write timing registers x (FSMC_BWTRx)
Address offset: 0x104 + 0x8 * (x - 1), (x = 1 to 4)
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank. It is used for SRAMs,
PSRAMs and NOR flash memories. When the EXTMOD bit is set in the FSMC_BCRx
register, then this register is active for write access.
31
30
29
28
27
26
25
24
23
22
21
20
Res.
Res.
ACCMOD[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
DATAST[7:0]
rw
rw
RM0430 Rev 9
rw
rw
18
17
16
BUSTURN[3:0]
ADDHLD[3:0]
Bits 31:30 Reserved, must be kept at reset value.
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ADDSET[3:0]
rw
rw
rw
RM0430
Flexible memory controller (FMC)
Bits 29:28 ACCMOD[1:0]: Access mode.
Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are
taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
Bits 27:20 Reserved, must be kept at reset value.
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
The programmed bus turnaround delay is inserted between an asynchronous write transfer and
any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can
be the same or different in case of read, in case of write the bank can be different expect for muxed
or mode D.
In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as
follows:
• The bus turnaround delay is not inserted between two consecutive asynchronous write transfers
to the same static memory bank except for muxed and D modes.
• There is a bus turnaround delay of 2 HCLK clock cycle between:
–Two consecutive synchronous writes (burst or single) to the same bank.
–A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or
from static memory bank.
• There is a bus turnaround delay of 3 HCLK clock cycle between:
–Two consecutive synchronous writes (burst or single) to different static bank.
–A synchronous write (burst or single) transfer and a synchronous read from the same or a
different bank.
0000: BUSTURN phase duration = 0 HCLK clock cycle added
...
1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
Bits 15:8 DATAST[7:0]: Data-phase duration.
These bits are written by software to define the duration of the data phase (refer to Figure 33 to
Figure 45), used in asynchronous SRAM, PSRAM and NOR flash memory accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 &times; HCLK clock cycles
0000 0010: DATAST phase duration = 2 &times; HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 &times; HCLK clock cycles (default value after reset)
Bits 7:4 ADDHLD[3:0]: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 42 to Figure 45), used in asynchronous multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration = 1 &times; HCLK clock cycle
0010: ADDHLD phase duration = 2 &times; HCLK clock cycle
...
1111: ADDHLD phase duration = 15 &times; HCLK clock cycles (default value after reset)
Note: In synchronous NOR flash accesses, this value is not used, the address hold phase is always
1 flash clock period duration.
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Flexible memory controller (FMC)
RM0430
Bits 3:0 ADDSET[3:0]: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK cycles
(refer to Figure 33 to Figure 45), used in asynchronous accesses:
0000: ADDSET phase duration = 0 &times; HCLK clock cycle
...
1111: ADDSET phase duration = 15 &times; HCLK clock cycles (default value after reset)
Note: In synchronous accesses, this value is not used, the address setup phase is always 1 flash
clock period duration. In muxed mode, the minimum ADDSET value is 1.
11.6.7
FSMC register map
FSMC_BTR3
Reset value
306/1321
Res.
0x14
0
0
0
DATLAT[3:0]
CLKDIV[3:0]
BUSTURN[3:0
]
1
1
1
1
1
1
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0]
BUSTURN[3:0
]
1
1
1
1
1
1
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0]
BUSTURN[3:0
]
1
1
1
1
1
1
1
1
1
1
1
RM0430 Rev 9
1
1
1
1
1
1
7
6
5
2
1
0
FACCEN
MUXEN
MBKEN
MUXEN
MBKEN
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
MBKEN
0
1
0
0
1
0
MWID MTYP
[1:0] [1:0]
MBKEN
0
0
0
0
1
0
1
0
1
1
0
0
0
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
DATAST[7:0]
1
1
MWID MTYP
[1:0] [1:0]
DATAST[7:0]
1
3
8
Res.
0
DATAST[7:0]
1
4
9
WAITPOL
0
MUXEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ACCMOD[1:0]
0
Res.
Reset value
0
ACCMOD[1:0]
FSMC_BTR2
Res.
0x0C
0
Res.
Reset value
ACCMOD[1:0]
Res.
Res.
FSMC_BTR1
MWID MTYP
[1:0] [1:0]
MUXEN
0
1
FACCEN
WAITCFG
WAITCFG
WAITCFG
1
1
1
FACCEN
WREN
WREN
WREN
1
0
1
FACCEN
WAITEN
WAITEN
WAITEN
0
0
0
Res.
EXTMOD
EXTMOD
EXTMOD
0
0
1
Res.
ASYNCWAIT
ASYNCWAIT
ASYNCWAIT
0
0
0
Res.
CBURSTRW
CBURSTRW
CBURSTRW
0
Res.
CPSIZE
[2:0]
Res.
FSMC_BCR4
Res.
0
Res.
1
Res.
1
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Reset value
Res.
CPSIZE
[2:0]
Reset value
0x04
0
BURSTEN
Res.
Res.
Res.
Res.
FSMC_BCR3
Res.
0
Res.
1
Res.
1
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0x18
Reset value
Res.
0x10
CPSIZE
[2:0]
FSMC_BCR2
Res.
0x08
0
WAITPOL
0
BURSTEN
11
1
WAITPOL
12
WAITCFG
1
BURSTEN
13
WREN
0
WAITPOL
14
WAITEN
0
MWID MTYP
[1:0] [1:0]
BURSTEN
15
EXTMOD
0
0
10
16
ASYNCWAIT
0
Res.
18
0
Res.
19
0
Res.
20
CBURSTRW
0
Res.
21
CCLKEN
CPSIZE
[2:0]
Reset value
17
22
WFDIS
23
24
25
26
27
28
Res.
Res.
Res.
Res.
Res.
Res.
Res.
30
29
Res.
FSMC_BCR1
Res.
0x00
Res.
Offset
31
Table 70. FSMC register map and reset values
Register name
reset value
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
1
1
RM0430
Flexible memory controller (FMC)
Reset value
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
6
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
DATAST[7:0]
1
1
ADDHLD[3:0] ADDSET[3:0]
DATAST[7:0]
1
1
ADDHLD[3:0] ADDSET[3:0]
DATAST[7:0]
1
7
8
9
11
10
12
1
ADDHLD[3:0] ADDSET[3:0]
DATAST[7:0]
BUSTURN
[3:0]
1
13
14
15
16
17
18
1
1
BUSTURN
[3:0]
1
Res.
0
1
DATAST[7:0]
BUSTURN[3:0
]
1
Res.
0
0
19
20
21
1
Res.
1
Res.
Res.
Res.
Res.
Res.
22
23
24
25
26
27
Res.
BUSTURN[3:0
]
Res.
FSMC_BWTR4
1
1
Res.
0
1
1
Res.
ACCMOD[1:0]
Reset value
1
1
Res.
FSMC_BWTR3
1
Res.
0
BUSTURN[3:0
]
Res.
ACCMOD[1:0]
Reset value
CLKDIV[3:0]
Res.
28
29
ACCMOD[1:0]
30
ACCMOD[1:0]
31
Res.
Res.
Res.
FSMC_BWTR2
Res.
0
Res.
Reset value
0
DATLAT[3:0]
Res.
0x11C
FSMC_BWTR1
ACCMOD[1:0]
0x114
0
Res.
0x10C
Reset value
Res.
0x104
FSMC_BTR4
Res.
0x1C
Register name
reset value
Res.
Offset
Res.
Table 70. FSMC register map and reset values (continued)
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
1
1
Refer to Section 2.2 on page 57 for the register boundary addresses.
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Quad-SPI interface (QUADSPI)
RM0430
12
Quad-SPI interface (QUADSPI)
12.1
Introduction
The QUADSPI is a specialized communication interface targeting single, dual- or quad-SPI
flash memories. It can operate in any of the three following modes:
•
indirect mode: all the operations are performed using the QUADSPI registers.
•
automatic status-polling mode: the external flash memory status register is periodically
read and an interrupt can be generated in case of flag setting.
•
memory-mapped mode: the external flash memory is mapped to the device address
space and is seen by the system as if it was an internal memory.
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
Quad-SPI flash memories are accessed simultaneously.
12.2
QUADSPI main features
•
Three functional modes: indirect, automatic status-polling, and memory-mapped
•
Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two
flash memories in parallel
•
SDR and DDR support
•
Fully programmable opcode for both indirect and memory-mapped modes
•
Fully programmable frame format for both indirect and memory-mapped modes
•
Integrated FIFO for reception and transmission
•
8-, 16-, and 32-bit data accesses allowed
•
DMA channel for indirect mode operations
•
Interrupt generation on FIFO threshold, timeout, operation complete, and access error
12.3
QUADSPI functional description
12.3.1
QUADSPI block diagram
Figure 51. QUADSPI block diagram when dual-flash mode is disabled
QUADSPI
Registers /
control
Clock
management
AHB
FIFO
Shift register
SPI FLASH
CLK
BK1_IO0/SO
BK1_IO1/SI
BK1_IO2
BK1_IO3
BK1_NCS
CLK
Q0/SI
Q1/SO
Q2/WP
Q3/HOLD
CS
MS35315V2
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Quad-SPI interface (QUADSPI)
Figure 52. QUADSPI block diagram when dual-flash mode is enabled
QUADSPI
Registers /
control
Clock
management
SPI FLASH 1
CLK
BK1_IO0/SO
BK1_IO1/SI
BK1_IO2
BK1_IO3
BK1_NCS
AHB
FIFO
CLK
Q0/SI
Q1/SO
Q2/WP
Q3/HOLD
CS
SPI FLASH 2
Shift register
BK2_IO0/SO
BK2_IO1/SI
BK2_IO2
BK2_IO3
BK2_NCS
CLK
Q0/SI
Q1/SO
Q2/WP
Q3/HOLD
CS
MS35316V2
12.3.2
QUADSPI pins
The table below lists the QUADSPI pins, six for interfacing with a single flash memory, or 10
to 11 for interfacing with two flash memories (FLASH 1 and FLASH 2) in dual-flash mode.
Table 71. QUADSPI pins
Signal name
Signal type
CLK
Digital output
Description
Clock to FLASH 1 and FLASH 2
BK1_IO0/SO Digital input/output Bidirectional I/O in dual/quad modes or serial output in single mode, for FLASH 1
BK1_IO1/SI
Digital input/output Bidirectional I/O in dual/quad modes or serial input in single mode, for FLASH 1
BK1_IO2
Digital input/output Bidirectional I/O in quad mode, for FLASH 1
BK1_IO3
Digital input/output Bidirectional I/O in quad mode, for FLASH 1
BK2_IO0/SO Digital input/output Bidirectional I/O in dual/quad modes or serial output in single mode, for FLASH 2
BK2_IO1/SI
Digital input/output Bidirectional I/O in dual/quad modes or serial input in single mode, for FLASH 2
BK2_IO2
Digital input/output Bidirectional I/O in quad mode, for FLASH 2
BK2_IO3
Digital input/output Bidirectional I/O in quad mode, for FLASH 2
BK1_NCS
Digital output
Chip select (active low) for FLASH 1. Can also be used for FLASH 2 if QUADSPI
is always used in dual-flash mode.
BK2_NCS
Digital output
Chip select (active low) for FLASH 2. Can also be used for FLASH 1 if QUADSPI
is always used in dual-flash mode.
12.3.3
QUADSPI command sequence
The QUADSPI communicates with the flash memory using commands. Each command can
include five phases: instruction, address, alternate byte, dummy, data. Any of these phases
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can be configured to be skipped, but at least one of the instruction, address, alternate byte,
or data phase must be present.
NCS falls before the start of each command and rises again after each command finishes.
Figure 53. Example of read command in quad-SPI mode
Instruction
Address
Alt.
Dummy
Data
NCS
SCLK
IO0
7
6
5
4
3
2
1
0
4
0
4
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
6
2
6
2
IO3
7
3
7
3
7
3
7
3
7
3
7
3
A23-16
A15-8
A7-0
M7-0
Byte 1
I/O switch from output to input
Byte 2
MS35317V2
Instruction phase
During this phase, an 8-bit instruction, configured in INSTRUCTION bitfield of
QUADSPI_CCR[7:0] register, is sent to the flash memory, specifying the type of operation to
be performed.
Most flash memories can receive instructions only one bit at a time from the IO0/SO signal
(single-SPI mode), the instruction phase can optionally send 2 bits at a time (over IO0/IO1 in
dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI mode). This can be
configured using the IMODE[1:0] bitfield of QUADSPI_CCR[9:8] register.
When IMODE = 00, the instruction phase is skipped, and the command sequence starts
with the address phase, if present.
Address phase
In the address phase, 1-4 bytes are sent to the flash memory to indicate the address of
the operation. The number of address bytes to be sent is configured in the ADSIZE[1:0]
bitfield of QUADSPI_CCR[13:12] register. In indirect and automatic status-polling modes,
address bytes to be sent are specified in the ADDRESS[31:0] bitfield of QUADSPI_AR
register, while in memory-mapped mode, the address is given directly via the AHB (from the
Cortex or from a DMA).
The address phase can send 1 bit at a time (over SO in single-SPI mode), 2 bits at a time
(over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI
mode). This can be configured using the ADMODE[1:0] bitfield of QUADSPI_CCR[11:10]
register.
When ADMODE = 00, the address phase is skipped, and the command sequence proceeds
directly to the next phase, if any.
Alternate-byte phase
In the alternate-byte phase, 1-4 bytes are sent to the flash memory, generally to control the
mode of operation. The number of alternate bytes to be sent is configured in the [1:0] bitfield
of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR
register.
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Quad-SPI interface (QUADSPI)
The alternate-bytes phase can send 1 bit at a time (over SO in single-SPI mode), 2 bits at a
time (over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI
mode). This can be configured using the ABMODE[1:0] bitfield of QUADSPI_CCR[15:14]
register.
When ABMODE = 00, the alternate-byte phase is skipped, and the command sequence
proceeds directly to the next phase, if any.
There may be times when only a single nibble needs to be sent during the alternate-byte
phase rather than a full byte, such as when the dual-mode is used and only two cycles are
used for the alternate bytes. In this case, the firmware can use quad-mode (ABMODE = 11)
and send a byte with bits 7 and 3 of ALTERNATE set to 1 (keeping the IO3 line high), and
bits 6 and 2 set to 0 (keeping the IO2 line low). In this case, the upper two bits of the nibble
to be sent are placed in bits 4:3 of ALTERNATE, while the lower two bits are placed in bits
1 and 0. For example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE
must be set to 0x8A (1000_1010).
Dummy-cycle phase
In the dummy-cycle phase, 1-31 cycles are given without any data being sent or received,
in order to give time to the flash memory to prepare for the data phase when higher clock
frequencies are used. The number of cycles given during this phase is specified in
the DCYC[4:0] bitfield of QUADSPI_CCR[22:18] register. In both SDR and DDR modes, the
duration is specified as a number of full CLK cycles.
When DCYC is zero, the dummy-cycles phase is skipped, and the command sequence
proceeds directly to the data phase, if present.
The operating mode of the dummy-cycles phase is determined by DMODE.
In order to assure enough “turn-around” time for changing data signals from output mode to
input mode, there must be at least one dummy cycle when using dual or quad mode to
receive data from the flash memory.
Data phase
During the data phase, any number of bytes can be sent to, or received from the flash
memory.
In indirect and automatic status-polling modes, the number of bytes to be sent/received is
specified in the QUADSPI_DLR register.
In indirect-write mode the data to be sent to the flash memory must be written to the
QUADSPI_DR register. In indirect-read mode the data received from the flash memory is
obtained by reading the QUADSPI_DR register.
In memory-mapped mode, the data which is read is sent back directly over the AHB to
the Cortex or to a DMA.
The data phase can send/receive 1 bit at a time (over SO/SI in single-SPI mode), 2 bits at a
time (over IO0/IO1 in dual-SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad-SPI
mode). This can be configured using the ABMODE[1:0] bitfield of QUADSPI_CCR[15:14]
register.
When DMODE = 00, the data phase is skipped, and the command sequence finishes
immediately by raising NCS. This configuration must only be used in only indirect write
mode.
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12.3.4
RM0430
QUADSPI signal interface protocol modes
Single-SPI mode
This legacy SPI mode allows just one single bit to be sent/received serially. In this mode,
data are sent to the flash memory over the SO signal (whose I/O shared with IO0). Data
received from the flash memory arrive via SI (whose I/O shared with IO1).
The different phases can each be configured separately to use this mode by setting the
IMODE/ADMODE/ABMODE/DMODE fields (in QUADSPI_CCR) to 01.
In each phase which is configured in single-SPI mode:
•
IO0 (SO) is in output mode.
•
IO1 (SI) is in input mode (high impedance).
•
IO2 is in output mode and forced to 0.
•
IO3 is in output mode and forced to 1 (to deactivate the “hold” function).
This is the case even for the dummy phase if DMODE = 01.
Dual-SPI mode
In dual-SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.
The different phases can each be configured separately to use dual-SPI mode by setting the
IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 10.
In each phase which is configured in dual-SPI mode:
•
IO0/IO1 are at high-impedance (input) during the data phase for read operations, and
outputs in all other cases.
•
IO2 is in output mode and forced to 0.
•
IO3 is in output mode and forced to 1.
In the dummy phase when DMODE = 01, IO0/IO1 are always high-impedance.
Quad-SPI mode
In quad-SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3
signals.
The different phases can each be configured separately to use quad-SPI mode by setting
the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 11.
In each phase which is configured in this mode, IO0/IO1/IO2/IO3 are all are at
high-impedance (input) during the data phase for read operations, and outputs in all other
cases.
In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance.
IO2 and IO3 are used only in quad-SPI mode. If none of the phases are configured to use
quad-SPI mode, then the pins corresponding to IO2 and IO3 can be used for other functions
even while the QUADSPI is active.
SDR mode
By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in
single-data rate (SDR) mode.
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Quad-SPI interface (QUADSPI)
In SDR mode, when the QUADSPI drives IO0/SO, IO1, IO2, IO3 signals, these signals
transition only with the falling edge of CLK.
When receiving data in SDR mode, the QUADSPI assumes that flash memories also send
the data using CLK falling edge. By default (when SSHIFT = 0), the signals are sampled
using the following (rising) edge of CLK.
DDR mode
When the DDRM bit (QUADSPI_CCR[31]) is set to 1, the QUADSPI operates in
double-data rate (DDR) mode.
In DDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals in the
address/alternate-byte/data phases, a bit is sent on each of CLK falling and rising edges.
The instruction phase is not affected by DDRM. The instruction is always sent using CLK
falling edge.
When receiving data in DDR mode, the QUADSPI assumes that flash memories also send
the data using both CLK rising and falling edges. When DDRM = 1, the firmware must clear
SSHIFT (bit 4 of QUADSPI_CR). Thus, the signals are sampled one half of a CLK cycle
later (on the following, opposite edge).
Figure 54. Example of a DDR command in quad-SPI mode
Instruction
Address Alt. Dummy
Data
NCS
SCLK
IO0
7
6
5
4
3
2
1
0
IO1
4 0 4 0 4 0 4 0
4 0 4 0
5 4 5 4 5 4 5 4
5 4 5 4
IO2
6 2 6 2 6 2 6 2
6 2 6 2
IO3
7 3 7 3 7 3 7 3
7 3 7 3
A23-16A15-8 A7-0 M7-0
Byte1Byte2
I/O switch from output to input
MS35318V2
Dual-flash mode
When the DFM bit (bit 6 of QUADSPI_CR) is 1, the QUADSPI is in dual-flash mode, where
two external quad-SPI flash memories (FLASH 1 and FLASH 2) are used in order to
send/receive 8 bits (or 16 bits in DDR mode) every cycle, effectively doubling the throughput
as well as the capacity.
Each of the flash memories uses the same CLK and optionally the same NCS signals, but
each have separate IO0, IO1, IO2, and IO3 signals.
The dual-flash mode can be used in conjunction with single-, dual-, and quad-SPI modes,
as well as with either SDR or DDR mode.
The flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), must reflect the
total flash memory capacity, which is double the size of one individual component.
If address X is even, then the byte which the QUADSPI gives for address X is the byte at the
address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the
byte at the address X/2 of FLASH 2. In other words, bytes at even addresses are all stored
in FLASH 1 and bytes at odd addresses are all stored in FLASH 2.
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RM0430
When reading the flash memories status registers in dual-flash mode, twice as many bytes
must be read compared to doing the same read in single-flash mode. This means that if
each flash memory gives 8 valid bits after the instruction for fetching the status register, then
the QUADSPI must be configured with a data length of 2 bytes (16 bits), and the QUADSPI
receives one byte from each flash memory. If each flash memory gives a status of 16 bits,
then the QUADSPI must be configured to read 4 bytes to get all the status bits of both flash
memories in dual-flash mode. The least-significant byte of the result (in the data register) is
the least-significant byte of FLASH 1 status register, while the next byte is the leastsignificant byte of FLASH 2 status register. Then, the third byte of the data register is
FLASH 1 second byte, while the forth byte is FLASH 2 second byte (in the case that the
flash memories have 16-bit status registers).
An even number of bytes must always be accessed in dual-flash mode. For this reason,
bit 0 of the data length bitfield (QUADSPI_DLR[0]) is stuck at 1 when DFM = 1.
In dual-flash mode, the behavior of FLASH 1 interface signals are basically the same as in
normal mode. FLASH 2 interface signals have exactly the same waveforms as FLASH 1
during the instruction, address, alternate-byte, and dummy-cycles phases. In other words,
each flash memory always receives the same instruction and the same address. Then,
during the data phase, the BK1_IOx and BK2_IOx buses are both transferring data in
parallel, but the data that are sent to (or received from) FLASH 1 are distinct from those
of FLASH 2.
12.3.5
QUADSPI indirect mode
When in indirect mode, commands are started by writing to QUADSPI registers, and data
are transferred by writing or reading the data register, in the same way as for other
communication peripherals.
When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect-write mode,
where bytes are sent to the flash memory during the data phase. Data are provided by
writing to the data register (QUADSPI_DR).
When FMODE = 01, the QUADSPI is in indirect-read mode, where bytes are received from
the flash memory during the data phase. Data are recovered by reading QUADSPI_DR.
The number of bytes to be read/written is specified in the data length register
(QUADSPI_DLR). If QUADSPI_DLR = 0xFFFF_FFFF (all 1s), then the data length is
considered undefined and the QUADSPI simply continues to transfer data until the end of
flash memory (as defined by FSIZE) is reached. If no bytes are to be transferred, DMODE
(QUADSPI_CCR[25:24]) must be set to 00.
If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4-Gbyte
flash memory), then in this special case, transfers continue indefinitely, stopping only after
an abort request or after the QUADSPI is disabled. After the last memory address is read (at
address 0xFFFF_FFFF), reading continues with address = 0x0000_0000.
When the programmed number of bytes to be transmitted or received is reached, TCF is set
and an interrupt is generated if TCIE = 1. In the case of undefined number of data, the TCF
is set when the limit of the external SPI memory is reached according to the flash memory
size defined in QUADSPI_CR.
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Quad-SPI interface (QUADSPI)
Triggering the start of a command
Essentially, a command starts as soon as firmware gives the last information that is
necessary for this command. Depending on the QUADSPI configuration, there are three
different ways to trigger the start of a command in indirect mode. The commands starts
immediately:
•
after a write is performed to INSTRUCTION[7:0] (QUADSPI_CCR), if no address is
necessary (when ADMODE = 00) and if no data needs to be provided by the firmware
(when FMODE = 01 or DMODE = 00)
•
after a write is performed to ADDRESS[31:0] (QUADSPI_AR), if an address is
necessary (when ADMODE ≠ 00) and if no data needs to be provided by the firmware
(when FMODE = 01 or DMODE = 00)
•
after a write is performed to DATA[31:0] (QUADSPI_DR), if data needs to be provided
by the firmware (when FMODE = 00 and DMODE != 00)
Writes to the alternate byte register (QUADSPI_ABR) never trigger the communication start.
If alternate bytes are required, they must be programmed before.
As soon as a command is started, BUSY (bit 5 of QUADSPI_SR) is automatically set.
FIFO and data management
In indirect mode, data go through a 32-byte FIFO which is internal to the QUADSPI.
FLEVEL[5:0] (QUADSPI_SR[13:8]) indicates how many bytes are currently being held in
the FIFO.
In indirect-write mode (FMODE = 00), the firmware adds data to the FIFO when it writes
QUADSPI_DR. Word writes add 4 bytes to the FIFO, halfword writes add 2 bytes, and byte
writes add only 1 byte. If the firmware adds too many bytes to the FIFO (more than is
indicated by DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write
operation (when TCF is set).
Byte/halfword accesses to QUADSPI_DR must be done only to the least significant
byte/halfword of the 32-bit register.
FTHRES[4:0] is used to define a FIFO threshold. When the threshold is reached, FTF (FIFO
threshold flag) is set. In indirect-read mode, FTF is set when the number of valid bytes to be
read from the FIFO is above the threshold. FTF is also set if there are data in the FIFO after
the last byte is read from the flash memory, regardless of the FTHRES setting.
In indirect-write mode, FTF is set when the number of empty bytes in the FIFO is above the
threshold.
If FTIE = 1, there is an interrupt when FTF is set. If DMAEN = 1, a DMA transfer is initiated
when FTF is set. FTF is cleared by hardware as soon as the threshold condition is no longer
true (after enough data is transferred by the CPU or DMA).
In indirect-read mode when the FIFO becomes full, the QUADSPI temporarily stops reading
bytes from the flash memory to avoid an overrun. The reading of the flash memory does not
restart until 4 bytes become vacant in the FIFO (when FLEVEL ≤ 11). Thus, when
FTHRES ≥ 13, the application must take care to read enough bytes to assure that the
QUADSPI starts retrieving data from the flash memory again. Otherwise, the FTF flag stays
at 0 as long as 11 &lt; FLEVEL &lt; FTHRES.
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12.3.6
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QUADSPI automatic status-polling mode
In automatic status-polling mode, the QUADSPI periodically starts a command to read
a defined number of status bytes (up to 4). The received bytes can be masked to isolate
some status bits and an interrupt can be generated when the selected bits have
a defined value.
Accesses to the flash memory begin in the same way as in indirect-read mode: if no address
is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written.
Otherwise, if an address is required, the first access begins when QUADSPI_AR is written.
BUSY goes high at this point and stays high even between the periodic accesses.
The contents of MASK[31:0] (QUADSPI_PSMAR) are used to mask the data from the flash
memory in automatic status-polling mode. If MASK[n] = 0, then bit n of the result is masked
and not considered. If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n]
(QUADSPI_PSMAR), then there is a match for bit n.
If the polling match mode bit (PMM, bit 23 of QUADSPI_CR) is 0, then “AND” match mode is
activated. This means status match flag (SMF) is set only when there is a match on all of the
unmasked bits.
If PMM = 1, then “OR” match mode is activated. This means SMF is set if there is a match
on any of the unmasked bits.
An interrupt is called when SMF is set if SMIE = 1.
If the automatic status-polling mode stop (APMS) bit is set, the operation stops and BUSY
goes to 0 as soon as a match is detected. Otherwise, BUSY stays at 1, and the periodic
accesses continue until there is an abort or the QUADSPI is disabled (EN = 0).
The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is
deactivated). The content of the data register is not affected by the masking used in the
matching logic. The FTF status bit is set as soon as a new reading of the status is complete,
and FTF is cleared as soon as the data is read.
12.3.7
QUADSPI memory-mapped mode
When configured in memory-mapped mode, the external SPI device is seen as an internal
memory.
It is forbidden to access the quad-SPI flash bank area before having properly configured
and enabled the QUADSPI peripheral.
No more than 256 Mbytes can addressed even if the flash memory capacity is larger.
If an access is made to an address outside of the range defined by FSIZE but still within the
256-Mbyte range, then a bus error is given. The effect of this error depends on the bus
master that attempted the access:
•
If it is the Cortex CPU, bus fault exception is generated when enabled (or an HardFault
exception when bus fault is disabled).
•
If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is
automatically disabled.
Byte, halfword, and word access types are all supported.
Support for execute in place (XIP) operation is implemented, where the QUADSPI
anticipates the next access and load in advance the byte at the following address. If the
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Quad-SPI interface (QUADSPI)
subsequent access is indeed made at a continuous address, the access is completed faster
since the value is already prefetched.
By default, the QUADSPI never stops its prefetch operation, keeping the previous read
operation active with NCS maintained low, even if no access to the flash memory occurs for
a long time. Since flash memories tend to consume more when NCS is held low,
the application may want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR)
so that NCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have
elapsed without any access since when the FIFO becomes full with prefetch data.
BUSY goes high as soon as the first memory-mapped access occurs. Because of the
prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the
peripheral is disabled.
12.3.8
QUADSPI flash memory configuration
The device configuration register (QUADSPI_DCR) can be used to specify the
characteristics of the external SPI flash memory.
The FSIZE[4:0] bitfield defines the size of external memory using the following formula:
Number of bytes in flash memory = 2[FSIZE+1]
FSIZE+1 is effectively the number of address bits required to address the flash memory.
The flash memory capacity can be up to 4 Gbytes (addressed using 32 bits) in indirect
mode, but the addressable space in memory-mapped mode is limited to 256 Mbytes.
If DFM = 1, FSIZE indicates the total capacity of the two flash memories together.
When the QUADSPI executes two commands, one immediately after the other, it raises
NCS high between the two commands for only one CLK cycle by default. If the flash
memory requires more time between commands, the CSHT bitfield can be used to specify
the minimum number of CLK cycles (up to 8) that NCS must remain high.
The clock mode (CKMODE) bit indicates the CLK signal logic level in between commands
(when NCS = 1).
12.3.9
QUADSPI delayed data sampling
By default, the QUADSPI samples the data driven by the flash memory one half of
a CLK cycle after the flash memory drives the signal.
In case of external signal delays, it may be beneficial to sample the data later.
Using SSHIFT (bit 4 of QUADSPI_CR), the sampling of the data can be shifted by half of
a CLK cycle.
Clock shifting is not supported in DDR mode: SSHIFT must be clear when DDRM bit is set.
12.3.10
QUADSPI configuration
The QUADSPI configuration is done in two phases:
1.
QUADSPI peripheral configuration
2.
QUADSPI flash memory configuration
Once configured and enabled, the QUADSPI can be used in one of its three operating
modes: indirect, automatic status-polling, or memory-mapped mode.
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QUADSPI configuration
The QUADSPI is configured using QUADSPI_CR. The user must configure the clock
prescaler division factor and the sample shifting settings for the incoming data.
The DDR mode can be set through the DDRM bit. When setting the quad-SPI interface in
DDR mode, the internal divider of kernel clock must be set with a division ratio of two or
more. Once enabled, the address and the alternate bytes are sent on both clock edges, and
the data are sent/received on both clock edges. Regardless of the DDRM bit setting,
instructions are always sent in SDR mode.
DMA requests are enabled setting the DMAEN bit. In case of interrupt usage, their
respective enable bit can be also set during this phase.
The FIFO level for either DMA request generation or interrupt generation is programmed in
the FTHRES bits.
If a timeout counter is needed, the TCEN bit can be set and the timeout value programmed
in the QUADSPI_LPTR register.
The dual-flash mode can be activated by setting DFM to 1.
QUADSPI flash memory configuration
The parameters related to the targeted external flash memory are configured through the
QUADSPI_DCR register.The user must program the flash memory size in the FSIZE bits,
the chip-select minimum high time in CSHT bits, and the functional mode (Mode 0 or
Mode 3) in the MODE bit.
12.3.11
QUADSPI use
The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]).
Indirect mode
When FMODE is programmed to 00, the indirect-write mode is selected and data can be
sent to the flash memory. With FMODE = 01, the indirect-read mode is selected where data
can be read from the flash memory.
When the QUADSPI is used in indirect mode, the frames are constructed in the following
way:
1.
Specify a number of data bytes to read or write in QUADSPI_DLR.
2.
Specify the frame format, mode and instruction code in QUADSPI_CCR.
3.
Specify optional alternate byte to be sent right after the address phase
in QUADSPI_ABR.
4.
Specify the operating mode in QUADSPI_CR. If FMODE = 00 (indirect-write mode) and
DMAEN = 1, then QUADSPI_AR must be specified before QUADSPI_CR. Otherwise
QUADSPI_DR can be written by the DMA before QUADSPI_AR is updated (if the DMA
controller has already been enabled).
5.
Specify the targeted address in QUADSPI_AR.
6.
Read/write the data from/to the FIFO through QUADSPI_DR.
When writing QUADSPI_CR, the user specifies the following settings:
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•
enable bit (EN) set to 1
•
DMA enable bit (DMAEN) for transferring data to/from RAM
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Quad-SPI interface (QUADSPI)
•
timeout counter enable bit (TCEN)
•
sample shift setting (SSHIFT)
•
FIFO threshold level (FTRHES) to indicate when the FTF flag must be set
•
interrupt enables
•
automatic status-polling mode parameters: match mode and stop mode (valid when
FMODE = 11)
•
clock prescaler
When writing QUADSPI_CCR, the user specifies the following parameters:
•
instruction byte through INSTRUCTION bits
•
the way the instruction has to be sent through the IMODE bits (1/2/4 lines)
•
the way the address has to be sent through the ADMODE bits (None/1/2/4 lines)
•
address size (8/16/24/32-bit) through ADSIZE bits
•
the way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines)
•
alternate bytes number (1/2/3/4) through the ABSIZE bits
•
presence or not of dummy bytes through the DBMODE bit
•
number of dummy bytes through the DCYC bits
•
the way data have to be sent/received (none/1/2/4 lines) through DMODE bits
If neither QUADSPI_AR nor QUADSPI_DR need to be updated for a particular command,
then the command sequence starts as soon as QUADSPI_CCR is written. This is the case
when both ADMODE and DMODE are 00, or if just ADMODE = 00 when in indirect read
mode (FMODE = 01).
When an address is required (ADMODE is not 00) and the data register does not need to be
written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the
address is updated with a write to QUADSPI_AR.
In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is
triggered by a write in the FIFO through QUADSPI_DR.
Automatic status-polling mode
This mode is enabled setting the FMODE bitfield (QUADSPI_CCR[27:26]) to 10. In this
mode, the programmed frame is sent and the data retrieved periodically.
The maximum amount of data read in each frame is 4 bytes. If more data is requested in
QUADSPI_DLR, it is ignored and only 4 bytes are read.
The periodicity is specified in the QUADSPI_PISR register.
Once the status data is retrieved, it can internally be processed:
•
to set the status match flag and generate an interrupt if enabled
•
to stop automatically the periodic retrieving of the status bytes
The received value can be masked with the value stored in QUADSPI_PSMKR and ORed
or ANDed with the value stored in QUADSPI_PSMAR.
In case of match, the status match flag is set and an interrupt is generated if enabled, and
the QUADSPI can be automatically stopped if the AMPS bit is set.
In any case, the latest retrieved value is available in QUADSPI_DR.
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Memory-mapped mode
In memory-mapped mode, the external flash memory is seen as an internal memory but
with some latency during accesses. Only read operations are allowed to the external flash
memory in this mode.
The memory-mapped mode is entered by setting FMODE to 11 in QUADSPI_CCR.
The programmed instruction and frame is sent when a master is accessing
the memory-mapped space.
The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to
QUADSPI_DR in this mode returns zero.
QUADSPI_DLR has no meaning in memory-mapped mode.
12.3.12
Sending the instruction only once
Some flash memories (for example: Winbound) provide a mode where an instruction must
be sent only with the first command sequence, while subsequent commands start directly
with the address. One can take advantage of such a feature using the SIOO bit
(QUADSPI_CCR[28]).
SIOO is valid for all functional modes (indirect, automatic status-polling, and
memory-mapped). If the SIOO bit is set, the instruction is sent only for the first command
following a write to QUADSPI_CCR. Subsequent command sequences skip the instruction
phase, until there is a write to QUADSPI_CCR.
SIOO has no effect when IMODE = 00 (no instruction).
12.3.13
QUADSPI error management
An error can be generated in the following case:
•
In indirect mode or automatic status-polling mode when a wrong address is
programmed in QUADSPI_AR (according to the flash memory size defined by
FSIZE[4:0] in the QUADSPI_DCR), TEF is set and an interrupt is generated if enabled.
Also in indirect mode, if the address plus the data length exceeds the flash memory
size, TEF is set as soon as the access is triggered.
•
In memory-mapped mode, when an out-of-range access is done by a master or when
the QUADSPI is disabled, a bus error is generated as a response to the faulty bus
master request.
When a master is accessing the memory mapped space while the memory-mapped
mode is disabled, a bus error is generated as a response to the faulty bus master
request.
12.3.14
QUADSPI busy bit and abort functionality
Once the QUADSPI starts an operation with the flash memory, the BUSY bit is automatically
set in QUADSPI_SR.
In indirect mode, BUSY is reset once the QUADSPI has completed the requested command
sequence, and the FIFO is empty.
In automatic status-polling mode, BUSY goes low only after the last periodic access is
complete, due to a match when APMS = 1, or due to an abort.
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After the first access in memory-mapped mode, BUSY goes low only on a timeout event or
on an abort.
Any operation can be aborted by setting the ABORT bit in QUADSPI_CR. Once the abort is
completed, BUSY and ABORT are automatically reset, and the FIFO is flushed.
Note:
Some flash memories may misbehave if a write operation to a status registers is aborted.
12.3.15
NCS behavior
By default, NCS is high, deselecting the external flash memory. NCS falls before an
operation begins and rises as soon as it finishes.
When CKMODE = 0 (“mode0”, where CLK stays low when no operation is in progress),
NCS falls one CLK cycle before an operation first rising CLK edge, and NCS rises one CLK
cycle after the operation final rising CLK edge, as shown in the figure below.
Figure 55. NCS when CKMODE = 0 (T = CLK period)
T
T
NCS
SCLK
MS35319V2
When CKMODE=1 (“mode3”, where CLK goes high when no operation is in progress) and
DDRM=0 (SDR mode), NCS still falls one CLK cycle before an operation first rising CLK
edge, and NCS rises one CLK cycle after the operation final rising CLK edge, as shown in
the figure below.
Figure 56. NCS when CKMODE = 1 in SDR mode (T = CLK period)
T
T
NCS
SCLK
MS35320V2
When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), NCS falls one CLK cycle
before an operation first rising CLK edge, and NCS rises one CLK cycle after the operation
final active rising CLK edge, as shown in the figure below. Because DDR operations must
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finish with a falling edge, CLK is low when NCS rises, and CLK rises back up one half of a
CLK cycle afterwards.
Figure 57. NCS when CKMODE = 1 in DDR mode (T = CLK period)
T
T
T/2
NCS
SCLK
MS35321V2
When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation,
the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs
when an operation is stalled, NCS rises just after the abort is requested and then CLK rises
one half of a CLK cycle later, as shown in Figure 58.
Figure 58. NCS when CKMODE = 1 with an abort (T = CLK period)
T
Clock stalled
T/2
NCS
SCLK
Abort
MS35322V2
When not in dual-flash mode (DFM = 0) and FSEL = 0 (default value), only FLASH 1 is
accessed. Thus BK2_NCS stays high, if FSEL = 1, only FLASH 2 is accessed and
BK1_NCS stays high. In dual-flash mode, BK2_NCS behaves exactly the same as
BK1_NCS. Thus, if there is a FLASH 2 and if the application is dual-flash mode only, then
BK1_NCS signal can be used for FLASH 2 as well, and the pin devoted to BK2_NCS can be
used for other functions.
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12.4
QUADSPI interrupts
An interrupt can be produced on the following events:
•
Timeout
•
Status match
•
FIFO threshold
•
Transfer complete
•
Transfer error
Separate interrupt enable bits are available for flexibility.
Table 72. QUADSPI interrupt requests
Interrupt event
Event flag
Enable control bit
Timeout
TOF
TOIE
Status match
SMF
SMIE
FIFO threshold
FTF
FTIE
Transfer complete
TCF
TCIE
Transfer error
TEF
TEIE
12.5
QUADSPI registers
12.5.1
QUADSPI control register (QUADSPI_CR)
Address offset: 0x000
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
PRESCALER[7:0]
23
22
21
20
19
18
17
16
PMM
APMS
Res.
TOIE
SMIE
FTIE
TCIE
TEIE
rw
rw
rw
rw
rw
5
4
3
2
1
0
Res.
SSHIF
T
TCEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
Res.
Res.
Res.
FTHRES[4:0]
rw
rw
rw
rw
rw
FSEL
DFM
rw
rw
DMAE
ABORT
N
rw
rw
EN
rw
Bits 31:24 PRESCALER[7:0]: Clock prescaler
This bitfield defines the scaler factor for generating CLK based on the AHB clock (value+1).
0: FCLK = FAHB, AHB clock used directly as QUADSPI CLK (prescaler bypassed)
1: FCLK = FAHB/2
2: FCLK = FAHB/3
...
255: FCLK = FAHB/256
For odd clock division factors, CLK duty cycle is not 50%. The clock signal remains low one
cycle longer than it stays high.
When setting quad-SPI interface in DDR mode, the prescaler must be set with a division ratio
of two or more.
Note: This bitfield can be modified only when BUSY = 0.
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Bit 23 PMM: Polling match mode
This bit indicates which method must be used for determining a “match” during automatic
status-polling mode.
0: AND match mode. SMF is set if all the unmasked bits received from the flash memory
match the corresponding bits in the match register.
1: OR match mode. SMF is set if any one of the unmasked bits received from the flash
memory matches its corresponding bit in the match register.
Note: This bit can be modified only when BUSY = 0.
Bit 22 APMS: Automatic status-polling mode stop
This bit determines if automatic status-polling is stopped after a match.
0: Automatic status-polling mode is stopped only by abort or by disabling the QUADSPI.
1: Automatic status-polling mode stops as soon as there is a match.
Note: This bit can be modified only when BUSY = 0.
Bit 21 Reserved, must be kept at reset value.
Bit 20 TOIE: Timeout interrupt enable
This bit enables the timeout interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 19 SMIE: Status match interrupt enable
This bit enables the status match interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 18 FTIE: FIFO threshold interrupt enable
This bit enables the FIFO threshold interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 17 TCIE: Transfer complete interrupt enable
This bit enables the transfer complete interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 16 TEIE: Transfer error interrupt enable
This bit enables the transfer error interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bits 15:13 Reserved, must be kept at reset value.
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Bits 12:8 FTHRES[4:0]: FIFO threshold level
This bitfield defines, in indirect mode, the threshold number of bytes in the FIFO that causes
the FIFO threshold flag (bit FTF in register QUADSPI_SR) to be set.
0: In indirect-write mode (FMODE = 00), FTF is set if there are one or more free bytes
location left in the FIF,O or indirect-read mode (FMODE = 01), FTF is set if there are one or
more valid bytes that can be read from the FIFO.
1: In indirect-write mode (FMODE = 00), FTF is set if there are two or more free bytes
location left in the FIFO, or indirect-read mode (FMODE = 01), FTF is set if there are two or
more valid bytes that can be read from the FIFO
...
31: In indirect-write mode (FMODE = 00), FTF is set if there are 32 free bytes location left in
the FIFO, or indirect-read mode (FMODE = 01), FTF is set if there are 32 valid bytes that can
be read from the FIFO.
If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled
before changing the FTHRES value.
Bit 7 FSEL: Flash memory selection
This bit selects the flash memory to be addressed in single-flash mode (when DFM = 0).
0: FLASH 1 selected
1: FLASH 2 selected
Note: This bit can be modified only when BUSY = 0. This bit is ignored when DFM = 1.
Bit 6 DFM: Dual-flash mode
This bit activates dual-flash mode, where two external flash memories are used
simultaneously to double throughput and capacity.
0: Dual-flash mode disabled
1: Dual-flash mode enabled
Note: This bit can be modified only when BUSY = 0.
Bit 5 Reserved, must be kept at reset value.
Bit 4 SSHIFT: Sample shift
By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the flash
memory. This bit allows the data to be sampled later in order to account for external signal
delays.
0: No shift
1: 1/2 cycle shift
The firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1).
Note: This bitfield can be modified only when BUSY = 0.
Bit 3 TCEN: Timeout counter enable
This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this
bit causes the NCS to be released (and thus reduces consumption) if there has not been an
access after a certain amount of time, where this time is defined by TIMEOUT[15:0]
(QUADSPI_LPTR). This bit enables the timeout counter.
By default, the QUADSPI never stops its prefetch operation, keeping the previous read
operation active with NCS maintained low, even if no access to the flash memory occurs for a
long time. Since flash memories tend to consume more when NCS is held low, the
application may want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so
that NCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have
elapsed without an access since when the FIFO becomes full with prefetch data.
0: Timeout counter is disabled, and thus the NCS remains active indefinitely after an access
in memory-mapped mode.
1: Timeout counter is enabled, and thus the NCS is released in memory-mapped mode after
TIMEOUT[15:0] cycles of flash memory inactivity.
Note: This bit can be modified only when BUSY = 0.
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Bit 2 DMAEN: DMA enable
In indirect mode, the DMA can be used to input or output data via the QUADSPI_DR register.
DMA transfers are initiated when the FIFO threshold flag, FTF, is set.
0: DMA is disabled for indirect mode.
1: DMA is enabled for indirect mode.
Bit 1 ABORT: Abort request
This bit aborts the ongoing command sequence. It is automatically reset once the abort is
complete. This bit stops the current transfer.
In automatic status-polling or memory-mapped mode, this bit also reset APM or DM bit.
0: No abort requested
1: Abort requested
Bit 0 EN: QUADSPI enable
0: QUADSPI disabled
1: QUADSPI enabled
12.5.2
QUADSPI device configuration register (QUADSPI_DCR)
Address offset: 0x004
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
Res.
Res.
Res.
CSHT[2:0]
rw
rw
Res.
Res.
Res.
20
19
18
17
16
rw
FSIZE[4:0]
rw
rw
rw
rw
4
3
2
1
0
Res.
CKMO
DE
Res.
Res.
Res.
rw
rw
Bits 31:21 Reserved, must be kept at reset value.
Bits 20:16 FSIZE[4:0]: Flash memory size
This bitfield defines the size of external memory using the following formula:
Number of bytes in flash memory = 2[FSIZE+1]
FSIZE+1 is effectively the number of address bits required to address the flash memory.
The flash memory capacity can be up to 4 Gbytes (addressed using 32 bits) in indirect mode,
but the addressable space in memory-mapped mode is limited to 256 Mbytes.
If DFM = 1, FSIZE indicates the total capacity of the two flash memories together.
Note: This bitfield can be modified only when BUSY = 0.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:8 CSHT[2:0]: Chip select high time
CSHT+1 defines the minimum number of CLK cycles which the chip select (NCS) must
remain high between commands issued to the flash memory.
0: NCS stays high for at least 1 cycle between flash memory commands
1: NCS stays high for at least 2 cycles between flash memory commands
...
7: NCS stays high for at least 8 cycles between flash memory commands
Note: This bitfield can be modified only when BUSY = 0.
Bits 7:1 Reserved, must be kept at reset value.
326/1321
RM0430 Rev 9
RM0430
Quad-SPI interface (QUADSPI)
Bit 0 CKMODE: Mode 0/mode 3
This bit indicates the level that CLK takes between commands (when NCS = 1).
0: CLK must stay low while NCS is high (chip select released). This is referred to as mode 0.
1: CLK must stay high while NCS is high (chip select released). This is referred to as mode 3.
Note: This bitfield can be modified only when BUSY = 0.
12.5.3
QUADSPI status register (QUADSPI_SR)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
Res.
Res.
FLEVEL[5:0]
r
r
r
r
r
7
6
5
4
3
2
1
0
Res.
Res.
BUSY
TOF
SMF
FTF
TCF
TEF
r
r
r
r
r
r
r
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:8 FLEVEL[5:0]: FIFO level
This bitfield gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0
when the FIFO is empty, and 32 when it is full. In memory-mapped mode and in automatic
status-polling mode, FLEVEL is zero.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 BUSY: Busy
This bit is set when an operation is on going. This bit clears automatically when the operation
with the flash memory is finished and the FIFO is empty.
Bit 4 TOF: Timeout flag
This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.
Bit 3 SMF: Status match flag
This bit is set in automatic status-polling mode when the unmasked received data matches
the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to
CSMF.
Bit 2 FTF: FIFO threshold flag
In indirect mode, this bit is set when the FIFO threshold is reached, or if there is any data left
in the FIFO after reads from the flash memory are complete. It is cleared automatically as
soon as threshold condition is no longer true.
In automatic status-polling mode this bit is set every time the status register is read, and the
bit is cleared when the data register is read.
Bit 1 TCF: Transfer complete flag
This bit is set in indirect mode when the programmed number of data is transferred or in any
mode when the transfer is aborted.It is cleared by writing 1 to CTCF.
Bit 0 TEF: Transfer error flag
This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It
is cleared by writing 1 to CTEF.
RM0430 Rev 9
327/1321
335
Quad-SPI interface (QUADSPI)
12.5.4
RM0430
QUADSPI flag clear register (QUADSPI_FCR)
Address offset: 0x00C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CTOF
CSMF
Res.
CTCF
CTEF
w
w
w
w
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 CTOF: Clear timeout flag
Writing 1 clears the TOF flag in QUADSPI_SR.
Bit 3 CSMF: Clear status match flag
Writing 1 clears the SMF flag in QUADSPI_SR.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CTCF: Clear transfer complete flag
Writing 1 clears the TCF flag in QUADSPI_SR.
Bit 0 CTEF: Clear transfer error flag
Writing 1 clears the TEF flag in QUADSPI_SR.
12.5.5
QUADSPI data length register (QUADSPI_DLR)
Address offset: 0x010
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DL[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DL[15:0]
rw
328/1321
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rw
rw
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rw
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rw
RM0430 Rev 9
RM0430
Quad-SPI interface (QUADSPI)
Bits 31:0 DL[31:0]: Data length
Number of data to be retrieved (value+1) in indirect and automatic status-polling modes.
A value no greater than 3 (indicating 4 bytes) must be used for automatic status-polling
mode.
All 1s in indirect mode means undefined length, where the QUADSPI continues until the end
of memory, as defined by FSIZE.
0x0000_0000: 1 byte is to be transferred
0x0000_0001: 2 bytes are to be transferred
0x0000_0002: 3 bytes are to be transferred
0x0000_0003: 4 bytes are to be transferred
...
0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred
0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred
0xFFFF_FFFF: undefined length -- all bytes until the end of flash memory (as defined by
FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F.
DL[0] is stuck at 1 in dual-flash mode (DFM = 1) even when 0 is written to this bit, thus
assuring that each access transfers an even number of bytes.
This bitfield has no effect when in memory-mapped mode (FMODE = 10).
Note: This bitfield can be written only when BUSY = 0.
12.5.6
QUADSPI communication configuration register (QUADSPI_CCR)
Address offset: 0x014
Reset value: 0x0000 0000
31
30
29
28
27
24
23
DDRM
DHHC
Res.
SIOO
FMODE[1:0]
DMODE[1:0]
Res.
rw
rw
rw
rw
rw
13
12
11
10
9
8
rw
rw
15
14
26
25
ABMODE[1:0]
ADSIZE[1:0]
ADMODE[1:0]
IMODE[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
7
22
21
20
19
18
DCYC[4:0]
17
16
ABSIZE[1:0]
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
rw
INSTRUCTION[7:0]
rw
rw
rw
rw
rw
Bit 31 DDRM: Double data rate mode
This bit sets the DDR mode for the address, alternate byte and data phase:
0: DDR mode disabled
1: DDR mode enabled
Note: This bit can be written only when BUSY = 0.
Bit 30 DHHC: DDR hold
This bit delays the data output by 1/4 of the QUADSPI output clock cycle in DDR mode:
0: Data output delayed using analog delay
1: Data output delayed by 1/4 of a QUADSPI output clock cycle
This feature is only active in DDR mode.
Note: This bit can be written only when BUSY = 0.
PRESCALER &gt; 0 is mandatory when DHHC = 1.
Bit 29 Reserved, must be kept at reset value.
RM0430 Rev 9
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Quad-SPI interface (QUADSPI)
RM0430
Bit 28 SIOO: Send instruction only once mode
This bit has no effect when IMODE = 00.See Section 12.3.12 for more details.
0: Instruction sent on every transaction
1: Instruction sent only for the first command
Note: This bit can be written only when BUSY = 0.
Bits 27:26 FMODE[1:0]: Functional mode
This bitfield defines the QUADSPI functional mode of operation.
00: Indirect-write mode
01: Indirect-read mode
10: Automatic status-polling mode
11: Memory-mapped mode
If DMAEN = 1 already, the DMA controller for the corresponding channel must be disabled
before changing the FMODE value.
Note: This bitfield can be written only when BUSY = 0.
Bits 25:24 DMODE[1:0]: Data mode
This bitfield defines the data phase mode of operation:
00: No data
01: Data on a single line
10: Data on two lines
11: Data on four lines
This bitfield also determines the dummy phase mode of operation.
Note: This bitfield can be written only when BUSY = 0.
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 DCYC[4:0]: Number of dummy cycles
This bitfield defines the duration of the dummy phase. In both SDR and DDR modes,
it specifies a number of CLK cycles (0-31).
Note: This bitfield can be written only when BUSY = 0.
Bits 17:16 ABSIZE[1:0]: Alternate-byte size
This bit defines the size of alternate bytes.
00: 8-bit alternate byte
01: 16-bit alternate bytes
10: 24-bit alternate bytes
11: 32-bit alternate bytes
Note: This bitfield can be written only when BUSY = 0.
Bits 15:14 ABMODE[1:0]: Alternate byte mode
This bitfield defines the alternate-byte phase mode of operation.
00: No alternate bytes
01: Alternate bytes on a single line
10: Alternate bytes on two lines
11: Alternate bytes on four lines
Note: This bitfield can be written only when BUSY = 0.
Bits 13:12 ADSIZE[1:0]: Address size
This bit defines address size:
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
Note: This bitfield can be written only when BUSY = 0.
330/1321
RM0430 Rev 9
RM0430
Quad-SPI interface (QUADSPI)
Bits 11:10 ADMODE[1:0]: Address mode
This bitfield defines the address phase mode of operation.
00: No address
01: Address on a single line
10: Address on two lines
11: Address on four lines
Note: This bitfield can be written only when BUSY = 0.
Bits 9:8 IMODE[1:0]: Instruction mode
This bitfield defines the instruction phase mode of operation.
00: No instruction
01: Instruction on a single line
10: Instruction on two lines
11: Instruction on four lines
Note: This bitfield can be written only when BUSY = 0.
Bits 7:0 INSTRUCTION[7:0]: Instruction
Instruction to be sent to the external SPI device.
Note: This bitfield can be written only when BUSY = 0.
12.5.7
QUADSPI address register (QUADSPI_AR)
Address offset: 0x018
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
ADDRESS[31:16]
ADDRESS[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 ADDRESS[31:0]: Address
This bitfield contains the address to be sent to the external flash memory.
Writes to this bitfield are ignored when BUSY = 1 or when FMODE = 11 (memory-mapped
mode).
In dual flash mode, ADDRESS[0] is automatically stuck to 0 as the address must
always be even
12.5.8
QUADSPI alternate-byte register (QUADSPI_ABR)
Address offset: 0x01C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ALTERNATE[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
ALTERNATE[15:0]
rw
rw
rw
rw
rw
rw
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RM0430 Rev 9
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335
Quad-SPI interface (QUADSPI)
RM0430
Bits 31:0 ALTERNATE[31:0]: Alternate bytes
Optional data to be send to the external SPI device right after the address.
Note: This bitfield can be written only when BUSY = 0.
12.5.9
QUADSPI data register (QUADSPI_DR)
Address offset: 0x020
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DATA[31:16]
DATA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 DATA[31:0]: Data
Data to be sent/received to/from the external SPI device.
In indirect write mode, data written to this register is stored on the FIFO before it is sent to the
flash memory during the data phase. If the FIFO is too full, a write operation is stalled until
the FIFO has enough space to accept the amount of data being written.
In indirect read mode, reading this register gives (via the FIFO) the data which was received
from the flash memory. If the FIFO does not have as many bytes as requested by the read
operation and if BUSY=1, the read operation is stalled until enough data is present or until
the transfer is complete, whichever happens first.
In automatic status-polling mode, this register contains the last data read from the flash
memory (without masking).
Word, halfword, and byte accesses to this register are supported. In indirect write mode, a
byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in indirect
read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a word read 4.
Accesses in indirect mode must be aligned to the bottom of this register: a byte read must
read DATA[7:0] and a halfword read must read DATA[15:0].
12.5.10
QUADSPI polling status mask register (QUADSPI_PSMKR)
Address offset: 0x024
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MASK[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MASK[15:0]
rw
332/1321
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RM0430 Rev 9
RM0430
Quad-SPI interface (QUADSPI)
Bits 31:0 MASK[31:0]: Status mask
Mask to be applied to the status bytes received in automatic status-polling mode.
For bit n:
0: Bit n of the data received in automatic status-polling mode is masked and its value is not
considered in the matching logic
1: Bit n of the data received in automatic status-polling mode is unmasked and its value is
considered in the matching logic
Note: This bitfield can be written only when BUSY = 0.
12.5.11
QUADSPI polling status match register (QUADSPI_PSMAR)
Address offset: 0x028
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MATCH[31:16]
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MATCH[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 MATCH[31:0]: Status match
Value to be compared with the masked status register to get a match.
Note: This bitfield can be written only when BUSY = 0.
12.5.12
QUADSPI polling interval register (QUADSPI_PIR)
Address offset: 0x02C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
INTERVAL[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 INTERVAL[15:0]: Polling interval
Number of CLK cycles between two read during automatic status-polling phases.
Note: This bitfield can be written only when BUSY = 0.
RM0430 Rev 9
333/1321
335
Quad-SPI interface (QUADSPI)
12.5.13
RM0430
QUADSPI low-power timeout register (QUADSPI_LPTR)
Address offset: 0x030
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
TIMEOUT[15:0]
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 TIMEOUT[15:0]: Timeout period
After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes
and holds these bytes in the FIFO. This bitfield indicates how many CLK cycles the
QUADSPI waits after the FIFO becomes full until it raises NCS, putting the flash memory in a
lower-consumption state.
Note: This bitfield can be written only when BUSY = 0.
12.5.14
QUADSPI register map
0x018
0x01C
0x020
334/1321
0
0
DCYC[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDRESS[31:0]
0 0 0 0 0 0
ALTERNATE[31:0]
0 0 0 0 0 0
DATA[31:0]
0 0 0 0 0 0
RM0430 Rev 9
TCEN
DMAEN
ABORT
EN
Res.
CKMODE
Res.
SMF
FTF
TCF
TEF
0
0
0
0
0
0
0
0
0
0
0
0
CTEF
0
Res.
Res.
0
CTCF
0
IMODE
[1:0]
0
0
ADMODE
[1:0]
0
0
0
SSHIFT
0
Res.
0
CSMF
0
TOF
0
CTOF
0
BUS
0
ADSIZE
[1:0]
0
0
0
Res.
0
ABMODE
[1:0]
0
0
Res.
DFM
Res.
Res.
FSEL
Res.
Res.
Res.
FLEVEL[5:0]
ABSIZE
[1:0]
Res.
0
0
DMODE
[1:0]
0
0
FMODE
[1:0]
Reset value
QUADSPI_AR
Reset value
QUADSPI_ABR
Reset value
QUADSPI_DR
Reset value
0
Res.
QUADSPI_CCR
0
SIOO
0
DHHC
0x014
0
DDRM
0x010
0
0
Reset value
QUADSPI_DLR
Reset value
0
0
0
Res.
Res.
0
Res.
0
DL[31:0]
0 0 0 0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
QUADSPI_FCR
0x00C
CSHT
0
Reset value
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
Res.
0
Res.
Res.
Res.
FSIZE[4:0]
FTHRES[4:0]
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
TEIE
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
QUADSPI_SR
Res.
Reset value
0x008
0
Res.
QUADSPI_DCR
Res.
0x004
0
Res.
0
FTIE
0
TCIE
0
Res.
0
SMIE
0
Res.
0
Res.
0
Res.
0
TOIE
0
PRESCALER[7:0]
Res.
0
QUADSPI_CR
0x000
Res.
PMM
APMS
Reset value
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 73. QUADSPI register map and reset values
Register
name
0
0
0
0
INSTRUCTION[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0430
Quad-SPI interface (QUADSPI)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
QUADSPI_PIR
0
Res.
0x02C
MASK[31:0]
0
Res.
0x028
QUADSPI_
PSMKR
Reset value
QUADSPI_
PSMAR
Reset value
Res.
0x024
Register
name
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 73. QUADSPI register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
INTERVAL[15:0]
0
Res.
0x030
0
MATCH[31:0]
Reset value
QUADSPI_
LPTR
0
0
0
0
0
TIMEOUT[15:0]
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2 for the register boundary addresses.
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13
Analog-to-digital converter (ADC)
13.1
ADC introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19
multiplexed channels allowing it to measure signals from 16 external sources, two internal
sources, and the VBAT channel. The A/D conversion of the channels can be performed in
single, continuous, scan or discontinuous mode. The result of the ADC is stored into a leftor right-aligned 16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes
beyond the user-defined, higher or lower thresholds.
13.2
ADC main features
•
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
•
Interrupt generation at the end of conversion, end of injected conversion, and in case of
analog watchdog or overrun events
•
Single and continuous conversion modes
•
Scan mode for automatic conversion of channel 0 to channel ‘n’
•
Data alignment with in-built data coherency
•
Channel-wise programmable sampling time
•
External trigger option with configurable polarity for both regular and injected
conversions
•
Discontinuous mode
•
Configurable delay between conversions in Dual/Triple interleaved mode
•
ADC input range: VREF– ≤ VIN ≤ VREF+
•
DMA request generation during regular channel conversion
Figure 59 shows the block diagram of the ADC.
Note:
336/1321
VREF–, if available (depending on package), must be tied to VSSA.
RM0430 Rev 9
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ADC functional description
Figure 59 shows a single ADC block diagram and Table 74 gives the ADC pin description.
Figure 59. Single ADC block diagram
Flags
DMA overrun
End of conversion
End of injected conversion
Analog watchdog event
Interrupt
enable bits
OVR
OVRIE
EOC
EOCIE
JEOC
JEOCIE
AWD
AWDIE
ADC interrupt to NVIC
Analog watchdog
Compare result
Address/data bus
13.3
Analog-to-digital converter (ADC)
Higher threshold (12 bits)
Lower threshold (12 bits
Injected data registers
(4 x 16 bits)
VVREF+
VVREF-
Regular data register
(16 bits)
VVDDA
VVSSA
Analog
mux
DMA request
ADCx_IN0
ADCx_IN1
GPIO
Ports
Up to 4
Injected
channels
Up to 16
ADCx_IN15
Regular
channels
Analog-todigital
converter
ADCCLK
Temp. sensor
VREFINT
VBAT
From ADC
prescaler
JEXTSEL
[3:0] bits
EXTSEL
[3:0] bits
JEXTEN
[1:0] bits
EXTEN
[1:0] bits
From timers
From timers
Start trigger
(injected
group)
Start trigger
(regular
group)
EXTI1_15
EXTI1_11
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Table 74. ADC pins
Name
13.3.1
Signal type
Remarks
VREF+
Input, analog reference
positive
The higher/positive reference voltage for the ADC
VDDA
Input, analog supply
Analog power supply equal to VDD
VREF–
Input, analog reference
negative
The lower/negative reference voltage for the ADC,
VREF– = VSSA
VSSA
Input, analog supply
ground
Ground for analog power supply equal to VSS
ADCx_IN[15:0]
Analog input signals
16 analog input channels
ADC on-off control
The ADC is powered on by setting the ADON bit in the ADC_CR2 register. When the ADON
bit is set for the first time, it wakes up the ADC from the Power-down mode.
The conversion starts when either the SWSTART or the JSWSTART bit is set.
The user can stop conversion and put the ADC in power down mode by clearing the ADON
bit. In this mode the ADC consumes almost no power (only a few &micro;A).
13.3.2
ADC clock
The ADC features two clock schemes:
•
Clock for the analog circuitry: ADCCLK
This clock is generated from the APB2 clock divided by a programmable prescaler that
allows the ADC to work at fPCLK2/2, /4, /6 or /8. Refer to the datasheets for the
maximum value of ADCCLK.
•
Clock for the digital interface (used for registers read/write access)
This clock is equal to the APB2 clock. The digital interface clock can be
enabled/disabled individually for each ADC through the RCC APB2 peripheral clock
enable register (RCC_APB2ENR).
13.3.3
Channel selection
There are 16 multiplexed channels. It is possible to organize the conversions in two groups:
regular and injected. A group consists of a sequence of conversions that can be done on
any channel and in any order. For instance, it is possible to implement the conversion
sequence in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0,
ADC_IN2, ADC_IN2, ADC_IN15.
338/1321
•
A regular group is composed of up to 16 conversions. The regular channels and their
order in the conversion sequence must be selected in the ADC_SQRx registers. The
total number of conversions in the regular group must be written in the L[3:0] bits in the
ADC_SQR1 register.
•
An injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADC_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADC_JSQR register.
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Analog-to-digital converter (ADC)
If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current
conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen
group.
Temperature sensor, VREFINT and VBAT internal channels
•
The temperature sensor is internally connected to ADC1_IN18 and ADC1_IN16
channels which is shared with VBAT. Only one conversion, temperature sensor or
VBAT, must be selected at a time. When the temperature sensor and VBAT conversion
are set simultaneously, only the VBAT conversion is performed.
The internal reference voltage VREFINT is connected to ADC1_IN17.
The VBAT channel is connected to ADC1_IN18 and ADC1_IN16 channels. It can also be
converted as an injected or regular channel.
13.3.4
Single conversion mode
In Single conversion mode the ADC does one conversion. This mode is started with the
CONT bit at 0 by either:
•
setting the SWSTART bit in the ADC_CR2 register (for a regular channel only)
•
setting the JSWSTART bit (for an injected channel)
•
external trigger (for a regular or injected channel)
Once the conversion of the selected channel is complete:
•
•
If a regular channel was converted:
–
The converted data are stored into the 16-bit ADC_DR register
–
The EOC (end of conversion) flag is set
–
An interrupt is generated if the EOCIE bit is set
If an injected channel was converted:
–
The converted data are stored into the 16-bit ADC_JDR1 register
–
The JEOC (end of conversion injected) flag is set
–
An interrupt is generated if the JEOCIE bit is set
Then the ADC stops.
13.3.5
Continuous conversion mode
In continuous conversion mode, the ADC starts a new conversion as soon as it finishes one.
This mode is started with the CONT bit at 1 either by external trigger or by setting the
SWSTART bit in the ADC_CR2 register (for regular channels only).
After each conversion:
•
Note:
If a regular group of channels was converted:
–
The last converted data are stored into the 16-bit ADC_DR register
–
The EOC (end of conversion) flag is set
–
An interrupt is generated if the EOCIE bit is set
Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to Auto-injection section).
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13.3.6
RM0430
Timing diagram
As shown in Figure 60, the ADC needs a stabilization time of tSTAB before it starts
converting accurately. After the start of the ADC conversion and after 15 clock cycles, the
EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
Figure 60. Timing diagram
ADC_CLK
ADON
SWSTART/
JSWSTART
Start 1st conversion
Start next conversion
ADC conversion
ADC
Next ADC conversion
Conversion time
tSTAB
(total conv. time)
EOC
Software clears the EOC bit
ai16047b
13.3.7
Analog watchdog
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds
before alignment.
Table 75 shows how the ADC_CR1 register should be configured to enable the analog
watchdog on one or more channels.
Figure 61. Analog watchdog’s guarded area
Analog voltage
Higher threshold
HTR
Guarded area
Lower threshold
LTR
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Analog-to-digital converter (ADC)
Table 75. Analog watchdog channel selection
Channels guarded by the analog
watchdog
ADC_CR1 register control bits (x = don’t care)
AWDSGL bit
AWDEN bit
JAWDEN bit
None
x
0
0
All injected channels
0
0
1
All regular channels
0
1
0
All regular and injected channels
0
1
1
(1)
injected channel
1
0
1
(1)
regular channel
1
1
0
Single (1) regular or injected channel
1
1
1
Single
Single
1. Selected by the AWDCH[4:0] bits
13.3.8
Scan mode
This mode is used to scan a group of analog channels.
The Scan mode is selected by setting the SCAN bit in the ADC_CR1 register. Once this bit
has been set, the ADC scans all the channels selected in the ADC_SQRx registers (for
regular channels) or in the ADC_JSQR register (for injected channels). A single conversion
is performed for each channel of the group. After each end of conversion, the next channel
in the group is converted automatically. If the CONT bit is set, regular channel conversion
does not stop at the last selected channel in the group but continues again from the first
selected channel.
If the DMA bit is set, the direct memory access (DMA) controller is used to transfer the data
converted from the regular group of channels (stored in the ADC_DR register) to SRAM
after each regular channel conversion.
The EOC bit is set in the ADC_SR register:
•
At the end of each regular group sequence if the EOCS bit is cleared to 0
•
At the end of each regular channel conversion if the EOCS bit is set to 1
The data converted from an injected channel are always stored into the ADC_JDRx
registers.
13.3.9
Injected channel management
Triggered injection
To use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register.
1.
Start the conversion of a group of regular channels either by external trigger or by
setting the SWSTART bit in the ADC_CR2 register.
2.
If an external injected trigger occurs or if the JSWSTART bit is set during the
conversion of a regular group of channels, the current conversion is reset and the
injected channel sequence switches to Scan-once mode.
3.
Then, the regular conversion of the regular group of channels is resumed from the last
interrupted regular conversion.
If a regular event occurs during an injected conversion, the injected conversion is not
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RM0430
interrupted but the regular sequence is executed at the end of the injected sequence.
Figure 62 shows the corresponding timing diagram.
Note:
When using triggered injection, one must ensure that the interval between trigger events is
longer than the injection sequence. For instance, if the sequence length is 30 ADC clock
cycles (that is two conversions with a sampling time of 3 clock periods), the minimum
interval between triggers must be 31 ADC clock cycles.
Auto-injection
If the JAUTO bit is set, then the channels in the injected group are automatically converted
after the regular group of channels. This can be used to convert a sequence of up to 20
conversions programmed in the ADC_SQRx and ADC_JSQR registers.
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected
channels are continuously converted.
Note:
It is not possible to use both the auto-injected and discontinuous modes simultaneously.
Figure 62. Injected conversion latency
ADCCLK
Injection event
Reset ADC
SOC
max latency (1)
ai16049
1. The maximum latency value can be found in the electrical characteristics of the STM32F413/423
datasheets.
13.3.10
Discontinuous mode
Regular group
This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to
convert a short sequence of n conversions (n ≤ 8) that is part of the sequence of
conversions selected in the ADC_SQRx registers. The value of n is specified by writing to
the DISCNUM[2:0] bits in the ADC_CR1 register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx
registers until all the conversions in the sequence are done. The total sequence length is
defined by the L[3:0] bits in the ADC_SQR1 register.
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Analog-to-digital converter (ADC)
Example:
Note:
•
n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10
•
1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each
conversion.
•
2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each
conversion
•
3rd trigger: sequence converted 9, 10.An EOC event is generated at each conversion
•
4th trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion
When a regular group is converted in discontinuous mode, no rollover occurs.
When all subgroups are converted, the next trigger starts the conversion of the first
subgroup. In the example above, the 4th trigger reconverts the channels 0, 1 and 2 in the
1st subgroup.
Injected group
This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to
convert the sequence selected in the ADC_JSQR register, channel by channel, after an
external trigger event.
When an external trigger occurs, it starts the next channel conversions selected in the
ADC_JSQR registers until all the conversions in the sequence are done. The total sequence
length is defined by the JL[1:0] bits in the ADC_JSQR register.
Example:
n = 1, channels to be converted = 1, 2, 3
1st trigger: channel 1 converted
2nd trigger: channel 2 converted
3rd trigger: channel 3 converted and JEOC event generated
4th trigger: channel 1
Note:
When all injected channels are converted, the next trigger starts the conversion of the first
injected channel. In the example above, the 4th trigger reconverts the 1st injected channel
1.
It is not possible to use both the auto-injected and discontinuous modes simultaneously.
Discontinuous mode must not be set for regular and injected groups at the same time.
Discontinuous mode must be enabled only for the conversion of one group.
13.4
Data alignment
The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in Figure 63 and Figure 64.
The converted data value from the injected group of channels is decreased by the userdefined offset written in the ADC_JOFRx registers so the result can be a negative value.
The SEXT bit represents the extended sign value.
For channels in a regular group, no offset is subtracted so only twelve bits are significant.
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Figure 63. Right alignment of 12-bit data
Injected group
SEXT SEXT SEXT SEXT
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Regular group
0
0
0
0
ai16050
Figure 64. Left alignment of 12-bit data
Injected group
SEXT
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
Regular group
D11
D10
D9
ai16051
Special case: when left-aligned, the data are aligned on a half-word basis except when the
resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in
Figure 65.
Figure 65. Left alignment of 6-bit data
Injected group
SEXT SEXT SEXT
SEXT
SEXT SEXT SEXT
SEXT SEXT
D5
D4
D3
D2
D1
D0
0
D4
D3
D2
D1
D0
0
0
Regular group
0
0
0
0
0
0
0
0
D5
ai16052
13.5
Channel-wise programmable sampling time
The ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12 cycles
Example:
With ADCCLK = 30 MHz and sampling time = 3 cycles:
Tconv = 3 + 12 = 15 cycles = 0.5 &micro;s with APB2 at 60 MHz
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13.6
Analog-to-digital converter (ADC)
Conversion on external trigger and trigger polarity
Conversion can be triggered by an external event (such as timer trigger/compare, EXTI
line). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an
injected conversion) are different from “0b00”, then external events are able to trigger a
conversion with the selected polarity. Table 76 provides the correspondence between the
EXTEN[1:0] and JEXTEN[1:0] values and the trigger polarity.
Table 76. Configuring the trigger polarity
Source
Note:
EXTEN[1:0] / JEXTEN[1:0]
Trigger detection disabled
00
Detection on the rising edge
01
Detection on the falling edge
10
Detection on both the rising and falling edges
11
The polarity of the external trigger can be changed on the fly.
The EXTSEL[3:0] and JEXTSEL[3:0] control bits are used to select which out of 16 possible
events can trigger conversion for the regular and injected groups.
Table 77 gives the possible external trigger for regular conversion.
Table 77. External trigger for regular channels
Source
Type
EXTSEL[3:0]
tim1_oc1 event
0000
tim1_oc2 event
0001
tim1_oc3 event
0010
tim2_oc2 event
0011
tim1_oc3 event
0100
tim1_oc4 event
0101
tim2_trgo event
0110
tim3_oc1 event
Internal signal from on-chip timers
0111
tim3_trgo event
1000
tim4_oc4 event
1001
tim5_oc1 event
1010
tim5_oc2 event
1011
tim5_oc3 event
1100
tim8_oc1 event
1101
tim8_trgo event
1110
exti11
External pin
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RM0430
Table 78 gives the possible external trigger for injected conversion.
Table 78. External trigger for injected channels
Source
Connection type
JEXTSEL[3:0]
tim1_oc4 event
0000
tim1_trgo event
0001
tim2_oc1 event
0010
tim2_trgo event
0011
tim3_oc2 event
0100
tim3_oc4 event
0101
tim4_oc1 event
0110
tim4_oc2 event
Internal signal from on-chip timers
0111
tim4_oc3 event
1000
tim4_trgo event
1001
tim5_oc4 event
1010
tim5_trgo event
1011
tim8_oc2 event
1100
tim8_oc3 event
1101
tim8_oc4 event
1110
exti15
External pin
1111
Software source trigger events can be generated by setting SWSTART (for regular
conversion) or JSWSTART (for injected conversion) in ADC_CR2.
A regular group conversion can be interrupted by an injected trigger.
Note:
The trigger selection can be changed on the fly. However, when the selection changes,
there is a time frame of 1 APB clock cycle during which the trigger detection is disabled.
This is to avoid spurious detection during transitions.
13.7
Fast conversion mode
It is possible to perform faster conversion by reducing the ADC resolution. The RES bits are
used to select the number of bits available in the data register. The minimum conversion
time for each resolution is then as follows:
346/1321
•
12 bits: 3 + 12 = 15 ADCCLK cycles
•
10 bits: 3 + 10 = 13 ADCCLK cycles
•
8 bits: 3 + 8 = 11 ADCCLK cycles
•
6 bits: 3 + 6 = 9 ADCCLK cycles
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Analog-to-digital converter (ADC)
13.8
Data management
13.8.1
Using the DMA
Since converted regular channel values are stored into a unique data register, it is useful to
use DMA for conversion of more than one regular channel. This avoids the loss of the data
already stored in the ADC_DR register.
When the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each
conversion of a regular channel, a DMA request is generated. This allows the transfer of the
converted data from the ADC_DR register to the destination location selected by the
software.
Despite this, if data are lost (overrun), the OVR bit in the ADC_SR register is set and an
interrupt is generated (if the OVRIE enable bit is set). DMA transfers are then disabled and
DMA requests are no longer accepted. In this case, if a DMA request is made, the regular
conversion in progress is aborted and further regular triggers are ignored. It is then
necessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to reinitialize both the DMA and the ADC to have the wanted converted channel data transferred
to the right memory location. Only then can the conversion be resumed and the data
transfer, enabled again. Injected channel conversions are not impacted by overrun errors.
When OVR = 1 in DMA mode, the DMA requests are blocked after the last valid data have
been transferred, which means that all the data transferred to the RAM can be considered
as valid.
At the end of the last DMA transfer (number of transfers configured in the DMA controller’s
DMA_SxNDTR register):
•
No new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the
ADC_CR2 register (this avoids generating an overrun error). However the DMA bit is
not cleared by hardware. It must be written to 0, then to 1 to start a new transfer.
•
Requests can continue to be generated if the DDS bit is set to 1. This allows
configuring the DMA in double-buffer circular mode.
To recover the ADC from OVR state when the DMA is used, follow the steps below:
13.8.2
1.
Reinitialize the DMA (adjust destination address and NDTR counter)
2.
Clear the ADC OVR bit in ADC_SR register
3.
Trigger the ADC to start the conversion.
Managing a sequence of conversions without using the DMA
If the conversions are slow enough, the conversion sequence can be handled by the
software. In this case the EOCS bit must be set in the ADC_CR2 register for the EOC status
bit to be set at the end of each conversion, and not only at the end of the sequence. When
EOCS = 1, overrun detection is automatically enabled. Thus, each time a conversion is
complete, EOC is set and the ADC_DR register can be read. The overrun management is
the same as when the DMA is used.
To recover the ADC from OVR state when the EOCS is set, follow the steps below:
1.
Clear the ADC OVR bit in ADC_SR register
2.
Trigger the ADC to start the conversion.
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13.8.3
RM0430
Conversions without DMA and without overrun detection
It may be useful to let the ADC convert one or more channels without reading the data each
time (if there is an analog watchdog for instance). For that, the DMA must be disabled
(DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this
configuration, overrun detection is disabled.
13.9
Temperature sensor
The temperature sensor can be used to measure the junction temperature (TJ) of the
device.
Figure 66 shows the block diagram of the temperature sensor.
When not in use, the sensor can be put in power down mode.
Note:
The TSVREFE bit must be set to enable the conversion of both internal channels: the
ADC1_IN18 (temperature sensor) and the ADC1_IN17 (VREFINT).
Main features
•
Supported temperature range: –40 to 125 &deg;C
•
Precision: &plusmn;1.5 &deg;C
Figure 66. Temperature sensor and VREFINT channel block diagram
TSVREFE control bit
V SENSE
ADC1_IN18
converted data
ADC1
Internal
power block
VREFINT
Address/data bus
Temperature
sensor
ADC1_IN17
MS35936V1
1. VSENSE is input to ADC1_IN18.
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RM0430
Analog-to-digital converter (ADC)
Reading the temperature
To use the sensor:
3.
Select ADC1_IN18 input channel.
4.
Select a sampling time greater than the minimum sampling time specified in the
datasheet.
5.
Set the TSVREFE bit in the ADC_CCR register to wake up the temperature sensor
from power down mode
6.
Start the ADC conversion by setting the SWSTART bit (or by external trigger)
7.
Read the resulting VSENSE data in the ADC data register
8.
Calculate the temperature using the following formula:
Temperature (in &deg;C) = {(VSENSE – V25) / Avg_Slope} + 25
Where:
–
V25 = VSENSE value for 25&deg; C
–
Avg_Slope = average slope of the temperature vs. VSENSE curve (given in mV/&deg;C
or &micro;V/&deg;C)
Refer to the datasheet electrical characteristics section for the actual values of V25 and
Avg_Slope.
Note:
The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADON and TSVREFE bits should be set at the same time.
The temperature sensor output voltage changes linearly with temperature. The offset of this
linear function depends on each chip due to process variation (up to 45 &deg;C from one chip to
another).
The internal temperature sensor is more suited for applications that detect temperature
variations instead of absolute temperatures. If accurate temperature reading is required, an
external temperature sensor should be used.
13.10
Battery charge monitoring
The VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the
VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the
VBAT pin is internally connected to a bridge divider.
When the VBATE is set, the bridge is automatically enabled to connect:
•
Note:
VBAT/4 to the ADC1_IN18 input channel
The VBAT and temperature sensor are connected to the same ADC internal channel
(ADC1_IN18). Only one conversion, either temperature sensor or VBAT, must be selected
at a time. When both conversion are enabled simultaneously, only the VBAT conversion is
performed.
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Analog-to-digital converter (ADC)
13.11
RM0430
ADC interrupts
An interrupt can be produced on the end of conversion for regular and injected groups,
when the analog watchdog status bit is set and when the overrun status bit is set. Separate
interrupt enable bits are available for flexibility.
Two other flags are present in the ADC_SR register, but there is no interrupt associated with
them:
•
JSTRT (Start of conversion for channels of an injected group)
•
STRT (Start of conversion for channels of a regular group)
Table 79. ADC interrupts
Interrupt event
350/1321
Event flag
Enable control bit
End of conversion of a regular group
EOC
EOCIE
End of conversion of an injected group
JEOC
JEOCIE
Analog watchdog status bit is set
AWD
AWDIE
Overrun
OVR
OVRIE
RM0430 Rev 9
RM0430
Analog-to-digital converter (ADC)
13.12
ADC registers
Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions.
The peripheral registers must be written at word level (32 bits). Read accesses can be done
by bytes (8 bits), half-words (16 bits) or words (32 bits).
13.12.1
ADC status register (ADC_SR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OVR
STRT
JSTRT
JEOC
EOC
AWD
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 OVR: Overrun
This bit is set by hardware when data are lost (either in single mode or in dual/triple mode). It
is cleared by software. Overrun detection is enabled only when DMA = 1 or EOCS = 1.
0: No overrun occurred
1: Overrun has occurred
Bit 4 STRT: Regular channel start flag
This bit is set by hardware when regular channel conversion starts. It is cleared by software.
0: No regular channel conversion started
1: Regular channel conversion has started
Bit 3 JSTRT: Injected channel start flag
This bit is set by hardware when injected group conversion starts. It is cleared by software.
0: No injected group conversion started
1: Injected group conversion has started
Bit 2 JEOC: Injected channel end of conversion
This bit is set by hardware at the end of the conversion of all injected channels in the group.
It is cleared by software.
0: Conversion is not complete
1: Conversion complete
Bit 1 EOC: Regular channel end of conversion
This bit is set by hardware at the end of the conversion of a regular group of channels. It is
cleared by software or by reading the ADC_DR register.
0: Conversion not complete (EOCS = 1), or sequence of conversions not complete
(EOCS = 0)
1: Conversion complete (EOCS = 1), or sequence of conversions complete (EOCS = 0)
Bit 0 AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values programmed in
the ADC_LTR and ADC_HTR registers. It is cleared by software.
0: No analog watchdog event occurred
1: Analog watchdog event occurred
RM0430 Rev 9
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Analog-to-digital converter (ADC)
13.12.2
RM0430
ADC control register 1 (ADC_CR1)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
Res.
Res.
Res.
Res.
Res.
OVRIE
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
SCAN
rw
DISCNUM[2:0]
rw
rw
rw
25
24
RES[1:0]
JDISCEN DISCEN JAUTO AWDSGL
rw
rw
rw
rw
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
3
2
1
0
JEOCIE
AWDIE
EOCIE
rw
rw
rw
rw
rw
rw
rw
AWDEN JAWDEN
AWDCH[4:0]
rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the Overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Bits 25:24 RES[1:0]: Resolution
These bits are written by software to select the resolution of the conversion.
00: 12-bit (minimum 15 ADCCLK cycles)
01: 10-bit (minimum 13 ADCCLK cycles)
10: 8-bit (minimum 11 ADCCLK cycles)
11: 6-bit (minimum 9 ADCCLK cycles)
Bit 23 AWDEN: Analog watchdog enable on regular channels
This bit is set and cleared by software.
0: Analog watchdog disabled on regular channels
1: Analog watchdog enabled on regular channels
Bit 22 JAWDEN: Analog watchdog enable on injected channels
This bit is set and cleared by software.
0: Analog watchdog disabled on injected channels
1: Analog watchdog enabled on injected channels
Bits 21:16 Reserved, must be kept at reset value.
Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count
These bits are written by software to define the number of regular channels to be converted
in discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
...
111: 8 channels
Bit 12 JDISCEN: Discontinuous mode on injected channels
This bit is set and cleared by software to enable/disable discontinuous mode on the injected
channels of a group.
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
352/1321
RM0430 Rev 9
RM0430
Analog-to-digital converter (ADC)
Bit 11 DISCEN: Discontinuous mode on regular channels
This bit is set and cleared by software to enable/disable Discontinuous mode on regular
channels.
0: Discontinuous mode on regular channels disabled
1: Discontinuous mode on regular channels enabled
Bit 10 JAUTO: Automatic injected group conversion
This bit is set and cleared by software to enable/disable automatic injected group conversion
after regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
This bit is set and cleared by software to enable/disable the analog watchdog on the channel
identified by the AWDCH[4:0] bits.
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Bit 8 SCAN: Scan mode
This bit is set and cleared by software to enable/disable the Scan mode. In Scan mode, the
inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.
0: Scan mode disabled
1: Scan mode enabled
Note: An EOC interrupt is generated if the EOCIE bit is set:
–
At the end of each regular group sequence if the EOCS bit is cleared to 0
–
At the end of each regular channel conversion if the EOCS bit is set to 1
Note: A JEOC interrupt is generated only on the end of conversion of the last channel if the
JEOCIE bit is set.
Bit 7 JEOCIE: Interrupt enable for injected channels
This bit is set and cleared by software to enable/disable the end of conversion interrupt for
injected channels.
0: JEOC interrupt disabled
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
Bit 6 AWDIE: Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Bit 5 EOCIE: Interrupt enable for EOC
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
Note: 00000: ADC analog input Channel0
00001: ADC analog input Channel1
...
01111: ADC analog input Channel15
10000: ADC analog input Channel16
10001: ADC analog input Channel17
10010: ADC analog input Channel18
Other values reserved
RM0430 Rev 9
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Analog-to-digital converter (ADC)
13.12.3
RM0430
ADC control register 2 (ADC_CR2)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
Res.
SWSTART
29
28
27
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
DDS
DMA
Res.
Res.
Res.
Res.
Res.
Res.
CONT
ADON
rw
rw
rw
rw
EXTEN[1:0]
26
25
24
EXTSEL[3:0]
ALIGN EOCS
rw
rw
23
22
Res.
JSWSTART
21
20
19
JEXTEN[1:0]
18
17
16
JEXTSEL[3:0]
Bit 31 Reserved, must be kept at reset value.
Bit 30 SWSTART: Start conversion of regular channels
This bit is set by software to start conversion and cleared by hardware as soon as the
conversion starts.
0: Reset state
1: Starts conversion of regular channels
Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.
Bits 29:28 EXTEN: External trigger enable for regular channels
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of a regular group.
00: Trigger detection disabled
01: Trigger detection on the rising edge
10: Trigger detection on the falling edge
11: Trigger detection on both the rising and falling edges
Bits 27:24 EXTSEL[3:0]: External event select for regular group
These bits select the external event used to trigger the start of conversion of a regular group:
0000: Timer 1 CC1 event
0001: Timer 1 CC2 event
0010: Timer 1 CC3 event
0011: Timer 2 CC2 event
0100: Timer 2 CC3 event
0101: Timer 2 CC4 event
0110: Timer 2 TRGO event
0111: Timer 3 CC1 event
1000: Timer 3 TRGO event
1001: Timer 4 CC4 event
1010: Timer 5 CC1 event
1011: Timer 5 CC2 event
1100: Timer 5 CC3 event
1101: Timer 8 CC1 event
1110: Timer 8 TRGO event
1111: EXTI line 11
Bit 23 Reserved, must be kept at reset value.
354/1321
RM0430 Rev 9
RM0430
Analog-to-digital converter (ADC)
Bit 22 JSWSTART: Start conversion of injected channels
This bit is set by software and cleared by hardware as soon as the conversion starts.
0: Reset state
1: Starts conversion of injected channels
This bit can be set only when ADON = 1 otherwise no conversion is launched.
Bits 21:20 JEXTEN: External trigger enable for injected channels
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of an injected group.
00: Trigger detection disabled
01: Trigger detection on the rising edge
10: Trigger detection on the falling edge
11: Trigger detection on both the rising and falling edges
Bits 19:16 JEXTSEL[3:0]: External event select for injected group
These bits select the external event used to trigger the start of conversion of an injected group.
0000: Timer 1 CC4 event
0001: Timer 1 TRGO event
0010: Timer 2 CC1 event
0011: Timer 2 TRGO event
0100: Timer 3 CC2 event
0101: Timer 3 CC4 event
0110: Timer 4 CC1 event
0111: Timer 4 CC2 event
1000: Timer 4 CC3 event
1001: Timer 4 TRGO event
1010: Timer 5 CC4 event
1011: Timer 5 TRGO event
1100: Timer 8 CC2 event
1101: Timer 8 CC3 event
1110: Timer 8 CC4 event
1111: EXTI line15
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 ALIGN: Data alignment
This bit is set and cleared by software. Refer to Figure 63 and Figure 64.
0: Right alignment
1: Left alignment
Bit 10 EOCS: End of conversion selection
This bit is set and cleared by software.
0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection
is enabled only if DMA=1.
1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.
Bit 9 DDS: DMA disable selection (for single ADC mode)
This bit is set and cleared by software.
0: No new DMA request is issued after the last transfer (as configured in the DMA controller)
1: DMA requests are issued as long as data are converted and DMA=1
RM0430 Rev 9
355/1321
365
Analog-to-digital converter (ADC)
RM0430
Bit 8 DMA: Direct memory access mode (for single ADC mode)
This bit is set and cleared by software. Refer to the DMA controller chapter for more details.
0: DMA mode disabled
1: DMA mode enabled
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 CONT: Continuous conversion
This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Bit 0 ADON: A/D Converter ON / OFF
This bit is set and cleared by software.
0: Disable ADC conversion and go to power down mode
1: Enable ADC
13.12.4
ADC sample time register 1 (ADC_SMPR1)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
rw
rw
SMP15_0
rw
SMP14[2:0]
rw
rw
26
25
24
23
SMP18[2:0]
22
21
20
SMP17[2:0]
19
18
SMP16[2:0]
17
16
SMP15[2:1]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
SMP13[2:0]
rw
SMP12[2:0]
rw
SMP11[2:0]
rw
SMP10[2:0]
rw
rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
Note: 000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
356/1321
RM0430 Rev 9
RM0430
Analog-to-digital converter (ADC)
13.12.5
ADC sample time register 2 (ADC_SMPR2)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
Res.
Res.
15
14
SMP5_0
29
28
27
26
SMP9[2:0]
rw
24
23
22
21
20
SMP7[2:0]
19
18
SMP6[2:0]
17
16
SMP5[2:1]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
SMP4[2:0]
rw
25
SMP8[2:0]
rw
SMP3[2:0]
rw
SMP2[2:0]
SMP1[2:0]
rw
SMP0[2:0]
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
Note: 000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
13.12.6
ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
Address offset: 0x14-0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
15
14
13
12
Res.
Res.
Res.
Res.
JOFFSETx[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
These bits are written by software to define the offset to be subtracted from the raw
converted data when converting injected channels. The conversion result can be read from
in the ADC_JDRx registers.
13.12.7
ADC watchdog higher threshold register (ADC_HTR)
Address offset: 0x24
Reset value: 0x0000 0FFF
RM0430 Rev 9
357/1321
365
Analog-to-digital converter (ADC)
RM0430
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
15
14
13
12
Res.
Res.
Res.
Res.
HT[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Note:
The software can write to these registers when an ADC conversion is ongoing. The
programmed value will be effective when the next conversion is complete. Writing to this
register is performed with a write delay that can create uncertainty on the effective time at
which the new value is programmed.
13.12.8
ADC watchdog lower threshold register (ADC_LTR)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
15
14
13
12
Res.
Res.
Res.
Res.
LT[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Note:
The software can write to these registers when an ADC conversion is ongoing. The
programmed value will be effective when the next conversion is complete. Writing to this
register is performed with a write delay that can create uncertainty on the effective time at
which the new value is programmed.
13.12.9
ADC regular sequence register 1 (ADC_SQR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
SQ16_0
rw
358/1321
12
11
10
9
8
SQ15[4:0]
rw
rw
rw
23
22
21
20
19
18
rw
rw
rw
rw
rw
rw
7
rw
rw
6
5
4
3
2
1
0
rw
rw
L[3:0]
rw
rw
rw
rw
RM0430 Rev 9
16
SQ16[4:1]
SQ14[4:0]
rw
17
SQ13[4:0]
rw
rw
rw
rw
rw
RM0430
Analog-to-digital converter (ADC)
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 L[3:0]: Regular channel sequence length
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
...
1111: 16 conversions
Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 16th in
the conversion sequence.
Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence
Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence
Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence
13.12.10 ADC regular sequence register 2 (ADC_SQR2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
Res.
Res.
15
14
29
28
rw
rw
13
12
26
25
24
23
rw
rw
rw
rw
rw
11
10
9
8
7
SQ12[4:0]
SQ10_0
rw
27
rw
rw
21
20
19
18
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
SQ11[4:0]
SQ9[4:0]
rw
22
rw
rw
rw
rw
16
SQ10[4:1]
SQ8[4:0]
rw
17
SQ7[4:0]
rw
rw
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:25 SQ12[4:0]: 12th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 12th in
the sequence to be converted.
Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence
Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence
Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence
Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence
Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence
RM0430 Rev 9
359/1321
365
Analog-to-digital converter (ADC)
RM0430
13.12.11 ADC regular sequence register 3 (ADC_SQR3)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
Res.
Res.
29
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
27
26
25
24
23
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
SQ6[4:0]
SQ4_0
rw
28
SQ3[4:0]
rw
22
21
20
19
SQ5[4:0]
17
16
SQ4[4:1]
SQ2[4:0]
rw
18
SQ1[4:0]
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 6th in the
sequence to be converted.
Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence
Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence
Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence
360/1321
RM0430 Rev 9
RM0430
Analog-to-digital converter (ADC)
13.12.12 ADC injected sequence register (ADC_JSQR)
Address offset: 0x38
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
JSQ4[0]
rw
JSQ3[4:0]
rw
21
20
19
JL[1:0]
17
16
JSQ4[4:1]
JSQ2[4:0]
rw
18
JSQ1[4:0]
rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:20 JL[1:0]: Injected sequence length
These bits are written by software to define the total number of conversions in the injected
channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0]=3, see note below)
These bits are written by software with the channel number (0..18) assigned as the 4th in the
sequence to be converted.
Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0]=3, see note below)
Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0]=3, see note below)
Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0]=3, see note below)
Note:
When JL[1:0]=3 (4 injected conversions in the sequencer), the ADC converts the channels
in the following order: JSQ1[4:0], JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].
When JL=2 (3 injected conversions in the sequencer), the ADC converts the channels in the
following order: JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].
When JL=1 (2 injected conversions in the sequencer), the ADC converts the channels in
starting from JSQ3[4:0], and then JSQ4[4:0].
When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0]
channel.
13.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
Address offset: 0x3C - 0x48
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
JDATA[15:0]
r
RM0430 Rev 9
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365
Analog-to-digital converter (ADC)
RM0430
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0]: Injected data
These bits are read-only. They contain the conversion result from injected channel x. The
data are left -or right-aligned as shown in Figure 63 and Figure 64.
13.12.14 ADC regular data register (ADC_DR)
Address offset: 0x4C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
DATA[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Regular data
These bits are read-only. They contain the conversion result from the regular
channels. The data are left- or right-aligned as shown in Figure 63 and
Figure 64.
13.12.15 ADC Common status register (ADC_CSR)
Address offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of ADC1. Nevertheless it is read-only and
does not allow to clear the different status bits. Instead each status bit must be cleared by
writing it to 0 in the corresponding ADC_SR register.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
4
3
2
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OVR1
STRT1 JSTRT1 JEOC 1
r
r
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 OVR1: Overrun flag of ADC1
This bit is a copy of the OVR bit in the ADC1_SR register.
Bit 4 STRT1: Regular channel Start flag of ADC1
This bit is a copy of the STRT bit in the ADC1_SR register.
Bit 3 JSTRT1: Injected channel Start flag of ADC1
This bit is a copy of the JSTRT bit in the ADC1_SR register.
362/1321
RM0430 Rev 9
r
r
1
0
EOC1
AWD1
r
r
RM0430
Analog-to-digital converter (ADC)
Bit 2 JEOC1: Injected channel end of conversion of ADC1
This bit is a copy of the JEOC bit in the ADC1_SR register.
Bit 1 EOC1: End of conversion of ADC1
This bit is a copy of the EOC bit in the ADC1_SR register.
Bit 0 AWD1: Analog watchdog flag of ADC1
This bit is a copy of the AWD bit in the ADC1_SR register.
13.12.16 ADC common control register (ADC_CCR)
Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
23
22
21
20
19
18
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
rw
rw
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSVREFE VBATE
17
16
ADCPRE
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSVREFE: Temperature sensor and VREFINT enable
This bit is set and cleared by software to enable/disable the temperature sensor and the
VREFINT channel.
0: Temperature sensor and VREFINT channel disabled
1: Temperature sensor and VREFINT channel enabled
Note: VBATE must be disabled when TSVREFE is set. If both bits are set, only the VBAT
conversion is performed.
Bit 22 VBATE: VBAT enable
This bit is set and cleared by software to enable/disable the VBAT channel.
0: VBAT channel disabled
1: VBAT channel enabled
Bits 21:18 Reserved, must be kept at reset value.
Bits 17:16 ADCPRE: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC. The clock is
common for all the ADCs.
Note: 00: PCLK2 divided by 2
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
Bits 15:0 Reserved, must be kept at reset value.
RM0430 Rev 9
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Analog-to-digital converter (ADC)
RM0430
13.12.17 ADC register map
The following table summarizes the ADC registers.
Table 80. ADC global register map
Offset
Register
0x000 - 0x04C
ADC1
0x050 - 0x2FC
Reserved
0x300 - 0x308
Common registers
0
JEOCIE
AWDIE
EOCIE
0
0
0
0
0
0
0
0
Res.
Res.
Res.
DDS
DMA
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC_JOFR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
364/1321
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
JOFFSET1[11:0]
Res.
0
0
0
0
0
0
0
0
0
0
JOFFSET3[11:0]
0
0
0
0
0
0
0
JOFFSET4[11:0]
0
0
0
0
0
0
HT[11:0]
1
1
1
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
JOFFSET2[11:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
1
1
LT[11:0]
0
0
0
0
0
0
Regular channel sequence SQx_x bits
0
Res.
0x30
L[3:0]
0
Res.
Reset value
ADC_SQR2
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_SQR1
0
0
Res.
Reset value
0x2C
0
1
Res.
0x28
0
0
Reset value
ADC_LTR
0
0
Res.
ADC_HTR
0
0
Reset value
0x24
0
0
Reset value
0x20
AWDCH[4:0]
Sample time bits SMPx_x
0
ADC_JOFR4
EOC
SCAN
0
0
ADC_JOFR3
AWD
AWD SGL
0
Reset value
0x1C
JEOC
JAUTO
0
Reset value
0x18
STRT
DISCEN
0
Reset value
ADC_JOFR2
JSTRT
Res.
JDISCEN
0
Res.
Res.
Res.
Res.
0
0
Sample time bits SMPx_x
ADC_SMPR2
0x14
0
0
ADON
0
0
CONT
Reset value
Res.
Res.
0
Res.
0
0
ADC_SMPR1
0
EOCS
0
JEXTSEL
[3:0]
0
ALIGN
0
0
JEXTEN[1:0]
0
JAWDEN
0
0
JSWSTART
EXTSEL [3:0]
AWDEN
RES[1:0]
0
Res.
0x10
0
0
0
DISC
NUM [2:0]
Res.
0x0C
0
0
Res.
Reset value
EXTEN[1:0]
Res.
ADC_CR2
0x08
SWSTART
Reset value
OVRIE
Res.
Res.
Res.
Res.
ADC_CR1
0x04
Res.
Reset value
OVR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_SR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
Register
Res.
Offset
Res.
Table 81. ADC register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Regular channel sequence SQx_x bits
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0430 Rev 9
0
0
0
0
0
0
0
RM0430
Analog-to-digital converter (ADC)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADC_SQR3
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
JL[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_JDR1
Res.
0x3C
Res.
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
JDATA[15:0]
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_DR
0
JDATA[15:0]
0
Res.
Reset value
0x4C
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x48
0
JDATA[15:0]
0
Res.
Reset value
ADC_JDR4
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_JDR3
0
JDATA[15:0]
0
Res.
Reset value
0x44
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x40
0
0
Res.
Reset value
ADC_JDR2
0
Injected channel sequence JSQx_x bits
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Res.
0x38
Res.
Reset value
ADC_JSQR
Regular channel sequence SQx_x bits
Res.
0x34
Register
Res.
Offset
Res.
Table 81. ADC register map and reset values (continued)
0
0
0
0
0
Regular DATA[15:0]
0
0
0
0
0
0
0
0
0
0
0
STRT
JSTRT
JEOC
EOC
AWD
0
0
0
Res.
Res.
Res.
Res.
0
0
Res.
Res.
0
OVR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADCPRE[1:0]
Res.
Res.
0
Res.
0
Res.
VBATE
Res.
Res.
Res.
Res.
Res.
TSVREFE.
Reset value
Res.
ADC_CCR
Res.
0x04
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_CSR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
Register
Res.
Offset
Res.
Table 82. ADC register map and reset values (common ADC registers)
Refer to Section 2.2 on page 57 for the register boundary addresses.
RM0430 Rev 9
365/1321
365
Digital-to-analog converter (DAC)
RM0430
14
Digital-to-analog converter (DAC)
14.1
DAC introduction
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In
12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each
with its own converter. In dual DAC channel mode, conversions could be done
independently or simultaneously when both channels are grouped together for synchronous
update operations. An input reference pin, VREF+ (shared with ADC) is available for better
resolution.
14.2
DAC main features
•
Two DAC converters: one output channel each
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
Dual DAC channel for independent or simultaneous conversions
•
DMA capability for each channel
•
DMA underrun error detection
•
External triggers for conversion
•
Input voltage reference, VREF+
Figure 67 shows the block diagram of a DAC channel and Table 83 gives the pin
description.
366/1321
RM0430 Rev 9
RM0430
Digital-to-analog converter (DAC)
Figure 67. DAC channel block diagram
DAC control register
EXTI_9
SWTR IGx
TIM2_T RGO
TIM4_T RGO
TIM5_T RGO
TIM6_T RGO
TIM7_T RGO
TIM8_T RGO
Trigger selectorx
TSELx[2:0] bits
DMAENx
DM A req ue stx
DHRx
12-bit
Control logicx
LFSRx
trianglex
TENx
MAMPx[3:0] bits
WAVENx[1:0] bits
12-bit
DORx
12-bit
VDDA
DAC_ OU Tx
Digital-to-analog
converterx
VSSA
VR EF+
ai14708b
Table 83. DAC pins
Name
Note:
Signal type
Remarks
VREF+
Input, analog reference
positive
The higher/positive reference voltage for the DAC,
V ≤ VREF+ ≤ VDDA
VDDA
Input, analog supply
Analog power supply
VSSA
Input, analog supply ground
Ground for analog power supply
DAC_OUTx
Analog output signal
DAC channelx analog output
Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is
automatically connected to the analog converter output (DAC_OUTx). In order to avoid
parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).
RM0430 Rev 9
367/1321
387
Digital-to-analog converter (DAC)
RM0430
14.3
DAC functional description
14.3.1
DAC channel enable
Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR
register. The DAC channel is then enabled after a startup time tWAKEUP.
Note:
The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital
interface is enabled even if the ENx bit is reset.
14.3.2
DAC output buffer enable
The DAC integrates two output buffers that can be used to reduce the output impedance,
and to drive external loads directly without having to add an external operational amplifier.
Each DAC channel output buffer can be enabled and disabled using the corresponding
BOFFx bit in the DAC_CR register.
14.3.3
DAC data format
Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
•
Single DAC channelx, there are three possibilities:
–
8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0]
bits (stored into the DHRx[11:4] bits)
–
12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4]
bits (stored into the DHRx[11:0] bits)
–
12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0]
bits (stored into the DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHRx (data holding registerx, which are internal non-memorymapped registers). The DHRx register is then loaded into the DORx register either
automatically, by software trigger or by an external event trigger.
368/1321
RM0430 Rev 9
RM0430
Digital-to-analog converter (DAC)
Figure 68. Data registers in single DAC channel mode
31
24
15
7
0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14710b
•
Dual DAC channels, there are three possibilities:
–
8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD
[7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded
into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)
–
12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD
[15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be
loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)
–
12-bit right alignment: data for DAC channel1 to be loaded into the
DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC
channel2 to be loaded into the DAC_DHR12LD [27:16] bits (stored into the
DHR2[11:0] bits)
Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted
and stored into DHR1 and DHR2 (data holding registers, which are internal non-memorymapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and
DOR2 registers, respectively, either automatically, by software trigger or by an external
event trigger.
Figure 69. Data registers in dual DAC channel mode
31
3124
24
15 15
77
0
0
8-bit right aligned
8-bit right aligned
12-bit left aligned
12-bit left aligned
12-bit right aligned
12-bit right aligned
ai14709
ai14709b
14.3.4
DAC conversion
The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx,
DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR
register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR
register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.
RM0430 Rev 9
369/1321
387
Digital-to-analog converter (DAC)
RM0430
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time tSETTLING that depends on the power supply voltage and the
analog output load.
Figure 70. Timing diagram for conversion with trigger disabled TEN = 0
APB1_CLK
DHR
DOR
0x1AC
Output voltage
available on DAC_OUT pin
0x1AC
tSETTLING
14.3.5
ai14711c
DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+.
The analog output voltages on each DAC channel pin are determined by the following
equation:
DOR
DACoutput = V REF &times; -------------4096
14.3.6
DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8
possible events will trigger conversion as shown in Table 84.
Table 84. External triggers
Source
Type
TSEL[2:0]
Timer 6 TRGO event
000
Timer 8 TRGO event
001
Timer 7 TRGO event
Timer 5 TRGO event
Internal signal from on-chip
timers
010
011
Timer 2 TRGO event
100
Timer 4 TRGO event
101
EXTI line9
External pin
110
SWTRIG
Software control bit
111
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
370/1321
RM0430 Rev 9
RM0430
Digital-to-analog converter (DAC)
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note:
TSELx[2:0] bit cannot be changed when the ENx bit is set.
When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DORx register takes only one APB1 clock cycle.
14.3.7
DMA request
Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
A DAC DMA request is generated when an external trigger (but not a software trigger)
occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred
into the DAC_DORx register.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one
DMA request is needed, the user should set only the corresponding DMAENx bit. In this
way, the application can manage both DAC channels in dual mode by using one DMA
request and a unique DMA channel.
DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgement for the first external trigger is received (first request), then no new
request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register
is set, reporting the error condition. DMA data transfers are then disabled and no further
DMA request is treated. The DAC channelx continues to convert old data.
The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the
used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer
correctly. The software should modify the DAC trigger conversion frequency or lighten the
DMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be
resumed by enabling both DMA data transfer and conversion trigger.
For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit
in the DAC_CR register is enabled.
14.3.8
Noise generation
In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The
preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after
each trigger event, following a specific calculation algorithm.
RM0430 Rev 9
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387
Digital-to-analog converter (DAC)
RM0430
Figure 71. DAC LFSR register calculation algorithm
XOR
X6
X 12
11
10
9
8
7
6
X4
5
4
X0
X
3
2
1
0
12
NOR
ai14713c
The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then stored into the DAC_DORx register.
If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.
Figure 72. DAC conversion (SW trigger enabled) with LFSR wave generation
APB1_CLK
DHR
0x00
0xAAA
DOR
0xD55
SWTRIG
ai14714b
Note:
The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
14.3.9
Triangle-wave generation
It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is
configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter
is incremented three APB1 clock cycles after each trigger event. The value of this counter is
then added to the DAC_DHRx register without overflow and the sum is stored into the
DAC_DORx register. The triangle counter is incremented as long as it is less than the
maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is
reached, the counter is decremented down to 0, then incremented again and so on.
372/1321
RM0430 Rev 9
RM0430
Digital-to-analog converter (DAC)
It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.
Figure 73. DAC triangle wave generation
en
n
tio
ta
cr
em
em
ta
cr
en
De
MAMPx[3:0] max amplitude
+ DAC_DHRx base value
n
In
tio
DAC_DHRx base value
0
ai14715c
Figure 74. DAC conversion (SW trigger enabled) with triangle wave generation
APB1_CLK
DHR
DOR
0x00
0xAAA
0xD55
SWTRIG
ai14714b
Note:
The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot
be changed.
14.4
Dual DAC channel conversion
To efficiently use the bus bandwidth in applications that require the two DAC channels at the
same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A
unique register access is then required to drive both DAC channels at the same time.
Eleven possible conversion modes are possible using the two DAC channels and these dual
registers. All the conversion modes can nevertheless be obtained using separate DHRx
registers if needed.
All modes are described in the paragraphs below.
RM0430 Rev 9
373/1321
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Digital-to-analog converter (DAC)
14.4.1
RM0430
Independent trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1
(three APB1 clock cycles later).
When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2
(three APB1 clock cycles later).
14.4.2
Independent trigger with single LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask
value in the MAMPx[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD
or DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to
the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles
later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). Then the LFSR2 counter is updated.
14.4.3
Independent trigger with different LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks
values in the MAMP1[3:0] and MAMP2[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by
MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1
(three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by
MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the LFSR2 counter is updated.
374/1321
RM0430 Rev 9
RM0430
14.4.4
Digital-to-analog converter (DAC)
Independent trigger with single triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum
amplitude value in the MAMPx[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same
triangle amplitude, is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then
updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same
triangle amplitude, is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then
updated.
14.4.5
Independent trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle
amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is
transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle
counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle
amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is
transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle
counter is then updated.
14.4.6
Simultaneous software start
To configure the DAC in this conversion mode, the following sequence is required:
•
Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are
transferred into DAC_DOR1 and DAC_DOR2, respectively.
RM0430 Rev 9
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387
Digital-to-analog converter (DAC)
14.4.7
RM0430
Simultaneous trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and
DAC_DOR2, respectively (after three APB1 clock cycles).
14.4.8
Simultaneous trigger with single LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask
value in the MAMPx[3:0] bits
•
Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or
DHR8RD)
When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1
register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The
LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask,
is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1
clock cycles later). The LFSR2 counter is then updated.
14.4.9
Simultaneous trigger with different LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR mask
values using the MAMP1[3:0] and MAMP2[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is
added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock
cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). The LFSR2 counter is then updated.
376/1321
RM0430 Rev 9
RM0430
14.4.10
Digital-to-analog converter (DAC)
Simultaneous trigger with single triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum
amplitude value using the MAMPx[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with the same triangle
amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three
APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is
added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock
cycles later). The DAC channel2 triangle counter is then updated.
14.4.11
Simultaneous trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude
configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is
updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured
by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.
RM0430 Rev 9
377/1321
387
Digital-to-analog converter (DAC)
14.5
RM0430
DAC registers
Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in
register descriptions.
The peripheral registers have to be accessed by words (32 bits).
14.5.1
DAC control register (DAC_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
Reserved
15
14
Reserved
29
28
DMAU
DRIE2
DMA
EN2
27
26
25
24
MAMP2[3:0]
23
22
21
WAVE2[1:0]
20
19
TSEL2[2:0]
18
17
16
TEN2
BOFF2
EN2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMAU
DRIE1
DMA
EN1
TEN1
BOFF1
EN1
rw
rw
rw
rw
rw
MAMP1[3:0]
rw
rw
rw
WAVE1[1:0]
rw
rw
rw
TSEL1[2:0]
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
This bit is set and cleared by software.
0: DAC channel2 DMA underrun interrupt disabled
1: DAC channel2 DMA underrun interrupt enabled
Bit 28 DMAEN2: DAC channel2 DMA enable
This bit is set and cleared by software.
0: DAC channel2 DMA mode disabled
1: DAC channel2 DMA mode enabled
Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
378/1321
RM0430 Rev 9
RM0430
Digital-to-analog converter (DAC)
Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection
These bits select the external event used to trigger DAC channel2
000: Timer 6 TRGO event
001: Timer 8 TRGO event
010: Timer 7 TRGO event
011: 5 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
Bit 18 TEN2: DAC channel2 trigger enable
This bit is set and cleared by software to enable/disable DAC channel2 trigger
0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are
transferred one APB1 clock cycle later to the DAC_DOR2 register
1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred
three APB1 clock cycles later to the DAC_DOR2 register
Note: When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DOR2 register takes only one APB1 clock cycle.
Bit 17 BOFF2: DAC channel2 output buffer disable
This bit is set and cleared by software to enable/disable DAC channel2 output buffer.
0: DAC channel2 output buffer enabled
1: DAC channel2 output buffer disabled
Bit 16 EN2: DAC channel2 enable
This bit is set and cleared by software to enable/disable DAC channel2.
0: DAC channel2 disabled
1: DAC channel2 enabled
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
This bit is set and cleared by software.
0: DAC channel1 DMA Underrun Interrupt disabled
1: DAC channel1 DMA Underrun Interrupt enabled
Bit 12 DMAEN1: DAC channel1 DMA enable
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
RM0430 Rev 9
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Digital-to-analog converter (DAC)
RM0430
Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable
These bits are set and cleared by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection
These bits select the external event used to trigger DAC channel1.
000: Timer 6 TRGO event
001: Timer 8 TRGO event
010: Timer 7 TRGO event
011: Timer TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bit 2 TEN1: DAC channel1 trigger enable
This bit is set and cleared by software to enable/disable DAC channel1 trigger.
0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are
transferred one APB1 clock cycle later to the DAC_DOR1 register
1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred
three APB1 clock cycles later to the DAC_DOR1 register
Note: When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DOR1 register takes only one APB1 clock cycle.
Bit 1 BOFF1: DAC channel1 output buffer disable
This bit is set and cleared by software to enable/disable DAC channel1 output buffer.
0: DAC channel1 output buffer enabled
1: DAC channel1 output buffer disabled
Bit 0 EN1: DAC channel1 enable
This bit is set and cleared by software to enable/disable DAC channel1.
0: DAC channel1 disabled
1: DAC channel1 enabled
380/1321
RM0430 Rev 9
RM0430
Digital-to-analog converter (DAC)
14.5.2
DAC software trigger register (DAC_SWTRIGR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
6
5
4
3
2
17
16
1
0
Reserved
15
14
13
12
11
10
9
8
7
SWTRIG2 SWTRIG1
Reserved
w
w
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 SWTRIG2: DAC channel2 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2
register value has been loaded into the DAC_DOR2 register.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1 register.
14.5.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
Reserved
Reserved
7
DACC1DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
RM0430 Rev 9
381/1321
387
Digital-to-analog converter (DAC)
14.5.4
RM0430
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
3
2
1
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
rw
rw
rw
rw
rw
DACC1DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
Reserved
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
14.5.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
6
5
20
19
18
17
16
4
3
2
1
0
rw
rw
rw
Reserved
15
14
13
12
11
10
9
8
7
DACC1DHR[7:0]
Reserved
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
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RM0430 Rev 9
RM0430
Digital-to-analog converter (DAC)
14.5.6
DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
Reserved
15
14
13
12
11
10
9
8
7
DACC2DHR[11:0]
Reserved
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
14.5.7
DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
3
2
1
0
Reserved
15
14
13
12
11
rw
rw
rw
rw
rw
10
9
8
7
6
5
4
rw
rw
rw
rw
rw
DACC2DHR[11:0]
rw
rw
Reserved
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 3:0 Reserved, must be kept at reset value.
14.5.8
DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2)
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
6
5
20
19
18
17
16
4
3
2
1
0
rw
rw
rw
Reserved
7
DACC2DHR[7:0]
Reserved
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.
RM0430 Rev 9
383/1321
387
Digital-to-analog converter (DAC)
14.5.9
RM0430
Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
14
13
26
25
24
23
22
21
20
19
18
17
16
DACC2DHR[11:0]
Reserved
15
27
12
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
17
16
DACC1DHR[11:0]
Reserved
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
14.5.10
DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
28
27
rw
rw
rw
rw
rw
15
14
13
12
11
26
25
24
23
22
21
20
19
DACC2DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
10
9
8
7
6
5
4
rw
rw
rw
rw
rw
DACC1DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
18
Reserved
3
2
Reserved
Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
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RM0430 Rev 9
1
0
RM0430
Digital-to-analog converter (DAC)
14.5.11
DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
6
5
20
19
18
17
16
4
3
2
1
0
rw
rw
rw
Reserved
15
14
13
12
11
10
9
8
7
DACC2DHR[7:0]
rw
rw
rw
rw
rw
DACC1DHR[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
14.5.12
DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
r
r
r
r
r
Reserved
15
14
13
12
11
10
9
8
7
r
r
r
r
r
DACC1DOR[11:0]
Reserved
r
r
Bits 31:12 Reserved, must be kept at reset value.
Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
14.5.13
DAC channel2 data output register (DAC_DOR2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
r
r
r
r
r
Reserved
15
14
13
Reserved
12
11
10
9
8
7
DACC2DOR[11:0]
r
r
r
r
r
r
r
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
These bits are read-only, they contain data output for DAC channel2.
RM0430 Rev 9
385/1321
387
Digital-to-analog converter (DAC)
14.5.14
RM0430
DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
Reserved
15
29
27
26
25
24
23
22
13
21
20
19
18
17
16
5
4
3
2
1
0
Reserved
rc_w1
14
Reserved
28
DMAUDR2
12
11
10
9
8
7
6
DMAUDR1
Reserved
rc_w1
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DMAUDR2: DAC channel2 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel2
1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is
driving DAC channel2 conversion at a frequency higher than the DMA service capability rate)
Bits 28:14 Reserved, must be kept at reset value.
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bits 12:0 Reserved, must be kept at reset value.
14.5.15
DAC register map
Table 85 summarizes the DAC registers.
386/1321
Reserved
DACC1DHR[11:0]
DACC1DHR[11:0]
Reserved
Reserved
RM0430 Rev 9
EN1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
20
21
22
Reserved
SWTRIG1
DAC_
DHR12R2
Reserved
TEN1
0x14
WAVE TSEL1[2
:0]
1[2:0]
BOFF1
DAC_
DHR8R1
MAMP1[3:0]
SWTRIG2
0x10
DMAEN1
DAC_
DHR12L1
DMAUDRIE1
0x0C
Reserved
DAC_
DHR12R1
TSEL2[2:0]
EN2
0x08
WAVE
2[2:0]
BOFF2
DAC_
SWTRIGR
MAMP2[3:0]
TEN2
0x04
DMAEN2
DAC_CR
DMAUDRIE2
0x00
Reserved
Offset Register
31
30
29
28
27
26
25
24
23
Table 85. DAC register map
Reserved
DACC1DHR[7:0]
DACC2DHR[11:0]
RM0430
Digital-to-analog converter (DAC)
0x1C
DAC_
DHR8R2
0x20
DAC_
DHR12RD
0x24
DAC_
DHR12LD
0x28
DAC_
DHR8RD
0x2C
DAC_
DOR1
Reserved
DACC1DOR[11:0]
0x30
DAC_
DOR2
Reserved
DACC2DOR[11:0]
0x34
DAC_SR
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
20
DAC_
DHR12L2
21
0x18
22
Offset Register
31
30
29
28
27
26
25
24
23
Table 85. DAC register map (continued)
DACC2DHR[11:0]
Reserved
DACC2DHR[11:0]
DACC2DHR[11:0]
Reserved
Reserved
DMAUDR2
Reserved
Reserved
DACC2DHR[7:0]
DACC1DHR[11:0]
DACC1DHR[11:0]
DACC2DHR[7:0]
Reserved
DMAUDR1
Reserved
Reserved
Reserved
DACC1DHR[7:0]
Reserved
Refer to Section 2.2 on page 57 for the register boundary addresses.
RM0430 Rev 9
387/1321
387
Digital filter for sigma delta modulators (DFSDM)
RM0430
15
Digital filter for sigma delta modulators (DFSDM)
15.1
Introduction
Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to
interface external Σ∆ modulators. It is featuring up to 8 external digital serial interfaces
(channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing
options to offer up to 24-bit final ADC resolution. DFSDM also features optional parallel data
stream input from device memory.
An external Σ∆ modulator provides digital data stream of converted analog values from the
external Σ∆ modulator analog input. This digital data stream is sent into a DFSDM input
channel through a serial interface. DFSDM supports several standards to connect various
Σ∆ modulator outputs: SPI interface and Manchester coded 1-wire interface (both with
adjustable parameters). DFSDM module supports the connection of up to 8 multiplexed
input digital serial channels which are shared with up to 4 DFSDM modules. DFSDM
module also supports alternative parallel data inputs from up to 8 internal 16-bit data
channels (from device memory).
DFSDM is converting an input data stream into a final digital data word which represents an
analog input value on a Σ∆ modulator analog input. The conversion is based on a
configurable digital process: the digital filtering and decimation of the input serial data
stream.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, length of filter, integrator length. The maximum
output data resolution is up to 24 bits. There are two conversion modes: single conversion
mode and continuous mode. The data can be automatically stored in a system RAM buffer
through DMA, thus reducing the software overhead.
A flexible timer triggering system can be used to control the start of conversion of DFSDM.
This timing control is capable of triggering simultaneous conversions or inserting a
programmable delay between conversions.
DFSDM features an analog watchdog function. Analog watchdog can be assigned to any of
the input channel data stream or to final output data. Analog watchdog has its own digital
filtering of input data stream to reach the required speed and resolution of watched data.
To detect short-circuit in control applications, there is a short-circuit detector. This block
watches each input channel data stream for occurrence of stable data for a defined time
duration (several 0’s or 1’s in an input data stream).
An extremes detector block watches final output data and stores maximum and minimum
values from the output data values. The extremes values stored can be restarted by
software.
Two power modes are supported: normal mode and stop mode.
388/1321
RM0430 Rev 9
RM0430
15.2
Digital filter for sigma delta modulators (DFSDM)
DFSDM main features
•
•
•
•
Up to 8 multiplexed input digital serial channels:
–
configurable SPI interface to connect various Σ∆ modulators
–
configurable Manchester coded 1 wire interface support
–
clock output for Σ∆ modulator(s)
Alternative inputs from up to 8 internal digital parallel channels:
–
inputs with up to 16 bit resolution
–
internal sources: memory (CPU/DMA write) data streams
Adjustable digital signal processing:
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
integrator: oversampling ratio (1..256)
Up to 24-bit output data resolution:
–
right bit-shifter on final data (0..31 bits)
•
Signed output data format
•
Automatic data offset correction (offset stored in register by user)
•
Continuous or single conversion
•
Start-of-conversion synchronization with:
•
•
–
software trigger
–
internal timers
–
external events
–
start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0)
Analog watchdog feature:
–
low value and high value data threshold registers
–
own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
input from output data register or from one or more input digital serial channels
–
continuous monitoring independently from standard conversion
Short-circuit detector to detect saturated analog input values (bottom and top ranges):
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream
–
monitoring continuously each channel (8 serial channel transceiver outputs)
•
Break generation on analog watchdog event or short-circuit detector event
•
Extremes detector:
–
store minimum and maximum values of output data values
–
refreshed by software
•
DMA may be used to read the conversion data
•
Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock
absence
•
“regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
RM0430 Rev 9
389/1321
449
Digital filter for sigma delta modulators (DFSDM)
15.3
RM0430
DFSDM implementation
This section describes the configuration implemented in DFSDMx.
Table 86. DFSDMx implementation
DFSDM features
DFSDM1
DFSDM2
Number of channels
4
8
Number of filters
2
4
Input from internal ADC
-
-
Supported trigger sources
(1)
11
11(1)
Pulses skipper
X(2)
X(2)
1. Refer to Table 89: DFSDM triggers connection for available trigger sources.
2. Specific pulses skipper implemented (see Section : Pulses skipper).
390/1321
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
15.4
DFSDM functional description
15.4.1
DFSDM block diagram
Figure 75. Single DFSDM block diagram
APB bus
Sample 1
Sample 0
16
Parallel input data
register 0
Sample 1 Sample 0
16
Channel multiplexer
Parallel input data
register 7
EXTRG[1:0]
Clock
control
CKOUT
DATIN0
Serial transceiver 0
Mode
Clock
control
control
Data 3
Clock 3
16
Data in
Filter
order
Oversampling
ratio
Oversampling
ratio
Sincx filter 0
Integrator unit 0
Filter Oversampling
Oversampling
order
ratio
ratio
Sincx filter 3
Clock in
Integrator unit 3
Serial transceiver 7
CKIN7
8 watchdog filters
8 watchdog comparators
1's, 0's counter
threshold
Short circuit
1's, 0
0's counter
detector
threshold
Interrupt,
break
Status
DATIN7
Mode
control
Config
CKIN0
Data 0
Clock 0
16
Filter 0
config
Interrupt,
break
High threshold
Low threshold
Analog watchdog 0
Short circuit
detector 7
Filter 3
config
High threshold
Low threshold
Right bit-shift
count
Right bit-shift
Calibration
count data
correction unit
Calibration data
DFSDMcorrection
data 0 unit
DFSDM data 3
Data output
Analog watchdog 3
APB bus
Control unit
Configuration
registers
DMA, interrupt, break
control, clock control
Maximum value
Minimum value
Extremes
Interrupts and events:
detector 0
1) end of conversion
Maximum value
2) analog watchdog
Minimum value
3) short circuit detection
Extremes
4) overrun
detector 3
RM0430 Rev 9
MS30765V6
391/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
1. This example shows 4 DFSDM filters and 8 input channels (max. configuration).
15.4.2
DFSDM pins and internal signals
Table 87. DFSDM external pins
Name
Signal Type
Remarks
VDD
Power supply
Digital power supply.
VSS
Power supply
Digital ground power supply.
CKIN[7:0]
Clock input
Clock signal provided from external Σ∆ modulator. FT input.
DATIN[7:0]
Data input
Data signal provided from external Σ∆ modulator. FT input.
CKOUT
Clock output
Clock output to provide clock signal into external Σ∆
modulator.
EXTRG[1:0]
External trigger Input trigger from two EXTI signals to start analog
signal
conversion (from GPIOs: EXTI11, EXTI15).
Table 88. DFSDM internal signals
Name
Signal Type
Remarks
dfsdm_jtrg[10:0]
Internal/
Input trigger from internal/external trigger sources to start
external trigger
analog conversion, see Table 89 for details.
signal
dfsdm_break[3:0]
break signal
output
Break signals event generation from Analog watchdog or
short-circuit detector
dfsdm_dma[3:0]
DMA request
signal
DMA request signal from each DFSDM_FLTx (x=0..3):
end of injected conversion event.
dfsdm_it[3:0]
Interrupt
request signal
Interrupt signal for each DFSDM_FLTx (x=0..3)
Table 89. DFSDM triggers connection
Trigger name
392/1321
Trigger source DFSDM1
Trigger source DFSDM2
dfsdm_jtrg0
TIM1_TRGO2
TIM1_TRGO3
dfsdm_jtrg1
TIM3_TRGO2
TIM3_TRGO3
dfsdm_jtrg2
TIM8_TRGO2
TIM8_TRGO4
dfsdm_jtrg3
TIM10_OC1
TIM10_OC1
dfsdm_jtrg4
N/A
TIM2_TRGO2
dfsdm_jtrg5
TIM4_TRGO2
TIM4_TRGO4
dfsdm_jtrg6
N/A
TIM11_OC1
dfsdm_jtrg7
TIM6_TRGO1
TIM6_TRGO2
dfsdm_jtrg8
N/A
TIM7_TRGO2
dfsdm_jtrg9
EXTI11
EXTI11
dfsdm_jtrg10
EXTI15
EXTI15
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
Table 90. DFSDM break connection
Break name
Break destination
dfsdm_break[0]
TIM1 break
dfsdm_break[1]
-
dfsdm_break[2]
TIM8 break
dfsdm_break[3]
15.4.3
-
DFSDM reset and clocks
DFSDM on-off control
The DFSDM interface is globally enabled by setting DFSDMEN=1 in the
DFSDM_CH0CFGR1 register. Once DFSDM is globally enabled, all input channels (y=0..7)
and digital filters DFSDM_FLTx (x=0..3) start to work if their enable bits are set (channel
enable bit CHEN in DFSDM_CHyCFGR1 and DFSDM_FLTx enable bit DFEN in
DFSDM_FLTxCR1).
Digital filter x DFSDM_FLTx (x=0..3) is enabled by setting DFEN=1 in the
DFSDM_FLTxCR1 register. Once DFSDM_FLTx is enabled (DFEN=1), both Sincx digital
filter unit and integrator unit are reinitialized.
By clearing DFEN, any conversion which may be in progress is immediately stopped and
DFSDM_FLTx is put into stop mode. All register settings remain unchanged except
DFSDM_FLTxAWSR and DFSDM_FLTxISR (which are reset).
Channel y (y=0..7) is enabled by setting CHEN=1 in the DFSDM_CHyCFGR1 register.
Once the channel is enabled, it receives serial data from the external Σ∆ modulator or
parallel internal data sources (CPU/DMA wire from memory).
DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CH0CFGR1) before
stopping the system clock to enter in the STOP mode of the device.
DFSDM clocks
The internal DFSDM clock fDFSDMCLK, which is used to drive the channel transceivers,
digital processing blocks (digital filter, integrator) and next additional blocks (analog
watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC
block and is derived from the system clock SYSCLK or peripheral clock PCLK2 (see
Section 6.3.27: RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)). The
DFSDM clock is automatically stopped in stop mode (if DFEN = 0 for all DFSDM_FLTx,
x=0..3).
The DFSDM serial channel transceivers can receive an external serial clock to sample an
external serial data stream. The internal DFSDM clock must be at least 4 times faster than
the external serial clock if standard SPI coding is used, and 6 times faster than the external
serial clock if Manchester coding is used.
DFSDM can provide one external output clock signal to drive external Σ∆ modulator(s) clock
input(s). It is provided on CKOUT pin. This output clock signal must be in the range
specified in given device datasheet and is derived from DFSDM clock or from audio clock
(see CKOUTSRC bit in DFSDM_CH0CFGR1 register) by programmable divider in the
range 2 - 256 (CKOUTDIV in DFSDM_CH0CFGR1 register). Audio clock source is SAI1
clock selected by SAI1SEL[1:0] field in RCC configuration (see ).
RM0430 Rev 9
393/1321
449
Digital filter for sigma delta modulators (DFSDM)
15.4.4
RM0430
Serial channel transceivers
There are 8 multiplexed serial data channels which can be selected for conversion by each
filter or Analog watchdog or Short-circuit detector. Those serial transceivers receive data
stream from external Σ∆ modulator. Data stream can be sent in SPI format or Manchester
coded format (see SITP[1:0] bits in DFSDM_CHyCFGR1 register).
The channel is enabled for operation by setting CHEN=1 in DFSDM_CHyCFGR1 register.
Channel inputs selection
Serial inputs (data and clock signals) from DATINy and CKINy pins can be redirected from
the following channel pins. This serial input channel redirection is set by CHINSEL bit in
DFSDM_CHyCFGR1 register.
Channel redirection can be used to collect audio data from PDM (pulse density modulation)
stereo microphone type. PDM stereo microphone has one data and one clock signal. Data
signal provides information for both left and right audio channel (rising clock edge samples
for left channel and falling clock edge samples for right channel).
Configuration of serial channels for PDM microphone input:
394/1321
•
PDM microphone signals (data, clock) will be connected to DFSDM input serial channel
y (DATINy, CKOUT) pins.
•
Channel y will be configured: CHINSEL = 0 (input from given channel pins: DATINy,
CKINy).
•
Channel (y-1) (modulo 8) will be configured: CHINSEL = 1 (input from the following
channel ((y-1)+1) pins: DATINy, CKINy).
•
Channel y: SITP[1:0] = 0 (rising edge to strobe data) =&gt; left audio channel on channel
y.
•
Channel (y-1): SITP[1:0] = 1 (falling edge to strobe data) =&gt; right audio channel on
channel y-1.
•
Two DFSDM filters will be assigned to channel y and channel (y-1) (to filter left and
right channels from PDM microphone).
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
Figure 76. Input channel pins redirection
(. . .)
Decode
DATIN(ymax)
CKIN(ymax)
.
.
.
.
.
.
CH(ymax)
.
.
.
FLT(xmax)
Decode
DATINy
CKINy
.
.
.
CHy
FLT(x+1)
FLTx
Decode
DATIN(y-1)
CKIN(y-1)
CH(y-1)
.
.
.
FLT0
.
.
.
.
.
.
.
.
.
Decode
DATAIN0
CKIN0
CH0
RCH
CHINSEL
(. . .)
MSv41632V1
Output clock generation
A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs.
The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see
CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV
bits in DFSDM_CH0CFGR1 register). If the output clock is stopped, then CKOUT signal is
set to low state (output clock can be stopped by CKOUTDIV=0 in DFSDM_CHyCFGR1
register or by DFSDMEN=0 in DFSDM_CH0CFGR1 register). The output clock stopping is
performed:
•
4 system clocks after DFSDMEN is cleared (if CKOUTSRC=0)
•
1 system clock and 3 audio clocks after DFSDMEN is cleared (if CKOUTSRC=1)
Before changing CKOUTSRC the software has to wait for CKOUT being stopped to avoid
glitch on CKOUT pin. The output clock signal frequency must be in the range 0 - 20 MHz.
RM0430 Rev 9
395/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
SPI data input format operation
In SPI format, the data stream is sent in serial format through data and clock signals. Data
signal is always provided from DATINy pin. A clock signal can be provided externally from
CKINy pin or internally from a signal derived from the CKOUT signal source.
In case of external clock source selection (SPICKSEL[1:0]=0) data signal (on DATINy pin) is
sampled on rising or falling clock edge (of CKINy pin) according SITP[1:0] bits setting (in
DFSDM_CHyCFGR1 register).
Internal clock sources - see SPICKSEL[1:0] in DFSDM_CHyCFGR1 register:
•
•
•
Note:
CKOUT signal:
–
For connection to external Σ∆ modulator which uses directly its clock input (from
CKOUT) to generate its output serial communication clock.
–
Sampling point: on rising/falling edge according SITP[1:0] setting.
CKOUT/2 signal (generated on CKOUT rising edge):
–
For connection to external Σ∆ modulator which divides its clock input (from
CKOUT) by 2 to generate its output serial communication clock (and this output
clock change is active on each clock input rising edge).
–
Sampling point: on each second CKOUT falling edge.
CKOUT/2 signal (generated on CKOUT falling edge):
–
For connection to external Σ∆ modulator which divides its clock input (from
CKOUT) by 2 to generate its output serial communication clock (and this output
clock change is active on each clock input falling edge).
–
Sampling point: on each second CKOUT rising edge.
An internal clock source can only be used when the external Σ∆ modulator uses CKOUT
signal as a clock input (to have synchronous clock and data operation).
Internal clock source usage can save CKINy pin connection (CKINy pins can be used for
other purpose).
The clock source signal frequency must be in the range 0 - 20 MHz for SPI coding and less
than fDFSDMCLK/4.
Manchester coded data input format operation
In Manchester coded format, the data stream is sent in serial format through DATINy pin
only. Decoded data and clock signal are recovered from serial stream after Manchester
decoding. There are two possible settings of Manchester codings (see SITP[1:0] bits in
DFSDM_CHyCFGR1 register):
•
signal rising edge = log 0; signal falling edge = log 1
•
signal rising edge = log 1; signal falling edge = log 0
The recovered clock signal frequency for Manchester coding must be in the range
0 - 10 MHz and less than fDFSDMCLK/6.
To correctly receive Manchester coded data, the CKOUTDIV divider (in
DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate
according formula:
( ( CKOUTDIV + 1 ) &times; T SYSCLK ) &lt; T Manchester clock &lt; ( 2 &times; CKOUTDIV &times; T SYSCLK )
396/1321
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
CKINy
(SPICKSEL=0)
tsu
th
twl
twh
tr
tf
tr
tf
SITP = 00
DATINy
SPI timing : SPICKSEL = 0
Figure 77. Channel transceiver timing diagrams
tsu
th
SITP = 01
CKOUT
SPICKSEL=2
SPICKSEL=1
tsu
th
twl
twh
SITP = 0
DATINy
SPI timing : SPICKSEL = 1, 2, 3
SPICKSEL=3
tsu
th
SITP = 1
DATINy
Manchester timing
SITP = 2
SITP = 3
recovered clock
recovered data
0
0
1
1
0
MS30766V3
RM0430 Rev 9
397/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
Clock absence detection
Channels serial clock inputs can be checked for clock absence/presence to ensure the
correct operation of conversion and error reporting. Clock absence detection can be
enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1
register. If enabled, then this clock absence detection is performed continuously on a given
channel. A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if
CKABIE=1) in case of an input clock error (see CKABF[7:0] in DFSDM_FLT0ISR register
and CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF
in DFSDM_FLT0ICR register), the clock absence flag is refreshed. Clock absence status bit
CKABF[y] is set also by hardware when corresponding channel y is disabled (if CHEN[y] = 0
then CKABF[y] is held in set state).
When a clock absence event has occurred, the data conversion (and/or analog watchdog
and short-circuit detector) provides incorrect data. The user should manage this event and
discard given data while a clock absence is reported.
The clock absence feature is available only when the system clock is used for the CKOUT
signal (CKOUTSRC=0 in DFSDM_CH0CFGR1 register).
When the transceiver is not yet synchronized, the clock absence flag is set and cannot be
cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register). The software sequence
concerning clock absence detection feature should be:
•
Enable given channel by CHEN = 1
•
Try to clear the clock absence flag (by CLRCKABF = 1) until the clock absence flag is
really cleared (CKABF = 0). At this time, the transceiver is synchronized (signal clock is
valid) and is able to receive data.
•
Enable the clock absence feature CKABEN = 1 and the associated interrupt CKABIE =
1 to detect if the SPI clock is lost or Manchester data edges are missing.
If SPI data format is used, then the clock absence detection is based on the comparison of
an external input clock with an output clock generation (CKOUT signal). The external input
clock signal into the input channel must be changed at least once per 8 signal periods of
CKOUT signal (which is controlled by CKOUTDIV field in DFSDM_CH0CFGR1 register).
Figure 78. Clock absence timing diagram for SPI
SPI clock presence
timing
max. 8 periods
CKOUT
2
0
1
2
3
4
5
6
7
0
restart counting
CKINy
last clock change
CKABF[y]
error reported
MS30767V2
If Manchester data format is used, then the clock absence means that the clock recovery is
unable to perform from Manchester coded signal. For a correct clock recovery, it is first
necessary to receive data with 1 to 0 or 0 to 1 transition (see Figure 80 for Manchester
synchronization).
398/1321
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
The detection of a clock absence in Manchester coding (after a first successful
synchronization) is based on changes comparison of coded serial data input signal with
output clock generation (CKOUT signal). There must be a voltage level change on DATINy
pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in
DFSDM_CH0CFGR1 register). This condition also defines the minimum data rate to be able
to correctly recover the Manchester coded data and clock signals.
The maximum data rate of Manchester coded data must be less than the CKOUT signal.
So to correctly receive Manchester coded data, the CKOUTDIV divider must be set
according the formula:
( ( CKOUTDIV + 1 ) &times; T SYSCLK ) &lt; T Manchester clock &lt; ( 2 &times; CKOUTDIV &times; T SYSCLK )
A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in
case of an input clock recovery error (see CKABF[7:0] in DFSDM_FLT0ISR register and
CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF in
DFSDM_FLT0ICR register), the clock absence flag is refreshed.
Figure 79. Clock absence timing diagram for Manchester coding
max. 2 periods
CKOUT
0
0
0
1
0
SITP = 2
DATINy
Manchester clock presence
timing
restart counting
last data change
SITP = 3
recovered clock
recovered data 0
0
1
?
?
CKABF[y]
error reported
MS30768V2
RM0430 Rev 9
399/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
Manchester/SPI code synchronization
The Manchester coded stream must be synchronized the first time after enabling the
channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data
transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The
end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after
it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence
detailed hereafter:
CKABF[y] flag is cleared by setting CLRCKABF[y] bit. If channel y is not yet synchronized
the hardware immediately set the CKABF[y] flag. Software is then reading back the
CKABF[y] flag and if it is set then perform again clearing of this flag by setting
CLRCKABF[y] bit. This software sequence (polling of CKABF[y] flag) continues until
CKABF[y] flag is set (signalizing that Manchester stream is synchronized). To be able to
synchronize/receive Manchester coded data the CKOUTDIV divider (in
DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate
according the formula below.
( ( CKOUTDIV + 1 ) &times; T SYSCLK ) &lt; T Manchester clock &lt; ( 2 &times; CKOUTDIV &times; T SYSCLK )
SPI coded stream is synchronized after first detection of clock input signal (valid
rising/falling edge).
Note:
400/1321
When the transceiver is not yet synchronized, the clock absence flag is set and cannot be
cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register).
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
Figure 80. First conversion for Manchester coding (Manchester synchronization)
DATINy
Manchester timing
SITP = 2
SITP = 3
recovered clock
data from
modulator 0
0
1
1
0
CHEN
real start of first conversion
first conversion
start trigger
recovered data
first data bit toggle - end of Manchester synchronization
?
?
1
1
0
CKABF[y]
clearing of CKABF[y] flag by software polling
MS30769V2
External serial clock frequency measurement
The measuring of a channel serial clock input frequency provides a real data rate from an
external Σ∆ modulator, which is important for application purposes.
An external serial clock input frequency can be measured by a timer counting DFSDM
clocks (fDFSDMCLK) during one conversion duration. The counting starts at the first input data
clock after a conversion trigger (regular or injected) and finishes by last input data clock
before conversion ends (end of conversion flag is set). Each conversion duration (time
between first serial sample and last serial sample) is updated in counter CNVCNT[27:0] in
register DFSDM_FLTxCNVTIMR when the conversion finishes (JEOCF=1 or REOCF=1).
The user can then compute the data rate according to the digital filter settings (FORD,
FOSR, IOSR, FAST). The external serial frequency measurement is stopped only if the filter
is bypassed (FOSR=0, only integrator is active, CNVCNT[27:0]=0 in
DFSDM_FLTxCNVTIMR register).
In case of parallel data input (Section 15.4.6: Parallel data inputs) the measured frequency
is the average input data rate during one conversion.
RM0430 Rev 9
401/1321
449
Digital filter for sigma delta modulators (DFSDM)
Note:
RM0430
When conversion is interrupted (e.g. by disabling/enabling the selected channel) the
interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not
interrupt the conversion for correct conversion duration result.
Conversion times:
injected conversion or regular conversion with FAST = 0 (or first conversion if
FAST=1):
for Sincx filters (x=1..5):
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN
for FastSinc filter:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN
regular conversion with FAST = 1 (except first conversion):
for Sincx and FastSinc filters:
t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where:
•
fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data
rate (in case of parallel data input)
•
FOSR is the filter oversampling ratio: FOSR = FOSR[9:0]+1 (see DFSDM_FLTxFCR
register)
•
IOSR is the integrator oversampling ratio: IOSR = IOSR[7:0]+1 (see DFSDM_FLTxFCR
register)
•
FORD is the filter order: FORD = FORD[2:0] (see DFSDM_FLTxFCR register)
Channel offset setting
Each channel has its own offset setting (in register) which is finally subtracted from each
conversion result (injected or regular) from a given channel. Offset correction is performed
after the data right bit shift. The offset is stored as a 24-bit signed value in OFFSET[23:0]
field in DFSDM_CHyCFGR2 register.
Data right bit shift
To have the result aligned to a 24-bit value, each channel defines a number of right bit shifts
which will be applied on each conversion result (injected or regular) from a given channel.
The data bit shift number is stored in DTRBS[4:0] bits in DFSDM_CHyCFGR2 register.
The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is
maintained, in order to have valid 24-bit signed format of result data.
Pulses skipper
Purpose of the pulses skipper is to implement delay line like behavior for given input
channel(s). Given number of samples from input serial data stream (serial stream only) can
be discarded before they enter into the filter. This data discarding is performed by skipping
given number of sampling input clock pulses (given serial data samples are then not
sampled by filter). The sampling clock is gated by pulses skipper function for given number
of clock pulses. When given clock pulses are skipped then the filtering continues for
following input data. With comparison to non skipped data stream this operation causes that
402/1321
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
the final output sample (and next samples) from filter will be calculated from later input data.
This final sample then looks a bit in forward - because it is calculated from newer input
samples than the “non-skipped” sample. The final “skipped sample” is converted later
because the skipped input data samples must be replaced by followed input data samples.
The final data buffers behavior (skipped and non-skipped output data buffers comparison)
looks like the non-skipped data stream is a bit delayed - both data buffers will be phase
shifted.
The implementation of clock skipping is based on a block named MCHDLY (multi-channel
delay block) added on the top level of DFSDMs (see Figure 81). This MCHDLY block is
controlled via a MCHDLYCR register (see the Section 8.2.10: DFSDM Multi-channel delay
control register (SYSCFG_MCHDLYCR)) where are all MCHDLY control bits.
By using MCHDLY block, the DFSDMs can be used for beamforming with up to 6 digital
microphones. In beamforming mode the clock to digital microphones (or sigma-delta
modulators) is provided by DFSDM2 clock output (dfsdm2_ckout signal on Figure 81). This
clock output signal is then distributed to (see Figure 81):
•
OR gates (to implement pulse skipping by clock masking/gating)
•
Trigger inputs (ETR) of two timers: TIM4 and TIM3 (to define how many pulses will be
skipped)
•
DFSDM1_CKOUT and DFSDM2_CKOUT pins outputs through M1 and M2
multiplexers (to generate output clock signal on DFSDMx pins)
The OR gates are used to skip the input serial clock pulses provided to the DFSDMs in
order to generate a delay on the corresponding input channel.
This clock gating is controlled by two timers (TIM4 and TIM3). Timers are programmed in
one shot mode to generate masking pulse with defined length to gate required number of
clock pulses.
In the Figure 81, MIC1 receives its serial clock via another clock output pin
(DFSDM1_CKOUT pin) which can provide either clock output from DFSDM2 or DFSDM1
CKOUT signal. This configuration allows to use for low-power use-cases only one
microphone (MIC1) - while DFSDM2_CKOUT is disabled and DFSDM1_CKOUT enabled
(for example voice detection), and reusing MIC1 for beamforming use cases (when
DFSDM2_CKOUT is enabled).
RM0430 Rev 9
403/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
Figure 81. Multi-channel delay block for pulse skipping
M8
DatIn3
DatIn2
1_CKIN3
0
1
1_CKIN2
0
1
L/R
M6
1
0
1_DATIN2
M5
CkIn3
Aclk
CkIn2
1_DATIN1
M7
DatIn1
DatIn0
1_CKIN0
0
1
CkIn1
CkIn0
CkOutB
0
CkOut
Aclk
2_CKOUT
M2
1
2_DATIN7
M20
DatIn7
0
1
0
1
CkIn7
CkIn6
2_DATIN5
DatIn4
0
1
L/R
GND
0
1
2_CKIN2
0
1
CkIn2
2_DATIN1
0
1
OC4
G6
G5
ETR
1
MCHDLY2EN
MCHDLY
RM0430 Rev 9
PCLK
OC3
OC2
OC1
M29
PCLK
TIM3
PCLK2
ETR
ETR
PCLK1
0
G3
G2
ETR
1
0
OC1
STM32
M28
ITR1
OC2
MCHDLY1EN
TIM4
CkIn1
CkIn0
MCHDLY1EN
G1
1 M27
0
MCHDLY2EN
BSCKSEL
PCLK
2_CKIN0
Clk1_gated DM1 1
0
Clk2_gated
1
0 DM2
Clk3_gated DM3 1
0
Clk4_gated
1
DM4
0
Clk5_gated DM5 1
0
Clk6_gated
1
0 DM6
0
1
dfsdm2_ckout
2_CKIN1
M10
2_DATIN0
DatIn0
M9
1
0
M17
DatIn1
L/R
G4
MIC6
CkIn3
M11
0
1
M12
DatIn2
2_CKIN3
DFSDM2CFG
MIC5
1
0
2_DATIN2
M18
DatIn3
L/R
VCC
404/1321
CkIn4
2_DATIN3
L/R
MCHDLY
CkIn5
ITR1
MIC4
2_CKIN4
M14
MIC3
2_CKIN5
M13
1
0
M19
DatIn5
2_DATIN4
GND
DFSDM2 (NBT=8, NBF=4)
2_CKIN7
2_CKIN6
M16
DatIn6
M15
1
0
2_DATIN6
VCC
From PLLI2S
0
1
DFSDM2CKOSEL
1_CKIN1
PCLK
1_DATIN0
M4
1
0
L/R
M3
MIC2
GND
VCC
DFSDM1 (NBT=4, NBF=2)
DFSDM1CFG
M1
1_DATIN3
DFSDM1CKOSEL
MIC1
1
From PLLI2S
CkOutB
CkOut
0
1_CKOUT
MSv43804v2
RM0430
Digital filter for sigma delta modulators (DFSDM)
The DFSDM shall be configured as follow:
•
CHINSEL must be set to 0 for all channels (channel data are taken from pins of the
same channel)
•
SPICKSEL must be set to 0 for all channels (in order to select external CKINy as input
clock)
The TIM3 and TIM4 shall be configured as follow:
•
TIM4 outputs (OC[2:1]) and TIM3 outputs (OC[4:1]) must be low in inactive mode
when no gating is required. When the application needs to provide delays to
microphones, then the timers shall be programmed in One Pulse Mode (OPM). In this
mode, the timer allows the counter to be started in response to a rising edge on ETRx
(or ITRx) input and to generate a pulse with a programmable length.
•
The ETRx input must be used when the bitstream clock is generated by the DFSDM2.
•
The clock reference used by the timers can be its APB clock or its APB clock multiplied
by 2 or 4. The higher this frequency is, the better it is.
While TIM3 and TIM4 are working with DFSDM2 using ETRx input, the timers
reference clock frequency must be at least 12 times the frequency of the input
bitstream clock, taking the assumption that the bitstream clock duty cycle is 50%. This
is due to the fact that ETRx input have a bigger propagation delay: up to 5 periods of
the timers reference clock.
•
Using these rules will prevent timing violation.
In case it is required to synchronize DFSDM1 and DFSDM2 filter conversions (for example
for beamforming applications), the following sequence should take place (refer to
Figure 81):
•
Enable audio clocks used by DFSDM
•
Program DFSDM to use the CkIn
•
Use the DFSDM2 CkOut to inject the DFSDM2 audio clock to the CkIn
•
Block the DFSDM2 CkOut signals: bit BSCKSEL=0
•
Start all filters conversions (all used DFSDM1 and DFSDM2 filters)
•
Release the DFSDM2 CkOut: bit BSCKSEL=1
Figure 82. Pulses skipper operation
Software access
dfsdm2_ckout
TIM3_OC1
clk3_gated
Timers clock reference
Margin
MSv43805V1
RM0430 Rev 9
405/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
Table 91. Demultiplexers (DM[6:1]) operation
Control
Output 0
Output 1
0
input
L
1
L
input
x
x 0 0
BSCKSEL
x
MCHDLYEN1
DFSDM1_D0SEL
x
G[2:1]
DFSDM1_D2SEL
M7
x 0 0 x
M[29:27]
DFSDM1_CK02SEL
M8
DFSDM2_D0SEL
M17
TIM3
DM2
DFSDM2_D2SEL
M18
TIM4
Beamforming4_
DFSDM_3_5
DFSDM1_CFG
DFSDM2_D4SEL
M19
x
ON OFF 1 1 0 0 0 0 x
DFSDM1_CK13SEL
DFSDM2_D6SEL
M20
x
OFF ON
DM1
DFSDM2_CK04SEL
DM6
x
Beamforming4_
DFSDM_1_3
M[6:3]
DFSDM2_CK15SEL
DM5
x
OFF OFF OFF ON
-
MCHDLYEN2
DFSDM2_CK26SEL
DM4
x
Speech recognition_1
-
DFSDM1_CKOSEL
DFSDM2_CK37SEL
DM3
x
-
Multiplexer/
gate on schematic
M1
DFSDM2_CFG
x
-
Use cases
G[6:3]
DFSDM2_CKOSEL
M2
x
DFSDM1
x
DFSDM2
M[16:9]
Table 92. Use-cases examples for beamforming applications
x 1 1 1 0 x
x
x
x
x 0 1
OFF ON
ON OFF 1 1 0 0 1 1 x 1 1 x 1 0 x
x
x
x
x 0 1
Beamforming4_
DFSDM_5_7
OFF ON
ON OFF 1 1 1 1 1 1 1 1 x
x 1 0 x
x
x
x
x 0 1
Beamforming4_
DFSDM_1_7
OFF ON
ON OFF 1 1 1 1 0 0 1 x
x 1 1 0 x
x
x
x
x 0 1
Beamforming6_
DFSDM_1_3_1
ON
ON
ON
ON
1 1 0 0 0 0 x
x 1 1 1 1 1 0 0 x 1 1 1
Beamforming6_
DFSDM_1_3_3
ON
ON
ON
ON
1 1 0 0 0 0 x
x 1 1 1 1 1 1 1 1 x 1 1
406/1321
RM0430 Rev 9
RM0430
15.4.5
Digital filter for sigma delta modulators (DFSDM)
Configuring the input serial interface
The following parameters must be configured for the input serial interface:
15.4.6
•
Output clock predivider. There is a programmable predivider to generate the output
clock from DFSDM clock (2 - 256). It is defined by CKOUTDIV[7:0] bits in
DFSDM_CH0CFGR1 register.
•
Serial interface type and input clock phase. Selection of SPI or Manchester coding
and sampling edge of input clock. It is defined by SITP [1:0] bits in
DFSDM_CHyCFGR1 register.
•
Input clock source. External source from CKINy pin or internal from CKOUT pin. It is
defined by SPICKSEL[1:0] field in DFSDM_CHyCFGR1 register.
•
Final data right bit-shift. Defines the final data right bit shift to have the result aligned
to a 24-bit value. It is defined by DTRBS[4:0] in DFSDM_CHyCFGR2 register.
•
Channel offset per channel. Defines the analog offset of a given serial channel (offset
of connected external Σ∆ modulator). It is defined by OFFSET[23:0] bits in
DFSDM_CHyCFGR2 register.
•
short-circuit detector and clock absence per channel enable. To enable or disable
the short-circuit detector (by SCDEN bit) and the clock absence monitoring (by
CKABEN bit) on a given serial channel in register DFSDM_CHyCFGR1.
•
Analog watchdog filter and short-circuit detector threshold settings. To configure
channel analog watchdog filter parameters and channel short-circuit detector
parameters. Configurations are defined in DFSDM_CHyAWSCDR register.
Parallel data inputs
Each input channel provides a register for 16-bit parallel data input (besides serial data
input). Each 16-bit parallel input can be sourced from internal data sources only:
•
direct CPU/DMA writing.
The selection for using serial or parallel data input for a given channel is done by field
DATMPX[1:0] of DFSDM_CHyCFGR1 register. In DATMPX[1:0] is also defined the parallel
data source: direct write by CPU/DMA.
Each channel contains a 32-bit data input register DFSDM_CHyDATINR in which it can be
written a 16-bit data. Data are in 16-bit signed format. Those data can be used as input to
the digital filter which is accepting 16-bit parallel data.
If serial data input is selected (DATMPX[1:0] = 0), the DFSDM_CHyDATINR register is write
protected.
Input from memory (direct CPU/DMA write)
The direct data write into DFSDM_CHyDATINR register by CPU or DMA (DATMPX[1:0]=2)
can be used as data input in order to process digital data streams from memory or
peripherals.
Data can be written by CPU or DMA into DFSDM_CHyDATINR register:
1.
CPU data write:
Input data are written directly by CPU into DFSDM_CHyDATINR register.
2.
DMA data write:
The DMA should be configured in memory-to-memory transfer mode to transfer data
from memory buffer into DFSDM_CHyDATINR register. The destination memory
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address is the address of DFSDM_CHyDATINR register. Data are transferred at DMA
transfer speed from memory to DFSDM parallel input.
This DMA transfer is different from DMA used to read DFSDM conversion results. Both
DMA can be used at the same time - first DMA (configured as memory-to-memory
transfer) for input data writings and second DMA (configured as peripheral-to-memory
transfer) for data results reading.
The accesses to DFSDM_CHyDATINR can be either 16-bit or 32-bit wide, allowing to load
respectively one or two samples in one write operation. 32-bit input data register
(DFSDM_CHyDATINR) can be filled with one or two 16-bit data samples, depending on the
data packing operation mode defined in field DATPACK[1:0] of DFSDM_CHyCFGR1
register:
1.
Standard mode (DATPACK[1:0]=0):
Only one sample is stored in field INDAT0[15:0] of DFSDM_CHyDATINR register which
is used as input data for channel y. The upper 16 bits (INDAT1[15:0]) are ignored and
write protected. The digital filter must perform one input sampling (from INDAT0[15:0])
to empty data register after it has been filled by CPU/DMA. This mode is used together
with 16-bit CPU/DMA access to DFSDM_CHyDATINR register to load one sample per
write operation.
2.
Interleaved mode (DATPACK[1:0]=1):
DFSDM_CHyDATINR register is used as a two sample buffer. The first sample is
stored in INDAT0[15:0] and the second sample is stored in INDAT1[15:0]. The digital
filter must perform two input samplings from channel y to empty DFSDM_CHyDATINR
register. This mode is used together with 32-bit CPU/DMA access to
DFSDM_CHyDATINR register to load two samples per write operation.
3.
Dual mode (DATPACK[1:0]=2):
Two samples are written into DFSDM_CHyDATINR register. The data INDAT0[15:0] is
for channel y, the data in INDAT1[15:0] is for channel y+1. The data in INDAT1[15:0] is
automatically copied INDAT0[15:0] of the following (y+1) channel data register
DFSDM_CH[y+1]DATINR). The digital filters must perform two samplings - one from
channel y and one from channel (y+1) - in order to empty DFSDM_CHyDATINR
registers.
Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y =
0, 2, 4, 6). If odd channel (y = 1, 3, 5, 7) is set to Dual mode then both INDAT0[15:0]
and INDAT1[15:0] parts are write protected for this channel. If even channel is set to
Dual mode then the following odd channel must be set into Standard mode
(DATPACK[1:0]=0) for correct cooperation with even channels.
See Figure 83 for DFSDM_CHyDATINR registers data modes and assignments of data
samples to channels.
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Figure 83. DFSDM_CHyDATINR registers operation modes and assignment
Standard mode
31
Unused
Interleaved mode
Dual mode
16 15
0 31
16 15
0 31
16 15
0
Ch0 (sample 0) Ch0 (sample 1) Ch0 (sample 0) Ch1 (sample 0) Ch0 (sample 0)
Unused
y=0
Unused
Ch1 (sample 0) Ch1 (sample 1) Ch1 (sample 0)
Ch1 (sample 0)
y=1
Unused
Ch2 (sample 0) Ch2 (sample 1) Ch2 (sample 0) Ch3 (sample 0) Ch2 (sample 0)
y=2
Unused
Ch3 (sample 0) Ch3 (sample 1) Ch3 (sample 0)
Ch3 (sample 0)
y=3
Unused
Ch4 (sample 0) Ch4 (sample 1) Ch4 (sample 0) Ch5 (sample 0) Ch4 (sample 0)
y=4
Unused
Ch5 (sample 0) Ch5 (sample 1) Ch5 (sample 0)
Ch5 (sample 0)
y=5
Unused
Ch6 (sample 0) Ch6 (sample 1) Ch6 (sample 0) Ch7 (sample 0) Ch6 (sample 0)
y=6
Unused
Ch7 (sample 0) Ch7 (sample 1) Ch7 (sample 0)
Unused
Unused
Unused
Ch7 (sample 0)
y=7
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The write into DFSDM_CHyDATINR register to load one or two samples must be performed
after the selected input channel (channel y) is enabled for data collection (starting
conversion for channel y). Otherwise written data are lost for next processing.
For example: for single conversion and interleaved mode, do not start writing pair of data
samples into DFSDM_CHyDATINR before the single conversion is started (any data
present in the DFSDM_CHyDATINR before starting a conversion is discarded).
15.4.7
Channel selection
There are 8 multiplexed channels which can be selected for conversion using the injected
channel group and/or using the regular channel.
The injected channel group is a selection of any or all of the 8 channels. JCHG[7:0] in the
DFSDM_FLTxJCHGR register selects the channels of the injected group, where JCHG[y]=1
means that channel y is selected.
Injected conversions can operate in scan mode (JSCAN=1) or single mode (JSCAN=0). In
scan mode, each of the selected channels is converted, one after another. The lowest
channel (channel 0, if selected) is converted first, followed immediately by the next higher
channel until all the channels selected by JCHG[7:0] have been converted. In single mode
(JSCAN=0), only one channel from the selected channels is converted, and the channel
selection is moved to the next channel. Writing to JCHG[7:0] if JSCAN=0 resets the channel
selection to the lowest selected channel.
Injected conversions can be launched by software or by a trigger. They are never
interrupted by regular conversions.
The regular channel is a selection of just one of the 8 channels. RCH[2:0] in the
DFSDM_FLTxCR1 register indicates the selected channel.
Regular conversions can be launched only by software (not by a trigger). A sequence of
continuous regular conversions is temporarily interrupted when an injected conversion is
requested.
Performing a conversion on a disabled channel (CHEN=0 in DFSDM_CHyCFGR1 register)
causes that the conversion will never end - because no input data is provided (with no clock
signal). In this case, it is necessary to enable a given channel (CHEN=1 in
DFSDM_CHyCFGR1 register) or to stop the conversion by DFEN=0 in DFSDM_FLTxCR1
register.
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15.4.8
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Digital filter configuration
DFSDM contains a Sincx type digital filter implementation. This Sincx filter performs an input
digital data stream filtering, which results in decreasing the output data rate (decimation)
and increasing the output data resolution. The Sincx digital filter is configurable in order to
reach the required output data rates and required output data resolution. The configurable
parameters are:
•
•
Filter order/type: (see FORD[2:0] bits in DFSDM_FLTxFCR register):
–
FastSinc
–
Sinc1
–
Sinc2
–
Sinc3
–
Sinc4
–
Sinc5
Filter oversampling/decimation ratio (see FOSR[9:0] bits in DFSDM_FLTxFCR
register):
–
FOSR = 1-1024
–
FOSR = 1-215
–
FOSR = 1-73
- for FastSinc filter and Sincx filter x = FORD = 1..3
- for Sincx filter x = FORD = 4
- for Sincx filter x = FORD = 5
The filter has the following transfer function (impulse response in H domain):
•
x
Sincx filter type:
⎛ 1 – z – FOSR⎞
-⎟
H ( z ) = ⎜ ---------------------------⎝ 1 – z–1 ⎠
FastSinc filter type:
⎛ 1 – z – FOSR⎞
-⎟ ⋅ ( 1 + z –( 2 ⋅ FOSR ) )
H ( z ) = ⎜ ---------------------------–1
⎝ 1–z
⎠
2
•
Gain (dB)
Figure 84. Example: Sinc3 filter response
Normalized frequency (fIN/fDATA )
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Table 93. Filter maximum output resolution (peak data values from filter output)
for some FOSR values
FOSR
Sinc1
Sinc2
FastSinc
Sinc3
Sinc4
Sinc5
x
+/- x
+/- x2
+/- 2x2
+/- x3
+/- x4
+/- x5
4
+/- 4
+/- 16
+/- 32
+/- 64
+/- 256
+/- 1024
8
+/- 8
+/- 64
+/- 128
+/- 512
+/- 4096
-
32
+/- 32
+/- 1024
+/- 2048
+/- 32768
+/- 1048576
+/- 33554432
64
+/- 64
+/- 4096
+/- 8192
+/- 262144
+/- 16777216
+/- 1073741824
128
+/- 128
+/- 16384
+/- 32768
+/- 2097152
+/- 268435456
256
+/- 256
+/- 65536
+/- 131072
+/- 16777216
1024
+/- 1024 +/- 1048576
Result can overflow on full scale
input (&gt; 32-bit signed integer)
+/- 2097152 +/- 1073741824
For more information about Sinc filter type properties and usage, it is recommended to study
the theory about digital filters (more resources can be downloaded from internet).
15.4.9
Integrator unit
The integrator performs additional decimation and a resolution increase of data coming from
the digital filter. The integrator simply performs the sum of data from a digital filter for a given
number of data samples from a filter.
The integrator oversampling ratio parameter defines how many data counts will be summed
to one data output from the integrator. IOSR can be set in the range 1-256 (see IOSR[7:0]
bits description in DFSDM_FLTxFCR register).
Table 94. Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data)
IOSR
x
15.4.10
Sinc1
Sinc2
FastSinc
+/- FOSR. x +/- FOSR2. x +/- 2.FOSR2. x
Sinc3
Sinc4
Sinc5
+/- FOSR3. x
+/- FOSR4. x
+/- FOSR5. x
4
-
-
-
+/- 67 108 864
-
-
32
-
-
-
+/- 536 870 912
-
-
128
-
-
-
+/- 2 147 483
648
-
-
256
-
-
-
+/- 232
-
-
Analog watchdog
The analog watchdog purpose is to trigger an external signal (break or interrupt) when an
analog signal reaches or crosses given maximum and minimum threshold values. An
interrupt/event/break generation can then be invoked.
Each analog watchdog will supervise serial data receiver outputs (after the analog watchdog
filter on each channel) or data output register (current injected or regular conversion result)
according to AWFSEL bit setting (in DFSDM_FLTxCR1 register). The input channels to be
monitored or not by the analog watchdog x will be selected by AWDCH[7:0] in
DFSDM_FLTxCR2 register.
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Analog watchdog conversions on input channels are independent from standard
conversions. In this case, the analog watchdog uses its own filters and signal processing on
each input channel independently from the main injected or regular conversions. Analog
watchdog conversions are performed in a continuous mode on the selected input channels
in order to watch channels also when main injected or regular conversions are paused
(RCIP = 0, JCIP = 0).
There are high and low threshold registers which are compared with given data values (set
by AWHT[23:0] bits in DFSDM_FLTxAWHTR register and by AWLT[23:0] bits in
DFSDM_FLTxAWLTR register).
There are 2 options for comparing the threshold registers with the data values
•
•
Option1: in this case, the input data are taken from final output data register
(AWFSEL=0). This option is characterized by:
–
high input data resolution (up to 24-bits)
–
slow response time - inappropriate for fast response applications like overcurrent
detection
–
for the comparison the final data are taken after bit shifting and offset data
correction
–
final data are available only after main regular or injected conversions are
performed
–
can be used in case of parallel input data source (DATMPX[1:0] ≠ 0 in
DFSDM_CHyCFGR1 register)
Option2: in this case, the input data are taken from any serial data receivers output
(AWFSEL=1). This option is characterized by:
–
input serial data are processed by dedicated analog watchdog Sincx channel
filters with configurable oversampling ratio (1..32) and filter order (1..3) (see
AWFOSR[4:0] and AWFORD[1:0] bits setting in DFSDM_CHyAWSCDR register)
–
lower resolution (up to 16-bit)
–
fast response time - appropriate for applications which require a fast response like
overcurrent/overvoltage detection)
–
data are available in continuous mode independently from main regular or injected
conversions activity
In case of input channels monitoring (AWFSEL=1), the data for comparison to threshold is
taken from channels selected by AWDCH[7:0] field (DFSDM_FLTxCR2 register). Each of
the selected channels filter result is compared to one threshold value pair (AWHT[23:0] /
AWLT[23:0]). In this case, only higher 16 bits (AWHT[23:8] / AWLT[23:8]) define the 16-bit
threshold compared with the analog watchdog filter output because data coming from the
analog watchdog filter is up to a 16-bit resolution. Bits AWHT[7:0] / AWLT[7:0] are not taken
into comparison in this case (AWFSEL=1).
Parameters of the analog watchdog filter configuration for each input channel are set in
DFSDM_CHyAWSCDR register (filter order AWFORD[1:0] and filter oversampling ratio
AWFOSR[4:0]).
Each input channel has its own comparator which compares the analog watchdog data
(from analog watchdog filter) with analog watchdog threshold values (AWHT/AWLT). When
several channels are selected (field AWDCH[7:0] field of DFSDM_FLTxCR2 register),
several comparison requests may be received simultaneously. In this case, the channel
request with the lowest number is managed first and then continuing to higher selected
channels. For each channel, the result can be recorded in a separate flag (fields
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AWHTF[7:0], AWLTF[7:0] of DFSDM_FLTxAWSR register). Each channel request is
executed in 8 DFSDM clock cycles. So, the bandwidth from each channel is limited to 8
DFSDM clock cycles (if AWDCH[7:0] = 0xFF). Because the maximum input channel
sampling clock frequency is the DFSDM clock frequency divided by 4, the configuration
AWFOSR = 0 (analog watchdog filter is bypassed) cannot be used for analog watchdog
feature at this input clock speed. Therefore user must properly configure the number of
watched channels and analog watchdog filter parameters with respect to input sampling
clock speed and DFSDM frequency.
Analog watchdog filter data for given channel y is available for reading by firmware on field
WDATA[15:0] in DFSDM_CHyWDATR register. That analog watchdog filter data is
converted continuously (if CHEN=1 in DFSDM_CHyCFGR1 register) with the data rate
given by the analog watchdog filter setting and the channel input clock frequency.
The analog watchdog filter conversion works like a regular Fast Continuous Conversion
without the intergator. The number of serial samples needed for one result from analog
watchdog filter output (at channel input clock frequency fCKIN):
first conversion:
for Sincx filters (x=1..5): number of samples = [FOSR * FORD + FORD + 1]
for FastSinc filter: number of samples = [FOSR * 4 + 2 + 1]
next conversions:
for Sincx and FastSinc filters: number of samples = [FOSR * IOSR]
where:
FOSR ....... filter oversampling ratio: FOSR = AWFOSR[4:0]+1 (see DFSDM_CHyAWSCDR
register)
FORD ....... the filter order: FORD = AWFORD[1:0] (see DFSDM_CHyAWSCDR register)
In case of output data register monitoring (AWFSEL=0), the comparison is done after a right
bit shift and an offset correction of final data (see OFFSET[23:0] and DTRBS[4:0] fields in
DFSDM_CHyCFGR2 register). A comparison is performed after each injected or regular
end of conversion for the channels selected by AWDCH[7:0] field (in DFSDM_FLTxCR2
register).
The status of an analog watchdog event is signalized in DFSDM_FLTxAWSR register where
a given event is latched. AWHTF[y]=1 flag signalizes crossing AWHT[23:0] value on
channel y. AWLTF[y]=1 flag signalizes crossing AWLT[23:0] value on channel y. Latched
events in DFSDM_FLTxAWSR register are cleared by writing ‘1’ into the corresponding
clearing bit CLRAWHTF[y] or CLRAWLTF[y] in DFSDM_FLTxAWCFR register.
The global status of an analog watchdog is signalized by the AWDF flag bit in
DFSDM_FLTxISR register (it is used for the fast detection of an interrupt source). AWDF=1
signalizes that at least one watchdog occurred (AWHTF[y]=1 or AWLTF[y]=1 for at least one
channel). AWDF bit is cleared when all AWHTF[7:0] and AWLTF[7:0] are cleared.
An analog watchdog event can be assigned to break output signal. There are four break
outputs to be assigned to a high or low threshold crossing event (dfsdm_break[3:0]). The
break signal assignment to a given analog watchdog event is done by BKAWH[3:0] and
BKAWL[3:0] fields in DFSDM_FLTxAWHTR and DFSDM_FLTxAWLTR register.
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15.4.11
RM0430
Short-circuit detector
The purpose of a short-circuit detector is to signalize with a very fast response time if an
analog signal reached saturated values (out of full scale ranges) and remained on this value
given time. This behavior can detect short-circuit or open circuit errors (e.g. overcurrent or
overvoltage). An interrupt/event/break generation can be invoked.
Input data into a short-circuit detector is taken from channel transceiver outputs.
There is an upcounting counter on each input channel which is counting consecutive 0’s or
1’s on serial data receiver outputs. A counter is restarted if there is a change in the data
stream received - 1 to 0 or 0 to 1 change of data signal. If this counter reaches a short-circuit
threshold register value (SCDT[7:0] bits in DFSDM_CHyAWSCDR register), then a shortcircuit event is invoked. Each input channel has its short-circuit detector. Any channel can
be selected to be continuously monitored by setting the SCDEN bit (in DFSDM_CHyCFGR1
register) and it has its own short-circuit detector settings (threshold value in SCDT[7:0] bits,
status bit SCDF[7:0], status clearing bits CLRSCDF[7:0]). Status flag SCDF[y] is cleared
also by hardware when corresponding channel y is disabled (CHEN[y] = 0).
On each channel, a short-circuit detector event can be assigned to break output signal
dfsdm_break[3:0]. There are four break outputs to be assigned to a short-circuit detector
event. The break signal assignment to a given channel short-circuit detector event is done
by BKSCD[3:0] field in DFSDM_CHyAWSCDR register.
Short circuit detector cannot be used in case of parallel input data channel selection
(DATMPX[1:0] ≠ 0 in DFSDM_CHyCFGR1 register).
Four break outputs are totally available (shared with the analog watchdog function).
15.4.12
Extreme detector
The purpose of an extremes detector is to collect the minimum and maximum values of final
output data words (peak to peak values).
If the output data word is higher than the value stored in the extremes detector maximum
register (EXMAX[23:0] bits in DFSDM_FLTxEXMAX register), then this register is updated
with the current output data word value and the channel from which the data is stored is in
EXMAXCH[2:0] bits (in DFSDM_FLTxEXMAX register) .
If the output data word is lower than the value stored in the extremes detector minimum
register (EXMIN[23:0] bits in DFSDM_FLTxEXMIN register), then this register is updated
with the current output data word value and the channel from which the data is stored is in
EXMINCH[2:0] bits (in DFSDM_FLTxEXMIN register).
The minimum and maximum register values can be refreshed by software (by reading given
DFSDM_FLTxEXMAX or DFSDM_FLTxEXMIN register). After refresh, the extremes
detector minimum data register DFSDM_FLTxEXMIN is filled with 0x7FFFFF (maximum
positive value) and the extremes detector maximum register DFSDM_FLTxEXMAX is filled
with 0x800000 (minimum negative value).
The extremes detector performs a comparison after a right bit shift and an offset data
correction. For each extremes detector, the input channels to be considered into computing
the extremes value are selected in EXCH[7:0] bits (in DFSDM_FLTxCR2 register).
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15.4.13
Digital filter for sigma delta modulators (DFSDM)
Data unit block
The data unit block is the last block of the whole processing path: External Σ∆ modulators Serial transceivers - Sinc filter - Integrator - Data unit block.
The output data rate depends on the serial data stream rate, and filter and integrator
settings. The maximum output data rate is:
Datarate samples ⁄ s
f CKIN
= --------------------------------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 )
Datarate samples ⁄ s
f CKIN
= ---------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 )
...FAST = 0, Sincx filter
...FAST = 0, FastSinc filter
or
Datarate samples ⁄ s
f CKIN
= --------------------------------F OSR ⋅ I OSR
...FAST = 1
Maximum output data rate in case of parallel data input:
Datarate samples ⁄ s
f DATAIN_RATE
= --------------------------------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 )
...FAST = 0, Sincx filter
or
Datarate samples ⁄ s
f DATAIN_RATE
= ---------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 )
...FAST = 0, FastSinc filter
or
Datarate samples ⁄ s
f DATAIN_RATE
= ----------------------------------F OSR ⋅ I OSR
...FAST=1 or any filter bypass case ( F OSR = 1 )
where: f DATAIN_RATE ...input data rate from CPU/DMA
The right bit-shift of final data is performed in this module because the final data width is 24bit and data coming from the processing path can be up to 32 bits. This right bit-shift is
configurable in the range 0-31 bits for each selected input channel (see DTRBS[4:0] bits in
DFSDM_CHyCFGR2 register). The right bit-shift is rounding the result to nearest integer
value. The sign of shifted result is maintained - to have valid 24-bit signed format of result
data.
In the next step, an offset correction of the result is performed. The offset correction value
(OFFSET[23:0] stored in register DFSDM_CHyCFGR2) is subtracted from the output data
for a given channel. Data in the OFFSET[23:0] field is set by software by the appropriate
calibration routine.
Due to the fact that all operations in digital processing are performed on 32-bit signed
registers, the following conditions must be fulfilled not to overflow the result:
FOSR FORD . IOSR &lt;= 231 ... for Sincx filters, x = 1..5)
2 . FOSR 2 . IOSR &lt;= 231 ... for FastSinc filter)
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Note:
In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate
(fDATAIN_RATE) must be limited to be able to read all output data:
fDATAIN_RATE ≤ fAPB
where fAPB is the bus frequency to which the DFSDM peripheral is connected.
15.4.14
Signed data format
Each DFSDM input serial channel can be connected to one external Σ∆ modulator. An
external Σ∆ modulator can have 2 differential inputs (positive and negative) which can be
used for a differential or single-ended signal measurement.
A Σ∆ modulator output is always assumed in a signed format (a data stream of zeros and
ones from a Σ∆ modulator represents values -1 and +1).
Signed data format in registers: Data is in a signed format in registers for final output data,
analog watchdog, extremes detector, offset correction. The msb of output data word
represents the sign of value (two’s complement format).
15.4.15
Launching conversions
Injected conversions can be launched using the following methods:
•
Software: writing ‘1’ to JSWSTART in the DFSDM_FLTxCR1 register.
•
Trigger: JEXTSEL[2:0] selects the trigger signal while JEXTEN activates the trigger
and selects the active edge at the same time (see the DFSDM_FLTxCR1 register).
•
Synchronous with DFSDM_FLT0 if JSYNC=1: for DFSDM_FLTx (x&gt;0), an injected
conversion is automatically launched when in DFSDM_FLT0; the injected conversion is
started by software (JSWSTART=1 in DFSDM_FLT0CR2 register). Each injected
conversion in DFSDM_FLTx (x&gt;0) is always executed according to its local
configuration settings (JSCAN, JCHG, etc.).
If the scan conversion is enabled (bit JSCAN=1) then, each time an injected conversion is
triggered, all of the selected channels in the injected group (JCHG[7:0] bits in
DFSDM_FLTxJCHGR register) are converted sequentially, starting with the lowest channel
(channel 0, if selected).
If the scan conversion is disabled (bit JSCAN=0) then, each time an injected conversion is
triggered, only one of the selected channels in the injected group (JCHG[7:0] bits in
DFSDM_FLTxJCHGR register) is converted and the channel selection is then moved to the
next selected channel. Writing to the JCHG[7:0] bits when JSCAN=0 sets the channel
selection to the lowest selected injected channel.
Only one injected conversion can be ongoing at a given time. Thus, any request to launch
an injected conversion is ignored if another request for an injected conversion has already
been issued but not yet completed.
Regular conversions can be launched using the following methods:
•
Software: by writing ‘1’ to RSWSTART in the DFSDM_FLTxCR1 register.
•
Synchronous with DFSDM_FLT0 if RSYNC=1: for DFSDM_FLTx (x&gt;0), a regular
conversion is automatically launched when in DFSDM_FLT0; a regular conversion is
started by software (RSWSTART=1 in DFSDM_FLT0CR2 register). Each regular
conversion in DFSDM_FLTx (x&gt;0) is always executed according to its local
configuration settings (RCONT, RCH, etc.).
Only one regular conversion can be pending or ongoing at a given time. Thus, any request
to launch a regular conversion is ignored if another request for a regular conversion has
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already been issued but not yet completed. A regular conversion can be pending if it was
interrupted by an injected conversion or if it was started while an injected conversion was in
progress. This pending regular conversion is then delayed and is performed when all
injected conversion are finished. Any delayed regular conversion is signalized by RPEND bit
in DFSDM_FLTxRDATAR register.
15.4.16
Continuous and fast continuous modes
Setting RCONT in the DFSDM_FLTxCR1 register causes regular conversions to execute in
continuous mode. RCONT=1 means that the channel selected by RCH[2:0] is converted
repeatedly after ‘1’ is written to RSWSTART.
The regular conversions executing in continuous mode can be stopped by writing ‘0’ to
RCONT. After clearing RCONT, the on-going conversion is stopped immediately.
In continuous mode, the data rate can be increased by setting the FAST bit in the
DFSDM_FLTxCR1 register. In this case, the filter does not need to be refilled by new fresh
data if converting continuously from one channel because data inside the filter is valid from
previously sampled continuous data. The speed increase depends on the chosen filter
order. The first conversion in fast mode (FAST=1) after starting a continuous conversion by
RSWSTART=1 takes still full time (as when FAST=0), then each subsequent conversion is
finished in shorter intervals.
Conversion time in continuous mode:
if FAST = 0 (or first conversion if FAST=1):
for Sincx filters:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN
for FastSinc filter:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN
if FAST = 1 (except first conversion):
for Sincx and FastSinc filters:
t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN
in case FOSR = FOSR[9:0]+1 = 1 (filter bypassed, only integrator active):
t = IOSR / fCKIN (... but CNVCNT=0)
Continuous mode is not available for injected conversions. Injected conversions can be
started by timer trigger to emulate the continuous mode with precise timing.
If a regular continuous conversion is in progress (RCONT=1) and if a write access to
DFSDM_FLTxCR1 register requesting regular continuous conversion (RCONT=1) is
performed, then regular continuous conversion is restarted from the next conversion cycle
(like new regular continuous conversion is applied for new channel selection - even if there
is no change in DFSDM_FLTxCR1 register).
15.4.17
Request precedence
An injected conversion has a higher precedence than a regular conversion. A regular
conversion which is already in progress is immediately interrupted by the request of an
injected conversion; this regular conversion is restarted after the injected conversion
finishes.
RM0430 Rev 9
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Digital filter for sigma delta modulators (DFSDM)
RM0430
An injected conversion cannot be launched if another injected conversion is pending or
already in progress: any request to launch an injected conversion (either by JSWSTART or
by a trigger) is ignored as long as bit JCIP is ‘1’ (in the DFSDM_FLTxISR register).
Similarly, a regular conversion cannot be launched if another regular conversion is pending
or already in progress: any request to launch a regular conversion (using RSWSTART) is
ignored as long as bit RCIP is ‘1’ (in the DFSDM_FLTxISR register).
However, if an injected conversion is requested while a regular conversion is already in
progress, the regular conversion is immediately stopped and an injected conversion is
launched. The regular conversion is then restarted and this delayed restart is signalized in
bit RPEND.
Injected conversions have precedence over regular conversions in that a injected
conversion can temporarily interrupt a sequence of continuous regular conversions. When
the sequence of injected conversions finishes, the continuous regular conversions start
again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular
conversion result).
Precedence also matters when actions are initiated by the same write to DFSDM, or if
multiple actions are pending at the end of another action. For example, suppose that, while
an injected conversion is in process (JCIP=1), a single write operation to DFSDM_FLTxCR1
writes ‘1’ to RSWSTART, requesting a regular conversion. When the injected sequence
finishes, the precedence dictates that the regular conversion is performed next and its
delayed start is signalized in RPEND bit.
15.4.18
Power optimization in run mode
In order to reduce the consumption, the DFSDM filter and integrator are automatically put
into idle when not used by conversions (RCIP=0, JCIP=0).
15.5
DFSDM interrupts
In order to increase the CPU performance, a set of interrupts related to the CPU event
occurrence has been implemented:
•
•
•
End of injected conversion interrupt:
–
enabled by JEOCIE bit in DFSDM_FLTxCR2 register
–
indicated in JEOCF bit in DFSDM_FLTxISR register
–
cleared by reading DFSDM_FLTxJDATAR register (injected data)
–
indication of which channel end of conversion occurred, reported in JDATACH[2:0]
bits in DFSDM_FLTxJDATAR register
End of regular conversion interrupt:
–
enabled by REOCIE bit in DFSDM_FLTxCR2 register
–
indicated in REOCF bit in DFSDM_FLTxISR register
–
cleared by reading DFSDM_FLTxRDATAR register (regular data)
–
indication of which channel end of conversion occurred, reported in
RDATACH[2:0] bits in DFSDM_FLTxRDATAR register
Data overrun interrupt for injected conversions:
–
418/1321
occurred when injected converted data were not read from DFSDM_FLTxJDATAR
register (by CPU or DMA) and were overwritten by a new injected conversion
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
•
•
•
•
–
enabled by JOVRIE bit in DFSDM_FLTxCR2 register
–
indicated in JOVRF bit in DFSDM_FLTxISR register
–
cleared by writing ‘1’ into CLRJOVRF bit in DFSDM_FLTxICR register
Data overrun interrupt for regular conversions:
–
occurred when regular converted data were not read from DFSDM_FLTxRDATAR
register (by CPU or DMA) and were overwritten by a new regular conversion
–
enabled by ROVRIE bit in DFSDM_FLTxCR2 register
–
indicated in ROVRF bit in DFSDM_FLTxISR register
–
cleared by writing ‘1’ into CLRROVRF bit in DFSDM_FLTxICR register
Analog watchdog interrupt:
–
occurred when converted data (output data or data from analog watchdog filter according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses
over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR
registers
–
enabled by AWDIE bit in DFSDM_FLTxCR2 register (on selected channels
AWDCH[7:0])
–
indicated in AWDF bit in DFSDM_FLTxISR register
–
separate indication of high or low analog watchdog threshold error by AWHTF[7:0]
and AWLTF[7:0] fields in DFSDM_FLTxAWSR register
–
cleared by writing ‘1’ into corresponding CLRAWHTF[7:0] or CLRAWLTF[7:0] bits
in DFSDM_FLTxAWCFR register
Short-circuit detector interrupt:
–
occurred when the number of stable data crosses over thresholds in
DFSDM_CHyAWSCDR register
–
enabled by SCDIE bit in DFSDM_FLTxCR2 register (on channel selected by
SCDEN bi tin DFSDM_CHyCFGR1 register)
–
indicated in SCDF[7:0] bits in DFSDM_FLTxISR register (which also reports the
channel on which the short-circuit detector event occurred)
–
cleared by writing ‘1’ into the corresponding CLRSCDF[7:0] bit in
DFSDM_FLTxICR register
Channel clock absence interrupt:
–
occurred when there is clock absence on CKINy pin (see Clock absence detection
in Section 15.4.4: Serial channel transceivers)
–
enabled by CKABIE bit in DFSDM_FLTxCR2 register (on channels selected by
CKABEN bit in DFSDM_CHyCFGR1 register)
–
indicated in CKABF[y] bit in DFSDM_FLTxISR register
–
cleared by writing ‘1’ into CLRCKABF[y] bit in DFSDM_FLTxICR register
Table 95. DFSDM interrupt requests
Interrupt event
Event/Interrupt clearing
method
Event flag
Interrupt enable
control bit
End of injected conversion
JEOCF
reading DFSDM_FLTxJDATAR
End of regular conversion
REOCF
reading DFSDM_FLTxRDATAR REOCIE
Injected data overrun
JOVRF
writing CLRJOVRF = 1
RM0430 Rev 9
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JOVRIE
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Digital filter for sigma delta modulators (DFSDM)
RM0430
Table 95. DFSDM interrupt requests (continued)
Interrupt event
15.6
Event/Interrupt clearing
method
Event flag
Interrupt enable
control bit
Regular data overrun
ROVRF
writing CLRROVRF = 1
ROVRIE
Analog watchdog
AWDF,
AWHTF[7:0],
AWLTF[7:0]
writing CLRAWHTF[7:0] = 1
writing CLRAWLTF[7:0] = 1
AWDIE,
(AWDCH[7:0])
short-circuit detector
SCDF[7:0]
writing CLRSCDF[7:0] = 1
SCDIE,
(SCDEN)
Channel clock absence
CKABF[7:0]
writing CLRCKABF[7:0] = 1
CKABIE,
(CKABEN)
DFSDM DMA transfer
To decrease the CPU intervention, conversions can be transferred into memory using a
DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1
in DFSDM_FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting
bit RDMAEN=1 in DFSDM_FLTxCR1 register.
Note:
With a DMA transfer, the interrupt flag is automatically cleared at the end of the injected or
regular conversion (JEOCF or REOCF bit in DFSDM_FLTxISR register) because DMA is
reading DFSDM_FLTxJDATAR or DFSDM_FLTxRDATAR register.
15.7
DFSDM channel y registers (y=0..7)
Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR
register. Write access to DFSDM_CHyDATINR register can be either word access (32-bit)
or half-word access (16-bit).
15.7.1
DFSDM channel y configuration register (DFSDM_CHyCFGR1)
This register specifies the parameters used by channel y.
Address offset: 0x00 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
31
30
DFSDM CKOUT
EN
SRC
rw
rw
15
14
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
22
21
20
17
16
rw
rw
rw
rw
rw
rw
rw
3
2
1
0
10
9
8
7
6
5
4
DATPACK[1:0]
DATMPX[1:0]
Res.
Res.
Res.
CHIN
SEL
CHEN
CKAB
EN
SCDEN
Res.
rw
rw
rw
rw
rw
rw
420/1321
18
rw
11
rw
19
CKOUTDIV[7:0]
12
rw
13
23
RM0430 Rev 9
SPICKSEL[1:0]
rw
rw
SITP[1:0]
rw
rw
RM0430
Digital filter for sigma delta modulators (DFSDM)
Bit 31 DFSDMEN: Global enable for DFSDM interface
0: DFSDM interface disabled
1: DFSDM interface enabled
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and
enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1).
Data cleared by setting DFSDMEN=0:
–all registers DFSDM_FLTxISR are set to reset state (x = 0..3)
–all registers DFSDM_FLTxAWSR are set to reset state (x = 0..3)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
Bit 30 CKOUTSRC: Output serial clock source selection
0: Source for output clock is from system clock
1: Source for output clock is from audio clock
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
Bits 29:24 Reserved, must be kept at reset value.
Bits 23:16 CKOUTDIV[7:0]: Output serial clock divider
0: Output clock generation is disabled (CKOUT signal is set to low state)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is
performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
Bits 15:14 DATPACK[1:0]: Data packing mode in DFSDM_CHyDATINR register.
0: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty
DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
1: Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
–first sample in INDAT0[15:0] (assigned to channel y)
–second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from
channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next
sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
–first sample INDAT0[15:0] (assigned to channel y)
–second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel
y and second sample must be read by another digital filter from channel y+1. Dual mode is
available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7)
DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following
odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even
channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
RM0430 Rev 9
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Digital filter for sigma delta modulators (DFSDM)
RM0430
Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y
0: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR
register is write protected.
1: Reserved
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write.
There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 CHINSEL: Channel inputs selection
0: Channel inputs are taken from pins of the same channel y.
1: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bit 7 CHEN: Channel y enable
0: Channel y disabled
1: Channel y enabled
If channel y is enabled, then serial data receiving is started according to the given channel setting.
Bit 6 CKABEN: Clock absence detector enable on channel y
0: Clock absence detector disabled on channel y
1: Clock absence detector enabled on channel y
Bit 5 SCDEN: Short-circuit detector enable on channel y
0: Input channel y will not be guarded by the short-circuit detector
1: Input channel y will be continuously guarded by the short-circuit detector
Bit 4 Reserved, must be kept at reset value.
Bits 3:2 SPICKSEL[1:0]: SPI clock select for channel y
0: clock coming from external CKINy input - sampling point according SITP[1:0]
1: clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to
generate its output serial communication clock (and this output clock change is active on each
clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to
generate its output serial communication clock (and this output clock change is active on each
clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bits 1:0 SITP[1:0]: Serial interface type for channel y
00: SPI with rising edge to strobe data
01: SPI with falling edge to strobe data
10: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
11: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
422/1321
RM0430 Rev 9
RM0430
15.7.2
Digital filter for sigma delta modulators (DFSDM)
DFSDM channel y configuration register (DFSDM_CHyCFGR2)
This register specifies the parameters used by channel y.
Address offset: 0x04 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OFFSET[23:8]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
OFFSET[7:0]
rw
rw
rw
rw
rw
DTRBS[4:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:8 OFFSET[23:0]: 24-bit calibration offset for channel y
For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.
Bits 7:3 DTRBS[4:0]: Data right bit-shift for channel y
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is
rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid
24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bits 2:0 Reserved, must be kept at reset value.
15.7.3
DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR)
Short-circuit detector and analog watchdog settings for channel y.
Address offset: 0x08 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AWFORD[1:0]
Res.
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
BKSCD[3:0]
rw
rw
rw
rw
rw
rw
7
6
5
20
19
18
17
16
AWFOSR[4:0]
rw
rw
rw
rw
rw
4
3
2
1
0
rw
rw
rw
SCDT[7:0]
rw
RM0430 Rev 9
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rw
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Digital filter for sigma delta modulators (DFSDM)
RM0430
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:22 AWFORD[1:0]: Analog watchdog Sinc filter order on channel y
0: FastSinc filter type
1: Sinc1 filter type
2: Sinc2 filter type
3: Sinc3 filter type
x
⎛ 1 – z – FOSR⎞
Sincx filter type transfer function:
-⎟
H ( z ) = ⎜ ---------------------------⎝ 1 – z –1 ⎠
2
⎛ 1 – z – FOSR⎞
-⎟ ⋅ ( 1 + z –( 2 ⋅ FOSR ) )
H ( z ) = ⎜ ---------------------------⎝ 1 – z–1 ⎠
FastSinc filter type transfer function:
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bit 21 Reserved, must be kept at reset value.
Bits 20:16 AWFOSR[4:0]: Analog watchdog filter oversampling ratio (decimation rate) on channel y
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).
Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
Bits 11:8 Reserved, must be kept at reset value.
Bits 7:0 SCDT[7:0]: short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this
value is reached, then a short-circuit detector event occurs on a given channel.
15.7.4
DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR)
This register contains the data resulting from the analog watchdog filter associated to the
input channel y.
Address offset: 0x0C + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
WDATA[15:0]
r
424/1321
r
r
r
r
r
r
r
r
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 WDATA[15:0]: Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted
(no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
15.7.5
DFSDM channel y data input register (DFSDM_CHyDATINR)
This register contains 16-bit input data to be processed by DFSDM filter module. Write
access can be either word access (32-bit) or half-word access (16-bit).
Address offset: 0x10 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INDAT1[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
INDAT0[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 INDAT1[15:0]: Input data for channel y or channel y+1
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored
into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y
data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of
channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See Section 15.4.6: Parallel data inputs for more details.
INDAT0[15:1] is in the16-bit signed format.
Bits 15:0 INDAT0[15:0]: Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored
into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y
data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See Section 15.4.6: Parallel data inputs for more details.
INDAT0[15:0] is in the16-bit signed format.
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449
Digital filter for sigma delta modulators (DFSDM)
15.8
RM0430
DFSDM filter x module registers (x=0..3)
Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR
register.
15.8.1
DFSDM filter x control register 1 (DFSDM_FLTxCR1)
Address offset: 0x100 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
Res.
AWF
SEL
FAST
rw
rw
14
13
15
Res.
29
JEXTEN[1:0]
rw
rw
28
Res.
12
Res.
27
26
Res.
11
25
24
RCH[2:0]
Res.
rw
rw
rw
10
9
8
Res.
JEXTSEL[2:0]
rw
rw
23
22
21
Res.
RDMA
EN
20
Res.
rw
7
Res.
rw
6
5
Res.
JDMA
EN
rw
4
19
17
16
RSW
START
Res.
rw
rw
3
2
1
0
Res.
JSW
START
DFEN
rt_w1
rw
JSCAN JSYNC
rw
18
RCON
RSYNC
T
rw
rt_w1
Bit 31 Reserved, must be kept at reset value.
Bit 30 AWFSEL: Analog watchdog fast mode select
0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset
correction and shift
1: Analog watchdog on channel transceivers value (after watchdog filter)
Bit 29 FAST: Fast conversion mode selection for regular conversions
0: Fast conversion mode disabled
1: Fast conversion mode enabled
When converting a regular conversion in continuous mode, having enabled the fast mode causes
each conversion (except the first) to execute faster than in standard mode. This bit has no effect on
conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in
case of parallel data input.
Bits 28:27 Reserved, must be kept at reset value.
Bits 26:24 RCH[2:0]: Regular channel selection
0: Channel 0 is selected as the regular channel
1: Channel 1 is selected as the regular channel
...
7: Channel 7 is selected as the regular channel
Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is
especially useful in continuous mode (when RCONT=1). It also affects regular conversions which
are pending (due to ongoing injected conversion).
Bits 23:22 Reserved, must be kept at reset value.
426/1321
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion
0: The DMA channel is not enabled to read regular data
1: The DMA channel is enabled to read regular data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 20 Reserved, must be kept at reset value.
Bit 19 RSYNC: Launch regular conversion synchronously with DFSDM_FLT0
0: Do not launch a regular conversion synchronously with DFSDM_FLT0
1: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion
is launched in DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 18 RCONT: Continuous mode selection for regular conversions
0: The regular channel is converted just once for each conversion request
1: The regular channel is converted repeatedly after each conversion request
Writing ‘0’ to this bit while a continuous regular conversion is already in progress stops the
continuous mode immediately.
Bit 17 RSWSTART: Software start of a conversion on the regular channel
0: Writing ‘0’ has no effect
1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to
become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if
RSYNC=1.
This bit is always read as ‘0’.
Bits 16:15 Reserved, must be kept at reset value.
Bits 14:13 JEXTEN[1:0]: Trigger enable and trigger edge selection for injected conversions
00: Trigger detection is disabled
01: Each rising edge on the selected trigger makes a request to launch an injected conversion
10: Each falling edge on the selected trigger makes a request to launch an injected conversion
11: Both rising edges and falling edges on the selected trigger make requests to launch injected
conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bits 12:11 Reserved, must be kept at reset value.
Bits 10:8 JEXTSEL[2:0]: Trigger signal selection for launching injected conversions
0x0-0x7: Trigger inputs selected by the following table.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
DFSDM1_FLT0
DFSDM1_FLT1
0x00
dfsdm_jtrg0
dfsdm_jtrg0
0x01
dfsdm_jtrg1
dfsdm_jtrg1
0x02
dfsdm_jtrg2
dfsdm_jtrg2
0x03
dfsdm_jtrg3
dfsdm_jtrg3
0x04
dfsdm_jtrg5
dfsdm_jtrg5
0x05
dfsdm_jtrg7
dfsdm_jtrg7
0x06
dfsdm_jtrg9
dfsdm_jtrg9
0x07
dfsdm_jtrg10
dfsdm_jtrg10
Refer to Table 89: DFSDM triggers connection.
RM0430 Rev 9
427/1321
449
Digital filter for sigma delta modulators (DFSDM)
DFSDM2_FLT0 DFSDM2_FLT1 DFSDM2_FLT2
0x00
dfsdm_jtrg0
dfsdm_jtrg0
dfsdm_jtrg0
0x01
dfsdm_jtrg1
dfsdm_jtrg1
dfsdm_jtrg1
0x02
dfsdm_jtrg2
dfsdm_jtrg2
dfsdm_jtrg2
0x03
dfsdm_jtrg3
dfsdm_jtrg3
dfsdm_jtrg3
0x04
dfsdm_jtrg5
dfsdm_jtrg5
dfsdm_jtrg5
0x05
dfsdm_jtrg7
dfsdm_jtrg7
dfsdm_jtrg8
0x06
dfsdm_jtrg9
dfsdm_jtrg9
dfsdm_jtrg9
0x07
dfsdm_jtrg10
dfsdm_jtrg10
dfsdm_jtrg10
Refer to Table 89: DFSDM triggers connection.
RM0430
DFSDM2_FLT3
dfsdm_jtrg0
dfsdm_jtrg1
dfsdm_jtrg2
dfsdm_jtrg4
dfsdm_jtrg6
dfsdm_jtrg8
dfsdm_jtrg9
dfsdm_jtrg10
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 JDMAEN: DMA channel enabled to read data for the injected channel group
0: The DMA channel is not enabled to read injected data
1: The DMA channel is enabled to read injected data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 4 JSCAN: Scanning conversion mode for injected conversions
0: One channel conversion is performed from the injected channel group and next the selected
channel from this group is selected.
1: The series of conversions for the injected group channels is executed, starting over with the
lowest selected channel.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
Bit 3 JSYNC: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
0: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected
conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 2 Reserved, must be kept at reset value.
Bit 1 JSWSTART: Start a conversion of the injected group of channels
0: Writing ‘0’ has no effect.
1: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing
JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect.
Writing ‘1’ has no effect if JSYNC=1.
This bit is always read as ‘0’.
Bit 0 DFEN: DFSDM_FLTx enable
0: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and
all DFSDM_FLTx functions are stopped.
1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating
according to its setting.
Data which are cleared by setting DFEN=0:
–register DFSDM_FLTxISR is set to the reset state
–register DFSDM_FLTxAWSR is set to the reset state
428/1321
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
15.8.2
DFSDM filter x control register 2 (DFSDM_FLTxCR2)
Address offset: 0x104 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
EXCH[7:0]
rw
rw
rw
rw
rw
rw
rw
23
22
21
20
19
18
17
16
rw
AWDCH[7:0]
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
Res.
CKAB
IE
ROVR
IE
JOVRI
E
REOC
IE
JEOCI
E
rw
rw
rw
rw
rw
SCDIE AWDIE
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 AWDCH[7:0]: Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y
Bits 15:8 EXCH[7:0]: Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y
Bit 7 Reserved, must be kept at reset value.
Bit 6 CKABIE: Clock absence interrupt enable
0: Detection of channel input clock absence interrupt is disabled
1: Detection of channel input clock absence interrupt is enabled
Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
Bit 5 SCDIE: Short-circuit detector interrupt enable
0: short-circuit detector interrupt is disabled
1: short-circuit detector interrupt is enabled
Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
Bit 4 AWDIE: Analog watchdog interrupt enable
0: Analog watchdog interrupt is disabled
1: Analog watchdog interrupt is enabled
Please see the explanation of AWDF in DFSDM_FLTxISR.
Bit 3 ROVRIE: Regular data overrun interrupt enable
0: Regular data overrun interrupt is disabled
1: Regular data overrun interrupt is enabled
Please see the explanation of ROVRF in DFSDM_FLTxISR.
RM0430 Rev 9
429/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
Bit 2 JOVRIE: Injected data overrun interrupt enable
0: Injected data overrun interrupt is disabled
1: Injected data overrun interrupt is enabled
Please see the explanation of JOVRF in DFSDM_FLTxISR.
Bit 1 REOCIE: Regular end of conversion interrupt enable
0: Regular end of conversion interrupt is disabled
1: Regular end of conversion interrupt is enabled
Please see the explanation of REOCF in DFSDM_FLTxISR.
Bit 0 JEOCIE: Injected end of conversion interrupt enable
0: Injected end of conversion interrupt is disabled
1: Injected end of conversion interrupt is enabled
Please see the explanation of JEOCF in DFSDM_FLTxISR.
15.8.3
DFSDM filter x interrupt and status register (DFSDM_FLTxISR)
Address offset: 0x108 + 0x80 * x, (x = 0 to 3)
Reset value: 0x00FF 0000
31
30
29
28
27
26
25
24
23
22
21
SCDF[7:0]
20
19
18
17
16
CKABF[7:0]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
RCIP
JCIP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
AWDF ROVRF JOVRF REOCF JEOCF
r
r
r
r
r
Bits 31:24 SCDF[7:0]: short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the
DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in
the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given
channel is disabled).
Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
Bits 23:16 CKABF[7:0]: Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at
CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at
CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by
software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
Bit 15 Reserved, must be kept at reset value.
Bit 14 RCIP: Regular conversion in progress status
0: No request to convert the regular channel has been issued
1: The conversion of the regular channel is in progress or a request for a regular conversion is
pending
A request to start a regular conversion is ignored when RCIP=1.
430/1321
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
Bit 13 JCIP: Injected conversion in progress status
0: No request to convert the injected channel group (neither by software nor by trigger) has been
issued
1: The conversion of the injected channel group is in progress or a request for a injected conversion
is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection
A request to start an injected conversion is ignored when JCIP=1.
Bits 12:5 Reserved, must be kept at reset value.
Bit 4 AWDF: Analog watchdog
0: No Analog watchdog event occurred
1: The analog watchdog block detected voltage which crosses the value programmed in the
DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and
AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing ‘1’ into the clear bits in
DFSDM_FLTxAWCFR register).
Bit 3 ROVRF: Regular conversion overrun flag
0: No regular conversion overrun has occurred
1: A regular conversion overrun has occurred, which means that a regular conversion finished while
REOCF was already ‘1’. RDATAR is not affected by overruns
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the
DFSDM_FLTxICR register.
Bit 2 JOVRF: Injected conversion overrun flag
0: No injected conversion overrun has occurred
1: An injected conversion overrun has occurred, which means that an injected conversion finished
while JEOCF was already ‘1’. JDATAR is not affected by overruns
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the
DFSDM_FLTxICR register.
Bit 1 REOCF: End of regular conversion flag
0: No regular conversion has completed
1: A regular conversion has completed and its data may be read
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
Bit 0 JEOCF: End of injected conversion flag
0: No injected conversion has completed
1: An injected conversion has completed and its data may be read
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
Note:
For each of the flag bits, an interrupt can be enabled by setting the corresponding bit in
DFSDM_FLTxCR2. If an interrupt is called, the flag must be cleared before exiting the
interrupt service routine.
All the bits of DFSDM_FLTxISR are automatically reset when DFEN=0.
RM0430 Rev 9
431/1321
449
Digital filter for sigma delta modulators (DFSDM)
15.8.4
RM0430
DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR)
Address offset: 0x10C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
CLRSCDF[7:0]
20
19
18
17
16
CLRCKABF[7:0]
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
CLRR
OVRF
CLRJ
OVRF
Res.
Res.
rc_w1
rc_w1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:24 CLRSCDF[7:0]: Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing ‘0’ has no effect
CLRSCDF[y]=1: Writing ‘1’ to position y clears the corresponding SCDF[y] bit in the
DFSDM_FLTxISR register
Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
Bits 23:16 CLRCKABF[7:0]: Clear the clock absence flag
CLRCKABF[y]=0: Writing ‘0’ has no effect
CLRCKABF[y]=1: Writing ‘1’ to position y clears the corresponding CKABF[y] bit in the
DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is
set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
Bits 15:4 Reserved, must be kept at reset value.
Bit 3 CLRROVRF: Clear the regular conversion overrun flag
0: Writing ‘0’ has no effect
1: Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register
Bit 2 CLRJOVRF: Clear the injected conversion overrun flag
0: Writing ‘0’ has no effect
1: Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register
Bits 1:0 Reserved, must be kept at reset value.
Note:
432/1321
The bits of DFSDM_FLTxICR are always read as ‘0’.
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
15.8.5
DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR)
Address offset: 0x110 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
JCHG[7:0]
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 JCHG[7:0]: Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel
(channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel
selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to
the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to
be zero are ignored.
15.8.6
DFSDM filter x control register (DFSDM_FLTxFCR)
Address offset: 0x114 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
FORD[2:0]
28
27
26
Res.
Res.
Res.
25
24
23
22
21
20
19
18
17
16
FOSR[9:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
IOSR[7:0]
rw
RM0430 Rev 9
rw
rw
rw
rw
433/1321
449
Digital filter for sigma delta modulators (DFSDM)
Bits 31:29 FORD[2:0]: Sinc filter order
0: FastSinc filter type
1: Sinc1 filter type
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved
Sincx filter type transfer function:
RM0430
⎛ 1 – z –FOSR⎞
-⎟
H ( z ) = ⎜ ---------------------------⎝ 1 – z –1 ⎠
x
2
⎛ 1 – z – FOSR⎞
-⎟ ⋅ ( 1 + z – ( 2 ⋅ FOSR ) )
H ( z ) = ⎜ ---------------------------⎝ 1 – z–1 ⎠
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
Bits 28:26 Reserved, must be kept at reset value.
Bits 25:16 FOSR[9:0]: Sinc filter oversampling ratio (decimation rate)
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 IOSR[7:0]: Integrator oversampling ratio (averaging length)
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
from Sinc filter will be summed into one output data sample from the integrator. The output data rate
from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
15.8.7
DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR)
Address offset: 0x118 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
JDATA[23:8]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
JDATA[7:0]
r
434/1321
r
r
r
r
r
r
r
RM0430 Rev 9
JDATACH[2:0]
r
r
r
RM0430
Digital filter for sigma delta modulators (DFSDM)
Bits 31:8 JDATA[23:0]: Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this
field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 JDATACH[2:0]: Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to
indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the
channel indicated by JDATACH[2:0].
Note:
DMA may be used to read the data from this register. Half-word accesses may be used to
read only the MSBs of conversion data.
Reading this register also clears JEOCF in DFSDM_FLTxISR. Thus, the firmware must not
read this register if DMA is activated to read data from this register.
15.8.8
DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR)
Address offset: 0x11C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RDATA[23:8]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
RPEND
Res.
RDATA[7:0]
r
r
r
r
r
r
r
r
r
RDATACH[2:0]
r
r
r
Bits 31:8 RDATA[23:0]: Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when
REOCF=1. Reading this register clears the corresponding REOCF.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 RPEND: Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 RDATACH[2:0]: Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was
converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be
updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the
channel indicated by RDATACH[2:0].
Note:
Half-word accesses may be used to read only the MSBs of conversion data.
Reading this register also clears REOCF in DFSDM_FLTxISR.
RM0430 Rev 9
435/1321
449
Digital filter for sigma delta modulators (DFSDM)
15.8.9
RM0430
DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR)
Address offset: 0x120 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
AWHT[23:8]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
AWHT[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
BKAWH[3:0]
rw
rw
rw
rw
Bits 31:8 AWHT[23:0]: Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the
16-bit threshold as compared with the analog watchdog filter output (because data coming from
the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWH[3:0]: Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
15.8.10
DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR)
Address offset: 0x124 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
AWLT[23:8]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
AWLT[7:0]
rw
436/1321
rw
rw
rw
rw
rw
rw
rw
RM0430 Rev 9
BKAWL[3:0]
rw
rw
rw
rw
RM0430
Digital filter for sigma delta modulators (DFSDM)
Bits 31:8 AWLT[23:0]: Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define
the 16-bit threshold as compared with the analog watchdog filter output (because data coming
from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWL[3:0]: Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
15.8.11
DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR)
Address offset: 0x128 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
AWHTF[7:0]
r
r
r
r
r
AWLTF[7:0]
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 AWHTF[7:0]: Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
Bits 7:0 AWLTF[7:0]: Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
Note:
All the bits of DFSDM_FLTxAWSR are automatically reset when DFEN=0.
RM0430 Rev 9
437/1321
449
Digital filter for sigma delta modulators (DFSDM)
15.8.12
RM0430
DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR)
Address offset: 0x12C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rc_w1
rc_w1
rc_w1
CLRAWHTF[7:0]
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
CLRAWLTF[7:0]
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing ‘0’ has no effect
CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the
DFSDM_FLTxAWSR register
Bits 7:0 CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing ‘0’ has no effect
CLRAWLTF[y]=1: Writing ‘1’ to position y clears the corresponding AWLTF[y] bit in the
DFSDM_FLTxAWSR register
15.8.13
DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX)
Address offset: 0x130 + 0x80 * x, (x = 0 to 3)
Reset value: 0x8000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EXMAX[23:8]
rs_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
EXMAX[7:0]
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
rc_r
EXMAXCH[2:0]
r
r
r
Bits 31:8 EXMAX[23:0]: Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx.
EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 EXMAXCH[2:0]: Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0].
Bits are cleared by reading of this register.
438/1321
RM0430 Rev 9
RM0430
Digital filter for sigma delta modulators (DFSDM)
15.8.14
DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN)
Address offset: 0x134 + 0x80 * x, (x = 0 to 3)
Reset value: 0x7FFF FF00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EXMIN[23:8]
rc_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
EXMIN[7:0]
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
rs_r
EXMINCH[2:0]
r
r
r
Bits 31:8 EXMIN[23:0]: Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx.
EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 EXMINCH[2:0]: Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits
are cleared by reading of this register.
15.8.15
DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR)
Address offset: 0x138 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CNVCNT[27:12]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
CNVCNT[11:0]
r
r
r
r
r
r
r
r
r
RM0430 Rev 9
r
r
r
439/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
Bits 31:4 CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time
measurement is started on each conversion start and stopped when conversion finishes (interval
between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion
time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in
case of parallel data input (from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also
this interruption time.
Bits 3:0 Reserved, must be kept at reset value.
15.8.16
DFSDM register map
The following table summarizes the DFSDM registers.
0
0
0
0
Res.
Res.
Res.
Res.
DATMPX[1:0]
0
0
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0430 Rev 9
SITP[1:0]
Res.
Res.
SPICKSEL
[1:0]
Res.
Res.
Res.
Res.
Res.
CHINSEL
Res.
Res.
Res.
SCDEN
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
DATMPX[1:0]
0
CHEN
Res.
0
CKABEN
Res.
DFSDM_
CH1CFGR1
DATPACK[1:0]
Res.
Res.
0
Reserved
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
INDAT0[15:0]
Res.
0
0
SCDT[7:0]
0
INDAT1[15:0]
0
0
WDATA[15:0]
0
DFSDM_
CH0DATINR
0
0
Res.
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
BKSCD[3:0]
Res.
Res.
Res.
0
AWFOSR[4:0]
Res.
AWFORD
[1:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFSDM_
CH0WDATR
Res.
Res.
Res.
Res.
Res.
0
reset value
440/1321
0
0
reset value
0x20
0
reset value
reset value
0x14 0x1C
0
DTRBS[4:0]
reset value
0x10
0
SITP[1:0]
0
Res.
0
SPICKSEL
[1:0]
0
SCDEN
0
CHEN
0
CKABEN
0
CHINSEL
0
OFFSET[23:0]
DFSDM_
CH0AWSCDR
0x0C
DATPACK[1:0]
Res.
Res.
Res.
Res.
Res.
0
Res.
DFSDMEN
CKOUTSRC
0
CKOUTDIV[7:0]
DFSDM_
CH0CFGR2
Res.
0x08
reset value
Res.
0x04
DFSDM_
CH0CFGR1
Res.
0x00
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 96. DFSDM register map and reset values
Register
name
0
0
0
0
0
0
0
RM0430
Digital filter for sigma delta modulators (DFSDM)
0
0
0
AWFOSR[4:0]
BKSCD[3:0]
0
0
0
0
0
0
reset value
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CHINSEL
CHEN
CKABEN
SCDEN
Res.
AWFOSR[4:0]
BKSCD[3:0]
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SITP[1:0]
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CHINSEL
CHEN
CKABEN
SCDEN
Res.
0
0
0
0
0
0
0
0
0
0
DTRBS[4:0]
0
RM0430 Rev 9
0
0
0
0
0
0
0
0
0
0
0
0
0
SITP[1:0]
0
0
0
Res.
DATMPX[1:0]
DATPACK[1:0]
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
SCDT[7:0]
OFFSET[23:0]
0
0
0
WDATA[15:0]
0
0
0
0
0
DFSDM_
CH3CFGR1
DFSDM_
CH3CFGR2
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
0
INDAT0[15:0]
Res.
0
0
0
Res.
AWFORD[1:0]
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
0
0
Res.
0
Res.
0
DTRBS[4:0]
Res.
0
Res.
Res.
Res.
0
SPICKSEL[1:0]
Res.
Res.
Res.
DATMPX[1:0]
Res.
Res.
Res.
Res.
DATPACK[1:0]
Res.
Res.
0
Res.
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
INDAT1[15:0]
0
0
0
Res.
Res.
Res.
Res.
0
0
0
Res.
Res.
Res.
0
0
0
Reserved
reset value
0
0
reset value
0x64
0
0
Res.
0x60
0
0
0
DFSDM_
CH2DATINR
reset value
0x54 0x5C
0
0
Res.
DFSDM_
CH2AWSCDR
Res.
0
0
0
Res.
0
Res.
0
0
0
reset value
0x50
0
Res.
0
Res.
0
0
0
Res.
0
0
0
Res.
0
Res.
0
reset value
0x4C
0
0
Res.
0
Res.
0
0
0
SCDT[7:0]
OFFSET[23:0]
reset value
0
0
WDATA[15:0]
0
DFSDM_
CH2CFGR2
0
0
0
DFSDM_
CH2CFGR1
DFSDM_
CH2WDATR
0
0
0
Reserved
Res.
0x48
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
reset value
0x44
0
0
INDAT0[15:0]
Res.
0x40
0
INDAT1[15:0]
Res.
reset value
0x34 0x3C
0
Res.
0x30
0
0
DFSDM_
CH1DATINR
Res.
0
Res.
0
Res.
AWFORD[1:0]
0
SPICKSEL[1:0]
Res.
0
Res.
Res.
Res.
0
0
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x2C
DFSDM_
CH1WDATR
0
Res.
DFSDM_
CH1AWSCDR
reset value
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
DTRBS[4:0]
Res.
0
Res.
0
Res.
0
Res.
reset value
Res.
OFFSET[23:0]
Res.
0x28
DFSDM_
CH1CFGR2
Res.
0x24
Register
name
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 96. DFSDM register map and reset values (continued)
0
441/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
0
0
0
Res.
Res.
Res.
reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CHINSEL
CHEN
CKABEN
SCDEN
Res.
AWFOSR[4:0]
BKSCD[3:0]
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CHINSEL
CHEN
CKABEN
SCDEN
Res.
0
0
0
0
AWFOSR[4:0]
BKSCD[3:0]
0
0
0
0
0
0
0
RM0430 Rev 9
0
0
0
0
0
0
0
0
0
0
0
0
SITP[1:0]
0
0
Res.
0
0
Res.
0
Res.
AWFORD[1:0]
0
DTRBS[4:0]
Res.
Res.
0
0
Res.
DATMPX[1:0]
0
Res.
Res.
SITP[1:0]
Res.
0
0
Res.
Res.
Res.
Res.
0
0
SPICKSEL[1:0]
Res.
0
DATPACK[1:0]
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Res.
0
0
Res.
Res.
0
0
Res.
Res.
0
0
Res.
0
0
0
Res.
Res.
0
0
0
Res.
DFSDM_
CH5AWSCDR
0
0
0
Res.
0
0
0
Res.
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
SCDT[7:0]
OFFSET[23:0]
0
0
0
WDATA[15:0]
0
0
0
0
0
DFSDM_
CH5CFGR1
reset value
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
0
INDAT0[15:0]
Res.
0
0
0
Res.
0
Res.
0
0
Res.
0
Res.
AWFORD[1:0]
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
SPICKSEL[1:0]
Res.
Res.
Res.
DATMPX[1:0]
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
0
DFSDM_
CH5CFGR2
442/1321
0
Res.
Res.
0
Reserved
reset value
0
DTRBS[4:0]
Res.
0
Res.
0xA8
DATPACK[1:0]
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
INDAT1[15:0]
0
0
0
Res.
Res.
Res.
Res.
0
0
0
reset value
0xA4
0
0
Res.
0xA0
0
0
Res.
reset value
0
0
0
DFSDM_
CH4DATINR
0x94 0x9C
0
0
reset value
0x90
0
0
Res.
Res.
Res.
Res.
0
0
0
Res.
DFSDM_
CH4AWSCDR
reset value
0
Res.
0
0x8C
0
Res.
0
Res.
0
0
0
Res.
0
0
0
Res.
0
Res.
0
0
0
Res.
0
Res.
0
DFSDM_
CH4WDATR
0
OFFSET[23:0]
Res.
0x88
0
0
0
0
0
DFSDM_
CH4CFGR1
reset value
0
0
Reserved
DFSDM_
CH4CFGR2
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
reset value
0x84
0
INDAT0[15:0]
Res.
0x80
0
INDAT1[15:0]
Res.
reset value
0x74 0x
0
SCDT[7:0]
WDATA[15:0]
0
DFSDM_
CH3DATINR
0x70
0
Res.
0
Res.
0
Res.
0
Res.
BKSCD[3:0]
Res.
Res.
Res.
0
AWFOSR[4:0]
Res.
AWFORD[1:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x6C
Res.
DFSDM_
CH3WDATR
Res.
reset value
Res.
Res.
Res.
Res.
Res.
0x68
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DFSDM_
CH3AWSCDR
Offset
Res.
Register
name
Res.
Table 96. DFSDM register map and reset values (continued)
0
0
0
SCDT[7:0]
0
0
0
0
0
0
RM0430
Digital filter for sigma delta modulators (DFSDM)
Res.
Res.
Res.
Res.
Res.
Res.
reset value
Res.
Res.
0
0
AWFOSR[4:0]
BKSCD[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CHINSEL
CHEN
CKABEN
SCDEN
Res.
0
0
0
AWFOSR[4:0]
BKSCD[3:0]
Res.
Res.
Res.
Res.
0
0
0
0
0
0
Res.
AWFORD[1:0]
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SITP[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DTRBS[4:0]
Res.
Res.
Res.
Res.
0
0
Res.
0
Res.
0
Res.
DATMPX[1:0]
0
SPICKSEL[1:0]
Res.
DATPACK[1:0]
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Res.
0
0
0
Res.
Res.
0
0
0
0
0
0
SCDT[7:0]
0
0
WDATA[15:0]
0
0
0
0
0
INDAT1[15:0]
0
0
0
0
DFSDM_
CH7DATINR
0
0
Res.
Res.
Res.
Res.
0
0
0
Res.
Res.
Res.
0
0
0
Res.
DFSDM_
CH7AWSCDR
Res.
0
Res.
0
Res.
0
0
0
Res.
0
0
0
Res.
0
Res.
0
0
0
Res.
0
0
0
Res.
0
Res.
0
0
SCDT[7:0]
OFFSET[23:0]
0
0
0
WDATA[15:0]
0
reset value
0
0
0
DFSDM_
CH7CFGR1
DFSDM_
CH7CFGR2
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
0
INDAT0[15:0]
Res.
0
0
0
Res.
0
Res.
0
0
Res.
0
Res.
0
Res.
0
0
SITP[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
SCDEN
0
Res.
AWFORD[1:0]
0
Res.
Res.
Res.
0
Res.
0
SPICKSEL[1:0]
Res.
CKABEN
0
Res.
Res.
Res.
CHEN
Res.
Res.
Res.
Res.
Res.
CHINSEL
Res.
0
Res.
Res.
Res.
0
Reserved
reset value
DATMPX[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
reset value
0xF0
0
Res.
Res.
Res.
0
INDAT1[15:0]
reset value
0xEC
0
0
Res.
Res.
0
0
DFSDM_
CH6DATINR
DFSDM_
CH7WDATR
0
Res.
Res.
Res.
Res.
0
Res.
0xE8
0
DTRBS[4:0]
reset value
0xE4
DATPACK[1:0]
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Res.
Res.
0
0
0
Res.
DFSDM_
CH6AWSCDR
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
0
0
Res.
0
Res.
0
0
0
Res.
0xE0
0
OFFSET[23:0]
reset value
reset value
0xD4 0xDC
0
0
reset value
0xD0
0
0
0
DFSDM_
CH6CFGR2
reset value
0xCC
0
0
DFSDM_
CH6CFGR1
DFSDM_
CH6WDATR
0
0
Reserved
Res.
0xC8
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
reset value
0xC4
0
INDAT0[15:0]
Res.
0xC0
0
INDAT1[15:0]
Res.
reset value
0xB4 0xBC
0
DFSDM_
CH5DATINR
Res.
0xB0
WDATA[15:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFSDM_
CH5WDATR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0xAC
Register
name
Res.
Offset
Res.
Table 96. DFSDM register map and reset values (continued)
0
0
0
0
INDAT0[15:0]
0
0
0
0
0
RM0430 Rev 9
0
0
0
0
0
0
0
0
0
0
0
443/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DFSDM_
FLT0AWSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
JDMAEN
JSCAN
JSYNC
Res.
JSW START
DFEN
SCDIE
AWDIE
ROVRIE
JOVRIE
REOCIE
JEOCIE
Res.
Res.
Res.
0
0
0
0
Res.
Res.
Res.
0
0
0
1
0
0
0
0
0
0
0
0
0
0
RDATA
CH[2:0]
0
0
0
BKAWH[3:0]
0
0
0
0
BKAWL[3:0]
0
0
0
0
0
0
0
0
AWLTF[7:0]
0
0
0
0
CLRAWHTF[7:0]
0
0
0
AWHTF[7:0]
0
RM0430 Rev 9
0
CKABIE
Res.
0
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
AWLT[23:0]
reset value
444/1321
0
AWHT[23:0]
DFSDM_
FLT0AWLTR
DFSDM_
FLT0AWCFR
0
RDATA[23:0]
reset value
0x12C
0
0
Res.
0
0
Res.
0
Res.
Res.
0
Res.
0x128
0
Res.
0x124
0
Res.
0
DFSDM_
FLT0AWHTR
reset value
0
Res.
0x120
0
JDATA[23:0]
DFSDM_
FLT0RDATAR
reset value
0
0
IOSR[7:0]
Res.
reset value
0
JEOCF
Res.
0
Res.
Res.
0
REOCF
Res.
0
Res.
Res.
0
0
JDATACH [2:0]
Res.
0
JOVRF
Res.
Res.
Res.
0
CLR JOVRF
Res.
0
DFSDM_
FLT0JDATAR
0x118
0x11C
0
FOSR[9:0]
ROVRF
Res.
reset value
Res.
DFSDM_
FLT0FCR
0x114
0
JCHG[7:0]
0
FORD[2:0]
reset value
CLR ROVRF
0
0
Res.
0
AWDF
0
0
Res.
0
0
RPEND
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
Res.
0
Res.
0
DFSDM_
FLT0JCHGR
0
Res.
reset value
Res.
CLRCKABF[7:0]
0
Res.
0
Res.
0
Res.
1
0
Res.
1
0
Res.
1
0
Res.
Res.
Res.
Res.
JEXTSEL[2:0] Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
CLRSCDF[7:0]
1
0
0
JCIP
1
0
0
Res.
1
0
0
Res.
1
Res.
Res.
Res.
0
RCIP
0
Res.
Res.
RSW START
0
CKABF[7:0]
0
JEXTEN[1:0]
Res.
0
Res.
0
0
Res.
0
0
Res.
0
RCONT
Res.
0
0
EXCH[7:0]
Res.
0x110
0
Res.
Res.
RDMAEN
0
DFSDM_
FLT0ICR
0x10C
0
SCDF[7:0]
0
RSYNC
Res.
Res.
AWDCH[7:0]
0
Res.
reset value
Res.
Res.
Res.
Res.
0
0
DFSDM_
FLT0ISR
0
0
reset value
0x108
0
0
Res.
Res.
Res.
Res.
DFSDM_
FLT0CR2
0x104
0
0
Res.
Res.
Res.
0
Res.
Res.
Res.
0
reset value
Res.
Res.
FAST
RCH[2:0]
Res.
Res.
DFSDM_
FLT0CR1
0x100
Res.
Reserved
Res.
0xF4 0xFC
AWFSEL
Register
name
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 96. DFSDM register map and reset values (continued)
0
0
0
0
CLRAWLTF[7:0]
0
0
0
0
0
0
0
0
0x198
reset value
reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DFSDM_
FLT1JDATAR
0
0
0
0
0
0
0
0
JDATA[23:0]
0
RM0430 Rev 9
0
0
0
0
0
0
0
0
0
Res.
Res.
reset value
0
0
0
0
REOCF
JEOCF
0
0
0
0
0
JCHG[7:0]
0
0
IOSR[7:0]
0
0
0
0
0
Res.
0
Res.
JOVRF
0
CLR JOVRF
reset value
ROVRF
0
Res.
Res.
0
Res.
0
Res.
0
DFEN
EXMINCH[2:0]
Res.
Res.
Res.
0
JSW START
Res.
Res.
Res.
0
JEOCIE
Res.
Res.
JSYNC
0
CLR ROVRF
0
Res.
CNVCNT[27:0]
JSCAN
0
AWDF
1
Res.
1
Res.
1
JDMAEN
1
Res.
1
Res.
Res.
1
Res.
Res.
1
Res.
Res.
Res.
1
Res.
Res.
1
Res.
Res.
Res.
1
Res.
EXCH[7:0]
Res.
0
JEXTSEL[2:0] Res.
0
Res.
0
Res.
0
REOCIE
Res.
0
Res.
0
JOVRIE
Res.
0
Res.
0
ROVRIE
0
Res.
0
Res.
0
AWDIE
0
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
0
Res.
0
JDATACH[2:0]
Res.
Res.
Res.
0
Res.
0
Res.
Res.
Res.
0
JEXTEN[1:0]
0
Res.
0
Res.
0
0
Res.
0
0
Res.
0
JCIP
0
Res.
reset value
Res.
0
Res.
0
Res.
0
RCIP
0
0
Res.
0
0
Res.
0
Res.
0
Res.
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
EXMIN[23:0]
0
Res.
FOSR[9:0]
Res.
0
Res.
AWDCH[7:0]
Res.
0
Res.
0
RSW START
0
Res.
0
Res.
1
Res.
0
Res.
0
RCONT
0
Res.
0
Res.
1
Res.
0
Res.
0
RSYNC
DFSDM_
FLT0CNVTIMR
0
Res.
0
Res.
1
Res.
Res.
0
Res.
1
0
Res.
0
Res.
1
Res.
Res.
RDMAEN
0
Res.
0
Res.
DFSDM_
FLT0EXMIN
Res.
Res.
Res.
0
Res.
0
Res.
1
Res.
Res.
Res.
0
Res.
0
Res.
reset value
Res.
0
Res.
1
Res.
Res.
0
Res.
0
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
FAST
0
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
EXMAXCH[2:0]
Res.
Res.
Res.
Res.
Res.
EXMAX[23:0]
Res.
DFSDM_
FLT1FCR
1
0
Res.
DFSDM_
FLT1JCHGR
0
Res.
DFSDM_
FLT1ICR
Res.
DFSDM_
FLT1ISR
AWFSEL
DFSDM_
FLT0EXMAX
Res.
0x194
DFSDM_
FLT1CR2
RCH[2:0]
Res.
reset value
0
1
0
Res.
0x190
DFSDM_
FLT1CR1
1
0
Res.
0x18C
Reserved
0
0
Res.
0x188
0
1
Res.
0x184
reset value
0
Res.
0x180
Res.
0x13C 0x17C
0
Res.
0x138
Res.
reset value
1
Res.
0x134
Res.
reset value
Res.
0x130
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
name
Res.
Offset
FORD[2:0]
RM0430
Digital filter for sigma delta modulators (DFSDM)
Table 96. DFSDM register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
445/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
CLRAWHTF[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Res.
0
0
0
0
0
0
0
JEOCIE
Res.
REOCIE
Res.
0
0
0
0
0
JEOCF
Res.
0
REOCF
Res.
0
0
0
0
0
0
Res.
Res.
0
Res.
Res.
Res.
0
JOVRIE
Res.
Res.
0
ROVRIE
Res.
Res.
0
JOVRF
Res.
Res.
0
ROVRF
Res.
Res.
0
CLR JOVRF
Res.
Res.
Res.
Res.
0
CLR ROVRF
0
RM0430 Rev 9
0
AWDF
0
0
0
Res.
0
Res.
0
0
0
AWDIE
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
EXCH[7:0]
Res.
Res.
Res.
0
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
AWDCH[7:0]
0
JEXTSEL[2:0] Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RSW START
Res.
Res.
RCONT
Res.
Res.
Res.
Res.
Res.
0
Res.
0
0
Res.
0
Res.
0
Res.
RSYNC
0
Res.
0
Res.
0
Res.
0
RDMAEN
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
FAST
0
Res.
0
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RCH[2:0]
Res.
RPEND
Res.
0
0
Res.
0
Res.
0
0
CLRAWLTF[7:0]
0
AWFSEL
Reserved
0
0
BKAWL[3:0]
0
CNVCNT[27:0]
0
0
AWLTF[7:0]
EXMIN[23:0]
0
Res.
0
Res.
0
reset value
446/1321
0
EXMAX[23:0]
1
0
AWHTF[7:0]
0
reset value
DFSDM_
FLT2ICR
0
EXMAXCH[2:0]
0
reset value
0x20C
0
EXMINCH[2:0]
0
DFSDM_
FLT2ISR
0
Res.
0
reset value
0x208
0
Res.
0
DFSDM_
FLT2CR2
0
Res.
0
reset value
0x204
0
Res.
0
DFSDM_
FLT2CR1
0
AWLT[23:0]
DFSDM_
FLT1CNVTIMR
0x200
0
DFEN
0
0
JSW START
0
Res.
0
Res.
0
Res.
0
Res.
0
0
BKAWH[3:0]
Res.
0
0
Res.
0
0
Res.
0
DFSDM_
FLT1EXMIN
0x1BC 0x1FC
0
JSYNC
0
Res.
0x1B8
0
Res.
0
0
reset value
0
Res.
0
DFSDM_
FLT1EXMAX
0x1B4
0
Res.
0
DFSDM_
FLT1AWSR
reset value
0
Res.
0
reset value
0x1B0
0
JSCAN
0
reset value
0x1AC
0
Res.
0
reset value
DFSDM_
FLT1AWCFR
0
Res.
Res.
0
Res.
0x1A8
0
AWHT[23:0]
DFSDM_
FLT1AWLTR
0x1A4
0
JEXTEN[1:0]
reset value
0
JCIP
0x1A0
0
Res.
0
Res.
0
Res.
0
Res.
0
JDMAEN
0
RDATA
CH[2:0]
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
DFSDM_
FLT1AWHTR
RCIP
reset value
RDATA[23:0]
Res.
DFSDM_
FLT1RDATAR
Res.
0x19C
Res.
Register
name
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 96. DFSDM register map and reset values (continued)
0
0
RM0430
Digital filter for sigma delta modulators (DFSDM)
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DFSDM_
FLT2EXMIN
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
CLRAWHTF[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Res.
Res.
Res.
Res.
Res.
JEXTSEL[2:0] Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RSW START
0
Res.
0
RCONT
Res.
0
Res.
0
RSYNC
0
Res.
0
Res.
0
Res.
0
RDMAEN
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
RM0430 Rev 9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
0
0
0
0
0
RCH[2:0]
0
BKAWL[3:0]
0
0
Res.
0
Res.
0
Res.
Reserved
0
0
CLRAWLTF[7:0]
0
FAST
0
JDATACH[2:0]
Res.
0
CNVCNT[27:0]
reset value
0
AWLTF[7:0]
EXMIN[23:0]
DFSDM_
FLT2CNVTIMR
0
BKAWH[3:0]
0
Res.
0
Res.
0
EXMAX[23:0]
0
0
0
AWHTF[7:0]
0
1
0
0
AWLT[23:0]
DFSDM_
FLT2EXMAX
Res.
0
RPEND
Res.
Res.
Res.
Res.
Res.
0
EXMAXCH[2:0]
0
0
reset value
0
Res.
0
0
DFSDM_
FLT3CR1
0
AWHT[23:0]
Res.
0x280
0
EXMINCH[2:0]
0
Res.
0
Res.
0
Res.
0
Res.
0
DFEN
0
RDATA
CH[2:0]
JSW START
0
0
Res.
0
0
Res.
0
0
Res.
0
Res.
0x23C 0x27C
0
Res.
0
Res.
0x238
0
Res.
0
DFSDM_
FLT2AWSR
reset value
0
Res.
0
AWFSEL
0x234
0
Res.
0
reset value
reset value
0
0
JSYNC
0
reset value
0x230
0
Res.
0
DFSDM_
FLT2AWLTR
DFSDM_
FLT2AWCFR
0
RDATA[23:0]
reset value
0x22C
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
Res.
0
0
JSCAN
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
JDATA[23:0]
0
Res.
0
1
Res.
0
0
Res.
0
0
Res.
0
0
JDMAEN
0
0
Res.
0
0
Res.
0
Res.
Res.
Res.
0
Res.
0x228
0
DFSDM_
FLT2AWHTR
reset value
0x224
0
DFSDM_
FLT2RDATAR
reset value
0x220
0
DFSDM_
FLT2JDATAR
reset value
0x21C
0
0
IOSR[7:0]
Res.
0x218
0
FOSR[9:0]
JEXTEN[1:0]
reset value
Res.
DFSDM_
FLT2FCR
Res.
0x214
0
FORD[2:0]
reset value
JCHG[7:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFSDM_
FLT2JCHGR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x210
Register
name
Res.
Offset
Res.
Table 96. DFSDM register map and reset values (continued)
447/1321
449
Digital filter for sigma delta modulators (DFSDM)
RM0430
JEOCIE
0
0
0
0
0
0
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DFSDM_
FLT3AWSR
448/1321
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0430 Rev 9
0
0
1
0
0
0
JDATACH[2:0]
0
0
0
0
0
0
RDATA
CH[2:0]
0
0
0
BKAWH[3:0]
0
0
0
0
0
BKAWL[3:0]
0
0
0
0
0
0
0
0
AWLTF[7:0]
0
0
0
0
CLRAWHTF[7:0]
0
0
0
0
CLRAWLTF[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EXMAX[23:0]
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
AWHTF[7:0]
0
DFSDM_
FLT3EXMAX
reset value
0
AWLT[23:0]
reset value
0x2B0
0
AWHT[23:0]
reset value
0x2AC
0
RDATA[23:0]
DFSDM_
FLT3AWLTR
DFSDM_
FLT3AWCFR
0
Res.
0
Res.
0
Res.
0x2A8
0
0
0
0
0
0
0
0
EXMAXCH[2:0]
0
Res.
0
Res.
0
RPEND
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
Res.
0x2A4
0
Res.
0
DFSDM_
FLT3AWHTR
reset value
0
Res.
0x2A0
0
JDATA[23:0]
DFSDM_
FLT3RDATAR
reset value
0
Res.
reset value
0
Res.
0
Res.
0
Res.
0
Res.
0
0
IOSR[7:0]
Res.
0
DFSDM_
FLT3JDATAR
0x298
Res.
Res.
Res.
0
0
Res.
0
0
Res.
0
FOSR[9:0]
0
Res.
reset value
Res.
DFSDM_
FLT3FCR
0x294
0x29C
0
FORD[2:0]
reset value
JCHG[7:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x290
Res.
DFSDM_
FLT3JCHGR
Res.
reset value
Res.
JEOCF
JOVRIE
REOCIE
0
Res.
REOCF
ROVRIE
JOVRF
0
ROVRF
0
CLR JOVRF
0
CLR ROVRF
Res.
AWDIE
0
AWDF
Res.
Res.
0
Res.
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFSDM_
FLT3ICR
0x28C
Res.
reset value
Res.
0
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
0
Res.
0
Res.
0
JCIP
0
Res.
0
Res.
0
RCIP
0
Res.
0
Res.
EXCH[7:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DFSDM_
FLT3ISR
0x288
Res.
reset value
AWDCH[7:0]
Res.
Res.
Res.
Res.
Res.
DFSDM_
FLT3CR2
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x284
Register
name
Res.
Offset
Res.
Table 96. DFSDM register map and reset values (continued)
0
0
0
RM0430
Digital filter for sigma delta modulators (DFSDM)
1
1
1
1
DFSDM_
FLT3CNVTIMR
1
1
1
1
1
1
1
1
1
1
1
1
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
0
Res.
Reserved
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
CNVCNT[27:0]
reset value
EXMINCH[2:0]
Res.
Res.
Res.
Res.
0
0
0
Res.
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
0x2BC 0x3FC
0
Res.
0x2B8
EXMIN[23:0]
Res.
reset value
Res.
DFSDM_
FLT3EXMIN
Res.
0x2B4
Register
name
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 96. DFSDM register map and reset values (continued)
Refer to Section 2.2 on page 57 for the register boundary addresses.
RM0430 Rev 9
449/1321
449
True random number generator (RNG)
RM0430
16
True random number generator (RNG)
16.1
Introduction
The RNG is a true random number generator that continuously provides 32-bit entropy
samples, based on an analog noise source. It can be used by the application as a live
entropy source to build a NIST compliant deterministic random bit generator (DRBG).
The RNG true random number generator has been tested using NIST statistical test suite
SP800-22 rev1a (April 2010).
16.2
RNG main features
•
The RNG delivers 32-bit true random numbers, produced by an analog entropy source
post-processed with linear-feedback shift registers (LFSR).
•
In the NIST configuration, it produces one 32-bit random samples every 42 RNG clock
cycles(dedicated clock).
•
It allows embedded continuous basic health tests with associated error management
–
450/1321
Includes too low sampling clock detection and repetition count tests.
•
It can be disabled to reduce power consumption.
•
It has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated). Warning! any write not equal to 32 bits might
corrupt the register content.
RM0430 Rev 9
RM0430
True random number generator (RNG)
16.3
RNG functional description
16.3.1
RNG block diagram
Figure 85 shows the RNG block diagram.
32-bit AHB Bus
Figure 85. RNG block diagram
True RNG
Banked Registers
RNG_CR
data
RNG_DR
status
RNG_SR
AHB
interface
rng_it
rng_hclk
AHB clock domain
Alarms
control
16-bit
Data shift reg
Fault detection
Clock checker
Post-processing logic
16-bit
8-bit LFSR (x2)
rng_clk
2-bit
Sampling &amp;
Normalization (x 2)
RNG clock domain
Analog
Analog
noise
noise
source 1 source 2
en_osc
Analog noise source
MSv42096V2
16.3.2
RNG internal signals
Table 97 describes a list of useful-to-know internal signals available at the RNG level, not at
the STM32 product level (on pads).
Table 97. RNG internal input/output signals
Signal name
Signal type
Description
rng_it
Digital output
RNG global interrupt request
rng_hclk
Digital input
AHB clock
rng_clk
Digital input
RNG dedicated clock, asynchronous to rng_hclk
RM0430 Rev 9
451/1321
460
True random number generator (RNG)
16.3.3
RM0430
Random number generation
The true random number generator (RNG) delivers truly random data through its AHB
interface at deterministic intervals. Within its boundary the RNG implements the entropy
source model pictured on Figure 86, and provides three main functions to the application:
•
Collects the bitstring output of the entropy source box
•
Obtains samples of the noise source for validation purpose
•
Collects error messages from continuous health tests
Figure 86. Entropy source model
Error
message
Heath
tests
Output
Conditioning
(optional)
Raw data
Post-processing
(optional)
Digitization
Output
Noise Source
(raw data or
digitized noise
source)
Entropy source
MSv42095V1
The main components of the RNG are:
•
A source of physical randomness (analog noise source)
•
A digitization stage for this analog noise source
•
A stage delivering post-processed noise source (raw data)
•
An output buffer for the raw data. If further cryptographic conditioning is required by the
application it needs to be performed by software.
•
An optional output for the digitized noise source (unbuffered, on digital pads)
•
Basic health tests on the digitized noise source
The components pictured above are detailed hereafter.
452/1321
RM0430 Rev 9
RM0430
True random number generator (RNG)
Noise source
The noise source is the component that contains the non-deterministic, entropy-providing
activity that is ultimately responsible for the uncertainty associated with the bitstring output
by the entropy source. It is composed of:
•
Two analog noise sources, each based on three XORed free-running ring oscillator
outputs. It is possible to disable those analog oscillators to save power, as described in
Section 16.3.8.
•
A sampling stage of these outputs clocked by a dedicated clock input (rng_clk),
delivering a 2-bit raw data output.
This noise source sampling is independent to the AHB interface clock frequency (rng_hclk).
Note:
In Section 16.6 the recommended RNG clock frequencies are given.
Post processing
The sample values obtained from a true random noise source consist of 2-bit bitstrings.
Because this noise source output is biased, the RNG implements a post-processing
component that reduces that bias to a tolerable level.
The RNG post-processing consists of two stages, applied to each noise source bits:
•
The RNG takes half of the bits from the sampled noise source, and half of the bits from
inverted sampled noise source. Thus, if the source generates more ‘1’ than ‘0’ (or the
opposite), it is filtered
•
A linear feedback shift register (LFSR) performs a whitening process, producing 8-bit
strings.
This component is clocked by the RNG clock.
The times required between two random number generations, and between the RNG
initialization and availability of first sample are described in Section 16.5.
Output buffer
The RNG_DR data output register can store up to two 16-bit words, which have been output
from the post-processing component (LFSR). In order to read back 32-bit random samples,
it is required to wait 42 RNG clock cycles.
Whenever a random number is available through the RNG_DR register, the DRDY flag
changes from 0 to 1. This flag remains high until the output buffer becomes empty after
reading one word from the RNG_DR register.
Note:
When interrupts are enabled an interrupt is generated when this data ready flag transitions
from 0 to 1. Interrupt is then cleared automatically by the RNG as explained above.
Health checks
This component ensures that the entire entropy source (with its noise source) starts then
operates as expected, obtaining assurance that failures are caught quickly and with a high
probability and reliability.
RM0430 Rev 9
453/1321
460
True random number generator (RNG)
RM0430
The RNG implements the following health check features.
1.
2.
Continuous health tests, running indefinitely on the output of the noise source
–
Repetition count test, flagging an error when:
a)
One of the noise source has provided more than 64 consecutive bits at a constant
value (“0” or “1”)
b)
One of the noise sources has delivered more than 32 consecutive occurrence of
two bits patterns (“01” or “10”)
Vendor specific continuous test
–
Real-time “too slow” sampling clock detector, flagging an error when one RNG
clock cycle is smaller than AHB clock cycle divided by 16.
The CECS and SECS status bits in the RNG_SR register indicate when an error condition is
detected, as detailed in Section 16.3.7: Error management.
Note:
An interrupt can be generated when an error is detected.
16.3.4
RNG initialization
When a hardware reset occurs the following chain of events occurs:
1.
The analog noise source is enabled, and the logic starts sampling the analog output
after four RNG clock cycles, filling LFSR shift register and associated 16-bit postprocessing shift register.
2.
The output buffer is refilled automatically according to the RNG usage.
The associated initialization time can be found in Section 16.5: RNG processing time.
16.3.5
RNG operation
Normal operations
To run the RNG using interrupts, the following steps are recommended:
1.
Enable the interrupts by setting the IE bit in the RNG_CR register. At the same time,
enable the RNG by setting the bit RNGEN=1.
2.
An interrupt is now generated when a random number is ready or when an error
occurs. Therefore, at each interrupt, check that:
–
No error occurred. The SEIS and CEIS bits must be set to 0 in the RNG_SR
register.
–
A random number is ready. The DRDY bit must be set to 1 in the RNG_SR
register.
–
If the above two conditions are true the content of the RNG_DR register can be
read.
To run the RNG in polling mode following steps are recommended:
1.
Enable the random number generation by setting the RNGEN bit to “1” in the RNG_CR
register.
2.
Read the RNG_SR register and check that:
3.
454/1321
–
No error occurred (the SEIS and CEIS bits must be set to 0)
–
A random number is ready (the DRDY bit must be set to 1)
If above conditions are true read the content of the RNG_DR register.
RM0430 Rev 9
RM0430
Note:
True random number generator (RNG)
When data is not ready (DRDY = 0) RNG_DR returns zero.
It is recommended to always verify that RNG_DR is different from zero. Because when it is
the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare
event).
Low-power operations
If the power consumption is a concern to the application, low-power strategies can be used,
as described in Section 16.3.8: RNG low-power use.
Software post-processing
If a NIST approved DRBG with 128 bits of security strength is required an approved random
generator software must be built around the RNG true random number generator.
16.3.6
RNG clocking
The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock.
The AHB clock is used to clock the AHB banked registers and the post-processing
component. The RNG clock is used for noise source sampling. Recommended clock
configurations are detailed in Section 16.6: RNG entropy source validation.
Note:
When the CED bit in the RNG_CR register is set to 0, the RNG clock frequency the must
be higher than the AHB clock frequency divided by 16, otherwise the clock checker always
flags a clock error (CECS = 1 in the RNG_SR register).
See Section 16.3.1: RNG block diagram for details (AHB and RNG clock domains).
16.3.7
Error management
In parallel to random number generation a health check block verifies the correct noise
source behavior and the frequency of the RNG source clock as detailed in this section.
Associated error state is also described.
Clock error detection
When the clock error detection is enabled (CED = 0) and if the RNG clock frequency is too
low, the RNG sets to 1 both the CEIS and CECS bits to indicate that a clock error occurred.
In this case, the application must check that the RNG clock is configured correctly (see
Section 16.3.6: RNG clocking) and then it must clear the CEIS bit interrupt flag. The CECS
bit is automatically cleared when the clocking condition is normal.
Note:
The clock error has no impact on generated random numbers that is the application can still
read the RNG_DR register.
CEIS is set only when CECS is set to 1 by RNG.
Noise source error detection
When a noise source (or seed) error occurs, the RNG stops generating random numbers
and sets to 1 both SEIS and SECS bits to indicate that a seed error occurred. If a value is
available in the RNG_DR register, it must not be used as it may not have enough entropy.
In order to fully recover from a seed error application must clear the SEIS bit by writing it to
“0”, then clear and set the RNGEN bit to reinitialize and restart the RNG.
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True random number generator (RNG)
16.3.8
RM0430
RNG low-power use
If power consumption is a concern, the RNG can be disabled as soon as the DRDY bit is set
to “1” by setting the RNGEN bit to “0” in the RNG_CR register. The 32-bit random value
stored in the RNG_DR register is still available. If a new random is needed the application
needs to re-enable the RNG and wait for 42+4 RNG clock cycles.
When disabling the RNG the user deactivates all the analog seed generators, whose power
consumption is given in the datasheet electrical characteristics section.
16.4
RNG interrupts
In the RNG an interrupt can be produced on the following events:
•
Data ready flag
•
Seed error, see Section 16.3.7: Error management
•
Clock error, see Section 16.3.7: Error management
Dedicated interrupt enable control bits are available as shown in Table 98.
Table 98. RNG interrupt requests
Interrupt acronym
RNG
Interrupt event
Event flag
Enable control bit
Interrupt clear method
Data ready flag
DRDY
IE
None (automatic)
Seed error flag
SEIS
IE
Write 0 to SEIS
Clock error flag
CEIS
IE
Write 0 to CEIS
The user can enable or disable the above interrupt sources individually by changing the
mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the
individual interrupt sources can be read from the RNG_SR register.
Note:
Interrupts are generated only when RNG is enabled.
16.5
RNG processing time
The RNG can produce one 32-bit random numbers every 42 RNG clock cycles.
After enabling or re-enabling the RNG using the RNGEN bit, it takes 46 RNG clock cycles
before random data are available.
16.6
RNG entropy source validation
16.6.1
Introduction
In order to assess the amount of entropy available from the RNG, STMicroelectronics has
tested the peripheral using NIST SP800-22 rev1a statistical tests. The results can be
provided on demand or the customer can reproduce the tests.
For more information on running this NIST statistical test suite, refer to STM32
microcontrollers random number generation validation using NIST statistical test suite
application note (AN4230), available on STMicroelectronics website.
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RM0430
True random number generator (RNG)
16.6.2
Validation conditions
STMicroelectronics has tested the RNG true random number generator in the following
conditions:
•
RNG clock rng_clk= 48 MHz (CED bit = ‘0’ in RNG_CR register) and rng_clk = 400 kHz
(CED bit = ‘1’ in RNG_CR register).
Table 99. RNG configurations
RNG_CR bits
Configuration
NISTC
bit
RNG_
CONFIG1
[5:0]
CLKDIV
[3:0]
RNG_
CONFIG2
[2:0](1)
Loop
number
CED
(N)
bit
RNG_
CONFIG3
[3:0](2)
RNG_
HTCR
register
RNG_
NCSR
register
A
Refer to NIST compliant RNG configuration table in AN4230 available from www.st.com.
This application note also indicates if this configuration is part of an existing NIST SP800-90B
Entropy Certificate listed on https://csrc.nist.gov/projects/cryptographic-module-validationprogram.
B
1
0x18
C
0
0x0F
0x0(3)
0x0
0x0
0
1
0x0
0xD
0
2
default
0x0000
NA(4)
default
1. 0x1 value is recommended instead of 0x0 for RNG_CONFIG2[2:0], when RNG power consumption is critical. See the end
of Section 16.3.8: RNG low-power use for details.
2. RNG_CONFIG3[1:0] defines the loop number N: 0x0 corresponds to N=1, 0x1 to N=2, 0x2 to N=3, 0x3 to N=4
3. The noise source sampling must be NA or less. Hence, if the RNG clock is different from NA, this value of CLKDIV must be
adapted. See the CLKDIV bitfield description in Section 16.7.1 for details.
4. This value can be fixed in the RNG driver (it doesn’t depend on the STM32 family).
16.6.3
Data collection
In order to run statistical tests, it is required to collect samples from the entropy source at the
raw data level as well as at the output of the entropy source.For details on data collection
and the running of statistical test suites refer to “STM32 microcontrollers random number
generation validation using NIST statistical test suite” application note (AN4230) available
from www.st.com.
In bypass mode the bits [31:30] of the 4th word are always stuck at zero. Hence the
continuous capture of samples is started from the 5th word.
16.7
RNG registers
The RNG is associated with a control register, a data register and a status register.
16.7.1
RNG control register (RNG_CR)
Address offset: 0x000
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
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RM0430
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CED
Res.
IE
RNGEN
Res.
Res.
rw
rw
rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 CED: Clock error detection
0: Clock error detection enabled
1: Clock error detection is disabled
The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is
enabled, that is to enable or disable CED, the RNG must be disabled.
Bit 4 Reserved, must be kept at reset value.
Bit 3 IE: Interrupt enable
0: RNG interrupt is disabled
1: RNG interrupt is enabled. An interrupt is pending as soon as the DRDY, SEIS, or CEIS is
set in the RNG_SR register.
Bit 2 RNGEN: True random number generator enable
0: True random number generator is disabled. Analog noise sources are powered off and
logic clocked by the RNG clock is gated.
1: True random number generator is enabled.
Bits 1:0 Reserved, must be kept at reset value.
16.7.2
RNG status register (RNG_SR)
Address offset: 0x004
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SEIS
CEIS
Res.
Res.
SECS
CECS
DRDY
rc_w0
rc_w0
r
r
r
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 SEIS: Seed error interrupt status
This bit is set at the same time as SECS. It is cleared by writing 0. Writing 1 has no effect.
0: No faulty sequence detected
1: At least one faulty sequence is detected. See SECS bit description for details.
An interrupt is pending if IE = 1 in the RNG_CR register.
Bit 5 CEIS: Clock error interrupt status
This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect.
0: The RNG clock is correct (fRNGCLK &gt; fHCLK/16)
1: The RNG is detected too slow (fRNGCLK &lt; fHCLK/16)
An interrupt is pending if IE = 1 in the RNG_CR register.
Bits 4:3 Reserved, must be kept at reset value.
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RM0430
True random number generator (RNG)
Bit 2 SECS: Seed error current status
0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a
faulty sequence was detected and the situation has been recovered.
1: One of the noise sources has provided more than 64 consecutive bits at a constant value
(“0” or “1”), or more than 32 consecutive occurrence of two bits patterns (“01” or “10”)
Bit 1 CECS: Clock error current status
0: The RNG clock is correct (fRNGCLK&gt; fHCLK/16). If the CEIS bit is set, this means that a
slow clock was detected and the situation has been recovered.
1: The RNG clock is too slow (fRNGCLK&lt; fHCLK/16).
Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0.
Bit 0 DRDY: Data ready
0: The RNG_DR register is not yet valid, no random data is available.
1: The RNG_DR register contains valid random data.
Once the RNG_DR register has been read, this bit returns to 0 until a new random value is
generated.
If IE=1 in the RNG_CR register, an interrupt is generated when DRDY = 1.
16.7.3
RNG data register (RNG_DR)
Address offset: 0x008
Reset value: 0x0000 0000
The RNG_DR register is a read-only register that delivers a 32-bit random value when read.
After being read, this register delivers a new random value after 42 periods of RNG clock if
the output FIFO is empty.
The content of this register is valid when the DRDY = 1 and the value is not 0x0, even if
RNGEN = 0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RNDATA[31:16]
r
r
r
r
r
r
r
15
14
13
12
11
10
9
r
r
r
r
r
r
r
r
r
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
RNDATA[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:0 RNDATA[31:0]: Random data
32-bit random data, which are valid when DRDY = 1. When DRDY = 0, the RNDATA value
is zero.
When DRDY is set, it is recommended to always verify that RNG_DR is different from zero.
The zero value means that a seed error occurred between RNG_SR polling and RND_DR
output reading (a rare event).
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16.7.4
RM0430
RNG register map
0
0
0
Res.
0
0
0
0
0
0
RNDATA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2: Memory organization for the register boundary addresses.
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CECS
IE
RNGEN
Res.
Res.
0
DRDY
Reset value
0
SECS
0x008
RNG_DR
0
CEIS
Res.
Reset value
0
SEIS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RNG_SR
Res.
0x004
Res.
Reset value
CED
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RNG_CR
Res.
0x000
Res.
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 100. RNG register map and reset map
RM0430 Rev 9
0
0
RM0430
Advanced-control timers (TIM1&amp;TIM8)
17
Advanced-control timers (TIM1&amp;TIM8)
17.1
TIM1&amp;TIM8 introduction
The advanced-control timer (TIM1&amp;TIM8) consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse length of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1) and general-purpose (TIMx) timers are completely
independent, and do not share any resources. They can be synchronized together as
described in Section 17.3.20.
17.2
TIM1&amp;TIM8 main features
TIM1&amp;TIM8 timer features include:
•
16-bit up, down, up/down auto-reload counter.
•
16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
frequency either by any factor between 1 and 65536.
•
Up to 4 independent channels for:
–
Input Capture
–
Output Compare
–
PWM generation (Edge and Center-aligned Mode)
–
One-pulse mode output
•
Complementary outputs with programmable dead-time
•
Synchronization circuit to control the timer with external signals and to interconnect
several timers together.
•
Repetition counter to update the timer registers only after a given number of cycles of
the counter.
•
Break input to put the timer’s output signals in reset state or in a known state.
•
Interrupt/DMA generation on the following events:
–
Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
–
Trigger event (counter start, stop, initialization or count by internal/external trigger)
–
Input capture
–
Output compare
–
Break input
•
Supports incremental (quadrature) encoder and Hall-sensor circuitry for positioning
purposes
•
Trigger input for external clock or cycle-by-cycle current management
RM0430 Rev 9
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Advanced-control timers (TIM1&amp;TIM8)
RM0430
TIMx_ETR
Figure 87. Advanced-control timer block diagram
CK_TIM18 from RCC
ETR
Internal clock (CK_INT)
Trigger
controller
ETRF
Polarity selection,
Edge detector and Prescaler
ETRP
TRGO
To other timers
To DAC and ADC
Input filter
ITR0
TGI
ITR1
TRGI
ITR2
TRC
ITR3
Slave mode
controller
TIF_ED
REP Register
IC1
TRC
TI2
Input filter &amp;
Edge detector
CC3I
IC2
TI3
Input filter &amp;
Edge detector
Prescaler
CC2I
IC3
Prescaler
TRC
TI4
Input filter &amp;
Edge detector
TI4FP3
CC1I
IC4
Prescaler
TI4FP4
Polarity selection
Output
control
Capture/Compare
2 Register
OC2REF
DTG
Output
control
OC2N
U
CC2I
OC3
Capture/Compare
3 Register
OC3REF
Capture/Compare
4 Register
OC4REF
DTG
Output
control
U
CC1I
IC4PS
Output
control
U
TRC
BRK
DTG
CC3I
IC3PS
TI3FP4
OC1REF
U
IC2PS
TI2FP2
TI3FP3
Capture/Compare
1 Register
Prescaler
TI1FP2
TI2FP1
CC4I
IC1PS
TIMx_CH2
TI1FP1
Input filter &amp;
Edge detector
DTG[7:0] registers
OC4
BI
Clock failure event from clock controller
CSS (Clock Security System)
TIMx_CH4
TIMx_CH3
TIMx_CH4
CNT
(counter)
CC4I
TI1
TRC
TIMx_BKIN
CK_CNT
OC3N
TIMx_CH1
TIMx_CH2
PSC
(prescaler)
TIMx_CH2N
Repetition counter
CK_PSC
TIMx_CH1N
OC1
AutoReload
Register
OC1N
U
TIMx_CH1
U
TIMx_CH3N TIMx_CH3
Encoder
interface
TI2FP2
UI
OC2
TI1FP1
Reset,
Enable,
Up/Down,
Count
Interrupt &amp; DMA output
Event
MS39906V2
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Advanced-control timers (TIM1&amp;TIM8)
17.3
TIM1&amp;TIM8 functional description
17.3.1
Time-base unit
The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
•
Counter register (TIMx_CNT)
•
Prescaler register (TIMx_PSC)
•
Auto-reload register (TIMx_ARR)
•
Repetition counter register (TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 88 and Figure 89 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:
RM0430 Rev 9
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Advanced-control timers (TIM1&amp;TIM8)
RM0430
Figure 88. Counter timing diagram with prescaler division change from 1 to 2
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
F7
F8
F9
FA FB FC
01
00
02
03
Update event (UEV)
Prescaler control register
0
1
Write a new value in TIMx_PSC
Prescaler buffer
0
Prescaler counter
0
1
0
1
0
1
1
0
1
0
MS31076V2
Figure 89. Counter timing diagram with prescaler division change from 1 to 4
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
F7
F8
F9
FA FB FC
00
01
Update event (UEV)
Prescaler control register
0
3
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
0
3
0
0
1
2
3
0
1
2
3
MS31077V2
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17.3.2
Advanced-control timers (TIM1&amp;TIM8)
Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register plus one
(TIMx_RCR+1). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The repetition counter is reloaded with the content of TIMx_RCR register,
•
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 90. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
31
32
33
34
35
36
00
01
02
03
04
05
06
07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31078V3
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Advanced-control timers (TIM1&amp;TIM8)
RM0430
Figure 91. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0034
0035
0036
0000
0001
0002
0003
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31079V3
Figure 92. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0035
0036
0000
0001
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31080V3
Figure 93. Counter timing diagram, internal clock divided by N
CK_PSC
Timerclock = CK_CNT
Counter register
1F
20
00
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31081V3
466/1321
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RM0430
Advanced-control timers (TIM1&amp;TIM8)
Figure 94. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded)
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
31
33
32
34
35
36
00
01
02
03
04
05
06
07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
FF
36
Write a new value in TIMx_ARR
MS31082V3
Figure 95. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded)
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
F0
F1
F2
F3
F4 F5
00
01
02
03
04
05
06
07
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
Auto-reload preload
register
F5
36
Auto-reload shadow
register
F5
Write a new value in TIMx_ARR
RM0430 Rev 9
36
MS31083V2
467/1321
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Advanced-control timers (TIM1&amp;TIM8)
RM0430
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is
repeated for the number of times programmed in the repetition counter register plus one
(TIMx_RCR+1). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The repetition counter is reloaded with the content of TIMx_RCR register
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
468/1321
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RM0430
Advanced-control timers (TIM1&amp;TIM8)
Figure 96. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
04
05
03
02
01 00
36
35
34 33 32
31
30
2F
Counter underflow
(cnt_udf)
Update event (UEV)
Update interrupt flag
(UIF)
MS31184V1
Figure 97. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0002
0001
0000
0036
0035
0034
0033
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31185V1
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RM0430
Figure 98. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0001
0000
0000
0001
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31186V1
Figure 99. Counter timing diagram, internal clock divided by N
CK_PSC
Timerclock = CK_CNT
Counter register
20
1F
00
36
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31187V1
470/1321
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RM0430
Advanced-control timers (TIM1&amp;TIM8)
Figure 100. Counter timing diagram, update event when repetition counter is not used
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
05
04
03
02
01 00
36 35 34
33
32
31 30 2F
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
Auto-reload preload
register
FF
36
Write a new value in TIMx_ARR
MS31188V1
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = &quot;01&quot;), the counter counts up (Center
aligned mode 2, CMS = &quot;10&quot;) the counter counts up and down (Center aligned mode 3,
CMS = &quot;11&quot;).
In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or
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RM0430
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The repetition counter is reloaded with the content of TIMx_RCR register
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 101. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
04
03
02
01 00
01
02
03 04
05
06
05 04
03
Counter underflow
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31189V2
1. Here, center-aligned mode 1 is used (for more details refer to Section 17.4: TIM1&amp;TIM8 registers).
Figure 102. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0003
0002
0001
0000
0001
0002
0003
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
MS31190V2
472/1321
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RM0430
Advanced-control timers (TIM1&amp;TIM8)
Figure 103. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
CK_PSC
CNT_EN
Timerclock = CK_CNT
0034
Counter register
0035
0036
0035
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31191V2
1.
Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 104. Counter timing diagram, internal clock divided by N
CK_PSC
Timerclock = CK_CNT
Counter register
20
1F
01
00
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
MS31192V2
RM0430 Rev 9
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RM0430
Figure 105. Counter timing diagram, update event with ARPE=1 (counter underflow)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
06
05
04 03
02 01
00
01
02
03
04
05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
FD
36
Write a new value in TIMx_ARR
Auto-reload active register
FD
36
MS31193V2
Figure 106. Counter timing diagram, update event with ARPE=1 (counter overflow)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F7
F8
F9
FA
FB FC 36
35 34
33
32
31
30 2F
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
FD
36
Write a new value in TIMx_ARR
Auto-reload active register
FD
36
MS31194V2
17.3.3
Repetition counter
Section 17.3.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N+1 counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
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Advanced-control timers (TIM1&amp;TIM8)
The repetition counter is decremented:
•
At each counter overflow in upcounting mode,
•
At each counter underflow in downcounting mode,
•
At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xTck, due to the symmetry of the pattern.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 107). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.
In center-aligned mode, for odd values of RCR, the update event occurs either on the
overflow or on the underflow depending on when the RCR register was written and when
the counter was started. If the RCR was written before starting the counter, the UEV occurs
on the overflow. If the RCR was written after starting the counter, the UEV occurs on the
underflow. For example for RCR = 3, the UEV is generated on each 4th overflow or
underflow event depending on when RCR was written.
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RM0430
Figure 107. Update rate examples depending on mode and TIMx_RCR register
settings
Edge-aligned mode
Counter-aligned mode
Upcounting
Counter
TIMx_CNT
TIMx_RCR = 0
TIMx_RCR = 1
TIMx_RCR = 2
TIMx_RCR = 3
TIMx_RCR = 3
and
re-synchronization
UEV
UEV
UEV
UEV
UEV
(by SW)
UEV
Downcounting
(by SW)
(by SW)
Update event: Preload registers transferred to active registers and update interrupt generated
Update Event if the repetition counter underflow occurs when the counter is equal to the auto-reload value.
MSv31195V1
476/1321
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RM0430
17.3.4
Advanced-control timers (TIM1&amp;TIM8)
Clock selection
The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin
•
External clock mode2: external trigger input ETR
•
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, Timer 1 can be configured to act as a prescaler for Timer 2. Refer to Using
one timer as prescaler for another timer for more details.
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 108 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 108. Control circuit in normal mode, internal clock divided by 1
Internal clock
CEN=CNT_EN
UG
CNT_INIT
Counter clock = CK_CNT = CK_PSC
Counter register
31
32
33
34
35 36
00 01
02
03 04 05
06
07
MS31085V2
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
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RM0430
Figure 109. TI2 external clock connection example
TIMx_SMCR
TS[2:0]
or TI2F
TI1F
ITRx
TI1_ED
TI1FP1
TI2
Filter
Edge
detector
TI2F_Rising
TI2F_Falling
0
1
TI2FP2
ETRF
or
or
0xx
100
TRGI
101
110
111
ETRF
CK_INT
ICF[3:0]
CC2P
TIMx_CCMR1
TIMx_CCER
(internal clock)
Encoder
mode
External clock
mode 1
External clock
mode 2
CK_PSC
Internal clock
mode
ECE
SMS[2:0]
TIMx_SMCR
MS31196V1
For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
Note:
1.
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
2.
Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
3.
Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER
register.
4.
Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5.
Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
6.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The capture prescaler is not used for triggering, so it does not need to be configured.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
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RM0430
Advanced-control timers (TIM1&amp;TIM8)
Figure 110. Control circuit in external clock mode 1
TI2
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
34
35
36
TIF
Write TIF=0
MS31087V2
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 111 gives an overview of the external trigger input block.
Figure 111. External trigger input block
or TI2F
TI1F
ETR
or
or
TRGI
0
ETR pin
1
Divider
/1, /2, /4, /8
ETRP
fDTS
Filter
downcounter
ETRF
CK_INT
ETP
ETPS[1:0]
ETF[3:0]
TIMx_SMCR
TIMx_SMCR
TIMx_SMCR
(internal clock)
Encoder
mode
External clock
mode 1
External clock
mode 2
CK_PSC
Internal clock
mode
ECE
SMS[2:0]
TIMx_SMCR
MS33116V1
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
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Advanced-control timers (TIM1&amp;TIM8)
RM0430
1.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3.
Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4.
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 112. Control circuit in external clock mode 2
f CK_INT
CNT_EN
ETR
ETRP
ETRF
Counter clock =
CK_INT =CK_PSC
Counter register
34
35
36
MS33111V2
17.3.5
Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 113 to Figure 116 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
480/1321
RM0430 Rev 9
RM0430
Advanced-control timers (TIM1&amp;TIM8)
Figure 113. Capture/compare channel (example: channel 1 input stage)
TI1F_ED
To the slave mode controller
TI1F_Rising
TI1
Filter
TI1F
downcounter
fDTS
Edge
detector
TI1F_Falling
0 TI1FP1
01
1
TI2FP1
CC1P/CC1NP
ICF[3:0]
TRC
TIMx_CCER
TIMx_CCMR1
TI2F_Rising
0
(from channel 2)
TI2F_Falling
1
(from channel 2)
IC1
10
(from slave mode
controller)
IC1PS
Divider
/1, /2, /4, /8
11
CC1S[1:0] ICPS[1:0]
CC1E
TIMx_CCMR1
TIMx_CCER
MS33115V1
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 114. Capture/compare channel 1 main circuit
APB Bus
Read CCR1L
read_in_progress
CC1S[0]
IC1PS
write_in_progress
Input
mode
S write CCR1H
Capture/compare preload register
R
R
compare_transfer
capture_transfer
CC1S[1]
8
low
Read CCR1H S
high
8
(if 16-bit)
MCU-peripheral interface
Output
mode
CNT&gt;CCR1
Counter
CC1S[0]
UEV
Comparator
CC1E
CC1S[1]
OC1PE
Capture/compare shadow register
Capture
write CCR1L
(from time
base unit)
OC1PE
TIM1_CCMR1
CNT=CCR1
CC1G
TIM1_EGR
MS31089V2
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RM0430
Figure 115. Output stage of capture/compare channel (channels 1 to 3)
To the master mode
controller
0
ETRF
‘0’
OC1REF
OC1REFC
OC1_DT
CNT&gt;CCR1 Output
mode
CNT=CCR1
controller
Output
selector
Dead-time
generator
(1)
11
OC1
Output
enable
circuit
OC1N
CC1P
TIM1_CCER
OC1N_DT
‘0’
OCxREF
OC5REF
1
x0
01
Output
enable
circuit
11
0
10
0x
1
CC1NE CC1E TIM1_CCER
OC1CE OC1M[3:0]
DTG[7:0]
CC1NE CC1E
CC1NP
MOE OSSI OSSR
TIM1_CCMR1
TIM1_BDTR
TIM1_CCER
TIM1_CCER
TIM1_BDTR
MS35909V1
Figure 116. Output stage of capture/compare channel (channel 4)
To the master
mode controller
ETR
0
1
CNT&gt;CCR4
CNT&gt;CCR4
Output
mode
controller
Output
enable
circuit
OC4
CC4E
TIM1_CCER
CC4P
OC4REF
TIM1_CCER
MOE
OC1M[3:0]
TIM1_CCMR2
OSSI
OIS4
TIM1_BDTR
TIM1_CR2
MS37370V1
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
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17.3.6
Advanced-control timers (TIM1&amp;TIM8)
Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
•
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
•
Program the appropriate input filter duration in relation with the signal connected to the
timer (by programming ICxF bits in the TIMx_CCMRx register if the input is a TIx input).
Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal
clock cycles. We must program a filter duration longer than these 5 clock cycles. We
can validate a transition on TI1 when 8 consecutive samples with the new level have
been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
•
Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP
bits to 0 in the TIMx_CCER register (rising edge in this case).
•
Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
•
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
•
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
•
The TIMx_CCR1 register gets the value of the counter on the active transition.
•
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
•
An interrupt is generated depending on the CC1IE bit.
•
A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:
IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.
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17.3.7
RM0430
PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:
•
Two ICx signals are mapped on the same TIx input.
•
These 2 ICx signals are active on edges with opposite polarity.
•
One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
•
Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
•
Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).
•
Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
•
Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to '1' and the CC2NP bit to '0' (active on falling edge).
•
Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
•
Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
•
Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.
Figure 117. PWM input mode timing
TI1
TIMx_CNT
0004
0000
0001
0002
TIMx_CCR1
0004
TIMx_CCR2
0002
IC1 capture
IC2 capture
reset counter
0003
0004
IC2 capture
pulse width
measurement
0000
IC1 capture
period
measurement
ai15413
17.3.8
Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
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Advanced-control timers (TIM1&amp;TIM8)
To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) =&gt; OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.
17.3.9
Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
•
Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
•
Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
•
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
•
Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One Pulse mode).
Procedure:
1.
Select the counter clock (internal, external, prescaler).
2.
Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3.
Set the CCxIE bit if an interrupt request is to be generated.
4.
5.
Select the output mode. For example:
–
Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
–
Write OCxPE = 0 to disable preload register
–
Write CCxP = 0 to select active high polarity
–
Write CCxE = 1 to enable the output
Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 118.
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RM0430
Figure 118. Output compare mode, toggle on OC1.
Write 0xB201 in the CC1R register
TIMx_CNT
0039
TIMx_CCR1
003A
003B
B200
B201
B201
003A
OC1REF= OC1
Match detected on CCR1
Interrupt generated if enabled
MSv67583V1
17.3.10
PWM mode
Pulse Width Modulation mode allows to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination of
the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
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RM0430
Advanced-control timers (TIM1&amp;TIM8)
PWM edge-aligned mode
•
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
Upcounting mode.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT &lt; TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.
Figure 119 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.
Figure 119. Edge-aligned PWM waveforms (ARR=8)
0
Counter register
CCRx=4
1
2
3
4
5
6
7
8
0
1
OCXREF
CCxIF
OCXREF
CCRx=8
CCxIF
OCXREF
‘1’
CCRx&gt;8
CCxIF
OCXREF
‘0’
CCRx=0
CCxIF
MS31093V1
•
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to
Downcounting mode.
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT &gt; TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM
is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
Center-aligned mode (up/down counting).
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Figure 120 shows some center-aligned PWM waveforms in an example where:
•
TIMx_ARR=8,
•
PWM mode is the PWM mode 1,
•
The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
Figure 120. Center-aligned PWM waveforms (ARR=8)
Counter register
0
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
0
1
OCxREF
CCRx = 4
CMS=01
CMS=10
CMS=11
CCxIF
OCxREF
CCRx=7
CMS=10 or 11
CCxIF
OCxREF
‘1’
CCRx=8
CMS=01
CMS=10
CMS=11
CCxIF
OCxREF
CCRx&gt;8
‘1’
CMS=01
CMS=10
CMS=11
CCxIF
OCxREF
CCRx=0
CCxIF
‘0’
CMS=01
CMS=10
CMS=11
AI14681b
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RM0430
Advanced-control timers (TIM1&amp;TIM8)
Hints on using center-aligned mode:
•
When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
•
Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
•
17.3.11
–
The direction is not updated if a value greater than the auto-reload value is written
in the counter (TIMx_CNT&gt;TIMx_ARR). For example, if the counter was counting
up, it continues to count up.
–
The direction is updated if 0 or the TIMx_ARR value is written in the counter but no
Update Event UEV is generated.
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.
Complementary outputs and dead-time insertion
The advanced-control timers (TIM1&amp;TIM8) can output two complementary signals and
manage the switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and it has to be adjusted depending on the
devices that are connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...)
The polarity of the outputs (main output OCx or complementary OCxN) can be selected
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to
Table 103 for more details. In particular, the dead-time is activated when switching to the
IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. DTG[7:0] bits of the TIMx_BDTR register are used to control the
dead-time generation for all channels. From a reference waveform OCxREF, it generates 2
outputs OCx and OCxN. If OCx and OCxN are active high:
•
The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.
•
The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples).
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Figure 121. Complementary output with dead-time insertion
OCxREF
OCx
delay
OCxN
delay
MS31095V1
Figure 122. Dead-time waveforms with delay greater than the negative pulse
OCxREF
OCx
delay
OCxN
MS31096V1
Figure 123. Dead-time waveforms with delay greater than the positive pulse
OCxREF
OCx
OCxN
delay
MS31097V1
The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register. Refer to Section 17.4.18: TIM1&amp;TIM8 break and deadtime register (TIMx_BDTR) for delay calculation.
Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER
register.
This allows to send a specific waveform (such as PWM or static active level) on one output
while the complementary remains at its inactive level. Other alternative possibilities are to
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RM0430
Advanced-control timers (TIM1&amp;TIM8)
have both outputs at inactive level or both outputs active and complementary with deadtime.
Note:
When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.
17.3.12
Using the break function
When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to Table 103 for more details.
The break source can be either the break input pin or a clock failure event, generated by the
Clock Security System (CSS), from the Reset Clock Controller. For further information on
the Clock Security System, refer to Section 6.2.7: Clock security system (CSS).
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
function can be enabled by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, when writing MOE to 1 whereas it was low, user
must insert a delay (dummy instruction) before reading it correctly. This is because user
writes the asynchronous signal and reads the synchronous signal.
When a break occurs (selected level on the break input):
•
The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.
•
Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.
•
When complementary outputs are used:
–
The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
–
If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
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RM0430
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
–
Note:
If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.
•
The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if
the BDE bit in the TIMx_DIER register is set.
•
If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until it is written with 1 again. In this case, it can be used for
security and the break input can be connected to an alarm from power drivers, thermal
sensors or any security components.
The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot
be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR Register.
There are two solutions to generate a break:
•
By using the BRK input which has a programmable polarity and an enable bit BKE in
the TIMx_BDTR register
•
By software through the BG bit of the TIMx_EGR register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows to freeze the
configuration of several parameters (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). The protection can be
selected among 3 levels with the LOCK bits in the TIMx_BDTR register. Refer to
Section 17.4.18: TIM1&amp;TIM8 break and dead-time register (TIMx_BDTR). The LOCK bits
can be written only once after an MCU reset.
Figure 124 shows an example of behavior of the outputs in response to a break.
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RM0430
Advanced-control timers (TIM1&amp;TIM8)
Figure 124. Output behavior in response to a break
BREAK (MOE
)
OCxREF
OCx
(OCxN not implemented, CCxP=0, OISx=1)
OCx
(OCxN not implemented, CCxP=0, OISx=0)
OCx
(OCxN not implemented, CCxP=1, OISx=1)
OCx
(OCxN not implemented, CCxP=1, OISx=0)
OCx
delay
delay
OCxN
(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)
delay
OCx
delay
delay
OCxN
(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)
delay
OCx
OCxN
(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)
delay
OCx
OCxN
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)
delay
OCx
OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)
MS31098V1
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Advanced-control timers (TIM1&amp;TIM8)
17.3.13
RM0430
Clearing the OCxREF signal on an external event
The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the ETR signal can be connected to the output of a comparator to be used for
current handling. In this case, the ETR must be configured as follow:
1.
The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to ‘00’.
2.
The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
‘0’.
3.
The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
Figure 125 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.
Figure 125. Clearing TIMx OCxREF
(CCRx)
Counter (CNT)
ETRF
OCxREF (OCxCE = ‘0’)
OCxREF (OCxCE = ‘1’)
ETRF becomes high
ETRF still high
MSv35889V1
Note:
494/1321
In case of a PWM with a 100% duty cycle (if CCRx&gt;ARR), then OCxREF is enabled again at
the next counter overflow.
RM0430 Rev 9
RM0430
17.3.14
Advanced-control timers (TIM1&amp;TIM8)
6-step PWM generation
When complementary outputs are used on a channel, preload bits are available on the
OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the
COM commutation event. Thus one can program in advance the configuration for the next
step and change the configuration of all the channels at the same time. COM can be
generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on
TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can
generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request
(if the COMDE bit is set in the TIMx_DIER register).
Figure 126 describes the behavior of the OCx and OCxN outputs when a COM event
occurs, in 3 different examples of programmed configurations.
Figure 126. 6-step generation, COM example (OSSR=1)
counter (CNT)
(CCRx)
OCxREF
Write COM to 1
COM event
Example 1
CCxE=1
write OCxM to 100
CCxNE=0
OCxM=100 (forced inactive)
CCxE=1
CCxNE=0
OCxM=100
Write CCxNE to 1
and OCxM to 101
CCxE=1
CCxNE=0
OCxM=100 (forced inactive)
CCxE=0
CCxNE=1
OCxM=101
OCx
OCxN
OCx
Example 2
OCxN
write CCxNE to 0
CCxE=1
and OCxM to 100
CCxNE=0
OCxM=100 (forced inactive)
Example 3
CCxE=1
CCxNE=0
OCxM=100
OCx
OCxN
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Advanced-control timers (TIM1&amp;TIM8)
17.3.15
RM0430
One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
•
In upcounting: CNT &lt; CCRx ≤ ARR (in particular, 0 &lt; CCRx)
•
In downcounting: CNT &gt; CCRx
Figure 127. Example of one pulse mode
TI2
OC1REF
OC1
Counter
TIMx_ARR
TIMx_CCR1
0
tDELAY
tPULSE
t
MSv67584V1
For example one may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
496/1321
•
Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
•
TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER
register.
•
Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.
•
TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).
RM0430 Rev 9
RM0430
Advanced-control timers (TIM1&amp;TIM8)
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
•
The tDELAY is defined by the value written in the TIMx_CCR1 register.
•
The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
•
Let’s say one want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the
TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing
OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case one has to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for
external trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the
TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over
from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0',
so the Repetitive Mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
17.3.16
Encoder interface mode
To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the
counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and
SMS=’011’ if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. When needed, the input filter can be programmed as well. CC1NP and CC2NP
must be kept low.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 101. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the
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531
Advanced-control timers (TIM1&amp;TIM8)
RM0430
TIMx_ARR must be configured before starting. In the same way, the capture, compare,
prescaler, repetition counter, trigger output features continue to work as normal. Encoder
mode and External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s
position. The count direction correspond to the rotation direction of the connected sensor.
Table 101 summarizes the possible combinations, assuming TI1 and TI2 do not switch at
the same time.
Table 101. Counting direction versus encoder signals
Level on opposite signal
(TI1FP1 for TI2,
TI2FP2 for TI1)
Rising
Falling
Rising
Falling
Counting on
TI1 only
High
Down
Up
No Count
No Count
Low
Up
Down
No Count
No Count
Counting on
TI2 only
High
No Count
No Count
Up
Down
Low
No Count
No Count
Down
Up
Counting on
TI1 and TI2
High
Down
Up
Up
Down
Low
Up
Down
Down
Up
Active edge
TI1FP1 signal
TI2FP2 signal
An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 128 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
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•
CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).
•
CC2S=’01’ (TIMx_CCMR1 register, TI1FP2 mapped on TI2).
•
CC1P=’0’, CC1NP=’0’, and IC1F = ‘0000’ (TIMx_CCER register, TI1FP1 non-inverted,
TI1FP1=TI1).
•
CC2P=’0’, CC2NP=’0’, and IC2F = ‘0000’ (TIMx_CCER register, TI1FP2 non-inverted,
TI1FP2= TI2).
•
SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling
edges).
•
CEN=’1’ (TIMx_CR1 register, Counter enabled).
RM0430 Rev 9
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Advanced-control timers (TIM1&amp;TIM8)
Figure 128. Example of counter operation in encoder interface mode
forward
jitter
backward
jitter
forward
TI1
TI2
Counter
up
down
up
MS33107V1
Figure 129 gives an example of ">
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Key features

Arm Cortex-M4 with FPU core
Embedded Flash memory
Various peripherals (ADC, DAC, DMA, GPIO)
Low-power modes (Sleep, Stop, Standby)
Bit-banding for efficient memory access
Adaptive real-time memory accelerator (ART Accelerator™)
Frequently asked questions

The STM32F413/423 uses an Arm Cortex-M4 with FPU core.
Embedded Flash and SRAM, with bit-banding support.
Sleep, Stop, and Standby modes for power optimization.
ADC, DAC, DMA, GPIO, and others for versatile embedded applications.
Via an adaptive real-time memory accelerator (ART Accelerator™) for efficient read operations.
What is the core of the STM32F413/423?

What memory types are supported?

What low-power modes are available?

What peripherals are included?

How is the Flash memory accessed?

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